repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 1,099 | gas/testsuite/gas/tic6x/insns16-m-unit.s | ; Test C64x+ M-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
m3_op_00:
.short 0x231e
.short 0x469f
.short 0x799e
.short 0x9c1f
.short 0xa71e
.short 0xca9f
.short 0xfd9e
m3_op_01:
.short 0x213e
.short 0x46bf
.short 0x7bbe
.short 0x9c3f
.short 0xa53e
.short 0xcabf
.short 0xffbe
.w... |
stsp/binutils-ia16 | 2,448 | gas/testsuite/gas/tic6x/insns16-dind.s | ; Test C64x+ dind compact instruction format
.text
.nocmp
dind:
nop
.align 16
nop
.align 16
.short 0x0404
.short 0x1404
.short 0x0604
.short 0x040c
.short 0x0405
.short 0x1405
.short 0x0605
.short 0x040d
.short 0x1405
.short 0x0405
.short 0x160d
.short 0x260d
.short 0x361d
.short 0x261d
.word... |
stsp/binutils-ia16 | 2,380 | gas/testsuite/gas/tic6x/insns16-ddec.s | ; Test C64x+ ddec compact instruction format
.text
ddec:
nop
.align 16
nop
.align 16
.short 0x4c04
.short 0x5c04
.short 0x4e04
.short 0x4c0c
.short 0x4c05
.short 0x5c05
.short 0x4e05
.short 0x4c0d
.short 0x5c05
.short 0x4c05
.short 0x5e0d
.short 0x6e0d
.short 0x7e1d
.short 0x6e1d
.word 0xefe00000
... |
stsp/binutils-ia16 | 2,246 | gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s | /* ldst-reg-unscaled-imm.s Test file for AArch64
load-store reg. (unscaled imm.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General ... |
stsp/binutils-ia16 | 3,813 | gas/testsuite/gas/aarch64/armv8_4-a.s | # Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
... |
stsp/binutils-ia16 | 3,583 | gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16.s | # Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
... |
stsp/binutils-ia16 | 4,958 | gas/testsuite/gas/aarch64/sve-reg-diagnostic.s | .equ x0, 0
.equ s0, 0
.equ z0, 0
.equ z0.s, 0
.equ p0, 0
.equ p0.b, 1
cmeq v0.4s, v1.4s, x0 // Error (wrong register type)
cmeq v0.4s, v1.4s, #x0 // OK
cmeq v0.4s, v1.4s, s0 // Error (wrong register type)
cmeq v0.4s, v1.4s, #s0 // OK
cmeq v0.4s, v1.4s, z0 // OK (for compatibility)
cmeq v0.4s, v1.4s, #z0 //... |
stsp/binutils-ia16 | 1,213 | gas/testsuite/gas/aarch64/mops.s | .arch armv8.8-a+memtag
dest .req x8
src .req x11
len .req x19
data .req x23
zero .req xzr
.macro pme_seq, op, suffix, r1, r2, r3
\op\()p\()\suffix \r1, \r2, \r3
\op\()m\()\suffix \r1, \r2, \r3
\op\()e\()\suffix \r1, \r2, \r3
.endm
.macro cpy_op1_op2, op, suffix
pme_seq \op, \suffix, [x0]!, [x1]!, x30!
pme_s... |
stsp/binutils-ia16 | 1,110 | gas/testsuite/gas/aarch64/system.s | .text
drps
//
// HINTS
//
nop
yield
wfe
wfi
sev
sevl
.macro all_hints from=0, to=127
hint \from
.if \to-\from
all_hints "(\from+1)", \to
.endif
.endm
all_hints from=0, to=63
all_hints from=64, to=127
//
// SYSL
//
sysl x7, #3, C15, C7, #7
//
// BARRIERS
//
.macro all_barriers op, from... |
stsp/binutils-ia16 | 2,163 | gas/testsuite/gas/aarch64/rdma.s | /* rdma.s Test file for AArch64 v8.1 Advanced-SIMD instructions.
Copyright (C) 2012-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
th... |
stsp/binutils-ia16 | 4,198 | gas/testsuite/gas/aarch64/sve1-extended-sve2.s | /*
Those instructions from the sve2.s file that share mnemonics with
instructions in SVE.
Created with the below command
`grep -E '^(ext|ldnt1b|ldnt1d|ldnt1h|ldnt1w|mla|mls|mul|smulh|splice|sqadd|sqsub|stnt1b|stnt1d|stnt1h|stnt1w|tbl|umulh|uqadd|uqsub)\b' sve2.s`
This test file is here to ensure those inst... |
stsp/binutils-ia16 | 2,056 | gas/testsuite/gas/aarch64/brbe-invalid.s | /* Write to read-only BRBE system registers. */
msr brbidr0_el1, x0
msr brbsrc0_el1, x0
msr brbsrc1_el1, x0
msr brbsrc2_el1, x0
msr brbsrc3_el1, x0
msr brbsrc4_el1, x0
msr brbsrc5_el1, x0
msr brbsrc6_el1, x0
msr brbsrc7_el1, x0
msr brbsrc8_el1, x0
msr brbsrc9_el1, x0
msr brbsrc10_el1, x0
msr brbsrc11_el1, x0
msr brbs... |
stsp/binutils-ia16 | 1,840 | gas/testsuite/gas/aarch64/bfloat16.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
stsp/binutils-ia16 | 5,190 | gas/testsuite/gas/aarch64/addsub.s | /* addsub.s Test file for AArch64 add-subtract instructions.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the ... |
stsp/binutils-ia16 | 1,140 | gas/testsuite/gas/aarch64/pac-feat.s | /* ARMv8.3 Pointer authentication instructions. */
.arch armv8-a+pauth
/* Basic instructions. */
pacia x3, x4
pacia x5, sp
pacib x3, x4
pacib x5, sp
pacda x3, x4
pacda x5, sp
pacdb x3, x4
pacdb x5, sp
autia x3, x4
autia x5, sp
autib x3, x4
autib x5, sp
autda x3, x4
autda x5, sp
autdb x3, x4
autdb... |
stsp/binutils-ia16 | 1,792 | gas/testsuite/gas/aarch64/lse-atomic.s | /* lse-atomic.s Test file For AArch64 LSE atomic instructions encoding.
Copyright (C) 2014-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published... |
stsp/binutils-ia16 | 1,051 | gas/testsuite/gas/aarch64/armv8-ras-1_1.s | /* Armv8-A RAS 1.1 extension system registers.
Please note that early Armv8-a architectures do not officially support RAS
extension.
Certain use cases require developers to enable only more generic architecture
(e.g. -march=armv8-a) during system development. Users must use RAS extension
registers bearing in mind tha... |
stsp/binutils-ia16 | 1,595 | gas/testsuite/gas/aarch64/armv8_4-a-registers.s | .macro gen_mrs reg
.irp m, 3, 11, 15
MRS X\m, \reg
.endr
.endm
.macro gen_tlbi reg
.irp m, 3, 11, 15
TLBI \reg, X\m
.endr
.endm
func:
# Secure second stage
gen_mrs VSTTBR_EL2
gen_mrs VSTCR_EL2
# Timer changes
gen_mrs CNTP_TVAL_EL0
gen_mrs CNTP_CTL_EL0
gen_mrs CNTP_CVAL_EL0
gen_mrs CNTV_TVAL_EL0
g... |
stsp/binutils-ia16 | 2,150 | gas/testsuite/gas/aarch64/float-fp16.s | /* Test file for AArch64 half-precision floating-point instructions. */
.text
fccmp s0, s0, #0, eq
fccmp h0, h0, #0, eq
fccmp s1, s2, #0, le
fccmp h1, h2, #0, le
fccmpe s0, s0, #0, eq
fccmpe h0, h0, #0, eq
fccmpe s1, s2, #0, le
fccmpe h1, h2, #0, le
fcmp s0, s0
fcmp h0, h0
fcmp s1, s2
fcmp h1, h2
fcm... |
stsp/binutils-ia16 | 4,376 | gas/testsuite/gas/aarch64/advsimd-fp16.s | /* simdhp.s Test file for AArch64 half-precision floating-point
vector instructions. */
/* Vector three-same. */
.macro three_same, op
\op v1.2d, v2.2d, v3.2d
\op v1.2s, v2.2s, v3.2s
\op v1.4s, v2.4s, v3.4s
\op v0.4h, v0.4h, v0.4h
\op v1.4h, v2.4h, v3.4h
\op v0.8h, v0.8h, v0.8h
\op v1.8h, v2.8h, v3.8h
... |
stsp/binutils-ia16 | 1,653 | gas/testsuite/gas/aarch64/fp-const0-parse.s | /* fp-const0-parse.s Test file For AArch64 float constant 0 parse.
Copyright (C) 2014-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
... |
stsp/binutils-ia16 | 2,607 | gas/testsuite/gas/aarch64/ldst-exclusive.s | /* ldst-exclusive.s Test file for AArch64 load-store exclusive
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as p... |
stsp/binutils-ia16 | 1,027 | gas/testsuite/gas/aarch64/advsimd-misc.s | /* advsimd-abs.s Test file for AArch64 Advanced-SIMD Integer absolute
instruction.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public Licens... |
stsp/binutils-ia16 | 1,064 | gas/testsuite/gas/aarch64/floatdp2.s | /* floatdp2.s Test file for AArch64 Floating-point data-processing
(2 source) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Publ... |
stsp/binutils-ia16 | 6,432 | gas/testsuite/gas/aarch64/diagnostic.s | // diagnostic.s Test file for diagnostic quality.
.text
fmul, s0, s1, s2
fmul , s0, s1, s2
fmul , s0, s1, s2
b.random label1
fmull s0
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
sys 1,c1,c3,3,
ext v0.8b, v1.8b, v2.8b, 8
ext v0.16b, v1.16b, v2.16b, 20
svc -1
svc 65536
ccmp w0, 32,... |
stsp/binutils-ia16 | 1,358 | gas/testsuite/gas/aarch64/neon-ins.s |
.macro iterate_regs_types macro_name reg
.irp index, 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
.irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
\macro_name \regs b \index \reg
.endr
.endr
.irp index, 0,1,2,3,4,5,6,7
.irp regs, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,1... |
stsp/binutils-ia16 | 2,311 | gas/testsuite/gas/aarch64/f64mm.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
stsp/binutils-ia16 | 3,543 | gas/testsuite/gas/aarch64/shifted.s | /* shifted.s Test file for AArch64 add-substract (extended reg.) and
add-substract (shifted reg.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of ... |
stsp/binutils-ia16 | 1,912 | gas/testsuite/gas/aarch64/armv8-ras-1.s | /* ARMv8 RAS Extension. */
.text
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
/* ARMv8-A. */
.arch armv8-a+ras
esb
hint #0x10
rw_sys_reg sys_reg=erridr_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=errselr_el1 xreg=x7 r=1 w=1
rw_sys... |
stsp/binutils-ia16 | 4,460 | gas/testsuite/gas/aarch64/reloc-insn.s | // Test file for AArch64 GAS -- instructions with relocation operators.
func:
// BFD_RELOC_AARCH64_MOVW_G0
// immediate
movz x0,#:abs_g0:u12
// BFD_RELOC_AARCH64_MOVW_G0_S
// immediate
movz x0,#:abs_g0_s:s12
// BFD_RELOC_AARCH64_MOVW_G1
// immediate
movz x1,#:abs_g1:u32
movk x1,#:abs_g0_nc:u32
// BFD_R... |
stsp/binutils-ia16 | 1,947 | gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | func:
# OP x[0,30], x[0,30], x[0,30]
.macro expand_3_reg op
\op x0, x0, x0
\op x27, x0, x0
\op x0, x27, x0
\op x0, x0, x27
\op x27, x27, x27
.endm
# OP x[0,30], x[0,30], #[0,30], #[0,14]
.macro expand_2_reg op
\op x0, x0, #0, #0
\op x27, x0, #0, #0
\op x0, x27, #0, #0
\op x27, x27, #0, #0
.endm
.macro... |
stsp/binutils-ia16 | 1,789 | gas/testsuite/gas/aarch64/undefined_advsimd_armv8_3.s | # Generates tests to see if the following conditions make the instruction
# undefined:
#
# 1) size == 0
# 2) size == 3 && Q == 0
#
# These patterns can't be created by the assembler so instead manually encode
# them from a starting pattern.
.macro gen_insns_same opc
.inst \opc
.inst (\opc & 0xff3fffff) // size == 0
... |
stsp/binutils-ia16 | 1,040 | gas/testsuite/gas/aarch64/pan.s | /* pan.s Test file for AArch64 PAN instructions.
Copyright (C) 2015-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Softwar... |
stsp/binutils-ia16 | 3,885 | gas/testsuite/gas/aarch64/bitfield-bfm.s | /* bitfield-bfm.s Test file for AArch64 bitfield instructions
sbfm, bfm and ubfm mnemonics.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Publ... |
stsp/binutils-ia16 | 3,073 | gas/testsuite/gas/aarch64/movi.s | // movi.s Test file for AArch64 AdvSIMD modified immediate instruction MOVI
.text
.macro all_64bit_mask_movi dst
.irp b7, 0, 0xff00000000000000
.irp b6, 0, 0xff000000000000
.irp b5, 0, 0xff0000000000
.irp b4, 0, 0xff00000000
.irp b3, 0, 0xff000000
.irp b2, 0, 0xff0000
.irp b1, 0, 0xff00
.irp b0, 0, 0xff
mo... |
stsp/binutils-ia16 | 1,438 | gas/testsuite/gas/aarch64/sme-2.s | /* Scalable Matrix Extension (SME). */
/* MOVA (tile to vector) variant. */
mova z0.b, p0/m, za0v.b[w12, 0]
mova z0.h, p0/m, za0v.h[w12, 0]
mova z0.s, p0/m, za0v.s[w12, 0]
mova z0.d, p0/m, za0v.d[w12, 0]
mova z0.q, p0/m, za0v.q[w12, 0]
mova z31.b, p7/m, za0v.b[w15, 15]
mova z31.h, p7/m, za1v.h[w15, 7]
mova z31.s, p... |
stsp/binutils-ia16 | 2,596 | gas/testsuite/gas/aarch64/neon-vfp-reglist.s |
# ARMv8 tests to test neon register
# lists syntax.
.macro ldnstn_reg_list type inst index rep
\inst\()1\rep {v0.\type}\index, [x0]
.ifb \index
.ifb \rep
\inst\()1 {v0.\type, v1.\type}\index, [x0]
\inst\()1 {v0.\type, v1.\type, v2.\type}\index, [x0]
\inst\()1 {v0.\type, v1.\type, v2.\type, v3.\type}\index, ... |
stsp/binutils-ia16 | 1,703 | gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s | /* ldst-reg-imm-pre-ind.s Test file for AArch64
load-store reg. (imm.pre-ind.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Pub... |
stsp/binutils-ia16 | 5,586 | gas/testsuite/gas/aarch64/neon-vfp-reglist-post.s |
# ARMv8 tests to test neon register
# lists syntax.
.text
.arch armv8-a
# Post-index multiple elements
.macro ldst1_reg_list_post_imm_64 inst type
\inst\()1 {v0.\type}, [x0], #8
\inst\()1 {v0.\type, v1.\type}, [x0], #16
\inst\()1 {v0.\type, v1.\type, v2.\type}, [x0], #24
\inst\()1 {v0.\type, v1.\type, v2.... |
stsp/binutils-ia16 | 2,433 | gas/testsuite/gas/aarch64/bitfield-alias.s | /* bitfield-alias.s Test file for AArch64 bitfield instructions
alias mnemonics.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License ... |
stsp/binutils-ia16 | 1,678 | gas/testsuite/gas/aarch64/sme-9.s | /* SVE2 instructions added to support SME. */
psel p1, p15, p3.b[w15, 0]
psel p2, p14, p5.b[w15, 0]
psel p3, p13, p7.b[w15, 7]
psel p5, p12, p9.b[w15, 15]
psel p8, p11, p15.h[w14, 0]
psel p13, p10, p1.h[w14, 0]
psel p15, p9, p0.h[w14, 3]
psel p1, p8, p6.h[w14, 7]
psel p2, p7, p15.s[w13, 0]
psel p3, p6, p15.s[w13, 0... |
stsp/binutils-ia16 | 5,708 | gas/testsuite/gas/aarch64/mops_invalid.s | .arch armv8.8-a
cpyfp x0, [x1]!, x2!
cpyfp x0!, [x1]!, x2!
cpyfp [x0], [x1]!, x2!
cpyfp [x0, #0]!, [x1]!, x2!
cpyfp [x0, xzr]!, [x1]!, x2!
cpyfp [x1]!, x0, x2!
cpyfp [x1]!, x0!, x2!
cpyfp [x1]!, [x0], x2!
cpyfp [x1]!, [x0, #0]!, x2!
cpyfp [x1]!, [x0, xzr]!, x2!
cpyfp [x0]!, [x1]!, x2
cpyfp [x0]!, [x1]!,... |
stsp/binutils-ia16 | 35,779 | gas/testsuite/gas/aarch64/sve-invalid.s | // Instructions in this file are invalid unless explicitly marked "OK".
// Other files provide more extensive testing of valid instructions;
// the only purpose of the valid instructions in this file is to show
// that the general form of the operands is correct.
fmov z1, z2
fmov z1, #1.0
fmov z1, #0.0
not z0.s,p... |
stsp/binutils-ia16 | 1,061 | gas/testsuite/gas/aarch64/undefined_by_elem_sz_l.s | # Generates tests to see if setting bit 22 (sz) and 21 (L) together correctly
# marks the instruction as undefined. This pattern can't be created by the
# assembler so instead manually encode it.
.macro gen_insns opc
.inst \opc
.inst (\opc | 0x600000)
.endm
# fmul s0, s0, v16.s[0]
gen_insns 0x5f909000
# fmla s0,... |
stsp/binutils-ia16 | 14,164 | gas/testsuite/gas/aarch64/illegal.s | /* illegal.s Test file for AArch64 instructions that should be rejected
by the assembler.
Copyright (C) 2011-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public L... |
stsp/binutils-ia16 | 2,866 | gas/testsuite/gas/aarch64/fp_cvt_int.s | /* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point
conversion and floating-point<->integer conversion instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it... |
stsp/binutils-ia16 | 1,133 | gas/testsuite/gas/aarch64/msr.s | /*
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, ... |
stsp/binutils-ia16 | 35,401 | gas/testsuite/gas/aarch64/sve2.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
stsp/binutils-ia16 | 6,553 | gas/testsuite/gas/aarch64/sysreg-1.s | /* sysreg-1.s Test file for AArch64 system registers.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free So... |
stsp/binutils-ia16 | 1,161 | gas/testsuite/gas/aarch64/sve-movprfx_25.s | /* Checks that CPY is allowed after a movprfx, special case in that SIMD&Scalar
version is also valid and Pg is 4 bits rather than 3.
Has invalid usages. Diagnosis required. */
.text
.arch armv8-a+sve
f:
/* OK, immediate predicated, alias mov. */
movprfx z1.d, p1/m, z3.d
cpy z1.d, p1/m, #12
/* ... |
stsp/binutils-ia16 | 1,728 | gas/testsuite/gas/aarch64/virthostext.s | /* virthostext.s Test file for ARMv8.1 Virtualization Host Extension
support.
Copyright (C) 2015-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as pu... |
stsp/binutils-ia16 | 1,126 | gas/testsuite/gas/aarch64/pac.s | /* ARMv8.3 Pointer authentication instructions. */
.text
/* Basic instructions. */
pacia x3, x4
pacia x5, sp
pacib x3, x4
pacib x5, sp
pacda x3, x4
pacda x5, sp
pacdb x3, x4
pacdb x5, sp
autia x3, x4
autia x5, sp
autib x3, x4
autib x5, sp
autda x3, x4
autda x5, sp
autdb x3, x4
autdb x5, sp
paci... |
stsp/binutils-ia16 | 1,464 | gas/testsuite/gas/aarch64/illegal-3.s | // Test the disassembler's detection of illegal binary sequences.
// PR 21380:
.inst 0x4dc2d4ec
.inst 0x4de2d4fc
.inst 0x4dc2f4ec
.inst 0x4de2f4fc
// PR 20319:
# Check FMOV for Unallocated Encodings
# FMOV (register): type == 0x10
.inst 0x1ea04000
# FMOV (scalar, immediate): type == 0x10... |
stsp/binutils-ia16 | 1,515 | gas/testsuite/gas/aarch64/crypto.s | /* crypto.s Test file for AArch64 Advanced-SIMD Crypto instructions.
Copyright (C) 2012-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
... |
stsp/binutils-ia16 | 1,323 | gas/testsuite/gas/aarch64/illegal-memtag.s | func:
# ADDG/SUBG : Fail uimm6
addg x1, x2, #0x3ef, #0x6
subg x1, x2, #0x400, #0x3
subg x1, x2, -16, #0x3
# ADDG/SUBG : Fail uimm4
addg x1, x2, #0x3f0, #0x10
subg x1, x2, #0x3f0, -4
# STG/STZG/ST2G/LDG : Fail imm
stg x2, [x1, #15]
stzg x2, [x1, #-4097]!
st2g x2, [x1], #4096
ldg x1, [x2, #33]
ldg x1, [x2,... |
stsp/binutils-ia16 | 2,507 | gas/testsuite/gas/aarch64/sme-4.s | /* SME Extension (ZERO). */
/* An all-zeros immediate is disassembled as an empty list { }. */
zero { }
/* An all-ones immediate is disassembled as {ZA}. */
zero { za }
zero { za0.b }
zero { za0.h, za1.h }
zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d }
zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2... |
stsp/binutils-ia16 | 1,315 | gas/testsuite/gas/aarch64/mops_invalid_2.s | .arch armv8.8-a+sve
cpyfpwtn [x0]!, [x1]!, x2!
cpyfewtn [x0]!, [x1]!, x2!
cpyfmwtn [x0]!, [x1]!, x2!
cpyfpwtn [x0]!, [x1]!, x2!
cpyfmtn [x0]!, [x1]!, x2!
cpyfetn [x0]!, [x1]!, x2!
cpyp [x0]!, [x1]!, x2!
setm [x0]!, x1!, x2
sete [x0]!, x1!, x2
cpyfpwt [x0]!, [x1]!, x2!
cpyfmwt [x3]!, [x1]!, x2!
cpyfewt ... |
stsp/binutils-ia16 | 1,378 | gas/testsuite/gas/aarch64/sysreg-2.s | /* sysreg-2.s Test file for ARMv8.2 system registers. */
.macro rw_sys_reg sys_reg xreg r w
.ifc \w, 1
msr \sys_reg, \xreg
.endif
.ifc \r, 1
mrs \xreg, \sys_reg
.endif
.endm
.text
rw_sys_reg sys_reg=id_aa64mmfr1_el1 xreg=x5 r=1 w=0
rw_sys_reg sys_reg=id_aa64mmfr2_el1 xreg=x7 r=1 w=0
/* RAS extension. ... |
stsp/binutils-ia16 | 4,188 | gas/testsuite/gas/aarch64/sme-i64.s | /* Scalable Matrix Extension (SME I64). */
/* ADDHA 64-bit variant. */
addha za0.d, p0/m, p1/m, z1.d
addha za1.d, p2/m, p3/m, z2.d
addha za2.d, p4/m, p5/m, z3.d
addha za3.d, p6/m, p7/m, z4.d
addha za4.d, p1/m, p0/m, z5.d
addha za5.d, p3/m, p2/m, z6.d
addha za6.d, p5/m, p4/m, z7.d
addha za7.d, p7/m, p6/m, z8.d
addha ... |
stsp/binutils-ia16 | 2,722 | gas/testsuite/gas/aarch64/v8-r-sysregs.s | // Armv8-R system registers
mrs x0, mpuir_el1
mrs x0, mpuir_el2
mrs x0, prbar_el1
msr prbar_el1, x0
mrs x0, prbar_el2
msr prbar_el2, x0
mrs x0, prbar1_el1
msr prbar1_el1, x0
mrs x0, prbar2_el1
msr prbar2_el1, x0
mrs x0, prbar3_el1
msr prbar3_el1, x0
mrs x0, prbar4_el1
msr prbar4_el1, x0
mrs x0, prbar5_el1
msr prbar5_el... |
stsp/binutils-ia16 | 2,807 | gas/testsuite/gas/aarch64/ls64-invalid.s | /* Atomic 64-byte load/store instructions limit register number Rt to below
condition: the <Xt> register number should be even and <= 22. */
.arch armv8.7-a+ls64
/* Single-copy Atomic 64-byte Load. */
ld64b x0, [x1]
ld64b x1, [x1]
ld64b x2, [x1]
ld64b x3, [x1]
ld64b x4, [x1]
ld64b x5, [x1]
ld64b x6, [x1]
... |
stsp/binutils-ia16 | 3,352 | gas/testsuite/gas/aarch64/sve-movprfx.s | movprfx z0, z0
MOVPRFX Z0, Z0
movprfx z1, z0
MOVPRFX Z1, Z0
movprfx z31, z0
MOVPRFX Z31, Z0
movprfx z0, z2
MOVPRFX Z0, Z2
movprfx z0, z31
MOVPRFX Z0, Z31
movprfx z0.b, p0/z, z0.b
MOVPRFX Z0.B, P0/Z, Z0.B
movprfx z1.b, p0/z, z0.b
MOVPRFX Z1.B, P0/Z, Z0.B
movprfx z31.b, p0/z, ... |
stsp/binutils-ia16 | 1,795 | gas/testsuite/gas/aarch64/tls.s | /* tls.s Test file for AArch64 TLS relocations.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software... |
stsp/binutils-ia16 | 1,212 | gas/testsuite/gas/aarch64/sme-7-illegal.s | /* Scalable Matrix Extension (SME). */
/* Load vector to ZA array. */
ldr za[w11, 0], [x0]
ldr za[w12, 1], [sp, x0]
ldr za[w12, 0], [sp, #1, mul vl]
ldr za[w13, 9], [x17, #19, mul vl]
ldr za[w13, 21], [x17, #21, mul vl]
ldr za[w15, 32], [x17, #15, mul vl]
ldr za[w16, 15], [sp, #15, mul vl]
ldr za[w12, 0], [x0, #0, m... |
stsp/binutils-ia16 | 1,704 | gas/testsuite/gas/aarch64/sme-6-illegal.s | /* Scalable Matrix Extension (SME). */
st1b {za0h.b[w11, 0]}, p0, [x0]
st1h {za0h.h[w16, 0]}, p0, [x0]
st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #3]
st1w {za3v.s[w15, 3]}, p7, [sp, lsl #2]
st1d {za0h.d[w12, 0]}, p0, [sp, x0, lsl #12]
st1q {za0v.q[w12]}, p0, [x0, x0, lsl #2]
st1b {za1h.b[w12, 0]}, p0, [x0]
st1b {za1v.b[... |
stsp/binutils-ia16 | 2,279 | gas/testsuite/gas/aarch64/brbe.s | /* Branch Record Buffer Extension system registers. */
/* Read from BRBE system registers. */
mrs x0, brbcr_el1
mrs x0, brbcr_el12
mrs x0, brbfcr_el1
mrs x0, brbts_el1
mrs x0, brbinfinj_el1
mrs x0, brbsrcinj_el1
mrs x0, brbtgtinj_el1
mrs x0, brbidr0_el1
mrs x0, brbcr_el2
mrs x0, brbsrc0_el1
mrs x0, brbsrc10_el1
mrs ... |
stsp/binutils-ia16 | 6,813 | gas/testsuite/gas/aarch64/etm.s | /* ETMv4 system registers. */
/* Read from system register. */
mrs x0, trcacatr0
mrs x0, trcacatr1
mrs x0, trcacatr2
mrs x0, trcacatr3
mrs x0, trcacatr4
mrs x0, trcacatr5
mrs x0, trcacatr6
mrs x0, trcacatr7
mrs x0, trcacatr8
mrs x0, trcacatr9
mrs x0, trcacatr10
mrs x0, trcacatr11
mrs x0, trcacatr12
mrs x0, trcacatr... |
stsp/binutils-ia16 | 1,090 | gas/testsuite/gas/aarch64/crc32.s | /* crc32.s Test file for AArch64 CRC-32 and CRC-32C checksum instructions.
Copyright (C) 2013-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as publis... |
stsp/binutils-ia16 | 1,184 | gas/testsuite/gas/aarch64/advsisd-copy.s | /* advsisd-copy.s Test file for AArch64 Advanced-SISD copy instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as publishe... |
stsp/binutils-ia16 | 47,576 | gas/testsuite/gas/aarch64/illegal-sve2.s | movprfx z0.d, z1.d
adclb z0.d, z1.d, z2.d
movprfx z0.d, p0/m, z1.d
adclb z0.d, z1.d, z2.d
adclb z0.d, z0.s, z0.s
adclb z32.d, z0.d, z0.d
adclb z0.d, z32.d, z0.d
adclb z0.d, z0.d, z32.d
adclt z0.d, z0.s, z0.s
adclt z32.s, z0.s, z0.s
adclt z0.s, z32.s, z0.s
adclt z0.s, z0.s, z32.s
addhnb z0.b, z0.h, z0.b
addhnb z32.b,... |
stsp/binutils-ia16 | 3,482 | gas/testsuite/gas/aarch64/sme-5.s | /* SME Extension (LD1x instructions). */
ld1b {za0h.b[w12, 0]}, p0/z, [x0]
ld1b {za0h.b[w12, 0]}, p0/z, [sp]
ld1b {za0h.b[w12, 0]}, p0/z, [sp, x0]
ld1b {za0h.b[w15, 15]}, p7/z, [x17]
ld1b {za0h.b[w15, 15]}, p7/z, [sp]
ld1b {za0h.b[w15, 15]}, p7/z, [sp, x17]
ld1h {za0h.h[w12, 0]}, p0/z, [x0]
ld1h {za0h.h[w12, 0]}, p0/... |
stsp/binutils-ia16 | 3,639 | gas/testsuite/gas/aarch64/sve-add.s | add z0.b, z0.b, #-255
add z0.b, z0.b, #-129
add z0.b, z0.b, #-128
add z0.b, z0.b, #-127
add z0.b, z0.b, #-1
add z0.b, z0.b, #0
add z0.b, z0.b, #1
add z0.b, z0.b, #127
add z0.b, z0.b, #128
add z0.b, z0.b, #255
add z0.h, z0.h, #-65536
add z0.h, z0.h, #-65535
add z0.h, z0.h, #-65536 + 127
add z0.h, z0.h, #-... |
stsp/binutils-ia16 | 2,209 | gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s | /* ldst-reg-reg-offset.s Test file for AArch64 load-store reg. (reg.offset)
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public... |
stsp/binutils-ia16 | 3,034 | gas/testsuite/gas/aarch64/sme-illegal.s | /* Scalable Matrix Extension (SME). */
/* ADDHA 32-bit variant. */
addha za4.s, p0/m, p1/m, z1.s
addha za15.s, p2/m, p3/m, z2.s
addha za0.s, p2/m, p3/m, z2.d
/* ADDHA 64-bit variant. */
addha za8.d, p0/m, p1/m, z1.d
addha za15.d, p2/m, p3/m, z2.d
addha za0.d, p2/m, p3/m, z2.s
/* ADDVA 32-bit variant. */
addva za... |
stsp/binutils-ia16 | 3,239 | gas/testsuite/gas/aarch64/neon-fp-cvt-int.s | /* neon-fp-cvt-ins.s Test file for AArch64 NEON
floating-point<->fixed-point conversion and
floating-point<->integer conversion instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or... |
stsp/binutils-ia16 | 3,107 | gas/testsuite/gas/aarch64/sve-dup.s | dup z0.b, #-255
dup z0.b, #-129
dup z0.b, #-128
dup z0.b, #-127
dup z0.b, #-1
dup z0.b, #0
dup z0.b, #1
dup z0.b, #127
dup z0.b, #128
dup z0.b, #255
dup z0.h, #-65535
dup z0.h, #-65536 + 127
dup z0.h, #-65536 + 256
dup z0.h, #-32768
dup z0.h, #-32768 + 256
dup z0.h, #-128
dup z0.h, #-127
dup z0.h, #-... |
stsp/binutils-ia16 | 1,792 | gas/testsuite/gas/aarch64/i8mm.s | /* The instructions with non-zero register numbers are there to ensure we have
the correct argument positioning (i.e. check that the first argument is at
the end of the word etc).
The instructions with all-zero register numbers are to ensure the previous
encoding didn't just "happen" to fit -- so that if we... |
stsp/binutils-ia16 | 2,442 | gas/testsuite/gas/aarch64/illegal-sysreg-8.s | .macro roreg, name
mrs x0, \name
.endm
.macro woreg, name
msr \name, x1
.endm
.macro rwreg, name
mrs x2, \name
msr \name, x3
.endm
roreg lorid_el1
.arch armv8.2-a
roreg ccsidr2_el1
.arch armv8.3-a
rwreg trfcr_el1
roreg pmmir_el1
rwreg trfcr_el2
rwreg trfcr_el12
rwreg amcr_el0
roreg amcfgr_e... |
stsp/binutils-ia16 | 1,279 | gas/testsuite/gas/aarch64/advsimd-across.s | /* advsimd-across.s Test file for AArch64 Advanced-SIMD across
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as p... |
stsp/binutils-ia16 | 1,335 | gas/testsuite/gas/aarch64/armv8_4-a-registers-illegal.s | # Secure second stage
MRS W0, VSTTBR_EL2
MRS W0, VSTCR_EL2
# Timer changes
MRS W0, CNTP_TVAL_EL0
MRS W0, CNTP_CTL_EL0
MRS W0, CNTP_CVAL_EL0
MRS W0, CNTV_TVAL_EL0
MRS W0, CNTV_CTL_EL0
MRS W0, CNTV_CVAL_EL0
MRS W0, CNTHVS_TVAL_EL2
MRS W0, CNTHVS_CVAL_EL2
MRS W0, CNTHVS_CTL_EL2
MRS W0, CNTHPS_TVAL_EL2
MRS W0, CNTHPS_CVA... |
stsp/binutils-ia16 | 2,037 | gas/testsuite/gas/aarch64/illegal-bfloat16.s | // SVE
bfdot z0.s, z1.h, z2.s // Fails from size types
bfdot z0.s, z1.h, z3.s[3] // Fails from size types
bfdot z0.s, z1.h, z3.h[4] // Fails from index size
bfdot z0.s, z1.h, z8.h[3] // Fails from vector number
bfmmla z0.s, z1.h, z2.s // Fails from size types
bfcvt z0.h, p1/z, z2.s // Fails from merge ... |
stsp/binutils-ia16 | 1,624 | gas/testsuite/gas/aarch64/illegal-by-element.s | .text
.macro gen_illegal op, p1, p2, p3
.irp w, v16.\p3, v27.\p3, v31.\p3
\op v2.\p1, v12.\p2, \w[0]
.endr
.endm
.macro gen_illegal2 op, p1, p2, p3
.irp x, \p1\()2
.irp y, \p2\()12
.irp w, v16.\p3, v27.\p3, v31.\p3
\op \x, \y, \w[0]
.endr
.endr
.endr
.endm
gen_illegal fmla, 4h, 4h, h
gen_illegal fml... |
stsp/binutils-ia16 | 2,190 | gas/testsuite/gas/aarch64/programmer-friendly.s | // programmer-friendly.s Test file for AArch64 instructions variants that are
// not part of the architectural assembly syntax but are supported for the
// ease of assembly level programming.
.text
// The preferred architectural syntax does not accept the shifter
// LSL or any other shift operator, when the destinat... |
stsp/binutils-ia16 | 2,925 | gas/testsuite/gas/aarch64/sme-6.s | /* SME Extension (ST1x instructions). */
st1b {za0h.b[w12, 0]}, p0, [x0]
st1b {za0h.b[w12, 0]}, p0, [sp]
st1b {za0h.b[w12, 0]}, p0, [sp, x0]
st1b {za0h.b[w15, 15]}, p7, [x17]
st1b {za0h.b[w15, 15]}, p7, [sp]
st1b {za0h.b[w15, 15]}, p7, [sp, x17]
st1h {za0h.h[w12, 0]}, p0, [x0]
st1h {za0h.h[w12, 0]}, p0, [sp]
st1h {za... |
stsp/binutils-ia16 | 1,447 | gas/testsuite/gas/aarch64/advsimd-armv8_3.s | /* Test file for ARMv8.3 complex arithmetics instructions. */
.text
.macro three_same op, sz
.irp rot, 0, 90, 180, 270
.irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
.irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
.irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
\op v\d, v\m, v\n, #\rot
.endr
.endr
.endr
.endr
.endm... |
stsp/binutils-ia16 | 2,107 | gas/testsuite/gas/aarch64/sme-5-illegal.s | /* Scalable Matrix Extension (SME). */
ld1b {za0h.b[w11, 0]}, p0/z, [x0]
ld1h {za0h.h[w16, 0]}, p0/z, [x0]
ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #3]
ld1w {za3v.s[w15, 3]}, p7/z, [sp, lsl #2]
ld1d {za0h.d[w12, 0]}, p0/z, [sp, x0, lsl #12]
ld1q {za0v.q[w12]}, p0/z, [x0, x0, lsl #2]
ld1b {za1h.b[w12, 0]}, p0/z, [x0]
... |
stsp/binutils-ia16 | 1,304 | gas/testsuite/gas/aarch64/ls64.s | /* Atomic 64-byte load/store instructions. */
.arch armv8.6-a+ls64
/* Single-copy Atomic 64-byte Load. */
ld64b x0, [x1]
ld64b x2, [x1]
ld64b x4, [x1]
ld64b x6, [x1]
ld64b x8, [x1]
ld64b x10, [x1]
ld64b x12, [x1]
ld64b x14, [x1]
ld64b x16, [x1]
ld64b x18, [x1]
ld64b x20, [x1]
ld64b x22, [x1]
/* Single-c... |
stsp/binutils-ia16 | 3,400 | gas/testsuite/gas/aarch64/int-insns.s | // Test file for AArch64 GAS -- basic integer instructions
func:
lsl x1, x2, x3
lsl x1, x2, #0
lsl x1, x2, #1
extr x1, x2, x3, #1
extr x1, x2, x3, #63
extr x1, x2, x3, #0
extr w1, w2, w3, #31
CSET x1, e... |
stsp/binutils-ia16 | 4,081 | gas/testsuite/gas/aarch64/sme.s | /* Scalable Matrix Extension (SME). */
/* ADDHA 32-bit variant. */
addha za0.s, p0/m, p1/m, z1.s
addha za1.s, p2/m, p3/m, z2.s
addha za2.s, p4/m, p5/m, z3.s
addha za3.s, p6/m, p7/m, z4.s
/* ADDVA 32-bit variant. */
addva za0.s, p0/m, p1/m, z1.s
addva za1.s, p2/m, p3/m, z2.s
addva za2.s, p4/m, p5/m, z3.s
addva za3.... |
stsp/binutils-ia16 | 2,784 | gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s | /* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm)
instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License... |
stsp/binutils-ia16 | 1,280,904 | gas/testsuite/gas/aarch64/sve.s | .equ z0, 1
.equ z0.b, 1
.equ z0.h, 1
.equ z0.s, 1
.equ z0.d, 1
.equ p0, 1
.equ p0.b, 1
.equ p0.h, 1
.equ p0.s, 1
.equ p0.d, 1
.equ b0, 1
.equ h0, 1
.equ s0, 1
.equ d0, 1
.equ w0, 1
.equ x0, 1
fmov z0.h, #2.0000000000
FMOV Z0.H, #2.0000000000
fmov z1.h, #2.0000000000
FMOV Z1.H, #... |
stsp/binutils-ia16 | 16,200 | gas/testsuite/gas/aarch64/dotproduct.s | UDOT V0.2S, V0.8B, V0.8B
UDOT V0.2S, V0.8B, V11.8B
UDOT V0.2S, V0.8B, V22.8B
UDOT V0.2S, V11.8B, V0.8B
UDOT V0.2S, V11.8B, V11.8B
UDOT V0.2S, V11.8B, V22.8B
UDOT V0.2S, V22.8B, V0.8B
UDOT V0.2S, V22.8B, V11.8B
UDOT V0.2S, V22.8B, V22.8B
UDOT V11.2S, V0.8B, V0.8B
UDOT V11.2S, V0.8B, V11.8B
UDOT V11.2S, V0.8B, V22.8B
UDO... |
stsp/binutils-ia16 | 3,643 | gas/testsuite/gas/aarch64/sysreg-8.s | .macro roreg, name
mrs x0, \name
.endm
.macro woreg, name
msr \name, x1
.endm
.macro rwreg, name
mrs x2, \name
msr \name, x3
.endm
roreg id_dfr1_el1
roreg id_mmfr5_el1
roreg id_isar6_el1
rwreg icc_pmr_el1
roreg icc_iar0_el1
woreg icc_eoir0_el1
roreg icc_hppir0_el1
rwreg icc_bpr0_el1
rwreg icc_ap0... |
stsp/binutils-ia16 | 1,704 | gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s | /* ldst-reg-imm-post-ind.s Test file for AArch64
load-store reg. (imm.post-ind.) instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General P... |
stsp/binutils-ia16 | 2,579 | gas/testsuite/gas/aarch64/ldst-reg-pair.s | /* ldst-reg-pair.s Test file for AArch64 load-store reg.pair instructions.
Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as publis... |
stsp/binutils-ia16 | 1,877 | gas/testsuite/gas/aarch64/illegal-lse.s | /* illegal-lse.s Test file For AArch64 LSE atomic instructions that
could be rejected by the assembler.
Copyright (C) 2014-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU ... |
stsp/binutils-ia16 | 1,183 | gas/testsuite/gas/aarch64/lor.s | /* lor.s Test file for AArch64 LOR extension instructions.
Copyright (C) 2015-2022 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free... |
stsp/binutils-ia16 | 1,171 | gas/testsuite/gas/aarch64/verbose-error.s | // verbose-error.s Test file for -mverbose-error
.text
strb w7, [x30, x0, lsl]
ubfm w0, x1, 8, 31
bfm w0, w1, 8, 43
strb w7, [x30, x0, lsl #1]
st2 {v4.2d,v5.2d},[x3,#3]
fmov v1.D[0],x0
ld1r {v1.4s, v2.4s, v3.4s}, [x3], x4
svc
add v0.4s, v1.4s, v2.2s
urecpe v0.1d,v7.1d
adds w0, wsp, x0, uxtx #1
fmov d0, s0
... |
stsp/binutils-ia16 | 2,902 | gas/testsuite/gas/aarch64/alias.s | /* alias.s Test file for AArch64 instructions aliases or disassembly
preference. It is also used to test the -Mno-aliases option in
the disassemler.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute i... |
stsp/binutils-ia16 | 13,140 | gas/testsuite/gas/ft32/insnsc.s | .section .text
add $r21,$r21,$r0
sub $r21,$r21,$r0
and $r21,$r21,$r0
or $r21,$r21,$r0
bins $r21,$r21,$r0
add $r21,$r21,$r1
sub $r21,$r21,$r1
and $r21,$r21,$r1
or $r21,$r21,$r1
ashl $r21,$r21,$r1
bins $r21,$r21,$r1
add $r21,$r21,$r2
sub $r21,$r21,$r2
and $r21,$r21,$r2
or $r21,$r21,$r2
bins $r21,$... |
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