repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 1,081 | gas/testsuite/gas/mips/jalr4.s | .abicalls
.text
.align 2
.globl foo
.ent foo
foo:
.reloc 1f, R_MIPS_JALR, bar0
1: jalr $25
.reloc 1f, R_MIPS_JALR, bar0
1: jalr $0, $25
.reloc 1f, R_MIPS_JALR, bar0
1: jr $25
.reloc 1f, R_MIPS_JALR, bar1
1: jalr $25
.reloc 1f, R_MIPS_JALR, bar1
1: jalr $0, $25
.reloc 1f, R_MIPS_JALR, bar1
1: jr $25
.reloc ... |
stsp/binutils-ia16 | 2,193 | gas/testsuite/gas/mips/elf-rel-got-n64.s | # MIPS ELF GOT reloc n64
.data
.align 3
sp1:
.space 60
.globl dg1
dg1:
dl1:
.space 60
.text
.globl fn
.ent fn
.type fn,@function
fn:
.Lfn:
dla $5,dg1+0
dla $5,dg1+12
dla $5,dg1+123456
dla $5,dg1+0($17)
dla $5,dg1+12($17)
dla $5,dg1+123456($17)
ld $5,dg1+0
ld $5,dg1+12
ld $5,dg1+0($17)
ld $5,dg1... |
stsp/binutils-ia16 | 1,768 | gas/testsuite/gas/mips/ldstla-32-1.s |
.text
ld $2, 0xfffffffeffffffff($4)
ld $2, 0xfffffffe00000000($4)
ld $2, 0xabcdef0123456789($4)
ld $2, 0x0123456789abcdef($4)
ld $2, 0x00000001ffffffff($4)
ld $2, 0x0000000100000000($4)
ld $2, 0xfffffffeffffffff
ld $2, 0xfffffffe00000000
ld $2, 0xabcdef0123456789
ld $2, 0x0123456789abcdef
ld $2, 0x0000000... |
stsp/binutils-ia16 | 1,849 | gas/testsuite/gas/mips/ush.s | # Source file used to test the ush macro.
.data
data_label:
.extern big_external_data_label,1000
.extern small_external_data_label,1
.comm big_external_common,1000
.comm small_external_common,1
.lcomm big_local_common,1000
.lcomm small_local_common,1
.text
ush $4,0
ush $4,1
ush $4,0x8000
ush $4,-0x8000
... |
stsp/binutils-ia16 | 1,161 | gas/testsuite/gas/mips/compact-eh-5.s | .gnu_attribute 4, 1
.abicalls
.hidden DW.ref.__gnu_compact_pr2
.weak DW.ref.__gnu_compact_pr2
.section .data.DW.ref.__gnu_compact_pr2,"awG",@progbits,DW.ref.__gnu_compact_pr2,comdat
.align 2
.type DW.ref.__gnu_compact_pr2, @object
.size DW.ref.__gnu_compac... |
stsp/binutils-ia16 | 1,355 | gas/testsuite/gas/mips/unaligned-branch-mips16-1.s | .text
.set noreorder
.space 0x1000
.align 4
.set mips16
.ent foo
foo:
not $2, $3
b bar0
not $2, $3
b bar1
not $2, $3
b bar2
not $2, $3
b bar3
not $2, $3
b bar4
not $2, $3
b bar4 + 1
not $2, $3
b bar4 + 2
not $2, $3
b bar4 + 3
not $2, $3
b bar4 + 4
not $2, $3
b bar16
not $2, $3
b b... |
stsp/binutils-ia16 | 1,510 | gas/testsuite/gas/mips/dli.s | # Source file used to test the dli macro.
foo:
dli $4,0
dli $4,1
dli $4,-1
dli $4,0x8000
dli $4,-0x8000
dli $4,0x10000
dli $4,0x1a5a5
dli $4,0x80001234
dli $4,0xffffffff
dli $4,0x00000000ffffffff
dli $4,0xffffffffffffffff
dli $4,0x000fffffffffffff
dli $4,0xffffffff80001234
dli $4,0xffff800012345678
dl... |
stsp/binutils-ia16 | 2,158 | gas/testsuite/gas/mips/unaligned-jump-micromips-2.s | .text
.set noreorder
.space 0x1000
.align 4
.set micromips
.ent foo
foo:
not $2, $3
jalx bar0
not $2, $3
jal bar0
not $2, $3
jals bar0
not $2, $3
j bar0
not $2, $3
jalx bar1
not $2, $3
jal bar1
not $2, $3
jals bar1
not $2, $3
j bar1
not $2, $3
jalx bar2
not $2, $3
jal bar2
not $2, ... |
stsp/binutils-ia16 | 4,686 | gas/testsuite/gas/mips/mips64r2-ill.s | # source file to test illegal mips64r2 instructions
.set noreorder
.set noat
.text
text_label:
# dext macro position/size checks
# constraint: 0 <= pos < 64
dext $4, $5, -1, 1 # error (position)
dext $4, $5, 0, 1
dext $4, $5, 63, 1
dext $4, $5, 64, 1 # error (position)
# constrain... |
stsp/binutils-ia16 | 1,966 | gas/testsuite/gas/mips/loongson-2f-mmi.s | .text
.set noreorder
simd_insns:
packsshb $f0, $f1, $f2
packsswh $f3, $f4, $f5
packushb $f6, $f7, $f8
paddb $f9, $f10, $f11
paddh $f12, $f13, $f14
paddw $f15, $f16, $f17
paddd $f18, $f19, $f20
paddsb $f21, $f22, $f23
paddsh $f24, $f25, $f26
paddusb $f27, $f28, $f29
paddush $f0, $f1, $f2
pandn $f... |
stsp/binutils-ia16 | 2,124 | gas/testsuite/gas/mips/vr5400.s | .text
stuff:
.ent stuff
/* Integer instructions. */
mul $4,$5,$6
mulu $4,$5,$6
mulhi $4,$5,$6
mulhiu $4,$5,$6
muls $4,$5,$6
mulsu $4,$5,$6
mulshi $4,$5,$6
mulshiu $4,$5,$6
macc $4,$5,$6
maccu $4,$5,$6
macchi $4,$5,$6
macchiu $4,$5,$6
msac $4,$5,$6
msacu $4,$5,$6
msachi $4,$5,$6
msachiu $4,$5,$6
... |
stsp/binutils-ia16 | 3,027 | gas/testsuite/gas/mips/ldstla-32.s | .text
ld $2, 0xffffffffffffffff($4)
ld $2, 0xffffffffabcdef01($4)
ld $2, 0xffffffff80000000($4)
ld $2, 0xffffffff7fffffff($4)
ld $2, 0xffffffff01234567($4)
ld $2, 0xffffffff00000000($4)
ld $2, 0xffffffff($4)
ld $2, 0xabcdef01($4)
ld $2, 0x80000000($4)
ld $2, 0x7fffffff($4)
ld $2, 0x01234567($4)
ld $2, 0x00... |
stsp/binutils-ia16 | 2,845 | gas/testsuite/gas/pdp11/opcode.s | # Opcode test for PDP-11.
# Copyright (C) 2002-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later... |
stsp/binutils-ia16 | 1,771 | gas/testsuite/gas/m68hc11/9s12x-mov.s | # Test for correct generation of 9s12x specific moves
.sect .text
;;
;; Test all s12x extended forms of movb, movw
;; page 273 et seq in S12XCPUV2
;;
v1=4
v2=68
v3=88
v4=0x89
v5=0xfe
v6=0x80
a1=0x1234
a2=0x3456
a3=0x8123
a4=0xc567
a5=0x2987
a6=0x1009
;movb
movb #v1, a1
movb #v2, 0,x
movb #v3,... |
stsp/binutils-ia16 | 1,541 | gas/testsuite/gas/m68hc11/insns9s12xg.s | # XGATE instruction set and all modes
.sect .text
val1 = 0x1234
val2 = 0x5432
u08_1 = 0x32
u08_2 = 0xa5
label1:
adc r1,r2,r3
label2:
add r4,r6,r1
label3:
add r7,#val1 ;splits out to addh, addl
addl r4,#u08_2
addh r4,#u08_1
and r7,r6,r5
and r2,#val2
andl r1, #u08_2
andh r1, #u08_1
asr r2,#3
asr r3,r4
bc... |
stsp/binutils-ia16 | 1,724 | gas/testsuite/gas/m68hc11/opers12.s |
#
# Try to verify all operand modes for 68HC12
#
sect .text
globl start
start:
anda [12,x] ; Indexed indirect
ldaa #10
ldx L1
L1: ldy ,x
addd 1,y ; Offset from register
subd -1,y
eora 15,y
eora -16,y
eorb 16,y
eorb -17,y
oraa 128,sp
orab -128,sp
orab 255,x
orab -256,x
anda 256,x
andb -257,x
anda [... |
stsp/binutils-ia16 | 3,160 | gas/testsuite/gas/m68hc11/indexed12.s | ;;
;; This file verifies the 68HC12 indexed addressing modes
;; with a 5, 9 and 16-bit offset.
;;
.sect .text
.globl _main
_main:
nop
;;; Global check (1st)
ldab L1-_main,x ; Offset/const of these 2 insns must be
ldaa #L1-_main ; identical (likewise for 2nd global check)
;;; Test gas relax with difference of symbo... |
stsp/binutils-ia16 | 1,261 | gas/testsuite/gas/m68hc11/insns9s12x.s | # Test for correct generation of 9s12x specific insns.
.sect .text
addx #0x5678
addy 2,x+
aded 0,x
adex 2,-y
adey [d,x]
andx #0x9988
andy 0x55aa
aslw 0x2004
aslx
asly
asrw 0x3000,y
asrx
asry
bitx [0x3456,sp]
bity [d,sp]
... |
stsp/binutils-ia16 | 4,821 | gas/testsuite/gas/m68hc11/malis.s | ;;
;; This file verifies the compliance with the Motorola specification:
;;
;; MOTOROLA STANDARDS
;; Document #1001, Version 1.0
;; SPECIFICATION FOR Motorola 8- and 16-Bit ASSEMBLY LANGUAGE INPUT STANDARD
;; 26, October 1999
;;
;; Available at:
;;
;; http://www.mcu.motsps.com/dev_tools/hc12/eabi/m8-16alis.pdf
;;
;; ... |
stsp/binutils-ia16 | 1,477 | gas/testsuite/gas/m68hc11/branchs12.s | #
# Try to verify all branchs for 68HC12
# Ensures that PC-relative relocations are correct.
#
sect .text
globl start
start:
L0:
;; Branchs to defined symbols, positive offset < 128
bgt L1
bge L1
ble L1
blt L1
bhi L1
bhs L1
bcc L1
beq L1
bls L1
blo L1
bcs L1
bmi L1
bvs L1
bra L1
bvc L1
bne L1
bpl L... |
stsp/binutils-ia16 | 2,258 | gas/testsuite/gas/m68hc11/9s12x-exg-sex-tfr.s | # Test for correct generation of 9s12x specific insns.
.sect .text
;;
;; Test all s12x extended forms of exg,tfr,sex where supported
;;
;; presently tmp register and h/l forms not supported in gas
;exg
;; none of shaded area is actually supported
exg a,a
exg b,a
; exg ccrh,a
; exg tmp3h,... |
stsp/binutils-ia16 | 5,500 | gas/testsuite/gas/m68hc11/movb.s | dog2=15
dog3=-16
dog4=7
dog5=-8
;; idx - idx
ldaa #0
movb 15,x,dog2,x
movb 15,x,cat2,x
movb 15,x,15,x
ldaa #1
movb dog2,x,15,x
movb cat2,x,15,x
movb 15,x,15,x
ldaa #2
movb 15,x,dog3,x
movb 15,x,cat3,x
movb 15,x,-16,x
ldaa #3
movb dog3,x,15,x
movb cat3,x,15,x
movb -16,x,15,x
ldaa #4
movw 15,x,... |
stsp/binutils-ia16 | 1,070 | gas/testsuite/gas/m68hc11/insns12.s | # Test for correct generation of 68HC12 specific insns.
.sect .text
;; Test the call insns
call_test:
call _foo ; 24-bit reloc
call _foo,1 ; 16-bit reloc, immediate page specification
call _foo,%page(foo_page) ; 16-bit reloc and 8-bit page reloc
call 0,x,3 ; 8-bit page reloc
call 4,y,12
call 7,sp,13
call 1... |
stsp/binutils-ia16 | 5,227 | gas/testsuite/gas/m68hc11/all_insns.s | # Example of M68hc11 instructions
.sect .text
_start:
L0: aba
L1: abx
L2: aby
L3: adca #103
L4: adca *Z198
L5: adca 105,X
L6: adca symbol115
L7: adca 81,X
L8: adcb #255
L9: adcb *Z74
L10: adcb 236,X
L11: adcb symbol41
L12: adcb 205,X
L13: adda #186
L14: adda *Z171
L15: adda 242,X
L16: adda symbol251
L17: adda 227,X... |
stsp/binutils-ia16 | 18,592 | gas/testsuite/gas/arm/thumb2_bad_reg.s | .syntax unified
.text
.align 2
.thumb
.thumb_func
test:
@ ADC (immediate)
adc r13, r0, #1
adc r15, r0, #1
adc r0, r13, #1
adc r0, r15, #1
@ ADC (register)
adc.w r13, r0, r1
adc.w r15, r0, r1
adc.w r0, r13, r1
adc.w r0, r15, r1
adc.w r0, r1, r13
adc.w r0, r1, r15
@ ADD (immediate)
add.... |
stsp/binutils-ia16 | 5,939 | gas/testsuite/gas/arm/cde-scalar.s | .syntax unified
# Extra tests everywhere:
# Ensure that setting the register to something in r[1-12] works.
# cx1{a} Has arguments in the following form
# 111a111000iiiiiidddd0pppi0iiiiii
#
# Variants to test:
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = ... |
stsp/binutils-ia16 | 1,314 | gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s | @ Tests that are meant to fail during encoding of LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.... |
stsp/binutils-ia16 | 3,072 | gas/testsuite/gas/arm/mve-vmov-2.s | .syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vm... |
stsp/binutils-ia16 | 7,483 | gas/testsuite/gas/arm/neon-const.s | @ test floating-point constant parsing.
.arm
.text
.syntax unified
vmov.f32 q0, 0.0
vmov.f32 q0, 2.0
vmov.f32 q0, 4.0
vmov.f32 q0, 8.0
vmov.f32 q0, 16.0
vmov.f32 q0, 0.125
vmov.f32 q0, 0.25
vmov.f32 q0, 0.5
vmov.f32 q0, 1.0
vmov.f32 q0, 2.1... |
stsp/binutils-ia16 | 3,646 | gas/testsuite/gas/arm/inst.s | @ Test file for ARM/GAS -- basic instructions
.text
.align
mov r0, #0
mov r1, r2
mov r3, r4, lsl #3
mov r5, r6, lsr r7
mov r8, r9, asr r10
mov r11, r12, asl r13
mov r14, r15, rrx
moval a2, a3
moveq a3, a4
movne v1, v2
movlt v3, v4
movge v5, v6
movle v7, v8
movgt ip, sp
movcc r1, r2
movcs r1, r3
movmi ... |
stsp/binutils-ia16 | 2,872 | gas/testsuite/gas/arm/iwmmxt2.s | .text
.global iwmmxt2
iwmmxt2:
waddhc wr4, wr5, wr6
waddwc wr7, wr8, wr9
wmadduxgt wr4, wr5, wr6
wmadduneq wr7, wr8, wr9
wmaddsxne wr4, wr5, wr6
wmaddsnge wr7, wr8, wr9
wmulumr wr1, wr2, wr3
wmulsmr wr1, wr2, wr3
torvscbgt r15
torvschne r15
torvscweq r15
wabsb wr1, wr2
wabsh wr3, wr4
wabsw w... |
stsp/binutils-ia16 | 1,159 | gas/testsuite/gas/arm/mve-vaddsub.s | .syntax unified
.thumb
.macro all_qqq op
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
\op \op1, \op2, \op3
.endr
.endr
.endr
.endm
.macro all_qqr op
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op \op1, \op2, \op3
.... |
stsp/binutils-ia16 | 2,348 | gas/testsuite/gas/arm/armv8-2-fp16-scalar-bad.s | .macro f16_sss_arithmetic reg0, reg1, reg2
.irp op, vdiv, vfma, vfms, vfnma, vfnms, vmla, vmls, vmul, vnmla, vnmls, vnmul, vsub
.irp cond, eq.f16, ne.f16, ge.f16, lt.f16, gt.f16, le.f16
\op\cond s\reg0, s\reg1, s\reg2
.endr
.endr
.endm
.macro f16_ss_arithmetic reg0, reg1
.irp op, vabs, vadd, vsqrt, vneg
... |
stsp/binutils-ia16 | 1,091 | gas/testsuite/gas/arm/armv1.s | .global entry
.text
entry:
and r0, r0, r0
ands r0, r0, r0
eor r0, r0, r0
eors r0, r0, r0
sub r0, r0, r0
subs r0, r0, r0
rsb r0, r0, r0
rsbs r0, r0, r0
add r0, r0, r0
adds r0, r0, r0
adc r0, r0, r0
adcs r0, r0, r0
sbc r0, r0, r0
sbcs r0, r0, r0
rsc r0, r0, r0
rscs r0, r0, r0
orr r0, r0, r0
orrs r0, r... |
stsp/binutils-ia16 | 1,326 | gas/testsuite/gas/arm/armv7e-m+fpv5-d16.s | .syntax unified
.text
.arch armv7e-m
.fpu fpv5-d16
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d8, d8, d8
vselge.f64 d15, d15, d15
vselgt.f64 d10, d10, d10
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s3... |
stsp/binutils-ia16 | 1,079 | gas/testsuite/gas/arm/neon-addressing-bad.s | .syntax unified
VLD1.8 {d0}, 1f
1:
VLD1.8 {D0}, R0
VLD1.8 {Q1}, R0
VLD1.8 {D0}, [PC]
VLD1.8 {D0}, [PC, #0]
VST1.8 {D0}, R0
VST1.8 {Q1}, R0
VST1.8 {D0}, [PC]
VST1.8 {D0}, [PC, #0]
VST1.8 {D0[]}, [R0]
VST2.8 {D0[], D2[]}, [R0]
VST3.16 {D0[], D1[], D2[]}, [R0]
VST4.32 {D0[], D1[], D2[], D3[]}, [R0]
VLD1.8 {Q0}, [R0, #8]
... |
stsp/binutils-ia16 | 1,725 | gas/testsuite/gas/arm/mve-vqdmladh.s | .syntax unified
.thumb
.irp data, s8, s16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
vqdmladh.\data \op1, \op2, \op3
vqdmladhx.\data \op1, \op2, \op3
vqrdmladh.\data \op1, \op2, \op3
vqrdmladhx.\data \op1, \op2, \op3
.endr
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3... |
stsp/binutils-ia16 | 1,392 | gas/testsuite/gas/arm/bundle.s | .syntax unified
.bundle_align_mode 4
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,16) by 2 or 4.
.macro offset_insn insn_name, offset, size
.p2align 4
\insn_name\()_offset_\offset\():
.rept \offset / \size
bkpt
.endr
\insn_name
.endm
.macro test_offsets_arm insn_... |
stsp/binutils-ia16 | 2,628 | gas/testsuite/gas/arm/thumb.s | .text
.code 16
.foo:
lsl r2, r1, #3
lsr r3, r4, #31
wibble/data:
asr r7, r0, #5
lsl r1, r2, #0
lsr r3, r4, #0
asr r4, r5, #0
lsr r6, r7, #32
asr r0, r1, #32
add r1, r2, r3
add r2, r4, #2
sub r3, r5, r7
sub r2, r4, #7
mov r4, #255
cmp r3, #250
add r6, #123
sub r5, #128
and r3, r5
eor r4, r6
l... |
stsp/binutils-ia16 | 4,160 | gas/testsuite/gas/arm/mve-vmov-3.s | vmov r0, r1, q1[2], q1[0]
vmov r0, r1, q2[2], q2[0]
vmov r0, r1, q3[2], q3[0]
vmov r0, r1, q4[2], q4[0]
vmov r0, r1, q5[2], q5[0]
vmov r0, r1, q6[2], q6[0]
vmov r0, r1, q7[2], q7[0]
vmov r1, r0, q0[2], q0[0]
vmov r2, r0, q0[2], q0[0]
vmov r3, r0, q0[2], q0[0]
vmov r4, r0, q0[2], q0[0]
vmov r5, r0, q0[2], q0[0]
vmov r6,... |
stsp/binutils-ia16 | 1,723 | gas/testsuite/gas/arm/mve-vqdmlsdh.s | .syntax unified
.thumb
.irp data, s8, s16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
vqdmlsdh.\data \op1, \op2, \op3
vqdmlsdhx.\data \op1, \op2, \op3
vqrdmlsdh.\data \op1, \op2, \op3
vqrdmlsdhx.\data \op1, \op2, \op3
.endr
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3,... |
stsp/binutils-ia16 | 1,225 | gas/testsuite/gas/arm/bundle-lock.s | .syntax unified
.bundle_align_mode 4
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,16) by 2 or 4.
size_arm = 4
size_thumb = 2
.macro offset_sequence which, size, offset
.p2align 4
\which\()_sequence_\size\()_offset_\offset\():
.rept \offset / size_\which
bkpt
.en... |
stsp/binutils-ia16 | 1,482 | gas/testsuite/gas/arm/branch-reloc.s | @ Check that non-local branches with and without mode switching
@ produce the right relocations with appropriate in-place addends.
.syntax unified
.text
.arm
.global arm_glob_sym1
.global arm_glob_sym2
.global thumb_glob_sym1
.global thumb_glob_sym2
nop
.type arm_glob_sym1, %function
arm_glob_sym1:
bl thumb... |
stsp/binutils-ia16 | 5,726 | gas/testsuite/gas/arm/vfp1xD_t2.s | @ VFP Instructions for v1xD variants (Single precision only)
@ Same as vfp1xD.s, but for Thumb-2
.syntax unified
.thumb
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison... |
stsp/binutils-ia16 | 2,779 | gas/testsuite/gas/arm/vldconst.s | @ Test file for ARM/GAS -- vldr reg, =... expressions.
.fpu neon
.text
.align
foo:
# test both low and high index of the
# Advanced SIMD and Floating-point reg.
.macro vlxr regtype const
.irp regindex, 0, 14, 28, 31
vldr \regtype\regindex, \const
.endr
.endm
.macro vlxreq regtype const
.irp regindex, 0... |
stsp/binutils-ia16 | 3,155 | gas/testsuite/gas/arm/mve-vldr-bad-3.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0]
.endr
.endm
.syntax unified
.thumb
vldrb.8 q0, [r0, #128]
vldrb.8 q0, [r0, #-128]
vldrb.u16 q0, [r0, #128]
vldrb.u16 q0, [r0, #-128]
vldrb.u32 q0, [r0, #128]
vldrb.u32 q0, [r0, #-128]
vldrb.8 q0, [r0, #128]!
vldrb.8 q0, [r0, #-128]!
vldr... |
stsp/binutils-ia16 | 1,822 | gas/testsuite/gas/arm/thumb2_ldmstm.s | .syntax unified
.thumb
ldmstm:
ldmia sp!, {r0}
ldmia sp!, {r8}
ldmia r1, {r9}
ldmia r2!, {ip}
ldmdb sp!, {r2}
ldmdb sp!, {r8}
ldmdb r6, {r4}
ldmdb r6, {r8}
ldmdb r2!, {r4}
ldmdb r2!, {ip}
stmia sp!, {r3}
stmia sp!, {r9}
stmia r3, {ip}
stmia r4!, {ip}
stmdb sp!, {r3}
stmdb sp!, {r9}
stmdb r7, {r5}
stmd... |
stsp/binutils-ia16 | 1,694 | gas/testsuite/gas/arm/attr-names.s | .eabi_attribute Tag_CPU_raw_name, "random-cpu"
.eabi_attribute Tag_CPU_name, "cpu"
.eabi_attribute Tag_CPU_arch, 1
.eabi_attribute Tag_CPU_arch_profile, 'S'
.eabi_attribute Tag_ARM_ISA_use, 1
.eabi_attribute Tag_THUMB_ISA_use, 1
.eabi_attribute Tag_FP_arch, 1
.eabi_attribute Tag_VFP_arch, 1
.eabi_attribute Tag_WMMX_arc... |
stsp/binutils-ia16 | 1,173 | gas/testsuite/gas/arm/thumb2_ldmstm_bad.s | .syntax unified
.thumb
ldmstm_bad:
@ UNPREDICTABLE Thumb-2 encodings of LDM/LDMIA/LDMFD as specified
@ by section A8.6.53 of the ARMARM.
ldmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE
ldmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE
ldmia r1, {r14, r15} @ Encoding T2, UNPREDICTABLE
ldmia r0!, {r0-r3} @ Encoding ... |
stsp/binutils-ia16 | 1,520 | gas/testsuite/gas/arm/arm-it-auto.s | .syntax unified
.arch armv7
.thumb
main:
@These branches are to see the labels in the generated file
bl .L888
bl .L111
bl .L777
@No IT block here:
bne .L4
@The following groups should be an IT block each.
@it ne
addne.n pc, r0
@it ne
tbbne [r0, r1]
@it eq
tbheq [r1, r0]
@The following group should be ... |
stsp/binutils-ia16 | 1,334 | gas/testsuite/gas/arm/mve-vmlsldav-bad.s | .macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlsldav.s16 r0, sp, q1, q2
vmlsldav.u16 r0, r1, q1, q2
cond vmlsldav
cond vmlsldava
cond vmlsldavx
cond vmlsldavax
vmlsldav.s64 r0, r1, q1, q2
vmlsldav.f32 r0, r1, q1, q2
vmlsldav.s8 r0, r1, q1, q2
... |
stsp/binutils-ia16 | 1,206 | gas/testsuite/gas/arm/archv6t2.s | .text
x:
bfi r0, r0, #0, #1
bfine r0, r0, #0, #1
bfi r9, r0, #0, #1
bfi r0, r9, #0, #1
bfi r0, r0, #0, #18
bfi r0, r0, #17, #1
bfi r0, #0, #0, #1
bfc r0, #0, #1
bfcne r0, #0, #1
bfc r9, #0, #1
bfc r0, #0, #18
bfc r0, #17, #1
sbfx r0, r0, #0, #1
sbfxne r0, r0, #0, #1
ubfx r0, r0, #0, #1
sbfx r9, r0, ... |
stsp/binutils-ia16 | 1,394 | gas/testsuite/gas/arm/mve-vqrshrn-bad.s | .macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q0, #1
.endr
.endm
.syntax unified
.thumb
vqrshrnt.s8 q0, q1, #1
vqrshrnt.s64 q0, q1, #1
vqrshrnt.s16 q0, q1, #0
vqrshrnt.s16 q0, q1, #9
vqrshrnt.s32 q0, q1, #0
vqrshrnt.s32 q0, q1, #17
vqrshrnb.s8 q0, q1, #1
vqrshrnb.s64 q0, q1, #1
vqrshrnb.s16 ... |
stsp/binutils-ia16 | 1,038 | gas/testsuite/gas/arm/archv8m.s | .thumb
.syntax unified
T:
blx r4
blx r9
bx r4
bx r9
tt r0, r1
tt r8, r9
ttt r0, r1
ttt r8, r9
movw r0, #0xF123
@ mov accept all immediate formats, including T3. It's also the suggested
@ assembly to use.
mov r8, #0xF123
@ .w means wide, specifies that the assembler must select a 32-bit encoding for
@ t... |
stsp/binutils-ia16 | 1,055 | gas/testsuite/gas/arm/arch7.s | # ARMV7 instructions
.text
.arch armv7r
label1:
pli [r6, r8]
pli [r9, r7]
pli [r0, r1, lsl #2]
pli [r5]
pli [r5, #4095]
pli [r5, #-4095]
dbg #0
dbg #15
dmb
dmb sy
dsb
dsb sy
dsb un
dsb st
dsb unst
isb
isb sy
.thumb
.thumb_func
label2:
pli [r6, r8]
pli [r9, r7]
pli [r0, r1, lsl #2]
pli [r5]
p... |
stsp/binutils-ia16 | 1,687 | gas/testsuite/gas/arm/armv8-ar+simd.s | .syntax unified
.arch_extension simd
.arm
vmaxnm.f32 d0, d0, d0
vmaxnm.f32 d16, d16, d16
vmaxnm.f32 d15, d15, d15
vmaxnm.f32 d31, d31, d31
vmaxnm.f32 q0, q0, q0
vmaxnm.f32 q8, q8, q8
vmaxnm.f32 q7, q7, q7
vmaxnm.f32 q15, q15, q15
vminnm.f32 d0, d0, d0
vminnm.f32 d16, d16, d16
vminnm.f32 d15, d15, d15
vm... |
stsp/binutils-ia16 | 6,275 | gas/testsuite/gas/arm/sp-pc-validations-bad.s | .syntax unified
@ Loads, ARM ================================================================
.arm
@ LDR (immediate, ARM)
@ LDR (literal)
@No unpredictable or undefined combinations.
@ LDR (register)
ldr r0,[r1,pc, LSL #2] @ Unpredictable
ldr r0,[r1,pc, LSL #2]! @ ditto
ldr r0,[r1],pc, LSL #2 @ ditto
ldr r0,[p... |
stsp/binutils-ia16 | 1,892 | gas/testsuite/gas/arm/neon-omit.s | @ test omitted optional arguments
.text
.arm
.syntax unified
vabd.u8 q1,q3
vhadd.s32 q14, q3
vrhadd.s32 q1,q2
vhsub.s32 q5,q7
vshl.u16 q3,q4
vqshl.u32 q5,q6
vand.64 q7,q8
veor.64 q7,q8
vceq.i16 q5,#0
vceq.i16 q5,q5
vclt.s16 q5,#0
vabs.s16 q5,q6
vneg.s16 d7,d8
vabs.f d7,d8
vneg.f q9,q10
vpmax.s32 d1... |
stsp/binutils-ia16 | 1,295 | gas/testsuite/gas/arm/fpv5-d16.s | .syntax unified
.text
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d8, d8, d8
vselge.f64 d15, d15, d15
vselgt.f64 d10, d10, d10
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s3... |
stsp/binutils-ia16 | 4,202 | gas/testsuite/gas/arm/msr-imm.s | @ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from Immediate
@ Write to application status register
msr APSR_nzcvq,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0... |
stsp/binutils-ia16 | 2,846 | gas/testsuite/gas/arm/mve-vstr-bad-3.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0]
.endr
.endm
.syntax unified
.thumb
vstrb.8 q0, [r0, #128]
vstrb.8 q0, [r0, #-128]
vstrb.16 q0, [r0, #128]
vstrb.16 q0, [r0, #-128]
vstrb.32 q0, [r0, #128]
vstrb.32 q0, [r0, #-128]
vstrb.8 q0, [r0, #128]!
vstrb.8 q0, [r0, #-128]!
vstrb.16 ... |
stsp/binutils-ia16 | 2,081 | gas/testsuite/gas/arm/float.s | .text
.align 0
l:
mvfe f0, f1
mvfeqe f3, f5
mvfeqd f4, #1.0
mvfs f4, f7
mvfsp f0, f1
mvfdm f3, f4
mvfez f7, f7
adfe f0, f1, #2.0
adfeqe f1, f2, #0.5
adfsm f3, f4, f5
sufd f0, f0, #2.0
sufs f1, f2, #10.0
sufneez f3, f4, f5
rsfs f1, f1, #0.0
rsfdp f3, f0, #5.0
rsfled f7, f6, f0
mufd f0, f0, f0
mu... |
stsp/binutils-ia16 | 13,220 | gas/testsuite/gas/arm/thumb32.s | .text
.thumb
.syntax unified
encode_thumb32_immediate:
orr r0, r1, #0x00000000
orr r0, r1, #0x000000a5
orr r0, r1, #0x00a500a5
orr r0, r1, #0xa500a500
orr r0, r1, #0xa5a5a5a5
orr r0, r1, #0xa5 << 31
orr r0, r1, #0xa5 << 30
orr r0, r1, #0xa5 << 29
orr r0, r1, #0xa5 << 28
orr r0, r1, #0xa5 << 27
orr r0, r... |
stsp/binutils-ia16 | 1,830 | gas/testsuite/gas/arm/thumb2_vpool.s | .text
.fpu neon
.thumb
.syntax unified
.thumb_func
thumb2_ldr:
.macro vlxr regtype const
.irp regindex, 0, 14, 28, 31
vldr \regtype\regindex, \const
.endr
.endm
# Thumb-2 support vldr literal pool also.
vlxr s "=0"
vlxr s "=0xff000000"
vlxr s "=-1"
vlxr s "=0x0fff0000"
.pool
vlxr s "=0"
vlxr s "=0x0... |
stsp/binutils-ia16 | 12,605 | gas/testsuite/gas/arm/maverick.s | .text
.align
load_store:
cfldrseq mvf5, [sp, #1020]
cfldrsmi mvf14, [r11, #292]
cfldrsvc mvf2, [r12, #-956]
cfldrslt mvf0, [sl, #-1020]
cfldrscc mvf12, [r1, #-156]
cfldrs mvf13, [r9, #416]!
cfldrscs mvf9, [r0, #-1020]!
cfldrsls mvf4, [r1, #-156]!
cfldrsle mvf7, [r9, #416]!
cfldrsvs mvf11, [r0, #-1020]!
cfl... |
stsp/binutils-ia16 | 11,472 | gas/testsuite/gas/arm/cde-warnings.s | .syntax unified
# cx1{a}
# Immediate out of range.
# Each register out of range.
# r13 => constrained unpredictable
# itblock => constrained unpredictable
# Error given when using coprocessor number not enabled on command line.
# Too many arguments
# Too little arguments
# r15 instead of APSR_nzcv
cx1 p0, r0, #8192
cx... |
stsp/binutils-ia16 | 3,870 | gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s | .macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s32 r0, r1, q2, q3
.endr
.endm
.syntax unified
.thumb
vrmlaldavh.s16 r0, r1, q2, q3
vrmlaldavh.i32 r0, r1, q2, q3
vrmlaldavha.s16 r0, r1, q2, q3
vrmlaldavha.i32 r0, r1, q2, q3
vrmlalvh.s16 r0, r1, q2, q3
vrmlalvh.i32 r0, r1, q2, q3
vrmlalvha.s16 r0, r1, ... |
stsp/binutils-ia16 | 1,311 | gas/testsuite/gas/arm/armv8_3-a-simd.s | .text
A1:
.arm
vcadd.f32 q1,q2,q3,#90
vcadd.f32 q1,q2,q3,#270
vcadd.f16 d21,d22,d23,#90
vcadd.f16 q1,q2,q3,#90
vcadd.f32 d21,d22,d23,#90
vcmla.f32 q1,q2,q3,#0
vcmla.f32 q1,q2,q3,#90
vcmla.f32 q1,q2,q3,#180
vcmla.f32 q1,q2,q3,#270
vcmla.f16 d21,d22,d23,#90
vcmla.f16 q1,q2,q3,#90
vcmla.f32 d21,d22,d23,#9... |
stsp/binutils-ia16 | 1,561 | gas/testsuite/gas/arm/archv8m-cmse-msr.s | T:
## MRS ##
# MSP
mrs r0, MSP
mrs r0, MSP_NS
mrs r0, msp
mrs r0, msp_ns
# PSP
mrs r1, PSP
mrs r1, PSP_NS
mrs r1, psp
mrs r1, psp_ns
# MSPLIM
mrs r2, MSPLIM
mrs r2, MSPLIM_NS
mrs r2, msplim
mrs r2, msplim_ns
# PSPLIM
mrs r3, PSPLIM
mrs r3, PSPLIM_NS
mrs r3, psplim
mrs r3, psplim_ns
... |
stsp/binutils-ia16 | 2,689 | gas/testsuite/gas/arm/mve-vstrldr-3.s | .syntax unified
.thumb
.macro n_vstr_w_vldr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
\op \op1, [\op2], #\imm
\op \op1, [\op2], #-\imm
.endr
.endr
.endm
.irp mnem, vstrb.16, vstrb.32
.irp imm, 0... |
stsp/binutils-ia16 | 1,052 | gas/testsuite/gas/arm/mve-vcvt-bad-4.s | .macro cond
.irp round, a, n, p, m
.irp cond, eq, ne, gt, ge, lt, le
.irp size, .s16.f16, .u16.f16, .s32.f32, .u32.f32
it \cond
vcvt\round\size q0, q1
.endr
.endr
.endr
.endm
.syntax unified
.thumb
cond
vcvta.s64.f64 q0, q1
vcvta.u64.f64 q0, q1
vcvta.f64.s64 q0, q1
vcvta.f64.u64 q0, q1
vcvtn.s64.f64 q0, q1
vcvtn.u64.f... |
stsp/binutils-ia16 | 13,442 | gas/testsuite/gas/arm/neon-cov.s | @ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
@ possible, but without causing instructions to be badly-formed.
.arm
.syntax unified
.text
.macro regs3_1 op opq vtype
\op\vtype q0,q0,q0
\opq\vtype q0,q0,q0
\op\vtype d0,d0,d0
.endm
.macro dregs3_1 op vtype
\op\vtype d0,d0,d0
... |
stsp/binutils-ia16 | 2,802 | gas/testsuite/gas/arm/fpa-dyadic.s | .text
.globl F
F:
adfs f0, f0, f0
adfsp f0, f0, f0
adfsm f0, f0, f0
adfsz f0, f0, f0
adfd f0, f0, f0
adfdp f0, f0, f0
adfdm f0, f0, f0
adfdz f0, f0, f0
adfe f0, f0, f0
adfep f0, f0, f0
adfem f0, f0, f0
adfez f0, f0, f0
sufs f0, f0, f0
sufsp f0, f0, f0
sufsm f0, f0, f0
sufsz f0, f0, f0
sufd f0, f0, f... |
stsp/binutils-ia16 | 3,936 | gas/testsuite/gas/arm/iwmmxt.s | .text
.global iwmmxt
iwmmxt:
tandcb r15
TANDCHLE r15
TANDCWge r15
TBCSTBlt wr0, r1
tbcsth wr1, r2
TBCSTWGT wr2, r3
textrcb r15, #7
textrcheq r15, #2
TEXTRCW r15, #0
TEXTRMUB r14, wr3, #6
textrmsbne r13, wr4, #5
textrmUH r12, wr5, #2
textrmSh r11, wr6, #0
TEXTRMUWcs r10, wr7, #1
textrmswhs r9, ... |
stsp/binutils-ia16 | 4,601 | gas/testsuite/gas/arm/vfp1_t2.s | @ VFP Instructions for D variants (Double precision)
@ Same as vfp1.s, but for Thumb-2
.syntax unified
.thumb
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operation... |
stsp/binutils-ia16 | 1,129 | gas/testsuite/gas/arm/neon-psyn.s | .arm
.syntax unified
fish .qn q2
cow .dn d2[1]
chips .dn d2
banana .dn d3
vmul fish.s16, fish.s16, fish.s16
vmul banana, banana, cow.s32
vmul d3.s32, d3.s32, d2.s32
vadd d2.s32, d3.s32
vmull fish.u32, chips.u16, chips.u16[1]
X .dn D0.S16
Y .dn D1.S16
Z .dn Y[2]
VMLA X, Y, Z
VMLA X, Y, Y[2]
foo .dn d5
ba... |
stsp/binutils-ia16 | 1,190 | gas/testsuite/gas/arm/cde.s | .syntax unified
.include "cde-scalar.s"
# vcx1{a} encoding has the following form
# 111a110i0d10iiiidddd0pppi1iiiiii (vector form)
# 111a110s0d10iiiidddd0pppi0iiiiii (S/D register form)
#
# Variants to test:
# - immediates that set each set of `i` to ones in turn.
# - each register set to something non-zero
# (whe... |
stsp/binutils-ia16 | 1,983 | gas/testsuite/gas/arm/neon-ldst-es.s | @ test element and structure loads and stores.
.text
.arm
.syntax unified
vst2.8 {d2,d3},[r6,:128]
vld3.8 {d1,d2,d3},[r7]!
vst3.16 {d1,d3,d5},[r9:64],r3
vld4.32 {d2,d3,d4,d5},[r10]
vst4.16 {d1,d3,d5,d7},[r10]
vld1.16 {d1[],d2[]},[r10]
vld1.16 {d1[]},[r10,:16]
vld2.32 {d1[],d3[]},[r10:64]
vld3.s8 {d3[],d4[... |
stsp/binutils-ia16 | 1,028 | gas/testsuite/gas/arm/req.s | .text
.global test_dot_req_and_unreq
test_dot_req_and_unreq:
# Check that builtin register alias 'r0' works.
add r0, r0, r0
# Create an alias for r0.
foo .req r0
# Check that it works.
add foo, foo, foo
# Now remove the alias.
.unreq foo
# And make sure that it no longer works.
add foo, foo, foo... |
stsp/binutils-ia16 | 2,306 | gas/testsuite/gas/arm/armv7-a+virt.s | .text
.syntax unified
.arm
foo:
hvc 0x0000
hvc 0xffff
eret
mrs r1, R8_usr
mrs r1, R9_usr
mrs r1, R10_usr
mrs r1, R11_usr
mrs r1, R12_usr
mrs r1, SP_usr
mrs r1, LR_usr
mrs r1, R8_fiq
mrs r1, R9_fiq
mrs r1, R10_fiq
mrs r1, R11_fiq
mrs r1, R12_fiq
mrs r1, SP_fiq
mrs r1, LR_fiq
mrs r1, SPSR_fiq
mrs r1... |
stsp/binutils-ia16 | 1,276 | gas/testsuite/gas/arm/group-reloc-ldrs.s | @ Tests for LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.endm
.macro ldrtest load store sym o... |
stsp/binutils-ia16 | 1,135 | gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s | @ Tests for LDC group relocations that are meant to fail during parsing.
.macro ldctest insn reg
\insn 0, \reg, [r0, #:pc_g0_nc:(sym)]
\insn 0, \reg, [r0, #:pc_g1_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g0_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g1_nc:(sym)]
\insn 0, \reg, [r0, #:foo:(sym)]
.endm
.macro ldctest2 ins... |
stsp/binutils-ia16 | 1,115 | gas/testsuite/gas/arm/mve-vqdmull.s | .syntax unified
.thumb
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, r0, r1, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s16 \op1, \op2, \op3
vqdmullb.s16 \op1, \op2, \op3
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3, r0, r2, r4, r7, r8, r10, r12, r14
vqdmullt.s32 q0, \op2, \op3
vqdmullb.s32 q... |
stsp/binutils-ia16 | 1,975 | gas/testsuite/gas/arm/armv8-ar-bad.s | .syntax unified
.text
// SWP
.arm
swp r0, r1, [r2]
// deprecated MCRs
mcr p15, 0, r0, c7, c5, 4
mcr p15, 0, r1, c7, c10, 4
mcr p15, 0, r2, c7, c10, 5
mrc p14, 6, r1, c0, c0, 0
mrc p14, 6, r0, c1, c0, 0
// deprecated SETEND
setend be
.thumb
setend le
// HLT A32
.arm
hlt 0x10000
hltne 0x1
// HLT... |
stsp/binutils-ia16 | 1,112 | gas/testsuite/gas/arm/group-reloc-ldr.s | @ Tests for LDR group relocations.
.text
.macro ldrtest load store sym offset
\load r0, [r0, #:pc_g0:(\sym \offset)]
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset... |
stsp/binutils-ia16 | 1,699 | gas/testsuite/gas/arm/bfloat16-neon.s | .syntax unified
// Check argument encoding by having different arguments.
// We use 20 and 11 since their binary encoding is 10100 and 01011
// respectively which ensures that we distinguish between the D/M/N bit
// encoding the first or last bit of the argument.
// q registers are encoded as double their actual number... |
stsp/binutils-ia16 | 2,786 | gas/testsuite/gas/arm/bfloat16-bad.s | .syntax unified
// Test warnings about type specifier being incorrect.
vdot.b16 d0, d0, d0
vmmla q0.b16, q0, q0
vdot.bf32 d0, d0, d0[1]
vdot d0.bf32, d0, d0
vdot d0.bf32, d0.bf16, d0.bf16
// Test conditions are not allowed in ARM.
vdotne d0, d0, d0
vdotne d0, d0, d0[1]
vmmlane q0, q0, q0
vfmatne.bf16 q0, d0, d0
vfm... |
stsp/binutils-ia16 | 1,317 | gas/testsuite/gas/arm/ldr-t.s | .syntax unified
.arch armv7-a
.thumb
.global foo
foo:
.align 4
@ldr-immediate
@!wback && (n == t)
ldr r1, [r1, #5]
@wback && !(n == t)
ldr r1, [r2, #5]!
@!(rt == r15) && rn == r15
@ && bits<0..1> (immediate) != 00
ldr r1, [r15, #5]
@rt == r15 && !(rn == r15)
@ && bits<0..1> (immediate) != 00
ldr r15,... |
stsp/binutils-ia16 | 2,618 | gas/testsuite/gas/arm/archv8m_1m-cmse-main.s | .thumb
.syntax unified
T:
clrm {r0, r2} @ Accepts list without APSR
clrm {APSR} @ Accepts APSR alone
clrm {r3, APSR} @ Accepts core register and APSR together
clrmeq {r4} @ Accepts conditional execution
vscclrm {VPR} @ Accepts list with only VPR
vscclrm {s30, VPR} @ Accept single-precision VFP register and VPR toget... |
stsp/binutils-ia16 | 1,166 | gas/testsuite/gas/arm/vfpv3-32drs.s | .arm
.syntax unified
fcpyd d3,d22
fcpyd d22,d3
fcvtds d22,s22
fcvtsd s22,d22
fmdhr d21,r4
fmdlr d27,r5
fmrdh r6,d23
fmrdl r7,d25
fsitod d22,s22
fuitod d21,s21
ftosid s20,d20
ftosizd s20,d20
ftouid s19,d19
ftouizd s19,d19
fldd d19,[r10,#4]
fstd d21,[r10,#4]
fldmiad r10!,{d5,d6}
fldmiad r10!,{d18,d19,d2... |
stsp/binutils-ia16 | 2,975 | gas/testsuite/gas/arm/vfp-neon-syntax-inc.s | @ VFP with Neon-style syntax
.syntax unified
.arch armv7-a
.include "itblock.s"
func:
.macro testvmov cond="" f32=".f32" f64=".f64"
itblock 4 \cond
vmov\cond\f32 s0,s1
vmov\cond\f64 d0,d1
vmov\cond\f32 s0,#0.25
vmov\cond\f64 d0,#1.0
itblock 4 \cond
vmov\cond r0,s1
... |
stsp/binutils-ia16 | 1,917 | gas/testsuite/gas/arm/mve-vstrldr-2.s | .syntax unified
.thumb
.macro all_vstr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
.endr
.endr
.endm
.irp data, .32, .u32, .s32, .f32
.irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 48... |
stsp/binutils-ia16 | 3,847 | gas/testsuite/gas/arm/unpredictable.s | .text
.global upredictable
unpredictable:
.word 0x004f00b1 @ strheq r0, [pc], #-1
.word 0x005fffff @ ldrsheq pc, [pc], #-255
.word 0x007fffff @ ldrsheq pc, [pc, #-255]!
.word 0x00cf00b0 @ strheq r0, [pc], #0
.word 0x00df00b0 @ ldrhe... |
stsp/binutils-ia16 | 1,341 | gas/testsuite/gas/arm/mve-vmullbt.s | .syntax unified
.thumb
.macro helper_q0 op
.irp op2, q1, q2, q4, q7
.irp op3, q1, q2, q4, q7
\op q0, \op2, \op3
.endr
.endr
.endm
.macro helper_q1 op
.irp op2, q0, q2, q4, q7
.irp op3, q0, q2, q4, q7
\op q1, \op2, \op3
.endr
.endr
.endm
.macro helper_q2 op
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
\op q2, \o... |
stsp/binutils-ia16 | 1,917 | gas/testsuite/gas/arm/armv8-2-fp16-scalar.s | .macro f16_sss_arithmetic reg0, reg1, reg2
.irp op, vdiv.f16, vfma.f16, vfms.f16, vfnma.f16, vfnms.f16, vmaxnm.f16, vminnm.f16, vmla.f16, vmls.f16, vmul.f16, vnmla.f16, vnmls.f16, vnmul.f16, vsub.f16
\op s\reg0, s\reg1, s\reg2
.endr
.endm
.macro f16_ss_arithmetic reg0, reg1
.irp op, vabs.f16, vadd.f16, vsqrt.f... |
stsp/binutils-ia16 | 1,265 | gas/testsuite/gas/arm/neon-cond-bad-inc.s | # Check for illegal conditional Neon instructions in ARM mode. The instructions
# which overlap with VFP are the tricky cases, so test those.
.include "itblock.s"
.syntax unified
.arch armv7-a
.fpu neon
.text
func:
itblock 4 eq
vmoveq q0,q1
vmoveq d0,d1
vmoveq.i32 q0,#0
vmoveq.i32 d0,#0
... |
stsp/binutils-ia16 | 1,202 | gas/testsuite/gas/arm/vfma1.s |
.eabi_attribute Tag_Advanced_SIMD_arch, 2
.eabi_attribute Tag_VFP_arch, 6
@VMLA
.inst 0xee000a00 @ VFP vmla.f32 s0,s0,s0
.inst 0xee000b00 @ VFP vmla.f64 d0,d0,d0
.inst 0xf2000d10 @ NEON vmla.f32 d0,d0,d0
.inst 0xf2000d50 @ NEON vmla.f32 q0,q0,q0
@VFMA new
.inst 0xeea00a00 @ VFP vfma.f32 s0,s0,s0
.inst ... |
stsp/binutils-ia16 | 1,461 | gas/testsuite/gas/arm/mve-vcadd.s | .syntax unified
.thumb
.irp data, i8, i16, f16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
.irp op4, #90, #270
vcadd.\data \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
.endr
.macro vcadd_q0 data, op2, op4
.irp op3, q1, q2, q4, q7
vcadd.\data q0, \op2, \op3, \op4
.endr
.endm... |
stsp/binutils-ia16 | 1,872 | gas/testsuite/gas/arm/sp-pc-usage-t.s | .arch armv7-r
.syntax unified
.text
.thumb
.global foo
foo:
.align 4
@ Section A6.1.3 "Use of 0b1101 as a register specifier".
@ R13 as the source or destination register of a mov instruction.
@ only register to register transfers without shifts are supported,
@ with no flag setting
mov sp,r0
mov r0,sp
@ Using the... |
stsp/binutils-ia16 | 2,844 | gas/testsuite/gas/arm/arch7em.s | # Instructions included in v7E-M architecture over v7-M.
.text
.thumb
.syntax unified
pkh:
pkhbt r0, r0, r0
pkhbt r9, r0, r0
pkhbt r0, r9, r0
pkhbt r0, r0, r9
pkhbt r0, r0, r0, lsl #0x14
pkhbt r0, r0, r0, lsl #3
pkhtb r1, r2, r3
pkhtb r1, r2, r3, asr #0x11
qadd:
qadd r1, r2, r3
qadd16 r1, r2, r3
qadd... |
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