repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 2,896 | gas/testsuite/gas/arm/mve-vmov-1.s | .syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vm... |
stsp/binutils-ia16 | 4,907 | gas/testsuite/gas/arm/armv8-2-fp16-simd.s | .macro f16_dq_ifsu reg0 reg1 reg2
.irp op, vabd.f16, vmax.f16, vmin.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_ifsu reg0 reg1 reg2
.irp op, vabdq.f16, vmaxq.f16, vminq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_abs_neg reg0 reg1
.irp op, vabs.f16, ... |
stsp/binutils-ia16 | 9,347 | gas/testsuite/gas/arm/sp-pc-validations-bad-t.s | .syntax unified
@ Enable Thumb mode
.thumb
.macro it_test opcode operands:vararg
itt eq
\opcode\()eq r15, \operands
moveq r0, r0
.endm
.macro it_testw opcode operands:vararg
itt eq
\opcode\()eq.w r15, \operands
moveq r0, r0
.endm
.macro LOAD operands:vararg
it_test ldr, \operands
.endm
.macro LOADw operands:vararg
i... |
stsp/binutils-ia16 | 1,461 | gas/testsuite/gas/arm/mve-vstld.s | .syntax unified
.thumb
.macro all_vstld2 op
.irp part, 0, 1
.irp size, .8, .16, .32
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op\()\part\()\size {q0, q1}, [\op2]
\op\()\part\()\size {q1, q2}, [\op2]
\op\()\part\()\size {q2, q3}, [\op2]
\op\()\part\()\size {q3, q4}, [\op2]
\op\()\part\()\size {q4, q5}, [\op... |
stsp/binutils-ia16 | 5,464 | gas/testsuite/gas/arm/mve-vstld-bad.s | .syntax unified
.thumb
vst20.8 {q0, q2}, [r0]
vst20.8 {q0, q1, q2}, [r0]
vst20.8 {q0}, [r0]
vst20.8 {q0, q1}, [pc]
vst20.8 {q0, q1}, [pc]!
vst20.8 {q0, q1}, [sp]!
vst20.8 {q3, q2}, [r0]
vst20.64 {q0, q1}, [r0]
vst21.8 {q0, q2}, [r0]
vst21.8 {q0, q1, q2}, [r0]
vst21.8 {q0}, [r0]
vst21.8 {q0, q1}, [pc]
vst21.8 {q0, q1}, ... |
stsp/binutils-ia16 | 1,985 | gas/testsuite/gas/arm/cde-mve-or-neon.s | .syntax unified
vcx1 p0, s0, #0
vcx1 p0, s0, #1920
vcx1 p0, s0, #64
vcx1 p0, s0, #63
vcx1 p7, s0, #0
vcx1 p0, s1, #0
vcx1 p0, s30, #0
vcx1 p0, d0, #0
vcx1 p0, d0, #1920
vcx1 p0, d0, #64
vcx1 p0, d0, #63
vcx1 p7, d0, #0
vcx1 p0, d15, #0
vcx1a p0, s0, #0
vcx1a p0, s0, #1920
vcx1a p0, s0, #64
vcx1a p0, s0, #63
vcx1a p7, s... |
stsp/binutils-ia16 | 2,675 | gas/testsuite/gas/arm/fpa-monadic.s | .text
.globl F
F:
mvfs f0, f0
mvfsp f0, f0
mvfsm f0, f0
mvfsz f0, f0
mvfd f0, f0
mvfdp f0, f0
mvfdm f0, f0
mvfdz f0, f0
mvfe f0, f0
mvfep f0, f0
mvfem f0, f0
mvfez f0, f0
mnfs f0, f0
mnfsp f0, f0
mnfsm f0, f0
mnfsz f0, f0
mnfd f0, f0
mnfdp f0, f0
mnfdm f0, f0
mnfdz f0, f0
mnfe f0, f0
mnfep f0, ... |
stsp/binutils-ia16 | 1,138 | gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s | .macro cond, op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s8 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vhadd.i8 q0, q1, q2
vhadd.s64 q0, q1, q2
vhadd.i8 q0, q1, r2
vhadd.s64 q0, q1, r2
vhsub.i16 q0, q1, q2
vhsub.u64 q0, q1, q2
vhsub.i16 q0, q1, r2
vhsub.u64 q0, q1, r2
vrhadd.i32 q0, q1, q2
v... |
stsp/binutils-ia16 | 1,101 | gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s | @ Tests that are supposed to fail during parsing of LDRS group relocations.
.text
@ No NC variants exist for the LDRS relocations.
ldrd r0, [r0, #:pc_g0_nc:(f)]
ldrd r0, [r0, #:pc_g1_nc:(f)]
ldrd r0, [r0, #:sb_g0_nc:(f)]
ldrd r0, [r0, #:sb_g1_nc:(f)]
strd r0, [r0, #:pc_g0_nc:(f)]
strd r0, [r0, #:pc_g1_nc:(f)... |
stsp/binutils-ia16 | 1,606 | gas/testsuite/gas/arm/mve-vcvt-bad.s | .macro cond1
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcvt\().f16.s16 q0, q1, #1
.endr
.endm
.syntax unified
.thumb
vcvt.f16.s16 q0, q1, #0
vcvt.f16.s16 q0, q1, #17
vcvt.f16.u16 q0, q1, #0
vcvt.f16.u16 q0, q1, #17
vcvt.s16.f16 q0, q1, #0
vcvt.s16.f16 q0, q1, #17
vcvt.u16.f16 q0, q1, #0
vcvt.u16.f16 q0, q1, #17
vcvt... |
stsp/binutils-ia16 | 3,574 | gas/testsuite/gas/arm/group-reloc-ldc.s | @ LDC group relocation tests.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store
\load 0, c0, [r0, #:pc_g0:(f + 0x214)]
\load 0, c0, [r0, #:pc_g1:(f + 0x214)]
\load 0, c0, [r0, #:pc_g2:(f + 0x214)]
\load 0, c0, [r0, #:sb_g0:(f + 0x214)]
\load 0, c0, [r0, #:sb_g1:(f + 0x214)]
\load 0,... |
stsp/binutils-ia16 | 1,435 | gas/testsuite/gas/arm/mve-vrmlaldavh.s | .syntax unified
.thumb
.irp op1, r0, r2, r4, r8, r10, r12, r14
.irp op2, r1, r3, r5, r7, r9, r11
.irp op3, q0, q1, q2, q4, q7
.irp op4, q0, q1, q2, q4, q7
.irp data, s32, u32
vrmlaldavh.\data \op1, \op2, \op3, \op4
vrmlaldavha.\data \op1, \op2, \op3, \op4
vrmlalvh.\data \op1, \op2, \op3, \op4
vrmlalvha.\data \op1, \op2... |
stsp/binutils-ia16 | 1,179 | gas/testsuite/gas/arm/cde-mve.s | .syntax unified
vcx1 p0, q0, #0
vcx1 p0, q0, #2048
vcx1 p0, q0, #1920
vcx1 p0, q0, #64
vcx1 p0, q0, #63
vcx1 p7, q0, #0
vcx1 p0, q7, #0
vcx1a p0, q0, #0
vcx1a p0, q0, #2048
vcx1a p0, q0, #1920
vcx1a p0, q0, #64
vcx1a p0, q0, #63
vcx1a p7, q0, #0
vcx1a p0, q7, #0
vptt.i8 eq, q0, q0
vcx1t p0, q0, #0
vcx1at p0, q0, #0
... |
stsp/binutils-ia16 | 6,271 | gas/testsuite/gas/arm/vfp1xD.s | @ VFP Instructions for v1xD variants (Single precision only)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fmstat
fcmpes s0, s0
fcmpezs s0
fcmps s0, s... |
stsp/binutils-ia16 | 4,433 | gas/testsuite/gas/arm/vfp1.s | @ VFP Instructions for D variants (Double precision)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fcmped d0, d0
fcmpezd d0
fcmpd d0, d0
fcmpzd d0
@ ... |
stsp/binutils-ia16 | 1,284 | gas/testsuite/gas/arm/r15-bad.s | .text
.align 0
label:
mul r15, r1, r2
mul r1, r15, r2
mla r15, r2, r3, r4
mla r1, r15, r3, r4
mla r1, r2, r15, r4
mla r1, r2, r3, r15
smlabb r15, r2, r3, r4
smlabb r1, r15, r3, r4
smlabb r1, r2, r15, r4
smlabb r1, r2, r3, r15
smlalbb r15, r2, r3, r4
smlalbb r1, r15, r3, r4
smlalbb r1, r2, r15, r4
smlalbb... |
stsp/binutils-ia16 | 2,681 | gas/testsuite/gas/arm/armv8-ar+fp.s | .syntax unified
.text
.arch_extension fp
.arm
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s3... |
stsp/binutils-ia16 | 2,460 | gas/testsuite/gas/arm/armv8-a+crypto.s | .syntax unified
.arch armv8-a
.arch_extension crypto
.arm
vmull.p64 q0, d0, d0
vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
aese.8 q15, q15
aesd.8 q0, q0
aesd.8 q7, q7
aesd.8 q8, q8
aesd.8 q15, q15
aesmc.8 q0, q0
aesmc.8 q7, q7
aesmc.8 q8, q8
aesmc.8 q15, q15
aesimc.8 q0, q0
ae... |
stsp/binutils-ia16 | 2,093 | gas/testsuite/gas/arm/mve-vldr-bad-1.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vldrb.16 q0, [r0, q1]
vldrb.p16 q0, [r0, q1]
vldrb.f16 q0, [r0, q1]
vldrb.32 q0, [r0, q1]
vldrb.f32 q0, [r0, q1]
vldrb.64 q0, [r0, q1]
vldrb.u64 q0, [r0, q1]
vldrb.s64 q0, [r0, q1]
vldrb.u32 q0, [pc... |
stsp/binutils-ia16 | 2,724 | gas/testsuite/gas/arm/mve-vstrldr-1.s | .syntax unified
.thumb
.macro all_vstr op, size, ext
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
.irp op3, q0, q1, q2, q4, q7
\op\()\size \op1, [\op2, \op3]
\op\()\size \op1, [\op2, \op3, uxtw #\ext]
.endr
.endr
.endr
.endm
.irp size, .8, .16, .32
all_vstr vstrb, \size, 0
.endr
... |
stsp/binutils-ia16 | 1,105 | gas/testsuite/gas/arm/mve-vqdmull-bad.s | .macro cond op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vqdmullt.s8 q0, q1, q2
vqdmullt.u8 q0, q1, q2
vqdmullt.i16 q0, q1, q2
vqdmullt.s64 q0, q1, q2
vqdmullb.s8 q0, q1, q2
vqdmullb.u8 q0, q1, q2
vqdmullb.i16 q0, q1, q2
vqdmullb.s64 q0, q1, q2
v... |
stsp/binutils-ia16 | 1,305 | gas/testsuite/gas/arm/mve-vmlaldav-bad.s | .macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlaldav.s16 r0, sp, q1, q2
cond vmlaldav
cond vmlaldava
cond vmlaldavx
cond vmlaldavax
vmlaldav.s64 r0, r1, q1, q2
vmlaldav.f32 r0, r1, q1, q2
vmlaldav.s8 r0, r1, q1, q2
vmlaldav.s16 r0, q1, q2
vmla... |
stsp/binutils-ia16 | 4,535 | gas/testsuite/gas/arm/archv6.s | .text
.align 0
label:
cps #15
cpsid if
cpsie if
ldrex r2, [r4]
ldrexne r4, [r8]
mcrr2 p0, 12, r7, r5, c3
mrrc2 p0, 12, r7, r5, c3
pkhbt r2, r5, r8
pkhbt r2, r5, r8, LSL #3
pkhbtal r2, r5, r8, LSL #3
pkhbteq r2, r5, r8, LSL #3
pkhtb r2, r5, r8 @ Equivalent to pkhbt r2, r8, r5.
pkhtb r2, r5, r8, ASR #3
pk... |
stsp/binutils-ia16 | 1,332 | gas/testsuite/gas/arm/arm7t.s | .text
.align 0
loadhalfwords:
ldrh r0, [r1]
ldrh r0, [r1]!
ldrh r0, [r1, r2]
ldrh r0, [r1, r2]!
ldrh r0, [r1,#0x0C]
ldrh r0, [r1,#0x0C]!
ldrh r0, [r1,#-0x0C]
ldrh r0, [r1], r2
ldrh r0, =0xFF00
ldrh r0, =0xC0DE
ldrh r0, .L2
storehalfwords:
strh r0, [r1]
strh r0, [r1]!
strh r0, [r1, r2]
strh r0, [r1, r... |
stsp/binutils-ia16 | 2,214 | gas/testsuite/gas/arm/mve-vstr-bad-1.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vstrb.s8 q0, [r0, q1]
vstrb.u8 q0, [r0, q1]
vstrb.s16 q0, [r0, q1]
vstrb.u16 q0, [r0, q1]
vstrb.f16 q0, [r0, q1]
vstrb.u32 q0, [r0, q1]
vstrb.s32 q0, [r0, q1]
vstrb.f32 q0, [r0, q1]
vstrb.64 q0, [r... |
stsp/binutils-ia16 | 4,056 | gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s | @ LDC group relocation tests that are supposed to fail during encoding.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store cst
\load 0, c0, [r0, #:pc_g0:(f + \cst)]
\load 0, c0, [r0, #:pc_g1:(f + \cst)]
\load 0, c0, [r0, #:pc_g2:(f + \cst)]
\load 0, c0, [r0, #:sb_g0:(f + \cst)]
\load ... |
stsp/binutils-ia16 | 1,975 | gas/testsuite/gas/arm/mve-vpt.s | .syntax unified
.thumb
.macro ins_2 cond2
vaddt.i32 q0, q1, q2
vadd\cond2\().i32 q0, q1, q2
.endm
.macro ins_3 cond2, cond3
ins_2 \cond2
vadd\cond3\().i32 q0, q1, q2
.endm
.macro ins_4 cond2, cond3, cond4
ins_3 \cond2, \cond3
vadd\cond4\().i32 q0, q1, q2
.endm
.macro vpt_1 data, cond, op1, op2
vpt\data \cond, \op1, \... |
stsp/binutils-ia16 | 1,602 | gas/testsuite/gas/arm/half-prec-vfpv3.s | .text
vcvtt.f32.f16 s0, s1
vcvtteq.f32.f16 s2, s3
vcvttne.f32.f16 s2, s3
vcvttcs.f32.f16 s2, s3
vcvttcc.f32.f16 s2, s3
vcvttmi.f32.f16 s2, s3
vcvttpl.f32.f16 s2, s3
vcvttvs.f32.f16 s2, s3
vcvttvc.f32.f16 s2, s3
vcvtthi.f32.f16 s2, s3
vcvttls.f32.f16 s2, s3
vcvttge.f32.f16 s2, s3
vcvttlt.f32.f1... |
stsp/binutils-ia16 | 1,067 | gas/testsuite/gas/arm/unwind.s | # Test generation of unwind tables
.text
foo: @ Simple function
.fnstart
.save {r4, lr}
mov r0, #0
.fnend
foo1: @ Typical frame pointer prologue
.fnstart
.movsp ip
@mov ip, sp
.pad #4
.save {fp, ip, lr}
@stmfd sp!, {fp, ip, lr, pc}
.setfp fp, ip, #4
@sub fp, ip, #4
mov r0, #1
.fnend
foo2: @ Custom person... |
stsp/binutils-ia16 | 1,716 | gas/testsuite/gas/arm/armv8-ar.s | .syntax unified
.text
.arch armv8-a
.arm
foo:
sevl
hlt 0x0
hlt 0xf
hlt 0xfff0
stlb r0, [r0]
stlb r1, [r1]
stlb r14, [r14]
stlh r0, [r0]
stlh r1, [r1]
stlh r14, [r14]
stl r0, [r0]
stl r1, [r1]
stl r14, [r14]
stlexb r0, r1, [r14]
stlexb r1, r14, [r0]
stlexb r14, r0, [r1]
stlexh r0, r1, [r14]
stlexh... |
stsp/binutils-ia16 | 1,240 | gas/testsuite/gas/arm/archv6t2-bad.s | @ We do not bother testing simple cases, e.g. immediates where
@ registers belong, trailing junk at end of line.
.text
x:
@ pc not allowed
bfc pc,#0,#1
bfi pc,r0,#0,#1
movw pc,#0
movt pc,#0
@ bitfield range limits
bfc r0,#0,#0
bfc r0,#32,#0
bfc r0,#0,#33
bfc r0,#33,#1
bfc r0,#32,#1
bfc r0,#28,#10
bfi ... |
stsp/binutils-ia16 | 2,935 | gas/testsuite/gas/arm/msr-reg.s | @ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from register
msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
@ Write to CPSR flags
msr CPSR,r9
msr CPSR_s... |
stsp/binutils-ia16 | 2,164 | gas/testsuite/gas/arm/t16-bad.s | @ Things you can't do with 16-bit Thumb instructions, but you can
@ do with the equivalent ARM instruction. Does not include errors
@ caught by fixup processing (e.g. out-of-range immediates).
.text
.code 16
.thumb_func
l:
@ Arithmetic instruction templates
.macro ar2 opc
\opc r8,r0
\opc r0,r8
.endm
.macr... |
stsp/binutils-ia16 | 1,641 | gas/testsuite/gas/sparc-solaris/sol-gcc.s | .file "hi-sol.c"
.stabs "/1h/devo/src/gas/testsuite/gas/",100,0,0,.LLtext0
.stabs "hi-sol.c",100,0,0,.LLtext0
.section ".text"
.LLtext0:
.stabs "gcc2_compiled.", 0x3c, 0, 0, 0
.stabs "int:t1=r1;-2147483648;2147483647;",128,0,0,0
.stabs "char:t2=r2;0;127;",128,0,0,0
.stabs "long int:t3=r1;-2147483648;2147483647;",128,... |
stsp/binutils-ia16 | 2,504 | gas/testsuite/gas/sparc-solaris/sol-cc.s | .section ".text" ! [internal]
.proc 4
.global main
.align 4
.global main
main:
!#PROLOGUE# 0
!#PROLOGUE# 1
save %sp,-96,%sp
sethi %hi(.L18),%o0
sethi %hi(msg),%o1
or %o1,%lo(msg),%o1 ! [internal]
call printf,2
or %o0,%lo(.L18),%o0 ! [internal]
ret
restore %g0,0,%o0
.type main,#function
.size main,(.-ma... |
stsp/binutils-ia16 | 20,650 | gas/testsuite/gas/xstormy16/allinsn.s | .data
foodata: .word 42
.text
footext:
.text
.global movlmemimm
movlmemimm:
mov.b 0,#0
mov.w 255,#65535
mov.w 128,#32768
mov.b 127,#32767
mov.w 1,#1
mov.w 81,#64681
mov.w 247,#42230
mov.b 84,#16647
.text
.global movhmemimm
movhmemimm:
mov.b 0x7f00+0,#0
mov.w 0x7f00+255,#65535
mov.w 0x7f00+128,#32768
m... |
stsp/binutils-ia16 | 21,767 | gas/testsuite/gas/mep/allinsn.s | .data
foodata: .word 42
.text
footext:
.text
.global sb
sb:
sb $7,($fp)
sb $5,($9)
sb $7,($14)
sb $14,($fp)
sb $15,($14)
.text
.global sh
sh:
sh $3,($fp)
sh $12,($1)
sh $13,($2)
sh $2,($8)
sh $12,($10)
.text
.global sw
sw:
sw $11,($0)
sw $3,($7)
sw $13,($14)
sw $8,($9)
sw $gp,($fp)
.text
.globa... |
stsp/binutils-ia16 | 21,991 | gas/testsuite/gas/mep/dj1.s |
mov $0,$0
mov $1,$0
mov $2,$0
mov $3,$0
mov $4,$0
mov $5,$0
mov $6,$0
mov $7,$0
mov $8,$0
mov $9,$0
mov $10,$0
mov $11,$0
mov $12,$0
mov $13,$0
mov $14,$0
mov $15,$0
mov $fp,$0
mov $tp,$0
mov $gp,$0
mov $sp,$0
sb $0,($0)
sh $0,($0)
sw $0,($0)
lb $0,($0)
lh $0,($0)
lw $0,($0)
lbu $0,($0)
... |
stsp/binutils-ia16 | 29,325 | gas/testsuite/gas/ia64/psn.s |
lfetch.count [r2], 1, 64
lfetch.count.d0 [r22], 5, -64
lfetch.count.nt1 [r23], 9, 1024-64
lfetch.count.d1 [r122], 12, -1024
lfetch.count.nt2 [r5], 16, 0x80
lfetch.count.d2 [r15], 20, -0x100
lfetch.count.nta [r125], 24, 512
lfetch.count.d3 [r8], 29, 960
... |
stsp/binutils-ia16 | 1,704 | gas/testsuite/gas/ia64/reloc.s | .global esym
.section .rodata.4, "a", @progbits
.section .rodata.8, "a", @progbits
.text
_start:
adds r1 = esym, r0
mov r2 = esym
movl r3 = esym
.xdata4 .rodata.4, esym
.xdata8 .rodata.8, esym
mov r2 = @gprel(esym)
movl r3 = @gprel(esym)
.xdata4 .rodata.4, @gprel(esym)
.xdata8 .rodata.8, @gprel(esym)... |
stsp/binutils-ia16 | 1,381 | gas/testsuite/gas/ia64/reloc-bad.s | .psr abi64
.global esym
.section .rodata, "a", @progbits
.text
_start:
adds r1 = @gprel(esym), r0
adds r1 = @ltoff(esym), r0
.xdata4 .rodata, @ltoff(esym)
.xdata8 .rodata, @ltoff(esym)
adds r1 = @pltoff(esym), r0
.xdata4 .rodata, @pltoff(esym)
adds r1 = @fptr(esym), r0
mov r2 = @fptr(esym)
adds r... |
stsp/binutils-ia16 | 2,474 | gas/testsuite/gas/ia64/invalid-ar.s | // AR 0 to AR 47 can be accessed only by M unit.
mov.i r1 = ar0
mov.i r1 = ar1
mov.i r1 = ar2
mov.i r1 = ar3
mov.i r1 = ar4
mov.i r1 = ar5
mov.i r1 = ar6
mov.i r1 = ar7
mov.i r1 = ar8
mov.i r1 = ar9
mov.i r1 = ar10
mov.i r1 = ar11
mov.i r1 = ar12
mov.i r1 = ar13
mov.i r1 = ar14
mov.i r1 = ar15
mov.i r1... |
stsp/binutils-ia16 | 4,746 | gas/testsuite/gas/ia64/opc-i.s | .text
.type _start,@function
_start:
pmpyshr2 r4 = r5, r6, 0
pmpyshr2.u r4 = r5, r6, 16
pmpy2.r r4 = r5, r6
pmpy2.l r4 = r5, r6
mix1.r r4 = r5, r6
mix2.r r4 = r5, r6
mix4.r r4 = r5, r6
mix1.l r4 = r5, r6
mix2.l r4 = r5, r6
mix4.l r4 = r5, r6
pack2.uss r4 = r5, r6
pack2.sss r4 = r5, r6
pack4.sss r4 = r... |
stsp/binutils-ia16 | 13,085 | gas/testsuite/gas/ia64/opc-f.s | .text
.type _start,@function
_start:
fma f4 = f5, f6, f7
fma.s0 f4 = f5, f6, f7
fma.s1 f4 = f5, f6, f7
fma.s2 f4 = f5, f6, f7
fma.s3 f4 = f5, f6, f7
fma.s f4 = f5, f6, f7
fma.s.s0 f4 = f5, f6, f7
fma.s.s1 f4 = f5, f6, f7
fma.s.s2 f4 = f5, f6, f7
fma.s.s3 f4 = f5, f6, f7
fma.d f4 = f5, f6, f7
fma.d.s0 f4... |
stsp/binutils-ia16 | 3,699 | gas/testsuite/gas/ia64/unwind-ok.s | .text
.proc personality
personality:
br.ret.sptk rp
.endp personality
.proc full1
full1:
.prologue
.spill 0
.save.g 0x1
nop 0
.save.f 0x1
nop 0
.save.b 0x01
nop 0
.save.g 0x8
nop 0
.save.f 0x8
nop 0
.save.b 0x10
nop 0
.altrp b7
nop 0
.unwabi @svr4, 0
nop 0
.body
.spillreg r4, r2
nop 0
.spillreg.p ... |
stsp/binutils-ia16 | 39,967 | gas/testsuite/gas/ia64/regs.s | .text
.type _start,@function
_start:
// Fixed and stacked integer registers.
{ .mii; mov r1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r6 = r0; nop.... |
stsp/binutils-ia16 | 1,153 | gas/testsuite/gas/ia64/tls.s | .section ".tdata", "awT", @progbits
.align 16
.global x#, y#, z#, a#, b#, c#
.protected a#, b#, c#
.type x#,@object
.size x#,4
x: data4 1
.type y#,@object
.size y#,4
y: data4 2
.type z#,@object
.size z#,4
z: data4 3
.align 8
.type a#,@object
.size a#,8
a: data8 4
.type b#,@object
.size b#,8
b: data8 5
.... |
stsp/binutils-ia16 | 18,157 | gas/testsuite/gas/ia64/opc-b.s | .L0:
{ .bbb; nop.b 0
(p2) br.cond.sptk .L1
br.cond.sptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.clr .L1
br.cond.sptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few .L1
br.cond.sptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few.clr .L1
br.cond.sptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.... |
stsp/binutils-ia16 | 1,741 | gas/testsuite/gas/ia64/unwind-bad.s | .text
.proc full1
full1:
.prologue
.spill 0
.save.g 0
nop 0
.save.g 0x10
nop 0
.save.g -1
nop 0
.save.g 0x3
nop 0
.save.g 0x4
nop 0
.save.g 0x1
nop 0
.save.f 0
nop 0
.save.f 0x100000
nop 0
.save.f -1
nop 0
.save.f 0x3
nop 0
.save.f 0x4
nop 0
.save.f 0x1
nop 0
.save.b 0
nop 0
.save.b 0x20
no... |
stsp/binutils-ia16 | 22,687 | gas/testsuite/gas/ia64/opc-m.s | .text
.type _start,@function
_start:
ld1 r4 = [r5]
ld1 r4 = [r5], r6
ld1 r4 = [r5], -256
ld1.nt1 r4 = [r5]
ld1.nt1 r4 = [r5], r6
ld1.nt1 r4 = [r5], -243
ld1.nta r4 = [r5]
ld1.nta r4 = [r5], r6
ld1.nta r4 = [r5], -230
ld1.s r4 = [r5]
ld1.s r4 = [r5], r6
ld1.s r4 = [r5], -217
ld1.s.nt1 r4 = [r5]
ld1.s.nt1... |
stsp/binutils-ia16 | 1,260 | gas/testsuite/gas/ia64/xdata.s | // Note that most of the section names used here aren't legal as operands
// to either .section or .xdata/.xreal/.xstring (quoted strings aren't in
// general), but since generic code accepts them for .section we also test
// this here for our target specific directives. This could be viewed as a
// shortcut of a pair ... |
stsp/binutils-ia16 | 7,828 | gas/testsuite/gas/ia64/dv-waw-err.s | //
// Detect WAW violations. Cases taken from DV tables.
//
.text
.explicit
// AR[BSP]
mov ar.bsp = r0
mov ar.bsp = r1
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov ar.bspstore = r3
;;
// AR[CCV]
mov ar.ccv = r4
mov ar.ccv = r4
;;
// AR[EC]
br.wtop.sptk L
mov ar.ec = r0
;;
// AR[FPSR].sf0.controls ... |
stsp/binutils-ia16 | 9,948 | gas/testsuite/gas/ia64/opc-a.s | .text
.type _start,@function
_start:
add r101 = r102, r103
(p1) add r104 = r105, r106
add r107 = r108, r109, 1
(p2) add r110 = r111, r112, 1
adds r20 = 0, r10
(p1) adds r21 = 1, r10
adds r22 = -1, r10
adds r23 = -0x2000, r10
(p2) adds r24 = 0x1FFF, r10
addl r30 = 0, r1
addl r31 = 1, r1
(p1) addl r32 = -1, r1... |
stsp/binutils-ia16 | 7,884 | gas/testsuite/gas/ia64/dv-raw-err.s | //
// Detect RAW violations. Cases taken from DV tables.
// This test is by no means complete but tries to hit the things that are
// likely to be missed.
//
.text
.explicit
// AR[BSP]
mov ar.bspstore = r0
mov r1 = ar.bsp
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov r3 = ar.bspstore
;;
// AR[CCV]
mov ar.... |
stsp/binutils-ia16 | 1,152 | gas/testsuite/gas/mmix/relax1.s | # Relaxation border-cases: just-within reach, just-out-of-reach, forward
# and backward. Have a few variable-length thingies in-between so it
# doesn't get too easy.
Main JMP l6
l0 JMP l6
l1 JMP l6
l01 JMP l6
GETA $7,nearfar1 % Within reach.
PUSHJ $191,nearfar2 % Within reach.
l2 JMP nearfar2 % Dummy.
.space 65530... |
stsp/binutils-ia16 | 5,977 | gas/testsuite/gas/mmix/pr25331.s | # 1 "pr25331.c"
! mmixal:= 8H LOC Data_Section
.text ! mmixal:= 9H LOC 8B
.global f
.data ! mmixal:= 8H LOC 9B
.p2align 3
LOC @+(8-@)&7
f IS @
LOC @+8
.global g
.p2align 2
LOC @+(4-@)&3
g IS @
LOC @+4
.global h
.p2align 3
LOC @+(8-@)&7
h IS @
LOC @+8
.section .rodata
.p2align 2
LOC @+(4-@)&3
LC:0 IS @
... |
stsp/binutils-ia16 | 1,784 | gas/testsuite/gas/mmix/regt-op.s | # All-registers, 'T'-type operands; optional third operand is
# register or constant.
Main LDA X,Y,Z
LDT $32,Y,Z
LDBU Y,$32,Z
LDTU $232,$133,Z
LDO X,Y,$73
LDOU $31,Y,$233
LDW X,$38,$212
LDWU $4,$175,$181
LDB X,Y,Z0
LDSF $32,Y,Z0
LDVTS Y,$32,Z0
LDUNC $232,$133,Z0
STHT X,Y,203
LDHT $31,Y,213
CSWAP X,$38,21... |
stsp/binutils-ia16 | 1,122 | gas/testsuite/gas/mmix/pushgo-op.s | # PUSHGO. Like T, but $X can be expressed as a constant.
# Using regt-op as a template caused this to go out of control.
Main PUSHGO X,Y,Z
PUSHGO XC,Y,Z
PUSHGO $32,Y,Z
PUSHGO 32,Y,Z
PUSHGO X,$32,Z
PUSHGO XC,$32,Z
PUSHGO $232,$133,Z
PUSHGO 232,$133,Z
PUSHGO X,Y,$73
PUSHGO XC,Y,$73
PUSHGO $31,Y,$233
PUSHGO 31... |
stsp/binutils-ia16 | 1,027 | gas/testsuite/gas/mmix/relax2.s | # PUSHJ stub border-cases: two with either or both stubs unreachable,
# local symbols, ditto non-local labels, similar with three PUSHJs.
# Note the absence of ":" on labels: because it's a symbol-character,
# it's concatenated with the parameter macro name and parsed as "\x:".
# This happens before gas deals with ":" ... |
stsp/binutils-ia16 | 1,446 | gas/testsuite/gas/mmix/comment-1.s | # Check that "naked" comments are accepted and ignored on all different
# mnemonic types and pseudos. The goal is to use all combinations of
# operands where varying number of operands are allowed. If any
# combinations are missing, for simplicity, add them to another file.
Main TRAP 123 ignore; x y z
TRAP 1,23 all;... |
stsp/binutils-ia16 | 4,890 | gas/testsuite/gas/mmix/list-insns.s | #
# Somewhat complete instruction set and operand type check. No
# relocations or deferred register definitions here.
#
#
#
Main TETRA 3
TRAP 3,4,5
FCMP $12,$23,$241
FLOT $112,ROUND_OFF,$41
FLOT $112,ROUND_NEAR,141
FLOT $191,$242
FLOT $195,42
FUN $122,$203,$4
FEQL $102,$30,$40
FLOTU $102,$14
FLOTU $132,ROUN... |
stsp/binutils-ia16 | 9,316 | gas/testsuite/gas/tic4x/allopcodes.S | ;;;
;;; Test all opcodes and argument permuation
;;; To make our job a lot simpler, we define a couple of
;;; insn classes, that we use to generate the proper
;;; test output.
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
;;;
;;; These definitions are used within this file:
;;; TEST_C3X E... |
stsp/binutils-ia16 | 12,646 | gas/testsuite/gas/tic4x/addressing.s | ;;
;; test all addressing modes and register constraints
;; (types/classes is read from include/opcodes/tic4x.h)
;;
.text
start:
;;
;; Type B - infix condition branch
;;
Type_BI:bu Type_BI ; Unconditional branch (00000)
bc Type... |
stsp/binutils-ia16 | 178,320 | gas/testsuite/gas/tic4x/opcodes.s | ; File is autogenerated from allopcodes.S - do not edit
; Please use ./rebuild.sh to rebuild this file
;;;
;;; Test all opcodes and argument permuation
;;; To make our job a lot simpler, we define a couple of
;;; insn classes, that we use to generate the proper
;;; test output.
;;;
;;; To rebuild this file you... |
stsp/binutils-ia16 | 1,549 | gas/testsuite/gas/tic4x/registers.s | ;; test all register names c3x
.text
;; Test the base names
.ifdef TEST_ALL
start: ldi R0,R0
ldi R0,R1
ldi R0,R2
ldi R0,R3
ldi R0,R4
ldi R0,R5
ldi R0,R6
ldi R0,R7
ldi R0,AR0
ldi ... |
stsp/binutils-ia16 | 1,321 | gas/testsuite/gas/arc/nps400-7.s | .text
;; mrgb
mrgb r0,r0,r1,4,5,3,8,6,2
mrgb.cl r2,r2,r1,4,5,3,8,6,2
;; mov2b
mov2b r1,r1,r2,4,3,2,8,1,6
mov2b.cl r1,r2,4,3,2,8,1,6
;; ext4b
ext4b r3,r3,r12,28,5,10,30,31
ext4b.cl r2,r13,28,5,10,30,31
;; ins4b
ins4b ... |
stsp/binutils-ia16 | 1,827 | gas/testsuite/gas/arc/pseudos.s | # Test pseudo instructions generation.
push r0
pop r1
.L1:
brgt r0, r1, @.L1 ; Encode as BRLT<.d> c,b,s9
brgt r0, -1, @.L1 ; Encode as BRGE<.d> b,u6+1,s9
brgt r0, 0x3F, @.L1 ; Encode as BRLT limm,b,s9
brgt r0, -2, @.L1 ; Encode as BRLT limm,b,s9
brgt -2, r0, @.L1 ; Encode as BRLT c,limm,s9
brgt -2, -1, @.L1 ; E... |
stsp/binutils-ia16 | 1,915 | gas/testsuite/gas/arc/nps400-12.s | .text
; Miscellaneous
; whash
whash r2,[cm:r0],r1
whash r5,[cm:r3],r14
whash 0,[cm:r0],r1
whash 0,[cm:r3],r14
whash r2,[cm:r0],7
whash 0,[cm:r0],7
whash r2,[cm:r0],64
whash 0,[cm:r0],64
... |
stsp/binutils-ia16 | 1,428 | gas/testsuite/gas/arc/nps400-9.s | .text
;; dcmac
dcmac r0,[cm:r0],[cm:r0],r0
dcmac r2,[cm:r4],[cm:r4],r7
dcmac r31,[cm:r31],[cm:r31],r31
dcmac r0,[cm:r0],[cm:0x0],r0
dcmac r2,[cm:r4],[cm:0x1234],r7
dcmac r31,[cm:r31],[cm:0xffff],r31
dcmac r0,[cm:0x0],[cm:r0],r0
dcmac r2,... |
stsp/binutils-ia16 | 12,136 | gas/testsuite/gas/arc/nps400-11.s | .text
; cp16/cp32 xa
cp16.na [cm:r1],[xa:r2]
cp16 [cm:r1],[xa:r2]
cp32.na [cm:r1],[xa:r2]
cp32 [cm:r1],[xa:r2]
cp16.na [cm:r1],[xa:r2,r1]
cp16 [cm:r1],[xa:r2,r1]
cp32.na [cm:r1],[xa:r2,r1]
cp32 [cm:r1],[xa:r2,r1]
... |
stsp/binutils-ia16 | 1,185 | gas/testsuite/gas/arc/textinsn3op.s | # Insn 3op .extInstruction test
.extInstruction myinsn, 0x07, 0x30, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_3OP
myinsn r0,r1,r2
myinsn r26,fp,sp
myinsn ilink1,ilink2,blink
myinsn r0,r1,0
myinsn r0,0,r2
myinsn 0,r1,r2
myinsn r0,r1,-1
myinsn r0,-1,r2
myinsn r0,r1,255
myinsn r0,255,r2
myinsn r0,r1,-256
myinsn r0,-2... |
stsp/binutils-ia16 | 3,845 | gas/testsuite/gas/arc/taux.s | lr r5, [lp_start]
lr r5, [lp_end]
lr r5, [identity]
lr r5, [debug]
lr r5, [pc]
lr r5, [status32]
lr r5, [ic_ivic]
lr r5, [ic_ctrl]
lr r5, [ic_ivil]
lr r5, [ic_ram_address]
lr r5, [ic_tag]
lr r5, [ic_wp]
lr r5, [ic_data]
lr r5, [count0]
lr r5, [control0]
lr r5, [limit0]
lr r5, [dc_ivdc]
lr r5, [dc_ctrl... |
stsp/binutils-ia16 | 2,004 | gas/testsuite/gas/arc/nps400-1.s | .text
movb r0, r0, r1, 4, 5, 6
movb r0, r0, r12, 4, 5, 6
movb r15, r15, r12, 4, 5, 6
movb.cl r0, r1, 4, 5, 6
movb.cl r0, r14, 4, 5, 6
movb.cl r13, r1, 4, 5, 6
movh r0, r0, 1234
movh r3, r3, 0xffff
movh.cl r0, 1234
movh.cl ... |
stsp/binutils-ia16 | 1,338 | gas/testsuite/gas/arc/ext3op.s | # 3 operand insn test
dsp_fp_div r0,r1,r2
dsp_fp_div gp,fp,sp
dsp_fp_div ilink,ilink,blink
dsp_fp_div r0,r1,0
dsp_fp_div r0,0,r2
dsp_fp_div 0,r1,r2
dsp_fp_div r0,r1,-1
dsp_fp_div r0,-1,r2
dsp_fp_div r0,r1,255
dsp_fp_div r0,255,r2
dsp_fp_div r0,r1,-256
dsp_fp_div r0,-256,r2
dsp_fp_div r1,r1,256
dsp_fp_... |
stsp/binutils-ia16 | 2,044 | gas/testsuite/gas/arc/nps400-8.s | .text
;; bdalc / sbdalc
bdalc r0,[cm:r0],r0,r0
bdalc r1,[cm:r2],r2,r3
bdalc r0,[cm:r0],r0,0,1
bdalc r2,[cm:r3],r3,1,1
bdalc r3,[cm:r4],r4,1,8
sbdalc r0, r0, 0
sbdalc r3, r4, 1
;; bdfre / sbdfre
bdfre 0,[cm:r0],r0,r0
bdfre ... |
stsp/binutils-ia16 | 6,388 | gas/testsuite/gas/arc/nps400-6.s | .text
.macro addb_like_test mnem
\mnem r0,r0,r1,0,8,2
\mnem\().f r0,r0,r1,16,8,2
\mnem\().f.sx r0,r0,r1,8,24,6
.endm
.macro andb_like_test mnem, size
\mnem r0,r0,r1,0,8,\size
\mnem\().f r0,r0,r1,16,8,\size
.endm
.macro notb_... |
stsp/binutils-ia16 | 1,633 | gas/testsuite/gas/arc/dsp.s | #Test if disassembler correctly prints DSP instructions.
vmac2hnfr r0,r2,r4
abssh r0,r2
aslacc r0
aslsacc r0
asrsr r0,r2,r4
cbflyhf0r r0,r2,r4
cbflyhf1r r0,r2
cmacchfr r0,r2,r4
cmacchnfr r0,r2,r4
cmachfr r0,r2,r4
cmachnfr r0,r2,r4
cmpychfr r0,r2,r4
cmpychnfr r0,r2,r4
cmpyhfmr r0,r2,r4
cmpyhfr r0,r2... |
stsp/binutils-ia16 | 1,600 | gas/testsuite/gas/loongarch/4opt_op.s | fmadd.s $f0,$f1,$f2,$f3
fmadd.d $f0,$f1,$f2,$f3
fmsub.s $f0,$f1,$f2,$f3
fmsub.d $f0,$f1,$f2,$f3
fnmadd.s $f0,$f1,$f2,$f3
fnmadd.d $f0,$f1,$f2,$f3
fnmsub.s $f0,$f1,$f2,$f3
fnmsub.d $f0,$f1,$f2,$f3
fcmp.caf.s $fcc0,$f1,$f2
fcmp.saf.s $fcc0,$f1,$f2
fcmp.clt.s $fcc0,$f1,$f2
fcmp.slt.s $fcc0,$f1,$f2
fcmp.sgt.s ... |
stsp/binutils-ia16 | 1,496 | gas/testsuite/gas/loongarch/float_op.s | fadd.s $f0,$f1,$f2
fadd.d $f0,$f1,$f2
fsub.s $f0,$f1,$f2
fsub.d $f0,$f1,$f2
fmul.s $f0,$f1,$f2
fmul.d $f0,$f1,$f2
fdiv.s $f0,$f1,$f2
fdiv.d $f0,$f1,$f2
fmax.s $f0,$f1,$f2
fmax.d $f0,$f1,$f2
fmin.s $f0,$f1,$f2
fmin.d $f0,$f1,$f2
fmaxa.s $f0,$f1,$f2
fmaxa.d $f0,$f1,$f2
fmina.s $f0,$f1,$f2
fmina.d $f0,$f1,... |
stsp/binutils-ia16 | 3,572 | gas/testsuite/gas/loongarch/load_store_op.s | ll.w $r4,$r5,0
ll.w $r4,$r5,0x3ffc
sc.w $r4,$r5,0
sc.w $r4,$r5,0x3ffc
ll.d $r4,$r5,0
ll.d $r4,$r5,0x3ffc
sc.d $r4,$r5,0
sc.d $r4,$r5,0x3ffc
ldptr.w $r4,$r5,0
ldptr.w $r4,$r5,0x3ffc
stptr.w $r4,$r5,0
stptr.w $r4,$r5,0x3ffc
ldptr.d $r4,$r5,0
ldptr.d $r4,$r5,0x3ffc
stptr.d $r4,$r5,0
stptr.d $r4,$r5,0x3ffc
... |
stsp/binutils-ia16 | 2,451 | gas/testsuite/gas/loongarch/fix_op.s | clo.w $r4,$r5
clz.w $r4,$r5
cto.w $r4,$r5
ctz.w $r4,$r5
clo.d $r4,$r5
clz.d $r4,$r5
cto.d $r4,$r5
ctz.d $r4,$r5
revb.2h $r4,$r5
revb.4h $r4,$r5
revb.2w $r4,$r5
revb.d $r4,$r5
revh.2w $r4,$r5
revh.d $r4,$r5
bitrev.4b $r4,$r5
bitrev.8b $r4,$r5
bitrev.w $r4,$r5
bitrev.d $r4,$r5
ext.w.h $r4,$r5
ext.w.b ... |
stsp/binutils-ia16 | 2,865 | gas/testsuite/gas/tic6x/insns-c674x-reloc.s | # Test C674x instructions generating relocations.
.data
w1:
.word 1
w2:
.word 2
.text
.nocmp
.globl ext1
.globl ext2
.globl ext3
.globl a1
.globl b1
.globl f
f:
addab .D1X b14,ext1,a5
addab .D2 b15,(ext2+7),b7
addab .D1X b14,(a1),a20
addab .D2 b14,(b1),b30
addab .D1X b14,w2-w1,a15
addab .D2 b14,w4-w3,b16
addah... |
stsp/binutils-ia16 | 2,636 | gas/testsuite/gas/tic6x/insns-c674x-pcrel.s | # Test C674x instructions generating PC-relative relocations.
.text
.nocmp
.globl ext1
.globl ext2
.globl ext3
.globl a1
.globl b1
.globl irp
.globl nrp
f:
nop
nop
nop
nop
nop
nop
nop
addkpc .S2 f,b1,3
[a2] addkpc .S2 f+4,b3,7
addkpc .S2 g,b4,0
addkpc .S2 ext1+8,b5,4
g:
nop
nop
nop
nop
nop
f2:
nop
nop... |
stsp/binutils-ia16 | 1,536 | gas/testsuite/gas/tic6x/insns16-lsd-unit.s | ; Test C64x+ L, S or D-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
lsdmvto:
.short 0x0006
.short 0x000f
.short 0x0016
.short 0x0017
.short 0x000e
.short 0x0007
.short 0x0006
.short 0x100f
... |
stsp/binutils-ia16 | 1,151 | gas/testsuite/gas/tic6x/insns-c674x-sploop.s | # Test C674x SPLOOP instructions. The present tests are placeholders
# to verify encoding that may not be valid when the full set of checks
# for invalid input are implemented and may need changing to valid
# code at that point.
.text
.nocmp
.globl f
f:
spmask
spmask l1
spmask L2
spmask s1
spmask S2
spmask D1
s... |
stsp/binutils-ia16 | 1,990 | gas/testsuite/gas/tic6x/unwind-bad-2.s | .cfi_sections .c6xabi.exidx
.cfi_startproc
# stack pointer offset too large for personality routine
.cfi_def_cfa_offset 0x3f8
.cfi_endproc
.personalityindex 3
.endp
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
# stack fra... |
stsp/binutils-ia16 | 1,745 | gas/testsuite/gas/tic6x/insns16-d-unit.s | ; Test C64x+ D-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
dstk: ; op = 0 | STW (.unit) src, *B15[ucst5]
; op = 1 | LDW (.unit)*B15[ucst5], dst
.short 0x8c05
.short 0x9c05
.short 0x8c05
.short 0x9c05
.short 0xcc35
.short 0xfc05
.short 0xdcf5
.short 0x8c0d
.short 0x9c0d
.shor... |
stsp/binutils-ia16 | 1,040 | gas/testsuite/gas/tic6x/predicate-bad-2.s | # Test predicates allowed or disallowed depending on the architecture.
.text
.globl f
f:
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c64x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
... |
stsp/binutils-ia16 | 3,716 | gas/testsuite/gas/tic6x/unwind-2.s | .cfi_sections .c6xabi.exidx
# standard layout
.p2align 8
f0:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# standard layout (pr0)
.p2align 8
f1:
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_of... |
stsp/binutils-ia16 | 3,750 | gas/testsuite/gas/tic6x/insns16-s-unit.s | ; Test C64x+ S-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
s3_nosat_op_0:
.short 0x000a
.short 0x201b
.short 0x512a
.short 0x713b
.short 0x824a
.short 0xa25b
.short 0xd36a
.short 0xf37b
.short 0xe28a
s3_nosat_op_1:
.short 0x0a9b
.short 0x39aa
.short 0x59bb
.short 0x68ca
.short ... |
stsp/binutils-ia16 | 38,810 | gas/testsuite/gas/tic6x/insns-c674x.s | # Test C674x instructions.
.text
.nocmp
.globl f
f:
abs .L1 a5,a7
abs .L1X b11,a14
[a1] abs .L2 b16,b19
[!b2] abs .L2X a7,b31
[b1] abs .L1 a11:a10,a19:a18
abs .L2 b13:b12,b1:b0
abs2 .L1 a9,a10
[a2] abs2 .L1X b23,a5
abs2 .L2 b3,b14
abs2 .L2X a28,b25
.word 0x0c180b20
absdp .S1 a7:a6,a25:a24
[a0] absdp .S2 b3... |
stsp/binutils-ia16 | 2,380 | gas/testsuite/gas/tic6x/insns16-dinc.s | ; Test C64x+ dinc compact instruction format
.text
dinc:
nop
.align 16
nop
.align 16
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0c05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe00000
... |
stsp/binutils-ia16 | 5,445 | gas/testsuite/gas/tic6x/reloc-bad-2.s | # Test expressions not representable by relocations.
.globl a
.globl b
.data
d:
.word $DSBT_INDEX(__c6xabi_DSBT_BASE)
.word $got(b)
.word $dpr_got(a)
.word $dpr_byte(b)
.word $dpr_hword(a)
.word $dpr_word(b)
.word $pcr_offset(b,f)
.text
.nocmp
.globl f
f:
addab .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
addab... |
stsp/binutils-ia16 | 3,732 | gas/testsuite/gas/tic6x/reloc-bad-6.s | # Test relocation overflow and insufficiently divisible values for
# PC-relative operands.
.text
.nocmp
f7_0:
nop
nop
nop
nop
nop
nop
nop
f7_28:
nop
f7_32:
.space 256
f7_288:
addkpc .S2 f7_32,b1,0
addkpc .S2 f7_28,b1,0
addkpc .S2 f7_32,b1,0
addkpc .S2 f7_0,b1,0
addkpc .S2 f7_544,b1,0
addkpc .S2 f7_540,b1... |
stsp/binutils-ia16 | 1,317 | gas/testsuite/gas/tic6x/insns16-s-unit-pcrel.s | ; Test C64x+ S-unit pcrel compact instruction formats
.text
nop
.align 16
nop
.align 16
sbs7:
.short 0x000a
.short 0x004a
.short 0x214b
.short 0x428a
.short 0x63cb
.short 0x840a
.short 0xa54b
.short 0x868a
.short 0x77cb
.short 0x580a
.short 0x394b
.short 0x1a8a
.short 0x3bcb
.short 0x5c0a
.word 0xe... |
stsp/binutils-ia16 | 2,751 | gas/testsuite/gas/tic6x/insns16-l-unit.s | ; Test C64x+ L-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
l3_nosat_l:
.short 0x0010
.short 0x2120
.short 0x4230
.short 0x6340
.short 0x8050
.short 0xa160
.short 0xc270
.short 0xeb80
.short 0x0890
.short 0x29a0
.short 0x4ab0
.short 0x6bc0
.short 0x88d0
.short 0xa9e0
.word 0xe... |
stsp/binutils-ia16 | 3,716 | gas/testsuite/gas/tic6x/unwind-1.s | .cfi_sections .c6xabi.exidx
# standard layout
.p2align 8
f0:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# standard layout (pr0)
.p2align 8
f1:
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_of... |
stsp/binutils-ia16 | 28,021 | gas/testsuite/gas/tic6x/insns-bad-1.s | # Test bad instructions and operands.
.text
.globl f
f:
nonesuch foo bar
nop nonconst
nop 2,
nop 2,3
nop 2 , 4
nop 2 4
nop 0
nop -1
nop 10000
nop 10
nop 15
abs .L1 a1,
abs .L1 a1
abs .S1 a1,a2
abs .L1 foo,bar
abs .L1X foo,bar
abs .L1 A0,A00
abs .L1 A32,A1
abs .L1 B1,A1
abs .L1 A1,B1
abs .L1X A1,A1
... |
stsp/binutils-ia16 | 2,174 | gas/testsuite/gas/tic6x/reloc-bad-3.s | # Test relocation overflow and insufficiently divisible values. Note
# that divisibility checks for constant values are only applicable to
# load and store offsets, not ADDA, because constant values are
# encoded literally for ADDA, and divisbility checks for offsets from
# symbols are only applicable with REL relocat... |
stsp/binutils-ia16 | 2,453 | gas/testsuite/gas/tic6x/insns16-doff4.s | ; Test C64x+ 16 bits instructions - doff4 format
.text
.nocmp
doff4:
nop
.align 16
nop
.align 16
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
... |
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