repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
stsp/binutils-ia16 | 4,042 | gas/testsuite/gas/ft32/insn.s | # Used for all instructions that have a 3-address form
.macro TERNARY insn
# reg-reg
\insn $r31, $r0, $r0
\insn $r0, $r31, $r0
\insn $r0, $r0, $r31
\insn $r1, $r2, $r4
\insn $r8, $r16, $r0
# immediate
\insn $r31, $r0, -512
\in... |
stsp/binutils-ia16 | 1,935 | gas/testsuite/gas/ppc/xcoff-visibility-1.s | # Tests every possible visibility using XCOFF format.
# Ensure that the visibility field is left empty if no
# visibility is provided.
# Ensure that only the last visibility is taken into
# account when several are provided.
# Csect visibility
.globl globl_novisibility[RW]
.csect globl_novisibility[RW]
.globl gl... |
stsp/binutils-ia16 | 3,545 | gas/testsuite/gas/ppc/altivec.s | # PowerPC AltiVec tests
#as: -m601 -maltivec
.text
start:
dss 3
dssall
dst 5,4,1
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2
lvebx 30,22,24
lvebx 21,0,24
lvehx 10,16,2
lvehx 20,0,23
lvewx 17,4,18
lvewx 23,0,8
lvsl 6,0,25
lvsl 2,0,6
lvsr 22,16,12
lvsr 0,0,29
lvxl 15,5,13
... |
stsp/binutils-ia16 | 1,222 | gas/testsuite/gas/ppc/test1xcoff32.s |
.csect [RW]
dsym0: .long 0xdeadbeef
dsym1:
.toc
.L_tsym0:
.tc ignored0[TC],dsym0
.L_tsym1:
.tc ignored1[TC],dsym1
.L_tsym2:
.tc ignored2[TC],usym0
.L_tsym3:
.tc ignored3[TC],usym1
.L_tsym4:
.tc ignored4[TC],esym0
.L_tsym5:
.tc ignored5[TC],esym1
.L_tsym6:
.tc ignored6[TC],.text
.csect .c... |
stsp/binutils-ia16 | 27,621 | gas/testsuite/gas/ppc/spe2.s | # PA SPE2 instructions
# Testcase for CMPE200GCC-5, CMPE200GCC-62
.section ".text"
.equ rA,1
.equ rB,2
.equ rD,0
.equ rS,0
.equ UIMM, 31
.equ UIMM_LT8, 7
.equ UIMM_LT16, 15
.equ UIMM_1, 1
.equ UIMM_2, 2
.equ UIMM_4, 4
.equ UIMM_8, 8
.equ SIMM, -16
.equ crD, 0
.equ nnn, 7
.equ bbb, 7
.equ dd,... |
stsp/binutils-ia16 | 1,477 | gas/testsuite/gas/ppc/altivec3.s | .text
start:
vmul10cuq 11,30
vcmpneb 30,1,23
vpermr 30,19,30,29
vmul10ecuq 20,20,17
vcmpneh 27,19,31
vrlwmi 6,9,23
vcmpnew 22,26,1
vrldmi 24,30,25
vcmpnezb 19,29,22
vcmpnezh 8,23,19
vrlwnm 27,24,11
vcmpnezw 21,13,10
vrldnm 5,20,29
vmul10uq ... |
stsp/binutils-ia16 | 3,331 | gas/testsuite/gas/ppc/vsx.s | .text
start:
lxsdx 40,10,20
lxvd2x 40,10,20
lxvdsx 40,10,20
lxvw4x 40,10,20
stxsdx 40,10,20
stxvd2x 40,10,20
stxvw4x 40,10,20
xsabsdp 40,60
xsadddp 40,50,60
xscmpodp 1,50,60
xscmpudp 1,50,60
xscpsgndp 40,50,60
xscvdpsp 40,60
xscvdpsxds 40,60
xscvdpsxws 40,60
xscv... |
stsp/binutils-ia16 | 2,623 | gas/testsuite/gas/ppc/vsx3.s | .text
vsx3:
lxvx 34,6,25
lxvx 20,0,10
lxvl 20,24,10
lxvl 54,0,29
lxvll 24,20,19
lxvll 34,0,14
mfvsrld 2,22
lxvwsx 58,26,25
lxvwsx 55,0,29
stxvx 14,21,4
stxvx 30,0,22
stxvl 0,26,4
stxvl 37,0,22
mtvsrws 2... |
stsp/binutils-ia16 | 1,174 | gas/testsuite/gas/ppc/vsx2.s | .text
vsx2:
lxsiwzx 62,14,26
lxsiwzx 40,0,25
lxsiwax 25,0,26
lxsiwax 3,0,3
mfvsrd 12,30
mffprd 12,30
mfvsrd 12,62
mfvrd 12,30
mfvsrwz 20,12
mffprwz 20,12
mfvsrwz 21,44
mfvrwz 21,12
stxsiwx 14,9,14
stxsiwx 21,0,8
mtvsrd 11,... |
stsp/binutils-ia16 | 1,281 | gas/testsuite/gas/ppc/e6500.s | # Power E6500 tests
.text
start:
vabsdub 0, 1, 2
vabsduh 0, 1, 2
vabsduw 0, 1, 2
mvidsplt 0, 1, 2
mviwsplt 0, 1, 2
lvexbx 0, 0, 2
lvexbx 0, 1, 2
lvexhx 0, 0, 2
lvexhx 0, 1, 2
lvexwx 0, 0, 2
lvexwx 0, 1, 2
stvexbx 0, 0, 2
stvexbx 0, 1, 2
stvexhx 0, 0, 2
stvexhx 0, 1, 2
stvexwx 0, 0, 2
stvexwx 0, 1, 2
... |
stsp/binutils-ia16 | 8,090 | gas/testsuite/gas/ppc/power9.s | .text
power9:
cnttzd 3,13
cnttzd. 4,14
cnttzw 5,15
cnttzw. 6,16
modsd 10,20,21
modsw 11,21,22
modud 12,22,23
moduw 13,23,24
bcdcfn. 3,4,0
bcdcfn. 3,4,1
bcdcfsq. 4,5,0
bcdcfsq. 4,5,1
bcdcfz. 5,6,0
bcdcfz. 5,6,1
bcdcpsgn. 6,7,8
bcdctn. ... |
stsp/binutils-ia16 | 4,175 | gas/testsuite/gas/ppc/lsp-checks.s | # Test PA LSP operands checks
.section ".text"
.equ rA,1
.equ rB,2
.equ rD,0 ;# ok
.equ rD_odd, 1 ;# GPR odd is illegal
.equ rS,0 ;# ok
.equ rS_odd, 1 ;# GPR odd is illegal
.equ UIMM_GT15, 16 ;# UIMM values >15 are illegal
.equ UIMM_2, 2 ;# ok
.equ UIMM_2_ILL, 3 ;# 3 is n... |
stsp/binutils-ia16 | 2,599 | gas/testsuite/gas/ppc/prefix-pcrel.s | .text
prefix:
# The following should all disassemble to: paddi rX,rY,disp
pla 10,0(9)
paddi 10,9,0
paddi 10,9,0,0
pla 11,~(1<<15)(9)
paddi 11,9,~(1<<15)
paddi 11,9,~(1<<15),0
pla 12,8589934591(9)
psubi 12,9,-8589934591
psubi 12,9,-8589934591,0
paddi 12,9,8589934591
paddi 12,9,8589934591,0
pla 13,-85899345... |
stsp/binutils-ia16 | 6,110 | gas/testsuite/gas/ppc/power8.s | .text
power8:
tabort. 5
tabortwc. 7,8,16
tabortdc. 20,11,10
tabortwci. 17,10,-13
tabortdci. 29,3,-5
tbegin. 0
tcheck 7
tend. 0
tend.
tend. 1
tendall.
treclaim. 24
trechkpt.
tsr. 0
tsuspend.
tsr. 1
tresume.
ori 2,2,0
.p... |
stsp/binutils-ia16 | 1,327 | gas/testsuite/gas/ppc/power4.s | .data
.p2align 4
dsym0: .llong 0xdeadbeef
.llong 0xc0ffee
dsym1:
.section ".toc"
.p2align 4
.L_tsym0:
.tc ignored0[TC],dsym0
.tc ignored1[TC],dsym1
.L_tsym1:
.tc ignored2[TC],usym0
.tc ignored3[TC],usym1
.text
.p2align 4
lq 4,dsym0@l(3)
lq 4,dsym1@l(3)
lq 4,usym0@l(3)
lq 4,usym1@l(3)
lq 4,esym0@l(3)
... |
stsp/binutils-ia16 | 2,429 | gas/testsuite/gas/ppc/common.s | .text
start:
and. 3,4,5
and 3,4,5
andc 13,14,15
andc. 16,17,18
ba label_abs
bc 0,1,foo
bca 4,5,foo_abs
bcl 2,3,foo
bcla 10,7,foo_abs
bctr
bctrl
bdza foo_abs
bdz foo
bdzla foo_abs
bdzl foo
beq 0,foo
beqa 2,foo_abs
beql 1,foo
beqla 3,foo_abs
bge 0,foo
bgea 4,foo_abs
bgel 2,foo
bgela 6,foo_abs
bgt... |
stsp/binutils-ia16 | 7,404 | gas/testsuite/gas/ppc/spe.s | # PA SPE instructions
.section ".text"
.equ rA,1
.equ rB,2
.equ rD,0
.equ rS,0
.equ rT,0
.equ UIMM, 31
.equ UIMM_2, 2
.equ UIMM_4, 4
.equ UIMM_8, 8
.equ SIMM, -16
.equ crD, 0
.equ crS, 0
evaddw rS, rA, rB
evaddiw rS, rB, UIMM
evsubfw rS, rA, rB
evsubw rS, rB, rA
evsu... |
stsp/binutils-ia16 | 6,857 | gas/testsuite/gas/ppc/476.s | .text
ppc476:
add 3,4,5
add. 3,4,5
addc 3,4,5
addc. 3,4,5
addco 3,4,5
addco. 3,4,5
adde 3,4,5
adde. 3,4,5
addeo 3,4,5
addeo. 3,4,5
addi 3,4,-128
addic 3,4,-128
addic. 3,4,-128
addis 3,4,-128
addme 3,4
addme. 3,4
addmeo 3,4
addmeo. 3,4
addo 3,4,5
addo. 3,4,5
addze 3,4
addze. 3,4
addzeo 3,4
addze... |
stsp/binutils-ia16 | 1,087 | gas/testsuite/gas/ppc/vle-mult-ld-st-insns.s | # VLE Instructions for Improving Interrupt Handler Efficiency (e200z760RM.pdf)
# Original Engineering Bullet (EB696.pdf) contains two writings of load instructions
# and has no ones for MCSRRs.
# e_lmvgprw, e_stmvgprw - load/store multiple volatile GPRs (r0, r3:r12)
# e_lmvsprw, e_stmvsprw - load/store multiple volati... |
stsp/binutils-ia16 | 1,383 | gas/testsuite/gas/ppc/broadway.s | # PowerPC Broadway instruction tests
.text
start:
mfiabr 0
mtiabr 1
mfdabr 2
mtdabr 3
mfgqr 4, 0
mfgqr 5, 1
mfgqr 6, 2
mfgqr 7, 3
mfgqr 8, 4
mfgqr 9, 5
mfgqr 10, 6
mfgqr 11, 7
mtgqr 0, 4
mtgqr 1, 5
mtgqr 2, 6
mtgqr 3, 7
mtgqr 4, 8
mtgqr 5, 9
mtgqr 6, 10
mtgqr 7, 11
mfwpar 12
mtwpar 13
mfdmal 14
... |
stsp/binutils-ia16 | 1,226 | gas/testsuite/gas/ppc/test1elf64.s |
.section ".data"
dsym0: .llong 0xdeadbeef
dsym1:
.section ".toc"
.L_tsym0:
.tc ignored0[TC],dsym0
.L_tsym1:
.tc ignored1[TC],dsym1
.L_tsym2:
.tc ignored2[TC],usym0
.L_tsym3:
.tc ignored3[TC],usym1
.L_tsym4:
.tc ignored4[TC],esym0
.L_tsym5:
.tc ignored5[TC],esym1
.section ".text"
ld 3,d... |
stsp/binutils-ia16 | 8,176 | gas/testsuite/gas/ppc/a2.s | .text
start:
add. 4,5,6
add 4,5,6
addc. 4,5,6
addc 4,5,6
addco. 4,5,6
addco 4,5,6
adde. 4,5,6
adde 4,5,6
addeo. 4,5,6
addeo 4,5,6
addi 4,5,13
addi 4,5,-13
addic. 4,5,13
addic. 4,5,-13
addic 4,5,13
addic 4,5,-13
addis 4,5,23
addis 4,5,-23
addme. 4,5
addme 4,5
addmeo. 4,5
addmeo 4,5
addo. 4,5,6
a... |
stsp/binutils-ia16 | 1,427 | gas/testsuite/gas/ppc/outerprod.s | .text
_start:
xxmfacc 5
xxmtacc 6
xxsetaccz 7
xvi4ger8 0,63,62
xvi4ger8pp 1,61,60
pmxvi4ger8 2,59,58,15,14,255
pmxvi4ger8pp 3,57,56,7,8,128
xvi8ger4 4,55,54
xvi8ger4pp 5,53,52
pmxvi8ger4 6,51,50,13,12,11
pmxvi8ger4pp 7,49,48,10,9,8
xvi16ger2s 0,47,46
xvi16ger2spp 1,45,44
pmxvi16ger2s 2,43,42,7,6,3
pmxvi... |
stsp/binutils-ia16 | 2,276 | gas/testsuite/gas/ppc/vle-reloc.s | .text
se_b sub1
se_bl sub1
se_bc 0,1,sub2
se_bc 1,2,sub2
e_b sub3
e_bl sub4
e_bc 0,5,sub5
e_bcl 1,10,sub5
e_or2i 1, low@l
e_or2i 2, high@h
e_or2i 3, high_adjust@ha
e_or2i 4, low_sdarel@sdarel@l
e_or2i 5, high_sdarel@sdarel@h
e_or2i 2, high_adjust_sdarel@sdarel@ha
e_and2i. 1, low@l
e_and2i. 2, high@h... |
stsp/binutils-ia16 | 4,070 | gas/testsuite/gas/ppc/titan.s | # AppliedMicro Titan tests
.text
start:
blr
tweqi 1, 0
macchw 2, 1, 0
macchw. 2, 1, 0
macchwo 2, 1, 0
macchwo. 2, 1, 0
macchws 2, 1, 0
macchws. 2, 1, 0
macchwso 2, 1, 0
macchwso. 2, 1, 0
macchwsu 2, 1, 0
macchwsu. 2, 1, 0
macchwsuo 2, 1, 0
macchwsuo. 2, 1, 0
macchwu 2, 1, 0
macchwu. 2, 1, 0
mac... |
stsp/binutils-ia16 | 21,400 | gas/testsuite/gas/ppc/lsp.s | # PA LSP instructions
# CMPE200GCC-62
.section ".text"
.equ rA,1
.equ rB,2
.equ rD,0
.equ rS,0
.equ UIMM, 15 ;#UIMM values >15 are illegal
.equ UIMM_2, 4
.equ UIMM_4, 8
.equ UIMM_8, 16
.equ SIMM, -16
.equ crD, 0
.equ offset, 1
zvaddih rD, rA, UIMM
zvsubifh rD, rA, UIMM
zvaddh ... |
stsp/binutils-ia16 | 3,479 | gas/testsuite/gas/ppc/spe2-checks.s | # PA SPE2 instructions
.section ".text"
.equ rA,1
.equ rB,2
.equ rD,0
.equ rS,0
.equ UIMM_ILL, 32
.equ UIMM_1_ZERO, 0
.equ UIMM_1_ILL, 32
.equ UIMM_2_ILL, 1
.equ UIMM_4_ILL, 3
.equ UIMM_8_ILL, 7
.equ UIMM_GT7, 8
.equ UIMM_GT15, 16
.equ nnn_ILL, 8
.equ bbb_ILL, 8
.equ dd, 3
.equ dd_... |
stsp/binutils-ia16 | 2,342 | gas/testsuite/gas/ppc/bc.s | .macro err op:vararg
.ifndef AT
.ifndef Y
\op
.endif
.endif
.endm
.macro errat op:vararg
.ifndef AT
\op
.endif
.endm
.macro erry op:vararg
.ifndef Y
\op
.endif
.endm
.text
bc 0,0,.
errat bc 1,0,. # z bit
bc 2,0,.
errat bc 3,0,. # z bit
bc 4,0,.
errat bc 5,0,. # at = 01 reserv... |
stsp/binutils-ia16 | 1,766 | gas/testsuite/gas/ppc/xcoff-tls.s | # An external tdata symbol
.globl tdata_ext[TL]
.csect tdata_ext[TL]
.long 1
.csect tdata_int_csect[TL]
# A first internal tdata symbol
tdata_int1:
.long 2
# A second internal tdata symbol
tdata_int2:
.long 3
# Two external tbss symbols.
# XCOFF doesn't seem to allow internal tbss
# (or bss) symbols.
.c... |
stsp/binutils-ia16 | 1,578 | gas/testsuite/gas/ppc/power7.s | .text
power7:
lxvd2x 3,4,5
lxvd2x 43,4,5
stxvd2x 3,4,5
stxvd2x 43,4,5
xxmrghd 3,4,5
xxmrghd 43,44,45
xxmrgld 3,4,5
xxmrgld 43,44,45
xxpermdi 3,4,5,0
xxpermdi 43,44,45,0
xxpermdi 3,4,5,3
xxpermdi 43,44,45,3
xxpermdi 3,4,5,1
xxpermdi 43,44,45,1
xxpermdi 3,4,5,2
xxpermdi 43,44,45... |
stsp/binutils-ia16 | 3,095 | gas/testsuite/gas/ppc/vle.s | # Freescale PowerPC VLE instruction tests
#as: -mvle
.text
.extern extern_subr
.equ UI8,0x37
.equ SCI0,UI8<<0
.equ SCI1,UI8<<8
.equ SCI2,UI8<<16
.equ SCI3,UI8<<24
.equ r0,0
.equ r1,1
.equ r2,2
.equ r3,3
.equ r4,4
.equ r5,5
.equ r6,6
.equ r7,7
.equ r8,8
.equ r9,9
.equ r10,10
.equ r11,11
.equ r12,12
... |
stsp/binutils-ia16 | 1,134 | gas/testsuite/gas/ppc/vle-simple-2.s | .text
target0:
e_bdnz target1
e_bdnzl target1
e_bdz target2
target1:
e_bdzl target0
e_beq target0
e_beq cr1, target8
target2:
e_beql cr0, target1
e_beql target6
e_bf 4*cr0+gt, target3
target3:
e_bfl cr0*4+un, target0
e_bge cr1, target1
e_bge target5
target4:
e_bgel cr2, target3
e_bgel target4
e_bgt... |
stsp/binutils-ia16 | 1,026 | gas/testsuite/gas/ppc/power6.s | # PowerPC POWER6 AltiVec tests
#as: -mpower6
.text
start:
doze
nap
sleep
rvwinkle
prtyw 3,4
prtyd 13,14
mfcfar 10
mtcfar 11
cmpb 3,4,5
mffgpr 6,7
mftgpr 8,9
lwzcix 10,11,12
lfdpx 12,14,15
dadd 16,17,18
daddq 20,22,24
dss 3
dssall
dst 5,4,1
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2
attn
mtcr 3
mtc... |
stsp/binutils-ia16 | 1,921 | gas/testsuite/gas/ppc/simpshft.s | # These are all the examples from section F.4 of
# "PowerPC Microprocessor Family: The Programming Environments".
# 64-bit examples
extrdi %r4,%r3,1,0
insrdi %r3,%r4,1,0
sldi %r5,%r5,8
clrldi %r4,%r3,32
# 32-bit examples
extrwi %r4,%r3,1,0
insrwi %r3,%r4,1,0
slwi %r5,%r5,8
clrlwi %r4,%r3,16
# These test the r... |
stsp/binutils-ia16 | 1,230 | gas/testsuite/gas/ppc/altivec2.s | .text
start:
vabsdub 6,17,16
vabsduh 21,18,4
vabsduw 25,20,9
vpermxor 6,17,20,26
vaddeuqm 29,26,15,28
vaddecuq 15,8,7,24
vsubeuqm 2,6,21,1
vsubecuq 29,6,0,4
vmulouw 14,9,3
vmuluwm 24,16,18
vaddudm 10,17,17
vmaxud 30,25,4
vrld 10,6,28
vcmpequd 27,7,7
vadduqm 22,16,25
vaddcuq 1,21,29
vmulo... |
stsp/binutils-ia16 | 1,131 | gas/testsuite/gas/ppc/ppc750ps.s | # PowerPC 750 paired single precision tests
.text
start:
psq_l 0, 4(3), 1, 5
psq_lu 1, 8(2), 0, 3
psq_lux 2, 5, 4, 1, 2
psq_lx 3, 2, 4, 0, 5
psq_st 3, 8(2), 0, 3
psq_stu 3, 8(2), 0, 7
psq_stux 2, 3, 4, 0, 5
psq_stx 6, 7, 8, 1, 4
ps_abs 5,7
ps_abs. 5,7
ps_add 1,2,3
ps_add. 1,2,3
ps_cmpo0 3,2,4
ps_cmpo1 3,... |
stsp/binutils-ia16 | 1,707 | gas/testsuite/gas/elf/dwarf-5-file0-3.s | .file "test.c"
.text
.Ltext0:
.file 0 "/current/directory" "/full/path/test.c"
.globl x
.section .bss
.balign 4
.type x, %object
.size x, 4
x:
.zero 4
.text
.Letext0:
.file 1 "/full/path/test.c"
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x32
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_a... |
stsp/binutils-ia16 | 2,486 | gas/testsuite/gas/elf/dwarf2-6.s | /* Test view number decoding.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your optio... |
stsp/binutils-ia16 | 1,138 | gas/testsuite/gas/elf/dwarf2-10.s | /* Test view numbering zero-assert checking with zero-sized align.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3... |
stsp/binutils-ia16 | 5,257 | gas/testsuite/gas/elf/dwarf2-1.s | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2009-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
stsp/binutils-ia16 | 1,654 | gas/testsuite/gas/elf/dwarf-5-file0-2.s | .file "test.c"
.text
.Ltext0:
.file 0 "/example" "test.c"
.globl x
.section .bss
.balign 4
.type x, %object
.size x, 4
x:
.zero 4
.text
.Letext0:
.file 1 "test.c"
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x32
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.uleb128 0x1
.4byte .LA... |
stsp/binutils-ia16 | 1,328 | gas/testsuite/gas/elf/dwarf2-5.s | /* Test view numbering.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any... |
stsp/binutils-ia16 | 1,213 | gas/testsuite/gas/elf/dwarf2-19.s | /* Test view numbering continuity at subsection borders.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Li... |
stsp/binutils-ia16 | 2,789 | gas/testsuite/gas/elf/dwarf2-3.s | .file "beginwarn.c"
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.section .debug_info,"",%progbits
.Ldebug_info0:
.section .debug_line,"",%progbits
.Ldebug_line0:
.text
.Ltext0:
.section .init_array
.align 4
.type init_array, %object
.size init_array, 4
init_array:
.long foo
.section .gnu.warning.foo... |
stsp/binutils-ia16 | 5,382 | gas/testsuite/gas/elf/dwarf2-2.s | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2009-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lic... |
stsp/binutils-ia16 | 3,644 | gas/testsuite/gas/msp430/msp430x.s | .text
.global foo
foo:
adc r4 ; MSP430 instruction for comparison purposes.
adcx r4
adcx.a bar
adcx.b r6
adcx.w r7
addcx r8, r9
addcx.a #0x12345, r10
addcx.b r11, r12
addcx.w r13, r14
ADDX @R9, PC
ADDX R9, PC
ADDX.A #FE000h, PC
ADDX.A &EDE, PC
ADDX.A @R9+, PC
ADDX.A EDE, PC
addx.b r1, r... |
stsp/binutils-ia16 | 1,279 | gas/testsuite/gas/msp430/nop-int.s | .text
;;; Test some common instruction patterns for disabling/enabling interrupts.
;;; "MOV &FOO,r10" is used as an artbitrary statement which isn't a NOP, to
;;; break up the instructions being tested.
fn1:
;;; 1: Test EINT
;; 430 ISA: NOP *not* required before *or* after EINT
;; 430x ISA: NOP *is* required before... |
stsp/binutils-ia16 | 2,145 | gas/testsuite/gas/wasm32/allinsn.s | block[]
br 0
br_if 0
br_table 1 1 1
call 0
call_indirect 0 0
drop
else
end
f32.abs
f32.add
f32.ceil
f32.const 3.14159
f32.convert_s/i32
f32.convert_s/i64
f32.convert_u/i32
f32.convert_u/i64
f32.copysign
f32.demote/f64
f32.div
f32.eq
f32.floor
f32.ge
f32.gt
f32.le
f32.load a=0 0
f32.lt
f32.ma... |
stsp/binutils-ia16 | 3,323 | gas/testsuite/gas/mcore/allinsn.s | .data
foodata: .word 42
.text
footext:
.macro test insn text=""
.export \insn
\insn:
\insn \text
.endm
test abs r0
test addc "r1,r2" // A double forward slash starts a line comment
test addi "r3, 1" # So does a hash
test addu "r4, r5" // White space between operands should be ignored
test and "r6,r... |
stsp/binutils-ia16 | 5,219 | gas/testsuite/gas/fr30/allinsn.s | .data
foodata: .word 42
.text
footext:
.global add
add:
add r0, r1
add #0, r2
.global add2
add2:
add2 #-1, r3
.global addc
addc:
addc r4, r5
.global addn
addn:
addn r6, r7
addn #15, r8
.global addn2
addn2:
addn2 #-16, r9
.global sub
sub:
sub r10, r11
.global subc
subc:
subc r12, r13
.global subn
sub... |
stsp/binutils-ia16 | 6,114 | gas/testsuite/gas/iq2000/allinsn.s | .data
foodata: .word 42
.text
footext:
.text
.global add
add:
add %0,%0,%0
.text
.global addi
addi:
addi %0,%0,-4
.text
.global addiu
addiu:
addiu %0,%0,4
.text
.global addu
addu:
addu %0,%0,%0
.text
.global ado16
ado16:
ado16 %0,%0,%0
.text
.global and
and:
and %0,%0,%0
.text
.global andi
andi:
... |
stsp/binutils-ia16 | 1,540 | gas/testsuite/gas/iq2000/yield0.s | # This test case includes a single case of a yield instruction
# (e.g. SLEEP) appearing in the branch delay slot. We expect
# the assembler to issue a warning about this!
.text
# yield insn in the branch delay slot.
beq %0,%0,foo
cfc2 %1, %1
# likewise for the rest.
beq %0,%0,foo
cfc3 %1, %1
beq %0,%0,foo
... |
stsp/binutils-ia16 | 2,027 | gas/testsuite/gas/score/rD_rA_rB.s | /*
* test relax
* add.c <-> add! : register number must be in 0-15
* addc.c <-> addc! : register number must be in 0-15
* sub.c <-> sub! : register number must be in 0-15
* and.c <-> and! : register number must be in 0-15
* or.c <-> or! : register number must be in 0-15
* xor.c <-> xor! : register nu... |
stsp/binutils-ia16 | 1,344 | gas/testsuite/gas/score/rD_rA.s | /*
* test relax
* not.c <-> not! : register number must be in 0-15
* neg.c <-> neg! : register number must be in 0-15
* cmp.c <-> cmp! : register number must be in 0-15
* Author: ligang
*/
/* This macro transform 32b instruction to 16b. */
.macro tran3216 insn32, insn16
.align 4
\insn32 r0, r7 #32b ... |
stsp/binutils-ia16 | 1,860 | gas/testsuite/gas/score/ls32ls16p.s | /*
* test relax
* lw <-> lwp! : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b
* lh <-> lhp! : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b
* lbu <-> lbu! : rs = r2, offset != 0, offset : 5b
* sw <-> swp! : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b
* sh <-> shp! : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b... |
stsp/binutils-ia16 | 1,600 | gas/testsuite/gas/score/ls32ls16.s | /*
* test relax
* lw <-> lw! : register number must be in 0-15, offset == 0
* lh <-> lh! : register number must be in 0-15, offset == 0
* lbu <-> lbu! : register number must be in 0-15, offset == 0
* sw <-> sw! : register number must be in 0-15, offset == 0
* sh <-> sh! : register number must be in 0-15, ... |
stsp/binutils-ia16 | 1,080 | gas/testsuite/gas/score/addi.s | /*
* test relax
* addi <-> addei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b
* (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
* (2)addei! rD, imm4 : rD = rD + 2**imm4
* addi <-> subei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b... |
stsp/binutils-ia16 | 1,649 | gas/testsuite/gas/score/rD_rA_BN.s | /*
* test relax
* bitclr.c <-> bitclr! : register number must be in 0-15
* bitset.c <-> bitset! : register number must be in 0-15
* bittgl.c <-> bittgl! : register number must be in 0-15
* slli.c <-> slli! : register number must be in 0-15
* srli.c <-> srli! : register number must be in 0-15
* Author: l... |
stsp/binutils-ia16 | 3,775 | gas/testsuite/gas/score/branch_32.s | /*
* tests for branch instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _b_op_pattern insn insn1
.balign 2
/*
* for local label 1, assembler should NOT alter instructions before .skip;
* but it SHOULD alter instructions afte it.
*/
1:
insn_16 "\insn! 1b"
tran_16_32 "\insn... |
stsp/binutils-ia16 | 1,118 | gas/testsuite/gas/score/postlw.s | /*
* test relax
* post lw <-> pop! : offset == 4
* syntax:
lw rD, [rA]+, simm12 : rD and rA can be 0-31
pop! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31
* Author: ligang
*/
/* This macro transform 32b instruction to 16b. */
.macro tran3216 insn32, insn16
.align 4
\insn32 r23, [r7]+, 4 #32b -> 1... |
stsp/binutils-ia16 | 1,133 | gas/testsuite/gas/score/presw.s | /*
* test relax
* pre sw <-> push! : offset == -4
* syntax:
sw rD, [rA, simm12]+ : rD and rA can be 0-31
push! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31
* Author: ligang
*/
/* This macro transform 32b instruction to 16b. */
.macro tran3216 insn32, insn16
.align 4
\insn32 r0, [r2, -4]+ #32b -... |
stsp/binutils-ia16 | 1,910 | gas/testsuite/gas/score/move.s | /*
* test relax
* mv <-> mv! : for mv! : register number must be in 0-15
* mv <-> mhfl! : for mhfl! : rD must be in 16-31, rS must be in 0-15
* mv <-> mlfh! : for mhfl! : rD must be in 0-15, rS must be in 16-31
* Author: ligang
*/
/* This block test mv -> mv! */
.align 4
mv r0, r15 #32b -> 16b
mv! ... |
stsp/binutils-ia16 | 1,107 | gas/testsuite/gas/score/bittst.s | /*
* test relax
* bittst.c <-> bittst! : register number must be in 0-15
* Author: ligang
*/
/* This macro transform 32b instruction to 16b. */
.macro tran3216 insn32, insn16
\insn32 r0, 2 #32b -> 16b
\insn16 r0, 2
\insn32 r15, 4 #32b -> 16b
\insn16 r15, 4
\insn32 r15, 1 #32b ->... |
stsp/binutils-ia16 | 1,129 | gas/testsuite/gas/score/ldi.s | /*
* test relax
* ldi <-> ldiu! : for ldiu! : register number must be in 0-15, simm16: [0-255]
* (1)ldi rD, simm16 : rD = simm16
* (2)ldiu! rD, imm8 : rD = ZE(imm8)
* Author: ligang
*/
/* This macro transform 32b instruction to 16b. */
.macro tran3216 insn32, insn16
.align 4
\insn32 r2, 0 ... |
stsp/binutils-ia16 | 1,491 | gas/testsuite/gas/score/load_store_32.s | /*
* tests for load/store instruction relaxation
*
* Author: libin
*/
.include "relaxation_macro.h"
.macro _ls_op_pattern insn
.balign 2
insn_32 "\insn r0, [r0,0]"
insn_32 "\insn r15, [r0,0]"
insn_32 "\insn r0, [r7,0]"
insn_32 "\insn r15, [r7,0]"
/* NOTE: offset MUST be word aligned */
insn_32 "\insn ... |
stsp/binutils-ia16 | 8,392 | gas/testsuite/gas/s390/esa-g5.s | .text
foo:
a %r6,4095(%r5,%r10)
ad %f6,4095(%r5,%r10)
adb %f6,4095(%r5,%r10)
adbr %f6,%f9
adr %f6,%f9
ae %f6,4095(%r5,%r10)
aeb %f6,4095(%r5,%r10)
aebr %f6,%f9
aer %f6,%f9
ah %r6,4095(%r5,%r10)
ahi %r6,-32767
al %r6,4095(%r5,%r10)
alr %r6,%r9
ap 4095(6,%r5),4095(9,%r10)
ar %r6,%r9
au %f6,4095(%r5,%r10)
... |
stsp/binutils-ia16 | 4,787 | gas/testsuite/gas/s390/zarch-arch12.s | .text
foo:
vbperm %v15,%v17,%v20
vllezlf %v15,4000(%r6,%r9)
vmsl %v15,%v17,%v20,%v24,13,12
vmslg %v15,%v17,%v20,%v24,13
vnx %v15,%v17,%v20
vnn %v15,%v17,%v20
voc %v15,%v17,%v20
vpopctb %v15,%v17
vpopcth %v15,%v17
vpopctf %v15,%v17
vpopctg %v15,%v17
vfasb %v15,%v17,%v20
wfasb %v15,%v17,%v20
wfaxb %v15,%v17... |
stsp/binutils-ia16 | 1,207 | gas/testsuite/gas/s390/zarch-zEC12.s | .text
foo:
etnd %r6
ntstg %r6,-5555(%r7,%r8)
tabort 4000(%r6)
tbegin 4000(%r6),65000
tbeginc 4000(%r6),65000
tend
bpp 10,.,4000(%r6)
bprp 10,.,.+24
niai 10,13
lat %r6,-5555(%r7,%r8)
lgat %r6,-5555(%r7,%r8)
lfhat %r6,-5555(%r7,%r8)
llgfat %r6,-5555(%r7,%r8)
llgtat %r6,-5555(%r7,%r8)
clt %r6,10,-5555(%r7)... |
stsp/binutils-ia16 | 1,329 | gas/testsuite/gas/s390/zarch-z9-ec.s | .text
foo:
lpdfr %f6,%f2
lndfr %f6,%f2
cpsdr %f6,%f1,%f2
lcdfr %f6,%f2
ldgr %f6,%r2
lgdr %r2,%f6
adtr %f6,%f2,%f4
axtr %f8,%f9,%f4
cdtr %f6,%f2
cxtr %f1,%f0
kdtr %f6,%f2
kxtr %f6,%f2
cedtr %f6,%f2
cextr %f1,%f0
cdgtr %f6,%r2
cxgtr %f1,%r2
cdstr %f6,%r2
cxstr %f6,%r2
cdutr %f6,%r2
cxutr %f1,%r2
cgdt... |
stsp/binutils-ia16 | 5,178 | gas/testsuite/gas/s390/zarch-z196.s | .text
foo:
ahhhr %r6,%r7,%r8
ahhlr %r6,%r7,%r8
aih %r6,-65000
alhhhr %r6,%r7,%r8
alhhlr %r6,%r7,%r8
alsih %r6,65000
alsihn %r6,65000
brcth %r6,.
chhr %r6,%r7
chlr %r6,%r7
chf %r6,5555(%r7,%r8)
cih %r6,65000
clhhr %r6,%r7
clhlr %r6,%r7
clhf %r6,5555(%r7,%r8)
clih %r6,650000
clih %r9,4000000000
lbh %r6,... |
stsp/binutils-ia16 | 2,724 | gas/testsuite/gas/s390/zarch-z900.s | .text
foo:
ag %r9,4095(%r5,%r10)
agf %r9,4095(%r5,%r10)
agfr %r9,%r6
aghi %r9,-32767
agr %r9,%r6
alcg %r9,4095(%r5,%r10)
alcgr %r9,%r6
alg %r9,4095(%r5,%r10)
algf %r9,4095(%r5,%r10)
algfr %r9,%r6
algr %r9,%r6
bctg %r9,4095(%r5,%r10)
bctgr %r9,%r6
brctg %r9,.
jctg %r6,.
brxhg %r9,%r6,.
jxhg %r6,%r9,.
b... |
stsp/binutils-ia16 | 3,479 | gas/testsuite/gas/s390/zarch-arch13.s | .text
foo:
ncrk %r6,%r9,%r11
ncgrk %r6,%r9,%r11
mvcrl 4000(%r6),4000(%r9)
nnrk %r6,%r9,%r11
nngrk %r6,%r9,%r11
nork %r6,%r9,%r11
nogrk %r6,%r9,%r11
nxrk %r6,%r9,%r11
nxgrk %r6,%r9,%r11
ocrk %r6,%r9,%r11
ocgrk %r6,%r9,%r11
popcnt %r6,%r9
popcnt %r6,%r9,13
selr %r6,%r9,%r11,13
selro %r6,%r9,%r11
selrh %r6... |
stsp/binutils-ia16 | 7,642 | gas/testsuite/gas/s390/zarch-z10.s | .text
foo:
asi 5555(%r6),-42
agsi 5555(%r6),-42
alsi 5555(%r6),-42
algsi 5555(%r6),-42
crl %r6,.
cgrl %r6,.
cgfrl %r6,.
crb %r6,%r7,10,1111(%r8)
crbh %r6,%r7,1111(%r8)
crbnle %r6,%r7,1111(%r8)
crbl %r6,%r7,1111(%r8)
crbnhe %r6,%r7,1111(%r8)
crblh %r6,%r7,1111(%r8)
crbne %r6,%r7,1111(%r8)
crbe %r6,%r7,111... |
stsp/binutils-ia16 | 15,787 | gas/testsuite/gas/s390/zarch-z13.s | .text
foo:
lcbb %r6,4000(%r9,%r11),13
vgef %v15,4000(%r6,%r9),13
vgeg %v15,4000(%r6,%r9),13
vgbm %v15,65533
vzero %v15
vone %v15
vgm %v15,253,252,11
vgmb %v15,253,252
vgmh %v15,253,252
vgmf %v15,253,252
vgmg %v15,253,252
vlr %v15,%v17
vlrep %v15,4000(%r6,%r9),13
vlrepb %v15,4000(%r6,%r9)
vlreph %v15,4000... |
stsp/binutils-ia16 | 3,296 | gas/testsuite/gas/s390/zarch-z990.s | .text
foo:
ag %r6,-524288(%r5,%r10)
agf %r6,-524288(%r5,%r10)
ahy %r6,-524288(%r5,%r10)
alc %r6,-524288(%r5,%r10)
alcg %r6,-524288(%r5,%r10)
alg %r6,-524288(%r5,%r10)
algf %r6,-524288(%r5,%r10)
aly %r6,-524288(%r5,%r10)
ay %r6,-524288(%r5,%r10)
bctg %r6,-524288(%r5)
bxhg %r6,%r9,-524288(%r5)
bxleg %r6,%r9,-... |
stsp/binutils-ia16 | 1,288 | gas/testsuite/gas/s390/zarch-z9-109.s | .text
foo:
afi %r6,-2147483648
agfi %r6,-2147483648
alfi %r6,4294967295
algfi %r6,4294967295
nihf %r6,4294967295
nilf %r6,4294967295
cfi %r6,-2147483648
cgfi %r6,-2147483648
clfi %r6,4294967295
clgfi %r6,4294967295
xihf %r6,4294967295
xilf %r6,4294967295
iihf %r6,4294967295
iilf %r6,4294967295
flogr %r6,... |
stsp/binutils-ia16 | 1,828 | gas/testsuite/gas/i386/x86-64-notrack.s | # Check 64bit NOTRACK prefix
.allow_index_reg
.text
_start:
notrack call *%rax
notrack call *%r8
notrack jmp *%rax
notrack jmp *%r8
notrack call *(%rax)
notrack call *(%r8)
notrack jmp *(%rax)
notrack jmp *(%r8)
notrack call *(%eax)
notrack call *(%r8d)
notrack jmp *(%eax)
notrack jmp *(%r8d)
notrack... |
stsp/binutils-ia16 | 3,065 | gas/testsuite/gas/i386/x86-64-bundle.s | .bundle_align_mode 5
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,31].
.macro offset_insn insn_name, offset
.p2align 5
\insn_name\()_offset_\offset\():
.if \offset
.space \offset, 0xf4
.endif
\insn_name
.endm
.macro test_offsets insn_name
offset_insn \insn_name, ... |
stsp/binutils-ia16 | 14,595 | gas/testsuite/gas/i386/x86-64-avx512f_vl-wig.s | # Check 64bit AVX512{F,VL} WIG instructions
.allow_index_reg
.text
_start:
vpmovsxbd %xmm29, %xmm30 # AVX512{F,VL}
vpmovsxbd %xmm29, %xmm30{%k7} # AVX512{F,VL}
vpmovsxbd %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vpmovsxbd (%rcx), %xmm30 # AVX512{F,VL}
vpmovsxbd 0x123(%rax,%r14,8), %xmm30 # AVX512{F,VL}
vpmovs... |
stsp/binutils-ia16 | 715,565 | gas/testsuite/gas/i386/x86-64-avx512f_vl.s | # Check 64bit AVX512{F,VL} instructions
.allow_index_reg
.text
_start:
vaddpd %xmm28, %xmm29, %xmm30 # AVX512{F,VL}
vaddpd %xmm28, %xmm29, %xmm30{%k7} # AVX512{F,VL}
vaddpd %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{F,VL}
vaddpd (%rcx), %xmm29, %xmm30 # AVX512{F,VL}
vaddpd 0x123(%rax,%r14,8), %xmm29, %xmm30 #... |
stsp/binutils-ia16 | 6,004 | gas/testsuite/gas/i386/x86-64-avx512vnni_vl.s | # Check 64bit AVX512{VNNI,VL} instructions
.allow_index_reg
.text
_start:
vpdpwssd %xmm20, %xmm22, %xmm26 # AVX512{VNNI,VL}
vpdpwssd %xmm20, %xmm22, %xmm26{%k3} # AVX512{VNNI,VL}
vpdpwssd %xmm20, %xmm22, %xmm26{%k3}{z} # AVX512{VNNI,VL}
vpdpwssd 0x123(%rax,%r14,8), %xmm22, %xmm26 # AVX512{VNNI,VL}
vpdpwssd ... |
stsp/binutils-ia16 | 10,356 | gas/testsuite/gas/i386/x86-64-avx512vbmi_vl.s | # Check 64bit AVX512{VBMI,VL} instructions
.allow_index_reg
.text
_start:
vpermb %xmm28, %xmm29, %xmm30 # AVX512{VBMI,VL}
vpermb %xmm28, %xmm29, %xmm30{%k7} # AVX512{VBMI,VL}
vpermb %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{VBMI,VL}
vpermb (%rcx), %xmm29, %xmm30 # AVX512{VBMI,VL}
vpermb 0x123(%rax,%r14,8), %x... |
stsp/binutils-ia16 | 2,228 | gas/testsuite/gas/i386/x86-64-avx512dq-rcig.s | # Check 64bit AVX512DQ-RCIG instructions
.allow_index_reg
.text
_start:
vrangepd $0xab, {sae}, %zmm28, %zmm29, %zmm30 # AVX512DQ
vrangepd $123, {sae}, %zmm28, %zmm29, %zmm30 # AVX512DQ
vrangeps $0xab, {sae}, %zmm28, %zmm29, %zmm30 # AVX512DQ
vrangeps $123, {sae}, %zmm28, %zmm29, %zmm30 # AVX512DQ
vrangesd $... |
stsp/binutils-ia16 | 4,894 | gas/testsuite/gas/i386/reloc64.s | .macro bad args:vararg
.ifdef _bad_
\args
.endif
.endm
.macro ill args:vararg
# This is used to mark entries that aren't handled consistently,
# and thus shouldn't currently be checked for.
# \args
.endm
.text
_start:
movabs $xtrn, %rax
add $xtrn, %rax
mov $xtrn, %eax
mov $xtrn, %ax
mov $xtrn, %a... |
stsp/binutils-ia16 | 5,772 | gas/testsuite/gas/i386/disassem.s | .text
.byte 0xFF, 0xEF
.byte 0xFF, 0xD8
.fill 0x5, 0x1, 0x90
.byte 0xC5, 0xEC, 0x4A, 0x9B
.byte 0xC5, 0xEC, 0x4A, 0x6F
.byte 0xC5, 0xEC, 0x4A, 0x3F
.byte 0xC5, 0xED, 0x4A, 0x9B
.byte 0xC5, 0xED, 0x4A, 0x6F
.byte 0xC5, 0xED, 0x4A, 0x3F
.byte 0xC4, 0xE1, 0xEC, 0x4A, 0x9B
.byte 0xC4, 0xE1, 0xEC, 0x4A, 0x6F
.byte 0xC4, 0xE... |
stsp/binutils-ia16 | 3,346 | gas/testsuite/gas/i386/noreg64.s | .macro pfx insn:vararg
.ifdef DATA16
data16 \insn
.else
.ifdef REX64
rex64 \insn
.else
\insn
.endif
.endif
.endm
.macro pfx16 insn:vararg
.ifndef REX64
pfx \insn
.endif
.endm
.macro pfx64 insn:vararg
.ifndef DATA16
pfx \insn
.endif
.endm
.text
noreg:
pfx adc $1, (%rax)
pfx adc $0x89, (%rax)... |
stsp/binutils-ia16 | 85,354 | gas/testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.s | # Check 64bit VCM.*{PH,SH} instructions
.allow_index_reg
.text
_start:
vcmpeq_oqph %zmm29, %zmm30, %k5
vcmpeq_oqph %zmm29, %zmm30, %k5{%k7}
vcmpeq_oqph {sae}, %zmm29, %zmm30, %k5
vcmpeq_oqph (%rcx), %zmm30, %k5
vcmpeq_oqph 0x123(%rax,%r14,8), %zmm30, %k5
vcmpeq_oqph (%rcx){1to32}, %zmm30, %k5
vc... |
stsp/binutils-ia16 | 4,634 | gas/testsuite/gas/i386/avx512vbmi.s | # Check 32bit AVX512VBMI instructions
.allow_index_reg
.text
_start:
vpermb %zmm4, %zmm5, %zmm6 # AVX512VBMI
vpermb %zmm4, %zmm5, %zmm6{%k7} # AVX512VBMI
vpermb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512VBMI
vpermb (%ecx), %zmm5, %zmm6 # AVX512VBMI
vpermb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512VBMI
vpermb 8... |
stsp/binutils-ia16 | 10,354 | gas/testsuite/gas/i386/avx512vbmi2.s | # Check 32bit AVX512VBMI2 instructions
.allow_index_reg
.text
_start:
vpcompressb %zmm6, (%ecx){%k7} # AVX512VBMI2
vpcompressb %zmm6, -123456(%esp,%esi,8) # AVX512VBMI2
vpcompressb %zmm6, 126(%edx) # AVX512VBMI2 Disp8
vpcompressb %zmm5, %zmm6 # AVX512VBMI2
vpcompressb %zmm5, %zmm6{%k7} # AVX512VBMI2
vpcom... |
stsp/binutils-ia16 | 95,745 | gas/testsuite/gas/i386/avx512dq_vl.s | # Check 32bit AVX512{DQ,VL} instructions
.allow_index_reg
.text
_start:
vbroadcastf64x2 (%ecx), %ymm6{%k7} # AVX512{DQ,VL}
vbroadcastf64x2 (%ecx), %ymm6{%k7}{z} # AVX512{DQ,VL}
vbroadcastf64x2 -123456(%esp,%esi,8), %ymm6{%k7} # AVX512{DQ,VL}
vbroadcastf64x2 2032(%edx), %ymm6{%k7} # AVX512{DQ,VL} Disp8
vbroa... |
stsp/binutils-ia16 | 1,482 | gas/testsuite/gas/i386/string-ok.s | .text
.code32
start32:
cmpsb (%edi), %cs:(%esi)
cmpsb %es:(%edi), (%esi)
cmpsb (%di), (%si)
cmpsb (%esi), (%edi)
insb (%dx), %es:(%edi)
insb (%dx), (%esi)
lodsb %cs:(%esi)
lodsb (%edi)
movsb %cs:(%esi), (%edi)
movsb (%esi), %es:(%edi)
movsb (%si), (%di)
movsb (%ebx), (%edi)
movsb (%esi), (%ebx)
outs... |
stsp/binutils-ia16 | 5,379 | gas/testsuite/gas/i386/avx512bitalg_vl.s | # Check 32bit AVX512{BITALG,VL} instructions
.allow_index_reg
.text
_start:
vpshufbitqmb %xmm4, %xmm5, %k5{%k7} # AVX512{BITALG,VL}
vpshufbitqmb -123456(%esp,%esi,8), %xmm5, %k5{%k7} # AVX512{BITALG,VL}
vpshufbitqmb 2032(%edx), %xmm5, %k5{%k7} # AVX512{BITALG,VL} Disp8
vpshufbitqmb %ymm4, %ymm5, %k5{%k7} # A... |
stsp/binutils-ia16 | 3,303 | gas/testsuite/gas/i386/avx512ifma.s | # Check 32bit AVX512IFMA instructions
.allow_index_reg
.text
_start:
vpmadd52luq %zmm4, %zmm5, %zmm6 # AVX512IFMA
vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA
vpmadd52luq %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512IFMA
vpmadd52luq (%ecx), %zmm5, %zmm6 # AVX512IFMA
vpmadd52luq -123456(%esp,%esi,8), %zmm5, %zmm... |
stsp/binutils-ia16 | 1,179 | gas/testsuite/gas/i386/x86-64-adx.s | # Check 64 bit ADX instructions.
.allow_index_reg
.text
_start:
adcx 400(%ecx), %eax
adcx %edx, %ecx
adcx -654321(%esp,%esi,8), %edx
adcx (%eax), %eax
adcxl %edx, %ecx
adcxl (%eax), %eax
adcx 400(%rcx), %r11
adcx %r14, %r12
adcx -654321(%esp,%esi,8), %rdx
adcx (%r8), %r... |
stsp/binutils-ia16 | 1,505 | gas/testsuite/gas/i386/avx512f_vaes-wig.s | # Check 32bit AVX512F,VAES WIG instructions
.allow_index_reg
.text
_start:
vaesdec %zmm4, %zmm5, %zmm6 # AVX512F,VAES
vaesdec -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,VAES
vaesdec 8128(%edx), %zmm5, %zmm6 # AVX512F,VAES Disp8
vaesdeclast %zmm4, %zmm5, %zmm6 # AVX512F,VAES
vaesdeclast -123456(%esp,%esi,... |
stsp/binutils-ia16 | 1,777 | gas/testsuite/gas/i386/x86-64-mpx-inval-2.s | # MPX instructions
.allow_index_reg
.text
### bndmk
bndmk (%eax), %bnd1
bndmk 0x3(%ecx,%ebx,1), %bnd1
bndmk (%rip), %bnd3
bndmk (%eip), %bnd2
### bndmov
bndmov (%r8d), %bnd1
bndmov 0x3(%r9d,%edx,1), %bnd1
bndmov %bnd1, (%eax)
bndmov %bnd1, 0x3(%ecx,%eax,1)
### bndcl
bndcl (%ecx), %bnd1
bndcl 0x3(%ecx... |
stsp/binutils-ia16 | 2,710 | gas/testsuite/gas/i386/x86-64-bmi.s | # Check 64bit BMI instructions
.allow_index_reg
.text
_start:
# Test for op r16, r/m16
tzcnt %ax,%bx
tzcnt (%rcx),%bx
tzcnt (%rcx),%r15w
# Test for op r32, r32, r/m32
andn %eax,%ebx,%esi
andn (%rcx),%ebx,%esi
andn %r9d,%r15d,%r10d
andn (%rcx),%r15d,%r10d
# Test for op r32, r/m32, r32
bextr %eax,%ebx,%esi
... |
stsp/binutils-ia16 | 5,370 | gas/testsuite/gas/i386/dw2-compress-1.s | /* This testcase is copied from a similar test in GDB.
Copyright (C) 2010-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the Lice... |
stsp/binutils-ia16 | 1,405 | gas/testsuite/gas/i386/dw2-compress-3.s | .file "dw2-compress-3.c"
.text
.Ltext0:
.comm foo,4,4
.Letext0:
.file 1 "dw2-compress-3.c"
.section .debug_info,"",@progbits
.Ldebug_info0:
.long 0x32
.value 0x4
.long .Ldebug_abbrev0
.byte 0x4
.uleb128 0x1
.long .LASF0
.byte 0x1
.long .LASF1
.long .LASF2
.long .Ldebug_line0
.uleb128 0x2
.string "foo"
... |
stsp/binutils-ia16 | 3,081 | gas/testsuite/gas/i386/avx512bw_vl-opts.s | # Check 32bit AVX512{BW,VL} swap instructions
.allow_index_reg
.text
_start:
vmovdqu8 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
vmovdqu8.s %xmm5, %xmm6{%k7} # AVX512{BW,VL}
vmovdqu8 %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
vmovdqu8.s %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
vmovdqu8 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
vmov... |
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