Subset (55)

assembly · 495k rows

Split (1)

train · 495k rows

repo_id stringlengths 5 115	size int64 590 5.01M	file_path stringlengths 4 212	content stringlengths 590 5.01M
tactcomplabs/xbgas-binutils-gdb	103,044	sim/testsuite/bfin/se_undefinedinstruction3.S	//Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction3/se_undefinedinstruction3.dsp // Description: 32 bit special cases Undefined Instructions in Supervisor Mode # mach: bfin # sim: --environment operating # xfail: "missing checks in A0/A1 macfunc" - #include "test.h" .include "testutils.inc" start // // Constants and Defines // include(gen_int.inc) include(selfcheck.inc) include(std.inc) include(mmrs.inc) include(symtable.inc) #ifndef STACKSIZE #define STACKSIZE 0x10 // change for how much stack you need #endif #ifndef ITABLE #define ITABLE 0xF0000000 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // etc.) // BOOT: INIT_R_REGS(0); // initialize general purpose regs INIT_P_REGS(0); // initialize the pointers INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); CLI R1; // inhibit events during MMR writes LD32_LABEL(sp, USTACK); // setup the user stack pointer USP = SP; LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer FP = SP; // and frame pointer LD32(p0, EVT0); // Setup Event Vectors and Handlers P0 += 4; // EVT0 not used (Emulation) P0 += 4; // EVT1 not used (Reset) LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; P0 += 4; // EVT4 not used (Global Interrupt Enable) LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R1 = -1; // Change this to mask interrupts () CSYNC; // wait for MMR writes to finish STI R1; // sync and reenable events (implicit write to IMASK) DUMMY: A0 = 0; // reset accumulators A1 = 0; R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs SYSCFG = r0; RETS = r0; // prevent X's breaking LINK instruction // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); CLI R1; // inhibit events during write to MMR [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; // wait for it STI R1; // reenable events with proper imask RAISE 15; // after we RTI, INT 15 should be taken RTI; // // The Main Program // STARTUSER: LINK 0; // change for how much stack frame space you need. JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // count of UI's will be in r5, which was initialized to 0 by header .dw 0xE802 ; .dw 0xB3FD ; .dw 0xE803 ; .dw 0xD461 ; .dw 0xE804 ; .dw 0x36A1 ; .dw 0xE805 ; .dw 0x7FED ; .dw 0xE806 ; .dw 0xFEB3 ; .dw 0xE807 ; .dw 0x8785 ; .dw 0xE808 ; .dw 0x2F21 ; .dw 0xE809 ; .dw 0x2889 ; .dw 0xE80A ; .dw 0x96B7 ; .dw 0xE80B ; .dw 0x8357 ; .dw 0xE80C ; .dw 0x5D07 ; .dw 0xE80D ; .dw 0x13D5 ; .dw 0xE80E ; .dw 0x1C11 ; .dw 0xE80F ; .dw 0x19D3 ; .dw 0xE810 ; .dw 0xBF4B ; .dw 0xE811 ; .dw 0xEF89 ; .dw 0xE812 ; .dw 0x2BD ; .dw 0xE813 ; .dw 0x6FC5 ; .dw 0xE814 ; .dw 0x89F1 ; .dw 0xE815 ; .dw 0x1D13 ; .dw 0xE816 ; .dw 0xA03F ; .dw 0xE817 ; .dw 0x9681 ; .dw 0xE818 ; .dw 0x2961 ; .dw 0xE819 ; .dw 0xEE23 ; .dw 0xE81A ; .dw 0x7ABB ; .dw 0xE81B ; .dw 0x8927 ; .dw 0xE81C ; .dw 0x2343 ; .dw 0xE81D ; .dw 0x308F ; .dw 0xE81E ; .dw 0x718F ; .dw 0xE81F ; .dw 0xC549 ; .dw 0xE820 ; .dw 0x2CD3 ; .dw 0xE821 ; .dw 0x81D9 ; .dw 0xE822 ; .dw 0xD76B ; .dw 0xE823 ; .dw 0xB735 ; .dw 0xE824 ; .dw 0x4EBB ; .dw 0xE825 ; .dw 0x6223 ; .dw 0xE826 ; .dw 0x15EB ; .dw 0xE827 ; .dw 0xB19F ; .dw 0xE828 ; .dw 0x6E6B ; .dw 0xE829 ; .dw 0x7EA3 ; .dw 0xE82A ; .dw 0xF2A7 ; .dw 0xE82B ; .dw 0xA8E1 ; .dw 0xE82C ; .dw 0x14ED ; .dw 0xE82D ; .dw 0x2BA5 ; .dw 0xE82E ; .dw 0xDD5 ; .dw 0xE82F ; .dw 0x69AD ; .dw 0xE830 ; .dw 0xCB47 ; .dw 0xE831 ; .dw 0x85F7 ; .dw 0xE832 ; .dw 0xB25D ; .dw 0xE833 ; .dw 0x8351 ; .dw 0xE834 ; .dw 0xE445 ; .dw 0xE835 ; .dw 0x33E5 ; .dw 0xE836 ; .dw 0x8F6B ; .dw 0xE837 ; .dw 0x9D5B ; .dw 0xE838 ; .dw 0xBE1 ; .dw 0xE839 ; .dw 0x3DB9 ; .dw 0xE83A ; .dw 0x7391 ; .dw 0xE83B ; .dw 0x70E5 ; .dw 0xE83C ; .dw 0x7409 ; .dw 0xE83D ; .dw 0xF5A9 ; .dw 0xE83E ; .dw 0xA15B ; .dw 0xE83F ; .dw 0x1D3F ; .dw 0xE840 ; .dw 0xF709 ; .dw 0xE841 ; .dw 0x6751 ; .dw 0xE842 ; .dw 0xD565 ; .dw 0xE843 ; .dw 0x1035 ; .dw 0xE844 ; .dw 0x755 ; .dw 0xE845 ; .dw 0x46AD ; .dw 0xE846 ; .dw 0x95F3 ; .dw 0xE847 ; .dw 0x39B3 ; .dw 0xE848 ; .dw 0xC4EB ; .dw 0xE849 ; .dw 0xD693 ; .dw 0xE84A ; .dw 0xE40F ; .dw 0xE84B ; .dw 0xC30F ; .dw 0xE84C ; .dw 0x101F ; .dw 0xE84D ; .dw 0xBEA7 ; .dw 0xE84E ; .dw 0xE617 ; .dw 0xE84F ; .dw 0x1BD ; .dw 0xE850 ; .dw 0xF203 ; .dw 0xE851 ; .dw 0x48D5 ; .dw 0xE852 ; .dw 0xA3DD ; .dw 0xE853 ; .dw 0xDD7F ; .dw 0xE854 ; .dw 0x3233 ; .dw 0xE855 ; .dw 0xFE45 ; .dw 0xE856 ; .dw 0x6C3D ; .dw 0xE857 ; .dw 0x6225 ; .dw 0xE858 ; .dw 0x722F ; .dw 0xE859 ; .dw 0x1BDD ; .dw 0xE85A ; .dw 0xFC35 ; .dw 0xE85B ; .dw 0xB4C1 ; .dw 0xE85C ; .dw 0xA635 ; .dw 0xE85D ; .dw 0xD62D ; .dw 0xE85E ; .dw 0xFF7D ; .dw 0xE85F ; .dw 0x2463 ; .dw 0xE860 ; .dw 0x439B ; .dw 0xE861 ; .dw 0xE4EF ; .dw 0xE862 ; .dw 0x299 ; .dw 0xE863 ; .dw 0x8E4F ; .dw 0xE864 ; .dw 0xFCA1 ; .dw 0xE865 ; .dw 0x4DFD ; .dw 0xE866 ; .dw 0x6E7D ; .dw 0xE867 ; .dw 0xCDAF ; .dw 0xE868 ; .dw 0x61D1 ; .dw 0xE869 ; .dw 0xE7C7 ; .dw 0xE86A ; .dw 0xA59D ; .dw 0xE86B ; .dw 0x6ED7 ; .dw 0xE86C ; .dw 0x40CF ; .dw 0xE86D ; .dw 0x8B4B ; .dw 0xE86E ; .dw 0xDA83 ; .dw 0xE86F ; .dw 0x5DF1 ; .dw 0xE870 ; .dw 0x18B5 ; .dw 0xE871 ; .dw 0x6D91 ; .dw 0xE872 ; .dw 0xB7EF ; .dw 0xE873 ; .dw 0xC941 ; .dw 0xE874 ; .dw 0x7BE9 ; .dw 0xE875 ; .dw 0x98A3 ; .dw 0xE876 ; .dw 0x7269 ; .dw 0xE877 ; .dw 0xEECF ; .dw 0xE878 ; .dw 0xB77B ; .dw 0xE879 ; .dw 0xFBFD ; .dw 0xE87A ; .dw 0x5B59 ; .dw 0xE87B ; .dw 0xDAD ; .dw 0xE87C ; .dw 0x97F5 ; .dw 0xE87D ; .dw 0xC8B ; .dw 0xE87E ; .dw 0x8DA1 ; .dw 0xE87F ; .dw 0x32A5 ; .dw 0xE880 ; .dw 0xA3B7 ; .dw 0xE881 ; .dw 0x6C27 ; .dw 0xE882 ; .dw 0xCBB7 ; .dw 0xE883 ; .dw 0x1873 ; .dw 0xE884 ; .dw 0xA2CF ; .dw 0xE885 ; .dw 0x9083 ; .dw 0xE886 ; .dw 0x2737 ; .dw 0xE887 ; .dw 0xD383 ; .dw 0xE888 ; .dw 0xCC51 ; .dw 0xE889 ; .dw 0xE1AD ; .dw 0xE88A ; .dw 0x8A01 ; .dw 0xE88B ; .dw 0x8123 ; .dw 0xE88C ; .dw 0x712D ; .dw 0xE88D ; .dw 0x47FF ; .dw 0xE88E ; .dw 0xB8CD ; .dw 0xE88F ; .dw 0xB23B ; .dw 0xE890 ; .dw 0x7C89 ; .dw 0xE891 ; .dw 0xA19F ; .dw 0xE892 ; .dw 0xE745 ; .dw 0xE893 ; .dw 0xC985 ; .dw 0xE894 ; .dw 0xA199 ; .dw 0xE895 ; .dw 0x176F ; .dw 0xE896 ; .dw 0x759D ; .dw 0xE897 ; .dw 0x54B ; .dw 0xE898 ; .dw 0x8EF7 ; .dw 0xE899 ; .dw 0xC987 ; .dw 0xE89A ; .dw 0xEFAB ; .dw 0xE89B ; .dw 0x6C97 ; .dw 0xE89C ; .dw 0xFF7B ; .dw 0xE89D ; .dw 0xCB35 ; .dw 0xE89E ; .dw 0xE57B ; .dw 0xE89F ; .dw 0x57F1 ; .dw 0xE8A0 ; .dw 0x8F ; .dw 0xE8A1 ; .dw 0xE667 ; .dw 0xE8A2 ; .dw 0xB56F ; .dw 0xE8A3 ; .dw 0xCD93 ; .dw 0xE8A4 ; .dw 0x460F ; .dw 0xE8A5 ; .dw 0x1EAF ; .dw 0xE8A6 ; .dw 0xDFD1 ; .dw 0xE8A7 ; .dw 0x6921 ; .dw 0xE8A8 ; .dw 0xE397 ; .dw 0xE8A9 ; .dw 0x6BB9 ; .dw 0xE8AA ; .dw 0xFBEB ; .dw 0xE8AB ; .dw 0x6E7 ; .dw 0xE8AC ; .dw 0x4367 ; .dw 0xE8AD ; .dw 0xA337 ; .dw 0xE8AE ; .dw 0xE6A3 ; .dw 0xE8AF ; .dw 0xEA89 ; .dw 0xE8B0 ; .dw 0xB2B1 ; .dw 0xE8B1 ; .dw 0xA6D ; .dw 0xE8B2 ; .dw 0x428D ; .dw 0xE8B3 ; .dw 0x993D ; .dw 0xE8B4 ; .dw 0x5B73 ; .dw 0xE8B5 ; .dw 0x8717 ; .dw 0xE8B6 ; .dw 0xE189 ; .dw 0xE8B7 ; .dw 0x1F87 ; .dw 0xE8B8 ; .dw 0x3D3 ; .dw 0xE8B9 ; .dw 0xE7ED ; .dw 0xE8BA ; .dw 0x2FDB ; .dw 0xE8BB ; .dw 0xFA71 ; .dw 0xE8BC ; .dw 0x6AF7 ; .dw 0xE8BD ; .dw 0x3C97 ; .dw 0xE8BE ; .dw 0x38B9 ; .dw 0xE8BF ; .dw 0x5C3B ; .dw 0xE8C0 ; .dw 0x9B53 ; .dw 0xE8C1 ; .dw 0xB51F ; .dw 0xE8C2 ; .dw 0x5C73 ; .dw 0xE8C3 ; .dw 0x49D ; .dw 0xE8C4 ; .dw 0xA8F ; .dw 0xE8C5 ; .dw 0xF3 ; .dw 0xE8C6 ; .dw 0x4FFB ; .dw 0xE8C7 ; .dw 0x6479 ; .dw 0xE8C8 ; .dw 0xDED5 ; .dw 0xE8C9 ; .dw 0xA557 ; .dw 0xE8CA ; .dw 0x7E0D ; .dw 0xE8CB ; .dw 0x4513 ; .dw 0xE8CC ; .dw 0x31AF ; .dw 0xE8CD ; .dw 0x4361 ; .dw 0xE8CE ; .dw 0x61B5 ; .dw 0xE8CF ; .dw 0xAACB ; .dw 0xE8D0 ; .dw 0xA85B ; .dw 0xE8D1 ; .dw 0x4569 ; .dw 0xE8D2 ; .dw 0xF277 ; .dw 0xE8D3 ; .dw 0x2B57 ; .dw 0xE8D4 ; .dw 0x39A5 ; .dw 0xE8D5 ; .dw 0xEC0F ; .dw 0xE8D6 ; .dw 0xB9DF ; .dw 0xE8D7 ; .dw 0x6F75 ; .dw 0xE8D8 ; .dw 0x793F ; .dw 0xE8D9 ; .dw 0x32A1 ; .dw 0xE8DA ; .dw 0xAA99 ; .dw 0xE8DB ; .dw 0x1829 ; .dw 0xE8DC ; .dw 0x4097 ; .dw 0xE8DD ; .dw 0x8323 ; .dw 0xE8DE ; .dw 0x510B ; .dw 0xE8DF ; .dw 0xBF73 ; .dw 0xE8E0 ; .dw 0xD31 ; .dw 0xE8E1 ; .dw 0xB1BD ; .dw 0xE8E2 ; .dw 0x756F ; .dw 0xE8E3 ; .dw 0x4C83 ; .dw 0xE8E4 ; .dw 0xEC7F ; .dw 0xE8E5 ; .dw 0x37BB ; .dw 0xE8E6 ; .dw 0xC767 ; .dw 0xE8E7 ; .dw 0x5379 ; .dw 0xE8E8 ; .dw 0x4D39 ; .dw 0xE8E9 ; .dw 0x25F9 ; .dw 0xE8EA ; .dw 0xAB13 ; .dw 0xE8EB ; .dw 0xB895 ; .dw 0xE8EC ; .dw 0x8E35 ; .dw 0xE8ED ; .dw 0xC6EB ; .dw 0xE8EE ; .dw 0xBFB3 ; .dw 0xE8EF ; .dw 0x4EF3 ; .dw 0xE8F0 ; .dw 0xA2B9 ; .dw 0xE8F1 ; .dw 0x6807 ; .dw 0xE8F2 ; .dw 0x37B3 ; .dw 0xE8F3 ; .dw 0xAAC3 ; .dw 0xE8F4 ; .dw 0xA461 ; .dw 0xE8F5 ; .dw 0x42C3 ; .dw 0xE8F6 ; .dw 0x9A4B ; .dw 0xE8F7 ; .dw 0xDF03 ; .dw 0xE8F8 ; .dw 0xAA6B ; .dw 0xE8F9 ; .dw 0xFD0F ; .dw 0xE8FA ; .dw 0x695 ; .dw 0xE8FB ; .dw 0x5EB1 ; .dw 0xE8FC ; .dw 0xBE8D ; .dw 0xE8FD ; .dw 0xB949 ; .dw 0xE8FE ; .dw 0x9023 ; .dw 0xE8FF ; .dw 0xB987 ; .dw 0xE900 ; .dw 0x475B ; .dw 0xE901 ; .dw 0x2DB5 ; .dw 0xE902 ; .dw 0xCD17 ; .dw 0xE903 ; .dw 0x6C33 ; .dw 0xE904 ; .dw 0xC013 ; .dw 0xE905 ; .dw 0xBB77 ; .dw 0xE906 ; .dw 0x2DC3 ; .dw 0xE907 ; .dw 0x7C11 ; .dw 0xE908 ; .dw 0x15F7 ; .dw 0xE909 ; .dw 0xFD0F ; .dw 0xE90A ; .dw 0x35B1 ; .dw 0xE90B ; .dw 0x165D ; .dw 0xE90C ; .dw 0x8327 ; .dw 0xE90D ; .dw 0xC449 ; .dw 0xE90E ; .dw 0x2E4F ; .dw 0xE90F ; .dw 0xEAEF ; .dw 0xE910 ; .dw 0x3EFB ; .dw 0xE911 ; .dw 0xFFB3 ; .dw 0xE912 ; .dw 0x6AF3 ; .dw 0xE913 ; .dw 0x7A73 ; .dw 0xE914 ; .dw 0xDBD7 ; .dw 0xE915 ; .dw 0x7FA7 ; .dw 0xE916 ; .dw 0xB681 ; .dw 0xE917 ; .dw 0x1023 ; .dw 0xE918 ; .dw 0xAA85 ; .dw 0xE919 ; .dw 0x12A9 ; .dw 0xE91A ; .dw 0x27F ; .dw 0xE91B ; .dw 0x9EF7 ; .dw 0xE91C ; .dw 0xFB09 ; .dw 0xE91D ; .dw 0xF179 ; .dw 0xE91E ; .dw 0xEFAD ; .dw 0xE91F ; .dw 0x3A67 ; .dw 0xE920 ; .dw 0x9301 ; .dw 0xE921 ; .dw 0xF273 ; .dw 0xE922 ; .dw 0x4819 ; .dw 0xE923 ; .dw 0x629F ; .dw 0xE924 ; .dw 0x3177 ; .dw 0xE925 ; .dw 0x7C9B ; .dw 0xE926 ; .dw 0x2BD ; .dw 0xE927 ; .dw 0xDC33 ; .dw 0xE928 ; .dw 0x783B ; .dw 0xE929 ; .dw 0xB20B ; .dw 0xE92A ; .dw 0xE895 ; .dw 0xE92B ; .dw 0x4B5D ; .dw 0xE92C ; .dw 0x12B7 ; .dw 0xE92D ; .dw 0xC9E7 ; .dw 0xE92E ; .dw 0x7335 ; .dw 0xE92F ; .dw 0x4AB1 ; .dw 0xE930 ; .dw 0x7251 ; .dw 0xE931 ; .dw 0x11E1 ; .dw 0xE932 ; .dw 0xFCE3 ; .dw 0xE933 ; .dw 0x3557 ; .dw 0xE934 ; .dw 0xF837 ; .dw 0xE935 ; .dw 0x8F27 ; .dw 0xE936 ; .dw 0xDA2F ; .dw 0xE937 ; .dw 0x5CC3 ; .dw 0xE938 ; .dw 0xE4BD ; .dw 0xE939 ; .dw 0xB6DF ; .dw 0xE93A ; .dw 0x7509 ; .dw 0xE93B ; .dw 0xE1EB ; .dw 0xE93C ; .dw 0xE439 ; .dw 0xE93D ; .dw 0x3621 ; .dw 0xE93E ; .dw 0x15D ; .dw 0xE93F ; .dw 0xEA05 ; .dw 0xE940 ; .dw 0x9151 ; .dw 0xE941 ; .dw 0x4169 ; .dw 0xE942 ; .dw 0xE325 ; .dw 0xE943 ; .dw 0x66B5 ; .dw 0xE944 ; .dw 0xC4DD ; .dw 0xE945 ; .dw 0x6395 ; .dw 0xE946 ; .dw 0x5E09 ; .dw 0xE947 ; .dw 0x29CD ; .dw 0xE948 ; .dw 0xB35 ; .dw 0xE949 ; .dw 0x4459 ; .dw 0xE94A ; .dw 0xA671 ; .dw 0xE94B ; .dw 0x7C83 ; .dw 0xE94C ; .dw 0x1715 ; .dw 0xE94D ; .dw 0x5E37 ; .dw 0xE94E ; .dw 0xEC19 ; .dw 0xE94F ; .dw 0xF227 ; .dw 0xE950 ; .dw 0x89E9 ; .dw 0xE951 ; .dw 0x1BFD ; .dw 0xE952 ; .dw 0x7637 ; .dw 0xE953 ; .dw 0xAE5B ; .dw 0xE954 ; .dw 0xE9AF ; .dw 0xE955 ; .dw 0x55B5 ; .dw 0xE956 ; .dw 0x6905 ; .dw 0xE957 ; .dw 0xD6D3 ; .dw 0xE958 ; .dw 0x1C47 ; .dw 0xE959 ; .dw 0xA523 ; .dw 0xE95A ; .dw 0x4CE1 ; .dw 0xE95B ; .dw 0x687F ; .dw 0xE95C ; .dw 0x404F ; .dw 0xE95D ; .dw 0x89B5 ; .dw 0xE95E ; .dw 0xEEE1 ; .dw 0xE95F ; .dw 0x2851 ; .dw 0xE960 ; .dw 0x3B7D ; .dw 0xE961 ; .dw 0xD409 ; .dw 0xE962 ; .dw 0xB2ED ; .dw 0xE963 ; .dw 0xE767 ; .dw 0xE964 ; .dw 0xD673 ; .dw 0xE965 ; .dw 0x50D5 ; .dw 0xE966 ; .dw 0xEF57 ; .dw 0xE967 ; .dw 0xD2D1 ; .dw 0xE968 ; .dw 0xBE17 ; .dw 0xE969 ; .dw 0x2B6B ; .dw 0xE96A ; .dw 0x69F1 ; .dw 0xE96B ; .dw 0x6C1 ; .dw 0xE96C ; .dw 0x426F ; .dw 0xE96D ; .dw 0xFFA9 ; .dw 0xE96E ; .dw 0x8EA9 ; .dw 0xE96F ; .dw 0x1D41 ; .dw 0xE970 ; .dw 0x2AF5 ; .dw 0xE971 ; .dw 0x1379 ; .dw 0xE972 ; .dw 0x779D ; .dw 0xE973 ; .dw 0xF075 ; .dw 0xE974 ; .dw 0x7871 ; .dw 0xE975 ; .dw 0xAFC1 ; .dw 0xE976 ; .dw 0x5EB3 ; .dw 0xE977 ; .dw 0x4845 ; .dw 0xE978 ; .dw 0x6C4F ; .dw 0xE979 ; .dw 0x10E1 ; .dw 0xE97A ; .dw 0x90B7 ; .dw 0xE97B ; .dw 0xABA3 ; .dw 0xE97C ; .dw 0xAD7B ; .dw 0xE97D ; .dw 0xE6A3 ; .dw 0xE97E ; .dw 0x79E9 ; .dw 0xE97F ; .dw 0xD37 ; .dw 0xE980 ; .dw 0xE2B5 ; .dw 0xE981 ; .dw 0xDBBF ; .dw 0xE982 ; .dw 0xE41D ; .dw 0xE983 ; .dw 0x8BA3 ; .dw 0xE984 ; .dw 0x9A6B ; .dw 0xE985 ; .dw 0x1CCB ; .dw 0xE986 ; .dw 0xFE53 ; .dw 0xE987 ; .dw 0xFD2D ; .dw 0xE988 ; .dw 0xD811 ; .dw 0xE989 ; .dw 0x56B1 ; .dw 0xE98A ; .dw 0x45C9 ; .dw 0xE98B ; .dw 0x7F05 ; .dw 0xE98C ; .dw 0x1EF7 ; .dw 0xE98D ; .dw 0x24AF ; .dw 0xE98E ; .dw 0xE895 ; .dw 0xE98F ; .dw 0xBFF1 ; .dw 0xE990 ; .dw 0x52A5 ; .dw 0xE991 ; .dw 0x65C7 ; .dw 0xE992 ; .dw 0xB9C5 ; .dw 0xE993 ; .dw 0x3E8F ; .dw 0xE994 ; .dw 0x44AB ; .dw 0xE995 ; .dw 0x71BD ; .dw 0xE996 ; .dw 0x4EEB ; .dw 0xE997 ; .dw 0x3307 ; .dw 0xE998 ; .dw 0x4807 ; .dw 0xE999 ; .dw 0xA58B ; .dw 0xE99A ; .dw 0x5F3B ; .dw 0xE99B ; .dw 0x5C45 ; .dw 0xE99C ; .dw 0xA1EB ; .dw 0xE99D ; .dw 0x3F5B ; .dw 0xE99E ; .dw 0xFC25 ; .dw 0xE99F ; .dw 0x68AD ; .dw 0xE9A0 ; .dw 0x3029 ; .dw 0xE9A1 ; .dw 0x1FD ; .dw 0xE9A2 ; .dw 0xBB69 ; .dw 0xE9A3 ; .dw 0x3259 ; .dw 0xE9A4 ; .dw 0x1CF5 ; .dw 0xE9A5 ; .dw 0x97E5 ; .dw 0xE9A6 ; .dw 0x6AB1 ; .dw 0xE9A7 ; .dw 0x86D3 ; .dw 0xE9A8 ; .dw 0xF853 ; .dw 0xE9A9 ; .dw 0x2D9B ; .dw 0xE9AA ; .dw 0x64A5 ; .dw 0xE9AB ; .dw 0xB23F ; .dw 0xE9AC ; .dw 0xEDD ; .dw 0xE9AD ; .dw 0x3BB5 ; .dw 0xE9AE ; .dw 0x1F8F ; .dw 0xE9AF ; .dw 0x8627 ; .dw 0xE9B0 ; .dw 0x5627 ; .dw 0xE9B1 ; .dw 0xF853 ; .dw 0xE9B2 ; .dw 0xD5F ; .dw 0xE9B3 ; .dw 0x139F ; .dw 0xE9B4 ; .dw 0xC691 ; .dw 0xE9B5 ; .dw 0x6815 ; .dw 0xE9B6 ; .dw 0x655B ; .dw 0xE9B7 ; .dw 0xD10B ; .dw 0xE9B8 ; .dw 0x7A9D ; .dw 0xE9B9 ; .dw 0x868F ; .dw 0xE9BA ; .dw 0xEF1F ; .dw 0xE9BB ; .dw 0x6355 ; .dw 0xE9BC ; .dw 0x6BD3 ; .dw 0xE9BD ; .dw 0x7E4B ; .dw 0xE9BE ; .dw 0x6747 ; .dw 0xE9BF ; .dw 0xC29D ; .dw 0xE9C0 ; .dw 0x2507 ; .dw 0xE9C1 ; .dw 0x6833 ; .dw 0xE9C2 ; .dw 0x957F ; .dw 0xE9C3 ; .dw 0xF27B ; .dw 0xE9C4 ; .dw 0x4241 ; .dw 0xE9C5 ; .dw 0x8A97 ; .dw 0xE9C6 ; .dw 0xAC1D ; .dw 0xE9C7 ; .dw 0x5B1 ; .dw 0xE9C8 ; .dw 0x160B ; .dw 0xE9C9 ; .dw 0x8F99 ; .dw 0xE9CA ; .dw 0x939 ; .dw 0xE9CB ; .dw 0xA561 ; .dw 0xE9CC ; .dw 0x4C51 ; .dw 0xE9CD ; .dw 0xAB2D ; .dw 0xE9CE ; .dw 0xF143 ; .dw 0xE9CF ; .dw 0xD3CF ; .dw 0xE9D0 ; .dw 0xE2AD ; .dw 0xE9D1 ; .dw 0x288F ; .dw 0xE9D2 ; .dw 0x5B1D ; .dw 0xE9D3 ; .dw 0x228F ; .dw 0xE9D4 ; .dw 0x4E4D ; .dw 0xE9D5 ; .dw 0x573B ; .dw 0xE9D6 ; .dw 0x65B1 ; .dw 0xE9D7 ; .dw 0x143F ; .dw 0xE9D8 ; .dw 0x2743 ; .dw 0xE9D9 ; .dw 0x4F61 ; .dw 0xE9DA ; .dw 0x8F0F ; .dw 0xE9DB ; .dw 0xE1C5 ; .dw 0xE9DC ; .dw 0x315D ; .dw 0xE9DD ; .dw 0x85E7 ; .dw 0xE9DE ; .dw 0x44FB ; .dw 0xE9DF ; .dw 0x5AFB ; .dw 0xE9E0 ; .dw 0x1A81 ; .dw 0xE9E1 ; .dw 0xA7D3 ; .dw 0xE9E2 ; .dw 0xE70F ; .dw 0xE9E3 ; .dw 0x1AF7 ; .dw 0xE9E4 ; .dw 0xC67D ; .dw 0xE9E5 ; .dw 0xB54D ; .dw 0xE9E6 ; .dw 0xD24B ; .dw 0xE9E7 ; .dw 0xC7B7 ; .dw 0xE9E8 ; .dw 0x806B ; .dw 0xE9E9 ; .dw 0xD419 ; .dw 0xE9EA ; .dw 0x8E35 ; .dw 0xE9EB ; .dw 0x955B ; .dw 0xE9EC ; .dw 0xE981 ; .dw 0xE9ED ; .dw 0xD187 ; .dw 0xE9EE ; .dw 0xB365 ; .dw 0xE9EF ; .dw 0xC4DF ; .dw 0xE9F0 ; .dw 0xFD67 ; .dw 0xE9F1 ; .dw 0xCBEB ; .dw 0xE9F2 ; .dw 0xA3AD ; .dw 0xE9F3 ; .dw 0x5653 ; .dw 0xE9F4 ; .dw 0x415 ; .dw 0xE9F5 ; .dw 0xFB9F ; .dw 0xE9F6 ; .dw 0xABA3 ; .dw 0xE9F7 ; .dw 0xA695 ; .dw 0xE9F8 ; .dw 0xC929 ; .dw 0xE9F9 ; .dw 0x136F ; .dw 0xE9FA ; .dw 0xA5BF ; .dw 0xE9FB ; .dw 0x3083 ; .dw 0xE9FC ; .dw 0xF0BF ; .dw 0xE9FD ; .dw 0x309B ; .dw 0xE9FE ; .dw 0xB6F5 ; .dw 0xE9FF ; .dw 0x29B7 ; .dw 0xEA00 ; .dw 0xC1C5 ; .dw 0xEA01 ; .dw 0xD249 ; .dw 0xEA02 ; .dw 0x3CCB ; .dw 0xEA03 ; .dw 0x32BF ; .dw 0xEA04 ; .dw 0x3DDB ; .dw 0xEA05 ; .dw 0xD07B ; .dw 0xEA06 ; .dw 0x84EB ; .dw 0xEA07 ; .dw 0xD2D7 ; .dw 0xEA08 ; .dw 0xDEA3 ; .dw 0xEA09 ; .dw 0xCA8F ; .dw 0xEA0A ; .dw 0x6645 ; .dw 0xEA0B ; .dw 0xF71B ; .dw 0xEA0C ; .dw 0xD09F ; .dw 0xEA0D ; .dw 0x533 ; .dw 0xEA0E ; .dw 0x53A3 ; .dw 0xEA0F ; .dw 0x2D41 ; .dw 0xEA10 ; .dw 0x383 ; .dw 0xEA11 ; .dw 0x2FD7 ; .dw 0xEA12 ; .dw 0xFFBF ; .dw 0xEA13 ; .dw 0xD1DB ; .dw 0xEA14 ; .dw 0xE815 ; .dw 0xEA15 ; .dw 0x9B1 ; .dw 0xEA16 ; .dw 0x2ADB ; .dw 0xEA17 ; .dw 0xE9FB ; .dw 0xEA18 ; .dw 0x337F ; .dw 0xEA19 ; .dw 0x5E29 ; .dw 0xEA1A ; .dw 0xB1DD ; .dw 0xEA1B ; .dw 0xE07F ; .dw 0xEA1C ; .dw 0x8025 ; .dw 0xEA1D ; .dw 0x50DB ; .dw 0xEA1E ; .dw 0x76E3 ; .dw 0xEA1F ; .dw 0xDEBF ; .dw 0xEA20 ; .dw 0x2407 ; .dw 0xEA21 ; .dw 0x7107 ; .dw 0xEA22 ; .dw 0x3B5F ; .dw 0xEA23 ; .dw 0xF8C1 ; .dw 0xEA24 ; .dw 0x148B ; .dw 0xEA25 ; .dw 0x8C8D ; .dw 0xEA26 ; .dw 0x3A9 ; .dw 0xEA27 ; .dw 0xE4FF ; .dw 0xEA28 ; .dw 0x2FE3 ; .dw 0xEA29 ; .dw 0xBA69 ; .dw 0xEA2A ; .dw 0x1C1D ; .dw 0xEA2B ; .dw 0x7791 ; .dw 0xEA2C ; .dw 0xC3D9 ; .dw 0xEA2D ; .dw 0x94A1 ; .dw 0xEA2E ; .dw 0x57AD ; .dw 0xEA2F ; .dw 0x98EB ; .dw 0xEA30 ; .dw 0xAA33 ; .dw 0xEA31 ; .dw 0x19C3 ; .dw 0xEA32 ; .dw 0xA003 ; .dw 0xEA33 ; .dw 0xF015 ; .dw 0xEA34 ; .dw 0xD27F ; .dw 0xEA35 ; .dw 0x2DE1 ; .dw 0xEA36 ; .dw 0x6F0B ; .dw 0xEA37 ; .dw 0xF863 ; .dw 0xEA38 ; .dw 0x9173 ; .dw 0xEA39 ; .dw 0x32FD ; .dw 0xEA3A ; .dw 0x4A19 ; .dw 0xEA3B ; .dw 0xBAAB ; .dw 0xEA3C ; .dw 0x8DC1 ; .dw 0xEA3D ; .dw 0xB113 ; .dw 0xEA3E ; .dw 0xD677 ; .dw 0xEA3F ; .dw 0xE203 ; .dw 0xEA40 ; .dw 0xA271 ; .dw 0xEA41 ; .dw 0x857B ; .dw 0xEA42 ; .dw 0x9F7F ; .dw 0xEA43 ; .dw 0x63EF ; .dw 0xEA44 ; .dw 0x8EBB ; .dw 0xEA45 ; .dw 0x91F7 ; .dw 0xEA46 ; .dw 0x2639 ; .dw 0xEA47 ; .dw 0x7421 ; .dw 0xEA48 ; .dw 0xCB59 ; .dw 0xEA49 ; .dw 0x6317 ; .dw 0xEA4A ; .dw 0x5269 ; .dw 0xEA4B ; .dw 0xFBAF ; .dw 0xEA4C ; .dw 0x5D63 ; .dw 0xEA4D ; .dw 0xC63F ; .dw 0xEA4E ; .dw 0xDD33 ; .dw 0xEA4F ; .dw 0x4BC7 ; .dw 0xEA50 ; .dw 0xFEA7 ; .dw 0xEA51 ; .dw 0xC71F ; .dw 0xEA52 ; .dw 0xCD29 ; .dw 0xEA53 ; .dw 0x43F1 ; .dw 0xEA54 ; .dw 0x7383 ; .dw 0xEA55 ; .dw 0xC9D ; .dw 0xEA56 ; .dw 0x9BE5 ; .dw 0xEA57 ; .dw 0xA3BB ; .dw 0xEA58 ; .dw 0x6637 ; .dw 0xEA59 ; .dw 0xD5F ; .dw 0xEA5A ; .dw 0x1D23 ; .dw 0xEA5B ; .dw 0xBFF7 ; .dw 0xEA5C ; .dw 0x9FC3 ; .dw 0xEA5D ; .dw 0x13B5 ; .dw 0xEA5E ; .dw 0xBF5D ; .dw 0xEA5F ; .dw 0x5375 ; .dw 0xEA60 ; .dw 0xF639 ; .dw 0xEA61 ; .dw 0x8919 ; .dw 0xEA62 ; .dw 0x3DD9 ; .dw 0xEA63 ; .dw 0xA337 ; .dw 0xEA64 ; .dw 0xC89D ; .dw 0xEA65 ; .dw 0x8125 ; .dw 0xEA66 ; .dw 0x5C47 ; .dw 0xEA67 ; .dw 0xAE2B ; .dw 0xEA68 ; .dw 0x6035 ; .dw 0xEA69 ; .dw 0xFC07 ; .dw 0xEA6A ; .dw 0xC3DD ; .dw 0xEA6B ; .dw 0xA063 ; .dw 0xEA6C ; .dw 0xF69 ; .dw 0xEA6D ; .dw 0xD881 ; .dw 0xEA6E ; .dw 0x99E7 ; .dw 0xEA6F ; .dw 0x41C9 ; .dw 0xEA70 ; .dw 0x660F ; .dw 0xEA71 ; .dw 0xED5B ; .dw 0xEA72 ; .dw 0xE7E3 ; .dw 0xEA73 ; .dw 0x9861 ; .dw 0xEA74 ; .dw 0x534F ; .dw 0xEA75 ; .dw 0x4259 ; .dw 0xEA76 ; .dw 0x6D17 ; .dw 0xEA77 ; .dw 0x75F3 ; .dw 0xEA78 ; .dw 0x8CFB ; .dw 0xEA79 ; .dw 0xE0BD ; .dw 0xEA7A ; .dw 0xF1AD ; .dw 0xEA7B ; .dw 0x2951 ; .dw 0xEA7C ; .dw 0x1459 ; .dw 0xEA7D ; .dw 0x3331 ; .dw 0xEA7E ; .dw 0xB349 ; .dw 0xEA7F ; .dw 0xB03 ; .dw 0xEA80 ; .dw 0x308B ; .dw 0xEA81 ; .dw 0x6D4F ; .dw 0xEA82 ; .dw 0x31D ; .dw 0xEA83 ; .dw 0x1D8B ; .dw 0xEA84 ; .dw 0xB661 ; .dw 0xEA85 ; .dw 0xF289 ; .dw 0xEA86 ; .dw 0xAD87 ; .dw 0xEA87 ; .dw 0x790F ; .dw 0xEA88 ; .dw 0xF5AB ; .dw 0xEA89 ; .dw 0x34AD ; .dw 0xEA8A ; .dw 0x4327 ; .dw 0xEA8B ; .dw 0xBA9D ; .dw 0xEA8C ; .dw 0x241B ; .dw 0xEA8D ; .dw 0x1D5 ; .dw 0xEA8E ; .dw 0xDB77 ; .dw 0xEA8F ; .dw 0x2EE1 ; .dw 0xEA90 ; .dw 0x9D99 ; .dw 0xEA91 ; .dw 0xB9E5 ; .dw 0xEA92 ; .dw 0x68DD ; .dw 0xEA93 ; .dw 0xF053 ; .dw 0xEA94 ; .dw 0xD215 ; .dw 0xEA95 ; .dw 0x6383 ; .dw 0xEA96 ; .dw 0x3651 ; .dw 0xEA97 ; .dw 0xB0FD ; .dw 0xEA98 ; .dw 0x38ED ; .dw 0xEA99 ; .dw 0x1885 ; .dw 0xEA9A ; .dw 0xA665 ; .dw 0xEA9B ; .dw 0x67A9 ; .dw 0xEA9C ; .dw 0x21B5 ; .dw 0xEA9D ; .dw 0xC1F9 ; .dw 0xEA9E ; .dw 0xCBE7 ; .dw 0xEA9F ; .dw 0x989F ; .dw 0xEAA0 ; .dw 0xBA99 ; .dw 0xEAA1 ; .dw 0x9B8D ; .dw 0xEAA2 ; .dw 0xF3FB ; .dw 0xEAA3 ; .dw 0x71D9 ; .dw 0xEAA4 ; .dw 0x2435 ; .dw 0xEAA5 ; .dw 0x7693 ; .dw 0xEAA6 ; .dw 0xB9A7 ; .dw 0xEAA7 ; .dw 0x72BB ; .dw 0xEAA8 ; .dw 0xEAE7 ; .dw 0xEAA9 ; .dw 0x3475 ; .dw 0xEAAA ; .dw 0xBAF9 ; .dw 0xEAAB ; .dw 0xD74F ; .dw 0xEAAC ; .dw 0xBDAB ; .dw 0xEAAD ; .dw 0x70A9 ; .dw 0xEAAE ; .dw 0x8793 ; .dw 0xEAAF ; .dw 0x7EFD ; .dw 0xEAB0 ; .dw 0xBA75 ; .dw 0xEAB1 ; .dw 0xD231 ; .dw 0xEAB2 ; .dw 0xE0CB ; .dw 0xEAB3 ; .dw 0x86B9 ; .dw 0xEAB4 ; .dw 0x2805 ; .dw 0xEAB5 ; .dw 0xFC89 ; .dw 0xEAB6 ; .dw 0xE343 ; .dw 0xEAB7 ; .dw 0x4EC7 ; .dw 0xEAB8 ; .dw 0xF53F ; .dw 0xEAB9 ; .dw 0x982B ; .dw 0xEABA ; .dw 0x31FB ; .dw 0xEABB ; .dw 0x23F1 ; .dw 0xEABC ; .dw 0xD607 ; .dw 0xEABD ; .dw 0x6A79 ; .dw 0xEABE ; .dw 0xBAEB ; .dw 0xEABF ; .dw 0x4437 ; .dw 0xEAC0 ; .dw 0x5593 ; .dw 0xEAC1 ; .dw 0xF541 ; .dw 0xEAC2 ; .dw 0x2D23 ; .dw 0xEAC3 ; .dw 0x7711 ; .dw 0xEAC4 ; .dw 0xB64B ; .dw 0xEAC5 ; .dw 0x95B3 ; .dw 0xEAC6 ; .dw 0xB859 ; .dw 0xEAC7 ; .dw 0xF11F ; .dw 0xEAC8 ; .dw 0xF71B ; .dw 0xEAC9 ; .dw 0x9AD1 ; .dw 0xEACA ; .dw 0x2DFF ; .dw 0xEACB ; .dw 0xBB69 ; .dw 0xEACC ; .dw 0xD649 ; .dw 0xEACD ; .dw 0x4B71 ; .dw 0xEACE ; .dw 0x1BEB ; .dw 0xEACF ; .dw 0x560D ; .dw 0xEAD0 ; .dw 0x29D7 ; .dw 0xEAD1 ; .dw 0x53AD ; .dw 0xEAD2 ; .dw 0xF85B ; .dw 0xEAD3 ; .dw 0xCE81 ; .dw 0xEAD4 ; .dw 0x654F ; .dw 0xEAD5 ; .dw 0x91DF ; .dw 0xEAD6 ; .dw 0xF79D ; .dw 0xEAD7 ; .dw 0x143 ; .dw 0xEAD8 ; .dw 0xA521 ; .dw 0xEAD9 ; .dw 0xBB1B ; .dw 0xEADA ; .dw 0xA31F ; .dw 0xEADB ; .dw 0x3F17 ; .dw 0xEADC ; .dw 0x177D ; .dw 0xEADD ; .dw 0xCF23 ; .dw 0xEADE ; .dw 0xCA05 ; .dw 0xEADF ; .dw 0xDBD ; .dw 0xEAE0 ; .dw 0x1AA7 ; .dw 0xEAE1 ; .dw 0xD3DF ; .dw 0xEAE2 ; .dw 0xE347 ; .dw 0xEAE3 ; .dw 0x3C25 ; .dw 0xEAE4 ; .dw 0xE8D3 ; .dw 0xEAE5 ; .dw 0xD059 ; .dw 0xEAE6 ; .dw 0x7949 ; .dw 0xEAE7 ; .dw 0x22D ; .dw 0xEAE8 ; .dw 0x2975 ; .dw 0xEAE9 ; .dw 0x7F33 ; .dw 0xEAEA ; .dw 0xB6ED ; .dw 0xEAEB ; .dw 0x63D9 ; .dw 0xEAEC ; .dw 0x4025 ; .dw 0xEAED ; .dw 0xB09B ; .dw 0xEAEE ; .dw 0xAE2F ; .dw 0xEAEF ; .dw 0x9003 ; .dw 0xEAF0 ; .dw 0xB0EB ; .dw 0xEAF1 ; .dw 0xD3C7 ; .dw 0xEAF2 ; .dw 0x703D ; .dw 0xEAF3 ; .dw 0x729B ; .dw 0xEAF4 ; .dw 0x7221 ; .dw 0xEAF5 ; .dw 0x9FF1 ; .dw 0xEAF6 ; .dw 0x8F11 ; .dw 0xEAF7 ; .dw 0x325F ; .dw 0xEAF8 ; .dw 0x83C1 ; .dw 0xEAF9 ; .dw 0x54C7 ; .dw 0xEAFA ; .dw 0x2081 ; .dw 0xEAFB ; .dw 0xD20D ; .dw 0xEAFC ; .dw 0xA449 ; .dw 0xEAFD ; .dw 0x8A67 ; .dw 0xEAFE ; .dw 0xDAE1 ; .dw 0xEAFF ; .dw 0xAD1F ; .dw 0xEB00 ; .dw 0x7B07 ; .dw 0xEB01 ; .dw 0x8D3 ; .dw 0xEB02 ; .dw 0x6315 ; .dw 0xEB03 ; .dw 0x803 ; .dw 0xEB04 ; .dw 0xFFB ; .dw 0xEB05 ; .dw 0x9EF5 ; .dw 0xEB06 ; .dw 0x642B ; .dw 0xEB07 ; .dw 0x6BD5 ; .dw 0xEB08 ; .dw 0xE929 ; .dw 0xEB09 ; .dw 0x7107 ; .dw 0xEB0A ; .dw 0x8871 ; .dw 0xEB0B ; .dw 0x58F ; .dw 0xEB0C ; .dw 0xA56D ; .dw 0xEB0D ; .dw 0xB695 ; .dw 0xEB0E ; .dw 0xEC0F ; .dw 0xEB0F ; .dw 0xC0CD ; .dw 0xEB10 ; .dw 0x6CE3 ; .dw 0xEB11 ; .dw 0x5FF3 ; .dw 0xEB12 ; .dw 0x2123 ; .dw 0xEB13 ; .dw 0x55F9 ; .dw 0xEB14 ; .dw 0xEAB ; .dw 0xEB15 ; .dw 0x9B33 ; .dw 0xEB16 ; .dw 0x5D4D ; .dw 0xEB17 ; .dw 0x40D ; .dw 0xEB18 ; .dw 0x2451 ; .dw 0xEB19 ; .dw 0xB09F ; .dw 0xEB1A ; .dw 0xE8D1 ; .dw 0xEB1B ; .dw 0x2DC1 ; .dw 0xEB1C ; .dw 0x129B ; .dw 0xEB1D ; .dw 0x2EB5 ; .dw 0xEB1E ; .dw 0x6731 ; .dw 0xEB1F ; .dw 0x924D ; .dw 0xEB20 ; .dw 0x3FE3 ; .dw 0xEB21 ; .dw 0xDD91 ; .dw 0xEB22 ; .dw 0x113D ; .dw 0xEB23 ; .dw 0x599D ; .dw 0xEB24 ; .dw 0x57F7 ; .dw 0xEB25 ; .dw 0x71F7 ; .dw 0xEB26 ; .dw 0x78AD ; .dw 0xEB27 ; .dw 0xAC03 ; .dw 0xEB28 ; .dw 0xF563 ; .dw 0xEB29 ; .dw 0x77BF ; .dw 0xEB2A ; .dw 0xED3B ; .dw 0xEB2B ; .dw 0xD7D ; .dw 0xEB2C ; .dw 0x8855 ; .dw 0xEB2D ; .dw 0x6BD1 ; .dw 0xEB2E ; .dw 0x1B3D ; .dw 0xEB2F ; .dw 0x345D ; .dw 0xEB30 ; .dw 0xD2EF ; .dw 0xEB31 ; .dw 0x7D9D ; .dw 0xEB32 ; .dw 0xFBB9 ; .dw 0xEB33 ; .dw 0x938B ; .dw 0xEB34 ; .dw 0xD321 ; .dw 0xEB35 ; .dw 0xF011 ; .dw 0xEB36 ; .dw 0xAE01 ; .dw 0xEB37 ; .dw 0x503B ; .dw 0xEB38 ; .dw 0x7201 ; .dw 0xEB39 ; .dw 0x9215 ; .dw 0xEB3A ; .dw 0x52C1 ; .dw 0xEB3B ; .dw 0xDB23 ; .dw 0xEB3C ; .dw 0xD0A1 ; .dw 0xEB3D ; .dw 0x467B ; .dw 0xEB3E ; .dw 0x80A7 ; .dw 0xEB3F ; .dw 0xE539 ; .dw 0xEB40 ; .dw 0x8A6B ; .dw 0xEB41 ; .dw 0x1385 ; .dw 0xEB42 ; .dw 0x6A6F ; .dw 0xEB43 ; .dw 0xE7E1 ; .dw 0xEB44 ; .dw 0xC4F1 ; .dw 0xEB45 ; .dw 0xB1CF ; .dw 0xEB46 ; .dw 0x4E7F ; .dw 0xEB47 ; .dw 0xF8AD ; .dw 0xEB48 ; .dw 0x6553 ; .dw 0xEB49 ; .dw 0x12CB ; .dw 0xEB4A ; .dw 0x47FB ; .dw 0xEB4B ; .dw 0x2091 ; .dw 0xEB4C ; .dw 0x4307 ; .dw 0xEB4D ; .dw 0xD6C1 ; .dw 0xEB4E ; .dw 0x1967 ; .dw 0xEB4F ; .dw 0xEEA1 ; .dw 0xEB50 ; .dw 0xB03D ; .dw 0xEB51 ; .dw 0x2A37 ; .dw 0xEB52 ; .dw 0x8B3 ; .dw 0xEB53 ; .dw 0x7E3D ; .dw 0xEB54 ; .dw 0x2FAF ; .dw 0xEB55 ; .dw 0x2FD ; .dw 0xEB56 ; .dw 0x64DD ; .dw 0xEB57 ; .dw 0xA8D9 ; .dw 0xEB58 ; .dw 0xAFFF ; .dw 0xEB59 ; .dw 0x3495 ; .dw 0xEB5A ; .dw 0xCCFF ; .dw 0xEB5B ; .dw 0x9B25 ; .dw 0xEB5C ; .dw 0x248D ; .dw 0xEB5D ; .dw 0x542D ; .dw 0xEB5E ; .dw 0xD0F1 ; .dw 0xEB5F ; .dw 0x85D1 ; .dw 0xEB60 ; .dw 0xD3CD ; .dw 0xEB61 ; .dw 0xE423 ; .dw 0xEB62 ; .dw 0x35D ; .dw 0xEB63 ; .dw 0xA1BF ; .dw 0xEB64 ; .dw 0x331F ; .dw 0xEB65 ; .dw 0xBEED ; .dw 0xEB66 ; .dw 0x1551 ; .dw 0xEB67 ; .dw 0x3FBD ; .dw 0xEB68 ; .dw 0xA82B ; .dw 0xEB69 ; .dw 0x399B ; .dw 0xEB6A ; .dw 0x1361 ; .dw 0xEB6B ; .dw 0x1BBD ; .dw 0xEB6C ; .dw 0x7B9 ; .dw 0xEB6D ; .dw 0xF5D1 ; .dw 0xEB6E ; .dw 0x5C3D ; .dw 0xEB6F ; .dw 0xAB89 ; .dw 0xEB70 ; .dw 0x29FF ; .dw 0xEB71 ; .dw 0xDB33 ; .dw 0xEB72 ; .dw 0x68BF ; .dw 0xEB73 ; .dw 0xA105 ; .dw 0xEB74 ; .dw 0x6C87 ; .dw 0xEB75 ; .dw 0x3069 ; .dw 0xEB76 ; .dw 0xFD91 ; .dw 0xEB77 ; .dw 0x57D9 ; .dw 0xEB78 ; .dw 0x797D ; .dw 0xEB79 ; .dw 0x4B91 ; .dw 0xEB7A ; .dw 0xDE3B ; .dw 0xEB7B ; .dw 0x66B7 ; .dw 0xEB7C ; .dw 0x2C8F ; .dw 0xEB7D ; .dw 0xD239 ; .dw 0xEB7E ; .dw 0x99BF ; .dw 0xEB7F ; .dw 0xC07 ; .dw 0xEB80 ; .dw 0xED3B ; .dw 0xEB81 ; .dw 0xD7 ; .dw 0xEB82 ; .dw 0x88B3 ; .dw 0xEB83 ; .dw 0xAE29 ; .dw 0xEB84 ; .dw 0x56AD ; .dw 0xEB85 ; .dw 0xF1BF ; .dw 0xEB86 ; .dw 0x94D3 ; .dw 0xEB87 ; .dw 0x2727 ; .dw 0xEB88 ; .dw 0x851B ; .dw 0xEB89 ; .dw 0x5B9F ; .dw 0xEB8A ; .dw 0xE21F ; .dw 0xEB8B ; .dw 0x13EF ; .dw 0xEB8C ; .dw 0xE097 ; .dw 0xEB8D ; .dw 0xBF73 ; .dw 0xEB8E ; .dw 0xF16F ; .dw 0xEB8F ; .dw 0xDF07 ; .dw 0xEB90 ; .dw 0xBD65 ; .dw 0xEB91 ; .dw 0x7DFD ; .dw 0xEB92 ; .dw 0x548D ; .dw 0xEB93 ; .dw 0xBECD ; .dw 0xEB94 ; .dw 0xA9D7 ; .dw 0xEB95 ; .dw 0xCCC1 ; .dw 0xEB96 ; .dw 0x8BCD ; .dw 0xEB97 ; .dw 0x5F29 ; .dw 0xEB98 ; .dw 0xC1AB ; .dw 0xEB99 ; .dw 0x279 ; .dw 0xEB9A ; .dw 0x2525 ; .dw 0xEB9B ; .dw 0x6EC5 ; .dw 0xEB9C ; .dw 0xDED5 ; .dw 0xEB9D ; .dw 0x330D ; .dw 0xEB9E ; .dw 0xB4C3 ; .dw 0xEB9F ; .dw 0xC7C9 ; .dw 0xEBA0 ; .dw 0xFFE3 ; .dw 0xEBA1 ; .dw 0x9313 ; .dw 0xEBA2 ; .dw 0xBF25 ; .dw 0xEBA3 ; .dw 0x6C0F ; .dw 0xEBA4 ; .dw 0xBBCD ; .dw 0xEBA5 ; .dw 0x9AB9 ; .dw 0xEBA6 ; .dw 0x2CB7 ; .dw 0xEBA7 ; .dw 0xCDB ; .dw 0xEBA8 ; .dw 0x1B53 ; .dw 0xEBA9 ; .dw 0x6047 ; .dw 0xEBAA ; .dw 0x5EE3 ; .dw 0xEBAB ; .dw 0x5619 ; .dw 0xEBAC ; .dw 0xAFD3 ; .dw 0xEBAD ; .dw 0x2217 ; .dw 0xEBAE ; .dw 0x7EAF ; .dw 0xEBAF ; .dw 0xB50B ; .dw 0xEBB0 ; .dw 0x3F9D ; .dw 0xEBB1 ; .dw 0x7807 ; .dw 0xEBB2 ; .dw 0x1CCF ; .dw 0xEBB3 ; .dw 0xD28B ; .dw 0xEBB4 ; .dw 0xDFD3 ; .dw 0xEBB5 ; .dw 0x2477 ; .dw 0xEBB6 ; .dw 0xBB43 ; .dw 0xEBB7 ; .dw 0x78BB ; .dw 0xEBB8 ; .dw 0xD3B9 ; .dw 0xEBB9 ; .dw 0xFCBD ; .dw 0xEBBA ; .dw 0x586F ; .dw 0xEBBB ; .dw 0x1C45 ; .dw 0xEBBC ; .dw 0x993 ; .dw 0xEBBD ; .dw 0xE11D ; .dw 0xEBBE ; .dw 0x93A9 ; .dw 0xEBBF ; .dw 0xC109 ; .dw 0xEBC0 ; .dw 0x8CF7 ; .dw 0xEBC1 ; .dw 0x3C47 ; .dw 0xEBC2 ; .dw 0x8361 ; .dw 0xEBC3 ; .dw 0x725F ; .dw 0xEBC4 ; .dw 0xC6AF ; .dw 0xEBC5 ; .dw 0x249 ; .dw 0xEBC6 ; .dw 0xD4AB ; .dw 0xEBC7 ; .dw 0x6C7 ; .dw 0xEBC8 ; .dw 0xE201 ; .dw 0xEBC9 ; .dw 0xA703 ; .dw 0xEBCA ; .dw 0x4C5D ; .dw 0xEBCB ; .dw 0x6729 ; .dw 0xEBCC ; .dw 0x2F9B ; .dw 0xEBCD ; .dw 0x42D ; .dw 0xEBCE ; .dw 0x41A9 ; .dw 0xEBCF ; .dw 0x1183 ; .dw 0xEBD0 ; .dw 0xDDD9 ; .dw 0xEBD1 ; .dw 0xA6C1 ; .dw 0xEBD2 ; .dw 0x2A31 ; .dw 0xEBD3 ; .dw 0xF29 ; .dw 0xEBD4 ; .dw 0xDEA7 ; .dw 0xEBD5 ; .dw 0x7BFB ; .dw 0xEBD6 ; .dw 0xCFA1 ; .dw 0xEBD7 ; .dw 0x167D ; .dw 0xEBD8 ; .dw 0x52D5 ; .dw 0xEBD9 ; .dw 0x55CB ; .dw 0xEBDA ; .dw 0x46C5 ; .dw 0xEBDB ; .dw 0x1021 ; .dw 0xEBDC ; .dw 0x52F3 ; .dw 0xEBDD ; .dw 0x3ED7 ; .dw 0xEBDE ; .dw 0x4025 ; .dw 0xEBDF ; .dw 0xB7B5 ; .dw 0xEBE0 ; .dw 0x6DA7 ; .dw 0xEBE1 ; .dw 0x15E3 ; .dw 0xEBE2 ; .dw 0xCA17 ; .dw 0xEBE3 ; .dw 0x9009 ; .dw 0xEBE4 ; .dw 0xB381 ; .dw 0xEBE5 ; .dw 0x68DD ; .dw 0xEBE6 ; .dw 0x1C5F ; .dw 0xEBE7 ; .dw 0xE2DB ; .dw 0xEBE8 ; .dw 0xA857 ; .dw 0xEBE9 ; .dw 0x743 ; .dw 0xEBEA ; .dw 0x853D ; .dw 0xEBEB ; .dw 0x40F ; .dw 0xEBEC ; .dw 0xF221 ; .dw 0xEBED ; .dw 0x4425 ; .dw 0xEBEE ; .dw 0x1011 ; .dw 0xEBEF ; .dw 0x905F ; .dw 0xEBF0 ; .dw 0x1D49 ; .dw 0xEBF1 ; .dw 0x5F9B ; .dw 0xEBF2 ; .dw 0xFD67 ; .dw 0xEBF3 ; .dw 0xDF9B ; .dw 0xEBF4 ; .dw 0x4E83 ; .dw 0xEBF5 ; .dw 0xFBD ; .dw 0xEBF6 ; .dw 0xA497 ; .dw 0xEBF7 ; .dw 0x6261 ; .dw 0xEBF8 ; .dw 0x3A31 ; .dw 0xEBF9 ; .dw 0xA117 ; .dw 0xEBFA ; .dw 0xD6DB ; .dw 0xEBFB ; .dw 0x234D ; .dw 0xEBFC ; .dw 0x392B ; .dw 0xEBFD ; .dw 0xA6A9 ; .dw 0xEBFE ; .dw 0x5BE5 ; .dw 0xEBFF ; .dw 0x23BD ; .dw 0xEC00 ; .dw 0xD323 ; .dw 0xEC01 ; .dw 0xB157 ; .dw 0xEC02 ; .dw 0x9FF7 ; .dw 0xEC03 ; .dw 0xCBFF ; .dw 0xEC04 ; .dw 0x9675 ; .dw 0xEC05 ; .dw 0x6E9 ; .dw 0xEC06 ; .dw 0x2B83 ; .dw 0xEC07 ; .dw 0x2709 ; .dw 0xEC08 ; .dw 0x9585 ; .dw 0xEC09 ; .dw 0xD077 ; .dw 0xEC0A ; .dw 0xFC33 ; .dw 0xEC0B ; .dw 0x21BD ; .dw 0xEC0C ; .dw 0x6195 ; .dw 0xEC0D ; .dw 0xB86F ; .dw 0xEC0E ; .dw 0x5795 ; .dw 0xEC0F ; .dw 0x8591 ; .dw 0xEC10 ; .dw 0xDB1B ; .dw 0xEC11 ; .dw 0x7005 ; .dw 0xEC12 ; .dw 0x2F1F ; .dw 0xEC13 ; .dw 0xE6D1 ; .dw 0xEC14 ; .dw 0xAF9B ; .dw 0xEC15 ; .dw 0x142D ; .dw 0xEC16 ; .dw 0xADD5 ; .dw 0xEC17 ; .dw 0x3E55 ; .dw 0xEC18 ; .dw 0xDCFB ; .dw 0xEC19 ; .dw 0xEA0F ; .dw 0xEC1A ; .dw 0x75F ; .dw 0xEC1B ; .dw 0x66B9 ; .dw 0xEC1C ; .dw 0x1267 ; .dw 0xEC1D ; .dw 0x6B05 ; .dw 0xEC1E ; .dw 0x2099 ; .dw 0xEC1F ; .dw 0x3513 ; .dw 0xEC20 ; .dw 0x4699 ; .dw 0xEC21 ; .dw 0x1813 ; .dw 0xEC22 ; .dw 0x29B3 ; .dw 0xEC23 ; .dw 0x652F ; .dw 0xEC24 ; .dw 0x5BB9 ; .dw 0xEC25 ; .dw 0xCD9 ; .dw 0xEC26 ; .dw 0xC1C7 ; .dw 0xEC27 ; .dw 0x1141 ; .dw 0xEC28 ; .dw 0x28BB ; .dw 0xEC29 ; .dw 0xCA0D ; .dw 0xEC2A ; .dw 0xBBF1 ; .dw 0xEC2B ; .dw 0xED21 ; .dw 0xEC2C ; .dw 0xC027 ; .dw 0xEC2D ; .dw 0x2F7B ; .dw 0xEC2E ; .dw 0x1DE5 ; .dw 0xEC2F ; .dw 0xFD07 ; .dw 0xEC30 ; .dw 0x4C81 ; .dw 0xEC31 ; .dw 0x1D6F ; .dw 0xEC32 ; .dw 0x7009 ; .dw 0xEC33 ; .dw 0xFFB9 ; .dw 0xEC34 ; .dw 0x5A19 ; .dw 0xEC35 ; .dw 0xB5BB ; .dw 0xEC36 ; .dw 0xF70D ; .dw 0xEC37 ; .dw 0x4449 ; .dw 0xEC38 ; .dw 0xE667 ; .dw 0xEC39 ; .dw 0xB423 ; .dw 0xEC3A ; .dw 0xEF01 ; .dw 0xEC3B ; .dw 0x2353 ; .dw 0xEC3C ; .dw 0xCD9 ; .dw 0xEC3D ; .dw 0xD65D ; .dw 0xEC3E ; .dw 0x5FF1 ; .dw 0xEC3F ; .dw 0xD3A7 ; .dw 0xEC40 ; .dw 0xA93B ; .dw 0xEC41 ; .dw 0xCB87 ; .dw 0xEC42 ; .dw 0xA3F7 ; .dw 0xEC43 ; .dw 0xD28B ; .dw 0xEC44 ; .dw 0xC781 ; .dw 0xEC45 ; .dw 0xA31F ; .dw 0xEC46 ; .dw 0x36DD ; .dw 0xEC47 ; .dw 0x976F ; .dw 0xEC48 ; .dw 0x3927 ; .dw 0xEC49 ; .dw 0x3379 ; .dw 0xEC4A ; .dw 0xE725 ; .dw 0xEC4B ; .dw 0xCB2D ; .dw 0xEC4C ; .dw 0x2805 ; .dw 0xEC4D ; .dw 0x6FB9 ; .dw 0xEC4E ; .dw 0xB1 ; .dw 0xEC4F ; .dw 0xBAB1 ; .dw 0xEC50 ; .dw 0xFEAB ; .dw 0xEC51 ; .dw 0x2549 ; .dw 0xEC52 ; .dw 0x88D5 ; .dw 0xEC53 ; .dw 0x3D43 ; .dw 0xEC54 ; .dw 0x7E33 ; .dw 0xEC55 ; .dw 0x18D5 ; .dw 0xEC56 ; .dw 0x23EB ; .dw 0xEC57 ; .dw 0xC62F ; .dw 0xEC58 ; .dw 0x59A1 ; .dw 0xEC59 ; .dw 0xFAC1 ; .dw 0xEC5A ; .dw 0xBC71 ; .dw 0xEC5B ; .dw 0xDA0D ; .dw 0xEC5C ; .dw 0x2EB1 ; .dw 0xEC5D ; .dw 0x2B1D ; .dw 0xEC5E ; .dw 0x839D ; .dw 0xEC5F ; .dw 0x9F67 ; .dw 0xEC60 ; .dw 0x3437 ; .dw 0xEC61 ; .dw 0xC523 ; .dw 0xEC62 ; .dw 0x6377 ; .dw 0xEC63 ; .dw 0xC301 ; .dw 0xEC64 ; .dw 0x75F9 ; .dw 0xEC65 ; .dw 0xEA2B ; .dw 0xEC66 ; .dw 0x7A71 ; .dw 0xEC67 ; .dw 0x6789 ; .dw 0xEC68 ; .dw 0xF5F9 ; .dw 0xEC69 ; .dw 0xC429 ; .dw 0xEC6A ; .dw 0xB87F ; .dw 0xEC6B ; .dw 0x58CF ; .dw 0xEC6C ; .dw 0x8B61 ; .dw 0xEC6D ; .dw 0x3799 ; .dw 0xEC6E ; .dw 0x35AB ; .dw 0xEC6F ; .dw 0x3A81 ; .dw 0xEC70 ; .dw 0xD6C7 ; .dw 0xEC71 ; .dw 0xBD03 ; .dw 0xEC72 ; .dw 0x5A35 ; .dw 0xEC73 ; .dw 0xEA61 ; .dw 0xEC74 ; .dw 0x2415 ; .dw 0xEC75 ; .dw 0x59EF ; .dw 0xEC76 ; .dw 0x7023 ; .dw 0xEC77 ; .dw 0xCDF7 ; .dw 0xEC78 ; .dw 0x91D9 ; .dw 0xEC79 ; .dw 0x315D ; .dw 0xEC7A ; .dw 0xB661 ; .dw 0xEC7B ; .dw 0x43D3 ; .dw 0xEC7C ; .dw 0x561D ; .dw 0xEC7D ; .dw 0xA3B7 ; .dw 0xEC7E ; .dw 0x8D4F ; .dw 0xEC7F ; .dw 0xF043 ; .dw 0xEC80 ; .dw 0x78C1 ; .dw 0xEC81 ; .dw 0x7657 ; .dw 0xEC82 ; .dw 0xD4E1 ; .dw 0xEC83 ; .dw 0x1D81 ; .dw 0xEC84 ; .dw 0xDB51 ; .dw 0xEC85 ; .dw 0xFA6F ; .dw 0xEC86 ; .dw 0x1437 ; .dw 0xEC87 ; .dw 0xE779 ; .dw 0xEC88 ; .dw 0xE665 ; .dw 0xEC89 ; .dw 0xAB8B ; .dw 0xEC8A ; .dw 0x82AF ; .dw 0xEC8B ; .dw 0x6AF9 ; .dw 0xEC8C ; .dw 0xB46B ; .dw 0xEC8D ; .dw 0x3D89 ; .dw 0xEC8E ; .dw 0x8A81 ; .dw 0xEC8F ; .dw 0xB067 ; .dw 0xEC90 ; .dw 0x1207 ; .dw 0xEC91 ; .dw 0x920D ; .dw 0xEC92 ; .dw 0xDCD5 ; .dw 0xEC93 ; .dw 0x8A01 ; .dw 0xEC94 ; .dw 0x2BF3 ; .dw 0xEC95 ; .dw 0x8D77 ; .dw 0xEC96 ; .dw 0xAF63 ; .dw 0xEC97 ; .dw 0x1D8F ; .dw 0xEC98 ; .dw 0x4243 ; .dw 0xEC99 ; .dw 0x4363 ; .dw 0xEC9A ; .dw 0x3B7F ; .dw 0xEC9B ; .dw 0x519B ; .dw 0xEC9C ; .dw 0x394F ; .dw 0xEC9D ; .dw 0x729B ; .dw 0xEC9E ; .dw 0x16B5 ; .dw 0xEC9F ; .dw 0xD62B ; .dw 0xECA0 ; .dw 0x6005 ; .dw 0xECA1 ; .dw 0xC893 ; .dw 0xECA2 ; .dw 0x7CE7 ; .dw 0xECA3 ; .dw 0xFD ; .dw 0xECA4 ; .dw 0x43BD ; .dw 0xECA5 ; .dw 0xE457 ; .dw 0xECA6 ; .dw 0x23DD ; .dw 0xECA7 ; .dw 0x3533 ; .dw 0xECA8 ; .dw 0xE997 ; .dw 0xECA9 ; .dw 0x9113 ; .dw 0xECAA ; .dw 0xB065 ; .dw 0xECAB ; .dw 0xE99 ; .dw 0xECAC ; .dw 0x4551 ; .dw 0xECAD ; .dw 0x2FFD ; .dw 0xECAE ; .dw 0x64E1 ; .dw 0xECAF ; .dw 0x851 ; .dw 0xECB0 ; .dw 0x459B ; .dw 0xECB1 ; .dw 0xC9D5 ; .dw 0xECB2 ; .dw 0x2169 ; .dw 0xECB3 ; .dw 0xD715 ; .dw 0xECB4 ; .dw 0x4DF7 ; .dw 0xECB5 ; .dw 0xBFDB ; .dw 0xECB6 ; .dw 0x4D5B ; .dw 0xECB7 ; .dw 0x2EE7 ; .dw 0xECB8 ; .dw 0x760B ; .dw 0xECB9 ; .dw 0x9447 ; .dw 0xECBA ; .dw 0xC279 ; .dw 0xECBB ; .dw 0x2C4F ; .dw 0xECBC ; .dw 0x6675 ; .dw 0xECBD ; .dw 0xC23B ; .dw 0xECBE ; .dw 0x517F ; .dw 0xECBF ; .dw 0x1913 ; .dw 0xECC0 ; .dw 0x2B33 ; .dw 0xECC1 ; .dw 0x1D45 ; .dw 0xECC2 ; .dw 0xF835 ; .dw 0xECC3 ; .dw 0xC463 ; .dw 0xECC4 ; .dw 0xD369 ; .dw 0xECC5 ; .dw 0xB055 ; .dw 0xECC6 ; .dw 0x6115 ; .dw 0xECC7 ; .dw 0x26A7 ; .dw 0xECC8 ; .dw 0x36C1 ; .dw 0xECC9 ; .dw 0x942D ; .dw 0xECCA ; .dw 0xC453 ; .dw 0xECCB ; .dw 0x889F ; .dw 0xECCC ; .dw 0xB845 ; .dw 0xECCD ; .dw 0xB561 ; .dw 0xECCE ; .dw 0xC281 ; .dw 0xECCF ; .dw 0xE62F ; .dw 0xECD0 ; .dw 0x5EB3 ; .dw 0xECD1 ; .dw 0x1CF ; .dw 0xECD2 ; .dw 0x509F ; .dw 0xECD3 ; .dw 0xC48B ; .dw 0xECD4 ; .dw 0x1A57 ; .dw 0xECD5 ; .dw 0xF58F ; .dw 0xECD6 ; .dw 0x4DBD ; .dw 0xECD7 ; .dw 0x33F1 ; .dw 0xECD8 ; .dw 0x9061 ; .dw 0xECD9 ; .dw 0xFF75 ; .dw 0xECDA ; .dw 0xDA05 ; .dw 0xECDB ; .dw 0x34E5 ; .dw 0xECDC ; .dw 0x43C3 ; .dw 0xECDD ; .dw 0xB503 ; .dw 0xECDE ; .dw 0x75D ; .dw 0xECDF ; .dw 0x38E5 ; .dw 0xECE0 ; .dw 0x737F ; .dw 0xECE1 ; .dw 0x4DE1 ; .dw 0xECE2 ; .dw 0xFB7F ; .dw 0xECE3 ; .dw 0xF6A5 ; .dw 0xECE4 ; .dw 0x8687 ; .dw 0xECE5 ; .dw 0x5ED9 ; .dw 0xECE6 ; .dw 0x1B8B ; .dw 0xECE7 ; .dw 0x49C3 ; .dw 0xECE8 ; .dw 0x5D11 ; .dw 0xECE9 ; .dw 0x4C4B ; .dw 0xECEA ; .dw 0x5925 ; .dw 0xECEB ; .dw 0x55FD ; .dw 0xECEC ; .dw 0x5F77 ; .dw 0xECED ; .dw 0x6C29 ; .dw 0xECEE ; .dw 0x390B ; .dw 0xECEF ; .dw 0xA5F3 ; .dw 0xECF0 ; .dw 0xA27D ; .dw 0xECF1 ; .dw 0x4F69 ; .dw 0xECF2 ; .dw 0xAB29 ; .dw 0xECF3 ; .dw 0x7D53 ; .dw 0xECF4 ; .dw 0xF93F ; .dw 0xECF5 ; .dw 0x2B01 ; .dw 0xECF6 ; .dw 0x4C35 ; .dw 0xECF7 ; .dw 0x169B ; .dw 0xECF8 ; .dw 0x4C79 ; .dw 0xECF9 ; .dw 0xD85F ; .dw 0xECFA ; .dw 0x28CD ; .dw 0xECFB ; .dw 0x447 ; .dw 0xECFC ; .dw 0xF65 ; .dw 0xECFD ; .dw 0x6565 ; .dw 0xECFE ; .dw 0x99FF ; .dw 0xECFF ; .dw 0x6D95 ; .dw 0xED00 ; .dw 0x2A15 ; .dw 0xED01 ; .dw 0xABD3 ; .dw 0xED02 ; .dw 0x5373 ; .dw 0xED03 ; .dw 0x5EB1 ; .dw 0xED04 ; .dw 0x3145 ; .dw 0xED05 ; .dw 0xE853 ; .dw 0xED06 ; .dw 0x3AF3 ; .dw 0xED07 ; .dw 0xE477 ; .dw 0xED08 ; .dw 0x43BB ; .dw 0xED09 ; .dw 0xC8DF ; .dw 0xED0A ; .dw 0x218F ; .dw 0xED0B ; .dw 0x2BA1 ; .dw 0xED0C ; .dw 0x6515 ; .dw 0xED0D ; .dw 0xEAC1 ; .dw 0xED0E ; .dw 0xF631 ; .dw 0xED0F ; .dw 0x5B8B ; .dw 0xED10 ; .dw 0xAE2B ; .dw 0xED11 ; .dw 0x4011 ; .dw 0xED12 ; .dw 0x89B3 ; .dw 0xED13 ; .dw 0x645F ; .dw 0xED14 ; .dw 0x2AE1 ; .dw 0xED15 ; .dw 0x549F ; .dw 0xED16 ; .dw 0x7C77 ; .dw 0xED17 ; .dw 0x78D5 ; .dw 0xED18 ; .dw 0xBD7F ; .dw 0xED19 ; .dw 0xEA75 ; .dw 0xED1A ; .dw 0x6D83 ; .dw 0xED1B ; .dw 0x6B69 ; .dw 0xED1C ; .dw 0xDF8D ; .dw 0xED1D ; .dw 0xE5CF ; .dw 0xED1E ; .dw 0x317 ; .dw 0xED1F ; .dw 0xA713 ; .dw 0xED20 ; .dw 0x9825 ; .dw 0xED21 ; .dw 0x8F ; .dw 0xED22 ; .dw 0xE4C1 ; .dw 0xED23 ; .dw 0xFB79 ; .dw 0xED24 ; .dw 0x7FD5 ; .dw 0xED25 ; .dw 0x3D33 ; .dw 0xED26 ; .dw 0x3EFB ; .dw 0xED27 ; .dw 0xF4B5 ; .dw 0xED28 ; .dw 0x29EB ; .dw 0xED29 ; .dw 0x9155 ; .dw 0xED2A ; .dw 0xE83F ; .dw 0xED2B ; .dw 0xF67D ; .dw 0xED2C ; .dw 0xCB51 ; .dw 0xED2D ; .dw 0xBF9D ; .dw 0xED2E ; .dw 0xBFA5 ; .dw 0xED2F ; .dw 0xD2E9 ; .dw 0xED30 ; .dw 0x76EB ; .dw 0xED31 ; .dw 0xD939 ; .dw 0xED32 ; .dw 0x5CF1 ; .dw 0xED33 ; .dw 0x149F ; .dw 0xED34 ; .dw 0xC76B ; .dw 0xED35 ; .dw 0x5EDB ; .dw 0xED36 ; .dw 0xAA31 ; .dw 0xED37 ; .dw 0xB491 ; .dw 0xED38 ; .dw 0x4EA3 ; .dw 0xED39 ; .dw 0x7929 ; .dw 0xED3A ; .dw 0x7ED9 ; .dw 0xED3B ; .dw 0x733B ; .dw 0xED3C ; .dw 0xA269 ; .dw 0xED3D ; .dw 0x40B5 ; .dw 0xED3E ; .dw 0xD453 ; .dw 0xED3F ; .dw 0x8D4D ; .dw 0xED40 ; .dw 0x5EE3 ; .dw 0xED41 ; .dw 0x8D81 ; .dw 0xED42 ; .dw 0xAC19 ; .dw 0xED43 ; .dw 0x3EB ; .dw 0xED44 ; .dw 0xF667 ; .dw 0xED45 ; .dw 0x45E9 ; .dw 0xED46 ; .dw 0x3F53 ; .dw 0xED47 ; .dw 0x306B ; .dw 0xED48 ; .dw 0xA6D1 ; .dw 0xED49 ; .dw 0xA51F ; .dw 0xED4A ; .dw 0x8FE7 ; .dw 0xED4B ; .dw 0xDB7F ; .dw 0xED4C ; .dw 0x6C5B ; .dw 0xED4D ; .dw 0x7129 ; .dw 0xED4E ; .dw 0xF315 ; .dw 0xED4F ; .dw 0x8FFB ; .dw 0xED50 ; .dw 0x49F1 ; .dw 0xED51 ; .dw 0x9853 ; .dw 0xED52 ; .dw 0xAD8F ; .dw 0xED53 ; .dw 0x60FF ; .dw 0xED54 ; .dw 0xBF0F ; .dw 0xED55 ; .dw 0x2E27 ; .dw 0xED56 ; .dw 0x3913 ; .dw 0xED57 ; .dw 0xDBBF ; .dw 0xED58 ; .dw 0xC319 ; .dw 0xED59 ; .dw 0x3FE7 ; .dw 0xED5A ; .dw 0x4B7D ; .dw 0xED5B ; .dw 0x5CAB ; .dw 0xED5C ; .dw 0x1E2B ; .dw 0xED5D ; .dw 0x7885 ; .dw 0xED5E ; .dw 0x3761 ; .dw 0xED5F ; .dw 0x8033 ; .dw 0xED60 ; .dw 0x777B ; .dw 0xED61 ; .dw 0xC1B ; .dw 0xED62 ; .dw 0xBE2B ; .dw 0xED63 ; .dw 0xE6F9 ; .dw 0xED64 ; .dw 0xF12B ; .dw 0xED65 ; .dw 0xE2E3 ; .dw 0xED66 ; .dw 0xEBAB ; .dw 0xED67 ; .dw 0x58B ; .dw 0xED68 ; .dw 0xA99F ; .dw 0xED69 ; .dw 0x7BAD ; .dw 0xED6A ; .dw 0x1333 ; .dw 0xED6B ; .dw 0x3799 ; .dw 0xED6C ; .dw 0xFA61 ; .dw 0xED6D ; .dw 0x7DD7 ; .dw 0xED6E ; .dw 0x8631 ; .dw 0xED6F ; .dw 0xCEB1 ; .dw 0xED70 ; .dw 0xCC69 ; .dw 0xED71 ; .dw 0x72CB ; .dw 0xED72 ; .dw 0x1C41 ; .dw 0xED73 ; .dw 0x5475 ; .dw 0xED74 ; .dw 0xD9FD ; .dw 0xED75 ; .dw 0x9EEF ; .dw 0xED76 ; .dw 0x24CF ; .dw 0xED77 ; .dw 0xB84D ; .dw 0xED78 ; .dw 0x360D ; .dw 0xED79 ; .dw 0x7221 ; .dw 0xED7A ; .dw 0xDA1F ; .dw 0xED7B ; .dw 0xA0A9 ; .dw 0xED7C ; .dw 0xF103 ; .dw 0xED7D ; .dw 0x87AF ; .dw 0xED7E ; .dw 0xEDF7 ; .dw 0xED7F ; .dw 0x97B7 ; .dw 0xED80 ; .dw 0x331F ; .dw 0xED81 ; .dw 0xADCF ; .dw 0xED82 ; .dw 0x47A9 ; .dw 0xED83 ; .dw 0x4B91 ; .dw 0xED84 ; .dw 0xA44F ; .dw 0xED85 ; .dw 0xEC95 ; .dw 0xED86 ; .dw 0x8BB3 ; .dw 0xED87 ; .dw 0x9A03 ; .dw 0xED88 ; .dw 0x7985 ; .dw 0xED89 ; .dw 0x46F ; .dw 0xED8A ; .dw 0x84D7 ; .dw 0xED8B ; .dw 0x9FB9 ; .dw 0xED8C ; .dw 0xFF95 ; .dw 0xED8D ; .dw 0x5C17 ; .dw 0xED8E ; .dw 0x6A9 ; .dw 0xED8F ; .dw 0x82FD ; .dw 0xED90 ; .dw 0xFB83 ; .dw 0xED91 ; .dw 0xD613 ; .dw 0xED92 ; .dw 0x61B7 ; .dw 0xED93 ; .dw 0x31EB ; .dw 0xED94 ; .dw 0xB865 ; .dw 0xED95 ; .dw 0x85A5 ; .dw 0xED96 ; .dw 0x111 ; .dw 0xED97 ; .dw 0xCC2B ; .dw 0xED98 ; .dw 0x1AB1 ; .dw 0xED99 ; .dw 0xBB47 ; .dw 0xED9A ; .dw 0x496F ; .dw 0xED9B ; .dw 0xF027 ; .dw 0xED9C ; .dw 0x911F ; .dw 0xED9D ; .dw 0x60A1 ; .dw 0xED9E ; .dw 0x51BF ; .dw 0xED9F ; .dw 0xA3C7 ; .dw 0xEDA0 ; .dw 0x3AFD ; .dw 0xEDA1 ; .dw 0x1C09 ; .dw 0xEDA2 ; .dw 0x8D41 ; .dw 0xEDA3 ; .dw 0x10A3 ; .dw 0xEDA4 ; .dw 0x1C05 ; .dw 0xEDA5 ; .dw 0x336D ; .dw 0xEDA6 ; .dw 0xFF1D ; .dw 0xEDA7 ; .dw 0xCBC3 ; .dw 0xEDA8 ; .dw 0xB5B3 ; .dw 0xEDA9 ; .dw 0xA6D5 ; .dw 0xEDAA ; .dw 0xF7F ; .dw 0xEDAB ; .dw 0xE0D1 ; .dw 0xEDAC ; .dw 0xDE27 ; .dw 0xEDAD ; .dw 0x7A5B ; .dw 0xEDAE ; .dw 0x9A2D ; .dw 0xEDAF ; .dw 0x58CF ; .dw 0xEDB0 ; .dw 0x2C73 ; .dw 0xEDB1 ; .dw 0xA79B ; .dw 0xEDB2 ; .dw 0x4E9D ; .dw 0xEDB3 ; .dw 0x7457 ; .dw 0xEDB4 ; .dw 0xD275 ; .dw 0xEDB5 ; .dw 0xAEB9 ; .dw 0xEDB6 ; .dw 0xF98D ; .dw 0xEDB7 ; .dw 0x514B ; .dw 0xEDB8 ; .dw 0x3C33 ; .dw 0xEDB9 ; .dw 0x3EC9 ; .dw 0xEDBA ; .dw 0xD01D ; .dw 0xEDBB ; .dw 0x3413 ; .dw 0xEDBC ; .dw 0x4CB1 ; .dw 0xEDBD ; .dw 0xEDCF ; .dw 0xEDBE ; .dw 0x546B ; .dw 0xEDBF ; .dw 0x2C53 ; .dw 0xEDC0 ; .dw 0x9047 ; .dw 0xEDC1 ; .dw 0x783B ; .dw 0xEDC2 ; .dw 0xEBA3 ; .dw 0xEDC3 ; .dw 0x4D21 ; .dw 0xEDC4 ; .dw 0x3C7B ; .dw 0xEDC5 ; .dw 0x7FD9 ; .dw 0xEDC6 ; .dw 0xBD97 ; .dw 0xEDC7 ; .dw 0x30BD ; .dw 0xEDC8 ; .dw 0x5557 ; .dw 0xEDC9 ; .dw 0x424F ; .dw 0xEDCA ; .dw 0xF5DF ; .dw 0xEDCB ; .dw 0xFFCF ; .dw 0xEDCC ; .dw 0xD047 ; .dw 0xEDCD ; .dw 0x3F0F ; .dw 0xEDCE ; .dw 0xFE6F ; .dw 0xEDCF ; .dw 0xB415 ; .dw 0xEDD0 ; .dw 0xC65 ; .dw 0xEDD1 ; .dw 0x44D5 ; .dw 0xEDD2 ; .dw 0xCBA5 ; .dw 0xEDD3 ; .dw 0xCEA3 ; .dw 0xEDD4 ; .dw 0x785F ; .dw 0xEDD5 ; .dw 0xDE9B ; .dw 0xEDD6 ; .dw 0xD1F1 ; .dw 0xEDD7 ; .dw 0x399B ; .dw 0xEDD8 ; .dw 0xBDC5 ; .dw 0xEDD9 ; .dw 0x9815 ; .dw 0xEDDA ; .dw 0xBCDB ; .dw 0xEDDB ; .dw 0x8D5F ; .dw 0xEDDC ; .dw 0x49E9 ; .dw 0xEDDD ; .dw 0x11A7 ; .dw 0xEDDE ; .dw 0x7FAD ; .dw 0xEDDF ; .dw 0x714F ; .dw 0xEDE0 ; .dw 0x8C2D ; .dw 0xEDE1 ; .dw 0x5BD5 ; .dw 0xEDE2 ; .dw 0xD77F ; .dw 0xEDE3 ; .dw 0x4FF9 ; .dw 0xEDE4 ; .dw 0xC1E3 ; .dw 0xEDE5 ; .dw 0x924D ; .dw 0xEDE6 ; .dw 0xD6D1 ; .dw 0xEDE7 ; .dw 0x16E1 ; .dw 0xEDE8 ; .dw 0xA7A3 ; .dw 0xEDE9 ; .dw 0x2E4D ; .dw 0xEDEA ; .dw 0x92A7 ; .dw 0xEDEB ; .dw 0x39A3 ; .dw 0xEDEC ; .dw 0xE823 ; .dw 0xEDED ; .dw 0x8A5 ; .dw 0xEDEE ; .dw 0x891D ; .dw 0xEDEF ; .dw 0xB0BF ; .dw 0xEDF0 ; .dw 0xA089 ; .dw 0xEDF1 ; .dw 0x832D ; .dw 0xEDF2 ; .dw 0xD981 ; .dw 0xEDF3 ; .dw 0x2BC3 ; .dw 0xEDF4 ; .dw 0xD251 ; .dw 0xEDF5 ; .dw 0xD1BB ; .dw 0xEDF6 ; .dw 0xE5ED ; .dw 0xEDF7 ; .dw 0x2F0D ; .dw 0xEDF8 ; .dw 0x1A97 ; .dw 0xEDF9 ; .dw 0xDA9F ; .dw 0xEDFA ; .dw 0x7657 ; .dw 0xEDFB ; .dw 0x54F9 ; .dw 0xEDFC ; .dw 0x86F7 ; .dw 0xEDFD ; .dw 0xA697 ; .dw 0xEDFE ; .dw 0xF533 ; .dw 0xEDFF ; .dw 0x6AA5 ; .dw 0xEE00 ; .dw 0xDFDF ; .dw 0xEE01 ; .dw 0xD847 ; .dw 0xEE02 ; .dw 0xDD85 ; .dw 0xEE03 ; .dw 0xA01D ; .dw 0xEE04 ; .dw 0x406D ; .dw 0xEE05 ; .dw 0x2335 ; .dw 0xEE06 ; .dw 0xF27B ; .dw 0xEE07 ; .dw 0x841D ; .dw 0xEE08 ; .dw 0x53C7 ; .dw 0xEE09 ; .dw 0x3A3D ; .dw 0xEE0A ; .dw 0x5883 ; .dw 0xEE0B ; .dw 0x33F ; .dw 0xEE0C ; .dw 0xFED ; .dw 0xEE0D ; .dw 0x2D8D ; .dw 0xEE0E ; .dw 0x27E7 ; .dw 0xEE0F ; .dw 0x22BF ; .dw 0xEE10 ; .dw 0x4613 ; .dw 0xEE11 ; .dw 0xB015 ; .dw 0xEE12 ; .dw 0x90DF ; .dw 0xEE13 ; .dw 0xAEA7 ; .dw 0xEE14 ; .dw 0xE07F ; .dw 0xEE15 ; .dw 0x3C89 ; .dw 0xEE16 ; .dw 0x2931 ; .dw 0xEE17 ; .dw 0x938F ; .dw 0xEE18 ; .dw 0x25D9 ; .dw 0xEE19 ; .dw 0x91D5 ; .dw 0xEE1A ; .dw 0x7B41 ; .dw 0xEE1B ; .dw 0x1BD3 ; .dw 0xEE1C ; .dw 0xDA09 ; .dw 0xEE1D ; .dw 0x7F11 ; .dw 0xEE1E ; .dw 0x6EAD ; .dw 0xEE1F ; .dw 0xC849 ; .dw 0xEE20 ; .dw 0x948B ; .dw 0xEE21 ; .dw 0x7701 ; .dw 0xEE22 ; .dw 0xA265 ; .dw 0xEE23 ; .dw 0xFC7B ; .dw 0xEE24 ; .dw 0x2449 ; .dw 0xEE25 ; .dw 0xE305 ; .dw 0xEE26 ; .dw 0x5045 ; .dw 0xEE27 ; .dw 0x3661 ; .dw 0xEE28 ; .dw 0x58F3 ; .dw 0xEE29 ; .dw 0xAD93 ; .dw 0xEE2A ; .dw 0xD225 ; .dw 0xEE2B ; .dw 0x991 ; .dw 0xEE2C ; .dw 0x9D3 ; .dw 0xEE2D ; .dw 0xFC35 ; .dw 0xEE2E ; .dw 0x607D ; .dw 0xEE2F ; .dw 0x9603 ; .dw 0xEE30 ; .dw 0xB22F ; .dw 0xEE31 ; .dw 0x90FD ; .dw 0xEE32 ; .dw 0x226F ; .dw 0xEE33 ; .dw 0xB23D ; .dw 0xEE34 ; .dw 0x7B15 ; .dw 0xEE35 ; .dw 0xCB75 ; .dw 0xEE36 ; .dw 0x276D ; .dw 0xEE37 ; .dw 0x8111 ; .dw 0xEE38 ; .dw 0xAB9 ; .dw 0xEE39 ; .dw 0xC127 ; .dw 0xEE3A ; .dw 0x6249 ; .dw 0xEE3B ; .dw 0xAADB ; .dw 0xEE3C ; .dw 0xF151 ; .dw 0xEE3D ; .dw 0x6587 ; .dw 0xEE3E ; .dw 0x3DCB ; .dw 0xEE3F ; .dw 0xF229 ; .dw 0xEE40 ; .dw 0xB63 ; .dw 0xEE41 ; .dw 0x3973 ; .dw 0xEE42 ; .dw 0xE2D1 ; .dw 0xEE43 ; .dw 0x5C05 ; .dw 0xEE44 ; .dw 0xB1A5 ; .dw 0xEE45 ; .dw 0x7A29 ; .dw 0xEE46 ; .dw 0xC7E1 ; .dw 0xEE47 ; .dw 0xA39F ; .dw 0xEE48 ; .dw 0xE55 ; .dw 0xEE49 ; .dw 0x47BD ; .dw 0xEE4A ; .dw 0xA23F ; .dw 0xEE4B ; .dw 0x318B ; .dw 0xEE4C ; .dw 0x7007 ; .dw 0xEE4D ; .dw 0xBB11 ; .dw 0xEE4E ; .dw 0x508F ; .dw 0xEE4F ; .dw 0x4E7B ; .dw 0xEE50 ; .dw 0xF20F ; .dw 0xEE51 ; .dw 0x6353 ; .dw 0xEE52 ; .dw 0xD6E1 ; .dw 0xEE53 ; .dw 0xC975 ; .dw 0xEE54 ; .dw 0x5243 ; .dw 0xEE55 ; .dw 0x22EF ; .dw 0xEE56 ; .dw 0x453 ; .dw 0xEE57 ; .dw 0xC985 ; .dw 0xEE58 ; .dw 0x4C69 ; .dw 0xEE59 ; .dw 0xE403 ; .dw 0xEE5A ; .dw 0xDA1F ; .dw 0xEE5B ; .dw 0x301 ; .dw 0xEE5C ; .dw 0x52FF ; .dw 0xEE5D ; .dw 0x1C65 ; .dw 0xEE5E ; .dw 0x4C3F ; .dw 0xEE5F ; .dw 0x837 ; .dw 0xEE60 ; .dw 0xFD97 ; .dw 0xEE61 ; .dw 0x990D ; .dw 0xEE62 ; .dw 0x7377 ; .dw 0xEE63 ; .dw 0xEDA9 ; .dw 0xEE64 ; .dw 0x4B3 ; .dw 0xEE65 ; .dw 0x8913 ; .dw 0xEE66 ; .dw 0xC8FB ; .dw 0xEE67 ; .dw 0xF9C5 ; .dw 0xEE68 ; .dw 0x231D ; .dw 0xEE69 ; .dw 0x4029 ; .dw 0xEE6A ; .dw 0x837F ; .dw 0xEE6B ; .dw 0x981B ; .dw 0xEE6C ; .dw 0xB4B9 ; .dw 0xEE6D ; .dw 0xA88F ; .dw 0xEE6E ; .dw 0xADCF ; .dw 0xEE6F ; .dw 0x4819 ; .dw 0xEE70 ; .dw 0x6AE1 ; .dw 0xEE71 ; .dw 0xDC8B ; .dw 0xEE72 ; .dw 0xEE7 ; .dw 0xEE73 ; .dw 0xBF41 ; .dw 0xEE74 ; .dw 0xEE3D ; .dw 0xEE75 ; .dw 0xDF65 ; .dw 0xEE76 ; .dw 0x7B91 ; .dw 0xEE77 ; .dw 0xF6DB ; .dw 0xEE78 ; .dw 0xC619 ; .dw 0xEE79 ; .dw 0xEDDD ; .dw 0xEE7A ; .dw 0xA975 ; .dw 0xEE7B ; .dw 0x5D37 ; .dw 0xEE7C ; .dw 0x5D41 ; .dw 0xEE7D ; .dw 0x5E1D ; .dw 0xEE7E ; .dw 0x1BB5 ; .dw 0xEE7F ; .dw 0xE261 ; .dw 0xEE80 ; .dw 0x7C55 ; .dw 0xEE81 ; .dw 0x873F ; .dw 0xEE82 ; .dw 0x4107 ; .dw 0xEE83 ; .dw 0x1859 ; .dw 0xEE84 ; .dw 0x11A3 ; .dw 0xEE85 ; .dw 0xA833 ; .dw 0xEE86 ; .dw 0x5B47 ; .dw 0xEE87 ; .dw 0x1EC5 ; .dw 0xEE88 ; .dw 0x9E7F ; .dw 0xEE89 ; .dw 0x464B ; .dw 0xEE8A ; .dw 0x4895 ; .dw 0xEE8B ; .dw 0x9233 ; .dw 0xEE8C ; .dw 0x2219 ; .dw 0xEE8D ; .dw 0xFB1F ; .dw 0xEE8E ; .dw 0xC5E9 ; .dw 0xEE8F ; .dw 0x36CD ; .dw 0xEE90 ; .dw 0xD9D7 ; .dw 0xEE91 ; .dw 0x2A13 ; .dw 0xEE92 ; .dw 0x432F ; .dw 0xEE93 ; .dw 0x968F ; .dw 0xEE94 ; .dw 0xAF2F ; .dw 0xEE95 ; .dw 0x954B ; .dw 0xEE96 ; .dw 0xE0D7 ; .dw 0xEE97 ; .dw 0x4B01 ; .dw 0xEE98 ; .dw 0xAAF7 ; .dw 0xEE99 ; .dw 0x4A21 ; .dw 0xEE9A ; .dw 0xAEF9 ; .dw 0xEE9B ; .dw 0x2A6B ; .dw 0xEE9C ; .dw 0x4649 ; .dw 0xEE9D ; .dw 0xDD1F ; .dw 0xEE9E ; .dw 0xC5E1 ; .dw 0xEE9F ; .dw 0x1099 ; .dw 0xEEA0 ; .dw 0xF0CF ; .dw 0xEEA1 ; .dw 0x6D77 ; .dw 0xEEA2 ; .dw 0x5031 ; .dw 0xEEA3 ; .dw 0x7B03 ; .dw 0xEEA4 ; .dw 0xA4A3 ; .dw 0xEEA5 ; .dw 0x67FB ; .dw 0xEEA6 ; .dw 0x1E73 ; .dw 0xEEA7 ; .dw 0xB08D ; .dw 0xEEA8 ; .dw 0xDFA7 ; .dw 0xEEA9 ; .dw 0x818F ; .dw 0xEEAA ; .dw 0xDC33 ; .dw 0xEEAB ; .dw 0xACC1 ; .dw 0xEEAC ; .dw 0xDA55 ; .dw 0xEEAD ; .dw 0xE12F ; .dw 0xEEAE ; .dw 0x7E91 ; .dw 0xEEAF ; .dw 0x8685 ; .dw 0xEEB0 ; .dw 0x5421 ; .dw 0xEEB1 ; .dw 0xF15B ; .dw 0xEEB2 ; .dw 0x467 ; .dw 0xEEB3 ; .dw 0x8A51 ; .dw 0xEEB4 ; .dw 0xCD49 ; .dw 0xEEB5 ; .dw 0xD10F ; .dw 0xEEB6 ; .dw 0x1FD5 ; .dw 0xEEB7 ; .dw 0xBFE7 ; .dw 0xEEB8 ; .dw 0x8635 ; .dw 0xEEB9 ; .dw 0xDC43 ; .dw 0xEEBA ; .dw 0xE159 ; .dw 0xEEBB ; .dw 0x138F ; .dw 0xEEBC ; .dw 0x1C45 ; .dw 0xEEBD ; .dw 0x43DB ; .dw 0xEEBE ; .dw 0xFC71 ; .dw 0xEEBF ; .dw 0xDACD ; .dw 0xEEC0 ; .dw 0x1C35 ; .dw 0xEEC1 ; .dw 0x2D29 ; .dw 0xEEC2 ; .dw 0xBDA7 ; .dw 0xEEC3 ; .dw 0xEC97 ; .dw 0xEEC4 ; .dw 0x61E7 ; .dw 0xEEC5 ; .dw 0x50D7 ; .dw 0xEEC6 ; .dw 0x4A31 ; .dw 0xEEC7 ; .dw 0x50D ; .dw 0xEEC8 ; .dw 0x9DC7 ; .dw 0xEEC9 ; .dw 0x9169 ; .dw 0xEECA ; .dw 0x4105 ; .dw 0xEECB ; .dw 0xACB5 ; .dw 0xEECC ; .dw 0xD79F ; .dw 0xEECD ; .dw 0x8133 ; .dw 0xEECE ; .dw 0x5575 ; .dw 0xEECF ; .dw 0x5B31 ; .dw 0xEED0 ; .dw 0x46EF ; .dw 0xEED1 ; .dw 0x4FD1 ; .dw 0xEED2 ; .dw 0xFB45 ; .dw 0xEED3 ; .dw 0xD75 ; .dw 0xEED4 ; .dw 0x58BF ; .dw 0xEED5 ; .dw 0x171F ; .dw 0xEED6 ; .dw 0xBC3B ; .dw 0xEED7 ; .dw 0x77F ; .dw 0xEED8 ; .dw 0x3B03 ; .dw 0xEED9 ; .dw 0xFFAF ; .dw 0xEEDA ; .dw 0x4F4B ; .dw 0xEEDB ; .dw 0xF991 ; .dw 0xEEDC ; .dw 0xC569 ; .dw 0xEEDD ; .dw 0x34C1 ; .dw 0xEEDE ; .dw 0x915 ; .dw 0xEEDF ; .dw 0x40EF ; .dw 0xEEE0 ; .dw 0x17B5 ; .dw 0xEEE1 ; .dw 0x1FC3 ; .dw 0xEEE2 ; .dw 0xBE17 ; .dw 0xEEE3 ; .dw 0x7C07 ; .dw 0xEEE4 ; .dw 0xC599 ; .dw 0xEEE5 ; .dw 0xE339 ; .dw 0xEEE6 ; .dw 0xAE2D ; .dw 0xEEE7 ; .dw 0x2A37 ; .dw 0xEEE8 ; .dw 0xE80D ; .dw 0xEEE9 ; .dw 0x8D45 ; .dw 0xEEEA ; .dw 0x91BF ; .dw 0xEEEB ; .dw 0x8F01 ; .dw 0xEEEC ; .dw 0xEC27 ; .dw 0xEEED ; .dw 0xF997 ; .dw 0xEEEE ; .dw 0x6047 ; .dw 0xEEEF ; .dw 0x90C3 ; .dw 0xEEF0 ; .dw 0x776F ; .dw 0xEEF1 ; .dw 0xDAE9 ; .dw 0xEEF2 ; .dw 0xE873 ; .dw 0xEEF3 ; .dw 0xCAEB ; .dw 0xEEF4 ; .dw 0x39BD ; .dw 0xEEF5 ; .dw 0xE3EF ; .dw 0xEEF6 ; .dw 0xD1BB ; .dw 0xEEF7 ; .dw 0x8BB7 ; .dw 0xEEF8 ; .dw 0x48F ; .dw 0xEEF9 ; .dw 0x87D7 ; .dw 0xEEFA ; .dw 0x1F79 ; .dw 0xEEFB ; .dw 0xF563 ; .dw 0xEEFC ; .dw 0xFFE1 ; .dw 0xEEFD ; .dw 0x4A41 ; .dw 0xEEFE ; .dw 0xCD7F ; .dw 0xEEFF ; .dw 0xFAED ; .dw 0xEF00 ; .dw 0x5481 ; .dw 0xEF01 ; .dw 0x16B3 ; .dw 0xEF02 ; .dw 0x9E2F ; .dw 0xEF03 ; .dw 0x7041 ; .dw 0xEF04 ; .dw 0x23EF ; .dw 0xEF05 ; .dw 0x9791 ; .dw 0xEF06 ; .dw 0xB21B ; .dw 0xEF07 ; .dw 0xE5F9 ; .dw 0xEF08 ; .dw 0x25AD ; .dw 0xEF09 ; .dw 0x495 ; .dw 0xEF0A ; .dw 0x10F ; .dw 0xEF0B ; .dw 0x8895 ; .dw 0xEF0C ; .dw 0xC21B ; .dw 0xEF0D ; .dw 0x60CF ; .dw 0xEF0E ; .dw 0x4CB3 ; .dw 0xEF0F ; .dw 0xBB29 ; .dw 0xEF10 ; .dw 0x2D3 ; .dw 0xEF11 ; .dw 0xA00F ; .dw 0xEF12 ; .dw 0xA4A3 ; .dw 0xEF13 ; .dw 0xA5A5 ; .dw 0xEF14 ; .dw 0x3075 ; .dw 0xEF15 ; .dw 0xABEB ; .dw 0xEF16 ; .dw 0x1403 ; .dw 0xEF17 ; .dw 0x6E7F ; .dw 0xEF18 ; .dw 0x760B ; .dw 0xEF19 ; .dw 0xC02B ; .dw 0xEF1A ; .dw 0x9095 ; .dw 0xEF1B ; .dw 0x57F3 ; .dw 0xEF1C ; .dw 0x61DD ; .dw 0xEF1D ; .dw 0x16CB ; .dw 0xEF1E ; .dw 0xC35B ; .dw 0xEF1F ; .dw 0x78B7 ; .dw 0xEF20 ; .dw 0x9BC9 ; .dw 0xEF21 ; .dw 0x5B6D ; .dw 0xEF22 ; .dw 0xC2A3 ; .dw 0xEF23 ; .dw 0x4837 ; .dw 0xEF24 ; .dw 0xA915 ; .dw 0xEF25 ; .dw 0xDE4D ; .dw 0xEF26 ; .dw 0x55A9 ; .dw 0xEF27 ; .dw 0xB645 ; .dw 0xEF28 ; .dw 0x15D3 ; .dw 0xEF29 ; .dw 0xFEC9 ; .dw 0xEF2A ; .dw 0xD9A5 ; .dw 0xEF2B ; .dw 0x65D ; .dw 0xEF2C ; .dw 0xDBAD ; .dw 0xEF2D ; .dw 0xC547 ; .dw 0xEF2E ; .dw 0x606D ; .dw 0xEF2F ; .dw 0x2655 ; .dw 0xEF30 ; .dw 0x5E49 ; .dw 0xEF31 ; .dw 0x24B7 ; .dw 0xEF32 ; .dw 0x2087 ; .dw 0xEF33 ; .dw 0xB893 ; .dw 0xEF34 ; .dw 0xD515 ; .dw 0xEF35 ; .dw 0xDB85 ; .dw 0xEF36 ; .dw 0xCEC3 ; .dw 0xEF37 ; .dw 0x89C9 ; .dw 0xEF38 ; .dw 0x7AA7 ; .dw 0xEF39 ; .dw 0x6C1D ; .dw 0xEF3A ; .dw 0xF951 ; .dw 0xEF3B ; .dw 0xAA33 ; .dw 0xEF3C ; .dw 0x5991 ; .dw 0xEF3D ; .dw 0x24CF ; .dw 0xEF3E ; .dw 0xFC5D ; .dw 0xEF3F ; .dw 0xE23F ; .dw 0xEF40 ; .dw 0xEBB ; .dw 0xEF41 ; .dw 0xAF5D ; .dw 0xEF42 ; .dw 0xA823 ; .dw 0xEF43 ; .dw 0xBAD7 ; .dw 0xEF44 ; .dw 0x593D ; .dw 0xEF45 ; .dw 0x1FE1 ; .dw 0xEF46 ; .dw 0x3087 ; .dw 0xEF47 ; .dw 0xD109 ; .dw 0xEF48 ; .dw 0xCFAF ; .dw 0xEF49 ; .dw 0xFB51 ; .dw 0xEF4A ; .dw 0x7E31 ; .dw 0xEF4B ; .dw 0xAD4F ; .dw 0xEF4C ; .dw 0x930D ; .dw 0xEF4D ; .dw 0x2D71 ; .dw 0xEF4E ; .dw 0x7923 ; .dw 0xEF4F ; .dw 0xD635 ; .dw 0xEF50 ; .dw 0x5703 ; .dw 0xEF51 ; .dw 0x664D ; .dw 0xEF52 ; .dw 0x64CD ; .dw 0xEF53 ; .dw 0x56A1 ; .dw 0xEF54 ; .dw 0x97CF ; .dw 0xEF55 ; .dw 0xD72F ; .dw 0xEF56 ; .dw 0xE5AB ; .dw 0xEF57 ; .dw 0x6F85 ; .dw 0xEF58 ; .dw 0x5591 ; .dw 0xEF59 ; .dw 0xC719 ; .dw 0xEF5A ; .dw 0xC85B ; .dw 0xEF5B ; .dw 0xAD11 ; .dw 0xEF5C ; .dw 0x2D29 ; .dw 0xEF5D ; .dw 0xF6BD ; .dw 0xEF5E ; .dw 0x2233 ; .dw 0xEF5F ; .dw 0x1773 ; .dw 0xEF60 ; .dw 0x2689 ; .dw 0xEF61 ; .dw 0x4BF5 ; .dw 0xEF62 ; .dw 0xE35B ; .dw 0xEF63 ; .dw 0xB711 ; .dw 0xEF64 ; .dw 0x1095 ; .dw 0xEF65 ; .dw 0xBCBB ; .dw 0xEF66 ; .dw 0x7265 ; .dw 0xEF67 ; .dw 0x2437 ; .dw 0xEF68 ; .dw 0xC273 ; .dw 0xEF69 ; .dw 0xF19F ; .dw 0xEF6A ; .dw 0x6963 ; .dw 0xEF6B ; .dw 0x5A55 ; .dw 0xEF6C ; .dw 0x1A6B ; .dw 0xEF6D ; .dw 0x97BF ; .dw 0xEF6E ; .dw 0xC85 ; .dw 0xEF6F ; .dw 0x86BB ; .dw 0xEF70 ; .dw 0x1231 ; .dw 0xEF71 ; .dw 0xDA43 ; .dw 0xEF72 ; .dw 0x9225 ; .dw 0xEF73 ; .dw 0xAC5 ; .dw 0xEF74 ; .dw 0xC0D3 ; .dw 0xEF75 ; .dw 0xFB55 ; .dw 0xEF76 ; .dw 0xD46B ; .dw 0xEF77 ; .dw 0x69A1 ; .dw 0xEF78 ; .dw 0xA1FD ; .dw 0xEF79 ; .dw 0x8491 ; .dw 0xEF7A ; .dw 0x8463 ; .dw 0xEF7B ; .dw 0x597D ; .dw 0xEF7C ; .dw 0xFAD7 ; .dw 0xEF7D ; .dw 0x705 ; .dw 0xEF7E ; .dw 0x768D ; .dw 0xEF7F ; .dw 0xB045 ; .dw 0xEF80 ; .dw 0xB463 ; .dw 0xEF81 ; .dw 0xE2A7 ; .dw 0xEF82 ; .dw 0x20FF ; .dw 0xEF83 ; .dw 0x63D7 ; .dw 0xEF84 ; .dw 0x834F ; .dw 0xEF85 ; .dw 0xD4B ; .dw 0xEF86 ; .dw 0xE2F3 ; .dw 0xEF87 ; .dw 0x55BD ; .dw 0xEF88 ; .dw 0xB54F ; .dw 0xEF89 ; .dw 0x511F ; .dw 0xEF8A ; .dw 0x2DED ; .dw 0xEF8B ; .dw 0x2265 ; .dw 0xEF8C ; .dw 0x7BF5 ; .dw 0xEF8D ; .dw 0xFA9D ; .dw 0xEF8E ; .dw 0x2843 ; .dw 0xEF8F ; .dw 0xABD5 ; .dw 0xEF90 ; .dw 0xD03 ; .dw 0xEF91 ; .dw 0x6E0B ; .dw 0xEF92 ; .dw 0xE13F ; .dw 0xEF93 ; .dw 0x97E9 ; .dw 0xEF94 ; .dw 0x7051 ; .dw 0xEF95 ; .dw 0x9C69 ; .dw 0xEF96 ; .dw 0xAEB5 ; .dw 0xEF97 ; .dw 0x7A0D ; .dw 0xEF98 ; .dw 0x5315 ; .dw 0xEF99 ; .dw 0xCFF5 ; .dw 0xEF9A ; .dw 0xCC19 ; .dw 0xEF9B ; .dw 0xE069 ; .dw 0xEF9C ; .dw 0xB8C9 ; .dw 0xEF9D ; .dw 0xC815 ; .dw 0xEF9E ; .dw 0xD31B ; .dw 0xEF9F ; .dw 0xFCA3 ; .dw 0xEFA0 ; .dw 0xE179 ; .dw 0xEFA1 ; .dw 0x9CDF ; .dw 0xEFA2 ; .dw 0x25BB ; .dw 0xEFA3 ; .dw 0x2019 ; .dw 0xEFA4 ; .dw 0x3D9B ; .dw 0xEFA5 ; .dw 0x61FF ; .dw 0xEFA6 ; .dw 0xE1E3 ; .dw 0xEFA7 ; .dw 0xC38D ; .dw 0xEFA8 ; .dw 0xC773 ; .dw 0xEFA9 ; .dw 0x141 ; .dw 0xEFAA ; .dw 0x767D ; .dw 0xEFAB ; .dw 0x5269 ; .dw 0xEFAC ; .dw 0x99DB ; .dw 0xEFAD ; .dw 0x447D ; .dw 0xEFAE ; .dw 0x720D ; .dw 0xEFAF ; .dw 0x7173 ; .dw 0xEFB0 ; .dw 0x1CA7 ; .dw 0xEFB1 ; .dw 0x8711 ; .dw 0xEFB2 ; .dw 0xA2CB ; .dw 0xEFB3 ; .dw 0xF903 ; .dw 0xEFB4 ; .dw 0x9E77 ; .dw 0xEFB5 ; .dw 0x6DB ; .dw 0xEFB6 ; .dw 0x2035 ; .dw 0xEFB7 ; .dw 0x5ABB ; .dw 0xEFB8 ; .dw 0xB40F ; .dw 0xEFB9 ; .dw 0x4CB5 ; .dw 0xEFBA ; .dw 0x562D ; .dw 0xEFBB ; .dw 0xAAC3 ; .dw 0xEFBC ; .dw 0x3531 ; .dw 0xEFBD ; .dw 0xA461 ; .dw 0xEFBE ; .dw 0xA98F ; .dw 0xEFBF ; .dw 0x47F ; .dw 0xEFC0 ; .dw 0x2EF9 ; .dw 0xEFC1 ; .dw 0x1C0F ; .dw 0xEFC2 ; .dw 0xCE43 ; .dw 0xEFC3 ; .dw 0x82C5 ; .dw 0xEFC4 ; .dw 0xA3A9 ; .dw 0xEFC5 ; .dw 0x34B ; .dw 0xEFC6 ; .dw 0x66E3 ; .dw 0xEFC7 ; .dw 0x8395 ; .dw 0xEFC8 ; .dw 0x700D ; .dw 0xEFC9 ; .dw 0x6179 ; .dw 0xEFCA ; .dw 0x5C3 ; .dw 0xEFCB ; .dw 0x6F55 ; .dw 0xEFCC ; .dw 0x2E51 ; .dw 0xEFCD ; .dw 0x5BCF ; .dw 0xEFCE ; .dw 0x2795 ; .dw 0xEFCF ; .dw 0xBB87 ; .dw 0xEFD0 ; .dw 0x6E4F ; .dw 0xEFD1 ; .dw 0x2C7 ; .dw 0xEFD2 ; .dw 0x3F7B ; .dw 0xEFD3 ; .dw 0x60FD ; .dw 0xEFD4 ; .dw 0x1B77 ; .dw 0xEFD5 ; .dw 0x7F1B ; .dw 0xEFD6 ; .dw 0x6C9F ; .dw 0xEFD7 ; .dw 0x7D99 ; .dw 0xEFD8 ; .dw 0x6817 ; .dw 0xEFD9 ; .dw 0x163F ; .dw 0xEFDA ; .dw 0xF151 ; .dw 0xEFDB ; .dw 0x597D ; .dw 0xEFDC ; .dw 0x163F ; .dw 0xEFDD ; .dw 0xFE55 ; .dw 0xEFDE ; .dw 0x395 ; .dw 0xEFDF ; .dw 0x87C7 ; .dw 0xEFE0 ; .dw 0x7615 ; .dw 0xEFE1 ; .dw 0x79A7 ; .dw 0xEFE2 ; .dw 0xF45 ; .dw 0xEFE3 ; .dw 0x5ACB ; .dw 0xEFE4 ; .dw 0xF1A7 ; .dw 0xEFE5 ; .dw 0x319B ; .dw 0xEFE6 ; .dw 0x1A3 ; .dw 0xEFE7 ; .dw 0x63C5 ; .dw 0xEFE8 ; .dw 0x7E4F ; .dw 0xEFE9 ; .dw 0x4935 ; .dw 0xEFEA ; .dw 0xB66F ; .dw 0xEFEB ; .dw 0x3617 ; .dw 0xEFEC ; .dw 0xCB83 ; .dw 0xEFED ; .dw 0x1F03 ; .dw 0xEFEE ; .dw 0x1E89 ; .dw 0xEFEF ; .dw 0x25FF ; .dw 0xEFF0 ; .dw 0x872B ; .dw 0xEFF1 ; .dw 0x369D ; .dw 0xEFF2 ; .dw 0x37FB ; .dw 0xEFF3 ; .dw 0x3ACB ; .dw 0xEFF4 ; .dw 0x8F81 ; .dw 0xEFF5 ; .dw 0x4199 ; .dw 0xEFF6 ; .dw 0x6FA1 ; .dw 0xEFF7 ; .dw 0xC99 ; .dw 0xEFF8 ; .dw 0x6A5F ; .dw 0xEFF9 ; .dw 0xC007 ; .dw 0xEFFA ; .dw 0x8433 ; .dw 0xEFFB ; .dw 0xC585 ; .dw 0xEFFC ; .dw 0xDA23 ; .dw 0xEFFD ; .dw 0x3065 ; .dw 0xEFFE ; .dw 0x82E1 ; .dw 0xEFFF ; .dw 0xFE6D ; .dw 0xC700 ; .dw 0xE7FB ; .dw 0xC701 ; .dw 0x4717 ; .dw 0xC702 ; .dw 0xF573 ; .dw 0xC703 ; .dw 0xAF1D ; .dw 0xC704 ; .dw 0x3BC7 ; .dw 0xC705 ; .dw 0x2563 ; .dw 0xC706 ; .dw 0xD9D3 ; .dw 0xC707 ; .dw 0xEA0F ; .dw 0xC708 ; .dw 0x1969 ; .dw 0xC709 ; .dw 0x7E5 ; .dw 0xC70A ; .dw 0x7B31 ; .dw 0xC70B ; .dw 0x9BA1 ; .dw 0xC70C ; .dw 0xDBA3 ; .dw 0xC70D ; .dw 0x6489 ; .dw 0xC70E ; .dw 0xC499 ; .dw 0xC70F ; .dw 0x4CD ; .dw 0xC710 ; .dw 0x446B ; .dw 0xC711 ; .dw 0xF003 ; .dw 0xC712 ; .dw 0x24FF ; .dw 0xC713 ; .dw 0x295D ; .dw 0xC714 ; .dw 0x7AC3 ; .dw 0xC715 ; .dw 0x82C5 ; .dw 0xC716 ; .dw 0x9CED ; .dw 0xC717 ; .dw 0xE9A9 ; .dw 0xC718 ; .dw 0xE15 ; .dw 0xC719 ; .dw 0x557B ; .dw 0xC71A ; .dw 0xD83 ; .dw 0xC71B ; .dw 0xFFCD ; .dw 0xC71C ; .dw 0xD70B ; .dw 0xC71D ; .dw 0x8CFD ; .dw 0xC71E ; .dw 0x6121 ; .dw 0xC71F ; .dw 0x985F ; .dw 0xC720 ; .dw 0xDDD ; .dw 0xC721 ; .dw 0x8DCF ; .dw 0xC722 ; .dw 0xA579 ; .dw 0xC723 ; .dw 0xBEA9 ; .dw 0xC724 ; .dw 0x6E39 ; .dw 0xC725 ; .dw 0xF0F ; .dw 0xC726 ; .dw 0xAF23 ; .dw 0xC727 ; .dw 0x5461 ; .dw 0xC728 ; .dw 0xC08B ; .dw 0xC729 ; .dw 0x64F9 ; .dw 0xC72A ; .dw 0x5EBB ; .dw 0xC72B ; .dw 0xCCE3 ; .dw 0xC72C ; .dw 0xA0E1 ; .dw 0xC72D ; .dw 0xFAD1 ; .dw 0xC72E ; .dw 0x1F75 ; .dw 0xC72F ; .dw 0x63DF ; .dw 0xC730 ; .dw 0xDB3D ; .dw 0xC731 ; .dw 0x7469 ; .dw 0xC732 ; .dw 0xB735 ; .dw 0xC733 ; .dw 0x7A1 ; .dw 0xC734 ; .dw 0x356F ; .dw 0xC735 ; .dw 0x6F0F ; .dw 0xC736 ; .dw 0x2F ; .dw 0xC737 ; .dw 0xAEB9 ; .dw 0xC738 ; .dw 0xFE6D ; .dw 0xC739 ; .dw 0x5A0B ; .dw 0xC73A ; .dw 0xA3F1 ; .dw 0xC73B ; .dw 0x5143 ; .dw 0xC73C ; .dw 0x3B29 ; .dw 0xC73D ; .dw 0x5E91 ; .dw 0xC73E ; .dw 0x7007 ; .dw 0xC73F ; .dw 0x3D8D ; .dw 0xC740 ; .dw 0xC8EB ; .dw 0xC741 ; .dw 0xCF3F ; .dw 0xC742 ; .dw 0x5C0B ; .dw 0xC743 ; .dw 0x61 ; .dw 0xC744 ; .dw 0x4D2B ; .dw 0xC745 ; .dw 0x1713 ; .dw 0xC746 ; .dw 0xD945 ; .dw 0xC747 ; .dw 0x98AD ; .dw 0xC748 ; .dw 0x4AE3 ; .dw 0xC749 ; .dw 0x9FDF ; .dw 0xC74A ; .dw 0x83BB ; .dw 0xC74B ; .dw 0x2EC9 ; .dw 0xC74C ; .dw 0x356B ; .dw 0xC74D ; .dw 0xA84B ; .dw 0xC74E ; .dw 0xCCCD ; .dw 0xC74F ; .dw 0x727 ; .dw 0xC750 ; .dw 0xD8D1 ; .dw 0xC751 ; .dw 0x813F ; .dw 0xC752 ; .dw 0xB74F ; .dw 0xC753 ; .dw 0xE887 ; .dw 0xC754 ; .dw 0xEFB3 ; .dw 0xC755 ; .dw 0x2AE7 ; .dw 0xC756 ; .dw 0x3D1B ; .dw 0xC757 ; .dw 0xADBB ; .dw 0xC758 ; .dw 0x3E93 ; .dw 0xC759 ; .dw 0xC925 ; .dw 0xC75A ; .dw 0x762D ; .dw 0xC75B ; .dw 0x3AD7 ; .dw 0xC75C ; .dw 0xCAB ; .dw 0xC75D ; .dw 0xE78D ; .dw 0xC75E ; .dw 0x193F ; .dw 0xC75F ; .dw 0x8DE9 ; .dw 0xC760 ; .dw 0x5255 ; .dw 0xC761 ; .dw 0x4D7 ; .dw 0xC762 ; .dw 0x6DD7 ; .dw 0xC763 ; .dw 0x2333 ; .dw 0xC764 ; .dw 0x74CF ; .dw 0xC765 ; .dw 0x5DDB ; .dw 0xC766 ; .dw 0x47E5 ; .dw 0xC767 ; .dw 0x64E1 ; .dw 0xC768 ; .dw 0xE7A1 ; .dw 0xC769 ; .dw 0x700B ; .dw 0xC76A ; .dw 0x24E1 ; .dw 0xC76B ; .dw 0x5E49 ; .dw 0xC76C ; .dw 0x8B73 ; .dw 0xC76D ; .dw 0x2B65 ; .dw 0xC76E ; .dw 0x253 ; .dw 0xC76F ; .dw 0x6A93 ; .dw 0xC770 ; .dw 0x225B ; .dw 0xC771 ; .dw 0x4BF5 ; .dw 0xC772 ; .dw 0x5F9 ; .dw 0xC773 ; .dw 0x1701 ; .dw 0xC774 ; .dw 0xB1C3 ; .dw 0xC775 ; .dw 0xD2BD ; .dw 0xC776 ; .dw 0x8F5D ; .dw 0xC777 ; .dw 0xF09F ; .dw 0xC778 ; .dw 0x29B7 ; .dw 0xC779 ; .dw 0x163D ; .dw 0xC77A ; .dw 0xCAE9 ; .dw 0xC77B ; .dw 0x757B ; .dw 0xC77C ; .dw 0x29C5 ; .dw 0xC77D ; .dw 0x6263 ; .dw 0xC77E ; .dw 0x5E7D ; .dw 0xC77F ; .dw 0xE161 ; .dw 0xC780 ; .dw 0x3B49 ; .dw 0xC781 ; .dw 0xA005 ; .dw 0xC782 ; .dw 0x478D ; .dw 0xC783 ; .dw 0xE0F ; .dw 0xC784 ; .dw 0x5955 ; .dw 0xC785 ; .dw 0xFBD9 ; .dw 0xC786 ; .dw 0x82B7 ; .dw 0xC787 ; .dw 0x1EEF ; .dw 0xC788 ; .dw 0x1DF9 ; .dw 0xC789 ; .dw 0x4E9 ; .dw 0xC78A ; .dw 0x94DD ; .dw 0xC78B ; .dw 0x304D ; .dw 0xC78C ; .dw 0x6D27 ; .dw 0xC78D ; .dw 0x3A93 ; .dw 0xC78E ; .dw 0x8DB3 ; .dw 0xC78F ; .dw 0xC213 ; .dw 0xC790 ; .dw 0xF507 ; .dw 0xC791 ; .dw 0x81F9 ; .dw 0xC792 ; .dw 0x9BE7 ; .dw 0xC793 ; .dw 0x15FD ; .dw 0xC794 ; .dw 0x5BCB ; .dw 0xC795 ; .dw 0x7AFF ; .dw 0xC796 ; .dw 0xCAA9 ; .dw 0xC797 ; .dw 0x3951 ; .dw 0xC798 ; .dw 0x730D ; .dw 0xC799 ; .dw 0x2CBF ; .dw 0xC79A ; .dw 0xD3 ; .dw 0xC79B ; .dw 0xF21D ; .dw 0xC79C ; .dw 0x48A3 ; .dw 0xC79D ; .dw 0x183 ; .dw 0xC79E ; .dw 0xD96D ; .dw 0xC79F ; .dw 0x47E7 ; .dw 0xC7A0 ; .dw 0x6CF9 ; .dw 0xC7A1 ; .dw 0x8A3D ; .dw 0xC7A2 ; .dw 0x6DDD ; .dw 0xC7A3 ; .dw 0xDFE7 ; .dw 0xC7A4 ; .dw 0x46EB ; .dw 0xC7A5 ; .dw 0x17D ; .dw 0xC7A6 ; .dw 0xA96B ; .dw 0xC7A7 ; .dw 0xE4C5 ; .dw 0xC7A8 ; .dw 0xCD17 ; .dw 0xC7A9 ; .dw 0x5ED ; .dw 0xC7AA ; .dw 0x3E5F ; .dw 0xC7AB ; .dw 0xB1C9 ; .dw 0xC7AC ; .dw 0x7CBB ; .dw 0xC7AD ; .dw 0x8443 ; .dw 0xC7AE ; .dw 0xD4A1 ; .dw 0xC7AF ; .dw 0xF999 ; .dw 0xC7B0 ; .dw 0xE607 ; .dw 0xC7B1 ; .dw 0x48BF ; .dw 0xC7B2 ; .dw 0x89C7 ; .dw 0xC7B3 ; .dw 0xA06D ; .dw 0xC7B4 ; .dw 0xA5FD ; .dw 0xC7B5 ; .dw 0x3021 ; .dw 0xC7B6 ; .dw 0x5AAF ; .dw 0xC7B7 ; .dw 0x1C7 ; .dw 0xC7B8 ; .dw 0x25C1 ; .dw 0xC7B9 ; .dw 0x701F ; .dw 0xC7BA ; .dw 0x8E99 ; .dw 0xC7BB ; .dw 0xD9AF ; .dw 0xC7BC ; .dw 0xF775 ; .dw 0xC7BD ; .dw 0xEF5D ; .dw 0xC7BE ; .dw 0xBBC3 ; .dw 0xC7BF ; .dw 0x8969 ; .dw 0xC7C0 ; .dw 0x2895 ; .dw 0xC7C1 ; .dw 0x24ED ; .dw 0xC7C2 ; .dw 0x7D79 ; .dw 0xC7C3 ; .dw 0xEFA9 ; .dw 0xC7C4 ; .dw 0x61C3 ; .dw 0xC7C5 ; .dw 0x7737 ; .dw 0xC7C6 ; .dw 0x73AD ; .dw 0xC7C7 ; .dw 0x8C53 ; .dw 0xC7C8 ; .dw 0x2C2D ; .dw 0xC7C9 ; .dw 0x9283 ; .dw 0xC7CA ; .dw 0xA419 ; .dw 0xC7CB ; .dw 0x27AD ; .dw 0xC7CC ; .dw 0x345B ; .dw 0xC7CD ; .dw 0xAEE3 ; .dw 0xC7CE ; .dw 0xD4CB ; .dw 0xC7CF ; .dw 0xB513 ; .dw 0xC7D0 ; .dw 0xE289 ; .dw 0xC7D1 ; .dw 0x3DB5 ; .dw 0xC7D2 ; .dw 0xF849 ; .dw 0xC7D3 ; .dw 0xA93F ; .dw 0xC7D4 ; .dw 0x2087 ; .dw 0xC7D5 ; .dw 0xF68F ; .dw 0xC7D6 ; .dw 0x431B ; .dw 0xC7D7 ; .dw 0x7BEB ; .dw 0xC7D8 ; .dw 0xA503 ; .dw 0xC7D9 ; .dw 0xBBC9 ; .dw 0xC7DA ; .dw 0x2F1 ; .dw 0xC7DB ; .dw 0x8D1F ; .dw 0xC7DC ; .dw 0x9C6F ; .dw 0xC7DD ; .dw 0x4E61 ; .dw 0xC7DE ; .dw 0xCF2F ; .dw 0xC7DF ; .dw 0x25D7 ; .dw 0xC7E0 ; .dw 0x74B ; .dw 0xC7E1 ; .dw 0x4983 ; .dw 0xC7E2 ; .dw 0x2B0D ; .dw 0xC7E3 ; .dw 0xCC47 ; .dw 0xC7E4 ; .dw 0xA60D ; .dw 0xC7E5 ; .dw 0x5D77 ; .dw 0xC7E6 ; .dw 0x312F ; .dw 0xC7E7 ; .dw 0xA38B ; .dw 0xC7E8 ; .dw 0xCA6B ; .dw 0xC7E9 ; .dw 0x421D ; .dw 0xC7EA ; .dw 0x60B7 ; .dw 0xC7EB ; .dw 0xEE7 ; .dw 0xC7EC ; .dw 0xE637 ; .dw 0xC7ED ; .dw 0x58E7 ; .dw 0xC7EE ; .dw 0x23E1 ; .dw 0xC7EF ; .dw 0x5073 ; .dw 0xC7F0 ; .dw 0x2FC1 ; .dw 0xC7F1 ; .dw 0x7649 ; .dw 0xC7F2 ; .dw 0x281D ; .dw 0xC7F3 ; .dw 0x5B63 ; .dw 0xC7F4 ; .dw 0x339B ; .dw 0xC7F5 ; .dw 0xCABD ; .dw 0xC7F6 ; .dw 0x1FA1 ; .dw 0xC7F7 ; .dw 0x91B3 ; .dw 0xC7F8 ; .dw 0xAC07 ; .dw 0xC7F9 ; .dw 0x632F ; .dw 0xC7FA ; .dw 0x485 ; .dw 0xC7FB ; .dw 0xA55F ; .dw 0xC7FC ; .dw 0x75BD ; .dw 0xC7FD ; .dw 0x38FF ; .dw 0xC7FE ; .dw 0x755D ; .dw 0xC7FF ; .dw 0x5523 ; .dw 0xE0C0 ; .dw 0x0000 ; .dw 0xE0A0 ; .dw 0x8000 ; .dw 0xE1A0 ; .dw 0x0 ; .dw 0xC401 ; .dw 0x4000 ; .dw 0xC404 ; .dw 0xC000 ; .dw 0xC406 ; .dw 0xC000 ; .dw 0xC407 ; .dw 0xC000 ; .dw 0xC40A ; .dw 0x8000 ; .dw 0xC40A ; .dw 0xC000 ; .dw 0xC40C ; .dw 0x8000 ; .dw 0xC40E ; .dw 0x8000 ; .dw 0xC40F ; .dw 0x0 ; .dw 0xC40F ; .dw 0x4000 ; .dw 0xC40F ; .dw 0x8000 ; .dw 0xC410 ; .dw 0x8000 ; .dw 0xC411 ; .dw 0x8000 ; .dw 0xC411 ; .dw 0xC000 ; .dw 0xC412 ; .dw 0x4000 ; .dw 0xC412 ; .dw 0x8000 ; .dw 0xC413 ; .dw 0x0 ; .dw 0xC413 ; .dw 0x4000 ; .dw 0xC413 ; .dw 0x8000 ; .dw 0xC413 ; .dw 0xC000 ; .dw 0xC414 ; .dw 0x8000 ; .dw 0xC414 ; .dw 0xC000 ; .dw 0xC415 ; .dw 0x8000 ; .dw 0xC415 ; .dw 0xC000 ; .dw 0xC418 ; .dw 0x8000 ; .dw 0xC418 ; .dw 0xC000 ; .dw 0xC417 ; .dw 0x4000 ; .dw 0xC417 ; .dw 0x8000 ; .dw 0xC417 ; .dw 0xC000 ; .dw 0xC419 ; .dw 0x0 ; .dw 0xC419 ; .dw 0x4000 ; .dw 0xC419 ; .dw 0x8000 ; .dw 0xC419 ; .dw 0xC000 ; .dw 0xC41A ; .dw 0x0 ; .dw 0xC41A ; .dw 0x4000 ; .dw 0xC41A ; .dw 0x8000 ; .dw 0xC41A ; .dw 0xC000 ; .dw 0xC41B ; .dw 0x0 ; .dw 0xC41B ; .dw 0x4000 ; .dw 0xC41B ; .dw 0x8000 ; .dw 0xC41B ; .dw 0xC000 ; .dw 0xC41C ; .dw 0x0 ; .dw 0xC41C ; .dw 0x4000 ; .dw 0xC41C ; .dw 0x8000 ; .dw 0xC41C ; .dw 0xC000 ; .dw 0xC41D ; .dw 0x0 ; .dw 0xC41D ; .dw 0x4000 ; .dw 0xC41D ; .dw 0x8000 ; .dw 0xC41D ; .dw 0xC000 ; .dw 0xC41E ; .dw 0x0 ; .dw 0xC41E ; .dw 0x4000 ; .dw 0xC41E ; .dw 0x8000 ; .dw 0xC41E ; .dw 0xC000 ; .dw 0xC41F ; .dw 0x0 ; .dw 0xC41F ; .dw 0x4000 ; .dw 0xC41F ; .dw 0x8000 ; .dw 0xC41F ; .dw 0xC000 ; .dw 0xC401 ; .dw 0x0 ; .dw 0xC401 ; .dw 0x240 ; .dw 0xC401 ; .dw 0x480 ; .dw 0xC401 ; .dw 0x6C0 ; .dw 0xC401 ; .dw 0x900 ; .dw 0xC401 ; .dw 0xB40 ; .dw 0xC401 ; .dw 0xD80 ; .dw 0xC401 ; .dw 0xFC0 ; .dw 0xC401 ; .dw 0x8000 ; .dw 0xC401 ; .dw 0x8240 ; .dw 0xC401 ; .dw 0x8480 ; .dw 0xC401 ; .dw 0x86C0 ; .dw 0xC401 ; .dw 0x8900 ; .dw 0xC401 ; .dw 0x8B40 ; .dw 0xC401 ; .dw 0x8D80 ; .dw 0xC401 ; .dw 0x8FC0 ; .dw 0xC401 ; .dw 0xC000 ; .dw 0xC401 ; .dw 0xC240 ; .dw 0xC401 ; .dw 0xC480 ; .dw 0xC401 ; .dw 0xC6C0 ; .dw 0xC401 ; .dw 0xC900 ; .dw 0xC401 ; .dw 0xCB40 ; .dw 0xC401 ; .dw 0xCD80 ; .dw 0xC401 ; .dw 0xCFC0 ; .dw 0xC404 ; .dw 0x8000 ; .dw 0xC404 ; .dw 0x8240 ; .dw 0xC404 ; .dw 0x8480 ; .dw 0xC404 ; .dw 0x86C0 ; .dw 0xC404 ; .dw 0x8900 ; .dw 0xC404 ; .dw 0x8B40 ; .dw 0xC404 ; .dw 0x8D80 ; .dw 0xC404 ; .dw 0x8FC0 ; .dw 0xC40C ; .dw 0x4000 ; .dw 0xC40C ; .dw 0x4240 ; .dw 0xC40C ; .dw 0x4480 ; .dw 0xC40C ; .dw 0x46C0 ; .dw 0xC40C ; .dw 0x4900 ; .dw 0xC40C ; .dw 0x4B40 ; .dw 0xC40C ; .dw 0x4D80 ; .dw 0xC40C ; .dw 0x4FC0 ; .dw 0xC40D ; .dw 0x0 ; .dw 0xC40D ; .dw 0x240 ; .dw 0xC40D ; .dw 0x480 ; .dw 0xC40D ; .dw 0x6C0 ; .dw 0xC40D ; .dw 0x900 ; .dw 0xC40D ; .dw 0xB40 ; .dw 0xC40D ; .dw 0xD80 ; .dw 0xC40D ; .dw 0xFC0 ; .dw 0xC40D ; .dw 0x4000 ; .dw 0xC40D ; .dw 0x4240 ; .dw 0xC40D ; .dw 0x4480 ; .dw 0xC40D ; .dw 0x46C0 ; .dw 0xC40D ; .dw 0x4900 ; .dw 0xC40D ; .dw 0x4B40 ; .dw 0xC40D ; .dw 0x4D80 ; .dw 0xC40D ; .dw 0x4FC0 ; .dw 0xC40D ; .dw 0x8000 ; .dw 0xC40D ; .dw 0x8240 ; .dw 0xC40D ; .dw 0x8480 ; .dw 0xC40D ; .dw 0x86C0 ; .dw 0xC40D ; .dw 0x8900 ; .dw 0xC40D ; .dw 0x8B40 ; .dw 0xC40D ; .dw 0x8D80 ; .dw 0xC40D ; .dw 0x8FC0 ; .dw 0xC40D ; .dw 0xC000 ; .dw 0xC40D ; .dw 0xC240 ; .dw 0xC40D ; .dw 0xC480 ; .dw 0xC40D ; .dw 0xC6C0 ; .dw 0xC40D ; .dw 0xC900 ; .dw 0xC40D ; .dw 0xCB40 ; .dw 0xC40D ; .dw 0xCD80 ; .dw 0xC40D ; .dw 0xCFC0 ; .dw 0xC411 ; .dw 0x0 ; .dw 0xC411 ; .dw 0x240 ; .dw 0xC411 ; .dw 0x480 ; .dw 0xC411 ; .dw 0x6C0 ; .dw 0xC411 ; .dw 0x900 ; .dw 0xC411 ; .dw 0xB40 ; .dw 0xC411 ; .dw 0xD80 ; .dw 0xC411 ; .dw 0xFC0 ; .dw 0xC411 ; .dw 0x4000 ; .dw 0xC411 ; .dw 0x4240 ; .dw 0xC411 ; .dw 0x4480 ; .dw 0xC411 ; .dw 0x46C0 ; .dw 0xC411 ; .dw 0x4900 ; .dw 0xC411 ; .dw 0x4B40 ; .dw 0xC411 ; .dw 0x4D80 ; .dw 0xC411 ; .dw 0x4FC0 ; .dw 0xC415 ; .dw 0x0 ; .dw 0xC415 ; .dw 0x240 ; .dw 0xC415 ; .dw 0x480 ; .dw 0xC415 ; .dw 0x6C0 ; .dw 0xC415 ; .dw 0x900 ; .dw 0xC415 ; .dw 0xB40 ; .dw 0xC415 ; .dw 0xD80 ; .dw 0xC415 ; .dw 0xFC0 ; .dw 0xC415 ; .dw 0x4000 ; .dw 0xC415 ; .dw 0x4240 ; .dw 0xC415 ; .dw 0x4480 ; .dw 0xC415 ; .dw 0x46C0 ; .dw 0xC415 ; .dw 0x4900 ; .dw 0xC415 ; .dw 0x4B40 ; .dw 0xC415 ; .dw 0x4D80 ; .dw 0xC415 ; .dw 0x4FC0 ; .dw 0xC418 ; .dw 0x4000 ; .dw 0xC418 ; .dw 0x4240 ; .dw 0xC418 ; .dw 0x4480 ; .dw 0xC418 ; .dw 0x46C0 ; .dw 0xC418 ; .dw 0x4900 ; .dw 0xC418 ; .dw 0x4B40 ; .dw 0xC418 ; .dw 0x4D80 ; .dw 0xC418 ; .dw 0x4FC0 ; .dw 0xC412 ; .dw 0x9 ; .dw 0xC412 ; .dw 0x1B ; .dw 0xC412 ; .dw 0x24 ; .dw 0xC412 ; .dw 0x2D ; .dw 0xC412 ; .dw 0x36 ; .dw 0xC412 ; .dw 0x3F ; .dw 0xC414 ; .dw 0x9 ; .dw 0xC414 ; .dw 0x1B ; .dw 0xC414 ; .dw 0x24 ; .dw 0xC414 ; .dw 0x2D ; .dw 0xC414 ; .dw 0x36 ; .dw 0xC414 ; .dw 0x3F ; .dw 0xC414 ; .dw 0x4009 ; .dw 0xC414 ; .dw 0x401B ; .dw 0xC414 ; .dw 0x4024 ; .dw 0xC414 ; .dw 0x402D ; .dw 0xC414 ; .dw 0x4036 ; .dw 0xC414 ; .dw 0x403F ; .dw 0xC415 ; .dw 0x9 ; .dw 0xC415 ; .dw 0x1B ; .dw 0xC415 ; .dw 0x24 ; .dw 0xC415 ; .dw 0x2D ; .dw 0xC415 ; .dw 0x36 ; .dw 0xC415 ; .dw 0x3F ; .dw 0xC415 ; .dw 0x4009 ; .dw 0xC415 ; .dw 0x401B ; .dw 0xC415 ; .dw 0x4024 ; .dw 0xC415 ; .dw 0x402D ; .dw 0xC415 ; .dw 0x4036 ; .dw 0xC415 ; .dw 0x403F ; .dw 0xC416 ; .dw 0x9 ; .dw 0xC416 ; .dw 0x1B ; .dw 0xC416 ; .dw 0x24 ; .dw 0xC416 ; .dw 0x2D ; .dw 0xC416 ; .dw 0x36 ; .dw 0xC416 ; .dw 0x3F ; .dw 0xC416 ; .dw 0x4009 ; .dw 0xC416 ; .dw 0x401B ; .dw 0xC416 ; .dw 0x4024 ; .dw 0xC416 ; .dw 0x402D ; .dw 0xC416 ; .dw 0x4036 ; .dw 0xC416 ; .dw 0x403F ; .dw 0xC416 ; .dw 0x8009 ; .dw 0xC416 ; .dw 0x801B ; .dw 0xC416 ; .dw 0x8024 ; .dw 0xC416 ; .dw 0x802D ; .dw 0xC416 ; .dw 0x8036 ; .dw 0xC416 ; .dw 0x803F ; .dw 0xC416 ; .dw 0xC009 ; .dw 0xC416 ; .dw 0xC01B ; .dw 0xC416 ; .dw 0xC024 ; .dw 0xC416 ; .dw 0xC02D ; .dw 0xC416 ; .dw 0xC036 ; .dw 0xC416 ; .dw 0xC03F ; .dw 0xC417 ; .dw 0x9 ; .dw 0xC417 ; .dw 0x1B ; .dw 0xC417 ; .dw 0x24 ; .dw 0xC417 ; .dw 0x2D ; .dw 0xC417 ; .dw 0x36 ; .dw 0xC417 ; .dw 0x3F ; .dw 0xC418 ; .dw 0x4009 ; .dw 0xC418 ; .dw 0x401B ; .dw 0xC418 ; .dw 0x4024 ; .dw 0xC418 ; .dw 0x402D ; .dw 0xC418 ; .dw 0x4036 ; .dw 0xC418 ; .dw 0x403F ; .dw 0xC600 ; .dw 0xC000 ; .dw 0xC601 ; .dw 0xC000 ; .dw 0xC603 ; .dw 0xC000 ; .dw 0xC605 ; .dw 0xC000 ; .dw 0xC608 ; .dw 0xC000 ; .dw 0xC60B ; .dw 0xC000 ; .dw 0xC60C ; .dw 0xC000 ; .dw 0xC60D ; .dw 0xC000 ; .dw 0xC606 ; .dw 0x8000 ; .dw 0xC608 ; .dw 0x8000 ; .dw 0xC60B ; .dw 0x8000 ; .dw 0xC60C ; .dw 0x8000 ; .dw 0xC60E ; .dw 0x0 ; .dw 0xC60E ; .dw 0x4000 ; .dw 0xC60E ; .dw 0x8000 ; .dw 0xC60E ; .dw 0xC000 ; .dw 0xC60F ; .dw 0x0 ; .dw 0xC60F ; .dw 0x4000 ; .dw 0xC60F ; .dw 0x8000 ; .dw 0xC60F ; .dw 0xC000 ; .dw 0xC610 ; .dw 0x0 ; .dw 0xC610 ; .dw 0x4000 ; .dw 0xC610 ; .dw 0x8000 ; .dw 0xC610 ; .dw 0xC000 ; .dw 0xC611 ; .dw 0x0 ; .dw 0xC611 ; .dw 0x4000 ; .dw 0xC611 ; .dw 0x8000 ; .dw 0xC611 ; .dw 0xC000 ; .dw 0xC612 ; .dw 0x0 ; .dw 0xC612 ; .dw 0x4000 ; .dw 0xC612 ; .dw 0x8000 ; .dw 0xC612 ; .dw 0xC000 ; .dw 0xC613 ; .dw 0x0 ; .dw 0xC613 ; .dw 0x4000 ; .dw 0xC613 ; .dw 0x8000 ; .dw 0xC613 ; .dw 0xC000 ; .dw 0xC614 ; .dw 0x0 ; .dw 0xC614 ; .dw 0x4000 ; .dw 0xC614 ; .dw 0x8000 ; .dw 0xC614 ; .dw 0xC000 ; .dw 0xC615 ; .dw 0x0 ; .dw 0xC615 ; .dw 0x4000 ; .dw 0xC615 ; .dw 0x8000 ; .dw 0xC615 ; .dw 0xC000 ; .dw 0xC616 ; .dw 0x0 ; .dw 0xC616 ; .dw 0x4000 ; .dw 0xC616 ; .dw 0x8000 ; .dw 0xC616 ; .dw 0xC000 ; .dw 0xC617 ; .dw 0x0 ; .dw 0xC617 ; .dw 0x4000 ; .dw 0xC617 ; .dw 0x8000 ; .dw 0xC617 ; .dw 0xC000 ; .dw 0xC618 ; .dw 0x0 ; .dw 0xC618 ; .dw 0x4000 ; .dw 0xC618 ; .dw 0x8000 ; .dw 0xC618 ; .dw 0xC000 ; .dw 0xC619 ; .dw 0x0 ; .dw 0xC619 ; .dw 0x4000 ; .dw 0xC619 ; .dw 0x8000 ; .dw 0xC619 ; .dw 0xC000 ; .dw 0xC61A ; .dw 0x0 ; .dw 0xC61A ; .dw 0x4000 ; .dw 0xC61A ; .dw 0x8000 ; .dw 0xC61A ; .dw 0xC000 ; .dw 0xC61B ; .dw 0x0 ; .dw 0xC61B ; .dw 0x4000 ; .dw 0xC61B ; .dw 0x8000 ; .dw 0xC61B ; .dw 0xC000 ; .dw 0xC61C ; .dw 0x0 ; .dw 0xC61C ; .dw 0x4000 ; .dw 0xC61C ; .dw 0x8000 ; .dw 0xC61C ; .dw 0xC000 ; .dw 0xC61D ; .dw 0x0 ; .dw 0xC61D ; .dw 0x4000 ; .dw 0xC61D ; .dw 0x8000 ; .dw 0xC61D ; .dw 0xC000 ; .dw 0xC61E ; .dw 0x0 ; .dw 0xC61E ; .dw 0x4000 ; .dw 0xC61E ; .dw 0x8000 ; .dw 0xC61E ; .dw 0xC000 ; .dw 0xC61F ; .dw 0x0 ; .dw 0xC61F ; .dw 0x4000 ; .dw 0xC61F ; .dw 0x8000 ; .dw 0xC61F ; .dw 0xC000 ; .dw 0xC608 ; .dw 0x0 ; .dw 0xC608 ; .dw 0x9 ; .dw 0xC608 ; .dw 0x12 ; .dw 0xC608 ; .dw 0x1B ; .dw 0xC608 ; .dw 0x24 ; .dw 0xC608 ; .dw 0x2D ; .dw 0xC608 ; .dw 0x36 ; .dw 0xC608 ; .dw 0x3F ; .dw 0xC608 ; .dw 0x4000 ; .dw 0xC608 ; .dw 0x4009 ; .dw 0xC608 ; .dw 0x4012 ; .dw 0xC608 ; .dw 0x401B ; .dw 0xC608 ; .dw 0x4024 ; .dw 0xC608 ; .dw 0x402D ; .dw 0xC608 ; .dw 0x4036 ; .dw 0xC608 ; .dw 0x403F ; .dw 0xC680 ; .dw 0xC000 ; .dw 0xC681 ; .dw 0xC000 ; .dw 0xC683 ; .dw 0xC000 ; .dw 0xC684 ; .dw 0x0 ; .dw 0xC684 ; .dw 0x4000 ; .dw 0xC684 ; .dw 0x8000 ; .dw 0xC684 ; .dw 0xC000 ; .dw 0xC685 ; .dw 0x0 ; .dw 0xC685 ; .dw 0x4000 ; .dw 0xC685 ; .dw 0x8000 ; .dw 0xC685 ; .dw 0xC000 ; .dw 0xC686 ; .dw 0x0 ; .dw 0xC686 ; .dw 0x4000 ; .dw 0xC686 ; .dw 0x8000 ; .dw 0xC686 ; .dw 0xC000 ; .dw 0xC687 ; .dw 0x0 ; .dw 0xC687 ; .dw 0x4000 ; .dw 0xC687 ; .dw 0x8000 ; .dw 0xC687 ; .dw 0xC000 ; .dw 0xC688 ; .dw 0x0 ; .dw 0xC688 ; .dw 0x4000 ; .dw 0xC688 ; .dw 0x8000 ; .dw 0xC688 ; .dw 0xC000 ; .dw 0xC689 ; .dw 0x0 ; .dw 0xC689 ; .dw 0x4000 ; .dw 0xC689 ; .dw 0x8000 ; .dw 0xC689 ; .dw 0xC000 ; .dw 0xC68A ; .dw 0x0 ; .dw 0xC68A ; .dw 0x4000 ; .dw 0xC68A ; .dw 0x8000 ; .dw 0xC68A ; .dw 0xC000 ; .dw 0xC68B ; .dw 0x0 ; .dw 0xC68B ; .dw 0x4000 ; .dw 0xC68B ; .dw 0x8000 ; .dw 0xC68B ; .dw 0xC000 ; .dw 0xC68C ; .dw 0x0 ; .dw 0xC68C ; .dw 0x4000 ; .dw 0xC68C ; .dw 0x8000 ; .dw 0xC68C ; .dw 0xC000 ; .dw 0xC68D ; .dw 0x0 ; .dw 0xC68D ; .dw 0x4000 ; .dw 0xC68D ; .dw 0x8000 ; .dw 0xC68D ; .dw 0xC000 ; .dw 0xC68E ; .dw 0x0 ; .dw 0xC68E ; .dw 0x4000 ; .dw 0xC68E ; .dw 0x8000 ; .dw 0xC68E ; .dw 0xC000 ; .dw 0xC68F ; .dw 0x0 ; .dw 0xC68F ; .dw 0x4000 ; .dw 0xC68F ; .dw 0x8000 ; .dw 0xC68F ; .dw 0xC000 ; .dw 0xC690 ; .dw 0x0 ; .dw 0xC690 ; .dw 0x4000 ; .dw 0xC690 ; .dw 0x8000 ; .dw 0xC690 ; .dw 0xC000 ; .dw 0xC691 ; .dw 0x0 ; .dw 0xC691 ; .dw 0x4000 ; .dw 0xC691 ; .dw 0x8000 ; .dw 0xC691 ; .dw 0xC000 ; .dw 0xC692 ; .dw 0x0 ; .dw 0xC692 ; .dw 0x4000 ; .dw 0xC692 ; .dw 0x8000 ; .dw 0xC692 ; .dw 0xC000 ; .dw 0xC693 ; .dw 0x0 ; .dw 0xC693 ; .dw 0x4000 ; .dw 0xC693 ; .dw 0x8000 ; .dw 0xC693 ; .dw 0xC000 ; .dw 0xC694 ; .dw 0x0 ; .dw 0xC694 ; .dw 0x4000 ; .dw 0xC694 ; .dw 0x8000 ; .dw 0xC694 ; .dw 0xC000 ; .dw 0xC695 ; .dw 0x0 ; .dw 0xC695 ; .dw 0x4000 ; .dw 0xC695 ; .dw 0x8000 ; .dw 0xC695 ; .dw 0xC000 ; .dw 0xC696 ; .dw 0x0 ; .dw 0xC696 ; .dw 0x4000 ; .dw 0xC696 ; .dw 0x8000 ; .dw 0xC696 ; .dw 0xC000 ; .dw 0xC697 ; .dw 0x0 ; .dw 0xC697 ; .dw 0x4000 ; .dw 0xC697 ; .dw 0x8000 ; .dw 0xC697 ; .dw 0xC000 ; .dw 0xC698 ; .dw 0x0 ; .dw 0xC698 ; .dw 0x4000 ; .dw 0xC698 ; .dw 0x8000 ; .dw 0xC698 ; .dw 0xC000 ; .dw 0xC699 ; .dw 0x0 ; .dw 0xC699 ; .dw 0x4000 ; .dw 0xC699 ; .dw 0x8000 ; .dw 0xC699 ; .dw 0xC000 ; .dw 0xC69A ; .dw 0x0 ; .dw 0xC69A ; .dw 0x4000 ; .dw 0xC69A ; .dw 0x8000 ; .dw 0xC69A ; .dw 0xC000 ; .dw 0xC69B ; .dw 0x0 ; .dw 0xC69B ; .dw 0x4000 ; .dw 0xC69B ; .dw 0x8000 ; .dw 0xC69B ; .dw 0xC000 ; .dw 0xC69C ; .dw 0x0 ; .dw 0xC69C ; .dw 0x4000 ; .dw 0xC69C ; .dw 0x8000 ; .dw 0xC69C ; .dw 0xC000 ; .dw 0xC69D ; .dw 0x0 ; .dw 0xC69D ; .dw 0x4000 ; .dw 0xC69D ; .dw 0x8000 ; .dw 0xC69D ; .dw 0xC000 ; .dw 0xC69E ; .dw 0x0 ; .dw 0xC69E ; .dw 0x4000 ; .dw 0xC69E ; .dw 0x8000 ; .dw 0xC69E ; .dw 0xC000 ; .dw 0xC69F ; .dw 0x0 ; .dw 0xC69F ; .dw 0x4000 ; .dw 0xC69F ; .dw 0x8000 ; .dw 0xC69F ; .dw 0xC000 ; .dw 0xC008 ; .dw 0x0 ; .dw 0xC008 ; .dw 0x40 ; .dw 0xC008 ; .dw 0xC0 ; .dw 0xC008 ; .dw 0x140 ; .dw 0xC008 ; .dw 0x1C0 ; .dw 0xC020 ; .dw 0x0 ; .dw 0xC040 ; .dw 0x0 ; .dw 0xC0A0 ; .dw 0x0 ; .dw 0xC0C0 ; .dw 0x0 ; .dw 0xC0E0 ; .dw 0x0 ; .dw 0xC120 ; .dw 0x0 ; .dw 0xC140 ; .dw 0x0 ; .dw 0xC160 ; .dw 0x0 ; .dw 0xC180 ; .dw 0x0 ; .dw 0xC1A0 ; .dw 0x0 ; .dw 0xC1C0 ; .dw 0x0 ; .dw 0xC1E0 ; .dw 0x0 ; .dw 0xC060 ; .dw 0x2000 ; .dw 0xC0E0 ; .dw 0x2000 ; .dw 0xC140 ; .dw 0x2000 ; .dw 0xC1A0 ; .dw 0x2000 ; .dw 0xC1C0 ; .dw 0x2000 ; .dw 0xC1E0 ; .dw 0x2000 ; .dw 0xC064 ; .dw 0x0 ; .dw 0xC0E4 ; .dw 0x0 ; .dw 0xC144 ; .dw 0x0 ; .dw 0xC1A4 ; .dw 0x0 ; .dw 0xC1C4 ; .dw 0x0 ; .dw 0xC1E4 ; .dw 0x0 ; .dw 0xC064 ; .dw 0x2000 ; .dw 0xC0E4 ; .dw 0x2000 ; .dw 0xC144 ; .dw 0x2000 ; .dw 0xC1A4 ; .dw 0x2000 ; .dw 0xC1C4 ; .dw 0x2000 ; .dw 0xC1E4 ; .dw 0x2000 ; .dw 0xC048 ; .dw 0x2000 ; .dw 0xC068 ; .dw 0x2000 ; .dw 0xC0A8 ; .dw 0x2000 ; .dw 0xC0C8 ; .dw 0x2000 ; .dw 0xC0E8 ; .dw 0x2000 ; .dw 0xC148 ; .dw 0x2000 ; .dw 0xC168 ; .dw 0x2000 ; .dw 0xC188 ; .dw 0x2000 ; .dw 0xC1A8 ; .dw 0x2000 ; .dw 0xC1C8 ; .dw 0x2000 ; .dw 0xC1E8 ; .dw 0x2000 ; .dw 0xC04C ; .dw 0x0 ; .dw 0xC06C ; .dw 0x0 ; .dw 0xC0AC ; .dw 0x0 ; .dw 0xC0CC ; .dw 0x0 ; .dw 0xC0EC ; .dw 0x0 ; .dw 0xC14C ; .dw 0x0 ; .dw 0xC16C ; .dw 0x0 ; .dw 0xC18C ; .dw 0x0 ; .dw 0xC1AC ; .dw 0x0 ; .dw 0xC1CC ; .dw 0x0 ; .dw 0xC1EC ; .dw 0x0 ; .dw 0xC04C ; .dw 0x2000 ; .dw 0xC06C ; .dw 0x2000 ; .dw 0xC0AC ; .dw 0x2000 ; .dw 0xC0CC ; .dw 0x2000 ; .dw 0xC0EC ; .dw 0x2000 ; .dw 0xC14C ; .dw 0x2000 ; .dw 0xC16C ; .dw 0x2000 ; .dw 0xC18C ; .dw 0x2000 ; .dw 0xC1AC ; .dw 0x2000 ; .dw 0xC1CC ; .dw 0x2000 ; .dw 0xC1EC ; .dw 0x2000 ; .dw 0xC20C ; .dw 0x2040 ; .dw 0xC20C ; .dw 0x20C0 ; .dw 0xC20C ; .dw 0x2140 ; .dw 0xC20C ; .dw 0x21C0 ; .dw 0xC248 ; .dw 0x2000 ; .dw 0xC268 ; .dw 0x2000 ; .dw 0xC2A8 ; .dw 0x2000 ; .dw 0xC2C8 ; .dw 0x2000 ; .dw 0xC2E8 ; .dw 0x2000 ; .dw 0xC348 ; .dw 0x2000 ; .dw 0xC368 ; .dw 0x2000 ; .dw 0xC388 ; .dw 0x2000 ; .dw 0xC3A8 ; .dw 0x2000 ; .dw 0xC3C8 ; .dw 0x2000 ; .dw 0xC3E8 ; .dw 0x2000 ; .dw 0xC24C ; .dw 0x0 ; .dw 0xC26C ; .dw 0x0 ; .dw 0xC2AC ; .dw 0x0 ; .dw 0xC2CC ; .dw 0x0 ; .dw 0xC2EC ; .dw 0x0 ; .dw 0xC34C ; .dw 0x0 ; .dw 0xC36C ; .dw 0x0 ; .dw 0xC38C ; .dw 0x0 ; .dw 0xC3AC ; .dw 0x0 ; .dw 0xC3CC ; .dw 0x0 ; .dw 0xC3EC ; .dw 0x0 ; .dw 0xC24C ; .dw 0x2000 ; .dw 0xC26C ; .dw 0x2000 ; .dw 0xC2AC ; .dw 0x2000 ; .dw 0xC2CC ; .dw 0x2000 ; .dw 0xC2EC ; .dw 0x2000 ; .dw 0xC34C ; .dw 0x2000 ; .dw 0xC36C ; .dw 0x2000 ; .dw 0xC38C ; .dw 0x2000 ; .dw 0xC3AC ; .dw 0x2000 ; .dw 0xC3CC ; .dw 0x2000 ; .dw 0xC3EC ; .dw 0x2000 ; .dw 0xC20D ; .dw 0x2800 ; .dw 0xC20E ; .dw 0x2800 ; .dw 0xC20F ; .dw 0x2800 ; .dw 0xC20D ; .dw 0x3000 ; .dw 0xC20E ; .dw 0x3000 ; .dw 0xC20F ; .dw 0x3000 ; .dw 0xC20D ; .dw 0x3800 ; .dw 0xC20E ; .dw 0x3800 ; .dw 0xC20F ; .dw 0x3800 ; .dw 0xC200 ; .dw 0x0 ; .dw 0xC264 ; .dw 0x2000 ; CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); // Xhandler counts all EXCAUSE = 0x21; CHECKREG(r5, 2871); // count of all 16 bit UI's. END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // NHANDLE: // NMI Handler 2 RTN; XHANDLE: // Exception Handler 3 // 32 bit illegal opcode handler - skips bad instruction // handler MADE LEAN and destructive so test runs more quckly // se_undefinedinstruction1.dsp tests using a "nice" handler // [--sp] = ASTAT; // save what we damage // [--sp] = (r7 - r6); R7 = SEQSTAT; R7 <<= 26; R7 >>= 26; // only want EXCAUSE R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction CC = r7 == r6; IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave // Also allow 0x22 for illegal instruction combinations (parallel) R6 = 0x22; CC = r7 == r6; IF CC JUMP UNDEFINEDINSTRUCTION; dbg_fail; UNDEFINEDINSTRUCTION: R7 = RETX; // Fix up return address R7 += 4; // skip offending 32 bit instruction RETX = r7; // and put back in RETX R5 += 1; // Increment global counter OUT: // (r7 - r6) = [sp++]; // ASTAT = [sp++]; RTX; HWHANDLE: // HW Error Handler 5 RTI; THANDLE: // Timer Handler 6 RTI; I7HANDLE: // IVG 7 Handler RTI; I8HANDLE: // IVG 8 Handler RTI; I9HANDLE: // IVG 9 Handler RTI; I10HANDLE: // IVG 10 Handler RTI; I11HANDLE: // IVG 11 Handler RTI; I12HANDLE: // IVG 12 Handler RTI; I13HANDLE: // IVG 13 Handler RTI; I14HANDLE: // IVG 14 Handler RTI; I15HANDLE: // IVG 15 Handler RTI; // padding for the icache EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; // // Data Segment // .data DATA: .space (0x10); // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	6,382	sim/testsuite/bfin/random_0026.S	# mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x4c60c810 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0x7fffffff; dmm32 A0.x, 0x00000000; imm32 R0, 0x00000000; imm32 R5, 0x00007fff; imm32 R7, 0x00000000; R7.L = (A0 += R0.L * R5.L) (IH); checkreg R7, 0x00007fff; checkreg A0.w, 0x7fffffff; checkreg A0.x, 0x00000000; checkreg ASTAT, (0x4c60c810 \| _VS \| _V \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x00500680 \| _VS \| _AV0S \| _AV0 \| _AC0 \| _AC0_COPY \| _AN); dmm32 A0.w, 0x80000000; dmm32 A0.x, 0xffffffff; imm32 R2, 0xffffffff; imm32 R4, 0xa8dd8000; imm32 R7, 0x80000000; R4.L = (A0 -= R2.L * R7.H) (IH); checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg R4, 0xa8dd8000; checkreg ASTAT, (0x00500680 \| _VS \| _AV0S \| _AV0 \| _AC0 \| _AC0_COPY \| _AN); dmm32 ASTAT, (0x50408c90 \| _VS \| _V \| _AV1S \| _AV0 \| _AC0 \| _AQ \| _CC \| _V_COPY \| _AN); dmm32 A1.w, 0xfa400000; dmm32 A1.x, 0xffffffad; imm32 R0, 0x366b1c84; imm32 R3, 0x7fffffff; imm32 R7, 0x32528aa5; R3.H = (A1 += R0.L * R7.L) (M, IH); checkreg R3, 0x8000ffff; checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x50408c90 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0 \| _AC0 \| _AQ \| _CC \| _V_COPY \| _AN); dmm32 ASTAT, (0x0c400c10 \| _VS \| _V \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _V_COPY \| _AC0_COPY \| _AN); dmm32 A1.w, 0xef56cbd3; dmm32 A1.x, 0x00000000; imm32 R3, 0x7fff0003; imm32 R4, 0x385cffff; imm32 R7, 0x680dffff; R7.H = (A1 -= R4.L * R3.H) (M, IH); checkreg R7, 0x7fffffff; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x0c400c10 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _V_COPY \| _AC0_COPY \| _AN); dmm32 ASTAT, (0x2c604c00 \| _AV1S \| _AV0 \| _AC1); dmm32 A1.w, 0xf54ee9bb; dmm32 A1.x, 0x0000004a; imm32 R3, 0x10bb4bdc; imm32 R4, 0x7f29c57d; imm32 R7, 0x2c03f00a; R4.H = (A1 -= R3.L * R7.H) (M, IH); checkreg R4, 0x7fffc57d; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x2c604c00 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0 \| _AC1 \| _V_COPY); dmm32 ASTAT, (0x2c304800 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _V_COPY); dmm32 A1.w, 0xc1a6b608; dmm32 A1.x, 0x00000056; imm32 R2, 0xd0457fff; imm32 R6, 0xf4b2ffff; R6.H = (A1 += R2.L * R6.H) (M, IH); checkreg R6, 0x7fffffff; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x2c304800 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _V_COPY); dmm32 ASTAT, (0x04a08810 \| _VS \| _AV1S \| _AC1 \| _AC0 \| _AN); dmm32 A1.w, 0xe9574334; dmm32 A1.x, 0x00000056; imm32 R3, 0xffffb2bc; imm32 R5, 0x03eb4d44; imm32 R6, 0x33852750; R5.H = (A1 -= R6.L * R3.L) (M, IH); checkreg R5, 0x7fff4d44; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x04a08810 \| _VS \| _V \| _AV1S \| _AV1 \| _AC1 \| _AC0 \| _V_COPY \| _AN); dmm32 ASTAT, (0x5860c210 \| _VS \| _V \| _AV1S \| _AC1 \| _AQ \| _V_COPY); dmm32 A1.w, 0xd5030654; dmm32 A1.x, 0x0000001c; imm32 R0, 0x20ccb6ee; imm32 R2, 0x74c21675; imm32 R4, 0x7fff7fff; R2.H = (A1 -= R0.L * R4.L) (M, IH); checkreg R2, 0x7fff1675; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x5860c210 \| _VS \| _V \| _AV1S \| _AV1 \| _AC1 \| _AQ \| _V_COPY); dmm32 ASTAT, (0x34800e00 \| _VS \| _AV1S \| _AV0S \| _AQ \| _CC \| _AC0_COPY \| _AN); dmm32 A1.w, 0xf0b59d3f; dmm32 A1.x, 0xffffffef; imm32 R4, 0x28bd7772; imm32 R6, 0xef66ce6a; imm32 R7, 0x80000000; R6.H = (A1 -= R4.L * R7.H) (M, IH); checkreg R6, 0x8000ce6a; checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x34800e00 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _CC \| _V_COPY \| _AC0_COPY \| _AN); dmm32 ASTAT, (0x5c804a90 \| _VS \| _AV1S \| _AV0S \| _AQ \| _AN); dmm32 A1.w, 0xc90d8c2f; dmm32 A1.x, 0xffffffee; imm32 R0, 0x80006a2f; imm32 R3, 0x80000000; R3.H = (A1 += R0.L * R0.H) (M, IH); checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x5c804a90 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _V_COPY \| _AN); dmm32 ASTAT, (0x5c90c010 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _CC \| _V_COPY \| _AN); dmm32 A1.w, 0x80ca2186; dmm32 A1.x, 0x00000000; imm32 R1, 0xf3ec0000; imm32 R3, 0x5a859a0a; imm32 R6, 0x19e852d9; R3.H = (A1 -= R1.L * R6.L) (M, IH); checkreg R3, 0x7fff9a0a; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x5c90c010 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AC0 \| _CC \| _V_COPY \| _AN); dmm32 ASTAT, (0x00f00a10 \| _VS \| _V \| _AV0S \| _CC \| _V_COPY \| _AN); dmm32 A1.w, 0x9f5baab0; dmm32 A1.x, 0x00000019; imm32 R1, 0x1bb2489b; imm32 R6, 0x0aa80127; R1.H = (A1 -= R6.L * R6.H) (M, IH); checkreg R1, 0x7fff489b; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x00f00a10 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _CC \| _V_COPY \| _AN); dmm32 ASTAT, (0x3c808210 \| _VS \| _V \| _AV1S \| _V_COPY \| _AN); dmm32 A1.w, 0xe09f1e24; dmm32 A1.x, 0x00000025; imm32 R1, 0x255b55bc; imm32 R2, 0x7f1bd115; imm32 R3, 0xbc978902; R2.H = (A1 -= R3.L * R1.H) (M, IH); checkreg R2, 0x7fffd115; checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x3c808210 \| _VS \| _V \| _AV1S \| _AV1 \| _V_COPY \| _AN); dmm32 ASTAT, (0x1ca04600 \| _VS \| _V \| _AV0S \| _V_COPY \| _AC0_COPY); dmm32 A1.w, 0xb80e1ddd; dmm32 A1.x, 0xffffffca; imm32 R0, 0x2155a4b5; imm32 R1, 0x5dd905c2; imm32 R2, 0x769083dc; R1.H = (A1 -= R2.L * R0.H) (M, IH); checkreg R1, 0x800005c2; checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x1ca04600 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x1cb0cc90 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _V_COPY \| _AC0_COPY \| _AN); dmm32 A1.w, 0xfc7c3973; dmm32 A1.x, 0xffffff8a; imm32 R1, 0x58a6c4e7; imm32 R4, 0x19b16033; imm32 R6, 0x301ff2ba; R6.H = (A1 -= R4.L * R1.H) (M, IH); checkreg R6, 0x8000f2ba; checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x1cb0cc90 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _V_COPY \| _AC0_COPY \| _AN); dmm32 ASTAT, (0x2c800810 \| _VS \| _AV1S \| _AQ \| _CC \| _AN); dmm32 A1.w, 0xd86a7676; dmm32 A1.x, 0xffffff97; imm32 R3, 0x443fea83; imm32 R4, 0x47ed4ac3; imm32 R6, 0x7fffffff; R4.H = (A1 += R3.L * R6.L) (M, IH); checkreg R4, 0x80004ac3; checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x2c800810 \| _VS \| _V \| _AV1S \| _AV1 \| _AQ \| _CC \| _V_COPY \| _AN); pass
tactcomplabs/xbgas-binutils-gdb	10,134	sim/testsuite/bfin/random_0036.S	# mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x3ce04490 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0x7d8d8272; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xe0004138; dmm32 A1.x, 0x0000007f; imm32 R0, 0x7d8e7fff; imm32 R2, 0xffff8001; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xfd8c0273; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x3ce04490 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x70b0c800 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _V_COPY \| _AC0_COPY); dmm32 A0.w, 0x53931540; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xf07795da; dmm32 A1.x, 0x0000007f; imm32 R2, 0x8931da0a; imm32 R4, 0xffff41eb; imm32 R5, 0x7fff41eb; A1 += R5.L * R4.H (M), R2 = (A0 -= R5.L * R4.H) (FU); checkreg R2, 0x11a8572b; checkreg A0.w, 0x11a8572b; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x70b0c800 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY); dmm32 ASTAT, (0x58100410 \| _VS \| _V \| _AV1S \| _AC0 \| _CC \| _V_COPY \| _AC0_COPY); dmm32 A0.w, 0xaeba0d61; dmm32 A0.x, 0x00000041; dmm32 A1.w, 0xbb313d2f; dmm32 A1.x, 0x0000007f; imm32 R4, 0x1ea2588d; imm32 R7, 0xffffffff; A1 += R4.L * R7.H (M), A0 += R4.L * R7.L (FU); checkreg A0.w, 0x0746b4d4; checkreg A0.x, 0x00000042; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x58100410 \| _VS \| _V \| _AV1S \| _AV1 \| _AC0 \| _CC \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x58704200 \| _VS \| _AV1S \| _AV0S); dmm32 A0.w, 0xb7ab4854; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xe0002429; dmm32 A1.x, 0x0000007f; imm32 R0, 0xb7ac8000; imm32 R2, 0x80008001; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xf7ab4854; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x58704200 \| _VS \| _AV1S \| _AV1 \| _AV0S); dmm32 ASTAT, (0x38d0c800 \| _VS \| _AV1S \| _AV0S); dmm32 A0.w, 0xfffe0001; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xffff4001; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R2, 0xffffffff; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xfffc0002; checkreg A0.x, 0x00000001; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x38d0c800 \| _VS \| _AV1S \| _AV1 \| _AV0S); dmm32 ASTAT, (0x24e0ca80 \| _VS \| _V \| _AV0S \| _AC0 \| _AQ \| _V_COPY); dmm32 A0.w, 0x0000000a; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xff5439dc; dmm32 A1.x, 0x0000007f; imm32 R0, 0x3ea961c5; imm32 R6, 0xffff0510; A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x24e0ca80 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AV0 \| _AC0 \| _AQ \| _V_COPY); dmm32 ASTAT, (0x7800cc80 \| _VS \| _AC1 \| _AC0 \| _CC \| _AC0_COPY); dmm32 A0.w, 0xfffe0001; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xffff4001; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R2, 0x0000ffff; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x7800cc80 \| _VS \| _AV1S \| _AV1 \| _AC1 \| _AC0 \| _CC \| _AC0_COPY); dmm32 ASTAT, (0x50200800 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY); dmm32 A0.w, 0x6970968f; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xe0004b47; dmm32 A1.x, 0x0000007f; imm32 R0, 0x69717fff; imm32 R2, 0xffff8001; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xe96f1690; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x50200800 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY); dmm32 ASTAT, (0x34704080 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _CC \| _AC0_COPY); dmm32 A0.w, 0x0839a708; dmm32 A0.x, 0xffffff80; dmm32 A1.w, 0xffffffff; dmm32 A1.x, 0x0000007f; imm32 R0, 0x0c8c109a; imm32 R2, 0x109a0c8c; imm32 R5, 0x006dd6ac; A1 -= R5.L * R0.L (M), R2.L = (A0 += R5.H * R0.L) (FU); checkreg R2, 0x109affff; checkreg A0.w, 0x0840b89a; checkreg A0.x, 0xffffff80; checkreg ASTAT, (0x34704080 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _CC \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x78108090 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0x21edde12; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xe0006f08; dmm32 A1.x, 0x0000007f; imm32 R0, 0x21ee7fff; imm32 R2, 0xffff8001; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xa1ec5e13; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x78108090 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x50b08a10 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _V_COPY \| _AC0_COPY); dmm32 A0.w, 0x00000007; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xf8b109fc; dmm32 A1.x, 0x0000007f; imm32 R0, 0x27827703; imm32 R6, 0xffff03ca; A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x50b08a10 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AV0 \| _AC1 \| _AC0 \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x34e0c800 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _V_COPY); dmm32 A0.w, 0xffffffff; dmm32 A0.x, 0xffffffff; dmm32 A1.w, 0xefc2be42; dmm32 A1.x, 0x0000007f; imm32 R0, 0x53574850; imm32 R6, 0xffff1400; A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); checkreg A0.w, 0xaca95356; checkreg A0.x, 0xffffffff; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x34e0c800 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _V_COPY); dmm32 ASTAT, (0x24608c80 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0x0f03f0fc; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xe000787d; dmm32 A1.x, 0x0000007f; imm32 R0, 0x0f04ffff; imm32 R2, 0xffff8001; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0x0f01f0fd; checkreg A0.x, 0x00000001; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x24608c80 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x58404690 \| _VS \| _AV0S \| _AC0 \| _AQ \| _CC \| _AC0_COPY); dmm32 A0.w, 0x1e65e19a; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xe00070cc; dmm32 A1.x, 0x0000007f; imm32 R0, 0x1e66ffff; imm32 R2, 0xffff8001; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0x1e63e19b; checkreg A0.x, 0x00000001; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x58404690 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC0 \| _AQ \| _CC \| _AC0_COPY); dmm32 ASTAT, (0x08004a10 \| _VS \| _AV1S \| _AV1 \| _AC0 \| _CC \| _AC0_COPY); dmm32 A1.w, 0xffffffff; dmm32 A1.x, 0x0000007f; imm32 R0, 0x293a8000; imm32 R3, 0xd0e6382b; A1 += R3.L * R0.H (M, FU); checkreg ASTAT, (0x08004a10 \| _VS \| _AV1S \| _AV1 \| _AC0 \| _CC \| _AC0_COPY); checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg R0, 0x293a8000; checkreg R3, 0xd0e6382b; dmm32 ASTAT, (0x28e00e00 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0xfffe0001; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xffff4001; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R2, 0x0000ffff; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x28e00e00 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x14004690 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY \| _AN); dmm32 A1.w, 0xffffffff; dmm32 A1.x, 0x0000007f; imm32 R0, 0x369a8000; imm32 R3, 0xf023457e; A1 += R3.L * R0.H (M, FU); checkreg ASTAT, (0x14004690 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY \| _AN); checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg R0, 0x369a8000; checkreg R3, 0xf023457e; dmm32 ASTAT, (0x5c600680 \| _VS \| _AV1S \| _AQ \| _CC); dmm32 A0.w, 0xfffe0001; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xffff4001; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R2, 0xffffffff; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xfffc0002; checkreg A0.x, 0x00000001; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x5c600680 \| _VS \| _AV1S \| _AV1 \| _AQ \| _CC); dmm32 ASTAT, (0x7cd00800 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY); dmm32 A0.w, 0xfffe0001; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xffff4001; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R2, 0x0000ffff; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x7cd00800 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY); dmm32 ASTAT, (0x78e0cc10 \| _VS \| _AV1S \| _AV0S \| _AC1); dmm32 A0.w, 0xfffe0001; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xffff4001; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R2, 0xffffffff; A1 -= R2.L * R0.L (M), A0 += R2.H * R0.L (FU); checkreg A0.w, 0xfffc0002; checkreg A0.x, 0x00000001; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x78e0cc10 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1); dmm32 ASTAT, (0x1cd04c80 \| _VS \| _V \| _AV0S \| _AC1 \| _V_COPY \| _AC0_COPY); dmm32 A0.w, 0x00000015; dmm32 A0.x, 0x00000000; dmm32 A1.w, 0xfeeaa91d; dmm32 A1.x, 0x0000007f; imm32 R0, 0x50246875; imm32 R6, 0xffff0aab; A1 += R0.L * R6.H (M), A0 -= R0.H * R6.H (FU); checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x1cd04c80 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AV0 \| _AC1 \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x18304890 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _CC \| _AC0_COPY); dmm32 A0.w, 0xfffffffe; dmm32 A0.x, 0xffffffff; dmm32 A1.w, 0xffffca85; dmm32 A1.x, 0x0000007f; imm32 R0, 0xffffffff; imm32 R3, 0xffffdc58; imm32 R7, 0xffff950a; A1 -= R7.L * R0.H (M), R3.L = (A0 -= R7.L * R0.H) (FU); checkreg R3, 0xffffffff; checkreg A0.w, 0x6af69508; checkreg A0.x, 0xffffffff; checkreg A1.w, 0xffffffff; checkreg A1.x, 0x0000007f; checkreg ASTAT, (0x18304890 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AC0 \| _AQ \| _CC \| _V_COPY \| _AC0_COPY); pass
tactcomplabs/xbgas-binutils-gdb	4,524	sim/testsuite/bfin/c_dsp32mult_pair_i.s	//Original:/testcases/core/c_dsp32mult_pair_i/c_dsp32mult_pair_i.dsp // Spec Reference: dsp32mult pair i # mach: bfin .include "testutils.inc" start imm32 r0, 0x8b235625; imm32 r1, 0x93ba5127; imm32 r2, 0xa3446725; imm32 r3, 0x00050027; imm32 r4, 0xb0ab6d29; imm32 r5, 0x10ace72b; imm32 r6, 0xc00c008d; imm32 r7, 0xd2467029; R1 = R0.L * R0.L, R0 = R0.L * R0.L (IS); R3 = R0.L * R1.L, R2 = R0.L * R1.H (IS); R5 = R1.L * R0.L, R4 = R1.H * R0.L (IS); R7 = R1.L * R1.L, R6 = R1.H * R1.H (IS); CHECKREG r0, 0x1CFCE159; CHECKREG r1, 0x1CFCE159; CHECKREG r2, 0xFC878F9C; CHECKREG r3, 0x03AB90F1; CHECKREG r4, 0xFC878F9C; CHECKREG r5, 0x03AB90F1; CHECKREG r6, 0x03481810; CHECKREG r7, 0x03AB90F1; imm32 r0, 0x5b33a635; imm32 r1, 0x6fbe5137; imm32 r2, 0x1324b735; imm32 r3, 0x9006d037; imm32 r4, 0x80abcb39; imm32 r5, 0xb0acef3b; imm32 r6, 0xa00c00dd; imm32 r7, 0x12469003; R1 = R2.L * R2.L, R0 = R2.L * R2.L (IS); R3 = R2.L * R3.L, R2 = R2.L * R3.H (IS); R5 = R3.L * R2.L, R4 = R3.H * R2.L (IS); R7 = R3.L * R3.L, R6 = R3.H * R3.H (IS); CHECKREG r0, 0x14B2D0F9; CHECKREG r1, 0x14B2D0F9; CHECKREG r2, 0x1FD71B3E; CHECKREG r3, 0x0D966C63; CHECKREG r4, 0x01721C54; CHECKREG r5, 0x0B88B0FA; CHECKREG r6, 0x00B893E4; CHECKREG r7, 0x2DE3AE49; imm32 r0, 0x1b235655; imm32 r1, 0xc4ba5157; imm32 r2, 0x63246755; imm32 r3, 0x00060055; imm32 r4, 0x90abc509; imm32 r5, 0x10acef5b; imm32 r6, 0xb00c005d; imm32 r7, 0x1246705f; R1 = R4.L * R4.L, R0 = R4.L * R4.L (IS); R3 = R4.L * R5.L, R2 = R4.L * R5.H (IS); R5 = R5.L * R4.L, R4 = R5.H * R4.L (IS); R7 = R5.L * R5.L, R6 = R5.H * R5.H (IS); CHECKREG r0, 0x0D94DA51; CHECKREG r1, 0x0D94DA51; CHECKREG r2, 0xFC28F20C; CHECKREG r3, 0x03D57133; CHECKREG r4, 0xFC28F20C; CHECKREG r5, 0x03D57133; CHECKREG r6, 0x000EAF39; CHECKREG r7, 0x320E1029; imm32 r0, 0xab235666; imm32 r1, 0xeaba5166; imm32 r2, 0x13d48766; imm32 r3, 0xf00b0066; imm32 r4, 0x90ab9d69; imm32 r5, 0x10ac5f6b; imm32 r6, 0x800cb66d; imm32 r7, 0x1246707f; R1 = R6.L * R6.L, R0 = R6.L * R6.L (IS); R3 = R6.L * R7.L, R2 = R6.L * R7.H (IS); R5 = R7.L * R6.L, R4 = R7.H * R6.L (IS); R7 = R7.L * R7.L, R6 = R7.H * R7.H (IS); CHECKREG r0, 0x15252A69; CHECKREG r1, 0x15252A69; CHECKREG r2, 0xFABF8BCE; CHECKREG r3, 0xDFAB3013; CHECKREG r4, 0xFABF8BCE; CHECKREG r5, 0xDFAB3013; CHECKREG r6, 0x014DEB24; CHECKREG r7, 0x316F5F01; // mix order imm32 r0, 0xab23a675; imm32 r1, 0xcfba5127; imm32 r2, 0x13246705; imm32 r3, 0x00060007; imm32 r4, 0x90abcd09; imm32 r5, 0x10acdfdb; imm32 r6, 0x000c000d; imm32 r7, 0x1246f00f; R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (IS); R3 = R1.L * R0.H, R2 = R1.H * R0.L (IS); R5 = R7.H * R4.L, R4 = R7.H * R4.L (IS); R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (IS); CHECKREG r0, 0x000085FC; CHECKREG r1, 0x0002D123; CHECKREG r2, 0xFFFF0BF8; CHECKREG r3, 0x00000000; CHECKREG r4, 0xFC5CB276; CHECKREG r5, 0xFC5CB276; CHECKREG r6, 0xFFFFD0AC; CHECKREG r7, 0xFFFC0FFE; imm32 r0, 0x9b235a75; imm32 r1, 0xc9ba5127; imm32 r2, 0x13946905; imm32 r3, 0x00090007; imm32 r4, 0x90ab9d09; imm32 r5, 0x10ace9db; imm32 r6, 0x000c0d9d; imm32 r7, 0x12467009; R3 = R6.L * R5.L, R2 = R6.L * R5.H (IS); R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (IS); R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (IS); R7 = R2.H * R7.L, R6 = R2.H * R7.L (IS); CHECKREG r0, 0xFF9549FA; CHECKREG r1, 0xB8ADBDCD; CHECKREG r2, 0x00E2F57C; CHECKREG r3, 0xFED28A4F; CHECKREG r4, 0x1B929715; CHECKREG r5, 0xD7646535; CHECKREG r6, 0x0062E7F2; CHECKREG r7, 0x0062E7F2; imm32 r0, 0x8b235675; imm32 r1, 0xc8ba5127; imm32 r2, 0x13846705; imm32 r3, 0x00080007; imm32 r4, 0x90ab8d09; imm32 r5, 0x10ace8db; imm32 r6, 0x000c008d; imm32 r7, 0x12467008; R3 = R6.H * R5.L, R2 = R6.L * R5.H (IS); R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (IS); R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (IS); R1 = R2.H * R7.L, R0 = R2.L * R7.H (IS); CHECKREG r0, 0x04A2FAE8; CHECKREG r1, 0x00043554; CHECKREG r2, 0x00092EBC; CHECKREG r3, 0xFFFEEA44; CHECKREG r4, 0x04B15568; CHECKREG r5, 0x4A43345C; CHECKREG r6, 0x00030A1D; CHECKREG r7, 0x196677B4; imm32 r0, 0xeb235675; imm32 r1, 0xceba5127; imm32 r2, 0x13e46705; imm32 r3, 0x000e0007; imm32 r4, 0x90abed09; imm32 r5, 0x10aceedb; imm32 r6, 0x000c00ed; imm32 r7, 0x1246700e; R1 = R1.H * R4.L, R0 = R1.H * R4.L (IS); R3 = R2.L * R5.L, R2 = R2.L * R5.H (IS); R5 = R3.H * R6.L, R4 = R3.L * R6.L (IS); R7 = R4.L * R0.H, R6 = R4.H * R0.L (IS); CHECKREG r0, 0x03A6768A; CHECKREG r1, 0x03A6768A; CHECKREG r2, 0x06B5875C; CHECKREG r3, 0xF919C747; CHECKREG r4, 0xFFCB7CBB; CHECKREG r5, 0xFFF99C25; CHECKREG r6, 0xFFE7756E; CHECKREG r7, 0x01C71242; pass
tactcomplabs/xbgas-binutils-gdb	5,429	sim/testsuite/bfin/c_dsp32alu_rmm.s	//Original:/testcases/core/c_dsp32alu_rmm/c_dsp32alu_rmm.dsp // Spec Reference: dsp32alu dreg = -/- ( dreg, dreg) # mach: bfin .include "testutils.inc" start // ALU operations include parallel addition, subtraction // and 32-bit data. If an operation use a single ALU only, it uses ALU0. imm32 r0, 0x15678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x34445515; imm32 r3, 0x46667717; imm32 r4, 0x5567891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x74445515; imm32 r7, 0x86667777; R0 = R0 -\|- R0; R1 = R0 -\|- R1; R2 = R0 -\|- R2; R3 = R0 -\|- R3; R4 = R0 -\|- R4; R5 = R0 -\|- R5; R6 = R0 -\|- R6; R7 = R0 -\|- R7; CHECKREG r0, 0x00000000; CHECKREG r1, 0xD87754E3; CHECKREG r2, 0xCBBCAAEB; CHECKREG r3, 0xB99A88E9; CHECKREG r4, 0xAA9976E5; CHECKREG r5, 0x987754E3; CHECKREG r6, 0x8BBCAAEB; CHECKREG r7, 0x799A8889; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r4, 0xd8889929; imm32 r5, 0xeaaabb2b; imm32 r6, 0xfcccdd2d; imm32 r7, 0x0eeeffff; R0 = R1 -\|- R0; R1 = R1 -\|- R1; R2 = R1 -\|- R2; R3 = R1 -\|- R3; R4 = R1 -\|- R4; R5 = R1 -\|- R5; R6 = R1 -\|- R6; R7 = R1 -\|- R7; CHECKREG r0, 0x12222202; CHECKREG r1, 0x00000000; CHECKREG r2, 0x4BBCAADB; CHECKREG r3, 0x399A88D9; CHECKREG r4, 0x277866D7; CHECKREG r5, 0x155644D5; CHECKREG r6, 0x033422D3; CHECKREG r7, 0xF1120001; imm32 r0, 0x416789ab; imm32 r1, 0x6289abcd; imm32 r2, 0x43445555; imm32 r3, 0x64667777; imm32 r4, 0x456789ab; imm32 r5, 0x6689abcd; imm32 r6, 0x47445555; imm32 r7, 0x68667777; R0 = R2 -\|- R0; R1 = R2 -\|- R1; R2 = R2 -\|- R2; R3 = R2 -\|- R3; R4 = R2 -\|- R4; R5 = R2 -\|- R5; R6 = R2 -\|- R6; R7 = R2 -\|- R7; CHECKREG r0, 0x01DDCBAA; CHECKREG r1, 0xE0BBA988; CHECKREG r2, 0x00000000; CHECKREG r3, 0x9B9A8889; CHECKREG r4, 0xBA997655; CHECKREG r5, 0x99775433; CHECKREG r6, 0xB8BCAAAB; CHECKREG r7, 0x979A8889; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; R0 = R3 -\|- R0; R1 = R3 -\|- R1; R2 = R3 -\|- R2; R3 = R3 -\|- R3; R4 = R3 -\|- R4; R5 = R3 -\|- R5; R6 = R3 -\|- R6; R7 = R3 -\|- R7; CHECKREG r0, 0x30FFEDFC; CHECKREG r1, 0x1EDDCBFA; CHECKREG r2, 0x12222202; CHECKREG r3, 0x00000000; CHECKREG r4, 0x456789AB; CHECKREG r5, 0x6689ABCD; CHECKREG r6, 0x47445555; CHECKREG r7, 0x68667777; imm32 r0, 0x4537891b; imm32 r1, 0x6759ab2d; imm32 r2, 0x44555535; imm32 r3, 0x66665747; imm32 r4, 0x88789565; imm32 r5, 0xaa8abb5b; imm32 r6, 0xcc9cdd85; imm32 r7, 0xeeaeff9f; R0 = R4 -\|- R0; R1 = R4 -\|- R1; R2 = R4 -\|- R2; R3 = R4 -\|- R3; R4 = R4 -\|- R4; R5 = R4 -\|- R5; R6 = R4 -\|- R6; R7 = R4 -\|- R7; CHECKREG r0, 0x43410C4A; CHECKREG r1, 0x211FEA38; CHECKREG r2, 0x44234030; CHECKREG r3, 0x22123E1E; CHECKREG r4, 0x00000000; CHECKREG r5, 0x557644A5; CHECKREG r6, 0x3364227B; CHECKREG r7, 0x11520061; imm32 r0, 0x456b89ab; imm32 r1, 0x69764bcd; imm32 r2, 0x49736564; imm32 r3, 0x61278394; imm32 r4, 0x98876439; imm32 r5, 0xaaaa0bbb; imm32 r6, 0xcccc1ddd; imm32 r7, 0x12346fff; R0 = R5 -\|- R0; R1 = R5 -\|- R1; R2 = R5 -\|- R2; R3 = R5 -\|- R3; R4 = R5 -\|- R4; R5 = R5 -\|- R5; R6 = R5 -\|- R6; R7 = R5 -\|- R7; CHECKREG r0, 0x653F8210; CHECKREG r1, 0x4134BFEE; CHECKREG r2, 0x6137A657; CHECKREG r3, 0x49838827; CHECKREG r4, 0x1223A782; CHECKREG r5, 0x00000000; CHECKREG r6, 0x3334E223; CHECKREG r7, 0xEDCC9001; imm32 r0, 0x456739ab; imm32 r1, 0x67694bcd; imm32 r2, 0x03456755; imm32 r3, 0x66666777; imm32 r4, 0x12345699; imm32 r5, 0x45678b6b; imm32 r6, 0x043290d6; imm32 r7, 0x1234567f; R0 = R6 -\|- R0; R1 = R6 -\|- R1; R2 = R6 -\|- R2; R3 = R6 -\|- R3; R4 = R6 -\|- R4; R5 = R6 -\|- R5; R6 = R6 -\|- R6; R7 = R6 -\|- R7; CHECKREG r0, 0xBECB572B; CHECKREG r1, 0x9CC94509; CHECKREG r2, 0x00ED2981; CHECKREG r3, 0x9DCC295F; CHECKREG r4, 0xF1FE3A3D; CHECKREG r5, 0xBECB056B; CHECKREG r6, 0x00000000; CHECKREG r7, 0xEDCCA981; imm32 r0, 0x476789ab; imm32 r1, 0x6779abcd; imm32 r2, 0x23456755; imm32 r3, 0x56789007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R0 = R7 -\|- R0; R1 = R7 -\|- R1; R2 = R7 -\|- R2; R3 = R7 -\|- R3; R4 = R7 -\|- R4; R5 = R7 -\|- R5; R6 = R7 -\|- R6; R7 = R7 -\|- R7; CHECKREG r0, 0x6466A64C; CHECKREG r1, 0x4454842A; CHECKREG r2, 0x8888C8A2; CHECKREG r3, 0x55559FF0; CHECKREG r4, 0x3333785E; CHECKREG r5, 0x0123243C; CHECKREG r6, 0x2222127A; CHECKREG r7, 0x00000000; imm32 r0, 0x456739ab; imm32 r1, 0x67694bcd; imm32 r2, 0x03456755; imm32 r3, 0x66666777; imm32 r4, 0x12345699; imm32 r5, 0x45678b6b; imm32 r6, 0x043290d6; imm32 r7, 0x1234567f; R4 = R4 -\|- R7 (S); R5 = R5 -\|- R5 (CO); R2 = R6 -\|- R3 (SCO); R6 = R0 -\|- R4 (S); R0 = R1 -\|- R6 (S); R2 = R2 -\|- R1 (CO); R1 = R3 -\|- R0 (CO); R7 = R7 -\|- R4 (SCO); CHECKREG r0, 0x2202123C; CHECKREG r1, 0x553B4464; CHECKREG r2, 0x51FF1897; CHECKREG r3, 0x66666777; CHECKREG r4, 0x0000001A; CHECKREG r5, 0x00000000; CHECKREG r6, 0x45673991; CHECKREG r7, 0x56651234; imm32 r0, 0x476789ab; imm32 r1, 0x6779abcd; imm32 r2, 0x23456755; imm32 r3, 0x56789007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R3 = R4 -\|- R0 (S); R5 = R5 -\|- R1 (SCO); R2 = R2 -\|- R2 (S); R7 = R7 -\|- R3 (CO); R4 = R3 -\|- R4 (CO); R0 = R1 -\|- R5 (S); R1 = R0 -\|- R6 (SCO); R6 = R6 -\|- R7 (SCO); CHECKREG r0, 0x078B2BCD; CHECKREG r1, 0x0E507DE0; CHECKREG r2, 0x00000000; CHECKREG r3, 0x31332DEE; CHECKREG r4, 0x7655B899; CHECKREG r5, 0x5FEE8000; CHECKREG r6, 0xA2E387A2; CHECKREG r7, 0x02097A9A; pass
tactcomplabs/xbgas-binutils-gdb	1,045	sim/testsuite/bfin/stk.s	# mach: bfin .include "testutils.inc" start // load up some registers. // setup up a global pointer table and load some state. // save the machine state and clear some of the values. // then restore and assert some of the values to ensure that // we maintain consitent machine state. R0 = 1; R1 = 2; R2 = 3; R3 = -7; R4 = 4; R5 = 5; R6 = 6; R7 = 7; loadsym P0, a; _DBG P0; SP = P0; FP = P0; P1 = [ P0 ++ ]; P2 = [ P0 ++ ]; P0 += 4; P4 = [ P0 ++ ]; P5 = [ P0 ++ ]; [ -- SP ] = ( R7:0, P5:0 ); _DBG SP; _DBG FP; R0 = R0 ^ R0; R1 = R1 ^ R1; R2 = R2 ^ R2; R4 = R4 ^ R4; R5 = R5 ^ R5; R6 = R6 ^ R6; R7 = R7 ^ R7; ( R7:0, P5:0 ) = [ SP ++ ]; DBGA ( R0.L , 1 ); DBGA ( R2.L , 3 ); DBGA ( R7.L , 7 ); R0 = SP; loadsym R1, a; CC = R0 == R1; IF !CC JUMP abrt; R0 = FP; CC = R0 == R1; CC = R0 == R1; IF !CC JUMP abrt; pass abrt: fail .data _gptab: .dw 0x200 .dw 0x000 .dw 0x300 .dw 0x400 .dw 0x500 .dw 0x600 .space (0x100) a: .dw 1 .dw 2 .dw 3 .dw 4 .dw 5 .dw 6 .dw 7 .dw 8 .dw 9 .dw 0xa
tactcomplabs/xbgas-binutils-gdb	1,313	sim/testsuite/bfin/c_dsp32alu_a0a1s.s	//Original:/testcases/core/c_dsp32alu_a0a1s/c_dsp32alu_a0a1s.dsp // Spec Reference: dsp32alu a0a1s # mach: bfin .include "testutils.inc" start A1 = A0 = 0; imm32 r0, 0x15678911; imm32 r1, 0xa789ab1d; imm32 r2, 0xd4445515; imm32 r3, 0xf6667717; imm32 r4, 0xe567891b; imm32 r5, 0x6789ab1d; imm32 r6, 0xb4445515; imm32 r7, 0x86667777; // A0 & A1 types A0 = R0; A1 = R1; R6 = A0.w; R7 = A1.w; A0 = 0; A1 = 0; R0 = A0.w; R1 = A1.w; A0 = R2; A1 = R3; A0 = A0 (S); A1 = A1 (S); R4 = A0.w; R5 = A1.w; A0 = A1; R2 = A0.w; A0 = R3; A1 = A0; R3 = A1.w; CHECKREG r0, 0x00000000; CHECKREG r1, 0x00000000; CHECKREG r2, 0xF6667717; CHECKREG r3, 0xF6667717; CHECKREG r4, 0xD4445515; CHECKREG r5, 0xF6667717; CHECKREG r6, 0x15678911; CHECKREG r7, 0xA789AB1D; A1 = A0 = 0; R0 = A0.w; R1 = A1.w; CHECKREG r0, 0x00000000; CHECKREG r1, 0x00000000; imm32 r0, 0xa1567891; imm32 r1, 0xba789abd; imm32 r2, 0xcd412355; imm32 r3, 0xdf646777; imm32 r4, 0xe567891b; imm32 r5, 0x6789ab1d; imm32 r6, 0xb4445515; imm32 r7, 0xf666aeb7; A0 = R4; A1 = R5; R0 = A0.w; R1 = A1.w; A0 = R6; A1 = R7; R2 = A0.w; R3 = A1.w; CHECKREG r0, 0xE567891B; CHECKREG r1, 0x6789AB1D; CHECKREG r2, 0xB4445515; CHECKREG r3, 0xF666AEB7; CHECKREG r4, 0xE567891B; CHECKREG r5, 0x6789AB1D; CHECKREG r6, 0xB4445515; CHECKREG r7, 0xF666AEB7; pass
tactcomplabs/xbgas-binutils-gdb	1,806	sim/testsuite/bfin/se_all64bitg1opcodes.S	/* * Blackfin testcase for testing illegal/legal 64-bit opcodes (group 1) * from userspace. we track all instructions which cause some sort of * exception when run from userspace, this is normally EXCAUSE : * - 0x22 : illegal instruction combination * and walk every instruction from 0x0000 to 0xffff / # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" #define SE_ALL_BITS 16 #include "se_allopcodes.h" .macro se_all_load_insn R2 = W[P5 + 4]; R0 = R2; .endm .macro se_all_next_insn / increment, and go again. / R0 = R2; R0 += 1; / finish once we hit the 32bit limit / imm32 R1, 0x10000; CC = R1 == R0; IF CC JUMP pass_lvl; W[P5 + 4] = R0; .endm .macro se_all_insn_init MNOP \|\| NOP \|\| NOP; .endm .macro se_all_insn_table / this table must be sorted, and end with zero / / start end SEQSTAT */ .dw 0x0001, 0x7fff, 0x22 .dw 0x9040, 0x9040, 0x22 .dw 0x9049, 0x9049, 0x22 .dw 0x9052, 0x9052, 0x22 .dw 0x905b, 0x905b, 0x22 .dw 0x9064, 0x9064, 0x22 .dw 0x906d, 0x906d, 0x22 .dw 0x9076, 0x9076, 0x22 .dw 0x907f, 0x907f, 0x22 .dw 0x90c0, 0x90c0, 0x22 .dw 0x90c9, 0x90c9, 0x22 .dw 0x90d2, 0x90d2, 0x22 .dw 0x90db, 0x90db, 0x22 .dw 0x90e4, 0x90e4, 0x22 .dw 0x90ed, 0x90ed, 0x22 .dw 0x90f6, 0x90f6, 0x22 .dw 0x90ff, 0x90ff, 0x22 .dw 0x9180, 0x91ff, 0x22 .dw 0x9380, 0x93ff, 0x22 .dw 0x9580, 0x95ff, 0x22 .dw 0x9640, 0x967f, 0x22 .dw 0x96c0, 0x96ff, 0x22 .dw 0x9740, 0x97ff, 0x22 .dw 0x9980, 0x99ff, 0x22 .dw 0x9a40, 0x9a7f, 0x22 .dw 0x9ac0, 0x9aff, 0x22 .dw 0x9b40, 0x9bff, 0x22 .dw 0x9c60, 0x9c7f, 0x22 .dw 0x9ce0, 0x9cff, 0x22 .dw 0x9d60, 0x9d7f, 0x22 .dw 0x9ef0, 0x9eff, 0x22 .dw 0x9f70, 0x9f7f, 0x22 .dw 0xc000, 0xffff, 0x22 .dw 0x0000, 0x0000, 0x00 .endm se_all_test
tactcomplabs/xbgas-binutils-gdb	17,730	sim/testsuite/bfin/se_loop_kill_dcr_01.S	//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start ///////////////////////////////////////////////////////////////////////////// ///////////////////////// Include Files ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// include(std.inc) include(selfcheck.inc) include(symtable.inc) include(mmrs.inc) ///////////////////////////////////////////////////////////////////////////// ///////////////////////// Defines ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// #ifndef USER_CODE_SPACE #define USER_CODE_SPACE CODE_ADDR_1 // #endif #ifndef STACKSIZE #define STACKSIZE 0x00000010 #endif #ifndef ITABLE #define ITABLE CODE_ADDR_2 // #endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////// RESET ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// RST_ISR : // Initialize Dregs INIT_R_REGS(0); // Initialize Pregs INIT_P_REGS(0); // Initialize ILBM Registers INIT_I_REGS(0); INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); // Initialize the Address of the Checkreg data segment // ** THIS IS NEEDED WHENEVER CHECKREG IS USED ** CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); // Setup User Stack LD32_LABEL(sp, USTACK); USP = SP; // Setup Kernel Stack LD32_LABEL(sp, KSTACK); // Setup Frame Pointer FP = SP; // Setup Event Vector Table LD32(p0, EVT0); LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler [ P0 ++ ] = R0; // Setup the EVT_OVERRIDE MMR R0 = 0; LD32(p0, EVT_OVERRIDE); [ P0 ] = R0; // Setup Interrupt Mask R0 = -1; LD32(p0, IMASK); [ P0 ] = R0; // Return to Supervisor Code RAISE 15; NOP; LD32_LABEL(r0, USER_CODE); RETI = R0; RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// ///////////////////////// EMU ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// EMU_ISR : RTE; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// NMI ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// NMI_ISR : RTN; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// EXC ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// EXC_ISR : RTX; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// HWE ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// HWE_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// TMR ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// TMR_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV7 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV7_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV8 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV8_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV9 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV9_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV10 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV10_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV11 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV11_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV12 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV12_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV13 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV13_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV14 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV14_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV15 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV15_ISR : P0 = 0x1 (Z); P1 = 0x2 (Z); P2 = 0x3 (Z); P3 = 0x4 (Z); P4 = 0x5 (Z); ///////////////////////////////////////////////////////////////////////////// // Loop 0 (with Kill WB) ///////////////////////////////////////////////////////////////////////////// // Kill Valid Dcr in WB LSETUP ( L0T , L0T ) LC0 = P0; EXCPT 0x5; L0T:R0 += 5; // Kill Valid Dcr in EX3 LSETUP ( L1T , L1B ) LC0 = P0; EXCPT 0x5; L1T:R0 += 5; L1B:R1 += 4; // Kill Valid Dcr in EX2 LSETUP ( L2T , L2B ) LC0 = P0; EXCPT 0x5; L2T:R0 += 5; R1 += 4; L2B:R2 += 3; // Kill Valid Dcr in EX1 LSETUP ( L3T , L3B ) LC0 = P0; EXCPT 0x5; L3T:R0 += 5; R1 += 4; R2 += 3; L3B:R3 += 2; // Kill Valid Dcr in AC LSETUP ( L4T , L4B ) LC0 = P0; EXCPT 0x5; L4T:R0 += 5; R1 += 4; R2 += 3; R3 += 2; L4B:R4 += 1; // Kill Valid Dcr in WB, EX3 LSETUP ( L5T , L5T ) LC0 = P1; EXCPT 0x5; L5T:R1 += 5; // Kill Valid Dcr in EX3, EX2 LSETUP ( L6T , L6T ) LC0 = P1; EXCPT 0x5; NOP; L6T:R2 += 5; // Kill Valid Dcr in EX2, EX1 LSETUP ( L7T , L7T ) LC0 = P1; EXCPT 0x5; NOP; NOP; L7T:R3 += 5; // Kill Valid Dcr in EX1, AC LSETUP ( L8T , L8T ) LC0 = P1; EXCPT 0x5; NOP; NOP; NOP; L8T:R4 += 5; // Kill Valid Dcr in WB, EX3, EX2 LSETUP ( L9T , L9T ) LC0 = P2; EXCPT 0x5; L9T:R5 += 5; // Kill Valid Dcr in EX3, EX2, EX1 LSETUP ( LAT , LAT ) LC0 = P2; EXCPT 0x5; NOP; LAT: R6 += 6; // Kill Valid Dcr in EX2, EX1, AC LSETUP ( LBT , LBT ) LC0 = P2; EXCPT 0x5; NOP; NOP; LBT: R5 += 5; // Kill Valid Dcr in WB, EX3, EX2, EX1 LSETUP ( LCT , LCT ) LC0 = P3; EXCPT 0x5; LCT: R7 += 7; // Kill Valid Dcr in EX3, EX2, EX1, AC LSETUP ( LDT , LDT ) LC0 = P3; EXCPT 0x5; NOP; LDT: R0 += 7; // Kill Valid Dcr in WB, EX3, EX2, EX1, AC LSETUP ( LET , LET ) LC0 = P4; EXCPT 0x5; LET: R1 += 1; // Kill Valid Dcr in WB, EX2 LSETUP ( LFT , LFB ) LC0 = P1; LFT: EXCPT 0x5; LFB: R1 += 2; // Kill Valid Dcr in WB, EX1 LSETUP ( LGT , LGB ) LC0 = P1; LGT: R2 += 3; EXCPT 0x5; LGB: R1 += 2; // Kill Valid Dcr in WB, AC LSETUP ( LHT , LHB ) LC0 = P1; LHT: R2 += 3; R3 += 4; EXCPT 0x5; LHB: R1 += 2; // Kill Valid Dcr in EX3, EX1 LSETUP ( LIT , LIB ) LC0 = P1; EXCPT 0x5; LIT: R2 += 1; LIB: R1 += 2; // Kill Valid Dcr in EX3, AC LSETUP ( LJT , LJB ) LC0 = P1; LJT: EXCPT 0x5; R2 += 1; LJB: R1 += 2; // Kill Valid Dcr in EX2, AC LSETUP ( LKT , LKB ) LC0 = P1; EXCPT 0x5; NOP; LKT: R2 += 1; LKB: R1 += 2; // Kill Valid Dcr in WB, EX2, AC LSETUP ( LLT , LLB ) LC0 = P2; LLT: EXCPT 0x5; LLB: R2 += 2; ///////////////////////////////////////////////////////////////////////////// // Loop 1 (with Kill WB) ///////////////////////////////////////////////////////////////////////////// // Kill Valid Dcr in WB LSETUP ( M0T , M0T ) LC1 = P0; EXCPT 0x5; M0T:R0 += 5; // Kill Valid Dcr in EX3 LSETUP ( M1T , M1B ) LC1 = P0; EXCPT 0x5; M1T:R0 += 5; M1B:R1 += 4; // Kill Valid Dcr in EX2 LSETUP ( M2T , M2B ) LC1 = P0; EXCPT 0x5; M2T:R0 += 5; R1 += 4; M2B:R2 += 3; // Kill Valid Dcr in EX1 LSETUP ( M3T , M3B ) LC1 = P0; EXCPT 0x5; M3T:R0 += 5; R1 += 4; R2 += 3; M3B:R3 += 2; // Kill Valid Dcr in AC LSETUP ( M4T , M4B ) LC1 = P0; EXCPT 0x5; M4T:R0 += 5; R1 += 4; R2 += 3; R3 += 2; M4B:R4 += 1; // Kill Valid Dcr in WB, EX3 LSETUP ( M5T , M5T ) LC1 = P1; EXCPT 0x5; M5T:R1 += 5; // Kill Valid Dcr in EX3, EX2 LSETUP ( M6T , M6T ) LC1 = P1; EXCPT 0x5; NOP; M6T:R2 += 5; // Kill Valid Dcr in EX2, EX1 LSETUP ( M7T , M7T ) LC1 = P1; EXCPT 0x5; NOP; NOP; M7T:R3 += 5; // Kill Valid Dcr in EX1, AC LSETUP ( M8T , M8T ) LC1 = P1; EXCPT 0x5; NOP; NOP; NOP; M8T:R4 += 5; // Kill Valid Dcr in WB, EX3, EX2 LSETUP ( M9T , M9T ) LC1 = P2; EXCPT 0x5; M9T:R5 += 5; // Kill Valid Dcr in EX3, EX2, EX1 LSETUP ( MAT , MAT ) LC1 = P2; EXCPT 0x5; NOP; MAT: R6 += 6; // Kill Valid Dcr in EX2, EX1, AC LSETUP ( MBT , MBT ) LC1 = P2; EXCPT 0x5; NOP; NOP; MBT: R5 += 5; // Kill Valid Dcr in WB, EX3, EX2, EX1 LSETUP ( MCT , MCT ) LC1 = P3; EXCPT 0x5; MCT: R7 += 7; // Kill Valid Dcr in EX3, EX2, EX1, AC LSETUP ( MDT , MDT ) LC1 = P3; EXCPT 0x5; NOP; MDT: R0 += 7; // Kill Valid Dcr in WB, EX3, EX2, EX1, AC LSETUP ( MET , MET ) LC1 = P4; EXCPT 0x5; MET: R1 += 1; // Kill Valid Dcr in WB, EX2 LSETUP ( MFT , MFB ) LC1 = P1; MFT: EXCPT 0x5; MFB: R1 += 2; // Kill Valid Dcr in WB, EX1 LSETUP ( MGT , MGB ) LC1 = P1; MGT: R2 += 3; EXCPT 0x5; MGB: R1 += 2; // Kill Valid Dcr in WB, AC LSETUP ( MHT , MHB ) LC1 = P1; MHT: R2 += 3; R3 += 4; EXCPT 0x5; MHB: R1 += 2; // Kill Valid Dcr in EX3, EX1 LSETUP ( MIT , MIB ) LC1 = P1; EXCPT 0x5; MIT: R2 += 1; MIB: R1 += 2; // Kill Valid Dcr in EX3, AC LSETUP ( MJT , MJB ) LC1 = P1; MJT: EXCPT 0x5; R2 += 1; MJB: R1 += 2; // Kill Valid Dcr in EX2, AC LSETUP ( MKT , MKB ) LC1 = P1; EXCPT 0x5; NOP; MKT: R2 += 1; MKB: R1 += 2; // Kill Valid Dcr in WB, EX2, AC LSETUP ( MLT , MLB ) LC1 = P2; MLT: EXCPT 0x5; MLB: R2 += 2; ///////////////////////////////////////////////////////////////////////////// // Loop 0 (with Kill EX3) ///////////////////////////////////////////////////////////////////////////// R0 = 1; CC = R0; // Kill %Valid Dcr in EX3 LSETUP ( N1T , N1T ) LC0 = P0; IF CC JUMP 2; N1T:R0 += 5; // Kill Valid Dcr in EX2 LSETUP ( N2T , N2B ) LC0 = P0; IF CC JUMP 2; N2T:R0 += 5; N2B:R2 += 3; // Kill Valid Dcr in EX1 LSETUP ( N3T , N3B ) LC0 = P0; IF CC JUMP 2; N3T:R0 += 5; R2 += 3; N3B:R3 += 2; // Kill Valid Dcr in AC LSETUP ( N4T , N4B ) LC0 = P0; IF CC JUMP 2; N4T:R0 += 5; R2 += 3; R3 += 2; N4B:R4 += 1; // Kill Valid Dcr in EX3, EX2 LSETUP ( N6T , N6T ) LC0 = P1; IF CC JUMP 2; N6T:R2 += 5; // Kill Valid Dcr in EX2, EX1 LSETUP ( N7T , N7T ) LC0 = P1; IF CC JUMP 2; NOP; N7T:R3 += 5; // Kill Valid Dcr in EX1, AC LSETUP ( N8T , N8T ) LC0 = P1; IF CC JUMP 2; NOP; NOP; N8T:R4 += 5; // Kill Valid Dcr in EX3, EX2, EX1 LSETUP ( NAT , NAT ) LC0 = P2; IF CC JUMP 2; NAT: R6 += 6; // Kill Valid Dcr in EX2, EX1, AC LSETUP ( NBT , NBT ) LC0 = P2; IF CC JUMP 2; NOP; NBT: R5 += 5; // Kill Valid Dcr in EX3, EX2, EX1, AC LSETUP ( NDT , NDT ) LC0 = P3; IF CC JUMP 2; NDT: R0 += 7; // Kill Valid Dcr in EX3, EX1 LSETUP ( NIT , NIB ) LC0 = P1; NIT: IF CC JUMP 2; NIB: R1 += 2; // Kill Valid Dcr in EX3, AC LSETUP ( NJT , NJB ) LC0 = P1; NJT: R2 += 1; IF CC JUMP 2; NJB: R1 += 2; // Kill Valid Dcr in EX2, AC LSETUP ( NKT , NKB ) LC0 = P1; IF CC JUMP 2; NKT: R2 += 1; NKB: R1 += 2; ///////////////////////////////////////////////////////////////////////////// // Loop 1 (with Kill EX3) ///////////////////////////////////////////////////////////////////////////// // Kill %Valid Dcr in EX3 LSETUP ( O1T , O1T ) LC1 = P0; IF CC JUMP 2; O1T:R0 += 5; // Kill Valid Dcr in EX2 LSETUP ( O2T , O2B ) LC1 = P0; IF CC JUMP 2; O2T:R0 += 5; O2B:R2 += 3; // Kill Valid Dcr in EX1 LSETUP ( O3T , O3B ) LC1 = P0; IF CC JUMP 2; O3T:R0 += 5; R2 += 3; O3B:R3 += 2; // Kill Valid Dcr in AC LSETUP ( O4T , O4B ) LC1 = P0; IF CC JUMP 2; O4T:R0 += 5; R2 += 3; R3 += 2; O4B:R4 += 1; // Kill Valid Dcr in EX3, EX2 LSETUP ( O6T , O6T ) LC1 = P1; IF CC JUMP 2; O6T:R2 += 5; // Kill Valid Dcr in EX2, EX1 LSETUP ( O7T , O7T ) LC1 = P1; IF CC JUMP 2; NOP; O7T:R3 += 5; // Kill Valid Dcr in EX1, AC LSETUP ( O8T , O8T ) LC1 = P1; IF CC JUMP 2; NOP; NOP; O8T:R4 += 5; // Kill Valid Dcr in EX3, EX2, EX1 LSETUP ( OAT , OAT ) LC1 = P2; IF CC JUMP 2; OAT: R6 += 6; // Kill Valid Dcr in EX2, EX1, AC LSETUP ( OBT , OBT ) LC1 = P2; IF CC JUMP 2; NOP; OBT: R5 += 5; // Kill Valid Dcr in EX3, EX2, EX1, AC LSETUP ( ODT , ODT ) LC1 = P3; IF CC JUMP 2; ODT: R0 += 7; // Kill Valid Dcr in EX3, EX1 LSETUP ( OIT , OIB ) LC1 = P1; OIT: IF CC JUMP 2; OIB: R1 += 2; // Kill Valid Dcr in EX3, AC LSETUP ( OJT , OJB ) LC1 = P1; OJT: R2 += 1; IF CC JUMP 2; OJB: R1 += 2; // Kill Valid Dcr in EX2, AC LSETUP ( OKT , OKB ) LC1 = P1; IF CC JUMP 2; OKT: R2 += 1; OKB: R1 += 2; ///////////////////////////////////////////////////////////////////////////// // Loop 0 (with Kill AC) ///////////////////////////////////////////////////////////////////////////// // Kill Valid Dcr in AC LSETUP ( P4T , P4T ) LC0 = P0; JUMP.S 2; P4T:R0 += 5; ///////////////////////////////////////////////////////////////////////////// // Loop 1 (with Kill AC) ///////////////////////////////////////////////////////////////////////////// // Kill Valid Dcr in AC LSETUP ( Q4T , Q4T ) LC1 = P0; JUMP.S 2; Q4T:R0 += 5; NOP; NOP; RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// USER CODE ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// USER_CODE : NOP; NOP; NOP; NOP; dbg_pass; // Call Endtest Macro ///////////////////////////////////////////////////////////////////////////// ///////////////////////// DATA MEMRORY ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// .section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" .dd 0xdeadbeef; .section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw" .dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> .dd 0x02020202; .dd 0x03030303; .dd 0x04040404; // Define Kernal Stack .data .space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >> KSTACK : .space (STACKSIZE); USTACK : ///////////////////////////////////////////////////////////////////////////// ///////////////////////// END OF TEST ///////////////////////////// /////////////////////////////////////////////////////////////////////////////
tactcomplabs/xbgas-binutils-gdb	1,128	sim/testsuite/bfin/lsetup.s	# Blackfin testcase for playing with LSETUP # mach: bfin .include "testutils.inc" start R0 = 0x123; P0 = R0; LSETUP (.L1, .L1) LC0 = P0; .L1: R0 += -1; R1 = 0; CC = R1 == R0; IF CC JUMP 1f; fail 1: p0=10; loadsym i0, _buf imm32 r0, 0x12345678 LSETUP(.L2, .L3) lc0 = p0; .L2: [i0++] = r0; .L3: [i0++] = r0; loadsym R1, _buf R0 = 0x50; R1 = R0 + R1; R0 = I0; CC = R0 == R1; if CC JUMP 2f; fail 2: r5=10; p1=r5; r7=20; lsetup (.L4, .L5) lc0=p1; .L4: nop; nop; nop; nop; jump .L5; nop; nop; nop; .L5: r7 += -1; R0 = 10 (Z); CC = R7 == R0; if CC jump 3f; fail 3: r1 = 1; r2 = 2; r0 = 0; p1 = 10; loadsym p0, _buf; lsetup (.L6, .L7) lc0 = p1; .L6: [p0++] = r1; .L7: [p0++] = r2; r3 = P0; loadsym r1, _buf r0 = 80; r1 = r1 + r0; CC = R1 == R3 if CC jump 4f; fail 4: R0 = 1; R1 = 2; R2 = 3; R4 = 4; P1 = R1; LSETUP (.L8, .L8) LC0 = P1; R5 = 5; R6 = 6; R7 = 7; .L8: R1 += 1; R7 = 4; CC = R7 == R1; if CC jump 5f; fail 5: P1 = R1; LSETUP (.L9, .L9 ) LC1 = P1; .L9: R1 += 1; R7 = 8; if CC jump 6f; fail 6: pass .data _buf: .rept 0x80 .long 0 .endr
tactcomplabs/xbgas-binutils-gdb	5,957	sim/testsuite/bfin/c_dsp32alu_rl_rnd20_m.s	//Original:/testcases/core/c_dsp32alu_rl_rnd20_m/c_dsp32alu_rl_rnd20_m.dsp // Spec Reference: dsp32alu dreg (half) # mach: bfin .include "testutils.inc" start imm32 r0, 0x75678911; imm32 r1, 0xa789ab1d; imm32 r2, 0x34745515; imm32 r3, 0x4b677717; imm32 r4, 0x5678791b; imm32 r5, 0xc789a71d; imm32 r6, 0x74445515; imm32 r7, 0x86667777; R0.L = R0 - R0 (RND20); R1.L = R0 - R1 (RND20); R2.L = R0 - R2 (RND20); R3.L = R0 - R3 (RND20); R4.L = R0 - R4 (RND20); R5.L = R0 - R5 (RND20); R6.L = R0 - R6 (RND20); R7.L = R0 - R7 (RND20); CHECKREG r0, 0x75670000; CHECKREG r1, 0xA7890CDE; CHECKREG r2, 0x3474040F; CHECKREG r3, 0x4B6702A0; CHECKREG r4, 0x567801EF; CHECKREG r5, 0xC7890ADE; CHECKREG r6, 0x74440012; CHECKREG r7, 0x86660EF0; imm32 r0, 0xe5678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x3e445515; imm32 r3, 0x46667717; imm32 r4, 0x56e8891b; imm32 r5, 0x678eab1d; imm32 r6, 0x74445515; imm32 r7, 0x86e67e77; R0.L = R1 - R0 (RND20); CHECKREG r0, 0xE5670422; R1.L = R1 - R1 (RND20); CHECKREG r1, 0x27890000; R2.L = R1 - R2 (RND20); CHECKREG r2, 0x3E44FE94; R3.L = R1 - R3 (RND20); CHECKREG r3, 0x4666FE12; R4.L = R1 - R4 (RND20); R5.L = R1 - R5 (RND20); R6.L = R1 - R6 (RND20); R7.L = R1 - R7 (RND20); CHECKREG r0, 0xE5670422; CHECKREG r1, 0x27890000; CHECKREG r2, 0x3E44FE94; CHECKREG r3, 0x4666FE12; CHECKREG r4, 0x56E8FD0A; CHECKREG r5, 0x678EFC00; CHECKREG r6, 0x7444FB34; CHECKREG r7, 0x86E60A0A; imm32 r0, 0xdd678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x3d445515; imm32 r3, 0x46667717; imm32 r4, 0x56d8891b; imm32 r5, 0x678dab1d; imm32 r6, 0x7444d515; imm32 r7, 0x86667d77; R0.L = R2 - R0 (RND20); R1.L = R2 - R1 (RND20); R2.L = R2 - R2 (RND20); R3.L = R2 - R3 (RND20); R4.L = R2 - R4 (RND20); R5.L = R2 - R5 (RND20); R6.L = R2 - R6 (RND20); R7.L = R2 - R7 (RND20); CHECKREG r0, 0xDD6705FE; CHECKREG r1, 0x2789015C; CHECKREG r2, 0x3D440000; CHECKREG r3, 0x4666FF6E; CHECKREG r4, 0x56D8FE67; CHECKREG r5, 0x678DFD5B; CHECKREG r6, 0x7444FC90; CHECKREG r7, 0x86660B6E; imm32 r0, 0xa5678911; imm32 r1, 0x2a89ab1d; imm32 r2, 0x34445515; imm32 r3, 0x46a67717; imm32 r4, 0x567a891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x7444c515; imm32 r7, 0x86667c77; R0.L = R3 - R0 (RND20); R1.L = R3 - R1 (RND20); R2.L = R3 - R2 (RND20); R3.L = R3 - R3 (RND20); R4.L = R3 - R4 (RND20); R5.L = R3 - R5 (RND20); R6.L = R3 - R6 (RND20); R7.L = R3 - R7 (RND20); CHECKREG r0, 0xA5670A14; CHECKREG r1, 0x2A8901C2; CHECKREG r2, 0x34440126; CHECKREG r3, 0x46A60000; CHECKREG r4, 0x567AFF03; CHECKREG r5, 0x6789FDF2; CHECKREG r6, 0x7444FD26; CHECKREG r7, 0x86660C04; imm32 r0, 0x15678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x34445515; imm32 r3, 0x46667717; imm32 r4, 0x5678891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x74445515; imm32 r7, 0x86667777; R0.L = R4 - R0 (RND20); R1.L = R4 - R1 (RND20); R2.L = R4 - R2 (RND20); R3.L = R4 - R3 (RND20); R4.L = R4 - R4 (RND20); R5.L = R4 - R5 (RND20); R6.L = R4 - R6 (RND20); R7.L = R4 - R7 (RND20); CHECKREG r0, 0x15670411; CHECKREG r1, 0x278902EF; CHECKREG r2, 0x34440223; CHECKREG r3, 0x46660101; CHECKREG r4, 0x56780000; CHECKREG r5, 0x6789FEEF; CHECKREG r6, 0x7444FE23; CHECKREG r7, 0x86660D01; imm32 r0, 0x95678911; imm32 r1, 0x8789ab1d; imm32 r2, 0x74445515; imm32 r3, 0x4a667717; imm32 r4, 0x56b8891b; imm32 r5, 0x678dab1d; imm32 r6, 0x7444e515; imm32 r7, 0x86667d77; R0.L = R5 - R0 (RND20); R1.L = R5 - R1 (RND20); R2.L = R5 - R2 (RND20); R3.L = R5 - R3 (RND20); R4.L = R5 - R4 (RND20); R5.L = R5 - R5 (RND20); R6.L = R5 - R6 (RND20); R7.L = R5 - R7 (RND20); CHECKREG r0, 0x95670D22; CHECKREG r1, 0x87890E00; CHECKREG r2, 0x7444FF35; CHECKREG r3, 0x4A6601D2; CHECKREG r4, 0x56B8010D; CHECKREG r5, 0x678D0000; CHECKREG r6, 0x7444FF35; CHECKREG r7, 0x86660E12; imm32 r0, 0x35678911; imm32 r1, 0x2459ab1d; imm32 r2, 0x34465515; imm32 r3, 0xe6667717; imm32 r4, 0x5d78891b; imm32 r5, 0x67b9ab1d; imm32 r6, 0x744a5515; imm32 r7, 0x8666c777; R0.L = R6 - R0 (RND20); R1.L = R6 - R1 (RND20); R2.L = R6 - R2 (RND20); R3.L = R6 - R3 (RND20); R4.L = R6 - R4 (RND20); R5.L = R6 - R5 (RND20); R6.L = R6 - R6 (RND20); R7.L = R6 - R7 (RND20); CHECKREG r0, 0x356703EE; CHECKREG r1, 0x245904FF; CHECKREG r2, 0x34460400; CHECKREG r3, 0xE66608DE; CHECKREG r4, 0x5D78016D; CHECKREG r5, 0x67B900C9; CHECKREG r6, 0x744A0000; CHECKREG r7, 0x86660EDE; imm32 r0, 0xa5678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x3a445515; imm32 r3, 0x4c667717; imm32 r4, 0x56b8891b; imm32 r5, 0x678dab1d; imm32 r6, 0x74445515; imm32 r7, 0x8666d777; R0.L = R7 - R0 (RND20); R1.L = R7 - R1 (RND20); R2.L = R7 - R2 (RND20); R3.L = R7 - R3 (RND20); R4.L = R7 - R4 (RND20); R5.L = R7 - R5 (RND20); R6.L = R7 - R6 (RND20); R7.L = R7 - R7 (RND20); CHECKREG r0, 0xA567FE10; CHECKREG r1, 0x2789F5EE; CHECKREG r2, 0x3A44F4C2; CHECKREG r3, 0x4C66F3A0; CHECKREG r4, 0x56B8F2FB; CHECKREG r5, 0x678DF1EE; CHECKREG r6, 0x7444F122; CHECKREG r7, 0x86660000; imm32 r0, 0xabd78911; imm32 r1, 0x2789ab1d; imm32 r2, 0xd4445515; imm32 r3, 0x4e667717; imm32 r4, 0x56f8891b; imm32 r5, 0x678aab1d; imm32 r6, 0x7444b515; imm32 r7, 0x86667d77; R6.L = R2 - R3 (RND20); R1.L = R4 - R5 (RND20); R5.L = R7 - R2 (RND20); R3.L = R0 - R0 (RND20); R0.L = R3 - R4 (RND20); R2.L = R5 - R7 (RND20); R7.L = R6 - R7 (RND20); R4.L = R1 - R6 (RND20); CHECKREG r0, 0xABD7FF77; CHECKREG r1, 0x2789FEF7; CHECKREG r2, 0xD4440E12; CHECKREG r3, 0x4E660000; CHECKREG r4, 0x56F8FB34; CHECKREG r5, 0x678AFB22; CHECKREG r6, 0x7444F85E; CHECKREG r7, 0x86660EDE; imm32 r0, 0x15678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x34445515; imm32 r3, 0x46667717; imm32 r4, 0x5678891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x74445515; imm32 r7, 0x86667777; R3.L = R4 - R0 (RND20); R1.L = R6 - R3 (RND20); R4.L = R3 - R2 (RND20); R6.L = R7 - R1 (RND20); R2.L = R5 - R4 (RND20); R7.L = R2 - R7 (RND20); R0.L = R1 - R6 (RND20); R5.L = R0 - R5 (RND20); CHECKREG r0, 0x1567FB34; CHECKREG r1, 0x278902DE; CHECKREG r2, 0x34440111; CHECKREG r3, 0x46660411; CHECKREG r4, 0x56780122; CHECKREG r5, 0x6789FADE; CHECKREG r6, 0x7444F5EE; CHECKREG r7, 0x86660ADE; pass
tactcomplabs/xbgas-binutils-gdb	3,646	sim/testsuite/bfin/c_dsp32shift_amix.s	//Original:/testcases/core/c_dsp32shift_amix/c_dsp32shift_amix.dsp // Spec Reference: dsp32shift ashift mix # mach: bfin .include "testutils.inc" start // Ashift (Arithmetic ) retain the sign bit (0-->0, 1-->1) imm32 r4, 0x00000000; imm32 r5, 0x00000000; imm32 r6, 0x00000000; imm32 r7, 0x00000000; // Ashift : positive data, count (+)=left (half reg) imm32 r0, 0x00010001; imm32 r1, 1; imm32 r2, 0x00020002; imm32 r3, 2; R4.H = ASHIFT R0.H BY R1.L; R4.L = ASHIFT R0.L BY R1.L; /* r4 = 0x00020002 / R5.H = ASHIFT R2.H BY R3.L; R5.L = ASHIFT R2.L BY R3.L; / r5 = 0x00080008 / R6 = ASHIFT R0 BY R1.L (V); / r6 = 0x00020002 / R7 = ASHIFT R2 BY R3.L (V); / r7 = 0x00080008 / CHECKREG r4, 0x00020002; CHECKREG r5, 0x00080008; CHECKREG r6, 0x00020002; CHECKREG r7, 0x00080008; // Ashift : (full reg) imm32 r1, 3; imm32 r3, 4; R6 = ASHIFT R0 BY R1.L; / r6 = 0x00080010 / R7 = ASHIFT R2 BY R3.L; CHECKREG r6, 0x00080008; / r7 = 0x00100010 / CHECKREG r7, 0x00200020; A0 = 0; A0.L = R0.L; A0.H = R0.H; A0 = ASHIFT A0 BY R1.L; / a0 = 0x00080008 / R5 = A0.w; / r5 = 0x00080008 / CHECKREG r5, 0x00080008; imm32 r4, 0x30000003; imm32 r1, 1; R5 = ASHIFT R4 BY R1.L; / r5 = 0x60000006 / CHECKREG r5, 0x60000006; imm32 r1, 2; R5 = ASHIFT R4 BY R1.L; / r5 = 0xc000000c like LSHIFT / CHECKREG r5, 0xc000000c; // Ashift : count (-)=right (half reg) imm32 r0, 0x10001000; imm32 r1, -1; imm32 r2, 0x10001000; imm32 r3, -2; R4.H = ASHIFT R0.H BY R1.L; R4.L = ASHIFT R0.L BY R1.L; / r4 = 0x08000800 / R5.H = ASHIFT R2.H BY R3.L; R5.L = ASHIFT R2.L BY R3.L; / r4 = 0x04000400 / R6 = ASHIFT R0 BY R1.L (V); / r4 = 0x08000800 / R7 = ASHIFT R2 BY R3.L (V); / r4 = 0x04000400 / CHECKREG r4, 0x08000800; CHECKREG r5, 0x04000400; CHECKREG r6, 0x08000800; CHECKREG r7, 0x04000400; // Ashift : (full reg) imm32 r1, -3; imm32 r3, -4; R6 = ASHIFT R0 BY R1.L; / r6 = 0x02000200 / R7 = ASHIFT R2 BY R3.L; / r7 = 0x01000100 / CHECKREG r6, 0x02000200; CHECKREG r7, 0x01000100; // NEGATIVE // Ashift : NEGATIVE data, count (+)=left (half reg) imm32 r0, 0xc00f800f; imm32 r1, 1; imm32 r2, 0xe00fe00f; imm32 r3, 2; R4.H = ASHIFT R0.H BY R1.L; R4.L = ASHIFT R0.L BY R1.L (S); / r4 = 0x801e801e / R5.H = ASHIFT R2.H BY R3.L; R5.L = ASHIFT R2.L BY R3.L; / r4 = 0x803c803c / CHECKREG r4, 0x801e8000; CHECKREG r5, 0x803c803c; imm32 r0, 0xc80fe00f; imm32 r2, 0xe40fe00f; imm32 r1, 4; imm32 r3, 5; R6 = ASHIFT R0 BY R1.L; / r6 = 0x80fe00f0 / R7 = ASHIFT R2 BY R3.L; / r7 = 0x81fc01e0 / CHECKREG r6, 0x80fe00f0; CHECKREG r7, 0x81fc01e0; imm32 r0, 0xf80fe00f; imm32 r2, 0xfc0fe00f; R6 = ASHIFT R0 BY R1.L (S); / r6 = 0x80fe00f0 / R7 = ASHIFT R2 BY R3.L (S); / r7 = 0x81fc01e0 / CHECKREG r6, 0x80fe00f0; CHECKREG r7, 0x81fc01e0; imm32 r0, 0xc80fe00f; imm32 r2, 0xe40fe00f; R6 = ASHIFT R0 BY R1.L (S); / r6 = 0x80000000 zero bubble tru MSB / R7 = ASHIFT R2 BY R3.L (S); / r7 = 0x80000000 / CHECKREG r6, 0x80000000; CHECKREG r7, 0x80000000; // Ashift : NEGATIVE data, count (-)=right (half reg) Working ok imm32 r0, 0x80f080f0; imm32 r1, -1; imm32 r2, 0x80f080f0; imm32 r3, -2; R4.H = ASHIFT R0.H BY R1.L; R4.L = ASHIFT R0.L BY R1.L; / r4 = 0xc078c078 / R5.H = ASHIFT R2.H BY R3.L; R5.L = ASHIFT R2.L BY R3.L; / r4 = 0xe03ce03c / CHECKREG r4, 0xc078c078; CHECKREG r5, 0xe03ce03c; R6 = ASHIFT R0 BY R1.L (V); / r6 = 0xc078c078 / R7 = ASHIFT R2 BY R3.L (V); / r7 = 0xe03ce03c / CHECKREG r6, 0xc078c078; CHECKREG r7, 0xe03ce03c; // Ashift : (full reg) imm32 r1, -3; imm32 r3, -4; R6 = ASHIFT R0 BY R1.L; / r6 = 0xf01e101e / R7 = ASHIFT R2 BY R3.L; / r7 = 0xf80f080f */ CHECKREG r6, 0xf01e101e; CHECKREG r7, 0xf80f080f; pass
tactcomplabs/xbgas-binutils-gdb	8,456	sim/testsuite/bfin/c_seq_ex3_ls_mmrj_mvp.S	//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmrj_mvp/c_seq_ex3_ls_mmrj_mvp.dsp // Spec Reference: sequencer stage ex3 (ldst + mmr + jump+ regmv + pushpopmultiple) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE DATA_ADDR_1 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK CSYNC; DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! // PUSH LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 //LD32(p2, DATA_ADDR_1); loadsym p2, DATA; LD32(p3, 0xab5fd490); LD32(p4, 0xa581bd94); LD32(r2, 0x14789232); [ P1 ] = R2; CSYNC; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; [ -- SP ] = ( R7:0 ); // RAISE 2; // RTN R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL1; P3 = R7; R4 = P3; [ -- SP ] = ( R7:0 ); R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; LABEL1: // RAISE 5; // RTI R2 = [ P2 ++ ]; P4 = R6; R3 = P4; [ -- SP ] = ( R7:0 ); R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; // wrt-rd EVT5 = 0xFFE02034 LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 RAISE 6; // RTI R4 = [ P2 ++ ]; R5 = [ P1 ]; JUMP.S LABEL2; P3 = R3; R6 = P3; [ -- SP ] = ( R7:0 ); // POP R0 = 0x00; R1 = 0x00; R2 = 0x00; R3 = 0x00; R4 = 0x00; R5 = 0x00; R6 = 0x00; R7 = 0x00; LABEL2: CSYNC; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x00000023); CHECKREG(r3, 0x00000024); CHECKREG(r4, 0x08090A0B); CHECKREG(r5, 0x14789232); CHECKREG(r6, 0x00000027); // RAISE 7; // RTI R0 = [ P2 ++ ]; R1 = [ P1 ]; P4 = R4; R2 = P4; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x04050607); CHECKREG(r3, 0x00000007); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); // wrt-rd EVT13 = 0xFFE02034 LD32(p1, 0xFFE02034); // RAISE 8; // RTI R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; //CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped //CHECKREG(r1, 0x000000b2); // so they cannot appear here //CHECKREG(r2, 0x000000c3); //CHECKREG(r3, 0x000000d4); //CHECKREG(r4, 0x000000e5); //CHECKREG(r5, 0x000000f6); //CHECKREG(r6, 0x00000017); //CHECKREG(r7, 0x00000028); R0 = 12; R1 = 13; R2 = 14; R3 = 15; R4 = 16; R5 = 17; R6 = 18; R7 = 19; LABEL3: CSYNC; CHECKREG(r0, 0x10111213); CHECKREG(r1, 0x14789232); // RAISE 9; // RTI P3 = R6; R7 = P3; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000003); CHECKREG(r3, 0x00000004); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG(r0, 0x00000000); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x00000002); CHECKREG(r3, 0x00000000); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 I0 += 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 I1 += 2; RTI; THANDLE: // Timer Handler 6 I2 += 2; RTI; I7HANDLE: // IVG 7 Handler I3 += 2; RTI; I8HANDLE: // IVG 8 Handler I0 += 2; RTI; I9HANDLE: // IVG 9 Handler I0 += 2; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .section MEM_DATA_ADDR_1,"aw" DATA: // .space (0x10); .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK: .section MEM_DATA_ADDR_2,"aw" .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0
tactcomplabs/xbgas-binutils-gdb	6,415	sim/testsuite/bfin/c_interr_pending.S	//Original:/proj/frio/dv/testcases/core/c_interr_pending/c_interr_pending.dsp // Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // // Include Files // include(std.inc) include(selfcheck.inc) // Defines #ifndef TCNTL #define TCNTL 0xFFE03000 #endif #ifndef TPERIOD #define TPERIOD 0xFFE03004 #endif #ifndef TSCALE #define TSCALE 0xFFE03008 #endif #ifndef TCOUNT #define TCOUNT 0xFFE0300c #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203c #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE 0x000FF000 #endif #ifndef PROGRAM_STACK #define PROGRAM_STACK 0x000FF100 #endif #ifndef STACKSIZE #define STACKSIZE 0x00000300 #endif // Boot code BOOT : INIT_R_REGS(0); // Initialize Dregs INIT_P_REGS(0); // Initialize Pregs // CHECK_INIT(p5, 0x00BFFFFC); // CHECK_INIT(p5, 0xE0000000); include(symtable.inc) CHECK_INIT_DEF(p5); LD32(sp, 0x000FF200); LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE); // IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK LD32_LABEL(p1, START); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; RAISE 15; // after we RTI, INT 15 should be taken LD32_LABEL(r7, START); RETI = r7; NOP; // Workaround for Bug 217 RTI; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; DUMMY: NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; //.code 0x200 START : P1 = 0x0; R7 = 0x0; R6 = 0x1; [ -- SP ] = RETI; // Enable Nested Interrupts CLI R1; // stop interrupt WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) WR_MMR(TPERIOD, 0x00000050, p0, r0); WR_MMR(TCOUNT, 0x00000013, p0, r0); WR_MMR(TSCALE, 0x00000000, p0, r0); CSYNC; // Read the contents of the Timer RD_MMR(TPERIOD, p0, r2); CHECKREG(r2, 0x00000050); // RD_MMR(TCOUNT, p0, r3); // CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910 WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) CSYNC; RD_MMR(TPERIOD, p0, r4); CHECKREG(r4, 0x00000050); // RD_MMR(TCNTL, p0, r5); // CHECKREG(r5, 0x0000000B); // INTERRUPT did happen WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; NOP; WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power WR_MMR(TPERIOD, 0x00000015, p0, r0); WR_MMR(TCOUNT, 0x00000013, p0, r0); WR_MMR(TSCALE, 0x00000002, p0, r0); WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1) CSYNC; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; JUMP.S label4; R4.L = 0x1111; // Will be killed R4.H = 0x1111; // Will be killed NOP; NOP; NOP; label5: R5.H = 0x7777; R5.L = 0x7888; JUMP.S label6; R5.L = 0x1111; // Will be killed R5.H = 0x1111; // Will be killed NOP; NOP; NOP; NOP; NOP; NOP; label4: R4.H = 0x5555; R4.L = 0x6666; NOP; JUMP.S label5; R5.L = 0x2222; // Will be killed R5.H = 0x2222; // Will be killed NOP; NOP; NOP; NOP; label6: R3.H = 0x7999; R3.L = 0x7aaa; NOP; NOP; NOP; NOP; NOP; NOP; NOP; // With auto reload // Read the contents of the Timer RAISE 7; RD_MMR(TPERIOD, p0, r2); CHECKREG(r2, 0x00000015); CHECKREG(p1, 0x00000000); // no interrupt being serviced CHECKREG(r7, 0x00000000); // no interrupt being serviced WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; STI R1; NOP; NOP; NOP; CHECKREG(r7, 0x00000001); // interrupt being serviced CHECKREG(p1, 0x00000001); // interrupt being serviced NOP; dbg_pass; // Call Endtest Macro //******************************************************************** // // Handlers for Events // //.code ITABLE EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 RTN; XHANDLE: // Exception Handler 3 RTX; HWHANDLE: // HW Error Handler 5 RTI; THANDLE: // Timer Handler 6 R7 = R7 + R6; RTI; I7HANDLE: // IVG 7 Handler P1 += 1; RTI; I8HANDLE: // IVG 8 Handler RTI; I9HANDLE: // IVG 9 Handler RTI; I10HANDLE: // IVG 10 Handler RTI; I11HANDLE: // IVG 11 Handler RTI; I12HANDLE: // IVG 12 Handler RTI; I13HANDLE: // IVG 13 Handler RTI; I14HANDLE: // IVG 14 Handler RTI; I15HANDLE: // IVG 15 Handler R5 = RETI; P0 = R5; JUMP ( P0 ); RTI; .section MEM_DATA_ADDR_1,"aw" .space (STACKSIZE); STACK: NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
tactcomplabs/xbgas-binutils-gdb	8,487	sim/testsuite/bfin/c_seq_wb_cs_lsmmrj_mvp.S	//Original:/proj/frio/dv/testcases/core/c_seq_wb_cs_lsmmrj_mvp/c_seq_wb_cs_lsmmrj_mvp.dsp // Spec Reference: sequencer:wb ( csync ldst mmr jump regmv pushpopmultiple) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE DATA_ADDR_1 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK CSYNC; DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! // PUSH LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 //LD32(p2, DATA_ADDR_1); loadsym P2, DATA; LD32(p3, 0xab5fd490); LD32(p4, 0xa581bd94); LD32(r2, 0x14789232); [ P1 ] = R2; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; [ -- SP ] = ( R7:0 ); // RAISE 2; // RTN CSYNC; R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL1; P3 = R7; R4 = P3; [ -- SP ] = ( R7:0 ); R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; LABEL1: // RAISE 5; // RTI CSYNC; R2 = [ P2 ++ ]; P4 = R6; R3 = P4; [ -- SP ] = ( R7:0 ); R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; // wrt-rd EVT5 = 0xFFE02034 LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 // RAISE 6; // RTI CSYNC; R4 = [ P2 ++ ]; R6 = [ P1 ]; JUMP.S LABEL2; P3 = R3; R5 = P3; [ -- SP ] = ( R7:0 ); // POP R0 = 0x00; R1 = 0x00; R2 = 0x00; R3 = 0x00; R4 = 0x00; R5 = 0x00; R6 = 0x00; R7 = 0x00; LABEL2: CSYNC; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x00000023); CHECKREG(r3, 0x00000024); CHECKREG(r4, 0x08090A0B); CHECKREG(r5, 0x00000026); CHECKREG(r6, 0x14789232); // RAISE 7; // RTI CSYNC; R0 = [ P2 ++ ]; R1 = [ P1 ]; P4 = R4; R2 = P4; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x04050607); CHECKREG(r3, 0x00000007); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); // wrt-rd EVT13 = 0xFFE02034 LD32(p1, 0xFFE02034); // RAISE 8; // RTI CSYNC; R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; //CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped //CHECKREG(r1, 0x000000b2); // so they cannot appear here //CHECKREG(r2, 0x000000c3); //CHECKREG(r3, 0x000000d4); //CHECKREG(r4, 0x000000e5); //CHECKREG(r5, 0x000000f6); //CHECKREG(r6, 0x00000017); //CHECKREG(r7, 0x00000028); R0 = 12; R1 = 13; R2 = 14; R3 = 15; R4 = 16; R5 = 17; R6 = 18; R7 = 19; LABEL3: CSYNC; CHECKREG(r0, 0x10111213); CHECKREG(r1, 0x14789232); // RAISE 9; // RTI CSYNC; P3 = R6; R7 = P3; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000003); CHECKREG(r3, 0x00000004); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG(r0, 0x00000000); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x00000000); CHECKREG(r3, 0x00000000); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 I0 += 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 I1 += 2; RTI; THANDLE: // Timer Handler 6 I2 += 2; RTI; I7HANDLE: // IVG 7 Handler I3 += 2; RTI; I8HANDLE: // IVG 8 Handler I0 += 2; RTI; I9HANDLE: // IVG 9 Handler I0 += 2; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .section MEM_DATA_ADDR_1,"aw" DATA: // .space (0x10); .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK: .section MEM_DATA_ADDR_2,"aw" .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0
tactcomplabs/xbgas-binutils-gdb	5,517	sim/testsuite/bfin/c_interr_excpt.S	//Original:/proj/frio/dv/testcases/core/c_interr_excpt/c_interr_excpt.dsp // Spec Reference: interr excpt # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE 0xF0000000 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // etc.) // BOOT: LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs SYSCFG = r0; RETS = r0; // prevent X's breaking LINK instruction // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; RAISE 15; // after we RTI, INT 15 should be taken RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! // Can't Raise 0, 3, or 4 // Raise 1 requires some intelligence so the test // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) R0 = 1; R1 = 2; R2 = 3; R3 = 4; EXCPT 1; // RTX EXCPT 2; // RTX EXCPT 3; // RTX EXCPT 4; // RTX EXCPT 5; // RTX EXCPT 5; // RTX EXCPT 6; // RTX EXCPT 7; // RTX EXCPT 8; // RTX EXCPT 9; // RTX EXCPT 10; // RTX EXCPT 11; // RTX EXCPT 12; // RTX EXCPT 13; // RTX EXCPT 14; // RTX EXCPT 15; // RTX CHECKREG(r0, 0x33333333); CHECKREG(r1, 0xCCCCCCCD); CHECKREG(r2, 0x00000000); CHECKREG(r3, 0x33333333); CHECKREG(r4, 0x00000000); CHECKREG(r5, 0x00000000); CHECKREG(r6, 0x00000000); CHECKREG(r7, 0x00000000); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 R0 = 2; RTN; XHANDLE: // Exception Handler 3 R0 = R1 + R2; R1 = R2 + R3; R2 = R0 + R1; R3 = R0 + R2; RTX; HWHANDLE: // HW Error Handler 5 R2 = 5; RTI; THANDLE: // Timer Handler 6 R3 = 6; RTI; I7HANDLE: // IVG 7 Handler R4 = 7; RTI; I8HANDLE: // IVG 8 Handler R5 = 8; RTI; I9HANDLE: // IVG 9 Handler R6 = 9; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // //.data 0xF0000000 .data DATA: .space (0x10); // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	7,980	sim/testsuite/bfin/s14.s	// reg-based SHIFT test program. // Test r4 = ASHIFT (r2 by rl3); // Test r4 = LSHIFT (r2 by rl3); # mach: bfin .include "testutils.inc" start R0.L = 0x0001; R0.H = 0x8000; // arithmetic // left by 31 // 8000 0001 -> 8000 0000 R7 = 0; ASTAT = R7; R3.L = 31; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x8000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 32 // 8000 0001 -> 8000 0000 R7 = 0; ASTAT = R7; R3.L = 32; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0xffff ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 40 // 8000 0001 -> 8000 0000 R7 = 0; ASTAT = R7; R3.L = 40; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0xFF80 ); DBGA ( R6.H , 0xFFFF ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by -32 // 8000 0001 -> 8000 0000 R7 = 0; ASTAT = R7; R3.L = -32; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0xffff ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 63 (off scale) // 8000 0001 -> 0000 0000 R7 = 0; ASTAT = R7; R0.L = 1; R0.H = 0; R3.L = 63; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 255 looks like -1 (mask 7 bits) // 8000 0001 -> 0000 0000 R7 = 0; ASTAT = R7; R0.L = 0x0100; R0.H = 0; R3.L = 255; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0x0080 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 1 // 8000 0001 -> 0000 0002 R0.L = 0x0001; R0.H = 0x8000; R3.L = 1; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0x0002 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // right by 1 // 8000 0001 -> 0000 0002 R0.L = 0x0001; R0.H = 0x8000; R3.L = -1; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0xc000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // right by -31 // 8000 0001 -> ffff ffff R0.L = 0x0001; R0.H = 0x8000; R3.L = -31; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0xffff ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // left by largest positive magnitude of 31 (0x1f) // 8000 0001 -> 8000 0000 R0.L = 0x0001; R0.H = 0x8000; R3.L = 31; R3.H = 0; R6 = ASHIFT R0 BY R3.L; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x8000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // left by 1 // 8000 0001 -> 0000 0002 R0.L = 0x0001; R0.H = 0x8000; R3.L = 1; R3.H = 0; R6 = LSHIFT R0 BY R3.L; DBGA ( R6.L , 0x0002 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // right by 1 // 8000 0001 -> 4000 0000 R0.L = 0x0001; R0.H = 0x8000; R3.L = -1; R3.H = 0; R6 = LSHIFT R0 BY R3.L; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x4000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // right by largest negative magnitude of -31 // 8000 0001 -> 0000 0001 R0.L = 0x0001; R0.H = 0x8000; R3.L = -31; R3.H = 0; R6 = LSHIFT R0 BY R3.L; DBGA ( R6.L , 0x0001 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // right by -32 // 8000 0001 -> 0000 0001 R0.L = 0x0001; R0.H = 0x8000; R3.L = -32; R3.H = 0; R6 = LSHIFT R0 BY R3.L; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // by +40 // 8000 0001 -> 0000 0001 R0.L = 0x0001; R0.H = 0x8000; R3.L = 40; R3.H = 0; R6 = LSHIFT R0 BY R3.L; DBGA ( R6.L , 0x0080 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // rot // left by 1 // 8000 0001 -> 0000 0002 cc=1 R7 = 0; CC = R7; R6 = ROT R0 BY 1; DBGA ( R6.L , 0x0002 ); DBGA ( R6.H , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // rot // right by -1 // 8000 0001 -> 4000 0000 cc=1 R7 = 0; CC = R7; R6 = ROT R0 BY -1; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x4000 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // rot // right by largest positive magnitude of 31 // 8000 0001 -> a000 0000 cc=0 R7 = 0; CC = R7; R6 = ROT R0 BY 31; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0xa000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // right by largest positive magnitude of 31 with cc=1 // 8000 0001 cc=1 -> a000 0000 cc=0 R7 = 1; CC = R7; R6 = ROT R0 BY 31; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0xe000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // right by largest negative magnitude of -31 // 8000 0001 -> 0000 0005 cc=0 R7 = 0; CC = R7; R6 = ROT R0 BY -31; DBGA ( R6.L , 0x0005 ); DBGA ( R6.H , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // right by largest negative magnitude of -31 with cc=1 // 8000 0001 cc=1 -> 0000 0007 cc=0 R7 = 1; CC = R7; R6 = ROT R0 BY -31; DBGA ( R6.L , 0x0007 ); DBGA ( R6.H , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // left by 7 // 8000 0001 cc=1 -> 0000 00e0 cc=0 R7 = 1; CC = R7; R6 = ROT R0 BY 7; DBGA ( R6.L , 0x00e0 ); DBGA ( R6.H , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot by zero // 8000 0001 -> 8000 000 R7 = 1; CC = R7; R6 = ROT R0 BY 0; DBGA ( R6.L , 0x0001 ); DBGA ( R6.H , 0x8000 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // 0 by 1 R7 = 0; R0 = 0; ASTAT = R7; R6 = R0 << 1; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); pass
tactcomplabs/xbgas-binutils-gdb	5,833	sim/testsuite/bfin/random_0029.S	# mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x2030ca00 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); dmm32 A1.w, 0xdf7ce5c7; dmm32 A1.x, 0xffffff9c; imm32 R0, 0x098ecb70; imm32 R1, 0x80000000; R1.H = (A1 += R0.L * R1.H) (M, ISS2); checkreg R1, 0x80000000; checkreg A1.w, 0xc534e5c7; checkreg A1.x, 0xffffff9c; checkreg ASTAT, (0x2030ca00 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); dmm32 ASTAT, (0x00100600 \| _VS \| _AQ \| _AZ); dmm32 A1.w, 0xdf39474d; dmm32 A1.x, 0xffffffd9; imm32 R2, 0x64864b87; imm32 R3, 0x61a97f85; imm32 R6, 0x1bcacb1a; R2.H = (A1 -= R6.L * R3.L) (M, ISS2); checkreg R2, 0x80004b87; checkreg A1.w, 0xf992dccb; checkreg A1.x, 0xffffffd9; checkreg ASTAT, (0x00100600 \| _VS \| _V \| _AQ \| _V_COPY \| _AZ); dmm32 ASTAT, (0x50f0c290 \| _VS \| _AC0 \| _AQ \| _CC \| _AC0_COPY); dmm32 A1.w, 0xb0a49eb4; dmm32 A1.x, 0x00000000; imm32 R0, 0x1a1607f3; imm32 R1, 0x6dcc7fff; imm32 R6, 0x80008000; R6.H = (A1 -= R1.L * R0.H) (M, ISS2); checkreg R6, 0x7fff8000; checkreg A1.w, 0xa399b8ca; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x50f0c290 \| _VS \| _V \| _AC0 \| _AQ \| _CC \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x48b04c10 \| _VS \| _AV1S \| _AV0S \| _AQ \| _CC \| _AC0_COPY \| _AN); dmm32 A1.w, 0x91b35cde; dmm32 A1.x, 0x0000006c; imm32 R1, 0xf473c458; imm32 R5, 0x1358b0c2; imm32 R7, 0xfbf00410; R5.H = (A1 -= R1.L * R7.H) (M, ISS2); checkreg R5, 0x7fffb0c2; checkreg A1.w, 0xcc69025e; checkreg A1.x, 0x0000006c; checkreg ASTAT, (0x48b04c10 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _CC \| _V_COPY \| _AC0_COPY \| _AN); dmm32 ASTAT, (0x1ca04210 \| _VS \| _AC0 \| _AQ \| _AN \| _AZ); dmm32 A1.w, 0xf516677c; dmm32 A1.x, 0x00000015; imm32 R5, 0x218d4960; imm32 R6, 0xfa8c8000; R5 = (A1 -= R6.L * R5.H) (M, ISS2); checkreg R5, 0x7fffffff; checkreg A1.w, 0x05dce77c; checkreg A1.x, 0x00000016; checkreg ASTAT, (0x1ca04210 \| _VS \| _V \| _AC0 \| _AQ \| _V_COPY \| _AN \| _AZ); dmm32 ASTAT, (0x04004490 \| _VS \| _AC1 \| _AN); dmm32 A1.w, 0xd1795d0a; dmm32 A1.x, 0x00000000; imm32 R2, 0x67bd270e; imm32 R3, 0xda302534; imm32 R7, 0x7fffa2af; R2.H = (A1 += R7.L * R3.L) (M, ISS2); checkreg R2, 0x7fff270e; checkreg A1.w, 0xc3e9b396; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x04004490 \| _VS \| _V \| _AC1 \| _V_COPY \| _AN); dmm32 ASTAT, (0x60600490 \| _VS \| _AV1S \| _AC1 \| _CC \| _AC0_COPY \| _AZ); dmm32 A1.w, 0xeb8abaea; dmm32 A1.x, 0x00000036; imm32 R1, 0x111687e8; imm32 R5, 0x111687e8; R1 = (A1 += R1.L * R5.L) (M, ISS2); checkreg R1, 0x7fffffff; checkreg A1.w, 0xabc93d2a; checkreg A1.x, 0x00000036; checkreg ASTAT, (0x60600490 \| _VS \| _V \| _AV1S \| _AC1 \| _CC \| _V_COPY \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x30200e80 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AQ \| _V_COPY \| _AN); dmm32 A1.w, 0xd3275e78; dmm32 A1.x, 0xffffff89; imm32 R3, 0xfee80d8d; imm32 R6, 0x1c1a8000; imm32 R7, 0x00000000; R3 = (A1 += R7.L * R6.L) (M, ISS2); checkreg R3, 0x80000000; checkreg A1.w, 0xd3275e78; checkreg A1.x, 0xffffff89; checkreg ASTAT, (0x30200e80 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AQ \| _V_COPY \| _AN); dmm32 ASTAT, (0x50208610 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _CC \| _AC0_COPY); dmm32 A1.w, 0xb3b71810; dmm32 A1.x, 0x00000000; imm32 R4, 0xfc2f7ffe; imm32 R5, 0x7fffffff; imm32 R7, 0x3488c040; R7.H = (A1 -= R4.L * R5.H) (M, ISS2); checkreg R7, 0x7fffc040; checkreg A1.w, 0x73b8980e; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x50208610 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _CC \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x48d04410 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ); dmm32 A1.w, 0xeb066305; dmm32 A1.x, 0xffffff9c; imm32 R0, 0x80002105; imm32 R4, 0xf4fbe11e; imm32 R7, 0xffffb83a; R7 = (A1 += R0.L * R4.L) (M, ISS2); checkreg R7, 0x80000000; checkreg A1.w, 0x080fa69b; checkreg A1.x, 0xffffff9d; checkreg ASTAT, (0x48d04410 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _V_COPY); dmm32 ASTAT, (0x3850c090 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _CC); dmm32 A1.w, 0xdfed6537; dmm32 A1.x, 0xffffffae; imm32 R0, 0xe962c700; imm32 R4, 0x32c97fff; imm32 R7, 0x28da7373; R4.H = (A1 += R7.L * R0.H) (M, ISS2); checkreg R4, 0x80007fff; checkreg A1.w, 0x492d423d; checkreg A1.x, 0xffffffaf; checkreg ASTAT, (0x3850c090 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _CC \| _V_COPY); dmm32 ASTAT, (0x78a0ce00 \| _VS \| _AV1S \| _AC0 \| _AQ \| _CC); dmm32 A1.w, 0x8c733a78; dmm32 A1.x, 0x0000002d; imm32 R1, 0x3840acb0; imm32 R3, 0x47b843ad; imm32 R7, 0x7fff4d00; R7 = (A1 += R1.L * R3.H) (M, ISS2); checkreg R7, 0x7fffffff; checkreg A1.w, 0x751c28f8; checkreg A1.x, 0x0000002d; checkreg ASTAT, (0x78a0ce00 \| _VS \| _V \| _AV1S \| _AC0 \| _AQ \| _CC \| _V_COPY); dmm32 ASTAT, (0x3cf08880 \| _VS \| _AV1S \| _AV0S \| _AC0); dmm32 A1.w, 0xbde0b55f; dmm32 A1.x, 0xfffffffd; imm32 R0, 0x80002300; imm32 R5, 0x635db45a; imm32 R7, 0x67e67af3; R7 = (A1 += R0.L * R5.L) (M, ISS2); checkreg R7, 0x80000000; checkreg A1.w, 0xd689035f; checkreg A1.x, 0xfffffffd; checkreg ASTAT, (0x3cf08880 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _V_COPY); dmm32 ASTAT, (0x58608410 \| _VS \| _AQ \| _CC \| _AZ); dmm32 A1.w, 0xe4660b32; dmm32 A1.x, 0xffffff84; imm32 R1, 0x2c6c9118; imm32 R2, 0x007793ad; imm32 R7, 0x526c17d9; R1.H = (A1 -= R2.L * R7.L) (M, ISS2); checkreg R1, 0x80009118; checkreg A1.w, 0xee7d528d; checkreg A1.x, 0xffffff84; checkreg ASTAT, (0x58608410 \| _VS \| _V \| _AQ \| _CC \| _V_COPY \| _AZ); dmm32 ASTAT, (0x2020c210 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AC0_COPY \| _AN); dmm32 A1.w, 0x8da6c28f; dmm32 A1.x, 0x00000000; imm32 R1, 0x0000fff7; imm32 R4, 0xf85a0000; imm32 R7, 0x7fff0000; R7 = (A1 += R4.L * R1.L) (M, ISS2); checkreg R7, 0x7fffffff; checkreg A1.w, 0x8da6c28f; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x2020c210 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _V_COPY \| _AC0_COPY \| _AN); pass
tactcomplabs/xbgas-binutils-gdb	2,651	sim/testsuite/bfin/c_ccflag_a0a1.S	//Original:/testcases/core/c_ccflag_a0a1/c_ccflag_a0a1.dsp // Spec Reference: ccflag a0-a1 (==, <, <=) # mach: bfin #include "test.h" .include "testutils.inc" start imm32 r0, 0x12345778; imm32 r1, 0x12345678; imm32 r2, 0x056789ab; imm32 r3, 0x80231345; imm32 r4, 0x00770088; imm32 r5, 0x009900aa; imm32 r6, 0x00bb00cc; imm32 r7, _UNSET; ASTAT = R7; R4 = ASTAT; A0 = R0; A1 = R0; // positive a0 EQUAL to a1 CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CHECKREG r4, _UNSET; CHECKREG r5, (_AC0\|_CC\|_AC0_COPY\|_AZ); CHECKREG r6, (_AC0\|_AC0_COPY\|_AZ); CC = A0 <= A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r5, (_AC0\|_CC\|_AC0_COPY\|_AZ); CHECKREG r6, (_AC0\|_AC0_COPY\|_AZ); CHECKREG r7, (_AC0\|_CC\|_AC0_COPY\|_AZ); // positive a0 GREATER than to positive a1 A1 = R1; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r5, (_AC0\|_AC0_COPY); // carry CHECKREG r6, (_AC0\|_AC0_COPY); CHECKREG r7, (_AC0\|_AC0_COPY); // positive a0 LESS than to positive a1 A1 = R2; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r5, (_AC0\|_AC0_COPY); CHECKREG r6, (_AC0\|_AC0_COPY); CHECKREG r7, (_AC0\|_AC0_COPY); // positive a0 GREATER than to neg a1 A1 = R3; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r5, _UNSET; CHECKREG r6, _UNSET; CHECKREG r7, _UNSET; // negative a0 and positive a1 imm32 r0, -1; imm32 r1, 2; imm32 r2, -3; imm32 r3, -4; A0 = R0; A1 = R1; R7 = 0; ASTAT = R7; R4 = ASTAT; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r4, _UNSET; CHECKREG r5, (_AC0\|_AC0_COPY\|_AN); CHECKREG r6, (_AC0\|_AC0_COPY\|_CC\|_AN); CHECKREG r7, (_AC0\|_AC0_COPY\|_CC\|_AN); // negative a0 LESS than neg a1 A0 = R3; A1 = R4; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r4, _UNSET; CHECKREG r5, (_AC0\|_AC0_COPY\|_AN); CHECKREG r6, (_AC0\|_AC0_COPY\|_CC\|_AN); CHECKREG r7, (_AC0\|_AC0_COPY\|_CC\|_AN); // negative a0 GREATER neg a1 A0 = R0; A1 = R3; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r4, _UNSET; CHECKREG r5, (_AC0\|_AC0_COPY); CHECKREG r6, (_AC0\|_AC0_COPY); CHECKREG r7, (_AC0\|_AC0_COPY); // negative a0 EQUAL neg imm3 A0 = R3; A1 = R3; CC = A0 == A1; R5 = ASTAT; CC = A0 < A1; R6 = ASTAT; CC = A0 <= A1; R7 = ASTAT; CHECKREG r4, _UNSET; CHECKREG r5, (_AC0\|_CC\|_AC0_COPY\|_AZ); CHECKREG r6, (_AC0\|_AC0_COPY\|_AZ); CHECKREG r7, (_AC0\|_CC\|_AC0_COPY\|_AZ); pass
tactcomplabs/xbgas-binutils-gdb	6,250	sim/testsuite/bfin/c_dsp32mac_pair_a0_i.s	//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_i/c_dsp32mac_pair_a0_i.dsp // Spec Reference: dsp32mac pair a0 I # mach: bfin .include "testutils.inc" start A1 = A0 = 0; // The result accumulated in A , and stored to a reg half imm32 r0, 0x63545abd; imm32 r1, 0x86bcfec7; imm32 r2, 0xa8645679; imm32 r3, 0x00860007; imm32 r4, 0xefb86569; imm32 r5, 0x1235860b; imm32 r6, 0x000c086d; imm32 r7, 0x678e0086; A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (IS); P1 = A0.w; A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (IS); P5 = A1.w; P2 = A0.w; A1 = R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (IS); P3 = A0.w; A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (IS); P4 = A0.w; CHECKREG r0, 0xFFFD9ABC; CHECKREG r1, 0x86BCFEC7; CHECKREG r2, 0xF9679ACC; CHECKREG r3, 0x00860007; CHECKREG r4, 0xF857FE25; CHECKREG r5, 0x1235860B; CHECKREG r6, 0x006EF115; CHECKREG r7, 0x678E0086; CHECKREG p1, 0x006EF115; CHECKREG p2, 0xFFFD9ABC; CHECKREG p3, 0xF9679ACC; CHECKREG p4, 0xF857FE25; CHECKREG p5, 0x00025D4F; imm32 r0, 0x98764abd; imm32 r1, 0xa1bcf4c7; imm32 r2, 0xa1145649; imm32 r3, 0x00010005; imm32 r4, 0xefbc1569; imm32 r5, 0x1235010b; imm32 r6, 0x000c001d; imm32 r7, 0x678e0001; A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (IS); P1 = A0.w; A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (IS); P2 = A0.w; A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (IS); P3 = A0.w; A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (IS); P4 = A0.w; CHECKREG r0, 0xFC8B26EA; CHECKREG r1, 0xA1BCF4C7; CHECKREG r2, 0xFC7F6BD4; CHECKREG r3, 0x00010005; CHECKREG r4, 0xFCB93CEB; CHECKREG r5, 0x1235010B; CHECKREG r6, 0x000C001D; CHECKREG r7, 0x678E0001; CHECKREG p1, 0xFCB93CEB; CHECKREG p2, 0xFCBB1787; CHECKREG p3, 0xFC7F6BD4; CHECKREG p4, 0xFC8B26EA; imm32 r0, 0x7136459d; imm32 r1, 0xabd69ec7; imm32 r2, 0x71145679; imm32 r3, 0x08010007; imm32 r4, 0xef9c1569; imm32 r5, 0x1225010b; imm32 r6, 0x0003401d; imm32 r7, 0x678e0561; A1 += R1.H * R0.L, R4 = ( A0 -= R1.L * R0.L ) (IS); P1 = A0.w; A1 -= R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (IS); P2 = A0.w; A1 = R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (IS); P3 = A0.w; A1 -= R6.H * R7.L, R4 = ( A0 += R6.L * R7.H ) (IS); P4 = A0.w; CHECKREG r0, 0x01A40FD3; CHECKREG r1, 0xABD69EC7; CHECKREG r2, 0x71145679; CHECKREG r3, 0x08010007; CHECKREG r4, 0x0B2A737B; CHECKREG r5, 0x1225010B; CHECKREG r6, 0x0003178C; CHECKREG r7, 0x678E0561; CHECKREG p1, 0x16FB23DF; CHECKREG p2, 0x0003178C; CHECKREG p3, 0x01A40FD3; CHECKREG p4, 0x0B2A737B; imm32 r0, 0x123489bd; imm32 r1, 0x91bcfec7; imm32 r2, 0xa9145679; imm32 r3, 0xd0910007; imm32 r4, 0xedb91569; imm32 r5, 0xd235910b; imm32 r6, 0x0d0c0999; imm32 r7, 0x67de0009; A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (IS); P1 = A0.w; A1 = R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (IS); P2 = A0.w; A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (IS); P3 = A0.w; A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (IS); P4 = A0.w; CHECKREG r0, 0xFFFCF74D; CHECKREG r1, 0x91BCFEC7; CHECKREG r2, 0xFF92B0C1; CHECKREG r3, 0xD0910007; CHECKREG r4, 0xFF911149; CHECKREG r5, 0xD235910B; CHECKREG r6, 0x007295B5; CHECKREG r7, 0x67DE0009; CHECKREG p1, 0xFFFCF74D; CHECKREG p2, 0xFF92B0C1; CHECKREG p3, 0xFF911149; CHECKREG p4, 0x007295B5; imm32 r0, 0x63545abd; imm32 r1, 0x86bcfec7; imm32 r2, 0xa8645679; imm32 r3, 0x00860007; imm32 r4, 0xefb86569; imm32 r5, 0x1235860b; imm32 r6, 0x000c086d; imm32 r7, 0x678e0086; A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ) (IS); P5 = A1.w; P1 = A0.w; A1 -= R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (IS); P2 = A0.w; A1 = R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (IS); P3 = A0.w; A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (IS); P4 = A0.w; CHECKREG r0, 0xFFFD9ABC; CHECKREG r1, 0x86BCFEC7; CHECKREG r2, 0xF9679ACC; CHECKREG r3, 0x00860007; CHECKREG r4, 0xFA773773; CHECKREG r5, 0x1235860B; CHECKREG r6, 0xFF910EEB; CHECKREG r7, 0x678E0086; CHECKREG p1, 0xFF910EEB; CHECKREG p2, 0xFFFD9ABC; CHECKREG p3, 0xF9679ACC; CHECKREG p4, 0xFA773773; CHECKREG p5, 0xFF89C73F; imm32 r0, 0x98764abd; imm32 r1, 0xa1bcf4c7; imm32 r2, 0xa1145649; imm32 r3, 0x00010005; imm32 r4, 0xefbc1569; imm32 r5, 0x1235010b; imm32 r6, 0x000c001d; imm32 r7, 0x678e0001; R4 = ( A0 -= R1.L * R0.L ) (IS); P1 = A0.w; R0 = ( A0 = R2.H * R3.L ) (IS); P2 = A0.w; R2 = ( A0 += R4.H * R5.H ) (IS); P3 = A0.w; R0 = ( A0 += R6.L * R7.H ) (IS); P4 = A0.w; CHECKREG r0, 0xFFE0B29B; CHECKREG r1, 0xA1BCF4C7; CHECKREG r2, 0xFFD4F785; CHECKREG r3, 0x00010005; CHECKREG r4, 0xFDBDFA88; CHECKREG r5, 0x1235010B; CHECKREG r6, 0x000C001D; CHECKREG r7, 0x678E0001; CHECKREG p1, 0xFDBDFA88; CHECKREG p2, 0xFFFE2564; CHECKREG p3, 0xFFD4F785; CHECKREG p4, 0xFFE0B29B; imm32 r0, 0x7136459d; imm32 r1, 0xabd69ec7; imm32 r2, 0x71145679; imm32 r3, 0x08010007; imm32 r4, 0xef9c1569; imm32 r5, 0x1225010b; imm32 r6, 0x0003401d; imm32 r7, 0x678e0561; A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (IS); P1 = A0.w; R6 = ( A0 -= R2.H * R3.L ) (IS); P2 = A0.w; A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (IS); P3 = A0.w; R4 = ( A0 += R6.L * R7.H ) (IS); P4 = A0.w; CHECKREG r0, 0xE3AD394F; CHECKREG r1, 0xABD69EC7; CHECKREG r2, 0x71145679; CHECKREG r3, 0x08010007; CHECKREG r4, 0xDB61F2C1; CHECKREG r5, 0x1225010B; CHECKREG r6, 0xE58CEB7F; CHECKREG r7, 0x678E0561; CHECKREG p1, 0xE590030B; CHECKREG p2, 0xE58CEB7F; CHECKREG p3, 0xE3AD394F; CHECKREG p4, 0xDB61F2C1; imm32 r0, 0x123489bd; imm32 r1, 0x91bcfec7; imm32 r2, 0xa9145679; imm32 r3, 0xd0910007; imm32 r4, 0xedb91569; imm32 r5, 0xd235910b; imm32 r6, 0x0d0c0999; imm32 r7, 0x67de0009; R0 = ( A0 = R5.L * R3.L ) (IS); P1 = A0.w; A1 -= R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (IS); P2 = A0.w; A1 = R7.H * R0.H (M), R4 = ( A0 += R7.H * R0.H ) (IS); P3 = A0.w; R6 = ( A0 += R4.L * R6.H ) (IS); P4 = A0.w; CHECKREG r0, 0xFFFCF74D; CHECKREG r1, 0x91BCFEC7; CHECKREG r2, 0x006A468C; CHECKREG r3, 0xD0910007; CHECKREG r4, 0x0068A714; CHECKREG r5, 0xD235910B; CHECKREG r6, 0xFBE08004; CHECKREG r7, 0x67DE0009; CHECKREG p1, 0xFFFCF74D; CHECKREG p2, 0x006A468C; CHECKREG p3, 0x0068A714; CHECKREG p4, 0xFBE08004; pass
tactcomplabs/xbgas-binutils-gdb	6,888	sim/testsuite/bfin/random_0019.S	# Test a few (W32) corner cases # mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x68b0ca90 \| _VS \| _AV1S \| _AV0S \| _CC \| _AC0_COPY \| _AN \| _AZ); dmm32 A1.w, 0x70da33ff; dmm32 A1.x, 0x0000000f; imm32 R0, 0x5e29f819; imm32 R1, 0x3f59520b; A1 += R0.L * R1.L (M, W32); checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x68b0ca90 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _CC \| _AC0_COPY \| _AN \| _AZ); dmm32 ASTAT, (0x18300c10 \| _VS \| _AV1S \| _AN); dmm32 A0.w, 0x1096b1c1; dmm32 A0.x, 0xfffffff1; imm32 R6, 0x3a0178ee; imm32 R7, 0x17c95e45; A0 -= R6.L * R7.L (W32); checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x18300c10 \| _VS \| _AV1S \| _AV0S \| _AV0 \| _AN); dmm32 ASTAT, (0x68508800 \| _VS \| _AV1S \| _AV0S \| _CC \| _AZ); dmm32 A0.w, 0x30c8f917; dmm32 A0.x, 0xffffffc8; imm32 R3, 0x7ad1091c; imm32 R4, 0x80002874; A0 -= R3.L * R4.L (W32); checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x68508800 \| _VS \| _AV1S \| _AV0S \| _AV0 \| _CC \| _AZ); dmm32 ASTAT, (0x58708e90 \| _VS \| _AV0 \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0x13de4c3d; dmm32 A0.x, 0xffffffa5; imm32 R0, 0xf70f956f; imm32 R2, 0xf837e08c; A0 -= R0.L * R2.H (W32); checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x58708e90 \| _VS \| _AV0S \| _AV0 \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x70800280 \| _VS \| _AV1S \| _AC1 \| _AQ \| _CC \| _AC0_COPY); dmm32 A0.w, 0x80140410; dmm32 A0.x, 0x00000000; imm32 R1, 0x028b09a4; imm32 R4, 0x00007ffc; A0 += R4.L * R1.H (W32); checkreg A0.w, 0x7fffffff; checkreg A0.x, 0x00000000; checkreg ASTAT, (0x70800280 \| _VS \| _AV1S \| _AV0S \| _AV0 \| _AC1 \| _AQ \| _CC \| _AC0_COPY); dmm32 ASTAT, (0x0060c610 \| _VS \| _AC1 \| _AC0 \| _AC0_COPY \| _AN \| _AZ); dmm32 A1.w, 0x1794b937; dmm32 A1.x, 0xfffffff5; imm32 R6, 0x008e1c0d; A1 -= R6.L * R6.L (W32); checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x0060c610 \| _VS \| _AV1S \| _AV1 \| _AC1 \| _AC0 \| _AC0_COPY \| _AN \| _AZ); dmm32 ASTAT, (0x2c600410 \| _VS \| _AV0S \| _AC1 \| _CC \| _AN); dmm32 A1.w, 0x2d03ef79; dmm32 A1.x, 0x00000079; imm32 R5, 0x15d1b500; imm32 R6, 0xf7962b39; A1 += R6.L * R5.H (W32); checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x2c600410 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AC1 \| _CC \| _AN); dmm32 ASTAT, (0x5cf04e10 \| _VS \| _AV0S \| _AC1 \| _CC \| _AC0_COPY); dmm32 A0.w, 0x4d50b3f0; dmm32 A0.x, 0xfffffffc; imm32 R4, 0x6671002a; imm32 R7, 0x00288000; A0 += R4.L * R7.L (W32); checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x5cf04e10 \| _VS \| _AV0S \| _AV0 \| _AC1 \| _CC \| _AC0_COPY); dmm32 ASTAT, (0x28908000 \| _VS \| _V \| _AV1S \| _AV0S \| _AQ \| _V_COPY \| _AN); dmm32 A1.w, 0xc94e99f1; dmm32 A1.x, 0x00000021; imm32 R4, 0x7fff52b7; imm32 R7, 0x3ebb26c6; A1 += R7.L * R4.L (M, W32); checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x28908000 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _V_COPY \| _AN); dmm32 ASTAT, (0x34708a00 \| _VS \| _AV0S \| _AQ \| _CC \| _AC0_COPY); dmm32 A1.w, 0xf61f316d; dmm32 A1.x, 0x00000061; imm32 R1, 0x86f0ffff; imm32 R3, 0x791048c5; A1 += R1.L * R3.L (M, W32); checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x34708a00 \| _VS \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _CC \| _AC0_COPY); dmm32 ASTAT, (0x5020c280 \| _VS \| _V \| _AC1 \| _AC0 \| _V_COPY); dmm32 A1.w, 0x8700591f; dmm32 A1.x, 0x00000007; imm32 R2, 0x145b00b1; imm32 R3, 0x7fffffff; A1 -= R3.L * R2.H (M, W32); checkreg A1.w, 0x7fffffff; checkreg A1.x, 0x00000000; checkreg ASTAT, (0x5020c280 \| _VS \| _V \| _AV1S \| _AV1 \| _AC1 \| _AC0 \| _V_COPY); dmm32 ASTAT, (0x00000290 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AQ \| _CC \| _V_COPY); dmm32 A0.w, 0xfe84e1ec; dmm32 A0.x, 0xffffffff; imm32 R1, 0x07e73e7b; imm32 R3, 0x00033e7b; A0 -= R3.L * R1.H (W32); checkreg A0.w, 0xfaa965f2; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x00000290 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AQ \| _CC \| _V_COPY); dmm32 ASTAT, (0x78204a80 \| _VS \| _AV1S \| _CC \| _AN); dmm32 A0.w, 0xca398210; dmm32 A0.x, 0xffffffff; imm32 R3, 0xffff0000; imm32 R7, 0x00000000; A0 += R7.L * R3.L (W32); checkreg ASTAT, (0x78204a80 \| _VS \| _AV1S \| _CC \| _AN); dmm32 ASTAT, (0x04208890 \| _VS \| _AC1 \| _AC0_COPY); dmm32 A0.w, 0x224cbaee; dmm32 A0.x, 0x00000000; imm32 R3, 0x3db86584; imm32 R6, 0xdb505ed8; A0 -= R6.L * R3.H (W32); checkreg A0.w, 0xf491746e; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x04208890 \| _VS \| _AC1 \| _AC0_COPY); dmm32 ASTAT, (0x3c908600 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 A0.w, 0x03f7c0ec; dmm32 A0.x, 0x00000000; imm32 R1, 0x1c25c7b4; imm32 R5, 0x3f7da612; A0 -= R5.L * R1.L (W32); checkreg A0.w, 0xdc6a3b9c; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x3c908600 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x7cb08680 \| _VS \| _AQ \| _CC \| _AN); dmm32 A0.w, 0xdc7c243c; dmm32 A0.x, 0xffffffff; imm32 R0, 0xe2ccef4c; imm32 R5, 0x7fff8000; A0 += R5.L * R0.L (W32); checkreg A0.w, 0xed30243c; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x7cb08680 \| _VS \| _AQ \| _CC \| _AN); dmm32 ASTAT, (0x78f00080 \| _VS \| _V \| _AV1S \| _AC1 \| _AQ \| _V_COPY \| _AN); dmm32 A0.w, 0x39180f38; dmm32 A0.x, 0x00000000; imm32 R4, 0x01308ac1; imm32 R6, 0x7ffff8fd; A0 = R6.L * R4.H (W32); checkreg A0.w, 0xffef58e0; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x78f00080 \| _VS \| _V \| _AV1S \| _AC1 \| _AQ \| _V_COPY \| _AN); dmm32 ASTAT, (0x7050c090 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _V_COPY \| _AC0_COPY \| _AN); dmm32 A1.w, 0x010909b0; dmm32 A1.x, 0x00000000; imm32 R0, 0x80000000; imm32 R6, 0x6ad06150; A1 = R6.L * R0.H (W32); checkreg A1.w, 0x9eb00000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x7050c090 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _V_COPY \| _AC0_COPY \| _AN); dmm32 ASTAT, (0x68c04c10 \| _VS \| _V \| _AV0S \| _AC0 \| _AQ \| _V_COPY \| _AN); dmm32 A0.w, 0x43687862; dmm32 A0.x, 0x00000000; imm32 R2, 0xff278000; imm32 R4, 0x0000436a; A0 += R2.L * R4.L (W32); checkreg A0.w, 0xfffe7862; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x68c04c10 \| _VS \| _V \| _AV0S \| _AC0 \| _AQ \| _V_COPY \| _AN); dmm32 ASTAT, (0x74a00200 \| _AV1 \| _AV0S \| _AV0 \| _AC1 \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); dmm32 A1.w, 0x64c15e6b; dmm32 A1.x, 0xffffff87; imm32 R4, 0x30b3e20d; imm32 R7, 0x4a562069; A1 = R4.L * R7.H (M, W32); checkreg A1.w, 0xf74db25e; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x74a00200 \| _AV0S \| _AV0 \| _AC1 \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); dmm32 ASTAT, (0x70f08410 \| _AV0 \| _AC1 \| _AC0_COPY \| _AN \| _AZ); dmm32 A0.w, 0x5f011b0d; dmm32 A0.x, 0xffffff86; imm32 R3, 0x21f93a90; imm32 R4, 0x1c82d429; A0 = R3.H * R4.L (W32); checkreg A0.w, 0xf45d49c2; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x70f08410 \| _AC1 \| _AC0_COPY \| _AN \| _AZ); pass
tactcomplabs/xbgas-binutils-gdb	3,816	sim/testsuite/bfin/c_ldimmhalf_pibml.s	//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_pibml/c_ldimmhalf_pibml.dsp // Spec Reference: ldimmhalf p i b m l # mach: bfin .include "testutils.inc" start // set all reg=-1 //p0 =0x0123; P1 = 0x1234 (X); P2 = 0x2345 (X); P3 = 0x3456 (X); P4 = 0x4567 (X); P5 = 0x5678 (X); FP = 0x6789 (X); SP = 0x789a (X); //CHECKREG p0, 0x00000123; CHECKREG p1, 0x00001234; CHECKREG p2, 0x00002345; CHECKREG p3, 0x00003456; CHECKREG p4, 0x00004567; CHECKREG p5, 0x00005678; CHECKREG fp, 0x00006789; CHECKREG sp, 0x0000789A; //p0 = -32768; P1 = -32768 (X); P2 = -2222 (X); P3 = -3333 (X); P4 = -4444 (X); P5 = -5555 (X); FP = -6666 (X); SP = -7777 (X); //CHECKREG r0, 0xFFFF8000; CHECKREG p1, 0xFFFF8000; CHECKREG p2, 0xFFFFF752; CHECKREG p3, 0xFFFFF2FB; CHECKREG p4, 0xFFFFEEA4; CHECKREG p5, 0xFFFFEA4D; CHECKREG fp, 0xFFFFE5F6; CHECKREG sp, 0xFFFFE19F; //p0 =0x0123; P1 = 0x7abc (X); P2 = 0x6def (X); P3 = 0x5f56 (X); P4 = 0x7dd7 (X); P5 = 0x4abd (X); FP = 0x7fff (X); SP = 0x7ffa (X); //CHECKREG p0, 0x00000123; CHECKREG p1, 0x00007abc; CHECKREG p2, 0x00006def; CHECKREG p3, 0x00005f56; CHECKREG p4, 0x00007dd7; CHECKREG p5, 0x00004abd; CHECKREG fp, 0x00007fff; CHECKREG sp, 0x00007ffa; I0 = 0x0123 (X); I1 = 0x1234 (X); I2 = 0x2345 (X); I3 = 0x3456 (X); B0 = 0x0567 (X); B1 = 0x1678 (X); B2 = 0x2789 (X); B3 = 0x389a (X); R0 = I0; R1 = I1; R2 = I2; R3 = I3; R4 = B0; R5 = B1; R6 = B2; R7 = B3; CHECKREG r0, 0x00000123; CHECKREG r1, 0x00001234; CHECKREG r2, 0x00002345; CHECKREG r3, 0x00003456; CHECKREG r4, 0x00000567; CHECKREG r5, 0x00001678; CHECKREG r6, 0x00002789; CHECKREG r7, 0x0000389A; I0 = -32768 (X); I1 = -12345 (X); I2 = -23456 (X); I3 = -3456 (X); B0 = -4567 (X); B1 = -5678 (X); B2 = -6678 (X); B3 = -7012 (X); R0 = I0; R1 = I1; R2 = I2; R3 = I3; R4 = B0; R5 = B1; R6 = B2; R7 = B3; CHECKREG r0, 0xFFFF8000; CHECKREG r1, 0xFFFFCFC7; CHECKREG r2, 0xFFFFA460; CHECKREG r3, 0xFFFFF280; CHECKREG r4, 0xFFFFEE29; CHECKREG r5, 0xFFFFE9D2; CHECKREG r6, 0xFFFFE5EA; CHECKREG r7, 0xFFFFE49C; I0 = 0x7abd (X); I1 = 0x7bf4 (X); I2 = 0x6c45 (X); I3 = 0x7d56 (X); B0 = 0x7e67 (X); B1 = 0x7f78 (X); B2 = 0x7ff9 (X); B3 = 0x7fff (X); R0 = I0; R1 = I1; R2 = I2; R3 = I3; R4 = B0; R5 = B1; R6 = B2; R7 = B3; CHECKREG r0, 0x00007abd; CHECKREG r1, 0x00007bf4; CHECKREG r2, 0x00006c45; CHECKREG r3, 0x00007d56; CHECKREG r4, 0x00007e67; CHECKREG r5, 0x00007f78; CHECKREG r6, 0x00007ff9; CHECKREG r7, 0x00007fff; M0 = 0x7123 (X); M1 = 0x7234 (X); M2 = 0x7345 (X); M3 = 0x7456 (X); L0 = 0x7567 (X); L1 = 0x7678 (X); L2 = 0x7789 (X); L3 = 0x789a (X); R0 = M0; R1 = M1; R2 = M2; R3 = M3; R4 = L0; R5 = L1; R6 = L2; R7 = L3; CHECKREG r0, 0x00007123; CHECKREG r1, 0x00007234; CHECKREG r2, 0x00007345; CHECKREG r3, 0x00007456; CHECKREG r4, 0x00007567; CHECKREG r5, 0x00007678; CHECKREG r6, 0x00007789; CHECKREG r7, 0x0000789A; M0 = -32768 (X); M1 = -123 (X); M2 = -234 (X); M3 = -345 (X); L0 = -456 (X); L1 = -567 (X); L2 = -667 (X); L3 = -701 (X); R0 = M0; R1 = M1; R2 = M2; R3 = M3; R4 = L0; R5 = L1; R6 = L2; R7 = L3; CHECKREG r0, 0xFFFF8000; CHECKREG r1, 0xFFFFFF85; CHECKREG r2, 0xFFFFFF16; CHECKREG r3, 0xFFFFFEA7; CHECKREG r4, 0xFFFFFE38; CHECKREG r5, 0xFFFFFDC9; CHECKREG r6, 0xFFFFFD65; CHECKREG r7, 0xFFFFFD43; M0 = 0x7aaa (X); M1 = 0x7bbb (X); M2 = 0x7ccc (X); M3 = 0x7ddd (X); L0 = 0x7eee (X); L1 = 0x7fa8 (X); L2 = 0x7fb9 (X); L3 = 0x7fcc (X); R0 = M0; R1 = M1; R2 = M2; R3 = M3; R4 = L0; R5 = L1; R6 = L2; R7 = L3; CHECKREG r0, 0x00007aaa; CHECKREG r1, 0x00007bbb; CHECKREG r2, 0x00007ccc; CHECKREG r3, 0x00007ddd; CHECKREG r4, 0x00007eee; CHECKREG r5, 0x00007fa8; CHECKREG r6, 0x00007fb9; CHECKREG r7, 0x00007fcc; pass
tactcomplabs/xbgas-binutils-gdb	6,235	sim/testsuite/bfin/se_bug_ui2.S	//Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp // Description: 16 bit special cases Undefined Instructions in Supervisor Mode # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // // Constants and Defines // include(gen_int.inc) include(selfcheck.inc) include(std.inc) include(mmrs.inc) include(symtable.inc) #ifndef STACKSIZE #define STACKSIZE 0x10 // change for how much stack you need #endif #ifndef ITABLE #define ITABLE 0xF0000000 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // etc.) // BOOT: INIT_R_REGS(0); // initialize general purpose regs INIT_P_REGS(0); // initialize the pointers INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); CLI R1; // inhibit events during MMR writes LD32_LABEL(sp, USTACK); // setup the user stack pointer USP = SP; LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer FP = SP; // and frame pointer LD32(p0, EVT0); // Setup Event Vectors and Handlers P0 += 4; // EVT0 not used (Emulation) P0 += 4; // EVT1 not used (Reset) LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; P0 += 4; // EVT4 not used (Global Interrupt Enable) LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R1 = -1; // Change this to mask interrupts () CSYNC; // wait for MMR writes to finish STI R1; // sync and reenable events (implicit write to IMASK) DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs SYSCFG = r0; RETS = r0; // prevent X's breaking LINK instruction // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); CLI R1; // inhibit events during write to MMR [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; // wait for it STI R1; // reenable events with proper imask RAISE 15; // after we RTI, INT 15 should be taken RTI; // // The Main Program // STARTUSER: LINK 0; // change for how much stack frame space you need. JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // count of UI's will be in r5, which was initialized to 0 by header // .dw 0x41FD ; // .dw 0x41FE ; // .dw 0x41FF ; .dw 0x9040 ; .dw 0x9049 ; .dw 0x9052 ; .dw 0x905B ; .dw 0x9064 ; .dw 0x906D ; .dw 0x9076 ; .dw 0x907F ; .dw 0x90C0 ; .dw 0x90C9 ; .dw 0x90D2 ; .dw 0x90DB ; .dw 0x90E4 ; .dw 0x90ED ; .dw 0x90F6 ; .dw 0x90FF ; .dw 0x9180 ; CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); // Xhandler counts all EXCAUSE = 0x21; CHECKREG(r5, 17); // count of all 16 bit UI's. END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // NHANDLE: // NMI Handler 2 RTN; XHANDLE: // Exception Handler 3 // 16 bit illegal opcode handler - skips bad instruction // handler MADE LEAN and destructive so test runs more quckly // se_undefinedinstruction1.dsp tests using a "nice" handler // [--sp] = ASTAT; // save what we damage // [--sp] = (r7 - r6); R7 = SEQSTAT; R7 <<= 26; R7 >>= 26; // only want EXCAUSE R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction CC = r7 == r6; IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave R6 = 0x22; // Also accept illegal insn combo CC = r7 == r6; IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave dbg_fail; UNDEFINEDINSTRUCTION: R7 = RETX; // Fix up return address R7 += 2; // skip offending 16 bit instruction RETX = r7; // and put back in RETX R5 += 1; // Increment global counter OUT: // (r7 - r6) = [sp++]; // ASTAT = [sp++]; RTX; HWHANDLE: // HW Error Handler 5 RTI; THANDLE: // Timer Handler 6 RTI; I7HANDLE: // IVG 7 Handler RTI; I8HANDLE: // IVG 8 Handler RTI; I9HANDLE: // IVG 9 Handler RTI; I10HANDLE: // IVG 10 Handler RTI; I11HANDLE: // IVG 11 Handler RTI; I12HANDLE: // IVG 12 Handler RTI; I13HANDLE: // IVG 13 Handler RTI; I14HANDLE: // IVG 14 Handler RTI; I15HANDLE: // IVG 15 Handler RTI; // padding for the icache EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; // // Data Segment // .data DATA: .space (0x10); // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	3,885	sim/testsuite/bfin/c_alu2op_conv_toggle.s	//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp // Spec Reference: alu2op (~) toggle # mach: bfin .include "testutils.inc" start imm32 r0, 0x00789abc; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x856789ab; imm32 r5, 0x96789abc; imm32 r6, 0xa789abcd; imm32 r7, 0xb89abcde; R0 = ~ R0; R1 = ~ R0; R2 = ~ R0; R3 = ~ R0; R4 = ~ R0; R5 = ~ R0; R6 = ~ R0; R7 = ~ R0; CHECKREG r0, 0xFF876543; CHECKREG r1, 0x00789ABC; CHECKREG r2, 0x00789ABC; CHECKREG r3, 0x00789ABC; CHECKREG r4, 0x00789ABC; CHECKREG r5, 0x00789ABC; CHECKREG r6, 0x00789ABC; CHECKREG r7, 0x00789ABC; imm32 r0, 0x01230002; imm32 r1, 0x00374659; imm32 r2, 0x93456789; imm32 r3, 0xa456789a; imm32 r4, 0xb56789ab; imm32 r5, 0xc6789abc; imm32 r6, 0xd789abcd; imm32 r7, 0xe89abcde; R0 = ~ R1; R1 = ~ R1; R2 = ~ R1; R3 = ~ R1; R4 = ~ R1; R5 = ~ R1; R6 = ~ R1; R7 = ~ R1; CHECKREG r0, 0xFFC8B9A6; CHECKREG r1, 0xFFC8B9A6; CHECKREG r2, 0x00374659; CHECKREG r3, 0x00374659; CHECKREG r4, 0x00374659; CHECKREG r5, 0x00374659; CHECKREG r6, 0x00374659; CHECKREG r7, 0x00374659; imm32 r0, 0x10789abc; imm32 r1, 0x11345678; imm32 r2, 0x93156789; imm32 r3, 0xd451789a; imm32 r4, 0x856719ab; imm32 r5, 0x267891bc; imm32 r6, 0xa789ab1d; imm32 r7, 0x989ab1de; R0 = ~ R2; R1 = ~ R2; R2 = ~ R2; R3 = ~ R2; R4 = ~ R2; R5 = ~ R2; R6 = ~ R2; R7 = ~ R2; CHECKREG r0, 0x6CEA9876; CHECKREG r1, 0x6CEA9876; CHECKREG r2, 0x6CEA9876; CHECKREG r3, 0x93156789; CHECKREG r4, 0x93156789; CHECKREG r5, 0x93156789; CHECKREG r6, 0x93156789; CHECKREG r7, 0x93156789; imm32 r0, 0x21230002; imm32 r1, 0x02374659; imm32 r2, 0x93256789; imm32 r3, 0xa952789a; imm32 r4, 0xb59729ab; imm32 r5, 0xc67992bc; imm32 r6, 0xd7899b2d; imm32 r7, 0xe89ab9d2; R0 = ~ R3; R1 = ~ R3; R2 = ~ R3; R3 = ~ R3; R4 = ~ R3; R5 = ~ R3; R6 = ~ R3; R7 = ~ R3; CHECKREG r0, 0x56AD8765; CHECKREG r1, 0x56AD8765; CHECKREG r2, 0x56AD8765; CHECKREG r3, 0x56AD8765; CHECKREG r4, 0xA952789A; CHECKREG r5, 0xA952789A; CHECKREG r6, 0xA952789A; CHECKREG r7, 0xA952789A; imm32 r0, 0xa0789abc; imm32 r1, 0x1a345678; imm32 r2, 0x23a56789; imm32 r3, 0x645a789a; imm32 r4, 0x8667a9ab; imm32 r5, 0x96689abc; imm32 r6, 0xa787abad; imm32 r7, 0xb89a7cda; R0 = ~ R4; R1 = ~ R4; R2 = ~ R4; R3 = ~ R4; R4 = ~ R4; R5 = ~ R4; R6 = ~ R4; R7 = ~ R4; CHECKREG r0, 0x79985654; CHECKREG r1, 0x79985654; CHECKREG r2, 0x79985654; CHECKREG r3, 0x79985654; CHECKREG r4, 0x79985654; CHECKREG r5, 0x8667A9AB; CHECKREG r6, 0x8667A9AB; CHECKREG r7, 0x8667A9AB; imm32 r0, 0xf1230002; imm32 r1, 0x0f374659; imm32 r2, 0x93f56789; imm32 r3, 0xa45f789a; imm32 r4, 0xb567f9ab; imm32 r5, 0xc6789fbc; imm32 r6, 0xd789abfd; imm32 r7, 0xe89abcdf; R0 = ~ R5; R1 = ~ R5; R2 = ~ R5; R3 = ~ R5; R4 = ~ R5; R5 = ~ R5; R6 = ~ R5; R7 = ~ R5; CHECKREG r0, 0x39876043; CHECKREG r1, 0x39876043; CHECKREG r2, 0x39876043; CHECKREG r3, 0x39876043; CHECKREG r4, 0x39876043; CHECKREG r5, 0x39876043; CHECKREG r6, 0xC6789FBC; CHECKREG r7, 0xC6789FBC; imm32 r0, 0xe0789abc; imm32 r1, 0xe2345678; imm32 r2, 0x2e456789; imm32 r3, 0x34e6789a; imm32 r4, 0x856e89ab; imm32 r5, 0x9678eabc; imm32 r6, 0xa789aecd; imm32 r7, 0xb89abcee; R0 = ~ R6; R1 = ~ R6; R2 = ~ R6; R3 = ~ R6; R4 = ~ R6; R5 = ~ R6; R6 = ~ R6; R7 = ~ R6; CHECKREG r0, 0x58765132; CHECKREG r1, 0x58765132; CHECKREG r2, 0x58765132; CHECKREG r3, 0x58765132; CHECKREG r4, 0x58765132; CHECKREG r5, 0x58765132; CHECKREG r6, 0x58765132; CHECKREG r7, 0xA789AECD; imm32 r0, 0x012300f5; imm32 r1, 0x80374659; imm32 r2, 0x98456589; imm32 r3, 0xa486589a; imm32 r4, 0xb56589ab; imm32 r5, 0xc6588abc; imm32 r6, 0xd589a8cd; imm32 r7, 0x589abc88; R0 = ~ R7; R1 = ~ R7; R2 = ~ R7; R3 = ~ R7; R4 = ~ R7; R5 = ~ R7; R7 = ~ R7; R6 = ~ R7; CHECKREG r0, 0xA7654377; CHECKREG r1, 0xA7654377; CHECKREG r2, 0xA7654377; CHECKREG r3, 0xA7654377; CHECKREG r4, 0xA7654377; CHECKREG r5, 0xA7654377; CHECKREG r6, 0x589ABC88; CHECKREG r7, 0xA7654377; pass
tactcomplabs/xbgas-binutils-gdb	5,142	sim/testsuite/bfin/c_dsp32mac_dr_a1.s	//Original:/testcases/core/c_dsp32mac_dr_a1/c_dsp32mac_dr_a1.dsp // Spec Reference: dsp32mac dr_a1 # mach: bfin .include "testutils.inc" start A1 = A0 = 0; // The result accumulated in A1 , and stored to a reg half imm32 r0, 0x13545abd; imm32 r1, 0xadbcfec7; imm32 r2, 0xa1245679; imm32 r3, 0x00060007; imm32 r4, 0xefbc4569; imm32 r5, 0x1235000b; imm32 r6, 0x000c000d; imm32 r7, 0x678e000f; R0.H = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L; R1 = A1.w; R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; R3 = A1.w; R4.H = ( A1 = R4.L * R5.L ), A0 += R4.H * R5.H; R5 = A1.w; R6.H = ( A1 += R6.L * R7.L ), A0 += R6.L * R7.H; R7 = A1.w; CHECKREG r0, 0xFF225ABD; CHECKREG r1, 0xFF221DD6; CHECKREG r2, 0x00055679; CHECKREG r3, 0x0004BA9E; CHECKREG r4, 0x00064569; CHECKREG r5, 0x0005F706; CHECKREG r6, 0x0006000D; CHECKREG r7, 0x0005F88C; imm32 r0, 0x13545abd; imm32 r1, 0xa1bcfec7; imm32 r2, 0xa1145679; imm32 r3, 0x00010007; imm32 r4, 0xefbc1569; imm32 r5, 0x1235010b; imm32 r6, 0x000c001d; imm32 r7, 0x678e0001; R4.H = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L; R5 = A1.w; R0.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L; R1 = A1.w; R2.H = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H; R3 = A1.w; R6.H = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H; R7 = A1.w; CHECKREG r0, 0x00015ABD; CHECKREG r1, 0x0000ACF2; CHECKREG r2, 0xFFF95679; CHECKREG r3, 0xFFF8F98C; CHECKREG r4, 0xFFD71569; CHECKREG r5, 0xFFD6B524; CHECKREG r6, 0x0010001D; CHECKREG r7, 0x00106FB8; imm32 r0, 0x83545abd; imm32 r1, 0xa8bcfec7; imm32 r2, 0xa1845679; imm32 r3, 0x00080007; imm32 r4, 0xefbc8569; imm32 r5, 0x1235080b; imm32 r6, 0x000c008d; imm32 r7, 0x678e0008; R6.H = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L; R7 = A1.w; R2.H = ( A1 = R2.H * R3.L ), A0 = R2.H * R3.L; R3 = A1.w; R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H; R5 = A1.w; R0.H = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H; R1 = A1.w; CHECKREG r0, 0x1B505ABD; CHECKREG r1, 0x1B4FC2A8; CHECKREG r2, 0xFFFB5679; CHECKREG r3, 0xFFFAD538; CHECKREG r4, 0xFEFA8569; CHECKREG r5, 0xFEFA5A28; CHECKREG r6, 0xC234008D; CHECKREG r7, 0xC233C550; imm32 r0, 0xc3545abd; imm32 r1, 0xacbcfec7; imm32 r2, 0xa1c45679; imm32 r3, 0x000c0007; imm32 r4, 0xefbcc569; imm32 r5, 0x12350c0b; imm32 r6, 0x000c00cd; imm32 r7, 0x678e000c; R6.H = ( A1 += R1.H * R0.H ), A0 = R1.L * R0.L; R7 = A1.w; R0.H = ( A1 = R2.H * R3.H ), A0 = R2.H * R3.L; R1 = A1.w; R4.H = ( A1 = R4.H * R5.H ), A0 += R4.H * R5.H; R5 = A1.w; R2.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H; R3 = A1.w; CHECKREG r0, 0xFFF75ABD; CHECKREG r1, 0xFFF72A60; CHECKREG r2, 0x20875679; CHECKREG r3, 0x2086A6C8; CHECKREG r4, 0xFDB0C569; CHECKREG r5, 0xFDAFB3D8; CHECKREG r6, 0x42C800CD; CHECKREG r7, 0x42C78608; imm32 r0, 0x01542abd; imm32 r1, 0x02bc4ec7; imm32 r2, 0x03240679; imm32 r3, 0x04061007; imm32 r4, 0x05bc2569; imm32 r5, 0x0635300b; imm32 r6, 0x070c200d; imm32 r7, 0x088e100f; R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L; R1 = A1.w; R2.H = ( A1 -= R2.L * R3.L ), A0 -= R2.H * R3.L; R3 = A1.w; R4.H = ( A1 -= R4.L * R5.L ), A0 += R4.H * R5.H; R5 = A1.w; R6.H = ( A1 += R6.L * R7.L ), A0 -= R6.L * R7.H; R7 = A1.w; CHECKREG r0, 0x06392ABD; CHECKREG r1, 0x063908F2; CHECKREG r2, 0x056A0679; CHECKREG r3, 0x05698E54; CHECKREG r4, 0xF75F2569; CHECKREG r5, 0xF75EF74E; CHECKREG r6, 0xFB64200D; CHECKREG r7, 0xFB6458D4; imm32 r0, 0x03545abd; imm32 r1, 0x31bcfec7; imm32 r2, 0x11145679; imm32 r3, 0x00010007; imm32 r4, 0xefbc1569; imm32 r5, 0x1235010b; imm32 r6, 0x000c001d; imm32 r7, 0x678e0001; R4.H = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L; R5 = A1.w; R0.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L; R1 = A1.w; R2.H = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H; R3 = A1.w; R6.H = ( A1 += R6.L * R7.H ), A0 -= R6.L * R7.H; R7 = A1.w; CHECKREG r0, 0xFB5C5ABD; CHECKREG r1, 0xFB5B887A; CHECKREG r2, 0xFC225679; CHECKREG r3, 0xFC223F02; CHECKREG r4, 0xFB5C1569; CHECKREG r5, 0xFB5C356C; CHECKREG r6, 0xFC3A001D; CHECKREG r7, 0xFC39B52E; imm32 r0, 0x83545abd; imm32 r1, 0xa8bcfec7; imm32 r2, 0xa1845679; imm32 r3, 0x00080007; imm32 r4, 0xefbc8569; imm32 r5, 0x1235080b; imm32 r6, 0x000c008d; imm32 r7, 0x678e0008; R6.H = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L; R7 = A1.w; R2.H = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L; R3 = A1.w; R4.H = ( A1 = R4.H * R5.L ), A0 -= R4.H * R5.H; R5 = A1.w; R0.H = ( A1 += R6.H * R7.L ), A0 -= R6.L * R7.H; R1 = A1.w; CHECKREG r0, 0xF9745ABD; CHECKREG r1, 0xF9741604; CHECKREG r2, 0xBE625679; CHECKREG r3, 0xBE62358E; CHECKREG r4, 0xFEFA8569; CHECKREG r5, 0xFEFA5A28; CHECKREG r6, 0xBE5D008D; CHECKREG r7, 0xBE5D0AC6; imm32 r0, 0xc3545abd; imm32 r1, 0xacbcfec7; imm32 r2, 0xa1c45679; imm32 r3, 0x000c0007; imm32 r4, 0xefbcc569; imm32 r5, 0x12350c0b; imm32 r6, 0x000c00cd; imm32 r7, 0x678e000c; R6.H = ( A1 += R1.H * R0.H ), A0 -= R1.L * R0.L; R7 = A1.w; R0.H = ( A1 = R2.H * R3.H ), A0 -= R2.H * R3.L; R1 = A1.w; R4.H = ( A1 -= R4.H * R5.H ), A0 += R4.H * R5.H; R5 = A1.w; R2.H = ( A1 -= R6.H * R7.H ), A0 += R6.L * R7.H; R3 = A1.w; CHECKREG r0, 0xFFF75ABD; CHECKREG r1, 0xFFF72A60; CHECKREG r2, 0xF9D05679; CHECKREG r3, 0xF9D00540; CHECKREG r4, 0x0247C569; CHECKREG r5, 0x02477688; CHECKREG r6, 0x20EC00CD; CHECKREG r7, 0x20EBD964; pass
tactcomplabs/xbgas-binutils-gdb	4,864	sim/testsuite/bfin/c_interr_timer_tcount.S	//Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp // Spec Reference: interrupt on HW TIMER tcount # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // // Include Files // include(std.inc) include(selfcheck.inc) // Defines #ifndef TCNTL #define TCNTL 0xFFE03000 #endif #ifndef TPERIOD #define TPERIOD 0xFFE03004 #endif #ifndef TSCALE #define TSCALE 0xFFE03008 #endif #ifndef TCOUNT #define TCOUNT 0xFFE0300c #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203c #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE 0x000FF000 #endif #ifndef PROGRAM_STACK #define PROGRAM_STACK 0x000FF100 #endif #ifndef STACKSIZE #define STACKSIZE 0x00000300 #endif // Boot code BOOT : INIT_R_REGS(0); // Initialize Dregs INIT_P_REGS(0); // Initialize Pregs // CHECK_INIT(p5, 0x00BFFFFC); // CHECK_INIT(p5, 0xE0000000); include(symtable.inc) CHECK_INIT_DEF(p5); LD32(sp, 0x000FF200); LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE); // IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK LD32_LABEL(p1, START); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; RAISE 15; // after we RTI, INT 15 should be taken LD32_LABEL(r7, START); RETI = r7; NOP; // Workaround for Bug 217 RTI; NOP; NOP; //.code 0x200 START : R7 = 0x0; R6 = 0x1; [ -- SP ] = RETI; // Enable Nested Interrupts WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) WR_MMR(TPERIOD, 0x00000010, p0, r0); WR_MMR(TCOUNT, 0x00000002, p0, r0); WR_MMR(TSCALE, 0x00000001, p0, r0); WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) CSYNC; RD_MMR(TCNTL, p0, r5); CHECKREG(r5, 0x0000000B); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; CHECKREG(r7, 0x00000001); R7 = 0; NOP; WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power WR_MMR(TPERIOD, 0x00000010, p0, r0); WR_MMR(TCOUNT, 0x00000002, p0, r0); WR_MMR(TSCALE, 0x00000003, p0, r0); WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer CSYNC; NOP; NOP; // Read the contents of the Timer RD_MMR(TCNTL , p0, r3); CHECKREG(r3, 0x0000000B); CHECKREG(r7, 0x00000001); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; NOP; NOP; NOP; dbg_pass; // Call Endtest Macro //******************************************************************** // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 RTN; XHANDLE: // Exception Handler 3 RTX; HWHANDLE: // HW Error Handler 5 RTI; THANDLE: // Timer Handler 6 R7 = R7 + R6; RTI; I7HANDLE: // IVG 7 Handler RTI; I8HANDLE: // IVG 8 Handler RTI; I9HANDLE: // IVG 9 Handler RTI; I10HANDLE: // IVG 10 Handler RTI; I11HANDLE: // IVG 11 Handler RTI; I12HANDLE: // IVG 12 Handler RTI; I13HANDLE: // IVG 13 Handler RTI; I14HANDLE: // IVG 14 Handler RTI; I15HANDLE: // IVG 15 Handler R5 = RETI; P0 = R5; JUMP ( P0 ); RTI; .section MEM_DATA_ADDR_1,"aw" .space (STACKSIZE); STACK: NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
tactcomplabs/xbgas-binutils-gdb	6,107	sim/testsuite/bfin/c_mmr_ppopm_illegal_adr.S	//Original:/proj/frio/dv/testcases/core/c_mmr_ppopm_illegal_adr/c_mmr_ppopm_illegal_adr.dsp // Spec Reference: mmr ppopm illegal address # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(gen_int.inc) include(selfcheck.inc) include(std.inc) include(mmrs.inc) #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef ITABLE #define ITABLE 0xF0000000 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we set the processor operating modes, initialize registers // etc.) // BOOT: INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); CLI R1; // inhibit events during MMR writes LD32_LABEL(sp, USTACK); // setup the user stack pointer USP = SP; // and frame pointer LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT0); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4) LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R1 = -1; // Change this to mask interrupts () CSYNC; // wait for MMR writes to finish STI R1; // sync and reenable events (implicit write to IMASK) DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs SYSCFG = r0; RETS = r0; // prevent X's breaking LINK instruction // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); CLI R1; // inhibit events during write to MMR [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; // wait for it STI R1; // reenable events with proper imask RAISE 15; // after we RTI, INT 15 should be taken RTI; // // The Main Program // STARTUSER: LINK 0; // change for how much stack frame space you need. JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE LD32(r0, 0206037020); LD32(r1, 0x10070030); LD32(r2, 0xe2000043); LD32(r3, 0x30305050); LD32(r4, 0x0f040860); LD32(r5, 0x0a0050d0); LD32(r6, 0x00000000); LD32(r7, 0x0f060071); [ -- SP ] = ( R7:7 ); LD32(r7, 0x123456af); [ -- SP ] = ( R7:6 ); // [--sp] = r7; // [--sp] = r6; .dd 0xffff R1 += 2; CHECKREG(r1, 0x10070034); CHECKREG(r2, 0xE2000046); CHECKREG(r3, 0x30305054); CHECKREG(r4, 0x0f040865); CHECKREG(r5, 0x0a0050d6); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x123456b7); R7 = [ SP ++ ]; CHECKREG(r7, 0x123456af); dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 R0 = 2; RTN; XHANDLE: // Exception Handler 3 R0 = RETX; // error handler:RETX has the address of the same Illegal instr R1 += 2; R2 += 3; R3 += 4; R4 += 5; R5 += 6; R6 += 7; R7 += 8; R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr) RETX = R0; NOP; NOP; NOP; NOP; RTX; HWHANDLE: // HW Error Handler 5 R2 = 5; RTI; THANDLE: // Timer Handler 6 R3 = 6; RTI; I7HANDLE: // IVG 7 Handler R4 = 7; RTI; I8HANDLE: // IVG 8 Handler R5 = 8; RTI; I9HANDLE: // IVG 9 Handler R6 = 9; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .section MEM_DATA_ADDR_1,"aw" DATA0: .dd 0x000a0000 .dd 0x000b0001 .dd 0x000c0002 .dd 0x000d0003 .dd 0x000e0004 .dd 0x000f0005 .dd 0x00100006 .dd 0x00200007 .dd 0x00300008 .dd 0x00400009 .dd 0x0050000a .dd 0x0060000b .dd 0x0070000c .dd 0x0080000d .dd 0x0090000e .dd 0x0100000f .dd 0x02000010 .dd 0x03000011 .dd 0x04000012 .dd 0x05000013 .dd 0x06000014 .dd 0x001a0000 .dd 0x001b0001 .dd 0x001c0002 // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	4,358	sim/testsuite/bfin/c_dsp32mult_pair.s	//Original:/testcases/core/c_dsp32mult_pair/c_dsp32mult_pair.dsp // Spec Reference: dsp32mult pair # mach: bfin .include "testutils.inc" start imm32 r0, 0x8b235625; imm32 r1, 0x93ba5127; imm32 r2, 0xa3446725; imm32 r3, 0x00050027; imm32 r4, 0xb0ab6d29; imm32 r5, 0x10ace72b; imm32 r6, 0xc00c008d; imm32 r7, 0xd2467029; R1 = R0.L * R0.L, R0 = R0.L * R0.L; R3 = R0.L * R1.L, R2 = R0.L * R1.H; R5 = R1.L * R0.L, R4 = R1.H * R0.L; R7 = R1.L * R1.L, R6 = R1.H * R1.H; CHECKREG r0, 0x39F9C2B2; CHECKREG r1, 0x39F9C2B2; CHECKREG r2, 0xE43C0244; CHECKREG r3, 0x1D5C8788; CHECKREG r4, 0xE43C0244; CHECKREG r5, 0x1D5C8788; CHECKREG r6, 0x1A41A862; CHECKREG r7, 0x1D5C8788; imm32 r0, 0x5b33a635; imm32 r1, 0x6fbe5137; imm32 r2, 0x1324b735; imm32 r3, 0x9006d037; imm32 r4, 0x80abcb39; imm32 r5, 0xb0acef3b; imm32 r6, 0xa00c00dd; imm32 r7, 0x12469003; R1 = R2.L * R2.L, R0 = R2.L * R2.L; R3 = R2.L * R3.L, R2 = R2.L * R3.H; R5 = R3.L * R2.L, R4 = R3.H * R2.L; R7 = R3.L * R3.L, R6 = R3.H * R3.H; CHECKREG r0, 0x2965A1F2; CHECKREG r1, 0x2965A1F2; CHECKREG r2, 0x3FAE367C; CHECKREG r3, 0x1B2CD8C6; CHECKREG r4, 0x0B90E2A0; CHECKREG r5, 0xEF4D87D0; CHECKREG r6, 0x05C49F20; CHECKREG r7, 0x0C057248; imm32 r0, 0x1b235655; imm32 r1, 0xc4ba5157; imm32 r2, 0x63246755; imm32 r3, 0x00060055; imm32 r4, 0x90abc509; imm32 r5, 0x10acef5b; imm32 r6, 0xb00c005d; imm32 r7, 0x1246705f; R1 = R4.L * R4.L, R0 = R4.L * R4.L; R3 = R4.L * R5.L, R2 = R4.L * R5.H; R5 = R5.L * R4.L, R4 = R5.H * R4.L; R7 = R5.L * R5.L, R6 = R5.H * R5.H; CHECKREG r0, 0x1B29B4A2; CHECKREG r1, 0x1B29B4A2; CHECKREG r2, 0xF851E418; CHECKREG r3, 0x07AAE266; CHECKREG r4, 0xF851E418; CHECKREG r5, 0x07AAE266; CHECKREG r6, 0x007579C8; CHECKREG r7, 0x06D88148; imm32 r0, 0xab235666; imm32 r1, 0xeaba5166; imm32 r2, 0x13d48766; imm32 r3, 0xf00b0066; imm32 r4, 0x90ab9d69; imm32 r5, 0x10ac5f6b; imm32 r6, 0x800cb66d; imm32 r7, 0x1246707f; R1 = R6.L * R6.L, R0 = R6.L * R6.L; R3 = R6.L * R7.L, R2 = R6.L * R7.H; R5 = R7.L * R6.L, R4 = R7.H * R6.L; R7 = R7.L * R7.L, R6 = R7.H * R7.H; CHECKREG r0, 0x2A4A54D2; CHECKREG r1, 0x2A4A54D2; CHECKREG r2, 0xF57F179C; CHECKREG r3, 0xBF566026; CHECKREG r4, 0xF57F179C; CHECKREG r5, 0xBF566026; CHECKREG r6, 0x029BD648; CHECKREG r7, 0x62DEBE02; // mix order imm32 r0, 0xab23a675; imm32 r1, 0xcfba5127; imm32 r2, 0x13246705; imm32 r3, 0x00060007; imm32 r4, 0x90abcd09; imm32 r5, 0x10acdfdb; imm32 r6, 0x000c000d; imm32 r7, 0x1246f00f; R1 = R3.L * R2.L (M), R0 = R3.L * R2.H; R3 = R1.L * R0.H, R2 = R1.H * R0.L; R5 = R7.H * R4.L, R4 = R7.H * R4.L; R7 = R5.L * R6.L (M), R6 = R5.H * R6.L; CHECKREG r0, 0x00010BF8; CHECKREG r1, 0x0002D123; CHECKREG r2, 0x00002FE0; CHECKREG r3, 0xFFFFA246; CHECKREG r4, 0xF8B964EC; CHECKREG r5, 0xF8B964EC; CHECKREG r6, 0xFFFF42CA; CHECKREG r7, 0x00051FFC; imm32 r0, 0x9b235a75; imm32 r1, 0xc9ba5127; imm32 r2, 0x13946905; imm32 r3, 0x00090007; imm32 r4, 0x90ab9d09; imm32 r5, 0x10ace9db; imm32 r6, 0x000c0d9d; imm32 r7, 0x12467009; R3 = R6.L * R5.L, R2 = R6.L * R5.H; R1 = R3.L * R0.H (M), R0 = R3.H * R0.L; R5 = R1.L * R4.L (M), R4 = R1.H * R4.L; R7 = R2.H * R7.L, R6 = R2.H * R7.L; CHECKREG r0, 0xFE55DCD2; CHECKREG r1, 0x0C7E7B9A; CHECKREG r2, 0x01C5EAF8; CHECKREG r3, 0xFDA5149E; CHECKREG r4, 0xF6576CDC; CHECKREG r5, 0x4BD1CA6A; CHECKREG r6, 0x018C7FDA; CHECKREG r7, 0x018C7FDA; imm32 r0, 0x8b235675; imm32 r1, 0xc8ba5127; imm32 r2, 0x13846705; imm32 r3, 0x00080007; imm32 r4, 0x90ab8d09; imm32 r5, 0x10ace8db; imm32 r6, 0x000c008d; imm32 r7, 0x12467008; R3 = R6.H * R5.L, R2 = R6.L * R5.H; R7 = R2.L * R0.H (M), R6 = R2.H * R0.L; R5 = R1.L * R3.L (M), R4 = R1.H * R3.L; R1 = R2.H * R7.L, R0 = R2.L * R7.H; CHECKREG r0, 0x2517D740; CHECKREG r1, 0xFFFDAAA0; CHECKREG r2, 0x00125D78; CHECKREG r3, 0xFFFDD488; CHECKREG r4, 0x12C555A0; CHECKREG r5, 0x435F68B8; CHECKREG r6, 0x000C2874; CHECKREG r7, 0x32CCEF68; imm32 r0, 0xeb235675; imm32 r1, 0xceba5127; imm32 r2, 0x13e46705; imm32 r3, 0x000e0007; imm32 r4, 0x90abed09; imm32 r5, 0x10aceedb; imm32 r6, 0x000c00ed; imm32 r7, 0x1246700e; R1 = R1.H * R4.L, R0 = R1.H * R4.L; R3 = R2.L * R5.L, R2 = R2.L * R5.H; R5 = R3.H * R6.L, R4 = R3.L * R6.L; R7 = R4.L * R0.H, R6 = R4.H * R0.L; CHECKREG r0, 0x074CED14; CHECKREG r1, 0x074CED14; CHECKREG r2, 0x0D6B0EB8; CHECKREG r3, 0xF2338E8E; CHECKREG r4, 0xFF2DF2EC; CHECKREG r5, 0xFFE6726E; CHECKREG r6, 0x001F3108; CHECKREG r7, 0xFF412420; pass
tactcomplabs/xbgas-binutils-gdb	8,487	sim/testsuite/bfin/c_seq_ex3_ls_mmr_mvp.S	//Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_mmr_mvp/c_seq_ex3_ls_mmr_mvp.dsp // Spec Reference: sequencer stage ex3 (ldst + mmr regmv + pushpopmultiple) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE DATA_ADDR_1 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK CSYNC; DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE R0 = 0; ASTAT = R0; // PUT YOUR TEST HERE! // PUSH LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 //LD32(p2, DATA_ADDR_1); loadsym p2, DATA; LD32(p3, 0xab5fd490); LD32(p4, 0xa581bd94); LD32(r2, 0x14789232); [ P1 ] = R2; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; [ -- SP ] = ( R7:0 ); // RAISE 2; // RTN R0 = [ P2 ++ ]; R1 = [ P1 ]; // brf LABEL1 (bp); P3 = R7; R4 = P3; [ -- SP ] = ( R7:0 ); R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; LABEL1: // RAISE 5; // RTI R2 = [ P2 ++ ]; R3 = [ P1 ]; // brt LABEL2 (bp); // not taken P4 = R6; R4 = P4; [ -- SP ] = ( R7:0 ); R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; // wrt-rd EVT5 = 0xFFE02034 LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 // RAISE 6; // RTI R4 = [ P2 ++ ]; R5 = [ P1 ]; // brf LABEL2 (bp) ; P3 = R3; R6 = P3; [ -- SP ] = ( R7:0 ); // POP // r0 = 0x00; // r1 = 0x00; // r2 = 0x00; // r3 = 0x00; // r4 = 0x00; // r5 = 0x00; // r6 = 0x00; // r7 = 0x00; LABEL2: CSYNC; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x00000012); CHECKREG(r2, 0x00000023); CHECKREG(r3, 0x00000024); CHECKREG(r4, 0x00000016); CHECKREG(r5, 0x14789232); // RAISE 7; // RTI R0 = [ P2 ++ ]; R1 = [ P1 ]; P4 = R4; R2 = P4; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x00000012); CHECKREG(r2, 0x00000023); CHECKREG(r3, 0x00000024); CHECKREG(r4, 0x00000016); CHECKREG(r5, 0x14789232); CHECKREG(r6, 0x00000024); CHECKREG(r7, 0x00000028); // wrt-rd EVT13 = 0xFFE02034 LD32(p1, 0xFFE02034); // RAISE 8; // RTI R0 = [ P2 ++ ]; R1 = [ P1 ]; // brf LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00010203); // CHECKREG can not be skipped CHECKREG(r1, 0x00000012); // so they cannot appear here CHECKREG(r2, 0x04050607); CHECKREG(r3, 0x14789232); CHECKREG(r4, 0x00000017); CHECKREG(r5, 0x00000016); CHECKREG(r6, 0x00000017); CHECKREG(r7, 0x00000018); R0 = 12; R1 = 13; R2 = 14; R3 = 15; R4 = 16; R5 = 17; R6 = 18; R7 = 19; LABEL3: CSYNC; CHECKREG(r0, 0x0000000C); CHECKREG(r1, 0x0000000D); // RAISE 9; // RTI P3 = R6; R7 = P3; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x00000003); CHECKREG(r3, 0x00000004); CHECKREG(r4, 0x00000008); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG(r0, 0x00000000); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x00000000); CHECKREG(r3, 0x00000000); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 I0 += 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 I1 += 2; RTI; THANDLE: // Timer Handler 6 I2 += 2; RTI; I7HANDLE: // IVG 7 Handler I3 += 2; RTI; I8HANDLE: // IVG 8 Handler I0 += 2; RTI; I9HANDLE: // IVG 9 Handler I0 += 2; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .section MEM_DATA_ADDR_1,"aw" DATA: // .space (0x10); .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK: .section MEM_DATA_ADDR_2,"aw" .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0
tactcomplabs/xbgas-binutils-gdb	1,232	sim/testsuite/bfin/stk6.s	// setup a dummy stack and put values in memory 0,1,2,3...n // then restore registers with pop instruction. # mach: bfin .include "testutils.inc" start SP += -12; P1 = SP; R1 = 0; P5.L = 0xdead; SP += -((8+5)*4); // lets move the stack pointer and include the current location. i.e. 5 P4 = (8+6); // 8 data registers and 6 pointer registers are being stored. LSETUP ( ls0 , le0 ) LC0 = P4; ls0: R1 += 1; le0: [ P1-- ] = R1; ( R7:0, P5:0 ) = [ SP ++ ]; DBGA ( R0.L , 1 ); DBGA ( R1.L , 2 ); DBGA ( R2.L , 3 ); DBGA ( R3.L , 4 ); DBGA ( R4.L , 5 ); DBGA ( R5.L , 6 ); DBGA ( R6.L , 7 ); DBGA ( R7.L , 8 ); R0 = P0; DBGA ( R0.L , 9 ); R0 = P1; DBGA ( R0.L , 10 ); R0 = P2; DBGA ( R0.L , 11 ); R0 = P3; DBGA ( R0.L , 12 ); R0 = P4; DBGA ( R0.L , 13 ); R0 = P5; DBGA ( R0.L , 14 ); R0 = 1; [ -- SP ] = ( R7:0, P5:0 ); ( R7:0, P5:0 ) = [ SP ++ ]; DBGA ( R0.L , 1 ); DBGA ( R1.L , 2 ); DBGA ( R2.L , 3 ); DBGA ( R3.L , 4 ); DBGA ( R4.L , 5 ); DBGA ( R5.L , 6 ); DBGA ( R6.L , 7 ); DBGA ( R7.L , 8 ); R0 = P0; DBGA ( R0.L , 9 ); R0 = P1; DBGA ( R0.L , 10 ); R0 = P2; DBGA ( R0.L , 11 ); R0 = P3; DBGA ( R0.L , 12 ); R0 = P4; DBGA ( R0.L , 13 ); R0 = P5; DBGA ( R0.L , 14 ); R0 = 1; pass
tactcomplabs/xbgas-binutils-gdb	3,770	sim/testsuite/bfin/c_regmv_dr_dr.s	//Original:/testcases/core/c_regmv_dr_dr/c_regmv_dr_dr.dsp // Spec Reference: regmv dreg-to-dreg # mach: bfin .include "testutils.inc" start // check R-reg to R-reg move imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R0; R1 = R0; R2 = R0; R3 = R0; R4 = R0; R5 = R0; R6 = R0; R7 = R0; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000001; CHECKREG r2, 0x00000001; CHECKREG r3, 0x00000001; CHECKREG r4, 0x00000001; CHECKREG r5, 0x00000001; CHECKREG r6, 0x00000001; CHECKREG r7, 0x00000001; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R1; R1 = R1; R2 = R1; R3 = R1; R4 = R1; R5 = R1; R6 = R1; R7 = R1; CHECKREG r0, 0x00020003; CHECKREG r1, 0x00020003; CHECKREG r2, 0x00020003; CHECKREG r3, 0x00020003; CHECKREG r4, 0x00020003; CHECKREG r5, 0x00020003; CHECKREG r6, 0x00020003; CHECKREG r7, 0x00020003; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R2; R1 = R2; R2 = R2; R3 = R2; R4 = R2; R5 = R2; R6 = R2; R7 = R2; CHECKREG r0, 0x00040005; CHECKREG r1, 0x00040005; CHECKREG r2, 0x00040005; CHECKREG r3, 0x00040005; CHECKREG r4, 0x00040005; CHECKREG r5, 0x00040005; CHECKREG r6, 0x00040005; CHECKREG r7, 0x00040005; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R3; R1 = R3; R2 = R3; R3 = R3; R4 = R3; R5 = R3; R6 = R3; R7 = R3; CHECKREG r0, 0x00060007; CHECKREG r1, 0x00060007; CHECKREG r2, 0x00060007; CHECKREG r3, 0x00060007; CHECKREG r4, 0x00060007; CHECKREG r5, 0x00060007; CHECKREG r6, 0x00060007; CHECKREG r7, 0x00060007; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R4; R1 = R4; R2 = R4; R3 = R4; R4 = R4; R5 = R4; R6 = R4; R7 = R4; CHECKREG r0, 0x00080009; CHECKREG r1, 0x00080009; CHECKREG r2, 0x00080009; CHECKREG r3, 0x00080009; CHECKREG r4, 0x00080009; CHECKREG r5, 0x00080009; CHECKREG r6, 0x00080009; CHECKREG r7, 0x00080009; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R5; R1 = R5; R2 = R5; R3 = R5; R4 = R5; R5 = R5; R6 = R5; R7 = R5; CHECKREG r0, 0x000a000b; CHECKREG r1, 0x000a000b; CHECKREG r2, 0x000a000b; CHECKREG r3, 0x000a000b; CHECKREG r4, 0x000a000b; CHECKREG r5, 0x000a000b; CHECKREG r6, 0x000a000b; CHECKREG r7, 0x000a000b; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R6; R1 = R6; R2 = R6; R3 = R6; R4 = R6; R5 = R6; R6 = R6; R7 = R6; CHECKREG r0, 0x000c000d; CHECKREG r1, 0x000c000d; CHECKREG r2, 0x000c000d; CHECKREG r3, 0x000c000d; CHECKREG r4, 0x000c000d; CHECKREG r5, 0x000c000d; CHECKREG r6, 0x000c000d; CHECKREG r7, 0x000c000d; imm32 r0, 0x00000001; imm32 r1, 0x00020003; imm32 r2, 0x00040005; imm32 r3, 0x00060007; imm32 r4, 0x00080009; imm32 r5, 0x000a000b; imm32 r6, 0x000c000d; imm32 r7, 0x000e000f; R0 = R7; R1 = R7; R2 = R7; R3 = R7; R4 = R7; R5 = R7; R6 = R7; R7 = R7; CHECKREG r0, 0x000e000f; CHECKREG r1, 0x000e000f; CHECKREG r2, 0x000e000f; CHECKREG r3, 0x000e000f; CHECKREG r4, 0x000e000f; CHECKREG r5, 0x000e000f; CHECKREG r6, 0x000e000f; CHECKREG r7, 0x000e000f; pass
tactcomplabs/xbgas-binutils-gdb	4,591	sim/testsuite/bfin/c_dsp32mult_pair_is.s	//Original:/testcases/core/c_dsp32mult_pair_is/c_dsp32mult_pair_is.dsp // Spec Reference: dsp32mult pair is # mach: bfin .include "testutils.inc" start imm32 r0, 0x8b235625; imm32 r1, 0x93ba5127; imm32 r2, 0xa3446725; imm32 r3, 0x00050027; imm32 r4, 0xb0ab6d29; imm32 r5, 0x10ace72b; imm32 r6, 0xc00c008d; imm32 r7, 0xd2467029; R1 = R0.L * R0.L, R0 = R0.L * R0.L (ISS2); R3 = R0.L * R1.L, R2 = R0.L * R1.H (ISS2); R5 = R1.L * R0.L, R4 = R1.H * R0.L (ISS2); R7 = R1.L * R1.L, R6 = R1.H * R1.H (ISS2); CHECKREG r0, 0x39F9C2B2; CHECKREG r1, 0x39F9C2B2; CHECKREG r2, 0xE43C0244; CHECKREG r3, 0x1D5C8788; CHECKREG r4, 0xE43C0244; CHECKREG r5, 0x1D5C8788; CHECKREG r6, 0x1A41A862; CHECKREG r7, 0x1D5C8788; imm32 r0, 0x5b33a635; imm32 r1, 0x6fbe5137; imm32 r2, 0x1324b735; imm32 r3, 0x9006d037; imm32 r4, 0x80abcb39; imm32 r5, 0xb0acef3b; imm32 r6, 0xa00c00dd; imm32 r7, 0x12469003; R1 = R2.L * R2.L, R0 = R2.L * R2.L (ISS2); R3 = R2.L * R3.L, R2 = R2.L * R3.H (ISS2); R5 = R3.L * R2.L, R4 = R3.H * R2.L (ISS2); R7 = R3.L * R3.L, R6 = R3.H * R3.H (ISS2); CHECKREG r0, 0x2965A1F2; CHECKREG r1, 0x2965A1F2; CHECKREG r2, 0x3FAE367C; CHECKREG r3, 0x1B2CD8C6; CHECKREG r4, 0x0B90E2A0; CHECKREG r5, 0xEF4D87D0; CHECKREG r6, 0x05C49F20; CHECKREG r7, 0x0C057248; imm32 r0, 0x1b235655; imm32 r1, 0xc4ba5157; imm32 r2, 0x63246755; imm32 r3, 0x00060055; imm32 r4, 0x90abc509; imm32 r5, 0x10acef5b; imm32 r6, 0xb00c005d; imm32 r7, 0x1246705f; R1 = R4.L * R4.L, R0 = R4.L * R4.L (ISS2); R3 = R4.L * R5.L, R2 = R4.L * R5.H (ISS2); R5 = R5.L * R4.L, R4 = R5.H * R4.L (ISS2); R7 = R5.L * R5.L, R6 = R5.H * R5.H (ISS2); CHECKREG r0, 0x1B29B4A2; CHECKREG r1, 0x1B29B4A2; CHECKREG r2, 0xF851E418; CHECKREG r3, 0x07AAE266; CHECKREG r4, 0xF851E418; CHECKREG r5, 0x07AAE266; CHECKREG r6, 0x007579C8; CHECKREG r7, 0x06D88148; imm32 r0, 0xab235666; imm32 r1, 0xeaba5166; imm32 r2, 0x13d48766; imm32 r3, 0xf00b0066; imm32 r4, 0x90ab9d69; imm32 r5, 0x10ac5f6b; imm32 r6, 0x800cb66d; imm32 r7, 0x1246707f; R1 = R6.L * R6.L, R0 = R6.L * R6.L (ISS2); R3 = R6.L * R7.L, R2 = R6.L * R7.H (ISS2); R5 = R7.L * R6.L, R4 = R7.H * R6.L (ISS2); R7 = R7.L * R7.L, R6 = R7.H * R7.H (ISS2); CHECKREG r0, 0x2A4A54D2; CHECKREG r1, 0x2A4A54D2; CHECKREG r2, 0xF57F179C; CHECKREG r3, 0xBF566026; CHECKREG r4, 0xF57F179C; CHECKREG r5, 0xBF566026; CHECKREG r6, 0x029BD648; CHECKREG r7, 0x62DEBE02; // mix order imm32 r0, 0xab23a675; imm32 r1, 0xcfba5127; imm32 r2, 0x13246705; imm32 r3, 0x00060007; imm32 r4, 0x90abcd09; imm32 r5, 0x10acdfdb; imm32 r6, 0x000c000d; imm32 r7, 0x1246f00f; R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (ISS2); R3 = R1.L * R0.H, R2 = R1.H * R0.L (ISS2); R5 = R7.H * R4.L, R4 = R7.H * R4.L (ISS2); R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (ISS2); CHECKREG r0, 0x00010BF8; CHECKREG r1, 0x0005A246; CHECKREG r2, 0x000077B0; CHECKREG r3, 0xFFFF448C; CHECKREG r4, 0xF8B964EC; CHECKREG r5, 0xF8B964EC; CHECKREG r6, 0xFFFF42CA; CHECKREG r7, 0x000A3FF8; imm32 r0, 0x9b235a75; imm32 r1, 0xc9ba5127; imm32 r2, 0x13946905; imm32 r3, 0x00090007; imm32 r4, 0x90ab9d09; imm32 r5, 0x10ace9db; imm32 r6, 0x000c0d9d; imm32 r7, 0x12467009; R3 = R6.L * R5.L, R2 = R6.L * R5.H (ISS2); R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (ISS2); R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (ISS2); R7 = R2.H * R7.L, R6 = R2.H * R7.L (ISS2); CHECKREG r0, 0xFE55DCD2; CHECKREG r1, 0x18FCF734; CHECKREG r2, 0x01C5EAF8; CHECKREG r3, 0xFDA5149E; CHECKREG r4, 0xECAED9B8; CHECKREG r5, 0xF53529A8; CHECKREG r6, 0x018C7FDA; CHECKREG r7, 0x018C7FDA; imm32 r0, 0x8b235675; imm32 r1, 0xc8ba5127; imm32 r2, 0x13846705; imm32 r3, 0x00080007; imm32 r4, 0x90ab8d09; imm32 r5, 0x10ace8db; imm32 r6, 0x000c008d; imm32 r7, 0x12467008; R3 = R6.H * R5.L, R2 = R6.L * R5.H (ISS2); R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (ISS2); R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (ISS2); R1 = R2.H * R7.L, R0 = R2.L * R7.H (ISS2); CHECKREG r0, 0x4A306970; CHECKREG r1, 0xFFFB5540; CHECKREG r2, 0x00125D78; CHECKREG r3, 0xFFFDD488; CHECKREG r4, 0x12C555A0; CHECKREG r5, 0x7FFFFFFF; CHECKREG r6, 0x000C2874; CHECKREG r7, 0x6599DED0; imm32 r0, 0xeb235675; imm32 r1, 0xceba5127; imm32 r2, 0x13e46705; imm32 r3, 0x000e0007; imm32 r4, 0x90abed09; imm32 r5, 0x10aceedb; imm32 r6, 0x000c00ed; imm32 r7, 0x1246700e; R1 = R1.H * R4.L, R0 = R1.H * R4.L (ISS2); R3 = R2.L * R5.L, R2 = R2.L * R5.H (ISS2); R5 = R3.H * R6.L, R4 = R3.L * R6.L (ISS2); R7 = R4.L * R0.H, R6 = R4.H * R0.L (ISS2); CHECKREG r0, 0x074CED14; CHECKREG r1, 0x074CED14; CHECKREG r2, 0x0D6B0EB8; CHECKREG r3, 0xF2338E8E; CHECKREG r4, 0xFF2DF2EC; CHECKREG r5, 0xFFE6726E; CHECKREG r6, 0x001F3108; CHECKREG r7, 0xFF412420; pass
tactcomplabs/xbgas-binutils-gdb	6,542	sim/testsuite/bfin/c_interr_timer_tscale.S	//Original:/proj/frio/dv/testcases/core/c_interr_timer_tscale/c_interr_timer_tscale.dsp // Spec Reference: interrupt on HW TIMER tscale # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // // Include Files // include(std.inc) include(selfcheck.inc) // Defines #ifndef TCNTL #define TCNTL 0xFFE03000 #endif #ifndef TPERIOD #define TPERIOD 0xFFE03004 #endif #ifndef TSCALE #define TSCALE 0xFFE03008 #endif #ifndef TCOUNT #define TCOUNT 0xFFE0300c #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203c #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE 0x000FF000 #endif #ifndef PROGRAM_STACK #define PROGRAM_STACK 0x000FF100 #endif #ifndef STACKSIZE #define STACKSIZE 0x00000300 #endif // Boot code BOOT : INIT_R_REGS(0); // Initialize Dregs INIT_P_REGS(0); // Initialize Pregs // CHECK_INIT(p5, 0x00BFFFFC); // CHECK_INIT(p5, 0xE0000000); include(symtable.inc) CHECK_INIT_DEF(p5); LD32(sp, 0x000FF200); LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE); // IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK LD32_LABEL(p1, START); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; RAISE 15; // after we RTI, INT 15 should be taken LD32_LABEL(r7, START); RETI = r7; NOP; // Workaround for Bug 217 RTI; NOP; NOP; //.code 0x200 START : R7 = 0x0; R6 = 0x1; [ -- SP ] = RETI; // Enable Nested Interrupts WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) WR_MMR(TPERIOD, 0x00000010, p0, r0); WR_MMR(TCOUNT, 0x00000002, p0, r0); WR_MMR(TSCALE, 0x00000001, p0, r0); CSYNC; // Read the contents of the Timer RD_MMR(TPERIOD, p0, r2); CHECKREG(r2, 0x00000010); RD_MMR(TCOUNT, p0, r3); CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace -seed 8b8db910 WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) CSYNC; RD_MMR(TCOUNT, p0, r4); CHECKREG(r4, 0x00000000); RD_MMR(TCNTL, p0, r5); CHECKREG(r5, 0x0000000B); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; CHECKREG(r7, 0x00000001); R7 = 0; NOP; WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power WR_MMR(TPERIOD, 0x00000010, p0, r0); WR_MMR(TCOUNT, 0x00000003, p0, r0); WR_MMR(TSCALE, 0x00000128, p0, r0); WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer CSYNC; NOP; NOP; label5: R5.H = 0x7777; R5.L = 0x7888; JUMP.S label6; R5.L = 0x1111; // Will be killed R5.H = 0x1111; // Will be killed NOP; label4: R4.H = 0x5555; R4.L = 0x6666; NOP; JUMP.S label5; R5.L = 0x2222; // Will be killed R5.H = 0x2222; // Will be killed NOP; label6: R3.H = 0x7999; R3.L = 0x7aaa; NOP; // With auto reload // Read the contents of the Timer RD_MMR(TPERIOD, p0, r2); CHECKREG(r2, 0x00000010); RD_MMR(TCNTL , p0, r3); CHECKREG(r3, 0x0000000b); CHECKREG(r7, 0x00000001); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn ON Timer auto-reload WR_MMR(TPERIOD, 0x00000020, p0, r0); WR_MMR(TSCALE, 0x00000003, p0, r0); WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto-reload NOP; NOP; R7 = 0; CSYNC; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; R1 = 1; R2 = 1; R3 = 2; RD_MMR(TCNTL, p0, r5); CHECKREG(r5, 0x0000000F); CC = R1 < R7; IF CC R2 = R3; CHECKREG(r2, 0x00000002); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; NOP; NOP; NOP; dbg_pass; // Call Endtest Macro //******************************************************************** // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 RTN; XHANDLE: // Exception Handler 3 RTX; HWHANDLE: // HW Error Handler 5 RTI; THANDLE: // Timer Handler 6 R7 = R7 + R6; RTI; I7HANDLE: // IVG 7 Handler RTI; I8HANDLE: // IVG 8 Handler RTI; I9HANDLE: // IVG 9 Handler RTI; I10HANDLE: // IVG 10 Handler RTI; I11HANDLE: // IVG 11 Handler RTI; I12HANDLE: // IVG 12 Handler RTI; I13HANDLE: // IVG 13 Handler RTI; I14HANDLE: // IVG 14 Handler RTI; I15HANDLE: // IVG 15 Handler R5 = RETI; P0 = R5; JUMP ( P0 ); RTI; .section MEM_DATA_ADDR_1,"aw" .space (STACKSIZE); STACK: NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
tactcomplabs/xbgas-binutils-gdb	3,011	sim/testsuite/bfin/c_dsp32mac_pair_a1_m.s	//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_m/c_dsp32mac_pair_a1_m.dsp // Spec Reference: dsp32mac pair a1 M MNOP # mach: bfin .include "testutils.inc" start A1 = A0 = 0; // The result accumulated in A1 , and stored to a reg half imm32 r0, 0x63547abd; imm32 r1, 0x86bc8ec7; imm32 r2, 0xa8695679; imm32 r3, 0x00060007; imm32 r4, 0xe6b86569; imm32 r5, 0x1A35860b; imm32 r6, 0x000c086d; imm32 r7, 0x67Be0086; R7 = ( A1 += R1.L * R0.L ); P1 = A1.w; R1 = ( A1 -= R2.H * R3.L ); P2 = A1.w; R3 = ( A1 = R7.L * R4.H ); P3 = A1.w; R5 = ( A1 += R6.H * R5.H ); P4 = A1.w; CHECKREG r0, 0x63547ABD; CHECKREG r1, 0x93734818; CHECKREG r2, 0xA8695679; CHECKREG r3, 0xE7256BA0; CHECKREG r4, 0xE6B86569; CHECKREG r5, 0xE727E098; CHECKREG r6, 0x000C086D; CHECKREG r7, 0x936E7DD6; CHECKREG p1, 0x936E7DD6; CHECKREG p2, 0x93734818; CHECKREG p3, 0xE7256BA0; CHECKREG p4, 0xE727E098; imm32 r0, 0x98764abd; imm32 r1, 0xa1bcf4c7; imm32 r2, 0xb1145649; imm32 r3, 0x0b010005; imm32 r4, 0xefbcbb69; imm32 r5, 0x123501bb; imm32 r6, 0x000c001b; imm32 r7, 0x678e0001; R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L; P1 = A1.w; R1 = ( A1 = R2.L * R3.H ) (M), A0 = R2.H * R3.L; P2 = A1.w; R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H; P3 = A1.w; R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H; P4 = A1.w; CHECKREG r0, 0x98764ABD; CHECKREG r1, 0x3FE4AC0B; CHECKREG r2, 0xB1145649; CHECKREG r3, 0x3FD9C011; CHECKREG r4, 0xEFBCBB69; CHECKREG r5, 0xE078DC52; CHECKREG r6, 0x000C001B; CHECKREG r7, 0x678E0001; CHECKREG p1, 0xE078DC52; CHECKREG p2, 0x03B57949; CHECKREG p3, 0x3FD9C011; CHECKREG p4, 0x3FE4AC0B; imm32 r0, 0x7136459d; imm32 r1, 0xabd69ec7; imm32 r2, 0x71145679; imm32 r3, 0xd8010007; imm32 r4, 0xeddc1569; imm32 r5, 0x122d010b; imm32 r6, 0x0003d01d; imm32 r7, 0x678e0d61; R5 = A1 , A0 = R1.L * R0.L; P1 = A1.w; R7 = A1 , A0 -= R2.H * R3.L; P2 = A1.w; R1 = A1 , A0 += R4.H * R5.H; P3 = A1.w; R5 = A1 , A0 += R6.L * R7.H; P4 = A1.w; CHECKREG r0, 0x7136459D; CHECKREG r1, 0x3FE4AC0B; CHECKREG r2, 0x71145679; CHECKREG r3, 0xD8010007; CHECKREG r4, 0xEDDC1569; CHECKREG r5, 0x3FE4AC0B; CHECKREG r6, 0x0003D01D; CHECKREG r7, 0x3FE4AC0B; CHECKREG p1, 0x3FE4AC0B; CHECKREG p2, 0x3FE4AC0B; CHECKREG p3, 0x3FE4AC0B; CHECKREG p4, 0x3FE4AC0B; imm32 r0, 0x123489bd; imm32 r1, 0x91bcfec7; imm32 r2, 0xa9145679; imm32 r3, 0xd0910007; imm32 r4, 0x34567899; imm32 r5, 0xd235910b; imm32 r6, 0x0d0c0999; imm32 r7, 0x67de0009; R1 = ( A1 += R5.H * R3.H ) (M); P1 = A1.w; R3 = ( A1 = R2.H * R1.H ) (M); P2 = A1.w; R5 = ( A1 -= R7.H * R0.H ) (M); P3 = A1.w; R7 = ( A1 += R4.H * R6.H ) (M); P4 = A1.w; CHECKREG r0, 0x123489BD; CHECKREG r1, 0x1A95CC10; CHECKREG r2, 0xA9145679; CHECKREG r3, 0xF6F970A4; CHECKREG r4, 0x34567899; CHECKREG r5, 0xEF96BB8C; CHECKREG r6, 0x0D0C0999; CHECKREG r7, 0xF2418D94; CHECKREG p1, 0x1A95CC10; CHECKREG p2, 0xF6F970A4; CHECKREG p3, 0xEF96BB8C; CHECKREG p4, 0xF2418D94; pass
tactcomplabs/xbgas-binutils-gdb	4,425	sim/testsuite/bfin/c_alu2op_divq.s	//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp // Spec Reference: alu2op divide q # mach: bfin .include "testutils.inc" start imm32 r0, 0x00000000; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x856789ab; imm32 r5, 0x96789abc; imm32 r6, 0xa789abcd; imm32 r7, 0xb89abcde; R0.L = 1; DIVQ ( R1 , R0 ); DIVQ ( R2 , R0 ); DIVQ ( R3 , R0 ); DIVQ ( R4 , R0 ); DIVQ ( R5 , R0 ); DIVQ ( R6 , R0 ); DIVQ ( R7 , R0 ); DIVQ ( R4 , R0 ); DIVQ ( R0 , R0 ); CHECKREG r1, 0x2466ACF1; CHECKREG r2, 0x4688CF13; CHECKREG r3, 0x68AAF135; CHECKREG r4, 0x159C26AD; CHECKREG r5, 0x2CF33578; CHECKREG r6, 0x4F15579A; CHECKREG r7, 0x713779BC; CHECKREG r0, 0xFFFE0002; imm32 r0, 0x01230002; imm32 r1, 0x00000000; imm32 r2, 0x93456789; imm32 r3, 0xa456789a; imm32 r4, 0xb56789ab; imm32 r5, 0xc6789abc; imm32 r6, 0xd789abcd; imm32 r7, 0xe89abcde; R1.L = -1; DIVQ ( R0 , R1 ); DIVQ ( R2 , R1 ); DIVQ ( R3 , R1 ); DIVQ ( R4 , R1 ); DIVQ ( R5 , R1 ); DIVQ ( R6 , R1 ); DIVQ ( R7 , R1 ); DIVQ ( R1 , R1 ); CHECKREG r0, 0x02440004; CHECKREG r1, 0x0003FFFE; CHECKREG r2, 0x2688CF13; CHECKREG r3, 0x48AEF135; CHECKREG r4, 0x6AD11357; CHECKREG r5, 0x8CF33579; CHECKREG r6, 0xAF15579B; CHECKREG r7, 0xD13779BD; imm32 r0, 0x51230002; imm32 r1, 0x12345678; imm32 r2, 0x00000000; imm32 r3, 0x3456789a; imm32 r4, 0x956789ab; imm32 r5, 0x86789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R2.L = 31; DIVQ ( R0 , R2 ); DIVQ ( R1 , R2 ); DIVQ ( R3 , R2 ); DIVQ ( R4 , R2 ); DIVQ ( R5 , R2 ); DIVQ ( R6 , R2 ); DIVQ ( R7 , R2 ); DIVQ ( R2 , R2 ); CHECKREG r0, 0xA2840005; CHECKREG r1, 0x242AACF1; CHECKREG r2, 0xFFC2003E; CHECKREG r3, 0x686EF135; CHECKREG r4, 0x2A911356; CHECKREG r5, 0x0D2F3578; CHECKREG r6, 0xCF51579B; CHECKREG r7, 0xF0F779BD; imm32 r0, 0x01230002; imm32 r1, 0x82345678; imm32 r2, 0x93456789; imm32 r3, 0x00000000; imm32 r4, 0xb56789ab; imm32 r5, 0xc6789abc; imm32 r6, 0xd789abcd; imm32 r7, 0xe89abcde; R3.L = -31; DIVQ ( R0 , R3 ); DIVQ ( R1 , R3 ); DIVQ ( R2 , R3 ); DIVQ ( R4 , R3 ); DIVQ ( R5 , R3 ); DIVQ ( R6 , R3 ); DIVQ ( R7 , R3 ); DIVQ ( R3 , R3 ); CHECKREG r0, 0x02080004; CHECKREG r1, 0x042AACF1; CHECKREG r2, 0x26C8CF13; CHECKREG r3, 0x003FFFC2; CHECKREG r4, 0x6B0D1357; CHECKREG r5, 0x8D2F3579; CHECKREG r6, 0xAF51579B; CHECKREG r7, 0xD17379BD; imm32 r0, 0x00000001; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x00000000; imm32 r5, 0x96789abc; imm32 r6, 0xa789abcd; imm32 r7, 0xb89abcde; R4.L = 15; DIVQ ( R1 , R4 ); DIVQ ( R2 , R4 ); DIVQ ( R3 , R4 ); DIVQ ( R0 , R4 ); DIVQ ( R5 , R4 ); DIVQ ( R6 , R4 ); DIVQ ( R7 , R4 ); DIVQ ( R4 , R4 ); CHECKREG r0, 0xFFE20002; CHECKREG r1, 0x2486ACF1; CHECKREG r2, 0x466CCF13; CHECKREG r3, 0x688EF135; CHECKREG r4, 0x001E001F; CHECKREG r5, 0x2D0F3578; CHECKREG r6, 0x4F31579A; CHECKREG r7, 0x715379BC; imm32 r0, 0x01230002; imm32 r1, 0x00000000; imm32 r2, 0x93456789; imm32 r3, 0xa456789a; imm32 r4, 0xb56789ab; imm32 r5, 0x00000000; imm32 r6, 0xd789abcd; imm32 r7, 0xe89abcde; R5.L = -15; DIVQ ( R0 , R5 ); DIVQ ( R1 , R5 ); DIVQ ( R2 , R5 ); DIVQ ( R3 , R5 ); DIVQ ( R4 , R5 ); DIVQ ( R6 , R5 ); DIVQ ( R7 , R5 ); DIVQ ( R5 , R5 ); CHECKREG r0, 0x02640004; CHECKREG r1, 0xFFE20001; CHECKREG r2, 0x26A8CF13; CHECKREG r3, 0x48CAF135; CHECKREG r4, 0x6AED1357; CHECKREG r5, 0x001FFFE2; CHECKREG r6, 0xAF31579B; CHECKREG r7, 0xD15379BD; imm32 r0, 0x51230002; imm32 r1, 0x12345678; imm32 r2, 0xb1256790; imm32 r3, 0x3456789a; imm32 r4, 0x956789ab; imm32 r5, 0x86789abc; imm32 r6, 0x00000000; imm32 r7, 0x789abcde; R6.L = 24; DIVQ ( R0 , R6 ); DIVQ ( R1 , R6 ); DIVQ ( R2 , R6 ); DIVQ ( R3 , R6 ); DIVQ ( R4 , R6 ); DIVQ ( R5 , R6 ); DIVQ ( R7 , R6 ); DIVQ ( R6 , R6 ); CHECKREG r0, 0xA2760005; CHECKREG r1, 0x2438ACF1; CHECKREG r2, 0x621ACF20; CHECKREG r3, 0x68DCF135; CHECKREG r4, 0x2A9F1356; CHECKREG r5, 0x0D213578; CHECKREG r6, 0xFFD00030; CHECKREG r7, 0xF16579BD; imm32 r0, 0x01230002; imm32 r1, 0x82345678; imm32 r2, 0x93456789; imm32 r3, 0xa456789a; imm32 r4, 0xb56789ab; imm32 r5, 0xc6789abc; imm32 r6, 0xd789abcd; imm32 r7, 0x00000000; R7.L = -24; DIVQ ( R0 , R7 ); DIVQ ( R1 , R7 ); DIVQ ( R2 , R7 ); DIVQ ( R3 , R7 ); DIVQ ( R4 , R7 ); DIVQ ( R5 , R7 ); DIVQ ( R6 , R7 ); DIVQ ( R7 , R7 ); CHECKREG r0, 0x02160004; CHECKREG r1, 0x0438ACF1; CHECKREG r2, 0x26BACF13; CHECKREG r3, 0x48DCF135; CHECKREG r4, 0x6AFF1357; CHECKREG r5, 0x8D213579; CHECKREG r6, 0xAF43579B; CHECKREG r7, 0x0031FFD0; pass
tactcomplabs/xbgas-binutils-gdb	1,500	sim/testsuite/bfin/random_0003.S	# Test for ASTAT AN setting when overflows occur # mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x18204a80 \| _AV1S \| _AV0 \| _AQ \| _CC \| _AC0_COPY \| _AN \| _AZ); dmm32 A1.w, 0x1098e30b; dmm32 A1.x, 0x0000001f; imm32 R0, 0x440ed6ae; imm32 R5, 0x3272c296; R0.H = (A1 += R0.L * R5.H); checkreg R0, 0x7fffd6ae; checkreg A1.w, 0x00500e03; checkreg A1.x, 0x0000001f; checkreg ASTAT, (0x18204a80 \| _VS \| _V \| _AV1S \| _AV0 \| _AQ \| _CC \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); dmm32 ASTAT, (0x28c08e90 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AC0_COPY \| _AN); dmm32 A0.w, 0xb9da9f02; dmm32 A0.x, 0x00000010; imm32 R0, 0xc104b252; R0.L = A0 (IS); checkreg R0, 0xc1047fff; checkreg ASTAT, (0x28c08e90 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _V_COPY \| _AC0_COPY); dmm32 ASTAT, (0x3cc04000 \| _AV0S \| _AV0 \| _CC \| _AC0_COPY \| _AZ); dmm32 A0.w, 0x2cc20f30; dmm32 A0.x, 0xffffffd0; imm32 R2, 0x367adfeb; imm32 R5, 0x53eeff3c; A0 += R5.H * R2.H (IS); checkreg A0.w, 0x3e9e429c; checkreg A0.x, 0xffffffd0; checkreg ASTAT, (0x3cc04000 \| _AV0S \| _CC \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x18c0ca90 \| _V \| _AV1S \| _AV1 \| _AV0 \| _AC1 \| _AC0 \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); dmm32 A1.w, 0x0614ca96; dmm32 A1.x, 0x00000053; imm32 R3, 0x6c490457; R3 = (A1 -= R3.L * R3.L) (M, S2RND); checkreg R3, 0x7fffffff; checkreg A1.w, 0x0601f505; checkreg A1.x, 0x00000053; checkreg ASTAT, (0x18c0ca90 \| _VS \| _V \| _AV1S \| _AV0 \| _AC1 \| _AC0 \| _V_COPY \| _AC0_COPY \| _AN \| _AZ); pass
tactcomplabs/xbgas-binutils-gdb	1,211	sim/testsuite/bfin/c_dsp32alu_absabs.s	//Original:/testcases/core/c_dsp32alu_absabs/c_dsp32alu_absabs.dsp // Spec Reference: dsp32alu dregs = abs / abs ( dregs, dregs) # mach: bfin .include "testutils.inc" start imm32 r0, 0x15678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x34445515; imm32 r3, 0x46667717; imm32 r4, 0x5567891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x74445515; imm32 r7, 0x86667777; R0 = ABS R0 (V); R1 = ABS R1 (V); R2 = ABS R2 (V); R3 = ABS R3 (V); R4 = ABS R4 (V); R5 = ABS R5 (V); R6 = ABS R6 (V); R7 = ABS R7 (V); CHECKREG r0, 0x156776EF; CHECKREG r1, 0x278954E3; CHECKREG r2, 0x34445515; CHECKREG r3, 0x46667717; CHECKREG r4, 0x556776E5; CHECKREG r5, 0x678954E3; CHECKREG r6, 0x74445515; CHECKREG r7, 0x799A7777; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r4, 0xd8889929; imm32 r5, 0xeaaabb2b; imm32 r6, 0xfcccdd2d; imm32 r7, 0x0eeeffff; R0 = ABS R7 (V); R1 = ABS R6 (V); R2 = ABS R5 (V); R3 = ABS R4 (V); R4 = ABS R3 (V); R5 = ABS R2 (V); R6 = ABS R1 (V); R7 = ABS R0 (V); CHECKREG r0, 0x0EEE0001; CHECKREG r1, 0x033422D3; CHECKREG r2, 0x155644D5; CHECKREG r3, 0x277866D7; CHECKREG r4, 0x277866D7; CHECKREG r5, 0x155644D5; CHECKREG r6, 0x033422D3; CHECKREG r7, 0x0EEE0001; pass
tactcomplabs/xbgas-binutils-gdb	9,511	sim/testsuite/bfin/c_dsp32shift_rot.s	//Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot/c_dsp32shift_rot.dsp // Spec Reference: dsp32shift rot # mach: bfin .include "testutils.inc" start R0 = 0; ASTAT = R0; imm32 r0, 0x01230001; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R1 = ROT R0 BY R0.L; R2 = ROT R1 BY R0.L; R3 = ROT R2 BY R0.L; R4 = ROT R3 BY R0.L; R5 = ROT R4 BY R0.L; R6 = ROT R5 BY R0.L; R7 = ROT R6 BY R0.L; R0 = ROT R7 BY R0.L; CHECKREG r1, 0x02460002; CHECKREG r0, 0x23000100; CHECKREG r2, 0x048C0004; CHECKREG r3, 0x09180008; CHECKREG r4, 0x12300010; CHECKREG r5, 0x24600020; CHECKREG r6, 0x48C00040; CHECKREG r7, 0x91800080; imm32 r0, 0x01230001; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R1.L = 15; R2 = ROT R0 BY R1.L; R3 = ROT R1 BY R1.L; R4 = ROT R2 BY R1.L; R5 = ROT R3 BY R1.L; R6 = ROT R4 BY R1.L; R7 = ROT R5 BY R1.L; R0 = ROT R6 BY R1.L; R1 = ROT R7 BY R1.L; CHECKREG r0, 0x2C04C400; CHECKREG r1, 0x5C489000; CHECKREG r2, 0x8000C048; CHECKREG r3, 0x0007C48D; CHECKREG r4, 0x60242000; CHECKREG r5, 0xE2468001; CHECKREG r6, 0x10005809; CHECKREG r7, 0x4000B891; imm32 r0, 0x01230002; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R2 = 16; R3 = ROT R0 BY R2.L; R4 = ROT R1 BY R2.L; R5 = ROT R2 BY R2.L; R6 = ROT R3 BY R2.L; R7 = ROT R4 BY R2.L; R0 = ROT R5 BY R2.L; R1 = ROT R6 BY R2.L; R2 = ROT R7 BY R2.L; CHECKREG r0, 0x00000008; CHECKREG r1, 0x00010048; CHECKREG r2, 0x2B3CC48D; CHECKREG r3, 0x00020091; CHECKREG r4, 0x5678891A; CHECKREG r5, 0x00100000; CHECKREG r6, 0x00910001; CHECKREG r7, 0x891A2B3C; imm32 r0, 0x01230003; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R3.L = 31; R4 = ROT R0 BY R3.L; R5 = ROT R1 BY R3.L; R6 = ROT R2 BY R3.L; R7 = ROT R3 BY R3.L; R0 = ROT R4 BY R3.L; R1 = ROT R5 BY R3.L; R2 = ROT R6 BY R3.L; R3 = ROT R7 BY R3.L; CHECKREG r0, 0x60123000; CHECKREG r1, 0x11234567; CHECKREG r2, 0x62345678; CHECKREG r3, 0xE3456001; CHECKREG r4, 0x8048C000; CHECKREG r5, 0x448D159E; CHECKREG r6, 0x88D159E2; CHECKREG r7, 0x8D158007; imm32 r0, 0x01230004; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R4.L = -1; R0 = ROT R0 BY R4.L; R1 = ROT R1 BY R4.L; R2 = ROT R2 BY R4.L; R3 = ROT R3 BY R4.L; R4 = ROT R4 BY R4.L; R5 = ROT R5 BY R4.L; R6 = ROT R6 BY R4.L; R7 = ROT R7 BY R4.L; CHECKREG r0, 0x80918002; CHECKREG r1, 0x091A2B3C; CHECKREG r2, 0x11A2B3C4; CHECKREG r3, 0x9A2B3C4D; CHECKREG r4, 0x22B3FFFF; CHECKREG r5, 0xAB3C4D5E; CHECKREG r6, 0x33C4D5E6; CHECKREG r7, 0xBC4D5E6F; imm32 r0, 0x01230005; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R5.L = -15; R6 = ROT R0 BY R5.L; R7 = ROT R1 BY R5.L; R0 = ROT R2 BY R5.L; R1 = ROT R3 BY R5.L; R2 = ROT R4 BY R5.L; R3 = ROT R5 BY R5.L; R4 = ROT R6 BY R5.L; R5 = ROT R7 BY R5.L; CHECKREG r0, 0x9E26468A; CHECKREG r1, 0xE26A68AC; CHECKREG r2, 0x26AE8ACF; CHECKREG r3, 0xFFC4ACF1; CHECKREG r4, 0x091A0028; CHECKREG r5, 0x91A0B3C0; CHECKREG r6, 0x00140246; CHECKREG r7, 0x59E02468; imm32 r0, 0x01230006; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R6.L = -16; R7 = ROT R0 BY R6.L; R0 = ROT R1 BY R6.L; R1 = ROT R2 BY R6.L; R2 = ROT R3 BY R6.L; R3 = ROT R4 BY R6.L; R4 = ROT R5 BY R6.L; R5 = ROT R6 BY R6.L; R6 = ROT R7 BY R6.L; CHECKREG r0, 0xACF01234; CHECKREG r1, 0xCF122345; CHECKREG r2, 0xF1343456; CHECKREG r3, 0x13564567; CHECKREG r4, 0x35795678; CHECKREG r5, 0xFFE16789; CHECKREG r6, 0x0247000C; CHECKREG r7, 0x000C0123; imm32 r0, 0x01230007; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R7.L = -27; R0 = ROT R0 BY R7.L; R1 = ROT R1 BY R7.L; R2 = ROT R2 BY R7.L; R3 = ROT R3 BY R7.L; R4 = ROT R4 BY R7.L; R5 = ROT R5 BY R7.L; R6 = ROT R6 BY R7.L; R7 = ROT R7 BY R7.L; CHECKREG r0, 0x48C001C0; CHECKREG r1, 0x8D159E02; CHECKREG r2, 0xD159E244; CHECKREG r3, 0x159E2686; CHECKREG r4, 0x59E26AE8; CHECKREG r5, 0x9E26AF2A; CHECKREG r6, 0xE26AF36C; CHECKREG r7, 0x26BFF96F; imm32 r0, 0x01230008; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R0.L = 7; //r0 = rot (r0 by rl0); R1 = ROT R1 BY R0.L; R2 = ROT R2 BY R0.L; R3 = ROT R3 BY R0.L; R4 = ROT R4 BY R0.L; R5 = ROT R5 BY R0.L; R6 = ROT R6 BY R0.L; R7 = ROT R7 BY R0.L; CHECKREG r0, 0x01230007; CHECKREG r1, 0x1A2B3C04; CHECKREG r2, 0xA2B3C4C8; CHECKREG r3, 0x2B3C4D4D; CHECKREG r4, 0xB3C4D591; CHECKREG r5, 0x3C4D5E15; CHECKREG r6, 0xC4D5E6D9; CHECKREG r7, 0x4D5E6F5E; imm32 r0, 0x01230009; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R1.L = 16; R0 = ROT R0 BY R1.L; //r1 = rot (r1 by rl1); R2 = ROT R2 BY R1.L; R3 = ROT R3 BY R1.L; R4 = ROT R4 BY R1.L; R5 = ROT R5 BY R1.L; R6 = ROT R6 BY R1.L; R7 = ROT R7 BY R1.L; CHECKREG r0, 0x00090091; CHECKREG r1, 0x12340010; CHECKREG r2, 0x678991A2; CHECKREG r3, 0x789A9A2B; CHECKREG r4, 0x89AB22B3; CHECKREG r5, 0x9ABCAB3C; CHECKREG r6, 0xABCD33C4; CHECKREG r7, 0xBCDEBC4D; imm32 r0, 0x0123000a; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R2.L = 30; R0 = ROT R0 BY R2.L; R1 = ROT R1 BY R2.L; //r2 = rot (r2 by rl2); R3 = ROT R3 BY R2.L; R4 = ROT R4 BY R2.L; R5 = ROT R5 BY R2.L; R6 = ROT R6 BY R2.L; R7 = ROT R7 BY R2.L; CHECKREG r0, 0x80246001; CHECKREG r1, 0x02468ACF; CHECKREG r2, 0x2345001E; CHECKREG r3, 0x868ACF13; CHECKREG r4, 0xC8ACF135; CHECKREG r5, 0x0ACF1357; CHECKREG r6, 0x6CF13579; CHECKREG r7, 0xAF13579B; imm32 r0, 0x0123000b; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R3.L = 31; R0 = ROT R0 BY R3.L; R1 = ROT R1 BY R3.L; R2 = ROT R2 BY R3.L; //r3 = rot (r3 by rl3); R4 = ROT R4 BY R3.L; R5 = ROT R5 BY R3.L; R6 = ROT R6 BY R3.L; R7 = ROT R7 BY R3.L; CHECKREG r0, 0xC048C002; CHECKREG r1, 0x448D159E; CHECKREG r2, 0x88D159E2; CHECKREG r3, 0x3456001F; CHECKREG r4, 0x9159E26A; CHECKREG r5, 0x559E26AF; CHECKREG r6, 0x99E26AF3; CHECKREG r7, 0x1E26AF37; imm32 r0, 0x0123000c; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R4.L = -2; R0 = ROT R0 BY R4.L; R1 = ROT R1 BY R4.L; R2 = ROT R2 BY R4.L; R3 = ROT R3 BY R4.L; //r4 = rot (r4 by rl4); R5 = ROT R5 BY R4.L; R6 = ROT R6 BY R4.L; R7 = ROT R7 BY R4.L; CHECKREG r0, 0x4048C003; CHECKREG r1, 0x048D159E; CHECKREG r2, 0x88D159E2; CHECKREG r3, 0x0D159E26; CHECKREG r4, 0x4567FFFE; CHECKREG r5, 0x559E26AF; CHECKREG r6, 0x99E26AF3; CHECKREG r7, 0x1E26AF37; imm32 r0, 0x0123000d; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R5.L = -17; R0 = ROT R0 BY R5.L; R1 = ROT R1 BY R5.L; R2 = ROT R2 BY R5.L; R3 = ROT R3 BY R5.L; R4 = ROT R4 BY R5.L; //r5 = rot (r5 by rl5); R6 = ROT R6 BY R5.L; R7 = ROT R7 BY R5.L; CHECKREG r0, 0x000D8091; CHECKREG r1, 0x5678891A; CHECKREG r2, 0x678911A2; CHECKREG r3, 0x789A9A2B; CHECKREG r4, 0x89AB22B3; CHECKREG r5, 0x5678FFEF; CHECKREG r6, 0xABCDB3C4; CHECKREG r7, 0xBCDEBC4D; imm32 r0, 0x0123000e; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R6.L = -30; R0 = ROT R0 BY R6.L; R1 = ROT R1 BY R6.L; R2 = ROT R2 BY R6.L; R3 = ROT R3 BY R6.L; R4 = ROT R4 BY R6.L; R5 = ROT R5 BY R6.L; //r6 = rot (r6 by rl6); R7 = ROT R7 BY R6.L; CHECKREG r0, 0x09180070; CHECKREG r1, 0x91A2B3C0; CHECKREG r2, 0x1A2B3C48; CHECKREG r3, 0xA2B3C4D4; CHECKREG r4, 0x2B3C4D5D; CHECKREG r5, 0xB3C4D5E1; CHECKREG r6, 0x6789FFE2; CHECKREG r7, 0xC4D5E6F1; imm32 r0, 0x0123000f; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R7.L = -31; R0 = ROT R0 BY R7.L; R1 = ROT R1 BY R7.L; R2 = ROT R2 BY R7.L; R3 = ROT R3 BY R7.L; R4 = ROT R4 BY R7.L; R5 = ROT R5 BY R7.L; R6 = ROT R6 BY R7.L; R7 = ROT R7 BY R7.L; CHECKREG r0, 0x048C003E; CHECKREG r1, 0x48D159E0; CHECKREG r2, 0x8D159E24; CHECKREG r3, 0xD159E268; CHECKREG r4, 0x159E26AC; CHECKREG r5, 0x59E26AF2; CHECKREG r6, 0x9E26AF36; CHECKREG r7, 0xE26BFF86; pass
tactcomplabs/xbgas-binutils-gdb	8,707	sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn_s.s	//Original:/testcases/core/c_dsp32shiftim_ahalf_rn_s/c_dsp32shiftim_ahalf_rn_s.dsp // Spec Reference: dsp32shift ashift # mach: bfin .include "testutils.inc" start imm32 r0, 0x00000000; R0.L = -1; imm32 r1, 0x00008001; imm32 r2, 0x00008002; imm32 r3, 0x00008003; imm32 r4, 0x00008004; imm32 r5, 0x00008005; imm32 r6, 0x00008006; imm32 r7, 0x00008007; R0.L = R0.L >>> 10; R1.L = R1.L >>> 10; R2.L = R2.L >>> 10; R3.L = R3.L >>> 10; R4.L = R4.L >>> 10; R5.L = R5.L >>> 10; R6.L = R6.L >>> 10; R7.L = R7.L >>> 10; CHECKREG r0, 0x0000FFFF; CHECKREG r1, 0x0000FFE0; CHECKREG r2, 0x0000FFE0; CHECKREG r3, 0x0000FFE0; CHECKREG r4, 0x0000FFE0; CHECKREG r5, 0x0000FFE0; CHECKREG r6, 0x0000FFE0; CHECKREG r7, 0x0000FFE0; imm32 r0, 0x02008020; imm32 r0, 0x02008021; imm32 r2, 0x02008022; imm32 r3, 0x02008023; imm32 r4, 0x02008024; imm32 r5, 0x02008025; imm32 r6, 0x02008026; imm32 r7, 0x02008027; R0.L = R0.L >>> 11; R1.L = R1.L >>> 11; R2.L = R2.L >>> 11; R3.L = R3.L >>> 11; R4.L = R4.L >>> 11; R5.L = R5.L >>> 11; R6.L = R6.L >>> 11; R7.L = R7.L >>> 11; CHECKREG r0, 0x0200FFF0; CHECKREG r1, 0x0000FFFF; CHECKREG r2, 0x0200FFF0; CHECKREG r3, 0x0200FFF0; CHECKREG r4, 0x0200FFF0; CHECKREG r5, 0x0200FFF0; CHECKREG r6, 0x0200FFF0; CHECKREG r7, 0x0200FFF0; imm32 r0, 0x00308001; imm32 r1, 0x00308001; R2.L = -15; imm32 r3, 0x00308003; imm32 r4, 0x00308004; imm32 r5, 0x00308005; imm32 r6, 0x00308006; imm32 r7, 0x00308007; R0.L = R0.L >>> 12; R1.L = R1.L >>> 12; R2.L = R2.L >>> 12; R3.L = R3.L >>> 12; R4.L = R4.L >>> 12; R5.L = R5.L >>> 12; R6.L = R6.L >>> 12; R7.L = R7.L >>> 12; CHECKREG r0, 0x0030FFF8; CHECKREG r1, 0x0030FFF8; CHECKREG r2, 0x0200FFFF; CHECKREG r3, 0x0030FFF8; CHECKREG r4, 0x0030FFF8; CHECKREG r5, 0x0030FFF8; CHECKREG r6, 0x0030FFF8; CHECKREG r7, 0x0030FFF8; imm32 r0, 0x00008401; imm32 r1, 0x00008401; imm32 r2, 0x00008402; R3.L = -16; imm32 r4, 0x00008404; imm32 r5, 0x00008405; imm32 r6, 0x00008406; imm32 r7, 0x00008407; R0.L = R0.L >>> 3; R1.L = R1.L >>> 3; R2.L = R2.L >>> 3; R3.L = R3.L >>> 3; R4.L = R4.L >>> 3; R5.L = R5.L >>> 3; R6.L = R6.L >>> 3; R7.L = R7.L >>> 3; CHECKREG r0, 0x0000F080; CHECKREG r1, 0x0000F080; CHECKREG r2, 0x0000F080; CHECKREG r3, 0x0030FFFE; CHECKREG r4, 0x0000F080; CHECKREG r5, 0x0000F080; CHECKREG r6, 0x0000F080; CHECKREG r7, 0x0000F080; // d_lo = ashift (d_hi BY d_lo) // RHx by RLx imm32 r0, 0x05000500; imm32 r1, 0x85010500; imm32 r2, 0x85020500; imm32 r3, 0x85030500; imm32 r4, 0x85040500; imm32 r5, 0x85050500; imm32 r6, 0x85060500; imm32 r7, 0x85070500; R0.L = R0.H >>> 10; R1.L = R1.H >>> 10; R2.L = R2.H >>> 10; R3.L = R3.H >>> 10; R4.L = R4.H >>> 10; R5.L = R5.H >>> 10; R6.L = R6.H >>> 10; R7.L = R7.H >>> 10; CHECKREG r0, 0x05000001; CHECKREG r1, 0x8501FFE1; CHECKREG r2, 0x8502FFE1; CHECKREG r3, 0x8503FFE1; CHECKREG r4, 0x8504FFE1; CHECKREG r5, 0x8505FFE1; CHECKREG r6, 0x8506FFE1; CHECKREG r7, 0x8507FFE1; imm32 r0, 0x80610000; R1.L = -1; imm32 r2, 0x80620000; imm32 r3, 0x80630000; imm32 r4, 0x80640000; imm32 r5, 0x80650000; imm32 r6, 0x80660000; imm32 r7, 0x80670000; R0.L = R0.H >>> 11; R1.L = R1.H >>> 11; R2.L = R2.H >>> 11; R3.L = R3.H >>> 11; R4.L = R4.H >>> 11; R5.L = R5.H >>> 11; R6.L = R6.H >>> 11; R7.L = R7.H >>> 11; CHECKREG r0, 0x8061FFF0; CHECKREG r1, 0x8501FFF0; CHECKREG r2, 0x8062FFF0; CHECKREG r3, 0x8063FFF0; CHECKREG r4, 0x8064FFF0; CHECKREG r5, 0x8065FFF0; CHECKREG r6, 0x8066FFF0; CHECKREG r7, 0x8067FFF0; imm32 r0, 0xa0010070; imm32 r1, 0xa0010070; R2.L = -15; imm32 r3, 0xa0030070; imm32 r4, 0xa0040070; imm32 r5, 0xa0050070; imm32 r6, 0xa0060070; imm32 r7, 0xa0070070; R0.L = R0.H >>> 12; R1.L = R1.H >>> 12; R2.L = R2.H >>> 12; R3.L = R3.H >>> 12; R4.L = R4.H >>> 12; R5.L = R5.H >>> 12; R6.L = R6.H >>> 12; R7.L = R7.H >>> 12; CHECKREG r0, 0xA001FFFA; CHECKREG r1, 0xA001FFFA; CHECKREG r2, 0x8062FFF8; CHECKREG r3, 0xA003FFFA; CHECKREG r4, 0xA004FFFA; CHECKREG r5, 0xA005FFFA; CHECKREG r6, 0xA006FFFA; CHECKREG r7, 0xA007FFFA; imm32 r0, 0xb8010001; imm32 r1, 0xb8010001; imm32 r2, 0xb8020002; R3.L = -16; imm32 r4, 0xb8040004; imm32 r5, 0xb8050005; imm32 r6, 0xb8060006; imm32 r7, 0xb8070007; R0.L = R0.H >>> 13; R1.L = R1.H >>> 13; R2.L = R2.H >>> 13; R3.L = R3.H >>> 13; R4.L = R4.H >>> 13; R5.L = R5.H >>> 13; R6.L = R6.H >>> 13; R7.L = R7.H >>> 13; CHECKREG r0, 0xB801FFFD; CHECKREG r1, 0xB801FFFD; CHECKREG r2, 0xB802FFFD; CHECKREG r3, 0xA003FFFD; CHECKREG r4, 0xB804FFFD; CHECKREG r5, 0xB805FFFD; CHECKREG r6, 0xB806FFFD; CHECKREG r7, 0xB807FFFD; // d_hi = ashft (d_lo BY d_lo) // RLx by RLx imm32 r0, 0x00009001; imm32 r1, 0x00009001; imm32 r2, 0x00009002; imm32 r3, 0x00009003; imm32 r4, 0x00009000; imm32 r5, 0x00009005; imm32 r6, 0x00009006; imm32 r7, 0x00009007; R0.H = R0.L >>> 14; R1.H = R1.L >>> 14; R2.H = R2.L >>> 14; R3.H = R3.L >>> 14; R4.H = R4.L >>> 14; R5.H = R5.L >>> 14; R6.H = R6.L >>> 14; R7.H = R7.L >>> 14; CHECKREG r0, 0xFFFE9001; CHECKREG r1, 0xFFFE9001; CHECKREG r2, 0xFFFE9002; CHECKREG r3, 0xFFFE9003; CHECKREG r4, 0xFFFE9000; CHECKREG r5, 0xFFFE9005; CHECKREG r6, 0xFFFE9006; CHECKREG r7, 0xFFFE9007; imm32 r0, 0xa0008001; imm32 r1, 0xa0008001; imm32 r2, 0xa0008002; imm32 r3, 0xa0008003; imm32 r4, 0xa0008004; R5.L = -1; imm32 r6, 0xa0008006; imm32 r7, 0xa0008007; R0.H = R0.L >>> 5; R1.H = R1.L >>> 5; R2.H = R2.L >>> 5; R3.H = R3.L >>> 5; R4.H = R4.L >>> 5; R5.H = R5.L >>> 5; R6.H = R6.L >>> 5; R7.H = R7.L >>> 5; CHECKREG r0, 0xFC008001; CHECKREG r1, 0xFC008001; CHECKREG r2, 0xFC008002; CHECKREG r3, 0xFC008003; CHECKREG r4, 0xFC008004; CHECKREG r5, 0xFFFFFFFF; CHECKREG r6, 0xFC008006; CHECKREG r7, 0xFC008007; imm32 r0, 0x00009b01; imm32 r1, 0x00009b01; imm32 r2, 0x00009b02; imm32 r3, 0x00009b03; imm32 r4, 0x00009b04; imm32 r5, 0x00009b05; R6.L = -15; imm32 r7, 0x00009007; R0.H = R0.L >>> 6; R1.H = R1.L >>> 6; R2.H = R2.L >>> 6; R3.H = R3.L >>> 6; R4.H = R4.L >>> 6; R5.H = R5.L >>> 6; R6.H = R6.L >>> 6; R7.H = R7.L >>> 6; CHECKREG r0, 0xFE6C9B01; CHECKREG r1, 0xFE6C9B01; CHECKREG r2, 0xFE6C9B02; CHECKREG r3, 0xFE6C9B03; CHECKREG r4, 0xFE6C9B04; CHECKREG r5, 0xFE6C9B05; CHECKREG r6, 0xFFFFFFF1; CHECKREG r7, 0xFE409007; imm32 r0, 0x0000a0c1; imm32 r1, 0x0000a0c1; imm32 r2, 0x0000a0c2; imm32 r3, 0x0000a0c3; imm32 r4, 0x0000a0c4; imm32 r5, 0x0000a0c5; imm32 r6, 0x0000a0c6; R7.L = -16; R0.H = R0.L >>> 7; R1.H = R1.L >>> 7; R2.H = R2.L >>> 7; R3.H = R3.L >>> 7; R4.H = R4.L >>> 7; R5.H = R5.L >>> 7; R6.H = R6.L >>> 7; R7.H = R7.L >>> 7; CHECKREG r0, 0xFF41A0C1; CHECKREG r1, 0xFF41A0C1; CHECKREG r2, 0xFF41A0C2; CHECKREG r3, 0xFF41A0C3; CHECKREG r4, 0xFF41A0C4; CHECKREG r5, 0xFF41A0C5; CHECKREG r6, 0xFF41A0C6; CHECKREG r7, 0xFFFFFFF0; imm32 r0, 0x80010d00; imm32 r1, 0x80010d00; imm32 r2, 0x80020d00; imm32 r3, 0x80030d00; R4.L = -1; imm32 r5, 0x80050d00; imm32 r6, 0x80060d00; imm32 r7, 0x80070d00; R0.H = R0.H >>> 14; R1.H = R1.H >>> 14; R2.H = R2.H >>> 14; R3.H = R3.H >>> 14; R4.H = R4.H >>> 14; R5.H = R5.H >>> 14; R6.H = R6.H >>> 14; R7.H = R7.H >>> 14; CHECKREG r0, 0xFFFE0D00; CHECKREG r1, 0xFFFE0D00; CHECKREG r2, 0xFFFE0D00; CHECKREG r3, 0xFFFE0D00; CHECKREG r4, 0xFFFFFFFF; CHECKREG r5, 0xFFFE0D00; CHECKREG r6, 0xFFFE0D00; CHECKREG r7, 0xFFFE0D00; imm32 r0, 0x8d010000; imm32 r1, 0x8d010000; imm32 r2, 0x8d020000; imm32 r3, 0x8d030000; imm32 r4, 0x8d040000; R5.L = -1; imm32 r6, 0x8d060000; imm32 r7, 0x8d070000; R0.H = R0.H >>> 15; R1.H = R1.H >>> 15; R2.H = R2.H >>> 15; R3.H = R3.H >>> 15; R4.H = R4.H >>> 15; R5.H = R5.H >>> 15; R6.H = R6.H >>> 15; R7.H = R7.H >>> 15; CHECKREG r0, 0xFFFF0000; CHECKREG r1, 0xFFFF0000; CHECKREG r2, 0xFFFF0000; CHECKREG r3, 0xFFFF0000; CHECKREG r4, 0xFFFF0000; CHECKREG r5, 0xFFFFFFFF; CHECKREG r6, 0xFFFF0000; CHECKREG r7, 0xFFFF0000; imm32 r0, 0xde010000; imm32 r1, 0xde010000; imm32 r2, 0xde020000; imm32 r3, 0xde030000; imm32 r4, 0xde040000; imm32 r5, 0xde050000; R6.L = -15; imm32 r7, 0xd0070000; R0.L = R0.H >>> 10; R1.L = R1.H >>> 10; R2.L = R2.H >>> 10; R3.L = R3.H >>> 10; R4.L = R4.H >>> 10; R5.L = R5.H >>> 10; R6.L = R6.H >>> 10; R7.L = R7.H >>> 10; CHECKREG r0, 0xDE01FFF7; CHECKREG r1, 0xDE01FFF7; CHECKREG r2, 0xDE02FFF7; CHECKREG r3, 0xDE03FFF7; CHECKREG r4, 0xDE04FFF7; CHECKREG r5, 0xDE05FFF7; CHECKREG r6, 0xFFFFFFFF; CHECKREG r7, 0xD007FFF4; imm32 r0, 0x9f010c00; imm32 r1, 0xaf010c00; imm32 r2, 0xbf020c00; imm32 r3, 0xcf030c00; imm32 r4, 0xdf040c00; imm32 r5, 0xef050c00; imm32 r6, 0xff060c00; R7.L = -16; R0.H = R0.H >>> 5; R1.H = R1.H >>> 5; R2.H = R2.H >>> 5; R3.H = R3.H >>> 5; R4.H = R4.H >>> 5; R5.H = R5.H >>> 5; R6.H = R6.H >>> 5; R7.H = R7.H >>> 5; CHECKREG r0, 0xFCF80C00; CHECKREG r1, 0xFD780C00; CHECKREG r2, 0xFDF80C00; CHECKREG r3, 0xFE780C00; CHECKREG r4, 0xFEF80C00; CHECKREG r5, 0xFF780C00; CHECKREG r6, 0xFFF80C00; CHECKREG r7, 0xFE80FFF0; pass
tactcomplabs/xbgas-binutils-gdb	11,608	sim/testsuite/bfin/c_ldstidxl_ld_preg.s	//Original:testcases/core/c_ldstidxl_ld_preg/c_ldstidxl_ld_preg.dsp // Spec Reference: c_ldstidxl load dreg # mach: bfin .include "testutils.inc" start // set all regs init_i_regs 0; init_b_regs 0; init_l_regs 0; init_m_regs 0; INIT_R_REGS 0; I0 = P3; I2 = SP; // initial values I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p1, DATA_ADDR_1, 0x00; loadsym p2, DATA_ADDR_2, 0xA0; loadsym i1, DATA_ADDR_1, 0x70; loadsym p4, DATA_ADDR_2, 0x70; loadsym p5, DATA_ADDR_1, 0x70; loadsym fp, DATA_ADDR_2, 0x70; loadsym i3, DATA_ADDR_1, 0x70; P3 = I1; SP = I3; P2 = [ P1 + 12 ]; P3 = [ P1 + 44 ]; P4 = [ P1 + 8 ]; P5 = [ P1 + 156 ]; SP = [ P1 + 16 ]; FP = [ P1 + 120 ]; P1 = [ P1 + 24 ]; CHECKREG p1, 0x18191A1B; CHECKREG p2, 0x0C0D0E0F; CHECKREG p3, 0x74757677; CHECKREG p4, 0x08090A0B; CHECKREG p5, 0x08090A0B; CHECKREG sp, 0x10111213; CHECKREG fp, 0x58596061; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p2, DATA_ADDR_2, 0xA0; P3 = I1; SP = I3; P1 = [ P2 + -128 ]; P3 = [ P2 + -36 ]; P4 = [ P2 + -40 ]; P5 = [ P2 + -144 ]; SP = [ P2 + -48 ]; FP = [ P2 + 52 ]; P2 = [ P2 + -132 ]; CHECKREG p1, 0xEBECEDEE; CHECKREG p2, 0x7C7D7E7F; CHECKREG p3, 0xA60CAD7E; CHECKREG p4, 0xA50CAD6E; CHECKREG p5, 0x70717273; CHECKREG sp, 0xA30CAD4E; CHECKREG fp, 0x64656667; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym i1, DATA_ADDR_1, 0x70; P3 = I1; SP = I3; P1 = [ P3 + 56 ]; P2 = [ P3 + -104 ]; P4 = [ P3 + 80 ]; P5 = [ P3 + -56 ]; SP = [ P3 + 52 ]; FP = [ P3 + -48 ]; P3 = [ P3 + 84 ]; CHECKREG p1, 0x14151617; CHECKREG p2, 0x08090A0B; CHECKREG p3, 0x82838485; CHECKREG p4, 0x74757677; CHECKREG p5, 0x80818283; CHECKREG sp, 0x10111213; CHECKREG fp, 0x01020304; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p4, DATA_ADDR_2, 0x70; P3 = I1; SP = I3; P1 = [ P4 + 44 ]; P2 = [ P4 + -40 ]; P3 = [ P4 + -96 ]; P5 = [ P4 + -68 ]; SP = [ P4 + 84 ]; FP = [ P4 + 108 ]; P4 = [ P4 + -32 ]; CHECKREG p1, 0x6C6D6E6F; CHECKREG p2, 0xAB0CAD03; CHECKREG p3, 0x70717273; CHECKREG p4, 0xAB0CAD05; CHECKREG p5, 0xFBFCFDFE; CHECKREG sp, 0x03040506; CHECKREG fp, 0x6C6D6E6F; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_1, 0x70; P3 = I1; SP = I3; P1 = [ P5 + 16 ]; P2 = [ P5 + 12 ]; P3 = [ P5 + 96 ]; P4 = [ P5 + 0 ]; SP = [ P5 + -44 ]; FP = [ P5 + 28 ]; P5 = [ P5 + -84 ]; CHECKREG p1, 0x66676869; CHECKREG p2, 0x62636465; CHECKREG p3, 0x84858687; CHECKREG p4, 0x50515253; CHECKREG p5, 0x1C1D1E1F; CHECKREG sp, 0x05060708; CHECKREG fp, 0x72636467; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym i3, DATA_ADDR_2, 0x70; P3 = I1; SP = I3; P1 = [ SP + -72 ]; P2 = [ SP + 16 ]; P3 = [ SP + -80 ]; P4 = [ SP + 92 ]; P5 = [ SP + -28 ]; FP = [ SP + 32 ]; SP = [ SP + -36 ]; CHECKREG p1, 0xF7F8F9FA; CHECKREG p2, 0xB455565B; CHECKREG p3, 0xEBECEDEE; CHECKREG p4, 0x0B0CAD0E; CHECKREG p5, 0xAB0CAD06; CHECKREG sp, 0xAB0CAD04; CHECKREG fp, 0x60616263; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym fp, DATA_ADDR_2, 0x70; P3 = I1; SP = I3; P1 = [ FP + 40 ]; P2 = [ FP + 44 ]; P3 = [ FP + 96 ]; P4 = [ FP + 52 ]; P5 = [ FP + 104 ]; SP = [ FP + 60 ]; FP = [ FP + 64 ]; CHECKREG p1, 0x68696A6B; CHECKREG p2, 0x6C6D6E6F; CHECKREG p3, 0x60616263; CHECKREG p4, 0x74757677; CHECKREG p5, 0x68696A6B; CHECKREG sp, 0x7C7D7E7F; CHECKREG fp, 0xEBECEDEE; P3 = I0; SP = I2; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xa667686a DATA_ADDR_2: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xA50CAD6E .dd 0xA60CAD7E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xA50CAD6E .dd 0xA60CAD7E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0x0F101213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0xBC0DBE21 .dd 0xBC1DBE22 .dd 0xBC2DBE23 .dd 0xBC3DBE24 .dd 0xBC4DBE65 .dd 0xBC5DBE27 .dd 0xBC6DBE28 .dd 0xBC7DBE29 .dd 0xBC8DBE2F .dd 0xBC9DBE20 .dd 0xBCADBE21 .dd 0xBCBDBE2F .dd 0xBCCDBE23 .dd 0xBCDDBE24 .dd 0xBCFDBE25 .dd 0xC455565C .dd 0xC859606C .dd 0xC263646C .dd 0xC667686C .dd 0xCC0DBE2C .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	3,526	sim/testsuite/bfin/c_dsp32mac_dr_a1_tu.s	//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp // Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction) # mach: bfin .include "testutils.inc" start A1 = A0 = 0; // The result accumulated in A1 , and stored to a reg half imm32 r0, 0xa3545abd; imm32 r1, 0xbdbcfec7; imm32 r2, 0xc1248679; imm32 r3, 0xd0069007; imm32 r4, 0xefbc4569; imm32 r5, 0xcd35500b; imm32 r6, 0xe00c800d; imm32 r7, 0xf78e900f; R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU); R1 = A1.w; R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU); R3 = A1.w; R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU); R5 = A1.w; R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU); R7 = A1.w; CHECKREG r0, 0x5A4E5ABD; CHECKREG r1, 0x5A4E0EEB; CHECKREG r2, 0x00008679; CHECKREG r3, 0x00000000; CHECKREG r4, 0x4AF54569; CHECKREG r5, 0x4AF50D14; CHECKREG r6, 0xFFFF800D; CHECKREG r7, 0x239CE7BC; // The result accumulated in A1, and stored to a reg half (MNOP) imm32 r0, 0x63548abd; imm32 r1, 0x7dbcfec7; imm32 r2, 0xC5885679; imm32 r3, 0xC5880000; imm32 r4, 0xcfbc4569; imm32 r5, 0xd235c00b; imm32 r6, 0xe00ca00d; imm32 r7, 0x678e700f; R0.H = ( A1 = R1.L * R0.L ) (TFU); R1 = A1.w; R2.H = ( A1 += R2.L * R3.H ) (TFU); R3 = A1.w; R4.H = ( A1 -= R4.H * R5.L ) (TFU); R5 = A1.w; R6.H = ( A1 = R6.H * R7.H ) (TFU); R7 = A1.w; CHECKREG r0, 0x8A138ABD; CHECKREG r1, 0x8A135EEB; CHECKREG r2, 0xCCCC5679; CHECKREG r3, 0xCCCC6C33; CHECKREG r4, 0x30F64569; CHECKREG r5, 0x30F67F1F; CHECKREG r6, 0x5AA1A00D; CHECKREG r7, 0x5AA11AA8; // The result accumulated in A1 , and stored to a reg half (MNOP) imm32 r0, 0x5354babd; imm32 r1, 0x6dbcdec7; imm32 r2, 0x7124e679; imm32 r3, 0x80067007; imm32 r4, 0x9fbc4569; imm32 r5, 0xa235900b; imm32 r6, 0xb00c300d; imm32 r7, 0xc78ea00f; R0.H = A1 , A0 -= R1.L * R0.L (TFU); R1 = A1.w; R2.H = A1 , A0 += R2.H * R3.L (TFU); R3 = A1.w; R4.H = A1 , A0 -= R4.H * R5.H (TFU); R5 = A1.w; R6.H = A1 , A0 = R6.L * R7.H (TFU); R7 = A1.w; CHECKREG r0, 0x5AA1BABD; CHECKREG r1, 0x5AA11AA8; CHECKREG r2, 0x5AA1E679; CHECKREG r3, 0x5AA11AA8; CHECKREG r4, 0x5AA14569; CHECKREG r5, 0x5AA11AA8; CHECKREG r6, 0x5AA1300D; CHECKREG r7, 0x5AA11AA8; // The result accumulated in A1 , and stored to a reg half imm32 r0, 0x33545abd; imm32 r1, 0x5dbcfec7; imm32 r2, 0x71245679; imm32 r3, 0x90060007; imm32 r4, 0xafbc4569; imm32 r5, 0xd235900b; imm32 r6, 0xc00ca00d; imm32 r7, 0x678ed00f; R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU); R1 = A1.w; R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU); R3 = A1.w; R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU); R5 = A1.w; R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU); R7 = A1.w; CHECKREG r0, 0xFF915ABD; CHECKREG r1, 0xFF910EEB; CHECKREG r2, 0x30375679; CHECKREG r3, 0x303725C1; CHECKREG r4, 0x5D604569; CHECKREG r5, 0x5D60D8AD; CHECKREG r6, 0x4382A00D; CHECKREG r7, 0x43823355; // The result accumulated in A1 MM=0, and stored to a reg half (MNOP) imm32 r0, 0x92005ABD; imm32 r1, 0x09300000; imm32 r2, 0x56749679; imm32 r3, 0x30A95000; imm32 r4, 0xa0009669; imm32 r5, 0x01000970; imm32 r6, 0xdf45609D; imm32 r7, 0x12345679; R0.H = ( A1 += R1.L * R0.L ) (M,TFU); R1 = A1.w; R2.H = ( A1 -= R2.L * R3.H ) (M,TFU); R3 = A1.w; R4.H = ( A1 = R4.H * R5.L ) (M,TFU); R5 = A1.w; R6.H = ( A1 -= R6.H * R7.H ) (M,TFU); R7 = A1.w; CHECKREG r0, 0x43825ABD; CHECKREG r1, 0x43823355; CHECKREG r2, 0x57919679; CHECKREG r3, 0x57912D74; CHECKREG r4, 0xFC769669; CHECKREG r5, 0xFC760000; CHECKREG r6, 0xFEC9609D; CHECKREG r7, 0xFEC9CBFC; pass
tactcomplabs/xbgas-binutils-gdb	5,343	sim/testsuite/bfin/c_ldst_st_p_d.s	//Original:/testcases/core/c_ldst_st_p_d/c_ldst_st_p_d.dsp // Spec Reference: c_ldst st_p_d # mach: bfin .include "testutils.inc" start imm32 r0, 0x0a231507; imm32 r1, 0x1b342618; imm32 r2, 0x2c453729; imm32 r3, 0x3d56483a; imm32 r4, 0x4e67594b; imm32 r5, 0x5f786a5c; imm32 r6, 0x60897b6d; imm32 r7, 0x719a8c7e; loadsym p5, DATA_ADDR_1; loadsym p1, DATA_ADDR_2; loadsym p2, DATA_ADDR_3; loadsym p4, DATA_ADDR_5; loadsym fp, DATA_ADDR_6; [ P5 ] = R0; [ P1 ] = R1; [ P2 ] = R2; [ P4 ] = R4; [ FP ] = R5; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x1B342618; CHECKREG r1, 0x2C453729; CHECKREG r3, 0x4E67594B; CHECKREG r4, 0x0A231507; CHECKREG r5, 0x5F786A5C; CHECKREG r7, 0x719A8C7E; imm32 r0, 0x1a231507; imm32 r1, 0x12342618; imm32 r2, 0x2c353729; imm32 r3, 0x3d54483a; imm32 r4, 0x4e67594b; imm32 r5, 0x5f78665c; imm32 r6, 0x60897b7d; imm32 r7, 0x719a8c78; [ P5 ] = R1; [ P1 ] = R2; [ P2 ] = R3; [ P4 ] = R5; [ FP ] = R6; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x2C353729; CHECKREG r1, 0x3D54483A; CHECKREG r3, 0x5F78665C; CHECKREG r4, 0x12342618; CHECKREG r5, 0x60897B7D; CHECKREG r7, 0x719A8C78; imm32 r0, 0x2a231507; imm32 r1, 0x12342618; imm32 r2, 0x2c253729; imm32 r3, 0x3d52483a; imm32 r4, 0x4e67294b; imm32 r5, 0x5f78625c; imm32 r6, 0x60897b2d; imm32 r7, 0x719a8c72; [ P5 ] = R2; [ P1 ] = R3; [ P2 ] = R4; [ P4 ] = R6; [ FP ] = R7; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x3D52483A; CHECKREG r1, 0x4E67294B; CHECKREG r3, 0x60897B2D; CHECKREG r4, 0x2C253729; CHECKREG r5, 0x719A8C72; CHECKREG r7, 0x719A8C72; imm32 r0, 0x3a231507; imm32 r1, 0x13342618; imm32 r2, 0x2c353729; imm32 r3, 0x3d53483a; imm32 r4, 0x4e67394b; imm32 r5, 0x5f78635c; imm32 r6, 0x60897b3d; imm32 r7, 0x719a8c73; [ P5 ] = R3; [ P1 ] = R4; [ P2 ] = R5; [ P4 ] = R7; [ FP ] = R0; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x4E67394B; CHECKREG r1, 0x5F78635C; CHECKREG r3, 0x719A8C73; CHECKREG r4, 0x3D53483A; CHECKREG r5, 0x3A231507; CHECKREG r7, 0x719A8C73; imm32 r0, 0x4a231507; imm32 r1, 0x14342618; imm32 r2, 0x2c453729; imm32 r3, 0x3d54483a; imm32 r4, 0x4e67494b; imm32 r5, 0x5f78645c; imm32 r6, 0x60897b4d; imm32 r7, 0x719a8c74; [ P5 ] = R4; [ P1 ] = R5; [ P2 ] = R6; [ P4 ] = R0; [ FP ] = R1; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x5F78645C; CHECKREG r1, 0x60897B4D; CHECKREG r3, 0x4A231507; CHECKREG r4, 0x4E67494B; CHECKREG r5, 0x14342618; CHECKREG r7, 0x719A8C74; imm32 r0, 0x5a231507; imm32 r1, 0x15342618; imm32 r2, 0x2c553729; imm32 r3, 0x3d55483a; imm32 r4, 0x4e67594b; imm32 r5, 0x5f78655c; imm32 r6, 0x60897b5d; imm32 r7, 0x719a8c75; [ P5 ] = R5; [ P1 ] = R6; [ P2 ] = R7; [ P4 ] = R1; [ FP ] = R2; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x60897B5D; CHECKREG r1, 0x719A8C75; CHECKREG r3, 0x15342618; CHECKREG r4, 0x5F78655C; CHECKREG r5, 0x2C553729; CHECKREG r7, 0x719A8C75; imm32 r0, 0x6a231507; imm32 r1, 0x16342618; imm32 r2, 0x2c653729; imm32 r3, 0x3d56483a; imm32 r4, 0x4e67694b; imm32 r5, 0x5f78665c; imm32 r6, 0x60897b6d; imm32 r7, 0x719a8c76; [ P5 ] = R6; [ P1 ] = R7; [ P2 ] = R0; [ P4 ] = R2; [ FP ] = R3; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x719A8C76; CHECKREG r1, 0x6A231507; CHECKREG r3, 0x2C653729; CHECKREG r4, 0x60897B6D; CHECKREG r5, 0x3D56483A; CHECKREG r7, 0x719A8C76; imm32 r0, 0x7a231507; imm32 r1, 0x17342618; imm32 r2, 0x2c753729; imm32 r3, 0x3d57483a; imm32 r4, 0x4e67794b; imm32 r5, 0x5f78675c; imm32 r6, 0x60897b7d; imm32 r7, 0x719a8c77; [ P5 ] = R7; [ P1 ] = R0; [ P2 ] = R1; [ P4 ] = R3; [ FP ] = R4; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x7A231507; CHECKREG r1, 0x17342618; CHECKREG r3, 0x3D57483A; CHECKREG r4, 0x719A8C77; CHECKREG r5, 0x4E67794B; CHECKREG r7, 0x719A8C77; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F DATA_ADDR_5: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F DATA_ADDR_6: .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF DATA_ADDR_7: .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	8,907	sim/testsuite/bfin/se_cc_kill.S	//Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp // Description: // Verify CC kill under the following condition: // // (1) CC = AZ killed in WB // (2) CC = AN killed in WB // (3) CC = AC killed in WB // (4) CC = AV0 killed in WB // (5) CC = AV1 killed in WB // (6) CC = AQ killed in WB # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // ---------------------------------------------------------------- // Include Files // ---------------------------------------------------------------- include(std.inc) include(selfcheck.inc) include(symtable.inc) include(mmrs.inc) // ---------------------------------------------------------------- // Defines // ---------------------------------------------------------------- #ifndef STACKSIZE #define STACKSIZE 0x00000010 #endif #ifndef ITABLE #define ITABLE CODE_ADDR_1 // #endif // ---------------------------------------------------------------- // Reset ISR // - set the processor operating modes // - initialize registers // - etc ... // ---------------------------------------------------------------- RST_ISR: // Initialize data registers //INIT_R_REGS(0); R7 = 0; R6 = 0; R5 = 0; R4 = 0; R3 = 0; R2 = 0; R1 = 0; R0 = 0; // Initialize pointer registers INIT_P_REGS(0); // Initialize address registers INIT_I_REGS(0); INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); // Initialize the address of the checkreg data segment // ** THIS IS NEEDED WHENEVER CHECKREG IS USED ** CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); // Inhibit events during MMR writes CLI R1; // Setup user stack LD32_LABEL(sp, USTACK); USP = SP; // Setup kernel stack LD32_LABEL(sp, KSTACK); // Setup frame pointer FP = SP; // Setup event vector table LD32(p0, EVT0); LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) [ P0 ++ ] = R0; LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) [ P0 ++ ] = R0; LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) [ P0 ++ ] = R0; LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // EVT4 not used LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) [ P0 ++ ] = R0; LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) [ P0 ++ ] = R0; LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler [ P0 ++ ] = R0; // Set the EVT_OVERRIDE MMR LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; // Disable L1 data cache WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); // Mask interrupts (*) R1 = -1; // Wait for MMR writes to finish CSYNC; // Re-enable events STI R1; // Reset loop counters to deterministic values R0 = 0 (Z); LT0 = R0; LB0 = R0; LC0 = R0; LT1 = R0; LB1 = R0; LC1 = R0; // Reset other internal regs ASTAT = R0; SYSCFG = R0; RETS = R0; // Setup the test to run in USER mode LD32_LABEL(r0, USER_CODE); RETI = R0; // Setup the test to run in SUPERVISOR mode // Comment the following line for a USER mode test JUMP.S SUPERVISOR_CODE; RTI; SUPERVISOR_CODE: // Load IVG15 general handler (Int15) with MAIN_CODE LD32_LABEL(p1, MAIN_CODE); LD32(p0, EVT15); CLI R1; [ P0 ] = P1; CSYNC; STI R1; // Take Int15 which branch to MAIN_CODE after RTI RAISE 15; RTI; USER_CODE: // Setup the stack pointer and the frame pointer LD32_LABEL(sp, USTACK); FP = SP; JUMP.S MAIN_CODE; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // ISR Table // ---------------------------------------------------------------- // ---------------------------------------------------------------- // EMU ISR // ---------------------------------------------------------------- EMU_ISR : RTE; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // NMI ISR // ---------------------------------------------------------------- NMI_ISR : RTN; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // EXC ISR // ---------------------------------------------------------------- EXC_ISR : RTX; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // HWE ISR // ---------------------------------------------------------------- HWE_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // TMR ISR // ---------------------------------------------------------------- TMR_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV7 ISR // ---------------------------------------------------------------- IGV7_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV8 ISR // ---------------------------------------------------------------- IGV8_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV9 ISR // ---------------------------------------------------------------- IGV9_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV10 ISR // ---------------------------------------------------------------- IGV10_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV11 ISR // ---------------------------------------------------------------- IGV11_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV12 ISR // ---------------------------------------------------------------- IGV12_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV13 ISR // ---------------------------------------------------------------- IGV13_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV14 ISR // ---------------------------------------------------------------- IGV14_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // IGV15 ISR // ---------------------------------------------------------------- IGV15_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF // ---------------------------------------------------------------- // Main Code // ---------------------------------------------------------------- MAIN_CODE: // Enable interrupts in SUPERVISOR mode // Comment the following line for a USER mode test [ -- SP ] = RETI; // Start of the program code // Verify CC kill under the following condition: // (1) CC = AZ killed in WB CC = R2 < R3; EXCPT 3; CC = AZ; // (2) CC = AN killed in WB CC = R2 == R3; EXCPT 3; CC = AN; // (3) CC = AC killed in WB CC = R2 < R3; EXCPT 3; CC = AC0; // (4) CC = AV0 killed in WB CC = R2 == R3; EXCPT 3; CC = AV0; // (5) CC = AV1 killed in WB CC = R2 == R3; EXCPT 3; CC = AV1; // (6) CC = AQ killed in WB CC = R2 == R3; EXCPT 3; CC = AQ; END: dbg_pass; // ---------------------------------------------------------------- // Data Segment // - define kernel and user stacks // ---------------------------------------------------------------- .data DATA: .space (STACKSIZE); .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	1,470	sim/testsuite/bfin/c_ldimmhalf_h_dr.s	//Original:/testcases/core/c_ldimmhalf_h_dr/c_ldimmhalf_h_dr.dsp // Spec Reference: ldimmhalf h dreg # mach: bfin .include "testutils.inc" start INIT_R_REGS -1; // test Dreg R0.H = 0x0000; R1.H = 0x0002; R2.H = 0x0004; R3.H = 0x0006; R4.H = 0x0008; R5.H = 0x000a; R6.H = 0x000c; R7.H = 0x000e; CHECKREG r0, 0x0000ffff; CHECKREG r1, 0x0002ffff; CHECKREG r2, 0x0004ffff; CHECKREG r3, 0x0006ffff; CHECKREG r4, 0x0008ffff; CHECKREG r5, 0x000affff; CHECKREG r6, 0x000cffff; CHECKREG r7, 0x000effff; R0.H = 0x0000; R1.H = 0x0020; R2.H = 0x0040; R3.H = 0x0060; R4.H = 0x0080; R5.H = 0x00a0; R6.H = 0x00c0; R7.H = 0x00e0; CHECKREG r0, 0x0000ffff; CHECKREG r1, 0x0020ffff; CHECKREG r2, 0x0040ffff; CHECKREG r3, 0x0060ffff; CHECKREG r4, 0x0080ffff; CHECKREG r5, 0x00a0ffff; CHECKREG r6, 0x00c0ffff; CHECKREG r7, 0x00e0ffff; R0.H = 0x0000; R1.H = 0x0200; R2.H = 0x0400; R3.H = 0x0600; R4.H = 0x0800; R5.H = 0x0a00; R6.H = 0x0c00; R7.H = 0x0e00; CHECKREG r0, 0x0000ffff; CHECKREG r1, 0x0200ffff; CHECKREG r2, 0x0400ffff; CHECKREG r3, 0x0600ffff; CHECKREG r4, 0x0800ffff; CHECKREG r5, 0x0a00ffff; CHECKREG r6, 0x0c00ffff; CHECKREG r7, 0x0e00ffff; R0.H = 0x0000; R1.H = 0x2000; R2.H = 0x4000; R3.H = 0x6000; R4.H = 0x8000; R5.H = 0xa000; R6.H = 0xc000; R7.H = 0xe000; CHECKREG r0, 0x0000ffff; CHECKREG r1, 0x2000ffff; CHECKREG r2, 0x4000ffff; CHECKREG r3, 0x6000ffff; CHECKREG r4, 0x8000ffff; CHECKREG r5, 0xa000ffff; CHECKREG r6, 0xc000ffff; CHECKREG r7, 0xe000ffff; pass
tactcomplabs/xbgas-binutils-gdb	5,448	sim/testsuite/bfin/c_ldst_st_p_d_b.s	//Original:/testcases/core/c_ldst_st_p_d_b/c_ldst_st_p_d_b.dsp // Spec Reference: c_ldst st_p d b # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; imm32 r0, 0x0a231507; imm32 r1, 0x1b342618; imm32 r2, 0x2c453729; imm32 r3, 0x3d56483a; imm32 r4, 0x4e67594b; imm32 r5, 0x5f786a5c; imm32 r6, 0x60897b6d; imm32 r7, 0x719a8c7e; loadsym p5, DATA_ADDR_1; loadsym p1, DATA_ADDR_2; loadsym p2, DATA_ADDR_3; loadsym p4, DATA_ADDR_5; loadsym fp, DATA_ADDR_6; B [ P5 ] = R0; B [ P1 ] = R1; B [ P2 ] = R2; B [ P4 ] = R4; B [ FP ] = R5; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x20212218; CHECKREG r1, 0x40414229; CHECKREG r3, 0x8081824B; CHECKREG r4, 0x00010207; CHECKREG r5, 0xA0A1A25C; CHECKREG r7, 0x719A8C7E; imm32 r0, 0x1a231507; imm32 r1, 0x11342618; imm32 r2, 0x2c153729; imm32 r3, 0x3d51483a; imm32 r4, 0x4e67194b; imm32 r5, 0x5f78615c; imm32 r6, 0x60897b1d; imm32 r7, 0x719a8c71; B [ P5 ] = R1; B [ P1 ] = R2; B [ P2 ] = R3; B [ P4 ] = R5; B [ FP ] = R6; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x20212229; CHECKREG r1, 0x4041423A; CHECKREG r3, 0x8081825C; CHECKREG r4, 0x00010218; CHECKREG r5, 0xA0A1A21D; CHECKREG r7, 0x719A8C71; imm32 r0, 0x2a231507; imm32 r1, 0x12342618; imm32 r2, 0x2c253729; imm32 r3, 0x3d52483a; imm32 r4, 0x4e67294b; imm32 r5, 0x5f78625c; imm32 r6, 0x60897b2d; imm32 r7, 0x719a8c72; B [ P5 ] = R2; B [ P1 ] = R3; B [ P2 ] = R4; B [ P4 ] = R6; B [ FP ] = R7; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x2021223A; CHECKREG r1, 0x4041424B; CHECKREG r2, 0x2c253729; CHECKREG r3, 0x8081822D; CHECKREG r4, 0x00010229; CHECKREG r5, 0xA0A1A272; CHECKREG r7, 0x719A8C72; imm32 r0, 0x3a231507; imm32 r1, 0x13342618; imm32 r3, 0x3d53483a; imm32 r4, 0x4e67394b; imm32 r5, 0x5f78635c; imm32 r6, 0x60897b3d; imm32 r7, 0x719a8c73; B [ P5 ] = R3; B [ P1 ] = R4; B [ P2 ] = R5; B [ P4 ] = R7; B [ FP ] = R0; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x2021224B; CHECKREG r1, 0x4041425C; CHECKREG r3, 0x80818273; CHECKREG r4, 0x0001023A; CHECKREG r5, 0xA0A1A207; CHECKREG r7, 0x719A8C73; imm32 r0, 0x4a231507; imm32 r1, 0x14342618; imm32 r2, 0x2c453729; imm32 r3, 0x3d54483a; imm32 r4, 0x4e67494b; imm32 r5, 0x5f78645c; imm32 r6, 0x60897b4d; imm32 r7, 0x719a8c74; B [ P5 ] = R4; B [ P1 ] = R5; B [ P2 ] = R6; B [ P4 ] = R0; B [ FP ] = R1; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x2021225C; CHECKREG r1, 0x4041424D; CHECKREG r3, 0x80818207; CHECKREG r4, 0x0001024B; CHECKREG r5, 0xA0A1A218; CHECKREG r7, 0x719A8C74; imm32 r0, 0x5a231507; imm32 r1, 0x15342618; imm32 r2, 0x2c553729; imm32 r3, 0x3d55483a; imm32 r4, 0x4e67594b; imm32 r5, 0x5f78655c; imm32 r6, 0x60897b5d; imm32 r7, 0x719a8c75; B [ P5 ] = R5; B [ P1 ] = R6; B [ P2 ] = R7; B [ P4 ] = R1; B [ FP ] = R2; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x2021225D; CHECKREG r1, 0x40414275; CHECKREG r3, 0x80818218; CHECKREG r4, 0x0001025C; CHECKREG r5, 0xA0A1A229; CHECKREG r7, 0x719A8C75; imm32 r0, 0x6a231507; imm32 r1, 0x16342618; imm32 r2, 0x2c653729; imm32 r3, 0x3d56483a; imm32 r4, 0x4e67694b; imm32 r5, 0x5f78665c; imm32 r6, 0x60897b6d; imm32 r7, 0x719a8c76; B [ P5 ] = R6; B [ P1 ] = R7; B [ P2 ] = R0; B [ P4 ] = R2; B [ FP ] = R3; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x20212276; CHECKREG r1, 0x40414207; CHECKREG r3, 0x80818229; CHECKREG r4, 0x0001026D; CHECKREG r5, 0xA0A1A23A; CHECKREG r7, 0x719A8C76; imm32 r0, 0x7a231507; imm32 r1, 0x17342618; imm32 r2, 0x2c753729; imm32 r3, 0x3d57483a; imm32 r4, 0x4e67794b; imm32 r5, 0x5f78675c; imm32 r6, 0x60897b7d; imm32 r7, 0x719a8c77; B [ P5 ] = R7; B [ P1 ] = R0; B [ P2 ] = R1; B [ P4 ] = R3; B [ FP ] = R4; R0 = [ P1 ]; R1 = [ P2 ]; R3 = [ P4 ]; R4 = [ P5 ]; R5 = [ FP ]; CHECKREG r0, 0x20212207; CHECKREG r1, 0x40414218; CHECKREG r3, 0x8081823A; CHECKREG r4, 0x00010277; CHECKREG r5, 0xA0A1A24B; CHECKREG r7, 0x719A8C77; pass // Pre-load memory witb known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F DATA_ADDR_5: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F DATA_ADDR_6: .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF DATA_ADDR_7: .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	2,790	sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s	//Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp // Spec Reference: compi2opd dregs += imm7 negative # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; R0 += 0; R1 += -1; R2 += -2; R3 += -3; R4 += -4; R5 += -5; R6 += -6; R7 += -7; CHECKREG r0, 0x00000000; CHECKREG r1, 0xFFFFFFFF; CHECKREG r2, 0xFFFFFFFE; CHECKREG r3, 0xFFFFFFFD; CHECKREG r4, 0xFFFFFFFC; CHECKREG r5, 0xFFFFFFFB; CHECKREG r6, 0xFFFFFFFA; CHECKREG r7, 0xFFFFFFF9; R0 += -8; R1 += -9; R2 += -10; R3 += -11; R4 += -12; R5 += -13; R6 += -14; R7 += -15; CHECKREG r0, 0xFFFFFFF8; CHECKREG r1, 0xFFFFFFF6; CHECKREG r2, 0xFFFFFFF4; CHECKREG r3, 0xFFFFFFF2; CHECKREG r4, 0xFFFFFFF0; CHECKREG r5, 0xFFFFFFEE; CHECKREG r6, 0xFFFFFFEC; CHECKREG r7, 0xFFFFFFEA; R0 += -16; R1 += -17; R2 += -18; R3 += -19; R4 += -20; R5 += -21; R6 += -22; R7 += -23; CHECKREG r0, 0xFFFFFFE8; CHECKREG r1, 0xFFFFFFE5; CHECKREG r2, 0xFFFFFFE2; CHECKREG r3, 0xFFFFFFDF; CHECKREG r4, 0xFFFFFFDC; CHECKREG r5, 0xFFFFFFD9; CHECKREG r6, 0xFFFFFFD6; CHECKREG r7, 0xFFFFFFD3; R0 += -24; R1 += -25; R2 += -26; R3 += -27; R4 += -28; R5 += -29; R6 += -30; R7 += -31; CHECKREG r0, 0xFFFFFFD0; CHECKREG r1, 0xFFFFFFCC; CHECKREG r2, 0xFFFFFFC8; CHECKREG r3, 0xFFFFFFC4; CHECKREG r4, 0xFFFFFFC0; CHECKREG r5, 0xFFFFFFBC; CHECKREG r6, 0xFFFFFFB8; CHECKREG r7, 0xFFFFFFB4; R0 += -32; R1 += -33; R2 += -34; R3 += -35; R4 += -36; R5 += -37; R6 += -38; R7 += -39; CHECKREG r0, 0xFFFFFFB0; CHECKREG r1, 0xFFFFFFAB; CHECKREG r2, 0xFFFFFFA6; CHECKREG r3, 0xFFFFFFA1; CHECKREG r4, 0xFFFFFF9C; CHECKREG r5, 0xFFFFFF97; CHECKREG r6, 0xFFFFFF92; CHECKREG r7, 0xFFFFFF8D; R0 += -40; R1 += -41; R2 += -42; R3 += -43; R4 += -44; R5 += -45; R6 += -46; R7 += -47; CHECKREG r0, 0xFFFFFF88; CHECKREG r1, 0xFFFFFF82; CHECKREG r2, 0xFFFFFF7C; CHECKREG r3, 0xFFFFFF76; CHECKREG r4, 0xFFFFFF70; CHECKREG r5, 0xFFFFFF6A; CHECKREG r6, 0xFFFFFF64; CHECKREG r7, 0xFFFFFF5E; R0 += -48; R1 += -49; R2 += -50; R3 += -51; R4 += -52; R5 += -53; R6 += -54; R7 += -55; CHECKREG r0, 0xFFFFFF58; CHECKREG r1, 0xFFFFFF51; CHECKREG r2, 0xFFFFFF4A; CHECKREG r3, 0xFFFFFF43; CHECKREG r4, 0xFFFFFF3C; CHECKREG r5, 0xFFFFFF35; CHECKREG r6, 0xFFFFFF2E; CHECKREG r7, 0xFFFFFF27; R0 += -56; R1 += -57; R2 += -58; R3 += -59; R4 += -60; R5 += -61; R6 += -62; R7 += -63; CHECKREG r0, 0xFFFFFF20; CHECKREG r1, 0xFFFFFF18; CHECKREG r2, 0xFFFFFF10; CHECKREG r3, 0xFFFFFF08; CHECKREG r4, 0xFFFFFF00; CHECKREG r5, 0xFFFFFEF8; CHECKREG r6, 0xFFFFFEF0; CHECKREG r7, 0xFFFFFEE8; R0 += -64; R1 += -64; R2 += -64; R3 += -64; R4 += -64; R5 += -64; R6 += -64; R7 += -64; CHECKREG r0, 0xFFFFFEE0; CHECKREG r1, 0xFFFFFED8; CHECKREG r2, 0xFFFFFED0; CHECKREG r3, 0xFFFFFEC8; CHECKREG r4, 0xFFFFFEC0; CHECKREG r5, 0xFFFFFEB8; CHECKREG r6, 0xFFFFFEB0; CHECKREG r7, 0xFFFFFEA8; pass
tactcomplabs/xbgas-binutils-gdb	8,716	sim/testsuite/bfin/c_seq_wb_rti_lsmmrj_mvp.S	//Original:/proj/frio/dv/testcases/core/c_seq_wb_rti_lsmmrj_mvp/c_seq_wb_rti_lsmmrj_mvp.dsp // Spec Reference: sequencer:wb ( rti ldst mmr jump regmv pushpopmultiple) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE DATA_ADDR_1 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK CSYNC; DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! // PUSH LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 //LD32(p2, DATA_ADDR_1); loadsym P2, DATA; LD32(p3, 0xab5fd490); LD32(p4, 0xa581bd94); LD32(r2, 0x14789232); [ P1 ] = R2; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; [ -- SP ] = ( R7:0 ); RAISE 2; // RTN R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL1; P3 = R7; R4 = P3; [ -- SP ] = ( R7:0 ); R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; LABEL1: RAISE 5; // RTI R2 = [ P2 ++ ]; P4 = R6; R3 = P4; [ -- SP ] = ( R7:0 ); R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; // wrt-rd EVT5 = 0xFFE02034 LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 RAISE 6; // RTI R4 = [ P2 ++ ]; R6 = [ P1 ]; JUMP.S LABEL2; P3 = R3; R5 = P3; [ -- SP ] = ( R7:0 ); // POP R0 = 0x00; R1 = 0x00; R2 = 0x00; R3 = 0x00; R4 = 0x00; R5 = 0x00; R6 = 0x00; R7 = 0x00; LABEL2: CSYNC; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x00000023); CHECKREG(r3, 0x00000024); CHECKREG(r4, 0x08090A0B); CHECKREG(r5, 0x00000026); CHECKREG(r6, 0x14789232); RAISE 7; // RTI R0 = [ P2 ++ ]; R1 = [ P1 ]; P4 = R4; R2 = P4; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00010203); CHECKREG(r1, 0x14789232); CHECKREG(r2, 0x04050607); CHECKREG(r3, 0x00000007); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); // wrt-rd EVT13 = 0xFFE02034 LD32(p1, 0xFFE02034); RAISE 8; // RTI R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; //CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped //CHECKREG(r1, 0x000000b2); // so they cannot appear here //CHECKREG(r2, 0x000000c3); //CHECKREG(r3, 0x000000d4); //CHECKREG(r4, 0x000000e5); //CHECKREG(r5, 0x000000f6); //CHECKREG(r6, 0x00000017); //CHECKREG(r7, 0x00000028); R0 = 12; R1 = 13; R2 = 14; R3 = 15; R4 = 16; R5 = 17; R6 = 18; R7 = 19; LABEL3: CSYNC; CHECKREG(r0, 0x10111213); CHECKREG(r1, 0x14789232); RAISE 9; // RTI P3 = R6; R7 = P3; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000003); CHECKREG(r3, 0x00000004); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG(r0, 0x00000006); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000002); CHECKREG(r3, 0x00000002); END: dbg_pass; // End the test //***************************************************************** // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 I0 += 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 I1 += 2; RTI; THANDLE: // Timer Handler 6 I2 += 2; RTI; I7HANDLE: // IVG 7 Handler I3 += 2; RTI; // ******* R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; // ******* I8HANDLE: // IVG 8 Handler I0 += 2; RTI; I9HANDLE: // IVG 9 Handler I0 += 2; RTI; // ******* R0 = [ P2 ++ ]; R1 = [ P1 ]; JUMP.S LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; // ********* I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .section MEM_DATA_ADDR_1,"aw" DATA: // .space (0x10); .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK: .section MEM_DATA_ADDR_2,"aw" .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0
tactcomplabs/xbgas-binutils-gdb	1,478	sim/testsuite/bfin/c_pushpopmultiple_preg.s	//Original:/testcases/core/c_pushpopmultiple_preg/c_pushpopmultiple_preg.dsp // Spec Reference: pushpopmultiple preg # mach: bfin .include "testutils.inc" start FP = SP; imm32 r0, 0x00000000; ASTAT = r0; P1 = 0xa1 (X); P2 = 0xa2 (X); P3 = 0xa3 (X); P4 = 0xa4 (X); P5 = 0xa5 (X); [ -- SP ] = ( P5:1 ); P1 = 0; P2 = 0; P3 = 0; P4 = 0; P5 = 0; ( P5:1 ) = [ SP ++ ]; CHECKREG p1, 0x000000a1; CHECKREG p2, 0x000000a2; CHECKREG p3, 0x000000a3; CHECKREG p4, 0x000000a4; CHECKREG p5, 0x000000a5; P2 = 0xb2 (X); P3 = 0xb3 (X); P4 = 0xb4 (X); P5 = 0xb5 (X); [ -- SP ] = ( P5:2 ); P2 = 0; P3 = 0; P4 = 0; P5 = 0; ( P5:2 ) = [ SP ++ ]; CHECKREG p1, 0x000000a1; CHECKREG p2, 0x000000b2; CHECKREG p3, 0x000000b3; CHECKREG p4, 0x000000b4; CHECKREG p5, 0x000000b5; P3 = 0xc3 (X); P4 = 0xc4 (X); P5 = 0xc5 (X); [ -- SP ] = ( P5:3 ); P3 = 0; P4 = 0; P5 = 0; ( P5:3 ) = [ SP ++ ]; CHECKREG p1, 0x000000a1; CHECKREG p2, 0x000000b2; CHECKREG p3, 0x000000c3; CHECKREG p4, 0x000000c4; CHECKREG p5, 0x000000c5; P4 = 0xd4 (X); P5 = 0xd5 (X); [ -- SP ] = ( P5:4 ); P4 = 0; P5 = 0; ( P5:4 ) = [ SP ++ ]; CHECKREG p1, 0x000000a1; CHECKREG p2, 0x000000b2; CHECKREG p3, 0x000000c3; CHECKREG p4, 0x000000d4; CHECKREG p5, 0x000000d5; P5 = 0xe5 (X); [ -- SP ] = ( P5:5 ); P5 = 0; ( P5:5 ) = [ SP ++ ]; CHECKREG p1, 0x000000a1; CHECKREG p2, 0x000000b2; CHECKREG p3, 0x000000c3; CHECKREG p4, 0x000000d4; CHECKREG p5, 0x000000e5; pass
tactcomplabs/xbgas-binutils-gdb	3,385	sim/testsuite/bfin/c_dsp32shiftim_amix.s	//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp # mach: bfin .include "testutils.inc" start // Spec Reference: dsp32shiftimm ashift: mix imm32 r4, 0x00000000; imm32 r5, 0x00000000; imm32 r6, 0x00000000; imm32 r7, 0x00000000; // Ashift : positive data, count (+)=left (half reg) imm32 r0, 0x00010001; imm32 r1, 1; imm32 r2, 0x00020002; imm32 r3, 2; R4.H = R0.H << 1; R4.L = R0.L << 1; /* r4 = 0x00020002 / R5.H = R2.H << 2; R5.L = R2.L << 2; / r5 = 0x00080008 / R6 = R0 << 1 (V); / r6 = 0x00020002 / R7 = R2 << 2 (V); / r7 = 0x00080008 / CHECKREG r4, 0x00020002; CHECKREG r5, 0x00080008; CHECKREG r6, 0x00020002; CHECKREG r7, 0x00080008; imm32 r1, 3; imm32 r3, 4; R6 = R0 << 3; / r6 = 0x00080010 / R7 = R2 << 4; CHECKREG r6, 0x00080008; / r7 = 0x00100010 / CHECKREG r7, 0x00200020; A0 = 0; A0.L = R0.L; A0.H = R0.H; A0 = A0 << 3; / a0 = 0x00080008 / R5 = A0.w; / r5 = 0x00080008 / CHECKREG r5, 0x00080008; imm32 r4, 0x30000003; imm32 r1, 1; R5 = R4 << 1; / r5 = 0x60000006 / imm32 r1, 2; R6 = ASHIFT R4 BY R1.L; / r5 = 0xc000000c like LSHIFT / CHECKREG r5, 0x60000006; CHECKREG r6, 0xc000000c; // Ashift : count (-)=right (half reg) imm32 r0, 0x10001000; imm32 r1, -1; imm32 r2, 0x10001000; imm32 r3, -2; R4.H = R0.H >>> 1; R4.L = R0.L >>> 1; / r4 = 0x08000800 / R5.H = R2.H >>> 2; R5.L = R2.L >>> 2; / r4 = 0x04000400 / R6 = R0 >>> 1 (V); / r4 = 0x08000800 / R7 = R2 >>> 2 (V); / r4 = 0x04000400 / CHECKREG r4, 0x08000800; CHECKREG r5, 0x04000400; CHECKREG r6, 0x08000800; CHECKREG r7, 0x04000400; // Ashift : (full reg) imm32 r1, -3; imm32 r3, -4; R6 = R0 >>> 3; / r6 = 0x02000200 / R7 = R2 >>> 4; / r7 = 0x01000100 / CHECKREG r6, 0x02000200; CHECKREG r7, 0x01000100; // NEGATIVE // Ashift : NEGATIVE data, count (+)=left (half reg) imm32 r0, 0xc00f800f; imm32 r1, 1; imm32 r2, 0xe00fe00f; imm32 r3, 2; R4.H = R0.H << 1; R4.L = R0.L << 1 (S); / r4 = 0x801e801e / R5.H = R2.H << 2; R5.L = R2.L << 2; / r4 = 0x803c803c / CHECKREG r4, 0x801e8000; CHECKREG r5, 0x803c803c; imm32 r0, 0xc80fe00f; imm32 r2, 0xe40fe00f; imm32 r1, 4; imm32 r3, 5; R6 = R0 << 4; / r6 = 0x80fe00f0 / R7 = R2 << 5; / r7 = 0x81fc01e0 / CHECKREG r6, 0x80fe00f0; CHECKREG r7, 0x81fc01e0; imm32 r0, 0xf80fe00f; imm32 r2, 0xfc0fe00f; R6 = R0 << 4 (S); / r6 = 0x80fe00f0 / R7 = R2 << 5 (S); / r7 = 0x81fc01e0 / CHECKREG r6, 0x80fe00f0; CHECKREG r7, 0x81fc01e0; imm32 r0, 0xc80fe00f; imm32 r2, 0xe40fe00f; R6 = R0 << 4 (S); / r6 = 0x80000000 zero bubble tru MSB / R7 = R2 << 5 (S); / r7 = 0x80000000 / CHECKREG r6, 0x80000000; CHECKREG r7, 0x80000000; imm32 r0, 0xFFFFFFF4; imm32 r2, 0xFFF00001; R6 = R0 << 31 (S); / r6 = 0x80000000 / R7 = R2 << 31 (S); / r7 = 0x80000000 / CHECKREG r6, 0x80000000; CHECKREG r7, 0x80000000; // Ashift : NEGATIVE data, count (-)=right (half reg) Working ok imm32 r0, 0x80f080f0; imm32 r1, -1; imm32 r2, 0x80f080f0; imm32 r3, -2; R4.H = R0.H >>> 1; R4.L = R0.L >>> 1; / r4 = 0xc078c078 / R5.H = R2.H >>> 2; R5.L = R2.L >>> 2; / r4 = 0xe03ce03c / CHECKREG r4, 0xc078c078; CHECKREG r5, 0xe03ce03c; R6 = R0 >>> 1 (V); / r6 = 0xc078c078 / R7 = R2 >>> 2 (V); / r7 = 0xe03ce03c / CHECKREG r6, 0xc078c078; CHECKREG r7, 0xe03ce03c; imm32 r1, -3; imm32 r3, -4; R6 = R0 >>> 3; / r6 = 0xf01e101e / R7 = R2 >>> 4; / r7 = 0xf80f080f */ CHECKREG r6, 0xf01e101e; CHECKREG r7, 0xf80f080f; pass
tactcomplabs/xbgas-binutils-gdb	5,459	sim/testsuite/bfin/c_ldst_ld_d_p_xb.s	//Original:/testcases/core/c_ldst_ld_d_p_xb/c_ldst_ld_d_p_xb.dsp // Spec Reference: c_ldst ld d [p] xb # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; loadsym p1, DATA_ADDR_1; loadsym p2, DATA_ADDR_2; loadsym p4, DATA_ADDR_4; loadsym p5, DATA_ADDR_5; loadsym fp, DATA_ADDR_6; // load 8 bits from memory & sign extend into 32-bit reg R4 = B [ P5 ] (X); R5 = B [ FP ] (X); R7 = B [ P1 ] (X); R0 = B [ P2 ] (X); R2 = B [ P4 ] (X); CHECKREG r0, 0x00000023; CHECKREG r2, 0x00000063; CHECKREG r3, 0x00000000; CHECKREG r4, 0xFFFFFF83; CHECKREG r5, 0x00000003; CHECKREG r7, 0x00000003; R5 = B [ FP ] (X); R7 = B [ P1 ] (X); R0 = B [ P2 ] (X); R2 = B [ P4 ] (X); R3 = B [ P5 ] (X); CHECKREG r0, 0x00000023; CHECKREG r2, 0x00000063; CHECKREG r3, 0xFFFFFF83; CHECKREG r4, 0xFFFFFF83; CHECKREG r5, 0x00000003; CHECKREG r7, 0x00000003; R7 = B [ P1 ] (X); R0 = B [ P2 ] (X); R2 = B [ P4 ] (X); R3 = B [ P5 ] (X); R4 = B [ FP ] (X); CHECKREG r0, 0x00000023; CHECKREG r2, 0x00000063; CHECKREG r3, 0xFFFFFF83; CHECKREG r4, 0x00000003; CHECKREG r5, 0x00000003; CHECKREG r7, 0x00000003; R7 = B [ P1 ] (X); R0 = B [ P2 ] (X); R2 = B [ P4 ] (X); R3 = B [ P5 ] (X); R4 = B [ FP ] (X); CHECKREG r0, 0x00000023; CHECKREG r2, 0x00000063; CHECKREG r3, 0xFFFFFF83; CHECKREG r4, 0x00000003; CHECKREG r7, 0x00000003; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B DATA_ADDR_5: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0x0F101213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0xBC0DBE21 .dd 0xBC1DBE22 .dd 0xBC2DBE23 .dd 0xBC3DBE24 .dd 0xBC4DBE65 .dd 0xBC5DBE27 .dd 0xBC6DBE28 .dd 0xBC7DBE29 .dd 0xBC8DBE2F .dd 0xBC9DBE20 .dd 0xBCADBE21 .dd 0xBCBDBE2F .dd 0xBCCDBE23 .dd 0xBCDDBE24 .dd 0xBCFDBE25 .dd 0xC455565C .dd 0xC859606C .dd 0xC263646C .dd 0xC667686C .dd 0xCC0DBE2C DATA_ADDR_6: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F DATA_ADDR_7: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	3,054	sim/testsuite/bfin/c_pushpopmultiple_dreg.s	//Original:/testcases/core/c_pushpopmultiple_dreg/c_pushpopmultiple_dreg.dsp // Spec Reference: pushpopmultiple dreg # mach: bfin .include "testutils.inc" start FP = SP; imm32 r0, 0x00000000; ASTAT = r0; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; [ -- SP ] = ( R7:0 ); R0 = 0; R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; ( R7:0 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000002; CHECKREG r2, 0x00000003; CHECKREG r3, 0x00000004; CHECKREG r4, 0x00000005; CHECKREG r5, 0x00000006; CHECKREG r6, 0x00000007; CHECKREG r7, 0x00000008; R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; [ -- SP ] = ( R7:1 ); R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; ( R7:1 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000013; CHECKREG r3, 0x00000014; CHECKREG r4, 0x00000015; CHECKREG r5, 0x00000016; CHECKREG r6, 0x00000017; CHECKREG r7, 0x00000018; R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; [ -- SP ] = ( R7:2 ); R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; ( R7:2 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000023; CHECKREG r3, 0x00000024; CHECKREG r4, 0x00000025; CHECKREG r5, 0x00000026; CHECKREG r6, 0x00000027; CHECKREG r7, 0x00000028; R3 = 0x34; R4 = 0x35; R5 = 0x36; R6 = 0x37; R7 = 0x38; [ -- SP ] = ( R7:3 ); R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0; ( R7:3 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000023; CHECKREG r3, 0x00000034; CHECKREG r4, 0x00000035; CHECKREG r5, 0x00000036; CHECKREG r6, 0x00000037; CHECKREG r7, 0x00000038; R4 = 0x45 (X); R5 = 0x46 (X); R6 = 0x47 (X); R7 = 0x48 (X); [ -- SP ] = ( R7:4 ); R4 = 0; R5 = 0; R6 = 0; R7 = 0; ( R7:4 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000023; CHECKREG r3, 0x00000034; CHECKREG r4, 0x00000045; CHECKREG r5, 0x00000046; CHECKREG r6, 0x00000047; CHECKREG r7, 0x00000048; R5 = 0x56 (X); R6 = 0x57 (X); R7 = 0x58 (X); [ -- SP ] = ( R7:5 ); R5 = 0; R6 = 0; R7 = 0; ( R7:5 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000023; CHECKREG r3, 0x00000034; CHECKREG r4, 0x00000045; CHECKREG r5, 0x00000056; CHECKREG r6, 0x00000057; CHECKREG r7, 0x00000058; R6 = 0x67 (X); R7 = 0x68 (X); [ -- SP ] = ( R7:6 ); R6 = 0; R7 = 0; ( R7:6 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000023; CHECKREG r3, 0x00000034; CHECKREG r4, 0x00000045; CHECKREG r5, 0x00000056; CHECKREG r6, 0x00000067; CHECKREG r7, 0x00000068; R7 = 0x78 (X); [ -- SP ] = ( R7:7 ); R7 = 0; ( R7:7 ) = [ SP ++ ]; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00000012; CHECKREG r2, 0x00000023; CHECKREG r3, 0x00000034; CHECKREG r4, 0x00000045; CHECKREG r5, 0x00000056; CHECKREG r6, 0x00000067; CHECKREG r7, 0x00000078; pass
tactcomplabs/xbgas-binutils-gdb	11,958	sim/testsuite/bfin/dbg_brprd_ntkn_src_kill.S	//Original:/proj/frio/dv/testcases/debug/dbg_brprd_ntkn_src_kill/dbg_brprd_ntkn_src_kill.dsp // Description: This test checks that the trace buffer keeps track of a // branch source instruction that is predicted but not taken getting killed // at each stage in the pipe. The test consists of 8 instances of an EXCPT // instruction followed by 0 to 7 NOPs and a BRF instruction (and bp), with // the trace buffer enabled. # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start ///////////////////////////////////////////////////////////////////////////// ///////////////////////// Include Files ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// include(std.inc) include(selfcheck.inc) include(symtable.inc) include(mmrs.inc) ///////////////////////////////////////////////////////////////////////////// ///////////////////////// Defines ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// #ifndef USER_CODE_SPACE #define USER_CODE_SPACE CODE_ADDR_1 // #endif #ifndef STACKSIZE #define STACKSIZE 0x00000020 #endif #ifndef ITABLE #define ITABLE CODE_ADDR_2 // #endif ///////////////////////////////////////////////////////////////////////////// ///////////////////////// RESET ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// RST_ISR : // Initialize Dregs INIT_R_REGS(0); // Initialize Pregs INIT_P_REGS(0); // Initialize ILBM Registers INIT_I_REGS(0); INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); // Initialize the Address of the Checkreg data segment // ** THIS IS NEEDED WHENEVER CHECKREG IS USED ** CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); // Setup User Stack LD32_LABEL(sp, USTACK); USP = SP; // Setup Kernel Stack LD32_LABEL(sp, KSTACK); // Setup Frame Pointer FP = SP; // Setup Event Vector Table LD32(p0, EVT0); LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler [ P0 ++ ] = R0; // Setup the EVT_OVERRIDE MMR R0 = 0; LD32(p0, EVT_OVERRIDE); [ P0 ] = R0; // Setup Interrupt Mask R0 = -1; LD32(p0, IMASK); [ P0 ] = R0; // Return to Supervisor Code RAISE 15; NOP; LD32_LABEL(r0, USER_CODE); RETI = R0; RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////// ///////////////////////// EMU ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// EMU_ISR : RTE; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// NMI ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// NMI_ISR : RTN; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// EXC ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// EXC_ISR : // Save all the registers used in the ISR [ -- SP ] = R0; [ -- SP ] = R1; [ -- SP ] = P0; [ -- SP ] = P1; [ -- SP ] = LC0; [ -- SP ] = LB0; [ -- SP ] = LT0; [ -- SP ] = ASTAT; // Get EXCAUSE bits out of SEQSTAT R0 = SEQSTAT; R0 = R0 << 26; R0 = R0 >> 26; // Check for Trace Exception // Load r1 with EXCAUSE for Trace Exception R1 = 0x0011 (Z); // Check for Trace Exception CC = R0 == R1; // Branch to OUT if the EXCAUSE is not TRACE. IF !CC JUMP OUT; // Read out the Trace Buffer. LD32(p0, TBUFSTAT); // Read TBUFSTAT MMR P1 = [ P0 ]; // if p1 is zero skip the loop. CC = P1 == 0; IF CC JUMP OUT; // Read out the Entire Trace Buffer. LD32(p0, TBUF); LSETUP ( l0s , l0e ) LC0 = P1; l0s:R0 = [ P0 ]; l0e:R0 = [ P0 ]; OUT: // Check for other exception, if any. // Restore all saved registers. ASTAT = [ SP ++ ]; LT0 = [ SP ++ ]; LB0 = [ SP ++ ]; LC0 = [ SP ++ ]; P1 = [ SP ++ ]; P0 = [ SP ++ ]; R1 = [ SP ++ ]; R0 = [ SP ++ ]; // Return RTX; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// HWE ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// HWE_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// TMR ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// TMR_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV7 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV7_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV8 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV8_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV9 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV9_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV10 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV10_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV11 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV11_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV12 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV12_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV13 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV13_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV14 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV14_ISR : RTI; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// IGV15 ISR ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// IGV15_ISR : WR_MMR(TBUFCTL, 0x7, p0, r0); // Enable trace buffer & overflow CSYNC; // Wait for MMR write to complete CC = R7 == R6; // Set CC EXCPT 1; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in WB stage NOP; NOP; EXCPT 2; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX3 stage NOP; NOP; EXCPT 3; NOP; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX2 stage NOP; NOP; EXCPT 4; NOP; NOP; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in EX1 stage NOP; NOP; EXCPT 5; NOP; NOP; NOP; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in AC stage NOP; NOP; EXCPT 6; NOP; NOP; NOP; NOP; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in DEC stage NOP; NOP; EXCPT 7; NOP; NOP; NOP; NOP; NOP; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF2 stage NOP; NOP; EXCPT 8; NOP; NOP; NOP; NOP; NOP; NOP; NOP; IF !CC JUMP 4 (BP); // Mispredicted branch gets killed in IF1 stage NOP; NOP; // Read out the Rest of the Trace Buffer. LD32(p0, TBUFSTAT); // Read TBUFSTAT MMR P1 = [ P0 ]; // if p1 is zero skip the loop. CC = P1 == 0; IF CC JUMP OUT1; // Read out the Entire Trace Buffer. LD32(p0, TBUF); LSETUP ( l1s , l1e ) LC0 = P1; l1s:R0 = [ P0 ]; l1e:R0 = [ P0 ]; // Don't RTI if you never wish to go to User Mode // use END_TEST instead. OUT1: dbg_pass; // rti; .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF .dw 0xFFFF ///////////////////////////////////////////////////////////////////////////// ///////////////////////// USER CODE ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// USER_CODE : // YOUR USER CODE GOES HERE. dbg_pass; // Call Endtest Macro ///////////////////////////////////////////////////////////////////////////// ///////////////////////// DATA MEMRORY ///////////////////////////// ///////////////////////////////////////////////////////////////////////////// .section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw" .dd 0x01010101; .dd 0x02020202; .dd 0x03030303; .dd 0x04040404; .dd 0x05050505; .dd 0x06060606; .dd 0x07070707; .dd 0x08080808; .dd 0x09090909; .dd 0x0a0a0a0a; .dd 0x0b0b0b0b; .dd 0x0c0c0c0c; .dd 0x0d0d0d0d; .dd 0x0e0e0e0e; .dd 0x0f0f0f0f; // Define Kernal Stack .section MEM_DATA_ADDR_2 //.data 0x00F00210,"aw" .space (STACKSIZE); KSTACK : .space (STACKSIZE); USTACK : ///////////////////////////////////////////////////////////////////////////// ///////////////////////// END OF TEST ///////////////////////////// /////////////////////////////////////////////////////////////////////////////
tactcomplabs/xbgas-binutils-gdb	4,740	sim/testsuite/bfin/s21.s	// Test A0 = ROT (A0 by imm6); # mach: bfin .include "testutils.inc" start init_r_regs 0; ASTAT = R0; A0 = A1 = 0; // rot // left by 1 // 00 8000 0001 -> 01 0000 0002 cc=0 R0.L = 0x0001; R0.H = 0x8000; R7 = 0; CC = R7; A1 = A0 = 0; A0.w = R0; A0 = ROT A0 BY 1; R1 = A0.w; DBGA ( R1.L , 0x0002 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0x0001 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // left by 1 // 80 0000 0001 -> 00 0000 0002 cc=1 R7 = 0; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY 1; R1 = A0.w; DBGA ( R1.L , 0x0002 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // rot // left by 1 with cc=1 // 80 8000 0001 -> 01 0000 0003 cc=1 R7 = 1; CC = R7; R0.L = 0x0001; R0.H = 0x8000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY 1; R1 = A0.w; DBGA ( R1.L , 0x0003 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0x0001 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // rot // left by 2 with cc=1 // 80 0000 0001 -> 00 0000 0007 cc=0 R7 = 1; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY 2; R1 = A0.w; DBGA ( R1.L , 0x0007 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // left by 3 with cc=0 R7 = 0; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY 3; R1 = A0.w; DBGA ( R1.L , 0x000a ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // left by largest positive magnitude of 31 // 80 0000 0001 -> 00 a000 0000 cc=0 R7 = 0; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY 31; R1 = A0.w; DBGA ( R1.L , 0x0000 ); DBGA ( R1.H , 0xa000 ); R1.L = A0.x; DBGA ( R1.L , 0x0000 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // right by 1 // 80 0000 0001 -> 40 0000 0000 cc=1 R7 = 0; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY -1; R1 = A0.w; DBGA ( R1.L , 0x0000 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0x0040 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // rot // right by 1 // 80 0000 0001 -> c0 0000 0000 cc=1 R7 = 1; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY -1; R1 = A0.w; DBGA ( R1.L , 0x0000 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0xffc0 ); R7 = CC; DBGA ( R7.L , 0x0001 ); // rot // right by 2 // 80 0000 0001 -> e0 0000 0000 cc=0 R7 = 1; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY -2; R1 = A0.w; DBGA ( R1.L , 0x0000 ); DBGA ( R1.H , 0x0000 ); R1.L = A0.x; DBGA ( R1.L , 0xffe0 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // right by 9 // 80 0000 0001 -> 01 c000 0000 cc=0 R7 = 1; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; A0 = ROT A0 BY -9; R1 = A0.w; DBGA ( R1.L , 0x0000 ); DBGA ( R1.H , 0xc000 ); R1.L = A0.x; DBGA ( R1.L , 0x0001 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot // right by 9 with reg // 80 0000 0001 -> 01 c000 0000 cc=0 R7 = 1; CC = R7; R0.L = 0x0001; R0.H = 0x0000; R1.L = 0x0080; A1 = A0 = 0; A0.w = R0; A0.x = R1.L; R5 = -9; A0 = ROT A0 BY R5.L; R1 = A0.w; DBGA ( R1.L , 0x0000 ); DBGA ( R1.H , 0xc000 ); R1.L = A0.x; DBGA ( R1.L , 0x0001 ); R7 = CC; DBGA ( R7.L , 0x0000 ); // rot left by 4 with cc=1 R0.L = 0x789a; R0.H = 0x3456; A0.w = R0; R0.L = 0x12; A0.x = R0; R0 = 1; CC = R0; A0 = ROT A0 BY 4; R4 = A0.w; R5 = A0.x; DBGA ( R4.H , 0x4567 ); DBGA ( R4.L , 0x89a8 ); DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0023 ); // rot left by 28 with cc=1 R0.L = 0x789a; R0.H = 0x3456; A0.w = R0; R0.L = 0x12; A0.x = R0; R0 = 1; CC = R0; A0 = ROT A0 BY 28; R4 = A0.w; R5 = A0.x; DBGA ( R4.H , 0xa891 ); DBGA ( R4.L , 0xa2b3 ); DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff89 ); // rot right by 4 with cc=1 R0.L = 0x789a; R0.H = 0x3456; A0.w = R0; R0.L = 0x12; A0.x = R0; R0 = 1; CC = R0; A0 = ROT A0 BY -4; R4 = A0.w; R5 = A0.x; DBGA ( R4.H , 0x2345 ); DBGA ( R4.L , 0x6789 ); DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0051 ); // rot right by 8 with cc=1 R0.L = 0x789a; R0.H = 0x3456; A0.w = R0; R0.L = 0x12; A0.x = R0; R0 = 1; CC = R0; A0 = ROT A0 BY -28; R4 = A0.w; R5 = A0.x; DBGA ( R4.H , 0xcf13 ); DBGA ( R4.L , 0x5123 ); DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff8a ); pass
tactcomplabs/xbgas-binutils-gdb	1,157	sim/testsuite/bfin/m11.s	// Test extraction from accumulators: // SCALE in SIGNED FRACTIONAL mode # mach: bfin .include "testutils.inc" start // load r0=0x3fff0000 // load r1=0x0fffc000 // load r2=0x7ff00000 // load r3=0x80100000 // load r4=0x000000ff loadsym P0, data0; R0 = [ P0 ++ ]; R1 = [ P0 ++ ]; R2 = [ P0 ++ ]; R3 = [ P0 ++ ]; R4 = [ P0 ++ ]; // SCALE // 0x003fff0000 -> SCALE 0x7ffe A1 = A0 = 0; A1.w = R0; A0.w = R0; R5.H = A1, R5.L = A0 (S2RND); DBGA ( R5.L , 0x7ffe ); DBGA ( R5.H , 0x7ffe ); // SCALE // 0x000fffc000 -> SCALE 0x2000 A1 = A0 = 0; A1.w = R1; A0.w = R1; R5.H = A1, R5.L = A0 (S2RND); DBGA ( R5.L , 0x2000 ); DBGA ( R5.H , 0x2000 ); // SCALE // 0x007ff00000 -> SCALE 0x7fff A1 = A0 = 0; A1.w = R2; A0.w = R2; R5.H = A1, R5.L = A0 (S2RND); DBGA ( R5.L , 0x7fff ); DBGA ( R5.H , 0x7fff ); // SCALE // 0xff80100000 -> SCALE 0x8000 A1 = A0 = 0; A1.w = R3; A0.w = R3; A1.x = R4.L; A0.x = R4.L; R5.H = A1, R5.L = A0 (S2RND); DBGA ( R5.L , 0x8000 ); DBGA ( R5.H , 0x8000 ); pass .data; data0: .dw 0x0000 .dw 0x3fff .dw 0xc000 .dw 0x0fff .dw 0x0000 .dw 0x7ff0 .dw 0x0000 .dw 0x8010 .dw 0x00ff .dw 0x0000
tactcomplabs/xbgas-binutils-gdb	1,050	sim/testsuite/bfin/c_brcc_brf_nbp.s	//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp // Spec Reference: brcc brf no bp # mach: bfin .include "testutils.inc" start imm32 r0, 0x00000000; imm32 r1, 0x00000000; imm32 r2, 0x00000000; imm32 r3, 0x00000000; imm32 r4, 0x00000000; imm32 r5, 0x00000000; imm32 r6, 0x00000000; imm32 r7, 0x00000000; begin: ASTAT = R0; // clear cc IF !CC JUMP good1; // branch on false (should branch) CC = ! CC; // set cc=1 R1 = 1; // if go here, error good1: IF !CC JUMP good2; // branch on false (should branch) bad1: R2 = 2; // if go here, error good2: CC = ! CC; // IF !CC JUMP bad2; // branch on false (should not branch) CC = ! CC; IF !CC JUMP good3; // branch on false (should branch) R3 = 3; // if go here, error good3: IF !CC JUMP end; // branch on true (should branch) bad2: R4 = 4; // if go here error end: CHECKREG r0, 0x00000000; CHECKREG r1, 0x00000000; CHECKREG r2, 0x00000000; CHECKREG r3, 0x00000000; CHECKREG r4, 0x00000000; CHECKREG r5, 0x00000000; CHECKREG r6, 0x00000000; CHECKREG r7, 0x00000000; pass
tactcomplabs/xbgas-binutils-gdb	4,780	sim/testsuite/bfin/c_dsp32mult_dr_m_t.s	//Original:/testcases/core/c_dsp32mult_dr_m_t/c_dsp32mult_dr_m_t.dsp // Spec Reference: dsp32mult single dr munop t # mach: bfin .include "testutils.inc" start imm32 r0, 0xfb235625; imm32 r1, 0x9fba5127; imm32 r2, 0xa3ff6725; imm32 r3, 0x0006f027; imm32 r4, 0xb0abcd29; imm32 r5, 0x1facef2b; imm32 r6, 0xc0fc002d; imm32 r7, 0xd24f702f; R4.L = R0.H * R0.L (T); R5.H = R0.L * R1.L (T); R6.L = R1.L * R0.H (T); R7.L = R1.L * R1.L (T); R0.H = R0.L * R0.L (T); R1.L = R0.L * R1.L (T); R2.L = R1.H * R0.L (T); R3.H = R1.L * R1.L (T); CHECKREG r0, 0x39F95625; CHECKREG r1, 0x9FBA369D; CHECKREG r2, 0xA3FFBF35; CHECKREG r3, 0x174DF027; CHECKREG r4, 0xB0ABFCBA; CHECKREG r5, 0x369DEF2B; CHECKREG r6, 0xC0FCFCEA; CHECKREG r7, 0xD24F3373; imm32 r0, 0xeb23a635; imm32 r1, 0x6fba5137; imm32 r2, 0x1324b7e5; imm32 r3, 0x9e060037; imm32 r4, 0x80ebcd39; imm32 r5, 0xb0aeef3b; imm32 r6, 0xa00ce03d; imm32 r7, 0x12467e03; R4.H = R2.L * R2.L (T); R5.L = R2.L * R3.H (T); R6.L = R3.H * R2.L (T); R7.H = R3.L * R3.L (T); R2.H = R2.L * R2.H (T); R3.L = R2.H * R3.H (T); R0.H = R3.L * R2.L (T); R1.L = R3.L * R3.L (T); CHECKREG r0, 0xFB59A635; CHECKREG r1, 0x6FBA0088; CHECKREG r2, 0xF537B7E5; CHECKREG r3, 0x9E060841; CHECKREG r4, 0x289ECD39; CHECKREG r5, 0xB0AE3731; CHECKREG r6, 0xA00C3731; CHECKREG r7, 0x00007E03; imm32 r0, 0xdd235655; imm32 r1, 0xc4dd5157; imm32 r2, 0x6324d755; imm32 r3, 0x00060055; imm32 r4, 0x90dbc509; imm32 r5, 0x10adef5b; imm32 r6, 0xb00cd05d; imm32 r7, 0x12467d5f; R0.L = R4.L * R4.H (T); R1.H = R4.H * R5.L (T); R2.L = R5.H * R4.L (T); R3.L = R5.L * R5.L (T); R4.H = R4.L * R4.H (T); R5.L = R4.L * R5.H (T); R6.H = R5.H * R4.H (T); R7.L = R5.H * R5.H (T); CHECKREG r0, 0xDD233333; CHECKREG r1, 0x0E735157; CHECKREG r2, 0x6324F851; CHECKREG r3, 0x0006022A; CHECKREG r4, 0x3333C509; CHECKREG r5, 0x10ADF851; CHECKREG r6, 0x06ABD05D; CHECKREG r7, 0x1246022C; imm32 r0, 0xcb235666; imm32 r1, 0xefba5166; imm32 r2, 0x1c248766; imm32 r3, 0xf0060066; imm32 r4, 0x90cb9d69; imm32 r5, 0x10acef6b; imm32 r6, 0x800cc06d; imm32 r7, 0x12467c6f; // test the unsigned U=1 R0.L = R6.L * R6.L (T); R1.H = R6.H * R7.L (T); R2.L = R7.L * R6.L (T); R3.L = R7.L * R7.L (T); R6.L = R6.L * R6.L (T); R7.L = R6.L * R7.L (T); R4.L = R7.L * R6.L (T); R5.L = R7.L * R7.L (T); CHECKREG r0, 0xCB231F93; CHECKREG r1, 0x839C5166; CHECKREG r2, 0x1C24C232; CHECKREG r3, 0xF00678F7; CHECKREG r4, 0x90CB0792; CHECKREG r5, 0x10AC075B; CHECKREG r6, 0x800C1F93; CHECKREG r7, 0x12461EB1; // mix order imm32 r0, 0xab23a675; imm32 r1, 0xcfba5127; imm32 r2, 0x13246705; imm32 r3, 0xe0060007; imm32 r4, 0x9eabcd09; imm32 r5, 0x10ecdfdb; imm32 r6, 0x000e000d; imm32 r7, 0x1246e00f; R0.H = R0.L * R7.H (T); R1.L = R1.H * R6.H (T); R2.L = R2.L * R5.L (T); R3.H = R3.H * R4.H (T); R4.L = R4.L * R3.H (T); R5.L = R5.H * R2.H (T); R6.H = R6.H * R1.L (T); R7.L = R7.L * R0.H (T); CHECKREG r0, 0xF337A675; CHECKREG r1, 0xCFBAFFFA; CHECKREG r2, 0x1324E620; CHECKREG r3, 0x18500007; CHECKREG r4, 0x9EABF651; CHECKREG r5, 0x10EC0287; CHECKREG r6, 0xFFFF000D; CHECKREG r7, 0x12460330; imm32 r0, 0x9b235a75; imm32 r1, 0xcfba5127; imm32 r2, 0x93246905; imm32 r3, 0x09060007; imm32 r4, 0x909bcd09; imm32 r5, 0x10a9e9db; imm32 r6, 0x000c9d0d; imm32 r7, 0x1246790f; R0.L = R7.L * R0.H (T); R1.L = R6.L * R1.L (T); R2.H = R5.L * R2.L (T); R3.L = R4.H * R3.L (T); R4.L = R3.H * R4.H (T); R5.H = R2.H * R5.L (T); R6.L = R1.H * R6.L (T); R7.L = R0.L * R7.L (T); CHECKREG r0, 0x9B23A09B; CHECKREG r1, 0xCFBAC144; CHECKREG r2, 0xEDD46905; CHECKREG r3, 0x0906FFF9; CHECKREG r4, 0x909BF825; CHECKREG r5, 0x0324E9DB; CHECKREG r6, 0x000C2551; CHECKREG r7, 0x1246A5C7; imm32 r0, 0xa9235675; imm32 r1, 0xc8ba5127; imm32 r2, 0x13246705; imm32 r3, 0x08060007; imm32 r4, 0x908bcd09; imm32 r5, 0x10a88fdb; imm32 r6, 0x000c080d; imm32 r7, 0x1246708f; R2.L = R3.L * R6.L (T); R3.L = R4.H * R7.L (T); R0.H = R7.L * R0.L, R0.L = R7.H * R0.H (T); R1.H = R6.L * R1.L (T); R4.L = R5.H * R2.L (T); R5.L = R2.L * R3.L (T); R6.L = R0.L * R4.L (T); R7.H = R1.H * R5.L (T); CHECKREG r0, 0x4C06F399; CHECKREG r1, 0x051A5127; CHECKREG r2, 0x13240000; CHECKREG r3, 0x08069DFD; CHECKREG r4, 0x908B0000; CHECKREG r5, 0x10A80000; CHECKREG r6, 0x000C0000; CHECKREG r7, 0x0000708F; imm32 r0, 0x7b235675; imm32 r1, 0xcfba5127; imm32 r2, 0x17246705; imm32 r3, 0x00760007; imm32 r4, 0x907bcd09; imm32 r5, 0x10a7efdb; imm32 r6, 0x000c700d; imm32 r7, 0x1246770f; R4.L = R5.L * R3.L (T); R6.L = R6.L * R4.H (T); R0.H = R7.L * R5.H (T); R1.L = R0.L * R6.L (T); R2.L = R1.L * R7.H (T); R5.L = R2.L * R2.H (T); R3.H = R3.H * R0.L (T); R7.L = R4.H * R1.H (T); CHECKREG r0, 0x0F7D5675; CHECKREG r1, 0xCFBABE0F; CHECKREG r2, 0x1724F696; CHECKREG r3, 0x004F0007; CHECKREG r4, 0x907BFFFF; CHECKREG r5, 0x10A7FE4C; CHECKREG r6, 0x000C9E60; CHECKREG r7, 0x12462A0E; pass
tactcomplabs/xbgas-binutils-gdb	1,626	sim/testsuite/bfin/c_cc_flag_ccmv_depend.S	//Original:/proj/frio/dv/testcases/core/c_cc_flag_ccmv_depend/c_cc_flag_ccmv_depend.dsp // Spec Reference: ccflag followed by ccmv (# stalls) # mach: bfin #include "test.h" .include "testutils.inc" start R0 = 0; ASTAT = R0; imm32 r0, 0xa08d2311; imm32 r1, 0x10120040; imm32 r2, 0x62b61557; imm32 r3, 0x07300007; imm32 r4, 0x00740088; imm32 r5, 0x609950aa; imm32 r6, 0x20bb06cc; imm32 r7, 0xd90e108f; imm32 p1, 0x1401101f; imm32 p2, 0x3204108e; imm32 fp, 0xd93f1084; imm32 p4, 0xeb04106f; imm32 p5, 0xa90e5089; CC = R7; // cc2dreg IF CC R0 = R3; // ccmov R6 = R0 + R4; CC = ! CC; // cc2dreg IF CC R1 = P1; // ccmov CC = R5 < R1; // ccflag R1 = ASTAT; IF !CC R2 = R5; // ccmov CC = R2 == R3; // ccflag IF CC P1 = R4; // ccmov CC = ! CC; CC = R7 < R5; IF CC P2 = P5; // ccmov CC = P5 == 3; IF CC FP = R2; // ccmov R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair CC = A0 == A1; IF !CC R3 = R6; // ccmov R7 = R3 + R2; A0 += A1 (W32); // dsp32alu a0 + a1 CC = A0 < A1; IF CC R4 = P4; // ccmov R6 = R4; R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac CC = A0 <= A1; IF CC R5 = P5; // ccmov A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac CC = A0 <= A1; IF CC P5 = R6; // ccmov CHECKREG r0, 0x07300007; CHECKREG r1, (_AC0\|_AC0_COPY); CHECKREG r2, 0x00766960; CHECKREG r3, 0x07A4008F; CHECKREG r4, 0xEB04106F; CHECKREG r5, 0xA90E5089; CHECKREG r6, 0xEB04106F; CHECKREG r7, 0x075D69EF; CHECKREG p1, 0x1401101F; CHECKREG p2, 0xA90E5089; CHECKREG fp, 0xD93F1084; CHECKREG p4, 0xEB04106F; CHECKREG p5, 0xA90E5089; pass
tactcomplabs/xbgas-binutils-gdb	5,467	sim/testsuite/bfin/c_ldst_ld_d_p_pp_b.s	//Original:/testcases/core/c_ldst_ld_d_p_pp_b/c_ldst_ld_d_p_pp_b.dsp // Spec Reference: c_ldst ld d [p++] b # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; loadsym p5, DATA_ADDR_1; loadsym p1, DATA_ADDR_2; loadsym p2, DATA_ADDR_3; loadsym p4, DATA_ADDR_5; loadsym fp, DATA_ADDR_6; R0 = B [ P5 ++ ] (Z); R1 = B [ P1 ++ ] (Z); R2 = B [ P2 ++ ] (Z); R4 = B [ P4 ++ ] (Z); R5 = B [ FP ++ ] (Z); CHECKREG r0, 0x00000003; CHECKREG r1, 0x00000023; CHECKREG r2, 0x00000043; CHECKREG r4, 0x00000083; CHECKREG r5, 0x00000003; R1 = B [ P5 ++ ] (Z); R2 = B [ P1 ++ ] (Z); R3 = B [ P2 ++ ] (Z); R5 = B [ P4 ++ ] (Z); R6 = B [ FP ++ ] (Z); CHECKREG r0, 0x00000003; CHECKREG r1, 0x00000002; CHECKREG r2, 0x00000022; CHECKREG r3, 0x00000042; CHECKREG r5, 0x00000082; CHECKREG r6, 0x00000002; R2 = B [ P5 ++ ] (Z); R3 = B [ P1 ++ ] (Z); R4 = B [ P2 ++ ] (Z); R6 = B [ P4 ++ ] (Z); R7 = B [ FP ++ ] (Z); CHECKREG r1, 0x00000002; CHECKREG r2, 0x00000001; CHECKREG r3, 0x00000021; CHECKREG r4, 0x00000041; CHECKREG r6, 0x00000081; CHECKREG r7, 0x00000001; R3 = B [ P5 ++ ] (Z); R4 = B [ P1 ++ ] (Z); R5 = B [ P2 ++ ] (Z); R7 = B [ P4 ++ ] (Z); R0 = B [ FP ++ ] (Z); CHECKREG r0, 0x00000000; CHECKREG r2, 0x00000001; CHECKREG r3, 0x00000000; CHECKREG r4, 0x00000020; CHECKREG r5, 0x00000040; CHECKREG r7, 0x00000080; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B DATA_ADDR_5: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0x0F101213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0xBC0DBE21 .dd 0xBC1DBE22 .dd 0xBC2DBE23 .dd 0xBC3DBE24 .dd 0xBC4DBE65 .dd 0xBC5DBE27 .dd 0xBC6DBE28 .dd 0xBC7DBE29 .dd 0xBC8DBE2F .dd 0xBC9DBE20 .dd 0xBCADBE21 .dd 0xBCBDBE2F .dd 0xBCCDBE23 .dd 0xBCDDBE24 .dd 0xBCFDBE25 .dd 0xC455565C .dd 0xC859606C .dd 0xC263646C .dd 0xC667686C .dd 0xCC0DBE2C DATA_ADDR_6: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F DATA_ADDR_7: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	9,410	sim/testsuite/bfin/lmu_excpt_default.S	//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp // Description: Default protection checks (CPLB disabled) // - MMR access in User mode // - DAG1 Access MMRs (supv/user mode, read/write) // - DAG1 Access Scratch SRAM (user or supervisor mode, read/write) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(selfcheck.inc) include(std.inc) include(mmrs.inc) #define EXCPT_PROTVIOL 0x23 #define OMODE_SUPV 0 // not used in the hardware CHECK_INIT(p5, 0xE0000000); // setup interrupt controller with exception handler address WR_MMR_LABEL(EVT3, handler, p0, r1); WR_MMR_LABEL(EVT15, Supv, p0, r1); WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); CSYNC; A0 = 0; // go to user mode. and enable exceptions LD32_LABEL(r0, User); RETI = R0; // But first raise interrupt 15 so we can run in supervisor mode. RAISE 15; RTI; Supv: //------------------------------------------------------- // DAG1 MMR Write access LD32(i1, (DCPLB_ADDR0)); LD32_LABEL(p2, Y01); // Exception handler will return to this address LD32(r0, 0xdeadbeef); R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X01: A0 = 0 \|\| NOP \|\| [ I1 ] = R1; // Exception should occur here Y01: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG1\|FAULT_SUPV)); // DCPLB_STATUS CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG1 MMR Read access LD32(i1, (DCPLB_ADDR1)); LD32_LABEL(p2, Y02); // Exception handler will return to this address R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X02: A0 = 0 \|\| NOP \|\| R1 = [ I1 ]; // Exception should occur here Y02: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS CHECKREG(r6, (FAULT_READ\|FAULT_DAG1\|FAULT_SUPV)); // DCPLB_STATUS CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!) #if 0 //------------------------------------------------------- // DAG1 Scratch SRAM Write access LD32(i1, (( 0xFF800000 + 0x300000))); LD32_LABEL(p2, Y03); // Exception handler will return to this address LD32(r1, 0xdeadbeef); R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X03: A0 = 0 \|\| NOP \|\| [ I1 ] = R1; // Exception should occur here Y03: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG1\|FAULT_SUPV)); // DCPLB_STATUS CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG1 Scratch SRAM Read access LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); LD32_LABEL(p2, Y04); // Exception handler will return to this address R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X04: A0 = 0 \|\| NOP \|\| R1 = [ I1 ]; // Exception should occur here Y04: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS CHECKREG(r6, (FAULT_READ\|FAULT_DAG1\|FAULT_SUPV)); // DCPLB_STATUS CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!) #endif //------------------------------------------------------- // Now, go to User mode LD32_LABEL(r0, User); RETI = R0; RTI; User: //------------------------------------------------------- // DAG0 MMR Write access (multi-issue) LD32(i1, (DCPLB_ADDR0)); LD32_LABEL(p2, Y11); // Exception handler will return to this address LD32(r0, 0xdeadbeef); R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X11: A0 = 0 \|\| [ I1 ] = R1 \|\| NOP; // Exception should occur here Y11: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG0\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG0 MMR Read access (multi-issue) LD32(i1, (DCPLB_ADDR1)); LD32_LABEL(p2, Y12); // Exception handler will return to this address R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X12: A0 = 0 \|\| R1 = [ I1 ] \|\| NOP; // Exception should occur here Y12: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS CHECKREG(r6, (FAULT_READ\|FAULT_DAG0\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG1 MMR Write access LD32(i1, (DCPLB_ADDR0)); LD32_LABEL(p2, Y13); // Exception handler will return to this address LD32(r0, 0xdeadbeef); R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X13: A0 = 0 \|\| NOP \|\| [ I1 ] = R1; // Exception should occur here Y13: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG1\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG1 MMR Read access LD32(i1, (DCPLB_ADDR1)); LD32_LABEL(p2, Y14); // Exception handler will return to this address R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X14: A0 = 0 \|\| NOP \|\| R1 = [ I1 ]; // Exception should occur here Y14: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS CHECKREG(r6, (FAULT_READ\|FAULT_DAG1\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!) #if 0 //------------------------------------------------------- // DAG1 Scratch SRAM Write access LD32(i1, (( 0xFF800000 + 0x300000))); LD32_LABEL(p2, Y15); // Exception handler will return to this address LD32(r1, 0xdeadbeef); R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X15: A0 = 0 \|\| NOP \|\| [ I1 ] = R1; // Exception should occur here Y15: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG1\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG1 Scratch SRAM Read access LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); LD32_LABEL(p2, Y16); // Exception handler will return to this address R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X16: A0 = 0 \|\| NOP \|\| R1 = [ I1 ]; // Exception should occur here Y16: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS CHECKREG(r6, (FAULT_READ\|FAULT_DAG1\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!) #endif //------------------------------------------------------- // DAG0 MMR Write access (single-issue) LD32(i1, (DCPLB_ADDR0)); LD32_LABEL(p2, Y17); // Exception handler will return to this address LD32(r0, 0xdeadbeef); R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X17: [ I1 ] = R1; // Exception should occur here Y17: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG0\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!) //------------------------------------------------------- // DAG0 MMR Read access (single-issue) LD32(i1, (DCPLB_ADDR1)); LD32_LABEL(p2, Y18); // Exception handler will return to this address R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first X18: R1 = [ I1 ]; // Exception should occur here Y18: // Now check that handler read correct values CHECKREG(r4, (OMODE_SUPV\|EXCPT_PROTVIOL)); // SEQSTAT CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS CHECKREG(r6, (FAULT_READ\|FAULT_DAG0\|FAULT_USER)); // DCPLB_STATUS CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!) //------------------------------------------------------- dbg_pass; handler: R4 = SEQSTAT; // Get exception cause // read and check fail addr (addr_which_causes_exception) // should not be set for alignment exception RD_MMR(DCPLB_FAULT_ADDR, p0, r5); RD_MMR(DCPLB_STATUS, p0, r6); R7 = RETX; // get address of excepting instruction RETX = P2; RTX;
tactcomplabs/xbgas-binutils-gdb	8,468	sim/testsuite/bfin/random_0024.S	# mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x3ce00800 \| _VS \| _AV1S \| _AV0S \| _AQ \| _AZ); imm32 R2, 0x00000000; imm32 R4, 0x00000000; imm32 R7, 0x00000000; R2 = ASHIFT R7 BY R4.L (S); checkreg ASTAT, (0x3ce00800 \| _VS \| _AV1S \| _AV0S \| _AQ \| _AZ); checkreg R2, 0x00000000; checkreg R4, 0x00000000; checkreg R7, 0x00000000; dmm32 ASTAT, (0x7c104680 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY \| _AZ); imm32 R7, 0x00000000; R7 = R7 << 0xe (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x7c104680 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x10d08690 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _CC \| _AC0_COPY \| _AN); imm32 R2, 0x0000ffff; imm32 R5, 0x00000000; R2 = R5 << 0x1a (S); checkreg R2, 0x00000000; checkreg ASTAT, (0x10d08690 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _CC \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x30f08e90 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _CC \| _AC0_COPY \| _AN); imm32 R6, 0x00000000; R6 = ASHIFT R6 BY R6.L (S); checkreg ASTAT, (0x30f08e90 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _CC \| _AC0_COPY \| _AZ); checkreg R6, 0x00000000; dmm32 ASTAT, (0x4060c800 \| _VS \| _AV0S \| _AC1 \| _CC \| _AZ); imm32 R5, 0x00000000; imm32 R7, 0x00000000; R5 = R7 << 0x15 (S); checkreg ASTAT, (0x4060c800 \| _VS \| _AV0S \| _AC1 \| _CC \| _AZ); checkreg R5, 0x00000000; checkreg R7, 0x00000000; dmm32 ASTAT, (0x78604a10 \| _VS \| _AN); imm32 R1, 0x00000000; imm32 R4, 0xe1a88000; R4 = R1 << 0xb (S); checkreg R4, 0x00000000; checkreg ASTAT, (0x78604a10 \| _VS \| _AZ); dmm32 ASTAT, (0x64304800 \| _VS \| _AV1S \| _AV0S \| _AC0_COPY); imm32 R2, 0x00000000; imm32 R7, 0x00000000; R7 = R2 << 0xa (S); checkreg ASTAT, (0x64304800 \| _VS \| _AV1S \| _AV0S \| _AC0_COPY \| _AZ); checkreg R2, 0x00000000; checkreg R7, 0x00000000; dmm32 ASTAT, (0x68f0c280 \| _VS \| _AC1 \| _AC0_COPY \| _AN); imm32 R2, 0x00000000; imm32 R5, 0x0000f74a; R5 = R2 << 0x10 (S); checkreg R5, 0x00000000; checkreg ASTAT, (0x68f0c280 \| _VS \| _AC1 \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x54200c80 \| _VS \| _AV1S \| _AV0S \| _AQ); imm32 R1, 0x00000000; imm32 R2, 0x00000000; R2 = R1 << 0xa (S); checkreg ASTAT, (0x54200c80 \| _VS \| _AV1S \| _AV0S \| _AQ \| _AZ); checkreg R1, 0x00000000; checkreg R2, 0x00000000; dmm32 ASTAT, (0x20300a80 \| _VS \| _AV1S \| _CC \| _AZ); imm32 R2, 0x00000000; imm32 R7, 0x00000000; R7 = R2 << 0x8 (S); checkreg ASTAT, (0x20300a80 \| _VS \| _AV1S \| _CC \| _AZ); checkreg R2, 0x00000000; checkreg R7, 0x00000000; dmm32 ASTAT, (0x14408e10 \| _VS \| _AV0S \| _AQ \| _CC \| _AZ); imm32 R4, 0x0000007f; imm32 R6, 0x00000000; R4 = R6 << 0x3 (S); checkreg R4, 0x00000000; checkreg ASTAT, (0x14408e10 \| _VS \| _AV0S \| _AQ \| _CC \| _AZ); dmm32 ASTAT, (0x2850c490 \| _VS \| _AV1S \| _AV0S \| _AZ); imm32 R5, 0x00000000; imm32 R7, 0xf67f0000; R7 = ASHIFT R5 BY R7.L (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x2850c490 \| _VS \| _AV1S \| _AV0S \| _AZ); dmm32 ASTAT, (0x24a00400 \| _VS \| _AV1S \| _AC0 \| _AC0_COPY \| _AN); imm32 R4, 0x00001e68; imm32 R6, 0x00000000; R4 = R6 << 0x8 (S); checkreg R4, 0x00000000; checkreg ASTAT, (0x24a00400 \| _VS \| _AV1S \| _AC0 \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x34608e00 \| _VS \| _V \| _AV1S \| _AV0S \| _AC1 \| _AQ \| _V_COPY \| _AN); imm32 R1, 0x00000000; imm32 R5, 0x272beb60; R5 = R1 << 0xa (S); checkreg R5, 0x00000000; checkreg ASTAT, (0x34608e00 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AQ \| _AZ); dmm32 ASTAT, (0x20800c90 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY \| _AN); imm32 R3, 0x532993ba; imm32 R5, 0x00000000; R3 = R5 << 0x9 (S); checkreg R3, 0x00000000; checkreg ASTAT, (0x20800c90 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x5430c090 \| _VS \| _V \| _AV0S \| _AC0 \| _AQ \| _V_COPY \| _AC0_COPY); imm32 R1, 0xb1510802; imm32 R6, 0x00000000; R1 = R6 << 0x1e (S); checkreg R1, 0x00000000; checkreg ASTAT, (0x5430c090 \| _VS \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x5cf04c90 \| _VS \| _AV1S \| _AC1 \| _AQ \| _AC0_COPY); dmm32 A1.w, 0xf9bc55b7; dmm32 A1.x, 0x0000002a; imm32 R0, 0x002d0024; imm32 R1, 0x16970042; A1 += R0.L * R1.L; checkreg A1.w, 0xf9bc6847; checkreg A1.x, 0x0000002a; checkreg ASTAT, (0x5cf04c90 \| _VS \| _AV1S \| _AC1 \| _AQ \| _AC0_COPY); dmm32 ASTAT, (0x7c804090 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _CC \| _AC0_COPY \| _AZ); imm32 R5, 0x00000000; imm32 R7, 0xfe773828; R7 = R5 << 0x19 (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x7c804090 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _CC \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x30f04e90 \| _VS \| _AV0S \| _AC0 \| _AQ); imm32 R3, 0x00000000; imm32 R7, 0x00000372; R7 = R3 << 0x6 (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x30f04e90 \| _VS \| _AV0S \| _AC0 \| _AQ \| _AZ); dmm32 ASTAT, (0x04708210 \| _VS \| _AV1S \| _AC0 \| _AQ \| _AN); imm32 R5, 0x00000000; imm32 R7, 0x79b3d220; R7 = R5 << 0x13 (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x04708210 \| _VS \| _AV1S \| _AC0 \| _AQ \| _AZ); dmm32 ASTAT, (0x24e08680 \| _VS \| _AV0S \| _AC1 \| _CC \| _AZ); imm32 R0, 0x00000000; imm32 R6, 0x00000000; imm32 R7, 0xa820afc0; R6 = ASHIFT R0 BY R7.L (S); checkreg ASTAT, (0x24e08680 \| _VS \| _AV0S \| _AC1 \| _CC \| _AZ); checkreg R0, 0x00000000; checkreg R6, 0x00000000; checkreg R7, 0xa820afc0; dmm32 ASTAT, (0x0ca0c090 \| _VS \| _AQ \| _AZ); imm32 R6, 0x00000000; imm32 R7, 0x0000001f; R7 = R6 << 0x14 (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x0ca0c090 \| _VS \| _AQ \| _AZ); dmm32 ASTAT, (0x20204680 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AC0_COPY); imm32 R6, 0x00000000; R6 = R6 << 0x15 (S); checkreg ASTAT, (0x20204680 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AC0_COPY \| _AZ); checkreg R6, 0x00000000; dmm32 ASTAT, (0x14f08c00 \| _VS \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY \| _AZ); imm32 R2, 0x00000000; imm32 R6, 0x00007fff; R6 = R2 << 0x1b (S); checkreg R6, 0x00000000; checkreg ASTAT, (0x14f08c00 \| _VS \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x50b08c00 \| _VS \| _AC1 \| _AQ \| _CC \| _AN); imm32 R1, 0x00000000; imm32 R4, 0x0000fffd; R4 = R1 << 0x9 (S); checkreg R4, 0x00000000; checkreg ASTAT, (0x50b08c00 \| _VS \| _AC1 \| _AQ \| _CC \| _AZ); dmm32 ASTAT, (0x1cb04200 \| _VS \| _AV0S \| _AC1 \| _CC); imm32 R0, 0x00000000; imm32 R2, 0xdeab0000; R2 = R0 << 0x1e (S); checkreg R2, 0x00000000; checkreg ASTAT, (0x1cb04200 \| _VS \| _AV0S \| _AC1 \| _CC \| _AZ); dmm32 ASTAT, (0x54c0ca00 \| _VS \| _AV1S \| _AV0S \| _AC1); imm32 R6, 0x00000000; imm32 R7, 0x9ec9c597; R7 = R6 << 0x8 (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x54c0ca00 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AZ); dmm32 ASTAT, (0x18804400 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY \| _AN); imm32 R7, 0x00000000; R7 = R7 << 0x1d (S); checkreg ASTAT, (0x18804400 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AC0_COPY \| _AZ); checkreg R7, 0x00000000; dmm32 ASTAT, (0x40c08e90 \| _VS \| _AV1S \| _AV0S \| _CC); imm32 R2, 0x00000000; imm32 R5, 0x80000000; imm32 R7, 0x00000000; R5 = ASHIFT R2 BY R7.L (S); checkreg R5, 0x00000000; checkreg ASTAT, (0x40c08e90 \| _VS \| _AV1S \| _AV0S \| _CC \| _AZ); dmm32 ASTAT, (0x70b04290 \| _VS \| _AV1S \| _AV0S \| _AQ \| _AZ); imm32 R5, 0x8000c2d0; imm32 R6, 0x00000000; R5 = R6 << 0x2 (S); checkreg R5, 0x00000000; checkreg ASTAT, (0x70b04290 \| _VS \| _AV1S \| _AV0S \| _AQ \| _AZ); dmm32 ASTAT, (0x7cf04480 \| _VS \| _AV0S \| _AC0 \| _AC0_COPY \| _AZ); imm32 R3, 0x00000000; imm32 R7, 0x00000000; R7 = ASHIFT R3 BY R7.L (S); checkreg ASTAT, (0x7cf04480 \| _VS \| _AV0S \| _AC0 \| _AC0_COPY \| _AZ); checkreg R3, 0x00000000; checkreg R7, 0x00000000; dmm32 ASTAT, (0x78d0c290 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _CC \| _AC0_COPY \| _AZ); imm32 R1, 0x7c98345a; imm32 R4, 0x00000000; R1 = ASHIFT R4 BY R1.L (S); checkreg R1, 0x00000000; checkreg ASTAT, (0x78d0c290 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _CC \| _AC0_COPY \| _AZ); dmm32 ASTAT, (0x58400e80 \| _VS \| _V \| _AV0S \| _AQ \| _CC \| _V_COPY); imm32 R2, 0x00000000; imm32 R4, 0x7fffffff; R4 = R2 << 0x8 (S); checkreg R4, 0x00000000; checkreg ASTAT, (0x58400e80 \| _VS \| _AV0S \| _AQ \| _CC \| _AZ); dmm32 ASTAT, (0x4c804080 \| _VS \| _V \| _AV1S \| _AV0S \| _AV0 \| _V_COPY); imm32 R3, 0x00000000; imm32 R7, 0x3d196b66; R7 = ASHIFT R3 BY R3.L (S); checkreg R7, 0x00000000; checkreg ASTAT, (0x4c804080 \| _VS \| _AV1S \| _AV0S \| _AV0 \| _AZ); dmm32 ASTAT, (0x44304a10 \| _VS \| _AV0S \| _AQ \| _AZ); imm32 R4, 0x00000000; imm32 R6, 0x00000000; R6 = R4 << 0x11 (S); checkreg ASTAT, (0x44304a10 \| _VS \| _AV0S \| _AQ \| _AZ); checkreg R4, 0x00000000; checkreg R6, 0x00000000; pass
tactcomplabs/xbgas-binutils-gdb	7,027	sim/testsuite/bfin/c_ldst_ld_p_p_mm.s	//Original:testcases/core/c_ldst_ld_p_p_mm/c_ldst_ld_p_p_mm.dsp // Spec Reference: c_ldst ld p [p--] # mach: bfin .include "testutils.inc" start // set all regs INIT_I_REGS -1; INIT_R_REGS 0; init_b_regs 0; init_l_regs 0; init_m_regs -1; I0 = P3; I2 = SP; // initial values I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p1, DATA_ADDR_1, 0x18; loadsym p2, DATA_ADDR_2, 0x18; loadsym i1, DATA_ADDR_3, 0x18; loadsym p4, DATA_ADDR_4, 0x18; loadsym p5, DATA_ADDR_5, 0x18; loadsym fp, DATA_ADDR_6, 0x18; loadsym i3, DATA_ADDR_7, 0x18; P3 = I1; SP = I3; P2 = [ P1 -- ]; P3 = [ P1 -- ]; P4 = [ P1 -- ]; P5 = [ P1 -- ]; SP = [ P1 -- ]; FP = [ P1 -- ]; CHECKREG p2, 0x18191A1B; CHECKREG p3, 0x14151617; CHECKREG p4, 0x10111213; CHECKREG p5, 0x0C0D0E0F; CHECKREG sp, 0x08090A0B; CHECKREG fp, 0x04050607; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p2, DATA_ADDR_2, 0x18; P3 = I1; SP = I3; P1 = [ P2 -- ]; P3 = [ P2 -- ]; P4 = [ P2 -- ]; P5 = [ P2 -- ]; SP = [ P2 -- ]; FP = [ P2 -- ]; CHECKREG p1, 0x38393A3B; CHECKREG p3, 0x34353637; CHECKREG p4, 0x30313233; CHECKREG p5, 0x2C2D2E2F; CHECKREG sp, 0x28292A2B; CHECKREG fp, 0x24252627; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym i1, DATA_ADDR_3, 0x18; P3 = I1; SP = I3; P1 = [ P3 -- ]; P2 = [ P3 -- ]; P4 = [ P3 -- ]; P5 = [ P3 -- ]; SP = [ P3 -- ]; FP = [ P3 -- ]; CHECKREG p1, 0x58595A5B; CHECKREG p2, 0x54555657; CHECKREG p4, 0x50515253; CHECKREG p5, 0x4C4D4E4F; CHECKREG sp, 0x48494A4B; CHECKREG fp, 0x44454647; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p4, DATA_ADDR_4, 0x18; P3 = I1; SP = I3; P1 = [ P4 -- ]; P2 = [ P4 -- ]; P3 = [ P4 -- ]; P5 = [ P4 -- ]; SP = [ P4 -- ]; FP = [ P4 -- ]; CHECKREG p1, 0x78797A7B; CHECKREG p2, 0x74757677; CHECKREG p3, 0x70717273; CHECKREG p5, 0x6C6D6E6F; CHECKREG sp, 0x68696A6B; CHECKREG fp, 0x64656667; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_5, 0x18; P3 = I1; SP = I3; P1 = [ P5 -- ]; P2 = [ P5 -- ]; P3 = [ P5 -- ]; P4 = [ P5 -- ]; SP = [ P5 -- ]; FP = [ P5 -- ]; CHECKREG p1, 0x98999A9B; CHECKREG p2, 0x94959697; CHECKREG p3, 0x90919293; CHECKREG p4, 0x8C8D8E8F; CHECKREG sp, 0x88898A8B; CHECKREG fp, 0x84858687; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym i3, DATA_ADDR_6, 0x18; P3 = I1; SP = I3; P1 = [ SP -- ]; P2 = [ SP -- ]; P3 = [ SP -- ]; P4 = [ SP -- ]; P5 = [ SP -- ]; FP = [ SP -- ]; CHECKREG p1, 0x18191A1B; CHECKREG p2, 0x14151617; CHECKREG p3, 0x10111213; CHECKREG p4, 0x0C0D0E0F; CHECKREG p5, 0x08090A0B; CHECKREG fp, 0x04050607; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym fp, DATA_ADDR_7, 0x18; P3 = I1; SP = I3; P1 = [ FP -- ]; P2 = [ FP -- ]; P3 = [ FP -- ]; P4 = [ FP -- ]; P5 = [ FP -- ]; SP = [ FP -- ]; CHECKREG p1, 0x98999A9B; CHECKREG p2, 0x94959697; CHECKREG p3, 0x90919293; CHECKREG p4, 0x8C8D8E8F; CHECKREG p5, 0x88898A8B; CHECKREG sp, 0x84858687; P3 = I0; SP = I2; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x78910213 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xAB0CAD0E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B DATA_ADDR_5: .dd 0x8A8B8C8D .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0x0F101213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0xBC0DBE21 .dd 0xBC1DBE22 .dd 0xBC2DBE23 .dd 0xBC3DBE24 .dd 0xBC4DBE65 .dd 0xBC5DBE27 .dd 0xBC6DBE28 .dd 0xBC7DBE29 .dd 0xBC8DBE2F .dd 0xBC9DBE20 .dd 0xBCADBE21 .dd 0xBCBDBE2F .dd 0xBCCDBE23 .dd 0xBCDDBE24 .dd 0xBCFDBE25 .dd 0xC455565C .dd 0xC859606C .dd 0xC263646C .dd 0xC667686C .dd 0xCC0DBE2C DATA_ADDR_6: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F DATA_ADDR_7: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	3,485	sim/testsuite/bfin/dotproduct2.s	/* Vector Dot Product * This program computes a simple vector dot product using hard * wired input buffers of 128 samples each. These values are in * 1.15 signed . / # mach: bfin .include "testutils.inc" start // load buffer addresses into pointer regs loadsym I0, data0; loadsym I1, data1; // loop control // number of loop iterations is 2^N with r4\|=1<<N // to process 128 samples need 64 iterations P4 = 63; LSETUP ( loop1 , loop1 ) LC0 = P4; A1 = A0 = 0; // For now, serialize two 32b loads. // These should be done in parallel with the dual mac. R0 = [ I0 ++ ]; R1 = [ I1 ++ ]; loop1: A1 += R0.H R1.H, A0 += R0.L * R1.L \|\| R0 = [ I0 ++ ] \|\| R1 = [ I1 ++ ]; A1 += R0.H * R1.H, A0 += R0.L * R1.L; // extract two partial results from accumulators // and do final addition R0 = ( A0 += A1 ); DBGA ( R0.L , 0x5600 ); // 0x00545600 = 0.002574 fract DBGA ( R0.H , 0x0054 ); pass .data data0: .dw 0x0 .dw 0x2 .dw 0x4 .dw 0x6 .dw 0x8 .dw 0xA .dw 0xC .dw 0xE .dw 0x10 .dw 0x12 .dw 0x14 .dw 0x16 .dw 0x18 .dw 0x1A .dw 0x1C .dw 0x1E .dw 0x20 .dw 0x22 .dw 0x24 .dw 0x26 .dw 0x28 .dw 0x2A .dw 0x2C .dw 0x2E .dw 0x30 .dw 0x32 .dw 0x34 .dw 0x36 .dw 0x38 .dw 0x3A .dw 0x3C .dw 0x3E .dw 0x40 .dw 0x42 .dw 0x44 .dw 0x46 .dw 0x48 .dw 0x4A .dw 0x4C .dw 0x4E .dw 0x50 .dw 0x52 .dw 0x54 .dw 0x56 .dw 0x58 .dw 0x5A .dw 0x5C .dw 0x5E .dw 0x60 .dw 0x62 .dw 0x64 .dw 0x66 .dw 0x68 .dw 0x6A .dw 0x6C .dw 0x6E .dw 0x70 .dw 0x72 .dw 0x74 .dw 0x76 .dw 0x78 .dw 0x7A .dw 0x7C .dw 0x7E .dw 0x80 .dw 0x82 .dw 0x84 .dw 0x86 .dw 0x88 .dw 0x8A .dw 0x8C .dw 0x8E .dw 0x90 .dw 0x92 .dw 0x94 .dw 0x96 .dw 0x98 .dw 0x9A .dw 0x9C .dw 0x9E .dw 0xA0 .dw 0xA2 .dw 0xA4 .dw 0xA6 .dw 0xA8 .dw 0xAA .dw 0xAC .dw 0xAE .dw 0xB0 .dw 0xB2 .dw 0xB4 .dw 0xB6 .dw 0xB8 .dw 0xBA .dw 0xBC .dw 0xBE .dw 0xC0 .dw 0xC2 .dw 0xC4 .dw 0xC6 .dw 0xC8 .dw 0xCA .dw 0xCC .dw 0xCE .dw 0xD0 .dw 0xD2 .dw 0xD4 .dw 0xD6 .dw 0xD8 .dw 0xDA .dw 0xDC .dw 0xDE .dw 0xE0 .dw 0xE2 .dw 0xE4 .dw 0xE6 .dw 0xE8 .dw 0xEA .dw 0xEC .dw 0xEE .dw 0xF0 .dw 0xF2 .dw 0xF4 .dw 0xF6 .dw 0xF8 .dw 0xFA .dw 0xFC .dw 0xFE data1: .dw 0x0 .dw 0x2 .dw 0x4 .dw 0x6 .dw 0x8 .dw 0xA .dw 0xC .dw 0xE .dw 0x10 .dw 0x12 .dw 0x14 .dw 0x16 .dw 0x18 .dw 0x1A .dw 0x1C .dw 0x1E .dw 0x20 .dw 0x22 .dw 0x24 .dw 0x26 .dw 0x28 .dw 0x2A .dw 0x2C .dw 0x2E .dw 0x30 .dw 0x32 .dw 0x34 .dw 0x36 .dw 0x38 .dw 0x3A .dw 0x3C .dw 0x3E .dw 0x40 .dw 0x42 .dw 0x44 .dw 0x46 .dw 0x48 .dw 0x4A .dw 0x4C .dw 0x4E .dw 0x50 .dw 0x52 .dw 0x54 .dw 0x56 .dw 0x58 .dw 0x5A .dw 0x5C .dw 0x5E .dw 0x60 .dw 0x62 .dw 0x64 .dw 0x66 .dw 0x68 .dw 0x6A .dw 0x6C .dw 0x6E .dw 0x70 .dw 0x72 .dw 0x74 .dw 0x76 .dw 0x78 .dw 0x7A .dw 0x7C .dw 0x7E .dw 0x80 .dw 0x82 .dw 0x84 .dw 0x86 .dw 0x88 .dw 0x8A .dw 0x8C .dw 0x8E .dw 0x90 .dw 0x92 .dw 0x94 .dw 0x96 .dw 0x98 .dw 0x9A .dw 0x9C .dw 0x9E .dw 0xA0 .dw 0xA2 .dw 0xA4 .dw 0xA6 .dw 0xA8 .dw 0xAA .dw 0xAC .dw 0xAE .dw 0xB0 .dw 0xB2 .dw 0xB4 .dw 0xB6 .dw 0xB8 .dw 0xBA .dw 0xBC .dw 0xBE .dw 0xC0 .dw 0xC2 .dw 0xC4 .dw 0xC6 .dw 0xC8 .dw 0xCA .dw 0xCC .dw 0xCE .dw 0xD0 .dw 0xD2 .dw 0xD4 .dw 0xD6 .dw 0xD8 .dw 0xDA .dw 0xDC .dw 0xDE .dw 0xE0 .dw 0xE2 .dw 0xE4 .dw 0xE6 .dw 0xE8 .dw 0xEA .dw 0xEC .dw 0xEE .dw 0xF0 .dw 0xF2 .dw 0xF4 .dw 0xF6 .dw 0xF8 .dw 0xFA .dw 0xFC .dw 0xFE
tactcomplabs/xbgas-binutils-gdb	1,212	sim/testsuite/bfin/c_dsp32shiftim_af_s.s	//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp # mach: bfin .include "testutils.inc" start // Spec Reference: dsp32shiftimm ashift: ashift saturated imm32 r0, 0x81230001; imm32 r1, 0x19345678; imm32 r2, 0x23c56789; imm32 r3, 0x3ed6789a; imm32 r4, 0x85d789ab; imm32 r5, 0x967f9abc; imm32 r6, 0xa789bbcd; imm32 r7, 0xb891acde; R0 = R0 << 0 (S); R1 = R1 << 3 (S); R2 = R2 << 7 (S); R3 = R3 << 8 (S); R4 = R4 << 15 (S); R5 = R5 << 24 (S); R6 = R6 << 31 (S); R7 = R7 << 20 (S); CHECKREG r0, 0x81230001; CHECKREG r1, 0x7FFFFFFF; CHECKREG r2, 0x7FFFFFFF; CHECKREG r3, 0x7FFFFFFF; CHECKREG r4, 0x80000000; CHECKREG r5, 0x80000000; CHECKREG r6, 0x80000000; CHECKREG r7, 0x80000000; imm32 r0, 0xa1230001; imm32 r1, 0x1e345678; imm32 r2, 0x23f56789; imm32 r3, 0x34db789a; imm32 r4, 0x85a7a9ab; imm32 r5, 0x967c9abc; imm32 r6, 0xa78dabcd; imm32 r7, 0xb8914cde; R6 = R0 >>> 1; R7 = R1 >>> 3; R0 = R2 >>> 7; R1 = R3 >>> 8; R2 = R4 >>> 15; R3 = R5 >>> 24; R4 = R6 >>> 31; R5 = R7 >>> 20; CHECKREG r0, 0x0047EACF; CHECKREG r1, 0x0034DB78; CHECKREG r2, 0xFFFF0B4F; CHECKREG r3, 0xFFFFFF96; CHECKREG r4, 0xFFFFFFFF; CHECKREG r5, 0x0000003C; CHECKREG r6, 0xD0918000; CHECKREG r7, 0x03C68ACF; pass
tactcomplabs/xbgas-binutils-gdb	6,034	sim/testsuite/bfin/c_dsp32alu_minmin.s	//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp // Spec Reference: dsp32alu dregs = min / min ( dregs, dregs) # mach: bfin .include "testutils.inc" start imm32 r0, 0x25678911; imm32 r1, 0x2389ab1d; imm32 r2, 0x2a445345; imm32 r3, 0x46657717; imm32 r4, 0xd567e91b; imm32 r5, 0x6789af1d; imm32 r6, 0x74445d85; imm32 r7, 0x8666a779; R0 = MIN ( R0 , R0 ) (V); R1 = MIN ( R0 , R1 ) (V); R2 = MIN ( R0 , R2 ) (V); R3 = MIN ( R0 , R3 ) (V); R4 = MIN ( R0 , R4 ) (V); R5 = MIN ( R0 , R5 ) (V); R6 = MIN ( R0 , R6 ) (V); R7 = MIN ( R0 , R7 ) (V); CHECKREG r0, 0x25678911; CHECKREG r1, 0x23898911; CHECKREG r2, 0x25678911; CHECKREG r3, 0x25678911; CHECKREG r4, 0xD5678911; CHECKREG r5, 0x25678911; CHECKREG r6, 0x25678911; CHECKREG r7, 0x86668911; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r4, 0xd8889929; imm32 r5, 0xeaaabb2b; imm32 r6, 0xfcccdd2d; imm32 r7, 0x0eeeffff; R0 = MIN ( R1 , R0 ) (V); R1 = MIN ( R1 , R1 ) (V); R2 = MIN ( R1 , R2 ) (V); R3 = MIN ( R1 , R3 ) (V); R4 = MIN ( R1 , R4 ) (V); R5 = MIN ( R1 , R5 ) (V); R6 = MIN ( R1 , R6 ) (V); R7 = MIN ( R1 , R7 ) (V); CHECKREG r0, 0x9567892B; CHECKREG r1, 0xA789AB2D; CHECKREG r2, 0xA789AB2D; CHECKREG r3, 0xA789AB2D; CHECKREG r4, 0xA7899929; CHECKREG r5, 0xA789AB2D; CHECKREG r6, 0xA789AB2D; CHECKREG r7, 0xA789AB2D; imm32 r0, 0x416789ab; imm32 r1, 0x5289abcd; imm32 r2, 0x43445555; imm32 r3, 0xa466a777; imm32 r4, 0x45678dab; imm32 r5, 0xf689abcd; imm32 r6, 0x47445555; imm32 r7, 0x68667777; R0 = MIN ( R2 , R0 ) (V); R1 = MIN ( R2 , R1 ) (V); R2 = MIN ( R2 , R2 ) (V); R3 = MIN ( R2 , R3 ) (V); R4 = MIN ( R2 , R4 ) (V); R5 = MIN ( R2 , R5 ) (V); R6 = MIN ( R2 , R6 ) (V); R7 = MIN ( R2 , R7 ) (V); CHECKREG r0, 0x416789AB; CHECKREG r1, 0x4344ABCD; CHECKREG r2, 0x43445555; CHECKREG r3, 0xA466A777; CHECKREG r4, 0x43448DAB; CHECKREG r5, 0xF689ABCD; CHECKREG r6, 0x43445555; CHECKREG r7, 0x43445555; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; R0 = MIN ( R3 , R0 ) (V); R1 = MIN ( R3 , R1 ) (V); R2 = MIN ( R3 , R2 ) (V); R3 = MIN ( R3 , R3 ) (V); R4 = MIN ( R3 , R4 ) (V); R5 = MIN ( R3 , R5 ) (V); R6 = MIN ( R3 , R6 ) (V); R7 = MIN ( R3 , R7 ) (V); CHECKREG r0, 0x9567892B; CHECKREG r1, 0xA789AB2D; CHECKREG r2, 0xB4445525; CHECKREG r3, 0xC6667727; CHECKREG r4, 0xC6668DAB; CHECKREG r5, 0xC666ABCD; CHECKREG r6, 0xC6665555; CHECKREG r7, 0xC6665555; imm32 r0, 0x5537891b; imm32 r1, 0x6759ab2d; imm32 r2, 0x74555535; imm32 r3, 0x86665747; imm32 r4, 0x98789565; imm32 r5, 0xaa8abb5b; imm32 r6, 0xcc9cdd85; imm32 r7, 0xeeaeff9f; R0 = MIN ( R4 , R0 ) (V); R1 = MIN ( R4 , R1 ) (V); R2 = MIN ( R4 , R2 ) (V); R3 = MIN ( R4 , R3 ) (V); R4 = MIN ( R4 , R4 ) (V); R5 = MIN ( R4 , R5 ) (V); R6 = MIN ( R4 , R6 ) (V); R7 = MIN ( R4 , R7 ) (V); CHECKREG r0, 0x9878891B; CHECKREG r1, 0x98789565; CHECKREG r2, 0x98789565; CHECKREG r3, 0x86669565; CHECKREG r4, 0x98789565; CHECKREG r5, 0x98789565; CHECKREG r6, 0x98789565; CHECKREG r7, 0x98789565; imm32 r0, 0x256b89ab; imm32 r1, 0x64764bcd; imm32 r2, 0x49736564; imm32 r3, 0x61278394; imm32 r4, 0x98876439; imm32 r5, 0xaaaa0bbb; imm32 r6, 0xcccc1ddd; imm32 r7, 0x43346fff; R0 = MIN ( R5 , R0 ) (V); R1 = MIN ( R5 , R1 ) (V); R2 = MIN ( R5 , R2 ) (V); R3 = MIN ( R5 , R3 ) (V); R4 = MIN ( R5 , R4 ) (V); R5 = MIN ( R5 , R5 ) (V); R6 = MIN ( R5 , R6 ) (V); R7 = MIN ( R5 , R7 ) (V); CHECKREG r0, 0xAAAA89AB; CHECKREG r1, 0xAAAA0BBB; CHECKREG r2, 0xAAAA0BBB; CHECKREG r3, 0xAAAA8394; CHECKREG r4, 0x98870BBB; CHECKREG r5, 0xAAAA0BBB; CHECKREG r6, 0xAAAA0BBB; CHECKREG r7, 0xAAAA0BBB; imm32 r0, 0x456739ab; imm32 r1, 0x67694bcd; imm32 r2, 0x03456755; imm32 r3, 0x66666777; imm32 r4, 0x12345699; imm32 r5, 0x45678b6b; imm32 r6, 0x043290d6; imm32 r7, 0x1234567f; R0 = MIN ( R6 , R0 ) (V); R1 = MIN ( R6 , R1 ) (V); R2 = MIN ( R6 , R2 ) (V); R3 = MIN ( R6 , R3 ) (V); R4 = MIN ( R6 , R4 ) (V); R5 = MIN ( R6 , R5 ) (V); R6 = MIN ( R6 , R6 ) (V); R7 = MIN ( R6 , R7 ) (V); CHECKREG r0, 0x043290D6; CHECKREG r1, 0x043290D6; CHECKREG r2, 0x034590D6; CHECKREG r3, 0x043290D6; CHECKREG r4, 0x043290D6; CHECKREG r5, 0x04328B6B; CHECKREG r6, 0x043290D6; CHECKREG r7, 0x043290D6; imm32 r0, 0x976789ab; imm32 r1, 0x6779abcd; imm32 r2, 0x8345a755; imm32 r3, 0x5678b007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R0 = MIN ( R7 , R0 ) (V); R1 = MIN ( R7 , R1 ) (V); R2 = MIN ( R7 , R2 ) (V); R3 = MIN ( R7 , R3 ) (V); R4 = MIN ( R7 , R4 ) (V); R5 = MIN ( R7 , R5 ) (V); R6 = MIN ( R7 , R6 ) (V); R7 = MIN ( R7 , R7 ) (V); CHECKREG r0, 0x976789AB; CHECKREG r1, 0xABCDABCD; CHECKREG r2, 0x8345A755; CHECKREG r3, 0xABCDB007; CHECKREG r4, 0xABCDB799; CHECKREG r5, 0xAAAA0BBB; CHECKREG r6, 0x89AB1D7D; CHECKREG r7, 0xABCD2FF7; imm32 r0, 0x456739ab; imm32 r1, 0x67694bcd; imm32 r2, 0x03456755; imm32 r3, 0x66666777; imm32 r4, 0x12345699; imm32 r5, 0x45678b6b; imm32 r6, 0x043290d6; imm32 r7, 0x1234567f; R4 = MIN ( R4 , R7 ) (V); R5 = MIN ( R5 , R5 ) (V); R2 = MIN ( R6 , R3 ) (V); R6 = MIN ( R0 , R4 ) (V); R0 = MIN ( R1 , R6 ) (V); R2 = MIN ( R2 , R1 ) (V); R1 = MIN ( R3 , R0 ) (V); R7 = MIN ( R7 , R4 ) (V); CHECKREG r0, 0x123439AB; CHECKREG r1, 0x123439AB; CHECKREG r2, 0x043290D6; CHECKREG r3, 0x66666777; CHECKREG r4, 0x1234567F; CHECKREG r5, 0x45678B6B; CHECKREG r6, 0x123439AB; CHECKREG r7, 0x1234567F; imm32 r0, 0xa76789ab; imm32 r1, 0x6779abcd; imm32 r2, 0xb3456755; imm32 r3, 0x5678d007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R3 = MIN ( R4 , R0 ) (V); R5 = MIN ( R5 , R1 ) (V); R2 = MIN ( R2 , R2 ) (V); R7 = MIN ( R7 , R3 ) (V); R4 = MIN ( R3 , R4 ) (V); R0 = MIN ( R1 , R5 ) (V); R1 = MIN ( R0 , R6 ) (V); R6 = MIN ( R6 , R7 ) (V); CHECKREG r0, 0xAAAAABCD; CHECKREG r1, 0x89ABABCD; CHECKREG r2, 0xB3456755; CHECKREG r3, 0xA76789AB; CHECKREG r4, 0xA76789AB; CHECKREG r5, 0xAAAAABCD; CHECKREG r6, 0x89AB89AB; CHECKREG r7, 0xA76789AB; pass
tactcomplabs/xbgas-binutils-gdb	6,034	sim/testsuite/bfin/c_dsp32alu_maxmax.s	//Original:/testcases/core/c_dsp32alu_maxmax/c_dsp32alu_maxmax.dsp // Spec Reference: dsp32alu dregs = max / max ( dregs, dregs) # mach: bfin .include "testutils.inc" start imm32 r0, 0x25678911; imm32 r1, 0x2389ab1d; imm32 r2, 0x34445515; imm32 r3, 0xe6657717; imm32 r4, 0x5a67891b; imm32 r5, 0x67b9ab1d; imm32 r6, 0x744d5515; imm32 r7, 0x8666c777; R0 = MAX ( R0 , R0 ) (V); R1 = MAX ( R0 , R1 ) (V); R2 = MAX ( R0 , R2 ) (V); R3 = MAX ( R0 , R3 ) (V); R4 = MAX ( R0 , R4 ) (V); R5 = MAX ( R0 , R5 ) (V); R6 = MAX ( R0 , R6 ) (V); R7 = MAX ( R0 , R7 ) (V); CHECKREG r0, 0x25678911; CHECKREG r1, 0x2567AB1D; CHECKREG r2, 0x34445515; CHECKREG r3, 0x25677717; CHECKREG r4, 0x5A67891B; CHECKREG r5, 0x67B9AB1D; CHECKREG r6, 0x744D5515; CHECKREG r7, 0x2567C777; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r4, 0xd8889929; imm32 r5, 0xeaaabb2b; imm32 r6, 0xfcccdd2d; imm32 r7, 0x0eeeffff; R0 = MAX ( R1 , R0 ) (V); R1 = MAX ( R1 , R1 ) (V); R2 = MAX ( R1 , R2 ) (V); R3 = MAX ( R1 , R3 ) (V); R4 = MAX ( R1 , R4 ) (V); R5 = MAX ( R1 , R5 ) (V); R6 = MAX ( R1 , R6 ) (V); R7 = MAX ( R1 , R7 ) (V); CHECKREG r0, 0xA789AB2D; CHECKREG r1, 0xA789AB2D; CHECKREG r2, 0xB4445525; CHECKREG r3, 0xC6667727; CHECKREG r4, 0xD888AB2D; CHECKREG r5, 0xEAAABB2B; CHECKREG r6, 0xFCCCDD2D; CHECKREG r7, 0x0EEEFFFF; imm32 r0, 0x416789ab; imm32 r1, 0x5289abcd; imm32 r2, 0x63445555; imm32 r3, 0xa7669777; imm32 r4, 0x456789ab; imm32 r5, 0xb689abcd; imm32 r6, 0xd7445555; imm32 r7, 0x68667777; R0 = MAX ( R2 , R0 ) (V); R1 = MAX ( R2 , R1 ) (V); R2 = MAX ( R2 , R2 ) (V); R3 = MAX ( R2 , R3 ) (V); R4 = MAX ( R2 , R4 ) (V); R5 = MAX ( R2 , R5 ) (V); R6 = MAX ( R2 , R6 ) (V); R7 = MAX ( R2 , R7 ) (V); CHECKREG r0, 0x63445555; CHECKREG r1, 0x63445555; CHECKREG r2, 0x63445555; CHECKREG r3, 0x63445555; CHECKREG r4, 0x63445555; CHECKREG r5, 0x63445555; CHECKREG r6, 0x63445555; CHECKREG r7, 0x68667777; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; R0 = MAX ( R3 , R0 ) (V); R1 = MAX ( R3 , R1 ) (V); R2 = MAX ( R3 , R2 ) (V); R3 = MAX ( R3 , R3 ) (V); R4 = MAX ( R3 , R4 ) (V); R5 = MAX ( R3 , R5 ) (V); R6 = MAX ( R3 , R6 ) (V); R7 = MAX ( R3 , R7 ) (V); CHECKREG r0, 0xC6667727; CHECKREG r1, 0xC6667727; CHECKREG r2, 0xC6667727; CHECKREG r3, 0xC6667727; CHECKREG r4, 0x63447727; CHECKREG r5, 0x63447727; CHECKREG r6, 0x63447727; CHECKREG r7, 0x68667777; imm32 r0, 0x4537891b; imm32 r1, 0x6759ab2d; imm32 r2, 0x44555535; imm32 r3, 0x66665747; imm32 r4, 0x88789565; imm32 r5, 0xaa8abb5b; imm32 r6, 0xcc9cdd85; imm32 r7, 0xeeaeff9f; R0 = MAX ( R4 , R0 ) (V); R1 = MAX ( R4 , R1 ) (V); R2 = MAX ( R4 , R2 ) (V); R3 = MAX ( R4 , R3 ) (V); R4 = MAX ( R4 , R4 ) (V); R5 = MAX ( R4 , R5 ) (V); R6 = MAX ( R4 , R6 ) (V); R7 = MAX ( R4 , R7 ) (V); CHECKREG r0, 0x45379565; CHECKREG r1, 0x6759AB2D; CHECKREG r2, 0x44555535; CHECKREG r3, 0x66665747; CHECKREG r4, 0x88789565; CHECKREG r5, 0xAA8ABB5B; CHECKREG r6, 0xCC9CDD85; CHECKREG r7, 0xEEAEFF9F; imm32 r0, 0xa56b89ab; imm32 r1, 0x659b4bcd; imm32 r2, 0xd9736564; imm32 r3, 0x61278394; imm32 r4, 0xb8876439; imm32 r5, 0xaaaa0bbb; imm32 r6, 0xcccc1ddd; imm32 r7, 0x12346fff; R0 = MAX ( R5 , R0 ) (V); R1 = MAX ( R5 , R1 ) (V); R2 = MAX ( R5 , R2 ) (V); R3 = MAX ( R5 , R3 ) (V); R4 = MAX ( R5 , R4 ) (V); R5 = MAX ( R5 , R5 ) (V); R6 = MAX ( R5 , R6 ) (V); R7 = MAX ( R5 , R7 ) (V); CHECKREG r0, 0xAAAA0BBB; CHECKREG r1, 0x659B4BCD; CHECKREG r2, 0xD9736564; CHECKREG r3, 0x61270BBB; CHECKREG r4, 0xB8876439; CHECKREG r5, 0xAAAA0BBB; CHECKREG r6, 0xCCCC1DDD; CHECKREG r7, 0x12346FFF; imm32 r0, 0x956739ab; imm32 r1, 0x67694bcd; imm32 r2, 0xd3456755; imm32 r3, 0x66666777; imm32 r4, 0x12345699; imm32 r5, 0x45678b6b; imm32 r6, 0x043290d6; imm32 r7, 0x1234567f; R0 = MAX ( R6 , R0 ) (V); R1 = MAX ( R6 , R1 ) (V); R2 = MAX ( R6 , R2 ) (V); R3 = MAX ( R6 , R3 ) (V); R4 = MAX ( R6 , R4 ) (V); R5 = MAX ( R6 , R5 ) (V); R6 = MAX ( R6 , R6 ) (V); R7 = MAX ( R6 , R7 ) (V); CHECKREG r0, 0x043239AB; CHECKREG r1, 0x67694BCD; CHECKREG r2, 0x04326755; CHECKREG r3, 0x66666777; CHECKREG r4, 0x12345699; CHECKREG r5, 0x456790D6; CHECKREG r6, 0x043290D6; CHECKREG r7, 0x1234567F; imm32 r0, 0x876789ab; imm32 r1, 0x6779abcd; imm32 r2, 0xd3456755; imm32 r3, 0x56789007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R0 = MAX ( R7 , R0 ) (V); R1 = MAX ( R7 , R1 ) (V); R2 = MAX ( R7 , R2 ) (V); R3 = MAX ( R7 , R3 ) (V); R4 = MAX ( R7 , R4 ) (V); R5 = MAX ( R7 , R5 ) (V); R6 = MAX ( R7 , R6 ) (V); R7 = MAX ( R7 , R7 ) (V); CHECKREG r0, 0xABCD2FF7; CHECKREG r1, 0x67792FF7; CHECKREG r2, 0xD3456755; CHECKREG r3, 0x56782FF7; CHECKREG r4, 0x789A2FF7; CHECKREG r5, 0xABCD2FF7; CHECKREG r6, 0xABCD2FF7; CHECKREG r7, 0xABCD2FF7; imm32 r0, 0x456739ab; imm32 r1, 0x67694bcd; imm32 r2, 0x03456755; imm32 r3, 0x66666777; imm32 r4, 0x12345699; imm32 r5, 0x45678b6b; imm32 r6, 0x043290d6; imm32 r7, 0x1234567f; R4 = MAX ( R4 , R7 ) (V); R5 = MAX ( R5 , R5 ) (V); R2 = MAX ( R6 , R3 ) (V); R6 = MAX ( R0 , R4 ) (V); R0 = MAX ( R1 , R6 ) (V); R2 = MAX ( R2 , R1 ) (V); R1 = MAX ( R3 , R0 ) (V); R7 = MAX ( R7 , R4 ) (V); CHECKREG r0, 0x67695699; CHECKREG r1, 0x67696777; CHECKREG r2, 0x67696777; CHECKREG r3, 0x66666777; CHECKREG r4, 0x12345699; CHECKREG r5, 0x45678B6B; CHECKREG r6, 0x45675699; CHECKREG r7, 0x12345699; imm32 r0, 0x876789ab; imm32 r1, 0x6779abcd; imm32 r2, 0x2345d755; imm32 r3, 0x5678b007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R3 = MAX ( R4 , R0 ) (V); R5 = MAX ( R5 , R1 ) (V); R2 = MAX ( R2 , R2 ) (V); R7 = MAX ( R7 , R3 ) (V); R4 = MAX ( R3 , R4 ) (V); R0 = MAX ( R1 , R5 ) (V); R1 = MAX ( R0 , R6 ) (V); R6 = MAX ( R6 , R7 ) (V); CHECKREG r0, 0x67790BBB; CHECKREG r1, 0x67791D7D; CHECKREG r2, 0x2345D755; CHECKREG r3, 0x789AB799; CHECKREG r4, 0x789AB799; CHECKREG r5, 0x67790BBB; CHECKREG r6, 0x789A2FF7; CHECKREG r7, 0x789A2FF7; pass
tactcomplabs/xbgas-binutils-gdb	2,263	sim/testsuite/bfin/se_kills2.S	//Original:/proj/frio/dv/testcases/seq/se_kills2/se_kills2.dsp // Description: Test se_kill for all supported types of RTL1 instructions # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // // Constants and Defines // include(selfcheck.inc) include(std.inc) include(symtable.inc) #ifndef STACKSIZE #define STACKSIZE 0x10 #endif // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // etc.) // BOOT: SP = 0 (Z); SP.L = KSTACK; // setup the stack pointer SP.H = KSTACK; FP = SP; // and frame pointer INIT_R_REGS(0); // initialize general purpose regs INIT_P_REGS(0); // initialize the pointers INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); ASTAT = r0; // reset sequencer registers // // The Main Program // START: // ** YOUR CODE GOES HERE // CHECK_INIT(p0, 0xFF7FFFFC); // original CHECK_INIT_DEF(p0); R0 = 0; R1 = 1; R2 = 2; R3 = 3; R4 = 4; R5 = 5; R6 = 6; R7 = 7; P1 = 11; // Assume CC is reset to 0. IF !CC JUMP NEXT1; // following instruction should be killed RAISE 13; NEXT1: IF !CC JUMP NEXT2; EXCPT 15; NEXT2: IF !CC JUMP NEXT3; ( R7:0, P5:0 ) = [ SP ++ ]; NEXT3: IF !CC JUMP NEXT4; [ -- SP ] = ( R7:0, P5:0 ); NEXT4: IF !CC JUMP NEXT5; EMUEXCPT; NEXT5: IF !CC JUMP NEXT6; .dd 0xFACEBABE NEXT6: IF !CC JUMP NEXT7; LINK 12; NEXT7: IF !CC JUMP NEXT8; UNLINK; NEXT8: IF !CC JUMP NEXT9; LSETUP (NEXT10, NEXT11) lc0 = p0; NEXT9: IF !CC JUMP NEXT10; NEXT10: IF !CC JUMP NEXT11; NEXT11: IF !CC JUMP NEXT12; NEXT12: IF !CC JUMP NEXT13; NEXT13: IF !CC JUMP NEXT14; NEXT14: IF !CC JUMP NEXT15; NEXT15: IF !CC JUMP NEXT16; NEXT16: END: CHECKREG(r0, 0); CHECKREG(r1, 1); CHECKREG(r2, 2); CHECKREG(r3, 3); CHECKREG(r4, 4); CHECKREG(r5, 5); CHECKREG(r6, 6); CHECKREG(r7, 7); dbg_pass; // Call Endtest Macro //******************************************************************* // // Data Segment // //.data 0xF0000000 .data DATA: .space (0x010); // Some data space // Stack Segments .space (STACKSIZE); KSTACK:
tactcomplabs/xbgas-binutils-gdb	8,703	sim/testsuite/bfin/c_dsp32shiftim_ahalf_rn.s	//Original:/testcases/core/c_dsp32shiftim_ahalf_rn/c_dsp32shiftim_ahalf_rn.dsp // Spec Reference: dsp32shift ashift # mach: bfin .include "testutils.inc" start imm32 r0, 0x00000000; R0.L = -1; imm32 r1, 0x00008001; imm32 r2, 0x00008002; imm32 r3, 0x00008003; imm32 r4, 0x00008004; imm32 r5, 0x00008005; imm32 r6, 0x00008006; imm32 r7, 0x00008007; R0.L = R0.L >>> 10; R1.L = R1.L >>> 10; R2.L = R2.L >>> 10; R3.L = R3.L >>> 10; R4.L = R4.L >>> 10; R5.L = R5.L >>> 10; R6.L = R6.L >>> 10; R7.L = R7.L >>> 10; CHECKREG r0, 0x0000FFFF; CHECKREG r1, 0x0000FFE0; CHECKREG r2, 0x0000FFE0; CHECKREG r3, 0x0000FFE0; CHECKREG r4, 0x0000FFE0; CHECKREG r5, 0x0000FFE0; CHECKREG r6, 0x0000FFE0; CHECKREG r7, 0x0000FFE0; imm32 r0, 0x02008020; imm32 r0, 0x02008021; imm32 r2, 0x02008022; imm32 r3, 0x02008023; imm32 r4, 0x02008024; imm32 r5, 0x02008025; imm32 r6, 0x02008026; imm32 r7, 0x02008027; R0.L = R0.L >>> 11; R1.L = R1.L >>> 11; R2.L = R2.L >>> 11; R3.L = R3.L >>> 11; R4.L = R4.L >>> 11; R5.L = R5.L >>> 11; R6.L = R6.L >>> 11; R7.L = R7.L >>> 11; CHECKREG r0, 0x0200FFF0; CHECKREG r1, 0x0000FFFF; CHECKREG r2, 0x0200FFF0; CHECKREG r3, 0x0200FFF0; CHECKREG r4, 0x0200FFF0; CHECKREG r5, 0x0200FFF0; CHECKREG r6, 0x0200FFF0; CHECKREG r7, 0x0200FFF0; imm32 r0, 0x00308001; imm32 r1, 0x00308001; R2.L = -15; imm32 r3, 0x00308003; imm32 r4, 0x00308004; imm32 r5, 0x00308005; imm32 r6, 0x00308006; imm32 r7, 0x00308007; R0.L = R0.L >>> 12; R1.L = R1.L >>> 12; R2.L = R2.L >>> 12; R3.L = R3.L >>> 12; R4.L = R4.L >>> 12; R5.L = R5.L >>> 12; R6.L = R6.L >>> 12; R7.L = R7.L >>> 12; CHECKREG r0, 0x0030FFF8; CHECKREG r1, 0x0030FFF8; CHECKREG r2, 0x0200FFFF; CHECKREG r3, 0x0030FFF8; CHECKREG r4, 0x0030FFF8; CHECKREG r5, 0x0030FFF8; CHECKREG r6, 0x0030FFF8; CHECKREG r7, 0x0030FFF8; imm32 r0, 0x00008401; imm32 r1, 0x00008401; imm32 r2, 0x00008402; R3.L = -16; imm32 r4, 0x00008404; imm32 r5, 0x00008405; imm32 r6, 0x00008406; imm32 r7, 0x00008407; R0.L = R0.L >>> 3; R1.L = R1.L >>> 3; R2.L = R2.L >>> 3; R3.L = R3.L >>> 3; R4.L = R4.L >>> 3; R5.L = R5.L >>> 3; R6.L = R6.L >>> 3; R7.L = R7.L >>> 3; CHECKREG r0, 0x0000F080; CHECKREG r1, 0x0000F080; CHECKREG r2, 0x0000F080; CHECKREG r3, 0x0030FFFE; CHECKREG r4, 0x0000F080; CHECKREG r5, 0x0000F080; CHECKREG r6, 0x0000F080; CHECKREG r7, 0x0000F080; // d_lo = ashift (d_hi BY d_lo) // RHx by RLx imm32 r0, 0x05000500; imm32 r1, 0x85010500; imm32 r2, 0x85020500; imm32 r3, 0x85030500; imm32 r4, 0x85040500; imm32 r5, 0x85050500; imm32 r6, 0x85060500; imm32 r7, 0x85070500; R0.L = R0.H >>> 10; R1.L = R1.H >>> 10; R2.L = R2.H >>> 10; R3.L = R3.H >>> 10; R4.L = R4.H >>> 10; R5.L = R5.H >>> 10; R6.L = R6.H >>> 10; R7.L = R7.H >>> 10; CHECKREG r0, 0x05000001; CHECKREG r1, 0x8501FFE1; CHECKREG r2, 0x8502FFE1; CHECKREG r3, 0x8503FFE1; CHECKREG r4, 0x8504FFE1; CHECKREG r5, 0x8505FFE1; CHECKREG r6, 0x8506FFE1; CHECKREG r7, 0x8507FFE1; imm32 r0, 0x80610000; R1.L = -1; imm32 r2, 0x80620000; imm32 r3, 0x80630000; imm32 r4, 0x80640000; imm32 r5, 0x80650000; imm32 r6, 0x80660000; imm32 r7, 0x80670000; R0.L = R0.H >>> 11; R1.L = R1.H >>> 11; R2.L = R2.H >>> 11; R3.L = R3.H >>> 11; R4.L = R4.H >>> 11; R5.L = R5.H >>> 11; R6.L = R6.H >>> 11; R7.L = R7.H >>> 11; CHECKREG r0, 0x8061FFF0; CHECKREG r1, 0x8501FFF0; CHECKREG r2, 0x8062FFF0; CHECKREG r3, 0x8063FFF0; CHECKREG r4, 0x8064FFF0; CHECKREG r5, 0x8065FFF0; CHECKREG r6, 0x8066FFF0; CHECKREG r7, 0x8067FFF0; imm32 r0, 0xa0010070; imm32 r1, 0xa0010070; R2.L = -15; imm32 r3, 0xa0030070; imm32 r4, 0xa0040070; imm32 r5, 0xa0050070; imm32 r6, 0xa0060070; imm32 r7, 0xa0070070; R0.L = R0.H >>> 12; R1.L = R1.H >>> 12; R2.L = R2.H >>> 12; R3.L = R3.H >>> 12; R4.L = R4.H >>> 12; R5.L = R5.H >>> 12; R6.L = R6.H >>> 12; R7.L = R7.H >>> 12; CHECKREG r0, 0xA001FFFA; CHECKREG r1, 0xA001FFFA; CHECKREG r2, 0x8062FFF8; CHECKREG r3, 0xA003FFFA; CHECKREG r4, 0xA004FFFA; CHECKREG r5, 0xA005FFFA; CHECKREG r6, 0xA006FFFA; CHECKREG r7, 0xA007FFFA; imm32 r0, 0xb8010001; imm32 r1, 0xb8010001; imm32 r2, 0xb8020002; R3.L = -16; imm32 r4, 0xb8040004; imm32 r5, 0xb8050005; imm32 r6, 0xb8060006; imm32 r7, 0xb8070007; R0.L = R0.H >>> 13; R1.L = R1.H >>> 13; R2.L = R2.H >>> 13; R3.L = R3.H >>> 13; R4.L = R4.H >>> 13; R5.L = R5.H >>> 13; R6.L = R6.H >>> 13; R7.L = R7.H >>> 13; CHECKREG r0, 0xB801FFFD; CHECKREG r1, 0xB801FFFD; CHECKREG r2, 0xB802FFFD; CHECKREG r3, 0xA003FFFD; CHECKREG r4, 0xB804FFFD; CHECKREG r5, 0xB805FFFD; CHECKREG r6, 0xB806FFFD; CHECKREG r7, 0xB807FFFD; // d_hi = ashft (d_lo BY d_lo) // RLx by RLx imm32 r0, 0x00009001; imm32 r1, 0x00009001; imm32 r2, 0x00009002; imm32 r3, 0x00009003; imm32 r4, 0x00009000; imm32 r5, 0x00009005; imm32 r6, 0x00009006; imm32 r7, 0x00009007; R0.H = R0.L >>> 14; R1.H = R1.L >>> 14; R2.H = R2.L >>> 14; R3.H = R3.L >>> 14; R4.H = R4.L >>> 14; R5.H = R5.L >>> 14; R6.H = R6.L >>> 14; R7.H = R7.L >>> 14; CHECKREG r0, 0xFFFE9001; CHECKREG r1, 0xFFFE9001; CHECKREG r2, 0xFFFE9002; CHECKREG r3, 0xFFFE9003; CHECKREG r4, 0xFFFE9000; CHECKREG r5, 0xFFFE9005; CHECKREG r6, 0xFFFE9006; CHECKREG r7, 0xFFFE9007; imm32 r0, 0xa0008001; imm32 r1, 0xa0008001; imm32 r2, 0xa0008002; imm32 r3, 0xa0008003; imm32 r4, 0xa0008004; R5.L = -1; imm32 r6, 0xa0008006; imm32 r7, 0xa0008007; R0.H = R0.L >>> 5; R1.H = R1.L >>> 5; R2.H = R2.L >>> 5; R3.H = R3.L >>> 5; R4.H = R4.L >>> 5; R5.H = R5.L >>> 5; R6.H = R6.L >>> 5; R7.H = R7.L >>> 5; CHECKREG r0, 0xFC008001; CHECKREG r1, 0xFC008001; CHECKREG r2, 0xFC008002; CHECKREG r3, 0xFC008003; CHECKREG r4, 0xFC008004; CHECKREG r5, 0xFFFFFFFF; CHECKREG r6, 0xFC008006; CHECKREG r7, 0xFC008007; imm32 r0, 0x00009b01; imm32 r1, 0x00009b01; imm32 r2, 0x00009b02; imm32 r3, 0x00009b03; imm32 r4, 0x00009b04; imm32 r5, 0x00009b05; R6.L = -15; imm32 r7, 0x00009007; R0.H = R0.L >>> 6; R1.H = R1.L >>> 6; R2.H = R2.L >>> 6; R3.H = R3.L >>> 6; R4.H = R4.L >>> 6; R5.H = R5.L >>> 6; R6.H = R6.L >>> 6; R7.H = R7.L >>> 6; CHECKREG r0, 0xFE6C9B01; CHECKREG r1, 0xFE6C9B01; CHECKREG r2, 0xFE6C9B02; CHECKREG r3, 0xFE6C9B03; CHECKREG r4, 0xFE6C9B04; CHECKREG r5, 0xFE6C9B05; CHECKREG r6, 0xFFFFFFF1; CHECKREG r7, 0xFE409007; imm32 r0, 0x0000a0c1; imm32 r1, 0x0000a0c1; imm32 r2, 0x0000a0c2; imm32 r3, 0x0000a0c3; imm32 r4, 0x0000a0c4; imm32 r5, 0x0000a0c5; imm32 r6, 0x0000a0c6; R7.L = -16; R0.H = R0.L >>> 7; R1.H = R1.L >>> 7; R2.H = R2.L >>> 7; R3.H = R3.L >>> 7; R4.H = R4.L >>> 7; R5.H = R5.L >>> 7; R6.H = R6.L >>> 7; R7.H = R7.L >>> 7; CHECKREG r0, 0xFF41A0C1; CHECKREG r1, 0xFF41A0C1; CHECKREG r2, 0xFF41A0C2; CHECKREG r3, 0xFF41A0C3; CHECKREG r4, 0xFF41A0C4; CHECKREG r5, 0xFF41A0C5; CHECKREG r6, 0xFF41A0C6; CHECKREG r7, 0xFFFFFFF0; imm32 r0, 0x80010d00; imm32 r1, 0x80010d00; imm32 r2, 0x80020d00; imm32 r3, 0x80030d00; R4.L = -1; imm32 r5, 0x80050d00; imm32 r6, 0x80060d00; imm32 r7, 0x80070d00; R0.H = R0.H >>> 14; R1.H = R1.H >>> 14; R2.H = R2.H >>> 14; R3.H = R3.H >>> 14; R4.H = R4.H >>> 14; R5.H = R5.H >>> 14; R6.H = R6.H >>> 14; R7.H = R7.H >>> 14; CHECKREG r0, 0xFFFE0D00; CHECKREG r1, 0xFFFE0D00; CHECKREG r2, 0xFFFE0D00; CHECKREG r3, 0xFFFE0D00; CHECKREG r4, 0xFFFFFFFF; CHECKREG r5, 0xFFFE0D00; CHECKREG r6, 0xFFFE0D00; CHECKREG r7, 0xFFFE0D00; imm32 r0, 0x8d010000; imm32 r1, 0x8d010000; imm32 r2, 0x8d020000; imm32 r3, 0x8d030000; imm32 r4, 0x8d040000; R5.L = -1; imm32 r6, 0x8d060000; imm32 r7, 0x8d070000; R0.H = R0.H >>> 15; R1.H = R1.H >>> 15; R2.H = R2.H >>> 15; R3.H = R3.H >>> 15; R4.H = R4.H >>> 15; R5.H = R5.H >>> 15; R6.H = R6.H >>> 15; R7.H = R7.H >>> 15; CHECKREG r0, 0xFFFF0000; CHECKREG r1, 0xFFFF0000; CHECKREG r2, 0xFFFF0000; CHECKREG r3, 0xFFFF0000; CHECKREG r4, 0xFFFF0000; CHECKREG r5, 0xFFFFFFFF; CHECKREG r6, 0xFFFF0000; CHECKREG r7, 0xFFFF0000; imm32 r0, 0xde010000; imm32 r1, 0xde010000; imm32 r2, 0xde020000; imm32 r3, 0xde030000; imm32 r4, 0xde040000; imm32 r5, 0xde050000; R6.L = -15; imm32 r7, 0xd0070000; R0.L = R0.H >>> 10; R1.L = R1.H >>> 10; R2.L = R2.H >>> 10; R3.L = R3.H >>> 10; R4.L = R4.H >>> 10; R5.L = R5.H >>> 10; R6.L = R6.H >>> 10; R7.L = R7.H >>> 10; CHECKREG r0, 0xDE01FFF7; CHECKREG r1, 0xDE01FFF7; CHECKREG r2, 0xDE02FFF7; CHECKREG r3, 0xDE03FFF7; CHECKREG r4, 0xDE04FFF7; CHECKREG r5, 0xDE05FFF7; CHECKREG r6, 0xFFFFFFFF; CHECKREG r7, 0xD007FFF4; imm32 r0, 0x9f010c00; imm32 r1, 0xaf010c00; imm32 r2, 0xbf020c00; imm32 r3, 0xcf030c00; imm32 r4, 0xdf040c00; imm32 r5, 0xef050c00; imm32 r6, 0xff060c00; R7.L = -16; R0.H = R0.H >>> 5; R1.H = R1.H >>> 5; R2.H = R2.H >>> 5; R3.H = R3.H >>> 5; R4.H = R4.H >>> 5; R5.H = R5.H >>> 5; R6.H = R6.H >>> 5; R7.H = R7.H >>> 5; CHECKREG r0, 0xFCF80C00; CHECKREG r1, 0xFD780C00; CHECKREG r2, 0xFDF80C00; CHECKREG r3, 0xFE780C00; CHECKREG r4, 0xFEF80C00; CHECKREG r5, 0xFF780C00; CHECKREG r6, 0xFFF80C00; CHECKREG r7, 0xFE80FFF0; pass
tactcomplabs/xbgas-binutils-gdb	4,307	sim/testsuite/bfin/c_dagmodik_lnz_imltbl.s	//Original:/testcases/core/c_dagmodik_lnz_imltbl/c_dagmodik_lnz_imltbl.dsp // Spec Reference: dagmodik l not zero & i+m < b # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; imm32 i0, 0x00001000; imm32 i1, 0x00001100; imm32 i2, 0x00001010; imm32 i3, 0x00001001; imm32 b0, 0x0000100e; imm32 b1, 0x0000110c; imm32 b2, 0x0000101a; imm32 b3, 0x00001008; imm32 l0, 0x000000a1; imm32 l1, 0x000000b2; imm32 l2, 0x000000c3; imm32 l3, 0x000000d4; imm32 m0, 0x00000005; imm32 m1, 0x00000004; imm32 m2, 0x00000003; imm32 m3, 0x00000002; I0 += 2; I1 += 2; I2 += 2; I3 += 2; R0 = I0; R1 = I1; R2 = I2; R3 = I3; I0 += 2; I1 += 2; I2 += 2; I3 += 2; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x00001002; CHECKREG r1, 0x00001102; CHECKREG r2, 0x00001012; CHECKREG r3, 0x00001003; CHECKREG r4, 0x00001004; CHECKREG r5, 0x00001104; CHECKREG r6, 0x00001014; CHECKREG r7, 0x00001005; I0 -= 2; I1 -= 2; I2 -= 2; I3 -= 2; R0 = I0; R1 = I1; R2 = I2; R3 = I3; I0 -= 2; I1 -= 2; I2 -= 2; I3 -= 2; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x000010A3; CHECKREG r1, 0x000011B4; CHECKREG r2, 0x000010D5; CHECKREG r3, 0x000010D7; CHECKREG r4, 0x000010A1; CHECKREG r5, 0x000011B2; CHECKREG r6, 0x000010D3; CHECKREG r7, 0x000010D5; I0 += 4; I1 += 4; I2 += 4; I3 += 4; R0 = I0; R1 = I1; R2 = I2; R3 = I3; I0 += 4; I1 += 4; I2 += 4; I3 += 4; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x000010A5; CHECKREG r1, 0x000011B6; CHECKREG r2, 0x000010D7; CHECKREG r3, 0x000010D9; CHECKREG r4, 0x000010A9; CHECKREG r5, 0x000011BA; CHECKREG r6, 0x000010DB; CHECKREG r7, 0x00001009; I0 -= 4; I0 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG r0, 0x000010A1; CHECKREG r1, 0x000011B2; CHECKREG r2, 0x000010D3; CHECKREG r3, 0x000010D5; CHECKREG r4, 0x000010A9; CHECKREG r5, 0x000011BA; CHECKREG r6, 0x000010DB; CHECKREG r7, 0x00001009; I0 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; I0 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x000010A1; CHECKREG r1, 0x000011B2; CHECKREG r2, 0x000010D3; CHECKREG r3, 0x000010D5; CHECKREG r4, 0x00001099; CHECKREG r5, 0x000011AA; CHECKREG r6, 0x000010CB; CHECKREG r7, 0x000010CD; // i+m = b+l imm32 i0, 0x00001000; imm32 i1, 0x00001100; imm32 i2, 0x00001010; imm32 i3, 0x00001001; imm32 b0, 0x0000100e; imm32 b1, 0x0000110c; imm32 b2, 0x0000101a; imm32 b3, 0x00001008; imm32 l0, 0x00000011; imm32 l1, 0x00000012; imm32 l2, 0x00000013; imm32 l3, 0x00000014; imm32 m0, 0x00000002; imm32 m1, 0x00000003; imm32 m2, 0x00000004; imm32 m3, 0x00000005; I0 += 2; I1 += 2; I2 += 2; I3 += 2; R0 = I0; R1 = I1; R2 = I2; R3 = I3; I0 += 2; I1 += 2; I2 += 2; I3 += 2; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x00001002; CHECKREG r1, 0x00001102; CHECKREG r2, 0x00001012; CHECKREG r3, 0x00001003; CHECKREG r4, 0x00001004; CHECKREG r5, 0x00001104; CHECKREG r6, 0x00001014; CHECKREG r7, 0x00001005; I0 -= 2; I1 -= 2; I2 -= 2; I3 -= 2; R0 = I0; R1 = I1; R2 = I2; R3 = I3; I0 -= 2; I1 -= 2; I2 -= 2; I3 -= 2; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x00001013; CHECKREG r1, 0x00001114; CHECKREG r2, 0x00001025; CHECKREG r3, 0x00001017; CHECKREG r4, 0x00001011; CHECKREG r5, 0x00001112; CHECKREG r6, 0x00001023; CHECKREG r7, 0x00001015; I0 += 4; I1 += 4; I2 += 4; I3 += 4; R0 = I0; R1 = I1; R2 = I2; R3 = I3; I0 += 4; I1 += 4; I2 += 4; I3 += 4; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x00001015; CHECKREG r1, 0x00001116; CHECKREG r2, 0x00001027; CHECKREG r3, 0x00001019; CHECKREG r4, 0x00001019; CHECKREG r5, 0x0000111A; CHECKREG r6, 0x0000102B; CHECKREG r7, 0x00001009; I0 -= 4; I0 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG r0, 0x00001011; CHECKREG r1, 0x00001112; CHECKREG r2, 0x00001023; CHECKREG r3, 0x00001015; CHECKREG r4, 0x00001019; CHECKREG r5, 0x0000111A; CHECKREG r6, 0x0000102B; CHECKREG r7, 0x00001009; I0 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; I0 -= 4; I1 -= 4; I2 -= 4; I3 -= 4; R4 = I0; R5 = I1; R6 = I2; R7 = I3; CHECKREG r0, 0x00001011; CHECKREG r1, 0x00001112; CHECKREG r2, 0x00001023; CHECKREG r3, 0x00001015; CHECKREG r4, 0x0000101A; CHECKREG r5, 0x0000111C; CHECKREG r6, 0x0000101B; CHECKREG r7, 0x0000100D; pass
tactcomplabs/xbgas-binutils-gdb	5,107	sim/testsuite/bfin/c_dsp32shift_expadj_l.s	//Original:/testcases/core/c_dsp32shift_expadj_l/c_dsp32shift_expadj_l.dsp // Spec Reference: dsp32shift expadj rl # mach: bfin .include "testutils.inc" start imm32 r0, 0x00000000; imm32 r1, 0x0000c001; imm32 r2, 0x0000c002; imm32 r3, 0x0000c003; imm32 r4, 0x0000c004; imm32 r5, 0x0000c005; imm32 r6, 0x0000c006; imm32 r7, 0x0000c007; R1.L = EXPADJ( R1.L , R0.L ); R2.L = EXPADJ( R2.L , R0.L ); R3.L = EXPADJ( R3.L , R0.L ); R4.L = EXPADJ( R4.L , R0.L ); R5.L = EXPADJ( R5.L , R0.L ); R6.L = EXPADJ( R6.L , R0.L ); R7.L = EXPADJ( R7.L , R0.L ); R0.L = EXPADJ( R0.L , R0.L ); CHECKREG r0, 0x00000000; CHECKREG r1, 0x00000000; CHECKREG r2, 0x00000000; CHECKREG r3, 0x00000000; CHECKREG r4, 0x00000000; CHECKREG r5, 0x00000000; CHECKREG r6, 0x00000000; CHECKREG r7, 0x00000000; imm32 r0, 0x11001001; imm32 r1, 0x11001001; imm32 r2, 0x11001002; imm32 r3, 0x11001003; imm32 r4, 0x11001004; imm32 r5, 0x11001005; imm32 r6, 0x11001006; imm32 r7, 0x11001007; R0.L = EXPADJ( R0.L , R1.L ); R2.L = EXPADJ( R2.L , R1.L ); R3.L = EXPADJ( R3.L , R1.L ); R4.L = EXPADJ( R4.L , R1.L ); R5.L = EXPADJ( R5.L , R1.L ); R6.L = EXPADJ( R6.L , R1.L ); R7.L = EXPADJ( R7.L , R1.L ); R1.L = EXPADJ( R1.L , R1.L ); CHECKREG r0, 0x11001001; CHECKREG r1, 0x11001001; CHECKREG r2, 0x11001001; CHECKREG r3, 0x11001001; CHECKREG r4, 0x11001001; CHECKREG r5, 0x11001001; CHECKREG r6, 0x11001001; CHECKREG r7, 0x11001001; imm32 r0, 0x2000c001; imm32 r1, 0x2000d001; imm32 r2, 0x2000000f; imm32 r3, 0x2000e003; imm32 r4, 0x2000f004; imm32 r5, 0x2000f005; imm32 r6, 0x2000f006; imm32 r7, 0x2000f007; R0.L = EXPADJ( R0.L , R2.L ); R1.L = EXPADJ( R1.L , R2.L ); R3.L = EXPADJ( R3.L , R2.L ); R4.L = EXPADJ( R4.L , R2.L ); R5.L = EXPADJ( R5.L , R2.L ); R6.L = EXPADJ( R6.L , R2.L ); R7.L = EXPADJ( R7.L , R2.L ); R2.L = EXPADJ( R2.L , R2.L ); CHECKREG r0, 0x20000001; CHECKREG r1, 0x20000001; CHECKREG r2, 0x2000000B; CHECKREG r3, 0x20000002; CHECKREG r4, 0x20000003; CHECKREG r5, 0x20000003; CHECKREG r6, 0x20000003; CHECKREG r7, 0x20000003; imm32 r0, 0x30009001; imm32 r1, 0x3000a001; imm32 r2, 0x3000b002; imm32 r3, 0x30000010; imm32 r4, 0x3000c004; imm32 r5, 0x3000d005; imm32 r6, 0x3000e006; imm32 r7, 0x3000f007; R0.L = EXPADJ( R0.L , R3.L ); R1.L = EXPADJ( R1.L , R3.L ); R2.L = EXPADJ( R2.L , R3.L ); R4.L = EXPADJ( R4.L , R3.L ); R5.L = EXPADJ( R5.L , R3.L ); R6.L = EXPADJ( R6.L , R3.L ); R7.L = EXPADJ( R7.L , R3.L ); R3.L = EXPADJ( R3.L , R3.L ); CHECKREG r0, 0x30000010; CHECKREG r1, 0x30000010; CHECKREG r2, 0x30000010; CHECKREG r3, 0x30000010; CHECKREG r4, 0x30000010; CHECKREG r5, 0x30000010; CHECKREG r6, 0x30000010; CHECKREG r7, 0x30000010; imm32 r0, 0x40000000; imm32 r1, 0x4000c001; imm32 r2, 0x4000c002; imm32 r3, 0x4000c003; imm32 r4, 0x4000c004; imm32 r5, 0x4000c005; imm32 r6, 0x4000c006; imm32 r7, 0x4000c007; R0.L = EXPADJ( R1.L , R4.L ); R1.L = EXPADJ( R2.L , R4.L ); R2.L = EXPADJ( R3.L , R4.L ); R3.L = EXPADJ( R4.L , R4.L ); R5.L = EXPADJ( R5.L , R4.L ); R6.L = EXPADJ( R6.L , R4.L ); R7.L = EXPADJ( R7.L , R4.L ); R4.L = EXPADJ( R0.L , R4.L ); CHECKREG r0, 0x40000001; CHECKREG r1, 0x40000001; CHECKREG r2, 0x40000001; CHECKREG r3, 0x40000001; CHECKREG r4, 0x4000C004; CHECKREG r5, 0x40000001; CHECKREG r6, 0x40000001; CHECKREG r7, 0x40000001; imm32 r0, 0x51001001; imm32 r1, 0x51001001; imm32 r2, 0x51001002; imm32 r3, 0x51001003; imm32 r4, 0x51001004; imm32 r5, 0x51001005; imm32 r6, 0x51001006; imm32 r7, 0x51001007; R0.L = EXPADJ( R0.L , R5.L ); R1.L = EXPADJ( R2.L , R5.L ); R2.L = EXPADJ( R3.L , R5.L ); R3.L = EXPADJ( R4.L , R5.L ); R4.L = EXPADJ( R5.L , R5.L ); R6.L = EXPADJ( R6.L , R5.L ); R7.L = EXPADJ( R7.L , R5.L ); R5.L = EXPADJ( R1.L , R5.L ); CHECKREG r0, 0x51000002; CHECKREG r1, 0x51000002; CHECKREG r2, 0x51000002; CHECKREG r3, 0x51000002; CHECKREG r4, 0x51000002; CHECKREG r5, 0x51001005; CHECKREG r6, 0x51000002; CHECKREG r7, 0x51000002; imm32 r0, 0x6000c001; imm32 r1, 0x6000d001; imm32 r2, 0x6000000f; imm32 r3, 0x6000e003; imm32 r4, 0x6000f004; imm32 r5, 0x6000f005; imm32 r6, 0x6000f006; imm32 r7, 0x6000f007; R0.L = EXPADJ( R0.L , R6.L ); R1.L = EXPADJ( R1.L , R6.L ); R2.L = EXPADJ( R3.L , R6.L ); R3.L = EXPADJ( R4.L , R6.L ); R4.L = EXPADJ( R5.L , R6.L ); R5.L = EXPADJ( R6.L , R6.L ); R7.L = EXPADJ( R7.L , R6.L ); R6.L = EXPADJ( R2.L , R6.L ); CHECKREG r0, 0x60000001; CHECKREG r1, 0x60000001; CHECKREG r2, 0x60000002; CHECKREG r3, 0x60000003; CHECKREG r4, 0x60000003; CHECKREG r5, 0x60000003; CHECKREG r6, 0x6000F006; CHECKREG r7, 0x60000003; imm32 r0, 0x70009001; imm32 r1, 0x7000a001; imm32 r2, 0x7000b002; imm32 r3, 0x70000010; imm32 r4, 0x7000c004; imm32 r5, 0x7000d005; imm32 r6, 0x7000e006; imm32 r7, 0x7000f007; R0.L = EXPADJ( R0.L , R7.L ); R1.L = EXPADJ( R1.L , R7.L ); R2.L = EXPADJ( R2.L , R7.L ); R3.L = EXPADJ( R4.L , R7.L ); R4.L = EXPADJ( R5.L , R7.L ); R5.L = EXPADJ( R6.L , R7.L ); R6.L = EXPADJ( R7.L , R7.L ); R7.L = EXPADJ( R3.L , R7.L ); CHECKREG r0, 0x70000000; CHECKREG r1, 0x70000000; CHECKREG r2, 0x70000000; CHECKREG r3, 0x70000001; CHECKREG r4, 0x70000001; CHECKREG r5, 0x70000002; CHECKREG r6, 0x70000003; CHECKREG r7, 0x7000F007; pass
tactcomplabs/xbgas-binutils-gdb	2,963	sim/testsuite/bfin/c_loopsetup_nested_prelc.s	//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp // Spec Reference: loopsetup nested preload lc0 lc1 # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; ASTAT = r0; //p0 = 2; P1 = 3; P2 = 4; P3 = 5; P4 = 6; P5 = 7; SP = 8; FP = 9; R0 = 0x05; R1 = 0x10; R2 = 0x12; R3 = 0x14; R4 = 0x18; R5 = 0x16; R6 = 0x16; R7 = 0x18; LC0 = R0; LC1 = R1; LSETUP ( start1 , end1 ) LC0; start1: R0 += 1; R1 += -2; LSETUP ( start2 , end2 ) LC1; start2: R4 += 4; end2: R5 += -5; R3 += 1; end1: R2 += 3; R3 += 4; LC0 = R7; LC1 = R6; LSETUP ( start3 , end3 ) LC0; start3: R6 += 6; LSETUP ( start4 , end4 ) LC1; start4: R0 += 1; R1 += -2; end4: R2 += 3; R3 += 4; end3: R7 += -7; R3 += 1; CHECKREG r0, 0x00000037; CHECKREG r1, 0xFFFFFFAC; CHECKREG r2, 0x000000A8; CHECKREG r3, 0x0000007E; CHECKREG r4, 0x00000068; CHECKREG r5, 0xFFFFFFB2; CHECKREG r6, 0x000000A6; CHECKREG r7, 0xFFFFFF70; R0 = 0x05; R1 = 0x10; R2 = 0x08; R3 = 0x0C; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x60 (X); R7 = 0x70 (X); LC0 = R2; LC1 = R3; LSETUP ( start5 , end5 ) LC0; start5: R4 += 1; LSETUP ( start6 , end6 ) LC1; start6: R6 += 4; end6: R7 += -5; R3 += 6; end5: R5 += -2; R3 += 3; CHECKREG r0, 0x00000005; CHECKREG r1, 0x00000010; CHECKREG r2, 0x00000008; CHECKREG r3, 0x0000003F; CHECKREG r4, 0x00000048; CHECKREG r5, 0x00000040; CHECKREG r6, 0x000000AC; CHECKREG r7, 0x00000011; LSETUP ( start7 , end7 ) LC0; start7: R4 += 4; end7: R5 += -5; R3 += 6; CHECKREG r0, 0x00000005; CHECKREG r1, 0x00000010; CHECKREG r2, 0x00000008; CHECKREG r3, 0x00000045; CHECKREG r4, 0x0000004C; CHECKREG r5, 0x0000003B; CHECKREG r6, 0x000000AC; CHECKREG r7, 0x00000011; P1 = 12; P2 = 14; P3 = 16; P4 = 18; P5 = 12; SP = 14; FP = 16; R0 = 0x05; R1 = 0x10; R2 = 0x14; R3 = 0x18; R4 = 0x16; R5 = 0x04; R6 = 0x30; R7 = 0x30; LC0 = R5; LC1 = R4; LSETUP ( start11 , end11 ) LC0; start11: R0 += 1; R1 += -1; LSETUP ( start15 , end15 ) LC1; start15: R4 += 1; end15: R5 += -1; R3 += 1; end11: R2 += 1; R3 += 1; LSETUP ( start13 , end13 ) LC0 = P5; start13: R6 += 1; LSETUP ( start12 , end12 ) LC1 = P2; start12: R4 += 1; end12: R5 += -1; R3 += 1; end13: R7 += -1; R3 += 1; CHECKREG r0, 0x00000009; CHECKREG r1, 0x0000000C; CHECKREG r2, 0x00000018; CHECKREG r3, 0x0000002A; CHECKREG r4, 0x000000D7; CHECKREG r5, 0xFFFFFF43; CHECKREG r6, 0x0000003C; CHECKREG r7, 0x00000024; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x14; R7 = 0x08; P4 = 6; FP = 8; LC0 = R6; LC1 = R7; LSETUP ( start14 , end14 ) LC0 = P4; start14: R0 += 1; R1 += -1; LSETUP ( start16 , end16 ) LC1; start16: R6 += 1; end16: R7 += -1; R3 += 1; LSETUP ( start17 , end17 ) LC1 = FP >> 1; start17: R4 += 1; end17: R5 += -1; R3 += 1; end14: R2 += 1; R3 += 1; CHECKREG r0, 0x0000000B; CHECKREG r1, 0x0000000A; CHECKREG r2, 0x00000026; CHECKREG r3, 0x0000003D; CHECKREG r4, 0x00000058; CHECKREG r5, 0x00000038; CHECKREG r6, 0x00000021; CHECKREG r7, 0xFFFFFFFB; pass
tactcomplabs/xbgas-binutils-gdb	3,313	sim/testsuite/bfin/a2.s	# mach: bfin .include "testutils.inc" start loadsym P0, middle; R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 ); R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 ); R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 ); R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 ); R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 ); R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 ); R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 ); R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 ); R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 ); R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 ); R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 ); R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 ); R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 ); R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 ); R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 ); R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 ); FP = P0; R0 = [ FP + 0 ]; DBGA ( R0.L , 50 ); R0 = [ FP + 4 ]; DBGA ( R0.L , 51 ); R0 = [ FP + 8 ]; DBGA ( R0.L , 52 ); R0 = [ FP + 12 ]; DBGA ( R0.L , 53 ); R0 = [ FP + 16 ]; DBGA ( R0.L , 54 ); R0 = [ FP + 20 ]; DBGA ( R0.L , 55 ); R0 = [ FP + 24 ]; DBGA ( R0.L , 56 ); R0 = [ FP + 28 ]; DBGA ( R0.L , 57 ); R0 = [ FP + 32 ]; DBGA ( R0.L , 58 ); R0 = [ FP + 36 ]; DBGA ( R0.L , 59 ); R0 = [ FP + 40 ]; DBGA ( R0.L , 60 ); R0 = [ FP + 44 ]; DBGA ( R0.L , 61 ); R0 = [ FP + 48 ]; DBGA ( R0.L , 62 ); R0 = [ FP + 52 ]; DBGA ( R0.L , 63 ); R0 = [ FP + 56 ]; DBGA ( R0.L , 64 ); R0 = [ FP + 60 ]; DBGA ( R0.L , 65 ); R0 = [ FP + -4 ]; DBGA ( R0.L , 49 ); R0 = [ FP + -8 ]; DBGA ( R0.L , 48 ); R0 = [ FP + -12 ]; DBGA ( R0.L , 47 ); R0 = [ FP + -16 ]; DBGA ( R0.L , 46 ); R0 = [ FP + -20 ]; DBGA ( R0.L , 45 ); R0 = [ FP + -24 ]; DBGA ( R0.L , 44 ); R0 = [ FP + -28 ]; DBGA ( R0.L , 43 ); R0 = [ FP + -32 ]; DBGA ( R0.L , 42 ); R0 = [ FP + -36 ]; DBGA ( R0.L , 41 ); R0 = [ FP + -40 ]; DBGA ( R0.L , 40 ); R0 = [ FP + -44 ]; DBGA ( R0.L , 39 ); R0 = [ FP + -48 ]; DBGA ( R0.L , 38 ); R0 = [ FP + -52 ]; DBGA ( R0.L , 37 ); R0 = [ FP + -56 ]; DBGA ( R0.L , 36 ); R0 = [ FP + -60 ]; DBGA ( R0.L , 35 ); R0 = [ FP + -64 ]; DBGA ( R0.L , 34 ); R0 = [ FP + -68 ]; DBGA ( R0.L , 33 ); R0 = [ FP + -72 ]; DBGA ( R0.L , 32 ); R0 = [ FP + -76 ]; DBGA ( R0.L , 31 ); R0 = [ FP + -80 ]; DBGA ( R0.L , 30 ); R0 = [ FP + -84 ]; DBGA ( R0.L , 29 ); R0 = [ FP + -88 ]; DBGA ( R0.L , 28 ); R0 = [ FP + -92 ]; DBGA ( R0.L , 27 ); R0 = [ FP + -96 ]; DBGA ( R0.L , 26 ); R0 = [ FP + -100 ]; DBGA ( R0.L , 25 ); R0 = [ FP + -104 ]; DBGA ( R0.L , 24 ); R0 = [ FP + -108 ]; DBGA ( R0.L , 23 ); R0 = [ FP + -112 ]; DBGA ( R0.L , 22 ); R0 = [ FP + -116 ]; DBGA ( R0.L , 21 ); pass .data base: .dd 0 .dd 1 .dd 2 .dd 3 .dd 4 .dd 5 .dd 6 .dd 7 .dd 8 .dd 9 .dd 10 .dd 11 .dd 12 .dd 13 .dd 14 .dd 15 .dd 16 .dd 17 .dd 18 .dd 19 .dd 20 .dd 21 .dd 22 .dd 23 .dd 24 .dd 25 .dd 26 .dd 27 .dd 28 .dd 29 .dd 30 .dd 31 .dd 32 .dd 33 .dd 34 .dd 35 .dd 36 .dd 37 .dd 38 .dd 39 .dd 40 .dd 41 .dd 42 .dd 43 .dd 44 .dd 45 .dd 46 .dd 47 .dd 48 .dd 49 middle: .dd 50 .dd 51 .dd 52 .dd 53 .dd 54 .dd 55 .dd 56 .dd 57 .dd 58 .dd 59 .dd 60 .dd 61 .dd 62 .dd 63 .dd 64 .dd 65 .dd 66 .dd 67 .dd 68 .dd 69 .dd 70 .dd 71 .dd 72 .dd 73 .dd 74 .dd 75 .dd 76 .dd 77 .dd 78 .dd 79 .dd 80 .dd 81 .dd 82 .dd 83 .dd 84 .dd 85 .dd 86 .dd 87 .dd 88 .dd 89 .dd 90 .dd 91 .dd 92 .dd 93 .dd 94 .dd 95 .dd 96 .dd 97 .dd 98 .dd 99
tactcomplabs/xbgas-binutils-gdb	4,342	sim/testsuite/bfin/c_dsp32shift_a0alr.s	//Original:/proj/frio/dv/testcases/core/c_dsp32shift_a0alr/c_dsp32shift_a0alr.dsp // Spec Reference: dsp32shift a0 ashift, lshift, rot # mach: bfin .include "testutils.inc" start R0 = 0; ASTAT = R0; imm32 r0, 0x11140000; imm32 r1, 0x012C003E; imm32 r2, 0x81359E24; imm32 r3, 0x81459E24; imm32 r4, 0xD159E268; imm32 r5, 0x51626AF2; imm32 r6, 0x9176AF36; imm32 r7, 0xE18BFF86; R0.L = 0; A0 = 0; A0.L = R1.L; A0.H = R1.H; A0 = ASHIFT A0 BY R0.L; /* a0 = 0x00000000 / R2 = A0.w; / r5 = 0x00000000 / CHECKREG r2, 0x012C003E; R1.L = 1; A0.L = R2.L; A0.H = R2.H; A0 = ASHIFT A0 BY R1.L; / a0 = 0x00000000 / R3 = A0.w; / r5 = 0x00000000 / CHECKREG r3, 0x0258007C; R2.L = 15; A0.L = R3.L; A0.H = R3.H; A0 = ASHIFT A0 BY R2.L; / a0 = 0x00000000 / R4 = A0.w; / r5 = 0x00000000 / CHECKREG r4, 0x003E0000; R3.L = 31; A0.L = R4.L; A0.H = R4.H; A0 = ASHIFT A0 BY R3.L; / a0 = 0x00000000 / R5 = A0.w; / r5 = 0x00000000 / CHECKREG r5, 0x00000000; R4.L = -1; A0.L = R5.L; A0.H = R5.H; A0 = ASHIFT A0 BY R4.L; / a0 = 0x00000000 / R6 = A0.w; / r5 = 0x00000000 / CHECKREG r6, 0x00000000; R5.L = -16; A0 = 0; A0.L = R6.L; A0.H = R6.H; A0 = ASHIFT A0 BY R5.L; / a0 = 0x00000000 / R7 = A0.w; / r5 = 0x00000000 / CHECKREG r7, 0x00000000; R6.L = -31; A0.L = R7.L; A0.H = R7.H; A0 = ASHIFT A0 BY R6.L; / a0 = 0x00000000 / R0 = A0.w; / r5 = 0x00000000 / CHECKREG r0, 0x00000000; R7.L = -32; A0.L = R0.L; A0.H = R0.H; A0 = ASHIFT A0 BY R7.L; / a0 = 0x00000000 / R1 = A0.w; / r5 = 0x00000000 / CHECKREG r1, 0x00000000; imm32 r0, 0x12340000; imm32 r1, 0x028C003E; imm32 r2, 0x82159E24; imm32 r3, 0x82159E24; imm32 r4, 0xD259E268; imm32 r5, 0x52E26AF2; imm32 r6, 0x9226AF36; imm32 r7, 0xE26BFF86; R0.L = 0; A0 = 0; A0.L = R1.L; A0.H = R1.H; A0 = LSHIFT A0 BY R0.L; / a0 = 0x00000000 / R2 = A0.w; / r5 = 0x00000000 / CHECKREG r2, 0x028C003E; R1.L = 1; A0.L = R2.L; A0.H = R2.H; A0 = LSHIFT A0 BY R1.L; / a0 = 0x00000000 / R3 = A0.w; / r5 = 0x00000000 / CHECKREG r3, 0x0518007C; R2.L = 15; A0.L = R3.L; A0.H = R3.H; A0 = LSHIFT A0 BY R2.L; / a0 = 0x00000000 / R4 = A0.w; / r5 = 0x00000000 / CHECKREG r4, 0x003E0000; R3.L = 31; A0.L = R4.L; A0.H = R4.H; A0 = LSHIFT A0 BY R3.L; / a0 = 0x00000000 / R5 = A0.w; / r5 = 0x00000000 / CHECKREG r5, 0x00000000; R4.L = -1; A0.L = R5.L; A0.H = R5.H; A0 = LSHIFT A0 BY R4.L; / a0 = 0x00000000 / R6 = A0.w; / r5 = 0x00000000 / CHECKREG r6, 0x00000000; R5.L = -16; A0 = 0; A0.L = R6.L; A0.H = R6.H; A0 = LSHIFT A0 BY R5.L; / a0 = 0x00000000 / R7 = A0.w; / r5 = 0x00000000 / CHECKREG r7, 0x00000000; R6.L = -31; A0.L = R7.L; A0.H = R7.H; A0 = LSHIFT A0 BY R6.L; / a0 = 0x00000000 / R0 = A0.w; / r5 = 0x00000000 / CHECKREG r0, 0x00000000; R7.L = -32; A0.L = R0.L; A0.H = R0.H; A0 = LSHIFT A0 BY R7.L; / a0 = 0x00000000 / R1 = A0.w; / r5 = 0x00000000 / CHECKREG r1, 0x00000000; imm32 r0, 0x13340000; imm32 r1, 0x038C003E; imm32 r2, 0x83159E24; imm32 r3, 0x83159E24; imm32 r4, 0xD359E268; imm32 r5, 0x53E26AF2; imm32 r6, 0x9326AF36; imm32 r7, 0xE36BFF86; R0.L = 0; A0 = 0; A0.L = R1.L; A0.H = R1.H; A0 = ROT A0 BY R0.L; / a0 = 0x00000000 / R2 = A0.w; / r5 = 0x00000000 / CHECKREG r2, 0x038C003E; R1.L = 1; A0.L = R2.L; A0.H = R2.H; A0 = ROT A0 BY R1.L; / a0 = 0x00000000 / R3 = A0.w; / r5 = 0x00000000 / CHECKREG r3, 0x0718007C; R2.L = 15; A0.L = R3.L; A0.H = R3.H; A0 = ROT A0 BY R2.L; / a0 = 0x00000000 / R4 = A0.w; / r5 = 0x00000000 / CHECKREG r4, 0x003E0001; R3.L = 31; A0.L = R4.L; A0.H = R4.H; A0 = ROT A0 BY R3.L; / a0 = 0x00000000 / R5 = A0.w; / r5 = 0x00000000 / CHECKREG r5, 0xE3000F80; R4.L = -1; A0.L = R5.L; A0.H = R5.H; A0 = ROT A0 BY R4.L; / a0 = 0x00000000 / R6 = A0.w; / r5 = 0x00000000 / CHECKREG r6, 0x718007C0; R5.L = -16; A0.L = R6.L; A0.H = R6.H; A0 = ROT A0 BY R5.L; / a0 = 0x00000000 / R7 = A0.w; / r5 = 0x00000000 / CHECKREG r7, 0x80007180; R6.L = -31; A0.L = R7.L; A0.H = R7.H; A0 = ROT A0 BY R6.L; / a0 = 0x00000000 / R0 = A0.w; / r5 = 0x00000000 / CHECKREG r0, 0x01C6001F; R7.L = -32; A0.L = R0.L; A0.H = R0.H; A0 = ROT A0 BY R7.L; / a0 = 0x00000000 / R1 = A0.w; / r5 = 0x00000000 */ CHECKREG r1, 0x8C003E00; pass
tactcomplabs/xbgas-binutils-gdb	9,721	sim/testsuite/bfin/c_ldstii_ld_preg.s	//Original:testcases/core/c_ldstii_ld_preg/c_ldstii_ld_preg.dsp // Spec Reference: c_ldstii load preg # mach: bfin .include "testutils.inc" start // set all regs init_i_regs 0; init_b_regs 0; init_l_regs 0; init_m_regs 0; INIT_R_REGS 0; I0 = P3; I2 = SP; // initial values I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p1, DATA_ADDR_1, 0x00; loadsym p2, DATA_ADDR_2, 0x04; loadsym i1, DATA_ADDR_3, 0x04; loadsym p4, DATA_ADDR_1, 0x00; loadsym p5, DATA_ADDR_2, 0x00; loadsym fp, DATA_ADDR_3, 0x00; loadsym i3, DATA_ADDR_4, 0x00; P3 = I1; SP = I3; P2 = [ P1 + 0 ]; P3 = [ P1 + 4 ]; P4 = [ P1 + 8 ]; P5 = [ P1 + 12 ]; SP = [ P1 + 16 ]; FP = [ P1 + 20 ]; P1 = [ P1 + 24 ]; CHECKREG p1, 0x18191A1B; CHECKREG p2, 0x00010203; CHECKREG p3, 0x04050607; CHECKREG p4, 0x08090A0B; CHECKREG p5, 0x0C0D0E0F; CHECKREG sp, 0x10111213; CHECKREG fp, 0x14151617; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p2, DATA_ADDR_2, 0x04; P3 = I1; SP = I3; P1 = [ P2 + 28 ]; P3 = [ P2 + 36 ]; P4 = [ P2 + 40 ]; P5 = [ P2 + 44 ]; SP = [ P2 + 48 ]; FP = [ P2 + 52 ]; P2 = [ P2 + 32 ]; CHECKREG p1, 0x91929394; CHECKREG p2, 0x95969798; CHECKREG p3, 0x99A1A2A3; CHECKREG p4, 0xA5A6A7A8; CHECKREG p5, 0xA9B0B1B2; CHECKREG sp, 0xB3B4B5B6; CHECKREG fp, 0xB7B8B9C0; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym i1, DATA_ADDR_3, 0x00; P3 = I1; SP = I3; P1 = [ P3 + 56 ]; P2 = [ P3 + 60 ]; P4 = [ P3 + 60 ]; P5 = [ P3 + 56 ]; SP = [ P3 + 52 ]; FP = [ P3 + 48 ]; P3 = [ P3 + 64 ]; CHECKREG p1, 0xE3E4E5E6; CHECKREG p2, 0x91E899EA; CHECKREG p3, 0x92E899EA; CHECKREG p4, 0x91E899EA; CHECKREG p5, 0xE3E4E5E6; CHECKREG sp, 0xDFE0E1E2; CHECKREG fp, 0xDBDCDDDE; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p4, DATA_ADDR_4, 0x00; P3 = I1; SP = I3; P1 = [ P4 + 44 ]; P2 = [ P4 + 40 ]; P3 = [ P4 + 36 ]; P5 = [ P4 + 28 ]; SP = [ P4 + 24 ]; FP = [ P4 + 20 ]; P4 = [ P4 + 32 ]; CHECKREG p1, 0xFBFCFDFE; CHECKREG p2, 0xF7F8F9FA; CHECKREG p3, 0xF3F4F5F6; CHECKREG p4, 0xEBECEDEE; CHECKREG p5, 0x7C7D7E7F; CHECKREG sp, 0x78797A7B; CHECKREG fp, 0x74757677; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_1, 0x00; P3 = I1; SP = I3; P1 = [ P5 + 16 ]; P2 = [ P5 + 12 ]; P3 = [ P5 + 8 ]; P4 = [ P5 + 0 ]; SP = [ P5 + 4 ]; FP = [ P5 + 8 ]; P5 = [ P5 + 4 ]; CHECKREG p1, 0x10111213; CHECKREG p2, 0x0C0D0E0F; CHECKREG p3, 0x08090A0B; CHECKREG p4, 0x00010203; CHECKREG p5, 0x04050607; CHECKREG sp, 0x04050607; CHECKREG fp, 0x08090A0B; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym i3, DATA_ADDR_2, 0x00; P3 = I1; SP = I3; P1 = [ SP + 12 ]; P2 = [ SP + 16 ]; P3 = [ SP + 20 ]; P4 = [ SP + 24 ]; P5 = [ SP + 28 ]; FP = [ SP + 32 ]; SP = [ SP + 36 ]; CHECKREG p1, 0x2C2D2E2F; CHECKREG p2, 0x30313233; CHECKREG p3, 0x34353637; CHECKREG p4, 0x38393A3B; CHECKREG p5, 0x3C3D3E3F; CHECKREG sp, 0x95969798; CHECKREG fp, 0x91929394; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym fp, DATA_ADDR_3, 0x00; P3 = I1; SP = I3; P1 = [ FP + 40 ]; P2 = [ FP + 44 ]; P3 = [ FP + 48 ]; P4 = [ FP + 52 ]; P5 = [ FP + 56 ]; SP = [ FP + 60 ]; FP = [ FP + 64 ]; CHECKREG p1, 0xD3D4D5D6; CHECKREG p2, 0xD7D8D9DA; CHECKREG p3, 0xDBDCDDDE; CHECKREG p4, 0xDFE0E1E2; CHECKREG p5, 0xE3E4E5E6; CHECKREG sp, 0x91E899EA; CHECKREG fp, 0x92E899EA; P3 = I0; SP = I2; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x11223344 .dd 0x55667788 .dd 0x99717273 .dd 0x74757677 .dd 0x82838485 .dd 0x86878889 .dd 0x80818283 .dd 0x84858687 .dd 0x01020304 .dd 0x05060708 .dd 0x09101112 .dd 0x14151617 .dd 0x18192021 .dd 0x22232425 .dd 0x26272829 .dd 0x30313233 .dd 0x34353637 .dd 0x38394041 .dd 0x42434445 .dd 0x46474849 .dd 0x50515253 .dd 0x54555657 .dd 0x58596061 .dd 0x62636465 .dd 0x66676869 .dd 0x74555657 .dd 0x78596067 .dd 0x72636467 .dd 0x76676867 DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x91929394 .dd 0x95969798 .dd 0x99A1A2A3 .dd 0xA5A6A7A8 .dd 0xA9B0B1B2 .dd 0xB3B4B5B6 .dd 0xB7B8B9C0 .dd 0x70717273 .dd 0x74757677 .dd 0x78798081 .dd 0x82838485 .dd 0x86C283C4 .dd 0x81C283C4 .dd 0x82C283C4 .dd 0x83C283C4 .dd 0x84C283C4 .dd 0x85C283C4 .dd 0x86C283C4 .dd 0x87C288C4 .dd 0x88C283C4 .dd 0x89C283C4 .dd 0x80C283C4 .dd 0x81C283C4 .dd 0x82C288C4 .dd 0x94555659 .dd 0x98596069 .dd 0x92636469 .dd 0x96676869 DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0xC5C6C7C8 .dd 0xC9CACBCD .dd 0xCFD0D1D2 .dd 0xD3D4D5D6 .dd 0xD7D8D9DA .dd 0xDBDCDDDE .dd 0xDFE0E1E2 .dd 0xE3E4E5E6 .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x97E899EA .dd 0x98E899EA .dd 0x99E899EA .dd 0x91E899EA .dd 0x92E899EA .dd 0x93E899EA .dd 0x94E899EA .dd 0x95E899EA .dd 0x96E899EA .dd 0x977899EA .dd 0xa455565a .dd 0xa859606a .dd 0xa263646a .dd 0xa667686a DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xA50CAD6E .dd 0xA60CAD7E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0xEBECEDEE .dd 0xF3F4F5F6 .dd 0xF7F8F9FA .dd 0xFBFCFDFE .dd 0xFF000102 .dd 0x03040506 .dd 0x0708090A .dd 0x0B0CAD0E .dd 0xAB0CAD01 .dd 0xAB0CAD02 .dd 0xAB0CAD03 .dd 0xAB0CAD04 .dd 0xAB0CAD05 .dd 0xAB0CAD06 .dd 0xAB0CAA07 .dd 0xAB0CAD08 .dd 0xAB0CAD09 .dd 0xA00CAD1E .dd 0xA10CAD2E .dd 0xA20CAD3E .dd 0xA30CAD4E .dd 0xA40CAD5E .dd 0xA50CAD6E .dd 0xA60CAD7E .dd 0xB455565B .dd 0xB859606B .dd 0xB263646B .dd 0xB667686B DATA_ADDR_5: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0x0F101213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0xBC0DBE21 .dd 0xBC1DBE22 .dd 0xBC2DBE23 .dd 0xBC3DBE24 .dd 0xBC4DBE65 .dd 0xBC5DBE27 .dd 0xBC6DBE28 .dd 0xBC7DBE29 .dd 0xBC8DBE2F .dd 0xBC9DBE20 .dd 0xBCADBE21 .dd 0xBCBDBE2F .dd 0xBCCDBE23 .dd 0xBCDDBE24 .dd 0xBCFDBE25 .dd 0xC455565C .dd 0xC859606C .dd 0xC263646C .dd 0xC667686C .dd 0xCC0DBE2C DATA_ADDR_6: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F DATA_ADDR_7: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF
tactcomplabs/xbgas-binutils-gdb	2,025	sim/testsuite/bfin/c_ldimmhalf_lzhi_dr.s	//Original:/testcases/core/c_ldimmhalf_lzhi_dr/c_ldimmhalf_lzhi_dr.dsp // Spec Reference: ldimmhalf lz & hi dreg # mach: bfin .include "testutils.inc" start INIT_R_REGS -1; // test Dreg R0 = 0x0001 (Z); R0.H = 0x0000; R1 = 0x0003 (Z); R1.H = 0x0002; R2 = 0x0005 (Z); R2.H = 0x0004; R3 = 0x0007 (Z); R3.H = 0x0006; R4 = 0x0009 (Z); R4.H = 0x0008; R5 = 0x000b (Z); R5.H = 0x000a; R6 = 0x000d (Z); R6.H = 0x000c; R7 = 0x000f (Z); R7.H = 0x000e; CHECKREG r0, 0x00000001; CHECKREG r1, 0x00020003; CHECKREG r2, 0x00040005; CHECKREG r3, 0x00060007; CHECKREG r4, 0x00080009; CHECKREG r5, 0x000a000b; CHECKREG r6, 0x000c000d; CHECKREG r7, 0x000e000f; R0 = 0x0010 (Z); R0.H = 0x0000; R1 = 0x0030 (Z); R1.H = 0x0020; R2 = 0x0050 (Z); R2.H = 0x0040; R3 = 0x0070 (Z); R3.H = 0x0060; R4 = 0x0090 (Z); R4.H = 0x0080; R5 = 0x00b0 (Z); R5.H = 0x00a0; R6 = 0x00d0 (Z); R6.H = 0x00c0; R7 = 0x00f0 (Z); R7.H = 0x00e0; CHECKREG r0, 0x00000010; CHECKREG r1, 0x00200030; CHECKREG r2, 0x00400050; CHECKREG r3, 0x00600070; CHECKREG r4, 0x00800090; CHECKREG r5, 0x00a000b0; CHECKREG r6, 0x00c000d0; CHECKREG r7, 0x00e000f0; R0 = 0x0100 (Z); R0.H = 0x0000; R1 = 0x0300 (Z); R1.H = 0x0200; R2 = 0x0500 (Z); R2.H = 0x0400; R3 = 0x0700 (Z); R3.H = 0x0600; R4 = 0x0900 (Z); R4.H = 0x0800; R5 = 0x0b00 (Z); R5.H = 0x0a00; R6 = 0x0d00 (Z); R6.H = 0x0c00; R7 = 0x0f00 (Z); R7.H = 0x0e00; CHECKREG r0, 0x00000100; CHECKREG r1, 0x02000300; CHECKREG r2, 0x04000500; CHECKREG r3, 0x06000700; CHECKREG r4, 0x08000900; CHECKREG r5, 0x0a000b00; CHECKREG r6, 0x0c000d00; CHECKREG r7, 0x0e000f00; R0 = 0x1000 (Z); R0.H = 0x0000; R1 = 0x3000 (Z); R1.H = 0x2000; R2 = 0x5000 (Z); R2.H = 0x4000; R3 = 0x7000 (Z); R3.H = 0x6000; R4 = 0x9000 (Z); R4.H = 0x8000; R5 = 0xb000 (Z); R5.H = 0xa000; R6 = 0xd000 (Z); R6.H = 0xc000; R7 = 0xf000 (Z); R7.H = 0xe000; CHECKREG r0, 0x00001000; CHECKREG r1, 0x20003000; CHECKREG r2, 0x40005000; CHECKREG r3, 0x60007000; CHECKREG r4, 0x80009000; CHECKREG r5, 0xa000b000; CHECKREG r6, 0xc000d000; CHECKREG r7, 0xe000f000; pass
tactcomplabs/xbgas-binutils-gdb	3,795	sim/testsuite/bfin/c_ccflag_dr_imm3.s	//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp // Spec Reference: ccflag dr-imm3 # mach: bfin .include "testutils.inc" start imm32 r0, 0x00000001; imm32 r1, 0x00000002; imm32 r2, 0x00000003; imm32 r3, 0x00000004; imm32 r4, 0x00770088; imm32 r5, 0x009900aa; imm32 r6, 0x00bb00cc; imm32 r7, 0x00000000; ASTAT = R7; R4 = ASTAT; // positive dreg EQUAL to positive imm3 CC = R0 == 1; R5 = ASTAT; CC = R0 < 1; R6 = ASTAT; CHECKREG r4, 0x00000000; CHECKREG r5, 0x00001025; CHECKREG r6, 0x00001005; CC = R0 <= 1; R5 = ASTAT; CC = R0 < 1; R6 = ASTAT; CC = R0 <= 1; R7 = ASTAT; CHECKREG r5, 0x00001025; CHECKREG r6, 0x00001005; CHECKREG r7, 0x00001025; // positive dreg GREATER than to positive imm3 CC = R1 == 1; R5 = ASTAT; CC = R1 < 1; R6 = ASTAT; CC = R1 <= 1; R7 = ASTAT; CHECKREG r5, 0x00001004; // carry CHECKREG r6, 0x00001004; CHECKREG r7, 0x00001004; // positive dreg LESS than to positive imm3 CC = R0 == 2; R5 = ASTAT; CC = R0 < 2; R6 = ASTAT; CC = R0 <= 2; R7 = ASTAT; CHECKREG r5, 0x00000002; CHECKREG r6, 0x00000022; CHECKREG r7, 0x00000022; // positive dreg GREATER than to neg imm3 CC = R2 == -4; R5 = ASTAT; CC = R2 < -4; R6 = ASTAT; CC = R2 <= -4; R7 = ASTAT; CHECKREG r5, 0x00000000; CHECKREG r6, 0x00000000; CHECKREG r7, 0x00000000; imm32 r0, -1; imm32 r1, -2; imm32 r2, -3; imm32 r3, -4; // negative dreg and positive imm3 R7 = 0; ASTAT = R7; R4 = ASTAT; CC = R3 == 1; R5 = ASTAT; CC = R3 < 1; R6 = ASTAT; CC = R3 <= 1; R7 = ASTAT; CHECKREG r4, 0x00000000; CHECKREG r5, 0x00001006; CHECKREG r6, 0x00001026; CHECKREG r7, 0x00001026; // negative dreg LESS than neg imm3 CC = R2 == -1; R4 = ASTAT; CC = R2 < -1; R5 = ASTAT; CC = R2 <= -1; R6 = ASTAT; CHECKREG r4, 0x00000002; CHECKREG r5, 0x00000022; CHECKREG r6, 0x00000022; // negative dreg GREATER neg imm3 CC = R0 == -4; R4 = ASTAT; CC = R0 < -4; R5 = ASTAT; CC = R0 <= -4; R6 = ASTAT; CHECKREG r4, 0x00001004; CHECKREG r5, 0x00001004; CHECKREG r6, 0x00001004; imm32 r0, 0x00000000; imm32 r1, 0x00000000; imm32 r2, 0x00000000; imm32 r3, 0x00000000; imm32 r4, 0x00000001; imm32 r5, 0x00000002; imm32 r6, 0x00000003; imm32 r7, 0x00000004; ASTAT = R0; R3 = ASTAT; // positive dreg EQUAL to positive imm3 CC = R4 == 1; R1 = ASTAT; CC = R4 < 1; R2 = ASTAT; CHECKREG r0, 0x00000000; CHECKREG r1, 0x00001025; CHECKREG r2, 0x00001005; CC = R4 <= 1; R1 = ASTAT; CC = R4 < 1; R2 = ASTAT; CC = R4 <= 1; R3 = ASTAT; CHECKREG r1, 0x00001025; CHECKREG r2, 0x00001005; CHECKREG r3, 0x00001025; // positive dreg GREATER than to positive imm3 CC = R5 == 1; R1 = ASTAT; CC = R5 < 1; R2 = ASTAT; CC = R5 <= 1; R3 = ASTAT; CHECKREG r1, 0x00001004; // carry CHECKREG r2, 0x00001004; CHECKREG r3, 0x00001004; // positive dreg LESS than to positive imm3 CC = R6 == 2; R1 = ASTAT; CC = R6 < 2; R2 = ASTAT; CC = R6 <= 2; R3 = ASTAT; CHECKREG r1, 0x00001004; CHECKREG r2, 0x00001004; CHECKREG r3, 0x00001004; // positive dreg GREATER than to neg imm3 CC = R6 == -4; R1 = ASTAT; CC = R6 < -4; R2 = ASTAT; CC = R6 <= -4; R3 = ASTAT; CHECKREG r1, 0x00000000; CHECKREG r2, 0x00000000; CHECKREG r3, 0x00000000; imm32 r4, -1; imm32 r5, -2; imm32 r6, -3; imm32 r7, -4; // negative dreg and positive imm3 R3 = 0; ASTAT = R3; R0 = ASTAT; CC = R7 == 1; R1 = ASTAT; CC = R7 < 1; R2 = ASTAT; CC = R7 <= 1; R3 = ASTAT; CHECKREG r0, 0x00000000; CHECKREG r1, 0x00001006; CHECKREG r2, 0x00001026; CHECKREG r3, 0x00001026; // negative dreg LESS than neg imm3 CC = R6 == -1; R0 = ASTAT; CC = R6 < -1; R1 = ASTAT; CC = R6 <= -1; R2 = ASTAT; CHECKREG r0, 0x00000002; CHECKREG r1, 0x00000022; CHECKREG r2, 0x00000022; // negative dreg GREATER neg imm3 CC = R4 == -4; R0 = ASTAT; CC = R4 < -4; R1 = ASTAT; CC = R4 <= -4; R2 = ASTAT; CHECKREG r0, 0x00001004; CHECKREG r1, 0x00001004; CHECKREG r2, 0x00001004; pass;
tactcomplabs/xbgas-binutils-gdb	6,094	sim/testsuite/bfin/c_dsp32mult_dr_u.s	//Original:/testcases/core/c_dsp32mult_dr_u/c_dsp32mult_dr_u.dsp // Spec Reference: dsp32mult single dr u # mach: bfin .include "testutils.inc" start imm32 r0, 0x8b235625; imm32 r1, 0x98ba5127; imm32 r2, 0xa3846725; imm32 r3, 0x00080027; imm32 r4, 0xb0ab8d29; imm32 r5, 0x10ace82b; imm32 r6, 0xc00c008d; imm32 r7, 0xd2467028; R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (FU); R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (FU); R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (FU); R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (FU); R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (FU); R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (FU); R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (FU); R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (FU); CHECKREG r0, 0x1CFD1CFD; CHECKREG r1, 0x0930114B; CHECKREG r2, 0x01F5010A; CHECKREG r3, 0x012B0054; CHECKREG r4, 0x1CFD1CFD; CHECKREG r5, 0x1B4F3365; CHECKREG r6, 0x1B4F3365; CHECKREG r7, 0x19BA5B1D; imm32 r0, 0x9923a635; imm32 r1, 0x6f995137; imm32 r2, 0x1324b735; imm32 r3, 0x99060037; imm32 r4, 0x809bcd39; imm32 r5, 0xb0a99f3b; imm32 r6, 0xa00c093d; imm32 r7, 0x12467093; R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (FU); R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (FU); R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (FU); R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (FU); R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (FU); R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (FU); R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (FU); R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (FU); CHECKREG r0, 0x00700070; CHECKREG r1, 0x00430043; CHECKREG r2, 0x0DB30DB3; CHECKREG r3, 0x08300830; CHECKREG r4, 0x0DB30DB3; CHECKREG r5, 0x6D830B71; CHECKREG r6, 0x00270004; CHECKREG r7, 0x00210021; imm32 r0, 0x19235655; imm32 r1, 0xc9ba5157; imm32 r2, 0x63246755; imm32 r3, 0x0a060055; imm32 r4, 0x90abc509; imm32 r5, 0x10acef5b; imm32 r6, 0xb00a005d; imm32 r7, 0x1246a05f; R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (FU); R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (FU); R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (FU); R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (FU); R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (FU); R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (FU); R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (FU); R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (FU); CHECKREG r0, 0x6F5997A7; CHECKREG r1, 0x87430CD5; CHECKREG r2, 0x0CD50CD5; CHECKREG r3, 0xDFCB0116; CHECKREG r4, 0x6F5997A7; CHECKREG r5, 0x681C8DCB; CHECKREG r6, 0x53FF3DAC; CHECKREG r7, 0x39AA2A57; imm32 r0, 0xb9235666; imm32 r1, 0xefba5166; imm32 r2, 0x19248766; imm32 r3, 0xe0960066; imm32 r4, 0x9ea99d69; imm32 r5, 0x10ec9f6b; imm32 r6, 0x800e906d; imm32 r7, 0x12467e6f; // test the unsigned U=1 R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (FU); R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (FU); R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (FU); R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (FU); R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (FU); R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (FU); R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (FU); R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (FU); CHECKREG r0, 0x400E517B; CHECKREG r1, 0x09240A4F; CHECKREG r2, 0x09240A4F; CHECKREG r3, 0x014E014E; CHECKREG r4, 0x01250174; CHECKREG r5, 0x00150015; CHECKREG r6, 0x400E517B; CHECKREG r7, 0x049205D1; // mix order imm32 r0, 0x9923a675; imm32 r1, 0xcf995127; imm32 r2, 0x13c49705; imm32 r3, 0x05069007; imm32 r4, 0x90accd09; imm32 r5, 0x10ac9fdb; imm32 r6, 0x000cc90d; imm32 r7, 0x1246fc9f; R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (FU); R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (FU); R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (FU); R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (FU); R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (FU); R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (FU); R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (FU); R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (FU); CHECKREG r0, 0xA4430AEE; CHECKREG r1, 0x3FBC0004; CHECKREG r2, 0x0C580C58; CHECKREG r3, 0x735B735B; CHECKREG r4, 0x5C645C64; CHECKREG r5, 0x00CE00CE; CHECKREG r6, 0x00030003; CHECKREG r7, 0x00C80BBA; imm32 r0, 0xab235a75; imm32 r1, 0xcfba5127; imm32 r2, 0xdd246905; imm32 r3, 0x00d6d007; imm32 r4, 0x90abcd09; imm32 r5, 0x10aceddb; imm32 r6, 0x000c0d0d; imm32 r7, 0x1246700f; R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (FU); R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (FU); R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (FU); R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (FU); R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (FU); R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (FU); R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (FU); R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (FU); CHECKREG r0, 0x0C370675; CHECKREG r1, 0x000A0423; CHECKREG r2, 0x0E6706D7; CHECKREG r3, 0x0079758F; CHECKREG r4, 0x00440061; CHECKREG r5, 0x00F00D62; CHECKREG r6, 0x00000001; CHECKREG r7, 0x007600DF; imm32 r0, 0xee235675; imm32 r1, 0xcfea5127; imm32 r2, 0x13fe6705; imm32 r3, 0x000fe007; imm32 r4, 0x90abfe09; imm32 r5, 0x10acefeb; imm32 r6, 0x000c00fe; imm32 r7, 0x1246700f; R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (FU); R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (FU); R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (FU); R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (FU); R4.H = R4.L * R2.L, R4.L = R4.L * R2.H (FU); R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (FU); R6.H = R6.H * R5.L, R6.L = R6.L * R5.H (FU); R7.H = R7.L * R4.L, R7.L = R7.H * R4.H (FU); CHECKREG r0, 0x00010050; CHECKREG r1, 0x1CDA0C0D; CHECKREG r2, 0x00560004; CHECKREG r3, 0x0ED75B03; CHECKREG r4, 0x00040055; CHECKREG r5, 0x0DE805ED; CHECKREG r6, 0x0000000E; CHECKREG r7, 0x00250000; imm32 r0, 0xfb2d5675; imm32 r1, 0xcfbad127; imm32 r2, 0x13f46d05; imm32 r3, 0x000f00d7; imm32 r4, 0x908bfd09; imm32 r5, 0x10a9efdb; imm32 r6, 0x000c5f0d; imm32 r7, 0x124676ff; R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (FU); R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (FU); R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (FU); R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (FU); R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (FU); R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (FU); R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (FU); R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (FU); CHECKREG r0, 0x08B12F7B; CHECKREG r1, 0x03172C7C; CHECKREG r2, 0x00010000; CHECKREG r3, 0x00280007; CHECKREG r4, 0x662512B2; CHECKREG r5, 0x00000000; CHECKREG r6, 0x00000006; CHECKREG r7, 0x11C0003A; pass
tactcomplabs/xbgas-binutils-gdb	1,469	sim/testsuite/bfin/c_ldimmhalf_l_pr.s	//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_pr/c_ldimmhalf_l_pr.dsp // Spec Reference: ldimmhalf l preg # mach: bfin .include "testutils.inc" start INIT_R_REGS -1; INIT_P_REGS -1; imm32 sp, 0xffffffff; imm32 fp, 0xffffffff; // test Preg P1.L = 0x0003; P2.L = 0x0005; P3.L = 0x0007; P4.L = 0x0009; P5.L = 0x000b; FP.L = 0x000d; SP.L = 0x000f; CHECKREG p1, 0xffff0003; CHECKREG p2, 0xffff0005; CHECKREG p3, 0xffff0007; CHECKREG p4, 0xffff0009; CHECKREG p5, 0xffff000b; CHECKREG fp, 0xffff000d; CHECKREG sp, 0xffff000f; P1.L = 0x0030; P2.L = 0x0050; P3.L = 0x0070; P4.L = 0x0090; P5.L = 0x00b0; FP.L = 0x00d0; SP.L = 0x00f0; //CHECKREG p0, 0x00000010; CHECKREG p1, 0xffff0030; CHECKREG p2, 0xffff0050; CHECKREG p3, 0xffff0070; CHECKREG p4, 0xffff0090; CHECKREG p5, 0xffff00b0; CHECKREG fp, 0xffff00d0; CHECKREG sp, 0xffff00f0; P1.L = 0x0300; P2.L = 0x0500; P3.L = 0x0700; P4.L = 0x0900; P5.L = 0x0b00; FP.L = 0x0d00; SP.L = 0x0f00; CHECKREG p1, 0xffff0300; CHECKREG p2, 0xffff0500; CHECKREG p3, 0xffff0700; CHECKREG p4, 0xffff0900; CHECKREG p5, 0xffff0b00; CHECKREG fp, 0xffff0d00; CHECKREG sp, 0xffff0f00; P1.L = 0x3000; P2.L = 0x5000; P3.L = 0x7000; P4.L = 0x9000; P5.L = 0xb000; FP.L = 0xd000; SP.L = 0xf000; CHECKREG p1, 0xffff3000; CHECKREG p2, 0xffff5000; CHECKREG p3, 0xffff7000; CHECKREG p4, 0xffff9000; CHECKREG p5, 0xffffb000; CHECKREG fp, 0xffffd000; CHECKREG sp, 0xfffff000; pass
tactcomplabs/xbgas-binutils-gdb	7,255	sim/testsuite/bfin/c_seq_ex2_brcc_mp_mv_pop.S	//Original:/proj/frio/dv/testcases/core/c_seq_ex2_brcc_mp_mv_pop/c_seq_ex2_brcc_mp_mv_pop.dsp // Spec Reference: sequencer stage ex2 ( brcc (mis-pred)+ regmv + pushpopmultiple) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE DATA_ADDR_1 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK CSYNC; DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! R0 = 0; ASTAT = R0; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; LD32(p1, 0x12345678); LD32(p2, 0x05612496); LD32(p3, 0xab5fd490); LD32(p4, 0xa581bd94); [ -- SP ] = ( R7:0 ); // RAISE 2; // RTN IF CC JUMP LABEL1 (BP); P1 = R1; R2 = P1; [ -- SP ] = ( R7:0 ); R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; LABEL1: // RAISE 5; // RTI P2 = R2; R3 = P2; [ -- SP ] = ( R7:0 ); R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; // RAISE 6; // RTI IF !CC JUMP LABEL2 (BP); P3 = R3; R4 = P3; [ -- SP ] = ( R7:0 ); // POP R0 = 0x00; R1 = 0x00; R2 = 0x00; R3 = 0x00; R4 = 0x00; R5 = 0x00; R6 = 0x00; R7 = 0x00; LABEL2: // RAISE 7; // RTI IF CC JUMP LABEL4 (BP); // SHOULD NOT EXECUTE P4 = R4; R5 = P4; ( R7:0 ) = [ SP ++ ]; LABEL4: CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000012); CHECKREG(r2, 0x00000013); CHECKREG(r3, 0x00000013); CHECKREG(r4, 0x00000015); CHECKREG(r5, 0x00000016); CHECKREG(r6, 0x00000017); CHECKREG(r7, 0x00000018); // RAISE 8; // RTI IF !CC JUMP LABEL3 (BP); P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; //CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped //CHECKREG(r1, 0x000000b2); // so they cannot appear here //CHECKREG(r2, 0x000000c3); //CHECKREG(r3, 0x000000d4); //CHECKREG(r4, 0x000000e5); //CHECKREG(r5, 0x000000f6); //CHECKREG(r6, 0x00000017); //CHECKREG(r7, 0x00000028); R0 = 12; R1 = 13; R2 = 14; R3 = 15; R4 = 16; R5 = 17; R6 = 18; R7 = 19; LABEL3: // RAISE 9; // RTI P2 = R6; R7 = P2; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000002); CHECKREG(r3, 0x00000004); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG(r0, 0x00000000); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x00000000); CHECKREG(r3, 0x00000000); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 I0 += 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 I1 += 2; RTI; THANDLE: // Timer Handler 6 I2 += 2; RTI; I7HANDLE: // IVG 7 Handler I3 += 2; RTI; I8HANDLE: // IVG 8 Handler I0 += 2; RTI; I9HANDLE: // IVG 9 Handler I0 += 2; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .data DATA: .space (0x10); // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	1,209	sim/testsuite/bfin/c_ccmv_ncc_dr_pr.s	//Original:/proj/frio/dv/testcases/core/c_ccmv_ncc_dr_pr/c_ccmv_ncc_dr_pr.dsp // Spec Reference: ccmv !cc dpreg = dpreg # mach: bfin .include "testutils.inc" start R0 = 0; ASTAT = R0; imm32 r0, 0x138d2301; imm32 r1, 0x20421053; imm32 r2, 0x3f051405; imm32 r3, 0x40b66507; imm32 r4, 0x50487709; imm32 r5, 0x6005908b; imm32 r6, 0x7a0c6609; imm32 r7, 0x890e108f; imm32 p1, 0x9d021053; imm32 p2, 0xafb41405; imm32 p3, 0xb0bf1507; imm32 p4, 0xd0483609; imm32 p5, 0xe005d00b; imm32 sp, 0xfa0c667d; imm32 fp, 0xc90e108f; IF !CC R0 = P0; CC = ! CC; IF !CC P1 = R3; IF !CC R2 = P5; IF !CC P2 = R2; IF !CC P3 = R6; IF !CC R5 = P1; CC = ! CC; IF !CC P4 = R7; IF !CC R7 = P4; IF !CC P5 = R3; IF !CC R6 = SP; CC = ! CC; IF !CC R3 = P2; IF !CC SP = R6; IF !CC R1 = P5; CC = ! CC; IF !CC FP = R4; IF !CC R3 = P3; CHECKREG r1, 0x20421053; CHECKREG r2, 0x3F051405; CHECKREG r3, 0xB0BF1507; CHECKREG r4, 0x50487709; CHECKREG r5, 0x6005908B; CHECKREG r6, 0xFA0C667D; CHECKREG r7, 0x890E108F; CHECKREG p1, 0x9D021053; CHECKREG p2, 0xAFB41405; CHECKREG p3, 0xB0BF1507; CHECKREG p4, 0x890E108F; CHECKREG p5, 0x40B66507; CHECKREG sp, 0xFA0C667D; CHECKREG fp, 0x50487709; pass
tactcomplabs/xbgas-binutils-gdb	4,824	sim/testsuite/bfin/random_0032.S	# mach: bfin #include "test.h" .include "testutils.inc" start dmm32 ASTAT, (0x74308400 \| _VS \| _AV1S \| _AV0S \| _CC \| _AN); dmm32 A0.w, 0x5d4cf98c; dmm32 A0.x, 0xffffffff; imm32 R0, 0xba16ffff; imm32 R4, 0x8000109d; imm32 R6, 0x8000b212; R6.L = (A0 -= R4.L * R0.L) (IH); checkreg R6, 0x80008000; checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x74308400 \| _VS \| _V \| _AV1S \| _AV0S \| _AV0 \| _CC \| _V_COPY \| _AN); dmm32 ASTAT, (0x34e0ce80 \| _VS \| _V \| _AV1S \| _V_COPY \| _AN); dmm32 A0.w, 0x64bb88af; dmm32 A0.x, 0xffffffff; imm32 R5, 0x00008000; imm32 R7, 0x0001ad69; R5.L = (A0 += R7.H * R7.L) (IH); checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x34e0ce80 \| _VS \| _V \| _AV1S \| _AV0S \| _AV0 \| _V_COPY \| _AN); dmm32 ASTAT, (0x4c204c10 \| _VS \| _V \| _AV0S \| _AQ \| _V_COPY \| _AN); dmm32 A1.w, 0x75642aaf; dmm32 A1.x, 0xffffffff; imm32 R2, 0x133dffff; imm32 R4, 0xc00006aa; imm32 R7, 0x7fffffff; R4.H = (A1 -= R2.L * R7.H) (IH); checkreg R4, 0x800006aa; checkreg A1.w, 0x80000000; checkreg A1.x, 0xffffffff; checkreg ASTAT, (0x4c204c10 \| _VS \| _V \| _AV1S \| _AV1 \| _AV0S \| _AQ \| _V_COPY \| _AN); dmm32 ASTAT, (0x48600400 \| _VS \| _V \| _AV0S \| _AC1 \| _AC0 \| _CC \| _V_COPY \| _AN); dmm32 A0.w, 0x534a596c; dmm32 A0.x, 0xffffffff; imm32 R1, 0x7fff86a7; imm32 R5, 0x1163d244; R1.L = (A0 -= R5.L * R1.L) (IH); checkreg R1, 0x7fff8000; checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x48600400 \| _VS \| _V \| _AV0S \| _AV0 \| _AC1 \| _AC0 \| _CC \| _V_COPY \| _AN); dmm32 ASTAT, (0x38008c90 \| _VS \| _V \| _AV1S \| _AC1 \| _CC \| _V_COPY \| _AN); dmm32 A1.w, 0x80000000; dmm32 A1.x, 0xffffffff; imm32 R0, 0x7fffffff; imm32 R1, 0xdee9214c; imm32 R4, 0x79f3c80a; R1.H = (A1 += R0.L * R4.H) (M, IH); checkreg R1, 0x8000214c; checkreg ASTAT, (0x38008c90 \| _VS \| _AV1S \| _AV1 \| _AC1 \| _CC \| _AN); dmm32 ASTAT, (0x4cb00a00 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AN); dmm32 A0.w, 0x804e7e2f; dmm32 A0.x, 0xffffffff; imm32 R1, 0x3fccdf09; imm32 R2, 0x09e71015; imm32 R6, 0x761ac984; R2.L = (A0 += R6.L * R1.H) (IH); checkreg R2, 0x09e78000; checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x4cb00a00 \| _VS \| _V \| _AV1S \| _AV0S \| _AV0 \| _AC1 \| _V_COPY \| _AN); dmm32 ASTAT, (0x08904c00 \| _VS \| _AV0S \| _AQ \| _AZ); dmm32 A0.w, 0x00000000; dmm32 A0.x, 0x00000000; imm32 R1, 0x80000000; imm32 R2, 0x0001de54; imm32 R5, 0x80000000; R1.L = (A0 -= R5.H * R2.H) (TFU); checkreg ASTAT, (0x08904c00 \| _VS \| _V \| _AV0S \| _AV0 \| _AQ \| _V_COPY \| _AZ); checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg R1, 0x80000000; checkreg R2, 0x0001de54; checkreg R5, 0x80000000; dmm32 ASTAT, (0x00d04810 \| _VS \| _AV0S \| _CC \| _AC0_COPY \| _AZ); dmm32 A0.w, 0x00000000; dmm32 A0.x, 0x00000000; imm32 R4, 0x00020000; imm32 R5, 0x35a26677; R4.L = (A0 -= R5.H * R4.H) (TFU); checkreg ASTAT, (0x00d04810 \| _VS \| _V \| _AV0S \| _AV0 \| _CC \| _V_COPY \| _AC0_COPY \| _AZ); checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg R4, 0x00020000; checkreg R5, 0x35a26677; dmm32 ASTAT, (0x08100a80 \| _VS \| _AV0S \| _AQ \| _CC); dmm32 A0.w, 0x00000000; dmm32 A0.x, 0x00000000; imm32 R0, 0x000300cc; imm32 R4, 0x00029150; imm32 R7, 0x00ff00ff; R4.L = (A0 -= R0.L * R7.L) (IU); checkreg R4, 0x00020000; checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg ASTAT, (0x08100a80 \| _VS \| _V \| _AV0S \| _AV0 \| _AQ \| _CC \| _V_COPY); dmm32 ASTAT, (0x6c20c400 \| _VS \| _AV1S \| _AV0S \| _CC); dmm32 A0.w, 0x860c9ac9; dmm32 A0.x, 0xffffffff; imm32 R2, 0x860c9a1b; R2.L = (A0 -= R2.H * R2.L) (IH); checkreg R2, 0x860c8000; checkreg A0.w, 0x80000000; checkreg A0.x, 0xffffffff; checkreg ASTAT, (0x6c20c400 \| _VS \| _V \| _AV1S \| _AV0S \| _AV0 \| _CC \| _V_COPY); dmm32 ASTAT, (0x20f00c10 \| _VS \| _AV0S \| _AQ); dmm32 A0.w, 0x0000de90; dmm32 A0.x, 0x00000000; imm32 R0, 0x00000003; imm32 R1, 0xfffd8000; imm32 R5, 0x4a31921c; R1.L = (A0 -= R5.L * R0.L) (FU); checkreg R1, 0xfffd0000; checkreg A0.w, 0x00000000; checkreg A0.x, 0x00000000; checkreg ASTAT, (0x20f00c10 \| _VS \| _V \| _AV0S \| _AV0 \| _AQ \| _V_COPY); dmm32 ASTAT, (0x38700690 \| _VS \| _V \| _AV1S \| _AC1 \| _AQ \| _V_COPY); dmm32 A1.w, 0x00000000; dmm32 A1.x, 0x00000000; imm32 R0, 0x58863d39; imm32 R1, 0x45377355; imm32 R6, 0x00030000; R1.H = (A1 -= R0.L * R6.H) (TFU); checkreg R1, 0x00007355; checkreg ASTAT, (0x38700690 \| _VS \| _V \| _AV1S \| _AV1 \| _AC1 \| _AQ \| _V_COPY); dmm32 ASTAT, (0x48704880 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY \| _AN); dmm32 A0.w, 0x7fffd68a; dmm32 A0.x, 0xffffffff; imm32 R7, 0x06d88000; R7.L = A0 (IH); checkreg A0.w, 0x7fffd68a; checkreg A0.x, 0xffffffff; checkreg R7, 0x06d88000; checkreg ASTAT, (0x48704880 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COPY \| _AN); pass
tactcomplabs/xbgas-binutils-gdb	2,286	sim/testsuite/bfin/c_loopsetup_prelc.s	//Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp // Spec Reference: loopsetup preload lc0 lc1 # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; ASTAT = r0; //p0 = 2; P1 = 3; P2 = 4; P3 = 5; P4 = 6; P5 = 7; SP = 8; FP = 9; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x60 (X); R7 = 0x70 (X); LC0 = R0; LC1 = R1; LSETUP ( start1 , end1 ) LC0; start1: R0 += 1; R1 += -2; end1: R2 += 3; R3 += 4; LSETUP ( start2 , end2 ) LC1; start2: R4 += 4; end2: R5 += -5; R3 += 1; LSETUP ( start3 , end3 ) LC0 = P3; start3: R6 += 6; end3: R7 += -7; R3 += 1; CHECKREG r0, 0x0000000a; CHECKREG r1, 0x00000006; CHECKREG r2, 0x0000002f; CHECKREG r3, 0x00000036; CHECKREG r4, 0x00000080; CHECKREG r5, 0x00000000; CHECKREG r6, 0x0000007E; CHECKREG r7, 0x0000004D; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x60 (X); R7 = 0x70 (X); LC0 = R2; LC1 = R3; LSETUP ( start4 , end4 ) LC0; start4: R0 += 1; R1 += -2; end4: R2 += 3; R3 += 4; LSETUP ( start5 , end5 ) LC1; start5: R4 += 1; end5: R5 += -2; R3 += 3; LSETUP ( start6 , end6 ) LC0 = P2; start6: R6 += 4; end6: R7 += -5; R3 += 6; CHECKREG r0, 0x00000025; CHECKREG r1, 0xFFFFFFD0; CHECKREG r2, 0x00000080; CHECKREG r3, 0x0000003D; CHECKREG r4, 0x00000070; CHECKREG r5, 0xFFFFFFF0; CHECKREG r6, 0x00000070; CHECKREG r7, 0x0000005C; LSETUP ( start7 , end7 ) LC1; start7: R4 += 4; end7: R5 += -5; R3 += 6; CHECKREG r0, 0x00000025; CHECKREG r1, 0xFFFFFFD0; CHECKREG r2, 0x00000080; CHECKREG r3, 0x00000043; CHECKREG r4, 0x00000074; CHECKREG r5, 0xFFFFFFEB; CHECKREG r6, 0x00000070; CHECKREG r7, 0x0000005C; P1 = 12; P2 = 14; P3 = 16; P4 = 18; P5 = 20; SP = 22; FP = 24; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x25; R7 = 0x32; LC0 = R6; LC1 = R7; LSETUP ( start11 , end11 ) LC0; start11: R0 += 1; R1 += -1; end11: R2 += 1; R3 += 1; LSETUP ( start12 , end12 ) LC1; start12: R4 += 1; end12: R5 += -1; R3 += 1; LSETUP ( start13 , end13 ) LC1 = P4; start13: R6 += 1; end13: R7 += -1; R3 += 1; CHECKREG r0, 0x0000002A; CHECKREG r1, 0xFFFFFFEB; CHECKREG r2, 0x00000045; CHECKREG r3, 0x00000033; CHECKREG r4, 0x00000072; CHECKREG r5, 0x0000001E; CHECKREG r6, 0x00000037; CHECKREG r7, 0x00000020; pass
tactcomplabs/xbgas-binutils-gdb	9,518	sim/testsuite/bfin/lmu_excpt_prot0.S	//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_prot0/lmu_excpt_prot0.dsp // Description: LMU protection exceptions # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(selfcheck.inc) include(std.inc) include(mmrs.inc) //------------------------------------- // Test LMU/CPLB exceptions // Basic outline: // Set exception handler // program CPLB Entries // Enable CPLB in DMEM_CNTL // perform access // verify exception occurred CHECK_INIT(p5, 0xEFFFFFFC); //------------------------- // Zero the CPLB Address and Data regs. LD32(p0, DCPLB_ADDR0); R0 = 0; [ P0 ++ ] = R0; // 0 [ P0 ++ ] = R0; // 1 [ P0 ++ ] = R0; // 2 [ P0 ++ ] = R0; // 3 [ P0 ++ ] = R0; // 4 [ P0 ++ ] = R0; // 5 [ P0 ++ ] = R0; // 6 [ P0 ++ ] = R0; // 7 [ P0 ++ ] = R0; // 8 [ P0 ++ ] = R0; // 9 [ P0 ++ ] = R0; // 10 [ P0 ++ ] = R0; // 11 [ P0 ++ ] = R0; // 12 [ P0 ++ ] = R0; // 13 [ P0 ++ ] = R0; // 14 [ P0 ++ ] = R0; // 15 LD32(p0, DCPLB_DATA0); [ P0 ++ ] = R0; // 0 [ P0 ++ ] = R0; // 1 [ P0 ++ ] = R0; // 2 [ P0 ++ ] = R0; // 3 [ P0 ++ ] = R0; // 4 [ P0 ++ ] = R0; // 5 [ P0 ++ ] = R0; // 6 [ P0 ++ ] = R0; // 7 [ P0 ++ ] = R0; // 8 [ P0 ++ ] = R0; // 9 [ P0 ++ ] = R0; // 10 [ P0 ++ ] = R0; // 11 [ P0 ++ ] = R0; // 12 [ P0 ++ ] = R0; // 13 [ P0 ++ ] = R0; // 14 [ P0 ++ ] = R0; // 15 // Now set the CPLB entries we will need // Data area for the desired error WR_MMR(DCPLB_ADDR0, 0x800, p0, r0); WR_MMR(DCPLB_ADDR1, 0x1000, p0, r0); WR_MMR(DCPLB_DATA0, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW, p0, r0); WR_MMR(DCPLB_ADDR2, 0x2000, p0, r0); WR_MMR(DCPLB_ADDR3, 0x3000, p0, r0); WR_MMR(DCPLB_ADDR4, 0x4000, p0, r0); WR_MMR(DCPLB_ADDR5, 0x5000, p0, r0); WR_MMR(DCPLB_ADDR6, 0x6000, p0, r0); WR_MMR(DCPLB_ADDR7, 0x7000, p0, r0); // CHECKREG segment WR_MMR(DCPLB_ADDR14, 0xEFFFFC00, p0, r0); WR_MMR(DCPLB_DATA14, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_WT\|CPLB_L1_CACHABLE\|CPLB_SUPV_WR\|CPLB_USER_RW, p0, r0); // MMR space WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M\|CPLB_VALID\|CPLB_DIRTY\|CPLB_SUPV_WR, p0, r0); // setup interrupt controller with exception handler address WR_MMR_LABEL(EVT3, handler, p0, r1); WR_MMR_LABEL(EVT15, int_15, p0, r1); WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); // enable CPLB WR_MMR(DMEM_CONTROL, ENDM \| ENDCPLB \| DMC_AB_CACHE, p0, r0); NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC // go to user mode. and enable exceptions LD32_LABEL(r0, User); RETI = R0; // But first raise interrupt 15 so we can do one test // in supervisor mode. RAISE 15; NOP; RTI; // Nops to work around ICache bug NOP;NOP;NOP;NOP;NOP; NOP;NOP;NOP;NOP;NOP; int_15: // Interrupt 15 handler - needed to try supervisor access with exceptions enabled //------------------------------------------------------- // Protection violation - Illegal Supervisor Write Access R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; LD32(p1, 0x800); LD32(r1, 0xDEADBEEF); LD32(p2, DCPLB_DATA0); LD32(r2, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_SUPV_WR); LD32(p3, DCPLB_DATA1); LD32(r3, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_SUPV_WR); X0: [ P1 ] = R1; // Exception should occur here // Now check that handler read correct values CHECKREG(r4,0x23); // supv and EXCPT_PROT CHECKREG(r5, 0x800); CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG0\|FAULT_SUPV\|FAULT_CPLB0)); CHECKREG_SYM(r7, X0, r0); // RETX should be value of X0 (HARDCODED ADDR!!) // go to user mode. and enable exceptions LD32_LABEL(r0, User); RTI; NOP;NOP;NOP;NOP;NOP; NOP;NOP;NOP;NOP;NOP; User: NOP;NOP;NOP;NOP;NOP; //------------------------------------------------------- // Protection violation - Illegal User Write Access R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; LD32(p1, 0x1000); LD32(r1, 0xDEADBEEF); // values to fix up current test LD32(p2, DCPLB_DATA1); LD32(r2, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); // values for next test LD32(p3, DCPLB_DATA2); LD32(r3, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE); X1: [ P1 ] = R1; // Exception should occur here // Now check that handler read correct values CHECKREG(r4,0x23); // supv and EXCPT_PROT CHECKREG(r5, 0x1000); CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG0\|FAULT_USER \| FAULT_CPLB1)); CHECKREG_SYM(r7, X1, r0); // RETX should be value of X1 (HARDCODED ADDR!!) //------------------------------------------------------- // Protection violation - Illegal User Read Access R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; LD32(p1, 0x2000); LD32(r1, 0xDEADBEEF); LD32(p2, DCPLB_DATA2); LD32(r2, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RO\|CPLB_SUPV_WR); LD32(p3, DCPLB_DATA3); LD32(r3, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); X2: //[p1] = r1; // Exception should occur here R0 = [ P1 ]; // Now check that handler read correct values CHECKREG(r4,0x23); // supv and EXCPT_PROT CHECKREG(r5, 0x2000); CHECKREG(r6, (FAULT_READ\|FAULT_DAG0\|FAULT_USER \| FAULT_CPLB2)); CHECKREG_SYM(r7, X2, r0); // RETX should be value of X2 (HARDCODED ADDR!!) //------------------------------------------------------- // Protection violation - Illegal Dirty Page Access R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; LD32(p1, 0x3000); LD32(r1, 0xDEADBEEF); LD32(p2, DCPLB_DATA3); LD32(r2, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); LD32(p3, DCPLB_DATA4); LD32(r3, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DA0ACC\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); X3: [ P1 ] = R1; // Exception should occur here // Now check that handler read correct values CHECKREG(r4,0x23); // supv and EXCPT_PROT CHECKREG(r5, 0x3000); CHECKREG(r6, (FAULT_WRITE\|FAULT_DAG0\|FAULT_USER \| FAULT_CPLB3)); CHECKREG_SYM(r7, X3, r0); // RETX should be value of X3 (HARDCODED ADDR!!) //------------------------------------------------------- // Protection violation - Illegal DAG1 Access // Since this test uses DAG0, there shouldn't be any exception R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0; LD32(p1, 0x4000); LD32(r1, 0xDEADBEEF); LD32(p2, DCPLB_DATA4); LD32(r2, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); LD32(p3, DCPLB_DATA5); LD32(r3, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); X4: [ P1 ] = R1; // Exception should NOT occur here // Now check that handler read correct values // Handler shouldn't have been invoked, so registers should // remain unchanged. CHECKREG(r4,0); // supv and EXCPT_PROT CHECKREG(r5, 0); CHECKREG(r6, 0); CHECKREG(r7, 0); // RETX should NOT be value of X4 (HARDCODED ADDR!!) //------------------------------------------------------- // L1Miss not implemented yet - skip for now.... // //------------------------------------------------------- // // Protection violation - L1 Miss // r0=0;r1=0;r2=0;r3=0;r4=0;r5=0;r6=0;r7=0; // // LD32(p1, 0x5000); // LD32(r1, 0xDEADBEEF); // // LD32(p2, DCPLB_DATA5); // LD32(r2, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_L1_CACHABLE\|CPLB_USER_RW\|CPLB_SUPV_WR); // // LD32(p3, DCPLB_DATA6); // LD32(r3, PAGE_SIZE_1K\|CPLB_VALID\|CPLB_DIRTY\|CPLB_USER_RW\|CPLB_SUPV_WR); // // //X5: //[p1] = r1; // Exception should occur here // r0 = [p1]; // // // // Now check that handler read correct values // CHECKREG(r4,0x23); // supv and EXCPT_PROT // CHECKREG(r5, 0x5000); // // CHECKREG(r6, FAULT_DATA \| FAULT_CPLB5); // CHECKREG_SYM(r7, X5, r0); // RETX should be value of X5 (HARDCODED ADDR!!) //------------------------------------------------------- dbg_pass; handler: // generic protection exception handler // Inputs: // p2: addr of CPLB entry to be modified ( current test) // r2: new data for CPLB entry // // p3: addr of CPLB entry to be modified ( next test) // r3: new data for CPLB entry // // Outputs: // r4: SEQSTAT // r5: DCPLB_FAULT_ADDR // r6: DCPLB_STATUS // r7: RETX (instruction addr where exception occurred) R4 = SEQSTAT; // Get exception cause // read data addr which caused exception RD_MMR(DCPLB_FAULT_ADDR, p0, r5); RD_MMR(DCPLB_STATUS, p0, r6); R7 = RETX; // get address of excepting instruction // modify CPLB to allow access. Main pgm passes in addr and data [ P2 ] = R2; // Set up for next test [ P3 ] = R3; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC; // return from exception and re-execute offending instruction RTX; // Nops to work around ICache bug NOP;NOP;NOP;NOP;NOP; NOP;NOP;NOP;NOP;NOP; .section MEM_0x800,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .section MEM_0x1000,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .section MEM_0x2000,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .section MEM_0x3000,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .section MEM_0x4000,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .section MEM_0x5000,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 // Need illegal SRAM addr to test CPLB_L1SRAM //.data 0x6000 // .dd 0x00000000 // .dd 0x00000000 // .dd 0x00000000 // .dd 0x00000000 .section MEM_0x7000,"aw" .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000
tactcomplabs/xbgas-binutils-gdb	5,431	sim/testsuite/bfin/c_dsp32alu_rpp.s	//Original:/testcases/core/c_dsp32alu_rpp/c_dsp32alu_rpp.dsp // Spec Reference: dsp32alu dreg = +/+ ( dreg, dreg) # mach: bfin .include "testutils.inc" start // ALU operations include parallel addition, subtraction // and 32-bit data. If an operation use a single ALU only, it uses ALU0. imm32 r0, 0x15678911; imm32 r1, 0x2789ab1d; imm32 r2, 0x34445515; imm32 r3, 0x46667717; imm32 r4, 0x5567891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x74445515; imm32 r7, 0x86667777; R0 = R0 +\|+ R0; R1 = R0 +\|+ R1; R2 = R0 +\|+ R2; R3 = R0 +\|+ R3; R4 = R0 +\|+ R4; R5 = R0 +\|+ R5; R6 = R0 +\|+ R6; R7 = R0 +\|+ R7; CHECKREG r0, 0x2ACE1222; CHECKREG r1, 0x5257BD3F; CHECKREG r2, 0x5F126737; CHECKREG r3, 0x71348939; CHECKREG r4, 0x80359B3D; CHECKREG r5, 0x9257BD3F; CHECKREG r6, 0x9F126737; CHECKREG r7, 0xB1348999; imm32 r0, 0x9567892b; imm32 r1, 0xa789ab2d; imm32 r2, 0xb4445525; imm32 r3, 0xc6667727; imm32 r4, 0xd8889929; imm32 r5, 0xeaaabb2b; imm32 r6, 0xfcccdd2d; imm32 r7, 0x0eeeffff; R0 = R1 +\|+ R0; R1 = R1 +\|+ R1; R2 = R1 +\|+ R2; R3 = R1 +\|+ R3; R4 = R1 +\|+ R4; R5 = R1 +\|+ R5; R6 = R1 +\|+ R6; R7 = R1 +\|+ R7; CHECKREG r0, 0x3CF03458; CHECKREG r1, 0x4F12565A; CHECKREG r2, 0x0356AB7F; CHECKREG r3, 0x1578CD81; CHECKREG r4, 0x279AEF83; CHECKREG r5, 0x39BC1185; CHECKREG r6, 0x4BDE3387; CHECKREG r7, 0x5E005659; imm32 r0, 0x416789ab; imm32 r1, 0x6289abcd; imm32 r2, 0x43445555; imm32 r3, 0x64667777; imm32 r4, 0x456789ab; imm32 r5, 0x6689abcd; imm32 r6, 0x47445555; imm32 r7, 0x68667777; R0 = R2 +\|+ R0; R1 = R2 +\|+ R1; R2 = R2 +\|+ R2; R3 = R2 +\|+ R3; R4 = R2 +\|+ R4; R5 = R2 +\|+ R5; R6 = R2 +\|+ R6; R7 = R2 +\|+ R7; CHECKREG r0, 0x84ABDF00; CHECKREG r1, 0xA5CD0122; CHECKREG r2, 0x8688AAAA; CHECKREG r3, 0xEAEE2221; CHECKREG r4, 0xCBEF3455; CHECKREG r5, 0xED115677; CHECKREG r6, 0xCDCCFFFF; CHECKREG r7, 0xEEEE2221; imm32 r0, 0xd567892b; imm32 r1, 0xad89ab2d; imm32 r2, 0xb4d45525; imm32 r3, 0xc66d7727; imm32 r0, 0x9567d92b; imm32 r1, 0xa789ad2d; imm32 r2, 0xb44455d5; imm32 r3, 0xc666772d; R0 = R3 +\|+ R0; R1 = R3 +\|+ R1; R2 = R3 +\|+ R2; R3 = R3 +\|+ R3; R4 = R3 +\|+ R4; R5 = R3 +\|+ R5; R6 = R3 +\|+ R6; R7 = R3 +\|+ R7; CHECKREG r0, 0x5BCD5058; CHECKREG r1, 0x6DEF245A; CHECKREG r2, 0x7AAACD02; CHECKREG r3, 0x8CCCEE5A; CHECKREG r4, 0x58BB22AF; CHECKREG r5, 0x79DD44D1; CHECKREG r6, 0x5A98EE59; CHECKREG r7, 0x7BBA107B; imm32 r0, 0x4577891b; imm32 r1, 0x6779ab2d; imm32 r2, 0x44755535; imm32 r3, 0x66765747; imm32 r4, 0x88779565; imm32 r5, 0xaa7abb5b; imm32 r6, 0xcc97dd85; imm32 r7, 0xeeae7f9f; R0 = R4 +\|+ R0; R1 = R4 +\|+ R1; R2 = R4 +\|+ R2; R3 = R4 +\|+ R3; R4 = R4 +\|+ R4; R5 = R4 +\|+ R5; R6 = R4 +\|+ R6; R7 = R4 +\|+ R7; CHECKREG r0, 0xCDEE1E80; CHECKREG r1, 0xEFF04092; CHECKREG r2, 0xCCECEA9A; CHECKREG r3, 0xEEEDECAC; CHECKREG r4, 0x10EE2ACA; CHECKREG r5, 0xBB68E625; CHECKREG r6, 0xDD85084F; CHECKREG r7, 0xFF9CAA69; imm32 r0, 0x456b89ab; imm32 r1, 0x69764bcd; imm32 r2, 0x49736564; imm32 r3, 0x61278394; imm32 r4, 0x98876439; imm32 r5, 0xaaaa0bbb; imm32 r6, 0xcccc1ddd; imm32 r7, 0x12346fff; R0 = R5 +\|+ R0; R1 = R5 +\|+ R1; R2 = R5 +\|+ R2; R3 = R5 +\|+ R3; R4 = R5 +\|+ R4; R5 = R5 +\|+ R5; R6 = R5 +\|+ R6; R7 = R5 +\|+ R7; CHECKREG r0, 0xF0159566; CHECKREG r1, 0x14205788; CHECKREG r2, 0xF41D711F; CHECKREG r3, 0x0BD18F4F; CHECKREG r4, 0x43316FF4; CHECKREG r5, 0x55541776; CHECKREG r6, 0x22203553; CHECKREG r7, 0x67888775; imm32 r0, 0xaa6739ab; imm32 r1, 0x67dd4bcd; imm32 r2, 0x03456755; imm32 r3, 0x6b66bb77; imm32 r4, 0x12345699; imm32 r5, 0x45b78b6b; imm32 r6, 0x043b90d6; imm32 r7, 0x12b4bb7f; R0 = R6 +\|+ R0; R1 = R6 +\|+ R1; R2 = R6 +\|+ R2; R3 = R6 +\|+ R3; R4 = R6 +\|+ R4; R5 = R6 +\|+ R5; R6 = R6 +\|+ R6; R7 = R6 +\|+ R7; CHECKREG r0, 0xAEA2CA81; CHECKREG r1, 0x6C18DCA3; CHECKREG r2, 0x0780F82B; CHECKREG r3, 0x6FA14C4D; CHECKREG r4, 0x166FE76F; CHECKREG r5, 0x49F21C41; CHECKREG r6, 0x087621AC; CHECKREG r7, 0x1B2ADD2B; imm32 r0, 0x976789ab; imm32 r1, 0x6979abcd; imm32 r2, 0x23956755; imm32 r3, 0x56799007; imm32 r4, 0x789a9799; imm32 r5, 0xaaaa09bb; imm32 r6, 0x89ab1d9d; imm32 r7, 0xabcd2ff9; R0 = R7 +\|+ R0; R1 = R7 +\|+ R1; R2 = R7 +\|+ R2; R3 = R7 +\|+ R3; R4 = R7 +\|+ R4; R5 = R7 +\|+ R5; R6 = R7 +\|+ R6; R7 = R7 +\|+ R7; CHECKREG r0, 0x4334B9A4; CHECKREG r1, 0x1546DBC6; CHECKREG r2, 0xCF62974E; CHECKREG r3, 0x0246C000; CHECKREG r4, 0x2467C792; CHECKREG r5, 0x567739B4; CHECKREG r6, 0x35784D96; CHECKREG r7, 0x579A5FF2; imm32 r0, 0x856739ab; imm32 r1, 0x87694bcd; imm32 r2, 0x08856755; imm32 r3, 0x66686777; imm32 r4, 0x12385699; imm32 r5, 0x4567886b; imm32 r6, 0x04329086; imm32 r7, 0x12345678; R4 = R4 +\|+ R7 (S); R5 = R5 +\|+ R5 (CO); R2 = R6 +\|+ R3 (SCO); R6 = R0 +\|+ R4 (S); R0 = R1 +\|+ R6 (S); R2 = R2 +\|+ R1 (CO); R1 = R3 +\|+ R0 (CO); R7 = R7 +\|+ R4 (SCO); CHECKREG r0, 0x80007FFF; CHECKREG r1, 0xE776E668; CHECKREG r2, 0xB6677F66; CHECKREG r3, 0x66686777; CHECKREG r4, 0x246C7FFF; CHECKREG r5, 0x10D68ACE; CHECKREG r6, 0xA9D37FFF; CHECKREG r7, 0x7FFF36A0; imm32 r0, 0x476789ab; imm32 r1, 0x6779abcd; imm32 r2, 0x23456755; imm32 r3, 0x56789007; imm32 r4, 0x789ab799; imm32 r5, 0xaaaa0bbb; imm32 r6, 0x89ab1d7d; imm32 r7, 0xabcd2ff7; R3 = R4 +\|+ R0 (S); R5 = R5 +\|+ R1 (SCO); R2 = R2 +\|+ R2 (S); R7 = R7 +\|+ R3 (CO); R4 = R3 +\|+ R4 (CO); R0 = R1 +\|+ R5 (S); R1 = R0 +\|+ R6 (SCO); R6 = R6 +\|+ R7 (SCO); CHECKREG r0, 0x1F01BDF0; CHECKREG r1, 0xDB6DA8AC; CHECKREG r2, 0x468A7FFF; CHECKREG r3, 0x7FFF8000; CHECKREG r4, 0x3799F899; CHECKREG r5, 0xB7881223; CHECKREG r6, 0x49498000; CHECKREG r7, 0xAFF72BCC; pass
tactcomplabs/xbgas-binutils-gdb	5,667	sim/testsuite/bfin/c_mode_supervisor.S	//Original:/proj/frio/dv/testcases/core/c_mode_supervisor/c_mode_supervisor.dsp // Spec Reference: mode_supervisor # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif // ////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // etc.) // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! // Can't Raise 0, 3, or 4 // Raise 1 requires some intelligence so the test // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) RAISE 2; // RTN RAISE 5; // RTI RAISE 6; // RTI RAISE 7; // RTI RAISE 8; // RTI RAISE 9; // RTI RAISE 10; // RTI RAISE 11; // RTI RAISE 12; // RTI RAISE 13; // RTI RAISE 14; // RTI RAISE 15; // RTI CHECKREG(r0, 0x0000000B); CHECKREG(r1, 0x0000000C); CHECKREG(r2, 0x0000000D); CHECKREG(r3, 0x0000000E); CHECKREG(r4, 0x00000007); CHECKREG(r5, 0x00000008); CHECKREG(r6, 0x00000009); CHECKREG(r7, 0x0000000A); R0 = I0; R1 = I1; R2 = I2; R3 = I3; R4 = M0; CHECKREG(r0, 0x00000002); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x00000005); CHECKREG(r3, 0x00000006); CHECKREG(r4, 0x00000007); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 R0 = 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 R2 = 5; RTI; THANDLE: // Timer Handler 6 R3 = 6; RTI; I7HANDLE: // IVG 7 Handler R4 = 7; RTI; I8HANDLE: // IVG 8 Handler R5 = 8; RTI; I9HANDLE: // IVG 9 Handler R6 = 9; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .data DATA: .space (0x10); // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	2,387	sim/testsuite/bfin/m4.s	// MAC test program. // Test basic edge values // SIGNED INTEGER mode // test ops: "+=" "-=" "=" "NOP" # mach: bfin .include "testutils.inc" start // load r0=0x80007fff // load r1=0x80007fff // load r2=0xf0000000 // load r3=0x0000007f // load r4=0x00000080 loadsym P0, data0; R0 = [ P0 ++ ]; R1 = [ P0 ++ ]; R2 = [ P0 ++ ]; R3 = [ P0 ++ ]; R4 = [ P0 ++ ]; // 0x7fff * 0x7fff = 0x003fff0001 A1 = A0 = 0; A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0x0001 ); DBGA ( R6.H , 0x3fff ); DBGA ( R7.L , 0x0000 ); // 0x8000 * 0x7fff = 0xffc0008000 A1 = A0 = 0; A1 += R0.H * R1.L, A0 += R0.H * R1.L (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0x8000 ); DBGA ( R6.H , 0xc000 ); DBGA ( R7.L , 0xffff ); // 0x8000 * 0x8000 = 0x0040000000 A1 = A0 = 0; A1 += R0.H * R1.H, A0 += R0.H * R1.H (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x4000 ); DBGA ( R7.L , 0x0000 ); // saturate positive by first loading large value into accums // expected value is 0x7fffffffff A1 = A0 = 0; A1.w = R2; A1.x = R3.L; A0.w = R2; A0.x = R3.L; A1 += R0.L * R1.L, A0 += R0.L * R1.L (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0xffff ); DBGA ( R7.L , 0x007f ); // saturate negative // expected value is 0x8000000000 A1 = A0 = 0; A1.x = R4.L; A0.x = R4.L; A1 += R0.L * R1.H, A0 += R0.L * R1.H (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x0000 ); DBGA ( R7.L , 0xff80 ); // saturate positive with "-=" // expected value is 0x7fffffffff A1 = A0 = 0; A1.w = R2; A1.x = R3.L; A0.w = R2; A0.x = R3.L; A1 -= R0.H * R1.L, A0 -= R0.H * R1.L (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0xffff ); DBGA ( R7.L , 0x007f ); // saturate negative with "-=" // expected value is 0x8000000000 A1 = A0 = 0; A1.x = R4.L; A0.x = R4.L; A1 -= R0.L * R1.L, A0 -= R0.L * R1.L (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0x0000 ); DBGA ( R7.L , 0xff80 ); // 0x8000 * 0x8000 = 0xffc0000000 with "-=" A1 = A0 = 0; A1 -= R0.H * R1.H, A0 -= R0.H * R1.H (IS); R6 = A1.w; R7.L = A1.x; DBGA ( R6.L , 0x0000 ); DBGA ( R6.H , 0xc000 ); DBGA ( R7.L , 0xffff ); pass .data 0x1000; data0: .dw 0x7fff .dw 0x8000 .dw 0x7fff .dw 0x8000 .dw 0x0000 .dw 0xf000 .dw 0x007f .dw 0x0000 .dw 0x0080 .dw 0x0000
tactcomplabs/xbgas-binutils-gdb	10,985	sim/testsuite/bfin/ashift.s	# Blackfin testcase for ashift # mach: bfin .include "testutils.inc" .macro ashift_test in:req, shift:req, out:req, opt r0 = \in (Z); r2.L = \shift; r2.h = ASHIFT R0.L BY R2.L \opt; DBGA (r2.h, \out); .endm start /* * 16-bit ashift and lshift uses a 6-bit signed magnitude, which * gives a range from -32 to 31. In the case where the magnitude * is -32, make sure the answer is correct. */ ashift_test 0x8001, 33, 0xffff; ashift_test 0x8001, 32, 0xffff; ashift_test 0x8001, 31, 0x0000; ashift_test 0x8001, 30, 0x0000; ashift_test 0x8001, 29, 0x0000; ashift_test 0x8001, 28, 0x0000; ashift_test 0x8001, 27, 0x0000; ashift_test 0x8001, 26, 0x0000; ashift_test 0x8001, 25, 0x0000; ashift_test 0x8001, 24, 0x0000; ashift_test 0x8001, 23, 0x0000; ashift_test 0x8001, 22, 0x0000; ashift_test 0x8001, 21, 0x0000; ashift_test 0x8001, 20, 0x0000; ashift_test 0x8001, 19, 0x0000; ashift_test 0x8001, 18, 0x0000; ashift_test 0x8001, 17, 0x0000; ashift_test 0x8001, 16, 0x0000; ashift_test 0x8001, 15, 0x8000; ashift_test 0x8001, 14, 0x4000; ashift_test 0x8001, 13, 0x2000; ashift_test 0x8001, 12, 0x1000; ashift_test 0x8001, 11, 0x0800; ashift_test 0x8001, 10, 0x0400; ashift_test 0x8001, 9, 0x0200; ashift_test 0x8001, 8, 0x0100; ashift_test 0x8001, 7, 0x0080; ashift_test 0x8001, 6, 0x0040; ashift_test 0x8001, 5, 0x0020; ashift_test 0x8001, 4, 0x0010; ashift_test 0x8001, 3, 0x0008; ashift_test 0x8001, 2, 0x0004; ashift_test 0x8001, 1, 0x0002; ashift_test 0x8001, 0, 0x8001; ashift_test 0x8001, -1, 0xc000; ashift_test 0x8001, -2, 0xe000; ashift_test 0x8001, -3, 0xf000; ashift_test 0x8001, -4, 0xf800; ashift_test 0x8001, -5, 0xfc00; ashift_test 0x8001, -6, 0xfe00; ashift_test 0x8001, -7, 0xff00; ashift_test 0x8001, -8, 0xff80; ashift_test 0x8001, -9, 0xffc0; ashift_test 0x8001, -10, 0xffe0; ashift_test 0x8001, -11, 0xfff0; ashift_test 0x8001, -12, 0xfff8; ashift_test 0x8001, -13, 0xfffc; ashift_test 0x8001, -14, 0xfffe; ashift_test 0x8001, -15, 0xffff; ashift_test 0x8001, -16, 0xffff; ashift_test 0x8001, -17, 0xffff; ashift_test 0x8001, -18, 0xffff; ashift_test 0x8001, -19, 0xffff; ashift_test 0x8001, -20, 0xffff; ashift_test 0x8001, -21, 0xffff; ashift_test 0x8001, -22, 0xffff; ashift_test 0x8001, -23, 0xffff; ashift_test 0x8001, -24, 0xffff; ashift_test 0x8001, -25, 0xffff; ashift_test 0x8001, -26, 0xffff; ashift_test 0x8001, -27, 0xffff; ashift_test 0x8001, -28, 0xffff; ashift_test 0x8001, -29, 0xffff; ashift_test 0x8001, -30, 0xffff; ashift_test 0x8001, -31, 0xffff; ashift_test 0x8001, -32, 0xffff; ashift_test 0x8001, -33, 0x0; ashift_test 0x8001, -34, 0x0; ashift_test 0x8001, 33, 0xffff, (S); ashift_test 0x8001, 32, 0xffff, (S); ashift_test 0x8001, 31, 0x8000, (S); ashift_test 0x8001, 30, 0x8000, (S); ashift_test 0x8001, 29, 0x8000, (S); ashift_test 0x8001, 28, 0x8000, (S); ashift_test 0x8001, 27, 0x8000, (S); ashift_test 0x8001, 26, 0x8000, (S); ashift_test 0x8001, 25, 0x8000, (S); ashift_test 0x8001, 24, 0x8000, (S); ashift_test 0x8001, 23, 0x8000, (S); ashift_test 0x8001, 22, 0x8000, (S); ashift_test 0x8001, 21, 0x8000, (S); ashift_test 0x8001, 20, 0x8000, (S); ashift_test 0x8001, 19, 0x8000, (S); ashift_test 0x8001, 18, 0x8000, (S); ashift_test 0x8001, 17, 0x8000, (S); ashift_test 0x8001, 16, 0x8000, (S); ashift_test 0x8001, 15, 0x8000, (S); ashift_test 0x8001, 14, 0x8000, (S); ashift_test 0x8001, 13, 0x8000, (S); ashift_test 0x8001, 12, 0x8000, (S); ashift_test 0x8001, 11, 0x8000, (S); ashift_test 0x8001, 10, 0x8000, (S); ashift_test 0x8001, 9, 0x8000, (S); ashift_test 0x8001, 8, 0x8000, (S); ashift_test 0x8001, 7, 0x8000, (S); ashift_test 0x8001, 6, 0x8000, (S); ashift_test 0x8001, 5, 0x8000, (S); ashift_test 0x8001, 4, 0x8000, (S); ashift_test 0x8001, 3, 0x8000, (S); ashift_test 0x8001, 2, 0x8000, (S); ashift_test 0x8001, 1, 0x8000, (S); ashift_test 0x8001, 0, 0x8001, (S); ashift_test 0x8001, -1, 0xc000, (S); ashift_test 0x8001, -2, 0xe000, (S); ashift_test 0x8001, -3, 0xf000, (S); ashift_test 0x8001, -4, 0xf800, (S); ashift_test 0x8001, -5, 0xfc00, (S); ashift_test 0x8001, -6, 0xfe00, (S); ashift_test 0x8001, -7, 0xff00, (S); ashift_test 0x8001, -8, 0xff80, (S); ashift_test 0x8001, -9, 0xffc0, (S); ashift_test 0x8001, -10, 0xffe0, (S); ashift_test 0x8001, -11, 0xfff0, (S); ashift_test 0x8001, -12, 0xfff8, (S); ashift_test 0x8001, -13, 0xfffc, (S); ashift_test 0x8001, -14, 0xfffe, (S); ashift_test 0x8001, -15, 0xffff, (S); ashift_test 0x8001, -16, 0xffff, (S); ashift_test 0x8001, -17, 0xffff, (S); ashift_test 0x8001, -18, 0xffff, (S); ashift_test 0x8001, -19, 0xffff, (S); ashift_test 0x8001, -20, 0xffff, (S); ashift_test 0x8001, -21, 0xffff, (S); ashift_test 0x8001, -22, 0xffff, (S); ashift_test 0x8001, -23, 0xffff, (S); ashift_test 0x8001, -24, 0xffff, (S); ashift_test 0x8001, -25, 0xffff, (S); ashift_test 0x8001, -26, 0xffff, (S); ashift_test 0x8001, -27, 0xffff, (S); ashift_test 0x8001, -28, 0xffff, (S); ashift_test 0x8001, -29, 0xffff, (S); ashift_test 0x8001, -30, 0xffff, (S); ashift_test 0x8001, -31, 0xffff, (S); ashift_test 0x8001, -32, 0xffff, (S); ashift_test 0x8001, -33, 0x8000, (S); ashift_test 0x8001, -34, 0x8000, (S); ashift_test 0x4002, 33, 0x0; ashift_test 0x4002, 32, 0x0; ashift_test 0x4002, 31, 0x0; ashift_test 0x4002, 30, 0x0; ashift_test 0x4002, 20, 0x0; ashift_test 0x4002, 19, 0x0; ashift_test 0x4002, 18, 0x0; ashift_test 0x4002, 17, 0x0; ashift_test 0x4002, 16, 0x0; ashift_test 0x4002, 15, 0x0; ashift_test 0x4002, 14, 0x8000; ashift_test 0x4002, 13, 0x4000; ashift_test 0x4002, 12, 0x2000; ashift_test 0x4002, 11, 0x1000; ashift_test 0x4002, 10, 0x0800; ashift_test 0x4002, 9, 0x0400; ashift_test 0x4002, 8, 0x0200; ashift_test 0x4002, 7, 0x0100; ashift_test 0x4002, 6, 0x0080; ashift_test 0x4002, 5, 0x0040; ashift_test 0x4002, 4, 0x0020; ashift_test 0x4002, 3, 0x0010; ashift_test 0x4002, 2, 0x0008; ashift_test 0x4002, 1, 0x8004; ashift_test 0x4002, 0, 0x4002; ashift_test 0x4002, -1, 0x2001; ashift_test 0x4002, -2, 0x1000; ashift_test 0x4002, -3, 0x0800; ashift_test 0x4002, -4, 0x0400; ashift_test 0x4002, -5, 0x0200; ashift_test 0x4002, -6, 0x0100; ashift_test 0x4002, -7, 0x0080; ashift_test 0x4002, -8, 0x0040; ashift_test 0x4002, -9, 0x0020; ashift_test 0x4002, -10, 0x0010; ashift_test 0x4002, -11, 0x0008; ashift_test 0x4002, -12, 0x0004; ashift_test 0x4002, -13, 0x0002; ashift_test 0x4002, -14, 0x0001; ashift_test 0x4002, -15, 0x0; ashift_test 0x4002, -16, 0x0; ashift_test 0x4002, -17, 0x0; ashift_test 0x4002, -31, 0x0; ashift_test 0x4002, -32, 0x0; ashift_test 0x4002, -33, 0x0; ashift_test 0x4002, -34, 0x0; ashift_test 0x4002, 33, 0x0, (S); ashift_test 0x4002, 32, 0x0, (S); ashift_test 0x4002, 31, 0x7fff, (S); ashift_test 0x4002, 30, 0x7fff, (S); ashift_test 0x4002, 20, 0x7fff, (S); ashift_test 0x4002, 19, 0x7fff, (S); ashift_test 0x4002, 18, 0x7fff, (S); ashift_test 0x4002, 17, 0x7fff, (S); ashift_test 0x4002, 16, 0x7fff, (S); ashift_test 0x4002, 15, 0x7fff, (S); ashift_test 0x4002, 14, 0x7fff, (S); ashift_test 0x4002, 13, 0x7fff, (S); ashift_test 0x4002, 12, 0x7fff, (S); ashift_test 0x4002, 11, 0x7fff, (S); ashift_test 0x4002, 10, 0x7fff, (S); ashift_test 0x4002, 9, 0x7fff, (S); ashift_test 0x4002, 8, 0x7fff, (S); ashift_test 0x4002, 7, 0x7fff, (S); ashift_test 0x4002, 6, 0x7fff, (S); ashift_test 0x4002, 5, 0x7fff, (S); ashift_test 0x4002, 4, 0x7fff, (S); ashift_test 0x4002, 3, 0x7fff, (S); ashift_test 0x4002, 2, 0x7fff, (S); ashift_test 0x4002, 1, 0x7fff, (S); ashift_test 0x4002, 0, 0x4002, (S); ashift_test 0x4002, -1, 0x2001, (S); ashift_test 0x4002, -2, 0x1000, (S); ashift_test 0x4002, -3, 0x0800, (S); ashift_test 0x4002, -4, 0x0400, (S); ashift_test 0x4002, -5, 0x0200, (S); ashift_test 0x4002, -6, 0x0100, (S); ashift_test 0x4002, -7, 0x0080, (S); ashift_test 0x4002, -8, 0x0040, (S); ashift_test 0x4002, -9, 0x0020, (S); ashift_test 0x4002, -10, 0x0010, (S); ashift_test 0x4002, -11, 0x0008, (S); ashift_test 0x4002, -12, 0x0004, (S); ashift_test 0x4002, -13, 0x0002, (S); ashift_test 0x4002, -14, 0x0001, (S); ashift_test 0x4002, -15, 0x0000, (S); ashift_test 0x4002, -16, 0x0000, (S); ashift_test 0x4002, -17, 0x0000, (S); ashift_test 0x4002, -31, 0x0000, (S); ashift_test 0x4002, -32, 0x0000, (S); ashift_test 0x4002, -33, 0x7fff, (S); ashift_test 0x4002, -34, 0x7fff, (S); ashift_test 0x0001, 33, 0x0000, (S); ashift_test 0x0001, 32, 0x0000, (S); ashift_test 0x0001, 31, 0x7fff, (S); ashift_test 0x0001, 30, 0x7fff, (S); ashift_test 0x0001, 29, 0x7fff, (S); ashift_test 0x0001, 28, 0x7fff, (S); ashift_test 0x0001, 27, 0x7fff, (S); ashift_test 0x0001, 26, 0x7fff, (S); ashift_test 0x0001, 25, 0x7fff, (S); ashift_test 0x0001, 24, 0x7fff, (S); ashift_test 0x0001, 23, 0x7fff, (S); ashift_test 0x0001, 22, 0x7fff, (S); ashift_test 0x0001, 21, 0x7fff, (S); ashift_test 0x0001, 20, 0x7fff, (S); ashift_test 0x0001, 19, 0x7fff, (S); ashift_test 0x0001, 18, 0x7fff, (S); ashift_test 0x0001, 17, 0x7fff, (S); ashift_test 0x0001, 16, 0x7fff, (S); ashift_test 0x0001, 15, 0x7fff, (S); ashift_test 0x0001, 14, 0x4000, (S); ashift_test 0x0001, 13, 0x2000, (S); ashift_test 0x0001, 12, 0x1000, (S); ashift_test 0x0001, 11, 0x0800, (S); ashift_test 0x0001, 10, 0x0400, (S); ashift_test 0x0001, 9, 0x0200, (S); ashift_test 0x0001, 8, 0x0100, (S); ashift_test 0x0001, 7, 0x0080, (S); ashift_test 0x0001, 6, 0x0040, (S); ashift_test 0x0001, 5, 0x0020, (S); ashift_test 0x0001, 4, 0x0010, (S); ashift_test 0x0001, 3, 0x0008, (S); ashift_test 0x0001, 2, 0x0004, (S); ashift_test 0x0001, 1, 0x0002, (S); ashift_test 0x0001, 0, 0x0001, (S); ashift_test 0x0001, -1, 0x0000, (S); ashift_test 0x0001, -2, 0x0000, (S); ashift_test 0x0001, -3, 0x0000, (S); ashift_test 0x0001, -4, 0x0000, (S); ashift_test 0x0001, -5, 0x0000, (S); ashift_test 0x0001, -6, 0x0000, (S); ashift_test 0x0001, -7, 0x0000, (S); ashift_test 0x0001, -8, 0x0000, (S); ashift_test 0x0001, -9, 0x0000, (S); ashift_test 0x0001, -10, 0x0000, (S); ashift_test 0x0001, -11, 0x0000, (S); ashift_test 0x0001, -12, 0x0000, (S); ashift_test 0x0001, -13, 0x0000, (S); ashift_test 0x0001, -14, 0x0, (S); ashift_test 0x0001, -15, 0x0, (S); ashift_test 0x0001, -16, 0x0, (S); ashift_test 0x0001, -17, 0x0, (S); ashift_test 0x0001, -18, 0x0, (S); ashift_test 0x0001, -19, 0x0, (S); ashift_test 0x0001, -20, 0x0, (S); ashift_test 0x0001, -21, 0x0, (S); ashift_test 0x0001, -22, 0x0, (S); ashift_test 0x0001, -23, 0x0, (S); ashift_test 0x0001, -24, 0x0, (S); ashift_test 0x0001, -25, 0x0, (S); ashift_test 0x0001, -26, 0x0, (S); ashift_test 0x0001, -27, 0x0, (S); ashift_test 0x0001, -28, 0x0, (S); ashift_test 0x0001, -29, 0x0, (S); ashift_test 0x0001, -30, 0x0, (S); ashift_test 0x0001, -31, 0x0, (S); ashift_test 0x0001, -32, 0x0, (S); ashift_test 0x0001, -33, 0x7fff, (S); ashift_test 0x0001, -34, 0x7fff, (S); pass
tactcomplabs/xbgas-binutils-gdb	5,875	sim/testsuite/bfin/c_interr_timer_reload.S	//Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp // Spec Reference: interrupt on HW TIMER auto-reload # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start // // Include Files // include(std.inc) include(selfcheck.inc) // Defines #ifndef TCNTL #define TCNTL 0xFFE03000 #endif #ifndef TPERIOD #define TPERIOD 0xFFE03004 #endif #ifndef TSCALE #define TSCALE 0xFFE03008 #endif #ifndef TCOUNT #define TCOUNT 0xFFE0300c #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203c #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE 0x000FF000 #endif #ifndef PROGRAM_STACK #define PROGRAM_STACK 0x000FF100 #endif #ifndef STACKSIZE #define STACKSIZE 0x00000300 #endif // Boot code BOOT : INIT_R_REGS(0); // Initialize Dregs INIT_P_REGS(0); // Initialize Pregs // CHECK_INIT(p5, 0x00BFFFFC); // CHECK_INIT(p5, 0xE0000000); include(symtable.inc) CHECK_INIT_DEF(p5); LD32(sp, 0x000FF200); LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE); // IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE); // IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE); // IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE); // IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE); // IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE); // IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK LD32_LABEL(p1, START); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start CSYNC; RAISE 15; // after we RTI, INT 15 should be taken LD32_LABEL(r7, START); RETI = r7; NOP; // Workaround for Bug 217 RTI; NOP; NOP; //.code 0x200 START : R7 = 0x0; R6 = 0x1; [ -- SP ] = RETI; // Enable Nested Interrupts WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) WR_MMR(TPERIOD, 0x00000020, p0, r0); WR_MMR(TCOUNT, 0x00000002, p0, r0); WR_MMR(TSCALE, 0x00000005, p0, r0); CSYNC; // Read the contents of the Timer RD_MMR(TPERIOD, p0, r2); CHECKREG(r2, 0x00000020); RD_MMR(TCOUNT, p0, r3); CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) CSYNC; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; RD_MMR(TCOUNT, p0, r4); CHECKREG(r4, 0x00000000); RD_MMR(TCNTL, p0, r5); CHECKREG(r5, 0x0000000B); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; CHECKREG(r7, 0x00000001); R7 = 0; NOP; WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power WR_MMR(TPERIOD, 0x00000020, p0, r0); WR_MMR(TCOUNT, 0x00000003, p0, r0); WR_MMR(TSCALE, 0x00000002, p0, r0); WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload CSYNC; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; // With auto reload // Read the contents of the Timer // CHECKREG(r7, 0x00000002); CC = R7 == 0; IF !CC JUMP LABEL1; WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE LABEL1: RD_MMR(TPERIOD, p0, r2); CHECKREG(r2, 0x00000020); RD_MMR(TCNTL , p0, r3); CHECKREG(r3, 0x0000000F); WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload CSYNC; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; RD_MMR(TCOUNT, p0, r4); CHECKREG(r4, 0x00000000); RD_MMR(TCNTL, p0, r5); CHECKREG(r5, 0x0000000B); WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer CSYNC; NOP; NOP; NOP; dbg_pass; // Call Endtest Macro //******************************************************************** // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 RTN; XHANDLE: // Exception Handler 3 RTX; HWHANDLE: // HW Error Handler 5 RTI; THANDLE: // Timer Handler 6 R7 = R7 + R6; RTI; I7HANDLE: // IVG 7 Handler RTI; I8HANDLE: // IVG 8 Handler RTI; I9HANDLE: // IVG 9 Handler RTI; I10HANDLE: // IVG 10 Handler RTI; I11HANDLE: // IVG 11 Handler RTI; I12HANDLE: // IVG 12 Handler RTI; I13HANDLE: // IVG 13 Handler RTI; I14HANDLE: // IVG 14 Handler RTI; I15HANDLE: // IVG 15 Handler R5 = RETI; P0 = R5; JUMP ( P0 ); RTI; .section MEM_DATA_ADDR_1,"aw" .space (STACKSIZE); STACK: NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
tactcomplabs/xbgas-binutils-gdb	3,232	sim/testsuite/bfin/s18.s	// Immediate dual 16b SHIFT test program. // Test r4 = ASHIFT/ASHIFT (r2 by 10); // Test r4 = ASHIFT/ASHIFT (r2 by 10) S; // Test r4 = LSHIFT/LSHIFT (r2 by 10); # mach: bfin .include "testutils.inc" start // arithmetic // left by largest positive magnitude of 15 (0xf) // 8001 -> 8000 R7 = 0; ASTAT = R7; R0.L = 0x8001; R0.H = 0x0100; R6 = R0 << 15 (V); DBGA ( R6.L , 0x8000 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by largest positive magnitude of 15 (0xf) with saturation R7 = 0; ASTAT = R7; R0.L = 0x8001; R0.H = 0x0100; R6 = R0 << 15 (V , S); DBGA ( R6.L , 0x8000 ); DBGA ( R6.H , 0x7fff ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 1 R7 = 0; ASTAT = R7; R0.L = 0x8001; R0.H = 0x0100; R6 = R0 << 1 (V); DBGA ( R6.L , 0x0002 ); DBGA ( R6.H , 0x0200 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 1 saturating R7 = 0; ASTAT = R7; R0.L = 0x8001; R0.H = 0x0100; R6 = R0 << 1 (V , S); DBGA ( R6.L , 0x8000 ); DBGA ( R6.H , 0x0200 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // left by 15 saturating R7 = 0; ASTAT = R7; R0.L = 0xfff0; R0.H = 0x0000; R6 = R0 << 15 (V , S); DBGA ( R6.L , 0x8000 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // right by 15 R7 = 0; ASTAT = R7; R0.L = 0x8000; R0.H = 0x0100; R6 = R0 >>> 15 (V); DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // arithmetic // right by 15 (sat has no effect) R7 = 0; ASTAT = R7; R0.L = 0x8000; R0.H = 0x0100; R6 = R0 >>> 15 (V); DBGA ( R6.L , 0xffff ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); // logic // right by 15 R7 = 0; ASTAT = R7; R0.L = 0x8000; R0.H = 0x0100; R6 = R0 >> 15 (V); DBGA ( R6.L , 0x0001 ); DBGA ( R6.H , 0x0000 ); CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); pass
tactcomplabs/xbgas-binutils-gdb	6,606	sim/testsuite/bfin/c_dsp32alu_rrppmm.s	//Original:/testcases/core/c_dsp32alu_rrppmm/c_dsp32alu_rrppmm.dsp // Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) amod0 # mach: bfin .include "testutils.inc" start imm32 r0, 0x95679911; imm32 r1, 0x2789ab1d; imm32 r2, 0x34945515; imm32 r3, 0x46967717; imm32 r4, 0x5597891b; imm32 r5, 0x6989ab1d; imm32 r6, 0x94445515; imm32 r7, 0x96667777; R0 = R0 +\|+ R0, R7 = R0 -\|- R0; R1 = R0 +\|+ R1, R6 = R0 -\|- R1; R2 = R0 +\|+ R2, R5 = R0 -\|- R2; R3 = R0 +\|+ R3, R4 = R0 -\|- R3; R4 = R0 +\|+ R4, R3 = R0 -\|- R4; R5 = R0 +\|+ R5, R2 = R0 -\|- R5; R6 = R0 +\|+ R6, R1 = R0 -\|- R6; R7 = R0 +\|+ R7, R0 = R0 -\|- R7; CHECKREG r0, 0x2ACE3222; CHECKREG r1, 0x2789AB1D; CHECKREG r2, 0x34945515; CHECKREG r3, 0x46967717; CHECKREG r4, 0x0F06ED2D; CHECKREG r5, 0x21080F2F; CHECKREG r6, 0x2E13B927; CHECKREG r7, 0x2ACE3222; imm32 r0, 0x11678911; imm32 r1, 0xa719ab1d; imm32 r2, 0x3a415515; imm32 r3, 0x46a67717; imm32 r4, 0x556a891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x74445a15; imm32 r7, 0x866677a7; R0 = R1 +\|+ R0, R7 = R1 -\|- R0; R1 = R1 +\|+ R1, R6 = R1 -\|- R1; R2 = R1 +\|+ R2, R5 = R1 -\|- R2; R3 = R1 +\|+ R3, R4 = R1 -\|- R3; R4 = R1 +\|+ R4, R3 = R1 -\|- R4; R5 = R1 +\|+ R5, R2 = R1 -\|- R5; R6 = R1 +\|+ R6, R1 = R1 -\|- R6; R7 = R1 +\|+ R7, R0 = R1 -\|- R7; CHECKREG r0, 0xB880342E; CHECKREG r1, 0x4E32563A; CHECKREG r2, 0x3A415515; CHECKREG r3, 0x46A67717; CHECKREG r4, 0x55BE355D; CHECKREG r5, 0x6223575F; CHECKREG r6, 0x4E32563A; CHECKREG r7, 0xE3E47846; imm32 r0, 0xb567891b; imm32 r1, 0x2b89abbd; imm32 r2, 0x34b45b15; imm32 r3, 0x466bb717; imm32 r4, 0x556bb91b; imm32 r5, 0x67b9ab1d; imm32 r6, 0x7b4455b5; imm32 r7, 0xb666777b; R0 = R2 +\|+ R0, R7 = R2 -\|- R0; R1 = R2 +\|+ R1, R6 = R2 -\|- R1; R2 = R2 +\|+ R2, R5 = R2 -\|- R2; R3 = R2 +\|+ R3, R4 = R2 -\|- R3; R4 = R2 +\|+ R4, R3 = R2 -\|- R4; R5 = R2 +\|+ R5, R2 = R2 -\|- R5; R6 = R2 +\|+ R6, R1 = R2 -\|- R6; R7 = R2 +\|+ R7, R0 = R2 -\|- R7; CHECKREG r0, 0xEA1BE430; CHECKREG r1, 0x603D06D2; CHECKREG r2, 0x6968B62A; CHECKREG r3, 0x466BB717; CHECKREG r4, 0x8C65B53D; CHECKREG r5, 0x6968B62A; CHECKREG r6, 0x72936582; CHECKREG r7, 0xE8B58824; imm32 r0, 0xbc678c11; imm32 r1, 0x27c9cb1d; imm32 r2, 0x344c5515; imm32 r3, 0x46c6c717; imm32 r4, 0x55678c1b; imm32 r5, 0x6c89abcd; imm32 r6, 0x7444551c; imm32 r7, 0x8c667777; R0 = R3 +\|+ R0, R7 = R3 -\|- R0; R1 = R3 +\|+ R1, R6 = R3 -\|- R1; R2 = R3 +\|+ R2, R5 = R3 -\|- R2; R3 = R3 +\|+ R3, R4 = R3 -\|- R3; R4 = R3 +\|+ R4, R3 = R3 -\|- R4; R5 = R3 +\|+ R5, R2 = R3 -\|- R5; R6 = R3 +\|+ R6, R1 = R3 -\|- R6; R7 = R3 +\|+ R7, R0 = R3 -\|- R7; CHECKREG r0, 0x032D5328; CHECKREG r1, 0x6E8F9234; CHECKREG r2, 0x7B121C2C; CHECKREG r3, 0x8D8C8E2E; CHECKREG r4, 0x8D8C8E2E; CHECKREG r5, 0xA0060030; CHECKREG r6, 0xAC898A28; CHECKREG r7, 0x17EBC934; imm32 r0, 0xd56789d1; imm32 r1, 0x2d89abdd; imm32 r2, 0x34d455d5; imm32 r3, 0x4d667717; imm32 r4, 0x5dd7891b; imm32 r5, 0x6789ab1d; imm32 r6, 0xd44d5515; imm32 r7, 0xd666d777; R0 = R4 +\|+ R0, R7 = R4 -\|- R0; R1 = R4 +\|+ R1, R6 = R4 -\|- R1; R2 = R4 +\|+ R2, R5 = R4 -\|- R2; R3 = R4 +\|+ R3, R4 = R4 -\|- R3; R4 = R4 +\|+ R4, R3 = R4 -\|- R4; R5 = R4 +\|+ R5, R2 = R4 -\|- R5; R6 = R4 +\|+ R6, R1 = R4 -\|- R6; R7 = R4 +\|+ R7, R0 = R4 -\|- R7; CHECKREG r0, 0x987224BE; CHECKREG r1, 0xF09446CA; CHECKREG r2, 0xF7DFF0C2; CHECKREG r3, 0x00000000; CHECKREG r4, 0x20E22408; CHECKREG r5, 0x49E5574E; CHECKREG r6, 0x51300146; CHECKREG r7, 0xA9522352; imm32 r0, 0xc567a911; imm32 r1, 0x278aab1d; imm32 r2, 0x3c445515; imm32 r3, 0x46a67717; imm32 r4, 0x55c7891b; imm32 r5, 0x6a8cab1d; imm32 r6, 0x7444c515; imm32 r7, 0xa6667c77; R0 = R5 +\|+ R0, R7 = R5 -\|- R0; R1 = R5 +\|+ R1, R6 = R5 -\|- R1; R2 = R5 +\|+ R2, R5 = R5 -\|- R2; R3 = R5 +\|+ R3, R4 = R5 -\|- R3; R4 = R5 +\|+ R4, R3 = R5 -\|- R4; R5 = R5 +\|+ R5, R2 = R5 -\|- R5; R6 = R5 +\|+ R6, R1 = R5 -\|- R6; R7 = R5 +\|+ R7, R0 = R5 -\|- R7; CHECKREG r0, 0xB76BAA04; CHECKREG r1, 0x198EAC10; CHECKREG r2, 0x00000000; CHECKREG r3, 0x46A67717; CHECKREG r4, 0x15EA34F9; CHECKREG r5, 0x5C90AC10; CHECKREG r6, 0x9F92AC10; CHECKREG r7, 0x01B5AE1C; imm32 r0, 0xd5678911; imm32 r1, 0x2ddddd1d; imm32 r2, 0x34ddd515; imm32 r3, 0x46d67717; imm32 r4, 0x5d6d891b; imm32 r5, 0x6789db1d; imm32 r6, 0x74445d15; imm32 r7, 0xd66677d7; R0 = R6 +\|+ R0, R7 = R6 -\|- R0; R1 = R6 +\|+ R1, R6 = R6 -\|- R1; R2 = R6 +\|+ R2, R5 = R6 -\|- R2; R3 = R6 +\|+ R3, R4 = R6 -\|- R3; R4 = R6 +\|+ R4, R3 = R6 -\|- R4; R5 = R6 +\|+ R5, R2 = R6 -\|- R5; R6 = R6 +\|+ R6, R1 = R6 -\|- R6; R7 = R6 +\|+ R7, R0 = R6 -\|- R7; CHECKREG r0, 0xEDF12BEC; CHECKREG r1, 0x00000000; CHECKREG r2, 0x34DDD515; CHECKREG r3, 0x46D67717; CHECKREG r4, 0x45F888D9; CHECKREG r5, 0x57F12ADB; CHECKREG r6, 0x8CCEFFF0; CHECKREG r7, 0x2BABD3F4; imm32 r0, 0xf567a911; imm32 r1, 0x2f8aab1d; imm32 r2, 0x34a45515; imm32 r3, 0x4a6f7717; imm32 r4, 0x5567f91b; imm32 r5, 0xa789af1d; imm32 r6, 0x74445515; imm32 r7, 0x866677f7; R0 = R7 +\|+ R0, R7 = R7 -\|- R0; R1 = R7 +\|+ R1, R6 = R7 -\|- R1; R2 = R7 +\|+ R2, R5 = R7 -\|- R2; R3 = R7 +\|+ R3, R4 = R7 -\|- R3; R4 = R7 +\|+ R4, R3 = R7 -\|- R4; R5 = R7 +\|+ R5, R2 = R7 -\|- R5; R6 = R7 +\|+ R6, R1 = R7 -\|- R6; R7 = R7 +\|+ R7, R0 = R7 -\|- R7; CHECKREG r0, 0x00000000; CHECKREG r1, 0x2F8AAB1D; CHECKREG r2, 0x34A45515; CHECKREG r3, 0x4A6F7717; CHECKREG r4, 0xD78F26B5; CHECKREG r5, 0xED5A48B7; CHECKREG r6, 0xF274F2AF; CHECKREG r7, 0x21FE9DCC; imm32 r0, 0xe5678911; imm32 r1, 0x2e89ab1d; imm32 r2, 0x34e45515; imm32 r3, 0x46667717; imm32 r4, 0x556e891b; imm32 r5, 0x6789ab1d; imm32 r6, 0x7444e515; imm32 r7, 0x86667e77; R4 = R2 +\|+ R5, R3 = R2 -\|- R5 (S); R0 = R5 +\|+ R3, R5 = R5 -\|- R3 (CO); R2 = R6 +\|+ R2, R0 = R6 -\|- R2 (SCO); R3 = R4 +\|+ R0, R2 = R4 -\|- R0 (S); R7 = R7 +\|+ R6, R6 = R7 -\|- R6 (CO); R6 = R1 +\|+ R7, R1 = R1 -\|- R7 (SCO); R5 = R0 +\|+ R4, R7 = R0 -\|- R4 (S); R1 = R3 +\|+ R1, R4 = R3 -\|- R1 (CO); CHECKREG r0, 0x90003F60; CHECKREG r1, 0x8FFF7371; CHECKREG r2, 0x7FFFC0D2; CHECKREG r3, 0x0FFF3F92; CHECKREG r4, 0x0BB38FFF; CHECKREG r5, 0x0FFF3F92; CHECKREG r6, 0x29330EA9; CHECKREG r7, 0x80003F2E; imm32 r0, 0xd5678911; imm32 r1, 0xff89ab1d; imm32 r2, 0x34f45515; imm32 r3, 0x46667717; imm32 r4, 0x556f891b; imm32 r5, 0x6789fb1d; imm32 r6, 0x74445f15; imm32 r7, 0x866677f7; R4 = R3 +\|+ R3, R5 = R3 -\|- R3 (SCO); R1 = R6 +\|+ R1, R6 = R6 -\|- R1 (SCO); R6 = R1 +\|+ R4, R4 = R1 -\|- R4 (S); R7 = R4 +\|+ R2, R0 = R4 -\|- R2 (S); R2 = R2 +\|+ R6, R1 = R2 -\|- R6 (CO); R3 = R5 +\|+ R5, R7 = R5 -\|- R5 (CO); R5 = R7 +\|+ R7, R3 = R7 -\|- R7 (SCO); R0 = R0 +\|+ R0, R2 = R0 -\|- R0 (SCO); CHECKREG r0, 0x80008000; CHECKREG r1, 0xD516B4F5; CHECKREG r2, 0x00000000; CHECKREG r3, 0x00000000; CHECKREG r4, 0xF3CE8A33; CHECKREG r5, 0x00000000; CHECKREG r6, 0x7FFF7FFF; CHECKREG r7, 0x00000000; pass
tactcomplabs/xbgas-binutils-gdb	2,885	sim/testsuite/bfin/c_loopsetup_nested_top.s	//Original:/testcases/core/c_loopsetup_nested_top/c_loopsetup_nested_top.dsp // Spec Reference: loopsetup nested top # mach: bfin .include "testutils.inc" start INIT_R_REGS 0; ASTAT = r0; //p0 = 2; P1 = 3; P2 = 4; P3 = 5; P4 = 6; P5 = 7; SP = 8; FP = 9; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x60 (X); R7 = 0x70 (X); LSETUP ( start1 , end1 ) LC0 = P1; start1: R0 += 1; R1 += -2; LSETUP ( start2 , end2 ) LC1 = P2; start2: R4 += 4; end2: R5 += -5; R3 += 1; end1: R2 += 3; R3 += 4; LSETUP ( start3 , end3 ) LC1 = P3; LSETUP ( start3 , end4 ) LC0 = P4; start3: R6 += 6; R0 += 1; R1 += -2; end4: R2 += 3; R3 += 4; end3: R7 += -7; R3 += 1; CHECKREG r0, 0x00000012; CHECKREG r1, 0xFFFFFFF6; CHECKREG r2, 0x00000047; CHECKREG r3, 0x0000004C; CHECKREG r4, 0x00000070; CHECKREG r5, 0x00000014; CHECKREG r6, 0x0000009C; CHECKREG r7, 0x0000004D; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x60 (X); R7 = 0x70 (X); LSETUP ( start5 , end5 ) LC0 = P5; LSETUP ( start5 , end6 ) LC1 = SP >> 1; start5: R4 += 1; R6 += 4; end6: R7 += -5; R3 += 6; end5: R5 += -2; R3 += 3; CHECKREG r0, 0x00000005; CHECKREG r1, 0x00000010; CHECKREG r2, 0x00000020; CHECKREG r3, 0x0000005D; CHECKREG r4, 0x0000004A; CHECKREG r5, 0x00000042; CHECKREG r6, 0x00000088; CHECKREG r7, 0x0000003E; LSETUP ( start7 , end7 ) LC0 = FP; start7: R4 += 4; end7: R5 += -5; R3 += 6; CHECKREG r0, 0x00000005; CHECKREG r1, 0x00000010; CHECKREG r2, 0x00000020; CHECKREG r3, 0x00000063; CHECKREG r4, 0x0000006E; CHECKREG r5, 0x00000015; CHECKREG r6, 0x00000088; CHECKREG r7, 0x0000003E; P1 = 8; P2 = 10; P3 = 12; P4 = 14; P5 = 16; SP = 18; FP = 20; R0 = 0x05; R1 = 0x10; R2 = 0x20; R3 = 0x30; R4 = 0x40 (X); R5 = 0x50 (X); R6 = 0x60 (X); R7 = 0x70 (X); LSETUP ( start11 , end11 ) LC1 = P1 >> 1; LSETUP ( start11 , end15 ) LC0 = P5; start11: R0 += 1; R1 += -1; R4 += 1; end15: R5 += -1; R3 += 1; end11: R2 += 1; R3 += 1; LSETUP ( start12 , end12 ) LC1 = P3 >> 1; LSETUP ( start12 , end13 ) LC0 = P2 >> 1; start12: R6 += 1; R4 += 1; end13: R5 += -1; R3 += 1; end12: R7 += -1; R3 += 1; CHECKREG r0, 0x00000018; CHECKREG r1, 0xFFFFFFFD; CHECKREG r2, 0x00000024; CHECKREG r3, 0x0000003C; CHECKREG r4, 0x0000005D; CHECKREG r5, 0x00000033; CHECKREG r6, 0x0000006A; CHECKREG r7, 0x0000006A; R0 = 0x04; R1 = 0x06; R2 = 0x08; R3 = 0x10; R4 = 0x12; R5 = 0x14; R6 = 0x16; R7 = 0x18; LSETUP ( start14 , end14 ) LC0 = P4; LSETUP ( start14 , end16 ) LC1 = SP >> 1; start14: R0 += 1; R1 += -1; R6 += 1; end16: R7 += -1; R3 += 1; LSETUP ( start17 , end17 ) LC1 = FP >> 1; start17: R4 += 1; end17: R5 += -1; R3 += 1; end14: R2 += 1; R3 += 1; CHECKREG r0, 0x0000001A; CHECKREG r1, 0xFFFFFFF0; CHECKREG r2, 0x00000016; CHECKREG r3, 0x0000002D; CHECKREG r4, 0x0000009E; CHECKREG r5, 0xFFFFFF88; CHECKREG r6, 0x0000002C; CHECKREG r7, 0x00000002; pass
tactcomplabs/xbgas-binutils-gdb	3,122	sim/testsuite/bfin/c_dsp32mac_pair_a0_m.s	//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp // Spec Reference: dsp32mac pair a0 m (M, MNOP) # mach: bfin .include "testutils.inc" start A1 = A0 = 0; // The result accumulated in A , and stored to a reg half imm32 r0, 0x63545abd; imm32 r1, 0x86bcfec7; imm32 r2, 0xa8645679; imm32 r3, 0x00860007; imm32 r4, 0xefb86569; imm32 r5, 0x1235860b; imm32 r6, 0x000c086d; imm32 r7, 0x678e0086; A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L ); P5 = A1.w; P1 = A0.w; A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ); P2 = A0.w; A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ); P3 = A0.w; A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ); P4 = A0.w; CHECKREG r0, 0xFFFB3578; CHECKREG r1, 0x86BCFEC7; CHECKREG r2, 0xF2CF3598; CHECKREG r3, 0x00860007; CHECKREG r4, 0xF70DA834; CHECKREG r5, 0x1235860B; CHECKREG r6, 0xFF221DD6; CHECKREG r7, 0x678E0086; CHECKREG p1, 0xFF221DD6; CHECKREG p2, 0xFFFB3578; CHECKREG p3, 0xF2CF3598; CHECKREG p4, 0xF70DA834; CHECKREG p5, 0xFF910EEB; imm32 r0, 0x98764abd; imm32 r1, 0xa1bcf4c7; imm32 r2, 0xa1145649; imm32 r3, 0x00010005; imm32 r4, 0xefbc1569; imm32 r5, 0x1235010b; imm32 r6, 0x000c001d; imm32 r7, 0x678e0001; R4 = ( A0 -= R1.L * R0.L ); P1 = A0.w; R0 = ( A0 = R2.H * R3.L ); P2 = A0.w; R2 = ( A0 += R4.H * R5.H ); P3 = A0.w; R0 = ( A0 += R6.L * R7.H ); P4 = A0.w; CHECKREG r0, 0xFFBC8F22; CHECKREG r1, 0xA1BCF4C7; CHECKREG r2, 0xFFA518F6; CHECKREG r3, 0x00010005; CHECKREG r4, 0xFD9B2E5E; CHECKREG r5, 0x1235010B; CHECKREG r6, 0x000C001D; CHECKREG r7, 0x678E0001; CHECKREG p1, 0xFD9B2E5E; CHECKREG p2, 0xFFFC4AC8; CHECKREG p3, 0xFFA518F6; CHECKREG p4, 0xFFBC8F22; imm32 r0, 0x7136459d; imm32 r1, 0xabd69ec7; imm32 r2, 0x71145679; imm32 r3, 0x08010007; imm32 r4, 0xef9c1569; imm32 r5, 0x1225010b; imm32 r6, 0x0003401d; imm32 r7, 0x678e0561; A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ); P1 = A0.w; R6 = ( A0 -= R2.H * R3.L ); P2 = A0.w; A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ); P3 = A0.w; R4 = ( A0 += R6.L * R7.H ); P4 = A0.w; CHECKREG r0, 0xC39B0E3E; CHECKREG r1, 0xABD69EC7; CHECKREG r2, 0x71145679; CHECKREG r3, 0x08010007; CHECKREG r4, 0xA26DF406; CHECKREG r5, 0x1225010B; CHECKREG r6, 0xCB19D6FE; CHECKREG r7, 0x678E0561; CHECKREG p1, 0xCB200616; CHECKREG p2, 0xCB19D6FE; CHECKREG p3, 0xC39B0E3E; CHECKREG p4, 0xA26DF406; imm32 r0, 0x123489bd; imm32 r1, 0x91bcfec7; imm32 r2, 0xa9145679; imm32 r3, 0xd0910007; imm32 r4, 0xedb91569; imm32 r5, 0xd235910b; imm32 r6, 0x0d0c0999; imm32 r7, 0x67de0009; R0 = ( A0 = R5.L * R3.L ); P1 = A0.w; A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ); P2 = A0.w; A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ); P3 = A0.w; R6 = ( A0 += R4.L * R6.H ); P4 = A0.w; CHECKREG r0, 0xFFF9EE9A; CHECKREG r1, 0x91BCFEC7; CHECKREG r2, 0x00D48D18; CHECKREG r3, 0xD0910007; CHECKREG r4, 0x00DA3B3C; CHECKREG r5, 0xD235910B; CHECKREG r6, 0x06E3E0DC; CHECKREG r7, 0x67DE0009; CHECKREG p1, 0xFFF9EE9A; CHECKREG p2, 0x00D48D18; CHECKREG p3, 0x00DA3B3C; CHECKREG p4, 0x06E3E0DC; pass
tactcomplabs/xbgas-binutils-gdb	4,507	sim/testsuite/bfin/c_dsp32shift_af_s.s	//Original:/proj/frio/dv/testcases/core/c_dsp32shift_af_s/c_dsp32shift_af_s.dsp // Spec Reference: dsp32shift ashift s # mach: bfin .include "testutils.inc" start // ashift : mix data, count (+)= (half reg) // d_reg = ashift (d BY d_lo) // Rx by RLx imm32 r0, 0x01230001; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x856789ab; imm32 r5, 0x96789abc; imm32 r6, 0xa789abcd; imm32 r7, 0xb89abcde; R4 = ASHIFT R0 BY R0.L (S); R5 = ASHIFT R1 BY R0.L (S); R6 = ASHIFT R2 BY R0.L (S); R7 = ASHIFT R3 BY R0.L (S); CHECKREG r4, 0x02460002; CHECKREG r5, 0x2468ACF0; CHECKREG r6, 0x468ACF12; CHECKREG r7, 0x68ACF134; imm32 r0, 0x01230002; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x956789ab; imm32 r5, 0xa6789abc; imm32 r6, 0xb789abcd; imm32 r7, 0xc89abcde; R1.L = 5; R5 = ASHIFT R0 BY R1.L (S); R6 = ASHIFT R1 BY R1.L (S); R7 = ASHIFT R2 BY R1.L (S); R4 = ASHIFT R3 BY R1.L (S); CHECKREG r4, 0x7FFFFFFF; CHECKREG r5, 0x24600040; CHECKREG r6, 0x7FFFFFFF; CHECKREG r7, 0x7FFFFFFF; imm32 r0, 0x01230002; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R2 = 14; R6 = ASHIFT R0 BY R2.L (S); R7 = ASHIFT R1 BY R2.L (S); R4 = ASHIFT R2 BY R2.L (S); R5 = ASHIFT R3 BY R2.L (S); CHECKREG r4, 0x00038000; CHECKREG r5, 0x7FFFFFFF; CHECKREG r6, 0x7FFFFFFF; CHECKREG r7, 0x7FFFFFFF; imm32 r0, 0x01230002; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0xa56789ab; imm32 r5, 0xb6789abc; imm32 r6, 0xc789abcd; imm32 r7, 0xd89abcde; R3.L = 15; R7 = ASHIFT R0 BY R3.L (S); R6 = ASHIFT R1 BY R3.L (S); R5 = ASHIFT R2 BY R3.L (S); R4 = ASHIFT R3 BY R3.L (S); CHECKREG r4, 0x7FFFFFFF; CHECKREG r5, 0x7FFFFFFF; CHECKREG r6, 0x7FFFFFFF; CHECKREG r7, 0x7FFFFFFF; imm32 r0, 0x01230002; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R4.L = -1; R7 = ASHIFT R0 BY R4.L; R0 = ASHIFT R1 BY R4.L; R1 = ASHIFT R2 BY R4.L; R2 = ASHIFT R3 BY R4.L; R3 = ASHIFT R4 BY R4.L; R4 = ASHIFT R5 BY R4.L; R5 = ASHIFT R6 BY R4.L; R6 = ASHIFT R7 BY R4.L; CHECKREG r0, 0x091A2B3C; CHECKREG r1, 0x11A2B3C4; CHECKREG r2, 0x1A2B3C4D; CHECKREG r3, 0x22B3FFFF; CHECKREG r4, 0x2B3C4D5E; CHECKREG r5, 0x40000000; CHECKREG r6, 0x40000000; CHECKREG r7, 0x00918001; imm32 r0, 0x01230002; imm32 r1, 0x82345678; imm32 r2, 0x93456789; imm32 r3, 0xa456789a; imm32 r4, 0xb56789ab; imm32 r5, 0xc6789abc; imm32 r6, 0xd789abcd; imm32 r7, 0xe89abcde; R5.L = -6; R6 = ASHIFT R0 BY R5.L (S); R7 = ASHIFT R1 BY R5.L (S); R0 = ASHIFT R2 BY R5.L (S); R1 = ASHIFT R3 BY R5.L (S); R2 = ASHIFT R4 BY R5.L (S); R3 = ASHIFT R5 BY R5.L (S); R4 = ASHIFT R6 BY R5.L (S); R5 = ASHIFT R7 BY R5.L (S); CHECKREG r0, 0xFE4D159E; CHECKREG r1, 0xFE9159E2; CHECKREG r2, 0xFED59E26; CHECKREG r3, 0xFF19E3FF; CHECKREG r4, 0x00001230; CHECKREG r5, 0xFFF82345; CHECKREG r6, 0x00048C00; CHECKREG r7, 0xFE08D159; imm32 r0, 0x01230002; imm32 r1, 0x12345678; imm32 r2, 0x23456789; imm32 r3, 0x3456789a; imm32 r4, 0x456789ab; imm32 r5, 0x56789abc; imm32 r6, 0x6789abcd; imm32 r7, 0x789abcde; R6.L = -15; R5 = ASHIFT R0 BY R6.L (S); R0 = ASHIFT R1 BY R6.L (S); R7 = ASHIFT R2 BY R6.L (S); R0 = ASHIFT R3 BY R6.L (S); R1 = ASHIFT R4 BY R6.L (S); R2 = ASHIFT R5 BY R6.L (S); R3 = ASHIFT R6 BY R6.L (S); R6 = ASHIFT R7 BY R6.L (S); CHECKREG r0, 0x000068AC; CHECKREG r1, 0x00008ACF; CHECKREG r2, 0x00000000; CHECKREG r3, 0x0000CF13; CHECKREG r4, 0x456789AB; CHECKREG r5, 0x00000246; CHECKREG r6, 0x00000000; CHECKREG r7, 0x0000468A; imm32 r0, 0x01230002; imm32 r1, 0x82345678; imm32 r2, 0x93456789; imm32 r3, 0xa456789a; imm32 r4, 0xb56789ab; imm32 r5, 0xc6789abc; imm32 r6, 0xd789abcd; imm32 r7, 0xe89abcde; R7.L = -14; R0 = ASHIFT R0 BY R7.L (S); R1 = ASHIFT R1 BY R7.L (S); R2 = ASHIFT R2 BY R7.L (S); R3 = ASHIFT R3 BY R7.L (S); R4 = ASHIFT R4 BY R7.L (S); R5 = ASHIFT R5 BY R7.L (S); R6 = ASHIFT R6 BY R7.L (S); R7 = ASHIFT R7 BY R7.L (S); CHECKREG r0, 0x0000048C; CHECKREG r1, 0xFFFE08D1; CHECKREG r2, 0xFFFE4D15; CHECKREG r3, 0xFFFE9159; CHECKREG r4, 0xFFFED59E; CHECKREG r5, 0xFFFF19E2; CHECKREG r6, 0xFFFF5E26; CHECKREG r7, 0xFFFFA26B; pass
tactcomplabs/xbgas-binutils-gdb	2,290	sim/testsuite/bfin/c_ccmv_ncc_dr_dr.s	//Original:/testcases/core/c_ccmv_ncc_dr_dr/c_ccmv_ncc_dr_dr.dsp // Spec Reference: ccmv !cc dreg = dreg # mach: bfin .include "testutils.inc" start R0 = 0; ASTAT = R0; imm32 r0, 0x808d2301; imm32 r1, 0x90021053; imm32 r2, 0x21041405; imm32 r3, 0x60261507; imm32 r4, 0x50447609; imm32 r5, 0xdfe5500b; imm32 r6, 0x2a0c660d; imm32 r7, 0xd90e1b8f; IF !CC R0 = R0; IF !CC R1 = R3; IF !CC R2 = R5; IF !CC R3 = R2; CC = ! CC; IF !CC R4 = R6; IF !CC R5 = R1; IF !CC R6 = R7; CC = ! CC; IF !CC R7 = R4; CHECKREG r0, 0x808D2301; CHECKREG r1, 0x60261507; CHECKREG r2, 0xDFE5500B; CHECKREG r3, 0xDFE5500B; CHECKREG r4, 0x50447609; CHECKREG r5, 0xDFE5500B; CHECKREG r6, 0x2A0C660D; CHECKREG r7, 0x50447609; imm32 r0, 0x308d2301; imm32 r1, 0xd4023053; imm32 r2, 0x2f041405; imm32 r3, 0x60f61507; imm32 r4, 0xd0487f09; imm32 r5, 0x300b900b; imm32 r6, 0x2a0cd60d; imm32 r7, 0xd90e189f; IF !CC R4 = R3; IF !CC R5 = R7; IF !CC R6 = R1; IF !CC R7 = R2; CC = ! CC; IF !CC R0 = R6; IF !CC R1 = R5; IF !CC R2 = R4; CC = ! CC; IF !CC R3 = R0; CHECKREG r0, 0x308D2301; CHECKREG r1, 0xD4023053; CHECKREG r2, 0x2F041405; CHECKREG r3, 0x308D2301; CHECKREG r4, 0x60F61507; CHECKREG r5, 0xD90E189F; CHECKREG r6, 0xD4023053; CHECKREG r7, 0x2F041405; imm32 r0, 0x708d2301; imm32 r1, 0xd8021053; imm32 r2, 0x2f041405; imm32 r3, 0x65b61507; imm32 r4, 0x59487609; imm32 r5, 0x3005900b; imm32 r6, 0x2abc660d; imm32 r7, 0xd90e108f; IF !CC R0 = R2; IF !CC R1 = R3; CC = ! CC; IF !CC R2 = R5; IF !CC R3 = R7; CC = ! CC; IF !CC R4 = R1; IF !CC R5 = R4; IF !CC R6 = R7; IF !CC R7 = R6; CHECKREG r0, 0x2F041405; CHECKREG r1, 0x65B61507; CHECKREG r2, 0x2F041405; CHECKREG r3, 0x65B61507; CHECKREG r4, 0x65B61507; CHECKREG r5, 0x65B61507; CHECKREG r6, 0xD90E108F; CHECKREG r7, 0xD90E108F; imm32 r0, 0xc08d2301; imm32 r1, 0xdb021053; imm32 r2, 0x2f041405; imm32 r3, 0x64b61507; imm32 r4, 0x50487609; imm32 r5, 0x30f5900b; imm32 r6, 0x2a4c660d; imm32 r7, 0x895e108f; IF !CC R4 = R3; IF !CC R5 = R7; CC = ! CC; IF !CC R6 = R2; IF !CC R7 = R6; CC = ! CC; IF !CC R0 = R1; IF !CC R1 = R2; IF !CC R2 = R0; IF !CC R3 = R4; CHECKREG r0, 0xDB021053; CHECKREG r1, 0x2F041405; CHECKREG r2, 0xDB021053; CHECKREG r3, 0x64B61507; CHECKREG r4, 0x64B61507; CHECKREG r5, 0x895E108F; CHECKREG r6, 0x2A4C660D; CHECKREG r7, 0x895E108F; pass
tactcomplabs/xbgas-binutils-gdb	5,681	sim/testsuite/bfin/iir.s	# mach: bfin // GENERIC BIQUAD: // --------------- // x ---------+---------\|---------+-------y // \| \|t1 \| // \| D \| // \| a1 \| b1 \| // +---<-----\|---->----+ // \| \| \| // \| D \| D's are delays // \| a2 \| b2 \| ">" represent multiplications // +---<-----\|---->----+ // To test this routine, use a biquad with a pole pair at z = (0.7 +- 0.1j), // and a double zero at z = -1.0, which is a low-pass. The transfer function is: // 1 + 2z^-1 + z^-2 // H(z) = ---------------------- // 1 - 1.4z^-1 + 0.5z^-2 // a1 = 1.4 // a2 = -0.5 // b1 = 2 // b2 = 1 // This filter conforms to the biquad test in BDT, since it has coefficients // larger than 1.0 in magnitude, and b0=1. (Note that the a's have a negative // sign.) // This filter can be simulated in matlab. To simulate one biquad, use // A = [1.0, -1.4, 0.5] // B = [1, 2, 1] // Y=filter(B,A,X) // To simulate two cascaded biquads, use // Y=filter(B,A,filter(B,A,X)) // SCALED COEFFICIENTS: // -------------------- // In order to conform to 1.15 representation, must scale coeffs by 0.5. // This requires an additional internal re-scale. The equations for the Type II // filter are: // t1 = x + a1t1z^-1 + a2t1z^-2 // y = b0t1 + b1t1z^-1 + b2t1z^-2 // (Note inclusion of term b0, which in the example is b0 = 1.) // If all coeffs are replaced by // ai --> ai' = 0.5a1 // then the two equations become // t1 = x + 2a1't1z^-1 + 2a2't1z^-2 // 0.5y = b0't1 + b1't1z^-1 + b2't1z^-2 // which can be implemented as: // 2.0 b0'=0.5 // x ---------+--->-----\|---->----+-------y // \| \|t1 \| // \| D \| // \| a1' \| b1' \| // +---<-----\|---->----+ // \| \| \| // \| D \| // \| a2' \| b2' \| // +---<-----\|---->----+ // But, b0' can be eliminated by: // x ---------+---------\|---------+-------y // \| \| \| // \| V 2.0 \| // \| \| \| // \| \|t1 \| // \| D \| // \| a1' \| b1' \| // +---<-----\|---->----+ // \| \| \| // \| D \| // \| a2' \| b2' \| // +---<-----\|---->----+ // Function biquadf() computes this implementation on float data. // CASCADED BIQUADS // ---------------- // Cascaded biquads are simulated by simply cascading copies of the // filter defined above. However, one must be careful with the resulting // filter, as it is not very stable numerically (double poles in the // vecinity of +1). It would of course be better to cascade different // filters, as that would result in more stable structures. // The functions biquadf() and biquadR() have been tested with up to 3 // stages using this technique, with inputs having small signal amplitude // (less than 0.001) and under 300 samples. // // In order to pipeline, need to maintain two pointers into the state // array: one to load (I0) and one to store (I2). This is required since // the load of iteration i+1 is hoisted above the store of iteration i. .include "testutils.inc" start // I3 points to input buffer loadsym I3, input; // P1 points to output buffer loadsym P1, output; R0 = 0; R7 = 0; P2 = 10; LSETUP ( L$0 , L$0end ) LC0 = P2; L$0: // I0 and I2 are pointers to state loadsym I0, state; I2 = I0; // pointer to coeffs loadsym I1, Coeff; R0.H = W [ I3 ++ ]; // load input value into RH0 A0.w = R0; // A0 holds x P2 = 2; LSETUP ( L$1 , L$1end ) LC1 = P2; // load 2 coeffs into R1 and R2 // load state into R3 R1 = [ I1 ++ ]; MNOP \|\| R2 = [ I1 ++ ] \|\| R3 = [ I0 ++ ]; L$1: // A1=b1s0 A0=a1s0+x A1 = R1.L * R3.L, A0 += R1.H * R3.L \|\| R1 = [ I1 ++ ] \|\| NOP; // A1+=b2s1 A0+=a2s1 // and move scaled value in A0 (t1) into RL4 A1 += R2.L * R3.H, R4.L = ( A0 += R2.H * R3.H ) (S2RND) \|\| R2 = [ I1 ++ ] \|\| NOP; // Advance state. before: // R4 = uuuu t1 // R3 = stat[1] stat[0] // after PACKLL: // R3 = stat[0] t1 R5 = PACK( R3.L , R4.L ) \|\| R3 = [ I0 ++ ] \|\| NOP; // collect output into A0, and move to RL0. // Keep output value in A0, since it is also // the accumulator used to store the input to // the next stage. Also, store updated state L$1end: R0.L = ( A0 += A1 ) \|\| [ I2 ++ ] = R5 \|\| NOP; // store output L$0end: W [ P1 ++ ] = R0; // Check results loadsym I2, output; R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0028 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0110 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0373 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x075b ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x0c00 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1064 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x13d3 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x15f2 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x16b9 ); R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x1650 ); pass .data state: .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .data Coeff: .dw 0x7fff .dw 0x5999 .dw 0x4000 .dw 0xe000 .dw 0x7fff .dw 0x5999 .dw 0x4000 .dw 0xe000 input: .dw 0x0028 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 output: .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000 .dw 0x0000
tactcomplabs/xbgas-binutils-gdb	4,334	sim/testsuite/bfin/c_interr_loopsetup_stld.S	//Original:/proj/frio/dv/testcases/core/c_interr_loopsetup_stld/c_interr_loopsetup_stld.dsp // Spec Reference: interrupt loopsetup_ldst # mach: bfin #include "test.h" .include "testutils.inc" start A0 = 0; // reset accumulators A1 = 0; P1 = 3; P2 = 4; LD32(r0, 0x00200005); LD32(r1, 0x00300010); LD32(r2, 0x00500012); LD32(r3, 0x00600024); LD32(r4, 0x00700016); LD32(r5, 0x00900028); LD32(r6, 0x0a000030); LD32(r7, 0x00b00044); loadsym I0, DATA0; loadsym I1, DATA1; R0 = [ I0 ++ ]; R1 = [ I1 ++ ]; LSETUP ( start1 , end1 ) LC0 = P1; start1: R0 += 1; R1 += 2; A1 += R0.H * R1.H, A0 += R0.L * R1.L \|\| R0 = [ I0 ++ ] \|\| R1 = [ I1 ++ ]; // dsp32mac dual // a1 += hh, a0 += ll (r0,r1) ; r0 = [i0++]; r1 = [i1++]; // dsp32mac R2 = ( R2 + R5 ) << 1; // alu2op DIVQ ( R5 , R3 ); R1 <<= R5; R1 >>>= R1; R6 = ~ R0; //MY_GEN_INT(10, 1) DIVQ ( R5 , R2 ); R0 = R3.B (X); DIVS ( R7 , R0 ); end1: R2 += 3; R3 = ( A0 += A1 ); CHECKREG(r0, 0x00000024); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x0670098D); CHECKREG(r3, 0x000015EC); CHECKREG(r4, 0x00700016); CHECKREG(r5, 0x0B240A39); CHECKREG(r6, 0xFFF2FFFC); CHECKREG(r7, 0x05800220); A0 = 0; A1 = 0; LSETUP ( start2 , end2 ) LC0 = P2; start2: R4 += 4; //a1 += hh, a0 += ll (r0,r1), r0 = [i0--], r1 = [i1--]; A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I0 -- ]; R1 = [ I1 -- ]; R1 <<= R5; R6 = R7.B (Z); R2 = - R6; R3 = R4.L (Z); DIVS ( R1 , R1 ); R6 = - R0; R0 >>= R0; DIVS ( R4 , R7 ); //MY_GEN_INT(13, 1) R1 = R2.L (Z); end2: R5 += -5; R6 = ( A0 += A1 ); CHECKREG(r0, 0x00000000); CHECKREG(r1, 0x0000FFE0); CHECKREG(r2, 0xFFFFFFE0); CHECKREG(r3, 0x000000EC); CHECKREG(r4, 0x070001D8); CHECKREG(r5, 0x0B240A25); CHECKREG(r6, 0x00000000); CHECKREG(r7, 0x05800220); LD32(r0, 0x01200805); LD32(r1, 0x02300710); LD32(r2, 0x03500612); LD32(r3, 0x04600524); LD32(r4, 0x05700416); LD32(r5, 0x06900328); LD32(r6, 0x0a700230); LD32(r7, 0x08b00044); loadsym I2, DATA0; loadsym I3, DATA1; [ I2 ++ ] = R0; [ I3 ++ ] = R1; LSETUP ( start3 , end3 ) LC0 = P1; start3: [ I2 ++ ] = R2; [ I3 ++ ] = R3; R2 += 1; end3: R3 += 1; A0 = 0; A1 = 0; LSETUP ( start4 , end4 ) LC0 = P2; R0 = [ I0 -- ]; R1 = [ I1 -- ]; start4: // a1 += hh, a0 += ll (r0,r1), r0 = [i2--], r1 = [i3--]; A1 += R0.H * R1.H, A0 += R0.L * R1.L; R0 = [ I2 -- ]; R1 = [ I3 -- ]; R4 = R4 + R0; // comp3op R5 = R7.L (Z); R4 >>>= R5; R0 = R7.B (X); DIVQ ( R6 , R6 ); //MY_GEN_INT(7, 1) end4: R5 = R5 + R1; R6 = ( A0 += A1 ); R7 = ( A0 += A1 ); CHECKREG(r0, 0x00000044); CHECKREG(r1, 0x04600524); CHECKREG(r2, 0x03500615); CHECKREG(r3, 0x04600527); CHECKREG(r4, 0x00000000); CHECKREG(r5, 0x04600568); CHECKREG(r6, 0x007C3498); CHECKREG(r7, 0x00812098); pass; // End the test // // Data Segment // .data DATA0: .dd 0x000a0000 .dd 0x000b0001 .dd 0x000c0002 .dd 0x000d0003 .dd 0x000e0004 .dd 0x000f0005 .dd 0x00100006 .dd 0x00200007 .dd 0x00300008 .dd 0x00400009 .dd 0x0050000a .dd 0x0060000b .dd 0x0070000c .dd 0x0080000d .dd 0x0090000e .dd 0x0100000f .dd 0x02000010 .dd 0x03000011 .dd 0x04000012 .dd 0x05000013 .dd 0x06000014 .dd 0x001a0000 .dd 0x001b0001 .dd 0x001c0002 .dd 0x001d0003 .dd 0x00010004 .dd 0x00010005 .dd 0x02100006 .dd 0x02200007 .dd 0x02300008 .dd 0x02200009 .dd 0x0250000a .dd 0x0260000b .dd 0x0270000c .dd 0x0280000d .dd 0x0290000e .dd 0x2100000f .dd 0x22000010 .dd 0x22000011 .dd 0x24000012 .dd 0x25000013 .dd 0x26000014 DATA1: .dd 0x00f00100 .dd 0x00e00101 .dd 0x00d00102 .dd 0x00c00103 .dd 0x00b00104 .dd 0x00a00105 .dd 0x00900106 .dd 0x00800107 .dd 0x00100108 .dd 0x00200109 .dd 0x0030010a .dd 0x0040010b .dd 0x0050011c .dd 0x0060010d .dd 0x0070010e .dd 0x0080010f .dd 0x00900110 .dd 0x01000111 .dd 0x02000112 .dd 0x03000113 .dd 0x04000114 .dd 0x05000115 .dd 0x03f00100 .dd 0x03e00101 .dd 0x03d00102 .dd 0x03c00103 .dd 0x03b00104 .dd 0x03a00105 .dd 0x03900106 .dd 0x03800107 .dd 0x03100108 .dd 0x03200109 .dd 0x0330010a .dd 0x0330010b .dd 0x0350011c .dd 0x0360010d .dd 0x0370010e .dd 0x0380010f .dd 0x03900110 .dd 0x31000111 .dd 0x32000112 .dd 0x33000113 .dd 0x34000114
tactcomplabs/xbgas-binutils-gdb	7,522	sim/testsuite/bfin/c_seq_ex2_mmrj_mvpop.S	//Original:/proj/frio/dv/testcases/core/c_seq_ex2_mmrj_mvpop/c_seq_ex2_mmrj_mvpop.dsp // Spec Reference: sequencer stage ex2 ( mmr + jump + regmv + pushpopmultiple) # mach: bfin # sim: --environment operating #include "test.h" .include "testutils.inc" start include(std.inc) include(selfcheck.inc) include(gen_int.inc) INIT_R_REGS(0); INIT_P_REGS(0); INIT_I_REGS(0); // initialize the dsp address regs INIT_M_REGS(0); INIT_L_REGS(0); INIT_B_REGS(0); //CHECK_INIT(p5, 0xe0000000); include(symtable.inc) CHECK_INIT_DEF(p5); #ifndef STACKSIZE #define STACKSIZE 0x10 #endif #ifndef EVT #define EVT 0xFFE02000 #endif #ifndef EVT15 #define EVT15 0xFFE0203C #endif #ifndef EVT_OVERRIDE #define EVT_OVERRIDE 0xFFE02100 #endif #ifndef ITABLE #define ITABLE DATA_ADDR_1 #endif GEN_INT_INIT(ITABLE) // set location for interrupt table // // Reset/Bootstrap Code // (Here we should set the processor operating modes, initialize registers, // BOOT: // in reset mode now LD32_LABEL(sp, KSTACK); // setup the stack pointer FP = SP; // and frame pointer LD32(p0, EVT); // Setup Event Vectors and Handlers LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) [ P0 ++ ] = R0; LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) [ P0 ++ ] = R0; LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) [ P0 ++ ] = R0; LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) [ P0 ++ ] = R0; [ P0 ++ ] = R0; // IVT4 not used LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) [ P0 ++ ] = R0; LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) [ P0 ++ ] = R0; LD32_LABEL(r0, I7HANDLE); // IVG7 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I8HANDLE); // IVG8 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I9HANDLE); // IVG9 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I10HANDLE);// IVG10 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I11HANDLE);// IVG11 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I12HANDLE);// IVG12 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I13HANDLE);// IVG13 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I14HANDLE);// IVG14 Handler [ P0 ++ ] = R0; LD32_LABEL(r0, I15HANDLE);// IVG15 Handler [ P0 ++ ] = R0; LD32(p0, EVT_OVERRIDE); R0 = 0; [ P0 ++ ] = R0; R0 = -1; // Change this to mask interrupts () [ P0 ] = R0; // IMASK CSYNC; DUMMY: R0 = 0 (Z); LT0 = r0; // set loop counters to something deterministic LB0 = r0; LC0 = r0; LT1 = r0; LB1 = r0; LC1 = r0; ASTAT = r0; // reset other internal regs // The following code sets up the test for running in USER mode LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a // ReturnFromInterrupt (RTI) RETI = r0; // We need to load the return address // Comment the following line for a USER Mode test JUMP STARTSUP; // jump to code start for SUPERVISOR mode RTI; STARTSUP: LD32_LABEL(p1, BEGIN); LD32(p0, EVT15); [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in // SUPERVISOR MODE & go to different RAISE in supervisor mode // until the end of the test. NOP; // Workaround for Bug 217 RTI; // // The Main Program // STARTUSER: LD32_LABEL(sp, USTACK); // setup the stack pointer FP = SP; // set frame pointer JUMP BEGIN; //****************************************************************** BEGIN: // COMMENT the following line for USER MODE tests [ -- SP ] = RETI; // enable interrupts in supervisor mode // YOUR CODE GOES HERE // PUT YOUR TEST HERE! // PUSH LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 LD32(p2, DATA_ADDR_1); LD32(p3, 0xab5fd490); LD32(p4, 0xa581bd94); LD32(r2, 0x14789232); [ P1 ] = R2; CSYNC; R0 = 0x01; R1 = 0x02; R2 = 0x03; R3 = 0x04; R4 = 0x05; R5 = 0x06; R6 = 0x07; R7 = 0x08; [ -- SP ] = ( R7:0 ); // RAISE 2; // RTN [ P1 ] = R0; JUMP.S LABEL1; P1 = R1; R2 = P1; [ -- SP ] = ( R7:0 ); R1 = 0x12; R2 = 0x13; R3 = 0x14; R4 = 0x15; R5 = 0x16; R6 = 0x17; R7 = 0x18; LABEL1: // RAISE 5; // RTI P2 = R2; R3 = P2; [ -- SP ] = ( R7:0 ); R2 = 0x23; R3 = 0x24; R4 = 0x25; R5 = 0x26; R6 = 0x27; R7 = 0x28; // wrt-rd EVT5 = 0xFFE02034 LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034 // RAISE 6; // RTI R0 = [ P1 ]; JUMP.S LABEL2; P3 = R3; R4 = P3; [ -- SP ] = ( R7:0 ); // POP R0 = 0x00; R1 = 0x00; R2 = 0x00; R3 = 0x00; R4 = 0x00; R5 = 0x00; R6 = 0x00; R7 = 0x00; LABEL2: CHECKREG(r0, 0x00000001); // RAISE 7; // RTI P4 = R4; R5 = P4; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000003); CHECKREG(r3, 0x00000003); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); // wrt-rd EVT13 = 0xFFE02034 LD32(p1, 0xFFE02034); // RAISE 8; // RTI R0 = [ P1 ]; JUMP.S LABEL3; P1 = R5; R6 = P1; ( R7:0 ) = [ SP ++ ]; //CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped //CHECKREG(r1, 0x000000b2); // so they cannot appear here //CHECKREG(r2, 0x000000c3); //CHECKREG(r3, 0x000000d4); //CHECKREG(r4, 0x000000e5); //CHECKREG(r5, 0x000000f6); //CHECKREG(r6, 0x00000017); //CHECKREG(r7, 0x00000028); R0 = 12; R1 = 13; R2 = 14; R3 = 15; R4 = 16; R5 = 17; R6 = 18; R7 = 19; LABEL3: CHECKREG(r0, 0x00000001); // RAISE 9; // RTI P2 = R6; R7 = P2; ( R7:0 ) = [ SP ++ ]; CHECKREG(r0, 0x00000001); CHECKREG(r1, 0x00000002); CHECKREG(r2, 0x00000003); CHECKREG(r3, 0x00000004); CHECKREG(r4, 0x00000005); CHECKREG(r5, 0x00000006); CHECKREG(r6, 0x00000007); CHECKREG(r7, 0x00000008); R0 = I0; R1 = I1; R2 = I2; R3 = I3; CHECKREG(r0, 0x00000000); CHECKREG(r1, 0x00000000); CHECKREG(r2, 0x00000000); CHECKREG(r3, 0x00000000); END: dbg_pass; // End the test //******************************************************************* // // Handlers for Events // EHANDLE: // Emulation Handler 0 RTE; RHANDLE: // Reset Handler 1 RTI; NHANDLE: // NMI Handler 2 I0 += 2; RTN; XHANDLE: // Exception Handler 3 R1 = 3; RTX; HWHANDLE: // HW Error Handler 5 I1 += 2; RTI; THANDLE: // Timer Handler 6 I2 += 2; RTI; I7HANDLE: // IVG 7 Handler I3 += 2; RTI; I8HANDLE: // IVG 8 Handler I0 += 2; RTI; I9HANDLE: // IVG 9 Handler I0 += 2; RTI; I10HANDLE: // IVG 10 Handler R7 = 10; RTI; I11HANDLE: // IVG 11 Handler I0 = R0; I1 = R1; I2 = R2; I3 = R3; M0 = R4; R0 = 11; RTI; I12HANDLE: // IVG 12 Handler R1 = 12; RTI; I13HANDLE: // IVG 13 Handler R2 = 13; RTI; I14HANDLE: // IVG 14 Handler R3 = 14; RTI; I15HANDLE: // IVG 15 Handler R4 = 15; RTI; NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug // // Data Segment // .data DATA: .space (0x10); // Stack Segments (Both Kernel and User) .space (STACKSIZE); KSTACK: .space (STACKSIZE); USTACK:
tactcomplabs/xbgas-binutils-gdb	3,017	sim/testsuite/bfin/s11.s	# mach: bfin // Shift test program. // Test instructions // RL0 = CC = BXOR (A0 AND R1) << 1; // RL0 = CC = BXOR A0 AND R1; // A0 <<=1 (BXOR A0 AND A1 CC); // RL3 = CC = BXOR A0 AND A1 CC; .include "testutils.inc" start init_r_regs 0; ASTAT = R0; // RL0 = CC = BXOR (A0 AND R1) << 1; R0.L = 0x1000; R0.H = 0x0000; A0.w = R0; R0.L = 0x0000; A0.x = R0.L; R1.L = 0xffff; R1.H = 0xffff; R2.L = CC = BXORSHIFT( A0 , R1 ); R0 = A0.w; DBGA ( R0.L , 0x2000 ); DBGA ( R0.H , 0x0000 ); R0.L = A0.x; DBGA ( R0.L , 0x0000 ); R0 = CC; DBGA ( R0.L , 0x0001 ); DBGA ( R0.H , 0x0000 ); DBGA ( R2.L , 0x0001 ); R0.L = 0x1000; R0.H = 0x0001; A0.w = R0; R0.L = 0x0000; A0.x = R0.L; R1.L = 0xffff; R1.H = 0xffff; R2.L = CC = BXORSHIFT( A0 , R1 ); R0 = A0.w; DBGA ( R0.L , 0x2000 ); DBGA ( R0.H , 0x0002 ); R0.L = A0.x; DBGA ( R0.L , 0x0000 ); R0 = CC; DBGA ( R0.L , 0x0000 ); DBGA ( R0.H , 0x0000 ); DBGA ( R2.L , 0x0000 ); R0.L = 0xffff; R0.H = 0xffff; A0.w = R0; R0.L = 0x00ff; A0.x = R0.L; R1.L = 0xffff; R1.H = 0xffff; R2.L = CC = BXORSHIFT( A0 , R1 ); R0 = A0.w; DBGA ( R0.L , 0xfffe ); DBGA ( R0.H , 0xffff ); R0.L = A0.x; DBGA ( R0.L , 0xffff ); R0 = CC; DBGA ( R0.L , 0x0001 ); DBGA ( R0.H , 0x0000 ); DBGA ( R2.L , 0x0001 ); // no R0.L = 0xffff; R0.H = 0xffff; A0.w = R0; R0.L = 0x00ff; A0.x = R0.L; R1.L = 0xffff; R1.H = 0xffff; R2.L = CC = BXOR( A0 , R1 ); R0 = A0.w; DBGA ( R0.L , 0xffff ); DBGA ( R0.H , 0xffff ); R0.L = A0.x; DBGA ( R0.L , 0xffff ); R0 = CC; DBGA ( R0.L , 0x0000 ); DBGA ( R0.H , 0x0000 ); DBGA ( R2.H , 0x0000 ); // A0 <<=1 (BXOR A0 AND A1 CC); R0.L = 0x1000; R0.H = 0x0000; A0.w = R0; R0.L = 0x0000; A0.x = R0.L; R0.L = 0xffff; R0.H = 0xffff; A1.w = R0; R0.L = 0x00ff; A1.x = R0.L; R0.L = 0x0000; R0.H = 0x0000; CC = R0; A0 = BXORSHIFT( A0 , A1, CC ); R0 = A0.w; DBGA ( R0.L , 0x2001 ); DBGA ( R0.H , 0x0000 ); R0.L = A0.x; DBGA ( R0.L , 0x0000 ); R0.L = 0x1000; R0.H = 0x0000; A0.w = R0; R0.L = 0x0000; A0.x = R0.L; R0.L = 0x0fff; R0.H = 0xffff; A1.w = R0; R0.L = 0x00ff; A1.x = R0.L; R0.L = 0x0000; R0.H = 0x0000; CC = R0; A0 = BXORSHIFT( A0 , A1, CC ); R0 = A0.w; DBGA ( R0.L , 0x2000 ); DBGA ( R0.H , 0x0000 ); R0.L = A0.x; DBGA ( R0.L , 0x0000 ); R0.L = 0x1000; R0.H = 0x0000; A0.w = R0; R0.L = 0x0000; A0.x = R0.L; R0.L = 0xffff; R0.H = 0xffff; A1.w = R0; R0.L = 0x00ff; A1.x = R0.L; R0.L = 0x0001; R0.H = 0x0000; CC = R0; A0 = BXORSHIFT( A0 , A1, CC ); R0 = A0.w; DBGA ( R0.L , 0x2000 ); DBGA ( R0.H , 0x0000 ); R0.L = A0.x; DBGA ( R0.L , 0x0000 ); // no R0.L = 0x1000; R0.H = 0x0000; A0.w = R0; R0.L = 0x0000; A0.x = R0.L; R0.L = 0xffff; R0.H = 0xffff; A1.w = R0; R0.L = 0x00ff; A1.x = R0.L; R0.L = 0x0000; R0.H = 0x0000; CC = R0; R2.L = CC = BXOR( A0 , A1, CC ); R0 = A0.w; DBGA ( R0.L , 0x1000 ); DBGA ( R0.H , 0x0000 ); R0.L = A0.x; DBGA ( R0.L , 0x0000 ); DBGA ( R2.L , 0x0001 ); R0 = CC; DBGA ( R0.L , 0x0001 ); pass
tactcomplabs/xbgas-binutils-gdb	1,426	sim/testsuite/bfin/c_br_preg_stall_ac.s	//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp // Spec Reference: brcc kills data cache hits # mach: bfin .include "testutils.inc" start /* This test likes to assume the current [SP] is valid */ SP += -12; imm32 r0, 0x00000000; imm32 r1, 0x00000001; imm32 r2, 0x00000002; imm32 r3, 0x00000003; imm32 r4, 0x00000004; imm32 r5, 0x00000005; imm32 r6, 0x00000006; imm32 r7, 0x00000007; imm32 p1, 0x00000011; imm32 p2, 0x00000012; .ifndef BFIN_HOST; imm32 p3, 0x00000013; .endif imm32 p4, 0x00000014; P1 = 4; P2 = 6; loadsym P5, DATA0; loadsym I0, DATA1; begin: ASTAT = R0; // clear CC R0 = CC; IF CC R1 = R0; [ SP ] = P2; P2 = [ SP ]; JUMP ( PC + P2 ); //brf LABEL1; // (bp); CC = R4 < R5; // CC FLAG killed R1 = 21; LABEL1: JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' CC = ! CC; LABEL2: JUMP ( PC + P1 ); //brf LABEL3; JUMP ( PC + P2 ); //BAD1; // UJUMP killed LABEL3: JUMP ( PC + P1 ); //brf LABELCHK1; BAD1: R7 = [ P5 ]; // LDST killed LABELCHK1: CHECKREG r0, 0x00000000; CHECKREG r1, 0x00000001; CHECKREG r2, 0x00000002; CHECKREG r3, 0x00000003; CHECKREG r4, 0x00000004; CHECKREG r5, 0x00000005; CHECKREG r6, 0x00000006; CHECKREG r7, 0x00000007; pass .data DATA0: .dd 0x000a0000 .dd 0x000b0001 .dd 0x000c0002 .dd 0x000d0003 .dd 0x000e0004 DATA1: .dd 0x00f00100 .dd 0x00e00101 .dd 0x00d00102 .dd 0x00c00103
tactcomplabs/xbgas-binutils-gdb	3,933	sim/testsuite/bfin/c_dsp32mult_pair_m_i.s	//Original:/testcases/core/c_dsp32mult_pair_m_i/c_dsp32mult_pair_m_i.dsp // Spec Reference: dsp32mult pair MUNOP i # mach: bfin .include "testutils.inc" start imm32 r0, 0x34235625; imm32 r1, 0x9f7a5127; imm32 r2, 0xa3286725; imm32 r3, 0x00069027; imm32 r4, 0xb0abc029; imm32 r5, 0x10acef2b; imm32 r6, 0xc00c00de; imm32 r7, 0xd246712f; R0 = R0.L * R0.L (IS); R2 = R0.L * R1.H (IS); R4 = R1.H * R1.H (IS); R6 = R0.L * R0.L (IS); CHECKREG r0, 0x1CFCE159; CHECKREG r1, 0x9F7A5127; CHECKREG r2, 0x0B8EAB6A; CHECKREG r3, 0x00069027; CHECKREG r4, 0x2464C624; CHECKREG r5, 0x10ACEF2B; CHECKREG r6, 0x03AB90F1; CHECKREG r7, 0xD246712F; imm32 r0, 0x5b23a635; imm32 r1, 0x6fba5137; imm32 r2, 0x1324b735; imm32 r3, 0x90060037; imm32 r4, 0x80abcd39; imm32 r5, 0xb0acef3b; imm32 r6, 0xa00c003d; imm32 r7, 0x12467003; R0 = R2.L * R2.L (IS); R2 = R2.L * R3.H (IS); R4 = R3.H * R2.H (IS); R6 = R2.L * R3.L (IS); CHECKREG r0, 0x14B2D0F9; CHECKREG r1, 0x6FBA5137; CHECKREG r2, 0x1FD71B3E; CHECKREG r3, 0x90060037; CHECKREG r4, 0xF212AF0A; CHECKREG r5, 0xB0ACEF3B; CHECKREG r6, 0x0005DA52; CHECKREG r7, 0x12467003; imm32 r0, 0x1b235655; imm32 r1, 0xc4ba5157; imm32 r2, 0x43246755; imm32 r3, 0x05060055; imm32 r4, 0x906bc509; imm32 r5, 0x10a7ef5b; imm32 r6, 0xb00c805d; imm32 r7, 0x1246795f; R0 = R4.L * R4.L (IS); R2 = R4.L * R5.H (IS); R4 = R5.H * R5.H (IS); R6 = R4.L * R5.L (IS); CHECKREG r0, 0x0D94DA51; CHECKREG r1, 0xC4BA5157; CHECKREG r2, 0xFC2A18DF; CHECKREG r3, 0x05060055; CHECKREG r4, 0x01154CF1; CHECKREG r5, 0x10A7EF5B; CHECKREG r6, 0xFAFF58AB; CHECKREG r7, 0x1246795F; imm32 r0, 0xbb235666; imm32 r1, 0xefba5166; imm32 r2, 0x13248766; imm32 r3, 0xf0060066; imm32 r4, 0x90ab9d69; imm32 r5, 0x10acef6b; imm32 r6, 0x800cb06d; imm32 r7, 0x1246706f; R0 = R6.L * R6.L (IS); R2 = R6.L * R7.H (IS); R4 = R7.H * R7.H (IS); R6 = R6.L * R7.L (IS); CHECKREG r0, 0x18BC0E69; CHECKREG r1, 0xEFBA5166; CHECKREG r2, 0xFA51E7CE; CHECKREG r3, 0xF0060066; CHECKREG r4, 0x014DEB24; CHECKREG r5, 0x10ACEF6B; CHECKREG r6, 0xDD0D2F43; CHECKREG r7, 0x1246706F; // mix order imm32 r0, 0xab23a675; imm32 r1, 0xcfba5127; imm32 r2, 0x13246705; imm32 r3, 0x00060007; imm32 r4, 0x90abcd09; imm32 r5, 0x10acdfdb; imm32 r6, 0x000c000d; imm32 r7, 0x1246f00f; R0 = R0.L * R7.L (IS); R2 = R1.L * R6.H (IS); R4 = R3.H * R4.H (IS); R6 = R4.L * R3.L (IS); CHECKREG r0, 0x059370DB; CHECKREG r1, 0xCFBA5127; CHECKREG r2, 0x0003CDD4; CHECKREG r3, 0x00060007; CHECKREG r4, 0xFFFD6402; CHECKREG r5, 0x10ACDFDB; CHECKREG r6, 0x0002BC0E; CHECKREG r7, 0x1246F00F; imm32 r0, 0xab235a75; imm32 r1, 0xcfba5127; imm32 r2, 0x13246905; imm32 r3, 0x00060007; imm32 r4, 0x90abcd09; imm32 r5, 0x10ace9db; imm32 r6, 0x000c0d0d; imm32 r7, 0x1246700f; R1 = R7.H * R0.H (IS); R3 = R6.H * R1.H (IS); R5 = R5.H * R2.L (IS); R7 = R4.L * R3.H (IS); CHECKREG r0, 0xAB235A75; CHECKREG r1, 0xF9F14192; CHECKREG r2, 0x13246905; CHECKREG r3, 0xFFFFB74C; CHECKREG r4, 0x90ABCD09; CHECKREG r5, 0x06D6DF5C; CHECKREG r6, 0x000C0D0D; CHECKREG r7, 0x000032F7; imm32 r0, 0x9b235675; imm32 r1, 0xc9ba5127; imm32 r2, 0x13946705; imm32 r3, 0x00090007; imm32 r4, 0x90ab9d09; imm32 r5, 0x10ace9db; imm32 r6, 0x000c009d; imm32 r7, 0x12467009; R1 = R6.H * R4.L (IS); R3 = R5.L * R3.H (IS); R5 = R3.H * R1.L (IS); R7 = R1.H * R2.H (IS); CHECKREG r0, 0x9B235675; CHECKREG r1, 0xFFFB5C6C; CHECKREG r2, 0x13946705; CHECKREG r3, 0xFFFF38B3; CHECKREG r4, 0x90AB9D09; CHECKREG r5, 0xFFFFA394; CHECKREG r6, 0x000C009D; CHECKREG r7, 0xFFFF9E1C; imm32 r0, 0xeb235675; imm32 r1, 0xceba5127; imm32 r2, 0x13e46705; imm32 r3, 0x000e0007; imm32 r4, 0x90abed09; imm32 r5, 0x10aceedb; imm32 r6, 0x000c00ed; imm32 r7, 0x1246700e; R1 = R4.L * R0.H (IS); R3 = R6.H * R1.H (IS); R5 = R1.L * R2.L (IS); R7 = R4.H * R2.L (IS); CHECKREG r0, 0xEB235675; CHECKREG r1, 0x018BAB3B; CHECKREG r2, 0x13E46705; CHECKREG r3, 0x00001284; CHECKREG r4, 0x90ABED09; CHECKREG r5, 0xDDE31527; CHECKREG r6, 0x000C00ED; CHECKREG r7, 0xD332A057; pass
tactcomplabs/xbgas-binutils-gdb	14,295	sim/testsuite/bfin/c_ldst_st_p_d_pp.s	//Original:testcases/core/c_ldst_st_p_d_pp/c_ldst_st_p_d_pp.dsp // Spec Reference: c_ldst st_p++ d # mach: bfin .include "testutils.inc" start // set all regs INIT_I_REGS -1; init_b_regs 0; init_l_regs 0; init_m_regs -1; I0 = P3; I2 = SP; imm32 r0, 0x0a231507; imm32 r1, 0x1b342618; imm32 r2, 0x2c453729; imm32 r3, 0x3d56483a; imm32 r4, 0x4e67594b; imm32 r5, 0x5f786a5c; imm32 r6, 0x60897b6d; imm32 r7, 0x719a8c7e; // initial values I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_1; loadsym p1, DATA_ADDR_2; loadsym p2, DATA_ADDR_3; loadsym i1, DATA_ADDR_4; loadsym p4, DATA_ADDR_5; loadsym fp, DATA_ADDR_6; loadsym i3, DATA_ADDR_7; P3 = I1; SP = I3; [ P5 ++ ] = R0; [ P1 ++ ] = R1; [ P2 ++ ] = R2; [ P3 ++ ] = R3; [ P4 ++ ] = R4; [ FP ++ ] = R5; [ SP ++ ] = R6; [ P5 ++ ] = R1; [ P1 ++ ] = R2; [ P2 ++ ] = R3; [ P3 ++ ] = R4; [ P4 ++ ] = R5; [ FP ++ ] = R6; [ SP ++ ] = R7; [ P5 ++ ] = R2; [ P1 ++ ] = R3; [ P2 ++ ] = R4; [ P3 ++ ] = R5; [ P4 ++ ] = R6; [ FP ++ ] = R7; [ SP ++ ] = R0; [ P5 ++ ] = R3; [ P1 ++ ] = R4; [ P2 ++ ] = R5; [ P3 ++ ] = R6; [ P4 ++ ] = R7; [ FP ++ ] = R0; [ SP ++ ] = R1; [ P5 ++ ] = R4; [ P1 ++ ] = R5; [ P2 ++ ] = R6; [ P3 ++ ] = R7; [ P4 ++ ] = R0; [ FP ++ ] = R1; [ SP ++ ] = R2; [ P5 ++ ] = R5; [ P1 ++ ] = R6; [ P2 ++ ] = R7; [ P3 ++ ] = R0; [ P4 ++ ] = R1; [ FP ++ ] = R2; [ SP ++ ] = R3; [ P5 ++ ] = R6; [ P1 ++ ] = R7; [ P2 ++ ] = R0; [ P3 ++ ] = R1; [ P4 ++ ] = R2; [ FP ++ ] = R3; [ SP ++ ] = R4; [ P5 ++ ] = R7; [ P1 ++ ] = R0; [ P2 ++ ] = R1; [ P3 ++ ] = R2; [ P4 ++ ] = R3; [ FP ++ ] = R4; [ SP ++ ] = R5; // Read back and check I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_1; loadsym p1, DATA_ADDR_2; loadsym p2, DATA_ADDR_3; loadsym i1, DATA_ADDR_4; loadsym p4, DATA_ADDR_5; loadsym fp, DATA_ADDR_6; loadsym i3, DATA_ADDR_7; P3 = I1; SP = I3; R0 = [ P1 ++ ]; R1 = [ P2 ++ ]; R2 = [ P3 ++ ]; R3 = [ P4 ++ ]; R4 = [ P5 ++ ]; R5 = [ FP ++ ]; R6 = [ SP ++ ]; CHECKREG r0, 0x1B342618; CHECKREG r1, 0x2C453729; CHECKREG r2, 0x3D56483A; CHECKREG r3, 0x4E67594B; CHECKREG r4, 0x0A231507; CHECKREG r5, 0x5F786A5C; CHECKREG r6, 0x60897B6D; CHECKREG r7, 0x719A8C7E; R1 = [ P1 ++ ]; R2 = [ P2 ++ ]; R3 = [ P3 ++ ]; R4 = [ P4 ++ ]; R5 = [ P5 ++ ]; R6 = [ FP ++ ]; R7 = [ SP ++ ]; CHECKREG r0, 0x1B342618; CHECKREG r1, 0x2C453729; CHECKREG r2, 0x3D56483A; CHECKREG r3, 0x4E67594B; CHECKREG r4, 0x5F786A5C; CHECKREG r5, 0x1B342618; CHECKREG r6, 0x60897B6D; CHECKREG r7, 0x719A8C7E; R2 = [ P1 ++ ]; R3 = [ P2 ++ ]; R4 = [ P3 ++ ]; R5 = [ P4 ++ ]; R6 = [ P5 ++ ]; R7 = [ FP ++ ]; R0 = [ SP ++ ]; CHECKREG r0, 0x0A231507; CHECKREG r1, 0x2C453729; CHECKREG r2, 0x3D56483A; CHECKREG r3, 0x4E67594B; CHECKREG r4, 0x5F786A5C; CHECKREG r5, 0x60897B6D; CHECKREG r6, 0x2C453729; CHECKREG r7, 0x719A8C7E; R3 = [ P1 ++ ]; R4 = [ P2 ++ ]; R5 = [ P3 ++ ]; R6 = [ P4 ++ ]; R7 = [ P5 ++ ]; R0 = [ FP ++ ]; R1 = [ SP ++ ]; CHECKREG r0, 0x0A231507; CHECKREG r1, 0x1B342618; CHECKREG r2, 0x3D56483A; CHECKREG r3, 0x4E67594B; CHECKREG r4, 0x5F786A5C; CHECKREG r5, 0x60897B6D; CHECKREG r6, 0x719A8C7E; CHECKREG r7, 0x3D56483A; R4 = [ P1 ++ ]; R5 = [ P2 ++ ]; R6 = [ P3 ++ ]; R7 = [ P4 ++ ]; R0 = [ P5 ++ ]; R1 = [ FP ++ ]; R2 = [ SP ++ ]; CHECKREG r0, 0x4E67594B; CHECKREG r1, 0x1B342618; CHECKREG r2, 0x2C453729; CHECKREG r3, 0x4E67594B; CHECKREG r4, 0x5F786A5C; CHECKREG r5, 0x60897B6D; CHECKREG r6, 0x719A8C7E; CHECKREG r7, 0x0A231507; R5 = [ P1 ++ ]; R6 = [ P2 ++ ]; R7 = [ P3 ++ ]; R0 = [ P4 ++ ]; R1 = [ P5 ++ ]; R2 = [ FP ++ ]; R3 = [ SP ++ ]; CHECKREG r0, 0x1B342618; CHECKREG r1, 0x5F786A5C; CHECKREG r2, 0x2C453729; CHECKREG r3, 0x3D56483A; CHECKREG r4, 0x5F786A5C; CHECKREG r5, 0x60897B6D; CHECKREG r6, 0x719A8C7E; CHECKREG r7, 0x0A231507; R6 = [ P1 ++ ]; R7 = [ P2 ++ ]; R0 = [ P3 ++ ]; R1 = [ P4 ++ ]; R2 = [ P5 ++ ]; R3 = [ FP ++ ]; R4 = [ SP ++ ]; CHECKREG r0, 0x1B342618; CHECKREG r1, 0x2C453729; CHECKREG r2, 0x60897B6D; CHECKREG r3, 0x3D56483A; CHECKREG r4, 0x4E67594B; CHECKREG r5, 0x60897B6D; CHECKREG r6, 0x719A8C7E; CHECKREG r7, 0x0A231507; R7 = [ P1 ++ ]; R0 = [ P2 ++ ]; R1 = [ P3 ++ ]; R2 = [ P4 ++ ]; R3 = [ P5 ++ ]; R4 = [ FP ++ ]; R5 = [ SP ++ ]; CHECKREG r0, 0x1B342618; CHECKREG r1, 0x2C453729; CHECKREG r2, 0x3D56483A; CHECKREG r3, 0x719A8C7E; CHECKREG r4, 0x4E67594B; CHECKREG r5, 0x5F786A5C; CHECKREG r6, 0x719A8C7E; CHECKREG r7, 0x0A231507; // reset values imm32 r0, 0x1a235507; imm32 r1, 0x12342518; imm32 r2, 0x23353729; imm32 r3, 0x3f54483a; imm32 r4, 0x4467694b; imm32 r5, 0x5ff86a5c; imm32 r6, 0x608b7b1d; imm32 r7, 0x719a8c71; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_1, 0x20; loadsym p1, DATA_ADDR_2, 0x20; loadsym p2, DATA_ADDR_3, 0x20; loadsym i1, DATA_ADDR_4, 0x20; loadsym p4, DATA_ADDR_5, 0x20; loadsym fp, DATA_ADDR_6, 0x20; loadsym i3, DATA_ADDR_7, 0x20; P3 = I1; SP = I3; [ P5 -- ] = R0; [ P1 -- ] = R1; [ P2 -- ] = R2; [ P3 -- ] = R3; [ P4 -- ] = R4; [ FP -- ] = R5; [ SP -- ] = R6; [ P5 -- ] = R1; [ P1 -- ] = R2; [ P2 -- ] = R3; [ P3 -- ] = R4; [ P4 -- ] = R5; [ FP -- ] = R6; [ SP -- ] = R7; [ P5 -- ] = R2; [ P1 -- ] = R3; [ P2 -- ] = R4; [ P3 -- ] = R5; [ P4 -- ] = R6; [ FP -- ] = R7; [ SP -- ] = R0; [ P5 -- ] = R3; [ P1 -- ] = R4; [ P2 -- ] = R5; [ P3 -- ] = R6; [ P4 -- ] = R7; [ FP -- ] = R0; [ SP -- ] = R1; [ P5 -- ] = R4; [ P1 -- ] = R5; [ P2 -- ] = R6; [ P3 -- ] = R7; [ P4 -- ] = R0; [ FP -- ] = R1; [ SP -- ] = R2; [ P5 -- ] = R5; [ P1 -- ] = R6; [ P2 -- ] = R7; [ P3 -- ] = R0; [ P4 -- ] = R1; [ FP -- ] = R2; [ SP -- ] = R3; [ P5 -- ] = R6; [ P1 -- ] = R7; [ P2 -- ] = R0; [ P3 -- ] = R1; [ P4 -- ] = R2; [ FP -- ] = R3; [ SP -- ] = R4; [ P5 -- ] = R7; [ P1 -- ] = R0; [ P2 -- ] = R1; [ P3 -- ] = R2; [ P4 -- ] = R3; [ FP -- ] = R4; [ SP -- ] = R5; I1 = P3; P3 = I0; I3 = SP; SP = I2; loadsym p5, DATA_ADDR_1, 0x20; loadsym p1, DATA_ADDR_2, 0x20; loadsym p2, DATA_ADDR_3, 0x20; loadsym i1, DATA_ADDR_4, 0x20; loadsym p4, DATA_ADDR_5, 0x20; loadsym fp, DATA_ADDR_6, 0x20; loadsym i3, DATA_ADDR_7, 0x20; P3 = I1; SP = I3; R0 = [ P1 -- ]; R1 = [ P2 -- ]; R2 = [ P3 -- ]; R3 = [ P4 -- ]; R4 = [ P5 -- ]; R5 = [ FP -- ]; R6 = [ SP -- ]; CHECKREG r0, 0x12342518; CHECKREG r1, 0x23353729; CHECKREG r2, 0x3F54483A; CHECKREG r3, 0x4467694B; CHECKREG r4, 0x1A235507; CHECKREG r5, 0x5FF86A5C; CHECKREG r6, 0x608B7B1D; CHECKREG r7, 0x719A8C71; R1 = [ P1 -- ]; R2 = [ P2 -- ]; R3 = [ P3 -- ]; R4 = [ P4 -- ]; R5 = [ P5 -- ]; R6 = [ FP -- ]; R7 = [ SP -- ]; CHECKREG r0, 0x12342518; CHECKREG r1, 0x23353729; CHECKREG r2, 0x3F54483A; CHECKREG r3, 0x4467694B; CHECKREG r4, 0x5FF86A5C; CHECKREG r5, 0x12342518; CHECKREG r6, 0x608B7B1D; CHECKREG r7, 0x719A8C71; R2 = [ P1 -- ]; R3 = [ P2 -- ]; R4 = [ P3 -- ]; R5 = [ P4 -- ]; R6 = [ P5 -- ]; R7 = [ FP -- ]; R0 = [ SP -- ]; CHECKREG r0, 0x1A235507; CHECKREG r1, 0x23353729; CHECKREG r2, 0x3F54483A; CHECKREG r3, 0x4467694B; CHECKREG r4, 0x5FF86A5C; CHECKREG r5, 0x608B7B1D; CHECKREG r6, 0x23353729; CHECKREG r7, 0x719A8C71; R3 = [ P1 -- ]; R4 = [ P2 -- ]; R5 = [ P3 -- ]; R6 = [ P4 -- ]; R7 = [ P5 -- ]; R0 = [ FP -- ]; R1 = [ SP -- ]; CHECKREG r0, 0x1A235507; CHECKREG r1, 0x12342518; CHECKREG r2, 0x3F54483A; CHECKREG r3, 0x4467694B; CHECKREG r4, 0x5FF86A5C; CHECKREG r5, 0x608B7B1D; CHECKREG r6, 0x719A8C71; CHECKREG r7, 0x3F54483A; R4 = [ P1 -- ]; R5 = [ P2 -- ]; R6 = [ P3 -- ]; R7 = [ P4 -- ]; R0 = [ P5 -- ]; R1 = [ FP -- ]; R2 = [ SP -- ]; CHECKREG r0, 0x4467694B; CHECKREG r1, 0x12342518; CHECKREG r2, 0x23353729; CHECKREG r3, 0x4467694B; CHECKREG r4, 0x5FF86A5C; CHECKREG r5, 0x608B7B1D; CHECKREG r6, 0x719A8C71; CHECKREG r7, 0x1A235507; R5 = [ P1 -- ]; R6 = [ P2 -- ]; R7 = [ P3 -- ]; R0 = [ P4 -- ]; R1 = [ P5 -- ]; R2 = [ FP -- ]; R3 = [ SP -- ]; CHECKREG r0, 0x12342518; CHECKREG r1, 0x5FF86A5C; CHECKREG r2, 0x23353729; CHECKREG r3, 0x3F54483A; CHECKREG r4, 0x5FF86A5C; CHECKREG r5, 0x608B7B1D; CHECKREG r6, 0x719A8C71; CHECKREG r7, 0x1A235507; R6 = [ P1 -- ]; R7 = [ P2 -- ]; R0 = [ P3 -- ]; R1 = [ P4 -- ]; R2 = [ P5 -- ]; R3 = [ FP -- ]; R4 = [ SP -- ]; CHECKREG r0, 0x12342518; CHECKREG r1, 0x23353729; CHECKREG r2, 0x608B7B1D; CHECKREG r3, 0x3F54483A; CHECKREG r4, 0x4467694B; CHECKREG r5, 0x608B7B1D; CHECKREG r6, 0x719A8C71; CHECKREG r7, 0x1A235507; R7 = [ P1 -- ]; R0 = [ P2 -- ]; R1 = [ P3 -- ]; R2 = [ P4 -- ]; R3 = [ P5 -- ]; R4 = [ FP -- ]; R5 = [ SP -- ]; CHECKREG r0, 0x12342518; CHECKREG r1, 0x23353729; CHECKREG r2, 0x3F54483A; CHECKREG r3, 0x719A8C71; CHECKREG r4, 0x4467694B; CHECKREG r5, 0x5FF86A5C; CHECKREG r6, 0x719A8C71; CHECKREG r7, 0x1A235507; P3 = I1; SP = I3; pass // Pre-load memory with known data // More data is defined than will actually be used .data DATA_ADDR_1: .dd 0x00010203 .dd 0x04050607 .dd 0x08090A0B .dd 0x0C0D0E0F .dd 0x10111213 .dd 0x14151617 .dd 0x18191A1B .dd 0x1C1D1E1F .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 DATA_ADDR_2: .dd 0x20212223 .dd 0x24252627 .dd 0x28292A2B .dd 0x2C2D2E2F .dd 0x30313233 .dd 0x34353637 .dd 0x38393A3B .dd 0x3C3D3E3F .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 DATA_ADDR_3: .dd 0x40414243 .dd 0x44454647 .dd 0x48494A4B .dd 0x4C4D4E4F .dd 0x50515253 .dd 0x54555657 .dd 0x58595A5B .dd 0x5C5D5E5F .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 DATA_ADDR_4: .dd 0x60616263 .dd 0x64656667 .dd 0x68696A6B .dd 0x6C6D6E6F .dd 0x70717273 .dd 0x74757677 .dd 0x78797A7B .dd 0x7C7D7E7F .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 DATA_ADDR_5: .dd 0x80818283 .dd 0x84858687 .dd 0x88898A8B .dd 0x8C8D8E8F .dd 0x90919293 .dd 0x94959697 .dd 0x98999A9B .dd 0x9C9D9E9F .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 DATA_ADDR_6: .dd 0xA0A1A2A3 .dd 0xA4A5A6A7 .dd 0xA8A9AAAB .dd 0xACADAEAF .dd 0xB0B1B2B3 .dd 0xB4B5B6B7 .dd 0xB8B9BABB .dd 0xBCBDBEBF .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 DATA_ADDR_7: .dd 0xC0C1C2C3 .dd 0xC4C5C6C7 .dd 0xC8C9CACB .dd 0xCCCDCECF .dd 0xD0D1D2D3 .dd 0xD4D5D6D7 .dd 0xD8D9DADB .dd 0xDCDDDEDF .dd 0xE0E1E2E3 .dd 0xE4E5E6E7 .dd 0xE8E9EAEB .dd 0xECEDEEEF .dd 0xF0F1F2F3 .dd 0xF4F5F6F7 .dd 0xF8F9FAFB .dd 0xFCFDFEFF .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000 .dd 0x00000000

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