repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
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tactcomplabs/xbgas-binutils-gdb | 1,303 | sim/testsuite/bfin/c_dsp32shiftim_rot.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp
// Spec Reference: dsp32shiftimm rot:
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R0 = ROT R0 BY 1;
R1 = ROT R1 BY 5;
R2 = ROT R2 BY 9;
R3 = ROT R3 BY 8;
R4 = ROT R4 BY 24;
R5 = ROT R5 BY 31;
R6 = ROT R6 BY 14;
R7 = ROT R7 BY 25;
CHECKREG r0, 0x42460002;
CHECKREG r1, 0x668ACF11;
CHECKREG r2, 0x8ACF1323;
CHECKREG r3, 0xD6789A9A;
CHECKREG r4, 0xAB42D3C4;
CHECKREG r5, 0x659F26AF;
CHECKREG r6, 0x6AF354F1;
CHECKREG r7, 0xBCB8912C;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R6 = ROT R0 BY -3;
R7 = ROT R1 BY -9;
R0 = ROT R2 BY -8;
R1 = ROT R3 BY -7;
R2 = ROT R4 BY -15;
R3 = ROT R5 BY -24;
R4 = ROT R6 BY -31;
R5 = ROT R7 BY -22;
CHECKREG r0, 0x1223C567;
CHECKREG r1, 0x6A69ACF1;
CHECKREG r2, 0x26AD0B4F;
CHECKREG r3, 0xF9357896;
CHECKREG r4, 0xD0918000;
CHECKREG r5, 0x6CD15DE0;
CHECKREG r6, 0x74246000;
CHECKREG r7, 0x780D9A2B;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,342 | sim/testsuite/bfin/c_interr_disable_enable.S | //Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp
// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0x00BFFFFC);
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
// LD32(sp, 0x000FF200);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
//.code 0x200
START :
P1 = 0;
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
CLI R1; // stop interrupt
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
// RD_MMR(TCOUNT, p0, r3);
// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
RD_MMR(TPERIOD, p0, r4);
CHECKREG(r4, 0x00000050);
// RD_MMR(TCNTL, p0, r5);
// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000015, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1)
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000015);
// RD_MMR(TCNTL , p0, r3);
// CHECKREG(r3, 0x0000000F);
CHECKREG(r7, 0x00000000); // no interrupt being serviced
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
STI R1;
NOP;
CHECKREG(r7, 0x00000001); // interrupt being serviced
WR_MMR(TCOUNT, 0x00000005, p0, r0);
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
CHECKREG(r7, 0x00000002); // interrupt being serviced
RAISE 7;
NOP; NOP;
CHECKREG(p1, 0x00000001); // interrupt being serviced
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
//.code ITABLE
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
P1 += 1;
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.data
.space (STACKSIZE);
KSTACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
tactcomplabs/xbgas-binutils-gdb | 2,922 | sim/testsuite/bfin/c_dsp32mac_dr_a0_m.s | //Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp
// Spec Reference: dsp32mac dr_a0 m
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H );
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0x1354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA124FF27;
CHECKREG r3, 0xFF274DDE;
CHECKREG r4, 0xEFBCFCD7;
CHECKREG r5, 0xFCD701B6;
CHECKREG r6, 0x000C000B;
CHECKREG r7, 0x000A846C;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.L = ( A0 += R6.L * R7.L );
R1 = A0.w;
R2.L = ( A0 -= R2.L * R3.H );
R3 = A0.w;
R4.L = ( A0 += R4.H * R5.L );
R5 = A0.w;
R6.L = ( A0 = R0.H * R1.H );
R7 = A0.w;
CHECKREG r0, 0x1354000B;
CHECKREG r1, 0x000A85F2;
CHECKREG r2, 0xA1240006;
CHECKREG r3, 0x00067846;
CHECKREG r4, 0xEFBC0005;
CHECKREG r5, 0x0005126E;
CHECKREG r6, 0x000C0002;
CHECKREG r7, 0x00018290;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
R0.L = ( A0 = R1.L * R0.L );
R1 = A0.w;
R2.L = ( A0 += R2.H * R3.L );
R3 = A0.w;
R4.L = ( A0 += R4.H * R5.H );
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H );
R7 = A0.w;
CHECKREG r0, 0x1354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xA124FF1D;
CHECKREG r3, 0xFF1CEDCE;
CHECKREG r4, 0xEFBCFCCD;
CHECKREG r5, 0xFCCCA1A6;
CHECKREG r6, 0x000CFCD7;
CHECKREG r7, 0xFCD72612;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L );
R7 = A0.w;
A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L );
R3 = A0.w;
A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H );
R5 = A0.w;
A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H );
R1 = A0.w;
CHECKREG r0, 0x1354000B;
CHECKREG r1, 0x000A83F2;
CHECKREG r2, 0xA124FDB0;
CHECKREG r3, 0xFDAFD834;
CHECKREG r4, 0xEFBCFDB0;
CHECKREG r5, 0xFDAFB3D8;
CHECKREG r6, 0x000CFDB5;
CHECKREG r7, 0xFDB5083C;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,881 | sim/testsuite/bfin/c_alu2op_conv_neg.s | //Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp
// Spec Reference: alu2op (-) negative
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = - R0;
R1 = - R0;
R2 = - R0;
R3 = - R0;
R4 = - R0;
R5 = - R0;
R6 = - R0;
R7 = - R0;
CHECKREG r0, 0xFF876544;
CHECKREG r1, 0x00789ABC;
CHECKREG r2, 0x00789ABC;
CHECKREG r3, 0x00789ABC;
CHECKREG r4, 0x00789ABC;
CHECKREG r5, 0x00789ABC;
CHECKREG r6, 0x00789ABC;
CHECKREG r7, 0x00789ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = - R1;
R1 = - R1;
R2 = - R1;
R3 = - R1;
R4 = - R1;
R5 = - R1;
R6 = - R1;
R7 = - R1;
CHECKREG r0, 0xFFC8B9A7;
CHECKREG r1, 0xFFC8B9A7;
CHECKREG r2, 0x00374659;
CHECKREG r3, 0x00374659;
CHECKREG r4, 0x00374659;
CHECKREG r5, 0x00374659;
CHECKREG r6, 0x00374659;
CHECKREG r7, 0x00374659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = - R2;
R1 = - R2;
R2 = - R2;
R3 = - R2;
R4 = - R2;
R5 = - R2;
R6 = - R2;
R7 = - R2;
CHECKREG r0, 0x6CEA9877;
CHECKREG r1, 0x6CEA9877;
CHECKREG r2, 0x6CEA9877;
CHECKREG r3, 0x93156789;
CHECKREG r4, 0x93156789;
CHECKREG r5, 0x93156789;
CHECKREG r6, 0x93156789;
CHECKREG r7, 0x93156789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = - R3;
R1 = - R3;
R2 = - R3;
R3 = - R3;
R4 = - R3;
R5 = - R3;
R6 = - R3;
R7 = - R3;
CHECKREG r0, 0x56AD8766;
CHECKREG r1, 0x56AD8766;
CHECKREG r2, 0x56AD8766;
CHECKREG r3, 0x56AD8766;
CHECKREG r4, 0xA952789A;
CHECKREG r5, 0xA952789A;
CHECKREG r6, 0xA952789A;
CHECKREG r7, 0xA952789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = - R4;
R1 = - R4;
R2 = - R4;
R3 = - R4;
R4 = - R4;
R5 = - R4;
R6 = - R4;
R7 = - R4;
CHECKREG r0, 0x79985655;
CHECKREG r1, 0x79985655;
CHECKREG r2, 0x79985655;
CHECKREG r3, 0x79985655;
CHECKREG r4, 0x79985655;
CHECKREG r5, 0x8667A9AB;
CHECKREG r6, 0x8667A9AB;
CHECKREG r7, 0x8667A9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = - R5;
R1 = - R5;
R2 = - R5;
R3 = - R5;
R4 = - R5;
R5 = - R5;
R6 = - R5;
R7 = - R5;
CHECKREG r0, 0x39876044;
CHECKREG r1, 0x39876044;
CHECKREG r2, 0x39876044;
CHECKREG r3, 0x39876044;
CHECKREG r4, 0x39876044;
CHECKREG r5, 0x39876044;
CHECKREG r6, 0xC6789FBC;
CHECKREG r7, 0xC6789FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = - R6;
R1 = - R6;
R2 = - R6;
R3 = - R6;
R4 = - R6;
R5 = - R6;
R6 = - R6;
R7 = - R6;
CHECKREG r0, 0x58765133;
CHECKREG r1, 0x58765133;
CHECKREG r2, 0x58765133;
CHECKREG r3, 0x58765133;
CHECKREG r4, 0x58765133;
CHECKREG r5, 0x58765133;
CHECKREG r6, 0x58765133;
CHECKREG r7, 0xA789AECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = - R7;
R1 = - R7;
R2 = - R7;
R3 = - R7;
R4 = - R7;
R5 = - R7;
R7 = - R7;
R6 = - R7;
CHECKREG r0, 0xA7654378;
CHECKREG r1, 0xA7654378;
CHECKREG r2, 0xA7654378;
CHECKREG r3, 0xA7654378;
CHECKREG r4, 0xA7654378;
CHECKREG r5, 0xA7654378;
CHECKREG r6, 0x589ABC88;
CHECKREG r7, 0xA7654378;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,180 | sim/testsuite/bfin/ashift_flags.s | # mach: bfin
.include "testutils.inc"
start
// load r1=0x7fffffff
// load r2=0x80000000
// load r3=0x000000ff
// load r4=0x00000000
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
_dbg r0;
_dbg r1;
_dbg r2;
_dbg r3;
_dbg r4;
R7 = 0;
ASTAT = R7;
r5 = r1 << 0x4 (s);
_DBG ASTAT;
r7=astat;
dbga (r5.h, 0x7fff);
dbga (r5.l, 0xffff);
dbga (r7.h, 0x0300); // V=1, VS=1
dbga (r7.l, 0x8);
R7 = 0;
ASTAT = R7;
r5.h = r1.h << 0x4 (s);
_DBG ASTAT;
r7=astat;
dbga (r5.h, 0x7fff);
dbga (r7.h, 0x0300); // V=1, VS=1
dbga (r7.l, 0x8);
A0 = 0;
A0.w = r1;
A0.x = r0.l;
r6 = 0x3;
_dbg r6;
_dbg A0;
R7 = 0;
ASTAT = R7;
A0 = ASHIFT A0 BY R6.L;
_DBG ASTAT;
_DBG A0;
r7 = astat;
dbga (r7.h, 0x0); // AV0=0, AV0S=0
dbga (r7.l, 0x2); // AN = 1
A1 = 0;
A1 = r1;
A1.x = r0.l;
r6 = 0x3;
_dbg A1;
R7 = 0;
ASTAT = R7;
A1 = ASHIFT A1 BY R6.L;
_DBG ASTAT;
_DBG A1;
r7 = astat;
dbga (r7.h, 0x0); // AV1=0, AV1S=0
dbga (r7.l, 0x2); // AN = 1
pass
.data 0x1000;
data0:
.dw 0x1111
.dw 0x1111
.dw 0xffff
.dw 0x7fff
.dw 0x0000
.dw 0x8000
.dw 0x00ff
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 4,138 | sim/testsuite/bfin/c_alu2op_arith_r_sft.s | //Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp
// Spec Reference: alu2op arith right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R1.L = 1;
R1 >>>= R0;
R2 >>>= R0;
R3 >>>= R0;
R4 >>>= R0;
R5 >>>= R0;
R6 >>>= R0;
R7 >>>= R0;
R4 >>>= R0;
R0 >>>= R0;
CHECKREG r1, 0x12340001;
CHECKREG r2, 0x23456789;
CHECKREG r3, 0x3456789A;
CHECKREG r4, 0x856789AB;
CHECKREG r5, 0x96789ABC;
CHECKREG r6, 0xA789ABCD;
CHECKREG r7, 0xB89ABCDE;
CHECKREG r0, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 >>>= R1;
R2 >>>= R1;
R3 >>>= R1;
R4 >>>= R1;
R5 >>>= R1;
R6 >>>= R1;
R7 >>>= R1;
R1 >>>= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 >>>= R2;
R1 >>>= R2;
R3 >>>= R2;
R4 >>>= R2;
R5 >>>= R2;
R6 >>>= R2;
R7 >>>= R2;
R2 >>>= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 >>>= R3;
R1 >>>= R3;
R2 >>>= R3;
R4 >>>= R3;
R5 >>>= R3;
R6 >>>= R3;
R7 >>>= R3;
R3 >>>= R3;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 >>>= R4;
R2 >>>= R4;
R3 >>>= R4;
R0 >>>= R4;
R5 >>>= R4;
R6 >>>= R4;
R7 >>>= R4;
R4 >>>= R4;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00002468;
CHECKREG r2, 0x0000468A;
CHECKREG r3, 0x000068AC;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xFFFF2CF1;
CHECKREG r6, 0xFFFF4F13;
CHECKREG r7, 0xFFFF7135;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 >>>= R5;
R1 >>>= R5;
R2 >>>= R5;
R3 >>>= R5;
R4 >>>= R5;
R6 >>>= R5;
R7 >>>= R5;
R5 >>>= R5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 >>>= R6;
R1 >>>= R6;
R2 >>>= R6;
R3 >>>= R6;
R4 >>>= R6;
R5 >>>= R6;
R7 >>>= R6;
R6 >>>= R6;
CHECKREG r0, 0x00000051;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0xFFFFFFB1;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0xFFFFFF95;
CHECKREG r5, 0xFFFFFF86;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 >>>= R7;
R1 >>>= R7;
R2 >>>= R7;
R3 >>>= R7;
R4 >>>= R7;
R5 >>>= R7;
R6 >>>= R7;
R7 >>>= R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0x00000000;
// special case
R2.L = -1;
R2.H = 32767;
R0 = 0;
R2 >>>= R0;
CHECKREG r2, 0x7FFFFFFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,121 | sim/testsuite/bfin/c_seq_ex1_raise_j_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_j_mv_pop/c_seq_ex1_raise_j_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
RAISE 2; // RTN
JUMP.S LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
JUMP.S LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
RAISE 8; // RTI
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 1,181 | sim/testsuite/bfin/algnbug2.s | # mach: bfin
.include "testutils.inc"
start
M0 = 1 (X);
loadsym I0, blocka;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
pass
.data;
.align 8
blocka:
.dw 0xfeff
.dw 0xfcfd
.dw 0xfafb
.dw 0xf8f9
|
tactcomplabs/xbgas-binutils-gdb | 6,170 | sim/testsuite/bfin/dbg_tr_umode.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_umode/dbg_tr_umode.dsp
// Description: Verify the basic functionality of TBUFPWR and TBUFEN in
// Supervisor mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x20
#endif
// This test embeds .text offsets, so pad our test so it lines up.
.space 0x64
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
CHECK_INIT(p5, 0x00BFFFFC);
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
LD32_LABEL(r7, DUMMY);
RETI = r7;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
// .code 0x200
START:
WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer
WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 1
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
RTI;
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
NOP;
NOP;
NOP;
JUMP.S label1;
R4.L = 0x1111;
R4.H = 0x1111;
NOP;
NOP;
NOP;
label2: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label3;
R6.L = 0x1111;
R6.H = 0x1111;
NOP;
NOP;
NOP;
NOP;
NOP;
label1: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label2;
R5.L = 0x1111;
R5.H = 0x1111;
NOP;
NOP;
NOP;
NOP;
label3:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// Checks the contents of the Trace Buffer
EXCPT 0;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000006);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x000002aa);
CHECKREG(r3, 0x0000029a);
CHECKREG(r4, 0x00000262);
CHECKREG(r5, 0x00000004);
CHECKREG(r6, 0x0000025a);
CHECKREG(r7, 0x00000288);
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
EXCPT 1;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000005);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x00000304);
CHECKREG(r3, 0x000002ac);
CHECKREG(r4, 0x00000470);
CHECKREG(r5, 0x00000003);
CHECKREG(r6, 0x00000276);
CHECKREG(r7, 0x0000024a);
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
EXCPT 2;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000004);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x0000035e);
CHECKREG(r3, 0x00000306);
CHECKREG(r4, 0x00000470);
CHECKREG(r5, 0x00000002);
CHECKREG(r6, 0x00000244);
CHECKREG(r7, 0x00000242);
NOP; NOP; NOP; NOP;
EXCPT 3;
NOP; NOP; NOP; NOP;
CHECKREG(r2, 0x00000003);
CHECKREG(r1, 0x00000416);
CHECKREG(r0, 0x000003b0);
CHECKREG(r3, 0x00000360);
CHECKREG(r4, 0x00000470);
CHECKREG(r5, 0x00000001);
CHECKREG(r6, 0x00000238);
CHECKREG(r7, 0x00000236);
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
R7 = SEQSTAT;
RD_MMR(TBUFSTAT, p0, r2);
RD_MMR(TBUF, p0, r1);
RD_MMR(TBUF, p0, r0);
RD_MMR(TBUF, p0, r3);
RD_MMR(TBUF, p0, r4);
RD_MMR(TBUFSTAT, p0, r5);
RD_MMR(TBUF, p0, r6);
RD_MMR(TBUF, p0, r7);
NOP; NOP; NOP; NOP;
RTX;
NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 7,005 | sim/testsuite/bfin/c_comp3op_pr_plus_pr_sh2.s | //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh2/c_comp3op_pr_plus_pr_sh2.dsp
// Spec Reference: comp3op pregs + pregs << 2
# mach: bfin
.include "testutils.inc"
start
imm32 p1, 0x89ab1def;
imm32 p2, 0x56781abc;
imm32 p3, 0xdef01234;
imm32 p4, 0x23451899;
imm32 p5, 0x78911345;
imm32 sp, 0x98761432;
imm32 fp, 0x12341678;
P1 = P1 + ( P1 << 2 );
P2 = P1 + ( P2 << 2 );
P3 = P1 + ( P3 << 2 );
P4 = P1 + ( P4 << 2 );
P5 = P1 + ( P5 << 2 );
SP = P1 + ( SP << 2 );
FP = P1 + FP;
CHECKREG p1, 0xB05795AB;
CHECKREG p2, 0x0A38009B;
CHECKREG p3, 0x2C17DE7B;
CHECKREG p4, 0x3D6BF80F;
CHECKREG p5, 0x929BE2BF;
CHECKREG sp, 0x122FE673;
CHECKREG fp, 0xC28BAC23;
imm32 p1, 0x89abcd2f;
imm32 p2, 0x56789a2c;
imm32 p3, 0xdef01224;
imm32 p4, 0x23456829;
imm32 p5, 0x78912325;
imm32 sp, 0x98765422;
imm32 fp, 0x12345628;
P1 = P2 + ( P1 << 2 );
P2 = P2 + ( P2 << 2 );
P3 = P2 + ( P3 << 2 );
P4 = P2 + ( P4 << 2 );
P5 = P2 + ( P5 << 2 );
SP = P2 + ( SP << 2 );
FP = P2 + ( FP << 2 );
CHECKREG p1, 0x7D27CEE8;
CHECKREG p2, 0xB05B02DC;
CHECKREG p3, 0x2C1B4B6C;
CHECKREG p4, 0x3D70A380;
CHECKREG p5, 0x929F8F70;
CHECKREG sp, 0x12345364;
CHECKREG fp, 0xF92C5B7C;
imm32 p1, 0x89abcde3;
imm32 p2, 0x56789ab3;
imm32 p3, 0xdef01233;
imm32 p4, 0x23456893;
imm32 p5, 0x78912343;
imm32 sp, 0x98765433;
imm32 fp, 0x12345673;
P1 = P3 + ( P1 << 2 );
P2 = P3 + ( P2 << 2 );
P3 = P3 + ( P3 << 2 );
P4 = P3 + ( P4 << 2 );
P5 = P3 + ( P5 << 2 );
SP = P3 + ( SP << 2 );
FP = P3 + ( FP << 2 );
CHECKREG p1, 0x059F49BF;
CHECKREG p2, 0x38D27CFF;
CHECKREG p3, 0x5AB05AFF;
CHECKREG p4, 0xE7C5FD4B;
CHECKREG p5, 0x3CF4E80B;
CHECKREG sp, 0xBC89ABCB;
CHECKREG fp, 0xA381B4CB;
imm32 p1, 0x49abcdef;
imm32 p2, 0x46789abc;
imm32 p3, 0x4ef01234;
imm32 p4, 0x43456899;
imm32 p5, 0x48912345;
imm32 sp, 0x48765432;
imm32 fp, 0x42345678;
P1 = P4 + ( P1 << 2 );
P2 = P4 + ( P2 << 2 );
P3 = P4 + ( P3 << 2 );
P4 = P4 + ( P4 << 2 );
P5 = P4 + ( P5 << 2 );
SP = P4 + ( SP << 2 );
FP = P4 + ( FP << 2 );
CHECKREG p1, 0x69F4A055;
CHECKREG p2, 0x5D27D389;
CHECKREG p3, 0x7F05B169;
CHECKREG p4, 0x505B0AFD;
CHECKREG p5, 0x729F9811;
CHECKREG sp, 0x72345BC5;
CHECKREG fp, 0x592C64DD;
imm32 p1, 0x85abcdef;
imm32 p2, 0x55789abc;
imm32 p3, 0xd5f01234;
imm32 p4, 0x25456899;
imm32 p5, 0x75912345;
imm32 sp, 0x95765432;
imm32 fp, 0x15345678;
P1 = P5 + ( P1 << 2 );
P2 = P5 + ( P2 << 2 );
P3 = P5 + ( P3 << 2 );
P4 = P5 + ( P4 << 2 );
P5 = P5 + ( P5 << 2 );
SP = P5 + ( SP << 2 );
FP = P5 + ( FP << 2 );
CHECKREG p1, 0x8C405B01;
CHECKREG p2, 0xCB738E35;
CHECKREG p3, 0xCD516C15;
CHECKREG p4, 0x0AA6C5A9;
CHECKREG p5, 0x4BD5B059;
CHECKREG sp, 0xA1AF0121;
CHECKREG fp, 0xA0A70A39;
imm32 p1, 0x89a6cdef;
imm32 p2, 0x56769abc;
imm32 p3, 0xdef61234;
imm32 p4, 0x23466899;
imm32 p5, 0x78962345;
imm32 sp, 0x98765432;
imm32 fp, 0x12365678;
P1 = SP + ( P1 << 2 );
P2 = SP + ( P2 << 2 );
P3 = SP + ( P3 << 2 );
P4 = SP + ( P4 << 2 );
P5 = SP + ( P5 << 2 );
SP = SP + ( SP << 2 );
FP = SP + ( FP << 2 );
CHECKREG p1, 0xBF118BEE;
CHECKREG p2, 0xF250BF22;
CHECKREG p3, 0x144E9D02;
CHECKREG p4, 0x258FF696;
CHECKREG p5, 0x7ACEE146;
CHECKREG sp, 0xFA4FA4FA;
CHECKREG fp, 0x4328FEDA;
imm32 p1, 0x89ab7def;
imm32 p2, 0x56787abc;
imm32 p3, 0xdef07234;
imm32 p4, 0x23457899;
imm32 p5, 0x78917345;
imm32 sp, 0x98767432;
imm32 fp, 0x12345678;
P1 = FP + ( P1 << 2 );
P2 = FP + ( P2 << 2 );
P3 = FP + ( P3 << 2 );
P4 = FP + ( P4 << 2 );
P5 = FP + ( P5 << 2 );
SP = FP + ( SP << 2 );
FP = FP + ( FP << 2 );
CHECKREG p1, 0x38E24E34;
CHECKREG p2, 0x6C164168;
CHECKREG p3, 0x8DF61F48;
CHECKREG p4, 0x9F4A38DC;
CHECKREG p5, 0xF47A238C;
CHECKREG sp, 0x740E2740;
CHECKREG fp, 0x5B05B058;
imm32 p1, 0x29ab1def;
imm32 p2, 0x52781abc;
imm32 p3, 0xde201234;
imm32 p4, 0x23421899;
imm32 p5, 0x78912345;
imm32 sp, 0x98761232;
imm32 fp, 0x12341628;
P1 = P3 + ( P1 << 2 );
P2 = P4 + ( P1 << 2 );
P3 = P5 + ( P1 << 2 );
P4 = SP + ( P1 << 2 );
P5 = FP + ( P1 << 2 );
FP = P1 + ( P1 << 2 );
CHECKREG p1, 0x84CC89F0;
CHECKREG p2, 0x36744059;
CHECKREG p3, 0x8BC34B05;
CHECKREG p4, 0xABA839F2;
CHECKREG p5, 0x25663DE8;
CHECKREG fp, 0x97FEB1B0;
imm32 p1, 0x893bcd2f;
imm32 p2, 0x56739a2c;
imm32 p3, 0x3ef03224;
imm32 p4, 0x23456329;
imm32 p5, 0x78312335;
imm32 sp, 0x98735423;
imm32 fp, 0x12343628;
P1 = P4 + ( P2 << 2 );
P2 = P5 + ( P2 << 2 );
P3 = SP + ( P2 << 2 );
P4 = FP + ( P2 << 2 );
SP = P1 + ( P2 << 2 );
FP = P2 + ( P2 << 2 );
CHECKREG p1, 0x7D13CBD9;
CHECKREG p2, 0xD1FF8BE5;
CHECKREG p3, 0xE07183B7;
CHECKREG p4, 0x5A3265BC;
CHECKREG sp, 0xC511FB6D;
CHECKREG fp, 0x19FDBB79;
imm32 p1, 0x894bcde3;
imm32 p2, 0x56749ab3;
imm32 p3, 0x4ef04233;
imm32 p4, 0x24456493;
imm32 p5, 0x78412344;
imm32 sp, 0x98745434;
imm32 fp, 0x12344673;
P1 = P5 + ( P3 << 2 );
P2 = SP + ( P3 << 2 );
P3 = FP + ( P3 << 2 );
P5 = P1 + ( P3 << 2 );
SP = P2 + ( P3 << 2 );
FP = P3 + ( P3 << 2 );
CHECKREG p1, 0xB4022C10;
CHECKREG p2, 0xD4355D00;
CHECKREG p3, 0x4DF54F3F;
CHECKREG p5, 0xEBD7690C;
CHECKREG sp, 0x0C0A99FC;
CHECKREG fp, 0x85CA8C3B;
imm32 p1, 0x49abc5ef;
imm32 p2, 0x46789a5c;
imm32 p3, 0x4ef01235;
imm32 p4, 0x53456899;
imm32 p5, 0x45912345;
imm32 sp, 0x48565432;
imm32 fp, 0x42355678;
P1 = SP + ( P4 << 2 );
P2 = FP + ( P4 << 2 );
P4 = P1 + ( P4 << 2 );
P5 = P2 + ( P4 << 2 );
SP = P3 + ( P4 << 2 );
FP = P4 + ( P4 << 2 );
CHECKREG p1, 0x956BF696;
CHECKREG p2, 0x8F4AF8DC;
CHECKREG p4, 0xE28198FA;
CHECKREG p5, 0x19515CC4;
CHECKREG sp, 0xD8F6761D;
CHECKREG fp, 0x6C87FCE2;
imm32 p1, 0x85ab6def;
imm32 p2, 0x657896bc;
imm32 p3, 0xd6f01264;
imm32 p4, 0x25656896;
imm32 p5, 0x75962345;
imm32 sp, 0x95766432;
imm32 fp, 0x15345678;
P1 = FP + ( P5 << 2 );
P3 = P1 + ( P5 << 2 );
P4 = P2 + ( P5 << 2 );
P5 = P3 + ( P5 << 2 );
SP = P4 + ( P5 << 2 );
FP = P5 + ( P5 << 2 );
CHECKREG p1, 0xEB8CE38C;
CHECKREG p3, 0xC1E570A0;
CHECKREG p4, 0x3BD123D0;
CHECKREG p5, 0x983DFDB4;
CHECKREG sp, 0x9CC91AA0;
CHECKREG fp, 0xF935F484;
imm32 p1, 0x89a7cdef;
imm32 p2, 0x56767abc;
imm32 p3, 0xdef61734;
imm32 p4, 0x73466879;
imm32 p5, 0x77962347;
imm32 sp, 0x98765432;
imm32 fp, 0x12375678;
P2 = P1 + ( SP << 2 );
P3 = P2 + ( SP << 2 );
P4 = P3 + ( SP << 2 );
P5 = P4 + ( SP << 2 );
SP = P5 + ( SP << 2 );
FP = SP + ( SP << 2 );
CHECKREG p2, 0xEB811EB7;
CHECKREG p3, 0x4D5A6F7F;
CHECKREG p4, 0xAF33C047;
CHECKREG p5, 0x110D110F;
CHECKREG sp, 0x72E661D7;
CHECKREG fp, 0x3E7FE933;
imm32 p1, 0x88ab78ef;
imm32 p2, 0x56887a8c;
imm32 p3, 0x8ef87238;
imm32 p4, 0x28458899;
imm32 p5, 0x78817845;
imm32 sp, 0x98787482;
imm32 fp, 0x12348678;
P1 = P2 + ( FP << 2 );
P2 = P3 + ( FP << 2 );
P3 = P4 + ( FP << 2 );
P4 = P5 + ( FP << 2 );
P5 = SP + ( FP << 2 );
SP = FP + ( FP << 2 );
CHECKREG p1, 0x9F5A946C;
CHECKREG p2, 0xD7CA8C18;
CHECKREG p3, 0x7117A279;
CHECKREG p4, 0xC1539225;
CHECKREG p5, 0xE14A8E62;
CHECKREG sp, 0x5B06A058;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,551 | sim/testsuite/bfin/random_0030.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x00a0cc80 | _VS | _AV1S | _AQ | _CC | _AN);
dmm32 A1.w, 0x8f7fea28;
dmm32 A1.x, 0x00000005;
imm32 R2, 0x000014f2;
imm32 R4, 0x7fff7fff;
imm32 R7, 0x14d3a258;
R7.H = (A1 -= R4.L * R2.H) (M, T);
checkreg R7, 0x7fffa258;
checkreg A1.w, 0x8f7fea28;
checkreg A1.x, 0x00000005;
checkreg ASTAT, (0x00a0cc80 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0xbfed6ffc;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x7fffffff;
imm32 R5, 0x00000000;
imm32 R6, 0xf70a7fff;
R0.H = (A1 -= R5.L * R6.L) (M, T);
checkreg ASTAT, (0x7c90c410 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
checkreg A1.w, 0xbfed6ffc;
checkreg A1.x, 0x00000000;
checkreg R0, 0x7fffffff;
checkreg R5, 0x00000000;
checkreg R6, 0xf70a7fff;
dmm32 ASTAT, (0x2c508a10 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A1.w, 0xfffd8001;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x00018000;
imm32 R4, 0x7fff8000;
imm32 R5, 0x7fff0002;
R3.H = (A1 += R5.L * R4.L) (M, T);
checkreg R3, 0x7fff8000;
checkreg A1.w, 0xfffe8001;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2c508a10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x28408c90 | _VS | _AV1S | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0x842fbc0a;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x04c44422;
imm32 R3, 0x40f67fff;
imm32 R7, 0x448c0856;
R7.H = (A1 -= R3.L * R0.H) (M, T);
checkreg R7, 0x7fff0856;
checkreg A1.w, 0x81cdc0ce;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x28408c90 | _VS | _V | _AV1S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x44708c10 | _AV1S | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xaa016cf5;
dmm32 A1.x, 0xffffffdb;
imm32 R2, 0x25908079;
imm32 R5, 0x46eabfcd;
imm32 R7, 0x67066230;
R2.H = (A1 += R5.L * R7.H) (M, T);
checkreg R2, 0x80008079;
checkreg A1.w, 0x902b66c3;
checkreg A1.x, 0xffffffdb;
checkreg ASTAT, (0x44708c10 | _VS | _V | _AV1S | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x8eef28b0;
dmm32 A1.x, 0x00000023;
imm32 R0, 0x000156b2;
imm32 R1, 0xfc1a8000;
imm32 R5, 0x7fff7fff;
R5.H = (A1 += R1.L * R0.H) (M, T);
checkreg A1.w, 0x8eeea8b0;
checkreg A1.x, 0x00000023;
checkreg ASTAT, (0x3c604090 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x74208e00 | _VS | _AV0S | _AC0 | _AQ | _AC0_COPY);
dmm32 A1.w, 0xed3c9973;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x80000000;
imm32 R1, 0x7fff8000;
imm32 R2, 0x00000000;
R1.H = (A1 -= R2.L * R0.H) (M, T);
checkreg ASTAT, (0x74208e00 | _VS | _V | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY);
checkreg A1.w, 0xed3c9973;
checkreg A1.x, 0x00000000;
checkreg R0, 0x80000000;
checkreg R1, 0x7fff8000;
checkreg R2, 0x00000000;
dmm32 ASTAT, (0x10308800 | _VS | _AV0S | _AC0 | _AC0_COPY);
dmm32 A1.w, 0x8b345e6e;
dmm32 A1.x, 0x00000000;
imm32 R3, 0xc40c1663;
imm32 R4, 0xd0347fff;
imm32 R7, 0x4249da20;
R3.H = (A1 += R4.L * R7.H) (M, T);
checkreg R3, 0x7fff1663;
checkreg A1.w, 0xac589c25;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x10308800 | _VS | _V | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ);
dmm32 A1.w, 0xa333ecbc;
dmm32 A1.x, 0xffffffea;
imm32 R2, 0x7fffffff;
imm32 R3, 0x72ea7fff;
imm32 R4, 0x07348ad1;
R4.H = (A1 += R2.L * R3.L) (M, T);
checkreg R4, 0x80008ad1;
checkreg A1.w, 0xa3336cbd;
checkreg A1.x, 0xffffffea;
checkreg ASTAT, (0x1c104880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AZ);
dmm32 ASTAT, (0x44904e00 | _VS);
dmm32 A1.w, 0x90202372;
dmm32 A1.x, 0xffffffc4;
imm32 R2, 0x138ac9fc;
imm32 R3, 0x720a427f;
imm32 R4, 0x800000f5;
R3.H = (A1 += R4.L * R2.H) (M, T);
checkreg R3, 0x8000427f;
checkreg A1.w, 0x9032d684;
checkreg A1.x, 0xffffffc4;
checkreg ASTAT, (0x44904e00 | _VS | _V | _V_COPY);
dmm32 ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 A1.w, 0xe9c97364;
dmm32 A1.x, 0xffffffef;
imm32 R2, 0x001dffe9;
imm32 R3, 0x50f06d20;
imm32 R6, 0x6179b75b;
R6.H = (A1 -= R3.L * R2.L) (M, T);
checkreg R6, 0x8000b75b;
checkreg A1.w, 0x7cb34144;
checkreg A1.x, 0xffffffef;
checkreg ASTAT, (0x48f04c90 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xf3d34812;
dmm32 A1.x, 0xffffff95;
imm32 R1, 0xf7419a18;
imm32 R6, 0x0fdf83b3;
imm32 R7, 0x0b831070;
R7.H = (A1 -= R6.L * R1.H) (M, T);
checkreg R7, 0x80001070;
checkreg A1.w, 0x6be1229f;
checkreg A1.x, 0xffffff96;
checkreg ASTAT, (0x68d00e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3060ce80 | _VS | _AV1S | _AC1 | _CC | _AN);
dmm32 A1.w, 0xe0c1fc60;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x00e97fff;
imm32 R7, 0x3fff0001;
R1.H = (A1 += R1.L * R7.H) (M, T);
checkreg R1, 0x7fff7fff;
checkreg A1.w, 0x00c13c61;
checkreg A1.x, 0x00000001;
checkreg ASTAT, (0x3060ce80 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x3c80c000 | _VS | _AV0S | _AC0_COPY | _AN);
dmm32 A1.w, 0xb0e43973;
dmm32 A1.x, 0xffffffbc;
imm32 R0, 0x511a6fe3;
imm32 R1, 0x43fe2c80;
imm32 R2, 0x424b5c19;
R0.H = (A1 -= R2.L * R1.H) (M, T);
checkreg R0, 0x80006fe3;
checkreg A1.w, 0x986e4da5;
checkreg A1.x, 0xffffffbc;
checkreg ASTAT, (0x3c80c000 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN);
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,996 | sim/testsuite/bfin/c_comp3op_dr_minus_dr.s | //Original:/testcases/core/c_comp3op_dr_minus_dr/c_comp3op_dr_minus_dr.dsp
// Spec Reference: comp3op dregs - dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 - R0;
R1 = R0 - R1;
R2 = R0 - R2;
R3 = R0 - R3;
R4 = R0 - R4;
R5 = R0 - R5;
R6 = R0 - R6;
R7 = R0 - R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x76543211;
CHECKREG r2, 0xA9876544;
CHECKREG r3, 0x210FEDCC;
CHECKREG r4, 0xDCBA9767;
CHECKREG r5, 0x876EDCBB;
CHECKREG r6, 0x6789ABCE;
CHECKREG r7, 0xEDCBA988;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 - R0;
R1 = R1 - R1;
R2 = R1 - R2;
R3 = R1 - R3;
R4 = R1 - R4;
R5 = R1 - R5;
R6 = R1 - R6;
R7 = R1 - R7;
CHECKREG r0, 0x88880888;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xA987E544;
CHECKREG r3, 0x210FEDCC;
CHECKREG r4, 0xDCBAE767;
CHECKREG r5, 0x876EECBB;
CHECKREG r6, 0x6789EBCE;
CHECKREG r7, 0xEDCBE988;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 - R0;
R1 = R2 - R1;
R2 = R2 - R2;
R3 = R2 - R3;
R4 = R2 - R4;
R5 = R2 - R5;
R6 = R2 - R6;
R7 = R2 - R7;
CHECKREG r0, 0x55555505;
CHECKREG r1, 0xCCCCCCFD;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x210FEDDC;
CHECKREG r4, 0xDCBA97D7;
CHECKREG r5, 0x876EDCDB;
CHECKREG r6, 0x6789ABDE;
CHECKREG r7, 0xEDCBA9D8;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 - R0;
R1 = R3 - R1;
R2 = R3 - R2;
R3 = R3 - R3;
R4 = R3 - R4;
R5 = R3 - R5;
R6 = R3 - R6;
R7 = R3 - R7;
CHECKREG r0, 0xDDCCCCD0;
CHECKREG r1, 0x55444450;
CHECKREG r2, 0x88777780;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xDCBA976D;
CHECKREG r5, 0x876EDCBD;
CHECKREG r6, 0x6789ABCD;
CHECKREG r7, 0xEDCBA98D;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 - R0;
R1 = R4 - R1;
R2 = R4 - R2;
R3 = R4 - R3;
R4 = R4 - R4;
R5 = R4 - R5;
R6 = R4 - R6;
R7 = R4 - R7;
CHECKREG r0, 0x02222332;
CHECKREG r1, 0xF9999AAA;
CHECKREG r2, 0xFCCCCDDD;
CHECKREG r3, 0xF4555665;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xB76EDCBB;
CHECKREG r6, 0xB789ABCE;
CHECKREG r7, 0xBDCBA988;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 - R0;
R1 = R5 - R1;
R2 = R5 - R2;
R3 = R5 - R3;
R4 = R5 - R4;
R5 = R5 - R5;
R6 = R5 - R6;
R7 = R5 - R7;
CHECKREG r0, 0x706DDDDE;
CHECKREG r1, 0xEFE55556;
CHECKREG r2, 0x20188889;
CHECKREG r3, 0x9FA11111;
CHECKREG r4, 0x504BBAAC;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x6A89ABCE;
CHECKREG r7, 0xEACBA988;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 - R0;
R1 = R6 - R1;
R2 = R6 - R2;
R3 = R6 - R3;
R4 = R6 - R4;
R5 = R6 - R5;
R6 = R6 - R6;
R7 = R6 - R7;
CHECKREG r0, 0x97500ECB;
CHECKREG r1, 0x0ECF8643;
CHECKREG r2, 0x41FFB976;
CHECKREG r3, 0xB98041FE;
CHECKREG r4, 0x752FEB99;
CHECKREG r5, 0x1FE030ED;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xEDC9A988;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 - R0;
R1 = R7 - R1;
R2 = R7 - R2;
R3 = R7 - R3;
R4 = R7 - R4;
R5 = R7 - R5;
R6 = R7 - R6;
R7 = R7 - R7;
CHECKREG r0, 0x1110E111;
CHECKREG r1, 0x8888D889;
CHECKREG r2, 0xBBBBDBBC;
CHECKREG r3, 0x3343E444;
CHECKREG r4, 0xEEEEDDDF;
CHECKREG r5, 0x99A2E333;
CHECKREG r6, 0x79BDE246;
CHECKREG r7, 0x00000000;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 - R0;
R1 = R2 - R0;
R2 = R3 - R0;
R3 = R4 - R0;
R4 = R5 - R0;
R5 = R6 - R0;
R6 = R7 - R0;
R7 = R0 - R0;
CHECKREG r0, 0x70888888;
CHECKREG r1, 0xE5901234;
CHECKREG r2, 0x6E6889AC;
CHECKREG r3, 0xB2BC9011;
CHECKREG r4, 0x080898BD;
CHECKREG r5, 0x27EDCB8A;
CHECKREG r6, 0xA1ABCDE9;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 - R1;
R1 = R3 - R1;
R2 = R4 - R1;
R3 = R5 - R1;
R4 = R6 - R1;
R5 = R7 - R1;
R6 = R0 - R1;
R7 = R1 - R1;
CHECKREG r0, 0x28CCFCCD;
CHECKREG r1, 0xB474F445;
CHECKREG r2, 0x6ECD2454;
CHECKREG r3, 0xC41C2F00;
CHECKREG r4, 0xE4011DED;
CHECKREG r5, 0x5DBF21E3;
CHECKREG r6, 0x74580888;
CHECKREG r7, 0x00000000;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R4 - R2;
R1 = R5 - R2;
R2 = R6 - R2;
R3 = R7 - R2;
R4 = R0 - R2;
R5 = R1 - R2;
R6 = R2 - R2;
R7 = R3 - R2;
CHECKREG r0, 0xCCD1C8FD;
CHECKREG r1, 0x21BD8909;
CHECKREG r2, 0x41FFB9F7;
CHECKREG r3, 0xD0347C31;
CHECKREG r4, 0x8AD20F06;
CHECKREG r5, 0xDFBDCF12;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x8E34C23A;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R5 - R3;
R1 = R6 - R3;
R2 = R7 - R3;
R3 = R0 - R3;
R4 = R1 - R3;
R5 = R2 - R3;
R6 = R3 - R3;
R7 = R4 - R3;
CHECKREG r0, 0x2950E111;
CHECKREG r1, 0x49841201;
CHECKREG r2, 0xC3440440;
CHECKREG r3, 0xDA609EDE;
CHECKREG r4, 0x6F237323;
CHECKREG r5, 0xE8E36562;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x94C2D445;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R6 - R4;
R1 = R7 - R4;
R2 = R0 - R4;
R3 = R1 - R4;
R4 = R2 - R4;
R5 = R3 - R4;
R6 = R4 - R4;
R7 = R5 - R4;
CHECKREG r0, 0xF510EB99;
CHECKREG r1, 0xEEEFEDDF;
CHECKREG r2, 0xA1CB8300;
CHECKREG r3, 0x9BAA8546;
CHECKREG r4, 0x4E861A67;
CHECKREG r5, 0x4D246ADF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFE9E5078;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R7 - R5;
R1 = R0 - R5;
R2 = R1 - R5;
R3 = R2 - R5;
R4 = R3 - R5;
R5 = R4 - R5;
R6 = R5 - R5;
R7 = R6 - R5;
CHECKREG r0, 0x9F9E3333;
CHECKREG r1, 0x2A080FEE;
CHECKREG r2, 0xB471ECA9;
CHECKREG r3, 0x3EDBC964;
CHECKREG r4, 0xC945A61F;
CHECKREG r5, 0x53AF82DA;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xAC507D26;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 - R6;
R1 = R0 - R6;
R2 = R1 - R6;
R3 = R2 - R6;
R4 = R3 - R6;
R5 = R4 - R6;
R6 = R5 - R6;
R7 = R6 - R6;
CHECKREG r0, 0x79C10246;
CHECKREG r1, 0xE14AAE14;
CHECKREG r2, 0x48D459E2;
CHECKREG r3, 0xB05E05B0;
CHECKREG r4, 0x17E7B17E;
CHECKREG r5, 0x7F715D4C;
CHECKREG r6, 0xE6FB091A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 - R7;
R1 = R2 - R7;
R2 = R3 - R7;
R3 = R4 - R7;
R4 = R5 - R7;
R5 = R6 - R7;
R6 = R7 - R7;
R7 = R0 - R7;
CHECKREG r0, 0x7676F277;
CHECKREG r1, 0x4453F414;
CHECKREG r2, 0x7CC3EBC0;
CHECKREG r3, 0x16110221;
CHECKREG r4, 0x664CF1CD;
CHECKREG r5, 0x8643EE0A;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x64426BFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,681 | sim/testsuite/bfin/c_dsp32mac_dr_a1_t.s | //Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp
// Spec Reference: dsp32mac dr a1 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0xFF225ABD;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0x2D8C8679;
CHECKREG r3, 0x2D8CEDAC;
CHECKREG r4, 0xF5D44569;
CHECKREG r5, 0xF5D41A28;
CHECKREG r6, 0x021B800D;
CHECKREG r7, 0x021BB550;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 = R1.L * R0.L ) (T);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (T);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (T);
R7 = A1.w;
CHECKREG r0, 0x011E8ABD;
CHECKREG r1, 0x011EBDD6;
CHECKREG r2, 0xCB175679;
CHECKREG r3, 0xCB172B82;
CHECKREG r4, 0x181D4569;
CHECKREG r5, 0x181DDA28;
CHECKREG r6, 0xE626A00D;
CHECKREG r7, 0xE6263550;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 = R1.L * R0.L (T);
R1 = A1.w;
R2.H = A1 , A0 = R2.H * R3.L (T);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (T);
R5 = A1.w;
R6.H = A1 , A0 += R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0xE626BABD;
CHECKREG r1, 0xE6263550;
CHECKREG r2, 0xE626E679;
CHECKREG r3, 0xE6263550;
CHECKREG r4, 0xE6264569;
CHECKREG r5, 0xE6263550;
CHECKREG r6, 0xE626300D;
CHECKREG r7, 0xE6263550;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T);
R3 = A0.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T);
R7 = A0.w;
CHECKREG r0, 0xFF915ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x30375679;
CHECKREG r3, 0x00062FF8;
CHECKREG r4, 0x030D4569;
CHECKREG r5, 0x030D72D5;
CHECKREG r6, 0xE621A00D;
CHECKREG r7, 0xCF173844;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x921c080b;
imm32 r6, 0x7901908d;
imm32 r7, 0x679e9008;
R0.H = ( A1 += R1.L * R0.L ) (M,T);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ) (M,T);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (M,T);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M,T);
R7 = A1.w;
CHECKREG r0, 0xE5B25ABD;
CHECKREG r1, 0xE5B26993;
CHECKREG r2, 0x09775679;
CHECKREG r3, 0x0977EFC8;
CHECKREG r4, 0x08858569;
CHECKREG r5, 0x0885038C;
CHECKREG r6, 0x30FA908D;
CHECKREG r7, 0x30FA159E;
imm32 r0, 0x03545abd;
imm32 r1, 0xb0bcfec7;
imm32 r2, 0xc1048679;
imm32 r3, 0xd0009007;
imm32 r4, 0xefbc0569;
imm32 r5, 0xcd35510b;
imm32 r6, 0xe00c802d;
imm32 r7, 0xf78e9003;
R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0x31D75ABD;
CHECKREG r1, 0x31D7F7C8;
CHECKREG r2, 0x2D928679;
CHECKREG r3, 0x2D92A000;
CHECKREG r4, 0x37DF0569;
CHECKREG r5, 0x37DF0DD8;
CHECKREG r6, 0x39FA802D;
CHECKREG r7, 0x39FAC328;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 -= R1.L * R0.L ) (T);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (T);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (T);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (T);
R7 = A1.w;
CHECKREG r0, 0x38DC8ABD;
CHECKREG r1, 0x38DC0552;
CHECKREG r2, 0x6EE35679;
CHECKREG r3, 0x6EE397A6;
CHECKREG r4, 0x56C54569;
CHECKREG r5, 0x56C5BD7E;
CHECKREG r6, 0x709FA00D;
CHECKREG r7, 0x709F882E;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 -= R1.L * R0.L (T);
R1 = A1.w;
R2.H = A1 , A0 -= R2.H * R3.L (T);
R3 = A1.w;
R4.H = A1 , A0 -= R4.H * R5.H (T);
R5 = A1.w;
R6.H = A1 , A0 -= R6.L * R7.H (T);
R7 = A1.w;
CHECKREG r0, 0x709FBABD;
CHECKREG r1, 0x709F882E;
CHECKREG r2, 0x709FE679;
CHECKREG r3, 0x709F882E;
CHECKREG r4, 0x709F4569;
CHECKREG r5, 0x709F882E;
CHECKREG r6, 0x709F300D;
CHECKREG r7, 0x709F882E;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T);
R3 = A0.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T);
R7 = A0.w;
CHECKREG r0, 0x710E5ABD;
CHECKREG r1, 0x710E7943;
CHECKREG r2, 0x40685679;
CHECKREG r3, 0x1ED0EB56;
CHECKREG r4, 0x133E4569;
CHECKREG r5, 0x133EAF81;
CHECKREG r6, 0xF960A00D;
CHECKREG r7, 0x4FB9B312;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x921c080b;
imm32 r6, 0x7901908d;
imm32 r7, 0x679e9008;
R0.H = ( A1 -= R1.L * R0.L ) (M,T);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M,T);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,T);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,T);
R7 = A1.w;
CHECKREG r0, 0xF9CE5ABD;
CHECKREG r1, 0xF9CEFB3E;
CHECKREG r2, 0xF0575679;
CHECKREG r3, 0xF0570B76;
CHECKREG r4, 0xF1498569;
CHECKREG r5, 0xF149F7B2;
CHECKREG r6, 0xC04F908D;
CHECKREG r7, 0xC04FE214;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,189 | sim/testsuite/bfin/se_ssync.S | //Original:/proj/frio/dv/testcases/seq/se_ssync/se_ssync.dsp
// Description: Test SSYNC by writing a bunch of MMRs and verifying read
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
LD32(p0, EVT5);
LD32(r0, 0x55555555);
LD32(p1, EVT6);
LD32(r1, 0xAAAAAAAA);
LD32(p2, EVT7);
LD32(r2, 0xBABEFACE);
LD32(p3, EVT8);
LD32(r3, 0xCFCFCFCF);
LD32(p4, EVT9);
LD32(r4, 0xDEADBEEF);
LD32(p5, EVT10);
LD32(r5, 0xBAD1BAD1);
[ P0 ] = R0; // write the MMRS
[ P1 ] = R1;
[ P2 ] = R2;
[ P3 ] = R3;
[ P4 ] = R4;
[ P5 ] = R5;
SSYNC; // wait for it
R7 = [ P5 ]; // read back MMRs
R6 = [ P4 ]; // should be updated
R5 = [ P3 ];
R4 = [ P2 ];
R3 = [ P1 ];
R2 = [ P0 ];
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
CHECKREG(r2, 0x55555555);
CHECKREG(r3, 0xAAAAAAAA);
CHECKREG(r4, 0xBABEFACE);
CHECKREG(r5, 0xCFCFCFCF);
CHECKREG(r6, 0xDEADBEEF);
CHECKREG(r7, 0xBAD1BAD1);
dbg_pass;
|
tactcomplabs/xbgas-binutils-gdb | 1,791 | sim/testsuite/bfin/c_progctrl_except_rtx.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_except_rtx/c_progctrl_except_rtx.dsp
// Spec Reference: c_progctrl_except_rtx
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
// load address of exception handler
P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION
P0.H = 0xFFE0;
R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3
R0.H = exception_handler;
[ P0 ] = R0;
// Jump to User mode and enable exceptions
R0 = MidUserCode (Z);
R0.H = MidUserCode;
RETI = R0;
RTI; // cause it to go to Midusercode, .dd cause exception
BeginUserCode:
P1 = 1;
P2 = 2;
P3 = 3;
P4 = 4;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000001);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000003);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
CHECKREG(p1, 0x00000001);
CHECKREG(p2, 0x00000002);
CHECKREG(p3, 0x00000003);
CHECKREG(p4, 0x00000004);
dbg_pass;
//jump 2;
//jump -2;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
//dbg_pass;
MidUserCode:
.dd 0xFFFFFFFF
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
CC = R0;
IF !CC JUMP BeginUserCode;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
exception_handler:
R4 = RETX; // error handler: RETX has the address of the same Illegal instr
R1 += 1;
R2 += 2;
R3 += 3;
R1 += 1;
R4 += 4; // we have to add 4 to point to next instr after return
RETX = R4;
RTX; // return from exception
.section MEM_DATA_ADDR_1,"aw"
.dd 0xDEADBEEF
.dd 0xBAD00BAD
|
tactcomplabs/xbgas-binutils-gdb | 10,594 | sim/testsuite/bfin/c_dsp32shift_ahalf_ln_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_ln_s/c_dsp32shift_ahalf_ln_s.dsp
// Spec Reference: <a pointer to reference the section of the spec>
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
imm32 r7, 0x0000c007;
R0.L = ASHIFT R0.L BY R0.L (S);
R1.L = ASHIFT R1.L BY R0.L (S);
R2.L = ASHIFT R2.L BY R0.L (S);
R3.L = ASHIFT R3.L BY R0.L (S);
R4.L = ASHIFT R4.L BY R0.L (S);
R5.L = ASHIFT R5.L BY R0.L (S);
R6.L = ASHIFT R6.L BY R0.L (S);
R7.L = ASHIFT R7.L BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c001;
CHECKREG r2, 0x0000c002;
CHECKREG r3, 0x0000c003;
CHECKREG r4, 0x0000c004;
CHECKREG r5, 0x0000c005;
CHECKREG r6, 0x0000c006;
CHECKREG r7, 0x0000c007;
imm32 r0, 0x00008001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000e007;
R0.L = ASHIFT R0.L BY R1.L (S);
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L (S);
R3.L = ASHIFT R3.L BY R1.L (S);
R4.L = ASHIFT R4.L BY R1.L (S);
R5.L = ASHIFT R5.L BY R1.L (S);
R6.L = ASHIFT R6.L BY R1.L (S);
R7.L = ASHIFT R7.L BY R1.L (S);
//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000a004;
CHECKREG r3, 0x0000c006;
CHECKREG r4, 0x0000e008;
CHECKREG r5, 0x0000800a;
CHECKREG r6, 0x0000a00c;
CHECKREG r7, 0x0000c00e;
imm32 r0, 0x0000c001;
imm32 r1, 0x0000d001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.L = ASHIFT R0.L BY R2.L (S);
R1.L = ASHIFT R1.L BY R2.L (S);
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L (S);
R4.L = ASHIFT R4.L BY R2.L (S);
R5.L = ASHIFT R5.L BY R2.L (S);
R6.L = ASHIFT R6.L BY R2.L (S);
R7.L = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00008000;
CHECKREG r4, 0x00008000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00008000;
CHECKREG r7, 0x00008000;
imm32 r0, 0x00009001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000b002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000f007;
R0.L = ASHIFT R0.L BY R3.L (S);
R1.L = ASHIFT R1.L BY R3.L (S);
R2.L = ASHIFT R2.L BY R3.L (S);
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L (S);
R5.L = ASHIFT R5.L BY R3.L (S);
R6.L = ASHIFT R6.L BY R3.L (S);
R7.L = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x00008000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00008000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00008000;
CHECKREG r7, 0x00008000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R0.L (S);
R1.L = ASHIFT R1.H BY R0.L (S);
R2.L = ASHIFT R2.H BY R0.L (S);
R3.L = ASHIFT R3.H BY R0.L (S);
R4.L = ASHIFT R4.H BY R0.L (S);
R5.L = ASHIFT R5.H BY R0.L (S);
R6.L = ASHIFT R6.H BY R0.L (S);
R7.L = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x90010000;
imm32 r1, 0x00010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R0.L = ASHIFT R0.H BY R1.L (S);
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L (S);
R3.L = ASHIFT R3.H BY R1.L (S);
R4.L = ASHIFT R4.H BY R1.L (S);
R5.L = ASHIFT R5.H BY R1.L (S);
R6.L = ASHIFT R6.H BY R1.L (S);
R7.L = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x90018000;
//CHECKREG r1, 0x00018000;
CHECKREG r2, 0x90028000;
CHECKREG r3, 0x90038000;
CHECKREG r4, 0x90048000;
CHECKREG r5, 0x90058000;
CHECKREG r6, 0x90068000;
CHECKREG r7, 0x90078000;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
imm32 r2, 0xa002000f;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0xa0018000;
CHECKREG r1, 0xa0018000;
//CHECKREG r2, 0xa002000f;
CHECKREG r3, 0xa0038000;
CHECKREG r4, 0xa0048000;
CHECKREG r5, 0xa0058000;
CHECKREG r6, 0xa0068000;
CHECKREG r7, 0xa0078000;
imm32 r0, 0xc0010001;
imm32 r1, 0xc0010001;
imm32 r2, 0xc0020002;
imm32 r3, 0xc0030010;
imm32 r4, 0xc0040004;
imm32 r5, 0xc0050005;
imm32 r6, 0xc0060006;
imm32 r7, 0xc0070007;
R0.L = ASHIFT R0.H BY R3.L (S);
R1.L = ASHIFT R1.H BY R3.L (S);
R2.L = ASHIFT R2.H BY R3.L (S);
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L (S);
R5.L = ASHIFT R5.H BY R3.L (S);
R6.L = ASHIFT R6.H BY R3.L (S);
R7.L = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0xc0018000;
CHECKREG r1, 0xc0018000;
CHECKREG r2, 0xc0028000;
CHECKREG r3, 0xc0030010;
CHECKREG r4, 0xc0048000;
CHECKREG r5, 0xc0058000;
CHECKREG r6, 0xc0068000;
CHECKREG r7, 0xc0078000;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R0.L (S);
R1.H = ASHIFT R1.L BY R0.L (S);
R2.H = ASHIFT R2.L BY R0.L (S);
R3.H = ASHIFT R3.L BY R0.L (S);
R4.H = ASHIFT R4.L BY R0.L (S);
R5.H = ASHIFT R5.L BY R0.L (S);
R6.H = ASHIFT R6.L BY R0.L (S);
R7.H = ASHIFT R7.L BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R0.H = ASHIFT R0.L BY R1.L (S);
R1.H = ASHIFT R1.L BY R1.L (S);
R2.H = ASHIFT R2.L BY R1.L (S);
R3.H = ASHIFT R3.L BY R1.L (S);
R4.H = ASHIFT R4.L BY R1.L (S);
R5.H = ASHIFT R5.L BY R1.L (S);
R6.H = ASHIFT R6.L BY R1.L (S);
R7.H = ASHIFT R7.L BY R1.L (S);
CHECKREG r0, 0xa002d001;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0xa004d002;
CHECKREG r3, 0xa006d003;
CHECKREG r4, 0xa008d004;
CHECKREG r5, 0xa00ad005;
CHECKREG r6, 0xa00cd006;
CHECKREG r7, 0xa00ed007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = ASHIFT R0.L BY R2.L (S);
R1.H = ASHIFT R1.L BY R2.L (S);
//rh2 = ashift (rl2 by rl2);
R3.H = ASHIFT R3.L BY R2.L (S);
R4.H = ASHIFT R4.L BY R2.L (S);
R5.H = ASHIFT R5.L BY R2.L (S);
R6.H = ASHIFT R6.L BY R2.L (S);
R7.H = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x8000e001;
CHECKREG r1, 0x8000e001;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x8000e003;
CHECKREG r4, 0x8000e004;
CHECKREG r5, 0x8000e005;
CHECKREG r6, 0x8000e006;
CHECKREG r7, 0x8000e007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.H = ASHIFT R0.L BY R3.L (S);
R1.H = ASHIFT R1.L BY R3.L (S);
R2.H = ASHIFT R2.L BY R3.L (S);
//rh3 = ashift (rl3 by rl3) s;
R4.H = ASHIFT R4.L BY R3.L (S);
R5.H = ASHIFT R5.L BY R3.L (S);
R6.H = ASHIFT R6.L BY R3.L (S);
R7.H = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x8000f001;
CHECKREG r1, 0x8000f001;
CHECKREG r2, 0x8000f002;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x8000f004;
CHECKREG r5, 0x8000f005;
CHECKREG r6, 0x8000f006;
CHECKREG r7, 0x8000f007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R0.L (S);
R1.H = ASHIFT R1.H BY R0.L (S);
R2.H = ASHIFT R2.H BY R0.L (S);
R3.H = ASHIFT R3.H BY R0.L (S);
R4.H = ASHIFT R4.H BY R0.L (S);
R5.H = ASHIFT R5.H BY R0.L (S);
R6.H = ASHIFT R6.H BY R0.L (S);
R7.H = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.H = ASHIFT R0.H BY R1.L (S);
R1.H = ASHIFT R1.H BY R1.L (S);
R2.H = ASHIFT R2.H BY R1.L (S);
R3.H = ASHIFT R3.H BY R1.L (S);
R4.H = ASHIFT R4.H BY R1.L (S);
R5.H = ASHIFT R5.H BY R1.L (S);
R6.H = ASHIFT R6.H BY R1.L (S);
R7.H = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x80000000;
//CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0xb0018000;
CHECKREG r1, 0xb0018000;
//CHECKREG r2, 0xb002000f;
CHECKREG r3, 0xb0038000;
CHECKREG r4, 0xb0048000;
CHECKREG r5, 0xb0058000;
CHECKREG r6, 0xb0068000;
CHECKREG r7, 0xb0078000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R0.H = ASHIFT R0.H BY R3.L (S);
R1.H = ASHIFT R1.H BY R3.L (S);
R2.H = ASHIFT R2.H BY R3.L (S);
R3.H = ASHIFT R3.H BY R3.L (S);
R4.H = ASHIFT R4.H BY R3.L (S);
R5.H = ASHIFT R5.H BY R3.L (S);
R6.H = ASHIFT R6.H BY R3.L (S);
R7.H = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000010;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,125 | sim/testsuite/bfin/issue83.s | # mach: bfin
.include "testutils.inc"
start
R0.H = -32768;
R0.L = 0;
R0 >>= 0x1;
_DBG R0;
R7 = ASTAT;
_DBG R7;
//DBGA ( R7.H , 0x0000 );
//DBGA ( R7.L , 0x0000 );
cc = az;
r0 = cc;
dbga( r0.l, 0);
cc = an;
r0 = cc;
dbga( r0.l, 0);
cc = av0;
r0 = cc;
dbga( r0.l, 0);
cc = av0s;
r0 = cc;
dbga( r0.l, 0);
cc = av1;
r0 = cc;
dbga( r0.l, 0);
cc = av1s;
r0 = cc;
dbga( r0.l, 0);
R0.H = 0;
R0.L = 1;
R0 <<= 0x1f;
_DBG R0;
R7 = ASTAT;
_DBG R7;
//DBGA ( R7.H , 0x0000 );
//DBGA ( R7.L , 0x0002 );
cc = az;
r0 = cc;
dbga( r0.l, 0);
cc = an;
r0 = cc;
dbga( r0.l, 1);
cc = av0;
r0 = cc;
dbga( r0.l, 0);
cc = av0s;
r0 = cc;
dbga( r0.l, 0);
cc = av1;
r0 = cc;
dbga( r0.l, 0);
cc = av1s;
r0 = cc;
dbga( r0.l, 0);
R1.L = -1;
R1.H = 32767;
R0 = 31;
R1 >>= R0;
_DBG R1;
R7 = ASTAT;
_DBG R7;
//DBGA ( R7.H , 0x0000 );
//DBGA ( R7.L , 0x0001 );
cc = az;
r0 = cc;
dbga( r0.l, 1);
cc = an;
r0 = cc;
dbga( r0.l, 0);
cc = av0;
r0 = cc;
dbga( r0.l, 0);
cc = av0s;
r0 = cc;
dbga( r0.l, 0);
cc = av1;
r0 = cc;
dbga( r0.l, 0);
cc = av1s;
r0 = cc;
dbga( r0.l, 0);
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,415 | sim/testsuite/bfin/c_compi2opp_pr_eq_i7_n.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_eq_i7_n/c_compi2opp_pr_eq_i7_n.dsp
// Spec Reference: compi2opp pregs = imm7 negative
# mach: bfin
.include "testutils.inc"
start
R0 = -0;
P1 = -1;
P2 = -2;
P3 = -3;
P4 = -4;
P5 = -5;
SP = -6;
FP = -7;
CHECKREG r0, -0;
CHECKREG p1, -1;
CHECKREG p2, -2;
CHECKREG p3, -3;
CHECKREG p4, -4;
CHECKREG p5, -5;
CHECKREG sp, -6;
CHECKREG fp, -7;
R0 = -8;
P1 = -9;
P2 = -10;
P3 = -11;
P4 = -12;
P5 = -13;
SP = -14;
FP = -15;
CHECKREG r0, -8;
CHECKREG p1, -9;
CHECKREG p2, -10;
CHECKREG p3, -11;
CHECKREG p4, -12;
CHECKREG p5, -13;
CHECKREG sp, -14;
CHECKREG fp, -15;
R0 = -16;
P1 = -17;
P2 = -18;
P3 = -19;
P4 = -20;
P5 = -21;
SP = -22;
FP = -23;
CHECKREG r0, -16;
CHECKREG p1, -17;
CHECKREG p2, -18;
CHECKREG p3, -19;
CHECKREG p4, -20;
CHECKREG p5, -21;
CHECKREG sp, -22;
CHECKREG fp, -23;
R0 = -24;
P1 = -25;
P2 = -26;
P3 = -27;
P4 = -28;
P5 = -29;
SP = -30;
FP = -31;
CHECKREG r0, -24;
CHECKREG p1, -25;
CHECKREG p2, -26;
CHECKREG p3, -27;
CHECKREG p4, -28;
CHECKREG p5, -29;
CHECKREG sp, -30;
CHECKREG fp, -31;
R0 = -32;
P1 = -33;
P2 = -34;
P3 = -35;
P4 = -36;
P5 = -37;
SP = -38;
FP = -39;
CHECKREG r0, -32;
CHECKREG p1, -33;
CHECKREG p2, -34;
CHECKREG p3, -35;
CHECKREG p4, -36;
CHECKREG p5, -37;
CHECKREG sp, -38;
CHECKREG fp, -39;
R0 = -40;
P1 = -41;
P2 = -42;
P3 = -43;
P4 = -44;
P5 = -45;
SP = -46;
FP = -47;
CHECKREG r0, -40;
CHECKREG p1, -41;
CHECKREG p2, -42;
CHECKREG p3, -43;
CHECKREG p4, -44;
CHECKREG p5, -45;
CHECKREG sp, -46;
CHECKREG fp, -47;
R0 = -48;
P1 = -49;
P2 = -50;
P3 = -51;
P4 = -52;
P5 = -53;
SP = -54;
FP = -55;
CHECKREG r0, -48;
CHECKREG p1, -49;
CHECKREG p2, -50;
CHECKREG p3, -51;
CHECKREG p4, -52;
CHECKREG p5, -53;
CHECKREG sp, -54;
CHECKREG fp, -55;
R0 = -56;
P1 = -57;
P2 = -58;
P3 = -59;
P4 = -60;
P5 = -61;
SP = -62;
FP = -63;
CHECKREG r0, -56;
CHECKREG p1, -57;
CHECKREG p2, -58;
CHECKREG p3, -59;
CHECKREG p4, -60;
CHECKREG p5, -61;
CHECKREG sp, -62;
CHECKREG fp, -63;
R0 = -64;
P1 = -64;
P2 = -64;
P3 = -64;
P4 = -64;
P5 = -64;
SP = -64;
FP = -64;
CHECKREG r0, -64;
CHECKREG p1, -64;
CHECKREG p2, -64;
CHECKREG p3, -64;
CHECKREG p4, -64;
CHECKREG p5, -64;
CHECKREG sp, -64;
CHECKREG fp, -64;
pass
|
tactcomplabs/xbgas-binutils-gdb | 11,001 | sim/testsuite/bfin/c_ldstidxl_st_dr_h.s | //Original:testcases/core/c_ldstidxl_st_dr_h/c_ldstidxl_st_dr_h.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0xc8;
loadsym i1, DATA_ADDR_1, 0x10;
loadsym p4, DATA_ADDR_2, 0xc8;
loadsym p5, DATA_ADDR_1, 0x00;
loadsym fp, DATA_ADDR_2, 0xc8;
loadsym i3, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
W [ P1 + 0x1002 ] = R0;
W [ P1 + 0x1004 ] = R1;
W [ P1 + 0x1006 ] = R2;
W [ P1 + 0x1008 ] = R3;
W [ P2 + -0x1010 ] = R4;
W [ P2 + -0x1022 ] = R5;
W [ P2 + -0x1034 ] = R6;
W [ P2 + -0x1046 ] = R7;
R6 = W [ P1 + 0x1002 ] (Z);
R5 = W [ P1 + 0x1004 ] (Z);
R4 = W [ P1 + 0x1006 ] (Z);
R3 = W [ P1 + 0x1008 ] (Z);
R2 = W [ P2 + -0x1010 ] (Z);
R7 = W [ P2 + -0x1022 ] (Z);
R0 = W [ P2 + -0x1034 ] (Z);
R1 = W [ P2 + -0x1046 ] (Z);
CHECKREG r0, 0x0000B0A6;
CHECKREG r1, 0x0000C0A7;
CHECKREG r2, 0x000090A4;
CHECKREG r3, 0x000080A3;
CHECKREG r4, 0x000070A2;
CHECKREG r5, 0x000060A1;
CHECKREG r6, 0x000050A0;
CHECKREG r7, 0x0000A0A5;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
W [ P3 + 0x1018 ] = R0;
W [ P3 + 0x1020 ] = R1;
W [ P3 + 0x1022 ] = R2;
W [ P3 + 0x1024 ] = R3;
W [ P4 + -0x1026 ] = R4;
W [ P4 + -0x1028 ] = R5;
W [ P4 + -0x1030 ] = R6;
W [ P4 + -0x1052 ] = R7;
R3 = W [ P3 + 0x1018 ] (Z);
R4 = W [ P3 + 0x1020 ] (Z);
R0 = W [ P3 + 0x1022 ] (Z);
R1 = W [ P3 + 0x1024 ] (Z);
R2 = W [ P4 + -0x1026 ] (Z);
R5 = W [ P4 + -0x1028 ] (Z);
R6 = W [ P4 + -0x1030 ] (Z);
R7 = W [ P4 + -0x1052 ] (Z);
CHECKREG r0, 0x000070B2;
CHECKREG r1, 0x000080B3;
CHECKREG r2, 0x000090B4;
CHECKREG r3, 0x000050B0;
CHECKREG r4, 0x000060B1;
CHECKREG r5, 0x0000A0B5;
CHECKREG r6, 0x0000B0B6;
CHECKREG r7, 0x0000C0B7;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
W [ P5 + 0x1034 ] = R0;
W [ P5 + 0x1036 ] = R1;
W [ P5 + 0x1038 ] = R2;
W [ P5 + 0x1040 ] = R3;
W [ SP + -0x1042 ] = R4;
W [ SP + -0x1054 ] = R5;
W [ SP + -0x1066 ] = R6;
W [ SP + -0x1078 ] = R7;
R6 = W [ P5 + 0x1034 ] (Z);
R5 = W [ P5 + 0x1036 ] (Z);
R4 = W [ P5 + 0x1038 ] (Z);
R3 = W [ P5 + 0x1040 ] (Z);
R2 = W [ SP + -0x1042 ] (Z);
R0 = W [ SP + -0x1054 ] (Z);
R7 = W [ SP + -0x1066 ] (Z);
R1 = W [ SP + -0x1078 ] (Z);
CHECKREG r0, 0x0000A0C5;
CHECKREG r1, 0x0000C0C7;
CHECKREG r2, 0x000090C4;
CHECKREG r3, 0x000080C3;
CHECKREG r4, 0x000070C2;
CHECKREG r5, 0x000060C1;
CHECKREG r6, 0x000050C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
W [ FP + 0x1050 ] = R0;
W [ FP + 0x1052 ] = R1;
W [ FP + 0x1054 ] = R2;
W [ FP + 0x1056 ] = R3;
W [ FP + 0x1058 ] = R4;
W [ FP + 0x1060 ] = R5;
W [ FP + 0x1062 ] = R6;
W [ FP + 0x1064 ] = R7;
R3 = W [ FP + 0x1050 ] (Z);
R4 = W [ FP + 0x1052 ] (Z);
R0 = W [ FP + 0x1054 ] (Z);
R1 = W [ FP + 0x1056 ] (Z);
R2 = W [ FP + 0x1058 ] (Z);
R5 = W [ FP + 0x1060 ] (Z);
R6 = W [ FP + 0x1062 ] (Z);
R7 = W [ FP + 0x1064 ] (Z);
CHECKREG r0, 0x000070D2;
CHECKREG r1, 0x000080D3;
CHECKREG r2, 0x000090D4;
CHECKREG r3, 0x000050D0;
CHECKREG r4, 0x000060D1;
CHECKREG r5, 0x0000A0D5;
CHECKREG r6, 0x0000B0D6;
CHECKREG r7, 0x0000C0D7;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
.space (0x2000);
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
// Make sure there is space for us to scribble
.space (0x2000);
|
tactcomplabs/xbgas-binutils-gdb | 5,401 | sim/testsuite/bfin/c_ccflag_dr_dr.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_dr/c_ccflag_dr_dr.dsp
// Spec Reference: ccflags dr-dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00110022;
imm32 r1, 0x00110022;
imm32 r2, 0x00330044;
imm32 r3, 0x00550066;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, 0x00000000;
ASTAT = R7;
R4 = ASTAT;
// positive dreg-1 EQUAL to positive dreg-2
CC = R0 == R1;
R5 = ASTAT;
CC = R0 < R1;
R6 = ASTAT;
CC = R0 <= R1;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CHECKREG r7, 0x00001025;
CC = R0 < R1;
R4 = ASTAT;
CC = R0 <= R1 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00001005;
CHECKREG r5, 0x00001025;
// positive dreg-1 GREATER than positive dreg-2
CC = R3 == R2;
R5 = ASTAT;
CC = R3 < R2;
R6 = ASTAT;
CC = R3 <= R2;
R7 = ASTAT;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
CC = R3 < R2 (IU);
R4 = ASTAT;
CC = R3 <= R2 (IU);
R5 = ASTAT;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001004;
// positive dreg-1 LESS than positive dreg-2
CC = R2 == R3;
R5 = ASTAT;
CC = R2 < R3;
R6 = ASTAT;
CC = R2 <= R3;
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
CC = R2 < R3;
R4 = ASTAT;
CC = R2 <= R3;
R5 = ASTAT;
CHECKREG r4, 0x00000022;
CHECKREG r5, 0x00000022;
imm32 r0, 0x01230123;
imm32 r1, 0x81230123;
imm32 r2, 0x04560456;
imm32 r3, 0x87890789;
// operate on negative number
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
// positive dreg-1 GREATER than negative dreg-2
CC = R0 == R1;
R5 = ASTAT;
CC = R0 < R1;
R6 = ASTAT;
CC = R0 <= R1;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// negative dreg-1 LESS than POSITIVE dreg-2 small
CC = R3 == R2;
R5 = ASTAT;
CC = R3 < R2;
R6 = ASTAT;
CC = R3 <= R2;
R7 = ASTAT;
CHECKREG r5, 0x00001006;
CHECKREG r6, 0x00001026;
CHECKREG r7, 0x00001026;
// negative dreg-1 GREATER than negative dreg-2
CC = R1 == R3;
R5 = ASTAT;
CC = R1 < R3;
R6 = ASTAT;
CC = R1 <= R3;
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// negative dreg-1 LESS than negative dreg-2
CC = R3 == R1;
R5 = ASTAT;
CC = R3 < R1;
R6 = ASTAT;
CC = R3 <= R1;
R7 = ASTAT;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
imm32 r0, 0x80230123;
imm32 r1, 0x00230123;
imm32 r2, 0x80560056;
imm32 r3, 0x00890089;
// operate on negative number
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
// negative dreg-1 LESS than POSITIVE dreg-2
CC = R2 == R3;
R5 = ASTAT;
CC = R2 < R3;
R6 = ASTAT;
CC = R2 <= R3;
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001006; // overflow and carry but not negative
CHECKREG r6, 0x00001026; // cc overflow, carry and negative
CHECKREG r7, 0x00001026;
imm32 r4, 0x44444444;
imm32 r5, 0x55555555;
imm32 r6, 0x66666666;
imm32 r7, 0x77777777;
imm32 r0, 0x00000000;
imm32 r1, 0x11111111;
imm32 r2, 0x22222222;
imm32 r3, 0x33333333;
ASTAT = R0;
R3 = ASTAT;
NOP;
CHECKREG r3, 0x00000000;
// positive dreg-1 EQUAL to positive dreg-2
CC = R4 == R5;
R0 = ASTAT;
CC = R4 < R5;
R1 = ASTAT;
CC = R4 <= R5;
R2 = ASTAT;
CC = R4 < R5;
R3 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CC = R4 <= R5;
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00000022;
// positive dreg-1 GREATER than positive dreg-2
CC = R7 == R6;
R0 = ASTAT;
CC = R7 < R6;
R1 = ASTAT;
CC = R7 <= R6;
R2 = ASTAT;
CC = R7 < R6;
R3 = ASTAT;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
CC = R7 <= R6 (IU);
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00001004;
// positive dreg-1 LESS than positive dreg-2
CC = R6 == R7;
R0 = ASTAT;
CC = R6 < R7;
R1 = ASTAT;
CC = R6 <= R7;
R2 = ASTAT;
CC = R6 < R7;
R3 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CC = R6 <= R7;
R0 = ASTAT;
NOP;
CHECKREG r0, 0x00000022;
imm32 r4, 0x01230123;
imm32 r5, 0x81230123;
imm32 r6, 0x04560456;
imm32 r7, 0x87890789;
// operate on negative number
R0 = 0;
ASTAT = R0;
R3 = ASTAT;
CHECKREG r3, 0x00000000;
// positive dreg-1 GREATER than negative dreg-2
CC = R4 == R5;
R1 = ASTAT;
CC = R4 < R5;
R2 = ASTAT;
CC = R4 <= R5;
R3 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
// negative dreg-1 LESS than POSITIVE dreg-2 small
CC = R7 == R6;
R0 = ASTAT;
CC = R7 < R6;
R1 = ASTAT;
CC = R7 <= R6;
R2 = ASTAT;
CHECKREG r0, 0x00001006;
CHECKREG r1, 0x00001026;
CHECKREG r2, 0x00001026;
// negative dreg-1 GREATER than negative dreg-2
CC = R5 == R7;
R0 = ASTAT;
CC = R5 < R7;
R1 = ASTAT;
CC = R5 <= R7;
R2 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000022;
// negative dreg-1 LESS than negative dreg-2
CC = R7 == R5;
R1 = ASTAT;
CC = R7 < R5;
R2 = ASTAT;
CC = R7 <= R5;
R3 = ASTAT;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
imm32 r4, 0x80230123;
imm32 r5, 0x00230123;
imm32 r6, 0x80560056;
imm32 r7, 0x00890089;
// operate on negative number
R3 = 0;
ASTAT = R3;
R0 = ASTAT;
// negative dreg-1 LESS than POSITIVE dreg-2
CC = R6 == R7;
R1 = ASTAT;
CC = R6 < R7;
R2 = ASTAT;
CC = R6 <= R7;
R3 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001006; // overflow and carry but not negative
CHECKREG r2, 0x00001026; // cc overflow, carry and negative
CHECKREG r3, 0x00001026;
pass;
|
tactcomplabs/xbgas-binutils-gdb | 4,328 | sim/testsuite/bfin/c_cc2stat_cc_av0.S | //Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp
// Spec Reference: cc2stat cc av0
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AV0 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC = AV0; //
R0 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC = AV0; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
CC = AV0; //
R2 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC = AV0; //
R3 = CC; //
// test cc |= AV0 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC |= AV0; //
R4 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC |= AV0; //
R5 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 0
CC |= AV0; //
R6 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC |= AV0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AV0 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC &= AV0; //
R4 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC &= AV0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
CC &= AV0; //
R6 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC &= AV0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
CC ^= AV0; //
R4 = CC; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
CC ^= AV0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
CC ^= AV0; //
R6 = CC; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
CC ^= AV0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AV0 = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 = CC; //
R0 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 = CC; //
R3 = ASTAT; //
// test AV0 |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 |= CC; //
R4 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV0);
CHECKREG r3, (_CC|_AV0);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV0;
CHECKREG r6, (_CC|_AV0);
CHECKREG r7, (_CC|_AV0);
// test AV0 &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 &= CC; //
R4 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV0);
CHECKREG r3, (_CC|_AV0);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, (_CC);
CHECKREG r7, (_CC|_AV0);
// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV0 = 0
AV0 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AV0;
ASTAT = R7; // cc = 0, AV0 = 1
AV0 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV0 = 0
AV0 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV0);
ASTAT = R7; // cc = 1, AV0 = 1
AV0 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV0);
CHECKREG r3, (_CC|_AV0);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV0;
CHECKREG r6, (_CC|_AV0);
CHECKREG r7, _CC;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,825 | sim/testsuite/bfin/c_dsp32alu_byteunpack.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteunpack/c_dsp32alu_byteunpack.dsp
// Spec Reference: dsp32alu byteunpack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
( R4 , R5 ) = BYTEUNPACK R1:0;
( R1 , R3 ) = BYTEUNPACK R1:0;
( R0 , R7 ) = BYTEUNPACK R1:0;
( R6 , R2 ) = BYTEUNPACK R1:0;
CHECKREG r0, 0x00150067;
CHECKREG r1, 0x00150067;
CHECKREG r2, 0x00000067;
CHECKREG r3, 0x00890011;
CHECKREG r4, 0x00150067;
CHECKREG r5, 0x00890011;
CHECKREG r6, 0x00000015;
CHECKREG r7, 0x00890011;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7cccdd2d;
imm32 r7, 0x8eeeffff;
( R1 , R0 ) = BYTEUNPACK R3:2;
( R3 , R4 ) = BYTEUNPACK R3:2;
( R5 , R2 ) = BYTEUNPACK R3:2;
( R7 , R6 ) = BYTEUNPACK R3:2;
CHECKREG r0, 0x00550025;
CHECKREG r1, 0x00340044;
CHECKREG r2, 0x00550025;
CHECKREG r3, 0x00340044;
CHECKREG r4, 0x00550025;
CHECKREG r5, 0x00340044;
CHECKREG r6, 0x00000025;
CHECKREG r7, 0x00000055;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
( R1 , R2 ) = BYTEUNPACK R1:0 (R);
( R3 , R6 ) = BYTEUNPACK R1:0 (R);
( R4 , R0 ) = BYTEUNPACK R1:0 (R);
( R5 , R7 ) = BYTEUNPACK R1:0 (R);
CHECKREG r0, 0x00000089;
CHECKREG r1, 0x00660089;
CHECKREG r2, 0x00AB00CD;
CHECKREG r3, 0x00000066;
CHECKREG r4, 0x00000066;
CHECKREG r5, 0x00000066;
CHECKREG r6, 0x00000089;
CHECKREG r7, 0x00000089;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0xaeaa4bbb;
imm32 r6, 0xcfccd44d;
imm32 r7, 0xe1eefff4;
( R0 , R1 ) = BYTEUNPACK R3:2 (R);
( R2 , R3 ) = BYTEUNPACK R3:2 (R);
( R4 , R5 ) = BYTEUNPACK R3:2 (R);
( R6 , R7 ) = BYTEUNPACK R3:2 (R);
CHECKREG r0, 0x006C0064;
CHECKREG r1, 0x00770077;
CHECKREG r2, 0x006C0064;
CHECKREG r3, 0x00770077;
CHECKREG r4, 0x00000077;
CHECKREG r5, 0x00000077;
CHECKREG r6, 0x00000077;
CHECKREG r7, 0x00000077;
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
( R0 , R1 ) = BYTEUNPACK R1:0;
( R2 , R3 ) = BYTEUNPACK R3:2 (R);
( R4 , R5 ) = BYTEUNPACK R1:0 (R);
( R6 , R7 ) = BYTEUNPACK R3:2;
CHECKREG r0, 0x00450037;
CHECKREG r1, 0x0089001B;
CHECKREG r2, 0x00660066;
CHECKREG r3, 0x00570047;
CHECKREG r4, 0x00000089;
CHECKREG r5, 0x0000001B;
CHECKREG r6, 0x00000066;
CHECKREG r7, 0x00000066;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,203 | sim/testsuite/bfin/random_0011.S | # test acc shifts larger than they should be, and ASTAT flags
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x7cc0c090 | _VS | _V | _AV0 | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x1890bdbc;
dmm32 A0.x, 0x00000079;
A0 = A0 << 0x2;
checkreg A0.w, 0x6242f6f0;
checkreg A0.x, 0xffffffe4;
checkreg ASTAT, (0x7cc0c090 | _VS | _V | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x02fe375e;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x21;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0xffffffaf;
checkreg ASTAT, (0x50508600 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x7c800a10 | _VS | _AV0S | _AV0 | _AC1);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
A0 = A0 << 0x1f;
checkreg ASTAT, (0x7c800a10 | _VS | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x2e4b0bba;
dmm32 A0.x, 0xffffff8c;
A0 = A0 >> 0x25;
checkreg A0.w, 0xd0000000;
checkreg A0.x, 0x0000005d;
checkreg ASTAT, (0x4440c080 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC);
dmm32 A1.w, 0x3ae26599;
dmm32 A1.x, 0xfffffff3;
A1 = A1 >> 0x25;
checkreg A1.w, 0xc8000000;
checkreg A1.x, 0x0000002c;
checkreg ASTAT, (0x4c90c680 | _VS | _AV1S | _AV0S | _AC0 | _CC);
dmm32 ASTAT, (0x3c204000 | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC);
dmm32 A1.w, 0x1686a378;
dmm32 A1.x, 0x0000006a;
A1 = A1 >> 0x16;
checkreg A1.w, 0x0001a85a;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x3c204000 | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC);
dmm32 ASTAT, (0x30500800 | _VS | _AV0S | _AQ);
dmm32 A1.w, 0x6575285f;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x2e;
checkreg A1.w, 0xa17c0000;
checkreg A1.x, 0xffffffd4;
checkreg ASTAT, (0x30500800 | _VS | _AV0S | _AQ | _AN);
dmm32 ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC);
dmm32 A1.w, 0x0c7da4e2;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x29;
checkreg A1.w, 0x71000000;
checkreg A1.x, 0xffffffd2;
checkreg ASTAT, (0x70c04010 | _VS | _AV0S | _AQ | _CC | _AN);
dmm32 ASTAT, (0x74000600 | _VS | _AC1 | _AQ);
dmm32 A0.w, 0xd0e47afa;
dmm32 A0.x, 0x00000006;
A0 = A0 >> 0x32;
checkreg A0.w, 0x1ebe8000;
checkreg A0.x, 0x00000039;
checkreg ASTAT, (0x74000600 | _VS | _AC1 | _AQ);
dmm32 ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ);
dmm32 A1.w, 0x1b158860;
dmm32 A1.x, 0x00000068;
A1 = A1 >> 0x21;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000030;
checkreg ASTAT, (0x4ce08200 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ);
dmm32 ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC | _AN);
dmm32 A1.w, 0x0a2c41e4;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x25;
checkreg A1.w, 0x20000000;
checkreg A1.x, 0x0000000f;
checkreg ASTAT, (0x48c00610 | _VS | _AV1S | _AQ | _CC);
dmm32 ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AZ);
dmm32 A0.w, 0xec125059;
dmm32 A0.x, 0xffffffff;
A0 = A0 >> 0x32;
checkreg A0.w, 0x94164000;
checkreg A0.x, 0x00000004;
checkreg ASTAT, (0x08700400 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY);
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,688 | sim/testsuite/bfin/s3.s | // SHIFT test program.
// Test A0 = ASHIFT (A0 by r3);
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0000001f
// load r1=0x00000020
// load r2=0x00000000
// load r3=0x00000000
// load r4=0x00000001
// load r5=0x00000080
loadsym P0, data0;
P1 = P0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
// left by largest positive magnitude of 31 (0x1f)
// A0: 80 0000 0001 -> 80 0000 0000
R7 = 0;
ASTAT = R7;
A0.w = R4;
A0.x = R5.L;
A0 = ASHIFT A0 BY R0.L;
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// left by largest positive magnitude + 1 = 32 (0x20), which is -32
// A0: 80 0000 0001 ->
R7 = 0;
ASTAT = R7;
A0.w = R4;
A0.x = R5.L;
A0 = ASHIFT A0 BY R1.L;
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0xff80 );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// by -1
// A0: 80 0000 0001 -> c0 0000 0000
A0.w = R4;
A0.x = R5.L;
R3.L = 0x00ff;
A0 = ASHIFT A0 BY R3.L;
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xffc0 );
pass
.data
data0:
.dw 0x001f
.dw 0x0000
.dw 0x0020
.dw 0x0000
.dw 0x0059
.dw 0x0000
.dw 0x005a
.dw 0x0000
.dw 0x0001
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 10,799 | sim/testsuite/bfin/se_loop_lr.S | //Original:/proj/frio/dv/testcases/seq/se_loop_lr/se_loop_lr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
LD32_LABEL(r0, l1e);
LSETUP ( l1e , l1e ) LC0 = P1;
l1s:LT0 = R0;
l1e:[ -- SP ] = R7;
LD32_LABEL(r0, ls1);
LSETUP ( l2s , l2e ) LC0 = P0;
l2s:LB0 = R0;
ls1:R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ls2);
LD32_LABEL(r1, ls3);
LSETUP ( l3s , l3e ) LC0 = P0;
l3s:LT0 = R0;
ls2:LB0 = R1;
ls3:R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ls4);
LD32_LABEL(r1, ls5);
LSETUP ( l4s , l4e ) LC0 = P0;
l4s:LT0 = R0;
LB0 = r1;
ls4:R7 += 3;
ls5:R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ls6);
LD32_LABEL(r1, ls7);
LSETUP ( l5s , l5e ) LC0 = P0;
l5s:LB0 = R1;
LT0 = r0;
ls6:R7 += 3;
R4 += 4;
R5 += 3;
ls7:R6 += 3;
l5e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ls8);
LD32_LABEL(r1, ls9);
LSETUP ( l6s , l6e ) LC0 = P0;
l6s:R5 += 1;
LB0 = r1;
LT0 = r0;
ls8:R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
ls9:R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
LD32_LABEL(r0, m1e);
LSETUP ( m1e , m1e ) LC1 = P1;
m1s:LT0 = R0;
m1e:[ -- SP ] = R7;
LD32_LABEL(r0, ms1);
LSETUP ( m2s , m2e ) LC1 = P0;
m2s:LB0 = R0;
ms1:R6 += 2;
m2e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ms2);
LD32_LABEL(r1, ms3);
LSETUP ( m3s , m3e ) LC1 = P0;
m3s:LT0 = R0;
ms2:LB0 = R1;
ms3:R7 += 3;
m3e:[ -- SP ] = ( R7:5 );
LD32_LABEL(r0, ms4);
LD32_LABEL(r1, ms5);
LSETUP ( m4s , m4e ) LC1 = P0;
m4s:LT0 = R0;
LB0 = r1;
ms4:R7 += 3;
ms5:R4 += 4;
m4e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ms6);
LD32_LABEL(r1, ms7);
LSETUP ( m5s , m5e ) LC1 = P0;
m5s:LB0 = R1;
LT0 = r0;
ms6:R7 += 3;
R4 += 4;
R5 += 3;
ms7:R6 += 3;
m5e:[ -- SP ] = ( R7:4 );
LD32_LABEL(r0, ms8);
LD32_LABEL(r1, ms9);
LSETUP ( m6s , m6e ) LC1 = P0;
m6s:R5 += 1;
LB0 = r1;
LT0 = r0;
ms8:R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
ms9:R7 += 5;
m6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 6,402 | sim/testsuite/bfin/c_ldst_st_p_p_pp.s | //Original:/testcases/core/c_ldst_st_p_p_pp/c_ldst_st_p_p_pp.dsp
// Spec Reference: c_ldst st p++ p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// initial values p-p
imm32 p5, 0x0a231507;
imm32 p1, 0x1b342618;
imm32 p2, 0x2c453729;
imm32 p0, 0x125afbd3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
[ P4 ++ ] = P1;
[ FP ++ ] = P2;
[ P4 ++ ] = P2;
[ FP ++ ] = P0;
[ P4 ++ ] = P0;
[ FP ++ ] = P5;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R1 = [ P4 ++ ];
R2 = [ FP ++ ];
R4 = [ P4 ++ ];
R5 = [ FP ++ ];
CHECKREG r1, 0x1B342618;
CHECKREG r2, 0x2C453729;
CHECKREG r4, 0x2C453729;
CHECKREG r5, 0x125AFBD3;
R1 = [ P4 ++ ];
R2 = [ FP ++ ];
R4 = [ P4 ++ ];
R5 = [ FP ++ ];
CHECKREG r1, 0x125AFBD3;
CHECKREG r2, 0x0A231507;
CHECKREG r4, 0x8C8D8E8F;
CHECKREG r5, 0xACADAEAF;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 5,801 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_xb.s | //Original:testcases/core/c_ldst_ld_d_p_mm_xb/c_ldst_ld_d_p_mm_xb.dsp
// Spec Reference: c_ldst ld d [p--] xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
R5 = B [ P5 -- ] (X);
R6 = B [ P1 -- ] (X);
R7 = B [ P2 -- ] (X);
R0 = B [ P3 -- ] (X);
R1 = B [ P4 -- ] (X);
R2 = B [ FP -- ] (X);
R3 = B [ SP -- ] (X);
CHECKREG r0, 0xFFFFFFEE;
CHECKREG r1, 0x00000013;
CHECKREG r2, 0x00000023;
CHECKREG r3, 0xFFFFFFA3;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000044;
CHECKREG r6, 0xFFFFFF94;
CHECKREG r7, 0xFFFFFFCD;
R6 = B [ P5 -- ] (X);
R7 = B [ P1 -- ] (X);
R0 = B [ P2 -- ] (X);
R1 = B [ P3 -- ] (X);
R2 = B [ P4 -- ] (X);
R3 = B [ FP -- ] (X);
R4 = B [ SP -- ] (X);
CHECKREG r0, 0xFFFFFFC5;
CHECKREG r1, 0x0000007C;
CHECKREG r2, 0xFFFFFF9C;
CHECKREG r3, 0x0000001C;
CHECKREG r4, 0xFFFFFF9C;
CHECKREG r5, 0x00000044;
CHECKREG r6, 0x0000001C;
CHECKREG r7, 0x0000003C;
R7 = B [ P5 -- ] (X);
R0 = B [ P1 -- ] (X);
R1 = B [ P2 -- ] (X);
R2 = B [ P3 -- ] (X);
R3 = B [ P4 -- ] (X);
R4 = B [ FP -- ] (X);
R5 = B [ SP -- ] (X);
CHECKREG r0, 0x0000003D;
CHECKREG r1, 0xFFFFFFC6;
CHECKREG r2, 0x0000007D;
CHECKREG r3, 0xFFFFFF9D;
CHECKREG r4, 0x0000001D;
CHECKREG r5, 0xFFFFFF9D;
CHECKREG r6, 0x0000001C;
CHECKREG r7, 0x0000001D;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 4,681 | sim/testsuite/bfin/c_regmv_pr_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_pr_dep_nostall/c_regmv_pr_dep_nostall.dsp
// Spec Reference: regmv pr-dep no stall
# mach: bfin
.include "testutils.inc"
start
//imm32 p0, 0x00001111;
imm32 p1, 0x32213330;
imm32 p2, 0x34415550;
imm32 p3, 0x36617770;
imm32 p4, 0x38819990;
imm32 p5, 0x3aa1bbb0;
imm32 fp, 0x3cc1ddd0;
imm32 sp, 0x3ee1fff0;
// P-reg to P-reg to R-reg: no stall
P4 = P1;
R1 = P4;
SP = P5;
R2 = SP;
P1 = FP;
R3 = P1;
CHECKREG r1, 0x32213330;
CHECKREG r2, 0x3AA1BBB0;
CHECKREG r3, 0x3CC1DDD0;
//imm32 p0, 0x00001111;
imm32 p1, 0x22213332;
imm32 p2, 0x44415552;
imm32 p3, 0x66617772;
imm32 p4, 0x88819992;
imm32 p5, 0xaaa1bbb2;
imm32 fp, 0xccc1ddd2;
imm32 sp, 0xeee1fff2;
// P-reg to P-reg to I reg: no stall
P1 = P2;
I0 = P1;
P3 = P2;
I1 = P3;
P5 = P4;
I2 = P5;
FP = SP;
I3 = FP;
R4 = I3;
R5 = I2;
R6 = I1;
R7 = I0;
CHECKREG r4, 0xEEE1FFF2;
CHECKREG r5, 0x88819992;
CHECKREG r6, 0x44415552;
CHECKREG r7, 0x44415552;
//imm32 p0, 0x00001111;
imm32 p1, 0x22213332;
imm32 p2, 0x44415552;
imm32 p3, 0x66617772;
imm32 p4, 0x88819992;
imm32 p5, 0xaaa1bbb2;
imm32 fp, 0xccc1ddd2;
imm32 sp, 0xe111fff2;
// P-reg to P-reg to M reg: no stall
P1 = P4;
M0 = P1;
P3 = P2;
M1 = P3;
P5 = P4;
M2 = P5;
FP = SP;
M3 = FP;
R4 = M3;
R5 = M2;
R6 = M1;
R7 = M0;
CHECKREG r4, 0xE111FFF2;
CHECKREG r5, 0x88819992;
CHECKREG r6, 0x44415552;
CHECKREG r7, 0x88819992;
//imm32 p0, 0x00001111;
imm32 p1, 0x22213332;
imm32 p2, 0x44215552;
imm32 p3, 0x66217772;
imm32 p4, 0x88219992;
imm32 p5, 0xaa21bbb2;
imm32 fp, 0xcc21ddd2;
imm32 sp, 0xee21fff2;
// P-reg to P-reg to L reg: no stall
P1 = P0;
L0 = P1;
P3 = P2;
L1 = P3;
P5 = P4;
L2 = P5;
FP = SP;
L3 = FP;
R4 = L3;
R5 = L2;
R6 = L1;
R7 = L0;
CHECKREG r4, 0xEE21FFF2;
CHECKREG r5, 0x88219992;
CHECKREG r6, 0x44215552;
//imm32 p0, 0x00001111;
imm32 p1, 0x22213332;
imm32 p2, 0x44415532;
imm32 p3, 0x66617732;
imm32 p4, 0x88819932;
imm32 p5, 0xaaa1bb32;
imm32 fp, 0xccc1dd32;
imm32 sp, 0xeee1ff32;
// P-reg to P-reg to B reg: no stall
P1 = FP;
B0 = P1;
P3 = P2;
B1 = P3;
P5 = P4;
B2 = P5;
FP = SP;
B3 = FP;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r4, 0xEEE1FF32;
CHECKREG r5, 0x88819932;
CHECKREG r6, 0x44415532;
CHECKREG r7, 0xccc1dd32;
imm32 i0, 0x03001131;
imm32 i1, 0x23223333;
imm32 i2, 0x43445535;
imm32 i3, 0x63667737;
imm32 m0, 0x83889939;
imm32 m1, 0xa3aabb3b;
imm32 m2, 0xc3ccdd3d;
imm32 m3, 0xe3eeff3f;
// I,M-reg to P-reg to R-reg: no stall
P1 = I0;
R0 = P1;
P2 = I1;
R1 = P2;
P3 = I2;
R2 = P3;
P4 = I3;
R3 = P4;
P5 = M0;
R4 = P5;
SP = M1;
R5 = SP;
FP = M2;
R6 = FP;
FP = M3;
R7 = FP;
CHECKREG r0, 0x03001131;
CHECKREG r1, 0x23223333;
CHECKREG r2, 0x43445535;
CHECKREG r3, 0x63667737;
CHECKREG r4, 0x83889939;
CHECKREG r5, 0xA3AABB3B;
CHECKREG r6, 0xC3CCDD3D;
CHECKREG r7, 0xE3EEFF3F;
imm32 i0, 0x12001111;
imm32 i1, 0x12221333;
imm32 i2, 0x12441555;
imm32 i3, 0x12661777;
imm32 m0, 0x12881999;
imm32 m1, 0x12aa1bbb;
imm32 m2, 0x12cc1ddd;
imm32 m3, 0x12ee1fff;
// I,M-reg to P-reg to L,B reg: no stall
P1 = I0;
L0 = P1;
P1 = I1;
L1 = P1;
P2 = I2;
L2 = P2;
P3 = I3;
L3 = P3;
P4 = M0;
B0 = P4;
P5 = M1;
B1 = P5;
SP = M2;
B2 = SP;
FP = M3;
B3 = FP;
//CHECKREG r0, 0x12001111;
CHECKREG p1, 0x12221333;
CHECKREG p2, 0x12441555;
CHECKREG p3, 0x12661777;
CHECKREG p4, 0x12881999;
CHECKREG p5, 0x12AA1BBB;
CHECKREG sp, 0x12CC1DDD;
CHECKREG fp, 0x12EE1FFF;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x12661777;
CHECKREG r1, 0x12441555;
CHECKREG r2, 0x12221333;
CHECKREG r3, 0x12001111;
CHECKREG r4, 0x12EE1FFF;
CHECKREG r5, 0x12CC1DDD;
CHECKREG r6, 0x12AA1BBB;
CHECKREG r7, 0x12881999;
imm32 l0, 0x23003111;
imm32 l1, 0x23223333;
imm32 l2, 0x23443555;
imm32 l3, 0x23663777;
imm32 b0, 0x23883999;
imm32 b0, 0x23aa3bbb;
imm32 b0, 0x23cc3ddd;
imm32 b0, 0x23ee3fff;
// L,B-reg to P-reg to I,M reg: no stall
P1 = L0;
I0 = P1;
P1 = L1;
I1 = P1;
P2 = L2;
I2 = P2;
P3 = L3;
I3 = P3;
P4 = B0;
M0 = P4;
P5 = B1;
M1 = P5;
SP = B2;
M2 = SP;
FP = B3;
M3 = FP;
R0 = M3;
R1 = M2;
R2 = M1;
R3 = M0;
R4 = I3;
R5 = I2;
R6 = I1;
R7 = I0;
//CHECKREG r0, 0x1EEE1FFF;
CHECKREG p1, 0x23223333;
CHECKREG p2, 0x23443555;
CHECKREG p3, 0x23663777;
CHECKREG p4, 0x23EE3FFF;
CHECKREG p5, 0x12AA1BBB;
CHECKREG sp, 0x12CC1DDD;
CHECKREG fp, 0x12EE1FFF;
CHECKREG r0, 0x12EE1FFF;
CHECKREG r1, 0x12CC1DDD;
CHECKREG r2, 0x12AA1BBB;
CHECKREG r3, 0x23EE3FFF;
CHECKREG r4, 0x23663777;
CHECKREG r5, 0x23443555;
CHECKREG r6, 0x23223333;
CHECKREG r7, 0x23003111;
pass
|
tactcomplabs/xbgas-binutils-gdb | 8,410 | sim/testsuite/bfin/c_ldst_st_p_d_mm_b.s | //Original:testcases/core/c_ldst_st_p_d_mm_b/c_ldst_st_p_d_mm_b.dsp
// Spec Reference: c_ldst st_p-- b byte
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// reset values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
B [ P5 -- ] = R0;
B [ P1 -- ] = R1;
B [ P2 -- ] = R2;
B [ P3 -- ] = R3;
B [ P4 -- ] = R4;
B [ FP -- ] = R5;
B [ SP -- ] = R6;
B [ P5 -- ] = R1;
B [ P1 -- ] = R2;
B [ P2 -- ] = R3;
B [ P3 -- ] = R4;
B [ P4 -- ] = R5;
B [ FP -- ] = R6;
B [ SP -- ] = R7;
B [ P5 -- ] = R2;
B [ P1 -- ] = R3;
B [ P2 -- ] = R4;
B [ P3 -- ] = R5;
B [ P4 -- ] = R6;
B [ FP -- ] = R7;
B [ SP -- ] = R0;
B [ P5 -- ] = R3;
B [ P1 -- ] = R4;
B [ P2 -- ] = R5;
B [ P3 -- ] = R6;
B [ P4 -- ] = R7;
B [ FP -- ] = R0;
B [ SP -- ] = R1;
B [ P5 -- ] = R4;
B [ P1 -- ] = R5;
B [ P2 -- ] = R6;
B [ P3 -- ] = R7;
B [ P4 -- ] = R0;
B [ FP -- ] = R1;
B [ SP -- ] = R2;
B [ P5 -- ] = R5;
B [ P1 -- ] = R6;
B [ P2 -- ] = R7;
B [ P3 -- ] = R0;
B [ P4 -- ] = R1;
B [ FP -- ] = R2;
B [ SP -- ] = R3;
B [ P5 -- ] = R6;
B [ P1 -- ] = R7;
B [ P2 -- ] = R0;
B [ P3 -- ] = R1;
B [ P4 -- ] = R2;
B [ FP -- ] = R3;
B [ SP -- ] = R4;
B [ P5 -- ] = R7;
B [ P1 -- ] = R0;
B [ P2 -- ] = R1;
B [ P3 -- ] = R2;
B [ P4 -- ] = R3;
B [ FP -- ] = R4;
B [ SP -- ] = R5;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
R0 = [ P1 -- ];
R1 = [ P2 -- ];
R2 = [ P3 -- ];
R3 = [ P4 -- ];
R4 = [ P5 -- ];
R5 = [ FP -- ];
R6 = [ SP -- ];
CHECKREG r1, 0x00000029;
CHECKREG r2, 0x0000003A;
CHECKREG r3, 0x0000004B;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x0000005C;
CHECKREG r6, 0xE0E1E26D;
CHECKREG r7, 0x719A8C7E;
R1 = [ P1 -- ];
R2 = [ P2 -- ];
R3 = [ P3 -- ];
R4 = [ P4 -- ];
R5 = [ P5 -- ];
R6 = [ FP -- ];
R7 = [ SP -- ];
CHECKREG r1, 0x293A4B5C;
CHECKREG r2, 0x3A4B5C6D;
CHECKREG r3, 0x4B5C6D7E;
CHECKREG r4, 0x5C6D7E07;
CHECKREG r5, 0x18293A4B;
CHECKREG r6, 0x6D7E0718;
CHECKREG r7, 0x7E071829;
R3 = [ P1 -- ];
R4 = [ P2 -- ];
R5 = [ P3 -- ];
R6 = [ P4 -- ];
R7 = [ P5 -- ];
R0 = [ FP -- ];
R1 = [ SP -- ];
CHECKREG r1, 0x3A4B5CDB;
CHECKREG r2, 0x3A4B5C6D;
CHECKREG r3, 0x6D7E073B;
CHECKREG r4, 0x7E07185B;
CHECKREG r5, 0x0718297B;
CHECKREG r6, 0x18293A9B;
CHECKREG r7, 0x5C6D7E1B;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 4,611 | sim/testsuite/bfin/c_dsp32shift_signbits_rh.s | //Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp
// Spec Reference: dsp32shift signbits dregs_hi
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xd1000000;
imm32 r1, 0xd2000001;
imm32 r2, 0xd3000002;
imm32 r3, 0xd4000003;
imm32 r4, 0xd5000004;
imm32 r5, 0xd6000005;
imm32 r6, 0xd7000006;
imm32 r7, 0xd8000007;
R0.L = SIGNBITS R0.H;
R1.L = SIGNBITS R0.H;
R2.L = SIGNBITS R0.H;
R3.L = SIGNBITS R0.H;
R4.L = SIGNBITS R0.H;
R5.L = SIGNBITS R0.H;
R6.L = SIGNBITS R0.H;
R7.L = SIGNBITS R0.H;
CHECKREG r0, 0xD1000001;
CHECKREG r1, 0xD2000001;
CHECKREG r2, 0xD3000001;
CHECKREG r3, 0xD4000001;
CHECKREG r4, 0xD5000001;
CHECKREG r5, 0xD6000001;
CHECKREG r6, 0xD7000001;
CHECKREG r7, 0xD8000001;
imm32 r0, 0xe200d001;
imm32 r1, 0xe2000001;
imm32 r2, 0xe200d002;
imm32 r3, 0xe200d003;
imm32 r4, 0xe200d004;
imm32 r5, 0xe200d005;
imm32 r6, 0xe200d006;
imm32 r7, 0xe200d007;
R0.L = SIGNBITS R1.H;
R1.L = SIGNBITS R1.H;
R2.L = SIGNBITS R1.H;
R3.L = SIGNBITS R1.H;
R4.L = SIGNBITS R1.H;
R5.L = SIGNBITS R1.H;
R6.L = SIGNBITS R1.H;
R7.L = SIGNBITS R1.H;
CHECKREG r0, 0xE2000002;
CHECKREG r1, 0xE2000002;
CHECKREG r2, 0xE2000002;
CHECKREG r3, 0xE2000002;
CHECKREG r4, 0xE2000002;
CHECKREG r5, 0xE2000002;
CHECKREG r6, 0xE2000002;
CHECKREG r7, 0xE2000002;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0xf000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.L = SIGNBITS R2.H;
R1.L = SIGNBITS R2.H;
R2.L = SIGNBITS R2.H;
R3.L = SIGNBITS R2.H;
R4.L = SIGNBITS R2.H;
R5.L = SIGNBITS R2.H;
R6.L = SIGNBITS R2.H;
R7.L = SIGNBITS R2.H;
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000003;
CHECKREG r2, 0xF0000003;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000003;
CHECKREG r5, 0x00000003;
CHECKREG r6, 0x00000003;
CHECKREG r7, 0x00000003;
imm32 r0, 0x0100f001;
imm32 r1, 0x0100f001;
imm32 r2, 0x0100f002;
imm32 r3, 0x01000010;
imm32 r4, 0x0100f004;
imm32 r5, 0x0100f005;
imm32 r6, 0x0100f006;
imm32 r7, 0x0100f007;
R0.L = SIGNBITS R3.H;
R1.L = SIGNBITS R3.H;
R2.L = SIGNBITS R3.H;
R3.L = SIGNBITS R3.H;
R4.L = SIGNBITS R3.H;
R5.L = SIGNBITS R3.H;
R6.L = SIGNBITS R3.H;
R7.L = SIGNBITS R3.H;
CHECKREG r0, 0x01000006;
CHECKREG r1, 0x01000006;
CHECKREG r2, 0x01000006;
CHECKREG r3, 0x01000006;
CHECKREG r4, 0x01000006;
CHECKREG r5, 0x01000006;
CHECKREG r6, 0x01000006;
CHECKREG r7, 0x01000006;
imm32 r0, 0x04000000;
imm32 r1, 0x04010000;
imm32 r2, 0x04020000;
imm32 r3, 0x04030000;
imm32 r4, 0x04040000;
imm32 r5, 0x04050000;
imm32 r6, 0x04060000;
imm32 r7, 0x04070000;
R0.L = SIGNBITS R4.H;
R1.L = SIGNBITS R4.H;
R2.L = SIGNBITS R4.H;
R3.L = SIGNBITS R4.H;
R4.L = SIGNBITS R4.H;
R5.L = SIGNBITS R4.H;
R6.L = SIGNBITS R4.H;
R7.L = SIGNBITS R4.H;
CHECKREG r0, 0x04000004;
CHECKREG r1, 0x04010004;
CHECKREG r2, 0x04020004;
CHECKREG r3, 0x04030004;
CHECKREG r4, 0x04040004;
CHECKREG r5, 0x04050004;
CHECKREG r6, 0x04060004;
CHECKREG r7, 0x04070004;
imm32 r0, 0xa5010000;
imm32 r1, 0xa5010001;
imm32 r2, 0xa5020000;
imm32 r3, 0xa5030000;
imm32 r4, 0xa5540000;
imm32 r5, 0xa5550000;
imm32 r6, 0xa5060000;
imm32 r7, 0xa5070000;
R0.L = SIGNBITS R5.H;
R1.L = SIGNBITS R5.H;
R2.L = SIGNBITS R5.H;
R3.L = SIGNBITS R5.H;
R4.L = SIGNBITS R5.H;
R5.L = SIGNBITS R5.H;
R6.L = SIGNBITS R5.H;
R7.L = SIGNBITS R5.H;
CHECKREG r0, 0xA5010000;
CHECKREG r1, 0xA5010000;
CHECKREG r2, 0xA5020000;
CHECKREG r3, 0xA5030000;
CHECKREG r4, 0xA5540000;
CHECKREG r5, 0xA5550000;
CHECKREG r6, 0xA5060000;
CHECKREG r7, 0xA5070000;
imm32 r0, 0xb6010000;
imm32 r1, 0xb6010000;
imm32 r2, 0xb602000f;
imm32 r3, 0xb6030000;
imm32 r4, 0xb6040000;
imm32 r5, 0xb6050000;
imm32 r6, 0xb6060000;
imm32 r7, 0xb6670000;
R0.L = SIGNBITS R6.H;
R1.L = SIGNBITS R6.H;
R2.L = SIGNBITS R6.H;
R3.L = SIGNBITS R6.H;
R4.L = SIGNBITS R6.H;
R5.L = SIGNBITS R6.H;
R6.L = SIGNBITS R6.H;
R7.L = SIGNBITS R6.H;
CHECKREG r0, 0xB6010000;
CHECKREG r1, 0xB6010000;
CHECKREG r2, 0xB6020000;
CHECKREG r3, 0xB6030000;
CHECKREG r4, 0xB6040000;
CHECKREG r5, 0xB6050000;
CHECKREG r6, 0xB6060000;
CHECKREG r7, 0xB6670000;
imm32 r0, 0xd7010000;
imm32 r1, 0xd7010000;
imm32 r2, 0xd7020000;
imm32 r3, 0xd7030010;
imm32 r4, 0xd7040000;
imm32 r5, 0xd7050000;
imm32 r6, 0xd7060000;
imm32 r7, 0xd7070000;
R0.L = SIGNBITS R7.H;
R1.L = SIGNBITS R7.H;
R2.L = SIGNBITS R7.H;
R3.L = SIGNBITS R7.H;
R4.L = SIGNBITS R7.H;
R5.L = SIGNBITS R7.H;
R6.L = SIGNBITS R7.H;
R7.L = SIGNBITS R7.H;
CHECKREG r0, 0xD7010001;
CHECKREG r1, 0xD7010001;
CHECKREG r2, 0xD7020001;
CHECKREG r3, 0xD7030001;
CHECKREG r4, 0xD7040001;
CHECKREG r5, 0xD7050001;
CHECKREG r6, 0xD7060001;
CHECKREG r7, 0xD7070001;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,778 | sim/testsuite/bfin/c_dsp32shift_align8.s | //Original:/testcases/core/c_dsp32shift_align8/c_dsp32shift_align8.dsp
// Spec Reference: dsp32shift align8
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x08000807;
R1 = ALIGN8 ( R1 , R0 );
R2 = ALIGN8 ( R2 , R0 );
R3 = ALIGN8 ( R3 , R0 );
R4 = ALIGN8 ( R4 , R0 );
R5 = ALIGN8 ( R5 , R0 );
R6 = ALIGN8 ( R6 , R0 );
R7 = ALIGN8 ( R7 , R0 );
R0 = ALIGN8 ( R0 , R0 );
CHECKREG r0, 0x01000000;
CHECKREG r1, 0x01000000;
CHECKREG r2, 0x02000000;
CHECKREG r3, 0x03000000;
CHECKREG r4, 0x04000000;
CHECKREG r5, 0x05000000;
CHECKREG r6, 0x66000000;
CHECKREG r7, 0x07000000;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000002;
imm32 r2, 0x09400002;
imm32 r3, 0x09100003;
imm32 r4, 0x09020004;
imm32 r5, 0x09003005;
imm32 r6, 0x09000406;
imm32 r7, 0x09000057;
R0 = ALIGN8 ( R0 , R1 );
R2 = ALIGN8 ( R2 , R1 );
R3 = ALIGN8 ( R3 , R1 );
R4 = ALIGN8 ( R4 , R1 );
R5 = ALIGN8 ( R5 , R1 );
R6 = ALIGN8 ( R6 , R1 );
R7 = ALIGN8 ( R7 , R1 );
R1 = ALIGN8 ( R1 , R1 );
CHECKREG r0, 0x01090000;
CHECKREG r1, 0x02090000;
CHECKREG r2, 0x02090000;
CHECKREG r3, 0x03090000;
CHECKREG r4, 0x04090000;
CHECKREG r5, 0x05090000;
CHECKREG r6, 0x06090000;
CHECKREG r7, 0x57090000;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a400010;
imm32 r4, 0x0a05e004;
imm32 r5, 0x0a006005;
imm32 r6, 0x0a00e706;
imm32 r7, 0x0a00e087;
R0 = ALIGN8 ( R0 , R2 );
R1 = ALIGN8 ( R1 , R2 );
R3 = ALIGN8 ( R3 , R2 );
R4 = ALIGN8 ( R4 , R2 );
R5 = ALIGN8 ( R5 , R2 );
R6 = ALIGN8 ( R6 , R2 );
R7 = ALIGN8 ( R7 , R2 );
R2 = ALIGN8 ( R2 , R2 );
CHECKREG r0, 0x010A0000;
CHECKREG r1, 0x010A0000;
CHECKREG r2, 0x0F0A0000;
CHECKREG r3, 0x100A0000;
CHECKREG r4, 0x040A0000;
CHECKREG r5, 0x050A0000;
CHECKREG r6, 0x060A0000;
CHECKREG r7, 0x870A0000;
imm32 r0, 0x2b00f001;
imm32 r1, 0x0300f001;
imm32 r2, 0x0b40f002;
imm32 r3, 0x0b050010;
imm32 r4, 0x0b006004;
imm32 r5, 0x0b00f705;
imm32 r6, 0x0b00f086;
imm32 r7, 0x0b00f009;
R0 = ALIGN8 ( R0 , R3 );
R1 = ALIGN8 ( R1 , R3 );
R2 = ALIGN8 ( R2 , R3 );
R4 = ALIGN8 ( R4 , R3 );
R5 = ALIGN8 ( R5 , R3 );
R6 = ALIGN8 ( R6 , R3 );
R7 = ALIGN8 ( R7 , R3 );
R3 = ALIGN8 ( R3 , R3 );
CHECKREG r0, 0x010B0500;
CHECKREG r1, 0x010B0500;
CHECKREG r2, 0x020B0500;
CHECKREG r3, 0x100B0500;
CHECKREG r4, 0x040B0500;
CHECKREG r5, 0x050B0500;
CHECKREG r6, 0x860B0500;
CHECKREG r7, 0x090B0500;
imm32 r0, 0x4c0000c0;
imm32 r1, 0x050100c0;
imm32 r2, 0x0c6200c0;
imm32 r3, 0x0c0700c0;
imm32 r4, 0x0c04800c;
imm32 r5, 0x0c0509c0;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c0700ca;
R0 = ALIGN8 ( R0 , R4 );
R1 = ALIGN8 ( R1 , R4 );
R2 = ALIGN8 ( R2 , R4 );
R3 = ALIGN8 ( R3 , R4 );
R5 = ALIGN8 ( R5 , R4 );
R6 = ALIGN8 ( R6 , R4 );
R7 = ALIGN8 ( R7 , R4 );
R4 = ALIGN8 ( R4 , R4 );
CHECKREG r0, 0xC00C0480;
CHECKREG r1, 0xC00C0480;
CHECKREG r2, 0xC00C0480;
CHECKREG r3, 0xC00C0480;
CHECKREG r4, 0x0C0C0480;
CHECKREG r5, 0xC00C0480;
CHECKREG r6, 0x000C0480;
CHECKREG r7, 0xCA0C0480;
imm32 r0, 0xa00100d0;
imm32 r1, 0xa00100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa0050007;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0 = ALIGN8 ( R0 , R5 );
R1 = ALIGN8 ( R1 , R5 );
R2 = ALIGN8 ( R2 , R5 );
R3 = ALIGN8 ( R3 , R5 );
R4 = ALIGN8 ( R4 , R5 );
R6 = ALIGN8 ( R6 , R5 );
R7 = ALIGN8 ( R7 , R5 );
R5 = ALIGN8 ( R5 , R5 );
CHECKREG r0, 0xD0A00500;
CHECKREG r1, 0xD1A00500;
CHECKREG r2, 0xD0A00500;
CHECKREG r3, 0xD0A00500;
CHECKREG r4, 0xD0A00500;
CHECKREG r5, 0x07A00500;
CHECKREG r6, 0xD0A00500;
CHECKREG r7, 0xD0A00500;
imm32 r0, 0xb2010000;
imm32 r1, 0xb0310000;
imm32 r2, 0xb042000f;
imm32 r3, 0xbf030000;
imm32 r4, 0xba040000;
imm32 r5, 0xbb050000;
imm32 r6, 0xbc060009;
imm32 r7, 0xb0e70000;
R0 = ALIGN8 ( R0 , R6 );
R1 = ALIGN8 ( R1 , R6 );
R2 = ALIGN8 ( R2 , R6 );
R3 = ALIGN8 ( R3 , R6 );
R4 = ALIGN8 ( R4 , R6 );
R5 = ALIGN8 ( R5 , R6 );
R6 = ALIGN8 ( R6 , R6 );
R7 = ALIGN8 ( R7 , R6 );
CHECKREG r0, 0x00BC0600;
CHECKREG r1, 0x00BC0600;
CHECKREG r2, 0x0FBC0600;
CHECKREG r3, 0x00BC0600;
CHECKREG r4, 0x00BC0600;
CHECKREG r5, 0x00BC0600;
CHECKREG r6, 0x09BC0600;
CHECKREG r7, 0x0009BC06;
imm32 r0, 0xd23100e0;
imm32 r1, 0xd04500e0;
imm32 r2, 0xde32f0e0;
imm32 r3, 0xd90300e0;
imm32 r4, 0xd07400e0;
imm32 r5, 0xdef500e0;
imm32 r6, 0xd06600e0;
imm32 r7, 0xd0080023;
R1 = ALIGN8 ( R0 , R7 );
R2 = ALIGN8 ( R1 , R7 );
R3 = ALIGN8 ( R2 , R7 );
R4 = ALIGN8 ( R3 , R7 );
R5 = ALIGN8 ( R4 , R7 );
R6 = ALIGN8 ( R5 , R7 );
R7 = ALIGN8 ( R6 , R7 );
R0 = ALIGN8 ( R7 , R7 );
CHECKREG r0, 0x0000D008;
CHECKREG r1, 0xE0D00800;
CHECKREG r2, 0x00D00800;
CHECKREG r3, 0x00D00800;
CHECKREG r4, 0x00D00800;
CHECKREG r5, 0x00D00800;
CHECKREG r6, 0x00D00800;
CHECKREG r7, 0x00D00800;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,546 | sim/testsuite/bfin/c_mode_user.S | //Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp
// Spec Reference: mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
A1 = A0 = 0;
ASTAT = R0;
// R-reg to P-reg to R reg: stall
LD32(r0, 0x1357bdad);
LD32(r1, 0x02dfe804);
LD32(r2, 0x12345679);
LD32(r3, 0x34751975);
LD32(r4, 0x08810990);
LD32(r5, 0x01a1b0b0);
LD32(r6, 0x01c1dd00);
LD32(r7, 0x01e1fff0);
R5 = R3.L * R1.L, R4 = R3.L * R1.L; // dsp32mult_pair
P4 = R5;
R6 = P4;
R1 = ( A1 += R5.L * R6.H ), A0 = R5.H * R6.L; // dsp32mac_pair
P3 = A0.w;
P4 = A1.w;
A1 = A1 (S), A0 = A0 (S); // dsp32alu_sat_aa
R6 = A0.w;
R7 = A1.w;
R0 = R7;
R2 = R0; // regmv
R2 >>>= R3; // c_alu2op_arith_r_sft.dsp
R4 = R2 - R1;
R5.L = ASHIFT R4.L BY R3.L;
R6 += -3; //c_compi2opd_dr_add_i7_n.dsp
I2 = R6;
I2 += 2;
I2 += M1;
R7 = I2;
CHECKREG(r0, 0x015AF820);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x34751975);
CHECKREG(r4, 0xFEA507E0);
CHECKREG(r5, 0xFB3A0000);
CHECKREG(r6, 0x015AF81D);
CHECKREG(r7, 0x015AF81F);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x015AF81F);
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0xFEA507E0);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
R0 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R1 = RETX;
R0 += 1;
R1 += 2;
R2 += 1;
R3 += 1;
R4 += 1;
R5 += 1;
R6 += 1;
R7 += 1;
RETX = r1;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
THANDLE: // Timer Handler 6
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = RETI;
R4 += 2;
RETI = r4;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = RETI;
R5 += 2;
RETI = r5;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = RETI;
R6 += 2;
RETI = r6;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = RETI;
R7 += 2;
RETI = r7;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = RETI;
R0 += 2;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = RETI;
R1 += 2;
RETI = r1;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
tactcomplabs/xbgas-binutils-gdb | 2,019 | sim/testsuite/bfin/c_ldst_st_p_p.s | //Original:/testcases/core/c_ldst_st_p_p/c_ldst_st_p_p.dsp
// Spec Reference: c_ldst st_p_p
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// initial values p-p
imm32 p5, 0x0a231507;
imm32 p1, 0x1b342618;
imm32 p2, 0x2c453729;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
[ P4 ] = P1;
[ FP ] = P2;
R5 = [ P4 ];
R6 = [ FP ];
CHECKREG r5, 0x1B342618;
CHECKREG r6, 0x2C453729;
[ P4 ] = P2;
[ FP ] = R3;
R5 = [ P4 ];
R6 = [ FP ];
CHECKREG r5, 0x2C453729;
CHECKREG r6, 0x3D56483A;
[ P4 ] = R3;
[ FP ] = P5;
R5 = [ P4 ];
R6 = [ FP ];
CHECKREG r5, 0x3D56483A;
CHECKREG r6, 0x0A231507;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 3,937 | sim/testsuite/bfin/c_dsp32mac_dr_a1a0_iutsh.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0_iutsh/c_dsp32mac_dr_a1a0_iutsh.dsp
// Spec Reference: dsp32mac dr_a1a0 iutsh
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0;
ASTAT = R0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x13545abd;
imm32 r1, 0xb2bcfec7;
imm32 r2, 0xc1348679;
imm32 r3, 0xd0049007;
imm32 r4, 0x2efbc556;
imm32 r5, 0xcd35560b;
imm32 r6, 0xe00c807d;
imm32 r7, 0xf78e9008;
A1 = A0 = 0;
R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L) (IS);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L) (FU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.L * R5.L) (M), R2.L = (A0 += R4.H * R5.H) (T);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H) (S2RND);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x13545ABD;
CHECKREG r1, 0x6BD10000;
CHECKREG r2, 0xEC48ED5B;
CHECKREG r3, 0x8000CEBE;
CHECKREG r4, 0x9CE8AA82;
CHECKREG r5, 0xE75ED19A;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0xF78E9008;
CHECKREG p1, 0x20296F89;
CHECKREG p2, 0x20296F89;
CHECKREG p3, 0x6BD12CD8;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0xEC485EB2;
CHECKREG fp, 0xED5B71EE;
imm32 r0, 0x13545abd;
imm32 r1, 0x22bcfec7;
imm32 r2, 0x43348679;
imm32 r3, 0x50049007;
imm32 r4, 0x6fbc5569;
imm32 r5, 0x7d35560b;
imm32 r6, 0x800c807d;
imm32 r7, 0xf98e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L) (IU);
P1 = A1.w;
P2 = A0.w;
R6.H = (A1 += R2.L * R2.H), R6.L = (A0 = R2.H * R2.L) (TFU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H) (ISS2);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H) (IH);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0x22BCFEC7;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x0F955721;
CHECKREG r4, 0x0F951905;
CHECKREG r5, 0x5721369E;
CHECKREG r6, 0x3689234C;
CHECKREG r7, 0xF98E9008;
CHECKREG p1, 0x133C5E4C;
CHECKREG p2, 0x5A4E0EEB;
CHECKREG p3, 0x368959E0;
CHECKREG p4, 0x234CFB94;
CHECKREG p5, 0x0CC36623;
CHECKREG fp, 0x59F2E980;
imm32 r0, 0x13545abd;
imm32 r1, 0x42bcfec7;
imm32 r2, 0x51348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x8d35560b;
imm32 r6, 0x900c807d;
imm32 r7, 0xa78e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.L), R0.L = (A0 = R1.L * R0.L) (IS);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.H * R3.L) (M), R1.L = (A0 -= R2.H * R3.L) (IU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H) (ISS2);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 -= R6.H * R7.L) (M), R3.L = (A0 += R6.L * R7.H) (IH);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x7FFFFFFF;
CHECKREG r2, 0x7FFF8000;
CHECKREG r3, 0x69EBC4A8;
CHECKREG r4, 0x69EB64B4;
CHECKREG r5, 0xC4A864C1;
CHECKREG r6, 0x900C807D;
CHECKREG r7, 0xA78E9008;
CHECKREG p1, 0x17A75CCC;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x4556D538;
CHECKREG p4, 0xD1E1967F;
CHECKREG p5, 0x2AEEA514;
CHECKREG fp, 0x989A946B;
imm32 r0, 0x03545abd;
imm32 r1, 0xb3bcfec7;
imm32 r2, 0x24348679;
imm32 r3, 0x60049007;
imm32 r4, 0x7fbc5569;
imm32 r5, 0x9d35560b;
imm32 r6, 0xa00c807d;
imm32 r7, 0x078e9008;
A1 = A0 = 0;
R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L) (FU);
P1 = A1.w;
P2 = A0.w;
R1.H = (A1 += R2.H * R3.H), R1.L = (A0 = R2.H * R3.L) (TFU);
P3 = A1.w;
P4 = A0.w;
R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H) (IU);
P5 = A1.w;
FP = A0.w;
R3.H = (A1 -= R6.H * R7.H) (M), R3.L = (A0 += R6.L * R7.H) (S2RND);
R4 = A1.w;
R5 = A0.w;
CHECKREG r0, 0x02560000;
CHECKREG r1, 0x0FEA145E;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x5145A344;
CHECKREG r5, 0x5B485C04;
CHECKREG r6, 0xA00C807D;
CHECKREG r7, 0x078E9008;
CHECKREG p1, 0x02562DB0;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x0FEA3E80;
CHECKREG p4, 0x145E3D6C;
CHECKREG p5, 0x4E70BDEC;
CHECKREG fp, 0x62CEFB58;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,159 | sim/testsuite/bfin/m6.s | // Test result extraction of mac instructions.
// Test basic edge values
// SIGNED INTEGER mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// integer extraction with no saturation
// 0x1 * 0x1 = 0x0000000001 -> 0x1
A1 = A0 = 0;
R5.H = (A1 += R0.L * R0.L), R5.L = (A0 += R0.L * R0.L) (IS);
DBGA ( R5.L , 0x1 );
DBGA ( R5.H , 0x1 );
// integer extraction with positive saturation
// 0x7fff * 0x7f -> 0x7fff
A1 = A0 = 0;
R5.H = (A1 += R1.L * R3.L), R5.L = (A0 += R1.L * R3.L) (IS);
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// integer extraction with negative saturation
// 0x8000 * 0x7f -> 0x8000
A1 = A0 = 0;
R5.H = (A1 += R1.H * R3.L), R5.L = (A0 += R1.H * R3.L) (IS);
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x8000 );
pass
.data;
data0:
.dw 0x0001
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 5,429 | sim/testsuite/bfin/c_dsp32alu_rpm.s | //Original:/testcases/core/c_dsp32alu_rpm/c_dsp32alu_rpm.dsp
// Spec Reference: dsp32alu dreg = +/- ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x65678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34845515;
imm32 r3, 0x46697717;
imm32 r4, 0x5567191b;
imm32 r5, 0x6789a31d;
imm32 r6, 0x74445545;
imm32 r7, 0x86667779;
R0 = R0 +|- R0;
R1 = R0 +|- R1;
R2 = R0 +|- R2;
R3 = R0 +|- R3;
R4 = R0 +|- R4;
R5 = R0 +|- R5;
R6 = R0 +|- R6;
R7 = R0 +|- R7;
CHECKREG r0, 0xCACE0000;
CHECKREG r1, 0xF25754E3;
CHECKREG r2, 0xFF52AAEB;
CHECKREG r3, 0x113788E9;
CHECKREG r4, 0x2035E6E5;
CHECKREG r5, 0x32575CE3;
CHECKREG r6, 0x3F12AABB;
CHECKREG r7, 0x51348887;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = R1 +|- R0;
R1 = R1 +|- R1;
R2 = R1 +|- R2;
R3 = R1 +|- R3;
R4 = R1 +|- R4;
R5 = R1 +|- R5;
R6 = R1 +|- R6;
R7 = R1 +|- R7;
CHECKREG r0, 0x3CF02202;
CHECKREG r1, 0x4F120000;
CHECKREG r2, 0x0356AADB;
CHECKREG r3, 0x157888D9;
CHECKREG r4, 0x279A66D7;
CHECKREG r5, 0x39BC44D5;
CHECKREG r6, 0x4BDE22D3;
CHECKREG r7, 0x5E000001;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = R2 +|- R0;
R1 = R2 +|- R1;
R2 = R2 +|- R2;
R3 = R2 +|- R3;
R4 = R2 +|- R4;
R5 = R2 +|- R5;
R6 = R2 +|- R6;
R7 = R2 +|- R7;
CHECKREG r0, 0x84ABCBAA;
CHECKREG r1, 0xA5CDA988;
CHECKREG r2, 0x86880000;
CHECKREG r3, 0xEAEE8889;
CHECKREG r4, 0xCBEF7655;
CHECKREG r5, 0xED115433;
CHECKREG r6, 0xCDCCAAAB;
CHECKREG r7, 0xEEEE8889;
imm32 r0, 0xa567892b;
imm32 r1, 0xaa89ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6a67727;
imm32 r0, 0x9a67892b;
imm32 r1, 0xa7a9ab2d;
imm32 r2, 0xb44a5525;
imm32 r3, 0xc666a727;
R0 = R3 +|- R0;
R1 = R3 +|- R1;
R2 = R3 +|- R2;
R3 = R3 +|- R3;
R4 = R3 +|- R4;
R5 = R3 +|- R5;
R6 = R3 +|- R6;
R7 = R3 +|- R7;
CHECKREG r0, 0x60CD1DFC;
CHECKREG r1, 0x6E0FFBFA;
CHECKREG r2, 0x7AB05202;
CHECKREG r3, 0x8CCC0000;
CHECKREG r4, 0x58BB89AB;
CHECKREG r5, 0x79DDABCD;
CHECKREG r6, 0x5A985555;
CHECKREG r7, 0x7BBA7777;
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = R4 +|- R0;
R1 = R4 +|- R1;
R2 = R4 +|- R2;
R3 = R4 +|- R3;
R4 = R4 +|- R4;
R5 = R4 +|- R5;
R6 = R4 +|- R6;
R7 = R4 +|- R7;
CHECKREG r0, 0xCDAF0C4A;
CHECKREG r1, 0xEFD1EA38;
CHECKREG r2, 0xCCCD4030;
CHECKREG r3, 0xEEDE3E1E;
CHECKREG r4, 0x10F00000;
CHECKREG r5, 0xBB7A44A5;
CHECKREG r6, 0xDD8C227B;
CHECKREG r7, 0xFF9E0061;
imm32 r0, 0x456b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = R5 +|- R0;
R1 = R5 +|- R1;
R2 = R5 +|- R2;
R3 = R5 +|- R3;
R4 = R5 +|- R4;
R5 = R5 +|- R5;
R6 = R5 +|- R6;
R7 = R5 +|- R7;
CHECKREG r0, 0xF0158210;
CHECKREG r1, 0x1420BFEE;
CHECKREG r2, 0xF41DA657;
CHECKREG r3, 0x0BD18827;
CHECKREG r4, 0x4331A782;
CHECKREG r5, 0x55540000;
CHECKREG r6, 0x2220E223;
CHECKREG r7, 0x67889001;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = R6 +|- R0;
R1 = R6 +|- R1;
R2 = R6 +|- R2;
R3 = R6 +|- R3;
R4 = R6 +|- R4;
R5 = R6 +|- R5;
R6 = R6 +|- R6;
R7 = R6 +|- R7;
CHECKREG r0, 0x4999572B;
CHECKREG r1, 0x6B9B4509;
CHECKREG r2, 0x07772981;
CHECKREG r3, 0x6A98295F;
CHECKREG r4, 0x16663A3D;
CHECKREG r5, 0x4999056B;
CHECKREG r6, 0x08640000;
CHECKREG r7, 0x1A98A981;
imm32 r0, 0xb76789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x2b456755;
imm32 r3, 0x56789007;
imm32 r4, 0x78bab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcdbff7;
R0 = R7 +|- R0;
R1 = R7 +|- R1;
R2 = R7 +|- R2;
R3 = R7 +|- R3;
R4 = R7 +|- R4;
R5 = R7 +|- R5;
R6 = R7 +|- R6;
R7 = R7 +|- R7;
CHECKREG r0, 0x6334364C;
CHECKREG r1, 0x1346142A;
CHECKREG r2, 0xD71258A2;
CHECKREG r3, 0x02452FF0;
CHECKREG r4, 0x2487085E;
CHECKREG r5, 0x5677B43C;
CHECKREG r6, 0x3578A27A;
CHECKREG r7, 0x579A0000;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = R4 +|- R7 (S);
R5 = R5 +|- R5 (CO);
R2 = R6 +|- R3 (SCO);
R6 = R0 +|- R4 (S);
R0 = R1 +|- R6 (S);
R2 = R2 +|- R1 (CO);
R1 = R3 +|- R0 (CO);
R7 = R7 +|- R4 (SCO);
CHECKREG r0, 0x7FFF123C;
CHECKREG r1, 0x553BE665;
CHECKREG r2, 0x1ECBE769;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x2468001A;
CHECKREG r5, 0x00008ACE;
CHECKREG r6, 0x69CF3991;
CHECKREG r7, 0x5665369C;
imm32 r0, 0xb76789ab;
imm32 r1, 0x6b79abcd;
imm32 r2, 0x2b456755;
imm32 r3, 0x56b89007;
imm32 r4, 0x78bab799;
imm32 r5, 0xaaab0bbb;
imm32 r6, 0x89abbd7d;
imm32 r7, 0xabcd2bf7;
R3 = R4 +|- R0 (S);
R5 = R5 +|- R1 (SCO);
R2 = R2 +|- R2 (S);
R7 = R7 +|- R3 (CO);
R4 = R3 +|- R4 (CO);
R0 = R1 +|- R5 (S);
R1 = R0 +|- R6 (SCO);
R6 = R6 +|- R7 (SCO);
CHECKREG r0, 0x7FFF95A9;
CHECKREG r1, 0xD82C09AA;
CHECKREG r2, 0x568A0000;
CHECKREG r3, 0x30212DEE;
CHECKREG r4, 0x7655A8DB;
CHECKREG r5, 0x5FEE1624;
CHECKREG r6, 0xE18F87B4;
CHECKREG r7, 0xFE09DBEE;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,280 | sim/testsuite/bfin/c_dsp32mac_pair_a0_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_is/c_dsp32mac_pair_a0_is.dsp
// Spec Reference: dsp32mac pair a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L, R6 = ( A0 -= R1.L * R0.L ) (ISS2);
P1 = A1.w;
A1 = R2.L * R3.L, R0 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A1.w;
A1 -= R7.L * R4.L, R2 = ( A0 += R7.H * R4.H ) (ISS2);
P3 = A1.w;
A1 += R6.L * R5.L, R4 = ( A0 += R6.L * R5.H ) (ISS2);
P4 = A1.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xF2CF3598;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xEE90C2FC;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0x00DDE22A;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0xFF910EEB;
CHECKREG p2, 0x00025D4F;
CHECKREG p3, 0xFFCD4859;
CHECKREG p4, 0x0E03FC27;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
A1 += R1.L * R0.H, R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
A1 -= R2.L * R3.H, R0 = ( A0 -= R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 -= R4.L * R5.H, R2 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
A1 += R6.L * R7.H, R0 = ( A0 += R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF89EF66E;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0xF8878042;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xFCB93CEB;
CHECKREG p2, 0xFCBB1787;
CHECKREG p3, 0xFC43C021;
CHECKREG p4, 0xFC4F7B37;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L, R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
A1 = R2.H * R3.L, R6 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 -= R4.H * R5.L, R0 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
A1 += R6.H * R7.L, R4 = ( A0 -= R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF8876658;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xD26DD7B8;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x00062F18;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0xE590030B;
CHECKREG p2, 0x0003178C;
CHECKREG p3, 0xFC43B32C;
CHECKREG p4, 0xE936EBDC;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
A1 += R5.H * R3.H, R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A0.w;
A1 -= R2.H * R1.H, R2 = ( A0 -= R2.H * R1.L ) (ISS2);
P2 = A0.w;
A1 = R7.H * R0.H, R4 = ( A0 += R7.H * R0.H ) (ISS2);
P3 = A0.w;
A1 += R4.H * R6.H, R6 = ( A0 += R4.L * R6.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0xFF256182;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0xFF1FB35E;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0xF750102E;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0xFFFCF74D;
CHECKREG p2, 0xFF92B0C1;
CHECKREG p3, 0xFF8FD9AF;
CHECKREG p4, 0xFBA80817;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
A1 += R1.L * R0.L (M), R6 = ( A0 -= R1.L * R0.L ) (ISS2);
P5 = A1.w;
P1 = A0.w;
A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H ) (ISS2);
P3 = A0.w;
A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x86BCFEC7;
CHECKREG r2, 0xF2CF3598;
CHECKREG r3, 0x00860007;
CHECKREG r4, 0xF0DDEE08;
CHECKREG r5, 0x1235860B;
CHECKREG r6, 0xF82DF258;
CHECKREG r7, 0x678E0086;
CHECKREG p1, 0xFC16F92C;
CHECKREG p2, 0xFFFD9ABC;
CHECKREG p3, 0xF9679ACC;
CHECKREG p4, 0xF86EF704;
CHECKREG p5, 0xFF82C04D;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
R0 = ( A0 -= R2.H * R3.L ) (ISS2);
P2 = A0.w;
R2 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
R0 = ( A0 += R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF89EF66E;
CHECKREG r1, 0xA1BCF4C7;
CHECKREG r2, 0xF8878042;
CHECKREG r3, 0x00010005;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0x1235010B;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xFCB93CEB;
CHECKREG p2, 0xFCBB1787;
CHECKREG p3, 0xFC43C021;
CHECKREG p4, 0xFC4F7B37;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A0.w;
R6 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H ) (ISS2);
P3 = A0.w;
R4 = ( A0 += R6.L * R7.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xF8876658;
CHECKREG r1, 0xABD69EC7;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x1EA0F4F8;
CHECKREG r5, 0x1225010B;
CHECKREG r6, 0x00062F18;
CHECKREG r7, 0x678E0561;
CHECKREG p1, 0xE590030B;
CHECKREG p2, 0x0003178C;
CHECKREG p3, 0xFC43B32C;
CHECKREG p4, 0x0F507A7C;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A0.w;
A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L ) (ISS2);
P2 = A0.w;
A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H ) (ISS2);
P3 = A0.w;
R6 = ( A0 += R4.L * R6.H ) (ISS2);
P4 = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0x91BCFEC7;
CHECKREG r2, 0x00D48D18;
CHECKREG r3, 0xD0910007;
CHECKREG r4, 0x00DA3B3C;
CHECKREG r5, 0xD235910B;
CHECKREG r6, 0x06E3E0DC;
CHECKREG r7, 0x67DE0009;
CHECKREG p1, 0xFFFCF74D;
CHECKREG p2, 0x006A468C;
CHECKREG p3, 0x006D1D9E;
CHECKREG p4, 0x0371F06E;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,752 | sim/testsuite/bfin/m2.s | // MAC test program.
// Test basic edge values
// SIGNED FRACTIONAL mode
// test ops: "+=" "-=" "=" "NOP"
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// 0x7fff * 0x7fff = 0x007ffe0002
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.L * R1.L, A0 += R0.L * R1.L;
R6 = A1.w;
_DBG ASTAT;
_DBG A0;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x7ffe );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x8000 * 0x7fff = 0xff80010000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.H * R1.L, A0 += R0.H * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8001 );
DBGA ( R7.L , 0xffff );
_DBG ASTAT;
R7 = ASTAT;
DBGA (R7.H, 0x0);
DBGA (R7.L, 0x0);
// 0x8000 * 0x8000 = 0x007fffffff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.H * R1.H, A0 += R0.H * R1.H;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate positive by first loading large value into accums
// expected value is 0x7fffffffff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
A1 += R0.L * R1.L, A0 += R0.L * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0x007f );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate negative
// expected value is 0x8000000000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.x = R4.L;
A0.x = R4.L;
A1 += R0.L * R1.H, A0 += R0.L * R1.H;
R6 = A1.w;
_DBG ASTAT;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xff80 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with "-="
// expected value is 0x7fffffffff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
A1 -= R0.H * R1.L, A0 -= R0.H * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0x007f );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate negative with "-="
// expected value is 0x8000000000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.x = R4.L;
A0.x = R4.L;
A1 -= R0.L * R1.L, A0 -= R0.L * R1.L;
R6 = A1.w;
_DBG ASTAT;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0xff80 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x1 );
// 0x8000 * 0x8000 = 0xff80000001 with "-="
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 -= R0.H * R1.H, A0 -= R0.H * R1.H;
R6 = A1.w;
_DBG ASTAT;
R7.L = A1.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x7fff * 0x7fff = 0x007ffe0002 with "="
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.L * R1.L, A0 += R0.L * R1.L;
A1 = R0.L * R1.L, A0 = R0.L * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x7ffe );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x7fff * 0x7fff = 0x007ffe0002 with "NOP"
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.L * R1.L;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x7ffe );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// 0x8000 * 0x8000 = 0x007fffffff with "NOP"
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1 += R0.H * R1.H;
_DBG A1;
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
_DBG ASTAT;
R7.L = A0.x;
_DBG ASTAT;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
R7 = ASTAT; _dbg astat;
//AV1 AV1S should be 0.
DBGA ( R7.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
_DBG ASTAT;
A1 = A0 = 0;
_DBG A1;
_DBG R0; _DBG R1;
A1 += R0.L * R1.L; // make sure overflow flag is not set to zero
_DBG A1;
_DBG ASTAT;
R7 = ASTAT;
//AV1S should be 0.
DBGA ( R7.H, 0x0000 );
DBGA ( R7.L, 0x0000 );
pass
.data
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 13,148 | sim/testsuite/bfin/c_ldst_ld_d_p_ppmm_hbx.s | //Original:/testcases/core/c_ldst_ld_d_p_ppmm_hbx/c_ldst_ld_d_p_ppmm_hbx.dsp
// Spec Reference: c_ldst ld d [p++/--] h b xh xb
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = W [ P5 ++ ] (Z);
R1 = W [ P1 ++ ] (Z);
R2 = W [ P2 ++ ] (Z);
R4 = W [ P4 ++ ] (Z);
R5 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
R1 = W [ P5 ++ ] (Z);
R2 = W [ P1 ++ ] (Z);
R3 = W [ P2 ++ ] (Z);
R5 = W [ P4 ++ ] (Z);
R6 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00002021;
CHECKREG r3, 0x00004041;
CHECKREG r5, 0x00008081;
CHECKREG r6, 0x00000001;
R2 = W [ P5 ++ ] (Z);
R3 = W [ P1 ++ ] (Z);
R4 = W [ P2 ++ ] (Z);
R6 = W [ P4 ++ ] (Z);
R7 = W [ FP ++ ] (Z);
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00004647;
CHECKREG r6, 0x00008687;
CHECKREG r7, 0x00000607;
R3 = W [ P5 ++ ] (Z);
R4 = W [ P1 ++ ] (Z);
R5 = W [ P2 ++ ] (Z);
R7 = W [ P4 ++ ] (Z);
R0 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000405;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00002425;
CHECKREG r5, 0x00004445;
CHECKREG r7, 0x00008485;
R4 = W [ P5 ++ ] (X);
R5 = W [ P1 ++ ] (X);
R6 = W [ P2 ++ ] (X);
R0 = W [ P4 ++ ] (X);
R1 = W [ FP ++ ] (X);
CHECKREG r0, 0xFFFF8A8B;
CHECKREG r1, 0x00000A0B;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00002A2B;
CHECKREG r6, 0x00004A4B;
R5 = W [ P5 ++ ] (X);
R6 = W [ P1 ++ ] (X);
R7 = W [ P2 ++ ] (X);
R1 = W [ P4 ++ ] (X);
R2 = W [ FP ++ ] (X);
CHECKREG r1, 0xFFFF8889;
CHECKREG r2, 0x00000809;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00002829;
CHECKREG r7, 0x00004849;
R6 = W [ P5 ++ ] (X);
R7 = W [ P1 ++ ] (X);
R0 = W [ P2 ++ ] (X);
R2 = W [ P4 ++ ] (X);
R3 = W [ FP ++ ] (X);
CHECKREG r0, 0x00004E4F;
CHECKREG r2, 0xFFFF8E8F;
CHECKREG r3, 0x00000E0F;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00000E0F;
CHECKREG r7, 0x00002E2F;
R7 = W [ P5 ++ ] (X);
R0 = W [ P1 ++ ] (X);
R1 = W [ P2 ++ ] (X);
R3 = W [ P4 ++ ] (X);
R4 = W [ FP ++ ] (X);
CHECKREG r0, 0x00002C2D;
CHECKREG r1, 0x00004C4D;
CHECKREG r3, 0xFFFF8C8D;
CHECKREG r4, 0x00000C0D;
CHECKREG r6, 0x00000E0F;
CHECKREG r7, 0x00000C0D;
R0 = W [ P5 -- ] (Z);
R1 = W [ P1 -- ] (Z);
R2 = W [ P2 -- ] (Z);
R4 = W [ P4 -- ] (Z);
R5 = W [ FP -- ] (Z);
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00003233;
CHECKREG r2, 0x00005253;
CHECKREG r4, 0x00009293;
CHECKREG r5, 0x00001213;
R1 = W [ P5 -- ] (Z);
R2 = W [ P1 -- ] (Z);
R3 = W [ P2 -- ] (Z);
R5 = W [ P4 -- ] (Z);
R6 = W [ FP -- ] (Z);
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00000C0D;
CHECKREG r2, 0x00002C2D;
CHECKREG r3, 0x00004C4D;
CHECKREG r5, 0x00008C8D;
CHECKREG r6, 0x00000C0D;
R2 = W [ P5 -- ] (Z);
R3 = W [ P1 -- ] (Z);
R4 = W [ P2 -- ] (Z);
R6 = W [ P4 -- ] (Z);
R7 = W [ FP -- ] (Z);
CHECKREG r1, 0x00000C0D;
CHECKREG r2, 0x00000E0F;
CHECKREG r3, 0x00002E2F;
CHECKREG r4, 0x00004E4F;
CHECKREG r6, 0x00008E8F;
CHECKREG r7, 0x00000E0F;
R3 = W [ P5 -- ] (Z);
R4 = W [ P1 -- ] (Z);
R5 = W [ P2 -- ] (Z);
R7 = W [ P4 -- ] (Z);
R0 = W [ FP -- ] (Z);
CHECKREG r0, 0x00000809;
CHECKREG r2, 0x00000E0F;
CHECKREG r3, 0x00000809;
CHECKREG r4, 0x00002829;
CHECKREG r5, 0x00004849;
CHECKREG r7, 0x00008889;
R4 = W [ P5 -- ] (X);
R5 = W [ P1 -- ] (X);
R6 = W [ P2 -- ] (X);
R0 = W [ P4 -- ] (X);
R1 = W [ FP -- ] (X);
CHECKREG r0, 0xFFFF8A8B;
CHECKREG r1, 0x00000A0B;
CHECKREG r3, 0x00000809;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00002A2B;
CHECKREG r6, 0x00004A4B;
R5 = W [ P5 -- ] (X);
R6 = W [ P1 -- ] (X);
R7 = W [ P2 -- ] (X);
R1 = W [ P4 -- ] (X);
R2 = W [ FP -- ] (X);
CHECKREG r1, 0xFFFF8485;
CHECKREG r2, 0x00000405;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00002425;
CHECKREG r7, 0x00004445;
R6 = W [ P5 -- ] (X);
R7 = W [ P1 -- ] (X);
R0 = W [ P2 -- ] (X);
R2 = W [ P4 -- ] (X);
R3 = W [ FP -- ] (X);
CHECKREG r0, 0x00004647;
CHECKREG r2, 0xFFFF8687;
CHECKREG r3, 0x00000607;
CHECKREG r5, 0x00000405;
CHECKREG r6, 0x00000607;
CHECKREG r7, 0x00002627;
R7 = W [ P5 -- ] (X);
R0 = W [ P1 -- ] (X);
R1 = W [ P2 -- ] (X);
R3 = W [ P4 -- ] (X);
R4 = W [ FP -- ] (X);
CHECKREG r0, 0x00002021;
CHECKREG r1, 0x00004041;
CHECKREG r3, 0xFFFF8081;
CHECKREG r4, 0x00000001;
CHECKREG r6, 0x00000607;
CHECKREG r7, 0x00000001;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = B [ P5 ++ ] (Z);
R1 = B [ P1 ++ ] (Z);
R2 = B [ P2 ++ ] (Z);
R4 = B [ P4 ++ ] (Z);
R5 = B [ FP ++ ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
R1 = B [ P5 ++ ] (Z);
R2 = B [ P1 ++ ] (Z);
R3 = B [ P2 ++ ] (Z);
R5 = B [ P4 ++ ] (Z);
R6 = B [ FP ++ ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000042;
CHECKREG r5, 0x00000082;
CHECKREG r6, 0x00000002;
R2 = B [ P5 ++ ] (Z);
R3 = B [ P1 ++ ] (Z);
R4 = B [ P2 ++ ] (Z);
R6 = B [ P4 ++ ] (Z);
R7 = B [ FP ++ ] (Z);
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000041;
CHECKREG r6, 0x00000081;
CHECKREG r7, 0x00000001;
R3 = B [ P5 ++ ] (Z);
R4 = B [ P1 ++ ] (Z);
R5 = B [ P2 ++ ] (Z);
R7 = B [ P4 ++ ] (Z);
R0 = B [ FP ++ ] (Z);
CHECKREG r0, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000040;
CHECKREG r7, 0x00000080;
R4 = B [ P5 ++ ] (X);
R5 = B [ P1 ++ ] (X);
R6 = B [ P2 ++ ] (X);
R0 = B [ P4 ++ ] (X);
R1 = B [ FP ++ ] (X);
CHECKREG r0, 0xFFFFFF87;
CHECKREG r1, 0x00000007;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x00000047;
R5 = B [ P5 ++ ] (X);
R6 = B [ P1 ++ ] (X);
R7 = B [ P2 ++ ] (X);
R1 = B [ P4 ++ ] (X);
R2 = B [ FP ++ ] (X);
CHECKREG r1, 0xFFFFFF86;
CHECKREG r2, 0x00000006;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000026;
CHECKREG r7, 0x00000046;
R6 = B [ P5 ++ ] (X);
R7 = B [ P1 ++ ] (X);
R0 = B [ P2 ++ ] (X);
R2 = B [ P4 ++ ] (X);
R3 = B [ FP ++ ] (X);
CHECKREG r0, 0x00000045;
CHECKREG r2, 0xFFFFFF85;
CHECKREG r3, 0x00000005;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000025;
R7 = B [ P5 ++ ] (X);
R0 = B [ P1 ++ ] (X);
R1 = B [ P2 ++ ] (X);
R3 = B [ P4 ++ ] (X);
R4 = B [ FP ++ ] (X);
CHECKREG r0, 0x00000024;
CHECKREG r1, 0x00000044;
CHECKREG r3, 0xFFFFFF84;
CHECKREG r4, 0x00000004;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000004;
R0 = B [ P5 -- ] (Z);
R1 = B [ P1 -- ] (Z);
R2 = B [ P2 -- ] (Z);
R4 = B [ P4 -- ] (Z);
R5 = B [ FP -- ] (Z);
CHECKREG r0, 0x0000000B;
CHECKREG r1, 0x0000002B;
CHECKREG r2, 0x0000004B;
CHECKREG r4, 0x0000008B;
CHECKREG r5, 0x0000000B;
R1 = B [ P5 -- ] (Z);
R2 = B [ P1 -- ] (Z);
R3 = B [ P2 -- ] (Z);
R5 = B [ P4 -- ] (Z);
R6 = B [ FP -- ] (Z);
CHECKREG r0, 0x0000000B;
CHECKREG r1, 0x00000004;
CHECKREG r2, 0x00000024;
CHECKREG r3, 0x00000044;
CHECKREG r5, 0x00000084;
CHECKREG r6, 0x00000004;
R2 = B [ P5 -- ] (Z);
R3 = B [ P1 -- ] (Z);
R4 = B [ P2 -- ] (Z);
R6 = B [ P4 -- ] (Z);
R7 = B [ FP -- ] (Z);
CHECKREG r1, 0x00000004;
CHECKREG r2, 0x00000005;
CHECKREG r3, 0x00000025;
CHECKREG r4, 0x00000045;
CHECKREG r6, 0x00000085;
CHECKREG r7, 0x00000005;
R3 = B [ P5 -- ] (Z);
R4 = B [ P1 -- ] (Z);
R5 = B [ P2 -- ] (Z);
R7 = B [ P4 -- ] (Z);
R0 = B [ FP -- ] (Z);
CHECKREG r0, 0x00000006;
CHECKREG r2, 0x00000005;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000026;
CHECKREG r5, 0x00000046;
CHECKREG r7, 0x00000086;
R4 = B [ P5 -- ] (X);
R5 = B [ P1 -- ] (X);
R6 = B [ P2 -- ] (X);
R0 = B [ P4 -- ] (X);
R1 = B [ FP -- ] (X);
CHECKREG r0, 0xFFFFFF87;
CHECKREG r1, 0x00000007;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x00000047;
R5 = B [ P5 -- ] (X);
R6 = B [ P1 -- ] (X);
R7 = B [ P2 -- ] (X);
R1 = B [ P4 -- ] (X);
R2 = B [ FP -- ] (X);
CHECKREG r1, 0xFFFFFF80;
CHECKREG r2, 0x00000000;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000040;
R6 = B [ P5 -- ] (X);
R7 = B [ P1 -- ] (X);
R0 = B [ P2 -- ] (X);
R2 = B [ P4 -- ] (X);
R3 = B [ FP -- ] (X);
CHECKREG r0, 0x00000041;
CHECKREG r2, 0xFFFFFF81;
CHECKREG r3, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000021;
R7 = B [ P5 -- ] (X);
R0 = B [ P1 -- ] (X);
R1 = B [ P2 -- ] (X);
R3 = B [ P4 -- ] (X);
R4 = B [ FP -- ] (X);
CHECKREG r0, 0x00000022;
CHECKREG r1, 0x00000042;
CHECKREG r3, 0xFFFFFF82;
CHECKREG r4, 0x00000002;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000002;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,661 | sim/testsuite/bfin/c_loopsetup_preg_lc1.s | //Original:/testcases/core/c_loopsetup_preg_lc1/c_loopsetup_preg_lc1.dsp
// Spec Reference: loopsetup preg lc1
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P1 = 12;
P2 = 14;
P3 = 16;
P4 = 18;
P5 = 20;
SP = 22;
FP = 24;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start11 , end11 ) LC1 = P1;
start11: R0 += 1;
R1 += -1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start12 , end12 ) LC1 = P2;
start12: R4 += 1;
end12: R5 += -1;
R3 += 1;
LSETUP ( start13 , end13 ) LC1 = P3;
start13: R6 += 1;
end13: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000011;
CHECKREG r1, 0x00000004;
CHECKREG r2, 0x0000002C;
CHECKREG r3, 0x00000033;
CHECKREG r4, 0x0000004E;
CHECKREG r5, 0x00000042;
CHECKREG r6, 0x00000070;
CHECKREG r7, 0x00000060;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start14 , end14 ) LC1 = P4;
start14: R0 += 1;
R1 += -1;
end14: R2 += 1;
R3 += 1;
LSETUP ( start15 , end15 ) LC1 = P5;
start15: R4 += 1;
end15: R5 += -1;
R3 += 1;
LSETUP ( start16 , end16 ) LC1 = SP;
start16: R6 += 1;
end16: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000017;
CHECKREG r1, 0xFFFFFFFE;
CHECKREG r2, 0x00000032;
CHECKREG r3, 0x00000033;
CHECKREG r4, 0x00000054;
CHECKREG r5, 0x0000003c;
CHECKREG r6, 0x00000076;
CHECKREG r7, 0x0000005A;
LSETUP ( start17 , end17 ) LC1 = FP;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
CHECKREG r0, 0x00000017;
CHECKREG r1, 0xFFFFFFFE;
CHECKREG r2, 0x00000032;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x0000006c;
CHECKREG r5, 0x00000024;
CHECKREG r6, 0x00000076;
CHECKREG r7, 0x0000005A;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,438 | sim/testsuite/bfin/c_compi2opd_dr_add_i7_p.s | //Original:/testcases/core/c_compi2opd_dr_add_i7_p/c_compi2opd_dr_add_i7_p.dsp
// Spec Reference: compi2opd dregs += imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 += 0;
R1 += 1;
R2 += 2;
R3 += 3;
R4 += 4;
R5 += 5;
R6 += 6;
R7 += 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
R0 += 8;
R1 += 9;
R2 += 10;
R3 += 11;
R4 += 12;
R5 += 13;
R6 += 14;
R7 += 15;
CHECKREG r0, 0x00000008;
CHECKREG r1, 0x0000000A;
CHECKREG r2, 0x0000000C;
CHECKREG r3, 0x0000000E;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000012;
CHECKREG r6, 0x00000014;
CHECKREG r7, 0x00000016;
R0 += 16;
R1 += 17;
R2 += 18;
R3 += 19;
R4 += 20;
R5 += 21;
R6 += 22;
R7 += 23;
CHECKREG r0, 0x00000018;
CHECKREG r1, 0x0000001B;
CHECKREG r2, 0x0000001E;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000024;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x0000002A;
CHECKREG r7, 0x0000002D;
R0 += 24;
R1 += 25;
R2 += 26;
R3 += 27;
R4 += 28;
R5 += 29;
R6 += 30;
R7 += 31;
CHECKREG r0, 0x00000030;
CHECKREG r1, 0x00000034;
CHECKREG r2, 0x00000038;
CHECKREG r3, 0x0000003C;
CHECKREG r4, 0x00000040;
CHECKREG r5, 0x00000044;
CHECKREG r6, 0x00000048;
CHECKREG r7, 0x0000004C;
R0 += 32;
R1 += 33;
R2 += 34;
R3 += 35;
R4 += 36;
R5 += 37;
R6 += 38;
R7 += 39;
CHECKREG r0, 0x00000050;
CHECKREG r1, 0x00000055;
CHECKREG r2, 0x0000005A;
CHECKREG r3, 0x0000005F;
CHECKREG r4, 0x00000064;
CHECKREG r5, 0x00000069;
CHECKREG r6, 0x0000006E;
CHECKREG r7, 0x00000073;
R0 += 40;
R1 += 41;
R2 += 42;
R3 += 43;
R4 += 44;
R5 += 45;
R6 += 46;
R7 += 47;
CHECKREG r0, 0x00000078;
CHECKREG r1, 0x0000007E;
CHECKREG r2, 0x00000084;
CHECKREG r3, 0x0000008A;
CHECKREG r4, 0x00000090;
CHECKREG r5, 0x00000096;
CHECKREG r6, 0x0000009C;
CHECKREG r7, 0x000000A2;
R0 += 48;
R1 += 49;
R2 += 50;
R3 += 51;
R4 += 52;
R5 += 53;
R6 += 54;
R7 += 55;
CHECKREG r0, 0x000000A8;
CHECKREG r1, 0x000000AF;
CHECKREG r2, 0x000000B6;
CHECKREG r3, 0x000000BD;
CHECKREG r4, 0x000000C4;
CHECKREG r5, 0x000000CB;
CHECKREG r6, 0x000000D2;
CHECKREG r7, 0x000000D9;
R0 += 56;
R1 += 57;
R2 += 58;
R3 += 59;
R4 += 60;
R5 += 61;
R6 += 62;
R7 += 63;
CHECKREG r0, 0x000000E0;
CHECKREG r1, 0x000000E8;
CHECKREG r2, 0x000000F0;
CHECKREG r3, 0x000000F8;
CHECKREG r4, 0x00000100;
CHECKREG r5, 0x00000108;
CHECKREG r6, 0x00000110;
CHECKREG r7, 0x00000118;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,312 | sim/testsuite/bfin/random_0018.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x40204090 | _AV1S | _AV0S | _AV0 | _AQ | _AN | _AZ);
imm32 R1, 0x33e91405;
imm32 R4, 0x3fa1377c;
R4.H = R1.H >>> 0x1d;
checkreg R4, 0x9f48377c;
checkreg ASTAT, (0x40204090 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x64800010 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
imm32 R0, 0xf64722bc;
R0.L = R0.L >>> 0xd (S);
checkreg R0, 0xf6470001;
checkreg ASTAT, (0x64800010 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x70300e10 | _VS | _AQ | _AC0_COPY | _AN);
imm32 R5, 0x2a8771ff;
R5 = R5 >>> 0x1d (V);
checkreg R5, 0x54388ff8;
checkreg ASTAT, (0x70300e10 | _VS | _V | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x04600000 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R6, 0x0c3a7fff;
imm32 R7, 0x03460f23;
R6.H = R7.L >>> 0x1f (S);
checkreg R6, 0x1e467fff;
checkreg ASTAT, (0x04600000 | _VS | _AV1S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x40704010 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R3, 0xfa2cee19;
imm32 R5, 0xfa2cee17;
R3.L = R5.H >>> 0xd (S);
checkreg R3, 0xfa2cffff;
checkreg ASTAT, (0x40704010 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 ASTAT, (0x20308c90 | _VS | _AV1S | _AV0S | _CC | _AN);
imm32 R2, 0xd4b70c2f;
imm32 R5, 0x0279838b;
R5.H = R2.H >>> 0x1f (S);
checkreg R5, 0xa96e838b;
checkreg ASTAT, (0x20308c90 | _VS | _AV1S | _AV0S | _CC | _AN);
dmm32 ASTAT, (0x10a08690 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R4, 0x5cae64fc;
imm32 R6, 0x288e1461;
R4.H = R6.L >>> 0x1e (S);
checkreg R4, 0x518464fc;
checkreg ASTAT, (0x10a08690 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x48908010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC);
imm32 R1, 0x4f8f004a;
imm32 R5, 0x7fff70c1;
R5.L = R1.L >>> 0x1e (S);
checkreg R5, 0x7fff0128;
checkreg ASTAT, (0x48908010 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 ASTAT, (0x00f00490 | _VS | _AV0S | _AV0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0x32b127c8;
dmm32 A0.x, 0x0000001a;
A0 = A0 >>> 0x6;
checkreg A0.w, 0x68cac49f;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x00f00490 | _VS | _AV0S | _AQ | _CC | _AC0_COPY);
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,080 | sim/testsuite/bfin/cec-snen-reti.S | # Blackfin testcase for having RETI LSB set correctly when self nested
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set our handler
imm32 P5, EVT11;
loadsym R1, _ivg11;
[P5] = R1;
loadsym R1, _fail_lvl;
[P5 + 4] = R1; /* IVG12 */
[P5 + 12] = R1; /* IVG14 */
loadsym R1, _ivg13;
[P5 + 8] = R1;
# Enable self nesting
R2 = SYSCFG;
BITSET (R2, 2);
SYSCFG = R2;
CSYNC;
# Enable IVG11/IVG13/IVG14 but not IVG12
cli R3;
BITSET (R3, 11);
BITCLR (R3, 12);
BITSET (R3, 13);
BITSET (R3, 14);
sti R3;
# Counter to keep track of nesting depth
R7 = 0;
# Lower ourselves to IVG11
loadsym R4, _fail_lvl;
RETI = R4;
RAISE 11;
RAISE 12;
RAISE 13;
RAISE 14;
RTI;
# This IVG makes sure RETI LSB is set correctly on transition in (RAISE)
_ivg11:
R0 = RETI;
# Make sure we are indeed at IVG11
imm32 P0, IPEND;
R1 = [P0];
CC = BITTST (R1, 11);
IF !CC JUMP _fail_lvl;
# Make sure LSB of RETI is set only on first pass
CC = ! BITTST (R0, 0);
R1 = CC;
CC = R7 == 0;
R2 = CC;
CC = R1 == R2;
IF !CC JUMP _fail_lvl;
# Nest ourselves a few times
R6 = 3;
CC = R7 < R6;
IF !CC JUMP 1f;
[--sp] = RETI;
R7 += 1;
RAISE 11;
MNOP;
JUMP _fail_lvl;
# Move down to IVG13 for next test
1: loadsym R4, _fail_lvl;
RETI = R4;
RTI;
# This IVG makes sure RETI LSB is respected on transition out (RTI)
_ivg13:
R0 = RETI;
# Make sure we are indeed at IVG13
imm32 P0, IPEND;
R1 = [P0];
CC = BITTST (R1, 13);
IF !CC JUMP _fail_lvl;
# RETI LSB should be set when re-entering IVG13
CC = ! BITTST (R0, 0);
R1 = CC;
CC = R7 == R6;
R2 = CC;
CC = R1 == R2;
IF !CC JUMP _fail_lvl;
# Should get here only after a few IVG11 tests
CC = R7 < R6;
IF CC JUMP _fail_lvl;
# Make sure IVG13 isn't pending
imm32 P0, ILAT;
R1 = [P0];
CC = BITTST (R1, 13);
IF CC JUMP _fail_lvl;
# Manually set RETI to with LSB set so we return there
R5 = R6;
R5 += 3;
CC = R7 < R5;
IF !CC JUMP 1f;
loadsym R1, _ivg13;
BITSET (R1, 0);
RETI = R1;
R7 += 1;
RTI;
# All done!
1: dbg_pass
_fail_lvl:
dbg_fail;
|
tactcomplabs/xbgas-binutils-gdb | 3,100 | sim/testsuite/bfin/a5.s | // ALU test program.
// Test instructions
// rL4= L+L (r2,r3);
// rH4= L+H (r2,r3) S;
// rL4= L-L (r2,r3);
// rH4= L-H (r2,r3) S;
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// overflow positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.L = R0.H + R1.L (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative
R0.L = 0xffff;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x8000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L + R1.H (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.L = R0.H + R1.L (S);
DBGA ( R3.L , 0x7fff );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative
R0.L = 0xffff;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x8000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.L = R0.L + R1.H (S);
DBGA ( R3.L , 0x8000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// overflow positive with subtraction
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.L = R0.H - R1.L (NS);
DBGA ( R3.L , 0x8000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative with subtraction
R0.L = 0x8000;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0001;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L - R1.H (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with subtraction
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.H = R0.H - R1.L (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative with subtraction
R0.L = 0x8000;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0001;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L - R1.H (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,129 | sim/testsuite/bfin/c_ldstpmod_st_dr_hi.s | //Original:testcases/core/c_ldstpmod_st_dr_hi/c_ldstpmod_st_dr_hi.dsp
// Spec Reference: c_ldstpmod store dreg hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm32 r2, 0x800d7002;
imm32 r3, 0x900c8003;
imm32 r4, 0xa00b9004;
imm32 r5, 0xb00aa005;
imm32 r6, 0xc009b006;
imm32 r7, 0xd008c007;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x08;
loadsym fp, DATA_ADDR_6, 0x0a;
loadsym i3, DATA_ADDR_7, 0x0c;
P3 = I1; SP = I3;
W [ P1 ] = R1.H;
W [ P2 ] = R2.H;
W [ P3 ] = R3.H;
W [ P4 ] = R4.H;
W [ P5 ] = R5.H;
W [ SP ] = R6.H;
W [ FP ] = R0.H;
R6.H = W [ P1 ];
R5.H = W [ P2 ];
R4.H = W [ P3 ];
R3.H = W [ P4 ];
R2.H = W [ P5 ];
R0.H = W [ SP ];
R1.H = W [ FP ];
CHECKREG r0, 0xC0095000;
CHECKREG r1, 0x600F6001;
CHECKREG r2, 0xB00A7002;
CHECKREG r3, 0xA00B8003;
CHECKREG r4, 0x900C9004;
CHECKREG r5, 0x800DA005;
CHECKREG r6, 0x700EB006;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x0c;
loadsym p2, DATA_ADDR_2, 0x0a;
loadsym i1, DATA_ADDR_3, 0x08;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x02;
loadsym i3, DATA_ADDR_7, 0x00;
P3 = I1; SP = I3;
W [ P1 ] = R2.H;
W [ P2 ] = R3.H;
W [ P3 ] = R4.H;
W [ P4 ] = R5.H;
W [ P5 ] = R6.H;
W [ SP ] = R7.H;
W [ FP ] = R1.H;
R1.L = W [ P1 ];
R2.L = W [ P2 ];
R3.L = W [ P3 ];
R4.L = W [ P4 ];
R5.L = W [ P5 ];
R6.L = W [ SP ];
R0.L = W [ FP ];
CHECKREG r0, 0x105F204E;
CHECKREG r1, 0x204E3003;
CHECKREG r2, 0x3003402C;
CHECKREG r3, 0x402C501B;
CHECKREG r4, 0x501B600A;
CHECKREG r5, 0x600A7019;
CHECKREG r6, 0x7019D028;
// initial values
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x12345675;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x10;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x00;
loadsym p4, DATA_ADDR_4, 0x08;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x06;
loadsym i3, DATA_ADDR_7, 0x02;
P3 = I1; SP = I3;
W [ P1 ] = R5.H;
W [ P2 ] = R6.H;
W [ P3 ] = R7.H;
W [ P4 ] = R0.H;
W [ P5 ] = R1.H;
W [ SP ] = R2.H;
W [ FP ] = R3.H;
R5.H = W [ P1 ];
R4.H = W [ P2 ];
R3.H = W [ P3 ];
R2.H = W [ P4 ];
R1.H = W [ P5 ];
R0.H = W [ SP ];
R6.H = W [ FP ];
CHECKREG r0, 0x30BD50B0;
CHECKREG r1, 0x20BE60B1;
CHECKREG r2, 0x10BF70B2;
CHECKREG r3, 0x80B880B3;
CHECKREG r4, 0x70B990B4;
CHECKREG r5, 0x12345675;
CHECKREG r6, 0x40BCB0B6;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 7,994 | sim/testsuite/bfin/c_comp3op_dr_plus_dr.s | //Original:/testcases/core/c_comp3op_dr_plus_dr/c_comp3op_dr_plus_dr.dsp
// Spec Reference: comp3op dregs + dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 + R0;
R1 = R0 + R1;
R2 = R0 + R2;
R3 = R0 + R3;
R4 = R0 + R4;
R5 = R0 + R5;
R6 = R0 + R6;
R7 = R0 + R7;
CHECKREG r0, 0x02468ACE;
CHECKREG r1, 0x8BF258BD;
CHECKREG r2, 0x58BF258A;
CHECKREG r3, 0xE1369D02;
CHECKREG r4, 0x258BF367;
CHECKREG r5, 0x7AD7AE13;
CHECKREG r6, 0x9ABCDF00;
CHECKREG r7, 0x147AE146;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 + R0;
R1 = R1 + R1;
R2 = R1 + R2;
R3 = R1 + R3;
R4 = R1 + R4;
R5 = R1 + R5;
R6 = R1 + R6;
R7 = R1 + R7;
CHECKREG r0, 0x8ACE3356;
CHECKREG r1, 0x13563BDE;
CHECKREG r2, 0x69CE569A;
CHECKREG r3, 0xF2464E12;
CHECKREG r4, 0x369B5477;
CHECKREG r5, 0x8BE74F23;
CHECKREG r6, 0xABCC5010;
CHECKREG r7, 0x258A5256;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 + R0;
R1 = R2 + R1;
R2 = R2 + R2;
R3 = R2 + R3;
R4 = R2 + R4;
R5 = R2 + R5;
R6 = R2 + R6;
R7 = R2 + R7;
CHECKREG r0, 0x579BDF53;
CHECKREG r1, 0xE024675B;
CHECKREG r2, 0xACF13458;
CHECKREG r3, 0x8BE1467C;
CHECKREG r4, 0xD0369C81;
CHECKREG r5, 0x2582577D;
CHECKREG r6, 0x4567887A;
CHECKREG r7, 0xBF258A80;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 + R0;
R1 = R3 + R1;
R2 = R3 + R2;
R3 = R3 + R3;
R4 = R3 + R4;
R5 = R3 + R5;
R6 = R3 + R6;
R7 = R3 + R7;
CHECKREG r0, 0xE0135796;
CHECKREG r1, 0x689BE016;
CHECKREG r2, 0x3568ACE6;
CHECKREG r3, 0xBDE02466;
CHECKREG r4, 0xE1258CF9;
CHECKREG r5, 0x367147A9;
CHECKREG r6, 0x56567899;
CHECKREG r7, 0xD0147AD9;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 + R0;
R1 = R4 + R1;
R2 = R4 + R2;
R3 = R4 + R3;
R4 = R4 + R4;
R5 = R4 + R5;
R6 = R4 + R6;
R7 = R4 + R7;
CHECKREG r0, 0x8468AE00;
CHECKREG r1, 0x8CF13688;
CHECKREG r2, 0x89BE0355;
CHECKREG r3, 0x92357ACD;
CHECKREG r4, 0x868AD132;
CHECKREG r5, 0xCF1BF477;
CHECKREG r6, 0xCF012564;
CHECKREG r7, 0xC8BF27AA;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 + R0;
R1 = R5 + R1;
R2 = R5 + R2;
R3 = R5 + R3;
R4 = R5 + R4;
R5 = R5 + R5;
R6 = R5 + R6;
R7 = R5 + R7;
CHECKREG r0, 0x7AB468AC;
CHECKREG r1, 0xFB3CF134;
CHECKREG r2, 0xCB09BE01;
CHECKREG r3, 0x4B813579;
CHECKREG r4, 0x9AD68BDE;
CHECKREG r5, 0xEB22468A;
CHECKREG r6, 0x80989ABC;
CHECKREG r7, 0x00569D02;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 + R0;
R1 = R6 + R1;
R2 = R6 + R2;
R3 = R6 + R3;
R4 = R6 + R4;
R5 = R6 + R5;
R6 = R6 + R6;
R7 = R6 + R7;
CHECKREG r0, 0x999C9999;
CHECKREG r1, 0x221D2221;
CHECKREG r2, 0xEEECEEEE;
CHECKREG r3, 0x776C6666;
CHECKREG r4, 0xBBBCBCCB;
CHECKREG r5, 0x110C7777;
CHECKREG r6, 0x30ECA864;
CHECKREG r7, 0x4322FEDC;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 + R0;
R1 = R7 + R1;
R2 = R7 + R2;
R3 = R7 + R3;
R4 = R7 + R4;
R5 = R7 + R5;
R6 = R7 + R6;
R7 = R7 + R7;
CHECKREG r0, 0x1357CBDF;
CHECKREG r1, 0x9BDFD467;
CHECKREG r2, 0x68ACD134;
CHECKREG r3, 0xF124C8AC;
CHECKREG r4, 0x3579CF11;
CHECKREG r5, 0x8AC5C9BD;
CHECKREG r6, 0xAAAACAAA;
CHECKREG r7, 0x2468ACF0;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 + R0;
R1 = R2 + R0;
R2 = R3 + R0;
R3 = R4 + R0;
R4 = R5 + R0;
R5 = R6 + R0;
R6 = R7 + R0;
R7 = R0 + R0;
CHECKREG r0, 0x92CF1356;
CHECKREG r1, 0xE8E7AE12;
CHECKREG r2, 0x71C0258A;
CHECKREG r3, 0xB6142BEF;
CHECKREG r4, 0x0B60349B;
CHECKREG r5, 0x2B456768;
CHECKREG r6, 0xA50369C7;
CHECKREG r7, 0x259E26AC;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 + R1;
R1 = R3 + R1;
R2 = R4 + R1;
R3 = R5 + R1;
R4 = R6 + R1;
R5 = R7 + R1;
R6 = R0 + R1;
R7 = R1 + R1;
CHECKREG r0, 0x7C2338AB;
CHECKREG r1, 0x07CB3023;
CHECKREG r2, 0x2B0D48BC;
CHECKREG r3, 0x805C5368;
CHECKREG r4, 0xA0414255;
CHECKREG r5, 0x19FF464B;
CHECKREG r6, 0x83EE68CE;
CHECKREG r7, 0x0F966046;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R3 + R2;
R1 = R4 + R2;
R2 = R5 + R2;
R3 = R6 + R2;
R4 = R7 + R2;
R5 = R0 + R2;
R6 = R1 + R2;
R7 = R2 + R2;
CHECKREG r0, 0x9563CC50;
CHECKREG r1, 0x79B8FD55;
CHECKREG r2, 0xCEA4BD61;
CHECKREG r3, 0x67181184;
CHECKREG r4, 0xE0D8F389;
CHECKREG r5, 0x640889B1;
CHECKREG r6, 0x485DBAB6;
CHECKREG r7, 0x9D497AC2;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R4 + R3;
R1 = R5 + R3;
R2 = R6 + R3;
R3 = R7 + R3;
R4 = R0 + R3;
R5 = R1 + R3;
R6 = R2 + R3;
R7 = R3 + R3;
CHECKREG r0, 0x7335A6C6;
CHECKREG r1, 0xC7316577;
CHECKREG r2, 0xE7649667;
CHECKREG r3, 0x612488A6;
CHECKREG r4, 0xD45A2F6C;
CHECKREG r5, 0x2855EE1D;
CHECKREG r6, 0x48891F0D;
CHECKREG r7, 0xC249114C;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R5 + R4;
R1 = R6 + R4;
R2 = R7 + R4;
R3 = R0 + R4;
R4 = R1 + R4;
R5 = R2 + R4;
R6 = R3 + R4;
R7 = R4 + R4;
CHECKREG r0, 0x98D68BDE;
CHECKREG r1, 0x9B9BBCCB;
CHECKREG r2, 0x957ABF11;
CHECKREG r3, 0xEC1BF477;
CHECKREG r4, 0xEEE12564;
CHECKREG r5, 0x845BE475;
CHECKREG r6, 0xDAFD19DB;
CHECKREG r7, 0xDDC24AC8;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R6 + R5;
R1 = R7 + R5;
R2 = R0 + R5;
R3 = R1 + R5;
R4 = R2 + R5;
R5 = R3 + R5;
R6 = R4 + R5;
R7 = R5 + R5;
CHECKREG r0, 0x0B0C8777;
CHECKREG r1, 0x8ACA79BD;
CHECKREG r2, 0x80A2AABC;
CHECKREG r3, 0x00609D02;
CHECKREG r4, 0xF638CE01;
CHECKREG r5, 0x75F6C047;
CHECKREG r6, 0x6C2F8E48;
CHECKREG r7, 0xEBED808E;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 + R6;
R1 = R0 + R6;
R2 = R1 + R6;
R3 = R2 + R6;
R4 = R3 + R6;
R5 = R4 + R6;
R6 = R5 + R6;
R7 = R6 + R6;
CHECKREG r0, 0xAAADAAAA;
CHECKREG r1, 0x4323FEDC;
CHECKREG r2, 0xDB9A530E;
CHECKREG r3, 0x7410A740;
CHECKREG r4, 0x0C86FB72;
CHECKREG r5, 0xA4FD4FA4;
CHECKREG r6, 0x3D73A3D6;
CHECKREG r7, 0x7AE747AC;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 + R7;
R1 = R2 + R7;
R2 = R3 + R7;
R3 = R4 + R7;
R4 = R5 + R7;
R5 = R6 + R7;
R6 = R7 + R7;
R7 = R0 + R7;
CHECKREG r0, 0x9ADFFF67;
CHECKREG r1, 0x68BD0104;
CHECKREG r2, 0xA12CF8B0;
CHECKREG r3, 0x3A7A0F11;
CHECKREG r4, 0x8AB5FEBD;
CHECKREG r5, 0xAAACFAFA;
CHECKREG r6, 0x24690CF0;
CHECKREG r7, 0xAD1485DF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 23,117 | sim/testsuite/bfin/se_undefinedinstruction4.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction4/se_undefinedinstruction4.dsp
// Description: 64 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// Starting 64bit section COUNT = 6406
.dw 0xCF00 ;
.dw 0xFA4D ;
.dw 0x4973 ;
.dw 0x434D ;
.dw 0xCF01 ;
.dw 0x3CAF ;
.dw 0xE7F7 ;
.dw 0xACAD ;
.dw 0xCF02 ;
.dw 0xC9A3 ;
.dw 0x705D ;
.dw 0x8EFF ;
.dw 0xCF03 ;
.dw 0x242D ;
.dw 0x26ED ;
.dw 0x1C67 ;
.dw 0xCF04 ;
.dw 0xBC83 ;
.dw 0x18BB ;
.dw 0xEF95 ;
.dw 0xCF05 ;
.dw 0xDFA7 ;
.dw 0x6AD9 ;
.dw 0x7FEF ;
.dw 0xCF06 ;
.dw 0x71F3 ;
.dw 0x19CB ;
.dw 0x1F69 ;
.dw 0xCF07 ;
.dw 0xA117 ;
.dw 0x23ED ;
.dw 0xE509 ;
.dw 0xCF08 ;
.dw 0x4DF9 ;
.dw 0x31C3 ;
.dw 0x5207 ;
.dw 0xCF09 ;
.dw 0xF35D ;
.dw 0x998F ;
.dw 0xC1A7 ;
.dw 0xCF0A ;
.dw 0xA7FF ;
.dw 0x73D ;
.dw 0x4ACB ;
.dw 0xCF0B ;
.dw 0xEE29 ;
.dw 0xAAE7 ;
.dw 0x3FD3 ;
.dw 0xCF0C ;
.dw 0xD3B5 ;
.dw 0x5549 ;
.dw 0xBCB7 ;
.dw 0xCF0D ;
.dw 0xF0B7 ;
.dw 0xB91B ;
.dw 0xC01F ;
.dw 0xCF0E ;
.dw 0xC169 ;
.dw 0x3D1F ;
.dw 0xB96B ;
.dw 0xCF0F ;
.dw 0x7CD3 ;
.dw 0xFD95 ;
.dw 0x2EA1 ;
.dw 0xCF10 ;
.dw 0x8907 ;
.dw 0x6013 ;
.dw 0x467D ;
.dw 0xCF11 ;
.dw 0x7F67 ;
.dw 0xFC1F ;
.dw 0x6611 ;
.dw 0xCF12 ;
.dw 0x1BB3 ;
.dw 0xCFE1 ;
.dw 0xF609 ;
.dw 0xCF13 ;
.dw 0x6AF1 ;
.dw 0xC229 ;
.dw 0x8009 ;
.dw 0xCF14 ;
.dw 0xF619 ;
.dw 0xF2C9 ;
.dw 0xF8C7 ;
.dw 0xCF15 ;
.dw 0xE413 ;
.dw 0x99F3 ;
.dw 0x7919 ;
.dw 0xCF16 ;
.dw 0x5E8B ;
.dw 0xCA1 ;
.dw 0xED71 ;
.dw 0xCF17 ;
.dw 0x3FBB ;
.dw 0x221B ;
.dw 0xDA89 ;
.dw 0xCF18 ;
.dw 0xDFED ;
.dw 0x1565 ;
.dw 0x12DB ;
.dw 0xCF19 ;
.dw 0x95FD ;
.dw 0xB71F ;
.dw 0xB9B ;
.dw 0xCF1A ;
.dw 0xAB8F ;
.dw 0xC14F ;
.dw 0xD777 ;
.dw 0xCF1B ;
.dw 0x9427 ;
.dw 0x2E69 ;
.dw 0x5F23 ;
.dw 0xCF1C ;
.dw 0xB9F1 ;
.dw 0xFE17 ;
.dw 0x6AA1 ;
.dw 0xCF1D ;
.dw 0x642B ;
.dw 0x676B ;
.dw 0xCA2B ;
.dw 0xCF1E ;
.dw 0x4399 ;
.dw 0x8C55 ;
.dw 0x5187 ;
.dw 0xCF1F ;
.dw 0xCED5 ;
.dw 0x9163 ;
.dw 0x4B95 ;
.dw 0xCF20 ;
.dw 0xE0F9 ;
.dw 0xA3AF ;
.dw 0x72EB ;
.dw 0xCF21 ;
.dw 0x120B ;
.dw 0x9161 ;
.dw 0x4C73 ;
.dw 0xCF22 ;
.dw 0xA97F ;
.dw 0x9BC3 ;
.dw 0xF2A9 ;
.dw 0xCF23 ;
.dw 0x9B6F ;
.dw 0x15F5 ;
.dw 0x83F3 ;
.dw 0xCF24 ;
.dw 0x67D3 ;
.dw 0x4385 ;
.dw 0xEF37 ;
.dw 0xCF25 ;
.dw 0xD3A3 ;
.dw 0xFB5B ;
.dw 0x119D ;
.dw 0xCF26 ;
.dw 0xCA67 ;
.dw 0xC3F5 ;
.dw 0x2109 ;
.dw 0xCF27 ;
.dw 0x459B ;
.dw 0xC69 ;
.dw 0x6BD3 ;
.dw 0xCF28 ;
.dw 0xBD4B ;
.dw 0x82E1 ;
.dw 0xDD07 ;
.dw 0xCF29 ;
.dw 0x9131 ;
.dw 0x4A0B ;
.dw 0x503B ;
.dw 0xCF2A ;
.dw 0x3383 ;
.dw 0x55B5 ;
.dw 0x7107 ;
.dw 0xCF2B ;
.dw 0x9F5D ;
.dw 0x14B3 ;
.dw 0xF6FF ;
.dw 0xCF2C ;
.dw 0xF3B1 ;
.dw 0x53DF ;
.dw 0x9A93 ;
.dw 0xCF2D ;
.dw 0x5A59 ;
.dw 0x3879 ;
.dw 0x41AD ;
.dw 0xCF2E ;
.dw 0xDD63 ;
.dw 0x9BEF ;
.dw 0x55B3 ;
.dw 0xCF2F ;
.dw 0x9B01 ;
.dw 0x563D ;
.dw 0x598B ;
.dw 0xCF30 ;
.dw 0xF1E3 ;
.dw 0x45E1 ;
.dw 0xD327 ;
.dw 0xCF31 ;
.dw 0xF0C7 ;
.dw 0xD19D ;
.dw 0x110D ;
.dw 0xCF32 ;
.dw 0x94B7 ;
.dw 0x68CF ;
.dw 0x6ADB ;
.dw 0xCF33 ;
.dw 0x4083 ;
.dw 0xAD23 ;
.dw 0x3F8B ;
.dw 0xCF34 ;
.dw 0x55D3 ;
.dw 0x6969 ;
.dw 0x38D9 ;
.dw 0xCF35 ;
.dw 0xD261 ;
.dw 0xF353 ;
.dw 0x1595 ;
.dw 0xCF36 ;
.dw 0x8897 ;
.dw 0x9A6D ;
.dw 0x2093 ;
.dw 0xCF37 ;
.dw 0x2673 ;
.dw 0xD509 ;
.dw 0xF435 ;
.dw 0xCF38 ;
.dw 0x5093 ;
.dw 0x6F8F ;
.dw 0x93D9 ;
.dw 0xCF39 ;
.dw 0xAAE1 ;
.dw 0xE2F1 ;
.dw 0x807F ;
.dw 0xCF3A ;
.dw 0x64D ;
.dw 0xFEF7 ;
.dw 0x103D ;
.dw 0xCF3B ;
.dw 0x1665 ;
.dw 0x1959 ;
.dw 0x608F ;
.dw 0xCF3C ;
.dw 0x43D9 ;
.dw 0x2CDD ;
.dw 0x2F3F ;
.dw 0xCF3D ;
.dw 0x950B ;
.dw 0x3B49 ;
.dw 0x2681 ;
.dw 0xCF3E ;
.dw 0xEA9D ;
.dw 0x8053 ;
.dw 0xC311 ;
.dw 0xCF3F ;
.dw 0x4D3 ;
.dw 0x9311 ;
.dw 0x498B ;
.dw 0xCF40 ;
.dw 0x6909 ;
.dw 0x27C3 ;
.dw 0x2B45 ;
.dw 0xCF41 ;
.dw 0x1347 ;
.dw 0xFC37 ;
.dw 0x8C9D ;
.dw 0xCF42 ;
.dw 0xD08F ;
.dw 0xFF4B ;
.dw 0x3223 ;
.dw 0xCF43 ;
.dw 0x485 ;
.dw 0x7C05 ;
.dw 0xB5BB ;
.dw 0xCF44 ;
.dw 0x49BB ;
.dw 0x5A71 ;
.dw 0xBD1B ;
.dw 0xCF45 ;
.dw 0x27D9 ;
.dw 0x39B ;
.dw 0xE099 ;
.dw 0xCF46 ;
.dw 0x85AF ;
.dw 0xC637 ;
.dw 0xC7EF ;
.dw 0xCF47 ;
.dw 0x5D7B ;
.dw 0x9FAF ;
.dw 0xE277 ;
.dw 0xCF48 ;
.dw 0x51C9 ;
.dw 0xD04B ;
.dw 0xE427 ;
.dw 0xCF49 ;
.dw 0x747B ;
.dw 0xB7F5 ;
.dw 0x4E5 ;
.dw 0xCF4A ;
.dw 0xCBDF ;
.dw 0xFB21 ;
.dw 0x2B5B ;
.dw 0xCF4B ;
.dw 0x6F59 ;
.dw 0x716D ;
.dw 0xB07B ;
.dw 0xCF4C ;
.dw 0x42CB ;
.dw 0x46CB ;
.dw 0x9CD5 ;
.dw 0xCF4D ;
.dw 0xC98B ;
.dw 0x2C5D ;
.dw 0x57FF ;
.dw 0xCF4E ;
.dw 0xF097 ;
.dw 0xF96D ;
.dw 0x9C45 ;
.dw 0xCF4F ;
.dw 0x8743 ;
.dw 0xD053 ;
.dw 0xF01F ;
.dw 0xCF50 ;
.dw 0xD12D ;
.dw 0x79ED ;
.dw 0x18D7 ;
.dw 0xCF51 ;
.dw 0xCB3 ;
.dw 0x860F ;
.dw 0x5F57 ;
.dw 0xCF52 ;
.dw 0x41B7 ;
.dw 0xFB03 ;
.dw 0x2985 ;
.dw 0xCF53 ;
.dw 0x514F ;
.dw 0x6F ;
.dw 0x74F1 ;
.dw 0xCF54 ;
.dw 0x32AF ;
.dw 0x4413 ;
.dw 0x4F1 ;
.dw 0xCF55 ;
.dw 0xDF13 ;
.dw 0xEB77 ;
.dw 0xFDC7 ;
.dw 0xCF56 ;
.dw 0xE7BF ;
.dw 0xF8FB ;
.dw 0x8881 ;
.dw 0xCF57 ;
.dw 0xD71 ;
.dw 0xE18B ;
.dw 0x58E1 ;
.dw 0xCF58 ;
.dw 0xE66B ;
.dw 0x396B ;
.dw 0x6441 ;
.dw 0xCF59 ;
.dw 0xEAE5 ;
.dw 0xC4B9 ;
.dw 0x5D65 ;
.dw 0xCF5A ;
.dw 0x2DA9 ;
.dw 0x2BBB ;
.dw 0xD621 ;
.dw 0xCF5B ;
.dw 0x2FD1 ;
.dw 0xEB81 ;
.dw 0x56F3 ;
.dw 0xCF5C ;
.dw 0x7E67 ;
.dw 0xE6E1 ;
.dw 0x907 ;
.dw 0xCF5D ;
.dw 0x40A3 ;
.dw 0x95B3 ;
.dw 0x3501 ;
.dw 0xCF5E ;
.dw 0xBE25 ;
.dw 0x12A5 ;
.dw 0x96D ;
.dw 0xCF5F ;
.dw 0x94C9 ;
.dw 0xF7F7 ;
.dw 0xA553 ;
.dw 0xCF60 ;
.dw 0xB291 ;
.dw 0x5C7D ;
.dw 0x32ED ;
.dw 0xCF61 ;
.dw 0xABB5 ;
.dw 0x3987 ;
.dw 0x90FB ;
.dw 0xCF62 ;
.dw 0xDE61 ;
.dw 0x6B43 ;
.dw 0x5F83 ;
.dw 0xCF63 ;
.dw 0xF03D ;
.dw 0x61AF ;
.dw 0x3713 ;
.dw 0xCF64 ;
.dw 0x854D ;
.dw 0x2B4B ;
.dw 0x5ACB ;
.dw 0xCF65 ;
.dw 0x669B ;
.dw 0xC7A9 ;
.dw 0xC7B5 ;
.dw 0xCF66 ;
.dw 0x2E5D ;
.dw 0xFFE5 ;
.dw 0x8929 ;
.dw 0xCF67 ;
.dw 0xA089 ;
.dw 0x8151 ;
.dw 0xCD41 ;
.dw 0xCF68 ;
.dw 0xC17F ;
.dw 0x7ECF ;
.dw 0xB3F9 ;
.dw 0xCF69 ;
.dw 0x1689 ;
.dw 0xEA61 ;
.dw 0xC17B ;
.dw 0xCF6A ;
.dw 0xF6A1 ;
.dw 0xB5D1 ;
.dw 0xE1D5 ;
.dw 0xCF6B ;
.dw 0x8CEB ;
.dw 0xFA5 ;
.dw 0xBF9B ;
.dw 0xCF6C ;
.dw 0x9A11 ;
.dw 0x79DB ;
.dw 0x6B09 ;
.dw 0xCF6D ;
.dw 0x769B ;
.dw 0xEED1 ;
.dw 0x3BE3 ;
.dw 0xCF6E ;
.dw 0x8B95 ;
.dw 0xC2E9 ;
.dw 0x782D ;
.dw 0xCF6F ;
.dw 0x3763 ;
.dw 0x756B ;
.dw 0xE4B1 ;
.dw 0xCF70 ;
.dw 0xB2F5 ;
.dw 0x7F09 ;
.dw 0x2A1B ;
.dw 0xCF71 ;
.dw 0x9A79 ;
.dw 0x5685 ;
.dw 0x30BF ;
.dw 0xCF72 ;
.dw 0xCE41 ;
.dw 0x72D1 ;
.dw 0x301B ;
.dw 0xCF73 ;
.dw 0xAA27 ;
.dw 0x909B ;
.dw 0x818D ;
.dw 0xCF74 ;
.dw 0x5BB9 ;
.dw 0x8C95 ;
.dw 0xEA9F ;
.dw 0xCF75 ;
.dw 0x3079 ;
.dw 0x3273 ;
.dw 0x87F ;
.dw 0xCF76 ;
.dw 0x5297 ;
.dw 0x639B ;
.dw 0xC64B ;
.dw 0xCF77 ;
.dw 0x6883 ;
.dw 0xF731 ;
.dw 0xA8DF ;
.dw 0xCF78 ;
.dw 0x4387 ;
.dw 0x53CB ;
.dw 0x9CA1 ;
.dw 0xCF79 ;
.dw 0xAB55 ;
.dw 0xF8B ;
.dw 0xC01D ;
.dw 0xCF7A ;
.dw 0x3335 ;
.dw 0xA1EB ;
.dw 0xFD35 ;
.dw 0xCF7B ;
.dw 0xB3D ;
.dw 0x3F6B ;
.dw 0xF1A1 ;
.dw 0xCF7C ;
.dw 0x6EA9 ;
.dw 0x33F3 ;
.dw 0xAB8B ;
.dw 0xCF7D ;
.dw 0xBB41 ;
.dw 0xBCB7 ;
.dw 0xAA7D ;
.dw 0xCF7E ;
.dw 0x1ABD ;
.dw 0x8C9F ;
.dw 0xBBA9 ;
.dw 0xCF7F ;
.dw 0xB089 ;
.dw 0x55A3 ;
.dw 0xED41 ;
.dw 0xCF80 ;
.dw 0xB59D ;
.dw 0xC0AD ;
.dw 0xE873 ;
.dw 0xCF81 ;
.dw 0xFEA7 ;
.dw 0xB265 ;
.dw 0xF55F ;
.dw 0xCF82 ;
.dw 0x8A87 ;
.dw 0xE7F9 ;
.dw 0x64D3 ;
.dw 0xCF83 ;
.dw 0xE769 ;
.dw 0x6783 ;
.dw 0x4547 ;
.dw 0xCF84 ;
.dw 0x9597 ;
.dw 0xFBE9 ;
.dw 0xE1DD ;
.dw 0xCF85 ;
.dw 0x5239 ;
.dw 0x6397 ;
.dw 0x99C1 ;
.dw 0xCF86 ;
.dw 0xE6FF ;
.dw 0x84B ;
.dw 0x31C7 ;
.dw 0xCF87 ;
.dw 0x3E93 ;
.dw 0x6CDD ;
.dw 0xE883 ;
.dw 0xCF88 ;
.dw 0x9A81 ;
.dw 0xEB3D ;
.dw 0x310B ;
.dw 0xCF89 ;
.dw 0xA8AF ;
.dw 0x405D ;
.dw 0xDFC7 ;
.dw 0xCF8A ;
.dw 0x515B ;
.dw 0x7C13 ;
.dw 0xD483 ;
.dw 0xCF8B ;
.dw 0x1EE3 ;
.dw 0xD5E9 ;
.dw 0x2FAD ;
.dw 0xCF8C ;
.dw 0x2A93 ;
.dw 0xB0E1 ;
.dw 0xC4C1 ;
.dw 0xCF8D ;
.dw 0xD1DD ;
.dw 0xB1E7 ;
.dw 0x1E29 ;
.dw 0xCF8E ;
.dw 0xD6ED ;
.dw 0x1DB1 ;
.dw 0x2C7F ;
.dw 0xCF8F ;
.dw 0x1935 ;
.dw 0x6711 ;
.dw 0x618D ;
.dw 0xCF90 ;
.dw 0xFB4D ;
.dw 0xD003 ;
.dw 0xB185 ;
.dw 0xCF91 ;
.dw 0x1969 ;
.dw 0xD80F ;
.dw 0xDD13 ;
.dw 0xCF92 ;
.dw 0xFDE7 ;
.dw 0xF487 ;
.dw 0x54AB ;
.dw 0xCF93 ;
.dw 0x4FDB ;
.dw 0xCA39 ;
.dw 0x7EAF ;
.dw 0xCF94 ;
.dw 0xF805 ;
.dw 0xC4BF ;
.dw 0x8F77 ;
.dw 0xCF95 ;
.dw 0x24E3 ;
.dw 0x5055 ;
.dw 0x491 ;
.dw 0xCF96 ;
.dw 0x37A9 ;
.dw 0xCD9D ;
.dw 0xD301 ;
.dw 0xCF97 ;
.dw 0x2379 ;
.dw 0xDD89 ;
.dw 0xBC7B ;
.dw 0xCF98 ;
.dw 0xE1F3 ;
.dw 0x977F ;
.dw 0xED8B ;
.dw 0xCF99 ;
.dw 0xF983 ;
.dw 0xCE75 ;
.dw 0x3E75 ;
.dw 0xCF9A ;
.dw 0x4081 ;
.dw 0xF3D5 ;
.dw 0x3185 ;
.dw 0xCF9B ;
.dw 0xCB77 ;
.dw 0x47AD ;
.dw 0x97E9 ;
.dw 0xCF9C ;
.dw 0x71AF ;
.dw 0x93E1 ;
.dw 0xE25B ;
.dw 0xCF9D ;
.dw 0x9139 ;
.dw 0xCE65 ;
.dw 0x33C3 ;
.dw 0xCF9E ;
.dw 0xF4F5 ;
.dw 0xEF8D ;
.dw 0xC8D5 ;
.dw 0xCF9F ;
.dw 0x1E1 ;
.dw 0x59A7 ;
.dw 0xE7A1 ;
.dw 0xCFA0 ;
.dw 0x4241 ;
.dw 0xCB25 ;
.dw 0x4265 ;
.dw 0xCFA1 ;
.dw 0xE769 ;
.dw 0x27E1 ;
.dw 0xCD97 ;
.dw 0xCFA2 ;
.dw 0xA491 ;
.dw 0xB5C1 ;
.dw 0x427 ;
.dw 0xCFA3 ;
.dw 0x6AD7 ;
.dw 0xC611 ;
.dw 0xD5AB ;
.dw 0xCFA4 ;
.dw 0x4DA9 ;
.dw 0x8A15 ;
.dw 0x83DD ;
.dw 0xCFA5 ;
.dw 0xE503 ;
.dw 0xCB71 ;
.dw 0x2189 ;
.dw 0xCFA6 ;
.dw 0x6A27 ;
.dw 0x2EBB ;
.dw 0xE6D9 ;
.dw 0xCFA7 ;
.dw 0xDF6B ;
.dw 0x35E5 ;
.dw 0x288D ;
.dw 0xCFA8 ;
.dw 0x42DD ;
.dw 0x6A67 ;
.dw 0xD7F1 ;
.dw 0xCFA9 ;
.dw 0x143B ;
.dw 0x70F9 ;
.dw 0x319D ;
.dw 0xCFAA ;
.dw 0x919B ;
.dw 0x7C3B ;
.dw 0x1B7B ;
.dw 0xCFAB ;
.dw 0x4413 ;
.dw 0x42CB ;
.dw 0xC3FF ;
.dw 0xCFAC ;
.dw 0x7D61 ;
.dw 0x27AB ;
.dw 0x818B ;
.dw 0xCFAD ;
.dw 0x839F ;
.dw 0x7FB1 ;
.dw 0x27A3 ;
.dw 0xCFAE ;
.dw 0x932D ;
.dw 0xE719 ;
.dw 0x5449 ;
.dw 0xCFAF ;
.dw 0x1289 ;
.dw 0xDED7 ;
.dw 0xC905 ;
.dw 0xCFB0 ;
.dw 0xE641 ;
.dw 0xDFAD ;
.dw 0xF1A5 ;
.dw 0xCFB1 ;
.dw 0xC0D1 ;
.dw 0xF7BD ;
.dw 0x3423 ;
.dw 0xCFB2 ;
.dw 0xAC39 ;
.dw 0xDC73 ;
.dw 0x4545 ;
.dw 0xCFB3 ;
.dw 0x3F39 ;
.dw 0xB1D9 ;
.dw 0x3DA7 ;
.dw 0xCFB4 ;
.dw 0x86A1 ;
.dw 0xE663 ;
.dw 0xB105 ;
.dw 0xCFB5 ;
.dw 0x52A1 ;
.dw 0xA52D ;
.dw 0xB8C7 ;
.dw 0xCFB6 ;
.dw 0x9D8B ;
.dw 0xE251 ;
.dw 0xFFB3 ;
.dw 0xCFB7 ;
.dw 0xA225 ;
.dw 0x7425 ;
.dw 0xA407 ;
.dw 0xCFB8 ;
.dw 0x13C3 ;
.dw 0xD553 ;
.dw 0x9F8F ;
.dw 0xCFB9 ;
.dw 0x9ABF ;
.dw 0x6487 ;
.dw 0xE63D ;
.dw 0xCFBA ;
.dw 0x971B ;
.dw 0xEBCD ;
.dw 0xF725 ;
.dw 0xCFBB ;
.dw 0x8B4F ;
.dw 0xCED3 ;
.dw 0x691B ;
.dw 0xCFBC ;
.dw 0x3C89 ;
.dw 0xFE7B ;
.dw 0x9105 ;
.dw 0xCFBD ;
.dw 0x86D9 ;
.dw 0xC0CD ;
.dw 0x75A5 ;
.dw 0xCFBE ;
.dw 0xD961 ;
.dw 0xF4C1 ;
.dw 0x7801 ;
.dw 0xCFBF ;
.dw 0xAAA3 ;
.dw 0xC993 ;
.dw 0x92C5 ;
.dw 0xCFC0 ;
.dw 0x8D ;
.dw 0xEAB5 ;
.dw 0xCF55 ;
.dw 0xCFC1 ;
.dw 0xF94D ;
.dw 0xB307 ;
.dw 0xA575 ;
.dw 0xCFC2 ;
.dw 0x140F ;
.dw 0x4CE7 ;
.dw 0xD78B ;
.dw 0xCFC3 ;
.dw 0xF359 ;
.dw 0x4DE7 ;
.dw 0x958B ;
.dw 0xCFC4 ;
.dw 0xD893 ;
.dw 0xBA3 ;
.dw 0x8A5D ;
.dw 0xCFC5 ;
.dw 0x5149 ;
.dw 0xCB4B ;
.dw 0x21E3 ;
.dw 0xCFC6 ;
.dw 0xA65 ;
.dw 0x7A85 ;
.dw 0x2571 ;
.dw 0xCFC7 ;
.dw 0xA2DF ;
.dw 0xC7F9 ;
.dw 0xB9AF ;
.dw 0xCFC8 ;
.dw 0xF8A3 ;
.dw 0x491D ;
.dw 0xBD37 ;
.dw 0xCFC9 ;
.dw 0xFA7B ;
.dw 0x8B45 ;
.dw 0xCD ;
.dw 0xCFCA ;
.dw 0x84F3 ;
.dw 0x1C97 ;
.dw 0xA6C7 ;
.dw 0xCFCB ;
.dw 0x1349 ;
.dw 0x6CD9 ;
.dw 0xF7E3 ;
.dw 0xCFCC ;
.dw 0x738D ;
.dw 0x9209 ;
.dw 0x90F9 ;
.dw 0xCFCD ;
.dw 0x6C31 ;
.dw 0x3A3D ;
.dw 0x7921 ;
.dw 0xCFCE ;
.dw 0x18E5 ;
.dw 0xB46F ;
.dw 0xE29B ;
.dw 0xCFCF ;
.dw 0x812D ;
.dw 0x2E4B ;
.dw 0xB56B ;
.dw 0xCFD0 ;
.dw 0x87E5 ;
.dw 0x18D5 ;
.dw 0xC509 ;
.dw 0xCFD1 ;
.dw 0x8005 ;
.dw 0xFAA1 ;
.dw 0x7DC1 ;
.dw 0xCFD2 ;
.dw 0xCCC5 ;
.dw 0xBEE7 ;
.dw 0x87FB ;
.dw 0xCFD3 ;
.dw 0x6D11 ;
.dw 0xE40B ;
.dw 0x47C5 ;
.dw 0xCFD4 ;
.dw 0xDE9F ;
.dw 0x6351 ;
.dw 0x24DB ;
.dw 0xCFD5 ;
.dw 0x8803 ;
.dw 0x690D ;
.dw 0xE3F5 ;
.dw 0xCFD6 ;
.dw 0x22C9 ;
.dw 0x505 ;
.dw 0xF573 ;
.dw 0xCFD7 ;
.dw 0xC055 ;
.dw 0xB295 ;
.dw 0xA7D3 ;
.dw 0xCFD8 ;
.dw 0x305 ;
.dw 0xD61D ;
.dw 0x933B ;
.dw 0xCFD9 ;
.dw 0xC59 ;
.dw 0x8CD1 ;
.dw 0x3D47 ;
.dw 0xCFDA ;
.dw 0x9095 ;
.dw 0x8C21 ;
.dw 0xAA23 ;
.dw 0xCFDB ;
.dw 0x5D97 ;
.dw 0x376F ;
.dw 0x3C85 ;
.dw 0xCFDC ;
.dw 0xDC49 ;
.dw 0xE393 ;
.dw 0xB31B ;
.dw 0xCFDD ;
.dw 0x9871 ;
.dw 0x61FF ;
.dw 0xCF1 ;
.dw 0xCFDE ;
.dw 0xEC8D ;
.dw 0xD8B ;
.dw 0x683D ;
.dw 0xCFDF ;
.dw 0x449D ;
.dw 0x82F5 ;
.dw 0x24FF ;
.dw 0xCFE0 ;
.dw 0x708D ;
.dw 0x8629 ;
.dw 0xB5D3 ;
.dw 0xCFE1 ;
.dw 0x7FA3 ;
.dw 0xC4EB ;
.dw 0x80C7 ;
.dw 0xCFE2 ;
.dw 0xD88F ;
.dw 0x5DBF ;
.dw 0x5113 ;
.dw 0xCFE3 ;
.dw 0xF1BD ;
.dw 0x6797 ;
.dw 0xEA3B ;
.dw 0xCFE4 ;
.dw 0xB965 ;
.dw 0x2E63 ;
.dw 0x56ED ;
.dw 0xCFE5 ;
.dw 0x15B ;
.dw 0x733 ;
.dw 0x5599 ;
.dw 0xCFE6 ;
.dw 0xB249 ;
.dw 0xAAFB ;
.dw 0xC29B ;
.dw 0xCFE7 ;
.dw 0x20C1 ;
.dw 0x26A9 ;
.dw 0x39 ;
.dw 0xCFE8 ;
.dw 0xD1E5 ;
.dw 0xCC2D ;
.dw 0x8D6D ;
.dw 0xCFE9 ;
.dw 0xB4C3 ;
.dw 0xF651 ;
.dw 0xF25 ;
.dw 0xCFEA ;
.dw 0x10F3 ;
.dw 0xFB75 ;
.dw 0x3E79 ;
.dw 0xCFEB ;
.dw 0x9B55 ;
.dw 0x2A7 ;
.dw 0xFEAB ;
.dw 0xCFEC ;
.dw 0x4623 ;
.dw 0x1BCD ;
.dw 0xFA9B ;
.dw 0xCFED ;
.dw 0xA3E3 ;
.dw 0x9B9B ;
.dw 0x2B6F ;
.dw 0xCFEE ;
.dw 0x58A9 ;
.dw 0xD303 ;
.dw 0x2287 ;
.dw 0xCFEF ;
.dw 0x3AF1 ;
.dw 0xBEFF ;
.dw 0xF90B ;
.dw 0xCFF0 ;
.dw 0xCC47 ;
.dw 0xDE4D ;
.dw 0x9E43 ;
.dw 0xCFF1 ;
.dw 0xFE51 ;
.dw 0x7DC7 ;
.dw 0x79BD ;
.dw 0xCFF2 ;
.dw 0x6B1D ;
.dw 0x6835 ;
.dw 0x7AD9 ;
.dw 0xCFF3 ;
.dw 0xC635 ;
.dw 0x955D ;
.dw 0xDE57 ;
.dw 0xCFF4 ;
.dw 0x2F0B ;
.dw 0x2555 ;
.dw 0xD887 ;
.dw 0xCFF5 ;
.dw 0xCB59 ;
.dw 0xAC01 ;
.dw 0x3CEB ;
.dw 0xCFF6 ;
.dw 0xFDF5 ;
.dw 0x510D ;
.dw 0xB54D ;
.dw 0xCFF7 ;
.dw 0xD1DB ;
.dw 0xA867 ;
.dw 0x482F ;
.dw 0xCFF8 ;
.dw 0xB1C9 ;
.dw 0x5AA7 ;
.dw 0x4121 ;
.dw 0xCFF9 ;
.dw 0x83A1 ;
.dw 0x5A65 ;
.dw 0x4161 ;
.dw 0xCFFA ;
.dw 0x9E7F ;
.dw 0xF1F ;
.dw 0x7E8F ;
.dw 0xCFFB ;
.dw 0x4D1F ;
.dw 0x7C11 ;
.dw 0xA17B ;
.dw 0xCFFC ;
.dw 0xB5FD ;
.dw 0x2AF7 ;
.dw 0x5C2B ;
.dw 0xCFFD ;
.dw 0xFA4F ;
.dw 0x580D ;
.dw 0x8E77 ;
.dw 0xCFFE ;
.dw 0xEB0B ;
.dw 0x633B ;
.dw 0x9099 ;
.dw 0xCFFF ;
.dw 0xE1A1 ;
.dw 0x7B5F ;
.dw 0xC9B ;
// COUNT = 6662
// count of UI's will be in r5, which was initialized to 0 by header
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x21;
CHECKREG(r5, 256); // count of all 16 bit UI's.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 64 bit illegal opcode handler - skips bad instruction
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
dbg_fail;
UNDEFINEDINSTRUCTION:
R7 = RETX; // Fix up return address
R7 += 8; // skip offending 64 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 5,691 | sim/testsuite/bfin/se_excpt_ssstep.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp
// Description: EXCPT instruction vs Single Step Exception Priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
//include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
R0 = 1;
SYSCFG = r0; // Enable Supervisor Single Step
CHECK_INIT_DEF(p2); //CHECK_INIT(p2, 0x2000);
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
R0 = 0;
R0 = 0;
R0 = 0;
R0 = 0;
R0 = 0;
EXCPT 15; // single step shouldn't happen for this.
R0 = 0;
R0 = 0;
R0 = 0;
R0 = 0;
R0 = 0;
EXCPT 3; // turn off single step via handler
CHECKREG(r4, 1); // one EXCPT 15 instruction
CHECKREG(r5, 14); // 14 instructions are executed before we disable single step
// PUT YOUR TEST HERE!
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x10; // EXCAUSE 0x10 means Single Step
CC = r7 == r6;
IF CC JUMP SINGLESTEP (BP); // Go to Single Step Handler
R6 = 15; // EXCAUSE 15 means EXCPT 15 instruction
CC = r7 == r6;
IF CC JUMP EXCPT15 (BP);
SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep
JUMP.S OUT;
EXCPT15:
R4 += 1; // R4 counts EXCPT 15s
JUMP.S OUT;
SINGLESTEP:
R5 += 1; // R5 counts single step events
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 7,992 | sim/testsuite/bfin/c_comp3op_dr_and_dr.s | //Original:/testcases/core/c_comp3op_dr_and_dr/c_comp3op_dr_and_dr.dsp
// Spec Reference: comp3op dregs & dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 & R0;
R1 = R0 & R1;
R2 = R0 & R2;
R3 = R0 & R3;
R4 = R0 & R4;
R5 = R0 & R5;
R6 = R0 & R6;
R7 = R0 & R7;
CHECKREG r0, 0x01234567;
CHECKREG r1, 0x01234567;
CHECKREG r2, 0x00200024;
CHECKREG r3, 0x00200024;
CHECKREG r4, 0x01014001;
CHECKREG r5, 0x00010145;
CHECKREG r6, 0x00224422;
CHECKREG r7, 0x00204460;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 & R0;
R1 = R1 & R1;
R2 = R1 & R2;
R3 = R1 & R3;
R4 = R1 & R4;
R5 = R1 & R5;
R6 = R1 & R6;
R7 = R1 & R7;
CHECKREG r0, 0x01231567;
CHECKREG r1, 0x89AB1DEF;
CHECKREG r2, 0x002818AC;
CHECKREG r3, 0x88A01024;
CHECKREG r4, 0x01011889;
CHECKREG r5, 0x08811145;
CHECKREG r6, 0x88221422;
CHECKREG r7, 0x00201468;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 & R0;
R1 = R2 & R1;
R2 = R2 & R2;
R3 = R2 & R3;
R4 = R2 & R4;
R5 = R2 & R5;
R6 = R2 & R6;
R7 = R2 & R7;
CHECKREG r0, 0x00200024;
CHECKREG r1, 0x0028882C;
CHECKREG r2, 0x56789A2C;
CHECKREG r3, 0x56701224;
CHECKREG r4, 0x02400828;
CHECKREG r5, 0x50100224;
CHECKREG r6, 0x10701020;
CHECKREG r7, 0x12301228;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 & R0;
R1 = R3 & R1;
R2 = R3 & R2;
R3 = R3 & R3;
R4 = R3 & R4;
R5 = R3 & R5;
R6 = R3 & R6;
R7 = R3 & R7;
CHECKREG r0, 0x00200023;
CHECKREG r1, 0x88A00023;
CHECKREG r2, 0x56701233;
CHECKREG r3, 0xDEF01233;
CHECKREG r4, 0x02400013;
CHECKREG r5, 0x58900203;
CHECKREG r6, 0x98701033;
CHECKREG r7, 0x12301233;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 & R0;
R1 = R4 & R1;
R2 = R4 & R2;
R3 = R4 & R3;
R4 = R4 & R4;
R5 = R4 & R5;
R6 = R4 & R6;
R7 = R4 & R7;
CHECKREG r0, 0x41014001;
CHECKREG r1, 0x41014889;
CHECKREG r2, 0x42400898;
CHECKREG r3, 0x42400010;
CHECKREG r4, 0x43456899;
CHECKREG r5, 0x40012001;
CHECKREG r6, 0x40444010;
CHECKREG r7, 0x42044018;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 & R0;
R1 = R5 & R1;
R2 = R5 & R2;
R3 = R5 & R3;
R4 = R5 & R4;
R5 = R5 & R5;
R6 = R5 & R6;
R7 = R5 & R7;
CHECKREG r0, 0x05010145;
CHECKREG r1, 0x05810145;
CHECKREG r2, 0x55100204;
CHECKREG r3, 0x55900204;
CHECKREG r4, 0x25012001;
CHECKREG r5, 0x75912345;
CHECKREG r6, 0x15100000;
CHECKREG r7, 0x15100240;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 & R0;
R1 = R6 & R1;
R2 = R6 & R2;
R3 = R6 & R3;
R4 = R6 & R4;
R5 = R6 & R5;
R6 = R6 & R6;
R7 = R6 & R7;
CHECKREG r0, 0x00264422;
CHECKREG r1, 0x88264422;
CHECKREG r2, 0x10761030;
CHECKREG r3, 0x98761030;
CHECKREG r4, 0x00464010;
CHECKREG r5, 0x18160000;
CHECKREG r6, 0x98765432;
CHECKREG r7, 0x10365430;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 & R0;
R1 = R7 & R1;
R2 = R7 & R2;
R3 = R7 & R3;
R4 = R7 & R4;
R5 = R7 & R5;
R6 = R7 & R6;
R7 = R7 & R7;
CHECKREG r0, 0x00205460;
CHECKREG r1, 0x00205468;
CHECKREG r2, 0x12305238;
CHECKREG r3, 0x12305230;
CHECKREG r4, 0x02045018;
CHECKREG r5, 0x10105240;
CHECKREG r6, 0x10345430;
CHECKREG r7, 0x12345678;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 & R0;
R1 = R2 & R0;
R2 = R3 & R0;
R3 = R4 & R0;
R4 = R5 & R0;
R5 = R6 & R0;
R6 = R7 & R0;
R7 = R0 & R0;
CHECKREG r0, 0x01234567;
CHECKREG r1, 0x00000024;
CHECKREG r2, 0x00210024;
CHECKREG r3, 0x01010001;
CHECKREG r4, 0x00010145;
CHECKREG r5, 0x00224402;
CHECKREG r6, 0x00204461;
CHECKREG r7, 0x01234567;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 & R1;
R1 = R3 & R1;
R2 = R4 & R1;
R3 = R5 & R1;
R4 = R6 & R1;
R5 = R7 & R1;
R6 = R0 & R1;
R7 = R1 & R1;
CHECKREG r0, 0x002818AC;
CHECKREG r1, 0x08201024;
CHECKREG r2, 0x00001000;
CHECKREG r3, 0x08000004;
CHECKREG r4, 0x08201020;
CHECKREG r5, 0x00201020;
CHECKREG r6, 0x00201024;
CHECKREG r7, 0x08201024;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R4 & R2;
R1 = R5 & R2;
R2 = R6 & R2;
R3 = R7 & R2;
R4 = R0 & R2;
R5 = R1 & R2;
R6 = R2 & R2;
R7 = R3 & R2;
CHECKREG r0, 0x02410228;
CHECKREG r1, 0x50310224;
CHECKREG r2, 0x10731020;
CHECKREG r3, 0x10301020;
CHECKREG r4, 0x00410020;
CHECKREG r5, 0x10310020;
CHECKREG r6, 0x10731020;
CHECKREG r7, 0x10301020;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R5 & R3;
R1 = R6 & R3;
R2 = R7 & R3;
R3 = R0 & R3;
R4 = R1 & R3;
R5 = R2 & R3;
R6 = R3 & R3;
R7 = R4 & R3;
CHECKREG r0, 0x48400200;
CHECKREG r1, 0x08704030;
CHECKREG r2, 0x02304233;
CHECKREG r3, 0x48400200;
CHECKREG r4, 0x08400000;
CHECKREG r5, 0x00000200;
CHECKREG r6, 0x48400200;
CHECKREG r7, 0x08400000;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R6 & R4;
R1 = R7 & R4;
R2 = R0 & R4;
R3 = R1 & R4;
R4 = R2 & R4;
R5 = R3 & R4;
R6 = R4 & R4;
R7 = R5 & R4;
CHECKREG r0, 0x40444010;
CHECKREG r1, 0x42054018;
CHECKREG r2, 0x40444010;
CHECKREG r3, 0x42054018;
CHECKREG r4, 0x40444010;
CHECKREG r5, 0x40044010;
CHECKREG r6, 0x40444010;
CHECKREG r7, 0x40044010;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R7 & R5;
R1 = R0 & R5;
R2 = R1 & R5;
R3 = R2 & R5;
R4 = R3 & R5;
R5 = R4 & R5;
R6 = R5 & R5;
R7 = R6 & R5;
CHECKREG r0, 0x15140240;
CHECKREG r1, 0x15140240;
CHECKREG r2, 0x15140240;
CHECKREG r3, 0x15140240;
CHECKREG r4, 0x15140240;
CHECKREG r5, 0x15140240;
CHECKREG r6, 0x15140240;
CHECKREG r7, 0x15140240;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 & R6;
R1 = R0 & R6;
R2 = R1 & R6;
R3 = R2 & R6;
R4 = R3 & R6;
R5 = R4 & R6;
R6 = R5 & R6;
R7 = R6 & R6;
CHECKREG r0, 0x10365430;
CHECKREG r1, 0x10365430;
CHECKREG r2, 0x10365430;
CHECKREG r3, 0x10365430;
CHECKREG r4, 0x10365430;
CHECKREG r5, 0x10365430;
CHECKREG r6, 0x10365430;
CHECKREG r7, 0x10365430;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 & R7;
R1 = R2 & R7;
R2 = R3 & R7;
R3 = R4 & R7;
R4 = R5 & R7;
R5 = R6 & R7;
R6 = R7 & R7;
R7 = R0 & R7;
CHECKREG r0, 0x00200068;
CHECKREG r1, 0x12000208;
CHECKREG r2, 0x02300238;
CHECKREG r3, 0x00048018;
CHECKREG r4, 0x10000040;
CHECKREG r5, 0x10300400;
CHECKREG r6, 0x12348678;
CHECKREG r7, 0x00200068;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,562 | sim/testsuite/bfin/c_dsp32alu_rrpm.s | //Original:/testcases/core/c_dsp32alu_rrpm/c_dsp32alu_rrpm.dsp
// Spec Reference: dsp32alu (dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x75678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34745515;
imm32 r3, 0x46677717;
imm32 r0, 0x5567a91b;
imm32 r1, 0x6789aa1d;
imm32 r2, 0x744455a5;
imm32 r3, 0x8666777a;
R0 = R0 + R0, R7 = R0 - R0 (NS);
R1 = R0 + R1, R6 = R0 - R1 (NS);
R2 = R0 + R2, R5 = R0 - R2 (NS);
R3 = R0 + R3, R4 = R0 - R3 (NS);
R4 = R0 + R4, R3 = R0 - R4 (NS);
R5 = R0 + R5, R2 = R0 - R5 (NS);
R6 = R0 + R6, R1 = R0 - R6 (NS);
R7 = R0 + R7, R0 = R0 - R7 (NS);
CHECKREG r0, 0xAACF5236;
CHECKREG r1, 0x6789AA1D;
CHECKREG r2, 0x744455A5;
CHECKREG r3, 0x8666777A;
CHECKREG r4, 0xCF382CF2;
CHECKREG r5, 0xE15A4EC7;
CHECKREG r6, 0xEE14FA4F;
CHECKREG r7, 0xAACF5236;
imm32 r0, 0x4567892b;
imm32 r1, 0x4489ab2d;
imm32 r2, 0x54445525;
imm32 r3, 0x66645727;
imm32 r4, 0x78889629;
imm32 r5, 0x8aaabb6b;
imm32 r6, 0x9cccdd2d;
imm32 r7, 0x0eee3fff;
R0 = R1 + R0, R7 = R1 - R0 (NS);
R1 = R1 + R1, R6 = R1 - R1 (NS);
R2 = R1 + R2, R5 = R1 - R2 (NS);
R3 = R1 + R3, R4 = R1 - R3 (NS);
R4 = R1 + R4, R3 = R1 - R4 (NS);
R5 = R1 + R5, R2 = R1 - R5 (NS);
R6 = R1 + R6, R1 = R1 - R6 (NS);
R7 = R1 + R7, R0 = R1 - R7 (NS);
CHECKREG r0, 0x89F13458;
CHECKREG r1, 0x8913565A;
CHECKREG r2, 0x54445525;
CHECKREG r3, 0x66645727;
CHECKREG r4, 0xABC2558D;
CHECKREG r5, 0xBDE2578F;
CHECKREG r6, 0x8913565A;
CHECKREG r7, 0x8835785C;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0x1eaa4bbb;
imm32 r6, 0x2fccd44d;
imm32 r7, 0x31eefff4;
R0 = R2 + R0, R7 = R2 - R0 (NS);
R1 = R2 + R1, R6 = R2 - R1 (NS);
R2 = R2 + R2, R5 = R2 - R2 (NS);
R3 = R2 + R3, R4 = R2 - R3 (NS);
R4 = R2 + R4, R3 = R2 - R4 (NS);
R5 = R2 + R5, R2 = R2 - R5 (NS);
R6 = R2 + R6, R1 = R2 - R6 (NS);
R7 = R2 + R7, R0 = R2 - R7 (NS);
CHECKREG r0, 0x94ABDF00;
CHECKREG r1, 0xAFCE0122;
CHECKREG r2, 0x9688AAAA;
CHECKREG r3, 0x6C647777;
CHECKREG r4, 0xC0ACDDDD;
CHECKREG r5, 0x9688AAAA;
CHECKREG r6, 0x7D435432;
CHECKREG r7, 0x98657654;
imm32 r0, 0xa537891b;
imm32 r1, 0x6a59ab2d;
imm32 r2, 0x44a55535;
imm32 r3, 0x166a5747;
imm32 r4, 0x6878a565;
imm32 r5, 0x7a8aba5b;
imm32 r6, 0x8c9cdd85;
imm32 r7, 0x9eaeffaf;
R0 = R3 + R0, R7 = R3 - R0 (NS);
R1 = R3 + R1, R6 = R3 - R1 (NS);
R2 = R3 + R2, R5 = R3 - R2 (NS);
R3 = R3 + R3, R4 = R3 - R3 (NS);
R4 = R3 + R4, R3 = R3 - R4 (NS);
R5 = R3 + R5, R2 = R3 - R5 (NS);
R6 = R3 + R6, R1 = R3 - R6 (NS);
R7 = R3 + R7, R0 = R3 - R7 (NS);
CHECKREG r0, 0xBBA1E062;
CHECKREG r1, 0x80C40274;
CHECKREG r2, 0x5B0FAC7C;
CHECKREG r3, 0x2CD4AE8E;
CHECKREG r4, 0x2CD4AE8E;
CHECKREG r5, 0xFE99B0A0;
CHECKREG r6, 0xD8E55AA8;
CHECKREG r7, 0x9E077CBA;
imm32 r0, 0x15678911;
imm32 r1, 0x9789ab1d;
imm32 r2, 0x94445515;
imm32 r3, 0x96667717;
imm32 r0, 0x5267891b;
imm32 r1, 0x67a9ab1d;
imm32 r2, 0x744c5515;
imm32 r3, 0x8666d777;
R0 = R4 + R0, R7 = R4 - R0 (NS);
R1 = R4 + R1, R6 = R4 - R1 (NS);
R2 = R4 + R2, R5 = R4 - R2 (NS);
R3 = R4 + R3, R4 = R4 - R3 (NS);
R4 = R4 + R4, R3 = R4 - R4 (NS);
R5 = R4 + R5, R2 = R4 - R5 (NS);
R6 = R4 + R6, R1 = R4 - R6 (NS);
R7 = R4 + R7, R0 = R4 - R7 (NS);
CHECKREG r0, 0x726E88BB;
CHECKREG r1, 0x87B0AABD;
CHECKREG r2, 0x945354B5;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x4CDBAE2E;
CHECKREG r5, 0x056407A7;
CHECKREG r6, 0x1206B19F;
CHECKREG r7, 0x2748D3A1;
imm32 r0, 0xa567892b;
imm32 r1, 0x4a89ab2d;
imm32 r2, 0x54a45525;
imm32 r3, 0x666d7727;
imm32 r4, 0x7888d929;
imm32 r5, 0x8aaabe2b;
imm32 r6, 0x9cccdd2d;
imm32 r7, 0x0eeeffef;
R0 = R5 + R0, R7 = R5 - R0 (NS);
R1 = R5 + R1, R6 = R5 - R1 (NS);
R2 = R5 + R2, R5 = R5 - R2 (NS);
R3 = R5 + R3, R4 = R5 - R3 (NS);
R4 = R5 + R4, R3 = R5 - R4 (NS);
R5 = R5 + R5, R2 = R5 - R5 (NS);
R6 = R5 + R6, R1 = R5 - R6 (NS);
R7 = R5 + R7, R0 = R5 - R7 (NS);
CHECKREG r0, 0x86C99D0C;
CHECKREG r1, 0x2BEBBF0E;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x666D7727;
CHECKREG r4, 0x059F5AE5;
CHECKREG r5, 0x6C0CD20C;
CHECKREG r6, 0xAC2DE50A;
CHECKREG r7, 0x5150070C;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0x1eaa4bbb;
imm32 r6, 0x2fccd44d;
imm32 r7, 0x31eefff4;
R0 = R6 + R0, R7 = R6 - R0 (NS);
R1 = R6 + R1, R6 = R6 - R1 (NS);
R2 = R6 + R2, R5 = R6 - R2 (NS);
R3 = R6 + R3, R4 = R6 - R3 (NS);
R4 = R6 + R4, R3 = R6 - R4 (NS);
R5 = R6 + R5, R2 = R6 - R5 (NS);
R6 = R6 + R6, R1 = R6 - R6 (NS);
R7 = R6 + R7, R0 = R6 - R7 (NS);
CHECKREG r0, 0xB021065E;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x4B445555;
CHECKREG r3, 0x6C647777;
CHECKREG r4, 0x2A21D989;
CHECKREG r5, 0x4B41FBAB;
CHECKREG r6, 0x96865100;
CHECKREG r7, 0x7CEB9BA2;
imm32 r0, 0xe537891b;
imm32 r1, 0xe759ab2d;
imm32 r2, 0x4e555535;
imm32 r3, 0x16e65747;
imm32 r4, 0x687e9565;
imm32 r5, 0x7a8aeb5b;
imm32 r6, 0x8c9cdd85;
imm32 r7, 0x9eaefe9f;
R0 = R7 + R0, R7 = R7 - R0 (NS);
R1 = R7 + R1, R6 = R7 - R1 (NS);
R2 = R7 + R2, R5 = R7 - R2 (NS);
R3 = R7 + R3, R4 = R7 - R3 (NS);
R4 = R7 + R4, R3 = R7 - R4 (NS);
R5 = R7 + R5, R2 = R7 - R5 (NS);
R6 = R7 + R6, R1 = R7 - R6 (NS);
R7 = R7 + R7, R0 = R7 - R7 (NS);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xE759AB2D;
CHECKREG r2, 0x4E555535;
CHECKREG r3, 0x16E65747;
CHECKREG r4, 0x5C0893C1;
CHECKREG r5, 0x249995D3;
CHECKREG r6, 0x8B953FDB;
CHECKREG r7, 0x72EEEB08;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0x1eaa4bbb;
imm32 r6, 0x2fccd44d;
imm32 r7, 0x31eefff4;
R2 = R4 + R0, R7 = R4 - R0 (S);
R3 = R7 + R1, R6 = R7 - R1 (NS);
R4 = R0 + R2, R5 = R0 - R2 (S);
R5 = R4 + R3, R4 = R4 - R3 (NS);
R6 = R2 + R4, R3 = R2 - R4 (S);
R7 = R3 + R5, R2 = R3 - R5 (NS);
R0 = R1 + R6, R1 = R1 - R6 (S);
R1 = R5 + R7, R0 = R5 - R7 (S);
CHECKREG r0, 0x64DDDDDE;
CHECKREG r1, 0xA4E4D39A;
CHECKREG r2, 0x9640C966;
CHECKREG r3, 0x9B222222;
CHECKREG r4, 0x3BCE0122;
CHECKREG r5, 0x04E158BC;
CHECKREG r6, 0x12BE2466;
CHECKREG r7, 0xA0037ADE;
imm32 r0, 0xa537891b;
imm32 r1, 0x6d59ab2d;
imm32 r2, 0x4f555535;
imm32 r3, 0x16c65747;
imm32 r4, 0x687c9565;
imm32 r5, 0x7a8acb5b;
imm32 r6, 0x8c9cdc85;
imm32 r7, 0x9eaefb9f;
R4 = R3 + R0, R1 = R3 - R0 (S);
R5 = R6 + R1, R2 = R6 - R1 (S);
R6 = R7 + R2, R3 = R7 - R2 (S);
R7 = R0 + R3, R4 = R0 - R3 (NS);
R0 = R2 + R4, R5 = R2 - R4 (S);
R1 = R1 + R5, R6 = R1 - R5 (S);
R2 = R5 + R6, R7 = R5 - R6 (NS);
R3 = R4 + R7, R0 = R4 - R7 (S);
CHECKREG r0, 0x052876A0;
CHECKREG r1, 0x6B0640B0;
CHECKREG r2, 0x718ECE2C;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x86888D7C;
CHECKREG r5, 0xF9777284;
CHECKREG r6, 0x78175BA8;
CHECKREG r7, 0x816016DC;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,244 | sim/testsuite/bfin/se_mv2lp.S | //Original:/proj/frio/dv/testcases/seq/se_mv2lp/se_mv2lp.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_1 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
P0 = 0x5 (Z);
P1 = 0xa (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LSETUP ( L0T , L0B ) LC0 = P0;
L0T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += 2;
LT0 = R0;
LB0 = R1;
L0B:R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LSETUP ( L1T , L1B ) LC1 = P0;
L1T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += 2;
LT1 = R0;
LB1 = R1;
L1B:R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
LD32_LABEL(r0, L2T);
LD32_LABEL(r1, L2B);
LSETUP ( L2T , L2B ) LC0 = P0;
L2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += -2;
LT0 = R0;
LB0 = R1;
R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
L2B:R6 += 5;
LD32_LABEL(r0, L3T);
LD32_LABEL(r1, L3B);
LSETUP ( L3T , L3B ) LC1 = P0;
L3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
R0 += 2;
R1 += -2;
LT1 = R0;
LB1 = R1;
R7 += 6;
R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
L3B:R6 += 5;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 3,444 | sim/testsuite/bfin/cec-multi-pending.S | # Blackfin testcase for multiple pending IVGs vs masked state
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
.macro check_cec mmr:req, valid:req
imm32 P3, \mmr;
R0 = [P3];
R1 = ~0x1f;
R0 = R0 & R1;
imm32 R1, \valid;
CC = R1 == R0;
IF CC JUMP 1f;
dbg_fail
1:
.endm
.macro delay cnt:req
imm32 P2, \cnt
LSETUP (1f, 1f) LC1 = P2;
1: mnop;
.endm
start
# First mark all EVTs as fails (they shouldn't be activated)
imm32 P5, EVT0;
P1 = P5;
loadsym R1, fail_lvl
imm32 P2, 16
LSETUP (1f, 1f) LC0 = P2;
1: [P1++] = R1;
# Lower ourselves to EVT15
set_evt 15, evt15;
R7 = 0 (x);
BITSET (R7, 15);
sti R7;
loadsym R1, wait;
RETI = R1;
RAISE 15;
RTI;
wait:
jump wait;
evt15:
# We shouldn't come back here
set_evt 15, fail_lvl;
# Activate interrupt nesting early
[--SP] = RETI;
# Raise some higher levels, but they should be masked and so
# they should never be activated ...
RAISE 6;
RAISE 5;
RAISE 9;
RAISE 12;
# Only IVG15 should be pending
check_cec IPEND, (1<<15);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<12);
# Delay a little in case a higher level wrongly activates
delay 30
# If we're still here, things are still good. So let's
# transition up *slightly*, but not to the highest latched.
set_evt 12, evt12;
cli R7;
BITSET (R7, 12);
sti R7;
# Let CEC raise us to IVG12
delay 30
# CEC should have been faster than this ...
dbg_fail
evt12:
# We shouldn't come back here
set_evt 12, fail_lvl;
# Raise some higher levels, but they should be masked and so
# they should never be activated ...
RAISE 11;
# Both IVG15 and IVG12 should be pending
check_cec IPEND, (1<<15) | (1<<12);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<6) | (1<<9) | (1<<11);
# Activate interrupt nesting a little later
[--SP] = RETI;
# Still here, so unmask a higher IVG again to move up
set_evt 9, evt9;
cli R7;
BITSET (R7, 9);
sti R7;
delay 30
# CEC should have been faster than this ...
dbg_fail
evt9:
# We shouldn't come back here
set_evt 9, fail_lvl;
# IVG9 should also be pending now
check_cec IPEND, (1<<15) | (1<<12) | (1<<9);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<6) | (1<<11);
# Unmask the next level, but IPEND[4] is set, so we should stay here
set_evt 6, evt6;
cli R7;
BITSET (R7, 6);
sti R7;
# Delay a little in case a higher level wrongly activates
delay 30
# Good, now unmask things globally
[--SP] = RETI;
delay 30
# CEC should have been faster than this ...
dbg_fail
evt6:
# We shouldn't come back here
set_evt 6, fail_lvl;
# IVG6 should also be pending now
check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6);
# But all should be latched
check_cec ILAT, (1<<5) | (1<<11);
# Activate interrupt nesting a little later
[--SP] = RETI;
# Unmask the next level, but do it via IMASK
set_evt 5, evt5;
imm32 P2, IMASK;
R7 = [P2];
BITSET (R7, 5);
[P2] = R7;
delay 30
# CEC should have been faster than this ...
dbg_fail
evt5:
# We shouldn't come back here
set_evt 5, fail_lvl;
# IVG5 should also be pending now
check_cec IPEND, (1<<15) | (1<<12) | (1<<9) | (1<<6) | (1<<5);
# But all should be latched
check_cec ILAT, (1<<11);
# All good!
dbg_pass;
fail_lvl:
dbg_fail;
|
tactcomplabs/xbgas-binutils-gdb | 6,112 | sim/testsuite/bfin/c_dsp32alu_rh_rnd12_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x45678ad1;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xf4445545;
imm32 r3, 0x46667767;
imm32 r4, 0xe678891b;
imm32 r5, 0x6f89ab1d;
imm32 r6, 0x7444d565;
imm32 r7, 0x8666b797;
R0.H = R0 - R0 (RND12);
R1.H = R0 - R1 (RND12);
R2.H = R0 - R2 (RND12);
R3.H = R0 - R3 (RND12);
R4.H = R0 - R4 (RND12);
R5.H = R0 - R5 (RND12);
R6.H = R0 - R6 (RND12);
R7.H = R0 - R7 (RND12);
CHECKREG r0, 0x00008AD1;
CHECKREG r1, 0x8000AB1D;
CHECKREG r2, 0x7fff5545;
CHECKREG r3, 0x80007767;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x8000D565;
CHECKREG r7, 0x7fffB797;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xa4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5b78891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74e45515;
imm32 r7, 0x86a6b777;
R0.H = R1 - R0 (RND12);
R1.H = R1 - R1 (RND12);
R2.H = R1 - R2 (RND12);
R3.H = R1 - R3 (RND12);
R4.H = R1 - R4 (RND12);
R5.H = R1 - R5 (RND12);
R6.H = R1 - R6 (RND12);
R7.H = R1 - R7 (RND12);
CHECKREG r0, 0x7fff8911;
CHECKREG r1, 0x0000AB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x80007717;
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x7fffB777;
imm32 r0, 0xa5678091;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xb4445515;
imm32 r3, 0x46667717;
imm32 r4, 0xd678891b;
imm32 r5, 0x6e89ab4d;
imm32 r6, 0x74445567;
imm32 r7, 0x86967757;
R0.H = R2 - R0 (RND12);
R1.H = R2 - R1 (RND12);
R2.H = R2 - R2 (RND12);
R3.H = R2 - R3 (RND12);
R4.H = R2 - R4 (RND12);
R5.H = R2 - R5 (RND12);
R6.H = R2 - R6 (RND12);
R7.H = R2 - R7 (RND12);
CHECKREG r0, 0x7fff8091;
CHECKREG r1, 0x8000AB1D;
CHECKREG r2, 0x00005515;
CHECKREG r3, 0x80007717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x8000AB4D;
CHECKREG r6, 0x80005567;
CHECKREG r7, 0x7fff7757;
imm32 r0, 0x35678991;
imm32 r1, 0x2789ab8d;
imm32 r2, 0xd4445515;
imm32 r3, 0x46667737;
imm32 r4, 0x5678891b;
imm32 r5, 0xeab9ab4d;
imm32 r6, 0x744e5515;
imm32 r7, 0x866e747f;
R0.H = R3 - R0 (RND12);
R1.H = R3 - R1 (RND12);
R2.H = R3 - R2 (RND12);
R3.H = R3 - R3 (RND12);
R4.H = R3 - R4 (RND12);
R5.H = R3 - R5 (RND12);
R6.H = R3 - R6 (RND12);
R7.H = R3 - R7 (RND12);
CHECKREG r0, 0x7fff8991;
CHECKREG r1, 0x7fffAB8D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x00007737;
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x7fffAB4D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x7fff747F;
imm32 r0, 0xe5678931;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34e45555;
imm32 r3, 0xd6667767;
imm32 r4, 0x5675891b;
imm32 r5, 0x6789abfd;
imm32 r6, 0xa4465515;
imm32 r7, 0x8b66e7b7;
R0.H = R4 - R0 (RND12);
R1.H = R4 - R1 (RND12);
R2.H = R4 - R2 (RND12);
R3.H = R4 - R3 (RND12);
R4.H = R4 - R4 (RND12);
R5.H = R4 - R5 (RND12);
R6.H = R4 - R6 (RND12);
R7.H = R4 - R7 (RND12);
CHECKREG r0, 0x7fff8931;
CHECKREG r1, 0x7fffAB1D;
CHECKREG r2, 0x7fff5555;
CHECKREG r3, 0x7fff7767;
CHECKREG r4, 0x0000891B;
CHECKREG r5, 0x8000ABFD;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x7fffE7B7;
imm32 r0, 0x35678931;
imm32 r1, 0x2789ab4d;
imm32 r2, 0x3e445585;
imm32 r3, 0x46667717;
imm32 r4, 0xe6f8899b;
imm32 r5, 0x6789db1d;
imm32 r6, 0xf44a5515;
imm32 r7, 0x866b77b7;
R0.H = R5 - R0 (RND12);
R1.H = R5 - R1 (RND12);
R2.H = R5 - R2 (RND12);
R3.H = R5 - R3 (RND12);
R4.H = R5 - R4 (RND12);
R5.H = R5 - R5 (RND12);
R6.H = R5 - R6 (RND12);
R7.H = R5 - R7 (RND12);
CHECKREG r0, 0x7fff8931;
CHECKREG r1, 0x7fffAB4D;
CHECKREG r2, 0x7fff5585;
CHECKREG r3, 0x7fff7717;
CHECKREG r4, 0x7fff899B;
CHECKREG r5, 0x0000DB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x7fff77B7;
imm32 r0, 0xb5678911;
imm32 r1, 0xc789ab1d;
imm32 r2, 0x3ab45515;
imm32 r3, 0x466b7717;
imm32 r4, 0x4678e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0xf4445515;
imm32 r7, 0x86e6f777;
R0.H = R6 - R0 (RND12);
R1.H = R6 - R1 (RND12);
R2.H = R6 - R2 (RND12);
R3.H = R6 - R3 (RND12);
R4.H = R6 - R4 (RND12);
R5.H = R6 - R5 (RND12);
R6.H = R6 - R6 (RND12);
R7.H = R6 - R7 (RND12);
CHECKREG r0, 0x7fff8911;
CHECKREG r1, 0x7fffAB1D;
CHECKREG r2, 0x80005515;
CHECKREG r3, 0x80007717;
CHECKREG r4, 0x8000E91B;
CHECKREG r5, 0x8000AF1D;
CHECKREG r6, 0x00005515;
CHECKREG r7, 0x7fffF777;
imm32 r0, 0xab678051;
imm32 r1, 0x2c89a26d;
imm32 r2, 0x34d455f5;
imm32 r3, 0x466e7717;
imm32 r4, 0x567f89bb;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x744e55a5;
imm32 r7, 0x8666ab77;
R0.H = R7 - R0 (RND12);
R1.H = R7 - R1 (RND12);
R2.H = R7 - R2 (RND12);
R3.H = R7 - R3 (RND12);
R4.H = R7 - R4 (RND12);
R5.H = R7 - R5 (RND12);
R6.H = R7 - R6 (RND12);
R7.H = R7 - R7 (RND12);
CHECKREG r0, 0x80008051;
CHECKREG r1, 0x8000A26D;
CHECKREG r2, 0x800055F5;
CHECKREG r3, 0x80007717;
CHECKREG r4, 0x800089BB;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x800055A5;
CHECKREG r7, 0x0000AB77;
imm32 r0, 0x15678901;
imm32 r1, 0x2789abad;
imm32 r2, 0x34445515;
imm32 r3, 0x466677d7;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445535;
imm32 r7, 0x86667747;
R6.H = R2 - R3 (RND12);
R1.H = R4 - R5 (RND12);
R5.H = R7 - R2 (RND12);
R3.H = R0 - R0 (RND12);
R0.H = R3 - R4 (RND12);
R2.H = R5 - R7 (RND12);
R7.H = R6 - R7 (RND12);
R4.H = R1 - R6 (RND12);
CHECKREG r0, 0x80008901;
CHECKREG r1, 0x8000ABAD;
CHECKREG r2, 0x99a35515;
CHECKREG r3, 0x000077D7;
CHECKREG r4, 0x0005891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x80005535;
CHECKREG r7, 0x999e7747;
imm32 r0, 0x15678121;
imm32 r1, 0x2789ab3d;
imm32 r2, 0x34445565;
imm32 r3, 0x4d667797;
imm32 r4, 0x567889ab;
imm32 r5, 0x67beabbd;
imm32 r6, 0x7b445515;
imm32 r7, 0x86d6e777;
R3.H = R4 - R0 (RND12);
R1.H = R6 - R3 (RND12);
R4.H = R3 - R2 (RND12);
R6.H = R7 - R1 (RND12);
R2.H = R5 - R4 (RND12);
R7.H = R2 - R7 (RND12);
R0.H = R1 - R6 (RND12);
R5.H = R0 - R5 (RND12);
CHECKREG r0, 0x7fff8121;
CHECKREG r1, 0xb44eAB3D;
CHECKREG r2, 0x80005565;
CHECKREG r3, 0x7fff7797;
CHECKREG r4, 0x7fff89AB;
CHECKREG r5, 0x7fffABBD;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x9297E777;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,686 | sim/testsuite/bfin/c_dsp32alu_rrpmmp.s | //Original:/testcases/core/c_dsp32alu_rrpmmp/c_dsp32alu_rrpmmp.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) amod0
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x67889b1d;
imm32 r2, 0x74445915;
imm32 r3, 0x86667797;
R0 = R0 +|- R0 , R7 = R0 -|+ R0;
R1 = R0 +|- R1 , R6 = R0 -|+ R1;
R2 = R0 +|- R2 , R5 = R0 -|+ R2;
R3 = R0 +|- R3 , R4 = R0 -|+ R3;
R4 = R0 +|- R4 , R3 = R0 -|+ R4;
R5 = R0 +|- R5 , R2 = R0 -|+ R5;
R6 = R0 +|- R6 , R1 = R0 -|+ R6;
R7 = R0 +|- R7 , R0 = R0 -|+ R7;
CHECKREG r0, 0xAACE1236;
CHECKREG r1, 0x67889B1D;
CHECKREG r2, 0x74445915;
CHECKREG r3, 0x86667797;
CHECKREG r4, 0xCF368869;
CHECKREG r5, 0xE158A6EB;
CHECKREG r6, 0xEE1464E3;
CHECKREG r7, 0xAACEEDCA;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x466e7717;
imm32 r0, 0x5567ee1b;
imm32 r1, 0x6789abed;
imm32 r2, 0x7444551e;
imm32 r3, 0x86e67777;
R0 = R1 +|- R0 , R7 = R1 -|+ R0;
R1 = R1 +|- R1 , R6 = R1 -|+ R1;
R2 = R1 +|- R2 , R5 = R1 -|+ R2;
R3 = R1 +|- R3 , R4 = R1 -|+ R3;
R4 = R1 +|- R4 , R3 = R1 -|+ R4;
R5 = R1 +|- R5 , R2 = R1 -|+ R5;
R6 = R1 +|- R6 , R1 = R1 -|+ R6;
R7 = R1 +|- R7 , R0 = R1 -|+ R7;
CHECKREG r0, 0xBCF0F1E2;
CHECKREG r1, 0xCF1257DA;
CHECKREG r2, 0x7444551E;
CHECKREG r3, 0x86E67777;
CHECKREG r4, 0x173E8889;
CHECKREG r5, 0x29E0AAE2;
CHECKREG r6, 0xCF12A826;
CHECKREG r7, 0xE134BDD2;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R2 +|- R0 , R7 = R2 -|+ R0;
R1 = R2 +|- R1 , R6 = R2 -|+ R1;
R2 = R2 +|- R2 , R5 = R2 -|+ R2;
R3 = R2 +|- R3 , R4 = R2 -|+ R3;
R4 = R2 +|- R4 , R3 = R2 -|+ R4;
R5 = R2 +|- R5 , R2 = R2 -|+ R5;
R6 = R2 +|- R6 , R1 = R2 -|+ R6;
R7 = R2 +|- R7 , R0 = R2 -|+ R7;
CHECKREG r0, 0xC9AB885A;
CHECKREG r1, 0xDBCDAA5C;
CHECKREG r2, 0xE888AA2A;
CHECKREG r3, 0x86667777;
CHECKREG r4, 0x4AAA8889;
CHECKREG r5, 0xE88855D6;
CHECKREG r6, 0xF543A9F8;
CHECKREG r7, 0x0765CBFA;
imm32 r0, 0x85678911;
imm32 r1, 0x2889ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5587891b;
imm32 r1, 0x6788ab1d;
imm32 r2, 0x74448515;
imm32 r3, 0x86667877;
R0 = R3 +|- R0 , R7 = R3 -|+ R0;
R1 = R3 +|- R1 , R6 = R3 -|+ R1;
R2 = R3 +|- R2 , R5 = R3 -|+ R2;
R3 = R3 +|- R3 , R4 = R3 -|+ R3;
R4 = R3 +|- R4 , R3 = R3 -|+ R4;
R5 = R3 +|- R5 , R2 = R3 -|+ R5;
R6 = R3 +|- R6 , R1 = R3 -|+ R6;
R7 = R3 +|- R7 , R0 = R3 -|+ R7;
CHECKREG r0, 0xDBEDF280;
CHECKREG r1, 0xEDEE1482;
CHECKREG r2, 0xFAAAEE7A;
CHECKREG r3, 0x0CCCF0EE;
CHECKREG r4, 0x0CCC0F12;
CHECKREG r5, 0x1EEEF362;
CHECKREG r6, 0x2BAACD5A;
CHECKREG r7, 0x3DABEF5C;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R4 +|- R0 , R7 = R4 -|+ R0;
R1 = R4 +|- R1 , R6 = R4 -|+ R1;
R2 = R4 +|- R2 , R5 = R4 -|+ R2;
R3 = R4 +|- R3 , R4 = R4 -|+ R3;
R4 = R4 +|- R4 , R3 = R4 -|+ R4;
R5 = R4 +|- R5 , R2 = R4 -|+ R5;
R6 = R4 +|- R6 , R1 = R4 -|+ R6;
R7 = R4 +|- R7 , R0 = R4 -|+ R7;
CHECKREG r0, 0x5567982D;
CHECKREG r1, 0x6789BA2F;
CHECKREG r2, 0x74446427;
CHECKREG r3, 0x00000D12;
CHECKREG r4, 0x0CCC0000;
CHECKREG r5, 0xA5549BD9;
CHECKREG r6, 0xB20F45D1;
CHECKREG r7, 0xC43167D3;
imm32 r0, 0x95678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x39445515;
imm32 r3, 0x46967717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74495515;
imm32 r3, 0x86669777;
R0 = R5 +|- R0 , R7 = R5 -|+ R0;
R1 = R5 +|- R1 , R6 = R5 -|+ R1;
R2 = R5 +|- R2 , R5 = R5 -|+ R2;
R3 = R5 +|- R3 , R4 = R5 -|+ R3;
R4 = R5 +|- R4 , R3 = R5 -|+ R4;
R5 = R5 +|- R5 , R2 = R5 -|+ R5;
R6 = R5 +|- R6 , R1 = R5 -|+ R6;
R7 = R5 +|- R7 , R0 = R5 -|+ R7;
CHECKREG r0, 0x122924F4;
CHECKREG r1, 0x244B46F6;
CHECKREG r2, 0x0000E1DC;
CHECKREG r3, 0x86667953;
CHECKREG r4, 0xDBB06889;
CHECKREG r5, 0x62160000;
CHECKREG r6, 0x9FE1B90A;
CHECKREG r7, 0xB203DB0C;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x86667777;
R0 = R6 +|- R0 , R7 = R6 -|+ R0;
R1 = R6 +|- R1 , R6 = R6 -|+ R1;
R2 = R6 +|- R2 , R5 = R6 -|+ R2;
R3 = R6 +|- R3 , R4 = R6 -|+ R3;
R4 = R6 +|- R4 , R3 = R6 -|+ R4;
R5 = R6 +|- R5 , R2 = R6 -|+ R5;
R6 = R6 +|- R6 , R1 = R6 -|+ R6;
R7 = R6 +|- R7 , R0 = R6 -|+ R7;
CHECKREG r0, 0x26364225;
CHECKREG r1, 0x0000C84E;
CHECKREG r2, 0x74441D63;
CHECKREG r3, 0x86663FC5;
CHECKREG r4, 0xEA4A8889;
CHECKREG r5, 0xFC6CAAEB;
CHECKREG r6, 0x70B00000;
CHECKREG r7, 0xBB2ABDDB;
imm32 r0, 0x67898911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3b445515;
imm32 r3, 0x46b67717;
imm32 r0, 0x5567891b;
imm32 r1, 0x678bab1d;
imm32 r2, 0x7444b515;
imm32 r3, 0x86667b77;
R0 = R7 +|- R0 , R7 = R7 -|+ R0;
R1 = R7 +|- R1 , R6 = R7 -|+ R1;
R2 = R7 +|- R2 , R5 = R7 -|+ R2;
R3 = R7 +|- R3 , R4 = R7 -|+ R3;
R4 = R7 +|- R4 , R3 = R7 -|+ R4;
R5 = R7 +|- R5 , R2 = R7 -|+ R5;
R6 = R7 +|- R6 , R1 = R7 -|+ R6;
R7 = R7 +|- R7 , R0 = R7 -|+ R7;
CHECKREG r0, 0x00008DEC;
CHECKREG r1, 0x678B3909;
CHECKREG r2, 0x74444301;
CHECKREG r3, 0x86660963;
CHECKREG r4, 0x45208489;
CHECKREG r5, 0x57424AEB;
CHECKREG r6, 0x63FB54E3;
CHECKREG r7, 0xCB860000;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34ee5515;
imm32 r3, 0x4666e717;
imm32 r0, 0x5567891b;
imm32 r1, 0x6789ae1d;
imm32 r2, 0x744455e5;
imm32 r3, 0x8666777e;
R4 = R2 +|- R5 , R3 = R2 -|+ R5 (S);
R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO);
R2 = R6 +|- R2 , R0 = R6 -|+ R2 (SCO);
R3 = R4 +|- R0 , R2 = R4 -|+ R0 (S);
R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO);
R6 = R1 +|- R7 , R1 = R1 -|+ R7 (SCO);
R5 = R0 +|- R4 , R7 = R0 -|+ R4 (S);
R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO);
CHECKREG r0, 0x7FFFEFB7;
CHECKREG r1, 0xFFFFE33B;
CHECKREG r2, 0x0000FAB1;
CHECKREG r3, 0x7FFF1B43;
CHECKREG r4, 0x534BFFFF;
CHECKREG r5, 0x7FFFE4BD;
CHECKREG r6, 0x7FFF0300;
CHECKREG r7, 0x0000FAB1;
imm32 r0, 0xff678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3f445515;
imm32 r3, 0x46f67717;
imm32 r0, 0x556f891b;
imm32 r1, 0x6789fb1d;
imm32 r2, 0x74445f15;
imm32 r3, 0x866677f7;
R4 = R3 +|- R3 , R5 = R3 -|+ R3 (SCO);
R1 = R6 +|- R1 , R6 = R6 -|+ R1 (SCO);
R6 = R1 +|- R4 , R4 = R1 -|+ R4 (S);
R7 = R4 +|- R2 , R0 = R4 -|+ R2 (S);
R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO);
R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO);
R5 = R7 +|- R7 , R3 = R7 -|+ R7 (SCO);
R0 = R0 +|- R0 , R2 = R0 -|+ R0 (SCO);
CHECKREG r0, 0x17760000;
CHECKREG r1, 0x66F87445;
CHECKREG r2, 0x7FFF0000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x7FFF07E3;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xFFFF07E3;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,072 | sim/testsuite/bfin/c_alu2op_log_r_sft.s | //Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp
// Spec Reference: alu2op logical right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
R1 >>= R0;
R2 >>= R0;
R3 >>= R0;
R4 >>= R0;
R5 >>= R0;
R6 >>= R0;
R7 >>= R0;
R4 >>= R0;
R0 >>= R0;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A2B3C4;
CHECKREG r3, 0x1A2B3C4D;
CHECKREG r4, 0x2159E26A;
CHECKREG r5, 0x4B3C4D5E;
CHECKREG r6, 0x53C4D5E6;
CHECKREG r7, 0x5C4D5E6F;
CHECKREG r0, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 >>= R1;
R2 >>= R1;
R3 >>= R1;
R4 >>= R1;
R5 >>= R1;
R6 >>= R1;
R7 >>= R1;
R1 >>= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 >>= R2;
R1 >>= R2;
R3 >>= R2;
R4 >>= R2;
R5 >>= R2;
R6 >>= R2;
R7 >>= R2;
R2 >>= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 >>= R3;
R1 >>= R3;
R2 >>= R3;
R4 >>= R3;
R5 >>= R3;
R6 >>= R3;
R7 >>= R3;
R3 >>= R3;
CHECKREG r0, 0x00;
CHECKREG r1, 0x0;
CHECKREG r2, 0x0;
CHECKREG r3, 0x0;
CHECKREG r4, 0x0;
CHECKREG r5, 0x0;
CHECKREG r6, 0x0;
CHECKREG r7, 0x0;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 >>= R4;
R2 >>= R4;
R3 >>= R4;
R0 >>= R4;
R5 >>= R4;
R6 >>= R4;
R7 >>= R4;
R4 >>= R4;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00002468;
CHECKREG r2, 0x0000468A;
CHECKREG r3, 0x000068AC;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00012CF1;
CHECKREG r6, 0x00014F13;
CHECKREG r7, 0x00017135;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 >>= R5;
R1 >>= R5;
R2 >>= R5;
R3 >>= R5;
R4 >>= R5;
R6 >>= R5;
R7 >>= R5;
R5 >>= R5;
CHECKREG r0, 0x000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x0000;
CHECKREG r3, 0x0000;
CHECKREG r4, 0x0000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x0000;
CHECKREG r7, 0x0000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 >>= R6;
R1 >>= R6;
R2 >>= R6;
R3 >>= R6;
R4 >>= R6;
R5 >>= R6;
R7 >>= R6;
R6 >>= R6;
CHECKREG r0, 0x00000051;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x000000B1;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000095;
CHECKREG r5, 0x00000086;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 >>= R7;
R1 >>= R7;
R2 >>= R7;
R3 >>= R7;
R4 >>= R7;
R5 >>= R7;
R6 >>= R7;
R7 >>= R7;
CHECKREG r0, 0x00;
CHECKREG r1, 0x00;
CHECKREG r2, 0x00;
CHECKREG r3, 0x00;
CHECKREG r4, 0x00;
CHECKREG r5, 0x00;
CHECKREG r6, 0x00;
CHECKREG r7, 0x00;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,800 | sim/testsuite/bfin/c_dsp32mult_dr.s | //Original:/testcases/core/c_dsp32mult_dr/c_dsp32mult_dr.dsp
// Spec Reference: dsp32mult single dr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L;
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H;
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L;
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H;
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L;
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H;
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L;
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H;
CHECKREG r0, 0x39FA39FA;
CHECKREG r1, 0x24C2CEF5;
CHECKREG r2, 0xE9C910A6;
CHECKREG r3, 0x12CA0A8E;
CHECKREG r4, 0x39FA39FA;
CHECKREG r5, 0x369EB722;
CHECKREG r6, 0x369EB722;
CHECKREG r7, 0x33735B96;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L;
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H;
R6.H = R3.L * R2.H, R6.L = R3.L * R2.L;
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H;
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L;
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H;
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L;
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H;
CHECKREG r0, 0xFF31FF31;
CHECKREG r1, 0x00B500B5;
CHECKREG r2, 0xF51DF51D;
CHECKREG r3, 0x09860986;
CHECKREG r4, 0xF51DF51D;
CHECKREG r5, 0x3FAEEF41;
CHECKREG r6, 0xF8DB1B2D;
CHECKREG r7, 0x29CE29CE;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L;
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H;
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L;
R3.H = R5.H * R5.L, R3.L = R5.H * R5.H;
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L;
R5.H = R4.H * R5.L, R5.L = R4.L * R5.H;
R6.H = R5.H * R4.L, R6.L = R5.H * R4.L;
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H;
CHECKREG r0, 0x33491B2A;
CHECKREG r1, 0x0E7AF852;
CHECKREG r2, 0xF852F852;
CHECKREG r3, 0xFDD5022C;
CHECKREG r4, 0x33491B2A;
CHECKREG r5, 0xF955038A;
CHECKREG r6, 0xFE96FE96;
CHECKREG r7, 0xFFD10059;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L;
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H;
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L;
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H;
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L;
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H;
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L;
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H;
CHECKREG r0, 0x7FE82A4A;
CHECKREG r1, 0xEDBCF57F;
CHECKREG r2, 0xEDBCF57F;
CHECKREG r3, 0x029C029C;
CHECKREG r4, 0x12400609;
CHECKREG r5, 0x029B029B;
CHECKREG r6, 0x7FE82A4A;
CHECKREG r7, 0x1243060A;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0.H = R0.L * R7.H (M), R0.L = R0.H * R7.L;
R1.H = R1.H * R6.H, R1.L = R1.H * R6.H;
R2.H = R2.H * R5.L, R2.L = R2.L * R5.L;
R3.H = R3.H * R4.L (M), R3.L = R3.H * R4.L;
R4.H = R4.L * R3.L, R4.L = R4.L * R3.H;
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L;
R6.H = R6.L * R1.H, R6.L = R6.L * R1.L;
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H;
CHECKREG r0, 0xF99C0A92;
CHECKREG r1, 0xFFFBFFFB;
CHECKREG r2, 0xFB31E621;
CHECKREG r3, 0x0005FFFE;
CHECKREG r4, 0x0001FFFE;
CHECKREG r5, 0xFCA1FCA1;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0182FF16;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R0.H = R7.H * R0.H, R0.L = R7.L * R0.L;
R1.H = R6.H * R1.L (M), R1.L = R6.H * R1.L;
R2.H = R5.H * R2.H, R2.L = R5.L * R2.L;
R3.H = R4.L * R3.H, R3.L = R4.H * R3.L;
R4.H = R3.H * R4.H, R4.L = R3.L * R4.L;
R5.H = R2.H * R5.L (M), R5.L = R2.H * R5.L;
R6.H = R1.L * R6.L, R6.L = R1.L * R6.H;
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H;
CHECKREG r0, 0xF19A4F2D;
CHECKREG r1, 0x00040008;
CHECKREG r2, 0x028DEDD5;
CHECKREG r3, 0xFFF9FFFA;
CHECKREG r4, 0x00060005;
CHECKREG r5, 0x0255FF8F;
CHECKREG r6, 0x00010000;
CHECKREG r7, 0x0B4EFDF2;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H;
R3.H = R1.H * R7.H (M), R3.L = R1.L * R7.L;
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H;
R1.H = R3.H * R1.L, R1.L = R3.L * R1.H;
R4.H = R4.L * R2.L, R4.L = R4.L * R2.H;
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L;
R6.H = R6.H * R4.L (M), R6.L = R6.L * R4.H;
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H;
CHECKREG r0, 0x0005FFA9;
CHECKREG r1, 0xFD80E154;
CHECKREG r2, 0x005F0008;
CHECKREG r3, 0xFC0E4707;
CHECKREG r4, 0xFFF9FFAB;
CHECKREG r5, 0x00B70940;
CHECKREG r6, 0x000C0000;
CHECKREG r7, 0x0819001A;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H;
R6.H = R6.H * R3.L (M), R6.L = R6.L * R3.H;
R0.H = R7.L * R4.H, R0.L = R7.H * R4.H;
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L;
R2.H = R1.H * R6.L (M), R2.L = R1.L * R6.H;
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L;
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H;
R7.H = R4.L * R1.L, R7.L = R4.L * R1.H;
CHECKREG r0, 0xF3ECFE08;
CHECKREG r1, 0xFFBE0044;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x0000FFFF;
CHECKREG r4, 0xF234FD56;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFFFF0001;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,982 | sim/testsuite/bfin/se_loop_nest_ppm_1.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_1/se_loop_nest_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x4 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
LSETUP ( l0s , l0s ) LC1 = P1;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
LSETUP ( l1s , l1e ) LC1 = P1;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
LSETUP ( l2s , l2e ) LC1 = P1;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
LSETUP ( l3s , l3e ) LC1 = P1;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
LSETUP ( l4s , l4e ) LC1 = P1;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
LSETUP ( l5s , l5e ) LC1 = P1;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC1 = P0;
LSETUP ( l6s , l6e ) LC1 = P1;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 4,076 | sim/testsuite/bfin/c_ccflag_pr_imm3_uu.s | //Original:/testcases/core/c_ccflag_pr_imm3_uu/c_ccflag_pr_imm3_uu.dsp
// Spec Reference: ccflag pr-imm3 (uu)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00000001;
imm32 p1, 0x00000001;
imm32 p2, 0x00000002;
imm32 p3, 0x00000003;
imm32 p4, 0x00000004;
imm32 p5, 0x00000005;
imm32 sp, 0x00000006;
imm32 fp, 0x00000007;
R0 = 0;
ASTAT = R0;
// positive preg EQUAL to positive imm3
CC = P1 == 1;
R0 = ASTAT;
CC = P1 < 1 (IU);
R1 = ASTAT;
CC = P1 <= 1 (IU);
R2 = ASTAT;
CC = P2 == 2;
R3 = ASTAT;
CC = P2 < 2 (IU);
R4 = ASTAT;
CC = P2 <= 2 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = P3 == 3;
R0 = ASTAT;
CC = P3 < 3 (IU);
R1 = ASTAT;
CC = P3 <= 3 (IU);
R2 = ASTAT;
CC = P4 == 3;
R3 = ASTAT;
CC = P4 < 4 (IU);
R4 = ASTAT;
CC = P4 <= 4 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = P5 == 3;
R0 = ASTAT;
CC = P5 < 5 (IU);
R1 = ASTAT;
CC = P5 <= 5 (IU);
R2 = ASTAT;
CC = SP == 3;
R3 = ASTAT;
CC = SP < 6 (IU);
R4 = ASTAT;
CC = SP <= 6 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000020;
CC = FP == 3;
R5 = ASTAT;
CC = FP < 7 (IU);
R6 = ASTAT;
CC = FP <= 7 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000020;
// positive preg GREATER than positive imm3
CC = P1 == 0;
R0 = ASTAT;
CC = P1 < 0 (IU);
R1 = ASTAT;
CC = P1 <= 0 (IU);
R2 = ASTAT;
CC = P2 == 1;
R3 = ASTAT;
CC = P2 < 1 (IU);
R4 = ASTAT;
CC = P2 <= 1 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P3 == 2;
R0 = ASTAT;
CC = P3 < 2 (IU);
R1 = ASTAT;
CC = P3 <= 2 (IU);
R2 = ASTAT;
CC = P4 == 3;
R3 = ASTAT;
CC = P4 < 3 (IU);
R4 = ASTAT;
CC = P4 <= 3 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = P5 == 3;
R0 = ASTAT;
CC = P5 < 4 (IU);
R1 = ASTAT;
CC = P5 <= 4 (IU);
R2 = ASTAT;
CC = SP == 3;
R3 = ASTAT;
CC = SP < 5 (IU);
R4 = ASTAT;
CC = SP <= 5 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CC = FP == 3;
R5 = ASTAT;
CC = FP < 6 (IU);
R6 = ASTAT;
CC = FP <= 6 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// positive preg LESS than positive imm3
imm32 p1, 0x00000000;
imm32 p2, 0x00000001;
imm32 p3, 0x00000002;
imm32 p4, 0x00000003;
imm32 p5, 0x00000004;
imm32 sp, 0x00000005;
imm32 fp, 0x00000006;
CC = P1 == 2;
R0 = ASTAT;
CC = P1 < 2 (IU);
R1 = ASTAT;
CC = P1 <= 2 (IU);
R2 = ASTAT;
CC = P2 == 3;
R3 = ASTAT;
CC = P2 < 3 (IU);
R4 = ASTAT;
CC = P2 <= 3 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = P3 == 3;
R0 = ASTAT;
CC = P3 < 4 (IU);
R1 = ASTAT;
CC = P3 <= 4 (IU);
R2 = ASTAT;
CC = P4 == 3;
R3 = ASTAT;
CC = P4 < 5 (IU);
R4 = ASTAT;
CC = P4 <= 5 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = P5 == 3;
R0 = ASTAT;
CC = P5 < 6 (IU);
R1 = ASTAT;
CC = P5 <= 6 (IU);
R2 = ASTAT;
CC = SP == 3;
R3 = ASTAT;
CC = SP < 7 (IU);
R4 = ASTAT;
CC = SP <= 7 (IU);
R5 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000020;
CHECKREG r5, 0x00000020;
CC = FP == 3;
R5 = ASTAT;
CC = FP < 7 (IU);
R6 = ASTAT;
CC = FP <= 7 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000020;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,480 | sim/testsuite/bfin/c_seq_ex2_raise_mmr_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmr_mvpop/c_seq_ex2_raise_mmr_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
// [--sp] = (r7-r0);
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
LD32(r0, 0x55552345);
RAISE 2; // RTN
[ P1 ] = R0;
// jump LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
CSYNC;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
RAISE 6; // RTI
R0 = [ P1 ];
// jump LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
RAISE 8; // RTI
R0 = [ P1 ];
// jump LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
CSYNC;
CHECKREG(r0, 0x55552345); // CHECKREG can not be skipped
CHECKREG(r1, 0x00000012); // so they cannot appear here
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
//CHECKREG(r0, 0x55552345);
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 5,477 | sim/testsuite/bfin/c_dsp32mult_dr_mix.s | //Original:/testcases/core/c_dsp32mult_dr_mix/c_dsp32mult_dr_mix.dsp
// Spec Reference: dsp32mult single dr (mix) u i t is tu ih
# mach: bfin
.include "testutils.inc"
start
// test the default (signed fraction) rounding U=0 I=0 T=0
imm32 r0, 0xab235615;
imm32 r1, 0xcfba5117;
imm32 r2, 0x13246715;
imm32 r3, 0x00060017;
imm32 r4, 0x90abcd19;
imm32 r5, 0x10acef1b;
imm32 r6, 0x000c001d;
imm32 r7, 0x1246701f;
R2.H = R1.L * R0.L, R2.L = R1.L * R0.L;
R3.L = R1.L * R0.H (ISS2);
R4.H = R1.H * R0.L;
R5.H = R1.L * R0.H (M), R5.L = R1.H * R0.H;
R6.H = R1.H * R0.L, R6.L = R1.L * R0.L;
R7.H = R1.H * R0.H (M), R7.L = R1.H * R0.H;
CHECKREG r2, 0x36893689;
CHECKREG r3, 0x00068000;
CHECKREG r4, 0xDF89CD19;
CHECKREG r5, 0x36352001;
CHECKREG r6, 0xDF893689;
CHECKREG r7, 0xDFBB2001;
// test the signed integer U=0 I=1
imm32 r0, 0x8b235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3246725;
imm32 r3, 0x00060027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c002d;
imm32 r7, 0xd246702f;
R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (TFU);
R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (IS);
R4.H = R1.L * R0.L, R4.L = R1.H * R0.L (ISS2);
R5.H = R1.L * R0.L, R5.L = R1.H * R0.H (IS);
R6.H = R1.L * R0.H, R6.L = R1.L * R0.L (IS);
R7.H = R1.L * R0.H, R7.L = R1.L * R0.H (IH);
CHECKREG r0, 0x8B235625;
CHECKREG r1, 0x9FBA5127;
CHECKREG r2, 0x1B4E1B4E;
CHECKREG r3, 0x7FFF8000;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x80007FFF;
CHECKREG r7, 0xDAF4DAF4;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0.H = R3.L * R2.H, R0.L = R3.H * R2.L (IS);
R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (ISS2);
R4.H = R3.H * R2.L, R4.L = R3.L * R2.L (IS);
R5.H = R3.H * R2.L, R5.L = R3.L * R2.H (IS);
R6.H = R3.H * R2.L, R6.L = R3.H * R2.L (IH);
R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (IS);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x1324B735;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0x7FFF8000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x1FD71FD7;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R0.H = R5.H * R4.H, R0.L = R5.L * R4.L (IS);
R1.H = R5.H * R4.H, R1.L = R5.L * R4.H (ISS2);
R2.H = R5.H * R4.H, R2.L = R5.H * R4.L (IS);
R3.H = R5.H * R4.H, R3.L = R5.H * R4.H (IS);
R4.H = R6.H * R7.L, R4.L = R6.H * R7.L (IH);
R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (IS);
CHECKREG r0, 0x80007FFF;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0xDCE8DCE8;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0xB00C005D;
CHECKREG r7, 0x1246705F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
// test the unsigned U=1
R2.H = R1.L * R0.L, R2.L = R1.L * R0.L (FU);
R3.H = R1.L * R0.L, R3.L = R1.L * R0.H (ISS2);
R4.H = R7.L * R6.L, R4.L = R7.H * R6.L (FU);
R5.H = R3.L * R2.L (M), R5.L = R3.H * R2.H (FU);
R6.H = R5.L * R4.H, R6.L = R5.L * R4.L (TFU);
R7.H = R5.L * R4.H, R7.L = R5.L * R4.H (FU);
CHECKREG r0, 0xBB235666;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0x1B791B79;
CHECKREG r3, 0x7FFF8000;
CHECKREG r4, 0x4D7C0C98;
CHECKREG r5, 0xF2440DBC;
CHECKREG r6, 0x042800AC;
CHECKREG r7, 0x04280428;
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0.H = R5.L * R4.H, R0.L = R5.H * R4.L (FU);
R1.H = R3.L * R2.H, R1.L = R3.H * R2.H (IU);
R2.H = R7.H * R6.L, R2.L = R7.L * R6.L (TFU);
R3.H = R5.H * R4.L, R3.L = R5.L * R4.H (FU);
R6.H = R1.H * R0.L, R6.L = R1.H * R0.L (IH);
R7.H = R3.H * R2.L, R7.L = R3.H * R2.H (FU);
CHECKREG r0, 0x7E810D5A;
CHECKREG r1, 0x85FC72D8;
CHECKREG r2, 0x0000000C;
CHECKREG r3, 0x0D5A7E81;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0xF9A3F9A3;
CHECKREG r7, 0x00010000;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R2.H = R1.H * R0.H, R2.L = R1.L * R0.L (TFU);
R3.H = R1.H * R0.L, R3.L = R1.L * R0.H (FU);
R4.H = R6.H * R7.H, R4.L = R6.H * R7.L (ISS2);
R5.H = R6.L * R7.H, R5.L = R6.H * R7.H (FU);
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x8ADD1CAC;
CHECKREG r3, 0x49663640;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x00EE0001;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x1246700F;
// test the ROUNDING only on signed fraction T=1
imm32 r0, 0xab235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246700f;
R2.H = R1.L * R0.L (M), R2.L = R1.L * R0.H (IS);
R3.H = R1.H * R0.L (M), R3.L = R1.H * R0.H (FU);
R0.H = R3.L * R2.L (M), R0.L = R3.H * R2.H (T);
R1.H = R5.L * R4.H (M), R1.L = R5.L * R4.L (S2RND);
R4.H = R7.H * R6.H (M), R4.L = R7.L * R6.L (IU);
R5.H = R7.L * R6.H (M), R5.L = R7.H * R6.L (TFU);
R6.H = R5.H * R4.L (M), R6.L = R5.L * R4.H (ISS2);
R7.H = R3.L * R2.H (M), R7.L = R3.L * R2.L (IH);
CHECKREG r0, 0xC56FEFB2;
CHECKREG r1, 0xEDC10CDB;
CHECKREG r2, 0x7FFF8000;
CHECKREG r3, 0xEFB28ADE;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x7FFF0000;
CHECKREG r7, 0xC56F3A91;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,849 | sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s | //Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp
// Spec Reference: compi2opd dregs = imm7 positive
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
CHECKREG r0, 0;
CHECKREG r1, 1;
CHECKREG r2, 2;
CHECKREG r3, 3;
CHECKREG r4, 4;
CHECKREG r5, 5;
CHECKREG r6, 6;
CHECKREG r7, 7;
R0 = 8;
R1 = 9;
R2 = 10;
R3 = 11;
R4 = 12;
R5 = 13;
R6 = 14;
R7 = 15;
CHECKREG r0, 8;
CHECKREG r1, 9;
CHECKREG r2, 10;
CHECKREG r3, 11;
CHECKREG r4, 12;
CHECKREG r5, 13;
CHECKREG r6, 14;
CHECKREG r7, 15;
R0 = 16;
R1 = 17;
R2 = 18;
R3 = 19;
R4 = 20;
R5 = 21;
R6 = 22;
R7 = 23;
CHECKREG r0, 16;
CHECKREG r1, 17;
CHECKREG r2, 18;
CHECKREG r3, 19;
CHECKREG r4, 20;
CHECKREG r5, 21;
CHECKREG r6, 22;
CHECKREG r7, 23;
R0 = 24;
R1 = 25;
R2 = 26;
R3 = 27;
R4 = 28;
R5 = 29;
R6 = 30;
R7 = 31;
CHECKREG r0, 24;
CHECKREG r1, 25;
CHECKREG r2, 26;
CHECKREG r3, 27;
CHECKREG r4, 28;
CHECKREG r5, 29;
CHECKREG r6, 30;
CHECKREG r7, 31;
R0 = 32;
R1 = 33;
R2 = 34;
R3 = 35;
R4 = 36;
R5 = 37;
R6 = 38;
R7 = 39;
CHECKREG r0, 32;
CHECKREG r1, 33;
CHECKREG r2, 34;
CHECKREG r3, 35;
CHECKREG r4, 36;
CHECKREG r5, 37;
CHECKREG r6, 38;
CHECKREG r7, 39;
R0 = 40;
R1 = 41;
R2 = 42;
R3 = 43;
R4 = 44;
R5 = 45;
R6 = 46;
R7 = 47;
CHECKREG r0, 40;
CHECKREG r1, 41;
CHECKREG r2, 42;
CHECKREG r3, 43;
CHECKREG r4, 44;
CHECKREG r5, 45;
CHECKREG r6, 46;
CHECKREG r7, 47;
R0 = 48;
R1 = 49;
R2 = 50;
R3 = 51;
R4 = 52;
R5 = 53;
R6 = 54;
R7 = 55;
CHECKREG r0, 48;
CHECKREG r1, 49;
CHECKREG r2, 50;
CHECKREG r3, 51;
CHECKREG r4, 52;
CHECKREG r5, 53;
CHECKREG r6, 54;
CHECKREG r7, 55;
R0 = 56;
R1 = 57;
R2 = 58;
R3 = 59;
R4 = 60;
R5 = 61;
R6 = 62;
R7 = 63;
CHECKREG r0, 56;
CHECKREG r1, 57;
CHECKREG r2, 58;
CHECKREG r3, 59;
CHECKREG r4, 60;
CHECKREG r5, 61;
CHECKREG r6, 62;
CHECKREG r7, 63;
pass
|
tactcomplabs/xbgas-binutils-gdb | 8,752 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY imm5)
// RLx by imm5
imm32 r0, 0x00100a00;
imm32 r1, 0x00100a01;
imm32 r2, 0x00100a02;
imm32 r3, 0x00100a03;
imm32 r4, 0x00100a04;
imm32 r5, 0x00100a05;
imm32 r6, 0x00100a06;
imm32 r7, 0x00100a07;
R7.L = R0.L << 0;
R0.L = R1.L << 1;
R1.L = R2.L << 2;
R2.L = R3.L << 3;
R3.L = R4.L << 4;
R4.L = R5.L << 5;
R5.L = R6.L << 6;
R6.L = R7.L << 7;
CHECKREG r1, 0x00102808;
CHECKREG r0, 0x00101402;
CHECKREG r2, 0x00105018;
CHECKREG r3, 0x0010A040;
CHECKREG r4, 0x001040A0;
CHECKREG r5, 0x00108180;
CHECKREG r6, 0x00100000;
CHECKREG r7, 0x00100A00;
imm32 r0, 0x00200018;
imm32 r1, 0x00200019;
imm32 r2, 0x0020001a;
imm32 r3, 0x0020001b;
imm32 r4, 0x0020001c;
imm32 r5, 0x0020001d;
imm32 r6, 0x0020001e;
imm32 r7, 0x0020001f;
R2.L = R0.L << 8;
R3.L = R1.L << 9;
R4.L = R2.L << 10;
R5.L = R3.L << 11;
R6.L = R4.L << 12;
R7.L = R5.L << 13;
R0.L = R6.L << 14;
R1.L = R7.L << 15;
CHECKREG r0, 0x00200000;
CHECKREG r1, 0x00200000;
CHECKREG r2, 0x00201800;
CHECKREG r3, 0x00203200;
CHECKREG r4, 0x00200000;
CHECKREG r5, 0x00200000;
CHECKREG r6, 0x00200000;
CHECKREG r7, 0x00200000;
imm32 r0, 0x05002001;
imm32 r1, 0x05002001;
imm32 r2, 0x0500000f;
imm32 r3, 0x05002003;
imm32 r4, 0x05002004;
imm32 r5, 0x05002005;
imm32 r6, 0x05002006;
imm32 r7, 0x05002007;
R3.L = R0.L << 0;
R4.L = R1.L << 1;
R5.L = R2.L << 2;
R6.L = R3.L << 3;
R7.L = R4.L << 4;
R0.L = R5.L << 5;
R1.L = R6.L << 6;
R2.L = R7.L << 7;
CHECKREG r0, 0x05000780;
CHECKREG r1, 0x05000200;
CHECKREG r2, 0x05001000;
CHECKREG r3, 0x05002001;
CHECKREG r4, 0x05004002;
CHECKREG r5, 0x0500003C;
CHECKREG r6, 0x05000008;
CHECKREG r7, 0x05000020;
imm32 r0, 0x03000031;
imm32 r1, 0x03000031;
imm32 r2, 0x03000032;
imm32 r3, 0x03000030;
imm32 r4, 0x03000034;
imm32 r5, 0x03000035;
imm32 r6, 0x03000036;
imm32 r7, 0x03000037;
R4.L = R0.L << 8;
R5.L = R1.L << 9;
R6.L = R2.L << 10;
R7.L = R3.L << 11;
R0.L = R4.L << 12;
R1.L = R5.L << 13;
R2.L = R6.L << 14;
R3.L = R7.L << 15;
CHECKREG r0, 0x03000000;
CHECKREG r1, 0x03000000;
CHECKREG r2, 0x03000000;
CHECKREG r3, 0x03000000;
CHECKREG r4, 0x03003100;
CHECKREG r5, 0x03006200;
CHECKREG r6, 0x0300C800;
CHECKREG r7, 0x03008000;
// RHx by RLx
imm32 r0, 0x03000000;
imm32 r1, 0x03000000;
imm32 r2, 0x03000000;
imm32 r3, 0x03000000;
imm32 r4, 0x03003100;
imm32 r5, 0x03006200;
imm32 r6, 0x0300C800;
imm32 r7, 0x03008000;
R5.L = R0.H << 0;
R6.L = R1.H << 1;
R7.L = R2.H << 2;
R0.L = R3.H << 3;
R1.L = R4.H << 4;
R2.L = R5.H << 5;
R3.L = R6.H << 6;
R4.L = R7.H << 7;
CHECKREG r0, 0x03001800;
CHECKREG r1, 0x03003000;
CHECKREG r2, 0x03006000;
CHECKREG r3, 0x0300C000;
CHECKREG r4, 0x03008000;
CHECKREG r5, 0x03000300;
CHECKREG r6, 0x03000600;
CHECKREG r7, 0x03000C00;
imm32 r0, 0x05018000;
imm32 r1, 0x05018001;
imm32 r2, 0x05028000;
imm32 r3, 0x05038000;
imm32 r4, 0x05048000;
imm32 r5, 0x05058000;
imm32 r6, 0x05068000;
imm32 r7, 0x05078000;
R6.L = R0.H << 8;
R7.L = R1.H << 9;
R0.L = R2.H << 10;
R1.L = R3.H << 11;
R2.L = R4.H << 12;
R3.L = R5.H << 13;
R4.L = R6.H << 14;
R5.L = R7.H << 15;
CHECKREG r0, 0x05010800;
CHECKREG r1, 0x05011800;
CHECKREG r2, 0x05024000;
CHECKREG r3, 0x0503A000;
CHECKREG r4, 0x05048000;
CHECKREG r5, 0x05058000;
CHECKREG r6, 0x05060100;
CHECKREG r7, 0x05070200;
imm32 r0, 0x60019000;
imm32 r1, 0x60019000;
imm32 r2, 0x6002900f;
imm32 r3, 0x60039000;
imm32 r4, 0x60049000;
imm32 r5, 0x60059000;
imm32 r6, 0x60069000;
imm32 r7, 0x60079000;
R7.L = R0.H << 0;
R0.L = R1.H << 1;
R1.L = R2.H << 2;
R2.L = R3.H << 3;
R3.L = R4.H << 4;
R4.L = R5.H << 5;
R5.L = R6.H << 6;
R6.L = R7.H << 7;
CHECKREG r0, 0x6001C002;
CHECKREG r1, 0x60018008;
CHECKREG r2, 0x60020018;
CHECKREG r3, 0x60030040;
CHECKREG r4, 0x600400A0;
CHECKREG r5, 0x60050180;
CHECKREG r6, 0x60060380;
CHECKREG r7, 0x60076001;
imm32 r0, 0x70010001;
imm32 r1, 0x70010001;
imm32 r2, 0x70020002;
imm32 r3, 0x77030010;
imm32 r4, 0x70040004;
imm32 r5, 0x70050005;
imm32 r6, 0x70060006;
imm32 r7, 0x70070007;
R0.L = R0.H << 8;
R1.L = R1.H << 9;
R2.L = R2.H << 10;
R3.L = R3.H << 11;
R4.L = R4.H << 12;
R5.L = R5.H << 13;
R6.L = R6.H << 14;
R7.L = R7.H << 15;
CHECKREG r0, 0x70010100;
CHECKREG r1, 0x70010200;
CHECKREG r2, 0x70020800;
CHECKREG r3, 0x77031800;
CHECKREG r4, 0x70044000;
CHECKREG r5, 0x7005A000;
CHECKREG r6, 0x70068000;
CHECKREG r7, 0x70078000;
// d_hi = lshft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0xa8000000;
imm32 r1, 0xa8000001;
imm32 r2, 0xa8000002;
imm32 r3, 0xa8000003;
imm32 r4, 0xa8000004;
imm32 r5, 0xa8000005;
imm32 r6, 0xa8000006;
imm32 r7, 0xa8000007;
R0.H = R0.L << 0;
R1.H = R1.L << 1;
R2.H = R2.L << 2;
R3.H = R3.L << 3;
R4.H = R4.L << 4;
R5.H = R5.L << 5;
R6.H = R6.L << 6;
R7.H = R7.L << 7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00080002;
CHECKREG r3, 0x00180003;
CHECKREG r4, 0x00400004;
CHECKREG r5, 0x00A00005;
CHECKREG r6, 0x01800006;
CHECKREG r7, 0x03800007;
imm32 r0, 0xf0090001;
imm32 r1, 0xf0090001;
imm32 r2, 0xf0090002;
imm32 r3, 0xf0090003;
imm32 r4, 0xf0090004;
imm32 r5, 0xf0090005;
imm32 r6, 0xf0000006;
imm32 r7, 0xf0000007;
R1.H = R0.L << 8;
R2.H = R1.L << 9;
R3.H = R2.L << 10;
R4.H = R3.L << 11;
R5.H = R4.L << 12;
R6.H = R5.L << 13;
R7.H = R6.L << 14;
R0.H = R7.L << 15;
CHECKREG r1, 0x01000001;
CHECKREG r2, 0x02000002;
CHECKREG r3, 0x08000003;
CHECKREG r4, 0x18000004;
CHECKREG r5, 0x40000005;
CHECKREG r6, 0xA0000006;
CHECKREG r7, 0x80000007;
CHECKREG r0, 0x80000001;
imm32 r0, 0x07000001;
imm32 r1, 0x07000001;
imm32 r2, 0x0700000f;
imm32 r3, 0x07000003;
imm32 r4, 0x07000004;
imm32 r5, 0x07000005;
imm32 r6, 0x07000006;
imm32 r7, 0x07000007;
R3.H = R0.L << 0;
R4.H = R1.L << 1;
R5.H = R2.L << 2;
R6.H = R3.L << 3;
R7.H = R4.L << 4;
R0.H = R5.L << 5;
R1.H = R6.L << 6;
R2.H = R7.L << 7;
CHECKREG r0, 0x00A00001;
CHECKREG r1, 0x01800001;
CHECKREG r2, 0x0380000F;
CHECKREG r3, 0x00010003;
CHECKREG r4, 0x00020004;
CHECKREG r5, 0x003C0005;
CHECKREG r6, 0x00180006;
CHECKREG r7, 0x00400007;
imm32 r0, 0x00000501;
imm32 r1, 0x00000501;
imm32 r2, 0x00000502;
imm32 r3, 0x00000510;
imm32 r4, 0x00000504;
imm32 r5, 0x00000505;
imm32 r6, 0x00000506;
imm32 r7, 0x00000507;
R4.H = R0.L << 8;
R5.H = R1.L << 9;
R6.H = R2.L << 10;
R7.H = R3.L << 11;
R0.H = R4.L << 12;
R1.H = R5.L << 13;
R2.H = R6.L << 14;
R3.H = R7.L << 15;
CHECKREG r0, 0x40000501;
CHECKREG r1, 0xA0000501;
CHECKREG r2, 0x80000502;
CHECKREG r3, 0x80000510;
CHECKREG r4, 0x01000504;
CHECKREG r5, 0x02000505;
CHECKREG r6, 0x08000506;
CHECKREG r7, 0x80000507;
imm32 r0, 0x00a00800;
imm32 r1, 0x00a10800;
imm32 r2, 0x00a20800;
imm32 r3, 0x00a30800;
imm32 r4, 0x00a40800;
imm32 r5, 0x00a50800;
imm32 r6, 0x00a60800;
imm32 r7, 0x00a70800;
R5.H = R0.H << 0;
R6.H = R1.H << 1;
R7.H = R2.H << 2;
R0.H = R3.H << 3;
R1.H = R4.H << 4;
R2.H = R5.H << 5;
R3.H = R6.H << 6;
R4.H = R7.H << 7;
CHECKREG r0, 0x05180800;
CHECKREG r1, 0x0A400800;
CHECKREG r2, 0x14000800;
CHECKREG r3, 0x50800800;
CHECKREG r4, 0x44000800;
CHECKREG r5, 0x00A00800;
CHECKREG r6, 0x01420800;
CHECKREG r7, 0x02880800;
imm32 r0, 0x0c010000;
imm32 r1, 0x0c010001;
imm32 r2, 0x0c020000;
imm32 r3, 0x0c030000;
imm32 r4, 0x0c040000;
imm32 r5, 0x0c050000;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c070000;
R6.H = R0.H << 8;
R7.H = R1.H << 9;
R0.H = R2.H << 10;
R1.H = R3.H << 11;
R2.H = R4.H << 12;
R3.H = R5.H << 13;
R4.H = R6.H << 14;
R5.H = R7.H << 15;
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x18000001;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0xA0000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x01000000;
CHECKREG r7, 0x02000000;
imm32 r0, 0x00b10000;
imm32 r1, 0x00b10000;
imm32 r2, 0x00b2000f;
imm32 r3, 0x00b30000;
imm32 r4, 0x00b40000;
imm32 r5, 0x00b50000;
imm32 r6, 0x00b60000;
imm32 r7, 0x00b70000;
R7.L = R0.H << 0;
R0.L = R1.H << 1;
R1.L = R2.H << 2;
R2.L = R3.H << 3;
R3.L = R4.H << 4;
R4.L = R5.H << 5;
R5.L = R6.H << 6;
R6.L = R7.H << 7;
CHECKREG r0, 0x00B10162;
CHECKREG r1, 0x00B102C8;
CHECKREG r2, 0x00B20598;
CHECKREG r3, 0x00B30B40;
CHECKREG r4, 0x00B416A0;
CHECKREG r5, 0x00B52D80;
CHECKREG r6, 0x00B65B80;
CHECKREG r7, 0x00B700B1;
imm32 r0, 0x0a010700;
imm32 r1, 0x0a010700;
imm32 r2, 0x0a020700;
imm32 r3, 0x0a030710;
imm32 r4, 0x0a040700;
imm32 r5, 0x0a050700;
imm32 r6, 0x0a060700;
imm32 r7, 0x0a070700;
R0.H = R0.H << 8;
R1.H = R1.H << 9;
R2.H = R2.H << 10;
R3.H = R3.H << 11;
R4.H = R4.H << 12;
R5.H = R5.H << 13;
R6.H = R6.H << 14;
R7.H = R7.H << 15;
CHECKREG r0, 0x01000700;
CHECKREG r1, 0x02000700;
CHECKREG r2, 0x08000700;
CHECKREG r3, 0x18000710;
CHECKREG r4, 0x40000700;
CHECKREG r5, 0xA0000700;
CHECKREG r6, 0x80000700;
CHECKREG r7, 0x80000700;
pass
|
tactcomplabs/xbgas-binutils-gdb | 21,914 | sim/testsuite/bfin/c_dsp32mac_a1a0_iuw32.s | //Original:/testcases/core/c_dsp32mac_a1a0_iuw32/c_dsp32mac_a1a0_iuw32.dsp
// Spec Reference: dsp32mac a1 a0 iuw32 MNOP
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the (signed integer: no ) I=1
imm32 r0, 0x22345628;
imm32 r1, 0x23456729;
imm32 r2, 0x3456782a;
imm32 r3, 0x45678922;
imm32 r4, 0x56789123;
imm32 r5, 0x67891224;
imm32 r6, 0xa1234527;
imm32 r7, 0xc1234567;
A1 = R0.L * R7.L, A0 = R0.L * R7.L (IS);
R0 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.L, A0 += R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 += R2.L * R3.L, A0 = R2.H * R3.L (IS);
R2 = A0.w;
R3 = A1.w;
A1 += R5.L * R4.L, A0 += R5.H * R4.H (IS);
R5 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x175B7218;
CHECKREG r1, 0x1BDDC43F;
CHECKREG r2, 0xE7B2F96C;
CHECKREG r3, 0xE41233D3;
CHECKREG r4, 0xDC3712BF;
CHECKREG r5, 0x0AAB87A4;
CHECKREG r6, 0x20E26A9B;
CHECKREG r7, 0x175B7218;
imm32 r0, 0x13335678;
imm32 r1, 0x23436789;
imm32 r2, 0x3353789a;
imm32 r3, 0xa3638912;
imm32 r4, 0x53739123;
imm32 r5, 0x63831234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 = R2.L * R7.H, A0 += R2.L * R7.L (IS);
R2 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.H, A0 += R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 += R0.L * R5.H, A0 = R0.H * R5.L (IS);
R0 = A0.w;
R5 = A1.w;
A1 += R4.L * R3.H, A0 = R4.H * R3.H (IS);
R4 = A0.w;
R3 = A1.w;
CHECKREG r0, 0x015D7C5C;
CHECKREG r1, 0x098F3EF5;
CHECKREG r2, 0x2B5D8F9A;
CHECKREG r3, 0x53474FE6;
CHECKREG r4, 0xE1CF7E79;
CHECKREG r5, 0x2B2BE65D;
CHECKREG r6, 0x34ECCE8F;
CHECKREG r7, 0xE262970E;
imm32 r0, 0x14345678;
imm32 r1, 0x24456789;
imm32 r2, 0x3456789a;
imm32 r3, 0x44678912;
imm32 r4, 0x54789123;
imm32 r5, 0x67891244;
imm32 r6, 0xa1234547;
imm32 r7, 0xc1234547;
A1 += R4.H * R0.L, A0 = R4.L * R0.L (IS);
R4 = A0.w;
R0 = A1.w;
A1 = R3.H * R1.L, A0 += R3.L * R1.H (IS);
R3 = A0.w;
R1 = A1.w;
A1 = R2.H * R6.L, A0 = R2.H * R6.L (IS);
R2 = A0.w;
R6 = A1.w;
A1 += R7.H * R5.L, A0 += R7.H * R5.H (IS);
R7 = A0.w;
R5 = A1.w;
CHECKREG r0, 0x6FCF3826;
CHECKREG r1, 0x1BAA0C1F;
CHECKREG r2, 0x0E29B1DA;
CHECKREG r3, 0xC9B44442;
CHECKREG r4, 0xDA8DCA68;
CHECKREG r5, 0x09AD7526;
CHECKREG r6, 0x0E29B1DA;
CHECKREG r7, 0xF4BD2295;
imm32 r0, 0x15345678;
imm32 r1, 0x23556789;
imm32 r2, 0x3455789a;
imm32 r3, 0x45675912;
imm32 r4, 0x56789523;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234557;
imm32 r7, 0xc1234565;
A1 += R0.H * R1.H, A0 = R0.L * R1.L (IS);
R0 = A0.w;
R1 = A1.w;
A1 = R5.H * R6.H, A0 = R5.L * R6.H (IS);
R5 = A0.w;
R6 = A1.w;
A1 = R4.H * R3.H, A0 += R4.H * R3.L (IS);
R4 = A0.w;
R3 = A1.w;
A1 = R2.H * R7.H, A0 = R2.H * R7.H (IS);
R2 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x22F88E38;
CHECKREG r1, 0x0C9A9B6A;
CHECKREG r2, 0xF3263C9F;
CHECKREG r3, 0x17712248;
CHECKREG r4, 0x1756FD8C;
CHECKREG r5, 0xF941311C;
CHECKREG r6, 0xD9A250BB;
CHECKREG r7, 0xF3263C9F;
// test the (unsigned or integer :no ) U=1
imm32 r0, 0x62345678;
imm32 r1, 0x26456789;
imm32 r2, 0x3466789a;
imm32 r3, 0x45668912;
imm32 r4, 0x56786123;
imm32 r5, 0x67891634;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234566;
A1 = R0.L * R2.L, A0 = R0.L * R2.L (FU);
R0 = A0.w;
R2 = A1.w;
A1 = R1.L * R3.L, A0 += R1.L * R3.H (FU);
R1 = A0.w;
R3 = A1.w;
A1 += R4.L * R6.L, A0 = R4.H * R6.L (FU);
R4 = A0.w;
R6 = A1.w;
A1 += R5.L * R7.L, A0 += R5.H * R7.H (FU);
R5 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x28BC4430;
CHECKREG r1, 0x44CD71C6;
CHECKREG r2, 0x28BC4430;
CHECKREG r3, 0x376F98A2;
CHECKREG r4, 0x17712248;
CHECKREG r5, 0x658D9303;
CHECKREG r6, 0x51C51CB7;
CHECKREG r7, 0x57C9F96F;
imm32 r0, 0x12345678;
imm32 r1, 0x73456789;
imm32 r2, 0x8456789a;
imm32 r3, 0x49998912;
imm32 r4, 0x56782123;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234577;
imm32 r7, 0xc1234567;
A1 = R2.L * R3.H, A0 = R2.L * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.L * R1.H, A0 = R0.L * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
A1 += R4.L * R5.H, A0 = R4.H * R5.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R7.L * R6.H, A0 += R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x26EF3658;
CHECKREG r1, 0x26EF3658;
CHECKREG r2, 0x4092E4D4;
CHECKREG r3, 0x22ABFE0A;
CHECKREG r4, 0x06260060;
CHECKREG r5, 0x34560713;
CHECKREG r6, 0x7FB76B29;
CHECKREG r7, 0x2BAF4415;
imm32 r0, 0x1234567a;
imm32 r1, 0x2345678a;
imm32 r2, 0x3456a89a;
imm32 r3, 0x4a678912;
imm32 r4, 0xa6789123;
imm32 r5, 0xc7891234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 = R5.H * R4.L, A0 = R5.L * R4.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R3.H * R2.L, A0 = R3.L * R2.H (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R1.H * R0.L, A0 = R1.H * R0.L (FU);
R0 = A0.w;
R1 = A1.w;
A1 = R7.H * R6.L, A0 = R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x0BE9FCE2;
CHECKREG r1, 0x0BE9FCE2;
CHECKREG r2, 0x1C05B40C;
CHECKREG r3, 0x310059F6;
CHECKREG r4, 0x0A51F11C;
CHECKREG r5, 0x711FE0BB;
CHECKREG r6, 0x79916AC9;
CHECKREG r7, 0x345C2415;
imm32 r0, 0xb2345678;
imm32 r1, 0x2b456789;
imm32 r2, 0x34b6789a;
imm32 r3, 0xc56b8912;
imm32 r4, 0x5c78b123;
imm32 r5, 0x67c91b34;
imm32 r6, 0xa12345b7;
imm32 r7, 0xc123456b;
A1 = R6.H * R7.H, A0 = R6.L * R7.L (FU);
R6 = A0.w;
R7 = A1.w;
A1 = R5.H * R4.H, A0 = R5.L * R4.H (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R2.H * R3.H, A0 = R2.H * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.H * R1.H, A0 = R0.H * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x1E1EC404;
CHECKREG r1, 0x1E1EC404;
CHECKREG r2, 0x1C391ACC;
CHECKREG r3, 0x28A61612;
CHECKREG r4, 0x09D37060;
CHECKREG r5, 0x257CE238;
CHECKREG r6, 0x12E7767D;
CHECKREG r7, 0x79916AC9;
// Test w32
imm32 r0, 0x123df178;
imm32 r1, 0x2245e189;
imm32 r2, 0x3256719a;
imm32 r3, 0x42678112;
imm32 r4, 0xa2789123;
imm32 r5, 0x62891134;
imm32 r6, 0xa2b34167;
imm32 r7, 0xc22d4167;
A1 = R0.L * R4.L, A0 += R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.L * R5.L, A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.L * R6.L, A0 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.L * R4.L, A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x2AB4BAD4;
CHECKREG r1, 0x13410376;
CHECKREG r2, 0x2CF930AA;
CHECKREG r3, 0x33802490;
CHECKREG r4, 0x091C5540;
CHECKREG r5, 0xFBE7D1A8;
CHECKREG r6, 0x3A0B9DEC;
CHECKREG r7, 0xC22D4167;
imm32 r0, 0x553df344;
imm32 r1, 0x2525e349;
imm32 r2, 0x3252734a;
imm32 r3, 0x42658342;
imm32 r4, 0xa5789343;
imm32 r5, 0x63591344;
imm32 r6, 0xa3b54347;
imm32 r7, 0xc32d4347;
A1 += R0.L * R4.H, A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 += R1.L * R5.H, A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.L * R6.H, A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.L * R4.H, A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x0AD16D98;
CHECKREG r1, 0xE9B67EC2;
CHECKREG r2, 0x1A72D57C;
CHECKREG r3, 0x0965C3AC;
CHECKREG r4, 0x970BD9DE;
CHECKREG r5, 0xFBD48BC2;
CHECKREG r6, 0xA8B3CE66;
CHECKREG r7, 0xC32D4347;
imm32 r0, 0x163df678;
imm32 r1, 0x2625e689;
imm32 r2, 0x3652769a;
imm32 r3, 0x46628612;
imm32 r4, 0xa6789623;
imm32 r5, 0x63691634;
imm32 r6, 0xa3634367;
imm32 r7, 0xc3264667;
A1 += R0.H * R4.L, A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.L, A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L, A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.H * R4.L, A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x07E204D0;
CHECKREG r1, 0xF41B1732;
CHECKREG r2, 0x1C9AA1FC;
CHECKREG r3, 0xD8C785D8;
CHECKREG r4, 0x5DCEA034;
CHECKREG r5, 0x069DDB08;
CHECKREG r6, 0x23387D04;
CHECKREG r7, 0xC3264667;
imm32 r0, 0x123df378;
imm32 r1, 0x2225e389;
imm32 r2, 0x3252739a;
imm32 r3, 0x42628312;
imm32 r4, 0xa3789323;
imm32 r5, 0x63891334;
imm32 r6, 0xa3b34367;
imm32 r7, 0xc32d4367;
A1 += R0.H * R4.H, A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.H, A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.H, A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.H, A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x0AA862D0;
CHECKREG r1, 0xE9DD7EA2;
CHECKREG r2, 0x1A7F69FC;
CHECKREG r3, 0x29CFB5BC;
CHECKREG r4, 0x29CFB5BC;
CHECKREG r5, 0x1A8D299A;
CHECKREG r6, 0xF643F446;
CHECKREG r7, 0xC32D4367;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 = R0.H * R4.L, A0 = R0.H * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.L, A0 = R1.H * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.H * R6.H, A0 = R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.H, A0 = R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF03416AE;
CHECKREG r1, 0x1DE7F7DA;
CHECKREG r2, 0x430479EC;
CHECKREG r3, 0x0E4EA750;
CHECKREG r4, 0xF76F51D8;
CHECKREG r5, 0x05040808;
CHECKREG r6, 0xD9715C44;
CHECKREG r7, 0xC12D4567;
// MNOP & w32
imm32 r0, 0x623df17a;
imm32 r1, 0x7245e18b;
imm32 r2, 0x8256719a;
imm32 r3, 0x92678112;
imm32 r4, 0xa2789123;
imm32 r5, 0xb2891134;
imm32 r6, 0xc2b34167;
imm32 r7, 0xd22d4167;
A0 += R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A0 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A0 = R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x1AE2E2AC;
CHECKREG r1, 0x126EB2C6;
CHECKREG r2, 0xD2393FFA;
CHECKREG r3, 0x273C7436;
CHECKREG r4, 0xF76F51D8;
CHECKREG r5, 0xF76F51D8;
CHECKREG r6, 0xF76F51D8;
CHECKREG r7, 0xF76F51D8;
imm32 r0, 0xa23df17a;
imm32 r1, 0x7b45e18b;
imm32 r2, 0x82c6719a;
imm32 r3, 0x126d8112;
imm32 r4, 0xc278e123;
imm32 r5, 0xb2491f34;
imm32 r6, 0x89b54167;
imm32 r7, 0xd25d6767;
A1 += R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x273C7436;
CHECKREG r1, 0x273C7436;
CHECKREG r2, 0x273C7436;
CHECKREG r3, 0x273C7436;
CHECKREG r4, 0xFAEFCD34;
CHECKREG r5, 0x127DED46;
CHECKREG r6, 0xD281B49A;
CHECKREG r7, 0xF96E3732;
// test MM=1(Mix mode), MAC1 executes a mixed mode multiplication: (one input is
// signed, the other input is unsigned
imm32 r0, 0x22345628;
imm32 r1, 0x23456729;
imm32 r2, 0x3456782a;
imm32 r3, 0x45678922;
imm32 r4, 0x56789123;
imm32 r5, 0x67891224;
imm32 r6, 0xa1234527;
imm32 r7, 0xc1234567;
A1 += R0.L * R7.L (M), A0 = R0.L * R7.L (IS);
R0 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.L (M), A0 += R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L (M), A0 = R2.H * R3.L (IS);
R2 = A0.w;
R3 = A1.w;
A1 += R5.L * R4.L (M), A0 += R5.H * R4.H (IS);
R5 = A0.w;
R4 = A1.w;
CHECKREG r0, 0x175B7218;
CHECKREG r1, 0x1BDDC43F;
CHECKREG r2, 0xE7B2F96C;
CHECKREG r3, 0x405E6F94;
CHECKREG r4, 0x4AA74E80;
CHECKREG r5, 0x0AAB87A4;
CHECKREG r6, 0x20E26A9B;
CHECKREG r7, 0x10C9A94A;
imm32 r0, 0x13335678;
imm32 r1, 0x23436789;
imm32 r2, 0x3353789a;
imm32 r3, 0xa3638912;
imm32 r4, 0x53739123;
imm32 r5, 0x63831234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 += R2.L * R7.H (M), A0 = R2.L * R7.L (IS);
R2 = A0.w;
R7 = A1.w;
A1 = R6.L * R1.H (M), A0 = R6.L * R1.H (IS);
R6 = A0.w;
R1 = A1.w;
A1 += R0.L * R5.H (M), A0 = R0.H * R5.L (IS);
R0 = A0.w;
R5 = A1.w;
A1 = R4.L * R3.H (M), A0 += R4.H * R3.H (IS);
R4 = A0.w;
R3 = A1.w;
CHECKREG r0, 0x015D7C5C;
CHECKREG r1, 0x098F3EF5;
CHECKREG r2, 0x20B207F6;
CHECKREG r3, 0xB93E6989;
CHECKREG r4, 0xE32CFAD5;
CHECKREG r5, 0x2B2BE65D;
CHECKREG r6, 0x098F3EF5;
CHECKREG r7, 0xA5A3E58E;
imm32 r0, 0x14345678;
imm32 r1, 0x24456789;
imm32 r2, 0x3456789a;
imm32 r3, 0x44678912;
imm32 r4, 0x54789123;
imm32 r5, 0x67891244;
imm32 r6, 0xa1234547;
imm32 r7, 0xc1234547;
A1 = R4.H * R0.L (M), A0 = R4.L * R0.L (IS);
R4 = A0.w;
R0 = A1.w;
A1 = R3.H * R1.L (M), A0 = R3.L * R1.H (IS);
R3 = A0.w;
R1 = A1.w;
A1 = R2.H * R6.L (M), A0 = R2.H * R6.L (IS);
R2 = A0.w;
R6 = A1.w;
A1 = R7.H * R5.L (M), A0 = R7.H * R5.H (IS);
R7 = A0.w;
R5 = A1.w;
CHECKREG r0, 0x1C87E840;
CHECKREG r1, 0x1BAA0C1F;
CHECKREG r2, 0x0E29B1DA;
CHECKREG r3, 0xEF2679DA;
CHECKREG r4, 0xDA8DCA68;
CHECKREG r5, 0xFB83C34C;
CHECKREG r6, 0x0E29B1DA;
CHECKREG r7, 0xE69370BB;
imm32 r0, 0x15345678;
imm32 r1, 0x23556789;
imm32 r2, 0x3455789a;
imm32 r3, 0x45675912;
imm32 r4, 0x56789523;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234557;
imm32 r7, 0xc1234565;
A1 = R0.H * R1.H (M), A0 = R0.L * R1.L (IS);
R0 = A0.w;
R1 = A1.w;
A1 = R5.H * R6.H (M), A0 = R5.L * R6.H (IS);
R5 = A0.w;
R6 = A1.w;
A1 += R4.H * R3.H (M), A0 = R4.H * R3.L (IS);
R4 = A0.w;
R3 = A1.w;
A1 += R2.H * R7.H (M), A0 = R2.H * R7.H (IS);
R2 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x22F88E38;
CHECKREG r1, 0x02ED2644;
CHECKREG r2, 0xF3263C9F;
CHECKREG r3, 0x589C7303;
CHECKREG r4, 0x1E15CC70;
CHECKREG r5, 0xF941311C;
CHECKREG r6, 0x412B50BB;
CHECKREG r7, 0x8017AFA2;
// test the (unsigned or integer :no ) U=1
imm32 r0, 0x62345678;
imm32 r1, 0x26456789;
imm32 r2, 0x3466789a;
imm32 r3, 0x45668912;
imm32 r4, 0x56786123;
imm32 r5, 0x67891634;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234566;
A1 = R0.L * R2.L (M), A0 = R0.L * R2.L (FU);
R0 = A0.w;
R2 = A1.w;
A1 += R1.L * R3.L (M), A0 = R1.L * R3.H (FU);
R1 = A0.w;
R3 = A1.w;
A1 = R4.L * R6.L (M), A0 = R4.H * R6.L (FU);
R4 = A0.w;
R6 = A1.w;
A1 += R5.L * R7.L (M), A0 = R5.H * R7.H (FU);
R5 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x28BC4430;
CHECKREG r1, 0x1C112D96;
CHECKREG r2, 0x28BC4430;
CHECKREG r3, 0x602BDCD2;
CHECKREG r4, 0x17712248;
CHECKREG r5, 0x4E1C70BB;
CHECKREG r6, 0x1A558415;
CHECKREG r7, 0x205A60CD;
imm32 r0, 0x12345678;
imm32 r1, 0x73456789;
imm32 r2, 0x8456789a;
imm32 r3, 0x49998912;
imm32 r4, 0x56782123;
imm32 r5, 0x67891234;
imm32 r6, 0xa1234577;
imm32 r7, 0xc1234567;
A1 = R2.L * R3.H (M), A0 = R2.L * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.L * R1.H (M), A0 = R0.L * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
A1 = R4.L * R5.H (M), A0 = R4.H * R5.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R7.L * R6.H (M), A0 = R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x26EF3658;
CHECKREG r1, 0x26EF3658;
CHECKREG r2, 0x4092E4D4;
CHECKREG r3, 0x22ABFE0A;
CHECKREG r4, 0x06260060;
CHECKREG r5, 0x0D66D0BB;
CHECKREG r6, 0x79916AC9;
CHECKREG r7, 0x2BAF4415;
imm32 r0, 0x1234567a;
imm32 r1, 0x2345678a;
imm32 r2, 0x3456a89a;
imm32 r3, 0x4a678912;
imm32 r4, 0xa6789123;
imm32 r5, 0xc7891234;
imm32 r6, 0xa1234567;
imm32 r7, 0xc1234567;
A1 = R5.H * R4.L (M), A0 += R5.L * R4.L (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R3.H * R2.L (M), A0 = R3.L * R2.H (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R1.H * R0.L (M), A0 += R1.H * R0.L (FU);
R0 = A0.w;
R1 = A1.w;
A1 = R7.H * R6.L (M), A0 = R7.H * R6.H (FU);
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x27EFB0EE;
CHECKREG r1, 0x0BE9FCE2;
CHECKREG r2, 0x1C05B40C;
CHECKREG r3, 0x310059F6;
CHECKREG r4, 0x83E35BE5;
CHECKREG r5, 0xDFFCE0BB;
CHECKREG r6, 0x79916AC9;
CHECKREG r7, 0xEEF52415;
imm32 r0, 0xb2345678;
imm32 r1, 0x2b456789;
imm32 r2, 0x34b6789a;
imm32 r3, 0xc56b8912;
imm32 r4, 0x5c78b123;
imm32 r5, 0x67c91b34;
imm32 r6, 0xa12345b7;
imm32 r7, 0xc123456b;
A1 += R6.H * R7.H (M), A0 = R6.L * R7.L (FU);
R6 = A0.w;
R7 = A1.w;
A1 += R5.H * R4.H (M), A0 = R5.L * R4.H (FU);
R4 = A0.w;
R5 = A1.w;
A1 = R2.H * R3.H (M), A0 += R2.H * R3.L (FU);
R2 = A0.w;
R3 = A1.w;
A1 = R0.H * R1.H (M), A0 += R0.H * R1.H (FU);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x442B4F30;
CHECKREG r1, 0xF2D9C404;
CHECKREG r2, 0x260C8B2C;
CHECKREG r3, 0x28A61612;
CHECKREG r4, 0x09D37060;
CHECKREG r5, 0xCCE07116;
CHECKREG r6, 0x12E7767D;
CHECKREG r7, 0xA7638EDE;
// Test w32
imm32 r0, 0x123df178;
imm32 r1, 0x2245e189;
imm32 r2, 0x3256719a;
imm32 r3, 0x42678112;
imm32 r4, 0xa2789123;
imm32 r5, 0x62891134;
imm32 r6, 0xa2b34167;
imm32 r7, 0xc22d4167;
A1 = R0.L * R7.L (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 += R1.L * R5.L (M), A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.L * R6.L (M), A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.L * R4.L (M), A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF8933E90;
CHECKREG r1, 0xE88C48A2;
CHECKREG r2, 0x19B82D34;
CHECKREG r3, 0xCF7A9C90;
CHECKREG r4, 0xD50FA66C;
CHECKREG r5, 0xFA3D881C;
CHECKREG r6, 0x1D05CEF6;
CHECKREG r7, 0xFC499F48;
imm32 r0, 0x553df344;
imm32 r1, 0x2525e349;
imm32 r2, 0x3252734a;
imm32 r3, 0x42658342;
imm32 r4, 0xa5789343;
imm32 r5, 0x63591344;
imm32 r6, 0xa3b54347;
imm32 r7, 0xc32d4347;
A1 = R0.L * R7.H (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 = R1.L * R5.H (M), A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.L * R6.H (M), A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.L * R4.H (M), A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF94E87B8;
CHECKREG r1, 0xE305067A;
CHECKREG r2, 0x1A72D57C;
CHECKREG r3, 0xEB7D462C;
CHECKREG r4, 0xAF5F10F0;
CHECKREG r5, 0xF4DB3F61;
CHECKREG r6, 0x49B9A152;
CHECKREG r7, 0xF64A8EF4;
imm32 r0, 0x163df678;
imm32 r1, 0x2625e689;
imm32 r2, 0x3652769a;
imm32 r3, 0x46628612;
imm32 r4, 0xa6789623;
imm32 r5, 0x63691634;
imm32 r6, 0xa3634367;
imm32 r7, 0xc3264667;
A1 = R0.H * R7.L (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 = R1.H * R5.L (M), A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L (M), A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.L (M), A0 = R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xFAC1F490;
CHECKREG r1, 0xEC391262;
CHECKREG r2, 0x1C9AA1FC;
CHECKREG r3, 0xCEC513E0;
CHECKREG r4, 0x29470B66;
CHECKREG r5, 0x034EED84;
CHECKREG r6, 0x119C3E82;
CHECKREG r7, 0x061DA08B;
imm32 r0, 0x123df378;
imm32 r1, 0x2225e389;
imm32 r2, 0x3252739a;
imm32 r3, 0x42628312;
imm32 r4, 0xa3789323;
imm32 r5, 0x63891334;
imm32 r6, 0xa3b34367;
imm32 r7, 0xc32d4367;
A1 = R0.H * R7.H (M), A0 = R0.L * R7.L (W32);
R0 = A0.w;
R7 = A1.w;
A1 = R1.H * R5.H (M), A0 = R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.H (M), A0 += R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 += R3.H * R4.H (M), A0 += R3.H * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF966BA90;
CHECKREG r1, 0xE9DD7EA2;
CHECKREG r2, 0x045CE89E;
CHECKREG r3, 0xD45FF07E;
CHECKREG r4, 0x57D77E13;
CHECKREG r5, 0x0D4694CD;
CHECKREG r6, 0x2D73FA23;
CHECKREG r7, 0x0DE7ABB9;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 = R0.H * R4.L (M), A0 = R0.H * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.H * R5.L (M), A0 = R1.H * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A1 = R2.H * R6.H (M), A0 = R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R4.H (M), A0 = R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF03416AE;
CHECKREG r1, 0x1DE7F7DA;
CHECKREG r2, 0x430479EC;
CHECKREG r3, 0xF6A29C3C;
CHECKREG r4, 0x02CD9C01;
CHECKREG r5, 0x02820404;
CHECKREG r6, 0x210EAE22;
CHECKREG r7, 0xC12D4567;
// MNOP & w32
imm32 r0, 0x623df17a;
imm32 r1, 0x7245e18b;
imm32 r2, 0x8256719a;
imm32 r3, 0x92678112;
imm32 r4, 0xa2789123;
imm32 r5, 0xb2891134;
imm32 r6, 0xc2b34167;
imm32 r7, 0xd22d4167;
A0 = R0.L * R4.L (W32);
R0 = A0.w;
R4 = A1.w;
A0 += R1.L * R5.H (W32);
R1 = A0.w;
R5 = A1.w;
A0 = R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A0 += R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x0C943B5C;
CHECKREG r1, 0x1F02EE22;
CHECKREG r2, 0xBFCA8D34;
CHECKREG r3, 0xE707016A;
CHECKREG r4, 0x02CD9C01;
CHECKREG r5, 0x02CD9C01;
CHECKREG r6, 0x02CD9C01;
CHECKREG r7, 0x02CD9C01;
imm32 r0, 0xa23df17a;
imm32 r1, 0x7b45e18b;
imm32 r2, 0x82c6719a;
imm32 r3, 0x126d8112;
imm32 r4, 0xc278e123;
imm32 r5, 0xb2491f34;
imm32 r6, 0x89b54167;
imm32 r7, 0xd25d6767;
A1 += R0.L * R4.L (M,W32);
R0 = A0.w;
R4 = A1.w;
A1 = R1.L * R5.H (M,W32);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.L (M,W32);
R2 = A0.w;
R6 = A1.w;
A1 = R3.H * R7.H (M,W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xE707016A;
CHECKREG r1, 0xE707016A;
CHECKREG r2, 0xE707016A;
CHECKREG r3, 0xE707016A;
CHECKREG r4, 0xF607D9AF;
CHECKREG r5, 0xEAC9F6A3;
CHECKREG r6, 0xCACBDA4D;
CHECKREG r7, 0x0F241B99;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 -= R0.H * R4.L (M), A0 += R0.H * R4.L (IS);
R0 = A0.w;
R4 = A1.w;
A1 -= R1.H * R5.L (M), A0 -= R1.H * R5.H (FU);
R1 = A0.w;
R5 = A1.w;
A1 += R2.H * R6.H (M), A0 -= R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 -= R3.H * R4.H (M), A0 -= R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xDF210CC1;
CHECKREG r1, 0xD02D10D4;
CHECKREG r2, 0x8D2896E8;
CHECKREG r3, 0x9181B214;
CHECKREG r4, 0x220C8AE5;
CHECKREG r5, 0x024B0C3E;
CHECKREG r6, 0x2359BA60;
CHECKREG r7, 0xC12D4567;
imm32 r0, 0x123df678;
imm32 r1, 0x2345e789;
imm32 r2, 0x34567b9a;
imm32 r3, 0x45678c12;
imm32 r4, 0xa6789123;
imm32 r5, 0x6c891234;
imm32 r6, 0xa1b34567;
imm32 r7, 0xc12d4567;
A1 -= R0.H * R4.L (M), A0 = R0.H * R4.L (IS);
R0 = A0.w;
R4 = A1.w;
A1 -= R1.H * R5.L (M), A0 = R1.H * R5.H (FU);
R1 = A0.w;
R5 = A1.w;
A1 -= R2.H * R6.H (M), A0 = R2.L * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A1 -= R3.H * R4.H (M), A0 = R3.L * R4.H (W32);
R3 = A0.w;
R4 = A1.w;
CHECKREG r0, 0xF81A0B57;
CHECKREG r1, 0x0EF3FBED;
CHECKREG r2, 0x430479EC;
CHECKREG r3, 0xEA874D74;
CHECKREG r4, 0xEDB77A95;
CHECKREG r5, 0x15337B8A;
CHECKREG r6, 0xF424CD68;
CHECKREG r7, 0xC12D4567;
// MNOP & w32
imm32 r0, 0x623df17a;
imm32 r1, 0x7245e18b;
imm32 r2, 0x8256719a;
imm32 r3, 0x92678112;
imm32 r4, 0xa2789123;
imm32 r5, 0xb2891134;
imm32 r6, 0xc2b34167;
imm32 r7, 0xd22d4167;
A0 -= R0.L * R4.L (IS);
R0 = A0.w;
R4 = A1.w;
A0 -= R1.L * R5.H (FU);
R1 = A0.w;
R5 = A1.w;
A0 -= R2.H * R6.L (W32);
R2 = A0.w;
R6 = A1.w;
A0 -= R3.H * R7.H (W32);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xE43D2FC6;
CHECKREG r1, 0x46F1D663;
CHECKREG r2, 0x8727492F;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xEDB77A95;
CHECKREG r5, 0xEDB77A95;
CHECKREG r6, 0xEDB77A95;
CHECKREG r7, 0xEDB77A95;
imm32 r0, 0xa23df17a;
imm32 r1, 0x7b45e18b;
imm32 r2, 0x82c6719a;
imm32 r3, 0x126d8112;
imm32 r4, 0xc278e123;
imm32 r5, 0xb2491f34;
imm32 r6, 0x89b54167;
imm32 r7, 0xd25d6767;
A1 -= R0.L * R4.L (M,IS);
R0 = A0.w;
R4 = A1.w;
A1 -= R1.L * R5.H (M,FU);
R1 = A0.w;
R5 = A1.w;
A1 -= R2.H * R6.L (M,W32);
R2 = A0.w;
R6 = A1.w;
A1 -= R3.H * R7.H (M,FU);
R3 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xFA7D3CE7;
CHECKREG r5, 0x0FB34644;
CHECKREG r6, 0x2FB1629A;
CHECKREG r7, 0x208D4701;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,910 | sim/testsuite/bfin/hwloop-branch-in.s | # Blackfin testcase for branching into the middle of a hardware loop
# mach: bfin
.include "testutils.inc"
.macro test_prep lc:req
loadsym P5, 1f;
dmm32 LC0, \lc
R5 = 0;
R6 = 0;
R7 = 0;
.endm
.macro test_check exp5:req, exp6:req, exp7:req, expLC:req
1:
imm32 R4, \exp5;
CC = R4 == R5;
IF !CC JUMP 2f;
imm32 R4, \exp6;
CC = R4 == R6;
IF !CC JUMP 2f;
imm32 R4, \exp7;
CC = R4 == R7;
IF !CC JUMP 2f;
R3 = LC0;
imm32 R4, \expLC;
CC = R4 == R3;
IF !CC JUMP 2f;
JUMP 3f;
2: fail
3:
.endm
.macro test_rts entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
loadsym R1, \entry;
RETS = R1;
test_prep \lc
RTS;
test_check \exp5, \exp6, \exp7, \expLC
.endm
.macro test_jump entry:req, lc:req, exp5:req, exp6:req, exp7:req, expLC:req
loadsym P1, \entry;
test_prep \lc
JUMP (P1);
test_check \exp5, \exp6, \exp7, \expLC
.endm
start
loadsym R1, hws;
LT0 = R1;
loadsym R1, hwe;
LB0 = R1;
test_rts hws, 0, 1, 1, 1, 0
test_rts hws, 1, 1, 1, 1, 0
test_rts hws, 2, 2, 2, 2, 0
test_rts hws, 20, 20, 20, 20, 0
test_rts hwm, 0, 0, 1, 1, 0
test_rts hwm, 1, 0, 1, 1, 0
test_rts hwm, 2, 1, 2, 2, 0
test_rts hwm, 20, 19, 20, 20, 0
test_rts hwe, 0, 0, 0, 1, 0
test_rts hwe, 1, 0, 0, 1, 0
test_rts hwe, 2, 1, 1, 2, 0
test_rts hwe, 20, 19, 19, 20, 0
test_rts hwp, 0, 0, 0, 0, 0
test_rts hwp, 1, 0, 0, 0, 1
test_rts hwp, 2, 0, 0, 0, 2
test_jump hws, 0, 1, 1, 1, 0
test_jump hws, 1, 1, 1, 1, 0
test_jump hws, 2, 2, 2, 2, 0
test_jump hws, 20, 20, 20, 20, 0
test_jump hwm, 0, 0, 1, 1, 0
test_jump hwm, 1, 0, 1, 1, 0
test_jump hwm, 2, 1, 2, 2, 0
test_jump hwm, 20, 19, 20, 20, 0
test_jump hwe, 0, 0, 0, 1, 0
test_jump hwe, 1, 0, 0, 1, 0
test_jump hwe, 2, 1, 1, 2, 0
test_jump hwe, 20, 19, 19, 20, 0
test_jump hwp, 0, 0, 0, 0, 0
test_jump hwp, 1, 0, 0, 0, 1
test_jump hwp, 2, 0, 0, 0, 2
pass
hws: R5 += 1;
hwm: R6 += 1;
hwe: R7 += 1;
hwp: JUMP (P5);
|
tactcomplabs/xbgas-binutils-gdb | 4,973 | sim/testsuite/bfin/c_regmv_imlb_dr.s | //Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp
// Spec Reference: regmv imlb to dr
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
// i to dreg
R0 = I0;
R1 = I0;
R2 = I0;
R3 = I0;
R4 = I1;
R5 = I1;
R6 = I1;
R7 = I1;
CHECKREG r0, 0x11111111;
CHECKREG r1, 0x11111111;
CHECKREG r2, 0x11111111;
CHECKREG r3, 0x11111111;
CHECKREG r4, 0x22222222;
CHECKREG r5, 0x22222222;
CHECKREG r6, 0x22222222;
CHECKREG r7, 0x22222222;
R0 = I1;
R1 = I1;
R2 = I1;
R3 = I1;
R4 = I0;
R5 = I0;
R6 = I0;
R7 = I0;
CHECKREG r0, 0x22222222;
CHECKREG r1, 0x22222222;
CHECKREG r2, 0x22222222;
CHECKREG r3, 0x22222222;
CHECKREG r4, 0x11111111;
CHECKREG r5, 0x11111111;
CHECKREG r6, 0x11111111;
CHECKREG r7, 0x11111111;
// i to dreg
R0 = I2;
R1 = I2;
R2 = I2;
R3 = I2;
R4 = I3;
R5 = I3;
R6 = I3;
R7 = I3;
CHECKREG r0, 0x33333333;
CHECKREG r1, 0x33333333;
CHECKREG r2, 0x33333333;
CHECKREG r3, 0x33333333;
CHECKREG r4, 0x44444444;
CHECKREG r5, 0x44444444;
CHECKREG r6, 0x44444444;
CHECKREG r7, 0x44444444;
R0 = I3;
R1 = I3;
R2 = I3;
R3 = I3;
R4 = I2;
R5 = I2;
R6 = I2;
R7 = I2;
CHECKREG r0, 0x44444444;
CHECKREG r1, 0x44444444;
CHECKREG r2, 0x44444444;
CHECKREG r3, 0x44444444;
CHECKREG r4, 0x33333333;
CHECKREG r5, 0x33333333;
CHECKREG r6, 0x33333333;
CHECKREG r7, 0x33333333;
imm32 m0, 0x55555555;
imm32 m1, 0x66666666;
imm32 m2, 0x77777777;
imm32 m3, 0x88888888;
// m to dreg
R0 = M0;
R1 = M0;
R2 = M0;
R3 = M0;
R4 = M1;
R5 = M1;
R6 = M1;
R7 = M1;
CHECKREG r0, 0x55555555;
CHECKREG r1, 0x55555555;
CHECKREG r2, 0x55555555;
CHECKREG r3, 0x55555555;
CHECKREG r4, 0x66666666;
CHECKREG r5, 0x66666666;
CHECKREG r6, 0x66666666;
CHECKREG r7, 0x66666666;
R0 = M1;
R1 = M1;
R2 = M1;
R3 = M1;
R4 = M0;
R5 = M0;
R6 = M0;
R7 = M0;
CHECKREG r0, 0x66666666;
CHECKREG r1, 0x66666666;
CHECKREG r2, 0x66666666;
CHECKREG r3, 0x66666666;
CHECKREG r4, 0x55555555;
CHECKREG r5, 0x55555555;
CHECKREG r6, 0x55555555;
CHECKREG r7, 0x55555555;
R0 = M2;
R1 = M2;
R2 = M2;
R3 = M2;
R4 = M3;
R5 = M3;
R6 = M3;
R7 = M3;
CHECKREG r0, 0x77777777;
CHECKREG r1, 0x77777777;
CHECKREG r2, 0x77777777;
CHECKREG r3, 0x77777777;
CHECKREG r4, 0x88888888;
CHECKREG r5, 0x88888888;
CHECKREG r6, 0x88888888;
CHECKREG r7, 0x88888888;
R0 = M3;
R1 = M3;
R2 = M3;
R3 = M3;
R4 = M2;
R5 = M2;
R6 = M2;
R7 = M2;
CHECKREG r0, 0x88888888;
CHECKREG r1, 0x88888888;
CHECKREG r2, 0x88888888;
CHECKREG r3, 0x88888888;
CHECKREG r4, 0x77777777;
CHECKREG r5, 0x77777777;
CHECKREG r6, 0x77777777;
CHECKREG r7, 0x77777777;
imm32 l0, 0x99999999;
imm32 l1, 0xaaaaaaaa;
imm32 l2, 0xbbbbbbbb;
imm32 l3, 0xcccccccc;
// l to dreg
R0 = L0;
R1 = L0;
R2 = L0;
R3 = L0;
R4 = L1;
R5 = L1;
R6 = L1;
R7 = L1;
CHECKREG r0, 0x99999999;
CHECKREG r1, 0x99999999;
CHECKREG r2, 0x99999999;
CHECKREG r3, 0x99999999;
CHECKREG r4, 0xaaaaaaaa;
CHECKREG r5, 0xaaaaaaaa;
CHECKREG r6, 0xaaaaaaaa;
CHECKREG r7, 0xaaaaaaaa;
R0 = L1;
R1 = L1;
R2 = L1;
R3 = L1;
R4 = L0;
R5 = L0;
R6 = L0;
R7 = L0;
CHECKREG r0, 0xaaaaaaaa;
CHECKREG r1, 0xaaaaaaaa;
CHECKREG r2, 0xaaaaaaaa;
CHECKREG r3, 0xaaaaaaaa;
CHECKREG r4, 0x99999999;
CHECKREG r5, 0x99999999;
CHECKREG r6, 0x99999999;
CHECKREG r7, 0x99999999;
R0 = L2;
R1 = L2;
R2 = L2;
R3 = L2;
R4 = L3;
R5 = L3;
R6 = L3;
R7 = L3;
CHECKREG r0, 0xbbbbbbbb;
CHECKREG r1, 0xbbbbbbbb;
CHECKREG r2, 0xbbbbbbbb;
CHECKREG r3, 0xbbbbbbbb;
CHECKREG r4, 0xcccccccc;
CHECKREG r5, 0xcccccccc;
CHECKREG r6, 0xcccccccc;
CHECKREG r7, 0xcccccccc;
R0 = L3;
R1 = L3;
R2 = L3;
R3 = L3;
R4 = L2;
R5 = L2;
R6 = L2;
R7 = L2;
CHECKREG r0, 0xcccccccc;
CHECKREG r1, 0xcccccccc;
CHECKREG r2, 0xcccccccc;
CHECKREG r3, 0xcccccccc;
CHECKREG r4, 0xbbbbbbbb;
CHECKREG r5, 0xbbbbbbbb;
CHECKREG r6, 0xbbbbbbbb;
CHECKREG r7, 0xbbbbbbbb;
imm32 b0, 0xdddddddd;
imm32 b1, 0xeeeeeeee;
imm32 b2, 0xffffffff;
imm32 b3, 0x12345678;
// b to dreg
R0 = B0;
R1 = B0;
R2 = B0;
R3 = B0;
R4 = B1;
R5 = B1;
R6 = B1;
R7 = B1;
CHECKREG r0, 0xdddddddd;
CHECKREG r1, 0xdddddddd;
CHECKREG r2, 0xdddddddd;
CHECKREG r3, 0xdddddddd;
CHECKREG r4, 0xeeeeeeee;
CHECKREG r5, 0xeeeeeeee;
CHECKREG r6, 0xeeeeeeee;
CHECKREG r7, 0xeeeeeeee;
R0 = B1;
R1 = B1;
R2 = B1;
R3 = B1;
R4 = B0;
R5 = B0;
R6 = B0;
R7 = B0;
CHECKREG r0, 0xeeeeeeee;
CHECKREG r1, 0xeeeeeeee;
CHECKREG r2, 0xeeeeeeee;
CHECKREG r3, 0xeeeeeeee;
CHECKREG r4, 0xdddddddd;
CHECKREG r5, 0xdddddddd;
CHECKREG r6, 0xdddddddd;
CHECKREG r7, 0xdddddddd;
R0 = B2;
R1 = B2;
R2 = B2;
R3 = B2;
R4 = B3;
R5 = B3;
R6 = B3;
R7 = B3;
CHECKREG r0, 0xffffffff;
CHECKREG r1, 0xffffffff;
CHECKREG r2, 0xffffffff;
CHECKREG r3, 0xffffffff;
CHECKREG r4, 0x12345678;
CHECKREG r5, 0x12345678;
CHECKREG r6, 0x12345678;
CHECKREG r7, 0x12345678;
R0 = B3;
R1 = B3;
R2 = B3;
R3 = B3;
R4 = B2;
R5 = B2;
R6 = B2;
R7 = B2;
CHECKREG r0, 0x12345678;
CHECKREG r1, 0x12345678;
CHECKREG r2, 0x12345678;
CHECKREG r3, 0x12345678;
CHECKREG r4, 0xffffffff;
CHECKREG r5, 0xffffffff;
CHECKREG r6, 0xffffffff;
CHECKREG r7, 0xffffffff;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,300 | sim/testsuite/bfin/c_ldst_ld_p_p.s | //Original:/testcases/core/c_ldst_ld_p_p/c_ldst_ld_p_p.dsp
// Spec Reference: c_ldst ld p [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ];
P4 = [ P1 ];
P5 = [ P1 ];
FP = [ P1 ];
CHECKREG p2, 0x78910213;
CHECKREG p4, 0x78910213;
CHECKREG p5, 0x78910213;
CHECKREG fp, 0x78910213;
loadsym p2, DATA_ADDR_2;
P1 = [ P2 ];
P4 = [ P2 ];
P5 = [ P2 ];
FP = [ P2 ];
CHECKREG p1, 0x20212223;
CHECKREG p4, 0x20212223;
CHECKREG p5, 0x20212223;
CHECKREG fp, 0x20212223;
loadsym p4, DATA_ADDR_4;
P1 = [ P4 ];
P2 = [ P4 ];
P5 = [ P4 ];
FP = [ P4 ];
CHECKREG p1, 0x60616263;
CHECKREG p2, 0x60616263;
CHECKREG p5, 0x60616263;
CHECKREG fp, 0x60616263;
loadsym p5, DATA_ADDR_5;
P1 = [ P5 ];
P2 = [ P5 ];
P4 = [ P5 ];
FP = [ P5 ];
CHECKREG p1, 0x8A8B8C8D;
CHECKREG p2, 0x8A8B8C8D;
CHECKREG p4, 0x8A8B8C8D;
CHECKREG fp, 0x8A8B8C8D;
loadsym fp, DATA_ADDR_7;
P1 = [ FP ];
P2 = [ FP ];
P4 = [ FP ];
P5 = [ FP ];
CHECKREG p1, 0x80818283;
CHECKREG p2, 0x80818283;
CHECKREG p4, 0x80818283;
CHECKREG p5, 0x80818283;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x78910213
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x8A8B8C8D
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 4,029 | sim/testsuite/bfin/c_dsp32mult_pair_m_s.s | //Original:/testcases/core/c_dsp32mult_pair_m_s/c_dsp32mult_pair_m_s.dsp
// Spec Reference: dsp32mult pair MUNOP s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R0 = R0.L * R0.L (S2RND);
R2 = R0.L * R1.H (S2RND);
R4 = R1.H * R1.H (S2RND);
R6 = R0.L * R0.L (S2RND);
CHECKREG r0, 0x73F38564;
CHECKREG r1, 0x9F7A5127;
CHECKREG r2, 0x7FFFFFFF;
CHECKREG r3, 0x00069027;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0x10ACEF2B;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0xD246712F;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0 = R2.L * R2.L (S2RND);
R2 = R2.L * R3.H (S2RND);
R4 = R3.H * R2.H (S2RND);
R6 = R2.L * R3.L (S2RND);
CHECKREG r0, 0x52CB43E4;
CHECKREG r1, 0x6FBA5137;
CHECKREG r2, 0x7F5C6CF8;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0xB0ACEF3B;
CHECKREG r6, 0x005DA520;
CHECKREG r7, 0x12467003;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0 = R4.L * R4.L (S2RND);
R2 = R4.L * R5.H (S2RND);
R4 = R5.H * R5.H (S2RND);
R6 = R4.L * R5.L (S2RND);
CHECKREG r0, 0x36536944;
CHECKREG r1, 0xC4BA5157;
CHECKREG r2, 0xF0A8637C;
CHECKREG r3, 0x05060055;
CHECKREG r4, 0x045533C4;
CHECKREG r5, 0x10A7EF5B;
CHECKREG r6, 0xF2898AB0;
CHECKREG r7, 0x1246795F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
R0 = R6.L * R6.L (S2RND);
R2 = R6.L * R7.H (S2RND);
R4 = R7.H * R7.H (S2RND);
R6 = R6.L * R7.L (S2RND);
CHECKREG r0, 0x62F039A4;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0xE9479F38;
CHECKREG r3, 0xF0060066;
CHECKREG r4, 0x0537AC90;
CHECKREG r5, 0x10ACEF6B;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x1246706F;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0 = R0.L * R7.L (S2RND);
R2 = R1.L * R6.H (S2RND);
R4 = R3.H * R4.H (S2RND);
R6 = R4.L * R3.L (S2RND);
CHECKREG r0, 0x164DC36C;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x000F3750;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0xFFF59008;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0xFFF3C0E0;
CHECKREG r7, 0x1246F00F;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R1 = R7.H * R0.H (S2RND);
R3 = R6.H * R1.H (S2RND);
R5 = R5.H * R2.L (S2RND);
R7 = R4.L * R3.H (S2RND);
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0xE7C50648;
CHECKREG r2, 0x13246905;
CHECKREG r3, 0xFFFB74F0;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x1B5B7D70;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x0003FB4C;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R1 = R6.H * R4.L (S2RND);
R3 = R5.L * R3.H (S2RND);
R5 = R3.H * R1.L (S2RND);
R7 = R1.H * R2.H (S2RND);
CHECKREG r0, 0x9B235675;
CHECKREG r1, 0xFFED71B0;
CHECKREG r2, 0x13946705;
CHECKREG r3, 0xFFFCE2CC;
CHECKREG r4, 0x90AB9D09;
CHECKREG r5, 0xFFF8E500;
CHECKREG r6, 0x000C009D;
CHECKREG r7, 0xFFFA3010;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R4.L * R0.H (S2RND);
R3 = R6.H * R1.H (S2RND);
R5 = R1.L * R2.L (S2RND);
R7 = R4.H * R2.L (S2RND);
CHECKREG r0, 0xEB235675;
CHECKREG r1, 0x062EACEC;
CHECKREG r2, 0x13E46705;
CHECKREG r3, 0x000128A0;
CHECKREG r4, 0x90ABED09;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x000C00ED;
CHECKREG r7, 0x80000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,994 | sim/testsuite/bfin/c_comp3op_dr_xor_dr.s | //Original:/testcases/core/c_comp3op_dr_xor_dr/c_comp3op_dr_xor_dr.dsp
// Spec Reference: comp3op dregs xor dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 ^ R0;
R1 = R0 ^ R1;
R2 = R0 ^ R2;
R3 = R0 ^ R3;
R4 = R0 ^ R4;
R5 = R0 ^ R5;
R6 = R0 ^ R6;
R7 = R0 ^ R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x89ABCDEF;
CHECKREG r2, 0x56789ABC;
CHECKREG r3, 0xDEF01234;
CHECKREG r4, 0x23456899;
CHECKREG r5, 0x78912345;
CHECKREG r6, 0x98765432;
CHECKREG r7, 0x12345678;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 ^ R0;
R1 = R1 ^ R1;
R2 = R1 ^ R2;
R3 = R1 ^ R3;
R4 = R1 ^ R4;
R5 = R1 ^ R5;
R6 = R1 ^ R6;
R7 = R1 ^ R7;
CHECKREG r0, 0x88880888;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x56781ABC;
CHECKREG r3, 0xDEF01234;
CHECKREG r4, 0x23451899;
CHECKREG r5, 0x78911345;
CHECKREG r6, 0x98761432;
CHECKREG r7, 0x12341678;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 ^ R0;
R1 = R2 ^ R1;
R2 = R2 ^ R2;
R3 = R2 ^ R3;
R4 = R2 ^ R4;
R5 = R2 ^ R5;
R6 = R2 ^ R6;
R7 = R2 ^ R7;
CHECKREG r0, 0x575BDF0B;
CHECKREG r1, 0xDFD35703;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xDEF01224;
CHECKREG r4, 0x23456829;
CHECKREG r5, 0x78912325;
CHECKREG r6, 0x98765422;
CHECKREG r7, 0x12345628;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 ^ R0;
R1 = R3 ^ R1;
R2 = R3 ^ R2;
R3 = R3 ^ R3;
R4 = R3 ^ R4;
R5 = R3 ^ R5;
R6 = R3 ^ R6;
R7 = R3 ^ R7;
CHECKREG r0, 0xDFD35750;
CHECKREG r1, 0x575BDFD0;
CHECKREG r2, 0x88888880;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x23456893;
CHECKREG r5, 0x78912343;
CHECKREG r6, 0x98765433;
CHECKREG r7, 0x12345673;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 ^ R0;
R1 = R4 ^ R1;
R2 = R4 ^ R2;
R3 = R4 ^ R3;
R4 = R4 ^ R4;
R5 = R4 ^ R5;
R6 = R4 ^ R6;
R7 = R4 ^ R7;
CHECKREG r0, 0x02662DFE;
CHECKREG r1, 0x0AEEA576;
CHECKREG r2, 0x053DF225;
CHECKREG r3, 0x0DB57AAD;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x48912345;
CHECKREG r6, 0x48765432;
CHECKREG r7, 0x42345678;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 ^ R0;
R1 = R5 ^ R1;
R2 = R5 ^ R2;
R3 = R5 ^ R3;
R4 = R5 ^ R4;
R5 = R5 ^ R5;
R6 = R5 ^ R6;
R7 = R5 ^ R7;
CHECKREG r0, 0x70B26622;
CHECKREG r1, 0xF03AEEAA;
CHECKREG r2, 0x20E9B9F9;
CHECKREG r3, 0xA0613171;
CHECKREG r4, 0x50D44BDC;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x95765432;
CHECKREG r7, 0x15345678;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 ^ R0;
R1 = R6 ^ R1;
R2 = R6 ^ R2;
R3 = R6 ^ R3;
R4 = R6 ^ R4;
R5 = R6 ^ R5;
R6 = R6 ^ R6;
R7 = R6 ^ R7;
CHECKREG r0, 0x99501155;
CHECKREG r1, 0x11D099DD;
CHECKREG r2, 0xCE00CE8E;
CHECKREG r3, 0x46804606;
CHECKREG r4, 0xBB303CAB;
CHECKREG r5, 0xE0E07777;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x12365678;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 ^ R0;
R1 = R7 ^ R1;
R2 = R7 ^ R2;
R3 = R7 ^ R3;
R4 = R7 ^ R4;
R5 = R7 ^ R5;
R6 = R7 ^ R6;
R7 = R7 ^ R7;
CHECKREG r0, 0x1317231F;
CHECKREG r1, 0x9B9F2B97;
CHECKREG r2, 0x444C2CC4;
CHECKREG r3, 0xCCC4244C;
CHECKREG r4, 0x31712EE1;
CHECKREG r5, 0x6AA5253D;
CHECKREG r6, 0x8A42224A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x11234567;
imm32 r1, 0x81abcdef;
imm32 r2, 0x56189abc;
imm32 r3, 0xdef11234;
imm32 r4, 0x23451899;
imm32 r5, 0x78912145;
imm32 r6, 0x98765412;
imm32 r7, 0x12345671;
R0 = R1 ^ R0;
R1 = R2 ^ R0;
R2 = R3 ^ R0;
R3 = R4 ^ R0;
R4 = R5 ^ R0;
R5 = R6 ^ R0;
R6 = R7 ^ R0;
R7 = R0 ^ R0;
CHECKREG r0, 0x90888888;
CHECKREG r1, 0xC6901234;
CHECKREG r2, 0x4E799ABC;
CHECKREG r3, 0xB3CD9011;
CHECKREG r4, 0xE819A9CD;
CHECKREG r5, 0x08FEDC9A;
CHECKREG r6, 0x82BCDEF9;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01231567;
imm32 r1, 0x29ab1def;
imm32 r2, 0x52781abc;
imm32 r3, 0xde201234;
imm32 r4, 0x23421899;
imm32 r5, 0x78912345;
imm32 r6, 0x98761232;
imm32 r7, 0x12341628;
R0 = R2 ^ R1;
R1 = R3 ^ R1;
R2 = R4 ^ R1;
R3 = R5 ^ R1;
R4 = R6 ^ R1;
R5 = R7 ^ R1;
R6 = R0 ^ R1;
R7 = R1 ^ R1;
CHECKREG r0, 0x7BD30753;
CHECKREG r1, 0xF78B0FDB;
CHECKREG r2, 0xD4C91742;
CHECKREG r3, 0x8F1A2C9E;
CHECKREG r4, 0x6FFD1DE9;
CHECKREG r5, 0xE5BF19F3;
CHECKREG r6, 0x8C580888;
CHECKREG r7, 0x00000000;
imm32 r0, 0x03234527;
imm32 r1, 0x893bcd2f;
imm32 r2, 0x56739a2c;
imm32 r3, 0x3ef03224;
imm32 r4, 0x23456329;
imm32 r5, 0x78312335;
imm32 r6, 0x98735423;
imm32 r7, 0x12343628;
R0 = R4 ^ R2;
R1 = R5 ^ R2;
R2 = R6 ^ R2;
R3 = R7 ^ R2;
R4 = R0 ^ R2;
R5 = R1 ^ R2;
R6 = R2 ^ R2;
R7 = R3 ^ R2;
CHECKREG r0, 0x7536F905;
CHECKREG r1, 0x2E42B919;
CHECKREG r2, 0xCE00CE0F;
CHECKREG r3, 0xDC34F827;
CHECKREG r4, 0xBB36370A;
CHECKREG r5, 0xE0427716;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x12343628;
imm32 r0, 0x04234563;
imm32 r1, 0x894bcde3;
imm32 r2, 0x56749ab3;
imm32 r3, 0x4ef04233;
imm32 r4, 0x24456493;
imm32 r5, 0x78412344;
imm32 r6, 0x98745434;
imm32 r7, 0x12344673;
R0 = R5 ^ R3;
R1 = R6 ^ R3;
R2 = R7 ^ R3;
R3 = R0 ^ R3;
R4 = R1 ^ R3;
R5 = R2 ^ R3;
R6 = R3 ^ R3;
R7 = R4 ^ R3;
CHECKREG r0, 0x36B16177;
CHECKREG r1, 0xD6841607;
CHECKREG r2, 0x5CC40440;
CHECKREG r3, 0x78412344;
CHECKREG r4, 0xAEC53543;
CHECKREG r5, 0x24852704;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xD6841607;
imm32 r0, 0x41235567;
imm32 r1, 0x49abc5ef;
imm32 r2, 0x46789a5c;
imm32 r3, 0x4ef01235;
imm32 r4, 0x53456899;
imm32 r5, 0x45912345;
imm32 r6, 0x48565432;
imm32 r7, 0x42355678;
R0 = R6 ^ R4;
R1 = R7 ^ R4;
R2 = R0 ^ R4;
R3 = R1 ^ R4;
R4 = R2 ^ R4;
R5 = R3 ^ R4;
R6 = R4 ^ R4;
R7 = R5 ^ R4;
CHECKREG r0, 0x1B133CAB;
CHECKREG r1, 0x11703EE1;
CHECKREG r2, 0x48565432;
CHECKREG r3, 0x42355678;
CHECKREG r4, 0x1B133CAB;
CHECKREG r5, 0x59266AD3;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x42355678;
imm32 r0, 0x05264567;
imm32 r1, 0x85ab6def;
imm32 r2, 0x657896bc;
imm32 r3, 0xd6f01264;
imm32 r4, 0x25656896;
imm32 r5, 0x75962345;
imm32 r6, 0x95766432;
imm32 r7, 0x15345678;
R0 = R7 ^ R5;
R1 = R0 ^ R5;
R2 = R1 ^ R5;
R3 = R2 ^ R5;
R4 = R3 ^ R5;
R5 = R4 ^ R5;
R6 = R5 ^ R5;
R7 = R6 ^ R5;
CHECKREG r0, 0x60A2753D;
CHECKREG r1, 0x15345678;
CHECKREG r2, 0x60A2753D;
CHECKREG r3, 0x15345678;
CHECKREG r4, 0x60A2753D;
CHECKREG r5, 0x15345678;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x15345678;
imm32 r0, 0x01764567;
imm32 r1, 0x89a7cdef;
imm32 r2, 0x56767abc;
imm32 r3, 0xdef61734;
imm32 r4, 0x73466879;
imm32 r5, 0x77962347;
imm32 r6, 0x98765432;
imm32 r7, 0x12375678;
R0 = R7 ^ R6;
R1 = R0 ^ R6;
R2 = R1 ^ R6;
R3 = R2 ^ R6;
R4 = R3 ^ R6;
R5 = R4 ^ R6;
R6 = R5 ^ R6;
R7 = R6 ^ R6;
CHECKREG r0, 0x8A41024A;
CHECKREG r1, 0x12375678;
CHECKREG r2, 0x8A41024A;
CHECKREG r3, 0x12375678;
CHECKREG r4, 0x8A41024A;
CHECKREG r5, 0x12375678;
CHECKREG r6, 0x8A41024A;
CHECKREG r7, 0x00000000;
imm32 r0, 0x81238567;
imm32 r1, 0x88ab78ef;
imm32 r2, 0x56887a8c;
imm32 r3, 0x8ef87238;
imm32 r4, 0x28458899;
imm32 r5, 0x78817845;
imm32 r6, 0x98787482;
imm32 r7, 0x12348678;
R0 = R1 ^ R7;
R1 = R2 ^ R7;
R2 = R3 ^ R7;
R3 = R4 ^ R7;
R4 = R5 ^ R7;
R5 = R6 ^ R7;
R6 = R7 ^ R7;
R7 = R0 ^ R7;
CHECKREG r0, 0x9A9FFE97;
CHECKREG r1, 0x44BCFCF4;
CHECKREG r2, 0x9CCCF440;
CHECKREG r3, 0x3A710EE1;
CHECKREG r4, 0x6AB5FE3D;
CHECKREG r5, 0x8A4CF2FA;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x88AB78EF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,990 | sim/testsuite/bfin/l0.s | // simple test to ensure that we can load data from memory.
# mach: bfin
.include "testutils.inc"
start
loadsym P0, tab;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
R6 = [ P0 ++ ];
R7 = [ P0 ++ ];
DBGA ( R0.H , 0x1111 );
DBGA ( R1.H , 0x2222 );
DBGA ( R2.H , 0x3333 );
DBGA ( R3.H , 0x4444 );
DBGA ( R4.H , 0x5555 );
DBGA ( R5.H , 0x6666 );
DBGA ( R6.H , 0x7777 );
DBGA ( R7.H , 0x8888 );
loadsym P0, tab2;
R0 = W [ P0 ++ ] (Z);
DBGA ( R0.L , 0x1111 );
R1 = W [ P0 ++ ] (Z);
DBGA ( R1.L , 0x8888 );
R2 = W [ P0 ++ ] (Z);
DBGA ( R2.L , 0x2222 );
R3 = W [ P0 ++ ] (Z);
DBGA ( R3.L , 0x7777 );
R4 = W [ P0 ++ ] (Z);
DBGA ( R4.L , 0x3333 );
R5 = W [ P0 ++ ] (Z);
DBGA ( R5.L , 0x6666 );
R0 = B [ P0 ++ ] (Z);
DBGA ( R0.L , 0x44 );
R1 = B [ P0 ++ ] (Z);
DBGA ( R1.L , 0x44 );
R2 = B [ P0 ++ ] (Z);
DBGA ( R2.L , 0x55 );
R3 = B [ P0 ++ ] (Z);
DBGA ( R3.L , 0x55 );
R0 = B [ P0 ++ ] (X);
DBGA ( R0.L , 0x55 );
R1 = B [ P0 ++ ] (X);
DBGA ( R1.L , 0x55 );
R0 = W [ P0 ++ ] (X);
DBGA ( R0.L , 0x4444 );
R1 = [ P0 ++ ];
DBGA ( R1.L , 0x6666 );
DBGA ( R1.H , 0x3333 );
P1 = [ P0 ++ ];
R0 = P1;
DBGA ( R0.L , 0x7777 );
DBGA ( R0.H , 0x2222 );
P1 = [ P0 ++ ];
R0 = P1;
DBGA ( R0.L , 0x8888 );
DBGA ( R0.H , 0x1111 );
loadsym P5, tab3;
R0 = B [ P5 ++ ] (X);
DBGA ( R0.H , 0 );
DBGA ( R0.L , 0 );
R0 = B [ P5 ++ ] (X);
DBGA ( R0.H , 0xffff );
DBGA ( R0.L , 0xffff );
R1 = W [ P5 ++ ] (X);
DBGA ( R1.H , 0xffff );
DBGA ( R1.L , 0xffff );
pass
.data
tab:
.dw 0
.dw 0x1111
.dw 0
.dw 0x2222
.dw 0
.dw 0x3333
.dw 0
.dw 0x4444
.dw 0
.dw 0x5555
.dw 0
.dw 0x6666
.dw 0
.dw 0x7777
.dw 0
.dw 0x8888
.dw 0
.dw 0
.dw 0
.dw 0
tab2:
.dw 0x1111
.dw 0x8888
.dw 0x2222
.dw 0x7777
.dw 0x3333
.dw 0x6666
.dw 0x4444
.dw 0x5555
.dw 0x5555
.dw 0x4444
.dw 0x6666
.dw 0x3333
.dw 0x7777
.dw 0x2222
.dw 0x8888
.dw 0x1111
tab3:
.dw 0xff00
.dw 0xffff
|
tactcomplabs/xbgas-binutils-gdb | 3,312 | sim/testsuite/bfin/random_0009.S | # Verify ASTAT bits are set correctly during dsp mac insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x16ba2677;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x80007fff;
A0 -= R4.H * R4.H (W32);
checkreg A0.w, 0x96ba2678;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x4450cc90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3c30c800 | _VS | _AV0S | _AC1 | _CC);
dmm32 A0.w, 0xf170d0c7;
dmm32 A0.x, 0xffffffff;
imm32 R2, 0x80008000;
A0 -= R2.H * R2.L (W32);
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x3c30c800 | _VS | _AV0S | _AV0 | _AC1 | _CC);
dmm32 ASTAT, (0x6c200880 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AN);
dmm32 A0.x, 0x560a1c52;
dmm32 A0.x, 0xffffffbb;
imm32 R5, 0x8000ffff;
A0 = R5.H * R5.H (W32);
checkreg A0.w, 0x7fffffff;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x6c200880 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _AN);
dmm32 ASTAT, (0x58908a90 | _VS | _AC1 | _AC0 | _AQ);
dmm32 A0.w, 0x00c5a4e0;
dmm32 A0.x, 0x00000000;
imm32 R0, 0xffffb33a;
imm32 R2, 0xffffb33a;
imm32 R3, 0xb33a4cc6;
R2 = (A0 -= R0.L * R3.H) (FU);
checkreg R2, 0x00000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x58908a90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY);
dmm32 ASTAT, (0x2cc00c90 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
dmm32 A0.w, 0x00a38000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x2aa2ffff;
imm32 R1, 0xff5c711e;
imm32 R4, 0x2913dc90;
R0 = (A0 -= R4.L * R1.L) (IU);
checkreg R0, 0x00000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x2cc00c90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3880c280 | _VS | _AC1 | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x139ad315;
imm32 R6, 0x7fff0000;
R4.L = (A0 -= R6.H * R6.H) (FU);
checkreg R4, 0x139a0000;
checkreg ASTAT, (0x3880c280 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AZ);
dmm32 ASTAT, (0x48408290 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x6b426a69;
dmm32 A0.x, 0xffffffba;
imm32 R0, 0x24038000;
imm32 R2, 0xf62c7780;
imm32 R3, 0x5a64f8e8;
R2.L = (A0 -= R3.L * R0.L) (IH);
checkreg R2, 0xf62c8000;
checkreg A0.w, 0x80000000;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x48408290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x7c00c210 | _VS | _AC1 | _AN);
dmm32 A1.w, 0x730173e9;
dmm32 A1.x, 0xffffffae;
imm32 R4, 0x8000ffff;
imm32 R5, 0x738559e8;
R5.H = (A1 -= R4.L * R5.L) (M, IH);
checkreg R5, 0x800059e8;
checkreg A1.w, 0x80000000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x7c00c210 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY | _AN);
dmm32 ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AZ);
dmm32 A0.w, 0x033a05f0;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x5992dd5a;
imm32 R4, 0x098a889e;
imm32 R6, 0x8000de08;
R6.L = (A0 -= R4.L * R3.H) (TFU);
checkreg R6, 0x80000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x4830c400 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AZ);
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,034 | sim/testsuite/bfin/c_ldst_st_p_d_h.s | //Original:/testcases/core/c_ldst_st_p_d_h/c_ldst_st_p_d_h.dsp
// Spec Reference: c_ldst st_p d h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
W [ P5 ] = R0;
W [ P1 ] = R1;
W [ P2 ] = R2;
W [ P4 ] = R4;
W [ FP ] = R5;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20212618;
CHECKREG r1, 0x40413729;
CHECKREG r3, 0x8081594B;
CHECKREG r4, 0x00011507;
CHECKREG r5, 0xA0A16A5C;
CHECKREG r7, 0x719A8C7E;
imm32 r0, 0x1a231507;
imm32 r1, 0x11342618;
imm32 r2, 0x2c153729;
imm32 r3, 0x3d51483a;
imm32 r4, 0x4e67194b;
imm32 r5, 0x5f78615c;
imm32 r6, 0x60897b1d;
imm32 r7, 0x719a8c71;
W [ P5 ] = R1;
W [ P1 ] = R2;
W [ P2 ] = R3;
W [ P4 ] = R5;
W [ FP ] = R6;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20213729;
CHECKREG r1, 0x4041483A;
CHECKREG r3, 0x8081615C;
CHECKREG r4, 0x00012618;
CHECKREG r5, 0xA0A17B1D;
CHECKREG r6, 0x60897b1d;
imm32 r0, 0x2a231507;
imm32 r1, 0x12342618;
imm32 r2, 0x2c253729;
imm32 r3, 0x3d52483a;
imm32 r4, 0x4e67294b;
imm32 r5, 0x5f78625c;
imm32 r6, 0x60897b2d;
imm32 r7, 0x719a8c72;
W [ P5 ] = R2;
W [ P1 ] = R3;
W [ P2 ] = R4;
W [ P4 ] = R6;
W [ FP ] = R7;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x2021483A;
CHECKREG r1, 0x4041294B;
CHECKREG r3, 0x80817B2D;
CHECKREG r4, 0x00013729;
CHECKREG r5, 0xA0A18C72;
CHECKREG r7, 0x719A8C72;
imm32 r0, 0x3a231507;
imm32 r1, 0x13342618;
imm32 r2, 0x2c353729;
imm32 r3, 0x3d53483a;
imm32 r4, 0x4e67394b;
imm32 r5, 0x5f78635c;
imm32 r6, 0x60897b3d;
imm32 r7, 0x719a8c73;
W [ P5 ] = R3;
W [ P1 ] = R4;
W [ P2 ] = R5;
W [ P4 ] = R7;
W [ FP ] = R0;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x2021394B;
CHECKREG r1, 0x4041635C;
CHECKREG r3, 0x80818C73;
CHECKREG r4, 0x0001483A;
CHECKREG r5, 0xA0A11507;
CHECKREG r7, 0x719A8C73;
imm32 r0, 0x4a231507;
imm32 r1, 0x14342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d54483a;
imm32 r4, 0x4e67494b;
imm32 r5, 0x5f78645c;
imm32 r6, 0x60897b4d;
imm32 r7, 0x719a8c74;
W [ P5 ] = R4;
W [ P1 ] = R5;
W [ P2 ] = R6;
W [ P4 ] = R0;
W [ FP ] = R1;
W [ P5 ] = R5;
W [ P1 ] = R6;
W [ P2 ] = R7;
W [ P4 ] = R1;
W [ FP ] = R2;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20217B4D;
CHECKREG r1, 0x40418C74;
CHECKREG r3, 0x80812618;
CHECKREG r4, 0x0001645C;
CHECKREG r5, 0xA0A13729;
CHECKREG r7, 0x719A8C74;
imm32 r0, 0x5a231507;
imm32 r1, 0x15342618;
imm32 r2, 0x2c553729;
imm32 r3, 0x3d55483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f78655c;
imm32 r6, 0x60897b5d;
imm32 r7, 0x719a8c75;
W [ P5 ] = R6;
W [ P1 ] = R7;
W [ P2 ] = R0;
W [ P4 ] = R2;
W [ FP ] = R3;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20218C75;
CHECKREG r1, 0x40411507;
CHECKREG r3, 0x80813729;
CHECKREG r4, 0x00017B5D;
CHECKREG r5, 0xA0A1483A;
CHECKREG r7, 0x719A8C75;
imm32 r0, 0x6a231507;
imm32 r1, 0x16342618;
imm32 r2, 0x2c653729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67694b;
imm32 r5, 0x5f78665c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c76;
W [ P5 ] = R7;
W [ P1 ] = R0;
W [ P2 ] = R1;
W [ P4 ] = R3;
W [ FP ] = R4;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
CHECKREG r0, 0x20211507;
CHECKREG r1, 0x40412618;
CHECKREG r3, 0x8081483A;
CHECKREG r4, 0x00018C76;
CHECKREG r5, 0xA0A1694B;
CHECKREG r7, 0x719A8C76;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,531 | sim/testsuite/bfin/c_dagmodim_lz_inc_dec.s | //Original:/testcases/core/c_dagmodim_lz_inc_dec/c_dagmodim_lz_inc_dec.dsp
// Spec Reference: dagmodim L=0, I incremented & decremented (by M)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x10001000;
imm32 i1, 0x02001100;
imm32 i2, 0x00301010;
imm32 i3, 0x00041001;
imm32 m0, 0x00000005;
imm32 m1, 0x00000006;
imm32 m2, 0x00000007;
imm32 m3, 0x00000008;
I0 += M0;
I1 += M1;
I2 += M2;
I3 += M3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M1;
I1 += M2;
I2 += M3;
I3 += M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x10001005;
CHECKREG r1, 0x02001106;
CHECKREG r2, 0x00301017;
CHECKREG r3, 0x00041009;
CHECKREG r4, 0x1000100B;
CHECKREG r5, 0x0200110D;
CHECKREG r6, 0x0030101F;
CHECKREG r7, 0x0004100E;
I0 -= M2;
I1 -= M3;
I2 -= M0;
I3 -= M1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= M3;
I1 -= M2;
I2 -= M1;
I3 -= M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x10001004;
CHECKREG r1, 0x02001105;
CHECKREG r2, 0x0030101A;
CHECKREG r3, 0x00041008;
CHECKREG r4, 0x10000FFC;
CHECKREG r5, 0x020010FE;
CHECKREG r6, 0x00301014;
CHECKREG r7, 0x00041003;
I0 += M3 (BREV);
I1 += M0 (BREV);
I2 += M1 (BREV);
I3 += M2 (BREV);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M2 (BREV);
I1 += M3 (BREV);
I2 += M0 (BREV);
I3 += M1 (BREV);
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x10000FF2;
CHECKREG r1, 0x020010F8;
CHECKREG r2, 0x00301011;
CHECKREG r3, 0x00041005;
CHECKREG r4, 0x10000FF4;
CHECKREG r5, 0x020010F4;
CHECKREG r6, 0x00301014;
CHECKREG r7, 0x00041000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,876 | sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s | //Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp
// Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xf3545abd;
imm32 r1, 0x7fbcfec7;
imm32 r2, 0xc7fff679;
imm32 r3, 0xd0799007;
imm32 r4, 0xefb79f69;
imm32 r5, 0xcd35700b;
imm32 r6, 0xe00c87fd;
imm32 r7, 0xf78e909f;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (TFU);
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (TFU);
R3 = A0.w;
A1 += R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ) (TFU);
R5 = A0.w;
A1 += R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (TFU);
R7 = A0.w;
CHECKREG r0, 0xF3545A4E;
CHECKREG r1, 0x5A4E0EEB;
CHECKREG r2, 0xC7FF0000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xEFB70000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xE00C8380;
CHECKREG r7, 0x83808956;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0xc5548abd;
imm32 r1, 0x9b5cfec7;
imm32 r2, 0xa9b55679;
imm32 r3, 0xb09b5007;
imm32 r4, 0xcfb9b5c9;
imm32 r5, 0x52359b5c;
imm32 r6, 0xe50c5098;
imm32 r7, 0x675e7509;
R0.L = ( A0 = R1.L * R0.L ) (TFU);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (TFU);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.L ) (TFU);
R5 = A0.w;
R6.L = ( A0 -= R6.H * R7.H ) (TFU);
R7 = A0.w;
CHECKREG r0, 0xC5548A13;
CHECKREG r1, 0x8A135EEB;
CHECKREG r2, 0xA9B5C5BA;
CHECKREG r3, 0xC5BAEA2E;
CHECKREG r4, 0xCFB97E0F;
CHECKREG r5, 0x7E0FA97C;
CHECKREG r6, 0xE50C2193;
CHECKREG r7, 0x2193BB14;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x4b54babd;
imm32 r1, 0x12346ec7;
imm32 r2, 0xa4bbe679;
imm32 r3, 0x8abdb707;
imm32 r4, 0x9f4b7b69;
imm32 r5, 0xa234877b;
imm32 r6, 0xb00c4887;
imm32 r7, 0xc78ea4b8;
R0.L = ( A0 -= R1.L * R0.L ) (TFU);
R1 = A0.w;
R2.L = ( A0 = R2.H * R3.L ) (TFU);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.H ) (TFU);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (TFU);
R7 = A0.w;
CHECKREG r0, 0x4B540000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xA4BB75C6;
CHECKREG r3, 0x75C62E1D;
CHECKREG r4, 0x9F4B10D8;
CHECKREG r5, 0x10D85CE1;
CHECKREG r6, 0xB00C4961;
CHECKREG r7, 0x496188C3;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x1a545abd;
imm32 r1, 0x42fcfec7;
imm32 r2, 0xc53f5679;
imm32 r3, 0x9c64f007;
imm32 r4, 0xafc7ec69;
imm32 r5, 0xd23c891b;
imm32 r6, 0xc00cc602;
imm32 r7, 0x678edc7e;
A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (TFU);
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (TFU);
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (TFU);
R5 = A0.w;
A1 -= R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (TFU);
R1 = A0.w;
CHECKREG r0, 0x1A5498EA;
CHECKREG r1, 0x98EA3745;
CHECKREG r2, 0xC53FA3AF;
CHECKREG r3, 0xA3AF97AE;
CHECKREG r4, 0xAFC7905A;
CHECKREG r5, 0x905A70A4;
CHECKREG r6, 0xC00C2ED1;
CHECKREG r7, 0x2ED15DDC;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,192 | sim/testsuite/bfin/c_dsp32mac_pair_a1.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp
// Spec Reference: dsp32mac pair a1
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L;
P1 = A1.w;
R1 = ( A1 = R2.L * R3.L ), A0 += R2.H * R3.L;
P2 = A1.w;
R3 = ( A1 -= R7.L * R4.L ), A0 += R7.H * R4.H;
P3 = A1.w;
R5 = ( A1 -= R6.L * R5.L ), A0 -= R6.L * R5.H;
P4 = A1.w;
CHECKREG r0, 0x63545ABD;
CHECKREG r1, 0x0004BA9E;
CHECKREG r2, 0xA8645679;
CHECKREG r3, 0xE8616512;
CHECKREG r4, 0xEFB86569;
CHECKREG r5, 0xF0688FB4;
CHECKREG r6, 0x000C086D;
CHECKREG r7, 0xFF221DD6;
CHECKREG p1, 0xFF221DD6;
CHECKREG p2, 0x0004BA9E;
CHECKREG p3, 0xE8616512;
CHECKREG p4, 0xF0688FB4;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L;
P1 = A1.w;
R1 = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L;
P2 = A1.w;
R3 = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H;
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H;
P4 = A1.w;
CHECKREG r0, 0x98764ABD;
CHECKREG r1, 0x012F2306;
CHECKREG r2, 0xA1145649;
CHECKREG r3, 0x0117ACDA;
CHECKREG r4, 0xEFBC1569;
CHECKREG r5, 0xF97C8728;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xF97C8728;
CHECKREG p2, 0x0000AC92;
CHECKREG p3, 0x0117ACDA;
CHECKREG p4, 0x012F2306;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L;
P1 = A1.w;
R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L;
P2 = A1.w;
R1 = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H;
P3 = A1.w;
R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H;
P4 = A1.w;
CHECKREG r0, 0x7136459D;
CHECKREG r1, 0xCABE16DA;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xEF9C1569;
CHECKREG r5, 0xCABE9156;
CHECKREG r6, 0x0003401D;
CHECKREG r7, 0xD363146A;
CHECKREG p1, 0xD3694382;
CHECKREG p2, 0xD363146A;
CHECKREG p3, 0xCABE16DA;
CHECKREG p4, 0xCABE9156;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L;
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L;
P2 = A1.w;
R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H;
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H;
P4 = A1.w;
CHECKREG r0, 0x123489BD;
CHECKREG r1, 0xDBB6D160;
CHECKREG r2, 0xA9145679;
CHECKREG r3, 0x18A4A070;
CHECKREG r4, 0xEDB91569;
CHECKREG r5, 0x09DF3640;
CHECKREG r6, 0x0D0C0999;
CHECKREG r7, 0x08024998;
CHECKREG p1, 0xDBB6D160;
CHECKREG p2, 0x18A4A070;
CHECKREG p3, 0x09DF3640;
CHECKREG p4, 0x08024998;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,403 | sim/testsuite/bfin/m7.s | // Test result extraction of mac instructions.
// Test basic edge values
// UNSIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80000001
// load r1=0x80007fff
// load r2=0xf000ffff
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extraction with no saturation (truncate)
// 0x8000 * 0x7fff = 0x003fff8000 -> 0x3fff
A1 = A0 = 0;
R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (TFU);
DBGA ( R5.L , 0x3fff );
DBGA ( R5.H , 0x3fff );
// extraction with no saturation (round)
// 0x8000 * 0x7fff = 0x003fff8000 -> 0x4000
A1 = A0 = 0;
R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L) (FU);
DBGA ( R5.L , 0x4000 );
DBGA ( R5.H , 0x4000 );
// extraction with no saturation
// 0xffff * 0xffff = 0x00fffe0001 -> 0xfffe
A1 = A0 = 0;
R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU);
DBGA ( R5.L , 0xfffe );
DBGA ( R5.H , 0xfffe );
// extraction with saturation
//0x7ffffe0001 -> 0xffff
A1 = A0 = 0;
A1.x = R3.L;
A0.x = R3.L;
R5.H = (A1 += R2.L * R2.L), R5.L = (A0 += R2.L * R2.L) (FU);
DBGA ( R5.L , 0xffff );
DBGA ( R5.H , 0xffff );
pass
.data
data0:
.dw 0x0001
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0xffff
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 4,150 | sim/testsuite/bfin/c_ccflag_pr_pr_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_pr_pr_uu/c_ccflag_pr_pr_uu.dsp
// Spec Reference: ccflag pr-pr (uu)
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
//imm32 p0, 0x00110022;
imm32 p1, 0x00110022;
imm32 p2, 0x00330044;
imm32 p3, 0x00550066;
imm32 p4, 0x00770088;
imm32 p5, 0x009900aa;
imm32 fp, 0x00bb00cc;
imm32 sp, 0x00000000;
ASTAT = R0;
R4 = ASTAT;
// positive preg-1 EQUAL to positive preg-2
CC = P2 < P1 (IU);
R6 = ASTAT;
CC = P2 <= P1 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// positive preg-1 GREATER than positive preg-2
CC = P3 < P2 (IU);
R6 = ASTAT;
CC = P3 <= P2 (IU);
R7 = ASTAT;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// positive preg-1 LESS than positive preg-2
CC = P2 < P3 (IU);
R6 = ASTAT;
CC = P2 <= P3 (IU);
R7 = ASTAT;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000020;
//imm32 p0, 0x01230123;
imm32 p1, 0x81230123;
imm32 p2, 0x04560456;
imm32 p3, 0x87890789;
// operate on negative number
R0 = 0;
ASTAT = R0;
R4 = ASTAT;
// positive preg-1 GREATER than negative preg-2
CC = P2 < P1 (IU);
R6 = ASTAT;
CC = P2 <= P1 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000020;
// negative preg-1 LESS than POSITIVE preg-2 small
CC = P3 < P2 (IU);
R6 = ASTAT;
CC = P3 <= P2 (IU);
R7 = ASTAT;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// negative preg-1 GREATER than negative preg-2
CC = P1 < P3 (IU);
R6 = ASTAT;
CC = P1 <= P3 (IU);
R7 = ASTAT;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000020;
// negative preg-1 LESS than negative preg-2
CC = P3 < P1 (IU);
R6 = ASTAT;
CC = P3 <= P1 (IU);
R7 = ASTAT;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
//imm32 p0, 0x80230123;
imm32 p1, 0x00230123;
imm32 p2, 0x80560056;
imm32 p3, 0x00890089;
// operate on negative number
R0 = 0;
ASTAT = R0;
R4 = ASTAT;
// negative preg-1 LESS than POSITIVE preg-2
CC = P2 < P3 (IU);
R6 = ASTAT;
CC = P2 <= P3 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000; // overflow and carry but not negative
CHECKREG r6, 0x00000000; // cc overflow, carry and negative
CHECKREG r7, 0x00000000;
imm32 p4, 0x44444444;
imm32 p5, 0x55555555;
imm32 fp, 0x66666666;
imm32 sp, 0x77777777;
//imm32 p0, 0x00000000;
imm32 p1, 0x11111111;
imm32 p2, 0x00000000;
imm32 p3, 0x33333333;
ASTAT = R0;
R3 = ASTAT;
CHECKREG r3, 0x00000000;
// positive preg-1 EQUAL to positive preg-2
CC = P4 < P5;
R1 = ASTAT;
CC = P4 <= P5;
R2 = ASTAT;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
// positive preg-1 GREATER than positive preg-2
CC = SP < FP (IU);
R1 = ASTAT;
CC = SP <= FP (IU);
R2 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
// positive preg-1 LESS than positive preg-2
CC = FP < SP (IU);
R1 = ASTAT;
CC = FP <= SP (IU);
R2 = ASTAT;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
imm32 p4, 0x01230123;
imm32 p5, 0x81230123;
imm32 fp, 0x04560456;
imm32 sp, 0x87890789;
// operate on negative number
R0 = 0;
ASTAT = R0;
R3 = ASTAT; // nop;
CHECKREG r3, 0x00000000;
// positive preg-1 GREATER than negative preg-2
CC = P4 < P5 (IU);
R2 = ASTAT;
CC = P4 <= P5 (IU);
R3 = ASTAT;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000020;
// negative preg-1 LESS than POSITIVE preg-2 small
CC = SP < FP (IU);
R1 = ASTAT;
CC = SP <= FP (IU);
R2 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
// negative preg-1 GREATER than negative preg-2
CC = P5 < SP (IU);
R1 = ASTAT;
CC = P5 <= SP (IU);
R2 = ASTAT;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000020;
// negative preg-1 LESS than negative preg-2
CC = SP < P5 (IU);
R2 = ASTAT;
CC = SP <= P5 (IU);
R3 = ASTAT;
CHECKREG r1, 0x00000020;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
imm32 p4, 0x80230123;
imm32 p5, 0x00230123;
imm32 fp, 0x80560056;
imm32 sp, 0x00890089;
// operate on negative number
R0 = 0;
ASTAT = R0;
R0 = ASTAT;
// negative preg-1 LESS than POSITIVE preg-2
CC = R6 < R7 (IU);
R2 = ASTAT;
CC = R6 <= R7 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00000000; // overflow and carry but not negative
CHECKREG r2, 0x00001005; // cc overflow, carry and negative
CHECKREG r3, 0x00001025;
pass;
|
tactcomplabs/xbgas-binutils-gdb | 6,993 | sim/testsuite/bfin/c_ldst_st_p_p_mm.s | //Original:testcases/core/c_ldst_st_p_p_mm/c_ldst_st_p_p_mm.dsp
// Spec Reference: c_ldst st p-- p
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// initial values p-p
imm32 p5, 0x0a231507;
imm32 p1, 0x1b342618;
imm32 p2, 0x2c453729;
imm32 p3, 0x4356789a;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_5, 0x18;
loadsym fp, DATA_ADDR_6, 0x18;
loadsym i3, DATA_ADDR_7, 0x18;
P3 = I1; SP = I3;
[ P4 -- ] = P1;
[ FP -- ] = P2;
[ SP -- ] = R3;
[ P4 -- ] = P2;
[ FP -- ] = P3;
[ SP -- ] = P5;
[ P4 -- ] = P3;
[ FP -- ] = P5;
[ SP -- ] = P1;
[ P4 -- ] = P5;
[ FP -- ] = P1;
[ SP -- ] = P2;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_5, 0x18;
loadsym fp, DATA_ADDR_6, 0x18;
loadsym i3, DATA_ADDR_7, 0x18;
P3 = I1; SP = I3;
R1 = [ P4 -- ];
R2 = [ FP -- ];
R3 = [ SP -- ];
R4 = [ P4 -- ];
R5 = [ FP -- ];
R6 = [ SP -- ];
CHECKREG r1, 0x1B342618;
CHECKREG r2, 0x2C453729;
CHECKREG r3, 0x3D56483A;
CHECKREG r4, 0x2C453729;
CHECKREG r5, 0x4356789A;
CHECKREG r6, 0x0A231507;
R1 = [ P4 -- ];
R2 = [ FP -- ];
R3 = [ SP -- ];
R4 = [ P4 -- ];
R5 = [ FP -- ];
R6 = [ SP -- ];
CHECKREG r1, 0x4356789A;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x0A231507;
CHECKREG r5, 0x1B342618;
CHECKREG r6, 0x2C453729;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x10000080
.dd 0x02000800
.dd 0x00207000
.dd 0x000d0000
.dd 0x0006b000
.dd 0x00500a00
.dd 0x0d0000f0
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x10006000
.dd 0xa2050800
.dd 0x0c30db00
.dd 0x00b40000
.dd 0xa0045000
.dd 0x0000f600
.dd 0x00d00070
.dd 0x00000008
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x10000000
.dd 0x0d000000
.dd 0x00400000
.dd 0x000b0000
.dd 0x000d0b00
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 1,919 | sim/testsuite/bfin/c_dsp32alu_byteop3.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_byteop3/c_dsp32alu_byteop3.dsp
// Spec Reference: dsp32alu byteop3
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R5 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
R6 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
CHECKREG r4, 0x00FF0000;
CHECKREG r5, 0xFF000000;
CHECKREG r6, 0x00FF0000;
CHECKREG r7, 0xFF000000;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7cccdd2d;
imm32 r7, 0x8eeeffff;
R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
CHECKREG r0, 0x00FF00FF;
CHECKREG r1, 0x00FF00FF;
CHECKREG r2, 0xFF00FF00;
CHECKREG r3, 0x00000000;
imm32 r0, 0x716789ab;
imm32 r1, 0x8289abcd;
imm32 r2, 0x93445555;
imm32 r3, 0xa4667777;
imm32 r4, 0xb56789ab;
imm32 r5, 0xd689abcd;
imm32 r6, 0xe7445555;
imm32 r7, 0x6f661235;
R4 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R5 = BYTEOP3P ( R1:0 , R3:2 ) (LO);
R6 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
R7 = BYTEOP3P ( R1:0 , R3:2 ) (HI);
CHECKREG r4, 0x00FF0000;
CHECKREG r5, 0x00FF0000;
CHECKREG r6, 0xFF000000;
CHECKREG r7, 0xFF000000;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R1 = BYTEOP3P ( R3:2 , R1:0 ) (LO);
R2 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
R3 = BYTEOP3P ( R3:2 , R1:0 ) (HI);
CHECKREG r0, 0x00FF00FF;
CHECKREG r1, 0x00FF00FF;
CHECKREG r2, 0xFF00FF00;
CHECKREG r3, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,856 | sim/testsuite/bfin/byteop2p.s | # Blackfin testcase for BYTEOP2P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req
dmm32 I0, \i0
R6 = BYTEOP2P (R1:0, R3:2) (rndl);
check_it \resRL
R6 = BYTEOP2P (R1:0, R3:2) (rndh);
check_it \resRH
R6 = BYTEOP2P (R1:0, R3:2) (tl);
check_it \resTL
R6 = BYTEOP2P (R1:0, R3:2) (th);
check_it \resTH
R6 = BYTEOP2P (R1:0, R3:2) (rndl, r);
check_it \resRLr
R6 = BYTEOP2P (R1:0, R3:2) (rndh, r);
check_it \resRHr
R6 = BYTEOP2P (R1:0, R3:2) (tl, r);
check_it \resTLr
R6 = BYTEOP2P (R1:0, R3:2) (th, r);
check_it \resTHr
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop2p 0, 0x00060008, 0x06000800, 0x00060008, 0x06000800, 0x00600080, 0x60008000, 0x00600080, 0x60008000
test_byteop2p 1, 0x00470007, 0x47000700, 0x00460007, 0x46000700, 0x00300070, 0x30007000, 0x00300070, 0x30007000
test_byteop2p 2, 0x00800006, 0x80000600, 0x00800006, 0x80000600, 0x00080060, 0x08006000, 0x00080060, 0x08006000
test_byteop2p 3, 0x00700047, 0x70004700, 0x00700046, 0x70004600, 0x00070030, 0x07003000, 0x00070030, 0x07003000
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop2p 0, 0x00f900f7, 0xf900f700, 0x00f900f7, 0xf900f700, 0x009f007f, 0x9f007f00, 0x009f007f, 0x9f007f00
test_byteop2p 1, 0x00b800f8, 0xb800f800, 0x00b800f8, 0xb800f800, 0x00cf008f, 0xcf008f00, 0x00ce008f, 0xce008f00
test_byteop2p 2, 0x007f00f9, 0x7f00f900, 0x007f00f9, 0x7f00f900, 0x00f7009f, 0xf7009f00, 0x00f7009f, 0xf7009f00
test_byteop2p 3, 0x008f00b8, 0x8f00b800, 0x008f00b8, 0x8f00b800, 0x00f800cf, 0xf800cf00, 0x00f800ce, 0xf800ce00
pass
|
tactcomplabs/xbgas-binutils-gdb | 12,527 | sim/testsuite/bfin/c_ldstidxl_st_preg.s | //Original:testcases/core/c_ldstidxl_st_preg/c_ldstidxl_st_preg.dsp
// Spec Reference: c_ldstidxl store preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
P3 = 0x0123 (X);
P4 = 0x4567 (X);
P5 = 0x79ab (X);
FP = 0x6def (X);
SP = 0x1ace (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x0000;
loadsym p2, DATA_ADDR_2, 0x00c8;
P3 = I1; SP = I3;
[ P1 + 0x1004 ] = P5;
[ P1 + 0x1008 ] = P3;
[ P1 + 0x1014 ] = P4;
[ P1 + 0x1018 ] = P3;
[ P2 + -0x1020 ] = P4;
[ P2 + -0x1024 ] = P5;
[ P2 + -0x1028 ] = SP;
[ P2 + -0x1034 ] = FP;
R6 = [ P1 + 0x1004 ];
R5 = [ P1 + 0x1008 ];
R4 = [ P1 + 0x1014 ];
R3 = [ P1 + 0x1018 ];
R2 = [ P2 + -0x1020 ];
R7 = [ P2 + -0x1024 ];
R0 = [ P2 + -0x1028 ];
R1 = [ P2 + -0x1034 ];
CHECKREG r0, 0x00001ACE;
CHECKREG r1, 0x00006DEF;
CHECKREG r2, 0x00004567;
CHECKREG r3, 0x00000123;
CHECKREG r4, 0x00004567;
CHECKREG r5, 0x00000123;
CHECKREG r6, 0x000079AB;
CHECKREG r7, 0x000079AB;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
P1 = 0x3456 (X);
P2 = 0x1234 (X);
P5 = 0x5e23 (X);
FP = 0x2ac5 (X);
SP = 0x6378 (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_1, 0x0000;
loadsym p4, DATA_ADDR_2, 0x00c8;
P3 = I1; SP = I3;
[ P3 + 0x1034 ] = P2;
[ P3 + 0x1040 ] = P1;
[ P3 + 0x1044 ] = P2;
[ P3 + 0x1048 ] = P1;
[ P4 + -0x1054 ] = P2;
[ P4 + -0x1058 ] = P5;
[ P4 + -0x1060 ] = SP;
[ P4 + -0x1064 ] = FP;
R3 = [ P3 + 0x1034 ];
R4 = [ P3 + 0x1040 ];
R0 = [ P3 + 0x1044 ];
R1 = [ P3 + 0x1048 ];
R2 = [ P4 + -0x1054 ];
R5 = [ P4 + -0x1058 ];
R6 = [ P4 + -0x1060 ];
R7 = [ P4 + -0x1064 ];
CHECKREG r0, 0x00001234;
CHECKREG r1, 0x00003456;
CHECKREG r2, 0x00001234;
CHECKREG r3, 0x00001234;
CHECKREG r4, 0x00003456;
CHECKREG r5, 0x00005E23;
CHECKREG r6, 0x00006378;
CHECKREG r7, 0x00002AC5;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
P1 = 0x2125 (X);
P2 = 0x7345 (X);
P3 = 0x3230 (X);
P4 = 0x5789 (X);
FP = 0x5bcd (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x0000;
loadsym i3, DATA_ADDR_2, 0x00c8;
P3 = I1; SP = I3;
[ P5 + 0x1004 ] = P2;
[ P5 + 0x1008 ] = P1;
[ P5 + 0x1014 ] = P2;
[ P5 + 0x1018 ] = P3;
[ SP + -0x1020 ] = P4;
[ SP + -0x1024 ] = P2;
[ SP + -0x1028 ] = P3;
[ SP + -0x1034 ] = FP;
R6 = [ P5 + 0x1004 ];
R5 = [ P5 + 0x1008 ];
R4 = [ P5 + 0x1014 ];
R3 = [ P5 + 0x1018 ];
R2 = [ SP + -0x1020 ];
R0 = [ SP + -0x1024 ];
R7 = [ SP + -0x1028 ];
R1 = [ SP + -0x1034 ];
CHECKREG r0, 0x00007345;
CHECKREG r1, 0x00005BCD;
CHECKREG r2, 0x00005789;
CHECKREG r3, 0x00003230;
CHECKREG r4, 0x00007345;
CHECKREG r5, 0x00002125;
CHECKREG r6, 0x00007345;
CHECKREG r7, 0x00003230;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
P1 = 0x5bcd (X);
P2 = 0x1122 (X);
P3 = 0x3455 (X);
P4 = 0x6677 (X);
P5 = 0x58ab (X);
SP = 0x1ace (X);
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0x0010;
P3 = I1; SP = I3;
[ FP + 0x1034 ] = P1;
[ FP + 0x2040 ] = P1;
[ FP + 0x1144 ] = P2;
[ FP + 0x2048 ] = P3;
[ FP + 0x1050 ] = P4;
[ FP + 0x2058 ] = P5;
[ FP + 0x1160 ] = P2;
[ FP + 0x2064 ] = SP;
R3 = [ FP + 0x1034 ];
R4 = [ FP + 0x2040 ];
R0 = [ FP + 0x1144 ];
R1 = [ FP + 0x2048 ];
R2 = [ FP + 0x1050 ];
R5 = [ FP + 0x2058 ];
R6 = [ FP + 0x1160 ];
R7 = [ FP + 0x2064 ];
CHECKREG r0, 0x00001122;
CHECKREG r1, 0x00003455;
CHECKREG r2, 0x00006677;
CHECKREG r3, 0x00005BCD;
CHECKREG r4, 0x00005BCD;
CHECKREG r5, 0x000058AB;
CHECKREG r6, 0x00001122;
CHECKREG r7, 0x00001ace;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
// Make sure there is space between the text and data sections
.space (0x2000);
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_2:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
// Make sure there is space for us to scribble
.space (0x2000);
|
tactcomplabs/xbgas-binutils-gdb | 1,530 | sim/testsuite/bfin/c_ldimmhalf_drlo.s | //Original:/testcases/core/c_ldimmhalf_drlo/c_ldimmhalf_drlo.dsp
// Spec Reference: ldimmhalf dreg lo
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.L = 0x0001;
R1.L = 0x0003;
R2.L = 0x0005;
R3.L = 0x0007;
R4.L = 0x0009;
R5.L = 0x000b;
R6.L = 0x000d;
R7.L = 0x000f;
CHECKREG r0, 0xFFFF0001;
CHECKREG r1, 0xFFFF0003;
CHECKREG r2, 0xFFFF0005;
CHECKREG r3, 0xFFFF0007;
CHECKREG r4, 0xFFFF0009;
CHECKREG r5, 0xFFFF000b;
CHECKREG r6, 0xFFFF000D;
CHECKREG r7, 0xFFFF000F;
R0.L = 0x0020;
R1.L = 0x0040;
R2.L = 0x0060;
R3.L = 0x0080;
R4.L = 0x00a0;
R5.L = 0x00b0;
R6.L = 0x00c0;
R7.L = 0x00d0;
CHECKREG r0, 0xFFFF0020;
CHECKREG r1, 0xFFFF0040;
CHECKREG r2, 0xFFFF0060;
CHECKREG r3, 0xFFFF0080;
CHECKREG r4, 0xFFFF00a0;
CHECKREG r5, 0xFFFF00b0;
CHECKREG r6, 0xFFFF00c0;
CHECKREG r7, 0xFFFF00d0;
R0.L = 0x0100;
R1.L = 0x0200;
R2.L = 0x0300;
R3.L = 0x0400;
R4.L = 0x0500;
R5.L = 0x0600;
R6.L = 0x0700;
R7.L = 0x0800;
CHECKREG r0, 0xFFFF0100;
CHECKREG r1, 0xFFFF0200;
CHECKREG r2, 0xFFFF0300;
CHECKREG r3, 0xFFFF0400;
CHECKREG r4, 0xFFFF0500;
CHECKREG r5, 0xFFFF0600;
CHECKREG r6, 0xFFFF0700;
CHECKREG r7, 0xFFFF0800;
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.L = 0x7fff;
R1.L = 0x7ffe;
R2.L = -32768;
R3.L = -32767;
R4.L = 32767;
R5.L = 32766;
R6.L = 32765;
R7.L = 32764;
CHECKREG r0, 0x00007fff;
CHECKREG r1, 0x00007ffe;
CHECKREG r2, 0x00008000;
CHECKREG r3, 0x00008001;
CHECKREG r4, 0x00007FFF;
CHECKREG r5, 0x00007FFE;
CHECKREG r6, 0x00007FFD;
CHECKREG r7, 0x00007FFC;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,782 | sim/testsuite/bfin/random_0014.S | # Test a few corner cases with various shift insns
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xf53d356e;
dmm32 A0.x, 0xffffffff;
imm32 R5, 0xaa156b54;
A0 = ASHIFT A0 BY R5.L;
checkreg A0.w, 0x56e00000;
checkreg A0.x, 0xffffffd3;
checkreg ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY);
dmm32 A0.w, 0x1dfd2a85;
dmm32 A0.x, 0xffffffbe;
imm32 R2, 0x4b7cf707;
A0 = LSHIFT A0 BY R2.L;
checkreg A0.w, 0xfe954280;
checkreg A0.x, 0x0000000e;
checkreg ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY);
dmm32 ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xd4aa6e10;
dmm32 A1.x, 0xffffffff;
imm32 R4, 0xb4bb3054;
A1 = ASHIFT A1 BY R4.L;
checkreg A1.w, 0xe1000000;
checkreg A1.x, 0xffffffa6;
checkreg ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x0dbadb4f;
dmm32 A1.x, 0x00000035;
imm32 R3, 0x3cc3f7db;
A1 = LSHIFT A1 BY R3.L;
checkreg A1.w, 0x78000000;
checkreg A1.x, 0xffffffda;
checkreg ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x14900e10 | _VS | _AC0 | _CC | _AC0_COPY);
imm32 R0, 0x6286ee56;
imm32 R7, 0x5cd969c5;
R0 = ASHIFT R0 BY R7.L;
checkreg R0, 0x50ddcac0;
checkreg ASTAT, (0x14900e10 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ);
imm32 R0, 0x00000000;
imm32 R5, 0x00008000;
imm32 R6, 0x03488f9a;
R0.L = ASHIFT R5.L BY R6.L;
checkreg ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ);
dmm32 ASTAT, (0x3c10c890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
imm32 R1, 0x29162006;
imm32 R3, 0xffff0345;
imm32 R4, 0x8ff5e6bb;
R1.H = ASHIFT R4.H BY R3.L;
checkreg R1, 0xfea02006;
checkreg ASTAT, (0x3c10c890 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78600e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC);
imm32 R0, 0xd5b1804d;
imm32 R1, 0x522c817d;
imm32 R5, 0xfca6f990;
R1.H = ASHIFT R5.H BY R0.L;
checkreg R1, 0xc000817d;
checkreg ASTAT, (0x78600e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R4, 0x80000000;
imm32 R6, 0x4e840a3e;
imm32 R7, 0x20102e48;
R6.L = ASHIFT R4.H BY R7.L;
checkreg R6, 0x4e840000;
checkreg ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,485 | sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_raise_rt_i_n/c_progctrl_raise_rt_i_n.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CHECK_INIT(p5, 0xe0000000);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
RAISE 2; // RTN
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
RAISE 15; // RTI
CHECKREG(r0, 0x0000000B);
CHECKREG(r1, 0x0000000C);
CHECKREG(r2, 0x0000000D);
CHECKREG(r3, 0x0000000E);
CHECKREG(r4, 0x00000007);
CHECKREG(r5, 0x00000008);
CHECKREG(r6, 0x00000009);
CHECKREG(r7, 0x0000000A);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
CHECKREG(r0, 0x00000002);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000005);
CHECKREG(r3, 0x00000006);
CHECKREG(r4, 0x00000007);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 11,066 | sim/testsuite/bfin/c_ldstidxl_st_dr_b.s | //Original:testcases/core/c_ldstidxl_st_dr_b/c_ldstidxl_st_dr_b.dsp
// Spec Reference: c_ldstidxl store dreg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x105f5080;
imm32 r1, 0x204e6091;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80b3;
imm32 r4, 0x501b90c4;
imm32 r5, 0x600aa0d5;
imm32 r6, 0x7019b0e6;
imm32 r7, 0xd028c0f7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0xc8;
loadsym i1, DATA_ADDR_1, 0x10;
loadsym p4, DATA_ADDR_2, 0xc8;
loadsym p5, DATA_ADDR_1, 0x00;
loadsym fp, DATA_ADDR_2, 0xc8;
loadsym i3, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
B [ P1 + 0x1101 ] = R0;
B [ P1 + 0x1013 ] = R1;
B [ P1 + 0x1015 ] = R2;
B [ P1 + 0x1007 ] = R3;
B [ P2 + -0x1019 ] = R4;
B [ P2 + -0x1011 ] = R5;
B [ P2 + -0x1013 ] = R6;
B [ P2 + -0x1015 ] = R7;
R6 = B [ P1 + 0x1101 ] (Z);
R5 = B [ P1 + 0x1013 ] (Z);
R4 = B [ P1 + 0x1015 ] (Z);
R3 = B [ P1 + 0x1007 ] (Z);
R2 = B [ P2 + -0x1019 ] (Z);
R7 = B [ P2 + -0x1011 ] (Z);
R0 = B [ P2 + -0x1013 ] (Z);
R1 = B [ P2 + -0x1015 ] (Z);
CHECKREG r0, 0x000000E6;
CHECKREG r1, 0x000000F7;
CHECKREG r2, 0x000000C4;
CHECKREG r3, 0x000000B3;
CHECKREG r4, 0x000000A2;
CHECKREG r5, 0x00000091;
CHECKREG r6, 0x00000080;
CHECKREG r7, 0x000000D5;
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
B [ P3 + 0x1011 ] = R0;
B [ P3 + 0x1023 ] = R1;
B [ P3 + 0x1025 ] = R2;
B [ P3 + 0x1027 ] = R3;
B [ P4 + -0x1029 ] = R4;
B [ P4 + -0x1021 ] = R5;
B [ P4 + -0x1033 ] = R6;
B [ P4 + -0x1035 ] = R7;
R3 = B [ P3 + 0x1011 ] (Z);
R4 = B [ P3 + 0x1023 ] (Z);
R0 = B [ P3 + 0x1025 ] (Z);
R1 = B [ P3 + 0x1027 ] (Z);
R2 = B [ P4 + -0x1029 ] (Z);
R5 = B [ P4 + -0x1021 ] (Z);
R6 = B [ P4 + -0x1033 ] (Z);
R7 = B [ P4 + -0x1035 ] (Z);
CHECKREG r0, 0x000000B2;
CHECKREG r1, 0x000000B3;
CHECKREG r2, 0x000000B4;
CHECKREG r3, 0x000000B0;
CHECKREG r4, 0x000000B1;
CHECKREG r5, 0x000000B5;
CHECKREG r6, 0x000000B6;
CHECKREG r7, 0x000000B7;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
B [ P5 + 0x1031 ] = R0;
B [ P5 + 0x1033 ] = R1;
B [ P5 + 0x1035 ] = R2;
B [ P5 + 0x1047 ] = R3;
B [ SP + -0x1049 ] = R4;
B [ SP + -0x1041 ] = R5;
B [ SP + -0x1043 ] = R6;
B [ SP + -0x1045 ] = R7;
R6 = B [ P5 + 0x1031 ] (Z);
R5 = B [ P5 + 0x1033 ] (Z);
R4 = B [ P5 + 0x1035 ] (Z);
R3 = B [ P5 + 0x1047 ] (Z);
R2 = B [ SP + -0x1049 ] (Z);
R0 = B [ SP + -0x1041 ] (Z);
R7 = B [ SP + -0x1043 ] (Z);
R1 = B [ SP + -0x1045 ] (Z);
CHECKREG r0, 0x000000C5;
CHECKREG r1, 0x000000C7;
CHECKREG r2, 0x000000C4;
CHECKREG r3, 0x000000C3;
CHECKREG r4, 0x000000C2;
CHECKREG r5, 0x000000C1;
CHECKREG r6, 0x000000C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
B [ FP + 0x1051 ] = R0;
B [ FP + 0x1053 ] = R1;
B [ FP + 0x1055 ] = R2;
B [ FP + 0x1057 ] = R3;
B [ FP + 0x1059 ] = R4;
B [ FP + 0x1061 ] = R5;
B [ FP + 0x1063 ] = R6;
B [ FP + 0x1065 ] = R7;
R3 = B [ FP + 0x1051 ] (Z);
R4 = B [ FP + 0x1053 ] (Z);
R0 = B [ FP + 0x1055 ] (Z);
R1 = B [ FP + 0x1057 ] (Z);
R2 = B [ FP + 0x1059 ] (Z);
R5 = B [ FP + 0x1061 ] (Z);
R6 = B [ FP + 0x1063 ] (Z);
R7 = B [ FP + 0x1065 ] (Z);
CHECKREG r0, 0x000000D2;
CHECKREG r1, 0x000000D3;
CHECKREG r2, 0x000000D4;
CHECKREG r3, 0x000000D0;
CHECKREG r4, 0x000000D1;
CHECKREG r5, 0x000000D5;
CHECKREG r6, 0x000000D6;
CHECKREG r7, 0x000000D7;
P3 = I0; SP = I2;
pass
// Pre-load memory witb known data
// More data is defined than will actually be used
.data
// Make sure there is space between the text and data sections
.space (0x2000);
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
// Make sure there is space for us to scribble
.space (0x2000);
|
tactcomplabs/xbgas-binutils-gdb | 6,097 | sim/testsuite/bfin/c_dsp32mult_dr_iu.s | //Original:/testcases/core/c_dsp32mult_dr_iu/c_dsp32mult_dr_iu.dsp
// Spec Reference: dsp32mult single dr iu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00010002;
imm32 r1, 0x00023004;
imm32 r2, 0x03843725;
imm32 r3, 0x00084027;
imm32 r4, 0x00ab5d29;
imm32 r5, 0x00ac682b;
imm32 r6, 0x000c708d;
imm32 r7, 0x02462028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IU);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IU);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IU);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IU);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IU);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IU);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IU);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IU);
CHECKREG r0, 0x00040004;
CHECKREG r1, 0xC0100008;
CHECKREG r2, 0x0020FFFF;
CHECKREG r3, 0x0040FFFF;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x60080004;
CHECKREG r6, 0x60080004;
CHECKREG r7, 0xFFFF0004;
imm32 r0, 0x00230635;
imm32 r1, 0x00995137;
imm32 r2, 0x00240735;
imm32 r3, 0x00060037;
imm32 r4, 0x009b0239;
imm32 r5, 0x00a9933b;
imm32 r6, 0x000c093d;
imm32 r7, 0x12407093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IU);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IU);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IU);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IU);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IU);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IU);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IU);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x2B3E00D8;
CHECKREG r6, 0xFFFF07BC;
CHECKREG r7, 0x014A014A;
imm32 r0, 0x09235655;
imm32 r1, 0x09ba5157;
imm32 r2, 0x03246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x00ab6509;
imm32 r5, 0x00ac7f5b;
imm32 r6, 0x000a005d;
imm32 r7, 0x0246405f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IU);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IU);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IU);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IU);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IU);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IU);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IU);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFF7390;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00230666;
imm32 r1, 0x00ba0166;
imm32 r2, 0x00240766;
imm32 r3, 0x00060066;
imm32 r4, 0x03ab0d69;
imm32 r5, 0x10ec3f6b;
imm32 r6, 0x000e206d;
imm32 r7, 0x00460e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IU);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IU);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IU);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IU);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IU);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IU);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IU);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IU);
CHECKREG r0, 0x00C4FFFF;
CHECKREG r1, 0x03D4FFFF;
CHECKREG r2, 0x03D4FFFF;
CHECKREG r3, 0x13241324;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00C4FFFF;
CHECKREG r7, 0x3598FFFF;
// mix order
imm32 r0, 0x0023a675;
imm32 r1, 0x00ba5127;
imm32 r2, 0x00c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x00accd09;
imm32 r5, 0x00acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x0246fc0f;
R0.H = R0.L * R7.H, R0.L = R0.H * R7.H (IU);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IU);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IU);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IU);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IU);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IU);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IU);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IU);
CHECKREG r0, 0xFFFF4F92;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00230a75;
imm32 r1, 0x00ba0127;
imm32 r2, 0x00240905;
imm32 r3, 0x00d60007;
imm32 r4, 0x00ab0d09;
imm32 r5, 0x00ac0ddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x0046000f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IU);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IU);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IU);
R3.H = R4.L * R3.H, R3.L = R4.H * R3.H (IU);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IU);
R5.H = R2.H * R5.L, R5.L = R2.L * R5.H (IU);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IU);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IU);
CHECKREG r0, 0x0992FFFF;
CHECKREG r1, 0x08B8FFFF;
CHECKREG r2, 0x1830FFFF;
CHECKREG r3, 0xFFFF8EF2;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x68A0FFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x0b230675;
imm32 r1, 0x00ba0127;
imm32 r2, 0x03f40705;
imm32 r3, 0x000f0007;
imm32 r4, 0x00ab0d09;
imm32 r5, 0x10ac0fdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246000f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IU);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IU);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IU);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IU);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IU);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IU);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IU);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFF4D7C;
CHECKREG r3, 0xFFFF0AE6;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x002d0675;
imm32 r1, 0x001a0027;
imm32 r2, 0x00240005;
imm32 r3, 0x000600d7;
imm32 r4, 0x008b0d09;
imm32 r5, 0x00a0000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x0006060f;
R3.H = R0.L * R2.L, R3.L = R0.L * R2.H (IU);
R4.H = R1.H * R3.L, R4.L = R1.H * R3.H (IU);
R5.H = R2.L * R4.L, R5.L = R2.L * R4.H (IU);
R6.H = R3.L * R5.H, R6.L = R3.L * R5.L (IU);
R0.H = R4.H * R6.L, R0.L = R4.H * R6.L (IU);
R1.H = R5.L * R7.H, R1.L = R5.H * R7.L (IU);
R2.H = R6.L * R0.L, R2.L = R6.L * R0.H (IU);
R7.H = R7.H * R1.L, R7.L = R7.L * R1.H (IU);
CHECKREG r0, 0xFFFFFFFF;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x2049E874;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,691 | sim/testsuite/bfin/c_dspldst_ld_dr_ippm.s | //Original:/testcases/core/c_dspldst_ld_dr_ippm/c_dspldst_ld_dr_ippm.dsp
// Spec Reference: c_dspldst ld_dr_i++m
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
M0 = 0 (X);
M1 = 0x4 (X);
M2 = 0x0 (X);
M3 = 0x4 (X);
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ M0 ];
R1 = [ I1 ++ M1 ];
R2 = [ I2 ++ M2 ];
R3 = [ I3 ++ M3 ];
R4 = [ I0 ++ M1 ];
R5 = [ I1 ++ M2 ];
R6 = [ I2 ++ M3 ];
R7 = [ I3 ++ M0 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r2, 0x40414243;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x00010203;
CHECKREG r5, 0x24252627;
CHECKREG r6, 0x40414243;
CHECKREG r7, 0x64656667;
R1 = [ I0 ++ M2 ];
R2 = [ I1 ++ M3 ];
R3 = [ I2 ++ M0 ];
R4 = [ I3 ++ M1 ];
R5 = [ I0 ++ M3 ];
R6 = [ I1 ++ M0 ];
R7 = [ I2 ++ M1 ];
R0 = [ I3 ++ M2 ];
CHECKREG r0, 0x68696A6B;
CHECKREG r1, 0x04050607;
CHECKREG r2, 0x24252627;
CHECKREG r3, 0x44454647;
CHECKREG r4, 0x64656667;
CHECKREG r5, 0x04050607;
CHECKREG r6, 0x28292A2B;
CHECKREG r7, 0x44454647;
M0 = 4 (X);
M1 = 0x0 (X);
M2 = 0x4 (X);
M3 = 0x0 (X);
R2 = [ I0 ++ M0 ];
R3 = [ I1 ++ M1 ];
R4 = [ I2 ++ M2 ];
R5 = [ I3 ++ M3 ];
R6 = [ I0 ++ M1 ];
R7 = [ I1 ++ M2 ];
R0 = [ I2 ++ M3 ];
R1 = [ I3 ++ M0 ];
CHECKREG r0, 0x4C4D4E4F;
CHECKREG r1, 0x68696A6B;
CHECKREG r2, 0x08090A0B;
CHECKREG r3, 0x28292A2B;
CHECKREG r4, 0x48494A4B;
CHECKREG r5, 0x68696A6B;
CHECKREG r6, 0x0C0D0E0F;
CHECKREG r7, 0x28292A2B;
R3 = [ I0 ++ M2 ];
R4 = [ I1 ++ M3 ];
R5 = [ I2 ++ M0 ];
R6 = [ I3 ++ M1 ];
R7 = [ I0 ++ M3 ];
R0 = [ I1 ++ M0 ];
R1 = [ I2 ++ M1 ];
R2 = [ I3 ++ M2 ];
CHECKREG r0, 0x2C2D2E2F;
CHECKREG r1, 0x50515253;
CHECKREG r2, 0x6C6D6E6F;
CHECKREG r3, 0x0C0D0E0F;
CHECKREG r4, 0x2C2D2E2F;
CHECKREG r5, 0x4C4D4E4F;
CHECKREG r6, 0x6C6D6E6F;
CHECKREG r7, 0x10111213;
R5 = [ I0 ++ M2 ];
R6 = [ I1 ++ M3 ];
R7 = [ I2 ++ M0 ];
R0 = [ I3 ++ M1 ];
R1 = [ I0 ++ M3 ];
R2 = [ I1 ++ M0 ];
R3 = [ I2 ++ M1 ];
R4 = [ I3 ++ M2 ];
CHECKREG r0, 0x70717273;
CHECKREG r1, 0x14151617;
CHECKREG r2, 0x30313233;
CHECKREG r3, 0x54555657;
CHECKREG r4, 0x70717273;
CHECKREG r5, 0x10111213;
CHECKREG r6, 0x30313233;
CHECKREG r7, 0x50515253;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,701 | sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s | //Original:/testcases/core/c_loopsetup_preg_div2_lc0/c_loopsetup_preg_div2_lc0.dsp
// Spec Reference: loopsetup preg lc0 / 2
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
P5 = 20;
P1 = 30;
P2 = 40;
P3 = 50;
P4 = 60;
//p5 = 7;
SP = 80 (X);
FP = 90 (X);
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start1 , end1 ) LC0 = P1 >> 1;
start1: R0 += 1;
R1 += -2;
end1: R2 += 3;
R3 += 4;
LSETUP ( start2 , end2 ) LC0 = P2 >> 1;
start2: R4 += 4;
end2: R5 += -5;
R3 += 1;
LSETUP ( start3 , end3 ) LC0 = P3 >> 1;
start3: R6 += 6;
end3: R7 += -7;
R3 += 1;
CHECKREG r0, 0x00000014;
CHECKREG r1, 0xFFFFFFF2;
CHECKREG r2, 0x0000004D;
CHECKREG r3, 0x00000036;
CHECKREG r4, 0x00000090;
CHECKREG r5, 0xFFFFFFEC;
CHECKREG r6, 0x000000F6;
CHECKREG r7, 0xFFFFFFC1;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x30;
R4 = 0x40 (X);
R5 = 0x50 (X);
R6 = 0x60 (X);
R7 = 0x70 (X);
LSETUP ( start4 , end4 ) LC0 = P4 >> 1;
start4: R0 += 1;
R1 += -2;
end4: R2 += 3;
R3 += 4;
LSETUP ( start5 , end5 ) LC0 = P5 >> 1;
start5: R4 += 1;
end5: R5 += -2;
R3 += 3;
LSETUP ( start6 , end6 ) LC0 = SP >> 1;
start6: R6 += 4;
end6: R7 += -5;
R3 += 6;
CHECKREG r0, 0x00000023;
CHECKREG r1, 0xFFFFFFD4;
CHECKREG r2, 0x0000007A;
CHECKREG r3, 0x0000003D;
CHECKREG r4, 0x0000004A;
CHECKREG r5, 0x0000003C;
CHECKREG r6, 0x00000100;
CHECKREG r7, 0xFFFFFFA8;
LSETUP ( start7 , end7 ) LC0 = FP >> 1;
start7: R4 += 4;
end7: R5 += -5;
R3 += 6;
CHECKREG r0, 0x00000023;
CHECKREG r1, 0xFFFFFFD4;
CHECKREG r2, 0x0000007A;
CHECKREG r3, 0x00000043;
CHECKREG r4, 0x000000FE;
CHECKREG r5, 0xFFFFFF5B;
CHECKREG r6, 0x00000100;
CHECKREG r7, 0xFFFFFFA8;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,717 | sim/testsuite/bfin/se_excpt_ifprotviol.S | //Original:/proj/frio/dv/testcases/seq/se_excpt_ifprotviol/se_excpt_ifprotviol.dsp
// Description: EXCPT instruction and IF Prot Viol priority
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x100 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
RETI = r0; // prevent Xs later on
RETX = r0;
RETN = r0;
RETE = r0;
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the user stack pointer
FP = SP;
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
R0 = 0;
R1 = -1;
EXCPT 2; // the RAISE should not prevent the EXCPT from being taken
RAISE 15;
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
CHECKREG(r5, 2); // check the flag
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction
CC = r7 == r6;
IF CC JUMP EXCPT2;
R6 = 0x2E; // EXCAUSE 0x2E means Illegal Use Supervisor Resource
CC = r7 == r6;
IF CC JUMP IFPROTVIOL;
JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
EXCPT2:
R5 = 1; // Set a Flag
JUMP.S OUT;
IFPROTVIOL:
R7 = RETX; // Fix up return address
R7 += 2; // skip offending 16 bit instruction
RETX = r7; // and put back in RETX
R5 <<= 1; // Alter Global Flag
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 1,453 | sim/testsuite/bfin/loop_strncpy.s | # Blackfin testcase for loop counter values when jumping out from the last insn
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
loadsym r1, dest;
r0 = r1;
loadsym r1, src;
r2 = 0x10;
_strncpy:
CC = R2 == 0;
if CC JUMP 4f;
P2 = R2 ; /* size */
P0 = R0 ; /* dst*/
P1 = R1 ; /* src*/
LSETUP (1f, 2f) LC0 = P2;
1:
R1 = B [P1++] (Z);
B [P0++] = R1;
CC = R1 == 0;
2:
if CC jump 3f;
fail
/* if src is shorter than n, we need to null pad bytes in dest
* but, we can get here when the last byte is zero, and we don't
* want to copy an extra byte at the end, so we need to check
*/
3:
R2 = LC0;
CHECKREG R2, 0x0a;
CC = R2
if ! CC jump 4f;
LSETUP(5f, 5f) LC0;
5:
B [P0++] = R1;
4:
loadsym P1, answer;
P0 = R0;
p2 = 0x20;
LSETUP (6f, 7f) LC0 = P2;
6:
R1 = B [P0++];
R2 = B [P1++];
CC = R1 == R2
IF ! CC JUMP wrong;
7:
NOP;
pass
wrong:
fail
.data
dest:
.db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
.db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F
src:
.db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30
answer:
.db 0x21, 0x22, 0x23, 0x24, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
.db 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F
|
tactcomplabs/xbgas-binutils-gdb | 5,619 | sim/testsuite/bfin/c_dspldst_st_dr_ipp.s | //Original:testcases/core/c_dspldst_st_dr_ipp/c_dspldst_st_dr_ipp.dsp
// Spec Reference: c_dspldst st_dr_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
//INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
// initial values
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
[ I0 ++ ] = R0;
[ I1 ++ ] = R1;
[ I2 ++ ] = R2;
[ I3 ++ ] = R3;
[ I0 ++ ] = R1;
[ I1 ++ ] = R2;
[ I2 ++ ] = R3;
[ I3 ++ ] = R4;
[ I0 ++ ] = R3;
[ I1 ++ ] = R4;
[ I2 ++ ] = R5;
[ I3 ++ ] = R6;
[ I0 ++ ] = R4;
[ I1 ++ ] = R5;
[ I2 ++ ] = R6;
[ I3 ++ ] = R7;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x0a234507;
CHECKREG r1, 0x1b345618;
CHECKREG r2, 0x2c456729;
CHECKREG r3, 0x3d56783a;
CHECKREG r4, 0x1B345618;
CHECKREG r5, 0x2C456729;
CHECKREG r6, 0x3D56783A;
CHECKREG r7, 0x4E67894B;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x3D56783A;
CHECKREG r1, 0x4E67894B;
CHECKREG r2, 0x5F789A5C;
CHECKREG r3, 0x6089AB6D;
CHECKREG r4, 0x4E67894B;
CHECKREG r5, 0x5F789A5C;
CHECKREG r6, 0x6089AB6D;
CHECKREG r7, 0x719ABC7E;
// initial values
imm32 r0, 0xa0b2c3d4;
imm32 r1, 0x1b245618;
imm32 r2, 0x22b36729;
imm32 r3, 0xbd3c483a;
imm32 r4, 0xde64d54b;
imm32 r5, 0x5f785e6c;
imm32 r6, 0x30896bf7;
imm32 r7, 0x719ab770;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
[ I0 -- ] = R0;
[ I1 -- ] = R1;
[ I2 -- ] = R2;
[ I3 -- ] = R3;
[ I0 -- ] = R4;
[ I1 -- ] = R5;
[ I2 -- ] = R6;
[ I3 -- ] = R7;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0xA0B2C3D4;
CHECKREG r1, 0x1B245618;
CHECKREG r2, 0x22B36729;
CHECKREG r3, 0xBD3C483A;
CHECKREG r4, 0xDE64D54B;
CHECKREG r5, 0x5F785E6C;
CHECKREG r6, 0x30896BF7;
CHECKREG r7, 0x719AB770;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 5,915 | sim/testsuite/bfin/c_ldst_ld_d_p_xh.s | //Original:/testcases/core/c_ldst_ld_d_p_xh/c_ldst_ld_d_p_xh.dsp
// Spec Reference: c_ldst ld d [p] xh
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 16 bits from memory and sign extend into 32-bit reg
R4 = W [ P5 ] (X);
R5 = W [ FP ] (X);
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 r1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFF8283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R5 = W [ FP ] (X);
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 R1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
R3 = W [ P5 ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0xFFFF8283;
CHECKREG r4, 0xFFFF8283;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 R1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
R3 = W [ P5 ] (X);
R4 = W [ FP ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0xFFFF8283;
CHECKREG r4, 0x00000203;
CHECKREG r5, 0x00000203;
CHECKREG r7, 0x00000203;
R7 = W [ P1 ] (X);
R0 = W [ P2 ] (X);
.ifndef BFIN_HOST
R1 = W [ P3 ] (X);
.else
imm32 R1, 0x00004243;
.endif
R2 = W [ P4 ] (X);
R3 = W [ P5 ] (X);
R4 = W [ FP ] (X);
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0xFFFF8283;
CHECKREG r4, 0x00000203;
CHECKREG r7, 0x00000203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,738 | sim/testsuite/bfin/c_dspldst_ld_dr_i.s | //Original:/testcases/core/c_dspldst_ld_dr_i/c_dspldst_ld_dr_i.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: c_dspldst ld_dr_i
// set all regs
INIT_R_REGS 0;
// initial values
loadsym I0, DATA1
loadsym I1, DATA2
loadsym I2, DATA3
loadsym I3, DATA4
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r2, 0x40414243;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x00010203;
CHECKREG r5, 0x20212223;
CHECKREG r6, 0x40414243;
CHECKREG r7, 0x60616263;
R1 = [ I0 ];
R2 = [ I1 ];
R3 = [ I2 ];
R4 = [ I3 ];
R5 = [ I0 ];
R6 = [ I1 ];
R7 = [ I2 ];
R0 = [ I3 ];
CHECKREG r0, 0x60616263;
CHECKREG r1, 0x00010203;
CHECKREG r2, 0x20212223;
CHECKREG r3, 0x40414243;
CHECKREG r4, 0x60616263;
CHECKREG r5, 0x00010203;
CHECKREG r6, 0x20212223;
CHECKREG r7, 0x40414243;
R2 = [ I0 ];
R3 = [ I1 ];
R4 = [ I2 ];
R5 = [ I3 ];
R6 = [ I0 ];
R7 = [ I1 ];
R0 = [ I2 ];
R1 = [ I3 ];
CHECKREG r0, 0x40414243;
CHECKREG r1, 0x60616263;
CHECKREG r2, 0x00010203;
CHECKREG r3, 0x20212223;
CHECKREG r4, 0x40414243;
CHECKREG r5, 0x60616263;
CHECKREG r6, 0x00010203;
CHECKREG r7, 0x20212223;
R3 = [ I0 ];
R4 = [ I1 ];
R5 = [ I2 ];
R6 = [ I3 ];
R7 = [ I0 ];
R0 = [ I1 ];
R1 = [ I2 ];
R2 = [ I3 ];
CHECKREG r0, 0x20212223;
CHECKREG r1, 0x40414243;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x00010203;
CHECKREG r4, 0x20212223;
CHECKREG r5, 0x40414243;
CHECKREG r6, 0x60616263;
CHECKREG r7, 0x00010203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 5,171 | sim/testsuite/bfin/se_more_ret_haz.S | //Original:/proj/frio/dv/testcases/seq/se_more_ret_haz/se_more_ret_haz.dsp
// Description: Return insts following pop, move.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
CLI R1;
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC;
STI R1;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
RAISE 2;
R2.L = 0xBAD;
CHECKREG(r2, 0);
AFTER_RTN:
EXCPT 5;
R2.L = 0xBAD;
CHECKREG(r2, 0);
AFTER_RTX:
RAISE 5;
R2.L = 0xBAD;
CHECKREG(r2, 0);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R1.L = AFTER_RTN;
R1.H = AFTER_RTN;
[ -- SP ] = R1;
RETN = [ SP ++ ];
RTN;
XHANDLE: // Exception Handler 3
R1.L = AFTER_RTX;
R1.H = AFTER_RTX;
[ -- SP ] = R1;
RETX = [ SP ++ ];
RTX;
HWHANDLE: // HW Error Handler 5
R1.L = END;
R1.H = END;
[ -- SP ] = R1;
RETI = [ SP ++ ];
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 3,151 | sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_neg_pr/c_ptr2op_pr_neg_pr.dsp
// Spec Reference: ptr2op preg -= preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0021003;
imm32 p2, 0x2e041005;
imm32 p3, 0x20d61007;
imm32 p4, 0x200a1009;
imm32 p5, 0x200a300b;
imm32 sp, 0x200c180d;
imm32 fp, 0x200e109f;
P1 -= P1;
P2 -= P1;
P3 -= P1;
P4 -= P1;
P5 -= P1;
SP -= P1;
FP -= P1;
CHECKREG p1, 0x00000000;
CHECKREG p2, 0x2E041005;
CHECKREG p3, 0x20D61007;
CHECKREG p4, 0x200A1009;
CHECKREG p5, 0x200A300B;
CHECKREG sp, 0x200C180D;
CHECKREG fp, 0x200E109F;
imm32 p1, 0x50021003;
imm32 p2, 0x26041005;
imm32 p3, 0x20761007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a900b;
imm32 sp, 0x200c1a0d;
imm32 fp, 0x200e10bf;
P1 -= P2;
P2 -= P2;
P3 -= P2;
P4 -= P2;
P5 -= P2;
SP -= P2;
FP -= P2;
CHECKREG p1, 0x29FDFFFE;
CHECKREG p2, 0x00000000;
CHECKREG p3, 0x20761007;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x200A900B;
CHECKREG sp, 0x200C1A0D;
CHECKREG fp, 0x200E10BF;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 -= P3;
P2 -= P3;
P3 -= P3;
P4 -= P3;
P5 -= P3;
SP -= P3;
FP -= P3;
CHECKREG p1, 0xFFFBFFFC;
CHECKREG p2, 0xFFFDFFFE;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x200A100B;
CHECKREG sp, 0x200C100D;
CHECKREG fp, 0x200E100F;
imm32 p1, 0xa0021003;
imm32 p2, 0x2c041005;
imm32 p3, 0x20b61007;
imm32 p4, 0x200d1009;
imm32 p5, 0x200ae00b;
imm32 sp, 0x200c110d;
imm32 fp, 0x200e104f;
P1 -= P4;
P2 -= P4;
P3 -= P4;
P4 -= P4;
P5 -= P4;
SP -= P4;
FP -= P4;
CHECKREG p1, 0x7FF4FFFA;
CHECKREG p2, 0x0BF6FFFC;
CHECKREG p3, 0x00A8FFFE;
CHECKREG p4, 0x00000000;
CHECKREG p5, 0x200AE00B;
CHECKREG sp, 0x200C110D;
CHECKREG fp, 0x200E104F;
imm32 p1, 0x10021003;
imm32 p2, 0x22041005;
imm32 p3, 0x20361007;
imm32 p4, 0x20041009;
imm32 p5, 0x200aa00b;
imm32 sp, 0x200c1b0d;
imm32 fp, 0x200e10cf;
P1 -= P5;
P2 -= P5;
P3 -= P5;
P4 -= P5;
P5 -= P5;
SP -= P5;
FP -= P5;
CHECKREG p1, 0xEFF76FF8;
CHECKREG p2, 0x01F96FFA;
CHECKREG p3, 0x002B6FFC;
CHECKREG p4, 0xFFF96FFE;
CHECKREG p5, 0x00000000;
CHECKREG sp, 0x200C1B0D;
CHECKREG fp, 0x200E10CF;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 -= SP;
P2 -= SP;
P3 -= SP;
P4 -= SP;
P5 -= SP;
SP -= SP;
FP -= SP;
CHECKREG p1, 0xFFF5FFF6;
CHECKREG p2, 0xFFF7FFF8;
CHECKREG p3, 0xFFF9FFFA;
CHECKREG p4, 0xFFFBFFFC;
CHECKREG p5, 0xFFFDFFFE;
CHECKREG sp, 0x00000000;
CHECKREG fp, 0x200E100F;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 -= FP;
P2 -= FP;
P3 -= FP;
P4 -= FP;
P5 -= FP;
SP -= FP;
FP -= FP;
CHECKREG p1, 0xFFF3FFF4;
CHECKREG p2, 0xFFF5FFF6;
CHECKREG p3, 0xFFF7FFF8;
CHECKREG p4, 0xFFF9FFFA;
CHECKREG p5, 0xFFFBFFFC;
CHECKREG sp, 0xFFFDFFFE;
CHECKREG fp, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,720 | sim/testsuite/bfin/c_mmr_timer.S | //Original:/proj/frio/dv/testcases/core/c_mmr_timer/c_mmr_timer.dsp
// Spec Reference: mmr timer
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// TCNTL: 4 bits, rw=1 = 0xFFE03000
LD32(p0, 0xFFE03000);
LD32(r0, 0x0000000D);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R1 = [ P0 ];
// TPERIOD: 32 bits, rw=1 = 0xFFE03004
LD32(p0, 0xFFE03004);
LD32(r0, 0x11112222);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R2 = [ P0 ];
// TSCALE: 8 bits, rw=1 = 0xFFE03008
LD32(p0, 0xFFE03008);
LD32(r0, 0x00000050);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R3 = [ P0 ];
// TCOUNT: 32 bits, rw=1 = 0xFFE0300C
LD32(p0, 0xFFE0300C);
LD32(r0, 0x00000100);
[ P0 ] = R0;
CSYNC; // without this it read out zero
R4 = [ P0 ];
CHECKREG(r1, 0x0000000D);
CHECKREG(r2, 0x11112222);
CHECKREG(r3, 0x00000050);
CHECKREG(r4, 0x00000100);
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
//.data 0xFFE03000
//.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 1,347 | sim/testsuite/bfin/c_dsp32alu_saa.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_saa/c_dsp32alu_saa.dsp
// Spec Reference: dsp32alu saa
# mach: bfin
.include "testutils.inc"
start
A1 = 0;
A0 = 0;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
A0 = 0;
A1 = 0;
SAA ( R1:0 , R3:2 );
R4 = A0.w;
R5 = A1.w;
CHECKREG r4, 0x00340004;
CHECKREG r5, 0x001F0023;
SAA ( R3:2 , R1:0 );
R6 = A0.w;
R7 = A1.w;
CHECKREG r6, 0x00680008;
CHECKREG r7, 0x003E0046;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x00340004;
imm32 r5, 0x001F0023;
imm32 r6, 0x00680008;
imm32 r7, 0x003E0046;
SAA ( R1:0 , R3:2 );
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x009C000E;
CHECKREG r1, 0x005D0069;
SAA ( R3:2 , R1:0 );
R2 = A0.w;
R3 = A1.w;
CHECKREG r2, 0x00F10025;
CHECKREG r3, 0x009100C1;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0xaeaa4bbb;
imm32 r6, 0xcfccd44d;
imm32 r7, 0xe1eefff4;
SAA ( R3:2 , R1:0 ) (R);
R0 = A0.w;
R1 = A1.w;
CHECKREG r0, 0x0125007B;
CHECKREG r1, 0x009900E6;
SAA ( R1:0 , R3:2 ) (R);
R6 = A0.w;
R7 = A1.w;
CHECKREG r6, 0x019C00EA;
CHECKREG r7, 0x0105011B;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,432 | sim/testsuite/bfin/m14.s | // Test extraction from accumulators:
// UNSIGNED FRACTIONAL and SIGNED INT mode into register PAIR
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffffff0
// load r1=0xfffffff0
// load r2=0x0fffffff
// load r3=0x00000001
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extract
// 0x00fffffff0 -> 0xffffffff0
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xfff0 );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xfff0 );
DBGA ( R6.H , 0xffff );
// extract with saturation
// 0x01fffffff0 -> 0xfffffffff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
A1.x = R3.L;
A0.x = R3.L;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
// extract with saturation
// 0xfffffffff0 -> 0xfffffffff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
A1.x = R4.L;
A0.x = R4.L;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
// extract unsigned
// 0x00fffffff0 -> 0xffffffff0
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R7 = A1, R6 = A0 (FU);
DBGA ( R7.L , 0xfff0 );
DBGA ( R7.H , 0xffff );
DBGA ( R6.L , 0xfff0 );
DBGA ( R6.H , 0xffff );
pass
.data
data0:
.dw 0xfff0
.dw 0x7fff
.dw 0xfff0
.dw 0xffff
.dw 0xffff
.dw 0x0fff
.dw 0x0001
.dw 0x0000
.dw 0x00ff
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 7,214 | sim/testsuite/bfin/c_seq_ex1_raise_brcc_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_raise_brcc_mv_pop/c_seq_ex1_raise_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (raise+ brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
R0 = 0;
ASTAT = R0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
RAISE 2; // RTN
IF !CC JUMP LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
IF !CC JUMP LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
RAISE 7; // RTI
IF CC JUMP LABEL4; // SHOULD NOT EXECUTE
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
LABEL4:
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
RAISE 8; // RTI
IF !CC JUMP LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 8,498 | sim/testsuite/bfin/c_seq_ex3_ls_brcc_mvp.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex3_ls_brcc_mvp/c_seq_ex3_ls_brcc_mvp.dsp
// Spec Reference: sequencer stage ex3 (ldst + brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
R0 = 0;
ASTAT = R0;
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
//LD32(p2, DATA_ADDR_1);
loadsym p2, DATA;
LD32(r0, 0x55552345);
// RAISE 2; // RTN
// r0 = [p2++];
R1 = [ P1 ];
IF !CC JUMP LABEL1 (BP);
P3 = R7;
R4 = P3;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
// r2 = [p2++];
R3 = [ P1 ];
IF CC JUMP LABEL2 (BP); // not taken
P4 = R6;
R4 = P4;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
// RAISE 6; // RTI
// r4 = [p2++];
R5 = [ P1 ];
IF !CC JUMP LABEL2 (BP);
P3 = R3;
R6 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
CSYNC;
CHECKREG(r0, 0x55552345);
//CHECKREG(r1, 0x000002B8);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000025);
//CHECKREG(r5, 0x000002B8);
// RAISE 7; // RTI
// r0 = [p2++];
R1 = [ P1 ];
P4 = R4;
R2 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
//CHECKREG(r1, 0x000002B8);
CHECKREG(r2, 0x00000003);
//CHECKREG(r3, 0x000002B8);
CHECKREG(r4, 0x00000007);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
// RAISE 8; // RTI
// r0 = [p2++];
R1 = [ P1 ];
IF !CC JUMP LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
CSYNC;
CHECKREG(r0, 0x55552345);
//CHECKREG(r1, 0x000002B8);
// RAISE 9; // RTI
P3 = R6;
R7 = P3;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA:
// .space (0x10);
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
.section MEM_DATA_ADDR_2,"aw"
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
|
tactcomplabs/xbgas-binutils-gdb | 8,188 | sim/testsuite/bfin/c_ldstpmod_ld_lohi.s | //Original:testcases/core/c_ldstpmod_ld_lohi/c_ldstpmod_ld_lohi.dsp
// Spec Reference: c_ldstpmod load dreg lo & hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
R0.L = W [ P5 ++ P1 ];
R1.L = W [ P5 ++ P1 ];
R2.L = W [ P5 ++ P2 ];
R3.L = W [ P5 ++ P3 ];
R4.L = W [ P5 ++ P4 ];
R5.L = W [ P5 ++ SP ];
R6.L = W [ P5 ++ FP ];
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00000A0B;
CHECKREG r5, 0x00000809;
CHECKREG r6, 0x00000E0F;
// initial values
P5 = 0x0000;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_2, 0x00;
P3 = I1; SP = I3;
R0.H = W [ P1 ++ P5 ];
R1.H = W [ P1 ++ P2 ];
R2.H = W [ P1 ++ P2 ];
R3.H = W [ P1 ++ P3 ];
R4.H = W [ P1 ++ P4 ];
R5.H = W [ P1 ++ SP ];
R6.H = W [ P1 ++ FP ];
CHECKREG r0, 0x22230203;
CHECKREG r1, 0x22230001;
CHECKREG r2, 0x20210607;
CHECKREG r3, 0x26270405;
CHECKREG r4, 0x24250A0B;
CHECKREG r5, 0x2A2B0809;
CHECKREG r6, 0x28290E0F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p2, DATA_ADDR_2, 0x02;
P3 = I1; SP = I3;
R0.L = W [ P2 ++ P5 ];
R0.H = W [ P2 ++ P1 ];
R1.L = W [ P2 ++ P1 ];
R1.H = W [ P2 ++ P3 ];
R2.H = W [ P2 ++ P4 ];
R2.L = W [ P2 ++ SP ];
R3.L = W [ P2 ++ FP ];
CHECKREG r0, 0x26272021;
CHECKREG r1, 0x2A2B2425;
CHECKREG r2, 0x28292E2F;
CHECKREG r3, 0x26272C2D;
CHECKREG r4, 0x24250A0B;
CHECKREG r5, 0x2A2B0809;
CHECKREG r6, 0x28290E0F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_3, 0x00;
P3 = I1; SP = I3;
R3.L = W [ P3 ++ P5 ];
R3.H = W [ P3 ++ P1 ];
R4.L = W [ P3 ++ P2 ];
R5.H = W [ P3 ++ P1 ];
R5.L = W [ P3 ++ P4 ];
R6.H = W [ P3 ++ SP ];
R6.L = W [ P3 ++ FP ];
CHECKREG r0, 0x26272021;
CHECKREG r1, 0x2A2B2425;
CHECKREG r2, 0x28292E2F;
CHECKREG r3, 0x40414243;
CHECKREG r4, 0x24254647;
CHECKREG r5, 0x44454A4B;
CHECKREG r6, 0x48494E4F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_4, 0x00;
P3 = I1; SP = I3;
R0.H = W [ P4 ++ P5 ];
R0.L = W [ P4 ++ P1 ];
R1.L = W [ P4 ++ P2 ];
R1.H = W [ P4 ++ P3 ];
R2.H = W [ P4 ++ P4 ];
R3.L = W [ P4 ++ SP ];
R3.H = W [ P4 ++ FP ];
CHECKREG r0, 0x62636061;
CHECKREG r1, 0x64656667;
CHECKREG r2, 0x6A6B2E2F;
CHECKREG r3, 0x68696A6B;
CHECKREG r4, 0x24254647;
CHECKREG r5, 0x44454A4B;
CHECKREG r6, 0x48494E4F;
// initial values
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_5, 0x00;
P3 = I1; SP = I3;
R0.H = W [ FP ++ P5 ];
R1.L = W [ FP ++ P1 ];
R2.H = W [ FP ++ P2 ];
R3.H = W [ FP ++ P3 ];
R4.L = W [ FP ++ P4 ];
R5.H = W [ FP ++ SP ];
R6.L = W [ FP ++ P1 ];
CHECKREG r0, 0x82836061;
CHECKREG r1, 0x64658081;
CHECKREG r2, 0x86872E2F;
CHECKREG r3, 0x84856A6B;
CHECKREG r4, 0x24258A8B;
CHECKREG r5, 0x88894A4B;
CHECKREG r6, 0x48498E8F;
// initial values
P5 = 0x0000;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i3, DATA_ADDR_6, 0x00;
P3 = I1; SP = I3;
R0.L = W [ SP ++ P5 ];
R1.H = W [ SP ++ P1 ];
R2.H = W [ SP ++ P2 ];
R3.L = W [ SP ++ P3 ];
R4.H = W [ SP ++ P4 ];
R5.L = W [ SP ++ P5 ];
R6.H = W [ SP ++ FP ];
CHECKREG r0, 0x82830203;
CHECKREG r1, 0x02038081;
CHECKREG r2, 0x00012E2F;
CHECKREG r3, 0x84850607;
CHECKREG r4, 0x04058A8B;
CHECKREG r5, 0x88890A0B;
CHECKREG r6, 0x0A0B8E8F;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
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