repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
taciclei/PrismChrono | 4,800 | benchmarks/prismchrono/trit_operations.s | # Benchmark: Trit Operations
# Implémentation d'opérations spécialisées trit par trit (TMIN, TMAX, TSUM, TCMP3)
# Ce benchmark démontre l'efficacité des instructions ternaires spécialisées
# Définition des constantes
.equ ARRAY_SIZE, 50 # Taille du tableau
.equ ARRAY_ADDR, 0x1000 # Adresse du premier tableau
.equ ARRAY2_ADDR, 0x1200 # Adresse du deuxième tableau
.equ RESULT_ADDR, 0x1400 # Adresse où stocker les résultats
# Section de données
.section .data
# Les tableaux seront initialisés par le simulateur ou le script d'exécution
# Section de code
.section .text
.global _start
_start:
# Initialisation des registres
MOVI r1, ARRAY_ADDR # Adresse du premier tableau
MOVI r2, ARRAY2_ADDR # Adresse du deuxième tableau
MOVI r3, RESULT_ADDR # Adresse des résultats
MOVI r4, ARRAY_SIZE # Taille du tableau
MOVI r5, 0 # Index courant
# Partie 1: Utilisation de TMIN pour trouver le minimum trit par trit
tmin_loop:
# Vérifier si on a parcouru tout le tableau
CMP r5, r4
BRANCH GE, tmax_init # Si index >= taille, passer à la partie suivante
# Calculer les adresses des éléments courants
ADD r6, r1, r5 # r6 = adresse1 + index
ADD r7, r2, r5 # r7 = adresse2 + index
ADD r8, r3, r5 # r8 = adresse_résultat + index
# Charger les valeurs
LOADW r9, r6, 0 # r9 = tableau1[index]
LOADW r10, r7, 0 # r10 = tableau2[index]
# Appliquer l'opération TMIN (minimum trit par trit)
TMIN r11, r9, r10 # r11 = min(r9, r10) trit par trit
# Stocker le résultat
STOREW r11, r8, 0 # résultat[index] = r11
# Incrémenter l'index
ADDI r5, r5, 1
BRANCH AL, tmin_loop # Continuer la boucle
# Partie 2: Utilisation de TMAX pour trouver le maximum trit par trit
tmax_init:
MOVI r5, 0 # Réinitialiser l'index
ADDI r3, r3, ARRAY_SIZE # Décaler l'adresse de résultat
tmax_loop:
# Vérifier si on a parcouru tout le tableau
CMP r5, r4
BRANCH GE, tsum_init # Si index >= taille, passer à la partie suivante
# Calculer les adresses des éléments courants
ADD r6, r1, r5 # r6 = adresse1 + index
ADD r7, r2, r5 # r7 = adresse2 + index
ADD r8, r3, r5 # r8 = adresse_résultat + index
# Charger les valeurs
LOADW r9, r6, 0 # r9 = tableau1[index]
LOADW r10, r7, 0 # r10 = tableau2[index]
# Appliquer l'opération TMAX (maximum trit par trit)
TMAX r11, r9, r10 # r11 = max(r9, r10) trit par trit
# Stocker le résultat
STOREW r11, r8, 0 # résultat[index] = r11
# Incrémenter l'index
ADDI r5, r5, 1
BRANCH AL, tmax_loop # Continuer la boucle
# Partie 3: Utilisation de TSUM pour la somme trit par trit (sans propagation)
tsum_init:
MOVI r5, 0 # Réinitialiser l'index
ADDI r3, r3, ARRAY_SIZE # Décaler l'adresse de résultat
tsum_loop:
# Vérifier si on a parcouru tout le tableau
CMP r5, r4
BRANCH GE, tcmp3_init # Si index >= taille, passer à la partie suivante
# Calculer les adresses des éléments courants
ADD r6, r1, r5 # r6 = adresse1 + index
ADD r7, r2, r5 # r7 = adresse2 + index
ADD r8, r3, r5 # r8 = adresse_résultat + index
# Charger les valeurs
LOADW r9, r6, 0 # r9 = tableau1[index]
LOADW r10, r7, 0 # r10 = tableau2[index]
# Appliquer l'opération TSUM (somme trit par trit sans propagation)
TSUM r11, r9, r10 # r11 = r9 + r10 trit par trit
# Stocker le résultat
STOREW r11, r8, 0 # résultat[index] = r11
# Incrémenter l'index
ADDI r5, r5, 1
BRANCH AL, tsum_loop # Continuer la boucle
# Partie 4: Utilisation de TCMP3 pour la comparaison ternaire à 3 états
tcmp3_init:
MOVI r5, 0 # Réinitialiser l'index
ADDI r3, r3, ARRAY_SIZE # Décaler l'adresse de résultat
tcmp3_loop:
# Vérifier si on a parcouru tout le tableau
CMP r5, r4
BRANCH GE, end # Si index >= taille, terminer
# Calculer les adresses des éléments courants
ADD r6, r1, r5 # r6 = adresse1 + index
ADD r7, r2, r5 # r7 = adresse2 + index
ADD r8, r3, r5 # r8 = adresse_résultat + index
# Charger les valeurs
LOADW r9, r6, 0 # r9 = tableau1[index]
LOADW r10, r7, 0 # r10 = tableau2[index]
# Appliquer l'opération TCMP3 (comparaison ternaire à 3 états)
TCMP3 r11, r9, r10 # r11[i] = -1 si r9[i] < r10[i], 0 si égaux, 1 si r9[i] > r10[i]
# Stocker le résultat
STOREW r11, r8, 0 # résultat[index] = r11
# Incrémenter l'index
ADDI r5, r5, 1
BRANCH AL, tcmp3_loop # Continuer la boucle
end:
# Fin du programme
HALT |
taciclei/PrismChrono | 3,112 | benchmarks/prismchrono/compact_format.s | # Benchmark: Compact Format
# Comparaison entre format standard et format compact
# Ce benchmark démontre les avantages du format d'instruction compact en termes de densité de code
# Définition des constantes
.equ ITERATIONS, 50 # Nombre d'itérations
.equ DATA_ADDR, 0x1000 # Adresse des données d'entrée
.equ RESULT_ADDR, 0x1200 # Adresse des résultats
# Section de données
.section .data
# Les données seront initialisées par le simulateur ou le script d'exécution
# Section de code
.section .text
.global _start
_start:
# Initialisation des registres
MOVI r1, DATA_ADDR # Adresse des données
MOVI r2, RESULT_ADDR # Adresse des résultats
MOVI r3, ITERATIONS # Nombre d'itérations
# Partie 1: Utilisation du format standard
standard_format:
# Initialisation pour la partie standard
MOVI r4, 0 # Compteur d'itérations
MOVI r5, 0 # Accumulateur
standard_loop:
# Vérifier si on a effectué toutes les itérations
CMP r4, r3
BRANCH GE, compact_format # Si compteur >= itérations, passer à la partie suivante
# Calculer l'adresse de la donnée courante
ADD r6, r1, r4 # r6 = adresse_données + compteur
# Charger la valeur
LOADW r7, r6, 0 # r7 = données[compteur]
# Effectuer des opérations standard
ADD r5, r5, r7 # Ajouter la valeur à l'accumulateur
ADDI r4, r4, 1 # Incrémenter le compteur
# Vérifier si l'accumulateur dépasse une certaine valeur
MOVI r8, 1000
CMP r5, r8
BRANCH LT, standard_loop # Si accumulateur < 1000, continuer la boucle
# Réinitialiser l'accumulateur si nécessaire
MOVI r5, 0
BRANCH AL, standard_loop # Continuer la boucle
# Partie 2: Utilisation du format compact
compact_format:
# Stocker le résultat de la partie standard
STOREW r5, r2, 0
# Initialisation pour la partie compact
MOVI r4, 0 # Compteur d'itérations
MOVI r5, 0 # Accumulateur
compact_loop:
# Vérifier si on a effectué toutes les itérations
CMP r4, r3
BRANCH GE, end # Si compteur >= itérations, terminer
# Calculer l'adresse de la donnée courante (utilisation du format compact)
CADD r4, r1 # r4 = r4 + r1 (format compact)
# Charger la valeur
LOADW r7, r4, 0 # r7 = données[compteur]
# Effectuer des opérations avec format compact
CADD r5, r7 # r5 = r5 + r7 (format compact)
CMOV r4, r1 # r4 = r1 (format compact)
CADD r4, r4 # r4 = r4 + r4 (format compact)
# Vérifier si l'accumulateur dépasse une certaine valeur
MOVI r8, 1000
CMP r5, r8
CBRANCH LT, compact_continue # Si accumulateur < 1000, continuer (format compact)
# Réinitialiser l'accumulateur si nécessaire
MOVI r5, 0
compact_continue:
CADD r4, r4 # r4 = r4 + r4 (format compact)
CBRANCH AL, compact_loop # Continuer la boucle (format compact)
end:
# Stocker le résultat de la partie compact
STOREW r5, r2, 4
# Fin du programme
HALT |
tactcomplabs/xbgas-binutils-gdb | 2,867 | binutils/testsuite/binutils-all/dwo.s | /* Assembler source used to create an object file for testing readelf's
and objdump's ability to process separate dwarf object files.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Create a .debug_str section for local use. This is also to check
the ability to dump the same section twice, if it exists in
both the main file and the separate debug info file. */
.section .debug_str,"MS",%progbits,1
string1:
.asciz "debugfile.dwo"
string2:
.asciz "/path/to/dwo/files"
string3:
.asciz "/another/path/"
.balign 2
string_end:
/* Create a .debug_info section that contains the dwo links. */
.section .debug_info,"",%progbits
.4byte debugE1 - debugS1 ;# Length of Compilation Unit Info
debugS1:
.short 0x4 ;# DWARF version number.
.4byte 0x0 ;# Offset into .debug_abbrev section.
.byte 0x4 ;# Pointer Size (in bytes).
.uleb128 0x1 ;# Use abbrev #1. This needs strings from the .debug_str section.
.4byte string1
.4byte string2
debugE1:
.4byte debugE2 - debugS2 ;# Length of Compilation Unit Info
debugS2:
.short 0x4 ;# DWARF version number.
.4byte 0x0 ;# Offset into .debug_abbrev section.
.byte 0x4 ;# Pointer Size (in bytes).
.uleb128 0x2 ;# Use abbrev #2.
.asciz "file.dwo"
.4byte string3
.8byte 0x12345678aabbccdd
;# Minimal section alignment on alpha-* is 2, so ensure no new invalid CU
;# will be started.
.balign 2, 0
debugE2:
.section .debug_abbrev,"",%progbits
/* Create an abbrev containing a DWARF5 style dwo link. */
.uleb128 0x01 ;# Abbrev code.
.uleb128 0x11 ;# DW_TAG_compile_unit
.byte 0x00 ;# DW_children_no
.uleb128 0x76 ;# DW_AT_dwo_name
.uleb128 0x0e ;# DW_FORM_strp
.uleb128 0x1b ;# DW_AT_comp_dir
.uleb128 0x0e ;# DW_FORM_strp
.byte 0x00 ;# End of abbrev
.byte 0x00
/* Create an abbrev containing a GNU style dwo link. */
.uleb128 0x02 ;# Abbrev code.
.uleb128 0x11 ;# DW_TAG_compile_unit
.byte 0x00 ;# DW_children_no
.uleb128 0x2130 ;# DW_AT_GNU_dwo_name
.uleb128 0x08 ;# DW_FORM_string
.uleb128 0x1b ;# DW_AT_comp_dir
.uleb128 0x0e ;# DW_FORM_strp
.uleb128 0x2131 ;# DW_AT_GNU_dwo_id
.uleb128 0x07 ;# DW_FORM_data8
.byte 0x00 ;# End of abbrev
.byte 0x00
.byte 0x0 ;# Abbrevs terminator
|
tactcomplabs/xbgas-binutils-gdb | 5,206 | binutils/testsuite/binutils-all/dw2-2.S | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2008-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Dummy function to provide debug information for. */
.text
.Lbegin_text1:
.globl func_cu2
.type func_cu2, %function
func_cu2:
.Lbegin_func_cu2:
.4byte 0
.Lend_func_cu2:
.size func_cu2, .-func_cu2
.Lend_text1:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lline1_begin /* DW_AT_stmt_list */
.4byte .Lend_text1 /* DW_AT_high_pc */
.4byte .Lbegin_text1 /* DW_AT_low_pc */
.ascii "file1.txt\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.byte 1 /* DW_AT_language (C) */
/* func_cu2 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.byte 1 /* DW_AT_external */
.byte 1 /* DW_AT_decl_file */
.byte 2 /* DW_AT_decl_line */
.ascii "func_cu2\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func_cu2 /* DW_AT_low_pc */
.4byte .Lend_func_cu2 /* DW_AT_high_pc */
.byte 1 /* DW_AT_frame_base: length */
.byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */
.Ltype_int:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Line table */
.section .debug_line
.Lline1_begin:
.4byte .Lline1_end - .Lline1_start /* Initial length */
.Lline1_start:
.2byte 2 /* Version */
.4byte .Lline1_lines - .Lline1_hdr /* header_length */
.Lline1_hdr:
.byte 1 /* Minimum insn length */
.byte 1 /* default_is_stmt */
.byte 1 /* line_base */
.byte 1 /* line_range */
.byte 0x10 /* opcode_base */
/* Standard lengths */
.byte 0
.byte 1
.byte 1
.byte 1
.byte 1
.byte 0
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 0
/* Include directories */
.byte 0
/* File names */
.ascii "file1.txt\0"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.Lline1_lines:
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func_cu2
.byte 3 /* DW_LNS_advance_line */
.sleb128 3 /* ... to 4 */
.byte 1 /* DW_LNS_copy */
.byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lend_func_cu2
.byte 0 /* DW_LNE_end_of_sequence */
.uleb128 1
.byte 1
.Lline1_end:
/* Abbrev table */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x10 /* DW_AT_stmt_list */
.uleb128 0x6 /* DW_FORM_data4 */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram */
.byte 0 /* has_children */
.uleb128 0x3f /* DW_AT_external */
.uleb128 0xc /* DW_FORM_flag */
.uleb128 0x3a /* DW_AT_decl_file */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3b /* DW_AT_decl_line */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x40 /* DW_AT_frame_base */
.uleb128 0xa /* DW_FORM_block1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
|
tactcomplabs/xbgas-binutils-gdb | 1,642 | binutils/testsuite/binutils-all/retain1.s | .global discard0
.section .bss.discard0,"aw"
.type discard0, %object
discard0:
.zero 2
.global discard1
.section .bss.discard1,"aw"
.type discard1, %object
discard1:
.zero 2
.global discard2
.section .data.discard2,"aw"
.type discard2, %object
discard2:
.word 1
.section .bss.sdiscard0,"aw"
.type sdiscard0, %object
sdiscard0:
.zero 2
.section .bss.sdiscard1,"aw"
.type sdiscard1, %object
sdiscard1:
.zero 2
.section .data.sdiscard2,"aw"
.type sdiscard2, %object
sdiscard2:
.word 1
.section .text.fndiscard0,"ax"
.global fndiscard0
.type fndiscard0, %function
fndiscard0:
.word 0
.global retain0
.section .bss.retain0,"awR"
.type retain0, %object
retain0:
.zero 2
.global retain1
.section .bss.retain1,"awR"
.type retain1, %object
retain1:
.zero 2
.global retain2
.section .data.retain2,"awR"
.type retain2, %object
retain2:
.word 1
.section .bss.sretain0,"awR"
.type sretain0, %object
sretain0:
.zero 2
.section .bss.sretain1,"awR"
.type sretain1, %object
sretain1:
.zero 2
.section .data.sretain2,"aRw"
.type sretain2, %object
sretain2:
.word 1
.section .text.fnretain1,"Rax"
.global fnretain1
.type fnretain1, %function
fnretain1:
.word 0
.section .text.fndiscard2,"ax"
.global fndiscard2
.type fndiscard2, %function
fndiscard2:
.word 0
.section .bss.lsretain0,"awR"
.type lsretain0.2, %object
lsretain0.2:
.zero 2
.section .bss.lsretain1,"aRw"
.type lsretain1.1, %object
lsretain1.1:
.zero 2
.section .data.lsretain2,"aRw"
.type lsretain2.0, %object
lsretain2.0:
.word 1
.section .text._start,"ax"
.global _start
.type _start, %function
_start:
.word 0
|
tactcomplabs/xbgas-binutils-gdb | 8,459 | binutils/testsuite/binutils-all/locview-1.s | .text
.Ltext0:
.LFB0:
/* locview.c:1 */
.LM1:
/* view -0 */
/* locview.c:2 */
.LM2:
/* view 1 */
.LVL0:
/* DEBUG i => 0 */
/* locview.c:3 */
.LM3:
/* view 2 */
/* DEBUG j => 0x1 */
/* locview.c:4 */
.LM4:
/* view 3 */
/* DEBUG i => 0x2 */
/* locview.c:5 */
.LM5:
/* view 4 */
/* DEBUG j => 0x3 */
/* locview.c:6 */
.LM6:
/* view 5 */
/* DEBUG k => 0x4 */
/* DEBUG l => 0x4 */
/* locview.c:7 */
.LM7:
/* view 6 */
/* DEBUG k => 0x5 */
/* DEBUG l => 0x5 */
/* locview.c:8 */
.LM8:
/* view 7 */
/* DEBUG k => 0x6 */
/* DEBUG l => 0x6 */
/* locview.c:9 */
.LM9:
/* view 8 */
.byte 0
.LFE0:
.Letext0:
.section .debug_info
.Ldebug_info0:
.LIbase:
.4byte .LIend - .LIstart /* Length of Compilation Unit Info */
.LIstart:
.2byte 0x4 /* DWARF version number */
.4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */
.byte 0x4 /* Pointer Size (in bytes) */
.LIcu:
.uleb128 0x1 /* (DIE (cu) DW_TAG_compile_unit) */
.ascii "hand-crafted based on GCC output\0"
.byte 0xc /* DW_AT_language */
.ascii "locview.c\0"
.ascii "/tmp\0"
.4byte 0 /* DW_AT_low_pc */
.LIsubf:
.uleb128 0x2 /* (DIE (subf) DW_TAG_subprogram) */
.ascii "f\0" /* DW_AT_name */
.byte 0x1 /* DW_AT_decl_file (locview.c) */
.byte 0x1 /* DW_AT_decl_line */
.4byte .LIint-.LIbase /* DW_AT_type */
.4byte .LFB0 /* DW_AT_low_pc */
.4byte 1 /* .LFE0-.LFB0 */ /* DW_AT_high_pc */
.uleb128 0x1 /* DW_AT_frame_base */
.byte 0x9c /* DW_OP_call_frame_cfa */
/* DW_AT_GNU_all_call_sites */
.4byte .LIint - .LIbase /* DW_AT_sibling */
.LIvari:
.uleb128 0x3 /* (DIE (vari) DW_TAG_variable) */
.ascii "i\0" /* DW_AT_name */
.byte 0x1 /* DW_AT_decl_file (locview.c) */
.byte 0x2 /* DW_AT_decl_line */
.4byte .LIint-.LIbase /* DW_AT_type */
.4byte .LLST0 /* DW_AT_location */
.4byte .LVUS0 /* DW_AT_GNU_locviews */
.LIvarj:
.uleb128 0x3 /* (DIE (varf) DW_TAG_variable) */
.ascii "j\0" /* DW_AT_name */
.byte 0x1 /* DW_AT_decl_file (locview.c) */
.byte 0x3 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LLST1 /* DW_AT_location */
.4byte .LVUS1 /* DW_AT_GNU_locviews */
.LIvark:
.uleb128 0x5 /* (DIE (vark) DW_TAG_variable) */
.ascii "k\0" /* DW_AT_name */
.byte 0x1 /* DW_AT_decl_file (locview.c) */
.byte 0x6 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LVUS2 /* DW_AT_GNU_locviews */
.4byte .LLST2 /* DW_AT_location */
.byte 0 /* end of children of subf */
.LIvarl:
.uleb128 0x5 /* (DIE (varl) DW_TAG_variable) */
.ascii "l\0" /* DW_AT_name */
.byte 0x1 /* DW_AT_decl_file (locview.c) */
.byte 0x6 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LVUS2 /* DW_AT_GNU_locviews */
.4byte .LLST2 /* DW_AT_location */
.byte 0 /* end of children of subf */
.LIint:
.uleb128 0x4 /* (DIE (int) DW_TAG_base_type) */
.byte 0x4 /* DW_AT_byte_size */
.byte 0x5 /* DW_AT_encoding */
.ascii "int\0" /* DW_AT_name */
.byte 0 /* end of children of cu */
.LIend:
.section .debug_abbrev
.Ldebug_abbrev0:
.LAbrv1:
.uleb128 0x1 /* (abbrev code) */
.uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x25 /* (DW_AT_producer) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x13 /* (DW_AT_language) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x1b /* (DW_AT_comp_dir) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.byte 0
.byte 0
.LAbrv2:
.uleb128 0x2 /* (abbrev code) */
.uleb128 0x2e /* (TAG: DW_TAG_subprogram) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x12 /* (DW_AT_high_pc) */
.uleb128 0x6 /* (DW_FORM_data4) */
.uleb128 0x40 /* (DW_AT_frame_base) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.uleb128 0x2117 /* (DW_AT_GNU_all_call_sites) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x1 /* (DW_AT_sibling) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.byte 0
.byte 0
.LAbrv3:
.uleb128 0x3 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.uleb128 0x2137 /* (DW_AT_GNU_locviews) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.LAbrv4:
.uleb128 0x4 /* (abbrev code) */
.uleb128 0x24 /* (TAG: DW_TAG_base_type) */
.byte 0 /* DW_children_no */
.uleb128 0xb /* (DW_AT_byte_size) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3e /* (DW_AT_encoding) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.byte 0
.byte 0
.LAbrv5:
.uleb128 0x5 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x2137 /* (DW_AT_GNU_locviews) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.byte 0
.section .debug_loc
.Ldebug_loc0:
.LVUS0:
.uleb128 0x2 /* View list begin (*.LVUS0) */
.uleb128 0x4 /* View list end (*.LVUS0) */
.uleb128 0x4 /* View list begin (*.LVUS0) */
.uleb128 0 /* View list end (*.LVUS0) */
.LLST0:
.4byte .LVL0 /* Location list begin address (*.LLST0) */
.4byte .LVL0 /* Location list end address (*.LLST0) */
.2byte 0x2 /* Location expression size */
.byte 0x30 /* DW_OP_lit0 */
.byte 0x9f /* DW_OP_stack_value */
.4byte .LVL0 /* Location list begin address (*.LLST0) */
.4byte .LFE0 /* Location list end address (*.LLST0) */
.2byte 0x2 /* Location expression size */
.byte 0x32 /* DW_OP_lit2 */
.byte 0x9f /* DW_OP_stack_value */
.4byte 0 /* Location list terminator begin (*.LLST0) */
.4byte 0 /* Location list terminator end (*.LLST0) */
.LLST1:
.4byte .LVL0 /* Location list begin address (*.LLST1) */
.4byte .LVL0 /* Location list end address (*.LLST1) */
.2byte 0x2 /* Location expression size */
.byte 0x31 /* DW_OP_lit1 */
.byte 0x9f /* DW_OP_stack_value */
.4byte .LVL0 /* Location list begin address (*.LLST1) */
.4byte .LFE0 /* Location list end address (*.LLST1) */
.2byte 0x2 /* Location expression size */
.byte 0x33 /* DW_OP_lit3 */
.byte 0x9f /* DW_OP_stack_value */
.4byte 0 /* Location list terminator begin (*.LLST1) */
.4byte 0 /* Location list terminator end (*.LLST1) */
.LVUS1:
.uleb128 0x3 /* View list begin (*.LVUS1) */
.uleb128 0x5 /* View list end (*.LVUS1) */
.uleb128 0x5 /* View list begin (*.LVUS1) */
.uleb128 0 /* View list end (*.LVUS1) */
.LVUS2:
.uleb128 0x6 /* View list begin (*.LVUS2) */
.uleb128 0x7 /* View list end (*.LVUS2) */
.uleb128 0x7 /* View list begin (*.LVUS2) */
.uleb128 0x8 /* View list end (*.LVUS2) */
.uleb128 0x8 /* View list begin (*.LVUS2) */
.uleb128 0 /* View list end (*.LVUS2) */
.LLST2:
.4byte .LVL0 /* Location list begin address (*.LLST2) */
.4byte .LVL0 /* Location list end address (*.LLST2) */
.2byte 0x2 /* Location expression size */
.byte 0x34 /* DW_OP_lit4 */
.byte 0x9f /* DW_OP_stack_value */
.4byte .LVL0 /* Location list begin address (*.LLST2) */
.4byte .LVL0 /* Location list end address (*.LLST2) */
.2byte 0x2 /* Location expression size */
.byte 0x35 /* DW_OP_lit5 */
.byte 0x9f /* DW_OP_stack_value */
.4byte .LVL0 /* Location list begin address (*.LLST2) */
.4byte .LFE0 /* Location list end address (*.LLST2) */
.2byte 0x2 /* Location expression size */
.byte 0x36 /* DW_OP_lit6 */
.byte 0x9f /* DW_OP_stack_value */
.4byte 0 /* Location list terminator begin (*.LLST2) */
.4byte 0 /* Location list terminator end (*.LLST2) */
|
tactcomplabs/xbgas-binutils-gdb | 3,119 | binutils/testsuite/binutils-all/pr18374.s | .section .debug_info,"",%progbits
.4byte 0x77
.2byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x4
.uleb128 0x1
.4byte .LASF3
.byte 0xc
.ascii "x.c\000"
.4byte .LASF4
.4byte .Ltext0
.4byte .Letext0
.4byte .Ldebug_line0
.uleb128 0x2
.ascii "foo\000"
.byte 0x1
.byte 0x2
.4byte .LFB0
.4byte .LFE0
.uleb128 0x1
.byte 0x9c
.4byte 0x64
.uleb128 0x3
.ascii "b\000"
.byte 0x1
.byte 0x2
.4byte 0x64
.4byte .LLST0
.uleb128 0x4
.4byte .LASF0
.byte 0x1
.byte 0x2
.4byte 0x66
.4byte .LLST1
.uleb128 0x5
.ascii "ptr\000"
.byte 0x1
.byte 0x4
.4byte 0x6d
.uleb128 0x1
.byte 0x50
.byte 0
.uleb128 0x6
.byte 0x4
.uleb128 0x7
.byte 0x4
.byte 0x7
.4byte .LASF1
.uleb128 0x8
.byte 0x4
.4byte 0x73
.uleb128 0x7
.byte 0x1
.byte 0x8
.4byte .LASF2
.byte 0
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x6
.uleb128 0x10
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x2e
.byte 0x1
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x27
.uleb128 0x19
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x6
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.uleb128 0x1
.uleb128 0x13
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x5
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0x8
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.byte 0
.byte 0
.uleb128 0x7
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.byte 0
.byte 0
.uleb128 0x8
.uleb128 0xf
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.byte 0
.byte 0
.byte 0
.section .debug_loc,"",%progbits
.Ldebug_loc0:
.LLST0:
.4byte .LVL0
.4byte .LVL2
.2byte 0x1
.byte 0x50
.4byte .LVL2
.4byte .LFE0
.2byte 0x4
.byte 0xf3
.uleb128 0x1
.byte 0x50
.byte 0x9f
.4byte 0
.4byte 0
.LLST1:
.4byte .LVL0
.4byte .LVL1
.2byte 0x1
.byte 0x51
.4byte .LVL1
.4byte .LVL2
.2byte 0x3
.byte 0x71
.sleb128 -1
.byte 0x9f
.4byte .LVL2
.4byte .LVL3
.2byte 0xb
.byte 0x70
.sleb128 0
.byte 0x20
.byte 0xf3
.uleb128 0x1
.byte 0x51
.byte 0x22
.byte 0x70
.sleb128 0
.byte 0x22
.byte 0x9f
.4byte .LVL3
.4byte .LFE0
.2byte 0xb
.byte 0x70
.sleb128 0
.byte 0x20
.byte 0x70
.sleb128 0
.byte 0x22
.byte 0xf3
.uleb128 0x1
.byte 0x51
.byte 0x22
.byte 0x9f
.4byte 0
.4byte 0
|
tactcomplabs/xbgas-binutils-gdb | 2,386 | binutils/testsuite/binutils-all/debuglink.s | /* Assembler source used to create an object file for testing readelf's
and objdump's ability to process separate debug information files.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Create a fake .gnu_debuglink section. */
.section .gnu_debuglink,"",%progbits
.asciz "this_is_a_debuglink.debug"
.balign 4
.4byte 0x12345678
/* Create a fake .gnu_debugaltlink section. */
.section .gnu_debugaltlink,"",%progbits
.asciz "linkdebug.debug"
.dc.b 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
.dc.b 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
.dc.b 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef
/* Create a .debug_str section for local use. This is also to check
the ability to dump the same section twice, if it exists in
both the main file and the separate debug info file. */
.section .debug_str,"MS",%progbits,1
string1:
.asciz "string-1"
.asciz "string-2"
.balign 2
string_end:
/* Create a .debug_info section that contains string references into
the separate debug info file. Plus the abbreviations are stored
in the separate file too... */
.section .debug_info,"",%progbits
.4byte debugE - debugS ;# Length of Compilation Unit Info
debugS:
.short 0x4 ;# DWARF version number.
.4byte 0x0 ;# Offset into .debug_abbrev section.
.byte 0x4 ;# Pointer Size (in bytes).
.uleb128 0x1 ;# Use abbrev #1. This needs a string from the local string table.
.4byte string1
.uleb128 0x2 ;# Use abbrev #2. This needs a string from the separate string table.
.4byte 0x0 ;# Avoid complicated expression resolution and hard code the offset...
;# Minimal section alignment on alpha-* is 2, so ensure no new invalid CU
;# will be started.
.balign 2, 0
debugE:
|
tactcomplabs/xbgas-binutils-gdb | 21,697 | binutils/testsuite/binutils-all/dw5.S | /* Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
.file "main.c"
.text
.Ltext0:
.p2align 4,,15
.globl func
.type func, %function
func:
.LFB0:
/* main.c:5 */
.LM1:
/* BLOCK 2 freq:10000 seq:0 */
/* PRED: ENTRY [100.0%] (FALLTHRU) */
/* main.c:5 */
.LM2:
.dc.b 0
/* SUCC: */
.dc.b 0
.LFE0:
.size func, .-func
.section .text.startup,"ax",%progbits
.p2align 4,,15
.globl main
.type main, %function
main:
.LFB1:
/* main.c:6 */
.LM3:
.LVL0:
/* BLOCK 2 freq:10000 seq:0 */
/* PRED: ENTRY [100.0%] (FALLTHRU) */
.dc.b 0
/* main.c:6 */
.LM4:
.dc.b 0
.LVL1:
.dc.b 0
.LVL2:
.dc.b 0
/* SUCC: EXIT [100.0%] */
.dc.b 0
.LFE1:
.size main, .-main
.ifdef HPUX
pvar .comm 8
yvar .comm 4
.else
.comm pvar,8,8
.comm yvar,4,4
.endif
.globl xvar
.data
.align 4
.type xvar, %object
.size xvar, 4
xvar:
.4byte 42
.text
.Letext0:
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x160 /* Length of Compilation Unit Info */
.2byte 0x5 /* DWARF version number */
.byte 0x1 /* DW_UT_compile */
.byte 0x8 /* Pointer Size (in bytes) */
.4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */
.uleb128 0x6 /* (DIE (0xc) DW_TAG_compile_unit) */
.4byte .LASF21 /* DW_AT_producer: "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" */
.byte 0x1d /* DW_AT_language */
.4byte .LASF0 /* DW_AT_name: "main.c" */
.4byte .LASF1 /* DW_AT_comp_dir: "" */
.4byte .LLRL2 /* DW_AT_ranges */
.8byte 0 /* DW_AT_low_pc */
.4byte .Ldebug_line0 /* DW_AT_stmt_list */
.uleb128 0x1 /* (DIE (0x2a) DW_TAG_base_type) */
.byte 0x1 /* DW_AT_byte_size */
.byte 0x8 /* DW_AT_encoding */
.4byte .LASF2 /* DW_AT_name: "unsigned char" */
.uleb128 0x1 /* (DIE (0x31) DW_TAG_base_type) */
.byte 0x2 /* DW_AT_byte_size */
.byte 0x7 /* DW_AT_encoding */
.4byte .LASF3 /* DW_AT_name: "short unsigned int" */
.uleb128 0x1 /* (DIE (0x38) DW_TAG_base_type) */
.byte 0x4 /* DW_AT_byte_size */
.byte 0x7 /* DW_AT_encoding */
.4byte .LASF4 /* DW_AT_name: "unsigned int" */
.uleb128 0x1 /* (DIE (0x3f) DW_TAG_base_type) */
.byte 0x8 /* DW_AT_byte_size */
.byte 0x7 /* DW_AT_encoding */
.4byte .LASF5 /* DW_AT_name: "long unsigned int" */
.uleb128 0x1 /* (DIE (0x46) DW_TAG_base_type) */
.byte 0x1 /* DW_AT_byte_size */
.byte 0x6 /* DW_AT_encoding */
.4byte .LASF6 /* DW_AT_name: "signed char" */
.uleb128 0x1 /* (DIE (0x4d) DW_TAG_base_type) */
.byte 0x2 /* DW_AT_byte_size */
.byte 0x5 /* DW_AT_encoding */
.4byte .LASF7 /* DW_AT_name: "short int" */
.uleb128 0x7 /* (DIE (0x54) DW_TAG_base_type) */
.byte 0x4 /* DW_AT_byte_size */
.byte 0x5 /* DW_AT_encoding */
.ascii "int\0" /* DW_AT_name */
.uleb128 0x1 /* (DIE (0x5b) DW_TAG_base_type) */
.byte 0x8 /* DW_AT_byte_size */
.byte 0x5 /* DW_AT_encoding */
.4byte .LASF8 /* DW_AT_name: "long int" */
.uleb128 0x1 /* (DIE (0x62) DW_TAG_base_type) */
.byte 0x8 /* DW_AT_byte_size */
.byte 0x7 /* DW_AT_encoding */
.4byte .LASF9 /* DW_AT_name: "sizetype" */
.uleb128 0x3 /* (DIE (0x69) DW_TAG_pointer_type) */
/* DW_AT_byte_size (0x8) */
.4byte 0x6e /* DW_AT_type */
.uleb128 0x1 /* (DIE (0x6e) DW_TAG_base_type) */
.byte 0x1 /* DW_AT_byte_size */
.byte 0x6 /* DW_AT_encoding */
.4byte .LASF10 /* DW_AT_name: "char" */
.uleb128 0x8 /* (DIE (0x75) DW_TAG_variable) */
.4byte .LASF11 /* DW_AT_name: "__environ" */
.byte 0x2 /* DW_AT_decl_file (/usr/include/unistd.h) */
.2byte 0x222 /* DW_AT_decl_line */
.4byte 0x81 /* DW_AT_type */
/* DW_AT_external */
/* DW_AT_declaration */
.uleb128 0x3 /* (DIE (0x81) DW_TAG_pointer_type) */
/* DW_AT_byte_size (0x8) */
.4byte 0x69 /* DW_AT_type */
.uleb128 0x2 /* (DIE (0x86) DW_TAG_variable) */
.4byte .LASF12 /* DW_AT_name: "optarg" */
/* DW_AT_decl_file (3, /usr/include/getopt.h) */
.byte 0x39 /* DW_AT_decl_line */
.4byte 0x69 /* DW_AT_type */
/* DW_AT_external */
/* DW_AT_declaration */
.uleb128 0x2 /* (DIE (0x90) DW_TAG_variable) */
.4byte .LASF13 /* DW_AT_name: "optind" */
/* DW_AT_decl_file (3, /usr/include/getopt.h) */
.byte 0x47 /* DW_AT_decl_line */
.4byte 0x54 /* DW_AT_type */
/* DW_AT_external */
/* DW_AT_declaration */
.uleb128 0x2 /* (DIE (0x9a) DW_TAG_variable) */
.4byte .LASF14 /* DW_AT_name: "opterr" */
/* DW_AT_decl_file (3, /usr/include/getopt.h) */
.byte 0x4c /* DW_AT_decl_line */
.4byte 0x54 /* DW_AT_type */
/* DW_AT_external */
/* DW_AT_declaration */
.uleb128 0x2 /* (DIE (0xa4) DW_TAG_variable) */
.4byte .LASF15 /* DW_AT_name: "optopt" */
/* DW_AT_decl_file (3, /usr/include/getopt.h) */
.byte 0x50 /* DW_AT_decl_line */
.4byte 0x54 /* DW_AT_type */
/* DW_AT_external */
/* DW_AT_declaration */
.uleb128 0x4 /* (DIE (0xae) DW_TAG_variable) */
.4byte .LASF16 /* DW_AT_name: "xvar" */
/* DW_AT_decl_file (1, main.c) */
.byte 0x2 /* DW_AT_decl_line */
.4byte 0x54 /* DW_AT_type */
/* DW_AT_external */
.uleb128 0x9 /* DW_AT_location */
.byte 0x3 /* DW_OP_addr */
.8byte 0x1234
.uleb128 0x4 /* (DIE (0xc2) DW_TAG_variable) */
.4byte .LASF17 /* DW_AT_name: "yvar" */
/* DW_AT_decl_file (1, main.c) */
.byte 0x3 /* DW_AT_decl_line */
.4byte 0x54 /* DW_AT_type */
/* DW_AT_external */
.uleb128 0x9 /* DW_AT_location */
.byte 0x3 /* DW_OP_addr */
.8byte 0x1234
.uleb128 0x4 /* (DIE (0xd6) DW_TAG_variable) */
.4byte .LASF18 /* DW_AT_name: "pvar" */
/* DW_AT_decl_file (1, main.c) */
.byte 0x4 /* DW_AT_decl_line */
.4byte 0xea /* DW_AT_type */
/* DW_AT_external */
.uleb128 0x9 /* DW_AT_location */
.byte 0x3 /* DW_OP_addr */
.8byte 0x1234
.uleb128 0x3 /* (DIE (0xea) DW_TAG_pointer_type) */
/* DW_AT_byte_size (0x8) */
.4byte 0x54 /* DW_AT_type */
.uleb128 0x9 /* (DIE (0xef) DW_TAG_subprogram) */
/* DW_AT_external */
.4byte .LASF22 /* DW_AT_name: "main" */
.byte 0x1 /* DW_AT_decl_file (main.c) */
.byte 0x6 /* DW_AT_decl_line */
/* DW_AT_prototyped */
.4byte 0x54 /* DW_AT_type */
.8byte 0x1234 /* DW_AT_low_pc */
.8byte 0x5678 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_AT_frame_base */
.byte 0x9c /* DW_OP_call_frame_cfa */
/* DW_AT_call_all_calls */
.4byte 0x13e /* DW_AT_sibling */
.uleb128 0x5 /* (DIE (0x110) DW_TAG_formal_parameter) */
.4byte .LASF19 /* DW_AT_name: "argc" */
/* DW_AT_decl_file (1, main.c) */
/* DW_AT_decl_line (0x6) */
.4byte 0x54 /* DW_AT_type */
.4byte .LLST0 /* DW_AT_location */
.uleb128 0x5 /* (DIE (0x11d) DW_TAG_formal_parameter) */
.4byte .LASF20 /* DW_AT_name: "argv" */
/* DW_AT_decl_file (1, main.c) */
/* DW_AT_decl_line (0x6) */
.4byte 0x81 /* DW_AT_type */
.4byte .LLST1 /* DW_AT_location */
.uleb128 0xa /* (DIE (0x12a) DW_TAG_call_site) */
.8byte 0x12345 /* DW_AT_call_return_pc */
.4byte 0x157 /* DW_AT_call_origin */
.uleb128 0xb /* (DIE (0x137) DW_TAG_call_site_parameter) */
.uleb128 0x1 /* DW_AT_location */
.byte 0x55 /* DW_OP_reg5 */
.uleb128 0x1 /* DW_AT_call_value */
.byte 0x30 /* DW_OP_lit0 */
.byte 0 /* end of children of DIE 0x12a */
.byte 0 /* end of children of DIE 0xef */
.uleb128 0xc /* (DIE (0x13e) DW_TAG_subprogram) */
/* DW_AT_external */
.4byte .LASF23 /* DW_AT_name: "func" */
.byte 0x1 /* DW_AT_decl_file (main.c) */
.byte 0x5 /* DW_AT_decl_line */
/* DW_AT_prototyped */
.8byte 0x1234 /* DW_AT_low_pc */
.8byte 0x5678 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_AT_frame_base */
.byte 0x9c /* DW_OP_call_frame_cfa */
/* DW_AT_call_all_calls */
.uleb128 0xd /* (DIE (0x157) DW_TAG_subprogram) */
/* DW_AT_external */
/* DW_AT_declaration */
.4byte .LASF24 /* DW_AT_linkage_name: "alarm" */
.4byte .LASF24 /* DW_AT_name: "alarm" */
.byte 0x2 /* DW_AT_decl_file (/usr/include/unistd.h) */
.2byte 0x1b3 /* DW_AT_decl_line */
.byte 0 /* end of children of DIE 0xc */
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.uleb128 0x1 /* (abbrev code) */
.uleb128 0x24 /* (TAG: DW_TAG_base_type) */
.byte 0 /* DW_children_no */
.uleb128 0xb /* (DW_AT_byte_size) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3e /* (DW_AT_encoding) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.byte 0
.byte 0
.uleb128 0x2 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 3 /* (/usr/include/getopt.h) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x3c /* (DW_AT_declaration) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.byte 0
.byte 0
.uleb128 0x3 /* (abbrev code) */
.uleb128 0xf /* (TAG: DW_TAG_pointer_type) */
.byte 0 /* DW_children_no */
.uleb128 0xb /* (DW_AT_byte_size) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 8
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.byte 0
.byte 0
.uleb128 0x4 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 1 /* (main.c) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.byte 0
.byte 0
.uleb128 0x5 /* (abbrev code) */
.uleb128 0x5 /* (TAG: DW_TAG_formal_parameter) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 1 /* (main.c) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 6
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.uleb128 0x6 /* (abbrev code) */
.uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x25 /* (DW_AT_producer) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x13 /* (DW_AT_language) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x1f /* (DW_FORM_line_strp) */
.uleb128 0x1b /* (DW_AT_comp_dir) */
.uleb128 0x1f /* (DW_FORM_line_strp) */
.uleb128 0x55 /* (DW_AT_ranges) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x10 /* (DW_AT_stmt_list) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.uleb128 0x7 /* (abbrev code) */
.uleb128 0x24 /* (TAG: DW_TAG_base_type) */
.byte 0 /* DW_children_no */
.uleb128 0xb /* (DW_AT_byte_size) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3e /* (DW_AT_encoding) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.byte 0
.byte 0
.uleb128 0x8 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0x5 /* (DW_FORM_data2) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x3c /* (DW_AT_declaration) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.byte 0
.byte 0
.uleb128 0x9 /* (abbrev code) */
.uleb128 0x2e /* (TAG: DW_TAG_subprogram) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x27 /* (DW_AT_prototyped) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x12 /* (DW_AT_high_pc) */
.uleb128 0x7 /* (DW_FORM_data8) */
.uleb128 0x40 /* (DW_AT_frame_base) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.uleb128 0x7a /* (DW_AT_call_all_calls) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x1 /* (DW_AT_sibling) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.byte 0
.byte 0
.uleb128 0xa /* (abbrev code) */
.uleb128 0x48 /* (TAG: DW_TAG_call_site) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x7d /* (DW_AT_call_return_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x7f /* (DW_AT_call_origin) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.byte 0
.byte 0
.uleb128 0xb /* (abbrev code) */
.uleb128 0x49 /* (TAG: DW_TAG_call_site_parameter) */
.byte 0 /* DW_children_no */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.uleb128 0x7e /* (DW_AT_call_value) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.byte 0
.byte 0
.uleb128 0xc /* (abbrev code) */
.uleb128 0x2e /* (TAG: DW_TAG_subprogram) */
.byte 0 /* DW_children_no */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x27 /* (DW_AT_prototyped) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x12 /* (DW_AT_high_pc) */
.uleb128 0x7 /* (DW_FORM_data8) */
.uleb128 0x40 /* (DW_AT_frame_base) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.uleb128 0x7a /* (DW_AT_call_all_calls) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.byte 0
.byte 0
.uleb128 0xd /* (abbrev code) */
.uleb128 0x2e /* (TAG: DW_TAG_subprogram) */
.byte 0 /* DW_children_no */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x3c /* (DW_AT_declaration) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x6e /* (DW_AT_linkage_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0x5 /* (DW_FORM_data2) */
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",%progbits
.4byte .Ldebug_loc2-.Ldebug_loc1 /* Length of Location Lists */
.Ldebug_loc1:
.2byte 0x5 /* DWARF Version */
.byte 0x8 /* Address Size */
.byte 0 /* Segment Size */
.4byte 0 /* Offset Entry Count */
.Ldebug_loc0:
.LLST0:
.byte 0x6 /* DW_LLE_base_address (*.LLST0) */
.8byte 0x1234 /* Base address (*.LLST0) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */
.uleb128 .LVL0-.LVL0 /* Location list begin address (*.LLST0) */
.uleb128 .LVL1-.LVL0 /* Location list end address (*.LLST0) */
.uleb128 0x1 /* Location expression size */
.byte 0x55 /* DW_OP_reg5 */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */
.uleb128 .LVL1-.LVL0 /* Location list begin address (*.LLST0) */
.uleb128 .LFE1-.LVL0 /* Location list end address (*.LLST0) */
.uleb128 0x4 /* Location expression size */
.byte 0xa3 /* DW_OP_entry_value */
.uleb128 0x1
.byte 0x55 /* DW_OP_reg5 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0 /* DW_LLE_end_of_list (*.LLST0) */
.LLST1:
.byte 0x6 /* DW_LLE_base_address (*.LLST1) */
.8byte 0x1234 /* Base address (*.LLST1) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */
.uleb128 .LVL0-.LVL0 /* Location list begin address (*.LLST1) */
.uleb128 .LVL2-1-.LVL0 /* Location list end address (*.LLST1) */
.uleb128 0x1 /* Location expression size */
.byte 0x54 /* DW_OP_reg4 */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */
.uleb128 .LVL2-1-.LVL0 /* Location list begin address (*.LLST1) */
.uleb128 .LFE1-.LVL0 /* Location list end address (*.LLST1) */
.uleb128 0x4 /* Location expression size */
.byte 0xa3 /* DW_OP_entry_value */
.uleb128 0x1
.byte 0x54 /* DW_OP_reg4 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0 /* DW_LLE_end_of_list (*.LLST1) */
.Ldebug_loc2:
.section .debug_aranges,"",%progbits
.4byte 0x3c /* Length of Address Ranges Info */
.2byte 0x2 /* DWARF Version */
.4byte .Ldebug_info0 /* Offset of Compilation Unit Info */
.byte 0x8 /* Size of Address */
.byte 0 /* Size of Segment Descriptor */
.2byte 0 /* Pad to 16 byte boundary */
.2byte 0
.8byte 0x1234 /* Address */
.8byte 0x4567 /* Length */
.8byte 0x1234 /* Address */
.8byte 0x5678 /* Length */
.8byte 0
.8byte 0
.section .debug_rnglists,"",%progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2 /* Length of Range Lists */
.Ldebug_ranges2:
.2byte 0x5 /* DWARF Version */
.byte 0x8 /* Address Size */
.byte 0 /* Segment Size */
.4byte 0 /* Offset Entry Count */
.LLRL2:
.byte 0x7 /* DW_RLE_start_length (*.LLRL2) */
.8byte 0x1234 /* Range begin address (*.LLRL2) */
.uleb128 .Letext0-.Ltext0 /* Range length (*.LLRL2) */
.byte 0x7 /* DW_RLE_start_length (*.LLRL2) */
.8byte 0x1234 /* Range begin address (*.LLRL2) */
.uleb128 .LFE1-.LFB1 /* Range length (*.LLRL2) */
.byte 0 /* DW_RLE_end_of_list (*.LLRL2) */
.Ldebug_ranges3:
.section .debug_line,"",%progbits
.Ldebug_line0:
.4byte .LELT0-.LSLT0 /* Length of Source Line Info */
.LSLT0:
.2byte 0x5 /* DWARF Version */
.byte 0x8 /* Address Size */
.byte 0 /* Segment Size */
.4byte .LELTP0-.LASLTP0 /* Prolog Length */
.LASLTP0:
.byte 0x1 /* Minimum Instruction Length */
.byte 0x1 /* Maximum Operations Per Instruction */
.byte 0x1 /* Default is_stmt_start flag */
.byte 0xf6 /* Line Base Value (Special Opcodes) */
.byte 0xf2 /* Line Range Value (Special Opcodes) */
.byte 0xd /* Special Opcode Base */
.byte 0 /* opcode: 0x1 has 0 args */
.byte 0x1 /* opcode: 0x2 has 1 arg */
.byte 0x1 /* opcode: 0x3 has 1 arg */
.byte 0x1 /* opcode: 0x4 has 1 arg */
.byte 0x1 /* opcode: 0x5 has 1 arg */
.byte 0 /* opcode: 0x6 has 0 args */
.byte 0 /* opcode: 0x7 has 0 args */
.byte 0 /* opcode: 0x8 has 0 args */
.byte 0x1 /* opcode: 0x9 has 1 arg */
.byte 0 /* opcode: 0xa has 0 args */
.byte 0 /* opcode: 0xb has 0 args */
.byte 0x1 /* opcode: 0xc has 1 arg */
.byte 0x1 /* Directory entry format count */
.uleb128 0x1 /* DW_LNCT_path */
.uleb128 0x1f /* DW_FORM_line_strp */
.uleb128 0x3 /* Directories count */
.4byte .LASF1 /* Directory Entry: 0: "" */
.4byte .LASF25 /* Directory Entry: 0: "" */
.4byte .LASF26 /* Directory Entry: 0: "/usr/include" */
.byte 0x2 /* File name entry format count */
.uleb128 0x1 /* DW_LNCT_path */
.uleb128 0x1f /* DW_FORM_line_strp */
.uleb128 0x2 /* DW_LNCT_directory_index */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x4 /* File names count */
.4byte .LASF0 /* File Entry: 0: "main.c" */
.byte 0
.4byte .LASF27 /* File Entry: 0: "main.c" */
.byte 0x1
.4byte .LASF28 /* File Entry: 0: "unistd.h" */
.byte 0x2
.4byte .LASF29 /* File Entry: 0: "getopt.h" */
.byte 0x2
.LELTP0:
.byte 0 /* set address *.LM3 */
.uleb128 0x9
.byte 0x2
.8byte 0x1234
.byte 0x1c /* line 6 */
.byte 0 /* set address *.LM4 */
.uleb128 0x9
.byte 0x2
.8byte 0x12346
.byte 0x1 /* copy line 6 */
.byte 0 /* set address *.LFE1 */
.uleb128 0x9
.byte 0x2
.8byte 0x1234
.byte 0 /* end sequence */
.uleb128 0x1
.byte 0x1
.byte 0 /* set address *.LM1 */
.uleb128 0x9
.byte 0x2
.8byte 0x1234
.byte 0x1b /* line 5 */
.byte 0 /* set address *.LM2 */
.uleb128 0x9
.byte 0x2
.8byte 0x1234
.byte 0x1 /* copy line 5 */
.byte 0 /* set address *.Letext0 */
.uleb128 0x9
.byte 0x2
.8byte 0x1234
.byte 0 /* end sequence */
.uleb128 0x1
.byte 0x1
.LELT0:
.section .debug_str,"MS",%progbits,1
.LASF4:
.asciz "unsigned int"
.LASF15:
.asciz "optopt"
.LASF22:
.asciz "main"
.LASF6:
.asciz "signed char"
.LASF16:
.asciz "xvar"
.LASF5:
.asciz "long unsigned int"
.LASF14:
.asciz "opterr"
.LASF21:
.asciz "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2"
.LASF2:
.asciz "unsigned char"
.LASF10:
.asciz "char"
.LASF13:
.asciz "optind"
.LASF8:
.asciz "long int"
.LASF19:
.asciz "argc"
.LASF3:
.asciz "short unsigned int"
.LASF17:
.asciz "yvar"
.LASF18:
.asciz "pvar"
.LASF11:
.asciz "__environ"
.LASF23:
.asciz "func"
.LASF12:
.asciz "optarg"
.LASF7:
.asciz "short int"
.LASF24:
.asciz "alarm"
.LASF9:
.asciz "sizetype"
.LASF20:
.asciz "argv"
.section .debug_line_str,"MS",%progbits,1
.LASF1:
.asciz ""
.LASF25:
.asciz ""
.LASF29:
.asciz "getopt.h"
.LASF28:
.asciz "unistd.h"
.LASF0:
.asciz "main.c"
.LASF27:
.asciz "main.c"
.LASF26:
.asciz "/usr/include"
.ident "GCC: (GNU) 7.0.1 20170218 (experimental)"
.section .note.GNU-stack,"",%progbits
|
tactcomplabs/xbgas-binutils-gdb | 5,436 | binutils/testsuite/binutils-all/dw5-op.S | /* Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
.file "main.c"
.text
.Letext0:
.section .debug_info,"",%progbits
.Ldebug_info0:
.4byte 0x4e /* Length of Compilation Unit Info */
.2byte 0x5 /* DWARF version number */
.byte 0x1 /* DW_UT_compile */
.byte 0x8 /* Pointer Size (in bytes) */
.4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */
.uleb128 0x3 /* (DIE (0xc) DW_TAG_compile_unit) */
.4byte .LASF21 /* DW_AT_producer: "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" */
.byte 0x1d /* DW_AT_language */
.4byte .LASF0 /* DW_AT_name: "main.c" */
.4byte .LASF1 /* DW_AT_comp_dir: "" */
.4byte .LLRL2 /* DW_AT_ranges */
.8byte 0 /* DW_AT_low_pc */
.4byte .Ldebug_line0 /* DW_AT_stmt_list */
.uleb128 0x1 /* (DIE (0x2a) DW_TAG_base_type) */
.byte 0x4 /* DW_AT_byte_size */
.byte 0x5 /* DW_AT_encoding */
.4byte .LASF2 /* DW_AT_name: "short int" */
.uleb128 0x2 /* (DIE (0x31) DW_TAG_variable) */
.4byte .LASF16 /* DW_AT_name: "xvar" */
/* DW_AT_decl_file (1, main.c) */
.byte 0x2 /* DW_AT_decl_line */
.4byte 0x2a /* DW_AT_type */
/* DW_AT_external */
.uleb128 0x9 /* DW_AT_location */
.byte 0x3 /* DW_OP_addr */
.8byte 0x1234
.uleb128 0x2 /* (DIE (0x45) DW_TAG_variable) */
.4byte .LASF17 /* DW_AT_name: "yvar" */
/* DW_AT_decl_file (1, main.c) */
.byte 0x3 /* DW_AT_decl_line */
.4byte 0x2a /* DW_AT_type */
/* DW_AT_external */
.uleb128 0x2 /* DW_AT_location */
.byte 0xa1 /* DW_OP_addrx */
.byte 0x0
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.uleb128 0x1 /* (abbrev code) */
.uleb128 0x24 /* (TAG: DW_TAG_base_type) */
.byte 0 /* DW_children_no */
.uleb128 0xb /* (DW_AT_byte_size) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3e /* (DW_AT_encoding) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.byte 0
.byte 0
.uleb128 0x2 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 1 /* (main.c) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x3f /* (DW_AT_external) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.byte 0
.byte 0
.uleb128 0x3 /* (abbrev code) */
.uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x25 /* (DW_AT_producer) */
.uleb128 0xe /* (DW_FORM_strp) */
.uleb128 0x13 /* (DW_AT_language) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x1f /* (DW_FORM_line_strp) */
.uleb128 0x1b /* (DW_AT_comp_dir) */
.uleb128 0x1f /* (DW_FORM_line_strp) */
.uleb128 0x55 /* (DW_AT_ranges) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x10 /* (DW_AT_stmt_list) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.byte 0
.section .debug_line,"",%progbits
.Ldebug_line0:
.4byte .LELT0-.LSLT0 /* Length of Source Line Info */
.LSLT0:
.2byte 0x5 /* DWARF Version */
.byte 0x8 /* Address Size */
.byte 0 /* Segment Size */
.4byte .LASF0 /* File Entry: 0: "main.c" */
.byte 0
.LELT0:
.section .debug_str,"MS",%progbits,1
.LASF22:
.asciz "main"
.LASF16:
.asciz "xvar"
.LASF21:
.asciz "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2"
.LASF17:
.asciz "yvar"
.LASF7:
.asciz "short int"
.section .debug_line_str,"MS",%progbits,1
.LASF1:
.asciz ""
.LASF25:
.asciz ""
.LASF0:
.asciz "main.c"
|
tactcomplabs/xbgas-binutils-gdb | 1,451 | binutils/testsuite/binutils-all/pr25662-pdp11.s | /* PR 25662: objcopy sets invalid sh_offset for the first section in a
no_contents segment containing program headers.
Several conditions are required for the bug to manifest:
- The first loadable segment (which contains the program headers) must only
contain SHT_NOBITS sections. .bss is the SHT_NOBITS section in this test.
- The next loadable segment must have a !SHT_NOBITS loadable section. .data
is the !SHT_NOBITS section in this test.
- .bss must be positioned after .data in the executable file itself.
- The size of .data must be such that the calculated VMA of the .bss
section that follows it is not congruent with the file offset of .bss,
modulo the p_align of its segment, i.e.:
(VMA(.data) + sizeof(.data)) % (.bss_segment.p_align) != 0
This will force the sh_offset of .bss to be aligned so it appears within
.data.
- The size of .data must be larger than the program headers in the first
loadable segment, so that the file offset of .bss is immediately
after .data, and not padded to a valid alignment by the program headers.
The bug originally only manifested for ELF targets, but there's no reason not
to run this testcase for other file formats. This variant source for pdp11
uses .text rather than .section text, etc., because the latter are not
supported, */
.bss
a:
.zero 0x2
.data
c:
.zero 0x201
.text
.global _start
_start:
.long 0
|
tactcomplabs/xbgas-binutils-gdb | 1,450 | binutils/testsuite/binutils-all/testranges-ia64.s | # Test .debug_info can reference .debug_ranges entries without ordering the
# offsets strictly as increasing.
.text
start:
.byte 1
sub:
.byte 2
end:
.section .debug_ranges,"",@progbits
range:
range_sub:
data4.ua @secrel(sub), @secrel(end)
data4.ua 0, 0 /* range terminator */
range_cu:
data4.ua @secrel(start), @secrel(end)
data4.ua 0, 0 /* range terminator */
.section .debug_info,"",@progbits
data4.ua debugE - debugS /* Length of Compilation Unit Info */
debugS:
.short 0x2 /* DWARF version number */
data4.ua @secrel(abbrev0) /* Offset Into Abbrev. Section */
.byte 0x4 /* Pointer Size (in bytes) */
.uleb128 0x1 /* (DIE (0xb) DW_TAG_compile_unit) */
data4.ua range_cu - range /* DW_AT_ranges */
.uleb128 0x2 /* (DIE (0x6d) DW_TAG_subprogram) */
.ascii "A\0" /* DW_AT_name */
data4.ua range_sub - range /* DW_AT_ranges */
debugE:
.section .debug_abbrev,"",@progbits
abbrev0:
.uleb128 0x1 /* (abbrev code) */
.uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */
.byte 0x0 /* DW_children_no */
.uleb128 0x55 /* (DW_AT_ranges) */
.uleb128 0x6 /* (DW_FORM_data4) */
.byte 0x0
.byte 0x0
.uleb128 0x2 /* (abbrev code) */
.uleb128 0x2e /* (TAG: DW_TAG_subprogram) */
.byte 0x0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x55 /* (DW_AT_ranges) */
.uleb128 0x6 /* (DW_FORM_data4) */
.byte 0x0
.byte 0x0
.byte 0x0 /* abbrevs terminator */
|
tactcomplabs/xbgas-binutils-gdb | 1,363 | binutils/testsuite/binutils-all/pr25662.s | /* PR 25662: objcopy sets invalid sh_offset for the first section in a
no_contents segment containing program headers.
Several conditions are required for the bug to manifest:
- The first loadable segment (which contains the program headers) must only
contain SHT_NOBITS sections. .bss is the SHT_NOBITS section in this test.
- The next loadable segment must have a !SHT_NOBITS loadable section. .data
is the !SHT_NOBITS section in this test.
- .bss must be positioned after .data in the executable file itself.
- The size of .data must be such that the calculated VMA of the .bss
section that follows it is not congruent with the file offset of .bss,
modulo the p_align of its segment, i.e.:
(VMA(.data) + sizeof(.data)) % (.bss_segment.p_align) != 0
This will force the sh_offset of .bss to be aligned so it appears within
.data.
- The size of .data must be larger than the program headers in the first
loadable segment, so that the file offset of .bss is immediately
after .data, and not padded to a valid alignment by the program headers.
The bug originally only manifested for ELF targets, but there's no reason not
to run this testcase for other file formats. */
.section .bss
aaa:
.zero 0x2
.section .data
ccc:
.zero 0x201
.section .text
.global _start
_start:
.long 0
|
tactcomplabs/xbgas-binutils-gdb | 5,276 | binutils/testsuite/binutils-all/dw2-1.S | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2008-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Dummy function to provide debug information for. */
.text
.globl _start
_start:
.4byte 0
.Lbegin_text1:
.globl func_cu1
.type func_cu1, %function
func_cu1:
.Lbegin_func_cu1:
.4byte 0
.global func_cu1_end
func_cu1_end:
.Lend_func_cu1:
.size func_cu1, .-func_cu1
.Lend_text1:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lline1_begin /* DW_AT_stmt_list */
.4byte .Lend_text1 /* DW_AT_high_pc */
.4byte .Lbegin_text1 /* DW_AT_low_pc */
.ascii "file1.txt\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.byte 1 /* DW_AT_language (C) */
/* func_cu1 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.byte 1 /* DW_AT_external */
.byte 1 /* DW_AT_decl_file */
.byte 2 /* DW_AT_decl_line */
.ascii "func_cu1\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func_cu1 /* DW_AT_low_pc */
.4byte .Lend_func_cu1 /* DW_AT_high_pc */
.byte 1 /* DW_AT_frame_base: length */
.byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */
.Ltype_int:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Line table */
.section .debug_line
.Lline1_begin:
.4byte .Lline1_end - .Lline1_start /* Initial length */
.Lline1_start:
.2byte 2 /* Version */
.4byte .Lline1_lines - .Lline1_hdr /* header_length */
.Lline1_hdr:
.byte 1 /* Minimum insn length */
.byte 1 /* default_is_stmt */
.byte 1 /* line_base */
.byte 1 /* line_range */
.byte 0x10 /* opcode_base */
/* Standard lengths */
.byte 0
.byte 1
.byte 1
.byte 1
.byte 1
.byte 0
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 0
/* Include directories */
.byte 0
/* File names */
.ascii "file1.txt\0"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.Lline1_lines:
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func_cu1
.byte 3 /* DW_LNS_advance_line */
.sleb128 3 /* ... to 4 */
.byte 1 /* DW_LNS_copy */
.byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lend_func_cu1
.byte 0 /* DW_LNE_end_of_sequence */
.uleb128 1
.byte 1
.Lline1_end:
/* Abbrev table */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x10 /* DW_AT_stmt_list */
.uleb128 0x6 /* DW_FORM_data4 */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram */
.byte 0 /* has_children */
.uleb128 0x3f /* DW_AT_external */
.uleb128 0xc /* DW_FORM_flag */
.uleb128 0x3a /* DW_AT_decl_file */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3b /* DW_AT_decl_line */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x40 /* DW_AT_frame_base */
.uleb128 0xa /* DW_FORM_block1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
|
tactcomplabs/xbgas-binutils-gdb | 2,212 | binutils/testsuite/binutils-all/linkdebug.s | /* Assembler source used to create an object file for testing readelf's
and objdump's ability to process separate debug information files.
Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This is the separate debug info file. */
/* Create .note.gnu.build-id note for use by the .gnu_debugaltlink
in the main object file. */
.section .note.gnu.build-id,"a",%note
.balign 4
.dc.l 0x04 ;# Name size
.dc.l 0x18 ;# Description size
.dc.l 0x03 ;# Type
.asciz "GNU" ;# Name
.dc.b 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
.dc.b 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
.dc.b 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef
/* Create a .debug_abbrev section for use by the .debug_info section
in the main object file. */
.section .debug_abbrev,"",%progbits
abbrevs:
.uleb128 0x01 ;# Abbrev code.
.uleb128 0x11 ;# DW_TAG_compile_unit
.byte 0x00 ;# DW_children_no
.uleb128 0x03 ;# DW_AT_name
.uleb128 0x0e ;# DW_FORM_strp
.byte 0x00 ;# End of abbrev
.byte 0x00
.uleb128 0x02 ;# Abbrev code.
.uleb128 0x2e ;# DW_TAG_subprogram
.byte 0x00 ;# DW_children_no
.uleb128 0x03 ;# DW_AT_name
.uleb128 0x1f21 ;# DW_FORM_GNU_strp_alt
.byte 0x0 ;# End of abbrev
.byte 0x0
.byte 0x0 ;# Abbrevs terminator
/* Create a .debug_str section for remote use. This is also to check
the ability to dump the same section twice, if it exists in
both the main file and the separate debug info file. */
.section .debug_str,"MS",%progbits,1
string3:
.asciz "string-3"
.asciz "string-4"
.balign 2
string_end:
|
tactcomplabs/xbgas-binutils-gdb | 9,143 | binutils/testsuite/binutils-all/dw2-3.S | /* This testcase is part of GDB, the GNU debugger.
Copyright (C) 2004-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Test a minimal file containing DWARF-2 information. This test also
serves as a skeleton for other DWARF-2 tests. Most other tests will
not be this extensively itemized and commented... */
/* Dummy function to provide debug information for. */
.text
.Lbegin_text1:
.globl func_cu1
.type func_cu1, %function
func_cu1:
.Lbegin_func_cu1:
.4byte 0
.Lend_func_cu1:
.size func_cu1, .-func_cu1
.Lend_text1:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lline1_begin /* DW_AT_stmt_list */
.4byte .Lend_text1 /* DW_AT_high_pc */
.4byte .Lbegin_text1 /* DW_AT_low_pc */
.ascii "file1.txt\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.byte 1 /* DW_AT_language (C) */
/* func_cu1 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.byte 1 /* DW_AT_external */
.byte 1 /* DW_AT_decl_file */
.byte 2 /* DW_AT_decl_line */
.ascii "func_cu1\0" /* DW_AT_name */
.4byte .Ltype_int2_in_cu2 /* DW_AT_type */
.4byte .Lbegin_func_cu1 /* DW_AT_low_pc */
.4byte .Lend_func_cu1 /* DW_AT_high_pc */
.byte 1 /* DW_AT_frame_base: length */
.byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */
/* This type is named "int1" and not "int" to ensure it is unique,
and thus we can easily ensure we expand this CU and not some
other CU with "int". */
.Ltype_int1_in_cu1:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int1\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.Ltype_const_int1_in_cu1:
.uleb128 4 /* Abbrev: DW_TAG_const_type */
.4byte .Ltype_int1_in_cu1-.Lcu1_begin /* DW_AT_type */
.uleb128 5 /* Abbrev: DW_TAG_variable */
.ascii "one\0" /* DW_AT_name */
.4byte .Ltype_const_int1_in_cu1-.Lcu1_begin /* DW_AT_type */
.byte 1 /* DW_AT_const_value */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Second compilation unit. */
.Lcu2_begin:
/* CU header */
.4byte .Lcu2_end - .Lcu2_start /* Length of Compilation Unit */
.Lcu2_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev2_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.ascii "file1.txt\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.byte 1 /* DW_AT_language (C) */
/* This type is named "int2" and not "int" to ensure it is unique,
and thus we can easily ensure we expand this CU and not some
other CU with "int". */
.Ltype_int2_in_cu2:
.uleb128 2 /* Abbrev: DW_TAG_base_type */
.ascii "int2\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.Ltype_const_int2_in_cu2:
.uleb128 3 /* Abbrev: DW_TAG_const_type */
.4byte .Ltype_int2_in_cu2-.Lcu2_begin /* DW_AT_type */
.uleb128 4 /* Abbrev: DW_TAG_variable */
.ascii "two\0" /* DW_AT_name */
.4byte .Ltype_const_int2_in_cu2-.Lcu2_begin /* DW_AT_type */
.byte 2 /* DW_AT_const_value */
.byte 0 /* End of children of CU */
.Lcu2_end:
/* Abbrev table */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x10 /* DW_AT_stmt_list */
.uleb128 0x6 /* DW_FORM_data4 */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram */
.byte 0 /* has_children */
.uleb128 0x3f /* DW_AT_external */
.uleb128 0xc /* DW_FORM_flag */
.uleb128 0x3a /* DW_AT_decl_file */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3b /* DW_AT_decl_line */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x10 /* DW_FORM_ref_addr */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x40 /* DW_AT_frame_base */
.uleb128 0xa /* DW_FORM_block1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 4 /* Abbrev code */
.uleb128 0x26 /* DW_TAG_const_type */
.byte 0x0 /* DW_children_no */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 5 /* Abbrev code */
.uleb128 0x34 /* DW_TAG_variable */
.byte 0x0 /* DW_children_no */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x1c /* DW_AT_const_value */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.Labbrev2_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x25 /* DW_AT_producer */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x26 /* DW_TAG_const_type */
.byte 0x0 /* DW_children_no */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 4 /* Abbrev code */
.uleb128 0x34 /* DW_TAG_variable */
.byte 0x0 /* DW_children_no */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x1c /* DW_AT_const_value */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
/* Line table */
.section .debug_line
.Lline1_begin:
.4byte .Lline1_end - .Lline1_start /* Initial length */
.Lline1_start:
.2byte 2 /* Version */
.4byte .Lline1_lines - .Lline1_hdr /* header_length */
.Lline1_hdr:
.byte 1 /* Minimum insn length */
.byte 1 /* default_is_stmt */
.byte 1 /* line_base */
.byte 1 /* line_range */
.byte 0x10 /* opcode_base */
/* Standard lengths */
.byte 0
.byte 1
.byte 1
.byte 1
.byte 1
.byte 0
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 0
/* Include directories */
.byte 0
/* File names */
.ascii "file1.txt\0"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.Lline1_lines:
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func_cu1
.byte 3 /* DW_LNS_advance_line */
.sleb128 3 /* ... to 4 */
.byte 1 /* DW_LNS_copy */
.byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lend_func_cu1
.byte 0 /* DW_LNE_end_of_sequence */
.uleb128 1
.byte 1
.Lline1_end:
|
tactcomplabs/xbgas-binutils-gdb | 1,400 | binutils/testsuite/binutils-all/testranges.s | # Test .debug_info can reference .debug_ranges entries without ordering the
# offsets strictly as increasing.
.text
start:
.byte 1
sub:
.byte 2
end:
.section .debug_ranges,"",%progbits
range:
range_sub:
.4byte sub, end
.4byte 0, 0 ;# range terminator
range_cu:
.4byte start, end
.4byte 0, 0 ;# range terminator
.section .debug_info,"",%progbits
.4byte debugE - debugS ;# Length of Compilation Unit Info
debugS:
.short 0x2 ;# DWARF version number
.4byte abbrev0 ;# Offset Into Abbrev. Section
.byte 0x4 ;# Pointer Size (in bytes)
.uleb128 0x1 ;# (DIE (0xb) DW_TAG_compile_unit)
.4byte range_cu - range ;# DW_AT_ranges
.uleb128 0x2 ;# (DIE (0x6d) DW_TAG_subprogram)
.ascii "A\0" ;# DW_AT_name
.4byte range_sub - range ;# DW_AT_ranges
;# minimal section alignment on alpha-* is 2, ensure no new invalid CU
;# will be started.
.balign 2
debugE:
.section .debug_abbrev,"",%progbits
abbrev0:
.uleb128 0x1 ;# (abbrev code)
.uleb128 0x11 ;# (TAG: DW_TAG_compile_unit)
.byte 0x0 ;# DW_children_no
.uleb128 0x55 ;# (DW_AT_ranges)
.uleb128 0x6 ;# (DW_FORM_data4)
.byte 0x0
.byte 0x0
.uleb128 0x2 ;# (abbrev code)
.uleb128 0x2e ;# (TAG: DW_TAG_subprogram)
.byte 0x0 ;# DW_children_no
.uleb128 0x3 ;# (DW_AT_name)
.uleb128 0x8 ;# (DW_FORM_string)
.uleb128 0x55 ;# (DW_AT_ranges)
.uleb128 0x6 ;# (DW_FORM_data4)
.byte 0x0
.byte 0x0
.byte 0x0 ;# abbrevs terminator
|
tactcomplabs/xbgas-binutils-gdb | 4,450 | binutils/testsuite/binutils-all/dwarf-attributes.S | /* Copyright (C) 2017-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file is intended to check the encoding and decoding of DWARF attributes.
Currently only numeric attributes are tested, but this file should be extended
to cover other types of attribute as well. */
.file "dwarf-attributes.S"
.section .debug_info,"",%progbits
.4byte .Ldebug_info_end - .Ldebug_info_start /* Length of Compilation Unit Info. */
.Ldebug_info_start:
.2byte 0x5 /* DWARF version number. */
.byte 0x1 /* DW_UT_compile. */
.byte 0x4 /* Pointer Size (in bytes). */
.4byte .Ldebug_abbrevs /* Offset Into Abbrev. Section. */
/* Start of DIE 0xc. */
.uleb128 0x1 /* Using abbrev #1 */
.byte 1 /* Ordering: column major. */
.2byte 1 /* Language: C89. */
.byte 1 /* Visibility: local. */
.byte 1 /* Inline: inlined. */
.byte 1 /* Accessibility: public. */
.byte 1 /* Calling convention: normal. */
.byte 3,1,1,2 /* Discriminate list: range. */
.byte 1 /* Encoding: address. */
.byte 1 /* Identifier case: up. */
.byte 1 /* Virtuality: virtual. */
.byte 1 /* Decimal sign: unsigned. */
.byte 1 /* Endianity: big. */
.byte 1 /* Defaulted: in class. */
.uleb128 0x1 /* Using abbrev #1 */
.byte 0 /* Ordering: row major */
.2byte 0x0016 /* Language: Go. */
.byte 2 /* Visibility: exported. */
.byte 0 /* Inline: not. */
.byte 2 /* Accessibility: protected. */
.byte 5 /* Calling convention: pass by value. */
.byte 2,0,1 /* Discriminate list: label. */
.byte 0x12 /* Encoding: ASCII. */
.byte 0 /* Identifier case: sensitive. */
.byte 0 /* Virtuality: none. */
.byte 2 /* Decimal sign: leading overpunch. */
.byte 0 /* Endianity: default. */
.byte 0 /* Defaulted: no. */
.uleb128 0x1 /* Using abbrev #1 */
.byte -1 /* Ordering: undefined. */
.2byte 0x8001 /* Language: MIPS Assembler. */
.byte 3 /* Visibility: qualified. */
.byte 3 /* Inline: declared. */
.byte 3 /* Accessibility: private. */
.byte 0x40 /* Calling convention: Renesas SH. */
.byte 5,1,2,3,0,4 /* Discriminate list: range and label. */
.byte 0x81 /* Encoding: user specified. */
.byte 3 /* Identifier case: insensitive. */
.byte 2 /* Virtuality: pure. */
.byte 5 /* Decimal sign: trailing separate. */
.byte 0x50 /* Endianity: user specified. */
.byte 2 /* Defaulted: out of class. */
.byte 0 /* End of children of DIE 0xc. */
.Ldebug_info_end:
.section .debug_abbrev,"",%progbits
.Ldebug_abbrevs:
.uleb128 0x1 /* (abbrev code) */
.uleb128 0x5555 /* (TAG: DW_TAG_lo_user + 0x1555) */
.byte 0 /* DW_children_no */
/* Attributes to be tested. Sorted by attribute value. */
.uleb128 0x9 /* (DW_AT_ordering) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x13 /* (DW_AT_language) */
.uleb128 0x05 /* (DW_FORM_data2) */
.uleb128 0x17 /* (DW_AT_visibility) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x20 /* (DW_AT_inline) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x32 /* (DW_AT_accessibility) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x36 /* (DW_AT_calling_convention) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x3d /* (DW_AT_discr_lists) */
.uleb128 0x0a /* (DW_FORM_block1) */
.uleb128 0x3e /* (DW_AT_encoding) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x42 /* (DW_AT_identifier_case) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x4c /* (DW_AT_virtuality) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x5e /* (DW_AT_decimal_sign) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x65 /* (DW_AT_endianity) */
.uleb128 0x0b /* (DW_FORM_data1) */
.uleb128 0x8b /* (DW_AT_defaulted) */
.uleb128 0x0b /* (DW_FORM_data1) */
.byte 0 /* End of abbreviation. */
.byte 0
.byte 0 /* End of abbreviations. */
|
tactcomplabs/xbgas-binutils-gdb | 11,323 | binutils/testsuite/binutils-all/locview-2.s | .text
.Ltext0:
.LFB0:
/* locview.c:1 */
.LM1:
/* view -0 */
/* locview.c:2 */
.LM2:
/* view 1 */
.LVL0:
/* DEBUG i => 0 */
/* locview.c:3 */
.LM3:
/* view 2 */
/* DEBUG j => 0x1 */
/* locview.c:4 */
.LM4:
/* view 3 */
/* DEBUG i => 0x2 */
/* locview.c:5 */
.LM5:
/* view 4 */
/* DEBUG j => 0x3 */
/* locview.c:6 */
.LM6:
/* view 5 */
/* DEBUG k => 0x4 */
/* DEBUG l => 0x4 */
/* locview.c:7 */
.LM7:
/* view 6 */
/* DEBUG k => 0x5 */
/* DEBUG l => 0x5 */
/* locview.c:8 */
.LM8:
/* view 7 */
/* DEBUG k => 0x6 */
/* DEBUG l => 0x6 */
/* locview.c:9 */
.LM9:
/* view 8 */
.byte 0
.LFE0:
.Letext0:
.section .debug_info
.Ldebug_info0:
.LIbase:
.4byte .LIend - .LIstart /* Length of Compilation Unit Info */
.LIstart:
.2byte 0x5 /* DWARF version number */
.byte 0x1 /* DW_UT_compile */
.byte 0x4 /* Pointer Size (in bytes) */
.4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */
.LIcu:
.uleb128 0x2 /* (DIE (cu) DW_TAG_compile_unit) */
.ascii "hand-crafted based on GCC output\0"
.byte 0x1d /* DW_AT_language */
.ascii "locview.c\0"
.ascii "/tmp\0"
.4byte 0 /* DW_AT_low_pc */
.LIsubf:
.uleb128 0x3 /* (DIE (subf) DW_TAG_subprogram) */
.ascii "f\0" /* DW_AT_name */
.byte 0x1 /* DW_AT_decl_file (locview.c) */
.byte 0x1 /* DW_AT_decl_line */
.4byte .LIint-.LIbase /* DW_AT_type */
.4byte .LFB0 /* DW_AT_low_pc */
.4byte 1 /* .LFE0-.LFB0 */ /* DW_AT_high_pc */
.uleb128 0x1 /* DW_AT_frame_base */
.byte 0x9c /* DW_OP_call_frame_cfa */
/* DW_AT_call_all_calls */
.4byte .LIint - .LIbase /* DW_AT_sibling */
.LIvari:
.uleb128 0x1 /* (DIE (vari) DW_TAG_variable) */
.ascii "i\0" /* DW_AT_name */
/* DW_AT_decl_file (1, locview.c) */
.byte 0x2 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LLST0 /* DW_AT_location */
.4byte .LVUS0 /* DW_AT_GNU_locviews */
.LIvarj:
.uleb128 0x1 /* (DIE (varj) DW_TAG_variable) */
.ascii "j\0" /* DW_AT_name */
/* DW_AT_decl_file (1, locview.c) */
.byte 0x3 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LLST1 /* DW_AT_location */
.4byte .LVUS1 /* DW_AT_GNU_locviews */
.LIvark:
.uleb128 0x5 /* (DIE (vark) DW_TAG_variable) */
.ascii "k\0" /* DW_AT_name */
/* DW_AT_decl_file (1, locview.c) */
.byte 0x6 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LVUS2 /* DW_AT_GNU_locviews */
.4byte .LLST2 /* DW_AT_location */
.LIvarl:
.uleb128 0x6 /* (DIE (varl) DW_TAG_variable) */
.ascii "l\0" /* DW_AT_name */
/* DW_AT_decl_file (1, locview.c) */
.byte 0x6 /* DW_AT_decl_line */
.4byte .LIint - .LIbase /* DW_AT_type */
.4byte .LLST3 /* DW_AT_location */
.byte 0 /* end of children of DIE subf */
.LIint:
.uleb128 0x4 /* (DIE (int) DW_TAG_base_type) */
.byte 0x4 /* DW_AT_byte_size */
.byte 0x5 /* DW_AT_encoding */
.ascii "int\0" /* DW_AT_name */
.byte 0 /* end of children of DIE cu */
.LIend:
.section .debug_abbrev
.Ldebug_abbrev0:
.LAbrv1:
.uleb128 0x1 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 1 /* (locview.c) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.uleb128 0x2137 /* (DW_AT_GNU_locviews) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.LAbrv2:
.uleb128 0x2 /* (abbrev code) */
.uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x25 /* (DW_AT_producer) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x13 /* (DW_AT_language) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x1b /* (DW_AT_comp_dir) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.byte 0
.byte 0
.LAbrv3:
.uleb128 0x3 /* (abbrev code) */
.uleb128 0x2e /* (TAG: DW_TAG_subprogram) */
.byte 0x1 /* DW_children_yes */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x11 /* (DW_AT_low_pc) */
.uleb128 0x1 /* (DW_FORM_addr) */
.uleb128 0x12 /* (DW_AT_high_pc) */
.uleb128 0x6 /* (DW_FORM_data4) */
.uleb128 0x40 /* (DW_AT_frame_base) */
.uleb128 0x18 /* (DW_FORM_exprloc) */
.uleb128 0x7a /* (DW_AT_call_all_calls) */
.uleb128 0x19 /* (DW_FORM_flag_present) */
.uleb128 0x1 /* (DW_AT_sibling) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.byte 0
.byte 0
.LAbrv4:
.uleb128 0x4 /* (abbrev code) */
.uleb128 0x24 /* (TAG: DW_TAG_base_type) */
.byte 0 /* DW_children_no */
.uleb128 0xb /* (DW_AT_byte_size) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3e /* (DW_AT_encoding) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.byte 0
.byte 0
.LAbrv5:
.uleb128 0x5 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 1 /* (locview.c) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x2137 /* (DW_AT_GNU_locviews) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.LAbrv6:
.uleb128 0x6 /* (abbrev code) */
.uleb128 0x34 /* (TAG: DW_TAG_variable) */
.byte 0 /* DW_children_no */
.uleb128 0x3 /* (DW_AT_name) */
.uleb128 0x8 /* (DW_FORM_string) */
.uleb128 0x3a /* (DW_AT_decl_file) */
.uleb128 0x21 /* (DW_FORM_implicit_const) */
.sleb128 1 /* (locview.c) */
.uleb128 0x3b /* (DW_AT_decl_line) */
.uleb128 0xb /* (DW_FORM_data1) */
.uleb128 0x49 /* (DW_AT_type) */
.uleb128 0x13 /* (DW_FORM_ref4) */
.uleb128 0x2 /* (DW_AT_location) */
.uleb128 0x17 /* (DW_FORM_sec_offset) */
.byte 0
.byte 0
.byte 0
.section .debug_loclists
.4byte .Ldebug_loc2-.Ldebug_loc1 /* Length of Location Lists */
.Ldebug_loc1:
.2byte 0x5 /* DWARF version number */
.byte 0x4 /* Address Size */
.byte 0 /* Segment Size */
.4byte 0 /* Offset Entry Count */
.Ldebug_loc0:
.LVUS0:
.uleb128 0x2 /* View list begin (*.LVUS0) */
.uleb128 0x4 /* View list end (*.LVUS0) */
.uleb128 0x4 /* View list begin (*.LVUS0) */
.uleb128 0 /* View list end (*.LVUS0) */
.LLST0:
.byte 0x6 /* DW_LLE_base_address (*.LLST0) */
.4byte .LVL0 /* Base address (*.LLST0) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST0) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST0) */
.uleb128 0x2 /* Location expression size */
.byte 0x30 /* DW_OP_lit0 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST0) */
.uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST0) */
.uleb128 0x2 /* Location expression size */
.byte 0x32 /* DW_OP_lit2 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0 /* DW_LLE_end_of_list (*.LLST0) */
.LLST1:
.byte 0x6 /* DW_LLE_base_address (*.LLST1) */
.4byte .LVL0 /* Base address (*.LLST1) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST1) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST1) */
.uleb128 0x2 /* Location expression size */
.byte 0x31 /* DW_OP_lit1 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST1) */
.uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST1) */
.uleb128 0x2 /* Location expression size */
.byte 0x33 /* DW_OP_lit3 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0 /* DW_LLE_end_of_list (*.LLST1) */
.LVUS1:
.uleb128 0x3 /* View list begin (*.LVUS1) */
.uleb128 0x5 /* View list end (*.LVUS1) */
.uleb128 0x5 /* View list begin (*.LVUS1) */
.uleb128 0 /* View list end (*.LVUS1) */
.LVUS2:
.uleb128 0x6 /* View list begin (*.LVUS2) */
.uleb128 0x7 /* View list end (*.LVUS2) */
.uleb128 0x7 /* View list begin (*.LVUS2) */
.uleb128 0x8 /* View list end (*.LVUS2) */
.uleb128 0x8 /* View list begin (*.LVUS2) */
.uleb128 0 /* View list end (*.LVUS2) */
.LLST2:
.byte 0x6 /* DW_LLE_base_address (*.LLST2) */
.4byte .LVL0 /* Base address (*.LLST2) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST2) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST2) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST2) */
.uleb128 0x2 /* Location expression size */
.byte 0x34 /* DW_OP_lit4 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST2) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST2) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST2) */
.uleb128 0x2 /* Location expression size */
.byte 0x35 /* DW_OP_lit5 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST2) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST2) */
.uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST2) */
.uleb128 0x2 /* Location expression size */
.byte 0x36 /* DW_OP_lit6 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0 /* DW_LLE_end_of_list (*.LLST2) */
.LLST3:
.byte 0x6 /* DW_LLE_base_address (*.LLST3) */
.4byte .LVL0 /* Base address (*.LLST3) */
.byte 0x9 /* DW_LLE_view_pair (extension proposed for DWARF6) */
.uleb128 0x6 /* View list begin (*.LLST3) */
.uleb128 0x7 /* View list end (*.LVUS3) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST3) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST3) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST3) */
.uleb128 0x2 /* Location expression size */
.byte 0x34 /* DW_OP_lit4 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0x9 /* DW_LLE_view_pair */
.uleb128 0x7 /* View list begin (*.LLST3) */
.uleb128 0x8 /* View list end (*.LVUS3) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST3) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST3) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST3) */
.uleb128 0x2 /* Location expression size */
.byte 0x35 /* DW_OP_lit5 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0x9 /* DW_LLE_view_pair */
.uleb128 0x8 /* View list begin (*.LLST3) */
.uleb128 0x0 /* View list end (*.LVUS3) */
.byte 0x4 /* DW_LLE_offset_pair (*.LLST3) */
.uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST3) */
.uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST3) */
.uleb128 0x2 /* Location expression size */
.byte 0x36 /* DW_OP_lit6 */
.byte 0x9f /* DW_OP_stack_value */
.byte 0 /* DW_LLE_end_of_list (*.LLST3) */
.Ldebug_loc2:
|
tactcomplabs/xbgas-binutils-gdb | 4,519 | binutils/testsuite/binutils-all/dw2-compressed.S | /* This testcase is derived from a similar test in GDB.
Copyright (C) 2008-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This tests that gdb can read compressed sections. The contents
are a basic assembly file, but the .debug_abbrev section has been
comrpessed using zlib. */
/* Dummy function to provide debug information for. */
.text
.globl _start
_start:
.int 0
.Lbegin_text1:
.globl func_cu1
.type func_cu1, %function
func_cu1:
.Lbegin_func_cu1:
.int 0
.Lend_func_cu1:
.size func_cu1, .-func_cu1
.Lend_text1:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lline1_begin /* DW_AT_stmt_list */
.4byte .Lend_text1 /* DW_AT_high_pc */
.4byte .Lbegin_text1 /* DW_AT_low_pc */
.ascii "file1.txt\0" /* DW_AT_name */
.ascii "GNU C 3.3.3\0" /* DW_AT_producer */
.byte 1 /* DW_AT_language (C) */
/* func_cu1 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.byte 1 /* DW_AT_external */
.byte 1 /* DW_AT_decl_file */
.byte 2 /* DW_AT_decl_line */
.ascii "func_cu1\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func_cu1 /* DW_AT_low_pc */
.4byte .Lend_func_cu1 /* DW_AT_high_pc */
.byte 1 /* DW_AT_frame_base: length */
.byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */
.Ltype_int:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.byte 0 /* End of children of CU */
.Lcu1_end:
/* Line table */
.section .debug_line
.Lline1_begin:
.4byte .Lline1_end - .Lline1_start /* Initial length */
.Lline1_start:
.2byte 2 /* Version */
.4byte .Lline1_lines - .Lline1_hdr /* header_length */
.Lline1_hdr:
.byte 1 /* Minimum insn length */
.byte 1 /* default_is_stmt */
.byte 1 /* line_base */
.byte 1 /* line_range */
.byte 0x10 /* opcode_base */
/* Standard lengths */
.byte 0
.byte 1
.byte 1
.byte 1
.byte 1
.byte 0
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 1
.byte 0
.byte 0
.byte 0
/* Include directories */
.byte 0
/* File names */
.ascii "file1.txt\0"
.uleb128 0
.uleb128 0
.uleb128 0
.byte 0
.Lline1_lines:
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lbegin_func_cu1
.byte 3 /* DW_LNS_advance_line */
.sleb128 3 /* ... to 4 */
.byte 1 /* DW_LNS_copy */
.byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */
.byte 0 /* DW_LNE_set_address */
.uleb128 5
.byte 2
.4byte .Lend_func_cu1
.byte 0 /* DW_LNE_end_of_sequence */
.uleb128 1
.byte 1
.Lline1_end:
/* Abbrev table -- compressed */
.section .zdebug_abbrev
.Labbrev1_begin:
.ascii "ZLIB"
.4byte 0
.2byte 0
.byte 0
.byte 51
.byte 0x78
.byte 0x5e
.byte 0x63
.byte 0x14
.byte 0x64
.byte 0x14
.byte 0x60
.byte 0x13
.byte 0x62
.byte 0x14
.byte 0x64
.byte 0x64
.byte 0xe6
.byte 0x50
.byte 0xe5
.byte 0x10
.byte 0xe6
.byte 0x66
.byte 0x60
.byte 0x60
.byte 0xd2
.byte 0x63
.byte 0xb0
.byte 0xe7
.byte 0xb1
.byte 0xe2
.byte 0xb6
.byte 0xe6
.byte 0x66
.byte 0xe6
.byte 0xf0
.byte 0x14
.byte 0x16
.byte 0x64
.byte 0x14
.byte 0x62
.byte 0x74
.byte 0xe0
.byte 0x02
.byte 0x00
.byte 0x25
.byte 0x78
.byte 0x02
.byte 0x81
.byte 0x78
.byte 0x9c
.byte 0x63
.byte 0x60
.byte 0x60
.byte 0x56
.byte 0x61
.byte 0x60
.byte 0xe6
.byte 0xe0
.byte 0xe6
.byte 0xb6
.byte 0xe3
.byte 0x66
.byte 0x00
.byte 0x02
.byte 0x00
.byte 0x04
.byte 0x9c
.byte 0x00
.byte 0x92
|
tactcomplabs/xbgas-binutils-gdb | 1,086 | binutils/testsuite/binutils-all/readelf.s | There are .* section headers, starting at offset .*:
Section Headers:
+\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0
# On the normal MIPS systems, sections must be aligned to 16 byte
# boundaries. On IA64, text sections are aligned to 16 byte boundaries.
+\[ 1\] .* +PROGBITS +00000000 0000(34|38|40) 0000(08|10) 00 +AX +0 +0 +(.|..)
+\[ 2\] .rel.* +REL. +0+ 0+.* 0000.. 0. +I +.+ +1 +4
# MIPS targets put .rela.text here.
#...
+\[ .\] .* +PROGBITS +00000000 0000(3c|40|44|48|50) 0000(04|10) 00 +WA +0 +0 +(.|..)
+\[ .\] .* +NOBITS +00000000 0000(40|44|48|4c|60) 000000 00 +WA +0 +0 +(.|..)
# ARM targets put .ARM.attributes here.
# MIPS targets put .reginfo, .mdebug, .MIPS.abiflags and .gnu.attributes here.
# v850 targets put .call_table_data and .call_table_text here.
# riscv targets put .riscv.attributes here.
#...
+\[..\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +.+ +4
+\[..\] .strtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +1
+\[..\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +.
Key to Flags:
#...
|
tactcomplabs/xbgas-binutils-gdb | 35,389 | binutils/testsuite/binutils-all/dw4.s | .file "main.c"
.text
.Ltext0:
.text
.globl main
.type main, %function
main:
.LFB0:
.file 1 "main.c"
.loc 1 6 1 view -0
.word 1234
.word 5678
.LFE0:
.size main, . - main
.globl g_my_private_global
.data
.align 4
.type g_my_private_global, %object
.size g_my_private_global, 4
g_my_private_global:
.zero 4
.globl g_my_externd_global
.data
.align 4
.type g_my_externd_global, %object
.size g_my_externd_global, 4
g_my_externd_global:
.zero 4
.text
.Letext0:
.section .debug_info,"",%progbits
.Ldebug_info0:
.long .Linfo_end - .Linfo_start
.Linfo_start:
.short 0x4
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0x1
.long .LASF345
.byte 0xc
.long .LASF346
.long .LASF347
.long .Ldebug_ranges0 + 0
.quad 0
.long .Ldebug_line0
.long .Ldebug_macro0
.Lvar_decl:
.uleb128 0x2
.long .LASF343
.byte 0x1
.byte 0x2
.byte 0xc
.long 0x39
.uleb128 0x3
.byte 0x4
.byte 0x5
.string "int"
.uleb128 0x4
.long .Lvar_decl - .Ldebug_info0
.byte 0x3
.byte 0x5
.uleb128 .Lblock1_end - .Lblock1_start
.Lblock1_start:
.byte 0x3
.dc.a g_my_externd_global
.Lblock1_end:
.uleb128 0x5
.long .LASF344
.byte 0x1
.byte 0x4
.byte 0x5
.long 0x39
.uleb128 .Lblock2_end - .Lblock2_start
.Lblock2_start:
.byte 0x3
.dc.a g_my_private_global
.Lblock2_end:
.uleb128 0x6
.long .LASF348
.byte 0x1
.byte 0x5
.byte 0x5
.long 0x39
.quad 0
.quad 0x10
.uleb128 0x1
.byte 0x9c
.byte 0
.Linfo_end:
.section .debug_abbrev,"",%progbits
.Ldebug_abbrev0:
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x55
.uleb128 0x17
.uleb128 0x11
.uleb128 0x1
.uleb128 0x10
.uleb128 0x17
.uleb128 0x2119
.uleb128 0x17
.byte 0
.byte 0
.uleb128 0x2
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x39
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3c
.uleb128 0x19
.byte 0
.byte 0
.uleb128 0x3
.uleb128 0x24
.byte 0
.uleb128 0xb
.uleb128 0xb
.uleb128 0x3e
.uleb128 0xb
.uleb128 0x3
.uleb128 0x8
.byte 0
.byte 0
.uleb128 0x4
.uleb128 0x34
.byte 0
.uleb128 0x47
.uleb128 0x13
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x39
.uleb128 0xb
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x5
.uleb128 0x34
.byte 0
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x39
.uleb128 0xb
.uleb128 0x49
.uleb128 0x13
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x2
.uleb128 0x18
.byte 0
.byte 0
.uleb128 0x6
.uleb128 0x2e
.byte 0
.uleb128 0x3f
.uleb128 0x19
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x39
.uleb128 0xb
.uleb128 0x27
.uleb128 0x19
.uleb128 0x49
.uleb128 0x13
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x7
.uleb128 0x40
.uleb128 0x18
.uleb128 0x2117
.uleb128 0x19
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"",%progbits
.long 0x2c
.short 0x2
.long .Ldebug_info0
.byte 0x8
.byte 0
.short 0
.short 0
.dc.a .LFB0
.quad .LFE0 - .LFB0
.quad 0
.quad 0
.section .debug_ranges,"",%progbits
.Ldebug_ranges0:
.dc.a .LFB0
.dc.a .LFE0
.quad 0
.quad 0
.section .debug_macro,"",%progbits
.Ldebug_macro0:
.short 0x4
.byte 0x2
.long .Ldebug_line0
.byte 0x3
.uleb128 0
.uleb128 0x1
.byte 0x5
.uleb128 0x1
.long .LASF0
.byte 0x5
.uleb128 0x2
.long .LASF1
.byte 0x5
.uleb128 0x3
.long .LASF2
.byte 0x5
.uleb128 0x4
.long .LASF3
.byte 0x5
.uleb128 0x5
.long .LASF4
.byte 0x5
.uleb128 0x6
.long .LASF5
.byte 0x5
.uleb128 0x7
.long .LASF6
.byte 0x5
.uleb128 0x8
.long .LASF7
.byte 0x5
.uleb128 0x9
.long .LASF8
.byte 0x5
.uleb128 0xa
.long .LASF9
.byte 0x5
.uleb128 0xb
.long .LASF10
.byte 0x5
.uleb128 0xc
.long .LASF11
.byte 0x5
.uleb128 0xd
.long .LASF12
.byte 0x5
.uleb128 0xe
.long .LASF13
.byte 0x5
.uleb128 0xf
.long .LASF14
.byte 0x5
.uleb128 0x10
.long .LASF15
.byte 0x5
.uleb128 0x11
.long .LASF16
.byte 0x5
.uleb128 0x12
.long .LASF17
.byte 0x5
.uleb128 0x13
.long .LASF18
.byte 0x5
.uleb128 0x14
.long .LASF19
.byte 0x5
.uleb128 0x15
.long .LASF20
.byte 0x5
.uleb128 0x16
.long .LASF21
.byte 0x5
.uleb128 0x17
.long .LASF22
.byte 0x5
.uleb128 0x18
.long .LASF23
.byte 0x5
.uleb128 0x19
.long .LASF24
.byte 0x5
.uleb128 0x1a
.long .LASF25
.byte 0x5
.uleb128 0x1b
.long .LASF26
.byte 0x5
.uleb128 0x1c
.long .LASF27
.byte 0x5
.uleb128 0x1d
.long .LASF28
.byte 0x5
.uleb128 0x1e
.long .LASF29
.byte 0x5
.uleb128 0x1f
.long .LASF30
.byte 0x5
.uleb128 0x20
.long .LASF31
.byte 0x5
.uleb128 0x21
.long .LASF32
.byte 0x5
.uleb128 0x22
.long .LASF33
.byte 0x5
.uleb128 0x23
.long .LASF34
.byte 0x5
.uleb128 0x24
.long .LASF35
.byte 0x5
.uleb128 0x25
.long .LASF36
.byte 0x5
.uleb128 0x26
.long .LASF37
.byte 0x5
.uleb128 0x27
.long .LASF38
.byte 0x5
.uleb128 0x28
.long .LASF39
.byte 0x5
.uleb128 0x29
.long .LASF40
.byte 0x5
.uleb128 0x2a
.long .LASF41
.byte 0x5
.uleb128 0x2b
.long .LASF42
.byte 0x5
.uleb128 0x2c
.long .LASF43
.byte 0x5
.uleb128 0x2d
.long .LASF44
.byte 0x5
.uleb128 0x2e
.long .LASF45
.byte 0x5
.uleb128 0x2f
.long .LASF46
.byte 0x5
.uleb128 0x30
.long .LASF47
.byte 0x5
.uleb128 0x31
.long .LASF48
.byte 0x5
.uleb128 0x32
.long .LASF49
.byte 0x5
.uleb128 0x33
.long .LASF50
.byte 0x5
.uleb128 0x34
.long .LASF51
.byte 0x5
.uleb128 0x35
.long .LASF52
.byte 0x5
.uleb128 0x36
.long .LASF53
.byte 0x5
.uleb128 0x37
.long .LASF54
.byte 0x5
.uleb128 0x38
.long .LASF55
.byte 0x5
.uleb128 0x39
.long .LASF56
.byte 0x5
.uleb128 0x3a
.long .LASF57
.byte 0x5
.uleb128 0x3b
.long .LASF58
.byte 0x5
.uleb128 0x3c
.long .LASF59
.byte 0x5
.uleb128 0x3d
.long .LASF60
.byte 0x5
.uleb128 0x3e
.long .LASF61
.byte 0x5
.uleb128 0x3f
.long .LASF62
.byte 0x5
.uleb128 0x40
.long .LASF63
.byte 0x5
.uleb128 0x41
.long .LASF64
.byte 0x5
.uleb128 0x42
.long .LASF65
.byte 0x5
.uleb128 0x43
.long .LASF66
.byte 0x5
.uleb128 0x44
.long .LASF67
.byte 0x5
.uleb128 0x45
.long .LASF68
.byte 0x5
.uleb128 0x46
.long .LASF69
.byte 0x5
.uleb128 0x47
.long .LASF70
.byte 0x5
.uleb128 0x48
.long .LASF71
.byte 0x5
.uleb128 0x49
.long .LASF72
.byte 0x5
.uleb128 0x4a
.long .LASF73
.byte 0x5
.uleb128 0x4b
.long .LASF74
.byte 0x5
.uleb128 0x4c
.long .LASF75
.byte 0x5
.uleb128 0x4d
.long .LASF76
.byte 0x5
.uleb128 0x4e
.long .LASF77
.byte 0x5
.uleb128 0x4f
.long .LASF78
.byte 0x5
.uleb128 0x50
.long .LASF79
.byte 0x5
.uleb128 0x51
.long .LASF80
.byte 0x5
.uleb128 0x52
.long .LASF81
.byte 0x5
.uleb128 0x53
.long .LASF82
.byte 0x5
.uleb128 0x54
.long .LASF83
.byte 0x5
.uleb128 0x55
.long .LASF84
.byte 0x5
.uleb128 0x56
.long .LASF85
.byte 0x5
.uleb128 0x57
.long .LASF86
.byte 0x5
.uleb128 0x58
.long .LASF87
.byte 0x5
.uleb128 0x59
.long .LASF88
.byte 0x5
.uleb128 0x5a
.long .LASF89
.byte 0x5
.uleb128 0x5b
.long .LASF90
.byte 0x5
.uleb128 0x5c
.long .LASF91
.byte 0x5
.uleb128 0x5d
.long .LASF92
.byte 0x5
.uleb128 0x5e
.long .LASF93
.byte 0x5
.uleb128 0x5f
.long .LASF94
.byte 0x5
.uleb128 0x60
.long .LASF95
.byte 0x5
.uleb128 0x61
.long .LASF96
.byte 0x5
.uleb128 0x62
.long .LASF97
.byte 0x5
.uleb128 0x63
.long .LASF98
.byte 0x5
.uleb128 0x64
.long .LASF99
.byte 0x5
.uleb128 0x65
.long .LASF100
.byte 0x5
.uleb128 0x66
.long .LASF101
.byte 0x5
.uleb128 0x67
.long .LASF102
.byte 0x5
.uleb128 0x68
.long .LASF103
.byte 0x5
.uleb128 0x69
.long .LASF104
.byte 0x5
.uleb128 0x6a
.long .LASF105
.byte 0x5
.uleb128 0x6b
.long .LASF106
.byte 0x5
.uleb128 0x6c
.long .LASF107
.byte 0x5
.uleb128 0x6d
.long .LASF108
.byte 0x5
.uleb128 0x6e
.long .LASF109
.byte 0x5
.uleb128 0x6f
.long .LASF110
.byte 0x5
.uleb128 0x70
.long .LASF111
.byte 0x5
.uleb128 0x71
.long .LASF112
.byte 0x5
.uleb128 0x72
.long .LASF113
.byte 0x5
.uleb128 0x73
.long .LASF114
.byte 0x5
.uleb128 0x74
.long .LASF115
.byte 0x5
.uleb128 0x75
.long .LASF116
.byte 0x5
.uleb128 0x76
.long .LASF117
.byte 0x5
.uleb128 0x77
.long .LASF118
.byte 0x5
.uleb128 0x78
.long .LASF119
.byte 0x5
.uleb128 0x79
.long .LASF120
.byte 0x5
.uleb128 0x7a
.long .LASF121
.byte 0x5
.uleb128 0x7b
.long .LASF122
.byte 0x5
.uleb128 0x7c
.long .LASF123
.byte 0x5
.uleb128 0x7d
.long .LASF124
.byte 0x5
.uleb128 0x7e
.long .LASF125
.byte 0x5
.uleb128 0x7f
.long .LASF126
.byte 0x5
.uleb128 0x80
.long .LASF127
.byte 0x5
.uleb128 0x81
.long .LASF128
.byte 0x5
.uleb128 0x82
.long .LASF129
.byte 0x5
.uleb128 0x83
.long .LASF130
.byte 0x5
.uleb128 0x84
.long .LASF131
.byte 0x5
.uleb128 0x85
.long .LASF132
.byte 0x5
.uleb128 0x86
.long .LASF133
.byte 0x5
.uleb128 0x87
.long .LASF134
.byte 0x5
.uleb128 0x88
.long .LASF135
.byte 0x5
.uleb128 0x89
.long .LASF136
.byte 0x5
.uleb128 0x8a
.long .LASF137
.byte 0x5
.uleb128 0x8b
.long .LASF138
.byte 0x5
.uleb128 0x8c
.long .LASF139
.byte 0x5
.uleb128 0x8d
.long .LASF140
.byte 0x5
.uleb128 0x8e
.long .LASF141
.byte 0x5
.uleb128 0x8f
.long .LASF142
.byte 0x5
.uleb128 0x90
.long .LASF143
.byte 0x5
.uleb128 0x91
.long .LASF144
.byte 0x5
.uleb128 0x92
.long .LASF145
.byte 0x5
.uleb128 0x93
.long .LASF146
.byte 0x5
.uleb128 0x94
.long .LASF147
.byte 0x5
.uleb128 0x95
.long .LASF148
.byte 0x5
.uleb128 0x96
.long .LASF149
.byte 0x5
.uleb128 0x97
.long .LASF150
.byte 0x5
.uleb128 0x98
.long .LASF151
.byte 0x5
.uleb128 0x99
.long .LASF152
.byte 0x5
.uleb128 0x9a
.long .LASF153
.byte 0x5
.uleb128 0x9b
.long .LASF154
.byte 0x5
.uleb128 0x9c
.long .LASF155
.byte 0x5
.uleb128 0x9d
.long .LASF156
.byte 0x5
.uleb128 0x9e
.long .LASF157
.byte 0x5
.uleb128 0x9f
.long .LASF158
.byte 0x5
.uleb128 0xa0
.long .LASF159
.byte 0x5
.uleb128 0xa1
.long .LASF160
.byte 0x5
.uleb128 0xa2
.long .LASF161
.byte 0x5
.uleb128 0xa3
.long .LASF162
.byte 0x5
.uleb128 0xa4
.long .LASF163
.byte 0x5
.uleb128 0xa5
.long .LASF164
.byte 0x5
.uleb128 0xa6
.long .LASF165
.byte 0x5
.uleb128 0xa7
.long .LASF166
.byte 0x5
.uleb128 0xa8
.long .LASF167
.byte 0x5
.uleb128 0xa9
.long .LASF168
.byte 0x5
.uleb128 0xaa
.long .LASF169
.byte 0x5
.uleb128 0xab
.long .LASF170
.byte 0x5
.uleb128 0xac
.long .LASF171
.byte 0x5
.uleb128 0xad
.long .LASF172
.byte 0x5
.uleb128 0xae
.long .LASF173
.byte 0x5
.uleb128 0xaf
.long .LASF174
.byte 0x5
.uleb128 0xb0
.long .LASF175
.byte 0x5
.uleb128 0xb1
.long .LASF176
.byte 0x5
.uleb128 0xb2
.long .LASF177
.byte 0x5
.uleb128 0xb3
.long .LASF178
.byte 0x5
.uleb128 0xb4
.long .LASF179
.byte 0x5
.uleb128 0xb5
.long .LASF180
.byte 0x5
.uleb128 0xb6
.long .LASF181
.byte 0x5
.uleb128 0xb7
.long .LASF182
.byte 0x5
.uleb128 0xb8
.long .LASF183
.byte 0x5
.uleb128 0xb9
.long .LASF184
.byte 0x5
.uleb128 0xba
.long .LASF185
.byte 0x5
.uleb128 0xbb
.long .LASF186
.byte 0x5
.uleb128 0xbc
.long .LASF187
.byte 0x5
.uleb128 0xbd
.long .LASF188
.byte 0x5
.uleb128 0xbe
.long .LASF189
.byte 0x5
.uleb128 0xbf
.long .LASF190
.byte 0x5
.uleb128 0xc0
.long .LASF191
.byte 0x5
.uleb128 0xc1
.long .LASF192
.byte 0x5
.uleb128 0xc2
.long .LASF193
.byte 0x5
.uleb128 0xc3
.long .LASF194
.byte 0x5
.uleb128 0xc4
.long .LASF195
.byte 0x5
.uleb128 0xc5
.long .LASF196
.byte 0x5
.uleb128 0xc6
.long .LASF197
.byte 0x5
.uleb128 0xc7
.long .LASF198
.byte 0x5
.uleb128 0xc8
.long .LASF199
.byte 0x5
.uleb128 0xc9
.long .LASF200
.byte 0x5
.uleb128 0xca
.long .LASF201
.byte 0x5
.uleb128 0xcb
.long .LASF202
.byte 0x5
.uleb128 0xcc
.long .LASF203
.byte 0x5
.uleb128 0xcd
.long .LASF204
.byte 0x5
.uleb128 0xce
.long .LASF205
.byte 0x5
.uleb128 0xcf
.long .LASF206
.byte 0x5
.uleb128 0xd0
.long .LASF207
.byte 0x5
.uleb128 0xd1
.long .LASF208
.byte 0x5
.uleb128 0xd2
.long .LASF209
.byte 0x5
.uleb128 0xd3
.long .LASF210
.byte 0x5
.uleb128 0xd4
.long .LASF211
.byte 0x5
.uleb128 0xd5
.long .LASF212
.byte 0x5
.uleb128 0xd6
.long .LASF213
.byte 0x5
.uleb128 0xd7
.long .LASF214
.byte 0x5
.uleb128 0xd8
.long .LASF215
.byte 0x5
.uleb128 0xd9
.long .LASF216
.byte 0x5
.uleb128 0xda
.long .LASF217
.byte 0x5
.uleb128 0xdb
.long .LASF218
.byte 0x5
.uleb128 0xdc
.long .LASF219
.byte 0x5
.uleb128 0xdd
.long .LASF220
.byte 0x5
.uleb128 0xde
.long .LASF221
.byte 0x5
.uleb128 0xdf
.long .LASF222
.byte 0x5
.uleb128 0xe0
.long .LASF223
.byte 0x5
.uleb128 0xe1
.long .LASF224
.byte 0x5
.uleb128 0xe2
.long .LASF225
.byte 0x5
.uleb128 0xe3
.long .LASF226
.byte 0x5
.uleb128 0xe4
.long .LASF227
.byte 0x5
.uleb128 0xe5
.long .LASF228
.byte 0x5
.uleb128 0xe6
.long .LASF229
.byte 0x5
.uleb128 0xe7
.long .LASF230
.byte 0x5
.uleb128 0xe8
.long .LASF231
.byte 0x5
.uleb128 0xe9
.long .LASF232
.byte 0x5
.uleb128 0xea
.long .LASF233
.byte 0x5
.uleb128 0xeb
.long .LASF234
.byte 0x5
.uleb128 0xec
.long .LASF235
.byte 0x5
.uleb128 0xed
.long .LASF236
.byte 0x5
.uleb128 0xee
.long .LASF237
.byte 0x5
.uleb128 0xef
.long .LASF238
.byte 0x5
.uleb128 0xf0
.long .LASF239
.byte 0x5
.uleb128 0xf1
.long .LASF240
.byte 0x5
.uleb128 0xf2
.long .LASF241
.byte 0x5
.uleb128 0xf3
.long .LASF242
.byte 0x5
.uleb128 0xf4
.long .LASF243
.byte 0x5
.uleb128 0xf5
.long .LASF244
.byte 0x5
.uleb128 0xf6
.long .LASF245
.byte 0x5
.uleb128 0xf7
.long .LASF246
.byte 0x5
.uleb128 0xf8
.long .LASF247
.byte 0x5
.uleb128 0xf9
.long .LASF248
.byte 0x5
.uleb128 0xfa
.long .LASF249
.byte 0x5
.uleb128 0xfb
.long .LASF250
.byte 0x5
.uleb128 0xfc
.long .LASF251
.byte 0x5
.uleb128 0xfd
.long .LASF252
.byte 0x5
.uleb128 0xfe
.long .LASF253
.byte 0x5
.uleb128 0xff
.long .LASF254
.byte 0x5
.uleb128 0x100
.long .LASF255
.byte 0x5
.uleb128 0x101
.long .LASF256
.byte 0x5
.uleb128 0x102
.long .LASF257
.byte 0x5
.uleb128 0x103
.long .LASF258
.byte 0x5
.uleb128 0x104
.long .LASF259
.byte 0x5
.uleb128 0x105
.long .LASF260
.byte 0x5
.uleb128 0x106
.long .LASF261
.byte 0x5
.uleb128 0x107
.long .LASF262
.byte 0x5
.uleb128 0x108
.long .LASF263
.byte 0x5
.uleb128 0x109
.long .LASF264
.byte 0x5
.uleb128 0x10a
.long .LASF265
.byte 0x5
.uleb128 0x10b
.long .LASF266
.byte 0x5
.uleb128 0x10c
.long .LASF267
.byte 0x5
.uleb128 0x10d
.long .LASF268
.byte 0x5
.uleb128 0x10e
.long .LASF269
.byte 0x5
.uleb128 0x10f
.long .LASF270
.byte 0x5
.uleb128 0x110
.long .LASF271
.byte 0x5
.uleb128 0x111
.long .LASF272
.byte 0x5
.uleb128 0x112
.long .LASF273
.byte 0x5
.uleb128 0x113
.long .LASF274
.byte 0x5
.uleb128 0x114
.long .LASF275
.byte 0x5
.uleb128 0x115
.long .LASF276
.byte 0x5
.uleb128 0x116
.long .LASF277
.byte 0x5
.uleb128 0x117
.long .LASF278
.byte 0x5
.uleb128 0x118
.long .LASF279
.byte 0x5
.uleb128 0x119
.long .LASF280
.byte 0x5
.uleb128 0x11a
.long .LASF281
.byte 0x5
.uleb128 0x11b
.long .LASF282
.byte 0x5
.uleb128 0x11c
.long .LASF283
.byte 0x5
.uleb128 0x11d
.long .LASF284
.byte 0x5
.uleb128 0x11e
.long .LASF285
.byte 0x5
.uleb128 0x11f
.long .LASF286
.byte 0x5
.uleb128 0x120
.long .LASF287
.byte 0x5
.uleb128 0x121
.long .LASF288
.byte 0x5
.uleb128 0x122
.long .LASF289
.byte 0x5
.uleb128 0x123
.long .LASF290
.byte 0x5
.uleb128 0x124
.long .LASF291
.byte 0x5
.uleb128 0x125
.long .LASF292
.byte 0x5
.uleb128 0x126
.long .LASF293
.byte 0x5
.uleb128 0x127
.long .LASF294
.byte 0x5
.uleb128 0x128
.long .LASF295
.byte 0x5
.uleb128 0x129
.long .LASF296
.byte 0x5
.uleb128 0x12a
.long .LASF297
.byte 0x5
.uleb128 0x12b
.long .LASF298
.byte 0x5
.uleb128 0x12c
.long .LASF299
.byte 0x5
.uleb128 0x12d
.long .LASF300
.byte 0x5
.uleb128 0x12e
.long .LASF301
.byte 0x5
.uleb128 0x12f
.long .LASF302
.byte 0x5
.uleb128 0x130
.long .LASF303
.byte 0x5
.uleb128 0x131
.long .LASF304
.byte 0x5
.uleb128 0x132
.long .LASF305
.byte 0x5
.uleb128 0x133
.long .LASF306
.byte 0x5
.uleb128 0x134
.long .LASF307
.byte 0x5
.uleb128 0x135
.long .LASF308
.byte 0x5
.uleb128 0x136
.long .LASF309
.byte 0x5
.uleb128 0x137
.long .LASF310
.byte 0x5
.uleb128 0x138
.long .LASF311
.byte 0x5
.uleb128 0x139
.long .LASF312
.byte 0x5
.uleb128 0x13a
.long .LASF313
.byte 0x5
.uleb128 0x13b
.long .LASF314
.byte 0x5
.uleb128 0x13c
.long .LASF315
.byte 0x5
.uleb128 0x13d
.long .LASF316
.byte 0x5
.uleb128 0x13e
.long .LASF317
.byte 0x5
.uleb128 0x13f
.long .LASF318
.byte 0x5
.uleb128 0x140
.long .LASF319
.byte 0x5
.uleb128 0x141
.long .LASF320
.byte 0x5
.uleb128 0x142
.long .LASF321
.byte 0x5
.uleb128 0x143
.long .LASF322
.byte 0x5
.uleb128 0x144
.long .LASF323
.byte 0x5
.uleb128 0x145
.long .LASF324
.byte 0x5
.uleb128 0x146
.long .LASF325
.byte 0x5
.uleb128 0x147
.long .LASF326
.byte 0x5
.uleb128 0x148
.long .LASF327
.byte 0x5
.uleb128 0x149
.long .LASF328
.byte 0x5
.uleb128 0x14a
.long .LASF329
.byte 0x5
.uleb128 0x14b
.long .LASF330
.byte 0x5
.uleb128 0x14c
.long .LASF331
.byte 0x5
.uleb128 0x14d
.long .LASF332
.byte 0x5
.uleb128 0x14e
.long .LASF333
.byte 0x5
.uleb128 0x14f
.long .LASF334
.byte 0x5
.uleb128 0x150
.long .LASF335
.byte 0x5
.uleb128 0x151
.long .LASF336
.byte 0x5
.uleb128 0x152
.long .LASF337
.byte 0x5
.uleb128 0x153
.long .LASF338
.file 2 "/usr/include/stdc-predef.h"
.byte 0x3
.uleb128 0x1f
.uleb128 0x2
.byte 0x7
.long .Ldebug_macro2
.byte 0x4
.byte 0x4
.byte 0
.section .debug_macro,"G",%progbits,wm4.stdcpredef.h.19.8dc41bed5d9037ff9622e015fb5f0ce3,comdat
.Ldebug_macro2:
.short 0x4
.byte 0
.byte 0x5
.uleb128 0x13
.long .LASF339
.byte 0x5
.uleb128 0x26
.long .LASF340
.byte 0x5
.uleb128 0x2e
.long .LASF341
.byte 0x5
.uleb128 0x3a
.long .LASF342
.byte 0
.section .debug_line,"",%progbits
.Ldebug_line0:
.section .debug_str,"MS",%progbits,1
.LASF122:
.string "__UINT_LEAST8_MAX__ 0xff"
.LASF219:
.string "__FLT64_HAS_DENORM__ 1"
.LASF250:
.string "__FLT64X_MANT_DIG__ 64"
.LASF2:
.string "__STDC_UTF_16__ 1"
.LASF252:
.string "__FLT64X_MIN_EXP__ (-16381)"
.LASF126:
.string "__UINT_LEAST32_MAX__ 0xffffffffU"
.LASF160:
.string "__FLT_EPSILON__ 1.19209289550781250000000000000000000e-7F"
.LASF8:
.string "__VERSION__ \"9.2.1 20190827 (Red Hat 9.2.1-1)\""
.LASF247:
.string "__FLT32X_HAS_DENORM__ 1"
.LASF334:
.string "__unix 1"
.LASF70:
.string "__UINTPTR_TYPE__ long unsigned int"
.LASF35:
.string "__SIZEOF_POINTER__ 8"
.LASF90:
.string "__WCHAR_WIDTH__ 32"
.LASF279:
.string "__DEC128_MIN_EXP__ (-6142)"
.LASF271:
.string "__DEC64_MANT_DIG__ 16"
.LASF272:
.string "__DEC64_MIN_EXP__ (-382)"
.LASF173:
.string "__DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L)"
.LASF141:
.string "__UINT_FAST64_MAX__ 0xffffffffffffffffUL"
.LASF335:
.string "__unix__ 1"
.LASF240:
.string "__FLT32X_MAX_EXP__ 1024"
.LASF184:
.string "__LDBL_MAX_10_EXP__ 4932"
.LASF267:
.string "__DEC32_MIN__ 1E-95DF"
.LASF215:
.string "__FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64"
.LASF249:
.string "__FLT32X_HAS_QUIET_NAN__ 1"
.LASF265:
.string "__DEC32_MIN_EXP__ (-94)"
.LASF234:
.string "__FLT128_HAS_INFINITY__ 1"
.LASF170:
.string "__DBL_MAX_10_EXP__ 308"
.LASF216:
.string "__FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64"
.LASF310:
.string "__amd64 1"
.LASF188:
.string "__LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L"
.LASF118:
.string "__INT_LEAST32_WIDTH__ 32"
.LASF144:
.string "__UINTPTR_MAX__ 0xffffffffffffffffUL"
.LASF19:
.string "__LP64__ 1"
.LASF129:
.string "__UINT64_C(c) c ## UL"
.LASF177:
.string "__DBL_HAS_INFINITY__ 1"
.LASF1:
.string "__STDC_VERSION__ 201710L"
.LASF321:
.string "__code_model_small__ 1"
.LASF239:
.string "__FLT32X_MIN_10_EXP__ (-307)"
.LASF117:
.string "__INT32_C(c) c"
.LASF245:
.string "__FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32x"
.LASF7:
.string "__GNUC_PATCHLEVEL__ 1"
.LASF261:
.string "__FLT64X_HAS_DENORM__ 1"
.LASF143:
.string "__INTPTR_WIDTH__ 64"
.LASF4:
.string "__STDC_HOSTED__ 1"
.LASF82:
.string "__WINT_MIN__ 0U"
.LASF148:
.string "__FLT_EVAL_METHOD_TS_18661_3__ 0"
.LASF190:
.string "__LDBL_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951L"
.LASF174:
.string "__DBL_EPSILON__ ((double)2.22044604925031308084726333618164062e-16L)"
.LASF253:
.string "__FLT64X_MIN_10_EXP__ (-4931)"
.LASF296:
.string "__GCC_ATOMIC_WCHAR_T_LOCK_FREE 2"
.LASF51:
.string "__UINT32_TYPE__ unsigned int"
.LASF325:
.string "__FXSR__ 1"
.LASF221:
.string "__FLT64_HAS_QUIET_NAN__ 1"
.LASF277:
.string "__DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD"
.LASF85:
.string "__SCHAR_WIDTH__ 8"
.LASF189:
.string "__LDBL_EPSILON__ 1.08420217248550443400745280086994171e-19L"
.LASF165:
.string "__DBL_MANT_DIG__ 53"
.LASF203:
.string "__FLT32_EPSILON__ 1.19209289550781250000000000000000000e-7F32"
.LASF204:
.string "__FLT32_DENORM_MIN__ 1.40129846432481707092372958328991613e-45F32"
.LASF130:
.string "__INT_FAST8_MAX__ 0x7f"
.LASF178:
.string "__DBL_HAS_QUIET_NAN__ 1"
.LASF217:
.string "__FLT64_EPSILON__ 2.22044604925031308084726333618164062e-16F64"
.LASF86:
.string "__SHRT_WIDTH__ 16"
.LASF266:
.string "__DEC32_MAX_EXP__ 97"
.LASF47:
.string "__INT32_TYPE__ int"
.LASF44:
.string "__SIG_ATOMIC_TYPE__ int"
.LASF273:
.string "__DEC64_MAX_EXP__ 385"
.LASF167:
.string "__DBL_MIN_EXP__ (-1021)"
.LASF18:
.string "_LP64 1"
.LASF115:
.string "__INT_LEAST16_WIDTH__ 16"
.LASF192:
.string "__LDBL_HAS_INFINITY__ 1"
.LASF64:
.string "__INT_FAST64_TYPE__ long int"
.LASF162:
.string "__FLT_HAS_DENORM__ 1"
.LASF224:
.string "__FLT128_MIN_EXP__ (-16381)"
.LASF231:
.string "__FLT128_EPSILON__ 1.92592994438723585305597794258492732e-34F128"
.LASF107:
.string "__UINT16_MAX__ 0xffff"
.LASF263:
.string "__FLT64X_HAS_QUIET_NAN__ 1"
.LASF68:
.string "__UINT_FAST64_TYPE__ long unsigned int"
.LASF33:
.string "__BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__"
.LASF309:
.string "__SIZEOF_PTRDIFF_T__ 8"
.LASF238:
.string "__FLT32X_MIN_EXP__ (-1021)"
.LASF34:
.string "__FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__"
.LASF124:
.string "__UINT_LEAST16_MAX__ 0xffff"
.LASF345:
.string "GNU C17 9.2.1 20190827 (Red Hat 9.2.1-1) -mtune=generic -march=x86-64 -g3 -gdwarf-4 -O1 -ffunction-sections -fdata-sections -fno-common"
.LASF305:
.string "__PRAGMA_REDEFINE_EXTNAME 1"
.LASF54:
.string "__INT_LEAST16_TYPE__ short int"
.LASF207:
.string "__FLT32_HAS_QUIET_NAN__ 1"
.LASF185:
.string "__DECIMAL_DIG__ 21"
.LASF72:
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|
tactcomplabs/xbgas-binutils-gdb | 4,440 | binutils/testsuite/binutils-all/dw2-ranges.S | /* Copyright (C) 2015-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This tests makes use of the .debug_ranges section, especially,
making sure that the base address encoding scheme is used. */
/* Dummy function to provide debug information for. */
.text
.globl _start
_start:
.4byte 0
.Lbegin_text1:
.globl func_cu1
.type func_cu1, %function
func_cu1:
.Lbegin_func_cu1:
.4byte 0
.Lend_func_cu1:
.size func_cu1, .-func_cu1
.Lend_text1:
.Lbegin_text2:
.globl func_cu2
.type func_cu2, %function
func_cu2:
.Lbegin_func_cu2:
.4byte 0
.Lend_func_cu2:
.size func_cu2, .-func_cu2
.Lend_text2:
/* Debug information */
.section .debug_info
.Lcu1_begin:
/* CU header */
.4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */
.Lcu1_start:
.2byte 2 /* DWARF Version */
.4byte .Labbrev1_begin /* Offset into abbrev section */
.byte 4 /* Pointer size */
/* CU die */
.uleb128 1 /* Abbrev: DW_TAG_compile_unit */
.4byte .Lrange1_begin
.ascii "file1.c\0" /* DW_AT_name */
.byte 1 /* DW_AT_language (C) */
/* func_cu1 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.ascii "func_cu1\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func_cu1 /* DW_AT_low_pc */
.4byte .Lend_func_cu1 /* DW_AT_high_pc */
/* func_cu1 */
.uleb128 2 /* Abbrev: DW_TAG_subprogram */
.ascii "func_cu2\0" /* DW_AT_name */
.4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */
.4byte .Lbegin_func_cu2 /* DW_AT_low_pc */
.4byte .Lend_func_cu2 /* DW_AT_high_pc */
.Ltype_int:
.uleb128 3 /* Abbrev: DW_TAG_base_type */
.ascii "int\0" /* DW_AT_name */
.byte 4 /* DW_AT_byte_size */
.byte 5 /* DW_AT_encoding */
.byte 0 /* End of children of CU */
.Lcu1_end:
.section .debug_ranges
.Lrange1_begin:
.4byte 0xffffffff /* base address marker */
.4byte .Lbegin_text1 /* base address */
.4byte 0 /* start offset */
.4byte .Lend_text1 - .Lbegin_text1 /* end offset */
.4byte 0xffffffff /* base address marker */
.4byte .Lbegin_text2 /* base address */
.4byte 0 /* start offset */
.4byte .Lend_text2 - .Lbegin_text2 /* end offset */
.4byte 0 /* End marker (Part 1) */
.4byte 0 /* End marker (Part 2) */
.section .debug_abbrev
.Labbrev1_begin:
.uleb128 1 /* Abbrev code */
.uleb128 0x11 /* DW_TAG_compile_unit */
.byte 1 /* has_children */
.uleb128 0x55 /* DW_AT_ranges */
.uleb128 0x17 /* DW_FORM_sec_offset */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x13 /* DW_AT_language */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 2 /* Abbrev code */
.uleb128 0x2e /* DW_TAG_subprogram */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0x49 /* DW_AT_type */
.uleb128 0x13 /* DW_FORM_ref4 */
.uleb128 0x11 /* DW_AT_low_pc */
.uleb128 0x1 /* DW_FORM_addr */
.uleb128 0x12 /* DW_AT_high_pc */
.uleb128 0x1 /* DW_FORM_addr */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.uleb128 3 /* Abbrev code */
.uleb128 0x24 /* DW_TAG_base_type */
.byte 0 /* has_children */
.uleb128 0x3 /* DW_AT_name */
.uleb128 0x8 /* DW_FORM_string */
.uleb128 0xb /* DW_AT_byte_size */
.uleb128 0xb /* DW_FORM_data1 */
.uleb128 0x3e /* DW_AT_encoding */
.uleb128 0xb /* DW_FORM_data1 */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
.byte 0x0 /* Terminator */
|
tactcomplabs/xbgas-binutils-gdb | 1,299 | binutils/testsuite/binutils-all/riscv/unknown.s | /* Copyright (C) 2021-2022 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
.text
/* The following instruction is in the area set aside for
custom instruction extensions. As such it is unlikely that
an upstream extension should ever clash with this. */
.insn r 0x0b, 0x0, 0x0, x3, x4, x5
/* Unlike the above, the following is just a reserved
instruction encoding. This means that in the future an
extension to the compressed instruction set might use this
encoding. If/when that happens we'll need to find a
different unused encoding within the compressed instruction
space. */
.insn ca 0x1, 0x27, 0x2, x8, x9
|
tactcomplabs/xbgas-binutils-gdb | 2,178 | binutils/testsuite/binutils-all/i386/compressed-1.s | .file "compressed-1.c"
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.cfi_sections .debug_frame
.p2align 4,,15
.globl foo2
.type foo2, @function
foo2:
.LFB1:
.file 1 "compressed-1.c"
.loc 1 11 0
.cfi_startproc
.loc 1 12 0
rep
ret
.cfi_endproc
.LFE1:
.size foo2, .-foo2
.p2align 4,,15
.globl foo1
.type foo1, @function
foo1:
.LFB0:
.loc 1 5 0
.cfi_startproc
subl $12, %esp
.cfi_def_cfa_offset 16
.loc 1 7 0
addl $12, %esp
.cfi_def_cfa_offset 4
.loc 1 6 0
jmp bar
.cfi_endproc
.LFE0:
.size foo1, .-foo1
.Letext0:
.section .debug_info
.long 0x46
.value 0x3
.long .Ldebug_abbrev0
.byte 0x4
.uleb128 0x1
.long .LASF2
.byte 0x1
.long .LASF3
.long .LASF4
.long .Ltext0
.long .Letext0
.long .Ldebug_line0
.uleb128 0x2
.byte 0x1
.long .LASF0
.byte 0x1
.byte 0xa
.long .LFB1
.long .LFE1
.byte 0x1
.byte 0x9c
.uleb128 0x2
.byte 0x1
.long .LASF1
.byte 0x1
.byte 0x4
.long .LFB0
.long .LFE0
.byte 0x1
.byte 0x9c
.byte 0x0
.section .debug_abbrev
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x10
.uleb128 0x6
.byte 0x0
.byte 0x0
.uleb128 0x2
.uleb128 0x2e
.byte 0x0
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0xa
.byte 0x0
.byte 0x0
.byte 0x0
.section .debug_pubnames,"",@progbits
.long 0x20
.value 0x2
.long .Ldebug_info0
.long 0x4a
.long 0x25
.string "foo2"
.long 0x37
.string "foo1"
.long 0x0
.section .debug_aranges,"",@progbits
.long 0x1c
.value 0x2
.long .Ldebug_info0
.byte 0x4
.byte 0x0
.value 0x0
.value 0x0
.long .Ltext0
.long .Letext0-.Ltext0
.long 0x0
.long 0x0
.section .debug_str,"MS",@progbits,1
.LASF2:
.string "GNU C 4.4.4"
.LASF0:
.string "foo2"
.LASF1:
.string "foo1"
.LASF4:
.string "."
.LASF3:
.string "compressed-1.c"
|
tactcomplabs/xbgas-binutils-gdb | 9,273 | binutils/testsuite/binutils-all/mips/mips16-extend-insn.s | .set mips16
.set noreorder
foo:
extend 0x123 # ADDIUSP
addiu $16, $29, 0
extend 0x123
addiu $16, $29, 128
extend 0x123
addiu $16, $29, 256
extend 0x123
addiu $16, $29, 384
extend 0x123
addiu $16, $29, 512
extend 0x123
addiu $16, $29, 640
extend 0x123
addiu $16, $29, 768
extend 0x123
addiu $16, $29, 896
extend 0x123 # ADDIUPC
addiu $16, $pc, 0
extend 0x123
addiu $16, $pc, 128
extend 0x123
addiu $16, $pc, 256
extend 0x123
addiu $16, $pc, 384
extend 0x123
addiu $16, $pc, 512
extend 0x123
addiu $16, $pc, 640
extend 0x123
addiu $16, $pc, 768
extend 0x123
addiu $16, $pc, 896
extend 0x123 # B
b . + 2
extend 0x123
b . + 66
extend 0x123
b . + 130
extend 0x123
b . + 194
extend 0x123
b . + 258
extend 0x123
b . + 322
extend 0x123
b . + 386
extend 0x123
b . + 450
extend 0x123 # BEQZ
beqz $16, . + 2
extend 0x123
beqz $16, . + 66
extend 0x123
beqz $16, . + 130
extend 0x123
beqz $16, . + 194
extend 0x123
beqz $16, . - 254
extend 0x123
beqz $16, . - 190
extend 0x123
beqz $16, . - 126
extend 0x123
beqz $16, . - 62
extend 0x123 # BNEZ
bnez $16, . + 2
extend 0x123
bnez $16, . + 66
extend 0x123
bnez $16, . + 130
extend 0x123
bnez $16, . + 194
extend 0x123
bnez $16, . - 254
extend 0x123
bnez $16, . - 190
extend 0x123
bnez $16, . - 126
extend 0x123
bnez $16, . - 62
extend 0x123 # SHIFT # SLL
sll $16, $16, 8
extend 0x123
sll $16, $16, 1
extend 0x123
sll $16, $16, 2
extend 0x123
sll $16, $16, 3
extend 0x123
sll $16, $16, 4
extend 0x123
sll $16, $16, 5
extend 0x123
sll $16, $16, 6
extend 0x123
sll $16, $16, 7
extend 0x123 # DSLL
dsll $16, $16, 8
extend 0x123
dsll $16, $16, 1
extend 0x123
dsll $16, $16, 2
extend 0x123
dsll $16, $16, 3
extend 0x123
dsll $16, $16, 4
extend 0x123
dsll $16, $16, 5
extend 0x123
dsll $16, $16, 6
extend 0x123
dsll $16, $16, 7
extend 0x123 # SRL
srl $16, $16, 8
extend 0x123
srl $16, $16, 1
extend 0x123
srl $16, $16, 2
extend 0x123
srl $16, $16, 3
extend 0x123
srl $16, $16, 4
extend 0x123
srl $16, $16, 5
extend 0x123
srl $16, $16, 6
extend 0x123
srl $16, $16, 7
extend 0x123 # SRA
sra $16, $16, 8
extend 0x123
sra $16, $16, 1
extend 0x123
sra $16, $16, 2
extend 0x123
sra $16, $16, 3
extend 0x123
sra $16, $16, 4
extend 0x123
sra $16, $16, 5
extend 0x123
sra $16, $16, 6
extend 0x123
sra $16, $16, 7
extend 0x123 # LD
ld $16, 0($16)
extend 0x123 # RRI-A # ADDIU
addiu $16, $16, 0
extend 0x123 # DADDIU
daddiu $16, $16, 0
extend 0x123 # ADDIU8
addiu $16, 0
extend 0x123
addiu $16, 32
extend 0x123
addiu $16, 64
extend 0x123
addiu $16, 96
extend 0x123
addiu $16, -128
extend 0x123
addiu $16, -96
extend 0x123
addiu $16, -64
extend 0x123
addiu $16, -32
extend 0x123 # SLTI
slti $16, 0
extend 0x123
slti $16, 32
extend 0x123
slti $16, 64
extend 0x123
slti $16, 96
extend 0x123
slti $16, 128
extend 0x123
slti $16, 160
extend 0x123
slti $16, 192
extend 0x123
slti $16, 224
extend 0x123 # SLTIU
sltiu $16, 0
extend 0x123
sltiu $16, 32
extend 0x123
sltiu $16, 64
extend 0x123
sltiu $16, 96
extend 0x123
sltiu $16, 128
extend 0x123
sltiu $16, 160
extend 0x123
sltiu $16, 192
extend 0x123
sltiu $16, 224
extend 0x123 # I8 # BTEQZ
bteqz . + 2
extend 0x123
bteqz . + 66
extend 0x123
bteqz . + 130
extend 0x123
bteqz . + 194
extend 0x123
bteqz . - 254
extend 0x123
bteqz . - 190
extend 0x123
bteqz . - 126
extend 0x123
bteqz . - 62
extend 0x123 # BTNEZ
btnez . + 2
extend 0x123
btnez . + 66
extend 0x123
btnez . + 130
extend 0x123
btnez . + 194
extend 0x123
btnez . - 254
extend 0x123
btnez . - 190
extend 0x123
btnez . - 126
extend 0x123
btnez . - 62
extend 0x123 # SWRASP
sw $31, 0($29)
extend 0x123
sw $31, 128($29)
extend 0x123
sw $31, 256($29)
extend 0x123
sw $31, 512($29)
extend 0x123
sw $31, 640($29)
extend 0x123
sw $31, 768($29)
extend 0x123
sw $31, 896($29)
extend 0x123
sw $31, 0($29)
extend 0x123 # ADJSP
addiu $29, 0
extend 0x123
addiu $29, 256
extend 0x123
addiu $29, 512
extend 0x123
addiu $29, 768
extend 0x123
addiu $29, -1024
extend 0x123
addiu $29, -768
extend 0x123
addiu $29, -512
extend 0x123
addiu $29, -256
extend 0x123 # SVRS # RESTORE
restore 128
extend 0x123 # SAVE
save 128
extend 0x123 # MOV32R
move $0, $16
extend 0x123
move $0, $17
extend 0x123 # MOVR32
move $16, $0
extend 0x123 # LI
li $16, 0
extend 0x123
li $16, 32
extend 0x123
li $16, 64
extend 0x123
li $16, 96
extend 0x123
li $16, 128
extend 0x123
li $16, 160
extend 0x123
li $16, 192
extend 0x123
li $16, 224
extend 0x123 # CMPI
cmpi $16, 0
extend 0x123
cmpi $16, 32
extend 0x123
cmpi $16, 64
extend 0x123
cmpi $16, 96
extend 0x123
cmpi $16, 128
extend 0x123
cmpi $16, 160
extend 0x123
cmpi $16, 192
extend 0x123
cmpi $16, 224
extend 0x123 # SD
sd $16, 0($16)
extend 0x123 # LB
lb $16, 0($16)
extend 0x123 # LH
lh $16, 0($16)
extend 0x123 # LWSP
lw $16, 0($29)
extend 0x123
lw $16, 128($29)
extend 0x123
lw $16, 256($29)
extend 0x123
lw $16, 384($29)
extend 0x123
lw $16, 512($29)
extend 0x123
lw $16, 640($29)
extend 0x123
lw $16, 768($29)
extend 0x123
lw $16, 896($29)
extend 0x123 # LW
lw $16, 0($16)
extend 0x123 # LBU
lbu $16, 0($16)
extend 0x123 # LHU
lhu $16, 0($16)
extend 0x123 # LWPC
lw $16, 0($pc)
extend 0x123
lw $16, 128($pc)
extend 0x123
lw $16, 256($pc)
extend 0x123
lw $16, 384($pc)
extend 0x123
lw $16, 512($pc)
extend 0x123
lw $16, 640($pc)
extend 0x123
lw $16, 768($pc)
extend 0x123
lw $16, 896($pc)
extend 0x123 # LWU
lwu $16, 0($16)
extend 0x123 # SB
sb $16, 0($16)
extend 0x123 # SH
sh $16, 0($16)
extend 0x123 # SWSP
sw $16, 0($29)
extend 0x123
sw $16, 128($29)
extend 0x123
sw $16, 256($29)
extend 0x123
sw $16, 384($29)
extend 0x123
sw $16, 512($29)
extend 0x123
sw $16, 640($29)
extend 0x123
sw $16, 768($29)
extend 0x123
sw $16, 896($29)
extend 0x123 # SW
sw $16, 0($16)
extend 0x123 # RRR # DADDU
daddu $16, $16, $16
extend 0x123 # ADDU
addu $16, $16, $16
extend 0x123 # DSUBU
dsubu $16, $16, $16
extend 0x123 # SUBU
subu $16, $16, $16
extend 0x123 # RR # J(AL)R(C) # JR rx
jr $16
extend 0x123 # JR ra
jr $31
extend 0x123 # JALR
jalr $16
extend 0x123 # JRC rx
jrc $16
extend 0x123 # JRC ra
jrc $31
extend 0x123 # JALRC
jalrc $16
extend 0x123 # SDBBP
sdbbp 0
extend 0x123 # SLT
slt $16, $16
extend 0x123 # SLTU
sltu $16, $16
extend 0x123 # SLLV
sllv $16, $16
extend 0x123 # BREAK
break 0
extend 0x123 # SRLV
srlv $16, $16
extend 0x123 # SRAV
srav $16, $16
extend 0x123 # DSRL
dsrl $16, 8
extend 0x123
dsrl $16, 1
extend 0x123
dsrl $16, 2
extend 0x123
dsrl $16, 3
extend 0x123
dsrl $16, 4
extend 0x123
dsrl $16, 5
extend 0x123
dsrl $16, 6
extend 0x123
dsrl $16, 7
extend 0x123 # ENTRY/EXIT
entry
extend 0x123
entry $31
extend 0x123
exit $f0
extend 0x123
exit $f0-$f1
extend 0x123
exit
extend 0x123 # CMP
cmp $16, $16
extend 0x123 # NEG
neg $16, $16
extend 0x123 # AND
and $16, $16
extend 0x123 # OR
or $16, $16
extend 0x123 # XOR
xor $16, $16
extend 0x123 # NOT
not $16, $16
extend 0x123 # MFHI
mfhi $16
extend 0x123 # CNVT # ZEB
zeb $16
extend 0x123 # ZEH
zeh $16
extend 0x123 # ZEW
zew $16
extend 0x123 # SEB
seb $16
extend 0x123 # SEH
seh $16
extend 0x123 # SEW
sew $16
extend 0x123 # MFLO
mflo $16
extend 0x123 # DSRA
dsra $16, 8
extend 0x123
dsra $16, 1
extend 0x123
dsra $16, 2
extend 0x123
dsra $16, 3
extend 0x123
dsra $16, 4
extend 0x123
dsra $16, 5
extend 0x123
dsra $16, 6
extend 0x123
dsra $16, 7
extend 0x123 # DSLLV
dsllv $16, $16
extend 0x123 # DSRLV
dsrlv $16, $16
extend 0x123 # DSRAV
dsrav $16, $16
extend 0x123 # MULT
mult $16, $16
extend 0x123 # MULTU
multu $16, $16
extend 0x123 # DIV
div $0, $16, $16
extend 0x123 # DIVU
divu $0, $16, $16
extend 0x123 # DMULT
dmult $16, $16
extend 0x123 # DMULTU
dmultu $16, $16
extend 0x123 # DDIV
ddiv $0, $16, $16
extend 0x123 # DDIVU
ddivu $0, $16, $16
extend 0x123 # EXTEND
extend 0
extend 0x123 # I64 # LDSP
ld $16, 0($29)
extend 0x123 # SDSP
sd $16, 0($29)
extend 0x123 # SDRASP
sd $31, 0($29)
extend 0x123
sd $31, 256($29)
extend 0x123
sd $31, 512($29)
extend 0x123
sd $31, 768($29)
extend 0x123
sd $31, 1024($29)
extend 0x123
sd $31, 1280($29)
extend 0x123
sd $31, 1536($29)
extend 0x123
sd $31, 1792($29)
extend 0x123 # DADJSP
daddiu $29, 0
extend 0x123
daddiu $29, 256
extend 0x123
daddiu $29, 512
extend 0x123
daddiu $29, 768
extend 0x123
daddiu $29, -1024
extend 0x123
daddiu $29, -768
extend 0x123
daddiu $29, -512
extend 0x123
daddiu $29, -256
extend 0x123 # LDPC
ld $16, 0($pc)
extend 0x123 # DADDIU5
daddiu $16, 0
extend 0x123 # DADDIUPC
daddiu $16, $pc, 0
extend 0x123 # DADDIUSP
daddiu $16, $sp, 0
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb | 3,702 | binutils/testsuite/binutils-all/mips/mips16-undecoded.s | .text
.set mips16
.globl foo
.ent foo
foo:
# Individual major opcodes.
addiu $2, $sp, 0x4011
.half 0xf008, 0x0211
.half 0xf008, 0x0231
.half 0xf008, 0x0251
.half 0xf008, 0x0291
addiu $2, $pc, 0x4011
.half 0xf008, 0x0a11
.half 0xf008, 0x0a31
.half 0xf008, 0x0a51
.half 0xf008, 0x0a91
b . + 0x8026
.half 0xf008, 0x1011
.half 0xf008, 0x1031
.half 0xf008, 0x1051
.half 0xf008, 0x1091
.half 0xf008, 0x1111
.half 0xf008, 0x1211
.half 0xf008, 0x1411
beqz $2, . + 0x8026
.half 0xf008, 0x2211
.half 0xf008, 0x2231
.half 0xf008, 0x2251
.half 0xf008, 0x2291
bnez $2, . + 0x8026
.half 0xf008, 0x2a11
.half 0xf008, 0x2a31
.half 0xf008, 0x2a51
.half 0xf008, 0x2a91
addiu $2, 0x4011
.half 0xf008, 0x4a11
.half 0xf008, 0x4a31
.half 0xf008, 0x4a51
.half 0xf008, 0x4a91
slti $2, 0x4011
.half 0xf008, 0x5211
.half 0xf008, 0x5231
.half 0xf008, 0x5251
.half 0xf008, 0x5291
sltiu $2, 0x4011
.half 0xf008, 0x5a11
.half 0xf008, 0x5a31
.half 0xf008, 0x5a51
.half 0xf008, 0x5a91
li $2, 0x4011
.half 0xf008, 0x6a11
.half 0xf008, 0x6a31
.half 0xf008, 0x6a51
.half 0xf008, 0x6a91
cmpi $2, 0x4011
.half 0xf008, 0x7211
.half 0xf008, 0x7231
.half 0xf008, 0x7251
.half 0xf008, 0x7291
lw $2, 0x4011($sp)
.half 0xf008, 0x9211
.half 0xf008, 0x9231
.half 0xf008, 0x9251
.half 0xf008, 0x9291
lw $2, 0x4011($pc)
.half 0xf008, 0xb211
.half 0xf008, 0xb231
.half 0xf008, 0xb251
.half 0xf008, 0xb291
sw $2, 0x4011($sp)
.half 0xf008, 0xd211
.half 0xf008, 0xd231
.half 0xf008, 0xd251
.half 0xf008, 0xd291
# I8 major opcode.
bteqz . + 0x8026
.half 0xf008, 0x6011
.half 0xf008, 0x6031
.half 0xf008, 0x6051
.half 0xf008, 0x6091
btnez . + 0x8026
.half 0xf008, 0x6111
.half 0xf008, 0x6131
.half 0xf008, 0x6151
.half 0xf008, 0x6191
sw $ra, 0x4011($sp)
.half 0xf008, 0x6211
.half 0xf008, 0x6231
.half 0xf008, 0x6251
.half 0xf008, 0x6291
addiu $sp, 0x4011
.half 0xf008, 0x6311
.half 0xf008, 0x6331
.half 0xf008, 0x6351
.half 0xf008, 0x6391
# SHIFT major opcode
sll $2, $3, 0x14
.half 0xf500, 0x3260
.half 0xf500, 0x3264
.half 0xf500, 0x3268
.half 0xf500, 0x3270
.half 0xf501, 0x3260
.half 0xf502, 0x3260
.half 0xf504, 0x3260
.half 0xf508, 0x3260
.half 0xf510, 0x3260
.half 0xf520, 0x3260
dsll $2, $3, 0x14
.half 0xf500, 0x3261
.half 0xf500, 0x3265
.half 0xf500, 0x3269
.half 0xf500, 0x3271
.half 0xf501, 0x3261
.half 0xf502, 0x3261
.half 0xf504, 0x3261
.half 0xf508, 0x3261
.half 0xf510, 0x3261
.half 0xf520, 0x3261
srl $2, $3, 0x14
.half 0xf500, 0x3262
.half 0xf500, 0x3266
.half 0xf500, 0x326a
.half 0xf500, 0x3272
.half 0xf501, 0x3262
.half 0xf502, 0x3262
.half 0xf504, 0x3262
.half 0xf508, 0x3262
.half 0xf510, 0x3262
.half 0xf520, 0x3262
sra $2, $3, 0x14
.half 0xf500, 0x3263
.half 0xf500, 0x3267
.half 0xf500, 0x326b
.half 0xf500, 0x3273
.half 0xf501, 0x3263
.half 0xf502, 0x3263
.half 0xf504, 0x3263
.half 0xf508, 0x3263
.half 0xf510, 0x3263
.half 0xf520, 0x3263
# RR major opcode
dsrl $2, 0x14
.half 0xf500, 0xe848
.half 0xf500, 0xe948
.half 0xf500, 0xea48
.half 0xf500, 0xec48
.half 0xf501, 0xe848
.half 0xf502, 0xe848
.half 0xf504, 0xe848
.half 0xf508, 0xe848
.half 0xf510, 0xe848
.half 0xf520, 0xe848
dsra $2, 0x14
.half 0xf500, 0xe853
.half 0xf500, 0xe953
.half 0xf500, 0xea53
.half 0xf500, 0xec53
.half 0xf501, 0xe853
.half 0xf502, 0xe853
.half 0xf504, 0xe853
.half 0xf508, 0xe853
.half 0xf510, 0xe853
.half 0xf520, 0xe853
# I64 major opcode.
daddiu $sp, 0x4011
.half 0xf008, 0xfb11
.half 0xf008, 0xfb31
.half 0xf008, 0xfb51
.half 0xf008, 0xfb91
.end foo
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
|
tactcomplabs/xbgas-binutils-gdb | 2,182 | binutils/testsuite/binutils-all/mips/mips16-pcrel.s | .module mips64
.set mips16
.set noreorder
.set noautoextend
.align 12, 0
foo0:
nop
nop
addiu $2, $pc, 0x3fc
nop
nop
nop
lw $3, 0x3fc($pc)
nop
nop
nop
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
nop
ld $5, 0xf8($pc)
.align 12, 0
foo1:
jal bar0
addiu $2, $pc, 0x3fc
nop
jal bar0
lw $3, 0x3fc($pc)
nop
jal bar0
daddiu $4, $pc, 0x7c
nop
nop
nop
jal bar0
ld $5, 0xf8($pc)
.align 12, 0
foo2:
jalx bar1
addiu $2, $pc, 0x3fc
nop
jalx bar1
lw $3, 0x3fc($pc)
nop
jalx bar1
daddiu $4, $pc, 0x7c
nop
nop
nop
jalx bar1
ld $5, 0xf8($pc)
.align 12, 0
foo3:
nop
jr $16
addiu $2, $pc, 0x3fc
nop
nop
jr $16
lw $3, 0x3fc($pc)
nop
nop
jr $16
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
jr $16
ld $5, 0xf8($pc)
.align 12, 0
foo4:
nop
jr $31
addiu $2, $pc, 0x3fc
nop
nop
jr $31
lw $3, 0x3fc($pc)
nop
nop
jr $31
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
jr $31
ld $5, 0xf8($pc)
.align 12, 0
foo5:
nop
jalr $16
addiu $2, $pc, 0x3fc
nop
nop
jalr $16
lw $3, 0x3fc($pc)
nop
nop
jalr $16
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
jalr $16
ld $5, 0xf8($pc)
.align 12, 0
foo6:
nop
.half 0xe860
addiu $2, $pc, 0x3fc
nop
nop
.half 0xe860
lw $3, 0x3fc($pc)
nop
nop
.half 0xe860
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
.half 0xe860
ld $5, 0xf8($pc)
.align 12, 0
foo7:
nop
jrc $16
addiu $2, $pc, 0x3fc
nop
nop
jrc $16
lw $3, 0x3fc($pc)
nop
nop
jrc $16
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
jrc $16
ld $5, 0xf8($pc)
.align 12, 0
foo8:
nop
jrc $31
addiu $2, $pc, 0x3fc
nop
nop
jrc $31
lw $3, 0x3fc($pc)
nop
nop
jrc $31
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
jrc $31
ld $5, 0xf8($pc)
.align 12, 0
foo9:
nop
jalrc $16
addiu $2, $pc, 0x3fc
nop
nop
jalrc $16
lw $3, 0x3fc($pc)
nop
nop
jalrc $16
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
jalrc $16
ld $5, 0xf8($pc)
.align 12, 0
fooa:
nop
.half 0xe960
addiu $2, $pc, 0x3fc
nop
nop
.half 0xe960
lw $3, 0x3fc($pc)
nop
nop
.half 0xe960
daddiu $4, $pc, 0x7c
nop
nop
nop
nop
.half 0xe960
ld $5, 0xf8($pc)
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 12, 0
|
tactcomplabs/xbgas-binutils-gdb | 2,087 | binutils/testsuite/binutils-all/x86-64/compressed-1.s | .file "compressed-1.c"
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.section .debug_line,"",@progbits
.Ldebug_line0:
.text
.Ltext0:
.cfi_sections .debug_frame
.p2align 4,,15
.globl foo2
.type foo2, @function
foo2:
.LFB1:
.file 1 "compressed-1.c"
.loc 1 11 0
.cfi_startproc
.loc 1 12 0
rep
ret
.cfi_endproc
.LFE1:
.size foo2, .-foo2
.p2align 4,,15
.globl foo1
.type foo1, @function
foo1:
.LFB0:
.loc 1 5 0
.cfi_startproc
.loc 1 6 0
jmp bar
.cfi_endproc
.LFE0:
.size foo1, .-foo1
.Letext0:
.section .debug_info
.long 0x5e
.value 0x3
.long .Ldebug_abbrev0
.byte 0x8
.uleb128 0x1
.long .LASF2
.byte 0x1
.long .LASF3
.long .LASF4
.quad .Ltext0
.quad .Letext0
.long .Ldebug_line0
.uleb128 0x2
.byte 0x1
.long .LASF0
.byte 0x1
.byte 0xa
.quad .LFB1
.quad .LFE1
.byte 0x1
.byte 0x9c
.uleb128 0x2
.byte 0x1
.long .LASF1
.byte 0x1
.byte 0x4
.quad .LFB0
.quad .LFE0
.byte 0x1
.byte 0x9c
.byte 0x0
.section .debug_abbrev
.uleb128 0x1
.uleb128 0x11
.byte 0x1
.uleb128 0x25
.uleb128 0xe
.uleb128 0x13
.uleb128 0xb
.uleb128 0x3
.uleb128 0xe
.uleb128 0x1b
.uleb128 0xe
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x10
.uleb128 0x6
.byte 0x0
.byte 0x0
.uleb128 0x2
.uleb128 0x2e
.byte 0x0
.uleb128 0x3f
.uleb128 0xc
.uleb128 0x3
.uleb128 0xe
.uleb128 0x3a
.uleb128 0xb
.uleb128 0x3b
.uleb128 0xb
.uleb128 0x11
.uleb128 0x1
.uleb128 0x12
.uleb128 0x1
.uleb128 0x40
.uleb128 0xa
.byte 0x0
.byte 0x0
.byte 0x0
.section .debug_pubnames,"",@progbits
.long 0x20
.value 0x2
.long .Ldebug_info0
.long 0x62
.long 0x2d
.string "foo2"
.long 0x47
.string "foo1"
.long 0x0
.section .debug_aranges,"",@progbits
.long 0x2c
.value 0x2
.long .Ldebug_info0
.byte 0x8
.byte 0x0
.value 0x0
.value 0x0
.quad .Ltext0
.quad .Letext0-.Ltext0
.quad 0x0
.quad 0x0
.section .debug_str,"MS",@progbits,1
.LASF2:
.string "GNU C 4.4.4"
.LASF0:
.string "foo2"
.LASF1:
.string "foo1"
.LASF4:
.string "."
.LASF3:
.string "compressed-1.c"
|
tactcomplabs/xbgas-binutils-gdb | 1,494 | binutils/testsuite/binutils-all/x86-64/pr23494a.s | .section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_X86_ISA_1_USED */
.long 0xc0010002 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.long 0xa
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
.section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_X86_ISA_1_NEEDED */
.long 0xc0008002 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.long 0xa0
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
.section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_X86_ISA_1_USED */
.long 0xc0010002 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.long 0xa0
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
|
tactcomplabs/xbgas-binutils-gdb | 1,979 | binutils/testsuite/binutils-all/x86-64/pr23494c.s | .section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_STACK_SIZE */
.long 1 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.dc.a -1
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
.section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_X86_ISA_1_USED */
.long 0xc0010002 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.long 0xa
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
.section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_X86_ISA_1_NEEDED */
.long 0xc0008002 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.long 0xa0
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
.section ".note.gnu.property", "a"
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
.long 1f - 0f /* name length. */
.long 3f - 1f /* data length. */
/* NT_GNU_PROPERTY_TYPE_0 */
.long 5 /* note type. */
0:
.asciz "GNU" /* vendor name. */
1:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
/* GNU_PROPERTY_X86_ISA_1_USED */
.long 0xc0010002 /* pr_type. */
.long 5f - 4f /* pr_datasz. */
4:
.long 0xa0
5:
.ifdef __64_bit__
.p2align 3
.else
.p2align 2
.endif
3:
|
tactcomplabs/xbgas-binutils-gdb | 1,478 | binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s | .text
func:
//scale 1, size<0> check for H.
#st1 {v30.h}[0], [x30]
.inst 0x0d0043de | (1 << 10)
#st2 {v29.h, v30.h}[0], [x30]
.inst 0x0d2043dd | (1 << 10)
#st3 {v28.h, v29.h, v30.h}[0], [x30]
.inst 0x0d0063dc | (1 << 10)
#st4 {v27.h, v28.h, v29.h, v30.h}[0], [x30]
.inst 0x0d2063db | (1 << 10)
//scale 2, size<1> check for S.
#st1 {v30.s}[0], [x30]
.inst 0x0d0083de | (1 << 11)
#st2 {v29.s, v30.s}[0], [x30]
.inst 0x0d2083dd | (1 << 11)
#st3 {v28.s, v29.s, v30.s}[0], [x30]
.inst 0x0d00a3dc | (1 << 11)
#st4 {v27.s, v28.s, v29.s, v30.s}[0], [x30]
.inst 0x0d20a3db | (1 << 11)
//scale 2, size<1> check for D.
#st1 {v30.d}[0], [x30]
.inst 0x0d0087de | (1 << 11)
#st2 {v29.d, v30.d}[0], [x30]
.inst 0x0d2087dd | (1 << 11)
#st3 {v28.d, v29.d, v30.d}[0], [x30]
.inst 0x0d00a7dc | (1 << 11)
#st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30]
.inst 0x0d20a7db | (1 << 11)
//scale 2, S-bit check for D.
#st1 {v30.d}[0], [x30]
.inst 0x0d0087de | (2 << 11)
#st2 {v29.d, v30.d}[0], [x30]
.inst 0x0d2087dd | (2 << 11)
#st3 {v28.d, v29.d, v30.d}[0], [x30]
.inst 0x0d00a7dc | (2 << 11)
#st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30]
.inst 0x0d20a7db | (2 << 11)
//scale 2, size<1> & S-bit check for D.
#st1 {v30.d}[0], [x30]
.inst 0x0d0087de | (3 << 11)
#st2 {v29.d, v30.d}[0], [x30]
.inst 0x0d2087dd | (3 << 11)
#st3 {v28.d, v29.d, v30.d}[0], [x30]
.inst 0x0d00a7dc | (3 << 11)
#st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30]
.inst 0x0d20a7db | (3 << 11)
|
tactcomplabs/xbgas-binutils-gdb | 1,568 | sim/bfin/linux-fixed-code.s | /* Linux fixed code userspace ABI
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* For more info, see this page:
http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:fixed-code */
.text
.align 16
_sigreturn_stub:
P0 = 173;
EXCPT 0;
0: JUMP.S 0b;
.align 16
_atomic_xchg32:
R0 = [P0];
[P0] = R1;
rts;
.align 16
_atomic_cas32:
R0 = [P0];
CC = R0 == R1;
IF !CC JUMP 1f;
[P0] = R2;
1:
rts;
.align 16
_atomic_add32:
R1 = [P0];
R0 = R1 + R0;
[P0] = R0;
rts;
.align 16
_atomic_sub32:
R1 = [P0];
R0 = R1 - R0;
[P0] = R0;
rts;
.align 16
_atomic_ior32:
R1 = [P0];
R0 = R1 | R0;
[P0] = R0;
rts;
.align 16
_atomic_and32:
R1 = [P0];
R0 = R1 & R0;
[P0] = R0;
rts;
.align 16
_atomic_xor32:
R1 = [P0];
R0 = R1 ^ R0;
[P0] = R0;
rts;
.align 16
_safe_user_instruction:
NOP; NOP; NOP; NOP;
EXCPT 0x4;
|
tactcomplabs/xbgas-binutils-gdb | 32,830 | sim/testsuite/sh/movxy.s | # sh testcase for movxy
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
src1: .word 1
src2: .word 2
src3: .word 3
src4: .word 4
src5: .word 5
src6: .word 6
src7: .word 7
src8: .word 8
src9: .word 9
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dst1: .word 0
dst2: .word 0
dst3: .word 0
dst4: .word 0
dst5: .word 0
dst6: .word 0
dst7: .word 0
dst8: .word 0
dst9: .word 0
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
start
movxw_nopy:
set_grs_a5a5
# load up pointers
mov.l srcp1, r4
mov.l dstp1, r5
# perform moves
movx.w @r4, x0
pcopy x0, a0
movx.w a0, @r5
# verify pointers unchanged
mov.l srcp1, r0
cmp/eq r0, r4
bt .L0
fail
.L0:
mov.l dstp1, r1
cmp/eq r1, r5
bt .L1
fail
.L1:
# verify copied values
mov.w @r0, r0
mov.w @r1, r1
cmp/eq r0, r1
bt .L2
fail
.L2:
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movyw_nopx:
set_grs_a5a5
# load up pointers
mov.l srcp2, r6
mov.l dstp2, r7
# perform moves
movy.w @r6, y0
pcopy y0, a0
movy.w a0, @r7
# verify pointers unchanged
mov.l srcp2, r2
cmp/eq r2, r6
bt .L3
fail
.L3:
mov.l dstp2, r3
cmp/eq r3, r7
bt .L4
fail
.L4:
# verify copied values
mov.w @r2, r2
mov.w @r3, r3
cmp/eq r2, r3
bt .L5
fail
.L5:
test_gr_a5a5 r0
test_gr_a5a5 r1
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movxw_movyw:
set_grs_a5a5
# load up pointers
mov.l srcp3, r4
mov.l dstp3, r5
mov.l srcp4, r6
mov.l dstp4, r7
# perform moves
movx.w @r4, x1 movy.w @r6, y1
pcopy x1, a0
pcopy y1, a1
movx.w a0, @r5 movy.w a1, @r7
# verify pointers unchanged
mov.l srcp3, r0
cmp/eq r0, r4
bt .L6
fail
.L6:
mov.l dstp3, r1
cmp/eq r1, r5
bt .L7
fail
.L7:
mov.l srcp4, r2
cmp/eq r2, r6
bt .L8
fail
.L8:
mov.l dstp4, r3
cmp/eq r3, r7
bt .L9
fail
.L9:
# verify copied values
mov.w @r0, r0
mov.w @r1, r1
cmp/eq r0, r1
bt .L10
fail
.L10:
mov.w @r2, r2
mov.w @r3, r3
cmp/eq r2, r3
bt .L11
fail
.L11:
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra movxw_movyw_new
nop
.align 2
srcp1: .long src1
srcp2: .long src2
srcp3: .long src3
srcp4: .long src4
srcp5: .long src5
srcp6: .long src6
srcp7: .long src7
srcp8: .long src8
srcp9: .long src9
dstp1: .long dst1
dstp2: .long dst2
dstp3: .long dst3
dstp4: .long dst4
dstp5: .long dst5
dstp6: .long dst6
dstp7: .long dst7
dstp8: .long dst8
dstp9: .long dst9
movxw_movyw_new:
set_grs_a5a5
# load up pointers
mov.l srcp5b, r0
mov.l dstp5b, r1
mov.l srcp6b, r2
mov.l dstp6b, r3
# perform moves
movx.w @r0, x1
movy.w @r2, y1
movx.w x1, @r1
movy.w y1, @r3
# verify pointers unchanged
mov.l srcp5b, r4
cmp/eq r0, r4
bt .L12
fail
.L12:
mov.l dstp5b, r5
cmp/eq r1, r5
bt .L13
fail
.L13:
mov.l srcp6b, r6
cmp/eq r2, r6
bt .L14
fail
.L14:
mov.l dstp6b, r7
cmp/eq r3, r7
bt .L15
fail
.L15:
# verify copied values
mov.w @r0, r0
mov.w @r1, r1
cmp/eq r0, r1
bt .L16
fail
.L16:
mov.w @r2, r2
mov.w @r3, r3
cmp/eq r2, r3
bt .L17
fail
.L17:
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mov.l srcp1b, r0
mov.l dstp1b, r1
mov.l srcp2b, r2
mov.l dstp2b, r3
mov.l srcp1b, r4
mov.l dstp1b, r5
mov.l srcp2b, r6
mov.l dstp2b, r7
mov #4, r8
mov #4, r9
bra .L18
nop
.align 2
srcp1b: .long src1
srcp2b: .long src2
srcp3b: .long src3
srcp4b: .long src4
srcp5b: .long src5
srcp6b: .long src6
srcp7b: .long src7
srcp8b: .long src8
srcp9b: .long src9
dstp1b: .long dst1
dstp2b: .long dst2
dstp3b: .long dst3
dstp4b: .long dst4
dstp5b: .long dst5
dstp6b: .long dst6
dstp7b: .long dst7
dstp8b: .long dst8
dstp9b: .long dst9
.L18:
# movx.w @Ax{}, Dx | nopy
movxwaxdx_nopy:
movx.w @r4,x0 ! .word 0xf004
movx.w @r4,x1 ! .word 0xf084
movx.w @r5,x0 ! .word 0xf204
movx.w @r5,x1 ! .word 0xf284
movx.w @r4+,x0 ! .word 0xf008
movx.w @r4+,x1 ! .word 0xf088
movx.w @r5+,x0 ! .word 0xf208
movx.w @r5+,x1 ! .word 0xf288
movx.w @r4+r8,x0 ! .word 0xf00c
movx.w @r4+r8,x1 ! .word 0xf08c
movx.w @r5+r8,x0 ! .word 0xf20c
movx.w @r5+r8,x1 ! .word 0xf28c
# movx.w Da, @Ax{} | nopy
movxwdaax_nopy:
movx.w a0,@r4 ! .word 0xf024
movx.w a1,@r4 ! .word 0xf0a4
movx.w a0,@r5 ! .word 0xf224
movx.w a1,@r5 ! .word 0xf2a4
movx.w a0,@r4+ ! .word 0xf028
movx.w a1,@r4+ ! .word 0xf0a8
movx.w a0,@r5+ ! .word 0xf228
movx.w a1,@r5+ ! .word 0xf2a8
movx.w a0,@r4+r8 ! .word 0xf02c
movx.w a1,@r4+r8 ! .word 0xf0ac
movx.w a0,@r5+r8 ! .word 0xf22c
movx.w a1,@r5+r8 ! .word 0xf2ac
# movy.w @Ay{}, Dy | nopx
movywaydy_nopx:
movy.w @r6,y0 ! .word 0xf001
movy.w @r6,y1 ! .word 0xf041
movy.w @r7,y0 ! .word 0xf101
movy.w @r7,y1 ! .word 0xf141
movy.w @r6+,y0 ! .word 0xf002
movy.w @r6+,y1 ! .word 0xf042
movy.w @r7+,y0 ! .word 0xf102
movy.w @r7+,y1 ! .word 0xf142
movy.w @r6+r9,y0 ! .word 0xf003
movy.w @r6+r9,y1 ! .word 0xf043
movy.w @r7+r9,y0 ! .word 0xf103
movy.w @r7+r9,y1 ! .word 0xf143
# movy.w Da, @Ay{} | nopx
movywdaay_nopx:
movy.w a0,@r6 ! .word 0xf011
movy.w a1,@r6 ! .word 0xf051
movy.w a0,@r7 ! .word 0xf111
movy.w a1,@r7 ! .word 0xf151
movy.w a0,@r6+ ! .word 0xf012
movy.w a1,@r6+ ! .word 0xf052
movy.w a0,@r7+ ! .word 0xf112
movy.w a1,@r7+ ! .word 0xf152
movy.w a0,@r6+r9 ! .word 0xf013
movy.w a1,@r6+r9 ! .word 0xf053
movy.w a0,@r7+r9 ! .word 0xf113
movy.w a1,@r7+r9 ! .word 0xf153
# movx {} || movy {}
movx_movy:
movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005
movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045
movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085
movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5
movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105
movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145
movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185
movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5
movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205
movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245
movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285
movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5
movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305
movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345
movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385
movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5
movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006
movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046
movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086
movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6
movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106
movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146
movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186
movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6
movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206
movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246
movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286
movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6
movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306
movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346
movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386
movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6
movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007
movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047
movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087
movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7
movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107
movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147
movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187
movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7
movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207
movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247
movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287
movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7
movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307
movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347
movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387
movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7
movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009
movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049
movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089
movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9
movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109
movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149
movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189
movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9
movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209
movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249
movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289
movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9
movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309
movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349
movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389
movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9
movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a
movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a
movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a
movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca
movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a
movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a
movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a
movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca
movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a
movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a
movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a
movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca
movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a
movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a
movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a
movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca
movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b
movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b
movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b
movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb
movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b
movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b
movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b
movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb
movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b
movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b
movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b
movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb
movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b
movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b
movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b
movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb
movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d
movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d
movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d
movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd
movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d
movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d
movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d
movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd
movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d
movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d
movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d
movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd
movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d
movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d
movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d
movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd
movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e
movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e
movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e
movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce
movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e
movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e
movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e
movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce
movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e
movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e
movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e
movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce
movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e
movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e
movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e
movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce
movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f
movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f
movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f
movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf
movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f
movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f
movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f
movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf
movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f
movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f
movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f
movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf
movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f
movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f
movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f
movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf
movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015
movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055
movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095
movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5
movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115
movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155
movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195
movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5
movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215
movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255
movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295
movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5
movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315
movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355
movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395
movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5
movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016
movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056
movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096
movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6
movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116
movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156
movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196
movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6
movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216
movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256
movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296
movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6
movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316
movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356
movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396
movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6
movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017
movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057
movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097
movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7
movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117
movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157
movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197
movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7
movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217
movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257
movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297
movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7
movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317
movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357
movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397
movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7
movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019
movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059
movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099
movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9
movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119
movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159
movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199
movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9
movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219
movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259
movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299
movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9
movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319
movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359
movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399
movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9
movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a
movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a
movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a
movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da
movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a
movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a
movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a
movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da
movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a
movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a
movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a
movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da
movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a
movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a
movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a
movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da
movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b
movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b
movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b
movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db
movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b
movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b
movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b
movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db
movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b
movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b
movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b
movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db
movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b
movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b
movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b
movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db
movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d
movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d
movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d
movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd
movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d
movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d
movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d
movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd
movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d
movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d
movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d
movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd
movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d
movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d
movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d
movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd
movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e
movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e
movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e
movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de
movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e
movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e
movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e
movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de
movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e
movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e
movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e
movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de
movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e
movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e
movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e
movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de
movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f
movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f
movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f
movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df
movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f
movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f
movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f
movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df
movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f
movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f
movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f
movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df
movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f
movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f
movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f
movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df
movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025
movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065
movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5
movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5
movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125
movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165
movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5
movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5
movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225
movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265
movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5
movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5
movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325
movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365
movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5
movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5
movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026
movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066
movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6
movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6
movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126
movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166
movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6
movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6
movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226
movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266
movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6
movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6
movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326
movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366
movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6
movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6
movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027
movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067
movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7
movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7
movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127
movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167
movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7
movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7
movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227
movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267
movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7
movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7
movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327
movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367
movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7
movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7
movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029
movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069
movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9
movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9
movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129
movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169
movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9
movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9
movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229
movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269
movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9
movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9
movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329
movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369
movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9
movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9
movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a
movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a
movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa
movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea
movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a
movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a
movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa
movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea
movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a
movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a
movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa
movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea
movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a
movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a
movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa
movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea
movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b
movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b
movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab
movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb
movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b
movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b
movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab
movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb
movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b
movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b
movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab
movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb
movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b
movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b
movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab
movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb
movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d
movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d
movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad
movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed
movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d
movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d
movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad
movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed
movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d
movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d
movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad
movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed
movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d
movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d
movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad
movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed
movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e
movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e
movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae
movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee
movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e
movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e
movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae
movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee
movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e
movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e
movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae
movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee
movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e
movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e
movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae
movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee
movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f
movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f
movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af
movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef
movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f
movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f
movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af
movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef
movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f
movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f
movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af
movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef
movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f
movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f
movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af
movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef
movxwaxydxy:
movx.w @r4,x0 !
movx.w @r4,y0 !
movx.w @r4,x1 !
movx.w @r4,y1 !
movx.w @r0,x0 !
movx.w @r0,y0 !
movx.w @r0,x1 !
movx.w @r0,y1 !
movx.w @r5,x0 !
movx.w @r5,y0 !
movx.w @r5,x1 !
movx.w @r5,y1 !
movx.w @r1,x0 !
movx.w @r1,y0 !
movx.w @r1,x1 !
movx.w @r1,y1 !
movx.w @r4+,x0 !
movx.w @r4+,y0 !
movx.w @r4+,x1 !
movx.w @r4+,y1 !
movx.w @r0+,x0 !
movx.w @r0+,y0 !
movx.w @r0+,x1 !
movx.w @r0+,y1 !
movx.w @r5+,x0 !
movx.w @r5+,y0 !
movx.w @r5+,x1 !
movx.w @r5+,y1 !
movx.w @r1+,x0 !
movx.w @r1+,y0 !
movx.w @r1+,x1 !
movx.w @r1+,y1 !
movx.w @r4+r8,x0 !
movx.w @r4+r8,y0 !
movx.w @r4+r8,x1 !
movx.w @r4+r8,y1 !
movx.w @r0+r8,x0 !
movx.w @r0+r8,y0 !
movx.w @r0+r8,x1 !
movx.w @r0+r8,y1 !
movx.w @r5+r8,x0 !
movx.w @r5+r8,y0 !
movx.w @r5+r8,x1 !
movx.w @r5+r8,y1 !
movx.w @r1+r8,x0 !
movx.w @r1+r8,y0 !
movx.w @r1+r8,x1 !
movx.w @r1+r8,y1 !
movxwdaxaxy: !
movx.w a0,@r4 !
movx.w x0,@r4 !
movx.w a1,@r4 !
movx.w x1,@r4 !
movx.w a0,@r0 !
movx.w x0,@r0 !
movx.w a1,@r0 !
movx.w x1,@r0 !
movx.w a0,@r5 !
movx.w x0,@r5 !
movx.w a1,@r5 !
movx.w x1,@r5 !
movx.w a0,@r1 !
movx.w x0,@r1 !
movx.w a1,@r1 !
movx.w x1,@r1 !
movx.w a0,@r4+ !
movx.w x0,@r4+ !
movx.w a1,@r4+ !
movx.w x1,@r4+ !
movx.w a0,@r0+ !
movx.w x0,@r0+ !
movx.w a1,@r0+ !
movx.w x1,@r0+ !
movx.w a0,@r5+ !
movx.w x0,@r5+ !
movx.w a1,@r5+ !
movx.w x1,@r5+ !
movx.w a0,@r1+ !
movx.w x0,@r1+ !
movx.w a1,@r1+ !
movx.w x1,@r1+ !
movx.w a0,@r4+r8 !
movx.w x0,@r4+r8 !
movx.w a1,@r4+r8 !
movx.w x1,@r4+r8 !
movx.w a0,@r0+r8 !
movx.w x0,@r0+r8 !
movx.w a1,@r0+r8 !
movx.w x1,@r0+r8 !
movx.w a0,@r5+r8 !
movx.w x0,@r5+r8 !
movx.w a1,@r5+r8 !
movx.w x1,@r5+r8 !
movx.w a0,@r1+r8 !
movx.w x0,@r1+r8 !
movx.w a1,@r1+r8 !
movx.w x1,@r1+r8 !
movywayxdyx: !
movy.w @r6,y0 !
movy.w @r6,y1 !
movy.w @r6,x0 !
movy.w @r6,x1 !
movy.w @r7,y0 !
movy.w @r7,y1 !
movy.w @r7,x0 !
movy.w @r7,x1 !
movy.w @r2,y0 !
movy.w @r2,y1 !
movy.w @r2,x0 !
movy.w @r2,x1 !
movy.w @r3,y0 !
movy.w @r3,y1 !
movy.w @r3,x0 !
movy.w @r3,x1 !
movy.w @r6+,y0 !
movy.w @r6+,y1 !
movy.w @r6+,x0 !
movy.w @r6+,x1 !
movy.w @r7+,y0 !
movy.w @r7+,y1 !
movy.w @r7+,x0 !
movy.w @r7+,x1 !
movy.w @r2+,y0 !
movy.w @r2+,y1 !
movy.w @r2+,x0 !
movy.w @r2+,x1 !
movy.w @r3+,y0 !
movy.w @r3+,y1 !
movy.w @r3+,x0 !
movy.w @r3+,x1 !
movy.w @r6+r9,y0 !
movy.w @r6+r9,y1 !
movy.w @r6+r9,x0 !
movy.w @r6+r9,x1 !
movy.w @r7+r9,y0 !
movy.w @r7+r9,y1 !
movy.w @r7+r9,x0 !
movy.w @r7+r9,x1 !
movy.w @r2+r9,y0 !
movy.w @r2+r9,y1 !
movy.w @r2+r9,x0 !
movy.w @r2+r9,x1 !
movy.w @r3+r9,y0 !
movy.w @r3+r9,y1 !
movy.w @r3+r9,x0 !
movy.w @r3+r9,x1 !
movywdayayx:
movy.w a0,@r6
movy.w a1,@r6
movy.w y0,@r6
movy.w y1,@r6
movy.w a0,@r7
movy.w a1,@r7
movy.w y0,@r7
movy.w y1,@r7
movy.w a0,@r2
movy.w a1,@r2
movy.w y0,@r2
movy.w y1,@r2
movy.w a0,@r3
movy.w a1,@r3
movy.w y0,@r3
movy.w y1,@r3
movy.w a0,@r6+
movy.w a1,@r6+
movy.w y0,@r6+
movy.w y1,@r6+
movy.w a0,@r7+
movy.w a1,@r7+
movy.w y0,@r7+
movy.w y1,@r7+
movy.w a0,@r2+
movy.w a1,@r2+
movy.w y0,@r2+
movy.w y1,@r2+
movy.w a0,@r3+
movy.w a1,@r3+
movy.w y0,@r3+
movy.w y1,@r3+
movy.w a0,@r6+r9
movy.w a1,@r6+r9
movy.w y0,@r6+r9
movy.w y1,@r6+r9
movy.w a0,@r7+r9
movy.w a1,@r7+r9
movy.w y0,@r7+r9
movy.w y1,@r7+r9
movy.w a0,@r2+r9
movy.w a1,@r2+r9
movy.w y0,@r2+r9
movy.w y1,@r2+r9
movy.w a0,@r3+r9
movy.w a1,@r3+r9
movy.w y0,@r3+r9
movy.w y1,@r3+r9
mov r4, r0
mov r4, r1
mov r4, r2
mov r4, r3
mov r4, r5
mov r4, r6
mov r5, r7
movxlaxydxy:
movx.l @r4,x0
movx.l @r4,y0
movx.l @r4,x1
movx.l @r4,y1
movx.l @r0,x0
movx.l @r0,y0
movx.l @r0,x1
movx.l @r0,y1
movx.l @r5,x0
movx.l @r5,y0
movx.l @r5,x1
movx.l @r5,y1
movx.l @r1,x0
movx.l @r1,y0
movx.l @r1,x1
movx.l @r1,y1
movx.l @r4+,x0
movx.l @r4+,y0
movx.l @r4+,x1
movx.l @r4+,y1
movx.l @r0+,x0
movx.l @r0+,y0
movx.l @r0+,x1
movx.l @r0+,y1
movx.l @r5+,x0
movx.l @r5+,y0
movx.l @r5+,x1
movx.l @r5+,y1
movx.l @r1+,x0
movx.l @r1+,y0
movx.l @r1+,x1
movx.l @r1+,y1
movx.l @r4+r8,x0
movx.l @r4+r8,y0
movx.l @r4+r8,x1
movx.l @r4+r8,y1
movx.l @r0+r8,x0
movx.l @r0+r8,y0
movx.l @r0+r8,x1
movx.l @r0+r8,y1
movx.l @r5+r8,x0
movx.l @r5+r8,y0
movx.l @r5+r8,x1
movx.l @r5+r8,y1
movx.l @r1+r8,x0
movx.l @r1+r8,y0
movx.l @r1+r8,x1
movx.l @r1+r8,y1
movxldaxaxy:
movx.l a0,@r4
movx.l x0,@r4
movx.l a1,@r4
movx.l x1,@r4
movx.l a0,@r0
movx.l x0,@r0
movx.l a1,@r0
movx.l x1,@r0
movx.l a0,@r5
movx.l x0,@r5
movx.l a1,@r5
movx.l x1,@r5
movx.l a0,@r1
movx.l x0,@r1
movx.l a1,@r1
movx.l x1,@r1
movx.l a0,@r4+
movx.l x0,@r4+
movx.l a1,@r4+
movx.l x1,@r4+
movx.l a0,@r0+
movx.l x0,@r0+
movx.l a1,@r0+
movx.l x1,@r0+
movx.l a0,@r5+
movx.l x0,@r5+
movx.l a1,@r5+
movx.l x1,@r5+
movx.l a0,@r1+
movx.l x0,@r1+
movx.l a1,@r1+
movx.l x1,@r1+
movx.l a0,@r4+r8
movx.l x0,@r4+r8
movx.l a1,@r4+r8
movx.l x1,@r4+r8
movx.l a0,@r0+r8
movx.l x0,@r0+r8
movx.l a1,@r0+r8
movx.l x1,@r0+r8
movx.l a0,@r5+r8
movx.l x0,@r5+r8
movx.l a1,@r5+r8
movx.l x1,@r5+r8
movx.l a0,@r1+r8
movx.l x0,@r1+r8
movx.l a1,@r1+r8
movx.l x1,@r1+r8
movylayxdyx:
movy.l @r6,y0
movy.l @r6,y1
movy.l @r6,x0
movy.l @r6,x1
movy.l @r7,y0
movy.l @r7,y1
movy.l @r7,x0
movy.l @r7,x1
movy.l @r2,y0
movy.l @r2,y1
movy.l @r2,x0
movy.l @r2,x1
movy.l @r3,y0
movy.l @r3,y1
movy.l @r3,x0
movy.l @r3,x1
movy.l @r6+,y0
movy.l @r6+,y1
movy.l @r6+,x0
movy.l @r6+,x1
movy.l @r7+,y0
movy.l @r7+,y1
movy.l @r7+,x0
movy.l @r7+,x1
movy.l @r2+,y0
movy.l @r2+,y1
movy.l @r2+,x0
movy.l @r2+,x1
movy.l @r3+,y0
movy.l @r3+,y1
movy.l @r3+,x0
movy.l @r3+,x1
movy.l @r6+r9,y0
movy.l @r6+r9,y1
movy.l @r6+r9,x0
movy.l @r6+r9,x1
movy.l @r7+r9,y0
movy.l @r7+r9,y1
movy.l @r7+r9,x0
movy.l @r7+r9,x1
movy.l @r2+r9,y0
movy.l @r2+r9,y1
movy.l @r2+r9,x0
movy.l @r2+r9,x1
movy.l @r3+r9,y0
movy.l @r3+r9,y1
movy.l @r3+r9,x0
movy.l @r3+r9,x1
movyldayayx:
movy.l a0,@r6
movy.l a1,@r6
movy.l y0,@r6
movy.l y1,@r6
movy.l a0,@r7
movy.l a1,@r7
movy.l y0,@r7
movy.l y1,@r7
movy.l a0,@r2
movy.l a1,@r2
movy.l y0,@r2
movy.l y1,@r2
movy.l a0,@r3
movy.l a1,@r3
movy.l y0,@r3
movy.l y1,@r3
movy.l a0,@r6+
movy.l a1,@r6+
movy.l y0,@r6+
movy.l y1,@r6+
movy.l a0,@r7+
movy.l a1,@r7+
movy.l y0,@r7+
movy.l y1,@r7+
movy.l a0,@r2+
movy.l a1,@r2+
movy.l y0,@r2+
movy.l y1,@r2+
movy.l a0,@r3+
movy.l a1,@r3+
movy.l y0,@r3+
movy.l y1,@r3+
movy.l a0,@r6+r9
movy.l a1,@r6+r9
movy.l y0,@r6+r9
movy.l y1,@r6+r9
movy.l a0,@r7+r9
movy.l a1,@r7+r9
movy.l y0,@r7+r9
movy.l y1,@r7+r9
movy.l a0,@r2+r9
movy.l a1,@r2+r9
movy.l y0,@r2+r9
movy.l y1,@r2+r9
movy.l a0,@r3+r9
movy.l a1,@r3+r9
movy.l y0,@r3+r9
movy.l y1,@r3+r9
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,647 | sim/testsuite/sh/bxor.s | # sh testcase for bxor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bxor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bxor.b #0, @(3, r1)
bt8k mfail
bxor.b #1, @(3, r1)
bt8k mfail
bxor.b #2, @(3, r1)
bf8k mfail
bxor.b #3, @(3, r1)
bf8k mfail
bxor.b #4, @(3, r1)
bf8k mfail
bxor.b #5, @(3, r1)
bt8k mfail
bxor.b #6, @(3, r1)
bt8k mfail
bxor.b #7, @(3, r1)
bf8k mfail
bxor.b #0, @(2, r1)
bt8k mfail
bxor.b #1, @(2, r1)
bt8k mfail
bxor.b #2, @(2, r1)
bf8k mfail
bxor.b #3, @(2, r1)
bf8k mfail
bra .L2
nop
.align 2
x: .long _x
.L2:
bxor.b #4, @(2, r1)
bf8k mfail
bxor.b #5, @(2, r1)
bt8k mfail
bxor.b #6, @(2, r1)
bt8k mfail
bxor.b #7, @(2, r1)
bf8k mfail
bxor.b #0, @(1, r1)
bt8k mfail
bxor.b #1, @(1, r1)
bt8k mfail
bxor.b #2, @(1, r1)
bf8k mfail
bxor.b #3, @(1, r1)
bf8k mfail
bxor.b #4, @(1, r1)
bf8k mfail
bxor.b #5, @(1, r1)
bt8k mfail
bxor.b #6, @(1, r1)
bt8k mfail
bxor.b #7, @(1, r1)
bf8k mfail
bxor.b #0, @(0, r1)
bt8k mfail
bxor.b #1, @(0, r1)
bt8k mfail
bxor.b #2, @(0, r1)
bf8k mfail
bxor.b #3, @(0, r1)
bf8k mfail
bxor.b #4, @(0, r1)
bf8k mfail
bxor.b #5, @(0, r1)
bt8k mfail
bxor.b #6, @(0, r1)
bt8k mfail
bxor.b #7, @(0, r1)
bf8k mfail
assertreg _x, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 4,699 | sim/testsuite/sh/fmov.s | # sh testcase for all fmov instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fldi1 fr3
.endm
start
fmov1: # Test fr -> fr.
set_grs_a5a5
set_fprs_a5a5
init
single_prec
sz_32
fmov fr0, fr1
# Ensure fr0 and fr1 are now equal.
fcmp/eq fr0, fr1
bt fmov2
fail
fmov2: # Test dr -> dr.
init
double_prec
sz_64
fmov dr0, dr2
# Ensure dr0 and dr2 are now equal.
fcmp/eq dr0, dr2
bt fmov3
fail
fmov3: # Test dr -> xd and xd -> dr.
init
sz_64
fmov dr0, xd0
# Ensure dr0 and xd0 are now equal.
fmov xd0, dr2
fcmp/eq dr0, dr2
bt fmov4
fail
fmov4: # Test xd -> xd.
init
sz_64
double_prec
fmov dr0, xd0
fmov xd0, xd2
fmov xd2, dr2
# Ensure dr0 and dr2 are now equal.
fcmp/eq dr0, dr2
bt .L0
fail
# FIXME: test fmov.s fr -> @gr, fmov dr -> @gr
# FIXME: test fmov.s @gr -> fr, fmov @gr -> dr
# FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr
# FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr
# FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr
# FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr)
.L0:
test_grs_a5a5
sz_32
single_prec
assert_fpreg_i 0, fr0
assert_fpreg_i 1, fr1
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fmov5: # Test fr -> @rn and @rn -> fr.
init
sz_32
single_prec
# FIXME! Use a reserved memory location!
mov #40, r0
shll8 r0
fmov fr0, @r0
fmov @r0, fr1
fcmp/eq fr0, fr1
bt fmov6
fail
fmov6: # Test dr -> @rn and @rn -> dr.
init
sz_64
double_prec
mov #40, r0
shll8 r0
fmov dr0, @r0
fmov @r0, dr2
fcmp/eq dr0, dr2
bt fmov7
fail
fmov7: # Test xd -> @rn and @rn -> xd.
init
sz_64
double_prec
mov #40, r0
shll8 r0
fmov dr0, xd0
fmov xd0, @r0
fmov @r0, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt fmov8
fail
fmov8: # Test fr -> @-rn.
init
sz_32
single_prec
mov #40, r0
shll8 r0
# Preserve.
mov r0, r1
fmov fr0, @-r0
fmov @r0, fr2
fcmp/eq fr0, fr2
bt f8b
fail
f8b: # check pre-dec.
add #4, r0
cmp/eq r0, r1
bt fmov9
fail
fmov9: # Test dr -> @-rn.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, @-r0
fmov @r0, dr2
fcmp/eq dr0, dr2
bt f9b
fail
f9b: # check pre-dec.
add #8, r0
cmp/eq r0, r1
bt fmov10
fail
fmov10: # Test xd -> @-rn.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, xd0
fmov xd0, @-r0
fmov @r0, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt f10b
fail
f10b: # check pre-dec.
add #8, r0
cmp/eq r0, r1
bt fmov11
fail
fmov11: # Test @rn+ -> fr.
init
sz_32
single_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov fr0, @r0
fmov @r0+, fr2
fcmp/eq fr0, fr2
bt f11b
fail
f11b: # check post-inc.
add #4, r1
cmp/eq r0, r1
bt fmov12
fail
fmov12: # Test @rn+ -> dr.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# preserve r0.
mov r0, r1
fmov dr0, @r0
fmov @r0+, dr2
fcmp/eq dr0, dr2
bt f12b
fail
f12b: # check post-inc.
add #8, r1
cmp/eq r0, r1
bt fmov13
fail
fmov13: # Test @rn -> xd.
init
sz_64
double_prec
mov #40, r0
shll8 r0
# Preserve r0.
mov r0, r1
fmov dr0, xd0
fmov xd0, @r0
fmov @r0+, xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt f13b
fail
f13b:
add #8, r1
cmp/eq r0, r1
bt fmov14
fail
fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
init
sz_32
single_prec
mov #40, r0
shll8 r0
mov #0, r1
fmov fr0, @(r0, r1)
fmov @(r0, r1), fr1
fcmp/eq fr0, fr1
bt fmov15
fail
fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
init
sz_64
double_prec
mov #40, r0
shll8 r0
mov #0, r1
fmov dr0, @(r0, r1)
fmov @(r0, r1), dr2
fcmp/eq dr0, dr2
bt fmov16
fail
fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
init
sz_64
double_prec
mov #40, r0
shll8 r0
mov #0, r1
fmov dr0, xd0
fmov xd0, @(r0, r1)
fmov @(r0, r1), xd2
fmov xd2, dr2
fcmp/eq dr0, dr2
bt .L1
fail
.L1:
assertreg0 0x2800
assertreg 0, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
sz_32
single_prec
assert_fpreg_i 0, fr0
assert_fpreg_i 1, fr1
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,619 | sim/testsuite/sh/fcmpeq.s | # sh testcase for fcmpeq
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpeq_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 == 1.0.
fldi1 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# 0.0 != 1.0.
fldi0 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L1
fail
.L1:
# 1.0 != 0.0.
fldi1 fr0
fldi0 fr1
fcmp/eq fr0, fr1
bf .L2
fail
.L2:
# 2.0 != 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fcmpeq_double:
# 1.0 == 1.0
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# 0.0 != 1.0
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L11
fail
.L11:
# 1.0 != 0.0
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L12
fail
.L12:
# 2.0 != 1.0
fldi1 fr0
single_prec
fadd fr0, fr0
double_prec
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,361 | sim/testsuite/sh/clip.s | # sh testcase for clips, clipu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
clips_b:
set_grs_a5a5
clips.b r1
test_gr0_a5a5
assertreg 0xffffff80 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
clipu_b:
set_grs_a5a5
clipu.b r1
test_gr0_a5a5
assertreg 0xff r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
clips_w:
set_grs_a5a5
clips.w r1
test_gr0_a5a5
assertreg 0xffff8000 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
clipu_w:
set_grs_a5a5
clipu.w r1
test_gr0_a5a5
assertreg 0xffff r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,247 | sim/testsuite/sh/add.s | # sh testcase for add
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 1
_y: .long 1
start
add_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
add r1, r2
test_gr0_a5a5
assertreg 2 r1
assertreg 4 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
add_reg_reg_indirect:
set_grs_a5a5
mov.l x, r1
mov.l y, r2
mov.l @r1, r1
mov.l @r2, r2
add r1, r2
test_gr0_a5a5
assertreg 1 r1
assertreg 2 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
add_imm_reg:
set_grs_a5a5
add #0x16, r1
test_gr0_a5a5
assertreg 0xa5a5a5bb r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
.align 2
x: .long _x
y: .long _y
i: .long 2
j: .long 2
|
tactcomplabs/xbgas-binutils-gdb | 1,326 | sim/testsuite/sh/fmac.s | # sh testcase for fmac
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fmac_:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * x + y = y.
fldi0 fr0
fldi1 fr1
fldi1 fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fcmp/eq fr0, fr2
bt .L0
fail
.L0:
# x * y + 0.0 = x * y.
fldi1 fr0
fldi1 fr1
fldi0 fr2
# double it.
fadd fr1, fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
fadd fr0, fr0
fcmp/eq fr0, fr2
bt .L1
fail
.L1:
# x * 0.0 + y = y.
fldi1 fr0
fldi0 fr1
fldi1 fr2
fadd fr2, fr2
fmac fr0, fr1, fr2
# check result.
fldi1 fr0
# double fr0.
fadd fr0, fr0
fcmp/eq fr0, fr2
bt .L2
fail
.L2:
# x * 0.0 + 0.0 = 0.0
fldi1 fr0
fadd fr0, fr0
fldi0 fr1
fldi0 fr2
fmac fr0, fr1, fr2
# check result.
fldi0 fr0
fcmp/eq fr0, fr2
bt .L3
fail
.L3:
# 0.0 * x + 0.0 = 0.0.
fldi0 fr0
fldi1 fr1
# double it.
fadd fr1, fr1
fldi0 fr2
fmac fr0, fr1, fr2
# check result.
fldi0 fr0
fcmp/eq fr0, fr2
bt .L4
fail
.L4:
test_grs_a5a5
assert_fpreg_i 0, fr0
assert_fpreg_i 2, fr1
assert_fpreg_i 0, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,643 | sim/testsuite/sh/fcmpgt.s | # sh testcase for fcmpgt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpgt_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L0
fail
.L0:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt .L1
fail
.L1:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr1
fcmp/gt fr0, fr1
bf .L2
fail
.L2:
# 2.0 > 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fcmpgt_double:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L10
fail
.L10:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bt .L11
fail
.L11:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L12
fail
.L12:
# 2.0 > 1.0.
fldi1 fr0
single_prec
fadd fr0, fr0
double_prec
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,387 | sim/testsuite/sh/bclr.s | # sh testcase for bclr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xffffffff
_y: .long 0x55555555
start
bclr_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bclr.b #0, @(3, r1)
assertmem _x, 0xfffffffe
bclr.b #1, @(3, r1)
assertmem _x, 0xfffffffc
bclr.b #2, @(3, r1)
assertmem _x, 0xfffffff8
bclr.b #3, @(3, r1)
assertmem _x, 0xfffffff0
bclr.b #4, @(3, r1)
assertmem _x, 0xffffffe0
bclr.b #5, @(3, r1)
assertmem _x, 0xffffffc0
bclr.b #6, @(3, r1)
assertmem _x, 0xffffff80
bclr.b #7, @(3, r1)
assertmem _x, 0xffffff00
bclr.b #0, @(2, r1)
assertmem _x, 0xfffffe00
bclr.b #1, @(2, r1)
assertmem _x, 0xfffffc00
bclr.b #2, @(2, r1)
assertmem _x, 0xfffff800
bclr.b #3, @(2, r1)
assertmem _x, 0xfffff000
bra .L2
nop
.align 2
x: .long _x
y: .long _y
.L2:
bclr.b #4, @(2, r1)
assertmem _x, 0xffffe000
bclr.b #5, @(2, r1)
assertmem _x, 0xffffc000
bclr.b #6, @(2, r1)
assertmem _x, 0xffff8000
bclr.b #7, @(2, r1)
assertmem _x, 0xffff0000
bclr.b #0, @(1, r1)
assertmem _x, 0xfffe0000
bclr.b #1, @(1, r1)
assertmem _x, 0xfffc0000
bclr.b #2, @(1, r1)
assertmem _x, 0xfff80000
bclr.b #3, @(1, r1)
assertmem _x, 0xfff00000
bclr.b #4, @(1, r1)
assertmem _x, 0xffe00000
bclr.b #5, @(1, r1)
assertmem _x, 0xffc00000
bclr.b #6, @(1, r1)
assertmem _x, 0xff800000
bclr.b #7, @(1, r1)
assertmem _x, 0xff000000
bclr.b #0, @(0, r1)
assertmem _x, 0xfe000000
bclr.b #1, @(0, r1)
assertmem _x, 0xfc000000
bclr.b #2, @(0, r1)
assertmem _x, 0xf8000000
bclr.b #3, @(0, r1)
assertmem _x, 0xf0000000
bclr.b #4, @(0, r1)
assertmem _x, 0xe0000000
bclr.b #5, @(0, r1)
assertmem _x, 0xc0000000
bclr.b #6, @(0, r1)
assertmem _x, 0x80000000
bclr.b #7, @(0, r1)
assertmem _x, 0x00000000
assertreg _x, r1
bclr_imm_reg:
set_greg 0xff, r1
bclr #0, r1
assertreg 0xfe, r1
bclr #1, r1
assertreg 0xfc, r1
bclr #2, r1
assertreg 0xf8, r1
bclr #3, r1
assertreg 0xf0, r1
bclr #4, r1
assertreg 0xe0, r1
bclr #5, r1
assertreg 0xc0, r1
bclr #6, r1
assertreg 0x80, r1
bclr #7, r1
assertreg 0x00, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 4,107 | sim/testsuite/sh/resbank.s | # sh testcase for ldbank stbank resbank
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.macro SEND reg bankno regno
set_greg ((\bankno << 7) + (\regno << 2)), \reg
.endm
start
stbank_1:
set_grs_a5a5
mov #0, r0
SEND r1, 0, 0
stbank r0, @r1
mov #1, r0
SEND r1, 0, 1
stbank r0, @r1
mov #2, r0
SEND r1, 0, 2
stbank r0, @r1
mov #3, r0
SEND r1, 0, 3
stbank r0, @r1
mov #4, r0
SEND r1, 0, 4
stbank r0, @r1
mov #5, r0
SEND r1, 0, 5
stbank r0, @r1
mov #6, r0
SEND r1, 0, 6
stbank r0, @r1
mov #7, r0
SEND r1, 0, 7
stbank r0, @r1
mov #8, r0
SEND r1, 0, 8
stbank r0, @r1
mov #9, r0
SEND r1, 0, 9
stbank r0, @r1
mov #10, r0
SEND r1, 0, 10
stbank r0, @r1
mov #11, r0
SEND r1, 0, 11
stbank r0, @r1
mov #12, r0
SEND r1, 0, 12
stbank r0, @r1
mov #13, r0
SEND r1, 0, 13
stbank r0, @r1
mov #14, r0
SEND r1, 0, 14
stbank r0, @r1
mov #15, r0
SEND r1, 0, 15
stbank r0, @r1
mov #16, r0
SEND r1, 0, 16
stbank r0, @r1
mov #17, r0
SEND r1, 0, 17
stbank r0, @r1
mov #18, r0
SEND r1, 0, 18
stbank r0, @r1
mov #19, r0
SEND r1, 0, 19
stbank r0, @r1
assertreg0 19
assertreg 19 << 2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
ldbank_1:
set_grs_a5a5
SEND r1, 0, 0
ldbank @r1, r0
assertreg0 0
SEND r1, 0, 1
ldbank @r1, r0
assertreg0 1
SEND r1, 0, 2
ldbank @r1, r0
assertreg0 2
SEND r1, 0, 3
ldbank @r1, r0
assertreg0 3
SEND r1, 0, 4
ldbank @r1, r0
assertreg0 4
SEND r1, 0, 5
ldbank @r1, r0
assertreg0 5
SEND r1, 0, 6
ldbank @r1, r0
assertreg0 6
SEND r1, 0, 7
ldbank @r1, r0
assertreg0 7
SEND r1, 0, 8
ldbank @r1, r0
assertreg0 8
SEND r1, 0, 9
ldbank @r1, r0
assertreg0 9
SEND r1, 0, 10
ldbank @r1, r0
assertreg0 10
SEND r1, 0, 11
ldbank @r1, r0
assertreg0 11
SEND r1, 0, 12
ldbank @r1, r0
assertreg0 12
SEND r1, 0, 13
ldbank @r1, r0
assertreg0 13
SEND r1, 0, 14
ldbank @r1, r0
assertreg0 14
SEND r1, 0, 15
ldbank @r1, r0
assertreg0 15
SEND r1, 0, 16
ldbank @r1, r0
assertreg0 16
SEND r1, 0, 17
ldbank @r1, r0
assertreg0 17
SEND r1, 0, 18
ldbank @r1, r0
assertreg0 18
SEND r1, 0, 19
ldbank @r1, r0
assertreg0 19
assertreg (19 << 2), r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
resbank_1:
set_grs_a5a5
mov #1, r0
trapa #13 ! magic trap, sets ibnr
resbank
assertreg0 0
assertreg 1, r1
assertreg 2, r2
assertreg 3, r3
assertreg 4, r4
assertreg 5, r5
assertreg 6, r6
assertreg 7, r7
assertreg 8, r8
assertreg 9, r9
assertreg 10, r10
assertreg 11, r11
assertreg 12, r12
assertreg 13, r13
assertreg 14, r14
assert_sreg 15, mach
assert_sreg 17, pr
assert_creg 18, gbr
assert_sreg 19, macl
resbank_2:
set_grs_a5a5
movi20 #555, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
add #-1, r0
mov.l r0, @-r15
set_sr_bit (1 << 14) ! set BO
resbank
assert_sreg 555, macl
assert_sreg 554, mach
assert_creg 553, gbr
assert_sreg 552, pr
assertreg 551, r14
assertreg 550, r13
assertreg 549, r12
assertreg 548, r11
assertreg 547, r10
assertreg 546, r9
assertreg 545, r8
assertreg 544, r7
assertreg 543, r6
assertreg 542, r5
assertreg 541, r4
assertreg 540, r3
assertreg 539, r2
assertreg 538, r1
assertreg0 537
mov r15, r0
assertreg0 stackt
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,318 | sim/testsuite/sh/shll.s | # sh testcase for shll
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll:
set_grs_a5a5
mov #1, r1
shll r1
assertreg 2, r1
shll r1
assertreg 4, r1
shll r1
assertreg 8, r1
shll r1
assertreg 16, r1
shll r1
assertreg 32, r1
shll r1
assertreg 64, r1
shll r1
assertreg 0x80, r1
shll r1
assertreg 0x100, r1
shll r1
assertreg 0x200, r1
shll r1
assertreg 0x400, r1
shll r1
assertreg 0x800, r1
shll r1
assertreg 0x1000, r1
shll r1
assertreg 0x2000, r1
shll r1
assertreg 0x4000, r1
shll r1
assertreg 0x8000, r1
shll r1
assertreg 0x10000, r1
shll r1
assertreg 0x20000, r1
shll r1
assertreg 0x40000, r1
shll r1
assertreg 0x80000, r1
shll r1
assertreg 0x100000, r1
shll r1
assertreg 0x200000, r1
shll r1
assertreg 0x400000, r1
shll r1
assertreg 0x800000, r1
shll r1
assertreg 0x1000000, r1
shll r1
assertreg 0x2000000, r1
shll r1
assertreg 0x4000000, r1
shll r1
assertreg 0x8000000, r1
shll r1
assertreg 0x10000000, r1
shll r1
assertreg 0x20000000, r1
shll r1
assertreg 0x40000000, r1
shll r1
assertreg 0x80000000, r1
shll r1
assertreg 0, r1
shll r1
assertreg 0, r1
# another:
mov #1, r1
shll r1
shll r1
shll r1
assertreg 8, r1
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,730 | sim/testsuite/sh/fsca.s | # sh testcase for fsca
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsca:
set_grs_a5a5
set_fprs_a5a5
# Start with angle zero
mov.l zero, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
mov.l plus_90, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 1, fr2
assert_fpreg_i 0, fr3
mov.l plus_180, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i -1, fr3
mov.l plus_270, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i -1, fr2
assert_fpreg_i 0, fr3
mov.l plus_360, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
mov.l minus_90, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i -1, fr2
assert_fpreg_i 0, fr3
mov.l minus_180, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i -1, fr3
mov.l minus_270, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 1, fr2
assert_fpreg_i 0, fr3
mov.l minus_360, r0
lds r0, fpul
fsca fpul, dr2
assert_fpreg_i 0, fr2
assert_fpreg_i 1, fr3
assertreg0 0xffff0000
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
test_fpr_a5a5 fr0
test_fpr_a5a5 fr1
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
.align 2
zero: .long 0
one_bitty: .long 1
plus_90: .long 0x04000
plus_180: .long 0x08000
plus_270: .long 0x0c000
plus_360: .long 0x10000
minus_90: .long 0xffffc000
minus_180: .long 0xffff8000
minus_270: .long 0xffff4000
minus_360: .long 0xffff0000
minus_1_bitty: .long 0xffffffff
|
tactcomplabs/xbgas-binutils-gdb | 2,256 | sim/testsuite/sh/bst.s | # sh testcase for bst
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bst_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bst.b #0, @(3, r1)
assertmem _x, 0x1
bst.b #1, @(3, r1)
assertmem _x, 0x3
bst.b #2, @(3, r1)
assertmem _x, 0x7
bst.b #3, @(3, r1)
assertmem _x, 0xf
bst.b #4, @(3, r1)
assertmem _x, 0x1f
bst.b #5, @(3, r1)
assertmem _x, 0x3f
bst.b #6, @(3, r1)
assertmem _x, 0x7f
bst.b #7, @(3, r1)
assertmem _x, 0xff
bst.b #0, @(2, r1)
assertmem _x, 0x1ff
bst.b #1, @(2, r1)
assertmem _x, 0x3ff
bst.b #2, @(2, r1)
assertmem _x, 0x7ff
bst.b #3, @(2, r1)
assertmem _x, 0xfff
bra .L2
nop
.align 2
x: .long _x
y: .long _y
.L2:
bst.b #4, @(2, r1)
assertmem _x, 0x1fff
bst.b #5, @(2, r1)
assertmem _x, 0x3fff
bst.b #6, @(2, r1)
assertmem _x, 0x7fff
bst.b #7, @(2, r1)
assertmem _x, 0xffff
bst.b #0, @(1, r1)
assertmem _x, 0x1ffff
bst.b #1, @(1, r1)
assertmem _x, 0x3ffff
bst.b #2, @(1, r1)
assertmem _x, 0x7ffff
bst.b #3, @(1, r1)
assertmem _x, 0xfffff
bst.b #4, @(1, r1)
assertmem _x, 0x1fffff
bst.b #5, @(1, r1)
assertmem _x, 0x3fffff
bst.b #6, @(1, r1)
assertmem _x, 0x7fffff
bst.b #7, @(1, r1)
assertmem _x, 0xffffff
bst.b #0, @(0, r1)
assertmem _x, 0x1ffffff
bst.b #1, @(0, r1)
assertmem _x, 0x3ffffff
bst.b #2, @(0, r1)
assertmem _x, 0x7ffffff
bst.b #3, @(0, r1)
assertmem _x, 0xfffffff
bst.b #4, @(0, r1)
assertmem _x, 0x1fffffff
bst.b #5, @(0, r1)
assertmem _x, 0x3fffffff
bst.b #6, @(0, r1)
assertmem _x, 0x7fffffff
bst.b #7, @(0, r1)
assertmem _x, 0xffffffff
assertreg _x, r1
bst_imm_reg:
set_greg 0, r1
bst #0, r1
assertreg 0x1, r1
bst #1, r1
assertreg 0x3, r1
bst #2, r1
assertreg 0x7, r1
bst #3, r1
assertreg 0xf, r1
bst #4, r1
assertreg 0x1f, r1
bst #5, r1
assertreg 0x3f, r1
bst #6, r1
assertreg 0x7f, r1
bst #7, r1
assertreg 0xff, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,609 | sim/testsuite/sh/fabs.s | # sh testcase for fabs
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fabs_freg_b0:
single_prec
bank0
set_grs_a5a5
set_fprs_a5a5
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L3
fail
.L3:
test_grs_a5a5
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fabs_dreg_b0:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# fabs(0.0) = 0.0.
fldi0 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 0 dr0
# fabs(1.0) = 1.0.
fldi1 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L4
fail
.L4:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L5
fail
.L5:
test_grs_a5a5
assert_dpreg_i 1 dr0
assert_dpreg_i 1 dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,325 | sim/testsuite/sh/and.s | # sh testcase for and
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
and_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
and r1, r2
test_gr0_a5a5
assertreg 0xa5a5a5a5 r1
assertreg 0xa0a0a0a0 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra and_imm_reg
nop
.align 2
i: .long 0xa5a5a5a5
j: .long 0xaaaaaaaa
and_imm_reg:
set_grs_a5a5
and #0xff, r0
assertreg 0xa5, r0
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
and_b_imm_ind:
set_grs_a5a5
mov.l x, r0
and.b #0x55, @(r0, GBR)
mov.l @r0, r0
assertreg 0xa5a5a505, r0
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
.align 2
x: .long _x
y: .long _y
|
tactcomplabs/xbgas-binutils-gdb | 1,715 | sim/testsuite/sh/fsqrt.s | # sh testcase for fsqrt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsqrt_single:
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
fsqrt fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# sqrt(1.0) = 1.0.
fldi1 fr0
fsqrt fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# sqrt(4.0) = 2.0
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
fsqrt fr0
fldi1 fr1
# Double it.
fadd fr1, fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 2, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fsqrt_double:
double_prec
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
_s2d fr0, dr0
fsqrt dr0
fldi0 fr2
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# sqrt(1.0) = 1.0.
fldi1 fr0
_s2d fr0, dr0
fsqrt dr0
fldi1 fr2
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# sqrt(4.0) = 2.0.
fldi1 fr0
# Double it.
single_prec
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
double_prec
_s2d fr0, dr0
fsqrt dr0
fldi1 fr2
# Double it.
single_prec
fadd fr2, fr2
double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L12
fail
.L12:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 2, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,169 | sim/testsuite/sh/float.s | # sh testcase for float
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
float_pos:
set_grs_a5a5
set_fprs_a5a5
single_prec
mov #3, r0
lds r0, fpul
float fpul, fr2
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fcmp/eq fr1, fr2
bt float_neg
fail
float_neg:
mov #3, r0
neg r0, r0
lds r0, fpul
float fpul, fr2
# Check the result.
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
assertreg0 -3
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
assert_fpreg_i 1, fr0
assert_fpreg_i -3, fr1
assert_fpreg_i -3, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
double_pos:
set_grs_a5a5
set_fprs_a5a5
double_prec
mov #3, r0
lds r0, fpul
float fpul, dr4
# check the result.
fldi1 fr0
fldi1 fr1
single_prec
fadd fr0, fr1
fadd fr0, fr1
double_prec
_s2d fr1, dr2
fcmp/eq dr2, dr4
bt double_neg
fail
double_neg:
double_prec
mov #3, r0
neg r0, r0
lds r0, fpul
float fpul, dr4
# check the result.
fldi1 fr0
fldi1 fr1
single_prec
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
double_prec
_s2d fr1, dr2
fcmp/eq dr2, dr4
bt .L2
fail
.L2:
assertreg0 -3
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
single_prec
assert_fpreg_i 1, fr0
assert_fpreg_i -3, fr1
double_prec
assert_dpreg_i -3, dr2
assert_dpreg_i -3, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,323 | sim/testsuite/sh/ftrc.s | # sh testcase for ftrc
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
ftrc_single:
set_grs_a5a5
set_fprs_a5a5
# ftrc(0.0) = 0.
fldi0 fr0
ftrc fr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L0
fail
.L0:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr1
fldi1 fr2
# double it.
fadd fr2, fr2
# form the fraction.
fdiv fr2, fr1
fadd fr1, fr0
# now we've got 1.5 in fr0.
ftrc fr0, fpul
# check results.
mov #1, r0
sts fpul, r1
cmp/eq r0, r1
bt .L1
fail
.L1:
# ftrc(-1.5) = -1.
fldi1 fr0
fneg fr0
fldi1 fr1
fldi1 fr2
# double it.
fadd fr2, fr2
# form the fraction.
fdiv fr2, fr1
fneg fr1
# -1 + -0.5 = -1.5.
fadd fr1, fr0
# now we've got 1.5 in fr0.
ftrc fr0, fpul
# check results.
mov #1, r0
neg r0, r0
sts fpul, r1
cmp/eq r0, r1
bt ftrc_double
fail
ftrc_double:
double_prec
# ftrc(0.0) = 0.
fldi0 fr0
_s2d fr0, dr0
ftrc dr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L10
fail
.L10:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr2
fldi1 fr4
# double it.
single_prec
fadd fr4, fr4
# form 0.5.
fdiv fr4, fr2
fadd fr2, fr0
double_prec
# now we've got 1.5 in fr0, so do some single->double
# conversions and perform the ftrc.
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
ftrc dr0, fpul
# check results.
mov #1, r0
sts fpul, r1
cmp/eq r0, r1
bt .L11
fail
.L11:
# ftrc(-1.5) = -1.
fldi1 fr0
fneg fr0
fldi1 fr2
fldi1 fr4
single_prec
# double it.
fadd fr4, fr4
# form the fraction.
fdiv fr4, fr2
fneg fr2
# -1 + -0.5 = -1.5.
fadd fr2, fr0
double_prec
# now we've got 1.5 in fr0, so do some single->double
# conversions and perform the ftrc.
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
ftrc dr0, fpul
# check results.
mov #1, r0
neg r0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L12
fail
.L12:
assertreg0 -1
assertreg -1, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
assert_dpreg_i 2, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,896 | sim/testsuite/sh/pshli.s | # sh testcase for pshl <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_imm: ! shift logical, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, a0
pshl #0, a0
assert_sreg 0x10000, a0
pshl #-0, a0
assert_sreg 0x10000, a0
pshl #1, a0
assert_sreg 0x20000, a0
pshl #-1, a0
assert_sreg 0x10000, a0
pshl #2, a0
assert_sreg 0x40000, a0
pshl #-2, a0
assert_sreg 0x10000, a0
pshl #3, a0
assert_sreg 0x80000, a0
pshl #-3, a0
assert_sreg 0x10000, a0
pshl #4, a0
assert_sreg 0x100000, a0
pshl #-4, a0
assert_sreg 0x10000, a0
pshl #5, a0
assert_sreg 0x200000, a0
pshl #-5, a0
assert_sreg 0x10000, a0
pshl #6, a0
assert_sreg 0x400000, a0
pshl #-6, a0
assert_sreg 0x10000, a0
pshl #7, a0
assert_sreg 0x800000, a0
pshl #-7, a0
assert_sreg 0x10000, a0
pshl #8, a0
assert_sreg 0x1000000, a0
pshl #-8, a0
assert_sreg 0x10000, a0
pshl #9, a0
assert_sreg 0x2000000, a0
pshl #-9, a0
assert_sreg 0x10000, a0
pshl #10, a0
assert_sreg 0x4000000, a0
pshl #-10, a0
assert_sreg 0x10000, a0
pshl #11, a0
assert_sreg 0x8000000, a0
pshl #-11, a0
assert_sreg 0x10000, a0
pshl #12, a0
assert_sreg 0x10000000, a0
pshl #-12, a0
assert_sreg 0x10000, a0
pshl #13, a0
assert_sreg 0x20000000, a0
pshl #-13, a0
assert_sreg 0x10000, a0
pshl #14, a0
assert_sreg 0x40000000, a0
pshl #-14, a0
assert_sreg 0x10000, a0
pshl #15, a0
assert_sreg 0x80000000, a0
pshl #-15, a0
assert_sreg 0x10000, a0
pshl #16, a0
assert_sreg 0x00000000, a0
pshl #-16, a0
assert_sreg 0x0, a0
test_grs_a5a5
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,142 | sim/testsuite/sh/movi.s | # sh testcase for all mov <#imm> instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
mov_i_reg: # Test <imm8>
set_grs_a5a5
mov #-0x55, r1
assertreg 0xffffffab, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movi20_reg: # Test <imm20>
set_grs_a5a5
movi20 #-0x55555,r1
assertreg 0xfffaaaab, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
movi20s_reg: # Test <imm20> << 8
set_grs_a5a5
movi20s #-0x5555500,r1
assertreg 0xfaaaab00, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,484 | sim/testsuite/sh/bldnot.s | # sh testcase for bldnot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bldnot_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bldnot.b #0, @(0, r1)
bt8k mfail
bldnot.b #1, @(0, r1)
bf8k mfail
bldnot.b #2, @(0, r1)
bt8k mfail
bldnot.b #3, @(0, r1)
bf8k mfail
bldnot.b #4, @(0, r1)
bf8k mfail
bldnot.b #5, @(0, r1)
bt8k mfail
bldnot.b #6, @(0, r1)
bf8k mfail
bldnot.b #7, @(0, r1)
bt8k mfail
bldnot.b #0, @(1, r1)
bt8k mfail
bldnot.b #1, @(1, r1)
bf8k mfail
bldnot.b #2, @(1, r1)
bt8k mfail
bldnot.b #3, @(1, r1)
bf8k mfail
bldnot.b #4, @(1, r1)
bf8k mfail
bldnot.b #5, @(1, r1)
bt8k mfail
bldnot.b #6, @(1, r1)
bf8k mfail
bldnot.b #7, @(1, r1)
bt8k mfail
bldnot.b #0, @(2, r1)
bt8k mfail
bldnot.b #1, @(2, r1)
bf8k mfail
bldnot.b #2, @(2, r1)
bt8k mfail
bldnot.b #3, @(2, r1)
bf8k mfail
bldnot.b #4, @(2, r1)
bf8k mfail
bldnot.b #5, @(2, r1)
bt8k mfail
bldnot.b #6, @(2, r1)
bf8k mfail
bldnot.b #7, @(2, r1)
bt8k mfail
bldnot.b #0, @(3, r1)
bt8k mfail
bldnot.b #1, @(3, r1)
bf8k mfail
bldnot.b #2, @(3, r1)
bt8k mfail
bldnot.b #3, @(3, r1)
bf8k mfail
bldnot.b #4, @(3, r1)
bf8k mfail
bldnot.b #5, @(3, r1)
bt8k mfail
bldnot.b #6, @(3, r1)
bf8k mfail
bldnot.b #7, @(3, r1)
bt8k mfail
assertreg _x, r1
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
.align 2
x: .long _x
y: .long _y
|
tactcomplabs/xbgas-binutils-gdb | 2,717 | sim/testsuite/sh/movua.s | # sh testcase for movua
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movua_1:
set_grs_a5a5
mov.l srcp, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x04030201
.else
assertreg0 0x01020304
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x05040302
.else
assertreg0 0x02030405
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x06050403
.else
assertreg0 0x03040506
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x07060504
.else
assertreg0 0x04050607
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x08070605
.else
assertreg0 0x05060708
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x09080706
.else
assertreg0 0x06070809
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0a090807
.else
assertreg0 0x0708090a
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0b0a0908
.else
assertreg0 0x08090a0b
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0c0b0a09
.else
assertreg0 0x090a0b0c
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0d0c0b0a
.else
assertreg0 0x0a0b0c0d
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0e0d0c0b
.else
assertreg0 0x0b0c0d0e
.endif
add #1, r1
movua.l @r1, r0
.ifdef LITTLE
assertreg0 0x0f0e0d0c
.else
assertreg0 0x0c0d0e0f
.endif
assertreg src+12, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
bra movua_4:
nop
.align 0
src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
.align 2
srcp: .long src
movua_4:
set_grs_a5a5
mov.l srcp2, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x03020100
.else
assertreg0 0x00010203
.endif
assertreg src+4, r1
mov.l srcp2, r1
add #1, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x04030201
.else
assertreg0 0x01020304
.endif
assertreg src+5, r1
mov.l srcp2, r1
add #2, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x05040302
.else
assertreg0 0x02030405
.endif
assertreg src+6, r1
mov.l srcp2, r1
add #3, r1
movua.l @r1+, r0
.ifdef LITTLE
assertreg0 0x06050403
.else
assertreg0 0x03040506
.endif
assertreg src+7, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
srcp2: .long src
|
tactcomplabs/xbgas-binutils-gdb | 1,585 | sim/testsuite/sh/fneg.s | # sh testcase for fneg
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fneg_single:
set_grs_a5a5
set_fprs_a5a5
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr1
fneg fr0
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# neg(1.0) = fsub(0,1)
fldi1 fr0
fneg fr0
fldi0 fr1
fldi1 fr2
fsub fr2, fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# neg(neg(1.0)) = 1.0.
fldi1 fr0
fldi1 fr1
fneg fr0
fneg fr0
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
test_grs_a5a5
assert_fpreg_i 1, fr0
assert_fpreg_i 1, fr1
assert_fpreg_i 1, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fneg_double:
set_grs_a5a5
set_fprs_a5a5
double_prec
# neg(0.0) = 0.0.
fldi0 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fneg dr0
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# neg(1.0) = fsub(0,1)
fldi1 fr0
_s2d fr0, dr0
fneg dr0
fldi0 fr2
fldi1 fr3
single_prec
fsub fr3, fr2
double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# neg(neg(1.0)) = 1.0.
fldi1 fr0
_s2d fr0, dr0
fldi1 fr2
_s2d fr2, dr2
fneg dr2
fneg dr2
fcmp/eq dr0, dr2
bt .L12
fail
.L12:
test_grs_a5a5
assert_dpreg_i 1, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,619 | sim/testsuite/sh/mulr.s | # sh testcase for mulr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
mulr_1: ! multiply by one
set_grs_a5a5
mov #1, r0
mulr r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_2: ! multiply by two
set_grs_a5a5
mov #2, r0
mov #12, r1
mulr r0, r1
assertreg0 2
assertreg 24, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_3: ! multiply five by five
set_grs_a5a5
mov #5, r0
mov #5, r1
mulr r0, r1
assertreg0 5
assertreg 25, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_4: ! multiply 127 by 127
set_grs_a5a5
mov #127, r0
mov #127, r1
mulr r0, r1
assertreg0 127
assertreg 0x3f01, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_5: ! multiply -1 by -1
set_grs_a5a5
mov #-1, r0
mov #-1, r1
mulr r0, r1
assertreg0 -1
assertreg 1, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_6: ! multiply 46340 by 46340
set_grs_a5a5
movi20 #46340, r0
movi20 #46340, r1
mulr r0, r1
assertreg0 46340
assertreg 0x7ffea810, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
mulr_7: ! multiply 7ffff by 7ffff (overflow)
set_grs_a5a5
movi20 #0x7ffff, r0
movi20 #0x7ffff, r1
mulr r0, r1
assertreg0 0x7ffff
assertreg 0xfff00001, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,665 | sim/testsuite/sh/fmul.s | # sh testcase for fmul
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.macro init
fldi0 fr0
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
.endm
start
fmul_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 * 0.0 = 0.0.
init
fmul fr0, fr0
assert_fpreg_i 0, fr0
# 0.0 * 1.0 = 0.0.
init
fmul fr1, fr0
assert_fpreg_i 0, fr0
# 1.0 * 0.0 = 0.0.
init
fmul fr0, fr1
assert_fpreg_i 0, fr1
# 1.0 * 1.0 = 1.0.
init
fmul fr1, fr1
assert_fpreg_i 1, fr1
# 2.0 * 1.0 = 2.0.
init
fmul fr2, fr1
assert_fpreg_i 2, fr1
test_grs_a5a5
assert_fpreg_i 0, fr0
assert_fpreg_i 2, fr1
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
.macro dinit
fldi0 fr0
fldi1 fr2
fldi1 fr4
single_prec
fadd fr4, fr4
double_prec
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
.endm
fmul_double:
double_prec
# 0.0 * 0.0 = 0.0.
dinit
fmul dr0, dr0
assert_dpreg_i 0, dr0
# 0.0 * 1.0 = 0.0.
dinit
fmul dr2, dr0
assert_dpreg_i 0, dr0
# 1.0 * 0.0 = 0.0.
dinit
fmul dr0, dr2
assert_dpreg_i 0, dr2
# 1.0 * 1.0 = 1.0.
dinit
fmul dr2, dr2
assert_dpreg_i 1, dr2
# 2.0 * 1.0 = 2.0.
dinit
fmul dr4, dr2
assert_dpreg_i 2, dr2
test_grs_a5a5
assert_dpreg_i 0, dr0
assert_dpreg_i 2, dr2
assert_dpreg_i 2, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,985 | sim/testsuite/sh/pswap.s | # sh testcase for pswap
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pswapx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
pswap x0, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pswapy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, y0
pswap y0, x0
assert_sreg 0x7777a5a5, x0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, y0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pswapa:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, a0
pcopy a0, a1
pswap a1, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, a0
assert_sreg2 0xa5a57777, a1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pswapm:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, a0
pcopy a0, m1
pswap m1, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, a0
assert_sreg2 0xa5a57777, m1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
dct_pswapx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
set_dcfalse
dct pswap x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dctrue
dct pswap x0, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dcf_pswapy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_greg 0xa5a57777, r0
lds r0, x0
set_dctrue
dcf pswap x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dcfalse
dcf pswap x0, y0
assert_sreg 0x7777a5a5, y0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a57777, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 6,051 | sim/testsuite/sh/loop.s | # sh testcase for loop control
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
loop1:
set_grs_a5a5
ldrs Loop1_start0+8
ldre Loop1_start0+4
setrc #5
Loop1_start0:
add #1, r1 ! Before loop
# Loop should execute one instruction five times.
Loop1_begin:
add #1, r1 ! Within loop
Loop1_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
assertreg 0xa5a5a5a5+8, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop2:
set_grs_a5a5
ldrs Loop2_start0+6
ldre Loop2_start0+4
setrc #5
Loop2_start0:
add #1, r1 ! Before loop
# Loop should execute two instructions five times.
Loop2_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop2_end:
add #3, r1 ! After loop
# r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)
assertreg 0xa5a5a5a5+14, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop3:
set_grs_a5a5
ldrs Loop3_start0+4
ldre Loop3_start0+4
setrc #5
Loop3_start0:
add #1, r1 ! Before loop
# Loop should execute three instructions five times.
Loop3_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop3_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
assertreg 0xa5a5a5a5+18, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop4:
set_grs_a5a5
ldrs Loop4_begin
ldre Loop4_last3+4
setrc #5
add #1, r1 ! Before loop
# Loop should execute four instructions five times.
Loop4_begin:
Loop4_last3:
add #1, r1 ! Within loop
Loop4_last2:
add #1, r1 ! Within loop
Loop4_last1:
add #1, r1 ! Within loop
Loop4_last:
add #1, r1 ! Within loop
Loop4_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)
assertreg 0xa5a5a5a5+23, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop5:
set_grs_a5a5
ldrs Loop5_begin
ldre Loop5_last3+4
setrc #5
add #1, r1 ! Before loop
# Loop should execute five instructions five times.
Loop5_begin:
add #1, r1 ! Within loop
Loop5_last3:
add #1, r1 ! Within loop
Loop5_last2:
add #1, r1 ! Within loop
Loop5_last1:
add #1, r1 ! Within loop
Loop5_last:
add #1, r1 ! Within loop
Loop5_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)
assertreg 0xa5a5a5a5+28, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loopn:
set_grs_a5a5
ldrs Loopn_begin
ldre Loopn_last3+4
setrc #5
add #1, r1 ! Before loop
# Loop should execute n instructions five times.
Loopn_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loopn_last3:
add #1, r1 ! Within loop
Loopn_last2:
add #1, r1 ! Within loop
Loopn_last1:
add #1, r1 ! Within loop
Loopn_last:
add #1, r1 ! Within loop
Loopn_end:
add #3, r1 ! After loop
# r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)
assertreg 0xa5a5a5a5+64, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop1e:
set_grs_a5a5
ldrs Loop1e_begin
ldre Loop1e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute one instruction five times.
Loop1e_begin:
Loop1e_last:
add #1, r1 ! Within loop
Loop1e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
assertreg 0xa5a5a5a5+8, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop2e:
set_grs_a5a5
ldrs Loop2e_begin
ldre Loop2e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute two instructions five times.
Loop2e_begin:
add #1, r1 ! Within loop
Loop2e_last:
add #1, r1 ! Within loop
Loop2e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)
assertreg 0xa5a5a5a5+13, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop3e:
set_grs_a5a5
ldrs Loop3e_begin
ldre Loop3e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute three instructions five times.
Loop3e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop3e_last:
add #1, r1 ! Within loop
Loop3e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
assertreg 0xa5a5a5a5+18, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop4e:
set_grs_a5a5
ldrs Loop4e_begin
ldre Loop4e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute four instructions five times.
Loop4e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop4e_last:
add #1, r1 ! Within loop
Loop4e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)
assertreg 0xa5a5a5a5+23, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop5e:
set_grs_a5a5
ldrs Loop5e_begin
ldre Loop5e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute five instructions five times.
Loop5e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop5e_last:
add #1, r1 ! Within loop
Loop5e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)
assertreg 0xa5a5a5a5+28, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
loop_n_e:
set_grs_a5a5
ldrs Loop_n_e_begin
ldre Loop_n_e_last
ldrc #5
add #1, r1 ! Before loop
# Loop should execute n instructions five times.
Loop_n_e_begin:
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
add #1, r1 ! Within loop
Loop_n_e_last:
add #1, r1 ! Within loop
Loop_n_e_end:
add #2, r1 ! After loop
# r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)
assertreg 0xa5a5a5a5+48, r1
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,589 | sim/testsuite/sh/bld.s | # sh testcase for bld
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
_y: .long 0x55555555
start
bld_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bld.b #0, @(0, r1)
bf8k mfail
bld.b #1, @(0, r1)
bt8k mfail
bld.b #2, @(0, r1)
bf8k mfail
bld.b #3, @(0, r1)
bt8k mfail
bld.b #4, @(0, r1)
bt8k mfail
bld.b #5, @(0, r1)
bf8k mfail
bld.b #6, @(0, r1)
bt8k mfail
bld.b #7, @(0, r1)
bf8k mfail
bld.b #0, @(1, r1)
bf8k mfail
bld.b #1, @(1, r1)
bt8k mfail
bld.b #2, @(1, r1)
bf8k mfail
bld.b #3, @(1, r1)
bt8k mfail
bld.b #4, @(1, r1)
bt8k mfail
bld.b #5, @(1, r1)
bf8k mfail
bld.b #6, @(1, r1)
bt8k mfail
bld.b #7, @(1, r1)
bf8k mfail
bld.b #0, @(2, r1)
bf8k mfail
bld.b #1, @(2, r1)
bt8k mfail
bld.b #2, @(2, r1)
bf8k mfail
bld.b #3, @(2, r1)
bt8k mfail
bld.b #4, @(2, r1)
bt8k mfail
bld.b #5, @(2, r1)
bf8k mfail
bld.b #6, @(2, r1)
bt8k mfail
bld.b #7, @(2, r1)
bf8k mfail
bld.b #0, @(3, r1)
bf8k mfail
bld.b #1, @(3, r1)
bt8k mfail
bld.b #2, @(3, r1)
bf8k mfail
bld.b #3, @(3, r1)
bt8k mfail
bld.b #4, @(3, r1)
bt8k mfail
bld.b #5, @(3, r1)
bf8k mfail
bld.b #6, @(3, r1)
bt8k mfail
bld.b #7, @(3, r1)
bf8k mfail
assertreg _x, r1
bld_imm_reg:
set_greg 0xa5a5a5a5, r1
bld #0, r1
bf8k mfail
bld #1, r1
bt8k mfail
bld #2, r1
bf8k mfail
bld #3, r1
bt8k mfail
bld #4, r1
bt8k mfail
bld #5, r1
bf8k mfail
bld #6, r1
bt8k mfail
bld #7, r1
bf8k mfail
test_grs_a5a5
pass
exit 0
.align 2
x: .long _x
y: .long _y
|
tactcomplabs/xbgas-binutils-gdb | 1,557 | sim/testsuite/sh/fdiv.s | # sh testcase for fdiv
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fdiv_single:
# Single test
set_grs_a5a5
set_fprs_a5a5
single_prec
# 1.0 / 0.0 should be INF
# (and not crash the sim).
fldi0 fr0
fldi1 fr1
fdiv fr0, fr1
assert_fpreg_x 0x7f800000, fr1
# 0.0 / 1.0 == 0.0.
fldi0 fr0
fldi1 fr1
fdiv fr1, fr0
assert_fpreg_x 0, fr0
# 2.0 / 1.0 == 2.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr1, fr2
assert_fpreg_i 2, fr2
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr2, fr1
# fr1 should contain 0.5.
fadd fr1, fr1
assert_fpreg_i 1, fr1
test_grs_a5a5
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fdiv_double:
# Double test
set_grs_a5a5
set_fprs_a5a5
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
# This add must be in single precision. The rest must be in double.
fadd fr2, fr2
double_prec
_s2d fr1, dr0
_s2d fr2, dr2
fdiv dr2, dr0
# dr0 should contain 0.5.
# double it, expect 1.0.
fadd dr0, dr0
assert_dpreg_i 1, dr0
assert_dpreg_i 2, dr2
test_grs_a5a5
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,167 | sim/testsuite/sh/fadd.s | # sh testcase for fadd
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fadd_freg_freg_b0:
set_grs_a5a5
set_fprs_a5a5
bank0
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 2 fr1
fldi0 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
fldi1 fr0
fldi0 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
test_grs_a5a5
assert_fpreg_i 1 fr0
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fadd_dreg_dreg_b0:
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
fldi1 fr2
flds fr0, fpul
fcnvsd fpul, dr0
flds fr2, fpul
fcnvsd fpul, dr2
fadd dr0, dr2
fcnvds dr2, fpul
fsts fpul, fr0
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_dpreg_i 2, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 3,257 | sim/testsuite/sh/div.s | # sh testcase for divs and divu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
divs_1: ! divide by one
set_grs_a5a5
mov #1, r0
divs r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_2: ! divide by two
set_grs_a5a5
mov #2, r0
divs r0, r1
assertreg0 2
assertreg 0xd2d2d2d3, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_3: ! divide by three
set_grs_a5a5
mov #3, r0
divs r0, r1
assertreg0 3
assertreg 0xe1e1e1e2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_0: ! divide by zero
set_grs_a5a5
mov #0, r0
divs r0, r1
assertreg0 0
assertreg 0x7fffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_o: ! divide signed overflow
set_grs_a5a5
mov #16, r0
movi20 #0x8000, r1
shad r0, r1 ! r1 == 0x80000000
mov #-1, r0
divs r0, r1
assertreg0 -1
assertreg 0x7fffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_1: ! divide by one, unsigned
set_grs_a5a5
mov #1, r0
divu r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_2: ! divide by two, unsigned
set_grs_a5a5
mov #2, r0
divu r0, r1
assertreg0 2
assertreg 0x52d2d2d2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_3: ! divide by three, unsigned
set_grs_a5a5
mov #3, r0
divu r0, r1
assertreg0 3
assertreg 0x37373737, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_0: ! divide by zero, unsigned
set_grs_a5a5
mov #0, r0
divu r0, r1
assertreg0 0
assertreg 0xffffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,911 | sim/testsuite/sh/fsub.s | # sh testcase for fsub
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsub_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr1
fsub fr0, fr1
fldi1 fr2
fcmp/eq fr1, fr2
bt .L1
fail
.L1:
# 1.0 - 1.0 = 0.0.
fldi1 fr0
fldi1 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L2
fail
.L2:
# 0.0 - 1.0 = -1.0.
fldi1 fr0
fldi0 fr1
fsub fr0, fr1
fldi1 fr2
fneg fr2
fcmp/eq fr1, fr2
bt .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 1, fr0
assert_fpreg_i -1, fr1
assert_fpreg_i -1, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fsub_double:
set_grs_a5a5
set_fprs_a5a5
double_prec
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi0 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L10
fail
.L10:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi1 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L11
fail
.L11:
# 1.0 - 1.0 = 0.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi0 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L12
fail
.L12:
# 0.0 - 1.0 = -1.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi1 fr4
single_prec
fneg fr4
double_prec
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 1, dr0
assert_dpreg_i -1, dr2
assert_dpreg_i -1, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,433 | sim/testsuite/sh/prnd.s | # sh testcase for prnd
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
# FIXME: opcode table ambiguity in ignored bits 4-7.
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
# prnd(0xa5a5a5a5) = 0xa5a60000
prnd x0, x0
prnd y0, y0
assert_sreg 0xa5a60000, x0
assert_sreg 0xa5a60000, y0
# prnd(1) = 1
mov #1, r0
shll16 r0
lds r0, x0
pcopy x0, y0
prnd x0, x0
prnd y0, y0
assert_sreg 0x10000, x0
assert_sreg 0x10000, y0
# prnd(1.4999999) = 1
mov #1, r0
shll8 r0
or #0x7f, r0
shll8 r0
or #0xff, r0
lds r0, x0
pcopy x0, y0
prnd x0, x0
prnd y0, y0
assert_sreg 0x10000, x0
assert_sreg 0x10000, y0
# prnd(1.5) = 2
mov #1, r0
shll8 r0
or #0x80, r0
shll8 r0
lds r0, x0
pcopy x0, y0
prnd x0, x0
prnd y0, y0
assert_sreg 0x20000, x0
assert_sreg 0x20000, y0
# dct prnd
set_dcfalse
dct prnd x0, x1
dct prnd y0, y1
assert_sreg2 0xa5a5a5a5, x1
assert_sreg2 0xa5a5a5a5, y1
set_dctrue
dct prnd x0, x1
dct prnd y0, y1
assert_sreg2 0x20000, x1
assert_sreg2 0x20000, y1
# dcf prnd
set_dctrue
dcf prnd x0, m0
dcf prnd y0, m1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
set_dcfalse
dcf prnd x0, m0
dcf prnd y0, m1
assert_sreg2 0x20000, m0
assert_sreg2 0x20000, m1
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,568 | sim/testsuite/sh/pshlr.s | # sh testcase for pshl <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pshl_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x10000, x0
set_sreg 0x0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x10000, y0
pshl x0, y0, x0
assert_sreg 0x20000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x20000, y0
pshl x0, y0, x0
assert_sreg 0x40000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x30000, y0
pshl x0, y0, x0
assert_sreg 0x80000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x40000, y0
pshl x0, y0, x0
assert_sreg 0x100000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x50000, y0
pshl x0, y0, x0
assert_sreg 0x200000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x60000, y0
pshl x0, y0, x0
assert_sreg 0x400000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x70000, y0
pshl x0, y0, x0
assert_sreg 0x800000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x80000, y0
pshl x0, y0, x0
assert_sreg 0x1000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x90000, y0
pshl x0, y0, x0
assert_sreg 0x2000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xa0000, y0
pshl x0, y0, x0
assert_sreg 0x4000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xb0000, y0
pshl x0, y0, x0
assert_sreg 0x8000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xc0000, y0
pshl x0, y0, x0
assert_sreg 0x10000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xd0000, y0
pshl x0, y0, x0
assert_sreg 0x20000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xe0000, y0
pshl x0, y0, x0
assert_sreg 0x40000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0xf0000, y0
pshl x0, y0, x0
assert_sreg 0x80000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x10000, x0
set_sreg 0x100000, y0
pshl x0, y0, x0
assert_sreg 0x00000000, x0
pneg y0, y0
pshl x0, y0, x0
assert_sreg 0x0, x0
test_grs_a5a5
assert_sreg2 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,805 | sim/testsuite/sh/pinc.s | # sh testcase for pinc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pincx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pinc x0, y0
assert_sreg 0xa5a60000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pincy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pinc y0, x0
assert_sreg 0xa5a60000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dct_pincx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dcfalse
dct pinc x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dctrue
dct pinc x0, y0
assert_sreg 0xa5a60000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dcf_pincy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dctrue
dcf pinc y0, x0
assert_sreg 0xa5a5a5a5, x0
set_dcfalse
dcf pinc y0, x0
assert_sreg 0xa5a60000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,911 | sim/testsuite/sh/mov.s | # sh testcase for all mov.[bwl] instructions
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
.align 2
_lsrc: .long 0x55555555
_wsrc: .long 0x55550000
_bsrc: .long 0x55000000
.align 2
_ldst: .long 0
_wdst: .long 0
_bdst: .long 0
start
movb_disp12_reg: # Test 8-bit @(disp12,gr) -> gr
set_grs_a5a5
mov.l bsrc, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.b @(444,r1), r2
assertreg _bsrc-444, r1
assertreg 0x55, r2
movb_reg_disp12: # Test 8-bit gr -> @(disp12,gr)
set_grs_a5a5
mov.l bdst, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.b r2, @(444,r1)
assertreg _bdst-444, r1
assertmem _bdst, 0xa5000000
movw_disp12_reg: # Test 16-bit @(disp12,gr) -> gr
set_grs_a5a5
mov.l wsrc, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.w @(444,r1), r2
assertreg _wsrc-444, r1
assertreg 0x5555, r2
movw_reg_disp12: # Test 16-bit gr -> @(disp12,gr)
set_grs_a5a5
mov.l wdst, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.w r2, @(444,r1)
assertreg _wdst-444, r1
assertmem _wdst, 0xa5a50000
movl_disp12_reg: # Test 32-bit @(disp12,gr) -> gr
set_grs_a5a5
mov.l lsrc, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.l @(444,r1), r2
assertreg _lsrc-444, r1
assertreg 0x55555555, r2
movl_reg_disp12: # Test 32-bit gr -> @(disp12,gr)
set_grs_a5a5
mov.l ldst, r1
add #-111, r1
add #-111, r1
add #-111, r1
add #-111, r1
mov.l r2, @(444,r1)
assertreg _ldst-444, r1
assertmem _ldst, 0xa5a5a5a5
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
lsrc: .long _lsrc
wsrc: .long _wsrc
bsrc: .long _bsrc
ldst: .long _ldst
wdst: .long _wdst
bdst: .long _bdst
|
tactcomplabs/xbgas-binutils-gdb | 2,500 | sim/testsuite/sh/pushpop.s | # sh testcase for push/pop (mov,movml,movmu...) insns.
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
movml_1:
set_greg 0, r0
set_greg 1, r1
set_greg 2, r2
set_greg 3, r3
set_greg 4, r4
set_greg 5, r5
set_greg 6, r6
set_greg 7, r7
set_greg 8, r8
set_greg 9, r9
set_greg 10, r10
set_greg 11, r11
set_greg 12, r12
set_greg 13, r13
set_greg 14, r14
set_sreg 15, pr
movml.l r15,@-r15
assertmem stackt-4, 15
assertmem stackt-8, 14
assertmem stackt-12, 13
assertmem stackt-16, 12
assertmem stackt-20, 11
assertmem stackt-24, 10
assertmem stackt-28, 9
assertmem stackt-32, 8
assertmem stackt-36, 7
assertmem stackt-40, 6
assertmem stackt-44, 5
assertmem stackt-48, 4
assertmem stackt-52, 3
assertmem stackt-56, 2
assertmem stackt-60, 1
assertmem stackt-64, 0
assertreg0 0
assertreg 1, r1
assertreg 2, r2
assertreg 3, r3
assertreg 4, r4
assertreg 5, r5
assertreg 6, r6
assertreg 7, r7
assertreg 8, r8
assertreg 9, r9
assertreg 10, r10
assertreg 11, r11
assertreg 12, r12
assertreg 13, r13
assertreg 14, r14
mov r15, r0
assertreg0 stackt-64
movml_2:
set_grs_a5a5
movml.l @r15+, r15
assert_sreg 15, pr
assertreg0 0
assertreg 1, r1
assertreg 2, r2
assertreg 3, r3
assertreg 4, r4
assertreg 5, r5
assertreg 6, r6
assertreg 7, r7
assertreg 8, r8
assertreg 9, r9
assertreg 10, r10
assertreg 11, r11
assertreg 12, r12
assertreg 13, r13
assertreg 14, r14
mov r15, r0
assertreg0 stackt
movmu_1:
set_grs_a5a5
add #1,r14
add #2,r13
add #3,r12
set_sreg 0xa5a5,pr
movmu.l r12,@-r15
assert_sreg 0xa5a5,pr
assertreg 0xa5a5a5a6, r14
assertreg 0xa5a5a5a7, r13
assertreg 0xa5a5a5a8, r12
test_gr_a5a5 r11
test_gr_a5a5 r10
test_gr_a5a5 r9
test_gr_a5a5 r8
test_gr_a5a5 r7
test_gr_a5a5 r6
test_gr_a5a5 r5
test_gr_a5a5 r4
test_gr_a5a5 r3
test_gr_a5a5 r2
test_gr_a5a5 r1
test_gr_a5a5 r0
mov r15, r0
assertreg stackt-16, r0
assertmem stackt-4, 0xa5a5
assertmem stackt-8, 0xa5a5a5a6
assertmem stackt-12, 0xa5a5a5a7
assertmem stackt-16, 0xa5a5a5a8
movmu_2:
set_grs_a5a5
movmu.l @r15+,r12
assert_sreg 0xa5a5, pr
assertreg 0xa5a5a5a6, r14
assertreg 0xa5a5a5a7, r13
assertreg 0xa5a5a5a8, r12
test_gr_a5a5 r11
test_gr_a5a5 r10
test_gr_a5a5 r9
test_gr_a5a5 r8
test_gr_a5a5 r7
test_gr_a5a5 r6
test_gr_a5a5 r5
test_gr_a5a5 r4
test_gr_a5a5 r3
test_gr_a5a5 r2
test_gr_a5a5 r1
test_gr_a5a5 r0
mov r15, r0
assertreg stackt, r0
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,029 | sim/testsuite/sh/fsrra.s | # sh testcase for fsrra
# mach: sh
# as(sh): -defsym sim_cpu=0
# xerror: test hasn't been run in a long time
.include "testutils.inc"
start
fsrra_single:
set_grs_a5a5
set_fprs_a5a5
# 1/sqrt(0.0) = +infinity.
fldi0 fr0
fsrra fr0
assert_fpreg_x 0x7f800000, fr0
# 1/sqrt(1.0) = 1.0.
fldi1 fr0
fsrra fr0
assert_fpreg_i 1, fr0
# 1/sqrt(4.0) = 1/2.0
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
fsrra fr0
fldi1 fr2
# Double it.
fadd fr2, fr2
fldi1 fr1
# Divide
fdiv fr2, fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
# Double-check (pun intended)
fadd fr0, fr0
assert_fpreg_i 1, fr0
fadd fr1, fr1
assert_fpreg_i 1, fr1
# And make sure the rest of the regs are un-affected.
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
test_grs_a5a5
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 4,383 | sim/testsuite/sh/pshar.s | # sh testcase for psha <reg>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_reg: ! shift arithmetic, register operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, x0
set_sreg 0x0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x10000, y0
psha x0, y0, x0
assert_sreg 0x2, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x20000, y0
psha x0, y0, x0
assert_sreg 0x4, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x30000, y0
psha x0, y0, x0
assert_sreg 0x8, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x40000, y0
psha x0, y0, x0
assert_sreg 0x10, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x50000, y0
psha x0, y0, x0
assert_sreg 0x20, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x60000, y0
psha x0, y0, x0
assert_sreg 0x40, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x70000, y0
psha x0, y0, x0
assert_sreg 0x80, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x80000, y0
psha x0, y0, x0
assert_sreg 0x100, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x90000, y0
psha x0, y0, x0
assert_sreg 0x200, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xa0000, y0
psha x0, y0, x0
assert_sreg 0x400, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xb0000, y0
psha x0, y0, x0
assert_sreg 0x800, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xc0000, y0
psha x0, y0, x0
assert_sreg 0x1000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xd0000, y0
psha x0, y0, x0
assert_sreg 0x2000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xe0000, y0
psha x0, y0, x0
assert_sreg 0x4000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0xf0000, y0
psha x0, y0, x0
assert_sreg 0x8000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x100000, y0
psha x0, y0, x0
assert_sreg 0x10000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x110000, y0
psha x0, y0, x0
assert_sreg 0x20000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x120000, y0
psha x0, y0, x0
assert_sreg 0x40000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x130000, y0
psha x0, y0, x0
assert_sreg 0x80000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x140000, y0
psha x0, y0, x0
assert_sreg 0x100000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x150000, y0
psha x0, y0, x0
assert_sreg 0x200000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x160000, y0
psha x0, y0, x0
assert_sreg 0x400000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x170000, y0
psha x0, y0, x0
assert_sreg 0x800000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x180000, y0
psha x0, y0, x0
assert_sreg 0x1000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x190000, y0
psha x0, y0, x0
assert_sreg 0x2000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1a0000, y0
psha x0, y0, x0
assert_sreg 0x4000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1b0000, y0
psha x0, y0, x0
assert_sreg 0x8000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1c0000, y0
psha x0, y0, x0
assert_sreg 0x10000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1d0000, y0
psha x0, y0, x0
assert_sreg 0x20000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1e0000, y0
psha x0, y0, x0
assert_sreg 0x40000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0x1, x0
set_sreg 0x1f0000, y0
psha x0, y0, x0
assert_sreg 0x80000000, x0
pneg y0, y0
psha x0, y0, x0
assert_sreg 0xffffffff, x0
set_sreg 0x200000, y0
psha x0, y0, x0
assert_sreg 0x00000000, x0
# I don't grok what should happen here...
# pneg y0, y0
# psha x0, y0, x0
# assert_sreg 0x0, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,259 | sim/testsuite/sh/bset.s | # sh testcase for bset
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0
_y: .long 0x55555555
start
bset_b_imm_disp12_reg:
set_grs_a5a5
mov.l x, r1
bset.b #0, @(3, r1)
assertmem _x, 0x1
bset.b #1, @(3, r1)
assertmem _x, 0x3
bset.b #2, @(3, r1)
assertmem _x, 0x7
bset.b #3, @(3, r1)
assertmem _x, 0xf
bset.b #4, @(3, r1)
assertmem _x, 0x1f
bset.b #5, @(3, r1)
assertmem _x, 0x3f
bset.b #6, @(3, r1)
assertmem _x, 0x7f
bset.b #7, @(3, r1)
assertmem _x, 0xff
bset.b #0, @(2, r1)
assertmem _x, 0x1ff
bset.b #1, @(2, r1)
assertmem _x, 0x3ff
bset.b #2, @(2, r1)
assertmem _x, 0x7ff
bset.b #3, @(2, r1)
assertmem _x, 0xfff
bra .L2
nop
.align 2
x: .long _x
y: .long _y
.L2:
bset.b #4, @(2, r1)
assertmem _x, 0x1fff
bset.b #5, @(2, r1)
assertmem _x, 0x3fff
bset.b #6, @(2, r1)
assertmem _x, 0x7fff
bset.b #7, @(2, r1)
assertmem _x, 0xffff
bset.b #0, @(1, r1)
assertmem _x, 0x1ffff
bset.b #1, @(1, r1)
assertmem _x, 0x3ffff
bset.b #2, @(1, r1)
assertmem _x, 0x7ffff
bset.b #3, @(1, r1)
assertmem _x, 0xfffff
bset.b #4, @(1, r1)
assertmem _x, 0x1fffff
bset.b #5, @(1, r1)
assertmem _x, 0x3fffff
bset.b #6, @(1, r1)
assertmem _x, 0x7fffff
bset.b #7, @(1, r1)
assertmem _x, 0xffffff
bset.b #0, @(0, r1)
assertmem _x, 0x1ffffff
bset.b #1, @(0, r1)
assertmem _x, 0x3ffffff
bset.b #2, @(0, r1)
assertmem _x, 0x7ffffff
bset.b #3, @(0, r1)
assertmem _x, 0xfffffff
bset.b #4, @(0, r1)
assertmem _x, 0x1fffffff
bset.b #5, @(0, r1)
assertmem _x, 0x3fffffff
bset.b #6, @(0, r1)
assertmem _x, 0x7fffffff
bset.b #7, @(0, r1)
assertmem _x, 0xffffffff
assertreg _x, r1
bset_imm_reg:
set_greg 0, r1
bset #0, r1
assertreg 0x1, r1
bset #1, r1
assertreg 0x3, r1
bset #2, r1
assertreg 0x7, r1
bset #3, r1
assertreg 0xf, r1
bset #4, r1
assertreg 0x1f, r1
bset #5, r1
assertreg 0x3f, r1
bset #6, r1
assertreg 0x7f, r1
bset #7, r1
assertreg 0xff, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,807 | sim/testsuite/sh/pdec.s | # sh testcase for pdec
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
pdecx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pdec x0, y0
assert_sreg 0xa5a40000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pdecy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
pdec y0, x0
assert_sreg 0xa5a40000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dct_pdecx:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dcfalse
dct pdec x0, y0
assert_sreg 0xa5a5a5a5, y0
set_dctrue
dct pdec x0, y0
assert_sreg 0xa5a40000, y0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
dcf_pdecy:
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_dctrue
dcf pdec y0, x0
assert_sreg 0xa5a5a5a5, x0
set_dcfalse
dcf pdec y0, x0
assert_sreg 0xa5a40000, x0
test_grs_a5a5
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 3,058 | sim/testsuite/sh/pshai.s | # sh testcase for psha <imm>
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
psha_imm: ! shift arithmetic, immediate operand
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x1, a0
psha #0, a0
assert_sreg 0x1, a0
psha #-0, a0
assert_sreg 0x1, a0
psha #1, a0
assert_sreg 0x2, a0
psha #-1, a0
assert_sreg 0x1, a0
psha #2, a0
assert_sreg 0x4, a0
psha #-2, a0
assert_sreg 0x1, a0
psha #3, a0
assert_sreg 0x8, a0
psha #-3, a0
assert_sreg 0x1, a0
psha #4, a0
assert_sreg 0x10, a0
psha #-4, a0
assert_sreg 0x1, a0
psha #5, a0
assert_sreg 0x20, a0
psha #-5, a0
assert_sreg 0x1, a0
psha #6, a0
assert_sreg 0x40, a0
psha #-6, a0
assert_sreg 0x1, a0
psha #7, a0
assert_sreg 0x80, a0
psha #-7, a0
assert_sreg 0x1, a0
psha #8, a0
assert_sreg 0x100, a0
psha #-8, a0
assert_sreg 0x1, a0
psha #9, a0
assert_sreg 0x200, a0
psha #-9, a0
assert_sreg 0x1, a0
psha #10, a0
assert_sreg 0x400, a0
psha #-10, a0
assert_sreg 0x1, a0
psha #11, a0
assert_sreg 0x800, a0
psha #-11, a0
assert_sreg 0x1, a0
psha #12, a0
assert_sreg 0x1000, a0
psha #-12, a0
assert_sreg 0x1, a0
psha #13, a0
assert_sreg 0x2000, a0
psha #-13, a0
assert_sreg 0x1, a0
psha #14, a0
assert_sreg 0x4000, a0
psha #-14, a0
assert_sreg 0x1, a0
psha #15, a0
assert_sreg 0x8000, a0
psha #-15, a0
assert_sreg 0x1, a0
psha #16, a0
assert_sreg 0x10000, a0
psha #-16, a0
assert_sreg 0x1, a0
psha #17, a0
assert_sreg 0x20000, a0
psha #-17, a0
assert_sreg 0x1, a0
psha #18, a0
assert_sreg 0x40000, a0
psha #-18, a0
assert_sreg 0x1, a0
psha #19, a0
assert_sreg 0x80000, a0
psha #-19, a0
assert_sreg 0x1, a0
psha #20, a0
assert_sreg 0x100000, a0
psha #-20, a0
assert_sreg 0x1, a0
psha #21, a0
assert_sreg 0x200000, a0
psha #-21, a0
assert_sreg 0x1, a0
psha #22, a0
assert_sreg 0x400000, a0
psha #-22, a0
assert_sreg 0x1, a0
psha #23, a0
assert_sreg 0x800000, a0
psha #-23, a0
assert_sreg 0x1, a0
psha #24, a0
assert_sreg 0x1000000, a0
psha #-24, a0
assert_sreg 0x1, a0
psha #25, a0
assert_sreg 0x2000000, a0
psha #-25, a0
assert_sreg 0x1, a0
psha #26, a0
assert_sreg 0x4000000, a0
psha #-26, a0
assert_sreg 0x1, a0
psha #27, a0
assert_sreg 0x8000000, a0
psha #-27, a0
assert_sreg 0x1, a0
psha #28, a0
assert_sreg 0x10000000, a0
psha #-28, a0
assert_sreg 0x1, a0
psha #29, a0
assert_sreg 0x20000000, a0
psha #-29, a0
assert_sreg 0x1, a0
psha #30, a0
assert_sreg 0x40000000, a0
psha #-30, a0
assert_sreg 0x1, a0
psha #31, a0
assert_sreg 0x80000000, a0
psha #-31, a0
assert_sreg 0xffffffff, a0
psha #32, a0
assert_sreg 0x00000000, a0
# I don't grok what should happen here...
# psha #-32, a0
# assert_sreg 0x0, a0
test_grs_a5a5
assert_sreg2 0xa5a5a5a5, a1
assert_sreg 0xa5a5a5a5, x0
assert_sreg 0xa5a5a5a5, x1
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,593 | sim/testsuite/sh/ldrc.s | # sh testcase for ldrc, strc
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
setrc_imm:
set_grs_a5a5
# Test setrc
#
ldrs lstart
ldre lend
setrc #0xff
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xff, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0 ! re unchanged
assertreg0 lend
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
setrc_reg:
set_grs_a5a5
# Test setrc
#
ldrs lstart
ldre lend
set_greg 0xfff, r0
setrc r0
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xfff, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0 ! re unchanged
assertreg0 lend
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
bra ldrc_imm
.global lstart
.align 2
lstart: nop
nop
nop
nop
.global lend
.align 2
lend: nop
nop
nop
nop
ldrc_imm:
set_grs_a5a5
# Test ldrc
setrc #0x0 ! zero rc
ldrc #0xa5
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xa5, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0
assertreg0 lend+1 ! bit 0 set in re
# fix up re for next test
dt r0 ! Ugh! No DEC insn!
ldc r0, re
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
ldrc_reg:
set_grs_a5a5
# Test ldrc
setrc #0x0 ! zero rc
set_greg 0xa5a, r0
ldrc r0
get_sr r1
shlr16 r1
set_greg 0xfff, r0
and r0, r1
assertreg 0xa5a, r1
stc rs, r0 ! rs unchanged
assertreg0 lstart
stc re, r0
assertreg0 lend+1 ! bit 0 set in re
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 1,638 | sim/testsuite/sh/bandor.s | # sh testcase for band, bor
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
band.b #0, @(3, r1)
bf8k mfail
bor.b #1, @(3, r1)
bf8k mfail
band.b #2, @(3, r1)
bf8k mfail
bor.b #3, @(3, r1)
bf8k mfail
bor.b #4, @(3, r1)
bf8k mfail
band.b #5, @(3, r1)
bf8k mfail
bor.b #6, @(3, r1)
bf8k mfail
band.b #7, @(3, r1)
bf8k mfail
band.b #0, @(2, r1)
bf8k mfail
bor.b #1, @(2, r1)
bf8k mfail
band.b #2, @(2, r1)
bf8k mfail
bor.b #3, @(2, r1)
bf8k mfail
bra .L2
nop
.align 2
x: .long _x
.L2:
bor.b #4, @(2, r1)
bf8k mfail
band.b #5, @(2, r1)
bf8k mfail
bor.b #6, @(2, r1)
bf8k mfail
band.b #7, @(2, r1)
bf8k mfail
band.b #0, @(1, r1)
bf8k mfail
bor.b #1, @(1, r1)
bf8k mfail
band.b #2, @(1, r1)
bf8k mfail
bor.b #3, @(1, r1)
bf8k mfail
bor.b #4, @(1, r1)
bf8k mfail
band.b #5, @(1, r1)
bf8k mfail
bor.b #6, @(1, r1)
bf8k mfail
band.b #7, @(1, r1)
bf8k mfail
band.b #0, @(0, r1)
bf8k mfail
bor.b #1, @(0, r1)
bf8k mfail
band.b #2, @(0, r1)
bf8k mfail
bor.b #3, @(0, r1)
bf8k mfail
bor.b #4, @(0, r1)
bf8k mfail
band.b #5, @(0, r1)
bf8k mfail
bor.b #6, @(0, r1)
bf8k mfail
band.b #7, @(0, r1)
bf8k mfail
assertreg _x, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 4,646 | sim/testsuite/sh/pdmsb.s | # sh testcase for pdmsb
# mach: shdsp
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
set_grs_a5a5
lds r0, a0
pcopy a0, a1
lds r0, x0
lds r0, x1
lds r0, y0
lds r0, y1
pcopy x0, m0
pcopy y1, m1
set_sreg 0x0, x0
L0: pdmsb x0, x1
# assert_sreg 31<<16, x1
set_sreg 0x1, x0
L1: pdmsb x0, x1
assert_sreg 30<<16, x1
set_sreg 0x3, x0
L2: pdmsb x0, x1
assert_sreg 29<<16, x1
set_sreg 0x7, x0
L3: pdmsb x0, x1
assert_sreg 28<<16, x1
set_sreg 0xf, x0
L4: pdmsb x0, x1
assert_sreg 27<<16, x1
set_sreg 0x1f, x0
L5: pdmsb x0, x1
assert_sreg 26<<16, x1
set_sreg 0x3f, x0
L6: pdmsb x0, x1
assert_sreg 25<<16, x1
set_sreg 0x7f, x0
L7: pdmsb x0, x1
assert_sreg 24<<16, x1
set_sreg 0xff, x0
L8: pdmsb x0, x1
assert_sreg 23<<16, x1
set_sreg 0x1ff, x0
L9: pdmsb x0, x1
assert_sreg 22<<16, x1
set_sreg 0x3ff, x0
L10: pdmsb x0, x1
assert_sreg 21<<16, x1
set_sreg 0x7ff, x0
L11: pdmsb x0, x1
assert_sreg 20<<16, x1
set_sreg 0xfff, x0
L12: pdmsb x0, x1
assert_sreg 19<<16, x1
set_sreg 0x1fff, x0
L13: pdmsb x0, x1
assert_sreg 18<<16, x1
set_sreg 0x3fff, x0
L14: pdmsb x0, x1
assert_sreg 17<<16, x1
set_sreg 0x7fff, x0
L15: pdmsb x0, x1
assert_sreg 16<<16, x1
set_sreg 0xffff, x0
L16: pdmsb x0, x1
assert_sreg 15<<16, x1
set_sreg 0x1ffff, x0
L17: pdmsb x0, x1
assert_sreg 14<<16, x1
set_sreg 0x3ffff, x0
L18: pdmsb x0, x1
assert_sreg 13<<16, x1
set_sreg 0x7ffff, x0
L19: pdmsb x0, x1
assert_sreg 12<<16, x1
set_sreg 0xfffff, x0
L20: pdmsb x0, x1
assert_sreg 11<<16, x1
set_sreg 0x1fffff, x0
L21: pdmsb x0, x1
assert_sreg 10<<16, x1
set_sreg 0x3fffff, x0
L22: pdmsb x0, x1
assert_sreg 9<<16, x1
set_sreg 0x7fffff, x0
L23: pdmsb x0, x1
assert_sreg 8<<16, x1
set_sreg 0xffffff, x0
L24: pdmsb x0, x1
assert_sreg 7<<16, x1
set_sreg 0x1ffffff, x0
L25: pdmsb x0, x1
assert_sreg 6<<16, x1
set_sreg 0x3ffffff, x0
L26: pdmsb x0, x1
assert_sreg 5<<16, x1
set_sreg 0x7ffffff, x0
L27: pdmsb x0, x1
assert_sreg 4<<16, x1
set_sreg 0xfffffff, x0
L28: pdmsb x0, x1
assert_sreg 3<<16, x1
set_sreg 0x1fffffff, x0
L29: pdmsb x0, x1
assert_sreg 2<<16, x1
set_sreg 0x3fffffff, x0
L30: pdmsb x0, x1
assert_sreg 1<<16, x1
set_sreg 0x7fffffff, x0
L31: pdmsb x0, x1
assert_sreg 0<<16, x1
set_sreg 0xffffffff, x0
L32: pdmsb x0, x1
# assert_sreg 31<<16, x1
set_sreg 0xfffffffe, x0
L33: pdmsb x0, x1
assert_sreg 30<<16, x1
set_sreg 0xfffffffc, x0
L34: pdmsb x0, x1
assert_sreg 29<<16, x1
set_sreg 0xfffffff8, x0
L35: pdmsb x0, x1
assert_sreg 28<<16, x1
set_sreg 0xfffffff0, x0
L36: pdmsb x0, x1
assert_sreg 27<<16, x1
set_sreg 0xffffffe0, x0
L37: pdmsb x0, x1
assert_sreg 26<<16, x1
set_sreg 0xffffffc0, x0
L38: pdmsb x0, x1
assert_sreg 25<<16, x1
set_sreg 0xffffff80, x0
L39: pdmsb x0, x1
assert_sreg 24<<16, x1
set_sreg 0xffffff00, x0
L40: pdmsb x0, x1
assert_sreg 23<<16, x1
set_sreg 0xfffffe00, x0
L41: pdmsb x0, x1
assert_sreg 22<<16, x1
set_sreg 0xfffffc00, x0
L42: pdmsb x0, x1
assert_sreg 21<<16, x1
set_sreg 0xfffff800, x0
L43: pdmsb x0, x1
assert_sreg 20<<16, x1
set_sreg 0xfffff000, x0
L44: pdmsb x0, x1
assert_sreg 19<<16, x1
set_sreg 0xffffe000, x0
L45: pdmsb x0, x1
assert_sreg 18<<16, x1
set_sreg 0xffffc000, x0
L46: pdmsb x0, x1
assert_sreg 17<<16, x1
set_sreg 0xffff8000, x0
L47: pdmsb x0, x1
assert_sreg 16<<16, x1
set_sreg 0xffff0000, x0
L48: pdmsb x0, x1
assert_sreg 15<<16, x1
set_sreg 0xfffe0000, x0
L49: pdmsb x0, x1
assert_sreg 14<<16, x1
set_sreg 0xfffc0000, x0
L50: pdmsb x0, x1
assert_sreg 13<<16, x1
set_sreg 0xfff80000, x0
L51: pdmsb x0, x1
assert_sreg 12<<16, x1
set_sreg 0xfff00000, x0
L52: pdmsb x0, x1
assert_sreg 11<<16, x1
set_sreg 0xffe00000, x0
L53: pdmsb x0, x1
assert_sreg 10<<16, x1
set_sreg 0xffc00000, x0
L54: pdmsb x0, x1
assert_sreg 9<<16, x1
set_sreg 0xff800000, x0
L55: pdmsb x0, x1
assert_sreg 8<<16, x1
set_sreg 0xff000000, x0
L56: pdmsb x0, x1
assert_sreg 7<<16, x1
set_sreg 0xfe000000, x0
L57: pdmsb x0, x1
assert_sreg 6<<16, x1
set_sreg 0xfc000000, x0
L58: pdmsb x0, x1
assert_sreg 5<<16, x1
set_sreg 0xf8000000, x0
L59: pdmsb x0, x1
assert_sreg 4<<16, x1
set_sreg 0xf0000000, x0
L60: pdmsb x0, x1
assert_sreg 3<<16, x1
set_sreg 0xe0000000, x0
L61: pdmsb x0, x1
assert_sreg 2<<16, x1
set_sreg 0xc0000000, x0
L62: pdmsb x0, x1
assert_sreg 1<<16, x1
set_sreg 0x80000000, x0
L63: pdmsb x0, x1
assert_sreg 0<<16, x1
set_sreg 0x00000000, x0
L64: pdmsb x0, x1
# assert_sreg 31<<16, x1
test_grs_a5a5
assert_sreg 0xa5a5a5a5, y0
assert_sreg 0xa5a5a5a5, y1
assert_sreg 0xa5a5a5a5, a0
assert_sreg2 0xa5a5a5a5, a1
assert_sreg2 0xa5a5a5a5, m0
assert_sreg2 0xa5a5a5a5, m1
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 2,333 | sim/testsuite/sh/fipr.s | # sh testcase for fipr $fvm, $fvn
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
initv0:
set_grs_a5a5
set_fprs_a5a5
# Load 1 into fr0.
fldi1 fr0
# Load 2 into fr1.
fldi1 fr1
fadd fr1, fr1
# Load 4 into fr2.
fldi1 fr2
fadd fr2, fr2
fadd fr2, fr2
# Load 8 into fr3.
fmov fr2, fr3
fadd fr2, fr3
initv8:
fldi1 fr8
fldi0 fr9
fldi1 fr10
fldi0 fr11
fipr fv0, fv8
test1:
# Result will be in fr11.
assert_fpreg_i 1, fr0
assert_fpreg_i 2, fr1
assert_fpreg_i 4, fr2
assert_fpreg_i 8, fr3
assert_fpreg_x 0xa5a5a5a5, fr4
assert_fpreg_x 0xa5a5a5a5, fr5
assert_fpreg_x 0xa5a5a5a5, fr6
assert_fpreg_x 0xa5a5a5a5, fr7
assert_fpreg_i 1, fr8
assert_fpreg_i 0, fr9
assert_fpreg_i 1, fr10
assert_fpreg_i 5, fr11
assert_fpreg_x 0xa5a5a5a5, fr12
assert_fpreg_x 0xa5a5a5a5, fr13
assert_fpreg_x 0xa5a5a5a5, fr14
assert_fpreg_x 0xa5a5a5a5, fr15
test_grs_a5a5
test_infp:
# Test positive infinity
fldi0 fr11
mov.l infp, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus infinity
assert_fpreg_x 0x7f800000, fr11
test_infm:
# Test negitive infinity
fldi0 fr11
mov.l infm, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus infinity
assert_fpreg_x 0xff800000, fr11
test_qnanp:
# Test positive qnan
fldi0 fr11
mov.l qnanp, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus qnan (or greater)
flds fr11, fpul
sts fpul, r1
cmp/ge r0, r1
bt .L0
fail
.L0:
test_snanp:
# Test positive snan
fldi0 fr11
mov.l snanp, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be plus snan (or greater)
flds fr11, fpul
sts fpul, r1
cmp/ge r0, r1
bt .L1
fail
.L1:
.if 0
# Handling of nan and inf not implemented yet.
test_qnanm:
# Test negantive qnan
fldi0 fr11
mov.l qnanm, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be minus qnan (or less)
flds fr11, fpul
sts fpul, r1
cmp/ge r1, r0
bt .L2
fail
.L2:
test_snanm:
# Test negative snan
fldi0 fr11
mov.l snanm, r0
lds r0, fpul
fsts fpul, fr0
fipr fv0, fv8
# fr11 should be minus snan (or less)
flds fr11, fpul
sts fpul, r1
cmp/ge r1, r0
bt .L3
fail
.L3:
.endif
pass
exit 0
.align 2
qnanp: .long 0x7f800001
qnanm: .long 0xff800001
snanp: .long 0x7fc00000
snanm: .long 0xffc00000
infp: .long 0x7f800000
infm: .long 0xff800000
|
tactcomplabs/xbgas-binutils-gdb | 1,740 | sim/testsuite/sh/bandornot.s | # sh testcase for bandnot, bornot
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 0xa5a5a5a5
start
bandor_b_imm_disp12_reg:
set_grs_a5a5
# Make sure T is true to start.
sett
mov.l x, r1
bandnot.b #0, @(3, r1)
bt8k mfail
bornot.b #1, @(3, r1)
bf8k mfail
bandnot.b #2, @(3, r1)
bt8k mfail
bornot.b #3, @(3, r1)
bf8k mfail
bornot.b #4, @(3, r1)
bf8k mfail
bandnot.b #5, @(3, r1)
bt8k mfail
bornot.b #6, @(3, r1)
bf8k mfail
bandnot.b #7, @(3, r1)
bt8k mfail
bandnot.b #0, @(2, r1)
bt8k mfail
bornot.b #1, @(2, r1)
bf8k mfail
bandnot.b #2, @(2, r1)
bt8k mfail
bornot.b #3, @(2, r1)
bf8k mfail
bra .L2
nop
.align 2
x: .long _x
.L2:
bornot.b #4, @(2, r1)
bf8k mfail
bandnot.b #5, @(2, r1)
bt8k mfail
bornot.b #6, @(2, r1)
bf8k mfail
bandnot.b #7, @(2, r1)
bt8k mfail
bandnot.b #0, @(1, r1)
bt8k mfail
bornot.b #1, @(1, r1)
bf8k mfail
bandnot.b #2, @(1, r1)
bt8k mfail
bornot.b #3, @(1, r1)
bf8k mfail
bornot.b #4, @(1, r1)
bf8k mfail
bandnot.b #5, @(1, r1)
bt8k mfail
bornot.b #6, @(1, r1)
bf8k mfail
bandnot.b #7, @(1, r1)
bt8k mfail
bandnot.b #0, @(0, r1)
bt8k mfail
bornot.b #1, @(0, r1)
bf8k mfail
bandnot.b #2, @(0, r1)
bt8k mfail
bornot.b #3, @(0, r1)
bf8k mfail
bornot.b #4, @(0, r1)
bf8k mfail
bandnot.b #5, @(0, r1)
bt8k mfail
bornot.b #6, @(0, r1)
bf8k mfail
bandnot.b #7, @(0, r1)
bt8k mfail
assertreg _x, r1
test_gr_a5a5 r0
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
|
tactcomplabs/xbgas-binutils-gdb | 17,132 | sim/testsuite/ft32/basic.s | # check that basic insns work.
# mach: ft32
.include "testutils.inc"
start
ldk $r0,__PMSIZE
EXPECT $r0,0x00040000
ldk $r0,__RAMSIZE
EXPECT $r0,0x00010000
ldk $r4,10
add $r4,$r4,23
EXPECT $r4,33
# lda, sta
.data
tmp: .long 0
.text
xor.l $r0,$r0,$r0
EXPECT $r0,0x00000000
xor.l $r0,$r0,$r0
add.l $r0,$r0,1
EXPECT $r0,0x00000001
ldk.l $r0,0x4567
EXPECT $r0,0x00004567
lpm.l $r0,k_12345678
EXPECT $r0,0x12345678
sta.l tmp,$r0
lda.l $r1,tmp
EXPECT $r1,0x12345678
lda.b $r1,tmp
EXPECT $r1,0x00000078
lda.b $r1,tmp+1
EXPECT $r1,0x00000056
lda.b $r1,tmp+2
EXPECT $r1,0x00000034
lda.b $r1,tmp+3
EXPECT $r1,0x00000012
sta.b tmp+1,$r0
lda.l $r1,tmp+0
EXPECT $r1,0x12347878
# immediate
ldk.l $r1,12
add.l $r1,$r1,4
EXPECT $r1,0x00000010
add.l $r1,$r1,0x1ff
EXPECT $r1,0x0000020f
add.l $r1,$r1,-0x200
EXPECT $r1,0x0000000f
# addk
xor.l $r1,$r0,$r0
add.l $r2,$r1,127
EXPECT $r2,0x0000007f
add.l $r2,$r2,127
EXPECT $r2,0x000000fe
add.l $r2,$r2,-127
EXPECT $r2,0x0000007f
add.l $r2,$r2,-128
EXPECT $r2,0xffffffff
add.l $r2,$r2,1
EXPECT $r2,0x00000000
# mul
ldk.l $r1,100
ldk.l $r2,77
mul.l $r3,$r1,$r2
EXPECT $r3,0x00001e14
# 0x12345678 ** 2 = 0x14b66dc1df4d840L
mul.l $r3,$r0,$r0
EXPECT $r3,0x1df4d840
muluh.l $r3,$r0,$r0
EXPECT $r3,0x014b66dc
# push and pop
push.l $r0
EXPECT $sp,0x0000fffc
ldi.l $r3,$sp,0
EXPECT $r3,0x12345678
pop.l $r4
EXPECT $sp,0x00000000
EXPECT $r4,0x12345678
ldk.l $r1,0x1111
push.l $r1
ldk.l $r1,0x2222
push.l $r1
ldk.l $r1,0x3333
push.l $r1
ldk.l $r1,0x4444
push.l $r1
EXPECT $sp,0x0000fff0
pop.l $r1
EXPECT $r1,0x00004444
pop.l $r1
EXPECT $r1,0x00003333
pop.l $r1
EXPECT $r1,0x00002222
pop.l $r1
EXPECT $r1,0x00001111
# push and pop with $sp changes
ldk.l $r1,0xa111
push.l $r1
sub.l $sp,$sp,4
ldk.l $r1,0xa222
push.l $r1
add.l $sp,$sp,-36
add.l $sp,$sp,36
pop.l $r1
EXPECT $r1,0x0000a222
add.l $sp,$sp,4
pop.l $r1
EXPECT $r1,0x0000a111
# sti
ldk.l $r2,80
EXPECT $r2,0x00000050
sti.l $r2,0,$r0
lda.l $r1,80
EXPECT $r1,0x12345678
ldk.l $r3,0xF0
sti.b $r2,0,$r3
lda.l $r1,80
EXPECT $r1,0x123456f0
add.l $r2,$r2,1
sti.l $r2,0,$r0
sti.b $r2,0,$r3
lda.l $r1,80
EXPECT $r1,0x1234f078
add.l $r2,$r2,1
sti.l $r2,0,$r0
sti.b $r2,0,$r3
lda.l $r1,80
EXPECT $r1,0x12f05678
add.l $r2,$r2,1
sti.l $r2,0,$r0
sti.b $r2,0,$r3
lda.l $r1,80
EXPECT $r1,0xf0345678
ldk.l $r2,80
sti.l $r2,0,$r0
ldk.s $r3,0xbeef
sti.s $r2,0,$r3
lda.l $r1,80
EXPECT $r1,0x1234beef
add.l $r2,$r2,2
sti.s $r2,0,$r3
lda.l $r1,80
EXPECT $r1,0xbeefbeef
# lpmi
ldk.l $r1,k_12345678
lpmi.l $r2,$r1,0
EXPECT $r2,0x12345678
lpmi.b $r2,$r1,0
EXPECT $r2,0x00000078
add.l $r1,$r1,1
lpmi.b $r2,$r1,0
EXPECT $r2,0x00000056
add.l $r1,$r1,1
lpmi.b $r2,$r1,0
EXPECT $r2,0x00000034
add.l $r1,$r1,1
lpmi.b $r2,$r1,0
EXPECT $r2,0x00000012
lpmi.l $r2,$r1,4
EXPECT $r2,0xabcdef01
lpmi.l $r2,$r1,-4
EXPECT $r2,0x10111213
lpmi.b $r2,$r1,-4
EXPECT $r2,0x00000010
ldk.l $r1,k_12345678
lpmi.s $r2,$r1,0
EXPECT $r2,0x00005678
lpmi.s $r2,$r1,2
EXPECT $r2,0x00001234
lpmi.b $r2,$r1,6
EXPECT $r2,0x000000cd
lpmi.b $r2,$r1,7
EXPECT $r2,0x000000ab
lpmi.b $r2,$r1,-1
EXPECT $r2,0x00000010
lpmi.s $r2,$r1,-2
EXPECT $r2,0x00001011
ldk.l $r1,k_12345678-127
lpmi.b $r2,$r1,127
EXPECT $r2,0x00000078
ldk.l $r1,k_12345678+128
lpmi.b $r2,$r1,-128
EXPECT $r2,0x00000078
# shifts
lpm.l $r0,k_12345678
ldk.l $r2,4
ashl.l $r1,$r0,$r2
EXPECT $r1,0x23456780
lshr.l $r1,$r0,$r2
EXPECT $r1,0x01234567
ashr.l $r1,$r0,$r2
EXPECT $r1,0x01234567
lpm.l $r0,k_abcdef01
ashl.l $r1,$r0,$r2
EXPECT $r1,0xbcdef010
lshr.l $r1,$r0,$r2
EXPECT $r1,0x0abcdef0
ashr.l $r1,$r0,$r2
EXPECT $r1,0xfabcdef0
# rotate right
lpm.l $r0,k_12345678
ror.l $r1,$r0,0
EXPECT $r1,0x12345678
ror.l $r1,$r0,12
EXPECT $r1,0x67812345
ror.l $r1,$r0,-4
EXPECT $r1,0x23456781
# jmpx
ldk $r28,0xaaaaa
jmpx 0,$r28,1,failcase
jmpx 1,$r28,0,failcase
jmpx 2,$r28,1,failcase
jmpx 3,$r28,0,failcase
jmpx 4,$r28,1,failcase
jmpx 5,$r28,0,failcase
jmpx 6,$r28,1,failcase
jmpx 7,$r28,0,failcase
jmpx 8,$r28,1,failcase
jmpx 9,$r28,0,failcase
jmpx 10,$r28,1,failcase
jmpx 11,$r28,0,failcase
jmpx 12,$r28,1,failcase
jmpx 13,$r28,0,failcase
jmpx 14,$r28,1,failcase
jmpx 15,$r28,0,failcase
jmpx 16,$r28,1,failcase
jmpx 17,$r28,0,failcase
jmpx 18,$r28,1,failcase
jmpx 19,$r28,0,failcase
move $r29,$r28
ldk $r28,0
jmpx 0,$r29,1,failcase
jmpx 1,$r29,0,failcase
jmpx 2,$r29,1,failcase
jmpx 3,$r29,0,failcase
jmpx 4,$r29,1,failcase
jmpx 5,$r29,0,failcase
jmpx 6,$r29,1,failcase
jmpx 7,$r29,0,failcase
jmpx 8,$r29,1,failcase
jmpx 9,$r29,0,failcase
jmpx 10,$r29,1,failcase
jmpx 11,$r29,0,failcase
jmpx 12,$r29,1,failcase
jmpx 13,$r29,0,failcase
jmpx 14,$r29,1,failcase
jmpx 15,$r29,0,failcase
jmpx 16,$r29,1,failcase
jmpx 17,$r29,0,failcase
jmpx 18,$r29,1,failcase
jmpx 19,$r29,0,failcase
move $r30,$r29
ldk $r29,0
jmpx 0,$r30,1,failcase
jmpx 1,$r30,0,failcase
jmpx 2,$r30,1,failcase
jmpx 3,$r30,0,failcase
jmpx 4,$r30,1,failcase
jmpx 5,$r30,0,failcase
jmpx 6,$r30,1,failcase
jmpx 7,$r30,0,failcase
jmpx 8,$r30,1,failcase
jmpx 9,$r30,0,failcase
jmpx 10,$r30,1,failcase
jmpx 11,$r30,0,failcase
jmpx 12,$r30,1,failcase
jmpx 13,$r30,0,failcase
jmpx 14,$r30,1,failcase
jmpx 15,$r30,0,failcase
jmpx 16,$r30,1,failcase
jmpx 17,$r30,0,failcase
jmpx 18,$r30,1,failcase
jmpx 19,$r30,0,failcase
# callx
ldk $r30,0xaaaaa
callx 0,$r30,0,skip1
jmp failcase
callx 1,$r30,1,skip1
jmp failcase
callx 2,$r30,0,skip1
jmp failcase
callx 3,$r30,1,skip1
jmp failcase
callx 0,$r30,1,skip1
ldk $r30,0x123
EXPECT $r30,0x123
#define BIT(N,M) ((((N) & 15) << 5) | (M))
# bextu
bextu.l $r1,$r0,(0<<5)|0
EXPECT $r1,0x00005678
bextu.l $r1,$r0,(4<<5)|0
EXPECT $r1,0x00000008
bextu.l $r1,$r0,(4<<5)|4
EXPECT $r1,0x00000007
bextu.l $r1,$r0,(4<<5)|28
EXPECT $r1,0x00000001
bextu.l $r1,$r0,(8<<5)|16
EXPECT $r1,0x00000034
ldk.l $r2,-1
bextu.l $r1,$r2,(6<<5)|(3)
EXPECT $r1,0x0000003f
# bexts
bexts.l $r1,$r0,(8<<5)|0
EXPECT $r1,0x00000078
bexts.l $r1,$r0,(0<<5)|16
EXPECT $r1,0x00001234
bexts.l $r1,$r0,(4<<5)|0
EXPECT $r1,0xfffffff8
# extract the '5' digit in widths 4-1
bexts.l $r1,$r0,(4<<5)|12
EXPECT $r1,0x00000005
bexts.l $r1,$r0,(3<<5)|12
EXPECT $r1,0xfffffffd
bexts.l $r1,$r0,(2<<5)|12
EXPECT $r1,0x00000001
bexts.l $r1,$r0,(1<<5)|12
EXPECT $r1,0xffffffff
# btst
# low four bits should be 0,0,0,1
btst.l $r0,(1<<5)|0
jmpc nz,failcase
btst.l $r0,(1<<5)|1
jmpc nz,failcase
btst.l $r0,(1<<5)|2
jmpc nz,failcase
btst.l $r0,(1<<5)|3
jmpc z,failcase
# the 6 bit field starting at position 24 is positive
btst.l $r0,(6<<5)|24
jmpc s,failcase
# the 5 bit field starting at position 24 is negative
btst.l $r0,(5<<5)|24
jmpc ns,failcase
EXPECT $r0,0x12345678
# bins
bins.l $r1,$r0,(8 << 5) | (0)
EXPECT $r1,0x12345600
bins.l $r1,$r0,(0 << 5) | (8)
EXPECT $r1,0x12000078
ldk.l $r1,(0xff << 10) | (8 << 5) | (8)
bins.l $r1,$r0,$r1
EXPECT $r1,0x1234ff78
call litr1
.long (0x8dd1 << 10) | (0 << 5) | (0)
bins.l $r1,$r0,$r1
EXPECT $r1,0x12348dd1
call litr1
.long (0x8dd1 << 10) | (0 << 5) | (16)
bins.l $r1,$r0,$r1
EXPECT $r1,0x8dd15678
ldk.l $r1,(0xde << 10) | (8 << 5) | (0)
bins.l $r1,$r0,$r1
EXPECT $r1,0x123456de
# ldl
ldk.l $r0,0
ldl.l $r3,$r0,0
EXPECT $r3,0x00000000
ldk.l $r0,-1
ldl.l $r3,$r0,-1
EXPECT $r3,0xffffffff
ldk.l $r0,(0x12345678 >> 10)
ldl.l $r3,$r0,(0x12345678 & 0x3ff)
EXPECT $r3,0x12345678
ldk.l $r0,(0xe2345678 >> 10)
ldl.l $r3,$r0,(0xe2345678 & 0x3ff)
EXPECT $r3,0xe2345678
# flip
ldk.l $r0,0x0000001
flip.l $r1,$r0,0
EXPECT $r1,0x00000001
lpm.l $r0,k_12345678
flip.l $r1,$r0,0
EXPECT $r1,0x12345678
flip.l $r1,$r0,24
EXPECT $r1,0x78563412
flip.l $r1,$r0,31
EXPECT $r1,0x1e6a2c48
# stack push pop
EXPECT $sp,0x00000000
ldk.l $r6,0x6666
push.l $r6
or.l $r0,$r0,$r0 # xxx
EXPECT $sp,0x0000fffc
ldi.l $r1,$sp,0
EXPECT $r1,0x00006666
pop.l $r1
EXPECT $r1,0x00006666
EXPECT $sp,0x00000000
# call/return
call fowia
push.l $r1
call fowia
pop.l $r2
sub.l $r1,$r1,$r2
EXPECT $r1,0x00000008
# add,carry
ldk.l $r0,0
ldk.l $r1,0
call add64
EXPECT $r1,0x00000000
EXPECT $r0,0x00000000
lpm.l $r0,k_abcdef01
lpm.l $r1,k_abcdef01
call add64
EXPECT $r1,0x00000001
EXPECT $r0,0x579bde02
ldk.l $r0,4
ldk.l $r1,-5
call add64
EXPECT $r1,0x00000000
EXPECT $r0,0xffffffff
ldk.l $r0,5
ldk.l $r1,-5
call add64
EXPECT $r1,0x00000001
EXPECT $r0,0x00000000
lpm.l $r0,k_12345678
ldk.l $r1,-1
call add64
EXPECT $r1,0x00000001
EXPECT $r0,0x12345677
ldk.l $r0,-1
ldk.l $r1,-1
call add64
EXPECT $r1,0x00000001
EXPECT $r0,0xfffffffe
# inline literal
call lit
.long 0xdecafbad
EXPECT $r0,0xdecafbad
ldk.l $r1,0xee
call lit
ldk.l $r1,0xfe
EXPECT $r1,0x000000ee
call lit
.long 0x01020304
EXPECT $r0,0x01020304
call lit
.long lit
calli $r0
.long 0xffaa55aa
EXPECT $r0,0xffaa55aa
# comparisons
ldk.l $r0,-100
ldk.l $r1,100
cmp.l $r0,$r1
ldk.l $r2,0
jmpc lt,.c1
ldk.l $r2,1
.c1:
EXPECT $r2,0x00000000
ldk.l $r2,0
jmpc gt,.c2
ldk.l $r2,1
.c2:
EXPECT $r2,0x00000001
ldk.l $r2,0
jmpc a,.c3
ldk.l $r2,1
.c3:
EXPECT $r2,0x00000000
ldk.l $r2,0
jmpc b,.c4
ldk.l $r2,1
.c4:
EXPECT $r2,0x00000001
ldk.l $r2,0
jmpc be,.c5
ldk.l $r2,1
.c5:
EXPECT $r2,0x00000001
# 8-bit comparisons
ldk.l $r0,0x8fe
ldk.l $r1,0x708
cmp.b $r0,$r1
ldk.l $r2,0
jmpc lt,.8c1
ldk.l $r2,1
.8c1:
EXPECT $r2,0x00000000
ldk.l $r2,0
jmpc gt,.8c2
ldk.l $r2,1
.8c2:
EXPECT $r2,0x00000001
ldk.l $r2,0
jmpc a,.8c3
ldk.l $r2,1
.8c3:
EXPECT $r2,0x00000000
ldk.l $r2,0
jmpc b,.8c4
ldk.l $r2,1
.8c4:
EXPECT $r2,0x00000001
ldk.l $r2,0
jmpc be,.8c5
ldk.l $r2,1
.8c5:
EXPECT $r2,0x00000001
ldk.l $r0,0x8aa
ldk.l $r1,0x7aa
cmp.b $r0,$r1
ldk.l $r2,0
jmpc z,.8c6
ldk.l $r2,1
.8c6:
EXPECT $r2,0x00000000
ldk.b $r0,1
ldk.b $r2,0xe0
cmp.b $r2,0x1c0
jmpc a,.8c7
ldk.b $r0,0
.8c7:
EXPECT $r0,0x00000001
# conditional call
cmp.l $r0,$r0
callc z,lit
.long 0xccddeeff
callc nz,zr0
EXPECT $r0,0xccddeeff
# modify return address
ldk.l $r0,0x66
call skip1
ldk.l $r0,0xAA
EXPECT $r0,0x00000066
ldk.l $r0,0x77
call skip2
ldk.l $r0,0xBB
EXPECT $r0,0x00000077
# simple recursive function
ldk.l $r0,1
call factorial
EXPECT $r0,0x00000001
ldk.l $r0,2
call factorial
EXPECT $r0,0x00000002
ldk.l $r0,3
call factorial
EXPECT $r0,0x00000006
ldk.l $r0,4
call factorial
EXPECT $r0,0x00000018
ldk.l $r0,5
call factorial
EXPECT $r0,0x00000078
ldk.l $r0,6
call factorial
EXPECT $r0,0x000002d0
ldk.l $r0,7
call factorial
EXPECT $r0,0x000013b0
ldk.l $r0,12
call factorial
EXPECT $r0,0x1c8cfc00
# read sp after a call
call nullfunc
EXPECT $sp,0x00000000
# CALLI->RETURN
ldk.l $r4,nullfunc
calli $r4
EXPECT $sp,0x00000000
# Link/unlink
ldk.l $r14,0x17566
link $r14,48
EXPECT $r14,0x0000fffc
sub.l $sp,$sp,200
unlink $r14
EXPECT $r14,0x00017566
# LINK->UNLINK
link $r14,48
unlink $r14
EXPECT $r14,0x00017566
# LINK->JUMPI
ldk.l $r3,.here
link $r14,48
jmpi $r3
jmp failcase
.here:
unlink $r14
EXPECT $r14,0x00017566
# LINK->RETURN
# (This is a nonsense combination, but can still exericse it by
# using a negative parameter for the link. "link $r14,-4" leaves
# $sp exactly unchanged.)
ldk.l $r0,.returnhere
push.l $r0
link $r14,0xfffc
return
.returnhere:
EXPECT $sp,0x00000000
# LPMI->CALLI
ldk.l $r0,k_abcdef01
ldk.l $r1,increment
lpmi.l $r0,$r0,0
calli $r1
EXPECT $r0,0xabcdef02
# STRLen
lpm.l $r4,str3
sta.l tmp,$r4
ldk.l $r0,tmp
strlen.b $r1,$r0
EXPECT $r1,0x00000003
strlen.s $r1,$r0
EXPECT $r1,0x00000003
strlen.l $r1,$r0
EXPECT $r1,0x00000003
ldk.l $r4,0
sta.b 4,$r4
strlen.l $r1,$r0
EXPECT $r1,0x00000000
ldk.l $r4,-1
sta.l 4,$r4
lpm.l $r4,str3
sta.l 8,$r4
strlen.l $r1,$r0
EXPECT $r1,0x00000007
# MEMSet
ldk.l $r0,4
ldk.l $r1,0xaa
memset.s $r0,$r1,8
ldk.l $r1,0x55
memset.b $r0,$r1,5
lda.l $r0,4
EXPECT $r0,0x55555555
lda.l $r0,8
EXPECT $r0,0xaaaaaa55
# first cycle after mispredict
ldk.l $r0,3
cmp.l $r0,$r0
jmpc nz,failcase
add.l $r0,$r0,7
EXPECT $r0,0x0000000a
jmpc nz,failcase
push.l $r0
EXPECT $sp,0x0000fffc
pop.l $r0
# $sp access after stall
lpm.l $r13,0
push.l $r0
EXPECT $sp,0x0000fffc
pop.l $r0
push.l $r0
add.l $sp,$sp,-484
EXPECT $sp,0x0000fe18
EXPECT $sp,0x0000fe18
EXPECT $sp,0x0000fe18
add.l $sp,$sp,484
EXPECT $sp,0x0000fffc
pop.l $r0
# atomic exchange
lpm.l $r0,k_12345678
lpm.l $r1,k_abcdef01
sta.l 100,$r1
exa.l $r0,100
EXPECT $r0,0xabcdef01
lda.l $r0,100
EXPECT $r0,0x12345678
lpm.l $r0,k_12345678
lpm.l $r1,k_abcdef01
sta.l 144,$r1
ldk.l $r7,20
exi.l $r0,$r7,124
EXPECT $r0,0xabcdef01
lda.l $r0,144
EXPECT $r0,0x12345678
lpm.l $r0,k_12345678
lpm.l $r1,k_abcdef01
push $r1
exi.l $r0,$sp,0
EXPECT $r0,0xabcdef01
pop.l $r0
EXPECT $r0,0x12345678
# PM write port
.equ PM_UNLOCK, 0x1fc80
.equ PM_ADDR, 0x1fc84
.equ PM_DATA, 0x1fc88
lpm.l $r0,k_12345678
lpm.l $r1,k_abcdef01
EXPECT $r0,0x12345678
EXPECT $r1,0xabcdef01
ldk.l $r3,(0x1337f7d1 >> 10)
ldl.l $r3,$r3,(0x1337f7d1 & 0x3ff)
EXPECT $r3,0x1337f7d1
ldk $r4,k_12345678
sta.l PM_ADDR,$r4
# write while locked does nothing
sta.l PM_DATA,$r1
sta.l PM_DATA,$r0
lpm.l $r0,k_12345678
lpm.l $r1,k_abcdef01
EXPECT $r0,0x12345678
EXPECT $r1,0xabcdef01
# write while unlocked modifies program memory
sta.l PM_UNLOCK,$r3
sta.l PM_DATA,$r1
sta.l PM_DATA,$r0
lpm.l $r0,k_12345678
lpm.l $r1,k_abcdef01
EXPECT $r0,0xabcdef01
EXPECT $r1,0x12345678
# final stack check
EXPECT $sp,0x00000000
PASS
# --------------------------------------------------
skip1: # skip the instruction after the call
pop.l $r1
add.l $r1,$r1,4
push.l $r1
return
skipparent: # skip the instruction after the caller's call
ldi.l $r1,$sp,4
add.l $r1,$r1,4
sti.l $sp,4,$r1
return
skip2:
call skipparent
return
add64:
addcc.l $r0,$r1
add.l $r0,$r0,$r1
ldk.l $r1,0
jmpc nc,.done
ldk.l $r1,1
.done:
return
fowia: # find out where I'm at
ldi.l $r1,$sp,0
return
lit: # load literal to $r0
pop.l $r14
lpmi.l $r0,$r14,0
add.l $r14,$r14,4
jmpi $r14
zr0:
ldk.l $r0,0
return
litr1:
ldi.l $r1,$sp,0
add.l $r1,$r1,4
sti.l $sp,0,$r1
lpmi.l $r1,$r1,-4
return
factorial:
ldk.l $r1,1
cmp.l $r0,$r1
jmpc z,.factdone
push.l $r0
add.l $r0,$r0,-1
call factorial
pop.l $r1
mul.l $r0,$r0,$r1
.factdone:
return
nullfunc:
return
increment:
add.l $r0,$r0,1
return
.long 0x10111213
k_12345678:
.long 0x12345678
k_abcdef01:
.long 0xabcdef01
str3:
.string "abc"
|
tactcomplabs/xbgas-binutils-gdb | 2,888 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_sn.s | //Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
imm32 p1, 0x1401101f;
imm32 p2, 0x3204108e;
imm32 p3, 0xd93f1084;
imm32 p4, 0xeb04106f;
imm32 p5, 0xa90e5089;
ASTAT = R0;
CC = R1; // cc2dreg
R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac
I0 = P1; // regmv
IF CC R1 = R3; // ccmov
CC = ! CC; // cc2dreg
R4.H = R1.L + R0.L (S); // dsp32alu
M0 = P2; // regmv
IF CC R3 = R2; // ccmov
CC = R0 < R1; // ccflag
R4.L = R5.L << 1; // dsp32shiftimm
I0 += M0; // dagmodim
R2 = R0 + R2; // comp3op dr plus dr
IF CC R4 = R5; // ccmov
CC = R2 == R3; // ccflag
R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult
R5 = R0 + R2; // comp3op dr plus dr
BITCLR( R6 , 1 );
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
IF !CC JUMP LABEL1; // branch on
CC = ! CC; // cc2dreg
P1.L = 0x3000; // ldimmhalf
A0 += A1 (W32); // dsp32alu a0 + a1
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R6 = R6 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R7;
CC = R0 < R1; // ccflag
P2 = A0.w;
IF CC JUMP END (BP); // branch
P3 = A1.w;
R5 = R5 + R7;
END:
CHECKREG r0, 0xA08D2311;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0xA08E3868;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x411B5B79;
CHECKREG r6, 0x056C9760;
CHECKREG r7, 0x4116F22D;
CHECKREG p1, 0x14013000;
CHECKREG p2, 0x033352A4;
CHECKREG p3, 0xD93F1084;
imm32 r0, 0x408d2711;
imm32 r1, 0x15124040;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
CC = R1; // cc2dreg
P1 = -15; // compi2opp_pr_eq_i7
R2 = ROT R2 BY 1; // dsp32shiftim_rot
CC = ! CC; // cc2dreg
R3 >>= R7; // alu2op sft
R4 = ROT R0 BY -3; // dsp32shiftim_rot
CC = R0 < R1; // ccflag
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
R5 = R0 + R2; // comp3op dr plus dr
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = R2 == R3; // ccflag
P2 = R1; // regmv
R4.H = R1.L + R3.H (S); // dsp32alu
I0 = P1; // regmv
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
I0 += 2;
P3 = I0;
R3.L = R5.L << 1; // dsp32shiftimm
R7 = ROT R6 BY R7.L; // dsp32shiftim_rot
CHECKREG r0, 0x408D2711;
CHECKREG r1, 0x2ACFF368;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xFFFD4E22;
CHECKREG r4, 0x403DA4E2;
CHECKREG r5, 0x408D2711;
CHECKREG r6, 0x15BD33A8;
CHECKREG r7, 0x56F4CEA2;
CHECKREG p1, 0xFFFFFFF1;
CHECKREG p2, 0x15124040;
CHECKREG p3, 0xFFFFFFF3;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,576 | sim/testsuite/bfin/c_dsp32mac_dr_a1_s.s | //Original:/testcases/core/c_dsp32mac_dr_a1_s/c_dsp32mac_dr_a1_s.dsp
// Spec Reference: dsp32mac dr_a1 s (scale by 2 signed fraction with round)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbabcfec7;
imm32 r2, 0xc1a48679;
imm32 r3, 0xd00a9007;
imm32 r4, 0xefbca569;
imm32 r5, 0xcd355a0b;
imm32 r6, 0xe00c80ad;
imm32 r7, 0xf78e900a;
R0.H = ( A1 -= R1.L * R0.L ), A0 += R1.L * R0.L (S2RND);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (S2RND);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ), A0 = R4.H * R5.H (S2RND);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (S2RND);
R7 = A1.w;
CHECKREG r0, 0x01BC5ABD;
CHECKREG r1, 0x00DDE22A;
CHECKREG r2, 0x5CCE8679;
CHECKREG r3, 0x2E67039E;
CHECKREG r4, 0xE91EA569;
CHECKREG r5, 0xF48ECA28;
CHECKREG r6, 0xED5580AD;
CHECKREG r7, 0xF6AA7F78;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x63bb8abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xab245679;
imm32 r3, 0xb0b69007;
imm32 r4, 0xcfbb4569;
imm32 r5, 0xd235b00b;
imm32 r6, 0xe00cab0d;
imm32 r7, 0x678e70bf;
R0.H = ( A1 += R1.L * R0.L ) (S2RND);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (S2RND);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (S2RND);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (S2RND);
R7 = A1.w;
CHECKREG r0, 0xEF928ABD;
CHECKREG r1, 0xF7C93D4E;
CHECKREG r2, 0x5AB45679;
CHECKREG r3, 0x2D59E942;
CHECKREG r4, 0x7FFF4569;
CHECKREG r5, 0x4B80E354;
CHECKREG r6, 0xCC4CAB0D;
CHECKREG r7, 0xE6263550;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x5c54babd;
imm32 r1, 0x6dccdec7;
imm32 r2, 0xc12ce679;
imm32 r3, 0x8c06c007;
imm32 r4, 0x9fcc4c69;
imm32 r5, 0xa23c90cb;
imm32 r6, 0xb00cc00c;
imm32 r7, 0xc78eac0f;
R0.H = A1 , A0 -= R1.L * R0.L (S2RND);
R1 = A1.w;
R2.H = A1 , A0 += R2.H * R3.L (S2RND);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (S2RND);
R5 = A1.w;
R6.H = A1 , A0 += R6.L * R7.H (S2RND);
R7 = A1.w;
CHECKREG r0, 0xCC4CBABD;
CHECKREG r1, 0xE6263550;
CHECKREG r2, 0xCC4CE679;
CHECKREG r3, 0xE6263550;
CHECKREG r4, 0xCC4C4C69;
CHECKREG r5, 0xE6263550;
CHECKREG r6, 0xCC4CC00C;
CHECKREG r7, 0xE6263550;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x3d545abd;
imm32 r1, 0x5ddcfec7;
imm32 r2, 0x712d5679;
imm32 r3, 0x9006d007;
imm32 r4, 0xafbc4d69;
imm32 r5, 0xd23590db;
imm32 r6, 0xd00ca00d;
imm32 r7, 0x6d8ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (S2RND);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (S2RND);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (S2RND);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (S2RND);
R7 = A1.w;
CHECKREG r0, 0xFF225ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x614C5679;
CHECKREG r3, 0x30A616D6;
CHECKREG r4, 0x06764D69;
CHECKREG r5, 0x033B2CAA;
CHECKREG r6, 0xDD6BA00D;
CHECKREG r7, 0xEEB5AF52;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83e45abd;
imm32 r1, 0xe8befec7;
imm32 r2, 0xce84e679;
imm32 r3, 0x1ce80e07;
imm32 r4, 0xe1ce85e9;
imm32 r5, 0x921ce80e;
imm32 r6, 0x79019e8d;
imm32 r7, 0x679e90e8;
R0.H = ( A1 += R1.L * R0.L ) (M,S2RND);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ) (M,S2RND);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (M,S2RND);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,S2RND);
R7 = A1.w;
CHECKREG r0, 0xDC8D5ABD;
CHECKREG r1, 0xEE46BE3D;
CHECKREG r2, 0xFA3CE679;
CHECKREG r3, 0xFD1E19A8;
CHECKREG r4, 0xC37E85E9;
CHECKREG r5, 0xE1BF22EC;
CHECKREG r6, 0x80009E8D;
CHECKREG r7, 0xB0C50D4E;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,135 | sim/testsuite/bfin/cec-syscfg-ssstep.S | # Blackfin testcase for hardware single stepping
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
# Set up exception handler
imm32 P4, EVT3;
loadsym R1, _evx;
[P4] = R1;
# Enable single stepping
R0 = 1;
SYSCFG = R0;
# Lower to the code we want to single step through
R1 = 1;
imm32 R5, 0xffff
R6 = 0;
R7 = 0;
loadsym R1, _usr;
RETI = R1;
RTI;
_usr:
# Single step and set a new bit every time
BITSET (R7, 0);
BITSET (R7, 1);
BITSET (R7, 2);
BITSET (R7, 3);
BITSET (R7, 4);
BITSET (R7, 5);
BITSET (R7, 6);
BITSET (R7, 7);
BITSET (R7, 8);
BITSET (R7, 9);
BITSET (R7, 10);
BITSET (R7, 11);
BITSET (R7, 12);
BITSET (R7, 13);
BITSET (R7, 14);
BITSET (R7, 15);
JUMP fail_lvl;
_evx:
# Make sure exception reason is single step
R3 = SEQSTAT;
R4 = 0x3f;
R3 = R3 & R4;
R4 = 0x10;
CC = R3 == R4;
IF !CC JUMP fail_lvl;
# Set a new bit in R6 every single step to match R7
CC = R1;
R6 = ROT R6 BY 1;
CC = R6 == R7;
IF !CC JUMP fail_lvl;
# Do it through each bit
CC = R5 == R6;
IF CC JUMP pass_lvl;
RTX;
pass_lvl:
dbg_pass;
fail_lvl:
dbg_fail;
|
tactcomplabs/xbgas-binutils-gdb | 2,946 | sim/testsuite/bfin/c_dspldst_ld_drhi_i.s | //Original:/testcases/core/c_dspldst_ld_drhi_i/c_dspldst_ld_drhi_i.dsp
// Spec Reference: c_dspldst ld_drhi_i
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load upper half of Dregs
R0.H = W [ I0 ];
R1.H = W [ I1 ];
R2.H = W [ I2 ];
R3.H = W [ I3 ];
R4.H = W [ I0 ];
R5.H = W [ I1 ];
R6.H = W [ I2 ];
R7.H = W [ I3 ];
CHECKREG r0, 0x02030000;
CHECKREG r1, 0x22230000;
CHECKREG r2, 0x42430000;
CHECKREG r3, 0x62630000;
CHECKREG r4, 0x02030000;
CHECKREG r5, 0x22230000;
CHECKREG r6, 0x42430000;
CHECKREG r7, 0x62630000;
R1.H = W [ I0 ];
R2.H = W [ I1 ];
R3.H = W [ I2 ];
R4.H = W [ I3 ];
R5.H = W [ I0 ];
R6.H = W [ I1 ];
R7.H = W [ I2 ];
R0.H = W [ I3 ];
CHECKREG r0, 0x62630000;
CHECKREG r1, 0x02030000;
CHECKREG r2, 0x22230000;
CHECKREG r3, 0x42430000;
CHECKREG r4, 0x62630000;
CHECKREG r5, 0x02030000;
CHECKREG r6, 0x22230000;
CHECKREG r7, 0x42430000;
R2.H = W [ I0 ];
R3.H = W [ I1 ];
R4.H = W [ I2 ];
R5.H = W [ I3 ];
R6.H = W [ I0 ];
R7.H = W [ I1 ];
R0.H = W [ I2 ];
R1.H = W [ I3 ];
CHECKREG r0, 0x42430000;
CHECKREG r1, 0x62630000;
CHECKREG r2, 0x02030000;
CHECKREG r3, 0x22230000;
CHECKREG r4, 0x42430000;
CHECKREG r5, 0x62630000;
CHECKREG r6, 0x02030000;
CHECKREG r7, 0x22230000;
R3.H = W [ I0 ];
R4.H = W [ I1 ];
R5.H = W [ I2 ];
R6.H = W [ I3 ];
R7.H = W [ I0 ];
R0.H = W [ I1 ];
R1.H = W [ I2 ];
R2.H = W [ I3 ];
CHECKREG r0, 0x22230000;
CHECKREG r1, 0x42430000;
CHECKREG r2, 0x62630000;
CHECKREG r3, 0x02030000;
CHECKREG r4, 0x22230000;
CHECKREG r5, 0x42430000;
CHECKREG r6, 0x62630000;
CHECKREG r7, 0x02030000;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,045 | sim/testsuite/bfin/random_0033.S | # Verify registers saturate and ASTAT bits are updated correctly
# with the RND12 subtract insn
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x24a00410 | _VS | _AV1S | _AV0 | _AC0 | _AC0_COPY | _AN);
imm32 R5, 0x0fb35119;
imm32 R6, 0xffffffff;
imm32 R7, 0x80000000;
R6.H = R5 - R7 (RND12);
checkreg R6, 0x7fffffff;
checkreg ASTAT, (0x24a00410 | _VS | _V | _AV1S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R3, 0x80003f8f;
imm32 R5, 0x6267c92c;
imm32 R6, 0x80000000;
R5.L = R3 - R6 (RND12);
checkreg R5, 0x62670004;
checkreg ASTAT, (0x08c08000 | _VS | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x04200c10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY);
imm32 R1, 0x7fff0000;
imm32 R5, 0x80000000;
R1.L = R5 - R5 (RND12);
checkreg ASTAT, (0x04200c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AZ);
checkreg R1, 0x7fff0000;
checkreg R5, 0x80000000;
dmm32 ASTAT, (0x40600e90 | _VS | _AV1S | _AV0S | _AQ | _CC);
imm32 R1, 0x80000000;
imm32 R5, 0x00008000;
imm32 R6, 0x00000000;
R5.L = R6 - R1 (RND12);
checkreg R5, 0x00007fff;
checkreg ASTAT, (0x40600e90 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x68300880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
imm32 R1, 0xf8ed0000;
imm32 R6, 0x80000000;
R1.H = R1 - R6 (RND12);
checkreg R1, 0x7fff0000;
checkreg ASTAT, (0x68300880 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x70d0c410 | _VS | _AV0S | _AQ);
imm32 R0, 0x80000000;
imm32 R1, 0x71455f95;
imm32 R4, 0xd4871012;
R4.H = R1 - R0 (RND12);
checkreg R4, 0x7fff1012;
checkreg ASTAT, (0x70d0c410 | _VS | _V | _AV0S | _AQ | _V_COPY);
dmm32 ASTAT, (0x34500e00 | _VS | _AV0S | _AC1 | _CC | _AZ);
imm32 R2, 0x00000000;
imm32 R5, 0x00000000;
imm32 R6, 0x80000000;
R2.L = R5 - R6 (RND12);
checkreg R2, 0x00007fff;
checkreg ASTAT, (0x34500e00 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY);
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,857 | sim/testsuite/bfin/c_dsp32alu_rh_rnd20_m.s | //Original:/testcases/core/c_dsp32alu_rh_rnd20_m/c_dsp32alu_rh_rnd20_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667a77;
R0.H = R0 - R0 (RND20);
R1.H = R0 - R1 (RND20);
R2.H = R0 - R2 (RND20);
R3.H = R0 - R3 (RND20);
R4.H = R0 - R4 (RND20);
R5.H = R0 - R5 (RND20);
R6.H = R0 - R6 (RND20);
R7.H = R0 - R7 (RND20);
CHECKREG r0, 0x00008911;
CHECKREG r1, 0xFD57AB1D;
CHECKREG r2, 0xFCB65515;
CHECKREG r3, 0xFB967717;
CHECKREG r4, 0xFA98891B;
CHECKREG r5, 0xF987AB1D;
CHECKREG r6, 0xF8BCA515;
CHECKREG r7, 0x079A7A77;
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xb4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5b78891b;
imm32 r5, 0x67bbab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667b77;
R0.H = R1 - R0 (RND20);
R1.H = R1 - R1 (RND20);
R2.H = R1 - R2 (RND20);
R3.H = R1 - R3 (RND20);
R4.H = R1 - R4 (RND20);
R5.H = R1 - R5 (RND20);
R6.H = R1 - R6 (RND20);
R7.H = R1 - R7 (RND20);
CHECKREG r0, 0x08228911;
CHECKREG r1, 0x0000AB1D;
CHECKREG r2, 0x04BC5515;
CHECKREG r3, 0xFB9A7717;
CHECKREG r4, 0xFA49891B;
CHECKREG r5, 0xF984AB1D;
CHECKREG r6, 0xF8BCB515;
CHECKREG r7, 0x079A7B77;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x3a445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x567a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0.H = R2 - R0 (RND20);
R1.H = R2 - R1 (RND20);
R2.H = R2 - R2 (RND20);
R3.H = R2 - R3 (RND20);
R4.H = R2 - R4 (RND20);
R5.H = R2 - R5 (RND20);
R6.H = R2 - R6 (RND20);
R7.H = R2 - R7 (RND20);
CHECKREG r0, 0x094E8911;
CHECKREG r1, 0x00FCAB1D;
CHECKREG r2, 0x00005515;
CHECKREG r3, 0xFB967717;
CHECKREG r4, 0xFA98891B;
CHECKREG r5, 0xF987AB1D;
CHECKREG r6, 0xF8BC5A15;
CHECKREG r7, 0x079A77A7;
imm32 r0, 0xb5678911;
imm32 r1, 0xb789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678ddb1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.H = R3 - R0 (RND20);
R1.H = R3 - R1 (RND20);
R2.H = R3 - R2 (RND20);
R3.H = R3 - R3 (RND20);
R4.H = R3 - R4 (RND20);
R5.H = R3 - R5 (RND20);
R6.H = R3 - R6 (RND20);
R7.H = R3 - R7 (RND20);
CHECKREG r0, 0x09178911;
CHECKREG r1, 0x08F5AB1D;
CHECKREG r2, 0x00995515;
CHECKREG r3, 0x00007717;
CHECKREG r4, 0xFA98891B;
CHECKREG r5, 0xF987DB1D;
CHECKREG r6, 0xF8BC5D15;
CHECKREG r7, 0x079A77D7;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5d78891b;
imm32 r5, 0x67d9ab1d;
imm32 r6, 0x744d5515;
imm32 r7, 0x8666dd77;
R0.H = R4 - R0 (RND20);
R1.H = R4 - R1 (RND20);
R2.H = R4 - R2 (RND20);
R3.H = R4 - R3 (RND20);
R4.H = R4 - R4 (RND20);
R5.H = R4 - R5 (RND20);
R6.H = R4 - R6 (RND20);
R7.H = R4 - R7 (RND20);
CHECKREG r0, 0x08818911;
CHECKREG r1, 0x035FAB1D;
CHECKREG r2, 0x08935515;
CHECKREG r3, 0x08717717;
CHECKREG r4, 0x0000891B;
CHECKREG r5, 0xF982AB1D;
CHECKREG r6, 0xF8BB5515;
CHECKREG r7, 0x079ADD77;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34d45515;
imm32 r3, 0x46667717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.H = R5 - R0 (RND20);
R1.H = R5 - R1 (RND20);
R2.H = R5 - R2 (RND20);
R3.H = R5 - R3 (RND20);
R4.H = R5 - R4 (RND20);
R5.H = R5 - R5 (RND20);
R6.H = R5 - R6 (RND20);
R7.H = R5 - R7 (RND20);
CHECKREG r0, 0x08228911;
CHECKREG r1, 0x0390AB1D;
CHECKREG r2, 0x032B5515;
CHECKREG r3, 0x02127717;
CHECKREG r4, 0x0111891B;
CHECKREG r5, 0x0000DB1D;
CHECKREG r6, 0xF8BC5D15;
CHECKREG r7, 0x079A77D7;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x46a67717;
imm32 r4, 0x56a8891b;
imm32 r5, 0x678aab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667a77;
R0.H = R6 - R0 (RND20);
R1.H = R6 - R1 (RND20);
R2.H = R6 - R2 (RND20);
R3.H = R6 - R3 (RND20);
R4.H = R6 - R4 (RND20);
R5.H = R6 - R5 (RND20);
R6.H = R6 - R6 (RND20);
R7.H = R6 - R7 (RND20);
CHECKREG r0, 0x0CEE8911;
CHECKREG r1, 0x049CAB1D;
CHECKREG r2, 0x03FA5515;
CHECKREG r3, 0x02DA7717;
CHECKREG r4, 0x01DA891B;
CHECKREG r5, 0x00CCAB1D;
CHECKREG r6, 0x0000A515;
CHECKREG r7, 0x079A7A77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R7 - R0 (RND20);
R1.H = R7 - R1 (RND20);
R2.H = R7 - R2 (RND20);
R3.H = R7 - R3 (RND20);
R4.H = R7 - R4 (RND20);
R5.H = R7 - R5 (RND20);
R6.H = R7 - R6 (RND20);
R7.H = R7 - R7 (RND20);
CHECKREG r0, 0xF7108911;
CHECKREG r1, 0xF5EEAB1D;
CHECKREG r2, 0xF5225515;
CHECKREG r3, 0xF4007717;
CHECKREG r4, 0xF2FF891B;
CHECKREG r5, 0xF1EEAB1D;
CHECKREG r6, 0xF1225515;
CHECKREG r7, 0x00007777;
imm32 r0, 0xe5678911;
imm32 r1, 0xe789ab1d;
imm32 r2, 0xe4445515;
imm32 r3, 0x4ee67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R6.H = R2 - R3 (RND20);
R1.H = R4 - R5 (RND20);
R5.H = R7 - R2 (RND20);
R3.H = R0 - R0 (RND20);
R0.H = R3 - R4 (RND20);
R2.H = R5 - R7 (RND20);
R7.H = R6 - R7 (RND20);
R4.H = R1 - R6 (RND20);
CHECKREG r0, 0xFA988911;
CHECKREG r1, 0xFEEFAB1D;
CHECKREG r2, 0x073C5515;
CHECKREG r3, 0x00007717;
CHECKREG r4, 0x005A891B;
CHECKREG r5, 0xFA22AB1D;
CHECKREG r6, 0xF956E515;
CHECKREG r7, 0x072F7E77;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x86667d77;
R3.H = R4 - R0 (RND20);
R1.H = R6 - R3 (RND20);
R4.H = R3 - R2 (RND20);
R6.H = R7 - R1 (RND20);
R2.H = R5 - R4 (RND20);
R7.H = R2 - R7 (RND20);
R0.H = R1 - R6 (RND20);
R5.H = R0 - R5 (RND20);
CHECKREG r0, 0x00EE8911;
CHECKREG r1, 0x06D3AB1D;
CHECKREG r2, 0x06AF5515;
CHECKREG r3, 0x07117717;
CHECKREG r4, 0xFC9D891B;
CHECKREG r5, 0xF996DB1D;
CHECKREG r6, 0xF7F9D515;
CHECKREG r7, 0x08057D77;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,881 | sim/testsuite/bfin/se_loop_nest_ppm_2.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm_2/se_loop_nest_ppm_2.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
// lsetup (l0s, l0s) lc0 = p0;
LSETUP ( l0s , l0s ) LC0 = P1;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
LSETUP ( l1e , l1e ) LC0 = P1;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
LSETUP ( l2e , l2e ) LC0 = P1;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
LSETUP ( l3e , l3e ) LC0 = P1;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
LSETUP ( l4e , l4e ) LC0 = P1;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
LSETUP ( l5e , l5e ) LC0 = P1;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC0 = P0;
LSETUP ( l6e , l6e ) LC0 = P1;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
LSETUP ( m0s , m0s ) LC1 = P0;
LSETUP ( m0s , m0s ) LC1 = P1;
m0s:[ -- SP ] = ( R7:5 );
LSETUP ( m1s , m1e ) LC1 = P0;
LSETUP ( m1e , m1e ) LC1 = P1;
m1s:R5 += 1;
m1e:[ -- SP ] = ( R7:5 );
LSETUP ( m2s , m2e ) LC1 = P0;
LSETUP ( m2e , m2e ) LC1 = P1;
m2s:R5 += 1;
R6 += 2;
m2e:[ -- SP ] = ( R7:5 );
LSETUP ( m3s , m3e ) LC1 = P0;
LSETUP ( m3e , m3e ) LC1 = P1;
m3s:R5 += 1;
R6 += 2;
R7 += 3;
m3e:[ -- SP ] = ( R7:5 );
LSETUP ( m4s , m4e ) LC1 = P0;
LSETUP ( m4e , m4e ) LC1 = P1;
m4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
m4e:[ -- SP ] = ( R7:4 );
LSETUP ( m5s , m5e ) LC1 = P0;
LSETUP ( m5e , m5e ) LC1 = P1;
m5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
m5e:[ -- SP ] = ( R7:4 );
LSETUP ( m6s , m6e ) LC1 = P0;
LSETUP ( m6e , m6e ) LC1 = P1;
m6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
m6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 2,927 | sim/testsuite/bfin/c_dspldst_ld_drlo_i.s | //Original:/testcases/core/c_dspldst_ld_drlo_i/c_dspldst_ld_drlo_i.dsp
// Spec Reference: c_dspldst ld_drlo_i
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
// Load Lower half of Dregs
R0.L = W [ I0 ];
R1.L = W [ I1 ];
R2.L = W [ I2 ];
R3.L = W [ I3 ];
R4.L = W [ I0 ];
R5.L = W [ I1 ];
R6.L = W [ I2 ];
R7.L = W [ I3 ];
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
CHECKREG r3, 0x00006263;
CHECKREG r4, 0x00000203;
CHECKREG r5, 0x00002223;
CHECKREG r6, 0x00004243;
CHECKREG r7, 0x00006263;
R1.L = W [ I0 ];
R2.L = W [ I1 ];
R3.L = W [ I2 ];
R4.L = W [ I3 ];
R5.L = W [ I0 ];
R6.L = W [ I1 ];
R7.L = W [ I2 ];
R0.L = W [ I3 ];
CHECKREG r0, 0x00006263;
CHECKREG r1, 0x00000203;
CHECKREG r2, 0x00002223;
CHECKREG r3, 0x00004243;
CHECKREG r4, 0x00006263;
CHECKREG r5, 0x00000203;
CHECKREG r6, 0x00002223;
CHECKREG r7, 0x00004243;
R2.L = W [ I0 ];
R3.L = W [ I1 ];
R4.L = W [ I2 ];
R5.L = W [ I3 ];
R6.L = W [ I0 ];
R7.L = W [ I1 ];
R0.L = W [ I2 ];
R1.L = W [ I3 ];
CHECKREG r0, 0x00004243;
CHECKREG r1, 0x00006263;
CHECKREG r2, 0x00000203;
CHECKREG r3, 0x00002223;
CHECKREG r4, 0x00004243;
CHECKREG r5, 0x00006263;
CHECKREG r6, 0x00000203;
CHECKREG r7, 0x00002223;
R3.L = W [ I0 ];
R4.L = W [ I1 ];
R5.L = W [ I2 ];
R6.L = W [ I3 ];
R7.L = W [ I0 ];
R0.L = W [ I1 ];
R1.L = W [ I2 ];
R2.L = W [ I3 ];
CHECKREG r0, 0x00002223;
CHECKREG r1, 0x00004243;
CHECKREG r2, 0x00006263;
CHECKREG r3, 0x00000203;
CHECKREG r4, 0x00002223;
CHECKREG r5, 0x00004243;
CHECKREG r6, 0x00006263;
CHECKREG r7, 0x00000203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 5,591 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_h.s | //Original:testcases/core/c_ldst_ld_d_p_mm_h/c_ldst_ld_d_p_mm_h.dsp
// Spec Reference: c_ldst ld d [p--] h
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// initial values
loadsym p5, DATA_ADDR_1, 0x10;
loadsym p1, DATA_ADDR_2, 0x10;
loadsym p2, DATA_ADDR_3, 0x10;
loadsym p4, DATA_ADDR_5, 0x10;
loadsym fp, DATA_ADDR_6, 0x10;
R0 = W [ P5 -- ] (Z);
R1 = W [ P1 -- ] (Z);
R2 = W [ P2 -- ] (Z);
R4 = W [ P4 -- ] (Z);
R5 = W [ FP -- ] (Z);
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00003233;
CHECKREG r2, 0x00005253;
CHECKREG r4, 0x00009293;
CHECKREG r5, 0x00001213;
R1 = W [ P5 -- ] (Z);
R2 = W [ P1 -- ] (Z);
R3 = W [ P2 -- ] (Z);
R5 = W [ P4 -- ] (Z);
R6 = W [ FP -- ] (Z);
CHECKREG r0, 0x00001213;
CHECKREG r1, 0x00000C0D;
CHECKREG r2, 0x00002C2D;
CHECKREG r3, 0x00004C4D;
CHECKREG r5, 0x00008C8D;
CHECKREG r6, 0x00000C0D;
R2 = W [ P5 -- ] (Z);
R3 = W [ P1 -- ] (Z);
R4 = W [ P2 -- ] (Z);
R6 = W [ P4 -- ] (Z);
R7 = W [ FP -- ] (Z);
CHECKREG r1, 0x00000C0D;
CHECKREG r2, 0x00000E0F;
CHECKREG r3, 0x00002E2F;
CHECKREG r4, 0x00004E4F;
CHECKREG r6, 0x00008E8F;
CHECKREG r7, 0x00000E0F;
R3 = W [ P5 -- ] (Z);
R4 = W [ P1 -- ] (Z);
R5 = W [ P2 -- ] (Z);
R7 = W [ P4 -- ] (Z);
R0 = W [ FP -- ] (Z);
CHECKREG r0, 0x00000809;
CHECKREG r2, 0x00000E0F;
CHECKREG r3, 0x00000809;
CHECKREG r4, 0x00002829;
CHECKREG r5, 0x00004849;
CHECKREG r7, 0x00008889;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,691 | sim/testsuite/bfin/c_dagmodim_lnz_imltbl.s | //Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp
// Spec Reference: dagmodim l not zero & i+m < b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 i0, 0x00001000;
imm32 i1, 0x00001100;
imm32 i2, 0x00001010;
imm32 i3, 0x00001001;
imm32 b0, 0x0000110e;
imm32 b1, 0x0000110c;
imm32 b2, 0x0000110a;
imm32 b3, 0x00001108;
imm32 l0, 0x000000a1;
imm32 l1, 0x000000b2;
imm32 l2, 0x000000c3;
imm32 l3, 0x000000d4;
imm32 m0, 0x00000005;
imm32 m1, 0x00000004;
imm32 m2, 0x00000003;
imm32 m3, 0x00000002;
I0 += M0;
I1 += M1;
I2 += M2;
I3 += M3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M1;
I1 += M2;
I2 += M3;
I3 += M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001005;
CHECKREG r1, 0x00001104;
CHECKREG r2, 0x00001013;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001009;
CHECKREG r5, 0x00001107;
CHECKREG r6, 0x00001015;
CHECKREG r7, 0x00001008;
I0 -= M2;
I1 -= M3;
I2 -= M0;
I3 -= M1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 -= M3;
I1 -= M2;
I2 -= M1;
I3 -= M0;
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x000010A7;
CHECKREG r1, 0x000011B7;
CHECKREG r2, 0x000010D3;
CHECKREG r3, 0x000010D8;
CHECKREG r4, 0x00001146;
CHECKREG r5, 0x000011B4;
CHECKREG r6, 0x00001192;
CHECKREG r7, 0x000011A7;
I0 += M3 (BREV);
I1 += M0 (BREV);
I2 += M1 (BREV);
I3 += M2 (BREV);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
I0 += M2 (BREV);
I1 += M3 (BREV);
I2 += M0 (BREV);
I3 += M1 (BREV);
R4 = I0;
R5 = I1;
R6 = I2;
R7 = I3;
CHECKREG r0, 0x00001145;
CHECKREG r1, 0x000011B3;
CHECKREG r2, 0x00001196;
CHECKREG r3, 0x000011A5;
CHECKREG r4, 0x00001146;
CHECKREG r5, 0x000011B0;
CHECKREG r6, 0x00001190;
CHECKREG r7, 0x000011A3;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,701 | sim/testsuite/bfin/c_dsp32alu_bytepack.s | //Original:/testcases/core/c_dsp32alu_bytepack/c_dsp32alu_bytepack.dsp
// Spec Reference: dsp32alu bytepack
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R4 = BYTEPACK ( R0 , R0 );
R5 = BYTEPACK ( R0 , R1 );
R6 = BYTEPACK ( R0 , R2 );
R7 = BYTEPACK ( R0 , R3 );
CHECKREG r4, 0x67116711;
CHECKREG r5, 0x891D6711;
CHECKREG r6, 0x44156711;
CHECKREG r7, 0x66176711;
imm32 r0, 0x1567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445525;
imm32 r3, 0x46667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7cccdd2d;
imm32 r7, 0x8eeeffff;
R4 = BYTEPACK ( R1 , R4 );
R5 = BYTEPACK ( R1 , R5 );
R6 = BYTEPACK ( R1 , R6 );
R7 = BYTEPACK ( R1 , R7 );
CHECKREG r4, 0x8829892D;
CHECKREG r5, 0xAA2B892D;
CHECKREG r6, 0xCC2D892D;
CHECKREG r7, 0xEEFF892D;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
R4 = BYTEPACK ( R2 , R0 );
R5 = BYTEPACK ( R2 , R1 );
R6 = BYTEPACK ( R2 , R2 );
R7 = BYTEPACK ( R2 , R3 );
CHECKREG r4, 0x67AB4455;
CHECKREG r5, 0x89CD4455;
CHECKREG r6, 0x44554455;
CHECKREG r7, 0x66774455;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0xaeaa4bbb;
imm32 r6, 0xcfccd44d;
imm32 r7, 0xe1eefff4;
R4 = BYTEPACK ( R3 , R4 );
R5 = BYTEPACK ( R3 , R5 );
R6 = BYTEPACK ( R3 , R6 );
R7 = BYTEPACK ( R3 , R7 );
CHECKREG r4, 0x88996477;
CHECKREG r5, 0xAABB6477;
CHECKREG r6, 0xCC4D6477;
CHECKREG r7, 0xEEF46477;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,638 | sim/testsuite/bfin/random_0012.S | # test VIT_MAX behavior when high Acc bits are set
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0xd81562e8;
dmm32 A0.x, 0xffffffff;
imm32 R4, 0x15c2d815;
imm32 R5, 0xc9bd3a6b;
R4.L = VIT_MAX (R5) (ASR);
checkreg R4, 0x15c23a6b;
checkreg A0.w, 0x6c0ab174;
checkreg A0.x, 0x0000007f;
checkreg ASTAT, (0x5860c690 | _VS | _AV0S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0x715cf6e6;
dmm32 A0.x, 0xffffffb6;
imm32 R3, 0x3a89c7ed;
imm32 R4, 0x4819bbf9;
R3.L = VIT_MAX (R4) (ASR);
checkreg R3, 0x3a89bbf9;
checkreg A0.w, 0x38ae7b73;
checkreg A0.x, 0x0000005b;
checkreg ASTAT, (0x48308090 | _AV1 | _AV0 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 A0.w, 0xea06f130;
dmm32 A0.x, 0xffffffff;
imm32 R2, 0x62ce98f1;
imm32 R5, 0x045415f9;
R2.L = VIT_MAX (R5) (ASR);
checkreg R2, 0x62ce15f9;
checkreg A0.w, 0x75037898;
checkreg A0.x, 0x0000007f;
checkreg ASTAT, (0x18104c10 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0xffffffff;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0xc9647fff;
imm32 R6, 0x1d4baeb8;
R6.L = VIT_MAX (R0) (ASR);
checkreg R6, 0x1d4bc964;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0x0000007f;
checkreg ASTAT, (0x0090ce10 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN);
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,235 | sim/testsuite/bfin/c_multi_issue_dsp_ld_ld.s | //Original:/testcases/core/c_multi_issue_dsp_ld_ld/c_multi_issue_dsp_ld_ld.dsp
// Spec Reference: dsp32mac and 2 loads
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
loadsym I0, DATA0
loadsym I1, DATA1
loadsym P1, DATA0
loadsym P2, DATA1
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
A1 += R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ I0 ++ ] || R3 = [ I1 ++ ];
A1 += R6.H * R7.H, A0 += R6.H * R7.L || R4 = [ P1 ++ ] || R5 = [ I1 ++ ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x000A0000;
CHECKREG r1, 0x00F00100;
CHECKREG r2, 0x000B0001;
CHECKREG r3, 0x00E00101;
CHECKREG r4, 0x000A0000;
CHECKREG r5, 0x00D00102;
CHECKREG r6, 0x92793486;
CHECKREG r7, 0xDD2F9BAA;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 = R0.L * R1.L, A0 = R0.L * R1.L || R4 = [ P1 ++ ] || R6 = [ I0 ++ ];
A1 -= R2.L * R3.L, A0 += R2.L * R3.H || R2 = [ P2 ++ ] || R3 = [ I1 ++ ];
A1 += R4.H * R6.H, A0 -= R4.H * R6.L || [ P2 ++ ] = R5 || R7 = [ I1 ++ ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x12245618;
CHECKREG r1, 0x23256719;
CHECKREG r2, 0x00F00100;
CHECKREG r3, 0x00C00103;
CHECKREG r4, 0x000B0001;
CHECKREG r5, 0x67291214;
CHECKREG r6, 0x863ABC70;
CHECKREG r7, 0xB4EF6A10;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 += R0.H * R1.H, A0 += R0.L * R1.L || R2 = [ P1 ++ ] || R0 = [ I1 -- ];
A1 += R2.H * R3.H, A0 += R2.L * R3.H || NOP || R4 = [ I0 ++ ];
A1 = R4.H * R5.L, A0 += R4.H * R5.L || R3 = [ P2 -- ] || R5 = [ I0 -- ];
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00A00105;
CHECKREG r1, 0x25256749;
CHECKREG r2, 0x000C0002;
CHECKREG r3, 0x00D00102;
CHECKREG r4, 0x000D0003;
CHECKREG r5, 0x000E0004;
CHECKREG r6, 0xCBDCD104;
CHECKREG r7, 0x0001DAE8;
imm32 r1, 0x02450789;
imm32 r2, 0x0356089a;
imm32 r3, 0x04670912;
imm32 r4, 0x05780123;
imm32 r5, 0x06890234;
imm32 r6, 0x07230567;
imm32 r7, 0x00230567;
R2 = R0 +|+ R7, R4 = R0 -|- R7 (ASR) || R1 = [ I1 ++ ] || R0 = [ I0 -- ];
R1 = R6 +|+ R3, R5 = R6 -|- R3 || R6 = [ P1 ] || R3 = [ I0 -- ];
R5 = R4 +|+ R2, R0 = R4 -|- R2 (CO) || NOP || R4 = [ I0 ++ ];
CHECKREG r0, 0xFA99FFDD;
CHECKREG r1, 0x0B8A0E79;
CHECKREG r2, 0x00610336;
CHECKREG r3, 0x000C0002;
CHECKREG r4, 0x000B0001;
CHECKREG r5, 0x009F0105;
CHECKREG r6, 0x000D0003;
CHECKREG r7, 0x00230567;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
.dd 0x001d0003
.dd 0x00010004
.dd 0x00010005
.dd 0x02100006
.dd 0x02200007
.dd 0x02300008
.dd 0x02200009
.dd 0x0250000a
.dd 0x0260000b
.dd 0x0270000c
.dd 0x0280000d
.dd 0x0290000e
.dd 0x2100000f
.dd 0x22000010
.dd 0x22000011
.dd 0x24000012
.dd 0x25000013
.dd 0x26000014
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
.dd 0x00b00104
.dd 0x00a00105
.dd 0x00900106
.dd 0x00800107
.dd 0x00100108
.dd 0x00200109
.dd 0x0030010a
.dd 0x0040010b
.dd 0x0050011c
.dd 0x0060010d
.dd 0x0070010e
.dd 0x0080010f
.dd 0x00900110
.dd 0x01000111
.dd 0x02000112
.dd 0x03000113
.dd 0x04000114
.dd 0x05000115
.dd 0x03f00100
.dd 0x03e00101
.dd 0x03d00102
.dd 0x03c00103
.dd 0x03b00104
.dd 0x03a00105
.dd 0x03900106
.dd 0x03800107
.dd 0x03100108
.dd 0x03200109
.dd 0x0330010a
.dd 0x0330010b
.dd 0x0350011c
.dd 0x0360010d
.dd 0x0370010e
.dd 0x0380010f
.dd 0x03900110
.dd 0x31000111
.dd 0x32000112
.dd 0x33000113
.dd 0x34000114
|
tactcomplabs/xbgas-binutils-gdb | 5,561 | sim/testsuite/bfin/dbg_tr_simplejp.S | //Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp
// Description: This test performs simple jumps and verifies the trace buffer
// recording for simple jumps.
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(mmrs.inc)
include(selfcheck.inc)
include(symtable.inc)
#ifndef ITABLE
#define ITABLE CODE_ADDR_1 //
#endif
// This test embeds .text offsets, so pad our test so it lines up.
.space 0x5e
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC);
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
LD32_LABEL(r7, DUMMY);
RETI = r7;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
START :
WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer
// TBUFPWR = 1
// TBUFEN = 1
// TBUFOVF = 0
// CMPLP = 0
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label1; // 0x0224
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label2: R5.H = 0x7777; // 0x0234
R5.L = 0x7888;
JUMP.S label3; //0x023c
R6.L = 0x1111; // Will be killed
R6.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
label1: R4.H = 0x5555; // 0x0250
R4.L = 0x6666;
NOP;
JUMP.S label2; // 0x0258
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
label3: R6.H = 0x7999; //0x026c
R6.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer
NOP;
NOP;
NOP;
NOP;
NOP;
// Read the contents of the Trace Buffer
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000003);
// Read 3rd Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x0000026c);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000003);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x0000023c);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000002);
// Read 2nd Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x00000234);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000002);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x0000025a);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000001);
// Read ist Entry of the Trace Buffer
RD_MMR(TBUF, p0, r0);
CHECKREG(r0, 0x00000250);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000001);
RD_MMR(TBUF, p0, r1);
CHECKREG(r1, 0x00000224);
RD_MMR(TBUFSTAT, p0, r2);
CHECKREG(r2, 0x00000000);
WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
|
tactcomplabs/xbgas-binutils-gdb | 4,081 | sim/testsuite/bfin/c_cc2stat_cc_aq.s | //Original:/testcases/core/c_cc2stat_cc_aq/c_cc2stat_cc_aq.dsp
// Spec Reference: cc2stat cc aq
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AQ 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC = AQ; //
R0 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC = AQ; //
R1 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC = AQ; //
R2 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC = AQ; //
R3 = CC; //
// test cc |= AQ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC |= AQ; //
R4 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC |= AQ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC |= AQ; //
R6 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC |= AQ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
// test CC &= AQ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC &= AQ; //
R4 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC &= AQ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC &= AQ; //
R6 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC &= AQ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
// test CC ^= AQ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
CC ^= AQ; //
R4 = CC; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
CC ^= AQ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
CC ^= AQ; //
R6 = CC; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
CC ^= AQ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
// test AQ = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ = CC; //
R0 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ = CC; //
R1 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ = CC; //
R2 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ = CC; //
R3 = ASTAT; //
// test AQ |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ |= CC; //
R4 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ |= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ |= CC; //
R6 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ |= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x00000060;
CHECKREG r7, 0x00000060;
// test AQ &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ &= CC; //
R4 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ &= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ &= CC; //
R6 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ &= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000060;
// test AQ ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AQ = 0
AQ ^= CC; //
R4 = ASTAT; //
R7 = 0x40 (X);
ASTAT = R7; // cc = 0, AQ = 1
AQ ^= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AQ = 0
AQ ^= CC; //
R6 = ASTAT; //
R7 = 0x60 (X);
ASTAT = R7; // cc = 1, AQ = 1
AQ ^= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000040;
CHECKREG r6, 0x00000060;
CHECKREG r7, 0x00000020;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,851 | sim/testsuite/bfin/c_seq_ac_regmv_pushpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp
// Spec Reference: sequencer stage AC (regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
//RAISE 2; // RTN
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
//RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:1 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
//RAISE 6; // RTI
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:2 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
//RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:2 ) = [ SP ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
//RAISE 8; // RTI
P1 = R1;
R5 = P1;
( R7:1 ) = [ SP ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
//RAISE 9; // RTI
P2 = R2;
R5 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 9,304 | sim/testsuite/bfin/c_dsp32shift_lf.s | //Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : mix data, count (+)= (half reg)
// d_reg = lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01210001;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R7 = LSHIFT R0 BY R0.L;
R6 = LSHIFT R1 BY R0.L;
R0 = LSHIFT R2 BY R0.L;
R1 = LSHIFT R3 BY R0.L;
R2 = LSHIFT R4 BY R0.L;
R3 = LSHIFT R5 BY R0.L;
R4 = LSHIFT R6 BY R0.L;
R5 = LSHIFT R7 BY R0.L;
CHECKREG r0, 0x4682CF12;
CHECKREG r1, 0xE2680000;
CHECKREG r2, 0x26AC0000;
CHECKREG r3, 0x6AF00000;
CHECKREG r4, 0xB3C00000;
CHECKREG r5, 0x00080000;
CHECKREG r6, 0x2462ACF0;
CHECKREG r7, 0x02420002;
imm32 r0, 0x01220002;
imm32 r1, 0x12325678;
imm32 r2, 0x23426789;
imm32 r3, 0x3452789a;
imm32 r4, 0x956289ab;
imm32 r5, 0xa6729abc;
imm32 r6, 0xb782abcd;
imm32 r7, 0xc892bcde;
R1.L = 2;
R3 = LSHIFT R0 BY R1.L;
R4 = LSHIFT R1 BY R1.L;
R5 = LSHIFT R2 BY R1.L;
R6 = LSHIFT R3 BY R1.L;
R7 = LSHIFT R4 BY R1.L;
R0 = LSHIFT R5 BY R1.L;
R1 = LSHIFT R6 BY R1.L;
R2 = LSHIFT R7 BY R1.L;
CHECKREG r0, 0x34267890;
CHECKREG r1, 0x48800080;
CHECKREG r2, 0x23200020;
CHECKREG r3, 0x04880008;
CHECKREG r4, 0x48C80008;
CHECKREG r5, 0x8D099E24;
CHECKREG r6, 0x12200020;
CHECKREG r7, 0x23200020;
imm32 r0, 0x01230002;
imm32 r1, 0x12335678;
imm32 r2, 0x23436789;
imm32 r3, 0x3453789a;
imm32 r4, 0x456389ab;
imm32 r5, 0x56739abc;
imm32 r6, 0x6783abcd;
imm32 r7, 0x789abcde;
R2 = 14;
R0 = LSHIFT R4 BY R2.L;
R1 = LSHIFT R5 BY R2.L;
R2 = LSHIFT R6 BY R2.L;
R3 = LSHIFT R7 BY R2.L;
CHECKREG r0, 0xE26AC000;
CHECKREG r1, 0xE6AF0000;
CHECKREG r2, 0xEAF34000;
CHECKREG r3, 0x789ABCDE;
imm32 r0, 0x01240002;
imm32 r1, 0x12345678;
imm32 r2, 0x23446789;
imm32 r3, 0x3454789a;
imm32 r4, 0xa56489ab;
imm32 r5, 0xb6749abc;
imm32 r6, 0xc784abcd;
imm32 r7, 0xd894bcde;
R3.L = 15;
R4 = LSHIFT R0 BY R3.L;
R5 = LSHIFT R1 BY R3.L;
R6 = LSHIFT R2 BY R3.L;
R7 = LSHIFT R3 BY R3.L;
R0 = LSHIFT R4 BY R3.L;
R1 = LSHIFT R5 BY R3.L;
R2 = LSHIFT R6 BY R3.L;
R3 = LSHIFT R7 BY R3.L;
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0xC0000000;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x2B3C0000;
CHECKREG r6, 0x33C48000;
CHECKREG r7, 0x00078000;
imm32 r0, 0x01250002;
imm32 r1, 0x12355678;
imm32 r2, 0x23456789;
imm32 r3, 0x3455789a;
imm32 r4, 0x456589ab;
imm32 r5, 0x56759abc;
imm32 r6, 0x6785abcd;
imm32 r7, 0x7895bcde;
R4.L = -1;
R7 = LSHIFT R0 BY R4.L;
R6 = LSHIFT R1 BY R4.L;
R5 = LSHIFT R2 BY R4.L;
R3 = LSHIFT R4 BY R4.L;
R2 = LSHIFT R5 BY R4.L;
R1 = LSHIFT R6 BY R4.L;
R0 = LSHIFT R7 BY R4.L;
R4 = LSHIFT R3 BY R4.L;
CHECKREG r0, 0x00494000;
CHECKREG r1, 0x048D559E;
CHECKREG r2, 0x08D159E2;
CHECKREG r3, 0x22B2FFFF;
CHECKREG r4, 0x11597FFF;
CHECKREG r5, 0x11A2B3C4;
CHECKREG r6, 0x091AAB3C;
CHECKREG r7, 0x00928001;
imm32 r0, 0x01260002;
imm32 r1, 0x82365678;
imm32 r2, 0x93466789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56689ab;
imm32 r5, 0xc6769abc;
imm32 r6, 0xd786abcd;
imm32 r7, 0xe896bcde;
R5.L = -8;
R6 = LSHIFT R0 BY R5.L;
R7 = LSHIFT R1 BY R5.L;
R0 = LSHIFT R2 BY R5.L;
R1 = LSHIFT R3 BY R5.L;
R2 = LSHIFT R4 BY R5.L;
R3 = LSHIFT R5 BY R5.L;
R4 = LSHIFT R6 BY R5.L;
R5 = LSHIFT R7 BY R5.L;
CHECKREG r0, 0x00934667;
CHECKREG r1, 0x00A45678;
CHECKREG r2, 0x00B56689;
CHECKREG r3, 0x00C676FF;
CHECKREG r4, 0x00000126;
CHECKREG r5, 0x00008236;
CHECKREG r6, 0x00012600;
CHECKREG r7, 0x00823656;
imm32 r0, 0x01270002;
imm32 r1, 0x12375678;
imm32 r2, 0x23476789;
imm32 r3, 0x3457789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56779abc;
imm32 r6, 0x6787abcd;
imm32 r7, 0x7897bcde;
R6.L = -15;
R7 = LSHIFT R0 BY R6.L;
R0 = LSHIFT R1 BY R6.L;
R1 = LSHIFT R2 BY R6.L;
R2 = LSHIFT R3 BY R6.L;
R3 = LSHIFT R4 BY R6.L;
R4 = LSHIFT R5 BY R6.L;
R5 = LSHIFT R6 BY R6.L;
R6 = LSHIFT R7 BY R6.L;
CHECKREG r0, 0x0000246E;
CHECKREG r1, 0x0000468E;
CHECKREG r2, 0x000068AE;
CHECKREG r3, 0x00008ACF;
CHECKREG r4, 0x0000ACEF;
CHECKREG r5, 0x0000CF0F;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0000024E;
imm32 r0, 0x01280002;
imm32 r1, 0x82385678;
imm32 r2, 0x93486789;
imm32 r3, 0xa458789a;
imm32 r4, 0xb56889ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd788abcd;
imm32 r7, 0xe898bcde;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L;
R1 = LSHIFT R1 BY R7.L;
R2 = LSHIFT R2 BY R7.L;
R3 = LSHIFT R3 BY R7.L;
R4 = LSHIFT R4 BY R7.L;
R5 = LSHIFT R5 BY R7.L;
R6 = LSHIFT R6 BY R7.L;
R7 = LSHIFT R7 BY R7.L;
CHECKREG r0, 0x00000128;
CHECKREG r1, 0x00008238;
CHECKREG r2, 0x00009348;
CHECKREG r3, 0x0000A458;
CHECKREG r4, 0x0000B568;
CHECKREG r5, 0x0000C678;
CHECKREG r6, 0x0000D788;
CHECKREG r7, 0x0000E898;
imm32 r0, 0x81290002;
imm32 r1, 0x92395678;
imm32 r2, 0xa3496789;
imm32 r3, 0xb459789a;
imm32 r4, 0xc56989ab;
imm32 r5, 0xd6799abc;
imm32 r6, 0xe789abcd;
imm32 r7, 0xf899bcde;
R0.L = 4;
//r0 = lshift (r0 by rl0);
R1 = LSHIFT R1 BY R0.L;
R2 = LSHIFT R2 BY R0.L;
R3 = LSHIFT R3 BY R0.L;
R4 = LSHIFT R4 BY R0.L;
R5 = LSHIFT R5 BY R0.L;
R6 = LSHIFT R6 BY R0.L;
R7 = LSHIFT R7 BY R0.L;
CHECKREG r1, 0x23956780;
CHECKREG r2, 0x34967890;
CHECKREG r3, 0x459789A0;
CHECKREG r4, 0x56989AB0;
CHECKREG r5, 0x6799ABC0;
CHECKREG r6, 0x789ABCD0;
CHECKREG r7, 0x899BCDE0;
imm32 r0, 0x012a0002;
imm32 r1, 0x123a5678;
imm32 r2, 0x234a6789;
imm32 r3, 0x345a789a;
imm32 r4, 0x456a89ab;
imm32 r5, 0x567a9abc;
imm32 r6, 0x678aabcd;
imm32 r7, 0xf89abcde;
R1.L = 2;
R7 = LSHIFT R0 BY R1.L;
R6 = LSHIFT R1 BY R1.L;
R5 = LSHIFT R2 BY R1.L;
R4 = LSHIFT R3 BY R1.L;
R3 = LSHIFT R4 BY R1.L;
R2 = LSHIFT R5 BY R1.L;
R0 = LSHIFT R6 BY R1.L;
R1 = LSHIFT R7 BY R1.L;
CHECKREG r0, 0x23A00020;
CHECKREG r1, 0x12A00020;
CHECKREG r2, 0x34A67890;
CHECKREG r3, 0x45A789A0;
CHECKREG r4, 0xD169E268;
CHECKREG r5, 0x8D299E24;
CHECKREG r6, 0x48E80008;
CHECKREG r7, 0x04A80008;
imm32 r0, 0x012b0002;
imm32 r1, 0x123b5678;
imm32 r2, 0x234b6789;
imm32 r3, 0x345b789a;
imm32 r4, 0x456b89ab;
imm32 r5, 0x567b9abc;
imm32 r6, 0x678babcd;
imm32 r7, 0x789bbcde;
R2.L = 15;
R0 = LSHIFT R0 BY R2.L;
R1 = LSHIFT R1 BY R2.L;
R3 = LSHIFT R3 BY R2.L;
R4 = LSHIFT R4 BY R2.L;
R5 = LSHIFT R5 BY R2.L;
R6 = LSHIFT R6 BY R2.L;
R7 = LSHIFT R7 BY R2.L;
R2 = LSHIFT R2 BY R2.L;
CHECKREG r0, 0x80010000;
CHECKREG r1, 0xAB3C0000;
CHECKREG r2, 0x80078000;
CHECKREG r3, 0xBC4D0000;
CHECKREG r4, 0xC4D58000;
CHECKREG r5, 0xCD5E0000;
CHECKREG r6, 0xD5E68000;
CHECKREG r7, 0xDE6F0000;
imm32 r0, 0x012c0002;
imm32 r1, 0x123c5678;
imm32 r2, 0x234c6789;
imm32 r3, 0x345c789a;
imm32 r4, 0x456c89ab;
imm32 r5, 0x567c9abc;
imm32 r6, 0x678cabcd;
imm32 r7, 0x789cbcde;
R3.L = 16;
R0 = LSHIFT R0 BY R3.L;
R1 = LSHIFT R1 BY R3.L;
R2 = LSHIFT R2 BY R3.L;
R4 = LSHIFT R4 BY R3.L;
R5 = LSHIFT R5 BY R3.L;
R6 = LSHIFT R6 BY R3.L;
R7 = LSHIFT R7 BY R3.L;
R3 = LSHIFT R3 BY R3.L;
CHECKREG r0, 0x00020000;
CHECKREG r1, 0x56780000;
CHECKREG r2, 0x67890000;
CHECKREG r3, 0x00100000;
CHECKREG r4, 0x89AB0000;
CHECKREG r5, 0x9ABC0000;
CHECKREG r6, 0xABCD0000;
CHECKREG r7, 0xBCDE0000;
imm32 r0, 0x012d0002;
imm32 r1, 0x123d5678;
imm32 r2, 0x234d6789;
imm32 r3, 0x345d789a;
imm32 r4, 0x456d89ab;
imm32 r5, 0x567d9abc;
imm32 r6, 0x678dabcd;
imm32 r7, 0x789dbcde;
R4.L = -9;
R7 = LSHIFT R0 BY R4.L;
R0 = LSHIFT R1 BY R4.L;
R1 = LSHIFT R2 BY R4.L;
R2 = LSHIFT R3 BY R4.L;
//r4 = lshift (r4 by rl4);
R3 = LSHIFT R5 BY R4.L;
R5 = LSHIFT R6 BY R4.L;
R6 = LSHIFT R7 BY R4.L;
CHECKREG r0, 0x00091EAB;
CHECKREG r1, 0x0011A6B3;
CHECKREG r2, 0x001A2EBC;
CHECKREG r3, 0x002B3ECD;
CHECKREG r4, 0x456DFFF7;
CHECKREG r5, 0x0033C6D5;
CHECKREG r6, 0x0000004B;
CHECKREG r7, 0x00009680;
imm32 r0, 0x012e0002;
imm32 r1, 0x123e5678;
imm32 r2, 0x234e6789;
imm32 r3, 0x345e789a;
imm32 r4, 0x456e89ab;
imm32 r5, 0x567e9abc;
imm32 r6, 0x678eabcd;
imm32 r7, 0x789ebcde;
R5.L = -14;
R0 = LSHIFT R0 BY R5.L;
R1 = LSHIFT R1 BY R5.L;
R2 = LSHIFT R2 BY R5.L;
R3 = LSHIFT R3 BY R5.L;
R4 = LSHIFT R4 BY R5.L;
//r5 = lshift (r5 by rl5);
R6 = LSHIFT R6 BY R5.L;
R7 = LSHIFT R7 BY R5.L;
CHECKREG r0, 0x000004B8;
CHECKREG r1, 0x000048F9;
CHECKREG r2, 0x00008D39;
CHECKREG r3, 0x0000D179;
CHECKREG r4, 0x000115BA;
CHECKREG r5, 0x567EFFF2;
CHECKREG r6, 0x00019E3A;
CHECKREG r7, 0x0001E27A;
imm32 r0, 0x012f0002;
imm32 r1, 0x623f5678;
imm32 r2, 0x734f6789;
imm32 r3, 0x845f789a;
imm32 r4, 0x956f89ab;
imm32 r5, 0xa67f9abc;
imm32 r6, 0xc78fabcd;
imm32 r7, 0xd89fbcde;
R6.L = -15;
R0 = LSHIFT R0 BY R6.L;
R1 = LSHIFT R1 BY R6.L;
R2 = LSHIFT R2 BY R6.L;
R3 = LSHIFT R3 BY R6.L;
R4 = LSHIFT R4 BY R6.L;
R5 = LSHIFT R5 BY R6.L;
//r6 = lshift (r6 by rl6);
R7 = LSHIFT R7 BY R6.L;
CHECKREG r0, 0x0000025E;
CHECKREG r1, 0x0000C47E;
CHECKREG r2, 0x0000E69E;
CHECKREG r3, 0x000108BE;
CHECKREG r4, 0x00012ADF;
CHECKREG r5, 0x00014CFF;
CHECKREG r6, 0xC78FFFF1;
CHECKREG r7, 0x0001B13F;
imm32 r0, 0x71230072;
imm32 r1, 0x82345678;
imm32 r2, 0x93456779;
imm32 r3, 0xa456787a;
imm32 r4, 0xb567897b;
imm32 r5, 0xc6789a7c;
imm32 r6, 0x6789ab7d;
imm32 r7, 0x789abc7e;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L;
R1 = LSHIFT R1 BY R7.L;
R2 = LSHIFT R2 BY R7.L;
R3 = LSHIFT R3 BY R7.L;
R4 = LSHIFT R4 BY R7.L;
R5 = LSHIFT R5 BY R7.L;
R6 = LSHIFT R6 BY R7.L;
R7 = LSHIFT R7 BY R7.L;
CHECKREG r0, 0x00007123;
CHECKREG r1, 0x00008234;
CHECKREG r2, 0x00009345;
CHECKREG r3, 0x0000A456;
CHECKREG r4, 0x0000B567;
CHECKREG r5, 0x0000C678;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x0000789A;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,891 | sim/testsuite/bfin/c_loopsetup_nested_bot.s | //Original:/testcases/core/c_loopsetup_nested_bot/c_loopsetup_nested_bot.dsp
// Spec Reference: loopsetup nested same bottom
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
ASTAT = r0;
//p0 = 2;
P1 = 2;
P2 = 4;
P3 = 6;
P4 = 8;
P5 = 10;
SP = 12;
FP = 14;
R0 = 0x05;
R1 = 0x10;
R2 = 0x20;
R3 = 0x32;
R4 = 0x46 (X);
R5 = 0x50 (X);
R6 = 0x68 (X);
R7 = 0x72 (X);
LSETUP ( start1 , end1 ) LC0 = P1;
start1: R0 += 1;
R1 += -2;
LSETUP ( start2 , end2 ) LC1 = P2;
start2: R4 += 4;
end2: R5 += -5;
R3 += 1;
end1: R2 += 3;
R3 += 4;
LSETUP ( start3 , end3 ) LC1 = P3;
start3: R6 += 6;
LSETUP ( start4 , end3 ) LC0 = P4 >> 1;
start4: R0 += 1;
R1 += -2;
end4: R2 += 3;
R3 += 4;
end3: R7 += -7;
R3 += 1;
CHECKREG r0, 0x00000010;
CHECKREG r1, 0xFFFFFFFA;
CHECKREG r2, 0x00000041;
CHECKREG r3, 0x0000005D;
CHECKREG r4, 0x00000066;
CHECKREG r5, 0x00000028;
CHECKREG r6, 0x0000008C;
CHECKREG r7, 0x00000033;
R0 = 0x05;
R1 = 0x10;
R2 = 0x14;
R3 = 0x18;
R4 = 0x20;
R5 = 0x12;
R6 = 0x24;
R7 = 0x16;
LSETUP ( start5 , end5 ) LC0 = P5;
start5: R4 += 1;
LSETUP ( start6 , end5 ) LC1 = SP >> 1;
start6: R6 += 4;
end6: R7 += -5;
R3 += 6;
end5: R5 += -2;
R3 += 3;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000014;
CHECKREG r3, 0x00000183;
CHECKREG r4, 0x0000002A;
CHECKREG r5, 0xFFFFFF9A;
CHECKREG r6, 0x00000114;
CHECKREG r7, 0xFFFFFEEA;
LSETUP ( start7 , end7 ) LC0 = FP;
start7: R4 += 4;
end7: R5 += -5;
R3 += 6;
CHECKREG r0, 0x00000005;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000014;
CHECKREG r3, 0x00000189;
CHECKREG r4, 0x00000062;
CHECKREG r5, 0xFFFFFF54;
CHECKREG r6, 0x00000114;
CHECKREG r7, 0xFFFFFEEA;
P1 = 04;
P2 = 08;
P3 = 10;
P4 = 12;
P5 = 14;
SP = 16;
FP = 18;
R0 = 0x05;
R1 = 0x10;
R2 = 0x12;
R3 = 0x20;
R4 = 0x18;
R5 = 0x14;
R6 = 0x16;
R7 = 0x28;
LSETUP ( start11 , end11 ) LC0 = P5;
start11: R0 += 1;
R1 += -1;
LSETUP ( start15 , end15 ) LC1 = P1;
start15: R4 += 1;
end15: R5 += -1;
R3 += 1;
end11: R2 += 1;
R3 += 1;
LSETUP ( start13 , end12 ) LC0 = P2;
start13: R6 += 1;
LSETUP ( start12 , end12 ) LC1 = P3;
start12: R4 += 1;
end12: R5 += -1;
R3 += 1;
end13: R7 += -1;
R3 += 1;
CHECKREG r0, 0x00000013;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000020;
CHECKREG r3, 0x00000031;
CHECKREG r4, 0x0000005A;
CHECKREG r5, 0xFFFFFFD2;
CHECKREG r6, 0x00000017;
CHECKREG r7, 0x00000027;
R0 = 0x05;
R1 = 0x08;
R2 = 0x12;
R3 = 0x24;
R4 = 0x18;
R5 = 0x20;
R6 = 0x32;
R7 = 0x46 (X);
LSETUP ( start14 , end14 ) LC0 = P4;
start14: R0 += 1;
R1 += -1;
LSETUP ( start16 , end16 ) LC1 = SP;
start16: R6 += 1;
end16: R7 += -1;
R3 += 1;
LSETUP ( start17 , end14 ) LC1 = FP >> 1;
start17: R4 += 1;
end17: R5 += -1;
R3 += 1;
end14: R2 += 1;
R3 += 1;
CHECKREG r0, 0x00000011;
CHECKREG r1, 0xFFFFFFFC;
CHECKREG r2, 0x0000007E;
CHECKREG r3, 0x0000009D;
CHECKREG r4, 0x00000084;
CHECKREG r5, 0xFFFFFFB4;
CHECKREG r6, 0x000000F2;
CHECKREG r7, 0xFFFFFF86;
pass
|
tactcomplabs/xbgas-binutils-gdb | 94,871 | sim/testsuite/bfin/lmu_cplb_multiple0.S | //Original:/proj/frio/dv/testcases/lmu/lmu_cplb_multiple0/lmu_cplb_multiple0.dsp
// Description: Multiple CPLB Hit exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
//-------------------------------------
// Test LMU/CPLB exceptions
// Basic outline:
// Set exception handler
// program CPLB Entries
// Enable CPLB in DMEM_CNTL
// perform access
// verify exception occurred
CHECK_INIT(p5, 0xEFFFFFFC);
//-------------------------
// Zero the CPLB Address and Data regs.
LD32(p0, DCPLB_ADDR0);
R0 = 0;
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
LD32(p0, DCPLB_DATA0);
[ P0 ++ ] = R0; // 0
[ P0 ++ ] = R0; // 1
[ P0 ++ ] = R0; // 2
[ P0 ++ ] = R0; // 3
[ P0 ++ ] = R0; // 4
[ P0 ++ ] = R0; // 5
[ P0 ++ ] = R0; // 6
[ P0 ++ ] = R0; // 7
[ P0 ++ ] = R0; // 8
[ P0 ++ ] = R0; // 9
[ P0 ++ ] = R0; // 10
[ P0 ++ ] = R0; // 11
[ P0 ++ ] = R0; // 12
[ P0 ++ ] = R0; // 13
[ P0 ++ ] = R0; // 14
[ P0 ++ ] = R0; // 15
// Now set the CPLB entries we will need
// Data area for the desired error
WR_MMR(DCPLB_ADDR0, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR1, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR2, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR3, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR4, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR5, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR6, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR7, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR8, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR9, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR10, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR11, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR12, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR13, 0x10000000, p0, r0);
WR_MMR(DCPLB_ADDR14, 0x10000000, p0, r0);
// MMR space
WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0);
WR_MMR(DCPLB_DATA15, PAGE_SIZE_4M|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR, p0, r0);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, int_15, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
CSYNC;
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we can do one test
// in supervisor mode.
RAISE 15;
NOP;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
handler:
// generic protection exception handler
// Inputs:
// p2: addr of CPLB entry to be modified ( current test)
//
// Outputs:
// r4: SEQSTAT
// r5: DCPLB_FAULT_ADDR
// r6: DCPLB_STATUS
// r7: RETX (instruction addr where exception occurred)
R4 = SEQSTAT; // Get exception cause
R4 <<= 24; // Clear HWERRCAUSE + SFTRESET
R4 >>= 24;
// read data addr which caused exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r5);
RD_MMR(DCPLB_STATUS, p0, r6);
R7 = RETX; // get address of excepting instruction
// disable the offending CPLB entries
R2 = 0;
[ P2 ] = R2;
CSYNC;
// return from exception and re-execute offending instruction
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
int_15:
// Interrupt 15 handler - test will run in supervisor mode
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x41C6 (Z);
LD32(p2, DCPLB_DATA1);
X0_1: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB1));
CHECKREG_SYM(r7, X0_1, r0); // RETX should be value of X0_1 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x167E (Z);
LD32(p2, DCPLB_DATA2);
X0_2: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB2));
CHECKREG_SYM(r7, X0_2, r0); // RETX should be value of X0_2 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2781 (Z);
LD32(p2, DCPLB_DATA3);
X0_3: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB3));
CHECKREG_SYM(r7, X0_3, r0); // RETX should be value of X0_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x446B (Z);
LD32(p2, DCPLB_DATA4);
X0_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB4));
CHECKREG_SYM(r7, X0_4, r0); // RETX should be value of X0_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x794B (Z);
LD32(p2, DCPLB_DATA5);
X0_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB5));
CHECKREG_SYM(r7, X0_5, r0); // RETX should be value of X0_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x15FB (Z);
LD32(p2, DCPLB_DATA6);
X0_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB6));
CHECKREG_SYM(r7, X0_6, r0); // RETX should be value of X0_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x59E2 (Z);
LD32(p2, DCPLB_DATA7);
X0_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB7));
CHECKREG_SYM(r7, X0_7, r0); // RETX should be value of X0_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1CFB (Z);
LD32(p2, DCPLB_DATA8);
X0_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB8));
CHECKREG_SYM(r7, X0_8, r0); // RETX should be value of X0_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3F54 (Z);
LD32(p2, DCPLB_DATA9);
X0_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB9));
CHECKREG_SYM(r7, X0_9, r0); // RETX should be value of X0_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0FF6 (Z);
LD32(p2, DCPLB_DATA10);
X0_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB10));
CHECKREG_SYM(r7, X0_10, r0); // RETX should be value of X0_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0ABD (Z);
LD32(p2, DCPLB_DATA11);
X0_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB11));
CHECKREG_SYM(r7, X0_11, r0); // RETX should be value of X0_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x31DF (Z);
LD32(p2, DCPLB_DATA12);
X0_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB12));
CHECKREG_SYM(r7, X0_12, r0); // RETX should be value of X0_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x237C (Z);
LD32(p2, DCPLB_DATA13);
X0_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB13));
CHECKREG_SYM(r7, X0_13, r0); // RETX should be value of X0_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA0, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2F1C (Z);
LD32(p2, DCPLB_DATA14);
X0_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA0, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB0|FAULT_CPLB14));
CHECKREG_SYM(r7, X0_14, r0); // RETX should be value of X0_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7DE1 (Z);
LD32(p2, DCPLB_DATA2);
X1_2: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB2));
CHECKREG_SYM(r7, X1_2, r0); // RETX should be value of X1_2 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4487 (Z);
LD32(p2, DCPLB_DATA3);
X1_3: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB3));
CHECKREG_SYM(r7, X1_3, r0); // RETX should be value of X1_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6201 (Z);
LD32(p2, DCPLB_DATA4);
X1_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB4));
CHECKREG_SYM(r7, X1_4, r0); // RETX should be value of X1_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x52BF (Z);
LD32(p2, DCPLB_DATA5);
X1_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB5));
CHECKREG_SYM(r7, X1_5, r0); // RETX should be value of X1_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6231 (Z);
LD32(p2, DCPLB_DATA6);
X1_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB6));
CHECKREG_SYM(r7, X1_6, r0); // RETX should be value of X1_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63DE (Z);
LD32(p2, DCPLB_DATA7);
X1_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB7));
CHECKREG_SYM(r7, X1_7, r0); // RETX should be value of X1_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6956 (Z);
LD32(p2, DCPLB_DATA8);
X1_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB8));
CHECKREG_SYM(r7, X1_8, r0); // RETX should be value of X1_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1372 (Z);
LD32(p2, DCPLB_DATA9);
X1_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB9));
CHECKREG_SYM(r7, X1_9, r0); // RETX should be value of X1_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x500F (Z);
LD32(p2, DCPLB_DATA10);
X1_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB10));
CHECKREG_SYM(r7, X1_10, r0); // RETX should be value of X1_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2847 (Z);
LD32(p2, DCPLB_DATA11);
X1_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB11));
CHECKREG_SYM(r7, X1_11, r0); // RETX should be value of X1_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2C67 (Z);
LD32(p2, DCPLB_DATA12);
X1_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB12));
CHECKREG_SYM(r7, X1_12, r0); // RETX should be value of X1_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7566 (Z);
LD32(p2, DCPLB_DATA13);
X1_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB13));
CHECKREG_SYM(r7, X1_13, r0); // RETX should be value of X1_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA1, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4287 (Z);
LD32(p2, DCPLB_DATA14);
X1_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA1, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB1|FAULT_CPLB14));
CHECKREG_SYM(r7, X1_14, r0); // RETX should be value of X1_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3359 (Z);
LD32(p2, DCPLB_DATA3);
X2_3: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB3));
CHECKREG_SYM(r7, X2_3, r0); // RETX should be value of X2_3 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4DAA (Z);
LD32(p2, DCPLB_DATA4);
X2_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB4));
CHECKREG_SYM(r7, X2_4, r0); // RETX should be value of X2_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6488 (Z);
LD32(p2, DCPLB_DATA5);
X2_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB5));
CHECKREG_SYM(r7, X2_5, r0); // RETX should be value of X2_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x773C (Z);
LD32(p2, DCPLB_DATA6);
X2_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB6));
CHECKREG_SYM(r7, X2_6, r0); // RETX should be value of X2_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6F59 (Z);
LD32(p2, DCPLB_DATA7);
X2_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB7));
CHECKREG_SYM(r7, X2_7, r0); // RETX should be value of X2_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6EEA (Z);
LD32(p2, DCPLB_DATA8);
X2_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB8));
CHECKREG_SYM(r7, X2_8, r0); // RETX should be value of X2_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5656 (Z);
LD32(p2, DCPLB_DATA9);
X2_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB9));
CHECKREG_SYM(r7, X2_9, r0); // RETX should be value of X2_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6113 (Z);
LD32(p2, DCPLB_DATA10);
X2_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB10));
CHECKREG_SYM(r7, X2_10, r0); // RETX should be value of X2_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4A7B (Z);
LD32(p2, DCPLB_DATA11);
X2_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB11));
CHECKREG_SYM(r7, X2_11, r0); // RETX should be value of X2_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x31D2 (Z);
LD32(p2, DCPLB_DATA12);
X2_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB12));
CHECKREG_SYM(r7, X2_12, r0); // RETX should be value of X2_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2D85 (Z);
LD32(p2, DCPLB_DATA13);
X2_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB13));
CHECKREG_SYM(r7, X2_13, r0); // RETX should be value of X2_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA2, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x19A1 (Z);
LD32(p2, DCPLB_DATA14);
X2_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA2, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB2|FAULT_CPLB14));
CHECKREG_SYM(r7, X2_14, r0); // RETX should be value of X2_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x69D8 (Z);
LD32(p2, DCPLB_DATA4);
X3_4: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB4));
CHECKREG_SYM(r7, X3_4, r0); // RETX should be value of X3_4 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x353C (Z);
LD32(p2, DCPLB_DATA5);
X3_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB5));
CHECKREG_SYM(r7, X3_5, r0); // RETX should be value of X3_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3B54 (Z);
LD32(p2, DCPLB_DATA6);
X3_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB6));
CHECKREG_SYM(r7, X3_6, r0); // RETX should be value of X3_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7D55 (Z);
LD32(p2, DCPLB_DATA7);
X3_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB7));
CHECKREG_SYM(r7, X3_7, r0); // RETX should be value of X3_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x102F (Z);
LD32(p2, DCPLB_DATA8);
X3_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB8));
CHECKREG_SYM(r7, X3_8, r0); // RETX should be value of X3_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1B37 (Z);
LD32(p2, DCPLB_DATA9);
X3_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB9));
CHECKREG_SYM(r7, X3_9, r0); // RETX should be value of X3_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7AAE (Z);
LD32(p2, DCPLB_DATA10);
X3_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB10));
CHECKREG_SYM(r7, X3_10, r0); // RETX should be value of X3_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5E65 (Z);
LD32(p2, DCPLB_DATA11);
X3_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB11));
CHECKREG_SYM(r7, X3_11, r0); // RETX should be value of X3_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x345B (Z);
LD32(p2, DCPLB_DATA12);
X3_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB12));
CHECKREG_SYM(r7, X3_12, r0); // RETX should be value of X3_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63DA (Z);
LD32(p2, DCPLB_DATA13);
X3_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB13));
CHECKREG_SYM(r7, X3_13, r0); // RETX should be value of X3_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA3, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6102 (Z);
LD32(p2, DCPLB_DATA14);
X3_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA3, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB3|FAULT_CPLB14));
CHECKREG_SYM(r7, X3_14, r0); // RETX should be value of X3_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7A79 (Z);
LD32(p2, DCPLB_DATA5);
X4_5: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB5));
CHECKREG_SYM(r7, X4_5, r0); // RETX should be value of X4_5 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0398 (Z);
LD32(p2, DCPLB_DATA6);
X4_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB6));
CHECKREG_SYM(r7, X4_6, r0); // RETX should be value of X4_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x28CC (Z);
LD32(p2, DCPLB_DATA7);
X4_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB7));
CHECKREG_SYM(r7, X4_7, r0); // RETX should be value of X4_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x60E3 (Z);
LD32(p2, DCPLB_DATA8);
X4_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB8));
CHECKREG_SYM(r7, X4_8, r0); // RETX should be value of X4_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1F1A (Z);
LD32(p2, DCPLB_DATA9);
X4_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB9));
CHECKREG_SYM(r7, X4_9, r0); // RETX should be value of X4_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x4B76 (Z);
LD32(p2, DCPLB_DATA10);
X4_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB10));
CHECKREG_SYM(r7, X4_10, r0); // RETX should be value of X4_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x058E (Z);
LD32(p2, DCPLB_DATA11);
X4_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB11));
CHECKREG_SYM(r7, X4_11, r0); // RETX should be value of X4_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7A5F (Z);
LD32(p2, DCPLB_DATA12);
X4_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB12));
CHECKREG_SYM(r7, X4_12, r0); // RETX should be value of X4_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x28D9 (Z);
LD32(p2, DCPLB_DATA13);
X4_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB13));
CHECKREG_SYM(r7, X4_13, r0); // RETX should be value of X4_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA4, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0799 (Z);
LD32(p2, DCPLB_DATA14);
X4_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA4, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB4|FAULT_CPLB14));
CHECKREG_SYM(r7, X4_14, r0); // RETX should be value of X4_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x388F (Z);
LD32(p2, DCPLB_DATA6);
X5_6: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB6));
CHECKREG_SYM(r7, X5_6, r0); // RETX should be value of X5_6 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x751F (Z);
LD32(p2, DCPLB_DATA7);
X5_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB7));
CHECKREG_SYM(r7, X5_7, r0); // RETX should be value of X5_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x493F (Z);
LD32(p2, DCPLB_DATA8);
X5_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB8));
CHECKREG_SYM(r7, X5_8, r0); // RETX should be value of X5_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0F36 (Z);
LD32(p2, DCPLB_DATA9);
X5_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB9));
CHECKREG_SYM(r7, X5_9, r0); // RETX should be value of X5_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x48EE (Z);
LD32(p2, DCPLB_DATA10);
X5_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB10));
CHECKREG_SYM(r7, X5_10, r0); // RETX should be value of X5_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2043 (Z);
LD32(p2, DCPLB_DATA11);
X5_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB11));
CHECKREG_SYM(r7, X5_11, r0); // RETX should be value of X5_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3F78 (Z);
LD32(p2, DCPLB_DATA12);
X5_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB12));
CHECKREG_SYM(r7, X5_12, r0); // RETX should be value of X5_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1E4D (Z);
LD32(p2, DCPLB_DATA13);
X5_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB13));
CHECKREG_SYM(r7, X5_13, r0); // RETX should be value of X5_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA5, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3D0D (Z);
LD32(p2, DCPLB_DATA14);
X5_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA5, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB5|FAULT_CPLB14));
CHECKREG_SYM(r7, X5_14, r0); // RETX should be value of X5_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x33FA (Z);
LD32(p2, DCPLB_DATA7);
X6_7: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB7));
CHECKREG_SYM(r7, X6_7, r0); // RETX should be value of X6_7 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6FBE (Z);
LD32(p2, DCPLB_DATA8);
X6_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB8));
CHECKREG_SYM(r7, X6_8, r0); // RETX should be value of X6_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x36A6 (Z);
LD32(p2, DCPLB_DATA9);
X6_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB9));
CHECKREG_SYM(r7, X6_9, r0); // RETX should be value of X6_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2DDA (Z);
LD32(p2, DCPLB_DATA10);
X6_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB10));
CHECKREG_SYM(r7, X6_10, r0); // RETX should be value of X6_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x30E4 (Z);
LD32(p2, DCPLB_DATA11);
X6_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB11));
CHECKREG_SYM(r7, X6_11, r0); // RETX should be value of X6_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0586 (Z);
LD32(p2, DCPLB_DATA12);
X6_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB12));
CHECKREG_SYM(r7, X6_12, r0); // RETX should be value of X6_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x148E (Z);
LD32(p2, DCPLB_DATA13);
X6_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB13));
CHECKREG_SYM(r7, X6_13, r0); // RETX should be value of X6_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA6, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x42DC (Z);
LD32(p2, DCPLB_DATA14);
X6_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA6, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB6|FAULT_CPLB14));
CHECKREG_SYM(r7, X6_14, r0); // RETX should be value of X6_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5929 (Z);
LD32(p2, DCPLB_DATA8);
X7_8: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB8));
CHECKREG_SYM(r7, X7_8, r0); // RETX should be value of X7_8 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x0C6D (Z);
LD32(p2, DCPLB_DATA9);
X7_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB9));
CHECKREG_SYM(r7, X7_9, r0); // RETX should be value of X7_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x334E (Z);
LD32(p2, DCPLB_DATA10);
X7_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB10));
CHECKREG_SYM(r7, X7_10, r0); // RETX should be value of X7_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x62FF (Z);
LD32(p2, DCPLB_DATA11);
X7_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB11));
CHECKREG_SYM(r7, X7_11, r0); // RETX should be value of X7_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1F56 (Z);
LD32(p2, DCPLB_DATA12);
X7_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB12));
CHECKREG_SYM(r7, X7_12, r0); // RETX should be value of X7_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2BE1 (Z);
LD32(p2, DCPLB_DATA13);
X7_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB13));
CHECKREG_SYM(r7, X7_13, r0); // RETX should be value of X7_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA7, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1D70 (Z);
LD32(p2, DCPLB_DATA14);
X7_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA7, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB7|FAULT_CPLB14));
CHECKREG_SYM(r7, X7_14, r0); // RETX should be value of X7_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x2620 (Z);
LD32(p2, DCPLB_DATA9);
X8_9: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB9));
CHECKREG_SYM(r7, X8_9, r0); // RETX should be value of X8_9 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x26FB (Z);
LD32(p2, DCPLB_DATA10);
X8_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB10));
CHECKREG_SYM(r7, X8_10, r0); // RETX should be value of X8_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x718F (Z);
LD32(p2, DCPLB_DATA11);
X8_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB11));
CHECKREG_SYM(r7, X8_11, r0); // RETX should be value of X8_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x04B1 (Z);
LD32(p2, DCPLB_DATA12);
X8_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB12));
CHECKREG_SYM(r7, X8_12, r0); // RETX should be value of X8_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5358 (Z);
LD32(p2, DCPLB_DATA13);
X8_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB13));
CHECKREG_SYM(r7, X8_13, r0); // RETX should be value of X8_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA8, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x3305 (Z);
LD32(p2, DCPLB_DATA14);
X8_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA8, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB8|FAULT_CPLB14));
CHECKREG_SYM(r7, X8_14, r0); // RETX should be value of X8_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5690 (Z);
LD32(p2, DCPLB_DATA10);
X9_10: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB10));
CHECKREG_SYM(r7, X9_10, r0); // RETX should be value of X9_10 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5DC5 (Z);
LD32(p2, DCPLB_DATA11);
X9_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB11));
CHECKREG_SYM(r7, X9_11, r0); // RETX should be value of X9_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7809 (Z);
LD32(p2, DCPLB_DATA12);
X9_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB12));
CHECKREG_SYM(r7, X9_12, r0); // RETX should be value of X9_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1DDC (Z);
LD32(p2, DCPLB_DATA13);
X9_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB13));
CHECKREG_SYM(r7, X9_13, r0); // RETX should be value of X9_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA9, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6B53 (Z);
LD32(p2, DCPLB_DATA14);
X9_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA9, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB9|FAULT_CPLB14));
CHECKREG_SYM(r7, X9_14, r0); // RETX should be value of X9_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x7BCD (Z);
LD32(p2, DCPLB_DATA11);
X10_11: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB11));
CHECKREG_SYM(r7, X10_11, r0); // RETX should be value of X10_11 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x63AA (Z);
LD32(p2, DCPLB_DATA12);
X10_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB12));
CHECKREG_SYM(r7, X10_12, r0); // RETX should be value of X10_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x373B (Z);
LD32(p2, DCPLB_DATA13);
X10_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB13));
CHECKREG_SYM(r7, X10_13, r0); // RETX should be value of X10_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA10, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x5648 (Z);
LD32(p2, DCPLB_DATA14);
X10_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA10, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB10|FAULT_CPLB14));
CHECKREG_SYM(r7, X10_14, r0); // RETX should be value of X10_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6799 (Z);
LD32(p2, DCPLB_DATA12);
X11_12: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB12));
CHECKREG_SYM(r7, X11_12, r0); // RETX should be value of X11_12 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1452 (Z);
LD32(p2, DCPLB_DATA13);
X11_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB13));
CHECKREG_SYM(r7, X11_13, r0); // RETX should be value of X11_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA11, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x23D3 (Z);
LD32(p2, DCPLB_DATA14);
X11_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA11, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB11|FAULT_CPLB14));
CHECKREG_SYM(r7, X11_14, r0); // RETX should be value of X11_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x1152 (Z);
LD32(p2, DCPLB_DATA13);
X12_13: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA12, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB13));
CHECKREG_SYM(r7, X12_13, r0); // RETX should be value of X12_13 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA12, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6E9D (Z);
LD32(p2, DCPLB_DATA14);
X12_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA12, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB12|FAULT_CPLB14));
CHECKREG_SYM(r7, X12_14, r0); // RETX should be value of X12_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
R0 = 0;R1 = 0;R2 = 0;R3 = 0;R4 = 0;R5 = 0;R6 = 0;R7 = 0;
WR_MMR(DCPLB_DATA13, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DCPLB_DATA14, (PAGE_SIZE_1K|CPLB_VALID|CPLB_DIRTY|CPLB_SUPV_WR|CPLB_USER_RW), p0, r0);
WR_MMR(DMEM_CONTROL, ENDM | ENDCPLB | DMC_AB_CACHE, p0, r0);
CSYNC;
LD32(i1, 0x10000000);
R1 = 0x6006 (Z);
LD32(p2, DCPLB_DATA14);
X13_14: [ I1 ] = R1; // Exception should occur here
WR_MMR(DMEM_CONTROL, ENDM | DMC_AB_CACHE, p0, r0);
CSYNC;
WR_MMR(DCPLB_DATA13, 0, p0, r0);
// Now check that handler read correct values
CHECKREG(r4,0x27); // supv and EXCPT_PROT
CHECKREG(r5, 0x10000000);
CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_SUPV|FAULT_CPLB13|FAULT_CPLB14));
CHECKREG_SYM(r7, X13_14, r0); // RETX should be value of X13_14 (HARDCODED ADDR!!)
//-------------------------------------------------------
User:
NOP;
dbg_pass;
|
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