repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
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tactcomplabs/xbgas-binutils-gdb | 1,036 | sim/testsuite/bfin/m16.s | // Test various moves to single register half
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7fffffff
// load r1=0x00ffffff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extract only to high half
R5 = 0;
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5.H = A1;
DBGA ( R5.L , 0x0000 );
DBGA ( R5.H , 0x7fff );
// extract only to low half
R5 = 0;
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x0000 );
// extract only to high half
R5 = 0;
A1 = A0 = 0;
R5.H = ( A1 += R0.H * R0.H ), A0 += R0.H * R0.H;
DBGA ( R5.L , 0x0000 );
DBGA ( R5.H , 0x7ffe );
// extract only to low half
R5 = 0;
A1 = A0 = 0;
A1 += R0.H * R0.H, R5.L = ( A0 += R0.H * R0.H );
DBGA ( R5.L , 0x7ffe );
DBGA ( R5.H , 0x0000 );
pass
.data
data0:
.dw 0xffff
.dw 0x7fff
.dw 0xffff
.dw 0x00ff
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 10,050 | sim/testsuite/bfin/c_dsp32shift_ahalf_lp.s | //Original:/testcases/core/c_dsp32shift_ahalf_lp/c_dsp32shift_ahalf_lp.dsp
// Spec Reference: dsp32shift ashift half reg left positive
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R0.L;
R1.L = ASHIFT R1.L BY R0.L;
R2.L = ASHIFT R2.L BY R0.L;
R3.L = ASHIFT R3.L BY R0.L;
R4.L = ASHIFT R4.L BY R0.L;
R5.L = ASHIFT R5.L BY R0.L;
R6.L = ASHIFT R6.L BY R0.L;
R7.L = ASHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R1.L;
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L;
R3.L = ASHIFT R3.L BY R1.L;
R4.L = ASHIFT R4.L BY R1.L;
R5.L = ASHIFT R5.L BY R1.L;
R6.L = ASHIFT R6.L BY R1.L;
R7.L = ASHIFT R7.L BY R1.L;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000008;
CHECKREG r5, 0x0000000a;
CHECKREG r6, 0x0000000c;
CHECKREG r7, 0x0000000e;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000000f;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R2.L;
R1.L = ASHIFT R1.L BY R2.L;
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L;
R4.L = ASHIFT R4.L BY R2.L;
R5.L = ASHIFT R5.L BY R2.L;
R6.L = ASHIFT R6.L BY R2.L;
R7.L = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00008000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00008000;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000010;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = ASHIFT R0.L BY R3.L;
R1.L = ASHIFT R1.L BY R3.L;
R2.L = ASHIFT R2.L BY R3.L;
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L;
R5.L = ASHIFT R5.L BY R3.L;
R6.L = ASHIFT R6.L BY R3.L;
R7.L = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R0.L;
R1.L = ASHIFT R1.H BY R0.L;
R2.L = ASHIFT R2.H BY R0.L;
R3.L = ASHIFT R3.H BY R0.L;
R4.L = ASHIFT R4.H BY R0.L;
R5.L = ASHIFT R5.H BY R0.L;
R6.L = ASHIFT R6.H BY R0.L;
R7.L = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R1.L;
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L;
R3.L = ASHIFT R3.H BY R1.L;
R4.L = ASHIFT R4.H BY R1.L;
R5.L = ASHIFT R5.H BY R1.L;
R6.L = ASHIFT R6.H BY R1.L;
R7.L = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x00010002;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020004;
CHECKREG r3, 0x00030006;
CHECKREG r4, 0x00040008;
CHECKREG r5, 0x0005000a;
CHECKREG r6, 0x0006000c;
CHECKREG r7, 0x0007000e;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x0002000f;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0x00018000;
CHECKREG r1, 0x00018000;
CHECKREG r2, 0x0002000f;
CHECKREG r3, 0x00038000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00058000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00078000;
imm32 r0, 0x00010001;
imm32 r1, 0x00010001;
imm32 r2, 0x00020002;
imm32 r3, 0x00030010;
imm32 r4, 0x00040004;
imm32 r5, 0x00050005;
imm32 r6, 0x00060006;
imm32 r7, 0x00070007;
R0.L = ASHIFT R0.H BY R3.L;
R1.L = ASHIFT R1.H BY R3.L;
R2.L = ASHIFT R2.H BY R3.L;
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L;
R5.L = ASHIFT R5.H BY R3.L;
R6.L = ASHIFT R6.H BY R3.L;
R7.L = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0x00010000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030010;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R0.L;
R1.H = ASHIFT R1.L BY R0.L;
R2.H = ASHIFT R2.L BY R0.L;
R3.H = ASHIFT R3.L BY R0.L;
R4.H = ASHIFT R4.L BY R0.L;
R5.H = ASHIFT R5.L BY R0.L;
R6.H = ASHIFT R6.L BY R0.L;
R7.H = ASHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R1.L;
R1.H = ASHIFT R1.L BY R1.L;
R2.H = ASHIFT R2.L BY R1.L;
R3.H = ASHIFT R3.L BY R1.L;
R4.H = ASHIFT R4.L BY R1.L;
R5.H = ASHIFT R5.L BY R1.L;
R6.H = ASHIFT R6.L BY R1.L;
R7.H = ASHIFT R7.L BY R1.L;
CHECKREG r0, 0x00020001;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00040002;
CHECKREG r3, 0x00060003;
CHECKREG r4, 0x00080004;
CHECKREG r5, 0x000a0005;
CHECKREG r6, 0x000c0006;
CHECKREG r7, 0x000e0007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000000f;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R2.L;
R1.H = ASHIFT R1.L BY R2.L;
//rh2 = ashift (rl2 by rl2);
R3.H = ASHIFT R3.L BY R2.L;
R4.H = ASHIFT R4.L BY R2.L;
R5.H = ASHIFT R5.L BY R2.L;
R6.H = ASHIFT R6.L BY R2.L;
R7.H = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x80000001;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x80000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x80000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x80000007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000010;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R3.L;
R1.H = ASHIFT R1.L BY R3.L;
R2.H = ASHIFT R2.L BY R3.L;
R3.H = ASHIFT R3.L BY R3.L;
R4.H = ASHIFT R4.L BY R3.L;
R5.H = ASHIFT R5.L BY R3.L;
R6.H = ASHIFT R6.L BY R3.L;
R7.H = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R0.L;
R1.H = ASHIFT R1.H BY R0.L;
R2.H = ASHIFT R2.H BY R0.L;
R3.H = ASHIFT R3.H BY R0.L;
R4.H = ASHIFT R4.H BY R0.L;
R5.H = ASHIFT R5.H BY R0.L;
R6.H = ASHIFT R6.H BY R0.L;
R7.H = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R1.L;
R1.H = ASHIFT R1.H BY R1.L;
R2.H = ASHIFT R2.H BY R1.L;
R3.H = ASHIFT R3.H BY R1.L;
R4.H = ASHIFT R4.H BY R1.L;
R5.H = ASHIFT R5.H BY R1.L;
R6.H = ASHIFT R6.H BY R1.L;
R7.H = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x00020000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00040000;
CHECKREG r3, 0x00060000;
CHECKREG r4, 0x00080000;
CHECKREG r5, 0x000a0000;
CHECKREG r6, 0x000c0000;
CHECKREG r7, 0x000e0000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x0002000f;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0x00018000;
CHECKREG r1, 0x00018000;
CHECKREG r2, 0x0002000f;
CHECKREG r3, 0x00038000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00058000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00078000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030010;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R3.L;
R1.H = ASHIFT R1.H BY R3.L;
R2.H = ASHIFT R2.H BY R3.L;
R3.H = ASHIFT R3.H BY R3.L;
R4.H = ASHIFT R4.H BY R3.L;
R5.H = ASHIFT R5.H BY R3.L;
R6.H = ASHIFT R6.H BY R3.L;
R7.H = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,862 | sim/testsuite/bfin/byteop1p.s | # Blackfin testcase for BYTEOP1P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP1P (R1:0, R3:2);
check_it \res
R6 = BYTEOP1P (R1:0, R3:2) (T);
check_it \resT
R6 = BYTEOP1P (R1:0, R3:2) (R);
check_it \resR
R6 = BYTEOP1P (R1:0, R3:2) (T, R);
check_it \resTR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop1p 0, 0, 0x06070809, 0x05060708, 0x58687888, 0x58687888
test_byteop1p 0, 1, 0x69060708, 0x68060708, 0x0f607080, 0x0e607080
test_byteop1p 0, 2, 0x61690708, 0x60690607, 0x0e176878, 0x0e166878
test_byteop1p 0, 3, 0x59616a07, 0x58616907, 0x0e161f70, 0x0d161e70
test_byteop1p 1, 0, 0x25060708, 0x25060708, 0x52607080, 0x52607080
test_byteop1p 1, 1, 0x88060708, 0x88050607, 0x09586878, 0x08586878
test_byteop1p 1, 2, 0x80690607, 0x80680607, 0x080f6070, 0x080e6070
test_byteop1p 1, 3, 0x78616907, 0x78606906, 0x080e1768, 0x070e1668
test_byteop1p 2, 0, 0x1d260708, 0x1d250607, 0x525a6878, 0x515a6878
test_byteop1p 2, 1, 0x80250607, 0x80250607, 0x08526070, 0x08526070
test_byteop1p 2, 2, 0x78880607, 0x78880506, 0x08095868, 0x07085868
test_byteop1p 2, 3, 0x70806906, 0x70806806, 0x07080f60, 0x07080e60
test_byteop1p 3, 0, 0x151e2607, 0x151d2607, 0x515a6270, 0x51596270
test_byteop1p 3, 1, 0x781d2607, 0x781d2506, 0x08525a68, 0x07515a68
test_byteop1p 3, 2, 0x70802506, 0x70802506, 0x07085260, 0x07085260
test_byteop1p 3, 3, 0x68788806, 0x68788805, 0x07080958, 0x06070858
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop1p 0, 0, 0xfaf9f8f7, 0xf9f8f7f6, 0xa7978777, 0xa7978777
test_byteop1p 0, 1, 0x97f9f8f7, 0x96f9f8f7, 0xf19f8f7f, 0xf09f8f7f
test_byteop1p 0, 2, 0x9f96f9f8, 0x9e96f8f7, 0xf1e99787, 0xf1e89787
test_byteop1p 0, 3, 0xa79e96f8, 0xa69e95f8, 0xf2e9e18f, 0xf1e9e08f
test_byteop1p 1, 0, 0xdaf9f8f7, 0xdaf9f8f7, 0xad9f8f7f, 0xad9f8f7f
test_byteop1p 1, 1, 0x77faf9f8, 0x77f9f8f7, 0xf7a79787, 0xf6a79787
test_byteop1p 1, 2, 0x7f97f9f8, 0x7f96f9f8, 0xf7f19f8f, 0xf7f09f8f
test_byteop1p 1, 3, 0x879f96f9, 0x879e96f8, 0xf8f1e997, 0xf7f1e897
test_byteop1p 2, 0, 0xe2daf9f8, 0xe2d9f8f7, 0xaea59787, 0xada59787
test_byteop1p 2, 1, 0x7fdaf9f8, 0x7fdaf9f8, 0xf7ad9f8f, 0xf7ad9f8f
test_byteop1p 2, 2, 0x8777faf9, 0x8777f9f8, 0xf8f7a797, 0xf7f6a797
test_byteop1p 2, 3, 0x8f7f97f9, 0x8f7f96f9, 0xf8f7f19f, 0xf8f7f09f
test_byteop1p 3, 0, 0xeae2d9f8, 0xeae1d9f8, 0xaea69d8f, 0xaea59d8f
test_byteop1p 3, 1, 0x87e2daf9, 0x87e2d9f8, 0xf8aea597, 0xf7ada597
test_byteop1p 3, 2, 0x8f7fdaf9, 0x8f7fdaf9, 0xf8f7ad9f, 0xf8f7ad9f
test_byteop1p 3, 3, 0x978777fa, 0x978777f9, 0xf9f8f7a7, 0xf8f7f6a7
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,642 | sim/testsuite/bfin/c_mmr_loop_user_except.S | //Original:/proj/frio/dv/testcases/core/c_mmr_loop_user_except/c_mmr_loop_user_except.dsp
// Spec Reference: c_mmr_loop_user_except
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
// LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
// [p0++] = r0;
// LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
// [p0++] = r0;
//*****************
// wrt-rd EVT13 = 0xFFE02034
LD32(p0, 0xFFE02034);
LD32(r0, 0xDDDDABC6);
[ P0 ] = R0;
// wrt-rd EVT14 = 0xFFE02038
LD32(p0, 0xFFE02038);
LD32(r0, 0xEEEEABC6);
[ P0 ] = R0;
//*****************
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
// LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
// RAISE 2; // RTN // exception because we execute this in USER mode
R0 = 0;
LD32(p0, 0xFFE02034);
P2 = 2;
LSETUP ( start1 , end1 ) LC0 = P2;
start1:
R0 = [ P0 ++ ]; // 16 bit instr
end1: R1 = R0;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
//CHECKREG(r3, 0x00000030);
CHECKREG(r4, 0x0000000F);
CHECKREG(r5, 0x00000012);
CHECKREG(r6, 0x00000015);
CHECKREG(r7, 0x00000018);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
R0 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R3 = RETX;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
R3 += 2; // for resturn address
RETX = r3;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
THANDLE: // Timer Handler 6
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = RETI;
R4 += 2;
RETI = r4;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = RETI;
R5 += 2;
RETI = r5;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = RETI;
R6 += 2;
RETI = r6;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = RETI;
R7 += 2;
RETI = r7;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = RETI;
R0 += 2;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = RETI;
R1 += 2;
RETI = r1;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = RETI;
R2 += 2;
RETI = r2;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = RETI;
R3 += 2;
RETI = r3;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
tactcomplabs/xbgas-binutils-gdb | 1,233 | sim/testsuite/bfin/c_dsp32shiftim_lhh.s | //Original:/testcases/core/c_dsp32shiftim_lhh/c_dsp32shiftim_lhh.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift / lshift
imm32 r0, 0x01230abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0 = R0 << 0 (V);
R1 = R1 << 3 (V);
R2 = R2 << 5 (V);
R3 = R3 << 8 (V);
R4 = R4 << 9 (V);
R5 = R5 << 15 (V);
R6 = R6 << 7 (V);
R7 = R7 << 13 (V);
CHECKREG r0, 0x01230ABC;
CHECKREG r1, 0x91A0B3C0;
CHECKREG r2, 0x68A0F120;
CHECKREG r3, 0x56009A00;
CHECKREG r4, 0xCE005600;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xC480E680;
CHECKREG r7, 0x4000C000;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7 = R0 >> 11 (V);
R0 = R1 >> 8 (V);
R1 = R2 >> 14 (V);
R2 = R3 >> 15 (V);
R3 = R4 >> 10 (V);
R4 = R5 >> 2 (V);
R5 = R6 >> 9 (V);
R6 = R7 >> 6 (V);
CHECKREG r0, 0x00120056;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00110022;
CHECKREG r4, 0x159E26AF;
CHECKREG r5, 0x00330055;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,963 | sim/testsuite/bfin/se_loop_ppm_1.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm_1/se_loop_ppm_1.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
LSETUP ( m0s , m0s ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m0s:[ -- SP ] = ( R7:5 );
LSETUP ( m1s , m1e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m1s:R5 += 1;
m1e:[ -- SP ] = ( R7:5 );
LSETUP ( m2s , m2e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m2s:R5 += 1;
R6 += 2;
m2e:[ -- SP ] = ( R7:5 );
LSETUP ( m3s , m3e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m3s:R5 += 1;
R6 += 2;
R7 += 3;
m3e:[ -- SP ] = ( R7:5 );
LSETUP ( m4s , m4e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
m4e:[ -- SP ] = ( R7:4 );
LSETUP ( m5s , m5e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
m5e:[ -- SP ] = ( R7:4 );
LSETUP ( m6s , m6e ) LC1 = P0;
R0 += 1;
R4 += 3;
R5 += 5;
m6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
m6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 1,409 | sim/testsuite/bfin/a22.s | // Test ALU NEG accumulators
# mach: bfin
.include "testutils.inc"
start
R0 = 0xffffffff;
A0.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A0 = - A0;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 );
R0 = 0x1;
A0.w = R0;
R0 = 0x0;
A0.x = R0;
A0 = - A0;
R4 = A0.w;
R5 = A0.x;
_DBG A0;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
R0 = 0xffffffff;
A0.w = R0;
R0 = 0xff (X);
A0.x = R0;
A0 = - A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = - A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
// NEG NEG
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
R0 = 0xffffffff;
A1.w = R0;
R0 = 0x7f (X);
A1.x = R0;
A1 = - A1, A0 = - A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R4 = A1.w;
R5 = A1.x;
_DBG A1;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 );
// NEG NEG register
R0.L = 0x0001;
R0.H = 0x8000;
R3 = - R0 (V);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
_DBG ASTAT;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,516 | sim/testsuite/bfin/c_seq_ac_raise_mv.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv/c_seq_ac_raise_mv.dsp
// Spec Reference: sequencer stage AC (raise + regmv)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0xa01 (X);
R1 = 0xb02 (X);
R2 = 0xc03 (X);
R3 = 0xd04 (X);
R4 = 0xe05 (X);
R5 = 0xf06 (X);
R6 = 0x107 (X);
R7 = 0x208 (X);
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
RAISE 2; // RTN
P1 = R7;
R0 = P1;
// [--sp] = (r7-r0);
RAISE 5; // RTI
P2 = R6;
R1 = P2;
// [--sp] = (r7-r1);
RAISE 6; // RTI
P3 = R5;
R2 = P3;
[ -- SP ] = ( R7:2 );
// POP
RAISE 7; // RTI
P4 = R4;
R3 = P4;
// (r7-r2) = [sp++];
CHECKREG(r0, 0x00000208);
CHECKREG(r1, 0x00000107);
CHECKREG(r2, 0x00000F06);
CHECKREG(r3, 0x00000E05);
CHECKREG(r4, 0x00000E05);
CHECKREG(r5, 0x00000F06);
CHECKREG(r6, 0x00000107);
CHECKREG(r7, 0x00000208);
R0 = 0xa41 (X);
R1 = 0xb52 (X);
R2 = 0xc63 (X);
R3 = 0xd74 (X);
R4 = 0xe85 (X);
R5 = 0xf96 (X);
R6 = 0x1a7 (X);
R7 = 0x2b8 (X);
RAISE 8; // RTI
P1 = R0;
R6 = P1;
// (r7-r1) = [sp++];
CHECKREG(r0, 0x00000A41);
CHECKREG(r1, 0x00000B52);
CHECKREG(r2, 0x00000C63);
CHECKREG(r3, 0x00000D74);
CHECKREG(r4, 0x00000E85);
CHECKREG(r5, 0x00000F96);
CHECKREG(r6, 0x00000A41);
CHECKREG(r7, 0x000002B8);
RAISE 9; // RTI
P2 = R1;
R7 = P2;
// (r7-r0) = [sp++];
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
CHECKREG(r4, 0x00000E85);
CHECKREG(r5, 0x00000F96);
CHECKREG(r6, 0x00000A41);
CHECKREG(r7, 0x00000B52);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I0 += 2;
RTI;
THANDLE: // Timer Handler 6
I1 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I2 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I3 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 5,429 | sim/testsuite/bfin/c_dsp32alu_rmp.s | //Original:/testcases/core/c_dsp32alu_rmp/c_dsp32alu_rmp.dsp
// Spec Reference: dsp32alu dreg = -/+ ( dreg, dreg)
# mach: bfin
.include "testutils.inc"
start
// ALU operations include parallel addition, subtraction
// and 32-bit data. If an operation use a single ALU only, it uses ALU0.
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = R0 -|+ R0;
R1 = R0 -|+ R1;
R2 = R0 -|+ R2;
R3 = R0 -|+ R3;
R4 = R0 -|+ R4;
R5 = R0 -|+ R5;
R6 = R0 -|+ R6;
R7 = R0 -|+ R7;
CHECKREG r0, 0x00001222;
CHECKREG r1, 0xD877BD3F;
CHECKREG r2, 0xCBBC6737;
CHECKREG r3, 0xB99A8939;
CHECKREG r4, 0xAA999B3D;
CHECKREG r5, 0x9877BD3F;
CHECKREG r6, 0x8BBC6737;
CHECKREG r7, 0x799A8999;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = R1 -|+ R0;
R1 = R1 -|+ R1;
R2 = R1 -|+ R2;
R3 = R1 -|+ R3;
R4 = R1 -|+ R4;
R5 = R1 -|+ R5;
R6 = R1 -|+ R6;
R7 = R1 -|+ R7;
CHECKREG r0, 0x12223458;
CHECKREG r1, 0x0000565A;
CHECKREG r2, 0x4BBCAB7F;
CHECKREG r3, 0x399ACD81;
CHECKREG r4, 0x2778EF83;
CHECKREG r5, 0x15561185;
CHECKREG r6, 0x03343387;
CHECKREG r7, 0xF1125659;
imm32 r0, 0x416789ab;
imm32 r1, 0x6289abcd;
imm32 r2, 0x43445555;
imm32 r3, 0x64667777;
imm32 r4, 0x456789ab;
imm32 r5, 0x6689abcd;
imm32 r6, 0x47445555;
imm32 r7, 0x68667777;
R0 = R2 -|+ R0;
R1 = R2 -|+ R1;
R2 = R2 -|+ R2;
R3 = R2 -|+ R3;
R4 = R2 -|+ R4;
R5 = R2 -|+ R5;
R6 = R2 -|+ R6;
R7 = R2 -|+ R7;
CHECKREG r0, 0x01DDDF00;
CHECKREG r1, 0xE0BB0122;
CHECKREG r2, 0x0000AAAA;
CHECKREG r3, 0x9B9A2221;
CHECKREG r4, 0xBA993455;
CHECKREG r5, 0x99775677;
CHECKREG r6, 0xB8BCFFFF;
CHECKREG r7, 0x979A2221;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
R0 = R3 -|+ R0;
R1 = R3 -|+ R1;
R2 = R3 -|+ R2;
R3 = R3 -|+ R3;
R4 = R3 -|+ R4;
R5 = R3 -|+ R5;
R6 = R3 -|+ R6;
R7 = R3 -|+ R7;
CHECKREG r4, 0x456722A3;
CHECKREG r5, 0x668944C5;
CHECKREG r6, 0x4744EE4D;
CHECKREG r7, 0x6866106F;
CHECKREG r4, 0x456722A3;
CHECKREG r5, 0x668944C5;
CHECKREG r6, 0x4744EE4D;
CHECKREG r7, 0x6866106F;
imm32 r0, 0x4537891b;
imm32 r1, 0x6759ab2d;
imm32 r2, 0x44555535;
imm32 r3, 0x66665747;
imm32 r4, 0x88789565;
imm32 r5, 0xaa8abb5b;
imm32 r6, 0xcc9cdd85;
imm32 r7, 0xeeaeff9f;
R0 = R4 -|+ R0;
R1 = R4 -|+ R1;
R2 = R4 -|+ R2;
R3 = R4 -|+ R3;
R4 = R4 -|+ R4;
R5 = R4 -|+ R5;
R6 = R4 -|+ R6;
R7 = R4 -|+ R7;
CHECKREG r0, 0x43411E80;
CHECKREG r1, 0x211F4092;
CHECKREG r2, 0x4423EA9A;
CHECKREG r3, 0x2212ECAC;
CHECKREG r4, 0x00002ACA;
CHECKREG r5, 0x5576E625;
CHECKREG r6, 0x3364084F;
CHECKREG r7, 0x11522A69;
imm32 r0, 0x456b89ab;
imm32 r1, 0x69764bcd;
imm32 r2, 0x49736564;
imm32 r3, 0x61278394;
imm32 r4, 0x98876439;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0xcccc1ddd;
imm32 r7, 0x12346fff;
R0 = R5 -|+ R0;
R1 = R5 -|+ R1;
R2 = R5 -|+ R2;
R3 = R5 -|+ R3;
R4 = R5 -|+ R4;
R5 = R5 -|+ R5;
R6 = R5 -|+ R6;
R7 = R5 -|+ R7;
CHECKREG r0, 0x653F9566;
CHECKREG r1, 0x41345788;
CHECKREG r2, 0x6137711F;
CHECKREG r3, 0x49838F4F;
CHECKREG r4, 0x12236FF4;
CHECKREG r5, 0x00001776;
CHECKREG r6, 0x33343553;
CHECKREG r7, 0xEDCC8775;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R0 = R6 -|+ R0;
R1 = R6 -|+ R1;
R2 = R6 -|+ R2;
R3 = R6 -|+ R3;
R4 = R6 -|+ R4;
R5 = R6 -|+ R5;
R6 = R6 -|+ R6;
R7 = R6 -|+ R7;
CHECKREG r0, 0xBECBCA81;
CHECKREG r1, 0x9CC9DCA3;
CHECKREG r2, 0x00EDF82B;
CHECKREG r3, 0x9DCCF84D;
CHECKREG r4, 0xF1FEE76F;
CHECKREG r5, 0xBECB1C41;
CHECKREG r6, 0x000021AC;
CHECKREG r7, 0xEDCC782B;
imm32 r0, 0x476789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x23456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R0 = R7 -|+ R0;
R1 = R7 -|+ R1;
R2 = R7 -|+ R2;
R3 = R7 -|+ R3;
R4 = R7 -|+ R4;
R5 = R7 -|+ R5;
R6 = R7 -|+ R6;
R7 = R7 -|+ R7;
CHECKREG r0, 0x6466B9A2;
CHECKREG r1, 0x4454DBC4;
CHECKREG r2, 0x8888974C;
CHECKREG r3, 0x5555BFFE;
CHECKREG r4, 0x3333E790;
CHECKREG r5, 0x01233BB2;
CHECKREG r6, 0x22224D74;
CHECKREG r7, 0x00005FEE;
imm32 r0, 0x456739ab;
imm32 r1, 0x67694bcd;
imm32 r2, 0x03456755;
imm32 r3, 0x66666777;
imm32 r4, 0x12345699;
imm32 r5, 0x45678b6b;
imm32 r6, 0x043290d6;
imm32 r7, 0x1234567f;
R4 = R4 -|+ R7 (S);
R5 = R5 -|+ R5 (CO);
R2 = R6 -|+ R3 (SCO);
R6 = R0 -|+ R4 (S);
R0 = R1 -|+ R6 (S);
R2 = R2 -|+ R1 (CO);
R1 = R3 -|+ R0 (CO);
R7 = R7 -|+ R4 (SCO);
CHECKREG r0, 0x22027FFF;
CHECKREG r1, 0xE7764464;
CHECKREG r2, 0xE99990E4;
CHECKREG r3, 0x66666777;
CHECKREG r4, 0x00007FFF;
CHECKREG r5, 0x16D60000;
CHECKREG r6, 0x45677FFF;
CHECKREG r7, 0x7FFF1234;
imm32 r0, 0x476789ab;
imm32 r1, 0x6779abcd;
imm32 r2, 0x23456755;
imm32 r3, 0x56789007;
imm32 r4, 0x789ab799;
imm32 r5, 0xaaaa0bbb;
imm32 r6, 0x89ab1d7d;
imm32 r7, 0xabcd2ff7;
R3 = R4 -|+ R0 (S);
R5 = R5 -|+ R1 (SCO);
R2 = R2 -|+ R2 (S);
R7 = R7 -|+ R3 (CO);
R4 = R3 -|+ R4 (CO);
R0 = R1 -|+ R5 (S);
R1 = R0 -|+ R6 (SCO);
R6 = R6 -|+ R7 (SCO);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x9D7D7FFF;
CHECKREG r2, 0x00007FFF;
CHECKREG r3, 0x31338000;
CHECKREG r4, 0x3799B899;
CHECKREG r5, 0xB7888000;
CHECKREG r6, 0x7FFFD9B4;
CHECKREG r7, 0xAFF77A9A;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,671 | sim/testsuite/bfin/c_dsp32alu_r_negneg.s | //Original:/testcases/core/c_dsp32alu_r_negneg/c_dsp32alu_r_negneg.dsp
// Spec Reference: dsp32alu dregs = neg / neg dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3b44b515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = - R0 (V);
R1 = - R1 (V);
R2 = - R2 (V);
R3 = - R3 (V);
R4 = - R4 (V);
R5 = - R5 (V);
R6 = - R6 (V);
R7 = - R7 (V);
CHECKREG r0, 0x5A9976EF;
CHECKREG r1, 0xD87754E3;
CHECKREG r2, 0xC4BC4AEB;
CHECKREG r3, 0xB99A88E9;
CHECKREG r4, 0xAA9976E5;
CHECKREG r5, 0x987754E3;
CHECKREG r6, 0x8BBCAAEB;
CHECKREG r7, 0x799A8889;
imm32 r0, 0xa567892b;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x344d5525;
imm32 r3, 0xd6667727;
imm32 r4, 0x58889929;
imm32 r5, 0x6aaabb2b;
imm32 r6, 0x7ccfdd2d;
imm32 r7, 0x8eeeffff;
R1 = - R0 (V);
R2 = - R1 (V);
R3 = - R2 (V);
R4 = - R3 (V);
R5 = - R4 (V);
R6 = - R5 (V);
R7 = - R6 (V);
R0 = - R7 (V);
CHECKREG r0, 0xA567892B;
CHECKREG r1, 0x5A9976D5;
CHECKREG r2, 0xA567892B;
CHECKREG r3, 0x5A9976D5;
CHECKREG r4, 0xA567892B;
CHECKREG r5, 0x5A9976D5;
CHECKREG r6, 0xA567892B;
CHECKREG r7, 0x5A9976D5;
imm32 r0, 0xb5678941;
imm32 r1, 0x2789ab5d;
imm32 r2, 0x34445565;
imm32 r3, 0xe6667777;
imm32 r4, 0x5567898b;
imm32 r5, 0x6789ab9d;
imm32 r6, 0xc4445505;
imm32 r7, 0x8666b777;
R2 = - R0 (V);
R3 = - R1 (V);
R4 = - R2 (V);
R5 = - R3 (V);
R6 = - R4 (V);
R7 = - R5 (V);
R0 = - R6 (V);
R1 = - R7 (V);
CHECKREG r0, 0xB5678941;
CHECKREG r1, 0x2789AB5D;
CHECKREG r2, 0x4A9976BF;
CHECKREG r3, 0xD87754A3;
CHECKREG r4, 0xB5678941;
CHECKREG r5, 0x2789AB5D;
CHECKREG r6, 0x4A9976BF;
CHECKREG r7, 0xD87754A3;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,071 | sim/testsuite/bfin/c_logi2op_log_l_shft_astat.S | # Test ASTAT bits with logical left shift (<<=)
# mach: bfin
.include "testutils.inc"
#include "test.h"
start
.macro __do val:req, shift:req, exp:req
# First test when ASTAT starts with all bits cleared
imm32 R2, \val;
ASTAT = R0;
R2 <<= \shift;
R3 = ASTAT;
CHECKREG R2, (\val << \shift);
CHECKREG R3, \exp;
# Then test when ASTAT starts with all bits set
imm32 R2, \val;
ASTAT = R1;
R2 <<= \shift;
R3 = ASTAT;
CHECKREG R3, (\exp) | ~(_AZ|_AN|_V|_V_COPY);
.endm
.macro _do shift:req, val:req
# Automatically test all shifted values
.if ((\val << \shift) & 0xffffffff) == 0
__do \val, \shift, _AZ
.else
.if (\val << \shift) == 0x80000000
__do \val, \shift, _AN
.else
__do \val, \shift, 0
.endif
.endif
.if (\val << 1) & 0xffffffff
_do \shift, (\val << 1)
.endif
.endm
.macro do shift:req
_l_shft_\shift:
_do \shift, 1
.endm
R0 = 0;
R1 = -1;
do 0
do 1
do 2
do 3
do 4
do 5
do 6
do 7
do 8
do 9
do 10
do 11
do 12
do 13
do 14
do 15
do 16
do 17
do 18
do 19
do 20
do 21
do 22
do 23
do 24
do 25
do 26
do 27
do 28
do 29
do 30
do 31
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,831 | sim/testsuite/bfin/c_except_illopcode.S | //Original:/proj/frio/dv/testcases/core/c_except_illopcode/c_except_illopcode.dsp
// Spec Reference: c_exception illegal opcode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
// load address of exception handler
P0 = 0x200C (Z); // 0xFFE0200C EVT3 EXCEPTION
P0.H = 0xFFE0;
R0 = exception_handler (Z); // wr address of exception handler to MMR EVT3
R0.H = exception_handler;
[ P0 ] = R0;
// Jump to User mode and enable exceptions
R0 = MidUserCode (Z);
R0.H = MidUserCode;
RETI = R0;
RTI; // cause it to go to Midusercode, .dd cause exception
BeginUserCode:
P1 = 1;
P2 = 2;
P3 = 3;
P4 = 4;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000001);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000003);
// CHECKREG(r4, 0x00000098);
CHECKREG(r5, 0x00000005);
CHECKREG(r6, 0x00000006);
CHECKREG(r7, 0x00000007);
CHECKREG(p1, 0x00000001);
CHECKREG(p2, 0x00000002);
CHECKREG(p3, 0x00000003);
CHECKREG(p4, 0x00000004);
dbg_pass;
//jump 2;
//jump -2;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
//dbg_pass;
MidUserCode:
.dd 0xFFFFFFFF
R0 = 0;
R1 = 1;
R2 = 2;
R3 = 3;
CC = R0;
IF !CC JUMP BeginUserCode;
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
.dd 0xFFFFFFFF
//.code 0x800
exception_handler:
R4 = RETX; // error handler: RETX has the address of the same Illegal instr
R5 = 5;
R6 = 6;
R7 = 7;
R4 += 4; // we have to add 4 to point to next instr after return
RETX = R4;
RTX; // return from exception
//nop;
.section MEM_DATA_ADDR_1,"aw"
.dd 0xDEADBEEF
.dd 0xBAD00BAD
|
tactcomplabs/xbgas-binutils-gdb | 1,803 | sim/testsuite/bfin/c_cc_regmvlogi_mvbrsft.s | //Original:/testcases/core/c_cc_regmvlogi_mvbrsft/c_cc_regmvlogi_mvbrsft.dsp
// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000020; // cc=1
imm32 r1, 0x00000000; // cc=0
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
ASTAT = R0; // cc=1 REGMV
IF CC R1 = R3; // ccmov
ASTAT = R1; // cc=0 REGMV
IF CC R3 = R2; // ccmv
CC = R0 < R1; // ccflag
IF CC R4 = R5; // ccmv
CC = ! BITTST( R0 , 4 ); // cc = 0
IF CC R4 = R5; // ccmv
CC = BITTST ( R1 , 4 ); // cc = 0
IF !CC JUMP LABEL1; // branch
CC = ! CC;
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R6 = R0 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R3;
CC = R0 < R1; // ccflag
IF CC JUMP END (BP); // branch on
R4 = R5 + R7;
END:
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0x62B61557;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x609950AA;
CHECKREG r6, 0x62B61577;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0x00000020;
imm32 r1, 0x00000000;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
ASTAT = R0; // cc=1 REGMV
R2 = ROT R2 BY 1; // dsp32shiftim_rot
ASTAT = R1; // cc=0 REGMV
R3 = ROT R3 BY 1; // dsp32shiftim_rot
CC = ! BITTST( R0 , 4 ); // cc = 0
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = BITTST ( R1 , 4 ); // cc = 0
IF CC R4 = R5; // ccmov
CC = BITTST ( R0 , 4 ); // cc = 1
R7 = ROT R6 BY R7.L;
CHECKREG r0, 0x00000020;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xC4CC2AAF;
CHECKREG r3, 0x0E76000E;
CHECKREG r4, 0x01F49088;
CHECKREG r5, 0x6E2959AA;
CHECKREG r6, 0x3E921110;
CHECKREG r7, 0xFA484440;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,161 | sim/testsuite/bfin/c_dsp32mult_dr_tu.s | //Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp
// Spec Reference: dsp32mult single dr tu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU);
CHECKREG r0, 0x1CFC1CFC;
CHECKREG r1, 0x0930114A;
CHECKREG r2, 0x01F5010A;
CHECKREG r3, 0x012A0054;
CHECKREG r4, 0x1CFC1CFC;
CHECKREG r5, 0x1B4E3364;
CHECKREG r6, 0x1B4E3364;
CHECKREG r7, 0x19B95B1D;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU);
CHECKREG r0, 0x00700070;
CHECKREG r1, 0x00420042;
CHECKREG r2, 0x0DB20DB2;
CHECKREG r3, 0x082F082F;
CHECKREG r4, 0x0DB20DB2;
CHECKREG r5, 0x6D820B70;
CHECKREG r6, 0x00270004;
CHECKREG r7, 0x00200020;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU);
CHECKREG r0, 0x6F5897A6;
CHECKREG r1, 0x87430CD4;
CHECKREG r2, 0x0CD40CD4;
CHECKREG r3, 0xDFCB0115;
CHECKREG r4, 0x6F5897A6;
CHECKREG r5, 0x681A8DC9;
CHECKREG r6, 0x53FD3DAA;
CHECKREG r7, 0x39A82A55;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU);
CHECKREG r0, 0x400EC4BE;
CHECKREG r1, 0x09231005;
CHECKREG r2, 0x09231005;
CHECKREG r3, 0x014D014D;
CHECKREG r4, 0x01240383;
CHECKREG r5, 0x00140014;
CHECKREG r6, 0x400EC4BE;
CHECKREG r7, 0x04920E0B;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU);
R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU);
R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU);
R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU);
R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU);
R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU);
R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU);
R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU);
CHECKREG r0, 0x00050005;
CHECKREG r1, 0x02EB02EB;
CHECKREG r2, 0xA3E40C49;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x3CE10003;
CHECKREG r6, 0x00010001;
CHECKREG r7, 0x00050005;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU);
CHECKREG r0, 0x0C370674;
CHECKREG r1, 0x00090423;
CHECKREG r2, 0x0E6606D6;
CHECKREG r3, 0x0078758E;
CHECKREG r4, 0x00430060;
CHECKREG r5, 0x00F00D60;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x007500DF;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU);
R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU);
R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU);
R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU);
R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU);
CHECKREG r0, 0x1B68CBC7;
CHECKREG r1, 0x001D0000;
CHECKREG r2, 0x00550004;
CHECKREG r3, 0x00060025;
CHECKREG r4, 0x00030030;
CHECKREG r5, 0x00050002;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU);
R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU);
R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU);
R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU);
CHECKREG r0, 0x08442F1A;
CHECKREG r1, 0x03102C21;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00270027;
CHECKREG r4, 0x662411EE;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x119B119B;
pass
|
tactcomplabs/xbgas-binutils-gdb | 12,557 | sim/testsuite/bfin/se_illegalcombination.S | //Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp
// Description: Multi-issue Illegal Combinations
# mach: bfin
# sim: --environment operating
# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x100 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Slot 0 can only be LDST LOAD with search instruction (2 instrs)
.dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP;
.dw 0x0210
.dw 0x9303
.dw 0x0000
// (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok
( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP;
// only nop or dspLDST allowed in slot 1 (1 instr)
// a0 = r0, nop, [p0] = r3;
.dw 0xCC09; // can't assemble
.dw 0x2000;
.dw 0x0000;
.dw 0x9303;
// Slot 0 illegal opcodes (1 instr)
// a0 = r0, raise 15, nop;
.dw 0xCC09; // can't assemble
.dw 0x2000;
.dw 0x009F;
.dw 0x0000;
// multiissue with two stores (8 instrs)
.dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4;
.dw 0x2000
.dw 0x8b5b
.dw 0x9f04
.dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4;
.dw 0x2000
.dw 0x9f12
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4;
.dw 0x2000
.dw 0x9318
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4;
.dw 0x2000
.dw 0x9358
.dw 0x9f04
.dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4;
.dw 0x2000
.dw 0xbb70
.dw 0x9f04
.dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4;
.dw 0x2000
.dw 0xbb48
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4;
.dw 0x2000
.dw 0xb219
.dw 0x9f04
.dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4;
.dw 0x2000
.dw 0xbe19
.dw 0x9f04
// multiissue two instructions can't modify same ireg (6 instrs)
.dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++];
.dw 0x2000
.dw 0x9ee4
.dw 0x9c21
.dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3];
.dw 0x2000
.dw 0x9e7d
.dw 0x9de8
.dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L;
.dw 0x2000
.dw 0x9f62
.dw 0x9e30
.dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7;
.dw 0x2000
.dw 0x9f6f
.dw 0x9fbf
.dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L;
.dw 0x2000
.dw 0x9c29
.dw 0x9e2a
.dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0];
.dw 0x2000
.dw 0x9ff7
.dw 0x9d96
// multiissue two instructions can't load same dreg (9 instrs)
.dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++];
.dw 0x2000
.dw 0x8210
.dw 0x9c00
.dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2];
.dw 0x2000
.dw 0x8e58
.dw 0x9d31
.dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3];
.dw 0x2000
.dw 0x8e98
.dw 0x9dea
.dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++];
.dw 0x2000
.dw 0x9c03
.dw 0x9c0b
.dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3];
.dw 0x2000
.dw 0x9d34
.dw 0x9d3c
.dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++];
.dw 0x2000
.dw 0x9ded
.dw 0x9c35
.dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++];
.dw 0x2000
.dw 0x9106
.dw 0x9c06
.dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1];
.dw 0x2000
.dw 0xb927
.dw 0x9d2f
.dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++];
.dw 0x2000
.dw 0xabc8
.dw 0x9c00
// dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins)
.dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP;
.dw 0x0013
.dw 0xabc8
.dw 0x0000
// other slot 0 dreg cases already covered
// dsp32alu one dest and slot 1 multi with same dest (1 ins)
.dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2];
.dw 0x0225
.dw 0x0000
.dw 0x9d31
// other slot 1 dreg dest cases already covered
// dsp32alu dual dests and slot 0 multi with either same dest (2 instrs)
.dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP;
.dw 0x4680
.dw 0x8e98
.dw 0x0000
.dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP;
.dw 0x0693
.dw 0x911b
.dw 0x0000
// dsp32alu dual dests and slot 1 multi with either same dest (2 instrs)
.dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3];
.dw 0x4b00
.dw 0x0000
.dw 0x9dec
.dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++];
.dw 0x0b13
.dw 0x0000
.dw 0x9c35
// dsp32shift one dest and slot 0 multi with same dest (1 instruction)
.dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP;
.dw 0x0c2c
.dw 0x9106
.dw 0x0000
// dsp32shift one dest and slot 1 multi with same dest (1 instruction)
.dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1];
.dw 0x1e38
.dw 0x0000
.dw 0x9d2f
// dsp32shift two dests and slot 0 multi with either same dest (2 instrs)
.dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP;
.dw 0x0001
.dw 0x8210
.dw 0x0000
.dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP;
.dw 0x4013
.dw 0x9c03
.dw 0x0000
// dsp32shift two dests and slot 1 multi with either same dest (2 instrs)
.dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3];
.dw 0x0025
.dw 0x0000
.dw 0x9d5c
.dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1];
.dw 0x4037
.dw 0x0000
.dw 0x9d2f
// dsp32shiftimm one dest and slot 0 with same dest (1 instr)
.dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP;
.dw 0x1238
.dw 0x8e58
.dw 0x0000
// dsp32shiftimm one dest and slot 1 with same dest (1 instr)
.dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++];
.dw 0x0a4a
.dw 0x0000
.dw 0x9c35
// dsp32mac one dest and slot 0 multi with same dest (1 inst)
.dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP;
.dw 0x4d88
.dw 0x8f98
.dw 0x0000
// dsp32mult one dest and slot 0 multi with same dest (1 inst)
.dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP;
.dw 0x41dc
.dw 0xb927
.dw 0x0000
// dsp32 mac one dest and slot 1 multi with same dest (1 inst)
.dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++];
.dw 0x4c08
.dw 0x0000
.dw 0x9c00
// dsp32mult one dest and slot 1 multi with same dest (1 inst)
.dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1];
.dw 0x405c
.dw 0x0000
.dw 0x9d49
// dsp32mac write to register pair and slot 0 same dest - even (1 instr)
.dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP;
.dw 0x6c88
.dw 0x8e98
.dw 0x0000
// dsp32mult write to register pair and slot 0 same dest - even (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP;
.dw 0x6508
.dw 0x8108
.dw 0x0000
// dsp32mac write to register pair and slot 1 same dest - even (1 instr)
.dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3];
.dw 0x6c88
.dw 0x0000
.dw 0x9dea
// dsp32mult write to register pair and slot 1 same dest - even (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3];
.dw 0x6508
.dw 0x0000
.dw 0x9dec
// dsp32mac write to register pair and slot 0 same dest - odd (1 instr)
.dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP;
.dw 0x4c88
.dw 0x8ed8
.dw 0x0000
// dsp32mult write to register pair and slot 0 same dest - odd (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP;
.dw 0x6508
.dw 0x8148
.dw 0x0000
// dsp32mac write to register pair and slot 1 same dest - odd (1 instr)
.dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3];
.dw 0x4c88
.dw 0x0000
.dw 0x9deb
// dsp32mult write to register pair and slot 1 same dest - odd (1 instr)
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3];
.dw 0x6508
.dw 0x0000
.dw 0x9ded
// CHECKER
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x22;
CHECKREG(r5, 53); // count of all Illegal Combination Exceptions.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 16 bit illegal opcode handler - skips bad instruction
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave
dbg_fail;
JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
ILLEGALCOMBINATION:
R7 = RETX; // Fix up return address
R7 += 8; // skip offending 64 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 3,836 | sim/testsuite/bfin/c_ccflag_dr_imm3_uu.s | //Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3_uu/c_ccflag_dr_imm3_uu.dsp
// Spec Reference: ccflag dr-imm3 (uu)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00000002;
imm32 r2, 0x00000003;
imm32 r3, 0x00000004;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, 0x00000000;
ASTAT = R7;
R4 = ASTAT;
// positive dreg EQUAL to positive imm3
CC = R0 == 1;
R5 = ASTAT;
CC = R0 < 1;
R6 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CC = R0 <= 1;
R5 = ASTAT;
CC = R0 < 1 (IU);
R6 = ASTAT;
CC = R0 <= 1 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00001025;
CHECKREG r6, 0x00001005;
CHECKREG r7, 0x00001025;
// positive dreg GREATER than to positive imm3
CC = R1 == 1;
R5 = ASTAT;
CC = R1 < 1 (IU);
R6 = ASTAT;
CC = R1 <= 1 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00001004; // carry
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
// positive dreg LESS than to positive imm3
CC = R0 == 2;
R5 = ASTAT;
CC = R0 < 2 (IU);
R6 = ASTAT;
CC = R0 <= 2 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// positive dreg GREATER than to neg imm3
CC = R2 == -4;
R5 = ASTAT;
CC = R2 < 4 (IU);
R6 = ASTAT;
CC = R2 <= 4 (IU);
R7 = ASTAT;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
imm32 r0, -1;
imm32 r1, -2;
imm32 r2, -3;
imm32 r3, -4;
// negative dreg and positive imm3
R7 = 0;
ASTAT = R7;
R4 = ASTAT;
CC = R3 == 1;
R5 = ASTAT;
CC = R3 < 1 (IU);
R6 = ASTAT;
CC = R3 <= 1 (IU);
R7 = ASTAT;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00001006;
CHECKREG r6, 0x00001004;
CHECKREG r7, 0x00001004;
// negative dreg LESS than neg imm3
CC = R2 == -1;
R4 = ASTAT;
CC = R2 < 1 (IU);
R5 = ASTAT;
CC = R2 <= 1 (IU);
R6 = ASTAT;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
// negative dreg GREATER neg imm3
CC = R0 == -2;
R4 = ASTAT;
CC = R0 < 4 (IU);
R5 = ASTAT;
CC = R0 <= 4 (IU);
R6 = ASTAT;
CHECKREG r4, 0x00001004;
CHECKREG r5, 0x00001004;
CHECKREG r6, 0x00001004;
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000001;
imm32 r5, 0x00000002;
imm32 r6, 0x00000003;
imm32 r7, 0x00000004;
ASTAT = R0;
R3 = ASTAT;
// positive dreg EQUAL to positive imm3
CC = R4 == 1;
R1 = ASTAT;
CC = R4 < 1 (IU);
R2 = ASTAT;
CC = R4 <= 1 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001025;
CHECKREG r2, 0x00001005;
CHECKREG r3, 0x00001025;
// positive dreg GREATER than to positive imm3
CC = R5 == 1;
R1 = ASTAT;
CC = R5 < 1 (IU);
R2 = ASTAT;
CC = R5 <= 1 (IU);
R3 = ASTAT;
CHECKREG r1, 0x00001004; // carry
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
// positive dreg LESS than to positive imm3
CC = R6 == 2;
R1 = ASTAT;
CC = R6 < 2 (IU);
R2 = ASTAT;
CC = R6 <= 2 (IU);
R3 = ASTAT;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
// positive dreg GREATER than to neg imm3
CC = R6 == -4;
R1 = ASTAT;
CC = R6 < 4 (IU);
R2 = ASTAT;
CC = R6 <= 4 (IU);
R3 = ASTAT;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
imm32 r4, -1;
imm32 r5, -2;
imm32 r6, -3;
imm32 r7, -4;
// negative dreg and positive imm3
R3 = 0;
ASTAT = R3;
R0 = ASTAT;
CC = R7 == 1;
R1 = ASTAT;
CC = R7 < 1 (IU);
R2 = ASTAT;
CC = R7 <= 1 (IU);
R3 = ASTAT;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001006;
CHECKREG r2, 0x00001004;
CHECKREG r3, 0x00001004;
// negative dreg LESS than neg imm3
CC = R6 == -1;
R0 = ASTAT;
CC = R6 < 1 (IU);
R1 = ASTAT;
CC = R6 <= 1 (IU);
R2 = ASTAT;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
// negative dreg GREATER neg imm3
CC = R4 == -4;
R0 = ASTAT;
CC = R4 < 4 (IU);
R1 = ASTAT;
CC = R4 <= 4 (IU);
R2 = ASTAT;
CHECKREG r0, 0x00001004;
CHECKREG r1, 0x00001004;
CHECKREG r2, 0x00001004;
pass;
|
tactcomplabs/xbgas-binutils-gdb | 1,999 | sim/testsuite/bfin/c_regmv_dag_lz_dep.s | //Original:/testcases/core/c_regmv_dag_lz_dep/c_regmv_dag_lz_dep.dsp
// Spec Reference: regmv dag lz dep forward
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x11111111;
imm32 r1, 0x22223331;
imm32 r2, 0x44445551;
imm32 r3, 0x66667771;
imm32 r4, 0x88889991;
imm32 r5, 0xaaaabbb1;
imm32 r6, 0xccccddd1;
imm32 r7, 0xeeeefff1;
I0 = R0;
I0 = 0x1122 (Z);
R0 = I0;
I1 = R1;
I1 = 0x3344 (Z);
R1 = I1;
I2 = R2;
I2 = 0x5566 (Z);
R2 = I2;
I3 = R3;
I3 = 0x7788 (Z);
R3 = I3;
B0 = R4;
B0 = 0x99aa (Z);
R4 = B0;
B1 = R5;
B1 = 0xbbcc (Z);
R5 = B1;
B2 = R6;
B2 = 0xddee (Z);
R6 = B2;
B3 = R7;
B3 = 0xff01 (Z);
R7 = B3;
CHECKREG r0, 0x00001122;
CHECKREG r1, 0x00003344;
CHECKREG r2, 0x00005566;
CHECKREG r3, 0x00007788;
CHECKREG r4, 0x000099AA;
CHECKREG r5, 0x0000BBCC;
CHECKREG r6, 0x0000DDEE;
CHECKREG r7, 0x0000FF01;
imm32 r0, 0x11111112;
imm32 r1, 0x22223332;
imm32 r2, 0x44445552;
imm32 r3, 0x66667772;
imm32 r4, 0x88889992;
imm32 r5, 0xaaaabbb2;
imm32 r6, 0xccccddd2;
imm32 r7, 0xeeeefff2;
M0 = R0;
M0 = 0xa1a2 (Z);
R0 = M0;
M1 = R1;
M1 = 0xb1b2 (Z);
R1 = M1;
M2 = R2;
M2 = 0xc1c2 (Z);
R2 = M2;
M3 = R3;
M3 = 0xd1d2 (Z);
R3 = M3;
L0 = R4;
L0 = 0xe1e2 (Z);
R4 = L0;
L1 = R5;
L1 = 0xf1f2 (Z);
R5 = L1;
L2 = R6;
L2 = 0x1112 (Z);
R6 = L2;
L3 = R7;
L3 = 0x2122 (Z);
R7 = L3;
CHECKREG r0, 0x0000A1A2;
CHECKREG r1, 0x0000B1B2;
CHECKREG r2, 0x0000C1C2;
CHECKREG r3, 0x0000D1D2;
CHECKREG r4, 0x0000E1E2;
CHECKREG r5, 0x0000F1F2;
CHECKREG r6, 0x00001112;
CHECKREG r7, 0x00002122;
imm32 r0, 0x11111113;
imm32 r1, 0x22223333;
imm32 r2, 0x44445553;
imm32 r3, 0x66667773;
imm32 r4, 0x88889993;
imm32 r5, 0xaaaabbb3;
imm32 r6, 0xccccddd3;
imm32 r7, 0xeeeefff3;
P1 = R1;
P1 = 0x3A3B (Z);
R1 = P1;
P2 = R2;
P2 = 0x4A4B (Z);
R2 = P2;
P3 = R3;
P3 = 0x5A5B (Z);
R3 = P3;
P4 = R4;
P4 = 0x6A6B (Z);
R4 = P4;
P5 = R5;
P5 = 0x7A7B (Z);
R5 = P5;
CHECKREG r1, 0x00003A3B;
CHECKREG r2, 0x00004A4B;
CHECKREG r3, 0x00005A5B;
CHECKREG r4, 0x00006A6B;
CHECKREG r5, 0x00007A7B;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,305 | sim/testsuite/bfin/c_cc2stat_cc_ac.S | //Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp
// Spec Reference: cc2stat cc ac
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, _UNSET;
imm32 r1, _UNSET;
imm32 r2, _UNSET;
imm32 r3, _UNSET;
imm32 r4, _UNSET;
imm32 r5, _UNSET;
imm32 r6, _UNSET;
imm32 r7, _UNSET;
// test CC = AC 0-0, 0-1, 1-0, 1-1
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC = AC0; //
R0 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC = AC0; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC = AC0; //
R2 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC = AC0; //
R3 = CC; //
// test cc |= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC |= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC |= AC0; //
R5 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 0
CC |= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC |= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC &= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC &= AC0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC &= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC &= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC ^= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC ^= AC0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC ^= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC ^= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AC0 = CC 0-0, 0-1, 1-0, 1-1
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 = CC; //
R0 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 = CC; //
R3 = ASTAT; //
// test AC0 |= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 |= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_AC0|_CC);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0);
CHECKREG r6, (_AC0|_CC);
CHECKREG r7, (_CC|_AC0);
// test AC0 &= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 &= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AC0);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _CC;
CHECKREG r7, (_CC|_AC0);
// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AC0);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0);
CHECKREG r6, (_CC|_AC0);
CHECKREG r7, _CC;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,017 | sim/testsuite/bfin/c_cc2stat_cc_az.s | //Original:/testcases/core/c_cc2stat_cc_az/c_cc2stat_cc_az.dsp
// Spec Reference: cc2stat cc az
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AZ 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
CC = AZ; //
R0 = CC; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
CC = AZ; //
R1 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
CC = AZ; //
R2 = CC; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
CC = AZ; //
R3 = CC; //
// test cc |= AZ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
CC |= AZ; //
R4 = CC; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
CC |= AZ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
CC |= AZ; //
R6 = CC; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
CC |= AZ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
// test CC &= AZ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
CC &= AZ; //
R4 = CC; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
CC &= AZ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
CC &= AZ; //
R6 = CC; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
CC &= AZ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
// test CC ^= AZ (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
CC ^= AZ; //
R4 = CC; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
CC ^= AZ; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
CC ^= AZ; //
R6 = CC; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
CC ^= AZ; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
// test AZ = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
AZ = CC; //
R0 = ASTAT; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
AZ = CC; //
R1 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
AZ = CC; //
R2 = ASTAT; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
AZ = CC; //
R3 = ASTAT; //
// test AZ |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
AZ |= CC; //
R4 = ASTAT; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
AZ |= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
AZ |= CC; //
R6 = ASTAT; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
AZ |= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000021;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000021;
CHECKREG r7, 0x00000021;
// test AZ &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
AZ &= CC; //
R4 = ASTAT; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
AZ &= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
AZ &= CC; //
R6 = ASTAT; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
AZ &= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000021;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000021;
// test AZ ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AZ = 0
AZ ^= CC; //
R4 = ASTAT; //
R7 = 0x01;
ASTAT = R7; // cc = 0, AZ = 1
AZ ^= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AZ = 0
AZ ^= CC; //
R6 = ASTAT; //
R7 = 0x21;
ASTAT = R7; // cc = 1, AZ = 1
AZ ^= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000021;
CHECKREG r3, 0x00000021;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000021;
CHECKREG r7, 0x00000020;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,064 | sim/testsuite/bfin/c_brcc_bp3.s | //Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,135 | sim/testsuite/bfin/c_dsp32alu_abs.s | //Original:/testcases/core/c_dsp32alu_abs/c_dsp32alu_abs.dsp
// Spec Reference: dsp32alu dregs = abs ( dregs, dregs)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = ABS R0;
R1 = ABS R1;
R2 = ABS R2;
R3 = ABS R3;
R4 = ABS R4;
R5 = ABS R5;
R6 = ABS R6;
R7 = ABS R7;
CHECKREG r0, 0x15678911;
CHECKREG r1, 0x2789AB1D;
CHECKREG r2, 0x34445515;
CHECKREG r3, 0x46667717;
CHECKREG r4, 0x5567891B;
CHECKREG r5, 0x6789AB1D;
CHECKREG r6, 0x74445515;
CHECKREG r7, 0x79998889;
imm32 r0, 0x9567892b;
imm32 r1, 0xa789ab2d;
imm32 r2, 0xb4445525;
imm32 r3, 0xc6667727;
imm32 r4, 0xd8889929;
imm32 r5, 0xeaaabb2b;
imm32 r6, 0xfcccdd2d;
imm32 r7, 0x0eeeffff;
R0 = ABS R7;
R1 = ABS R6;
R2 = ABS R5;
R3 = ABS R4;
R4 = ABS R3;
R5 = ABS R2;
R6 = ABS R1;
R7 = ABS R0;
CHECKREG r0, 0x0EEEFFFF;
CHECKREG r1, 0x033322D3;
CHECKREG r2, 0x155544D5;
CHECKREG r3, 0x277766D7;
CHECKREG r4, 0x277766D7;
CHECKREG r5, 0x155544D5;
CHECKREG r6, 0x033322D3;
CHECKREG r7, 0x0EEEFFFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,096 | sim/testsuite/bfin/c_brcc_brf_brt_bp.s | //Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp
// Spec Reference: brcc brfbrt
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000444;
imm32 r5, 0x00000555;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = R4 < R5;
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP bad2 (BP); // branch on true (should not branch)
IF CC JUMP end; // we're done
bad2: R0 = 8; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000444;
CHECKREG r5, 0x00000555;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,983 | sim/testsuite/bfin/a6.s | // ALU test program.
// Test instructions
// r7 = +/+ (r0,r1);
// r7 = +/+ (r0,r1) s;
// r7 = +/+ (r0,r1) sx;
# mach: bfin
.include "testutils.inc"
start
// one result overflows positive
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// one result overflows negative
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x8000;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x7fff );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// one result zero
R0.L = 0x0001;
R0.H = 0xffff;
R1.L = 0x0001;
R1.H = 0x0001;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x0002 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R5 = CC; DBGA ( R5.L , 0x1 );
CC = AN; R5 = CC; DBGA ( R5.L , 0x0 );
CC = V; R5 = CC; DBGA ( R5.L , 0x0 );
CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 );
// one result saturates positive
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (S);
DBGA ( R7.L , 0x7fff );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// one result saturates negative
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x8000;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (S);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// two results saturates negative
R0.L = 0xffff;
R0.H = 0xfff0;
R1.L = 0x8000;
R1.H = 0x8000;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (S);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// one result overflows positive and cross
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (CO);
DBGA ( R7.L , 0x0020 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// one result saturates negative and cross
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x8000;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (SCO);
DBGA ( R7.L , 0x0020 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,583 | sim/testsuite/bfin/a0shift.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
// 0xfffffe371c
r0 = 0;
r1 = 0;
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
a1 = a0 =0;
astat = R0;
R6.L = 0x8000;
R5.H = 0x8000;
// load acc with values;
R0.L = 0xc062;
R0.H = 0xffee;
A0.w = R0;
R0.L = 0xc52c;
A0.x = R0;
R0.L = 0x8d10;
R0.H = 0x34c;
A1.w = R0;
R0.L = 0xe10c;
A1.x = R0;
// load regs with values;
R0.L = 0xe844;
R0.H = 0x4aba;
R1.L = 0xa294;
R1.H = 0x52ea;
R2.L = 0xafda;
R2.H = 0x5c32;
// end load regs and acc;
R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU);
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY);
CHECKREG R0, 0xffff;
R0 = A1.w
CHECKREG R0, 0;
R0 = A1.x
CHECKREG R0, 0;
R0 = A0.w
CHECKREG R0, 0xffeec062;
R0 = A0.x
CHECKREG R0, 0x2c;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY);
R4 = R6 +|- R5 , R3 = R6 -|+ R5;
CHECKREG R3, 0x80008000;
CHECKREG R4, 0x80008000;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS);
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
R7.H = R1.H * R3.L (TFU);
CHECKREG R7, 0x29750000;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H;
CHECKREG R7, 0xafda0000;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x50260000;
R0 = A0.x
CHECKREG R0, 0x0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS);
CHECKREG R3, 0;
CHECKREG R2, 0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU);
CHECKREG R1, 0xafda57ed;
P0 = ASTAT;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x57ed0000;
R0 = A0.x
CHECKREG R0, 0x0;
CHECKREG P0, (_VS|_AN);
R3 = R6.H * R5.L (FU);
CHECKREG R3, 0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2);
CHECKREG R5, 0x80000000;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x57ed0000;
R0 = A0.x
CHECKREG R0, 0x0;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO);
CHECKREG R3, 0x80000000;
CHECKREG R6, 0x00008000;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H );
R0 = A1.w
CHECKREG R0, 0x83e38000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0xa8130000;
R0 = A0.x
CHECKREG R0, 0x0;
CHECKREG R6, 0x7fffffff
CHECKREG R7, 0x83e38000
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
IF CC P2 = R1;
R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2);
CHECKREG R2, 0x80007fff
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T);
CHECKREG R3, 0x7fff8001
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU);
CHECKREG R7, 0xaabe7c4e
P0 = ASTAT;
CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU);
CHECKREG R0, 0x3e273e27
P0 = ASTAT;
CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2);
CHECKREG R5, 0x78b74f88
CHECKREG R4, 0xc73635f8
R0 = A1.w
CHECKREG R0, 0x3c5ba7c4;
R0 = A1.x
CHECKREG R0, 0x0;
R0 = A0.w
CHECKREG R0, 0xe39b1afc;
R0 = A0.x
CHECKREG R0, 0xffffffff;
R0 = ASTAT;
CHECKREG r0, (_VS|_AV0S|_AZ|_AN);
A0 = A0 >> 2;
R0 = ASTAT;
checkreg r0, (_VS|_AV0S);
R0 = A0.x;
DBGA (R0.L, 0x3f);
R0 = A0.w;
checkreg r0, 0xF8E6C6BF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,476 | sim/testsuite/bfin/hwloop-bits.S | # Blackfin testcase for HW Loops and user->super transitions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
.macro check_hwloop_regs lc:req, lt:req, lb:req
R0 = LC0;
CC = R0 == \lc;
IF !CC JUMP fail;
R0 = LT0;
CC = R0 == \lt;
IF !CC JUMP fail;
R0 = LB0;
CC = R0 == \lb;
IF !CC JUMP fail;
R0 = LC1;
CC = R0 == \lc;
IF !CC JUMP fail;
R0 = LT1;
CC = R0 == \lt;
IF !CC JUMP fail;
R0 = LB1;
CC = R0 == \lb;
IF !CC JUMP fail;
.endm
start
imm32 P0, EVT3;
loadsym R0, exception;
[P0] = R0;
imm32 P0, EVT2;
loadsym R0, nmi;
[P0] = R0;
loadsym R0, usermode;
RETI = R0;
# Set the LC/LB/LT up with LSB set
# - Hardware clears LT LSB, but LB remains until we lower
imm32 R6, 0xaaaa5555
R4 = R6;
BITCLR (R4, 0);
imm32 R7, 0xaa55aa55
R5 = R7;
BITCLR (R5, 0);
LC0 = R6;
LT0 = R6;
LB0 = R7;
LC1 = R6;
LT1 = R6;
LB1 = R7;
# Sanity check
check_hwloop_regs R6, R4, R7
RTI;
usermode:
# Make sure LSB has been cleared in LB
check_hwloop_regs R6, R4, R5
# Clear LSB in all LC/LT/LB
LC0 = R4;
LT0 = R4;
LB0 = R5;
LC1 = R4;
LT1 = R4;
LB1 = R5;
# Now move back up to supervisor
EXCPT 4;
exception:
# Make sure LSB is set in LB
check_hwloop_regs R4, R4, R7
# Clear the LSB and move up another supervisor level
LC0 = R4;
LT0 = R4;
LB0 = R5;
LC1 = R4;
LT1 = R4;
LB1 = R5;
RAISE 2;
nmi:
# Make sure LSB stayed clear
check_hwloop_regs R4, R4, R5
dbg_pass
fail:
dbg_fail
|
tactcomplabs/xbgas-binutils-gdb | 6,286 | sim/testsuite/bfin/c_dsp32mult_dr_s.s | //Original:/testcases/core/c_dsp32mult_dr_s/c_dsp32mult_dr_s.dsp
// Spec Reference: dsp32mult single dr s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (S2RND);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (S2RND);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (S2RND);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (S2RND);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (S2RND);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (S2RND);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (S2RND);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (S2RND);
CHECKREG r0, 0x73F473F4;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x73F473F4;
CHECKREG r5, 0x6D3B8000;
CHECKREG r6, 0x6D3B8000;
CHECKREG r7, 0x66E77FFF;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (S2RND);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (S2RND);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (S2RND);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (S2RND);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (S2RND);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (S2RND);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (S2RND);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (S2RND);
CHECKREG r0, 0xF416F416;
CHECKREG r1, 0x132C132C;
CHECKREG r2, 0xEA3BEA3B;
CHECKREG r3, 0x23072307;
CHECKREG r4, 0xEA3BEA3B;
CHECKREG r5, 0x7520E134;
CHECKREG r6, 0xFFC10010;
CHECKREG r7, 0xFFA8FFA8;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (S2RND);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (S2RND);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (S2RND);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (S2RND);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (S2RND);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (S2RND);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (S2RND);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (S2RND);
CHECKREG r0, 0x66933653;
CHECKREG r1, 0x1CF4F0A4;
CHECKREG r2, 0xF0A4F0A4;
CHECKREG r3, 0x04540458;
CHECKREG r4, 0x66933653;
CHECKREG r5, 0xE553F1DF;
CHECKREG r6, 0xF402E95B;
CHECKREG r7, 0x05E40B1E;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (S2RND);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (S2RND);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (S2RND);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (S2RND);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (S2RND);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (S2RND);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (S2RND);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (S2RND);
CHECKREG r0, 0x7FFF0F94;
CHECKREG r1, 0xDB78F6FC;
CHECKREG r2, 0xDB78F6FC;
CHECKREG r3, 0x05380538;
CHECKREG r4, 0x491708E5;
CHECKREG r5, 0x14DF14DF;
CHECKREG r6, 0x7FFF0F94;
CHECKREG r7, 0x248C0473;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (S2RND);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (S2RND);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (S2RND);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (S2RND);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (S2RND);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (S2RND);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (S2RND);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (S2RND);
CHECKREG r0, 0x0584E80E;
CHECKREG r1, 0xAEE9000F;
CHECKREG r2, 0xF613F613;
CHECKREG r3, 0xFFFAFFFA;
CHECKREG r4, 0x00050005;
CHECKREG r5, 0xFD6AFD6A;
CHECKREG r6, 0xFFF1FFF1;
CHECKREG r7, 0xF92A0193;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (S2RND);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (S2RND);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (S2RND);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (S2RND);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (S2RND);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (S2RND);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (S2RND);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (S2RND);
CHECKREG r0, 0xE7C519D4;
CHECKREG r1, 0xFFF7108C;
CHECKREG r2, 0xF6EB1B5B;
CHECKREG r3, 0xFE8C5374;
CHECKREG r4, 0x02870128;
CHECKREG r5, 0xFDA20293;
CHECKREG r6, 0x0000FFFE;
CHECKREG r7, 0x0760F915;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (S2RND);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (S2RND);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (S2RND);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (S2RND);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (S2RND);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (S2RND);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (S2RND);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (S2RND);
CHECKREG r0, 0x0016FFE6;
CHECKREG r1, 0x94D30A65;
CHECKREG r2, 0x01560010;
CHECKREG r3, 0xF238AB7A;
CHECKREG r4, 0xFFFFFDAD;
CHECKREG r5, 0x037AE9FB;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xD97200FE;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (S2RND);
R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (S2RND);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (S2RND);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (S2RND);
R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (S2RND);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (S2RND);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (S2RND);
R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (S2RND);
CHECKREG r0, 0xF718CD46;
CHECKREG r1, 0xF2CC0CCC;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0xFF56FFE2;
CHECKREG r4, 0xE480FB2C;
CHECKREG r5, 0x00000004;
CHECKREG r6, 0x00000008;
CHECKREG r7, 0xFA8000FF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,562 | sim/testsuite/bfin/c_brcc_kills_dmiss.s | //Original:/testcases/core/c_brcc_kills_dmiss/c_brcc_kills_dmiss.dsp
// Spec Reference: brcc kills data cache miss
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
IF !CC JUMP LABEL2; // (bp);
CC = ! CC;
LABEL2:
IF !CC JUMP LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
IF !CC JUMP LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
IF !CC JUMP LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
IF !CC JUMP LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
IF !CC JUMP LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
IF !CC JUMP LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
IF !CC JUMP LABEL9;
JUMP.S BAD1; // UJUMP killed
LABEL9:
IF !CC JUMP LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
LABEL10:
IF !CC JUMP LABEL11;
R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L;
// DSP32MAC killed
LABEL11:
IF !CC JUMP LABEL12;
R2 = R2 +|+ R3; // DSP32ALU killed
LABEL12:
IF !CC JUMP LABEL13;
R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed
LABEL13:
IF !CC JUMP LABEL14;
R4.H = R1.L << 6; // DSP32SHIFTIMM killed
LABEL14:
IF !CC JUMP LABEL15;
P2 = P1; // REGMV PREG-PREG killed
LABEL15:
IF !CC JUMP LABEL16;
R5 = P1; // REGMV Pr-to-Dr killed
LABEL16:
IF !CC JUMP LABEL17;
ASTAT = R2; // REGMV Dr-to-sys killed
LABEL17:
IF !CC JUMP LABEL18;
R6 = ASTAT; // REGMV sys-to-Dr killed
LABEL18:
IF !CC JUMP LABEL19;
[ I0 ] = R2; // DSPLDST store killed
LABEL19:
IF !CC JUMP end;
R7 = [ I0 ]; // DSPLDST load killed
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.data
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
|
tactcomplabs/xbgas-binutils-gdb | 7,130 | sim/testsuite/bfin/c_ldstpmod_st_dr_lo.s | //Original:testcases/core/c_ldstpmod_st_dr_lo/c_ldstpmod_st_dr_lo.dsp
// Spec Reference: c_ldstpmod store dreg lo
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm32 r2, 0x800d7002;
imm32 r3, 0x900c8003;
imm32 r4, 0xa00b9004;
imm32 r5, 0xb00aa005;
imm32 r6, 0xc009b006;
imm32 r7, 0xd008c007;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x04;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x08;
loadsym fp, DATA_ADDR_6, 0x0a;
loadsym i3, DATA_ADDR_7, 0x0c;
P3 = I1; SP = I3;
W [ P1 ] = R1.L;
W [ P2 ] = R2.L;
W [ P3 ] = R3.L;
W [ P4 ] = R4.L;
W [ P5 ] = R5.L;
W [ SP ] = R6.L;
W [ FP ] = R0.L;
R6.L = W [ P1 ];
R5.L = W [ P2 ];
R4.L = W [ P3 ];
R3.L = W [ P4 ];
R2.L = W [ P5 ];
R0.L = W [ SP ];
R1.L = W [ FP ];
CHECKREG r0, 0x600FB006;
CHECKREG r1, 0x700E5000;
CHECKREG r2, 0x800DA005;
CHECKREG r3, 0x900C9004;
CHECKREG r4, 0xA00B8003;
CHECKREG r5, 0xB00A7002;
CHECKREG r6, 0xC0096001;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x0c;
loadsym p2, DATA_ADDR_2, 0x0a;
loadsym i1, DATA_ADDR_3, 0x08;
loadsym p4, DATA_ADDR_4, 0x06;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x02;
loadsym i3, DATA_ADDR_7, 0x00;
P3 = I1; SP = I3;
W [ P1 ] = R2.L;
W [ P2 ] = R3.L;
W [ P3 ] = R4.L;
W [ P4 ] = R5.L;
W [ P5 ] = R6.L;
W [ SP ] = R7.L;
W [ FP ] = R1.L;
R1.L = W [ P1 ];
R2.L = W [ P2 ];
R3.L = W [ P3 ];
R4.L = W [ P4 ];
R5.L = W [ P5 ];
R6.L = W [ SP ];
R0.L = W [ FP ];
CHECKREG r0, 0x105F60A1;
CHECKREG r1, 0x204E70A2;
CHECKREG r2, 0x300380A3;
CHECKREG r3, 0x402C90A4;
CHECKREG r4, 0x501BA0A5;
CHECKREG r5, 0x600AB0A6;
CHECKREG r6, 0x7019C0A7;
// initial values
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x10;
loadsym p2, DATA_ADDR_2, 0x02;
loadsym i1, DATA_ADDR_3, 0x00;
loadsym p4, DATA_ADDR_4, 0x08;
loadsym p5, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x06;
loadsym i3, DATA_ADDR_7, 0x02;
P3 = I1; SP = I3;
W [ P1 ] = R5.L;
W [ P2 ] = R6.L;
W [ P3 ] = R7.L;
W [ P4 ] = R0.L;
W [ P5 ] = R1.L;
W [ SP ] = R2.L;
W [ FP ] = R3.L;
R5.L = W [ P1 ];
R4.L = W [ P2 ];
R3.L = W [ P3 ];
R2.L = W [ P4 ];
R1.L = W [ P5 ];
R0.L = W [ SP ];
R6.L = W [ FP ];
CHECKREG r0, 0x10BF70B2;
CHECKREG r1, 0x20BE60B1;
CHECKREG r2, 0x30BD50B0;
CHECKREG r3, 0x40BCC0B7;
CHECKREG r4, 0x55BBB0B6;
CHECKREG r5, 0x60BAA0B5;
CHECKREG r6, 0x70B980B3;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 14,881 | sim/testsuite/bfin/c_logi2op_nbittst.s | //Original:/testcases/core/c_logi2op_nbittst/c_logi2op_nbittst.dsp
// Spec Reference: Logi2op !bittst
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// bit(0-7) tst set clr toggle
CC = ! BITTST( R0 , 0 ); /* cc = 0 */
BITSET( R0 , 0 ); /* r0 = 0x00000001 */
R1 = CC;
CC = ! BITTST( R0 , 0 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 0 ); /* r0 = 0x00000000 */
CC = ! BITTST( R0 , 0 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 0 ); /* r0 = 0x00000001 */
CC = ! BITTST( R0 , 0 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CC = ! BITTST( R1 , 1 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 1 ); /* r0 = 0x00000002 */
CC = ! BITTST( R1 , 1 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 1 ); /* r0 = 0x00000000 */
CC = ! BITTST( R1 , 1 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 1 ); /* r0 = 0x00000002 */
CC = ! BITTST( R1 , 1 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x00000003;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CC = ! BITTST( R2 , 2 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 2 ); /* r0 = 0x00000004 */
CC = ! BITTST( R2 , 2 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 2 ); /* r0 = 0x00000000 */
CC = ! BITTST( R2 , 2 ); /* cc = 1 */
R5 = CC;
BITTGL( R2 , 2 ); /* r0 = 0x00000004 */
CC = ! BITTST( R2 , 2 ); /* cc = 1 */
R6 = CC;
CHECKREG r2, 0x00000005;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CC = ! BITTST( R3 , 3 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 3 ); /* r0 = 0x00000008 */
CC = ! BITTST( R3 , 3 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 3 ); /* r0 = 0x00000000 */
CC = ! BITTST( R3 , 3 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 3 ); /* r0 = 0x00000008 */
CC = ! BITTST( R3 , 3 ); /* cc = 1 */
R7 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000003;
CHECKREG r2, 0x00000005;
CHECKREG r3, 0x00000009;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CC = ! BITTST( R4 , 4 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 4 ); /* r0 = 0x00000010 */
CC = ! BITTST( R4 , 4 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 4 ); /* r0 = 0x00000000 */
CC = ! BITTST( R4 , 4 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 4 ); /* r0 = 0x00000010 */
CC = ! BITTST( R4 , 4 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x00000011;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CC = ! BITTST( R5 , 5 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 5 ); /* r0 = 0x00000020 */
CC = ! BITTST( R5 , 5 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 5 ); /* r0 = 0x00000000 */
CC = ! BITTST( R5 , 5 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 5 ); /* r0 = 0x00000020 */
CC = ! BITTST( R5 , 5 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x00000021;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CC = ! BITTST( R6 , 6 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 6 ); /* r0 = 0x00000040 */
CC = ! BITTST( R6 , 6 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 6 ); /* r0 = 0x00000000 */
CC = ! BITTST( R6 , 6 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 6 ); /* r0 = 0x00000040 */
CC = ! BITTST( R6 , 6 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x00000041;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CC = ! BITTST( R7 , 7 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 7 ); /* r0 = 0x00000080 */
CC = ! BITTST( R7 , 7 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 7 ); /* r0 = 0x00000000 */
CC = ! BITTST( R7 , 7 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 7 ); /* r0 = 0x00000080 */
CC = ! BITTST( R7 , 7 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000011;
CHECKREG r5, 0x00000021;
CHECKREG r6, 0x00000041;
CHECKREG r7, 0x00000081;
// bit(8-15) tst set clr toggle
CC = ! BITTST( R0 , 8 ); /* cc = 0 */
R1 = CC;
BITSET( R0 , 8 ); /* r0 = 0x00000101 */
CC = ! BITTST( R0 , 8 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 8 ); /* r0 = 0x00000000 */
CC = ! BITTST( R0 , 8 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 8 ); /* r0 = 0x00000101 */
CC = ! BITTST( R0 , 8 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x00000101;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CC = ! BITTST( R1 , 9 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 9 ); /* r0 = 0x00000202 */
CC = ! BITTST( R1 , 9 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 9 ); /* r0 = 0x00000000 */
CC = ! BITTST( R1 , 9 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 9 ); /* r0 = 0x00000202 */
CC = ! BITTST( R1 , 9 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x00000201;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CC = ! BITTST( R2 , 10 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 10 ); /* r0 = 0x00000404 */
CC = ! BITTST( R2 , 10 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 10 ); /* r0 = 0x00000000 */
CC = ! BITTST( R2 , 10 ); /* cc = 1 */
R5 = CC;
BITTGL( R2 , 10 ); /* r0 = 0x00000404 */
CC = ! BITTST( R2 , 10 ); /* cc = 1 */
R6 = CC;
CHECKREG r2, 0x00000401;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CC = ! BITTST( R3 , 11 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 11 ); /* r0 = 0x00000808 */
CC = ! BITTST( R3 , 11 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 11 ); /* r0 = 0x00000000 */
CC = ! BITTST( R3 , 11 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 11 ); /* r0 = 0x00000808 */
CC = ! BITTST( R3 , 11 ); /* cc = 1 */
R7 = CC;
CHECKREG r3, 0x00000801;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CC = ! BITTST( R4 , 12 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 12 ); /* r0 = 0x00001010 */
CC = ! BITTST( R4 , 12 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 12 ); /* r0 = 0x00000000 */
CC = ! BITTST( R4 , 12 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 12 ); /* r0 = 0x00001010 */
CC = ! BITTST( R4 , 12 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x00001001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CC = ! BITTST( R5 , 13 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 13 ); /* r0 = 0x00002020 */
CC = ! BITTST( R5 , 13 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 13 ); /* r0 = 0x00000000 */
CC = ! BITTST( R5 , 13 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 13 ); /* r0 = 0x00002020 */
CC = ! BITTST( R5 , 13 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x00002001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CC = ! BITTST( R6 , 14 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 14 ); /* r0 = 0x00004040 */
CC = ! BITTST( R6 , 14 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 14 ); /* r0 = 0x00000000 */
CC = ! BITTST( R6 , 14 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 14 ); /* r0 = 0x00004040 */
CC = ! BITTST( R6 , 14 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x00004001;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CC = ! BITTST( R7 , 15 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 15 ); /* r0 = 0x00008080 */
CC = ! BITTST( R7 , 15 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 15 ); /* r0 = 0x00000000 */
CC = ! BITTST( R7 , 15 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 15 ); /* r0 = 0x00008080 */
CC = ! BITTST( R7 , 15 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00001001;
CHECKREG r5, 0x00002001;
CHECKREG r6, 0x00004001;
CHECKREG r7, 0x00008001;
// bit(16-23) tst set clr toggle
CC = ! BITTST( R0 , 16 ); /* cc = 0 */
R1 = CC;
BITSET( R0 , 16 ); /* r0 = 0x00000001 */
CC = ! BITTST( R0 , 16 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 16 ); /* r0 = 0x00000000 */
CC = ! BITTST( R0 , 16 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 16 ); /* r0 = 0x00000001 */
CC = ! BITTST( R0 , 16 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CC = ! BITTST( R1 , 17 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 17 ); /* r0 = 0x00000002 */
CC = ! BITTST( R1 , 17 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 17 ); /* r0 = 0x00000000 */
CC = ! BITTST( R1 , 17 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 17 ); /* r0 = 0x00000002 */
CC = ! BITTST( R1 , 17 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CC = ! BITTST( R2 , 18 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 18 ); /* r0 = 0x00000004 */
CC = ! BITTST( R2 , 18 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 18 ); /* r0 = 0x00000000 */
CC = ! BITTST( R2 , 18 ); /* cc = 1 */
R4 = CC;
BITTGL( R2 , 18 ); /* r0 = 0x00000004 */
CC = ! BITTST( R2 , 18 ); /* cc = 1 */
R5 = CC;
CHECKREG r2, 0x00040001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00004001;
CC = ! BITTST( R3 , 19 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 19 ); /* r0 = 0x00000008 */
CC = ! BITTST( R3 , 19 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 19 ); /* r0 = 0x00000000 */
CC = ! BITTST( R3 , 19 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 19 ); /* r0 = 0x00000008 */
CC = ! BITTST( R3 , 19 ); /* cc = 1 */
R7 = CC;
CHECKREG r3, 0x00080001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CC = ! BITTST( R4 , 20 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 20 ); /* r0 = 0x00000010 */
CC = ! BITTST( R4 , 20 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 20 ); /* r0 = 0x00000000 */
CC = ! BITTST( R4 , 20 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 20 ); /* r0 = 0x00000010 */
CC = ! BITTST( R4 , 20 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x00100001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CC = ! BITTST( R5 , 21 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 21 ); /* r0 = 0x00000020 */
CC = ! BITTST( R5 , 21 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 21 ); /* r0 = 0x00000000 */
CC = ! BITTST( R5 , 21 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 21 ); /* r0 = 0x00000020 */
CC = ! BITTST( R5 , 21 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x00200001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CC = ! BITTST( R6 , 22 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 22 ); /* r0 = 0x00000040 */
CC = ! BITTST( R6 , 22 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 22 ); /* r0 = 0x00000000 */
CC = ! BITTST( R6 , 22 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 22 ); /* r0 = 0x00000040 */
CC = ! BITTST( R6 , 22 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x00400001;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CC = ! BITTST( R7 , 23 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 23 ); /* r0 = 0x00000080 */
CC = ! BITTST( R7 , 23 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 23 ); /* r0 = 0x00000000 */
CC = ! BITTST( R7 , 23 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 23 ); /* r0 = 0x00000080 */
CC = ! BITTST( R7 , 23 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00100001;
CHECKREG r5, 0x00200001;
CHECKREG r6, 0x00400001;
CHECKREG r7, 0x00800001;
// bit(24-31) tst set clr toggle
CC = ! BITTST( R0 , 24 ); /* cc = 0 */
R1 = CC;
BITSET( R0 , 24 ); /* r0 = 0x00000101 */
CC = ! BITTST( R0 , 24 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 24 ); /* r0 = 0x00000000 */
CC = ! BITTST( R0 , 24 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 24 ); /* r0 = 0x00000101 */
CC = ! BITTST( R0 , 24 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x01000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CC = ! BITTST( R1 , 25 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 25 ); /* r0 = 0x00000202 */
CC = ! BITTST( R1 , 25 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 25 ); /* r0 = 0x00000000 */
CC = ! BITTST( R1 , 25 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 25 ); /* r0 = 0x00000202 */
CC = ! BITTST( R1 , 25 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x02000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CC = ! BITTST( R2 , 26 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 26 ); /* r0 = 0x00000404 */
CC = ! BITTST( R2 , 26 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 26 ); /* r0 = 0x00000000 */
CC = ! BITTST( R2 , 26 ); /* cc = 1 */
R5 = CC;
BITTGL( R2 , 26 ); /* r0 = 0x00000404 */
CC = ! BITTST( R2 , 26 ); /* cc = 1 */
R6 = CC;
CHECKREG r2, 0x04000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CC = ! BITTST( R3 , 27 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 27 ); /* r0 = 0x00000808 */
CC = ! BITTST( R3 , 27 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 27 ); /* r0 = 0x00000000 */
CC = ! BITTST( R3 , 27 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 27 ); /* r0 = 0x00000808 */
CC = ! BITTST( R3 , 27 ); /* cc = 1 */
R7 = CC;
CHECKREG r3, 0x08000001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CC = ! BITTST( R4 , 28 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 28 ); /* r0 = 0x00001010 */
CC = ! BITTST( R4 , 28 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 28 ); /* r0 = 0x00000000 */
CC = ! BITTST( R4 , 28 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 28 ); /* r0 = 0x00001010 */
CC = ! BITTST( R4 , 28 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x10000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CC = ! BITTST( R5 , 29 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 29 ); /* r0 = 0x00002020 */
CC = ! BITTST( R5 , 29 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 29 ); /* r0 = 0x00000000 */
CC = ! BITTST( R5 , 29 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 29 ); /* r0 = 0x00002020 */
CC = ! BITTST( R5 , 29 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x20000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CC = ! BITTST( R6 , 30 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 30 ); /* r0 = 0x00004040 */
CC = ! BITTST( R6 , 30 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 30 ); /* r0 = 0x00000000 */
CC = ! BITTST( R6 , 30 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 30 ); /* r0 = 0x00004040 */
CC = ! BITTST( R6 , 30 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x40000001;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CC = ! BITTST( R7 , 31 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 31 ); /* r0 = 0x00008080 */
CC = ! BITTST( R7 , 31 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 31 ); /* r0 = 0x00000000 */
CC = ! BITTST( R7 , 31 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 31 ); /* r0 = 0x80808080 */
CC = ! BITTST( R7 , 31 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x10000001;
CHECKREG r5, 0x20000001;
CHECKREG r6, 0x40000001;
CHECKREG r7, 0x80000001;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,478 | sim/testsuite/bfin/c_dsp32shift_signbits_r.s | //Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp
// Spec Reference: dsp32shift signbits dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x88880000;
imm32 r1, 0x34560001;
imm32 r2, 0x08000002;
imm32 r3, 0x08000003;
imm32 r4, 0x08000004;
imm32 r5, 0x08000005;
imm32 r6, 0x08000006;
imm32 r7, 0x08000007;
R7.L = SIGNBITS R0;
R1.L = SIGNBITS R0;
R2.L = SIGNBITS R0;
R3.L = SIGNBITS R0;
R4.L = SIGNBITS R0;
R5.L = SIGNBITS R0;
R6.L = SIGNBITS R0;
R0.L = SIGNBITS R0;
CHECKREG r0, 0x88880000;
CHECKREG r1, 0x34560000;
CHECKREG r2, 0x08000000;
CHECKREG r3, 0x08000000;
CHECKREG r4, 0x08000000;
CHECKREG r5, 0x08000000;
CHECKREG r6, 0x08000000;
CHECKREG r7, 0x08000000;
imm32 r0, 0x9999001E;
imm32 r1, 0x0000001E;
imm32 r2, 0x0000001E;
imm32 r3, 0x0000001E;
imm32 r4, 0x0000001E;
imm32 r5, 0x0000001E;
imm32 r6, 0x0000001E;
imm32 r7, 0x0000001E;
R0.L = SIGNBITS R1;
R7.L = SIGNBITS R1;
R2.L = SIGNBITS R1;
R3.L = SIGNBITS R1;
R4.L = SIGNBITS R1;
R5.L = SIGNBITS R1;
R6.L = SIGNBITS R1;
R1.L = SIGNBITS R1;
CHECKREG r0, 0x9999001A;
CHECKREG r1, 0x0000001A;
CHECKREG r2, 0x0000001A;
CHECKREG r3, 0x0000001A;
CHECKREG r4, 0x0000001A;
CHECKREG r5, 0x0000001A;
CHECKREG r6, 0x0000001A;
CHECKREG r7, 0x0000001A;
imm32 r0, 0x0aaae001;
imm32 r1, 0x0000e001;
imm32 r2, 0xaaaa000f;
imm32 r3, 0x0a00e003;
imm32 r4, 0x00a0e004;
imm32 r5, 0x00a0e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0b00e007;
R0.L = SIGNBITS R2;
R1.L = SIGNBITS R2;
R7.L = SIGNBITS R2;
R3.L = SIGNBITS R2;
R4.L = SIGNBITS R2;
R5.L = SIGNBITS R2;
R6.L = SIGNBITS R2;
R2.L = SIGNBITS R2;
CHECKREG r0, 0x0AAA0000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xAAAA0000;
CHECKREG r3, 0x0A000000;
CHECKREG r4, 0x00A00000;
CHECKREG r5, 0x00A00000;
CHECKREG r6, 0x0A000000;
CHECKREG r7, 0x0B000000;
imm32 r0, 0x0b00f001;
imm32 r1, 0x0a00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0xbbbb0010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x00b0f007;
R0.L = SIGNBITS R3;
R1.L = SIGNBITS R3;
R2.L = SIGNBITS R3;
R7.L = SIGNBITS R3;
R4.L = SIGNBITS R3;
R5.L = SIGNBITS R3;
R6.L = SIGNBITS R3;
R3.L = SIGNBITS R3;
CHECKREG r0, 0x0B000000;
CHECKREG r1, 0x0A000000;
CHECKREG r2, 0x0B000000;
CHECKREG r3, 0xBBBB0000;
CHECKREG r4, 0x0B000000;
CHECKREG r5, 0x0B000000;
CHECKREG r6, 0x0B000000;
CHECKREG r7, 0x00B00000;
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0xcccc0000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = SIGNBITS R4;
R1.L = SIGNBITS R4;
R2.L = SIGNBITS R4;
R3.L = SIGNBITS R4;
R7.L = SIGNBITS R4;
R5.L = SIGNBITS R4;
R6.L = SIGNBITS R4;
R4.L = SIGNBITS R4;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020001;
CHECKREG r3, 0x00030001;
CHECKREG r4, 0xCCCC0001;
CHECKREG r5, 0x00050001;
CHECKREG r6, 0x00060001;
CHECKREG r7, 0x00070001;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xdddd0000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = SIGNBITS R5;
R1.L = SIGNBITS R5;
R2.L = SIGNBITS R5;
R3.L = SIGNBITS R5;
R4.L = SIGNBITS R5;
R7.L = SIGNBITS R5;
R6.L = SIGNBITS R5;
R5.L = SIGNBITS R5;
CHECKREG r0, 0xA0010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0xA0020001;
CHECKREG r3, 0xA0030001;
CHECKREG r4, 0xA0040001;
CHECKREG r5, 0xDDDD0001;
CHECKREG r6, 0xA0060001;
CHECKREG r7, 0xA0070001;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xeeee0000;
imm32 r7, 0xb0070000;
R0.L = SIGNBITS R6;
R1.L = SIGNBITS R6;
R2.L = SIGNBITS R6;
R3.L = SIGNBITS R6;
R4.L = SIGNBITS R6;
R5.L = SIGNBITS R6;
R7.L = SIGNBITS R6;
R6.L = SIGNBITS R6;
CHECKREG r0, 0xB0010002;
CHECKREG r1, 0xB0010002;
CHECKREG r2, 0xB0020002;
CHECKREG r3, 0xB0030002;
CHECKREG r4, 0xB0040002;
CHECKREG r5, 0xB0050002;
CHECKREG r6, 0xEEEE0002;
CHECKREG r7, 0xB0070002;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xffff0000;
R0.L = SIGNBITS R7;
R1.L = SIGNBITS R7;
R2.L = SIGNBITS R7;
R3.L = SIGNBITS R7;
R4.L = SIGNBITS R7;
R5.L = SIGNBITS R7;
R6.L = SIGNBITS R7;
R7.L = SIGNBITS R7;
CHECKREG r0, 0xD001000F;
CHECKREG r1, 0xD001000F;
CHECKREG r2, 0xD002000F;
CHECKREG r3, 0xD003000F;
CHECKREG r4, 0xD004000F;
CHECKREG r5, 0xD005000F;
CHECKREG r6, 0xD006000F;
CHECKREG r7, 0xFFFF000F;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,130 | sim/testsuite/bfin/c_alu2op_conv_h.s | //Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp
// Spec Reference: alu2op convert h
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.L (Z);
R1 = R0.L (Z);
R2 = R0.L (Z);
R3 = R0.L (Z);
R4 = R0.L (Z);
R5 = R0.L (Z);
R6 = R0.L (Z);
R7 = R0.L (Z);
CHECKREG r0, 0x00009ABC;
CHECKREG r1, 0x00009ABC;
CHECKREG r2, 0x00009ABC;
CHECKREG r3, 0x00009ABC;
CHECKREG r4, 0x00009ABC;
CHECKREG r5, 0x00009ABC;
CHECKREG r6, 0x00009ABC;
CHECKREG r7, 0x00009ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.L (Z);
R2 = R1.L (Z);
R3 = R1.L (Z);
R4 = R1.L (Z);
R5 = R1.L (Z);
R6 = R1.L (Z);
R7 = R1.L (Z);
R1 = R1.L (Z);
CHECKREG r0, 0x00004659;
CHECKREG r1, 0x00004659;
CHECKREG r2, 0x00004659;
CHECKREG r3, 0x00004659;
CHECKREG r4, 0x00004659;
CHECKREG r5, 0x00004659;
CHECKREG r6, 0x00004659;
CHECKREG r7, 0x00004659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.L (Z);
R1 = R2.L (Z);
R3 = R2.L (Z);
R4 = R2.L (Z);
R5 = R2.L (Z);
R6 = R2.L (Z);
R7 = R2.L (Z);
R2 = R2.L (Z);
CHECKREG r0, 0x00006789;
CHECKREG r1, 0x00006789;
CHECKREG r2, 0x00006789;
CHECKREG r3, 0x00006789;
CHECKREG r4, 0x00006789;
CHECKREG r5, 0x00006789;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x00006789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.L (Z);
R1 = R3.L (Z);
R2 = R3.L (Z);
R4 = R3.L (Z);
R5 = R3.L (Z);
R6 = R3.L (Z);
R7 = R3.L (Z);
R3 = R3.L (Z);
CHECKREG r0, 0x0000789A;
CHECKREG r1, 0x0000789A;
CHECKREG r2, 0x0000789A;
CHECKREG r3, 0x0000789A;
CHECKREG r4, 0x0000789A;
CHECKREG r5, 0x0000789A;
CHECKREG r6, 0x0000789A;
CHECKREG r7, 0x0000789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.L (Z);
R1 = R4.L (Z);
R2 = R4.L (Z);
R3 = R4.L (Z);
R4 = R4.L (Z);
R5 = R4.L (Z);
R6 = R4.L (Z);
R7 = R4.L (Z);
CHECKREG r0, 0x0000A9AB;
CHECKREG r1, 0x0000A9AB;
CHECKREG r2, 0x0000A9AB;
CHECKREG r3, 0x0000A9AB;
CHECKREG r4, 0x0000A9AB;
CHECKREG r5, 0x0000A9AB;
CHECKREG r6, 0x0000A9AB;
CHECKREG r7, 0x0000A9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.L (Z);
R1 = R5.L (Z);
R2 = R5.L (Z);
R3 = R5.L (Z);
R4 = R5.L (Z);
R6 = R5.L (Z);
R7 = R5.L (Z);
R5 = R5.L (Z);
CHECKREG r0, 0x00009FBC;
CHECKREG r1, 0x00009FBC;
CHECKREG r2, 0x00009FBC;
CHECKREG r3, 0x00009FBC;
CHECKREG r4, 0x00009FBC;
CHECKREG r5, 0x00009FBC;
CHECKREG r6, 0x00009FBC;
CHECKREG r7, 0x00009FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.L (Z);
R1 = R6.L (Z);
R2 = R6.L (Z);
R3 = R6.L (Z);
R4 = R6.L (Z);
R5 = R6.L (Z);
R7 = R6.L (Z);
R6 = R6.L (Z);
CHECKREG r0, 0x0000AECD;
CHECKREG r1, 0x0000AECD;
CHECKREG r2, 0x0000AECD;
CHECKREG r3, 0x0000AECD;
CHECKREG r4, 0x0000AECD;
CHECKREG r5, 0x0000AECD;
CHECKREG r6, 0x0000AECD;
CHECKREG r7, 0x0000AECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.L (Z);
R1 = R7.L (Z);
R2 = R7.L (Z);
R3 = R7.L (Z);
R4 = R7.L (Z);
R5 = R7.L (Z);
R6 = R7.L (Z);
R7 = R7.L (Z);
CHECKREG r0, 0x0000BC88;
CHECKREG r1, 0x0000BC88;
CHECKREG r2, 0x0000BC88;
CHECKREG r3, 0x0000BC88;
CHECKREG r4, 0x0000BC88;
CHECKREG r5, 0x0000BC88;
CHECKREG r6, 0x0000BC88;
CHECKREG r7, 0x0000BC88;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,914 | sim/testsuite/bfin/c_dsp32alu_rh_p.s | //Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34645515;
imm32 r3, 0x46667717;
imm32 r4, 0xd678891b;
imm32 r5, 0x6e89ab1d;
imm32 r6, 0x74b45515;
imm32 r7, 0x866cc777;
R0.H = R0.L + R0.L (NS);
R1.H = R0.L + R1.H (NS);
R2.H = R0.H + R2.L (NS);
R3.H = R0.H + R3.H (NS);
R4.H = R0.L + R4.L (NS);
R5.H = R0.L + R5.H (NS);
R6.H = R0.H + R6.L (NS);
R7.H = R0.H + R7.H (NS);
CHECKREG r4, 0x122C891B;
CHECKREG r5, 0xF79AAB1D;
CHECKREG r6, 0x67375515;
CHECKREG r7, 0x988EC777;
CHECKREG r4, 0x122C891B;
CHECKREG r5, 0xF79AAB1D;
CHECKREG r6, 0x67375515;
CHECKREG r7, 0x988EC777;
imm32 r0, 0x12348911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567b891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0x86667a77;
R0.H = R1.L + R0.L (NS);
R1.H = R1.L + R1.H (NS);
R2.H = R1.H + R2.L (NS);
R3.H = R1.H + R3.H (NS);
R4.H = R1.L + R4.L (NS);
R5.H = R1.L + R5.H (NS);
R6.H = R1.H + R6.L (NS);
R7.H = R1.H + R7.H (NS);
CHECKREG r4, 0x3438891B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0x8EBBB515;
CHECKREG r7, 0x600C7A77;
CHECKREG r4, 0x3438891B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0x8EBBB515;
CHECKREG r7, 0x600C7A77;
imm32 r0, 0x85678911;
imm32 r1, 0x3989ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x5e78891b;
imm32 r5, 0x67d9ab1d;
imm32 r6, 0x744b5515;
imm32 r7, 0x86668777;
R0.H = R2.L + R0.L (NS);
R1.H = R2.L + R1.H (NS);
R2.H = R2.H + R2.L (NS);
R3.H = R2.H + R3.H (NS);
R4.H = R2.L + R4.L (NS);
R5.H = R2.L + R5.H (NS);
R6.H = R2.H + R6.L (NS);
R7.L = R2.H + R7.H (NS);
CHECKREG r4, 0xDE30891B;
CHECKREG r5, 0xBCEEAB1D;
CHECKREG r6, 0xDE6E5515;
CHECKREG r7, 0x86660FBF;
CHECKREG r4, 0xDE30891B;
CHECKREG r5, 0xBCEEAB1D;
CHECKREG r6, 0xDE6E5515;
CHECKREG r7, 0x86660FBF;
imm32 r0, 0x25678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x3e445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567f891b;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667b77;
R0.H = R3.L + R0.L (NS);
R1.H = R3.L + R1.H (NS);
R2.H = R3.H + R2.L (NS);
R3.H = R3.H + R3.H (NS);
R4.H = R3.L + R4.L (NS);
R5.H = R3.L + R5.H (NS);
R6.H = R3.H + R6.L (NS);
R7.H = R3.H + R7.H (NS);
CHECKREG r4, 0x0032891B;
CHECKREG r5, 0xDEA0BB1D;
CHECKREG r6, 0xE2C15515;
CHECKREG r7, 0x14127B77;
CHECKREG r4, 0x0032891B;
CHECKREG r5, 0xDEA0BB1D;
CHECKREG r6, 0xE2C15515;
CHECKREG r7, 0x14127B77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R4.L + R0.L (NS);
R1.H = R4.L + R1.H (NS);
R2.H = R4.H + R2.L (NS);
R3.H = R4.H + R3.H (NS);
R4.H = R4.L + R4.L (NS);
R5.H = R4.L + R5.H (NS);
R6.H = R4.H + R6.L (NS);
R7.H = R4.H + R7.H (NS);
CHECKREG r4, 0x1236891B;
CHECKREG r5, 0xF0A4AB1D;
CHECKREG r6, 0x674B5515;
CHECKREG r7, 0x989C7777;
CHECKREG r4, 0x1236891B;
CHECKREG r5, 0xF0A4AB1D;
CHECKREG r6, 0x674B5515;
CHECKREG r7, 0x989C7777;
imm32 r0, 0xa5678911;
imm32 r1, 0x2a89ab1d;
imm32 r2, 0x34d45515;
imm32 r3, 0x466b7717;
imm32 r4, 0x5678f91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444a515;
imm32 r7, 0x86667b77;
R0.H = R5.L + R0.L (NS);
R1.H = R5.L + R1.H (NS);
R2.H = R5.H + R2.L (NS);
R3.H = R5.H + R3.H (NS);
R4.H = R5.L + R4.L (NS);
R5.H = R5.L + R5.H (NS);
R6.H = R5.H + R6.L (NS);
R7.H = R5.H + R7.H (NS);
CHECKREG r4, 0xA438F91B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0xB7BBA515;
CHECKREG r7, 0x990C7B77;
CHECKREG r4, 0xA438F91B;
CHECKREG r5, 0x12A6AB1D;
CHECKREG r6, 0xB7BBA515;
CHECKREG r7, 0x990C7B77;
imm32 r0, 0xf5678911;
imm32 r1, 0x2f89ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46f67717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678fab1d;
imm32 r6, 0x7444f515;
imm32 r7, 0x86667f77;
R0.L = R6.L + R0.L (NS);
R1.H = R6.L + R1.H (NS);
R2.H = R6.H + R2.L (NS);
R3.H = R6.H + R3.H (NS);
R4.H = R6.L + R4.L (NS);
R5.H = R6.L + R5.H (NS);
R6.H = R6.H + R6.L (NS);
R7.H = R6.H + R7.H (NS);
CHECKREG r4, 0x7E30891B;
CHECKREG r5, 0x5CA4AB1D;
CHECKREG r6, 0x6959F515;
CHECKREG r7, 0xEFBF7F77;
CHECKREG r4, 0x7E30891B;
CHECKREG r5, 0x5CA4AB1D;
CHECKREG r6, 0x6959F515;
CHECKREG r7, 0xEFBF7F77;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.H = R7.L + R0.L (NS);
R1.H = R7.L + R1.H (NS);
R2.H = R7.H + R2.L (NS);
R3.H = R7.H + R3.H (NS);
R4.H = R7.L + R4.L (NS);
R5.H = R7.L + R5.H (NS);
R6.H = R7.H + R6.L (NS);
R7.H = R7.H + R7.H (NS);
CHECKREG r4, 0x0092891B;
CHECKREG r5, 0xDF00AB1D;
CHECKREG r6, 0xDB7B5515;
CHECKREG r7, 0x0CCC7777;
CHECKREG r4, 0x0092891B;
CHECKREG r5, 0xDF00AB1D;
CHECKREG r6, 0xDB7B5515;
CHECKREG r7, 0x0CCC7777;
imm32 r0, 0x56678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34645515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5678e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0x744455f5;
imm32 r7, 0x866677b7;
R6.H = R2.L + R3.L (S);
R1.H = R4.L + R5.H (S);
R5.H = R7.H + R2.L (S);
R3.H = R0.H + R0.H (S);
R0.H = R3.L + R4.L (S);
R2.H = R5.L + R7.H (S);
R7.H = R6.H + R7.L (S);
R4.H = R1.H + R6.H (S);
CHECKREG r4, 0x7FFFE91B;
CHECKREG r5, 0xDB7BAF1D;
CHECKREG r6, 0x7FFF55F5;
CHECKREG r7, 0x7FFF77B7;
CHECKREG r4, 0x7FFFE91B;
CHECKREG r5, 0xDB7BAF1D;
CHECKREG r6, 0x7FFF55F5;
CHECKREG r7, 0x7FFF77B7;
imm32 r0, 0x95678911;
imm32 r1, 0x2989ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46967717;
imm32 r4, 0x5679891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74449515;
imm32 r7, 0x86667977;
R3.H = R4.L + R0.L (S);
R1.H = R6.L + R3.H (S);
R4.H = R3.H + R2.L (S);
R6.H = R7.H + R1.H (S);
R2.H = R5.L + R4.L (S);
R7.H = R2.L + R7.H (S);
R0.H = R1.H + R6.L (S);
R5.H = R0.H + R5.H (S);
CHECKREG r4, 0xD515891B;
CHECKREG r5, 0xE789AB1D;
CHECKREG r6, 0x80009515;
CHECKREG r7, 0xDB7B7977;
CHECKREG r4, 0xD515891B;
CHECKREG r5, 0xE789AB1D;
CHECKREG r6, 0x80009515;
CHECKREG r7, 0xDB7B7977;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,203 | sim/testsuite/bfin/byteunpack.s | # Blackfin testcase for playing with BYTEUNPACK
# mach: bfin
.include "testutils.inc"
start
.macro _bu_pre_test i0:req, src0:req, src1:req
dmm32 I0, \i0
imm32 R0, \src0
imm32 R1, \src1
.endm
.macro _bu_chk_test dst0:req, dst1:req
imm32 R2, \dst0
imm32 R3, \dst1
CC = R5 == R2;
IF !CC jump 1f;
CC = R6 == R3;
IF !CC jump 1f;
.endm
.macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req
_bu_pre_test \i0, \src0, \src1
(R6, R5) = BYTEUNPACK R1:0;
_bu_chk_test \dst0, \dst1
.endm
.macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req
_bu_pre_test \i0, \src0, \src1
(R6, R5) = BYTEUNPACK R1:0 (R);
_bu_chk_test \dst0, \dst1
.endm
# Taken from PRM
bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE
bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE
bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE
bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE
# Taken from PRM
bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE
pass
1: fail
|
tactcomplabs/xbgas-binutils-gdb | 6,093 | sim/testsuite/bfin/c_dsp32mac_pair_a1_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_u/c_dsp32mac_pair_a1_u.dsp
// Spec Reference: dsp32mac pair a1 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
imm32 r3, 0x00890007;
imm32 r4, 0xefb89569;
imm32 r5, 0x1235890b;
imm32 r6, 0x000c089d;
imm32 r7, 0x678e0089;
R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (FU);
P1 = A1.w;
R1 = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L (FU);
P2 = A1.w;
R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (FU);
P3 = A1.w;
R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (FU);
P4 = A1.w;
CHECKREG r0, 0x93545ABD;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0xA8945679;
CHECKREG r3, 0x08B4E563;
CHECKREG r4, 0xEFB89569;
CHECKREG r5, 0x0D514922;
CHECKREG r6, 0x000C089D;
CHECKREG r7, 0x5A4E0EEB;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0x00025D4F;
CHECKREG p3, 0x08B4E563;
CHECKREG p4, 0x0D514922;
imm32 r0, 0x98464abd;
imm32 r1, 0xa1b5f4c7;
imm32 r2, 0xa1146649;
imm32 r3, 0x00010805;
imm32 r4, 0xefbc1599;
imm32 r5, 0x12350100;
imm32 r6, 0x200c001d;
imm32 r7, 0x628e0001;
R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (FU);
P1 = A1.w;
R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (FU);
P2 = A1.w;
R3 = ( A1 = R4.L * R5.H ), A0 += R4.H * R5.H (FU);
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (FU);
P4 = A1.w;
CHECKREG r0, 0x98464ABD;
CHECKREG r1, 0x0D7355F0;
CHECKREG r2, 0xA1146649;
CHECKREG r3, 0x0D682BDA;
CHECKREG r4, 0xEFBC1599;
CHECKREG r5, 0x9EEA5F8C;
CHECKREG r6, 0x200C001D;
CHECKREG r7, 0x628E0001;
CHECKREG p1, 0x9EEA5F8C;
CHECKREG p2, 0x00006649;
CHECKREG p3, 0x0D682BDA;
CHECKREG p4, 0x0D7355F0;
imm32 r0, 0x713a459d;
imm32 r1, 0xabd6aec7;
imm32 r2, 0x7a145a79;
imm32 r3, 0x08a100a7;
imm32 r4, 0xef9a156a;
imm32 r5, 0x1225a10b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0a61;
R5 = ( A1 += R7.H * R3.L ), A0 = R7.L * R3.L (FU);
P1 = A1.w;
R7 = ( A1 = R2.H * R4.L ), A0 -= R2.H * R4.L (FU);
P2 = A1.w;
R1 = ( A1 -= R0.H * R5.L ), A0 += R0.H * R5.H (FU);
P3 = A1.w;
R5 = ( A1 += R6.H * R1.L ), A0 += R6.L * R1.H (FU);
P4 = A1.w;
CHECKREG r0, 0x713A459D;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x7A145A79;
CHECKREG r3, 0x08A100A7;
CHECKREG r4, 0xEF9A156A;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x0003401D;
CHECKREG r7, 0x0A363048;
CHECKREG p1, 0x0DB6E392;
CHECKREG p2, 0x0A363048;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x00000000;
imm32 r0, 0x773489bd;
imm32 r1, 0x917cfec7;
imm32 r2, 0xa9177679;
imm32 r3, 0xd0910777;
imm32 r4, 0xedb91579;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d077999;
imm32 r7, 0x677e0709;
R1 = ( A1 += R5.H * R3.H ), A0 -= R5.L * R3.L (FU);
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L (FU);
P2 = A1.w;
R5 = ( A1 = R7.H * R0.H ), A0 += R7.H * R0.H (FU);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (FU);
P4 = A1.w;
CHECKREG r0, 0x773489BD;
CHECKREG r1, 0xAB422005;
CHECKREG r2, 0xA9177679;
CHECKREG r3, 0x711DF4EE;
CHECKREG r4, 0xEDB91579;
CHECKREG r5, 0x30309798;
CHECKREG r6, 0x0D077999;
CHECKREG r7, 0x3C497CA7;
CHECKREG p1, 0xAB422005;
CHECKREG p2, 0x711DF4EE;
CHECKREG p3, 0x30309798;
CHECKREG p4, 0x3C497CA7;
imm32 r0, 0x83547abd;
imm32 r1, 0x88bc8ec7;
imm32 r2, 0xa8895679;
imm32 r3, 0x00080007;
imm32 r4, 0xe6b86569;
imm32 r5, 0x1A35860b;
imm32 r6, 0x000c896d;
imm32 r7, 0x67Be0096;
R7 = ( A1 += R1.L * R0.L ) (FU);
P1 = A1.w;
R1 = ( A1 = R2.H * R3.L ) (FU);
P2 = A1.w;
R3 = ( A1 -= R7.L * R4.H ) (FU);
P3 = A1.w;
R5 = ( A1 += R6.H * R5.H ) (FU);
P4 = A1.w;
CHECKREG r0, 0x83547ABD;
CHECKREG r1, 0x00049BBF;
CHECKREG r2, 0xA8895679;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xE6B86569;
CHECKREG r5, 0x00013A7C;
CHECKREG r6, 0x000C896D;
CHECKREG r7, 0x80BDBB92;
CHECKREG p1, 0x80BDBB92;
CHECKREG p2, 0x00049BBF;
CHECKREG p3, 0x00000000;
CHECKREG p4, 0x00013A7C;
imm32 r0, 0x9aa64abd;
imm32 r1, 0xa1baf4c7;
imm32 r2, 0xb114a649;
imm32 r3, 0x0b010005;
imm32 r4, 0xefbcdb69;
imm32 r5, 0x123501bb;
imm32 r6, 0x000c0d1b;
imm32 r7, 0x678e0d01;
R5 = ( A1 += R5.L * R0.H ) (M), A0 = R5.L * R0.L (FU);
P1 = A1.w;
R1 = ( A1 = R1.L * R3.H ) (M), A0 = R1.H * R3.L (FU);
P2 = A1.w;
R3 = ( A1 -= R2.L * R6.H ) (M), A0 += R2.H * R6.H (FU);
P3 = A1.w;
R1 = ( A1 += R4.L * R7.H ) (M), A0 += R4.L * R7.H (FU);
P4 = A1.w;
CHECKREG r0, 0x9AA64ABD;
CHECKREG r1, 0xF0BBA999;
CHECKREG r2, 0xB114A649;
CHECKREG r3, 0xFF88B65B;
CHECKREG r4, 0xEFBCDB69;
CHECKREG r5, 0x010CD7BE;
CHECKREG r6, 0x000C0D1B;
CHECKREG r7, 0x678E0D01;
CHECKREG p1, 0x010CD7BE;
CHECKREG p2, 0xFF8481C7;
CHECKREG p3, 0xFF88B65B;
CHECKREG p4, 0xF0BBA999;
imm32 r0, 0xd136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0xdd010007;
imm32 r4, 0xeddc1569;
imm32 r5, 0x122d010b;
imm32 r6, 0x00e3d01d;
imm32 r7, 0x678e0d61;
R5 = A1 , A0 = R1.L * R0.L (FU);
P1 = A1.w;
R7 = A1 , A0 = R2.H * R3.L (FU);
P2 = A1.w;
R1 = A1 , A0 += R4.H * R5.H (FU);
P3 = A1.w;
R5 = A1 , A0 += R6.L * R7.H (FU);
P4 = A1.w;
CHECKREG r0, 0xD136459D;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0xDD010007;
CHECKREG r4, 0xEDDC1569;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00E3D01D;
CHECKREG r7, 0xFFFFFFFF;
CHECKREG p1, 0xF0BBA999;
CHECKREG p2, 0xF0BBA999;
CHECKREG p3, 0xF0BBA999;
CHECKREG p4, 0xF0BBA999;
imm32 r0, 0x125489bd;
imm32 r1, 0x91b5fec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910507;
imm32 r4, 0x34567859;
imm32 r5, 0xd2359105;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ) (M,FU);
P1 = A1.w;
R3 = ( A1 -= R2.H * R1.H ) (M,FU);
P2 = A1.w;
R5 = ( A1 = R7.H * R0.H ) (M,FU);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ) (M,FU);
P4 = A1.w;
CHECKREG r0, 0x125489BD;
CHECKREG r1, 0xCB6CC99E;
CHECKREG r2, 0xA9145679;
CHECKREG r3, 0x107E992E;
CHECKREG r4, 0x34567859;
CHECKREG r5, 0x076FB0D8;
CHECKREG r6, 0x0D0C0999;
CHECKREG r7, 0x0A1A82E0;
CHECKREG p1, 0xCB6CC99E;
CHECKREG p2, 0x107E992E;
CHECKREG p3, 0x076FB0D8;
CHECKREG p4, 0x0A1A82E0;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,821 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0/c_dsp32mac_pair_a1a0.dsp
// Spec Reference: dsp32mac pair a1a0
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L );
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L );
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H );
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H );
FP = A1.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x0004BA9E;
CHECKREG r2, 0x00177258;
CHECKREG r3, 0x17A3558C;
CHECKREG r4, 0x0455E4F4;
CHECKREG r5, 0xFB35EDF0;
CHECKREG r6, 0xFF221DD6;
CHECKREG r7, 0xFF221DD6;
CHECKREG p1, 0xFF221DD6;
CHECKREG p2, 0xFF221DD6;
CHECKREG p3, 0x0004BA9E;
CHECKREG p4, 0xFFFB3578;
CHECKREG p5, 0x17A3558C;
CHECKREG sp, 0x00177258;
CHECKREG fp, 0xFB35EDF0;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 = R1.L * R0.L );
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 -= R2.H * R3.L );
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H );
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H );
FP = A0.w;
CHECKREG r0, 0xF955783E;
CHECKREG r1, 0xFC03F6B2;
CHECKREG r2, 0xF93E0212;
CHECKREG r3, 0xFBEC8086;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0x0449E564;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x0449E564;
CHECKREG p2, 0xF9762F0E;
CHECKREG p3, 0x0000AC92;
CHECKREG p4, 0xF9762F0E;
CHECKREG p5, 0xFBEC8086;
CHECKREG sp, 0xF93E0212;
CHECKREG fp, 0xF955783E;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L );
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 -= R2.H * R3.L );
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H );
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 += R6.L * R7.H );
FP = A0.w;
CHECKREG r0, 0xDFA7BA7E;
CHECKREG r1, 0xF66CBF80;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xEF9AE3A2;
CHECKREG r5, 0x004EF7CC;
CHECKREG r6, 0xCB19D6FE;
CHECKREG r7, 0xCE37E816;
CHECKREG p1, 0xCE3E172E;
CHECKREG p2, 0xCB200616;
CHECKREG p3, 0xCE37E816;
CHECKREG p5, 0xF66CBF80;
CHECKREG p4, 0xCB19D6FE;
CHECKREG sp, 0xDFA7BA7E;
CHECKREG fp, 0xEF9AE3A2;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L );
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L );
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H );
P5 = A1.w;
SP = A0.w;
R7 = ( A1 -= R4.H * R6.H ), R6 = ( A0 -= R4.L * R6.H );
FP = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0x114737D6;
CHECKREG r2, 0xDA154570;
CHECKREG r3, 0xF4447118;
CHECKREG r4, 0xDA0F974C;
CHECKREG r5, 0xF44A1F3C;
CHECKREG r6, 0xE4BBB02C;
CHECKREG r7, 0xF82827D4;
CHECKREG p1, 0x114737D6;
CHECKREG p2, 0xFFF9EE9A;
CHECKREG p3, 0xF4447118;
CHECKREG p4, 0xDA154570;
CHECKREG p5, 0xF44A1F3C;
CHECKREG sp, 0xDA0F974C;
CHECKREG fp, 0xE4BBB02C;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,831 | sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp
// Spec Reference: ptr2op shadd preg, pregs, 1 (2)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4, 0xa00a1089;
imm32 p5, 0x400a300b;
imm32 sp, 0xe07c180d;
imm32 fp, 0x206e109f;
P1 = ( P1 + P1 ) << 2;
P2 = ( P2 + P1 ) << 2;
P3 = ( P3 + P1 ) << 2;
P4 = ( P4 + P1 ) << 1;
P5 = ( P5 + P1 ) << 2;
SP = ( SP + P1 ) << 2;
FP = ( FP + P1 ) << 1;
CHECKREG p1, 0x84909018;
CHECKREG p2, 0x0A528C74;
CHECKREG p3, 0x559A907C;
CHECKREG p4, 0x49354142;
CHECKREG p5, 0x126B008C;
CHECKREG sp, 0x9432A094;
CHECKREG fp, 0x49FD416E;
imm32 p1, 0x50021003;
imm32 p2, 0x26041005;
imm32 p3, 0x60761007;
imm32 p4, 0x20081009;
imm32 p5, 0xf00a900b;
imm32 sp, 0xb00c1a0d;
imm32 fp, 0x200e10bf;
P1 = ( P1 + P2 ) << 1;
P2 = ( P2 + P2 ) << 2;
P3 = ( P3 + P2 ) << 1;
P4 = ( P4 + P2 ) << 2;
P5 = ( P5 + P2 ) << 2;
SP = ( SP + P2 ) << 1;
FP = ( FP + P2 ) << 2;
CHECKREG p1, 0xEC0C4010;
CHECKREG p2, 0x30208028;
CHECKREG p3, 0x212D205E;
CHECKREG p4, 0x40A240C4;
CHECKREG p5, 0x80AC40CC;
CHECKREG sp, 0xC059346A;
CHECKREG fp, 0x40BA439C;
imm32 p1, 0x30026003;
imm32 p2, 0x40051005;
imm32 p3, 0x20e65057;
imm32 p4, 0x2d081089;
imm32 p5, 0xf00ab07b;
imm32 sp, 0x200c1b0d;
imm32 fp, 0x200e100f;
P1 = ( P1 + P3 ) << 2;
P2 = ( P2 + P3 ) << 1;
P3 = ( P3 + P3 ) << 2;
P4 = ( P4 + P3 ) << 2;
P5 = ( P5 + P3 ) << 2;
SP = ( SP + P3 ) << 1;
FP = ( FP + P3 ) << 2;
CHECKREG p1, 0x43A2C168;
CHECKREG p2, 0xC1D6C0B8;
CHECKREG p3, 0x073282B8;
CHECKREG p4, 0xD0EA4D04;
CHECKREG p5, 0xDCF4CCCC;
CHECKREG sp, 0x4E7D3B8A;
CHECKREG fp, 0x9D024B1C;
imm32 p1, 0xa0021003;
imm32 p2, 0x2c041005;
imm32 p3, 0x40b61007;
imm32 p4, 0x250d1009;
imm32 p5, 0x260ae00b;
imm32 sp, 0x700c110d;
imm32 fp, 0x900e104f;
P1 = ( P1 + P4 ) << 1;
P2 = ( P2 + P4 ) << 2;
P3 = ( P3 + P4 ) << 2;
P4 = ( P4 + P4 ) << 2;
P5 = ( P5 + P4 ) << 1;
SP = ( SP + P4 ) << 2;
FP = ( FP + P4 ) << 2;
CHECKREG p1, 0x8A1E4018;
CHECKREG p2, 0x44448038;
CHECKREG p3, 0x970C8040;
CHECKREG p4, 0x28688048;
CHECKREG p5, 0x9CE6C0A6;
CHECKREG sp, 0x61D24554;
CHECKREG fp, 0xE1DA425C;
imm32 p1, 0xae021003;
imm32 p2, 0x22041705;
imm32 p3, 0x20361487;
imm32 p4, 0x90743009;
imm32 p5, 0xa60aa00b;
imm32 sp, 0xb00c1b0d;
imm32 fp, 0x200e10cf;
P1 = ( P1 + P5 ) << 2;
P2 = ( P2 + P5 ) << 2;
P3 = ( P3 + P5 ) << 2;
P4 = ( P4 + P5 ) << 2;
P5 = ( P5 + P5 ) << 1;
SP = ( SP + P5 ) << 2;
FP = ( FP + P5 ) << 2;
CHECKREG p1, 0x5032C038;
CHECKREG p2, 0x203ADC40;
CHECKREG p3, 0x1902D248;
CHECKREG p4, 0xD9FB4050;
CHECKREG p5, 0x982A802C;
CHECKREG sp, 0x20DA6CE4;
CHECKREG fp, 0xE0E243EC;
imm32 p1, 0x50021003;
imm32 p2, 0x62041005;
imm32 p3, 0x70e61007;
imm32 p4, 0x290f1009;
imm32 p5, 0x700ab00b;
imm32 sp, 0x2a0c1d0d;
imm32 fp, 0xb00e1e0f;
P1 = ( P1 + SP ) << 2;
P2 = ( P2 + SP ) << 1;
P3 = ( P3 + SP ) << 2;
P4 = ( P4 + SP ) << 2;
P5 = ( P5 + SP ) << 2;
SP = ( SP + SP ) << 1;
FP = ( FP + SP ) << 2;
CHECKREG p1, 0xE838B440;
CHECKREG p2, 0x18205A24;
CHECKREG p3, 0x6BC8B450;
CHECKREG p4, 0x4C6CB458;
CHECKREG p5, 0x685B3460;
CHECKREG sp, 0xA8307434;
CHECKREG fp, 0x60FA490C;
imm32 p1, 0x32002003;
imm32 p2, 0x24004005;
imm32 p3, 0xe0506007;
imm32 p4, 0xd0068009;
imm32 p5, 0x230ae00b;
imm32 sp, 0x205c1f0d;
imm32 fp, 0x200e10bf;
P1 = ( P1 + FP ) << 2;
P2 = ( P2 + FP ) << 1;
P3 = ( P3 + FP ) << 2;
P4 = ( P4 + FP ) << 2;
P5 = ( P5 + FP ) << 2;
SP = ( SP + FP ) << 2;
FP = ( FP + FP ) << 2;
CHECKREG p1, 0x4838C308;
CHECKREG p2, 0x881CA188;
CHECKREG p3, 0x0179C318;
CHECKREG p4, 0xC0524320;
CHECKREG p5, 0x0C63C328;
CHECKREG sp, 0x01A8BF30;
CHECKREG fp, 0x007085F8;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,385 | sim/testsuite/bfin/se_cof.S | //Original:/proj/frio/dv/testcases/seq/se_cof/se_cof.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
NOP;
//lz(p0) = 0x0004;
//h(p0) = 0xffe0;
LD32(p0, DMEM_CONTROL);
CSYNC;
R0 = [ P0 ]; // MMR load will Stall
JUMP.S lab1; // Branch in EX1
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
lab1:
[ -- SP ] = ( R7:3 );
IF !CC JUMP 2; // Mispredicted branch;
NOP;
JUMP.S lab2; // Branch in EX1
NOP;
NOP;
NOP;
NOP;
lab2:
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_3 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 7,545 | sim/testsuite/bfin/c_ldst_st_p_d_pp_b.s | //Original:/testcases/core/c_ldst_st_p_d_pp_b/c_ldst_st_p_d_pp_b.dsp
// Spec Reference: c_ldst st_p++ b byte
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// store incremented by 1 loc
B [ P5 ++ ] = R0;
B [ P1 ++ ] = R1;
B [ P2 ++ ] = R2;
B [ P4 ++ ] = R4;
B [ FP ++ ] = R5;
B [ P5 ++ ] = R1;
B [ P1 ++ ] = R2;
B [ P2 ++ ] = R3;
B [ P4 ++ ] = R5;
B [ FP ++ ] = R6;
B [ P5 ++ ] = R2;
B [ P1 ++ ] = R3;
B [ P2 ++ ] = R4;
B [ P4 ++ ] = R6;
B [ FP ++ ] = R7;
B [ P5 ++ ] = R3;
B [ P1 ++ ] = R4;
B [ P2 ++ ] = R5;
B [ P4 ++ ] = R7;
B [ FP ++ ] = R0;
B [ P5 ++ ] = R4;
B [ P1 ++ ] = R5;
B [ P2 ++ ] = R6;
B [ P4 ++ ] = R0;
B [ FP ++ ] = R1;
B [ P5 ++ ] = R5;
B [ P1 ++ ] = R6;
B [ P2 ++ ] = R7;
B [ P4 ++ ] = R1;
B [ FP ++ ] = R2;
B [ P5 ++ ] = R6;
B [ P1 ++ ] = R7;
B [ P2 ++ ] = R0;
B [ P4 ++ ] = R2;
B [ FP ++ ] = R3;
B [ P5 ++ ] = R7;
B [ P1 ++ ] = R0;
B [ P2 ++ ] = R1;
B [ P4 ++ ] = R3;
B [ FP ++ ] = R4;
// Read back and check
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
CHECKREG r0, 0x4B3A2918;
CHECKREG r1, 0x5C4B3A29;
CHECKREG r3, 0x7E6D5C4B;
CHECKREG r4, 0x3A291807;
CHECKREG r5, 0x077E6D5C;
CHECKREG r7, 0x719A8C7E;
R1 = [ P1 ++ ];
R2 = [ P2 ++ ];
R4 = [ P4 ++ ];
R5 = [ P5 ++ ];
R6 = [ FP ++ ];
CHECKREG r0, 0x4B3A2918;
CHECKREG r1, 0x077E6D5C;
CHECKREG r2, 0x18077E6D;
CHECKREG r4, 0x3A291807;
CHECKREG r5, 0x7E6D5C4B;
CHECKREG r6, 0x4B3A2918;
R2 = [ P1 ++ ];
R3 = [ P2 ++ ];
R5 = [ P4 ++ ];
R6 = [ P5 ++ ];
R7 = [ FP ++ ];
CHECKREG r1, 0x077E6D5C;
CHECKREG r2, 0x28292A2B;
CHECKREG r3, 0x48494A4B;
CHECKREG r5, 0x88898A8B;
CHECKREG r6, 0x08090A0B;
CHECKREG r7, 0xA8A9AAAB;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 6,135 | sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678911;
imm32 r1, 0x9189ab1d;
imm32 r2, 0xa4245515;
imm32 r3, 0xb6637717;
imm32 r4, 0xc678491b;
imm32 r5, 0x6789a51d;
imm32 r6, 0xe4445565;
imm32 r7, 0x86667777;
R0.L = R0 - R0 (RND12);
R1.L = R0 - R1 (RND12);
R2.L = R0 - R2 (RND12);
R3.L = R0 - R3 (RND12);
R4.L = R0 - R4 (RND12);
R5.L = R0 - R5 (RND12);
R6.L = R0 - R6 (RND12);
R7.L = R0 - R7 (RND12);
CHECKREG r0, 0x85670000;
CHECKREG r1, 0x91898000;
CHECKREG r2, 0xA4248000;
CHECKREG r3, 0xB6638000;
CHECKREG r4, 0xC6788000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0xE4448000;
CHECKREG r7, 0x8666F009;
imm32 r0, 0x75678921;
imm32 r1, 0x2789ab14;
imm32 r2, 0xd4745515;
imm32 r3, 0x4d677767;
imm32 r4, 0x56d8791b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86a6d777;
R0.L = R1 - R0 (RND12);
R1.L = R1 - R1 (RND12);
R2.L = R1 - R2 (RND12);
R3.L = R1 - R3 (RND12);
R4.L = R1 - R4 (RND12);
R5.L = R1 - R5 (RND12);
R6.L = R1 - R6 (RND12);
R7.L = R1 - R7 (RND12);
CHECKREG r0, 0x75678000;
CHECKREG r1, 0x27890000;
CHECKREG r2, 0xD4747FFF;
CHECKREG r3, 0x4D678000;
CHECKREG r4, 0x56D88000;
CHECKREG r5, 0x678D8000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86A67fff;
imm32 r0, 0x55678911;
imm32 r1, 0x2689ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46967717;
imm32 r4, 0xa67a891b;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x8666c777;
R0.L = R2 - R0 (RND12);
R1.L = R2 - R1 (RND12);
R2.L = R2 - R2 (RND12);
R3.L = R2 - R3 (RND12);
R4.L = R2 - R4 (RND12);
R5.L = R2 - R5 (RND12);
R6.L = R2 - R6 (RND12);
R7.L = R2 - R7 (RND12);
CHECKREG r0, 0x55678000;
CHECKREG r1, 0x26897fff;
CHECKREG r2, 0x3D440000;
CHECKREG r3, 0x46968000;
CHECKREG r4, 0xA67A7fff;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86667fff;
imm32 r0, 0xf5678911;
imm32 r1, 0xd789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xe6667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6d89ab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0xe6667b77;
R0.L = R3 - R0 (RND12);
R1.L = R3 - R1 (RND12);
R2.L = R3 - R2 (RND12);
R3.L = R3 - R3 (RND12);
R4.L = R3 - R4 (RND12);
R5.L = R3 - R5 (RND12);
R6.L = R3 - R6 (RND12);
R7.L = R3 - R7 (RND12);
CHECKREG r0, 0xF5678000;
CHECKREG r1, 0xD7897fff;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0xE6660000;
CHECKREG r4, 0x56788000;
CHECKREG r5, 0x6D898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0xE666FFF8;
imm32 r0, 0xa5678911;
imm32 r1, 0x2b89ab1d;
imm32 r2, 0x34c45515;
imm32 r3, 0x46d67717;
imm32 r4, 0x56e8891b;
imm32 r5, 0x67f9ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86687777;
R0.L = R4 - R0 (RND12);
R1.L = R4 - R1 (RND12);
R2.L = R4 - R2 (RND12);
R3.L = R4 - R3 (RND12);
R4.L = R4 - R4 (RND12);
R5.L = R4 - R5 (RND12);
R6.L = R4 - R6 (RND12);
R7.L = R4 - R7 (RND12);
CHECKREG r0, 0xa5677fff;
CHECKREG r1, 0x2b897fff;
CHECKREG r2, 0x34c47fff;
CHECKREG r3, 0x46d67fff;
CHECKREG r4, 0x56E80000;
CHECKREG r5, 0x67F98000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86687fff;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5ff8891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8666a7b7;
R0.L = R5 - R0 (RND12);
R1.L = R5 - R1 (RND12);
R2.L = R5 - R2 (RND12);
R3.L = R5 - R3 (RND12);
R4.L = R5 - R4 (RND12);
R5.L = R5 - R5 (RND12);
R6.L = R5 - R6 (RND12);
R7.L = R5 - R7 (RND12);
CHECKREG r0, 0xE5677fff;
CHECKREG r1, 0x27897fff;
CHECKREG r2, 0x34447fff;
CHECKREG r3, 0xD6667fff;
CHECKREG r4, 0x5FF87912;
CHECKREG r5, 0x67890000;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x86667fff;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ae1d;
imm32 r2, 0x344455e5;
imm32 r3, 0x4666771d;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789abdd;
imm32 r6, 0x74a45515;
imm32 r7, 0x866c77b7;
R0.L = R6 - R0 (RND12);
R1.L = R6 - R1 (RND12);
R2.L = R6 - R2 (RND12);
R3.L = R6 - R3 (RND12);
R4.L = R6 - R4 (RND12);
R5.L = R6 - R5 (RND12);
R6.L = R6 - R6 (RND12);
R7.L = R6 - R7 (RND12);
CHECKREG r0, 0x15677fff;
CHECKREG r1, 0x27897fff;
CHECKREG r2, 0x34447fff;
CHECKREG r3, 0x46667fff;
CHECKREG r4, 0x56787fff;
CHECKREG r5, 0x67897fff;
CHECKREG r6, 0x74A40000;
CHECKREG r7, 0x866C7fff;
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46567717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0xb666a777;
R0.L = R7 - R0 (RND12);
R1.L = R7 - R1 (RND12);
R2.L = R7 - R2 (RND12);
R3.L = R7 - R3 (RND12);
R4.L = R7 - R4 (RND12);
R5.L = R7 - R5 (RND12);
R6.L = R7 - R6 (RND12);
R7.L = R7 - R7 (RND12);
CHECKREG r0, 0x25678000;
CHECKREG r1, 0x23898000;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0x46568000;
CHECKREG r4, 0x56788000;
CHECKREG r5, 0x678D8000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0xB6660000;
imm32 r0, 0xaa678911;
imm32 r1, 0x27ddab1d;
imm32 r2, 0x344bb515;
imm32 r3, 0x46667717;
imm32 r4, 0x56dd891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444bb15;
imm32 r7, 0x86ff7777;
R6.L = R2 - R3 (RND12);
R1.L = R4 - R5 (RND12);
R5.L = R7 - R2 (RND12);
R3.L = R0 - R0 (RND12);
R0.L = R3 - R4 (RND12);
R2.L = R5 - R7 (RND12);
R7.L = R6 - R7 (RND12);
R4.L = R1 - R6 (RND12);
CHECKREG r0, 0xAA678000;
CHECKREG r1, 0x27DD8000;
CHECKREG r2, 0x344B7fff;
CHECKREG r3, 0x46660000;
CHECKREG r4, 0x56DD8000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86FF7fff;
imm32 r0, 0x95678911;
imm32 r1, 0x2d89ab1d;
imm32 r2, 0x34b45515;
imm32 r3, 0x46c67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x678fab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8b66a777;
R3.L = R4 - R0 (RND12);
R1.L = R6 - R3 (RND12);
R4.L = R3 - R2 (RND12);
R6.L = R7 - R1 (RND12);
R2.L = R5 - R4 (RND12);
R7.L = R2 - R7 (RND12);
R0.L = R1 - R6 (RND12);
R5.L = R0 - R5 (RND12);
CHECKREG r0, 0x95678000;
CHECKREG r1, 0x2D897fff;
CHECKREG r2, 0x34B47fff;
CHECKREG r3, 0x46C67fff;
CHECKREG r4, 0x567E7fff;
CHECKREG r5, 0x678F8000;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x8B667FFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 8,465 | sim/testsuite/bfin/c_mmr_loop.S | //Original:/proj/frio/dv/testcases/core/c_mmr_loop/c_mmr_loop.dsp
// Spec Reference: mmr loop (interr control) no exception
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// EVTx
// wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000
LD32(p0, 0xFFE02000);
LD32(r0, 0x00000000);
[ P0 ] = R0;
// wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004
LD32(p0, 0xFFE02004);
LD32(r0, 0x00000000);
[ P0 ] = R0;
// wrt-rd EVT2 = 0xFFE02008
LD32(p0, 0xFFE02008);
LD32(r0, 0xE1DE5D1C);
[ P0 ] = R0;
// wrt-rd EVT3 = 0xFFE0200C
LD32(p0, 0xFFE0200C);
LD32(r0, 0x9CC20332);
[ P0 ] = R0;
// wrt-rd EVT4 = 0xFFE02010
LD32(p0, 0xFFE02010);
LD32(r0, 0x00000000); // not implemented
[ P0 ] = R0;
// wrt-rd EVT5 = 0xFFE02014
LD32(p0, 0xFFE02014);
LD32(r0, 0x55552345);
[ P0 ] = R0;
// wrt-rd EVT6 = 0xFFE02018
LD32(p0, 0xFFE02018);
LD32(r0, 0x66663456);
[ P0 ] = R0;
// wrt-rd EVT7 = 0xFFE0201C
LD32(p0, 0xFFE0201C);
LD32(r0, 0x77774567);
[ P0 ] = R0;
// wrt-rd EVT8 = 0xFFE02020
LD32(p0, 0xFFE02020);
LD32(r0, 0x88885678);
[ P0 ] = R0;
// wrt-rd EVT9 = 0xFFE02024
LD32(p0, 0xFFE02024);
LD32(r0, 0x99996789);
[ P0 ] = R0;
// wrt-rd EVT10 = 0xFFE02028
LD32(p0, 0xFFE02028);
LD32(r0, 0xaaaa1234);
[ P0 ] = R0;
// wrt-rd EVT11 = 0xFFE0202C
LD32(p0, 0xFFE0202C);
LD32(r0, 0xBBBBABC6);
[ P0 ] = R0;
// wrt-rd EVT12 = 0xFFE02030
LD32(p0, 0xFFE02030);
LD32(r0, 0xCCCCABC6);
[ P0 ] = R0;
// wrt-rd EVT13 = 0xFFE02034
LD32(p0, 0xFFE02034);
LD32(r0, 0xDDDDABC6);
[ P0 ] = R0;
// wrt-rd EVT14 = 0xFFE02038
LD32(p0, 0xFFE02038);
LD32(r0, 0xEEEEABC6);
[ P0 ] = R0;
// wrt-rd EVT15 = 0xFFE0203C
LD32(p0, 0xFFE0203C);
LD32(r0, 0xFFFFABC6);
[ P0 ] = R0;
// wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100
LD32(p0, 0xFFE02100);
LD32(r0, 0x000001ff);
[ P0 ] = R0;
// wrt-rd IMASK: 16 bits = 0xFFE02104
LD32(p0, 0xFFE02104);
LD32(r0, 0x00000fe0);
[ P0 ] = R0;
// wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108
LD32(p0, 0xFFE02108);
LD32(r0, 0x00000000);
//[p0] = r0;
RAISE 12;
RAISE 13;
// wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C
LD32(p0, 0xFFE0210C);
LD32(r0, 0x00000000);
//[p0] = r0;
CSYNC;
//*** read ops
P1.L = DATA0;
P1.H = DATA0;
LD32(p0, 0xFFE02000);
P2 = 16;
LSETUP ( start1 , end1 ) LC0 = P2;
start1:
R0 = [ P0 ++ ];
end1: [ P1 ++ ] = R0;
//nop;
P1.L = DATA0;
P1.H = DATA0;
R0 = [ P1 ++ ];
R1 = [ P1 ++ ];
R2 = [ P1 ++ ];
R3 = [ P1 ++ ];
R4 = [ P1 ++ ];
R5 = [ P1 ++ ];
R6 = [ P1 ++ ];
R7 = [ P1 ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0xE1DE5D1C);
CHECKREG(r3, 0x9CC20332);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x55552345);
CHECKREG(r6, 0x66663456);
CHECKREG(r7, 0x77774567);
R0 = [ P1 ++ ];
R1 = [ P1 ++ ];
R2 = [ P1 ++ ];
R3 = [ P1 ++ ];
R4 = [ P1 ++ ];
R5 = [ P1 ++ ];
R6 = [ P1 ++ ];
R7 = [ P1 ++ ];
CHECKREG(r0, 0x88885678);
CHECKREG(r1, 0x99996789);
CHECKREG(r2, 0xAAAA1234);
CHECKREG(r3, 0xBBBBABC6);
CHECKREG(r4, 0xCCCCABC6);
CHECKREG(r5, 0xDDDDABC6);
CHECKREG(r6, 0xEEEEABC6);
CHECKREG(r7, 0xFFFFABC6);
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R7 = 0x00006789 (X);
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 1,523 | sim/testsuite/bfin/s6.s | // Test r4 = VMAX/VMAX (r5,r1) A0<<2;
# mach: bfin
.include "testutils.inc"
start
// Both max values are in high half, hence both bits
// into A0 are 1
A0 = 0;
R1.L = 0x2; // max in r1 is 3
R1.H = 0x3;
R0.L = 0x6; // max in r0 is 7
R0.H = 0x7;
R6 = VIT_MAX( R1 , R0 ) (ASL);
DBGA ( R6.L , 0x0007 );
DBGA ( R6.H , 0x0003 );
R7 = A0.w;
DBGA ( R7.L , 0x0003 );
DBGA ( R7.H , 0x0000 );
R7.L = A0.x;
DBGA ( R7.L , 0x0000 );
// max value in r1 is in low, so second bit into A0 is zero
A0 = 0;
R1.L = 0x3; // max in r1 is 3
R1.H = 0x2;
R0.L = 0x6; // max in r0 is 7
R0.H = 0x7;
R6 = VIT_MAX( R1 , R0 ) (ASL);
DBGA ( R6.L , 0x0007 );
DBGA ( R6.H , 0x0003 );
R7 = A0.w;
DBGA ( R7.L , 0x0002 );
DBGA ( R7.H , 0x0000 );
R7.L = A0.x;
DBGA ( R7.L , 0x0000 );
// both max values in low, so both bits into A0 are zero
R0.L = 0x8000;
R0.H = 0x0;
A0.w = R0;
R1.L = 0x3; // max in r1 is 3
R1.H = 0x2;
R0.L = 0x7; // max in r0 is 7
R0.H = 0x6;
R6 = VIT_MAX( R1 , R0 ) (ASL);
DBGA ( R6.L , 0x0007 );
DBGA ( R6.H , 0x0003 );
R7 = A0.w;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0002 );
R7.L = A0.x;
DBGA ( R7.L , 0x0000 );
// Test for correct max when one value overflows
A0 = 0;
R1.L = 0x7fff; // max in r1 is 0x8001 (overflowed)
R1.H = 0x8001;
R0.L = 0x6; // max in r0 is 7
R0.H = 0x7;
R6 = VIT_MAX( R1 , R0 ) (ASL);
DBGA ( R6.L , 0x0007 );
DBGA ( R6.H , 0x8001 );
R7 = A0.w;
DBGA ( R7.L , 0x0003 );
DBGA ( R7.H , 0x0000 );
R7.L = A0.x;
DBGA ( R7.L , 0x0000 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,120 | sim/testsuite/bfin/load.s | # Blackfin testcase for register load instructions
# mach: bfin
.include "testutils.inc"
start
.macro load32 num:req, reg0:req, reg1:req
imm32 \reg0 \num
imm32 \reg1 \num
CC = \reg0 == \reg1
if CC jump 2f;
fail
2:
.endm
.macro load32p num:req preg:req
imm32 r0 \num
imm32 \preg \num
r1 = \preg
cc = r0 == r1
if CC jump 3f;
fail
3:
imm32 \preg 0
.endm
.macro load16z num:req reg0:req reg1:req
\reg0 = \num (Z);
imm32 \reg1 \num
CC = \reg0 == \reg1
if CC jump 4f;
fail
4:
.endm
.macro load16zp num:req reg:req
\reg = \num (Z);
imm32 r1 \num;
r0 = \reg;
cc = r0 == r1
if CC jump 5f;
fail
5:
.endm
.macro load16x num:req reg0:req reg1:req
\reg0 = \num (X);
imm32 \reg1, \num
CC = \reg0 == \reg1
if CC jump 6f;
fail
6:
.endm
/* Clobbers R0 */
.macro loadinc preg0:req, preg1:req, dreg:req
loadsym \preg0, _buf
\preg1 = \preg0;
\dreg = \preg0;
[\preg0\()++] = \preg0;
\dreg += 4;
R0 = \preg0;
CC = \dreg == R0;
if CC jump 7f;
fail
7:
R0 = [ \preg1\() ];
\dreg += -4;
CC = \dreg == R0;
if CC jump 8f;
fail
8:
.endm
/* test a bunch of values */
/* load_immediate (Half-Word Load)
* register = constant
* reg_lo = uimm16;
* reg_hi = uimm16;
*/
load32 0 R0 R1
load32 0xFFFFFFFF R0 R1
load32 0x55aaaa55 r0 r1
load32 0x12345678 r0 r1
load32 0x12345678 R0 R2
load32 0x23456789 R0 R3
load32 0x3456789a R0 R4
load32 0x456789ab R0 R5
load32 0x56789abc R0 R6
load32 0x6789abcd R0 R7
load32 0x789abcde R0 R0
load32 0x89abcdef R1 R0
load32 0x9abcdef0 R2 R0
load32 0xabcdef01 R3 R0
load32 0xbcdef012 R4 R0
load32 0xcdef0123 R5 R0
load32 0xdef01234 R6 R0
load32 0xef012345 R7 R0
load32p 0xf0123456 P0
load32p 0x01234567 P1
load32p 0x12345678 P2
.ifndef BFIN_HOST
load32p 0x23456789 P3
.endif
load32p 0x3456789a P4
load32p 0x456789ab P5
load32p 0x56789abc SP
load32p 0x6789abcd FP
load32p 0x789abcde I0
load32p 0x89abcdef I1
load32p 0x9abcdef0 I2
load32p 0xabcdef01 I3
load32p 0xbcdef012 M0
load32p 0xcdef0123 M1
load32p 0xdef01234 M2
load32p 0xef012345 M3
load32p 0xf0123456 B0
load32p 0x01234567 B1
load32p 0x12345678 B2
load32p 0x23456789 B3
load32p 0x3456789a L0
load32p 0x456789ab L1
load32p 0x56789abc L2
load32p 0x6789abcd L3
/* Zero Extended */
load16z 0x1234 R0 R1
load16z 0x2345 R0 R1
load16z 0x3456 R0 R2
load16z 0x4567 R0 R3
load16z 0x5678 R0 R4
load16z 0x6789 R0 R5
load16z 0x789a R0 R6
load16z 0x89ab R0 R7
load16z 0x9abc R1 R0
load16z 0xabcd R2 R0
load16z 0xbcde R3 R0
load16z 0xcdef R4 R0
load16z 0xdef0 R5 R0
load16z 0xef01 R6 R0
load16z 0xf012 R7 R0
load16zp 0x0123 P0
load16zp 0x1234 P1
load16zp 0x1234 p2
.ifndef BFIN_HOST
load16zp 0x2345 p3
.endif
load16zp 0x3456 p4
load16zp 0x4567 p5
load16zp 0x5678 sp
load16zp 0x6789 fp
load16zp 0x789a i0
load16zp 0x89ab i1
load16zp 0x9abc i2
load16zp 0xabcd i3
load16zp 0xbcde m0
load16zp 0xcdef m1
load16zp 0xdef0 m2
load16zp 0xef01 m3
load16zp 0xf012 b0
load16zp 0x0123 b1
load16zp 0x1234 b2
load16zp 0x2345 b3
load16zp 0x3456 l0
load16zp 0x4567 l1
load16zp 0x5678 l2
load16zp 0x6789 l3
/* Sign Extended */
load16x 0x20 R0 R1
load16x 0x3F R0 R1
load16x -0x20 R0 R1
load16x -0x3F R0 R1
load16x 0x1234 R0 R1
load16x 0x2345 R0 R1
load16x 0x3456 R0 R2
load16x 0x4567 R0 R3
load16x 0x5678 R0 R4
load16x 0x6789 R0 R5
load16x 0x789a R0 R6
load16x 0x09ab R0 R7
load16x -0x1abc R1 R0
load16x -0x2bcd R2 R0
load16x -0x3cde R3 R0
load16x -0x4def R4 R0
load16x -0x5ef0 R5 R0
load16x -0x6f01 R6 R0
load16x -0x7012 R7 R0
loadinc P0, P1, R1
loadinc P1, P2, R1
loadinc P2, P1, R2
.ifndef BFIN_HOST
loadinc P3, P4, R3
.endif
loadinc P4, P5, R4
loadinc FP, P0, R7
loadinc P0, I0, R1
loadinc P1, I1, R1
loadinc P2, I2, R1
.ifndef BFIN_HOST
loadinc P3, I0, R1
.endif
loadinc P4, I2, R1
loadinc P5, I3, R1
A1 = A0 = 0;
R0 = 0x01 (Z);
A0.x = R0;
imm32 r4, 0x32e02d1a
A1.x = R4;
A0.w = A1.x;
R3 = A0.w;
R2 = A0.x;
imm32 r0, 0x0000001a
imm32 r1, 0x00000001
CC = R1 == R2;
if CC jump 1f;
fail
1:
CC = R0 == R3
if CC jump 2f;
fail
2:
pass
.data
_buf:
.rept 0x80
.long 0
.endr
|
tactcomplabs/xbgas-binutils-gdb | 11,838 | sim/testsuite/bfin/c_ldstpmod_st_lohi.s | //Original:testcases/core/c_ldstpmod_st_lohi/c_ldstpmod_st_lohi.dsp
// Spec Reference: c_ldstpmod store dreg lo & hi
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
I0 = P3;
I2 = SP;
// initial values
imm32 r0, 0x600f5000;
imm32 r1, 0x700e6001;
imm32 r2, 0x800d7002;
imm32 r3, 0x900c8003;
imm32 r4, 0xa00b9004;
imm32 r5, 0xb00aa005;
imm32 r6, 0xc009b006;
imm32 r7, 0xd008c007;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0006;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_5, 0x00;
P3 = I1; SP = I3;
W [ P5 ++ P1 ] = R0.L;
W [ P5 ++ P1 ] = R1.L;
W [ P5 ++ P2 ] = R2.L;
W [ P5 ++ P3 ] = R3.L;
W [ P5 ++ P4 ] = R4.L;
W [ P5 ++ SP ] = R5.L;
W [ P5 ++ FP ] = R6.L;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0002;
FP = 0x0002;
SP = 0x0006;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_5, 0x00;
P3 = I1; SP = I3;
R6.L = W [ P5 ++ P1 ];
R5.L = W [ P5 ++ P1 ];
R4.L = W [ P5 ++ P2 ];
R3.L = W [ P5 ++ P3 ];
R2.L = W [ P5 ++ P4 ];
R0.L = W [ P5 ++ SP ];
R1.L = W [ P5 ++ FP ];
CHECKREG r0, 0x600FA005;
CHECKREG r1, 0x700EB006;
CHECKREG r2, 0x800D9004;
CHECKREG r3, 0x900C8003;
CHECKREG r4, 0xA00B7002;
CHECKREG r5, 0xB00A6001;
CHECKREG r6, 0xC0095000;
// initial values
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x204EA0A5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
P5 = 0x0002;
P2 = 0x0002;
P3 = 0x0004;
P4 = 0x0002;
FP = 0x0006;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
W [ P1 ++ P5 ] = R0.H;
W [ P1 ++ P2 ] = R1.H;
W [ P1 ++ P2 ] = R2.H;
W [ P1 ++ P3 ] = R3.H;
W [ P1 ++ P4 ] = R4.H;
W [ P1 ++ SP ] = R5.H;
W [ P1 ++ FP ] = R6.H;
P5 = 0x0002;
P2 = 0x0002;
P3 = 0x0004;
P4 = 0x0002;
FP = 0x0006;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
P3 = I1; SP = I3;
R6.H = W [ P1 ++ P5 ];
R5.H = W [ P1 ++ P2 ];
R4.H = W [ P1 ++ P2 ];
R3.H = W [ P1 ++ P3 ];
R2.H = W [ P1 ++ P4 ];
R0.H = W [ P1 ++ SP ];
R1.H = W [ P1 ++ FP ];
CHECKREG r0, 0x204E50A0;
CHECKREG r1, 0x701960A1;
CHECKREG r2, 0x501B70A2;
CHECKREG r3, 0x402C80A3;
CHECKREG r4, 0x300390A4;
CHECKREG r5, 0x204EA0A5;
CHECKREG r6, 0x105FB0A6;
// initial values
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
P5 = 0x0002;
P1 = 0x0002;
P3 = 0x0004;
P4 = 0x0004;
FP = 0x0006;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p2, DATA_ADDR_2, 0x02;
P3 = I1; SP = I3;
W [ P2 ++ P5 ] = R0.L;
W [ P2 ++ P1 ] = R0.H;
W [ P2 ++ P2 ] = R2.H;
W [ P2 ++ P3 ] = R2.H;
W [ P2 ++ P4 ] = R4.L;
W [ P2 ++ SP ] = R4.H;
W [ P2 ++ FP ] = R6.L;
P5 = 0x0002;
P1 = 0x0002;
P3 = 0x0002;
P4 = 0x0004;
FP = 0x0006;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p2, DATA_ADDR_2, 0x02;
P3 = I1; SP = I3;
R3.L = W [ P2 ++ P5 ];
R3.H = W [ P2 ++ P1 ];
R0.L = W [ P2 ++ P2 ];
R0.H = W [ P2 ++ P3 ];
R2.L = W [ P2 ++ P4 ];
R2.H = W [ P2 ++ SP ];
R6.L = W [ P2 ++ FP ];
CHECKREG r0, 0x30BD30BD;
CHECKREG r1, 0x20BE60B1;
CHECKREG r2, 0x2E2F2A2B;
CHECKREG r3, 0x10BF50B0;
CHECKREG r4, 0x55BB90B4;
CHECKREG r5, 0x60BAA0B5;
CHECKREG r6, 0x70B955BB;
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P4 = 0x0004;
FP = 0x0006;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_3, 0x02;
P3 = I1; SP = I3;
W [ P3 ++ P5 ] = R1.H;
W [ P3 ++ P1 ] = R1.L;
W [ P3 ++ P2 ] = R3.L;
W [ P3 ++ P2 ] = R3.H;
W [ P3 ++ P4 ] = R5.H;
W [ P3 ++ SP ] = R6.H;
W [ P3 ++ FP ] = R6.L;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P4 = 0x0004;
FP = 0x0006;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i1, DATA_ADDR_3, 0x02;
P3 = I1; SP = I3;
R6.L = W [ P3 ++ P5 ];
R6.H = W [ P3 ++ P1 ];
R4.H = W [ P3 ++ P2 ];
R4.L = W [ P3 ++ P2 ];
R5.L = W [ P3 ++ P4 ];
R5.H = W [ P3 ++ SP ];
R1.L = W [ P3 ++ FP ];
CHECKREG r0, 0x10CF50C0;
CHECKREG r1, 0x20CEB0C6;
CHECKREG r2, 0x30C370C2;
CHECKREG r3, 0x40CC80C3;
CHECKREG r4, 0x80C340CC;
CHECKREG r5, 0x70C960CA;
CHECKREG r6, 0x60C120CE;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_4, 0x02;
P3 = I1; SP = I3;
W [ P4 ++ P5 ] = R0.L;
W [ P4 ++ P1 ] = R1.H;
W [ P4 ++ P2 ] = R2.L;
W [ P4 ++ P3 ] = R3.H;
W [ P4 ++ P3 ] = R4.H;
W [ P4 ++ SP ] = R5.L;
W [ P4 ++ FP ] = R6.H;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
FP = 0x0002;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p4, DATA_ADDR_4, 0x02;
P3 = I1; SP = I3;
R5.L = W [ P4 ++ P5 ];
R6.L = W [ P4 ++ P1 ];
R0.H = W [ P4 ++ P2 ];
R1.L = W [ P4 ++ P3 ];
R2.L = W [ P4 ++ P3 ];
R3.H = W [ P4 ++ SP ];
R4.H = W [ P4 ++ FP ];
CHECKREG r0, 0x70D250D0;
CHECKREG r1, 0x70DE90DC;
CHECKREG r2, 0x80DDA0DB;
CHECKREG r3, 0xA0D580D3;
CHECKREG r4, 0xC0D990D4;
CHECKREG r5, 0xB0DA50D0;
CHECKREG r6, 0xC0D970DE;
// initial values
imm32 r0, 0x1e5f50e0;
imm32 r1, 0x2e4e60e1;
imm32 r2, 0x3e0370e2;
imm32 r3, 0x4e2c80e3;
imm32 r4, 0x5e1b90e4;
imm32 r5, 0x6e0aa0e5;
imm32 r6, 0x7e19b0e6;
imm32 r7, 0xde28c0e7;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0004;
P3 = 0x0004;
P4 = 0x0002;
FP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i3, DATA_ADDR_6, 0x02;
P3 = I1; SP = I3;
W [ SP ++ P5 ] = R0.H;
W [ SP ++ P1 ] = R1.H;
W [ SP ++ P2 ] = R2.L;
W [ SP ++ P3 ] = R3.L;
W [ SP ++ P4 ] = R4.H;
W [ SP ++ FP ] = R5.H;
W [ SP ++ FP ] = R6.L;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0004;
P3 = 0x0004;
P4 = 0x0004;
FP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym i3, DATA_ADDR_6, 0x02;
P3 = I1; SP = I3;
R6.H = W [ SP ++ P5 ];
R5.H = W [ SP ++ P1 ];
R4.H = W [ SP ++ P2 ];
R3.H = W [ SP ++ P3 ];
R3.L = W [ SP ++ P4 ];
R0.L = W [ SP ++ FP ];
R1.L = W [ SP ++ FP ];
CHECKREG r0, 0x1E5FB0E6;
CHECKREG r1, 0x2E4E1617;
CHECKREG r2, 0x3E0370E2;
CHECKREG r3, 0x80E35E1B;
CHECKREG r4, 0x70E290E4;
CHECKREG r5, 0x2E4EA0E5;
CHECKREG r6, 0x1E5FB0E6;
// initial values
imm32 r0, 0x10ff50f0;
imm32 r1, 0x20fe60f1;
imm32 r2, 0x30fd70f2;
imm32 r3, 0x40fc80f3;
imm32 r4, 0x55fb90f4;
imm32 r5, 0x60faa0f5;
imm32 r6, 0x70f9b0f6;
imm32 r7, 0x80f8c0f7;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0004;
SP = 0x0002;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_7, 0x02;
P3 = I1; SP = I3;
W [ FP ++ P5 ] = R0.L;
W [ FP ++ P1 ] = R1.H;
W [ FP ++ P2 ] = R2.H;
W [ FP ++ P3 ] = R3.H;
W [ FP ++ P4 ] = R4.L;
W [ FP ++ SP ] = R5.L;
W [ FP ++ SP ] = R6.L;
P5 = 0x0002;
P1 = 0x0002;
P2 = 0x0002;
P3 = 0x0002;
P4 = 0x0004;
SP = 0x0004;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_7, 0x02;
P3 = I1; SP = I3;
R3.L = W [ FP ++ P5 ];
R4.L = W [ FP ++ P1 ];
R0.H = W [ FP ++ P2 ];
R1.H = W [ FP ++ P3 ];
R2.L = W [ FP ++ P4 ];
R5.H = W [ FP ++ SP ];
R6.H = W [ FP ++ SP ];
CHECKREG r0, 0x30FD50F0;
CHECKREG r1, 0x40FC60F1;
CHECKREG r2, 0x30FD90F4;
CHECKREG r3, 0x40FC50F0;
CHECKREG r4, 0x55FB20FE;
CHECKREG r5, 0xA0F5A0F5;
CHECKREG r6, 0x9091B0F6;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 3,767 | sim/testsuite/bfin/c_dsp32mult_pair_m.s | //Original:/testcases/core/c_dsp32mult_pair_m/c_dsp32mult_pair_m.dsp
// Spec Reference: dsp32mult pair MUNOP
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R0 = R0.L * R0.L;
R2 = R0.L * R1.H;
R4 = R1.H * R1.H;
R6 = R0.L * R0.L;
CHECKREG r0, 0x39F9C2B2;
CHECKREG r1, 0x9F7A5127;
CHECKREG r2, 0x2E3AADA8;
CHECKREG r3, 0x00069027;
CHECKREG r4, 0x48C98C48;
CHECKREG r5, 0x10ACEF2B;
CHECKREG r6, 0x1D5C8788;
CHECKREG r7, 0xD246712F;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R0 = R2.L * R2.L;
R2 = R2.L * R3.H;
R4 = R3.H * R2.H;
R6 = R2.L * R3.L;
CHECKREG r0, 0x2965A1F2;
CHECKREG r1, 0x6FBA5137;
CHECKREG r2, 0x3FAE367C;
CHECKREG r3, 0x90060037;
CHECKREG r4, 0xC84ABC28;
CHECKREG r5, 0xB0ACEF3B;
CHECKREG r6, 0x00176948;
CHECKREG r7, 0x12467003;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0 = R4.L * R4.L;
R2 = R4.L * R5.H;
R4 = R5.H * R5.H;
R6 = R4.L * R5.L;
CHECKREG r0, 0x1B29B4A2;
CHECKREG r1, 0xC4BA5157;
CHECKREG r2, 0xF85431BE;
CHECKREG r3, 0x05060055;
CHECKREG r4, 0x022A99E2;
CHECKREG r5, 0x10A7EF5B;
CHECKREG r6, 0x0D4762AC;
CHECKREG r7, 0x1246795F;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
R0 = R6.L * R6.L;
R2 = R6.L * R7.H;
R4 = R7.H * R7.H;
R6 = R6.L * R7.L;
CHECKREG r0, 0x31781CD2;
CHECKREG r1, 0xEFBA5166;
CHECKREG r2, 0xF4A3CF9C;
CHECKREG r3, 0xF0060066;
CHECKREG r4, 0x029BD648;
CHECKREG r5, 0x10ACEF6B;
CHECKREG r6, 0xBA1A5E86;
CHECKREG r7, 0x1246706F;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0 = R0.L * R7.L;
R2 = R1.L * R6.H;
R4 = R3.H * R4.H;
R6 = R4.L * R3.L;
CHECKREG r0, 0x0B26E1B6;
CHECKREG r1, 0xCFBA5127;
CHECKREG r2, 0x00079BA8;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0xFFFAC804;
CHECKREG r5, 0x10ACDFDB;
CHECKREG r6, 0xFFFCF038;
CHECKREG r7, 0x1246F00F;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R1 = R7.H * R0.H;
R3 = R6.H * R1.H;
R5 = R5.H * R2.L;
R7 = R4.L * R3.H;
CHECKREG r0, 0xAB235A75;
CHECKREG r1, 0xF3E28324;
CHECKREG r2, 0x13246905;
CHECKREG r3, 0xFFFEDD30;
CHECKREG r4, 0x90ABCD09;
CHECKREG r5, 0x0DADBEB8;
CHECKREG r6, 0x000C0D0D;
CHECKREG r7, 0x0000CBDC;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R1 = R6.H * R4.L;
R3 = R5.L * R3.H;
R5 = R3.H * R1.L;
R7 = R1.H * R2.H;
CHECKREG r0, 0x9B235675;
CHECKREG r1, 0xFFF6B8D8;
CHECKREG r2, 0x13946705;
CHECKREG r3, 0xFFFE7166;
CHECKREG r4, 0x90AB9D09;
CHECKREG r5, 0x00011CA0;
CHECKREG r6, 0x000C009D;
CHECKREG r7, 0xFFFE7870;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R4.L * R0.H;
R3 = R6.H * R1.H;
R5 = R1.L * R2.L;
R7 = R4.H * R2.L;
CHECKREG r0, 0xEB235675;
CHECKREG r1, 0x03175676;
CHECKREG r2, 0x13E46705;
CHECKREG r3, 0x00004A28;
CHECKREG r4, 0x90ABED09;
CHECKREG r5, 0x4596549C;
CHECKREG r6, 0x000C00ED;
CHECKREG r7, 0xA66540AE;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,027 | sim/testsuite/bfin/c_dsp32shift_lhalf_lp.s | //Original:/testcases/core/c_dsp32shift_lhalf_lp/c_dsp32shift_lhalf_lp.dsp
// Spec Reference: dsp32shift lshift
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = LSHIFT R0.L BY R0.L;
R1.L = LSHIFT R1.L BY R0.L;
R2.L = LSHIFT R2.L BY R0.L;
R3.L = LSHIFT R3.L BY R0.L;
R4.L = LSHIFT R4.L BY R0.L;
R5.L = LSHIFT R5.L BY R0.L;
R6.L = LSHIFT R6.L BY R0.L;
R7.L = LSHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = LSHIFT R0.L BY R1.L;
//rl1 = lshift (rl1 by rl1);
R2.L = LSHIFT R2.L BY R1.L;
R3.L = LSHIFT R3.L BY R1.L;
R4.L = LSHIFT R4.L BY R1.L;
R5.L = LSHIFT R5.L BY R1.L;
R6.L = LSHIFT R6.L BY R1.L;
R7.L = LSHIFT R7.L BY R1.L;
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000006;
CHECKREG r4, 0x00000008;
CHECKREG r5, 0x0000000a;
CHECKREG r6, 0x0000000c;
CHECKREG r7, 0x0000000e;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000000f;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = LSHIFT R0.L BY R2.L;
R1.L = LSHIFT R1.L BY R2.L;
//rl2 = lshift (rl2 by rl2);
R3.L = LSHIFT R3.L BY R2.L;
R4.L = LSHIFT R4.L BY R2.L;
R5.L = LSHIFT R5.L BY R2.L;
R6.L = LSHIFT R6.L BY R2.L;
R7.L = LSHIFT R7.L BY R2.L;
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00008000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00008000;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000010;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.L = LSHIFT R0.L BY R3.L;
R1.L = LSHIFT R1.L BY R3.L;
R2.L = LSHIFT R2.L BY R3.L;
//rl3 = lshift (rl3 by rl3);
R4.L = LSHIFT R4.L BY R3.L;
R5.L = LSHIFT R5.L BY R3.L;
R6.L = LSHIFT R6.L BY R3.L;
R7.L = LSHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = LSHIFT R0.H BY R0.L;
R1.L = LSHIFT R1.H BY R0.L;
R2.L = LSHIFT R2.H BY R0.L;
R3.L = LSHIFT R3.H BY R0.L;
R4.L = LSHIFT R4.H BY R0.L;
R5.L = LSHIFT R5.H BY R0.L;
R6.L = LSHIFT R6.H BY R0.L;
R7.L = LSHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = LSHIFT R0.H BY R1.L;
//rl1 = lshift (rh1 by rl1);
R2.L = LSHIFT R2.H BY R1.L;
R3.L = LSHIFT R3.H BY R1.L;
R4.L = LSHIFT R4.H BY R1.L;
R5.L = LSHIFT R5.H BY R1.L;
R6.L = LSHIFT R6.H BY R1.L;
R7.L = LSHIFT R7.H BY R1.L;
CHECKREG r0, 0x00010002;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020004;
CHECKREG r3, 0x00030006;
CHECKREG r4, 0x00040008;
CHECKREG r5, 0x0005000a;
CHECKREG r6, 0x0006000c;
CHECKREG r7, 0x0007000e;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x0002000f;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = LSHIFT R0.H BY R2.L;
R1.L = LSHIFT R1.H BY R2.L;
//rl2 = lshift (rh2 by rl2);
R3.L = LSHIFT R3.H BY R2.L;
R4.L = LSHIFT R4.H BY R2.L;
R5.L = LSHIFT R5.H BY R2.L;
R6.L = LSHIFT R6.H BY R2.L;
R7.L = LSHIFT R7.H BY R2.L;
CHECKREG r0, 0x00018000;
CHECKREG r1, 0x00018000;
CHECKREG r2, 0x0002000f;
CHECKREG r3, 0x00038000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00058000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00078000;
imm32 r0, 0x00010001;
imm32 r1, 0x00010001;
imm32 r2, 0x00020002;
imm32 r3, 0x00030010;
imm32 r4, 0x00040004;
imm32 r5, 0x00050005;
imm32 r6, 0x00060006;
imm32 r7, 0x00070007;
R0.L = LSHIFT R0.H BY R3.L;
R1.L = LSHIFT R1.H BY R3.L;
R2.L = LSHIFT R2.H BY R3.L;
//rl3 = lshift (rh3 by rl3);
R4.L = LSHIFT R4.H BY R3.L;
R5.L = LSHIFT R5.H BY R3.L;
R6.L = LSHIFT R6.H BY R3.L;
R7.L = LSHIFT R7.H BY R3.L;
CHECKREG r0, 0x00010000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030010;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = LSHIFT R0.L BY R0.L;
R1.H = LSHIFT R1.L BY R0.L;
R2.H = LSHIFT R2.L BY R0.L;
R3.H = LSHIFT R3.L BY R0.L;
R4.H = LSHIFT R4.L BY R0.L;
R5.H = LSHIFT R5.L BY R0.L;
R6.H = LSHIFT R6.L BY R0.L;
R7.H = LSHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = LSHIFT R0.L BY R1.L;
R1.H = LSHIFT R1.L BY R1.L;
R2.H = LSHIFT R2.L BY R1.L;
R3.H = LSHIFT R3.L BY R1.L;
R4.H = LSHIFT R4.L BY R1.L;
R5.H = LSHIFT R5.L BY R1.L;
R6.H = LSHIFT R6.L BY R1.L;
R7.H = LSHIFT R7.L BY R1.L;
CHECKREG r0, 0x00020001;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00040002;
CHECKREG r3, 0x00060003;
CHECKREG r4, 0x00080004;
CHECKREG r5, 0x000a0005;
CHECKREG r6, 0x000c0006;
CHECKREG r7, 0x000e0007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000000f;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = LSHIFT R0.L BY R2.L;
R1.H = LSHIFT R1.L BY R2.L;
//rh2 = lshift (rl2 by rl2);
R3.H = LSHIFT R3.L BY R2.L;
R4.H = LSHIFT R4.L BY R2.L;
R5.H = LSHIFT R5.L BY R2.L;
R6.H = LSHIFT R6.L BY R2.L;
R7.H = LSHIFT R7.L BY R2.L;
CHECKREG r0, 0x80000001;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x80000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x80000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x80000007;
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000010;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = LSHIFT R0.L BY R3.L;
R1.H = LSHIFT R1.L BY R3.L;
R2.H = LSHIFT R2.L BY R3.L;
R3.H = LSHIFT R3.L BY R3.L;
R4.H = LSHIFT R4.L BY R3.L;
R5.H = LSHIFT R5.L BY R3.L;
R6.H = LSHIFT R6.L BY R3.L;
R7.H = LSHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = LSHIFT R0.H BY R0.L;
R1.H = LSHIFT R1.H BY R0.L;
R2.H = LSHIFT R2.H BY R0.L;
R3.H = LSHIFT R3.H BY R0.L;
R4.H = LSHIFT R4.H BY R0.L;
R5.H = LSHIFT R5.H BY R0.L;
R6.H = LSHIFT R6.H BY R0.L;
R7.H = LSHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = LSHIFT R0.H BY R1.L;
R1.H = LSHIFT R1.H BY R1.L;
R2.H = LSHIFT R2.H BY R1.L;
R3.H = LSHIFT R3.H BY R1.L;
R4.H = LSHIFT R4.H BY R1.L;
R5.H = LSHIFT R5.H BY R1.L;
R6.H = LSHIFT R6.H BY R1.L;
R7.H = LSHIFT R7.H BY R1.L;
CHECKREG r0, 0x00020000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00040000;
CHECKREG r3, 0x00060000;
CHECKREG r4, 0x00080000;
CHECKREG r5, 0x000a0000;
CHECKREG r6, 0x000c0000;
CHECKREG r7, 0x000e0000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x0002000f;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = LSHIFT R0.H BY R2.L;
R1.L = LSHIFT R1.H BY R2.L;
//rl2 = lshift (rh2 by rl2);
R3.L = LSHIFT R3.H BY R2.L;
R4.L = LSHIFT R4.H BY R2.L;
R5.L = LSHIFT R5.H BY R2.L;
R6.L = LSHIFT R6.H BY R2.L;
R7.L = LSHIFT R7.H BY R2.L;
CHECKREG r0, 0x00018000;
CHECKREG r1, 0x00018000;
CHECKREG r2, 0x0002000f;
CHECKREG r3, 0x00038000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00058000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00078000;
imm32 r0, 0x00010000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030010;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = LSHIFT R0.H BY R3.L;
R1.H = LSHIFT R1.H BY R3.L;
R2.H = LSHIFT R2.H BY R3.L;
R3.H = LSHIFT R3.H BY R3.L;
R4.H = LSHIFT R4.H BY R3.L;
R5.H = LSHIFT R5.H BY R3.L;
R6.H = LSHIFT R6.H BY R3.L;
R7.H = LSHIFT R7.H BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 14,115 | sim/testsuite/bfin/random_0020.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xfcdbede4;
dmm32 A1.x, 0xffffffff;
imm32 R5, 0x14c5c1c7;
imm32 R7, 0x006a5040;
R5 = (A1 += R7.L * R7.H) (M, IU);
checkreg R5, 0xfcfd2864;
checkreg A1.w, 0xfcfd2864;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x0cb08810 | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
dmm32 ASTAT, (0x6c508a90 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x0bcd165c;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x439a7ef1;
imm32 R3, 0x47670015;
imm32 R6, 0x00008000;
R3 = (A1 += R6.L * R0.L) (M, IU);
checkreg R3, 0xcc54965c;
checkreg A1.w, 0xcc54965c;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x6c508a90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 ASTAT, (0x38900480 | _VS | _AV0S | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x8000ffff;
imm32 R3, 0x0000ffff;
imm32 R6, 0xcb2cf810;
R3 = (A1 += R6.L * R1.L) (M, IU);
checkreg R3, 0xf81007f0;
checkreg A1.w, 0xf81007f0;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x38900480 | _VS | _AV0S | _AN);
dmm32 ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN);
dmm32 A1.w, 0x36491cf0;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x10771108;
imm32 R2, 0x7fb14fe2;
imm32 R7, 0x3649ffff;
R1 = (A1 = R7.L * R2.H) (M, IU);
checkreg R1, 0xffff804f;
checkreg A1.w, 0xffff804f;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x20100610 | _VS | _AC1 | _AQ | _AN);
dmm32 ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ);
dmm32 A1.w, 0xd831c3b7;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0x3a98144b;
imm32 R7, 0xd831c3b7;
R7 = (A1 -= R3.L * R3.H) (M, IU);
checkreg R7, 0xd38cb92f;
checkreg A1.w, 0xd38cb92f;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x6c304400 | _VS | _AV1S | _AC1 | _AQ);
dmm32 ASTAT, (0x3c50c810 | _VS | _AV1S | _AN | _AZ);
dmm32 A0.w, 0x13cd1c6c;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x4000e935;
imm32 R3, 0xe0b313cd;
R3.L = (A0 += R3.H * R2.L) (IU);
checkreg R3, 0xe0b3ffff;
checkreg A0.w, 0xe07e8c7b;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x3c50c810 | _VS | _V | _AV1S | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A0.w, 0x057e5874;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x1c0af520;
imm32 R6, 0x7caea317;
imm32 R7, 0x107e8ce4;
R6.L = (A0 += R7.L * R0.L) (IU);
checkreg R6, 0x7caeffff;
checkreg A0.w, 0x8c6628f4;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x6cf04090 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 A0.w, 0xdc7d7b8c;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x788e00d2;
imm32 R6, 0x03666070;
R0.L = (A0 -= R6.H * R6.H) (IU);
checkreg R0, 0x788effff;
checkreg A0.w, 0xdc71eee8;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x6cf04090 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY | _AZ);
dmm32 ASTAT, (0x4cc04c80 | _VS | _CC);
dmm32 A1.w, 0x41620ea7;
dmm32 A1.x, 0x00000057;
imm32 R1, 0xf611262c;
imm32 R3, 0x7fff7fff;
imm32 R4, 0x247ee19c;
R1 = (A1 += R4.L * R3.L) (IU);
checkreg R1, 0xffffffff;
checkreg A1.w, 0xb22f2d0b;
checkreg A1.x, 0x00000057;
checkreg ASTAT, (0x4cc04c80 | _VS | _V | _CC | _V_COPY);
dmm32 ASTAT, (0x28e04610 | _VS | _AV0S | _AC1 | _AC0 | _AN);
dmm32 A0.w, 0xe1753d16;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x7fffffff;
imm32 R5, 0x2792ffff;
imm32 R7, 0xffffd6fa;
R7.L = (A0 = R0.L * R5.L) (IU);
checkreg R7, 0xffffffff;
checkreg A0.w, 0xfffe0001;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x28e04610 | _VS | _V | _AV0S | _AC1 | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x7c900280 | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A0.w, 0x057e5874;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x1c0af520;
imm32 R6, 0x7caea317;
imm32 R7, 0x107e8ce4;
R6.L = (A0 += R7.L * R0.L) (IU);
checkreg R6, 0x7caeffff;
checkreg A0.w, 0x8c6628f4;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x7c900280 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x00304000 | _VS | _AV1S | _AQ | _AZ);
dmm32 A0.w, 0x615bac86;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x6d2cbec6;
imm32 R3, 0xe09db667;
R3.L = (A0 += R3.H * R2.H) (IU);
checkreg R3, 0xe09dffff;
checkreg A0.w, 0xc1252082;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x00304000 | _VS | _V | _AV1S | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x5cc00080 | _VS | _AV1S | _AC0 | _CC);
dmm32 A1.w, 0x70d9985a;
dmm32 A1.x, 0xffffffd6;
imm32 R1, 0x8000fdeb;
imm32 R2, 0x20e07e89;
R1.H = (A1 += R2.L * R1.L) (M, IU);
checkreg A1.w, 0xee5b251d;
checkreg A1.x, 0xffffffd6;
checkreg ASTAT, (0x5cc00080 | _VS | _V | _AV1S | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x60e0ce80 | _VS | _AC0 | _AQ | _CC);
dmm32 A1.w, 0x67798cf6;
dmm32 A1.x, 0x00000044;
imm32 R0, 0x00000000;
imm32 R1, 0x00008e16;
imm32 R7, 0x00000000;
R7 = (A1 -= R0.L * R1.L) (M, IU);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0x67798cf6;
checkreg A1.x, 0x00000044;
checkreg ASTAT, (0x60e0ce80 | _VS | _V | _AC0 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x6f47fe74;
dmm32 A1.x, 0x00000022;
imm32 R5, 0x3482aa64;
imm32 R6, 0x48320cd9;
R5.H = (A1 -= R6.L * R5.L) (M, IU);
checkreg R5, 0x7fffaa64;
checkreg A1.w, 0x66badfb0;
checkreg A1.x, 0x00000022;
checkreg ASTAT, (0x00500210 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x43fdb94f;
dmm32 A1.x, 0xffffff97;
imm32 R1, 0x80000000;
imm32 R7, 0x0f9b234b;
R1.H = (A1 += R7.L * R1.H) (M, IU);
checkreg A1.w, 0x55a3394f;
checkreg A1.x, 0xffffff97;
checkreg ASTAT, (0x60f04890 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x60f0c280 | _V | _AV1S | _AV1 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x33205f9e;
dmm32 A1.x, 0xfffffffc;
imm32 R3, 0x39e0545d;
imm32 R6, 0x0e133731;
R3 = (A1 -= R3.L * R6.H) (M, IU);
checkreg R3, 0x80000000;
checkreg A1.w, 0x2e7d06b7;
checkreg A1.x, 0xfffffffc;
checkreg ASTAT, (0x60f0c280 | _VS | _V | _AV1S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x6c300490 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x2a477a36;
dmm32 A1.x, 0xfffffff8;
imm32 R0, 0xff020000;
imm32 R5, 0x00000000;
imm32 R7, 0xffff8000;
R5.H = (A1 -= R0.L * R7.H) (M, IU);
checkreg R5, 0x80000000;
checkreg ASTAT, (0x6c300490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x1400c210 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN);
dmm32 A1.w, 0x68033dca;
dmm32 A1.x, 0xffffffff;
imm32 R1, 0x00000000;
imm32 R3, 0x00a36a42;
imm32 R7, 0x3afd7fff;
R3.H = (A1 -= R1.L * R7.H) (M, IU);
checkreg R3, 0x80006a42;
checkreg ASTAT, (0x1400c210 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x00104810 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xeb4e9a1d;
dmm32 A1.x, 0xffffff8c;
imm32 R1, 0xffffec05;
imm32 R5, 0x80000000;
imm32 R6, 0x5ffa604a;
R1.H = (A1 += R6.L * R5.H) (M, IU);
checkreg R1, 0x8000ec05;
checkreg A1.w, 0x1b739a1d;
checkreg A1.x, 0xffffff8d;
checkreg ASTAT, (0x00104810 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x48600280 | _VS | _AV1S | _AV0 | _AC1 | _CC | _AC0_COPY);
dmm32 A1.w, 0x54463e5f;
dmm32 A1.x, 0xffffff94;
imm32 R1, 0x2e0d6820;
imm32 R4, 0x37855c3d;
imm32 R6, 0x7b3ca7a0;
R6.H = (A1 += R4.L * R1.L) (M, IU);
checkreg R6, 0x8000a7a0;
checkreg A1.w, 0x79ca8dff;
checkreg A1.x, 0xffffff94;
checkreg ASTAT, (0x48600280 | _VS | _V | _AV1S | _AV0 | _AC1 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3c008480 | _VS | _AV1S | _AC1 | _AC0 | _CC);
dmm32 A0.w, 0xcdff712a;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x2f3dfc31;
imm32 R2, 0x1b1a4b4c;
imm32 R6, 0x7cbed409;
R2 = (A0 += R6.H * R0.L) (IU);
checkreg R2, 0xffffffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x3c008480 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x4ce0ce80 | _VS | _AC1 | _AC0 | _CC);
dmm32 A0.w, 0xfefe27a4;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x08270055;
imm32 R1, 0x0000ffc2;
imm32 R6, 0x5ca7213b;
R6.L = (A0 += R1.L * R0.H) (IU);
checkreg R6, 0x5ca7ffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x4ce0ce80 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x7020ca10 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY);
dmm32 A0.w, 0xec60b144;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x147e9190;
imm32 R1, 0x2b813e9e;
imm32 R4, 0xab65ffff;
R0 = (A0 += R1.L * R4.H) (IU);
checkreg R0, 0xffffffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x7020ca10 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x28e08210 | _VS | _AQ | _AN);
dmm32 A0.w, 0xe650ec98;
dmm32 A0.x, 0xffffffff;
imm32 R1, 0xcca1b6ef;
imm32 R2, 0xd762b783;
imm32 R3, 0xef34e465;
R2 = (A0 += R3.L * R1.H) (IU);
checkreg R2, 0xffffffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x28e08210 | _VS | _V | _AV0S | _AV0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x58904e00 | _VS | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A0.w, 0xb84b0e88;
dmm32 A0.x, 0xffffffff;
imm32 R0, 0x8367ffff;
imm32 R1, 0xb6a1af0a;
R1.L = (A0 += R0.H * R1.H) (IU);
checkreg R1, 0xb6a1ffff;
checkreg A0.w, 0xffffffff;
checkreg A0.x, 0xffffffff;
checkreg ASTAT, (0x58904e00 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x30900810 | _VS | _AV1S | _AC1 | _AQ | _CC);
dmm32 A1.w, 0xd0762eff;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x00000000;
imm32 R1, 0x1d9b7fff;
imm32 R3, 0xf32bf32b;
R0.H = (A1 += R1.L * R3.L) (M, IU);
checkreg R0, 0x7fff0000;
checkreg A1.w, 0x4a0abbd4;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x30900810 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0xf1008000;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0x0bb78001;
imm32 R5, 0x0be78000;
imm32 R7, 0x17cd9a40;
R3.H = (A1 += R7.L * R5.L) (M, IU);
checkreg R3, 0x80008001;
checkreg A1.w, 0xbe208000;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x74408290 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x40900490 | _VS | _AV1S);
dmm32 A1.w, 0xa9d97d12;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x4e01ffff;
imm32 R3, 0x12abdd35;
imm32 R7, 0xa9d966d6;
R7.H = (A1 += R0.L * R3.L) (M, IU);
checkreg R7, 0x800066d6;
checkreg A1.w, 0xa9d89fdd;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x40900490 | _VS | _V | _AV1S | _V_COPY);
dmm32 ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 A1.w, 0xe552d880;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0xfe6bf901;
imm32 R5, 0xfae40000;
imm32 R6, 0x3917f106;
R5.H = (A1 += R6.L * R3.H) (M, IU);
checkreg R5, 0x80000000;
checkreg A1.w, 0xd6708a02;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x20a04290 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x2050c490 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xfcd2b056;
dmm32 A1.x, 0xffffffff;
imm32 R2, 0xff36c118;
imm32 R4, 0xfffe0001;
imm32 R7, 0x7fff00f4;
R7.H = (A1 += R2.L * R4.H) (M, IU);
checkreg R7, 0x800000f4;
checkreg A1.w, 0xbdeb2e26;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x2050c490 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x391f1bbc;
dmm32 A1.x, 0x0000004d;
imm32 R3, 0xae387ec2;
imm32 R4, 0x7fff99ff;
imm32 R5, 0x46730cf4;
R5 = (A1 += R4.L * R3.H) (M, IU);
checkreg R5, 0x7fffffff;
checkreg A1.w, 0xf3b41d84;
checkreg A1.x, 0x0000004c;
checkreg ASTAT, (0x30708290 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x60d00200 | _VS | _AV1S | _CC);
dmm32 A1.w, 0x002b5780;
dmm32 A1.x, 0x00000000;
imm32 R1, 0xa07dffff;
imm32 R2, 0xf90db994;
imm32 R4, 0x46150060;
R2.H = (A1 -= R1.L * R4.L) (M, IU);
checkreg R2, 0x7fffb994;
checkreg A1.w, 0x002b57e0;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60d00200 | _VS | _V | _AV1S | _CC | _V_COPY);
dmm32 ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV1 | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x52768086;
dmm32 A1.x, 0x00000035;
imm32 R2, 0x1e89d049;
imm32 R6, 0x5312dd14;
imm32 R7, 0x02e3d1f4;
R7 = (A1 += R2.L * R6.L) (M, IU);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0x2941cb3a;
checkreg A1.x, 0x00000035;
checkreg ASTAT, (0x5c600a80 | _VS | _V | _AV1S | _AV0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 A1.w, 0x00005d96;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x00006828;
imm32 R5, 0xfffe5480;
imm32 R7, 0x40000009;
R5 = (A1 -= R1.L * R7.H) (M, IU);
checkreg R5, 0xe5f65d96;
checkreg A1.w, 0xe5f65d96;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x60908080 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x3cb08080 | _VS | _AC1 | _CC | _AC0_COPY | _AZ);
dmm32 A1.w, 0x8b063fca;
dmm32 A1.x, 0xffffffa2;
imm32 R3, 0x5f5b566b;
imm32 R4, 0x800022e6;
imm32 R5, 0x741acdad;
R3 = (A1 += R5.L * R4.L) (M, IU);
checkreg R3, 0x80000000;
checkreg A1.w, 0x842a0338;
checkreg A1.x, 0xffffffa2;
checkreg ASTAT, (0x3cb08080 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x60d08a00 | _VS | _AC0 | _AQ | _AN);
dmm32 A1.w, 0x54eebd9e;
dmm32 A1.x, 0x00000000;
imm32 R5, 0x05fa881c;
imm32 R7, 0xb0728448;
R5 = (A1 -= R7.L * R5.L) (M, IU);
checkreg R5, 0x7fffffff;
checkreg A1.w, 0x96b605be;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60d08a00 | _VS | _V | _AC0 | _AQ | _V_COPY | _AN);
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,097 | sim/testsuite/bfin/c_dsp32mult_dr_ih.s | //Original:/testcases/core/c_dsp32mult_dr_ih/c_dsp32mult_dr_ih.dsp
// Spec Reference: dsp32mult single dr ih
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IH);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IH);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IH);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IH);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IH);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IH);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IH);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IH);
CHECKREG r0, 0x1CFD1CFD;
CHECKREG r1, 0x0930F44E;
CHECKREG r2, 0xFEAD010A;
CHECKREG r3, 0x00890054;
CHECKREG r4, 0x1CFD1CFD;
CHECKREG r5, 0x1B4FDD40;
CHECKREG r6, 0x1B4FDD40;
CHECKREG r7, 0x19BA29A9;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IH);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IH);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IH);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IH);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IH);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IH);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IH);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IH);
CHECKREG r0, 0xFFF4FFF4;
CHECKREG r1, 0x00050005;
CHECKREG r2, 0xFA8FFA8F;
CHECKREG r3, 0x02300230;
CHECKREG r4, 0xFA8FFA8F;
CHECKREG r5, 0x1D48F84D;
CHECKREG r6, 0xFFF00004;
CHECKREG r7, 0xFFEAFFEA;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IH);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IH);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IH);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IH);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IH);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IH);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IH);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IH);
CHECKREG r0, 0x19A50D95;
CHECKREG r1, 0x073DFC29;
CHECKREG r2, 0xFC29FC29;
CHECKREG r3, 0x01150116;
CHECKREG r4, 0x19A50D95;
CHECKREG r5, 0xFE55FF1E;
CHECKREG r6, 0xFFF4FFE9;
CHECKREG r7, 0x00010003;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IH);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IH);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IH);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IH);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IH);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IH);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IH);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IH);
CHECKREG r0, 0x3FF203E5;
CHECKREG r1, 0xF6DEFDBF;
CHECKREG r2, 0xF6DEFDBF;
CHECKREG r3, 0x014E014E;
CHECKREG r4, 0x01240012;
CHECKREG r5, 0x00150015;
CHECKREG r6, 0x3FF203E5;
CHECKREG r7, 0x04910047;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IH);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IH);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IH);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IH);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IH);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IH);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IH);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IH);
CHECKREG r0, 0x0161FA04;
CHECKREG r1, 0xEBBA0004;
CHECKREG r2, 0xFD85FD85;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xFFD7FFD7;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFF930019;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (IH);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (IH);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (IH);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (IH);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (IH);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IH);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (IH);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (IH);
CHECKREG r0, 0xF9F10675;
CHECKREG r1, 0xFFFE0423;
CHECKREG r2, 0xFDBB06D7;
CHECKREG r3, 0xFFA314DD;
CHECKREG r4, 0x00280013;
CHECKREG r5, 0xFFDA0029;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0076FF91;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IH);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IH);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IH);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IH);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IH);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IH);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IH);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IH);
CHECKREG r0, 0x0001FFFE;
CHECKREG r1, 0xF94D00A6;
CHECKREG r2, 0x00550004;
CHECKREG r3, 0xFC8EEADF;
CHECKREG r4, 0x0000FFDB;
CHECKREG r5, 0x0038FEA0;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0xFF660004;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IH);
R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (IH);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IH);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IH);
R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IH);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IH);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IH);
R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (IH);
CHECKREG r0, 0xFF71FCD4;
CHECKREG r1, 0xFFCB0033;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xFFFD0000;
CHECKREG r4, 0xF920FECB;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000002;
CHECKREG r7, 0xFFFF0000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,441 | sim/testsuite/bfin/c_ldimmhalf_h_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_pr/c_ldimmhalf_h_pr.dsp
// Spec Reference: ldimmhalf h preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
INIT_P_REGS -1;
imm32 sp, 0xffffffff;
imm32 fp, 0xffffffff;
// test Preg
P1.H = 0x0002;
P2.H = 0x0004;
P3.H = 0x0006;
P4.H = 0x0008;
P5.H = 0x000a;
FP.H = 0x000c;
SP.H = 0x000e;
CHECKREG p1, 0x0002ffff;
CHECKREG p2, 0x0004ffff;
CHECKREG p3, 0x0006ffff;
CHECKREG p4, 0x0008ffff;
CHECKREG p5, 0x000affff;
CHECKREG fp, 0x000cffff;
CHECKREG sp, 0x000effff;
P1.H = 0x0020;
P2.H = 0x0040;
P3.H = 0x0060;
P4.H = 0x0080;
P5.H = 0x00a0;
FP.H = 0x00c0;
SP.H = 0x00e0;
CHECKREG p1, 0x0020ffff;
CHECKREG p2, 0x0040ffff;
CHECKREG p3, 0x0060ffff;
CHECKREG p4, 0x0080ffff;
CHECKREG p5, 0x00a0ffff;
CHECKREG fp, 0x00c0ffff;
CHECKREG sp, 0x00e0ffff;
P1.H = 0x0200;
P2.H = 0x0400;
P3.H = 0x0600;
P4.H = 0x0800;
P5.H = 0x0a00;
FP.H = 0x0c00;
SP.H = 0x0e00;
CHECKREG p1, 0x0200ffff;
CHECKREG p2, 0x0400ffff;
CHECKREG p3, 0x0600ffff;
CHECKREG p4, 0x0800ffff;
CHECKREG p5, 0x0a00ffff;
CHECKREG fp, 0x0c00ffff;
CHECKREG sp, 0x0e00ffff;
P1.H = 0x2000;
P2.H = 0x4000;
P3.H = 0x6000;
P4.H = 0x8000;
P5.H = 0xa000;
FP.H = 0xc000;
SP.H = 0xe000;
CHECKREG p1, 0x2000ffff;
CHECKREG p2, 0x4000ffff;
CHECKREG p3, 0x6000ffff;
CHECKREG p4, 0x8000ffff;
CHECKREG p5, 0xa000ffff;
CHECKREG fp, 0xc000ffff;
CHECKREG sp, 0xe000ffff;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,735 | sim/testsuite/bfin/c_compi2opp_pr_add_i7_n.s | //Original:/proj/frio/dv/testcases/core/c_compi2opp_pr_add_i7_n/c_compi2opp_pr_add_i7_n.dsp
// Spec Reference: compi2opp pregs += imm7 negative
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_P_REGS 0;
imm32 sp, 0x00000000;
imm32 fp, 0x00000000;
P1 += -1;
P2 += -2;
P3 += -3;
P4 += -4;
P5 += -5;
SP += -6;
FP += -7;
CHECKREG p1, 0xFFFFFFFF;
CHECKREG p2, 0xFFFFFFFE;
CHECKREG p3, 0xFFFFFFFD;
CHECKREG p4, 0xFFFFFFFC;
CHECKREG p5, 0xFFFFFFFB;
CHECKREG sp, 0xFFFFFFFA;
CHECKREG fp, 0xFFFFFFF9;
P1 += -9;
P2 += -10;
P3 += -11;
P4 += -12;
P5 += -13;
SP += -14;
FP += -15;
CHECKREG p1, 0xFFFFFFF6;
CHECKREG p2, 0xFFFFFFF4;
CHECKREG p3, 0xFFFFFFF2;
CHECKREG p4, 0xFFFFFFF0;
CHECKREG p5, 0xFFFFFFEE;
CHECKREG sp, 0xFFFFFFEC;
CHECKREG fp, 0xFFFFFFEA;
P1 += -17;
P2 += -18;
P3 += -19;
P4 += -20;
P5 += -21;
SP += -22;
FP += -23;
CHECKREG p1, 0xFFFFFFE5;
CHECKREG p2, 0xFFFFFFE2;
CHECKREG p3, 0xFFFFFFDF;
CHECKREG p4, 0xFFFFFFDC;
CHECKREG p5, 0xFFFFFFD9;
CHECKREG sp, 0xFFFFFFD6;
CHECKREG fp, 0xFFFFFFD3;
P1 += -25;
P2 += -26;
P3 += -27;
P4 += -28;
P5 += -29;
SP += -30;
FP += -31;
CHECKREG p1, 0xFFFFFFCC;
CHECKREG p2, 0xFFFFFFC8;
CHECKREG p3, 0xFFFFFFC4;
CHECKREG p4, 0xFFFFFFC0;
CHECKREG p5, 0xFFFFFFBC;
CHECKREG sp, 0xFFFFFFB8;
CHECKREG fp, 0xFFFFFFB4;
P1 += -33;
P2 += -34;
P3 += -35;
P4 += -36;
P5 += -37;
SP += -38;
FP += -39;
CHECKREG p1, 0xFFFFFFAB;
CHECKREG p2, 0xFFFFFFA6;
CHECKREG p3, 0xFFFFFFA1;
CHECKREG p4, 0xFFFFFF9C;
CHECKREG p5, 0xFFFFFF97;
CHECKREG sp, 0xFFFFFF92;
CHECKREG fp, 0xFFFFFF8D;
P1 += -41;
P2 += -42;
P3 += -43;
P4 += -44;
P5 += -45;
SP += -46;
FP += -47;
CHECKREG p1, 0xFFFFFF82;
CHECKREG p2, 0xFFFFFF7C;
CHECKREG p3, 0xFFFFFF76;
CHECKREG p4, 0xFFFFFF70;
CHECKREG p5, 0xFFFFFF6A;
CHECKREG sp, 0xFFFFFF64;
CHECKREG fp, 0xFFFFFF5E;
P1 += -49;
P2 += -50;
P3 += -51;
P4 += -52;
P5 += -53;
SP += -54;
FP += -55;
CHECKREG p1, 0xFFFFFF51;
CHECKREG p2, 0xFFFFFF4A;
CHECKREG p3, 0xFFFFFF43;
CHECKREG p4, 0xFFFFFF3C;
CHECKREG p5, 0xFFFFFF35;
CHECKREG sp, 0xFFFFFF2E;
CHECKREG fp, 0xFFFFFF27;
P1 += -57;
P2 += -58;
P3 += -59;
P4 += -60;
P5 += -61;
SP += -62;
FP += -63;
CHECKREG p1, 0xFFFFFF18;
CHECKREG p2, 0xFFFFFF10;
CHECKREG p3, 0xFFFFFF08;
CHECKREG p4, 0xFFFFFF00;
CHECKREG p5, 0xFFFFFEF8;
CHECKREG sp, 0xFFFFFEF0;
CHECKREG fp, 0xFFFFFEE8;
P1 += -64;
P2 += -64;
P3 += -64;
P4 += -64;
P5 += -64;
SP += -64;
FP += -64;
CHECKREG p1, 0xFFFFFED8;
CHECKREG p2, 0xFFFFFED0;
CHECKREG p3, 0xFFFFFEC8;
CHECKREG p4, 0xFFFFFEC0;
CHECKREG p5, 0xFFFFFEB8;
CHECKREG sp, 0xFFFFFEB0;
CHECKREG fp, 0xFFFFFEA8;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,256 | sim/testsuite/bfin/c_ccmv_cc_dr_dr.s | //Original:/testcases/core/c_ccmv_cc_dr_dr/c_ccmv_cc_dr_dr.dsp
// Spec Reference: ccmv cc dreg = dreg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0xa08d2301;
imm32 r1, 0xd0021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x60b61507;
imm32 r4, 0x50487609;
imm32 r5, 0x3005900b;
imm32 r6, 0x2a0c660d;
imm32 r7, 0xd90e108f;
IF CC R0 = R0;
IF CC R1 = R3;
IF CC R2 = R5;
IF CC R3 = R2;
CC = ! CC;
IF CC R4 = R6;
IF CC R5 = R1;
IF CC R6 = R7;
CC = ! CC;
IF CC R7 = R4;
CHECKREG r0, 0xA08D2301;
CHECKREG r1, 0xD0021053;
CHECKREG r2, 0x2F041405;
CHECKREG r3, 0x60B61507;
CHECKREG r4, 0x2A0C660D;
CHECKREG r5, 0xD0021053;
CHECKREG r6, 0xD90E108F;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0x308d2301;
imm32 r1, 0xd4023053;
imm32 r2, 0x2f041405;
imm32 r3, 0x60f61507;
imm32 r4, 0xd0487f09;
imm32 r5, 0x300b900b;
imm32 r6, 0x2a0cd60d;
imm32 r7, 0xd90e189f;
IF CC R4 = R3;
IF CC R5 = R7;
IF CC R6 = R1;
IF CC R7 = R2;
CC = ! CC;
IF CC R0 = R6;
IF CC R1 = R5;
IF CC R2 = R4;
CC = ! CC;
IF CC R3 = R0;
CHECKREG r0, 0x2A0CD60D;
CHECKREG r1, 0x300B900B;
CHECKREG r2, 0xD0487F09;
CHECKREG r3, 0x60F61507;
CHECKREG r4, 0xD0487F09;
CHECKREG r5, 0x300B900B;
CHECKREG r6, 0x2A0CD60D;
CHECKREG r7, 0xD90E189F;
imm32 r0, 0x708d2301;
imm32 r1, 0xd8021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x65b61507;
imm32 r4, 0x59487609;
imm32 r5, 0x3005900b;
imm32 r6, 0x2abc660d;
imm32 r7, 0xd90e108f;
IF CC R0 = R2;
IF CC R1 = R3;
CC = ! CC;
IF CC R2 = R5;
IF CC R3 = R7;
CC = ! CC;
IF CC R4 = R1;
IF CC R5 = R4;
IF CC R6 = R7;
IF CC R7 = R6;
CHECKREG r0, 0x708D2301;
CHECKREG r1, 0xD8021053;
CHECKREG r2, 0x3005900B;
CHECKREG r3, 0xD90E108F;
CHECKREG r4, 0x59487609;
CHECKREG r5, 0x3005900B;
CHECKREG r6, 0x2ABC660D;
CHECKREG r7, 0xD90E108F;
imm32 r0, 0xc08d2301;
imm32 r1, 0xdb021053;
imm32 r2, 0x2f041405;
imm32 r3, 0x64b61507;
imm32 r4, 0x50487609;
imm32 r5, 0x30f5900b;
imm32 r6, 0x2a4c660d;
imm32 r7, 0x895e108f;
IF CC R4 = R3;
IF CC R5 = R7;
CC = ! CC;
IF CC R6 = R2;
IF CC R7 = R6;
CC = ! CC;
IF CC R0 = R1;
IF CC R1 = R2;
IF CC R2 = R0;
IF CC R3 = R4;
CHECKREG r0, 0xC08D2301;
CHECKREG r1, 0xDB021053;
CHECKREG r2, 0x2F041405;
CHECKREG r3, 0x64B61507;
CHECKREG r4, 0x50487609;
CHECKREG r5, 0x30F5900B;
CHECKREG r6, 0x2F041405;
CHECKREG r7, 0x2F041405;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,719 | sim/testsuite/bfin/c_dsp32mac_dr_a1_i.s | //Original:/testcases/core/c_dsp32mac_dr_a1_i/c_dsp32mac_dr_a1_i.dsp
// Spec Reference: dsp32mac dr a1 i (signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (IS);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (IS);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (IS);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x7FFF8679;
CHECKREG r3, 0x16C676D6;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xFAEA0D14;
CHECKREG r6, 0x7FFF800D;
CHECKREG r7, 0x010DDAA8;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xFFFF8000;
imm32 r6, 0x7FFF800D;
imm32 r7, 0x00007FFF;
R0.H = ( A1 = R1.L * R0.L ) (IS);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (IS);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (IS);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (IS);
R7 = A1.w;
CHECKREG r0, 0x7FFF8ABD;
CHECKREG r1, 0x008F5EEB;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0xE58B95C1;
CHECKREG r4, 0x7FFF4569;
CHECKREG r5, 0x18220000;
CHECKREG r6, 0x0000800D;
CHECKREG r7, 0x00000000;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 = R1.L * R0.L (IS);
R1 = A1.w;
R2.H = A1 , A0 = R2.H * R3.L (IS);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (IS);
R5 = A1.w;
R6.H = A1 , A0 += R6.L * R7.H (IS);
R7 = A1.w;
CHECKREG r0, 0x0000BABD;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x0000E679;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00004569;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x0000300D;
CHECKREG r7, 0x00000000;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS);
R3 = A0.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (IS);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS);
R7 = A0.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x7FFF5679;
CHECKREG r3, 0x000317FC;
CHECKREG r4, 0x7FFF4569;
CHECKREG r5, 0x030D72D5;
CHECKREG r6, 0x8000A00D;
CHECKREG r7, 0xE78B9C22;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x921c080b;
imm32 r6, 0x7901908d;
imm32 r7, 0x679e9008;
R0.H = ( A1 += R1.L * R0.L ) (M,IS);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ) (M,IS);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ) (M,IS);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M,IS);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xE5B26993;
CHECKREG r2, 0x7FFF5679;
CHECKREG r3, 0x0977EFC8;
CHECKREG r4, 0x7FFF8569;
CHECKREG r5, 0x0885038C;
CHECKREG r6, 0x7FFF908D;
CHECKREG r7, 0x30FA159E;
imm32 r0, 0x03545abd;
imm32 r1, 0x1dbcfec7;
imm32 r2, 0x21248679;
imm32 r3, 0x30069007;
imm32 r4, 0x4fbc4569;
imm32 r5, 0x5d35500b;
imm32 r6, 0x600c800d;
imm32 r7, 0x778e900f;
R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (IS);
R1 = A1.w;
R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (IS);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IS);
R7 = A1.w;
CHECKREG r0, 0x7FFF5ABD;
CHECKREG r1, 0x316906B3;
CHECKREG r2, 0x80008679;
CHECKREG r3, 0xE933D6D6;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xD045A9C2;
CHECKREG r6, 0x8000800D;
CHECKREG r7, 0xA36ACF1A;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63540abd;
imm32 r1, 0x7dbc1ec7;
imm32 r2, 0xa1242679;
imm32 r3, 0x40063007;
imm32 r4, 0x1fbc4569;
imm32 r5, 0x2FFF4000;
imm32 r6, 0x7FFF800D;
imm32 r7, 0x10007FFF;
R0.H = ( A1 -= R1.L * R0.L ) (IS);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (IS);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (IS);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (IS);
R7 = A1.w;
CHECKREG r0, 0x80000ABD;
CHECKREG r1, 0xA220502F;
CHECKREG r2, 0x80002679;
CHECKREG r3, 0x98812959;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0x90922959;
CHECKREG r6, 0x8000800D;
CHECKREG r7, 0x88923959;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x2354babd;
imm32 r1, 0x3dbcdec7;
imm32 r2, 0x7424e679;
imm32 r3, 0x80067007;
imm32 r4, 0x95bc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb06c300d;
imm32 r7, 0xc787a00f;
R0.H = A1 , A0 -= R1.L * R0.L (IS);
R1 = A1.w;
R2.H = A1 , A0 -= R2.H * R3.L (IS);
R3 = A1.w;
R4.H = A1 , A0 -= R4.H * R5.H (IS);
R5 = A1.w;
R6.H = A1 , A0 -= R6.L * R7.H (IS);
R7 = A1.w;
CHECKREG r0, 0x8000BABD;
CHECKREG r1, 0x88923959;
CHECKREG r2, 0x8000E679;
CHECKREG r3, 0x88923959;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0x88923959;
CHECKREG r6, 0x8000300D;
CHECKREG r7, 0x88923959;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (IS);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IS);
R3 = A0.w;
R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IS);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M), A0 += R6.L * R7.H (IS);
R7 = A0.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0x89012A6E;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0x000317FC;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0x2B3160AC;
CHECKREG r6, 0x8000A00D;
CHECKREG r7, 0xCAD78046;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x83545abd;
imm32 r1, 0xa8bcfec7;
imm32 r2, 0xc1845679;
imm32 r3, 0x1c080007;
imm32 r4, 0xe1cc8569;
imm32 r5, 0x921c080b;
imm32 r6, 0x7901908d;
imm32 r7, 0x679e9008;
R0.H = ( A1 -= R1.L * R0.L ) (M,IS);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M,IS);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,IS);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,IS);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0x457EF719;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0x3C070751;
CHECKREG r4, 0x80008569;
CHECKREG r5, 0x3CF9F38D;
CHECKREG r6, 0x8000908D;
CHECKREG r7, 0x0BFFDDEF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,741 | sim/testsuite/bfin/se_event_quad.S | //Original:/proj/frio/dv/testcases/seq/se_event_quad/se_event_quad.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
P0 = 0x5 (Z);
P1 = 0xa (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
R0 = 0xf0f0 (Z);
R0.H = 0x0f0f;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 6,169 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_xb.s | //Original:testcases/core/c_ldst_ld_d_p_pp_xb/c_ldst_ld_d_p_pp_xb.dsp
// Spec Reference: c_ldst ld d [p++] xb
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x04;
loadsym p1, DATA_ADDR_2, 0x04;
loadsym p2, DATA_ADDR_3, 0x04;
loadsym i1, DATA_ADDR_4, 0x04;
loadsym p4, DATA_ADDR_5, 0x04;
loadsym fp, DATA_ADDR_6, 0x04;
loadsym i3, DATA_ADDR_7, 0x04;
P3 = I1; SP = I3;
R4 = B [ P5 ++ ] (X);
R5 = B [ P1 ++ ] (X);
R6 = B [ P2 ++ ] (X);
R7 = B [ P3 ++ ] (X);
R0 = B [ P4 ++ ] (X);
R1 = B [ FP ++ ] (X);
R2 = B [ SP ++ ] (X);
CHECKREG r0, 0xFFFFFF87;
CHECKREG r1, 0x00000007;
CHECKREG r2, 0xFFFFFF87;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000027;
CHECKREG r6, 0x00000047;
CHECKREG r7, 0x00000067;
R5 = B [ P5 ++ ] (X);
R6 = B [ P1 ++ ] (X);
R7 = B [ P2 ++ ] (X);
R0 = B [ P3 ++ ] (X);
R1 = B [ P4 ++ ] (X);
R2 = B [ FP ++ ] (X);
R3 = B [ SP ++ ] (X);
CHECKREG r0, 0x00000066;
CHECKREG r1, 0xFFFFFF86;
CHECKREG r2, 0x00000006;
CHECKREG r3, 0xFFFFFF86;
CHECKREG r4, 0x00000007;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000026;
CHECKREG r7, 0x00000046;
R6 = B [ P5 ++ ] (X);
R7 = B [ P1 ++ ] (X);
R0 = B [ P2 ++ ] (X);
R1 = B [ P3 ++ ] (X);
R2 = B [ P4 ++ ] (X);
R3 = B [ FP ++ ] (X);
R4 = B [ SP ++ ] (X);
CHECKREG r0, 0x00000045;
CHECKREG r1, 0x00000065;
CHECKREG r2, 0xFFFFFF85;
CHECKREG r3, 0x00000005;
CHECKREG r4, 0xFFFFFF85;
CHECKREG r5, 0x00000006;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000025;
R7 = B [ P5 ++ ] (X);
R0 = B [ P1 ++ ] (X);
R1 = B [ P2 ++ ] (X);
R2 = B [ P3 ++ ] (X);
R3 = B [ P4 ++ ] (X);
R4 = B [ FP ++ ] (X);
R5 = B [ SP ++ ] (X);
CHECKREG r0, 0x00000024;
CHECKREG r1, 0x00000044;
CHECKREG r2, 0x00000064;
CHECKREG r3, 0xFFFFFF84;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0xFFFFFF84;
CHECKREG r6, 0x00000005;
CHECKREG r7, 0x00000004;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 5,236 | sim/testsuite/bfin/c_regmv_imlb_pr.s | //Original:/proj/frio/dv/testcases/core/c_regmv_imlb_pr/c_regmv_imlb_pr.dsp
// Spec Reference: regmv imlb to dr
# mach: bfin
.include "testutils.inc"
start
// initialize source regs
imm32 i0, 0x11111111;
imm32 i1, 0x22222222;
imm32 i2, 0x33333333;
imm32 i3, 0x44444444;
// i to preg
R0 = I0;
P1 = I0;
P2 = I0;
P3 = I0;
P4 = I1;
P5 = I1;
SP = I1;
FP = I1;
CHECKREG r0, 0x11111111;
CHECKREG p1, 0x11111111;
CHECKREG p2, 0x11111111;
CHECKREG p3, 0x11111111;
CHECKREG p4, 0x22222222;
CHECKREG p5, 0x22222222;
CHECKREG sp, 0x22222222;
CHECKREG fp, 0x22222222;
R0 = I1;
P1 = I1;
P2 = I1;
P3 = I1;
P4 = I0;
P5 = I0;
SP = I0;
FP = I0;
CHECKREG r0, 0x22222222;
CHECKREG p1, 0x22222222;
CHECKREG p2, 0x22222222;
CHECKREG p3, 0x22222222;
CHECKREG p4, 0x11111111;
CHECKREG p5, 0x11111111;
CHECKREG sp, 0x11111111;
CHECKREG fp, 0x11111111;
R0 = I2;
P1 = I2;
P2 = I2;
P3 = I2;
P4 = I3;
P5 = I3;
SP = I3;
FP = I3;
CHECKREG r0, 0x33333333;
CHECKREG p1, 0x33333333;
CHECKREG p2, 0x33333333;
CHECKREG p3, 0x33333333;
CHECKREG p4, 0x44444444;
CHECKREG p5, 0x44444444;
CHECKREG sp, 0x44444444;
CHECKREG fp, 0x44444444;
R0 = I3;
P1 = I3;
P2 = I3;
P3 = I3;
P4 = I2;
P5 = I2;
SP = I2;
FP = I2;
CHECKREG r0, 0x44444444;
CHECKREG p1, 0x44444444;
CHECKREG p2, 0x44444444;
CHECKREG p3, 0x44444444;
CHECKREG p4, 0x33333333;
CHECKREG p5, 0x33333333;
CHECKREG sp, 0x33333333;
CHECKREG fp, 0x33333333;
imm32 m0, 0x55555555;
imm32 m1, 0x66666666;
imm32 m2, 0x77777777;
imm32 m3, 0x88888888;
// m to preg
R0 = M0;
P1 = M0;
P2 = M0;
P3 = M0;
P4 = M1;
P5 = M1;
SP = M1;
FP = M1;
CHECKREG r0, 0x55555555;
CHECKREG p1, 0x55555555;
CHECKREG p2, 0x55555555;
CHECKREG p3, 0x55555555;
CHECKREG p4, 0x66666666;
CHECKREG p5, 0x66666666;
CHECKREG sp, 0x66666666;
CHECKREG fp, 0x66666666;
R0 = M1;
P1 = M1;
P2 = M1;
P3 = M1;
P4 = M0;
P5 = M0;
SP = M0;
FP = M0;
CHECKREG r0, 0x66666666;
CHECKREG p1, 0x66666666;
CHECKREG p2, 0x66666666;
CHECKREG p3, 0x66666666;
CHECKREG p4, 0x55555555;
CHECKREG p5, 0x55555555;
CHECKREG sp, 0x55555555;
CHECKREG fp, 0x55555555;
R0 = M2;
P1 = M2;
P2 = M2;
P3 = M2;
P4 = M3;
P5 = M3;
SP = M3;
FP = M3;
CHECKREG r0, 0x77777777;
CHECKREG p1, 0x77777777;
CHECKREG p2, 0x77777777;
CHECKREG p3, 0x77777777;
CHECKREG p4, 0x88888888;
CHECKREG p5, 0x88888888;
CHECKREG sp, 0x88888888;
CHECKREG fp, 0x88888888;
R0 = M3;
P1 = M3;
P2 = M3;
P3 = M3;
P4 = M2;
P5 = M2;
SP = M2;
FP = M2;
CHECKREG r0, 0x88888888;
CHECKREG p1, 0x88888888;
CHECKREG p2, 0x88888888;
CHECKREG p3, 0x88888888;
CHECKREG p4, 0x77777777;
CHECKREG p5, 0x77777777;
CHECKREG sp, 0x77777777;
CHECKREG fp, 0x77777777;
imm32 l0, 0x99999999;
imm32 l1, 0xaaaaaaaa;
imm32 l2, 0xbbbbbbbb;
imm32 l3, 0xcccccccc;
// l to preg
R0 = L0;
P1 = L0;
P2 = L0;
P3 = L0;
P4 = L1;
P5 = L1;
SP = L1;
FP = L1;
CHECKREG r0, 0x99999999;
CHECKREG p1, 0x99999999;
CHECKREG p2, 0x99999999;
CHECKREG p3, 0x99999999;
CHECKREG p4, 0xaaaaaaaa;
CHECKREG p5, 0xaaaaaaaa;
CHECKREG sp, 0xaaaaaaaa;
CHECKREG fp, 0xaaaaaaaa;
R0 = L1;
P1 = L1;
P2 = L1;
P3 = L1;
P4 = L0;
P5 = L0;
SP = L0;
FP = L0;
CHECKREG r0, 0xaaaaaaaa;
CHECKREG p1, 0xaaaaaaaa;
CHECKREG p2, 0xaaaaaaaa;
CHECKREG p3, 0xaaaaaaaa;
CHECKREG p4, 0x99999999;
CHECKREG p5, 0x99999999;
CHECKREG sp, 0x99999999;
CHECKREG fp, 0x99999999;
R0 = L2;
P1 = L2;
P2 = L2;
P3 = L2;
P4 = L3;
P5 = L3;
SP = L3;
FP = L3;
CHECKREG r0, 0xbbbbbbbb;
CHECKREG p1, 0xbbbbbbbb;
CHECKREG p2, 0xbbbbbbbb;
CHECKREG p3, 0xbbbbbbbb;
CHECKREG p4, 0xcccccccc;
CHECKREG p5, 0xcccccccc;
CHECKREG sp, 0xcccccccc;
CHECKREG fp, 0xcccccccc;
R0 = L3;
P1 = L3;
P2 = L3;
P3 = L3;
P4 = L2;
P5 = L2;
SP = L2;
FP = L2;
CHECKREG r0, 0xcccccccc;
CHECKREG p1, 0xcccccccc;
CHECKREG p2, 0xcccccccc;
CHECKREG p3, 0xcccccccc;
CHECKREG p4, 0xbbbbbbbb;
CHECKREG p5, 0xbbbbbbbb;
CHECKREG sp, 0xbbbbbbbb;
CHECKREG fp, 0xbbbbbbbb;
imm32 b0, 0xdddddddd;
imm32 b1, 0xeeeeeeee;
imm32 b2, 0xffffffff;
imm32 b3, 0x12345678;
// b to preg
R0 = B0;
P1 = B0;
P2 = B0;
P3 = B0;
P4 = B1;
P5 = B1;
SP = B1;
FP = B1;
CHECKREG r0, 0xdddddddd;
CHECKREG p1, 0xdddddddd;
CHECKREG p2, 0xdddddddd;
CHECKREG p3, 0xdddddddd;
CHECKREG p4, 0xeeeeeeee;
CHECKREG p5, 0xeeeeeeee;
CHECKREG sp, 0xeeeeeeee;
CHECKREG fp, 0xeeeeeeee;
R0 = B1;
P1 = B1;
P2 = B1;
P3 = B1;
P4 = B0;
P5 = B0;
SP = B0;
FP = B0;
CHECKREG r0, 0xeeeeeeee;
CHECKREG p1, 0xeeeeeeee;
CHECKREG p2, 0xeeeeeeee;
CHECKREG p3, 0xeeeeeeee;
CHECKREG p4, 0xdddddddd;
CHECKREG p5, 0xdddddddd;
CHECKREG sp, 0xdddddddd;
CHECKREG fp, 0xdddddddd;
R0 = B2;
P1 = B2;
P2 = B2;
P3 = B2;
P4 = B3;
P5 = B3;
SP = B3;
FP = B3;
CHECKREG r0, 0xffffffff;
CHECKREG p1, 0xffffffff;
CHECKREG p2, 0xffffffff;
CHECKREG p3, 0xffffffff;
CHECKREG p4, 0x12345678;
CHECKREG p5, 0x12345678;
CHECKREG sp, 0x12345678;
CHECKREG fp, 0x12345678;
R0 = B3;
P1 = B3;
P2 = B3;
P3 = B3;
P4 = B2;
P5 = B2;
SP = B2;
FP = B2;
CHECKREG r0, 0x12345678;
CHECKREG p1, 0x12345678;
CHECKREG p2, 0x12345678;
CHECKREG p3, 0x12345678;
CHECKREG p4, 0xffffffff;
CHECKREG p5, 0xffffffff;
CHECKREG sp, 0xffffffff;
CHECKREG fp, 0xffffffff;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,095 | sim/testsuite/bfin/c_dsp32shift_lhh.s | //Original:/testcases/core/c_dsp32shift_lhh/c_dsp32shift_lhh.dsp
// Spec Reference: dsp32shift lshift/lshift
# mach: bfin
.include "testutils.inc"
start
// lshift/lshift : = (half reg)
// d_reg = lshift/lshift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1 = LSHIFT R0 BY R0.L (V);
R2 = LSHIFT R1 BY R0.L (V);
R3 = LSHIFT R2 BY R0.L (V);
R4 = LSHIFT R3 BY R0.L (V);
R5 = LSHIFT R4 BY R0.L (V);
R6 = LSHIFT R5 BY R0.L (V);
R7 = LSHIFT R6 BY R0.L (V);
R0 = LSHIFT R7 BY R0.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 5;
R2 = LSHIFT R0 BY R1.L (V);
R3 = LSHIFT R1 BY R1.L (V);
R4 = LSHIFT R2 BY R1.L (V);
R5 = LSHIFT R3 BY R1.L (V);
R6 = LSHIFT R4 BY R1.L (V);
R7 = LSHIFT R5 BY R1.L (V);
R0 = LSHIFT R6 BY R1.L (V);
R1 = LSHIFT R7 BY R1.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2 = 15;
R3 = LSHIFT R0 BY R2.L (V);
R4 = LSHIFT R1 BY R2.L (V);
R5 = LSHIFT R2 BY R2.L (V);
R6 = LSHIFT R3 BY R2.L (V);
R7 = LSHIFT R4 BY R2.L (V);
R0 = LSHIFT R5 BY R2.L (V);
R1 = LSHIFT R6 BY R2.L (V);
R2 = LSHIFT R7 BY R2.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R4 = LSHIFT R0 BY R3.L (V);
R5 = LSHIFT R1 BY R3.L (V);
R6 = LSHIFT R2 BY R3.L (V);
R7 = LSHIFT R3 BY R3.L (V);
R0 = LSHIFT R4 BY R3.L (V);
R1 = LSHIFT R5 BY R3.L (V);
R2 = LSHIFT R6 BY R3.L (V);
R3 = LSHIFT R7 BY R3.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R0 = LSHIFT R0 BY R4.L (V);
R1 = LSHIFT R1 BY R4.L (V);
R2 = LSHIFT R2 BY R4.L (V);
R3 = LSHIFT R3 BY R4.L (V);
R4 = LSHIFT R4 BY R4.L (V);
R5 = LSHIFT R5 BY R4.L (V);
R6 = LSHIFT R6 BY R4.L (V);
R7 = LSHIFT R7 BY R4.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -6;
R6 = LSHIFT R0 BY R5.L (V);
R7 = LSHIFT R1 BY R5.L (V);
R0 = LSHIFT R2 BY R5.L (V);
R1 = LSHIFT R3 BY R5.L (V);
R2 = LSHIFT R4 BY R5.L (V);
R3 = LSHIFT R5 BY R5.L (V);
R4 = LSHIFT R6 BY R5.L (V);
R5 = LSHIFT R7 BY R5.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R7 = LSHIFT R0 BY R6.L (V);
R0 = LSHIFT R1 BY R6.L (V);
R1 = LSHIFT R2 BY R6.L (V);
R2 = LSHIFT R3 BY R6.L (V);
R3 = LSHIFT R4 BY R6.L (V);
R4 = LSHIFT R5 BY R6.L (V);
R5 = LSHIFT R6 BY R6.L (V);
R6 = LSHIFT R7 BY R6.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L (V);
R1 = LSHIFT R1 BY R7.L (V);
R2 = LSHIFT R2 BY R7.L (V);
R3 = LSHIFT R3 BY R7.L (V);
R4 = LSHIFT R4 BY R7.L (V);
R5 = LSHIFT R5 BY R7.L (V);
R6 = LSHIFT R6 BY R7.L (V);
R7 = LSHIFT R7 BY R7.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0.L = 4;
//r0 = lshift/lshift (r0 by rl0);
R1 = LSHIFT R1 BY R0.L (V);
R2 = LSHIFT R2 BY R0.L (V);
R3 = LSHIFT R3 BY R0.L (V);
R4 = LSHIFT R4 BY R0.L (V);
R5 = LSHIFT R5 BY R0.L (V);
R6 = LSHIFT R6 BY R0.L (V);
R7 = LSHIFT R7 BY R0.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 6;
R0 = LSHIFT R0 BY R1.L (V);
//r1 = lshift/lshift (r1 by rl1);
R2 = LSHIFT R2 BY R1.L (V);
R3 = LSHIFT R3 BY R1.L (V);
R4 = LSHIFT R4 BY R1.L (V);
R5 = LSHIFT R5 BY R1.L (V);
R6 = LSHIFT R6 BY R1.L (V);
R7 = LSHIFT R7 BY R1.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 15;
R0 = LSHIFT R0 BY R2.L (V);
R1 = LSHIFT R1 BY R2.L (V);
//r2 = lshift/lshift (r2 by rl2);
R3 = LSHIFT R3 BY R2.L (V);
R4 = LSHIFT R4 BY R2.L (V);
R5 = LSHIFT R5 BY R2.L (V);
R6 = LSHIFT R6 BY R2.L (V);
R7 = LSHIFT R7 BY R2.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R0 = LSHIFT R0 BY R3.L (V);
R1 = LSHIFT R1 BY R3.L (V);
R2 = LSHIFT R2 BY R3.L (V);
//r3 = lshift/lshift (r3 by rl3);
R4 = LSHIFT R4 BY R3.L (V);
R5 = LSHIFT R5 BY R3.L (V);
R6 = LSHIFT R6 BY R3.L (V);
R7 = LSHIFT R7 BY R3.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -9;
R0 = LSHIFT R0 BY R4.L (V);
R1 = LSHIFT R1 BY R4.L (V);
R2 = LSHIFT R2 BY R4.L (V);
R3 = LSHIFT R3 BY R4.L (V);
//r4 = lshift/lshift (r4 by rl4);
R5 = LSHIFT R5 BY R4.L (V);
R6 = LSHIFT R6 BY R4.L (V);
R7 = LSHIFT R7 BY R4.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -14;
R0 = LSHIFT R0 BY R5.L (V);
R1 = LSHIFT R1 BY R5.L (V);
R2 = LSHIFT R2 BY R5.L (V);
R3 = LSHIFT R3 BY R5.L (V);
R4 = LSHIFT R4 BY R5.L (V);
//r5 = lshift/lshift (r5 by rl5);
R6 = LSHIFT R6 BY R5.L (V);
R7 = LSHIFT R7 BY R5.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R0 = LSHIFT R0 BY R6.L (V);
R1 = LSHIFT R1 BY R6.L (V);
R2 = LSHIFT R2 BY R6.L (V);
R3 = LSHIFT R3 BY R6.L (V);
R4 = LSHIFT R4 BY R6.L (V);
R5 = LSHIFT R5 BY R6.L (V);
//r6 = lshift/lshift (r6 by rl6);
R7 = LSHIFT R7 BY R6.L (V);
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = LSHIFT R0 BY R7.L (V);
R1 = LSHIFT R1 BY R7.L (V);
R2 = LSHIFT R2 BY R7.L (V);
R3 = LSHIFT R3 BY R7.L (V);
R4 = LSHIFT R4 BY R7.L (V);
R5 = LSHIFT R5 BY R7.L (V);
R6 = LSHIFT R6 BY R7.L (V);
R7 = LSHIFT R7 BY R7.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,036 | sim/testsuite/bfin/c_dsp32mult_dr_m_s.s | //Original:/testcases/core/c_dsp32mult_dr_m_s/c_dsp32mult_dr_m_s.dsp
// Spec Reference: dsp32mult single dr munop s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm32 r7, 0xd24f702f;
R4.L = R0.H * R0.L (S2RND);
R5.H = R0.L * R1.L (S2RND);
R6.L = R1.L * R0.H (S2RND);
R7.L = R1.L * R1.L (S2RND);
R0.H = R0.L * R0.L (S2RND);
R1.L = R0.L * R1.L (S2RND);
R2.L = R1.H * R0.L (S2RND);
R3.H = R1.L * R1.L (S2RND);
CHECKREG r0, 0x73F45625;
CHECKREG r1, 0x9FBA6D3B;
CHECKREG r2, 0xA3FF8000;
CHECKREG r3, 0x7FFFF027;
CHECKREG r4, 0xB0ABF974;
CHECKREG r5, 0x6D3BEF2B;
CHECKREG r6, 0xC0FCF9D5;
CHECKREG r7, 0xD24F66E7;
imm32 r0, 0xeb23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b7e5;
imm32 r3, 0x9e060037;
imm32 r4, 0x80ebcd39;
imm32 r5, 0xb0aeef3b;
imm32 r6, 0xa00ce03d;
imm32 r7, 0x12467e03;
R4.H = R2.L * R2.L (S2RND);
R5.L = R2.L * R3.H (S2RND);
R6.L = R3.H * R2.L (S2RND);
R7.H = R3.L * R3.L (S2RND);
R2.H = R2.L * R2.H (S2RND);
R3.L = R2.H * R3.H (S2RND);
R0.H = R3.L * R2.L (S2RND);
R1.L = R3.L * R3.L (S2RND);
CHECKREG r0, 0xDACEA635;
CHECKREG r1, 0x6FBA1108;
CHECKREG r2, 0xEA6FB7E5;
CHECKREG r3, 0x9E062104;
CHECKREG r4, 0x513DCD39;
CHECKREG r5, 0xB0AE6E63;
CHECKREG r6, 0xA00C6E63;
CHECKREG r7, 0x00007E03;
imm32 r0, 0xdd235655;
imm32 r1, 0xc4dd5157;
imm32 r2, 0x6324d755;
imm32 r3, 0x00060055;
imm32 r4, 0x90dbc509;
imm32 r5, 0x10adef5b;
imm32 r6, 0xb00cd05d;
imm32 r7, 0x12467d5f;
R0.L = R4.L * R4.H (S2RND);
R1.H = R4.H * R5.L (S2RND);
R2.L = R5.H * R4.L (S2RND);
R3.L = R5.L * R5.L (S2RND);
R4.H = R4.L * R4.H (S2RND);
R5.L = R4.L * R5.H (S2RND);
R6.H = R5.H * R4.H (S2RND);
R7.L = R5.H * R5.H (S2RND);
CHECKREG r0, 0xDD236666;
CHECKREG r1, 0x1CE85157;
CHECKREG r2, 0x6324F0A3;
CHECKREG r3, 0x00060454;
CHECKREG r4, 0x6666C509;
CHECKREG r5, 0x10ADF0A3;
CHECKREG r6, 0x1AAED05D;
CHECKREG r7, 0x12460458;
imm32 r0, 0xcb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x1c248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90cb9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cc06d;
imm32 r7, 0x12467c6f;
// test the unsigned U=1
R0.L = R6.L * R6.L (S2RND);
R1.H = R6.H * R7.L (S2RND);
R2.L = R7.L * R6.L (S2RND);
R3.L = R7.L * R7.L (S2RND);
R6.L = R6.L * R6.L (S2RND);
R7.L = R6.L * R7.L (S2RND);
R4.L = R7.L * R6.L (S2RND);
R5.L = R7.L * R7.L (S2RND);
CHECKREG r0, 0xCB233F27;
CHECKREG r1, 0x80005166;
CHECKREG r2, 0x1C248465;
CHECKREG r3, 0xF0067FFF;
CHECKREG r4, 0x90CB7929;
CHECKREG r5, 0x10AC7FFF;
CHECKREG r6, 0x800C3F27;
CHECKREG r7, 0x12467AC9;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0xe0060007;
imm32 r4, 0x9eabcd09;
imm32 r5, 0x10ecdfdb;
imm32 r6, 0x000e000d;
imm32 r7, 0x1246e00f;
R0.H = R0.L * R7.H (S2RND);
R1.L = R1.H * R6.H (S2RND);
R2.L = R2.L * R5.L (S2RND);
R3.H = R3.H * R4.H (S2RND);
R4.L = R4.L * R3.H (S2RND);
R5.L = R5.H * R2.H (S2RND);
R6.H = R6.H * R1.L (S2RND);
R7.L = R7.L * R0.H (S2RND);
CHECKREG r0, 0xE66FA675;
CHECKREG r1, 0xCFBAFFF5;
CHECKREG r2, 0x1324CC42;
CHECKREG r3, 0x30A10007;
CHECKREG r4, 0x9EABD947;
CHECKREG r5, 0x10EC0510;
CHECKREG r6, 0x0000000D;
CHECKREG r7, 0x12460CC3;
imm32 r0, 0x9b235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x93246905;
imm32 r3, 0x09060007;
imm32 r4, 0x909bcd09;
imm32 r5, 0x10a9e9db;
imm32 r6, 0x000c9d0d;
imm32 r7, 0x1246790f;
R0.L = R7.L * R0.H (S2RND);
R1.L = R6.L * R1.L (S2RND);
R2.H = R5.L * R2.L (S2RND);
R3.L = R4.H * R3.L (S2RND);
R4.L = R3.H * R4.H (S2RND);
R5.H = R2.H * R5.L (S2RND);
R6.L = R1.H * R6.L (S2RND);
R7.L = R0.L * R7.L (S2RND);
CHECKREG r0, 0x9B238000;
CHECKREG r1, 0xCFBA8288;
CHECKREG r2, 0xDBAA6905;
CHECKREG r3, 0x0906FFF4;
CHECKREG r4, 0x909BF04B;
CHECKREG r5, 0x0C93E9DB;
CHECKREG r6, 0x000C4AA2;
CHECKREG r7, 0x12468000;
imm32 r0, 0xa9235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x08060007;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a88fdb;
imm32 r6, 0x000c080d;
imm32 r7, 0x1246708f;
R2.L = R4.L * R6.L (S2RND);
R3.L = R2.H * R2.L (S2RND);
R0.H = R2.L * R3.L, R0.L = R2.H * R3.H (S2RND);
R1.H = R3.L * R1.L (S2RND);
R4.L = R4.H * R0.L (S2RND);
R5.L = R5.L * R5.L (S2RND);
R6.L = R6.L * R5.H (S2RND);
R7.H = R6.H * R7.L (S2RND);
CHECKREG r0, 0x00310266;
CHECKREG r1, 0xFD915127;
CHECKREG r2, 0x1324F997;
CHECKREG r3, 0x0806FE15;
CHECKREG r4, 0x908BFBD3;
CHECKREG r5, 0x10A87FFF;
CHECKREG r6, 0x000C0218;
CHECKREG r7, 0x0015708F;
imm32 r0, 0x7b235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x17246705;
imm32 r3, 0x00760007;
imm32 r4, 0x907bcd09;
imm32 r5, 0x10a7efdb;
imm32 r6, 0x000c700d;
imm32 r7, 0x1246770f;
R4.L = R5.L * R2.L (S2RND);
R6.L = R6.L * R3.H (S2RND);
R0.H = R7.L * R4.H (S2RND);
R1.L = R0.H * R5.L (S2RND);
R2.L = R1.L * R6.L (S2RND);
R5.L = R2.L * R7.H (S2RND);
R3.H = R3.H * R0.L (S2RND);
R7.L = R4.H * R1.H (S2RND);
CHECKREG r0, 0x80005675;
CHECKREG r1, 0xCFBA204A;
CHECKREG r2, 0x17240068;
CHECKREG r3, 0x009F0007;
CHECKREG r4, 0x907BE603;
CHECKREG r5, 0x10A7001E;
CHECKREG r6, 0x000C00CF;
CHECKREG r7, 0x1246541E;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,542 | sim/testsuite/bfin/c_except_user_mode.S | //Original:/proj/frio/dv/testcases/core/c_except_user_mode/c_except_user_mode.dsp
// Spec Reference: except_mode_user
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
//
////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI; // execute this instr put us in USER mode
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// USER MODE & go to different RAISE in USER mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
RAISE 2; // RTN // exception because we execute this in USER mode
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG(r0, 0x00000018);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = RETN;
R0 += 2;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
RETN = r0;
RTN;
XHANDLE: // Exception Handler 3
R1 = RETX;
I0 += 2;
R1 += 2; // for return address
RETX = r1;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = RETI;
R2 += 2;
I0 += 2;
I1 += 2;
RETI = r2;
RTI;
THANDLE: // Timer Handler 6
R3 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
R3 += 2;
RETI = r3;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = RETI;
I0 += 2;
I1 += 2;
I3 += 2;
R4 += 2;
RETI = r4;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R5 += 2;
RETI = r5;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R6 += 2;
RETI = r6;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R7 += 2;
RETI = r7;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = RETI;
R0 += 2;
M0 = I0;
M1 = I1;
M2 = I2;
M3 = I3;
RETI = r0;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R1 += 2;
RETI = r1;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R2 += 2;
RETI = r2;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = RETI;
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
R3 += 2;
RETI = r3;
RTI;
I15HANDLE: // IVG 15 Handler
I0 += 2;
I1 += 2;
I2 += 2;
I3 += 2;
RTI;
// nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
// .space (STACKSIZE); // adding this may solve the problem
|
tactcomplabs/xbgas-binutils-gdb | 8,629 | sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s | //Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// lshift : positive data, count (+)=left (half reg)
// d_lo = lshift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x90000001;
imm32 r2, 0x90000002;
imm32 r3, 0x90000003;
imm32 r4, 0x90000004;
imm32 r5, 0x90000005;
imm32 r6, 0x90000006;
imm32 r7, 0x90000007;
R0.L = R0.L << 0;
R1.L = R1.L >> 1;
R2.L = R2.L >> 2;
R3.L = R3.L >> 3;
R4.L = R4.L >> 4;
R5.L = R5.L >> 5;
R6.L = R6.L >> 6;
R7.L = R7.L >> 7;
CHECKREG r0, 0x0000FFFF;
CHECKREG r1, 0x90000000;
CHECKREG r2, 0x90000000;
CHECKREG r3, 0x90000000;
CHECKREG r4, 0x90000000;
CHECKREG r5, 0x90000000;
CHECKREG r6, 0x90000000;
CHECKREG r7, 0x90000000;
imm32 r0, 0x00001001;
R1.L = -1;
imm32 r2, 0xa0002002;
imm32 r3, 0xa0003003;
imm32 r4, 0xa0004004;
imm32 r5, 0xa0005005;
imm32 r6, 0xa0006006;
imm32 r7, 0xa0007007;
R0.L = R0.L >> 1;
R1.L = R1.L >> 1;
R2.L = R2.L >> 1;
R3.L = R3.L >> 1;
R4.L = R4.L >> 1;
R5.L = R5.L >> 1;
R6.L = R6.L >> 1;
R7.L = R7.L >> 1;
CHECKREG r0, 0x00000800;
CHECKREG r1, 0x90007FFF;
CHECKREG r2, 0xA0001001;
CHECKREG r3, 0xA0001801;
CHECKREG r4, 0xA0002002;
CHECKREG r5, 0xA0002802;
CHECKREG r6, 0xA0003003;
CHECKREG r7, 0xA0003803;
imm32 r0, 0xb0001001;
imm32 r1, 0xb0001001;
R2.L = -15;
imm32 r3, 0xb0003003;
imm32 r4, 0xb0004004;
imm32 r5, 0xb0005005;
imm32 r6, 0xb0006006;
imm32 r7, 0xb0007007;
R0.L = R0.L >> 15;
R1.L = R1.L >> 15;
R2.L = LSHIFT R2.L BY R2.L;
R3.L = R3.L >> 15;
R4.L = R4.L >> 15;
R5.L = R5.L >> 15;
R6.L = R6.L >> 15;
R7.L = R7.L >> 15;
CHECKREG r0, 0xb0000000;
CHECKREG r1, 0xb0000000;
CHECKREG r2, 0xA0000001;
CHECKREG r3, 0xB0000000;
CHECKREG r4, 0xb0000000;
CHECKREG r5, 0xb0000000;
CHECKREG r6, 0xb0000000;
CHECKREG r7, 0xB0000000;
imm32 r0, 0xc0001001;
imm32 r1, 0xc0001001;
imm32 r2, 0xc0002002;
R3.L = -16;
imm32 r4, 0xc0004004;
imm32 r5, 0xc0005005;
imm32 r6, 0xc0006006;
imm32 r7, 0xc0007007;
R0.L = R0.L >> 13;
R1.L = R1.L >> 13;
R2.L = R2.L >> 13;
R3.L = R3.L >> 13;
R4.L = R4.L >> 13;
R5.L = R5.L >> 13;
R6.L = R6.L >> 13;
R7.L = R7.L >> 13;
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xC0000001;
CHECKREG r3, 0xB0000007;
CHECKREG r4, 0xC0000002;
CHECKREG r5, 0xC0000002;
CHECKREG r6, 0xC0000003;
CHECKREG r7, 0xC0000003;
// RHx by RLx
imm32 r0, 0x0000c000;
imm32 r1, 0x0001c000;
imm32 r2, 0x0002c000;
imm32 r3, 0x0003c000;
imm32 r4, 0x0004c000;
imm32 r5, 0x0005c000;
imm32 r6, 0x0006c000;
imm32 r7, 0x0007c000;
R0.L = R0.H << 0;
R1.L = R1.H << 0;
R2.L = R2.H << 0;
R3.L = R3.H << 0;
R4.L = R4.H << 0;
R5.L = R5.H << 0;
R6.L = R6.H << 0;
R7.L = R7.H << 0;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x10010000;
R1.L = -1;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.L = R0.H >> 1;
R1.L = R1.H >> 1;
R2.L = R2.H >> 1;
R3.L = R3.H >> 1;
R4.L = R4.H >> 1;
R5.L = R5.H >> 1;
R6.L = R6.H >> 1;
R7.L = R7.H >> 1;
CHECKREG r0, 0x10010800;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x20021001;
CHECKREG r3, 0x30031801;
CHECKREG r4, 0x40042002;
CHECKREG r5, 0x50052802;
CHECKREG r6, 0x60063003;
CHECKREG r7, 0x70073803;
imm32 r0, 0x1001e000;
imm32 r1, 0x1001e000;
R2.L = -15;
imm32 r3, 0x3003e000;
imm32 r4, 0x4004e000;
imm32 r5, 0x5005e000;
imm32 r6, 0x6006e000;
imm32 r7, 0x7007e000;
R0.L = R0.H >> 15;
R1.L = R1.H >> 15;
R2.L = R2.H >> 15;
R3.L = R3.H >> 15;
R4.L = R4.H >> 15;
R5.L = R5.H >> 15;
R6.L = R6.H >> 15;
R7.L = R7.H >> 15;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020000;
CHECKREG r3, 0x30030000;
CHECKREG r4, 0x40040000;
CHECKREG r5, 0x50050000;
CHECKREG r6, 0x60060000;
CHECKREG r7, 0x70070000;
imm32 r0, 0x1001f001;
imm32 r1, 0x1001f001;
imm32 r2, 0x2002f002;
R3.L = -16;
imm32 r4, 0x4004f004;
imm32 r5, 0x5005f005;
imm32 r6, 0x6006f006;
imm32 r7, 0x7007f007;
R0.L = R0.H >> 13;
R1.L = R1.H >> 13;
R2.L = R2.H >> 13;
R3.L = R3.H >> 13;
R4.L = R4.H >> 13;
R5.L = R5.H >> 13;
R6.L = R6.H >> 13;
R7.L = R7.H >> 13;
CHECKREG r0, 0x10010000;
CHECKREG r1, 0x10010000;
CHECKREG r2, 0x20020001;
CHECKREG r3, 0x30030001;
CHECKREG r4, 0x40040002;
CHECKREG r5, 0x50050002;
CHECKREG r6, 0x60060003;
CHECKREG r7, 0x70070003;
// RLx by RLx
imm32 r0, 0x00001001;
imm32 r1, 0x00001001;
imm32 r2, 0x00001002;
imm32 r3, 0x00001003;
imm32 r4, 0x00001000;
imm32 r5, 0x00001005;
imm32 r6, 0x00001006;
imm32 r7, 0x00001007;
R0.H = R0.L >> 14;
R1.H = R1.L >> 14;
R2.H = R2.L >> 14;
R3.H = R3.L >> 14;
R4.H = R4.L >> 14;
R5.H = R5.L >> 14;
R6.H = R6.L >> 14;
R7.H = R7.L >> 14;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00001001;
CHECKREG r2, 0x00001002;
CHECKREG r3, 0x00001003;
CHECKREG r4, 0x00001000;
CHECKREG r5, 0x00001005;
CHECKREG r6, 0x00001006;
CHECKREG r7, 0x00001007;
imm32 r0, 0x00002001;
imm32 r1, 0x00002001;
imm32 r2, 0x00002002;
imm32 r3, 0x00002003;
imm32 r4, 0x00002004;
R5.L = -1;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = R0.L >> 5;
R1.H = R1.L >> 5;
R2.H = R2.L >> 5;
R3.H = R3.L >> 5;
R4.H = R4.L >> 5;
R5.H = R5.L >> 5;
R6.H = R6.L >> 5;
R7.H = R7.L >> 5;
CHECKREG r0, 0x01002001;
CHECKREG r1, 0x01002001;
CHECKREG r2, 0x01002002;
CHECKREG r3, 0x01002003;
CHECKREG r4, 0x01002004;
CHECKREG r5, 0x07FFFFFF;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
imm32 r0, 0x30001001;
imm32 r1, 0x30001001;
imm32 r1, 0x30002002;
imm32 r3, 0x30003003;
imm32 r4, 0x30004004;
imm32 r5, 0x30005005;
R6.L = -15;
imm32 r7, 0x00007007;
R0.H = R0.L >> 15;
R1.H = R1.L >> 15;
R2.H = R2.L >> 15;
R3.H = R3.L >> 15;
R4.H = R4.L >> 15;
R5.H = R5.L >> 15;
R6.H = R6.L >> 15;
R7.H = R7.L >> 15;
CHECKREG r0, 0x00001001;
CHECKREG r1, 0x00002002;
CHECKREG r2, 0x00002002;
CHECKREG r3, 0x00003003;
CHECKREG r4, 0x00004004;
CHECKREG r5, 0x00005005;
CHECKREG r6, 0x0001FFF1;
CHECKREG r7, 0x00007007;
imm32 r0, 0x40001001;
imm32 r1, 0x40002001;
imm32 r2, 0x40002002;
imm32 r3, 0x40003003;
imm32 r4, 0x40004004;
imm32 r5, 0x40005005;
imm32 r6, 0x40006006;
R7.L = -16;
R0.H = R0.L >> 7;
R1.H = R1.L >> 7;
R2.H = R2.L >> 7;
R3.H = R3.L >> 7;
R4.H = R4.L >> 7;
R5.H = R5.L >> 7;
R6.H = R6.L >> 7;
R7.H = R7.L >> 7;
CHECKREG r0, 0x00201001;
CHECKREG r1, 0x00402001;
CHECKREG r2, 0x00402002;
CHECKREG r3, 0x00603003;
CHECKREG r4, 0x00804004;
CHECKREG r5, 0x00A05005;
CHECKREG r6, 0x00C06006;
CHECKREG r7, 0x01FFFFF0;
// RHx by RLx
imm32 r0, 0x50010000;
imm32 r1, 0x50010000;
imm32 r2, 0x50020000;
imm32 r3, 0x50030000;
R4.L = -1;
imm32 r5, 0x50050000;
imm32 r6, 0x50060000;
imm32 r7, 0x50070000;
R0.H = R0.H >> 1;
R1.H = R1.H >> 1;
R2.H = R2.H >> 1;
R3.H = R3.H >> 1;
R4.H = R4.H >> 1;
R5.H = R5.H >> 1;
R6.H = R6.H >> 1;
R7.H = R7.H >> 1;
CHECKREG r0, 0x28000000;
CHECKREG r1, 0x28000000;
CHECKREG r2, 0x28010000;
CHECKREG r3, 0x28010000;
CHECKREG r4, 0x0040FFFF;
CHECKREG r5, 0x28020000;
CHECKREG r6, 0x28030000;
CHECKREG r7, 0x28030000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
R5.L = -1;
imm32 r6, 0x60060000;
imm32 r7, 0x70070000;
R0.H = R0.H >> 5;
R1.H = R1.H >> 5;
R2.H = R2.H >> 5;
R3.H = R3.H >> 5;
R4.H = R4.H >> 5;
R5.H = R5.H >> 5;
R6.H = R6.H >> 5;
R7.H = R7.H >> 5;
CHECKREG r0, 0x00800000;
CHECKREG r1, 0x00800000;
CHECKREG r2, 0x01000000;
CHECKREG r3, 0x01800000;
CHECKREG r4, 0x02000000;
CHECKREG r5, 0x0140FFFF;
CHECKREG r6, 0x03000000;
CHECKREG r7, 0x03800000;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r3, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
R6.L = -15;
imm32 r7, 0x70070000;
R0.L = R0.H >> 6;
R1.L = R1.H >> 6;
R2.L = R2.H >> 6;
R3.L = R3.H >> 6;
R4.L = R4.H >> 6;
R5.L = R5.H >> 6;
R6.L = R6.H >> 6;
R7.L = R7.H >> 6;
CHECKREG r0, 0x10010040;
CHECKREG r1, 0x10010040;
CHECKREG r2, 0x20020080;
CHECKREG r3, 0x300300C0;
CHECKREG r4, 0x40040100;
CHECKREG r5, 0x50050140;
CHECKREG r6, 0x0300000C;
CHECKREG r7, 0x700701C0;
imm32 r0, 0x10010000;
imm32 r1, 0x10010000;
imm32 r2, 0x20020000;
imm32 r2, 0x30030000;
imm32 r4, 0x40040000;
imm32 r5, 0x50050000;
imm32 r6, 0x60060000;
R7.L = -16;
R0.H = R0.H >> 15;
R1.H = R1.H >> 15;
R2.H = R2.H >> 15;
R3.H = R3.H >> 15;
R4.H = R4.H >> 15;
R5.H = R5.H >> 15;
R6.H = R6.H >> 15;
R7.H = R7.H >> 15;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x000000C0;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x0000FFF0;
pass
|
tactcomplabs/xbgas-binutils-gdb | 8,604 | sim/testsuite/bfin/random_0027.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x2850c890 | _VS | _AV1S | _AV0S | _AQ | _CC | _AC0_COPY);
dmm32 A1.w, 0xa605868e;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x56dd0982;
imm32 R4, 0x50e37862;
imm32 R5, 0x597fc81a;
R4.H = (A1 -= R5.L * R1.L) (M, IS);
checkreg R4, 0x7fff7862;
checkreg A1.w, 0xa818ff5a;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x2850c890 | _VS | _V | _AV1S | _AV0S | _AQ | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x08100a00 | _VS | _AC1 | _AC0 | _CC);
dmm32 A1.w, 0xeb710132;
dmm32 A1.x, 0xffffffcf;
imm32 R4, 0x750d92cc;
imm32 R7, 0xf9a22cee;
R4.H = (A1 -= R7.L * R7.H) (M, IS);
checkreg R4, 0x800092cc;
checkreg A1.w, 0xbfa11496;
checkreg A1.x, 0xffffffcf;
checkreg ASTAT, (0x08100a00 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY);
dmm32 ASTAT, (0x44e00410 | _VS | _AV0S | _AQ | _AN);
dmm32 A1.w, 0x95489ea8;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x360dca41;
imm32 R4, 0x7fffe848;
imm32 R7, 0x278abda8;
R7 = (A1 -= R4.L * R1.L) (M, IS);
checkreg R7, 0x7fffffff;
checkreg A1.w, 0xa805d460;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x44e00410 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0xcfa4f43b;
dmm32 A1.x, 0x0000006c;
imm32 R3, 0x0903dd55;
imm32 R7, 0x7fffc2b1;
A1 -= R3.L * R7.L (M, IS);
checkreg A1.w, 0xea028276;
checkreg A1.x, 0x0000006c;
checkreg ASTAT, (0x0480c800 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x3c204410 | _VS | _AV0S | _AN);
dmm32 A1.w, 0x928b984e;
dmm32 A1.x, 0xffffffd5;
imm32 R5, 0x00003ddd;
imm32 R7, 0x8000ffff;
A1 += R5.L * R7.L (M, IS);
checkreg A1.w, 0xd0685a71;
checkreg A1.x, 0xffffffd5;
checkreg ASTAT, (0x3c204410 | _VS | _AV0S | _AN);
dmm32 ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 A1.w, 0x8837abf1;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x10c90000;
imm32 R7, 0x7fffe6b8;
A1 += R7.L * R3.H (M, IS);
checkreg A1.w, 0x868f5269;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x4840c890 | _VS | _AV1S | _AV0S | _AC0 | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0xdca875cf;
dmm32 A1.x, 0x0000002c;
imm32 R3, 0x4c0892ef;
imm32 R5, 0x001fea98;
R5.H = (A1 += R5.L * R3.H) (M, IS);
checkreg R5, 0x7fffea98;
checkreg A1.w, 0xd64cea8f;
checkreg A1.x, 0x0000002c;
checkreg ASTAT, (0x78604a80 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xec5ef880;
dmm32 A1.x, 0xfffffffe;
imm32 R0, 0x229657d6;
imm32 R7, 0xedd48000;
A1 += R0.L * R7.L (M, IS);
checkreg A1.w, 0x1849f880;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x00a04210 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A1.w, 0xe4a5a6e1;
dmm32 A1.x, 0x00000078;
imm32 R0, 0xf059329d;
imm32 R7, 0x7fff7512;
A1 += R7.L * R0.L (M, IS);
checkreg A1.w, 0xfbcaf6eb;
checkreg A1.x, 0x00000078;
checkreg ASTAT, (0x0840ce80 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ);
dmm32 A1.w, 0xd56a8232;
dmm32 A1.x, 0x00000033;
imm32 R0, 0x09b22c69;
imm32 R7, 0x434f1d64;
A1 -= R0.L * R7.L (M, IS);
checkreg A1.w, 0xd051442e;
checkreg A1.x, 0x00000033;
checkreg ASTAT, (0x60100810 | _VS | _AV0S | _AQ | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x86c9a59e;
dmm32 A1.x, 0xffffff9a;
imm32 R1, 0x22573f31;
imm32 R6, 0x2d0c0155;
A1 += R1.L * R6.H (M, IS);
checkreg A1.w, 0x91e838ea;
checkreg A1.x, 0xffffff9a;
checkreg ASTAT, (0x58e08410 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xc5c840aa;
dmm32 A1.x, 0x00000000;
imm32 R4, 0xffff7fff;
imm32 R7, 0x658e833f;
A1 -= R7.L * R4.H (M, IS);
checkreg A1.w, 0x4288c3e9;
checkreg A1.x, 0x00000001;
checkreg ASTAT, (0x64a0c690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 A1.w, 0xf1000000;
dmm32 A1.x, 0x00000040;
imm32 R3, 0x0cd4edf1;
imm32 R6, 0x4dfc08b8;
R6.H = (A1 += R6.L * R3.H) (M, IS);
checkreg R6, 0x7fff08b8;
checkreg A1.w, 0xf16fd860;
checkreg A1.x, 0x00000040;
checkreg ASTAT, (0x08804610 | _VS | _V | _AV0S | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x7c004690 | _VS | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0xd4deb886;
dmm32 A1.x, 0x00000001;
imm32 R1, 0x80008000;
imm32 R6, 0x22fb6e50;
imm32 R7, 0x3fcb147f;
R1.H = (A1 -= R7.L * R6.L) (M, IS);
checkreg R1, 0x7fff8000;
checkreg A1.w, 0xcc09bed6;
checkreg A1.x, 0x00000001;
checkreg ASTAT, (0x7c004690 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 A1.w, 0x9698e35b;
dmm32 A1.x, 0xfffffffc;
imm32 R5, 0x8000038c;
imm32 R6, 0x3152ffff;
A1 -= R6.L * R5.L (M, IS);
checkreg A1.w, 0x9698e6e7;
checkreg A1.x, 0xfffffffc;
checkreg ASTAT, (0x40a00400 | _VS | _V | _AV1S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ);
dmm32 A1.w, 0x9b02b9c6;
dmm32 A1.x, 0xffffffd4;
imm32 R2, 0xff020105;
imm32 R3, 0xa8ff8000;
R3.H = (A1 -= R2.L * R3.L) (M, IS);
checkreg R3, 0x80008000;
checkreg A1.w, 0x9a8039c6;
checkreg A1.x, 0xffffffd4;
checkreg ASTAT, (0x54c00810 | _VS | _V | _AC1 | _CC | _V_COPY | _AN | _AZ);
dmm32 ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x990456b2;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x2b76c7b2;
imm32 R3, 0x659803c8;
imm32 R7, 0x7fffffff;
R3.H = (A1 += R7.L * R0.L) (M, IS);
checkreg R3, 0x7fff03c8;
checkreg A1.w, 0x99038f00;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x58808680 | _VS | _V | _AC1 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 A1.w, 0x95d1d45a;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x4331b012;
imm32 R5, 0x7fff8000;
A1 -= R0.L * R5.H (M, IS);
checkreg A1.w, 0xbdc8846c;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x3ce04690 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY);
dmm32 ASTAT, (0x30e04410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC);
dmm32 A1.w, 0xcf49e4c9;
dmm32 A1.x, 0x00000000;
imm32 R1, 0xe968a740;
imm32 R3, 0xd7383cd5;
imm32 R6, 0x5a87c89b;
R1 = (A1 += R3.L * R6.H) (M, IS);
checkreg R1, 0x7fffffff;
checkreg A1.w, 0xe4ccdb1c;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x30e04410 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY);
dmm32 A1.w, 0x8bdaf471;
dmm32 A1.x, 0xffffffbd;
imm32 R3, 0x728d99b1;
imm32 R7, 0x181d83c2;
A1 -= R7.L * R3.L (M, IS);
checkreg A1.w, 0xd671e94f;
checkreg A1.x, 0xffffffbd;
checkreg ASTAT, (0x2cb04890 | _VS | _AC1 | _AQ | _AC0_COPY);
dmm32 ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ);
dmm32 A1.w, 0xc1cb8a00;
dmm32 A1.x, 0x00000000;
imm32 R1, 0xc1e98ea8;
imm32 R7, 0x0000961f;
A1 -= R7.L * R1.L (M, IS);
checkreg A1.w, 0xfccbd3a8;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x20908680 | _VS | _AV0S | _AC1 | _AQ | _CC | _AZ);
dmm32 ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ);
dmm32 A1.w, 0xfb328cb4;
dmm32 A1.x, 0xffffff9b;
imm32 R2, 0x8000ffff;
imm32 R3, 0x64d21863;
imm32 R6, 0x3b7618a6;
R2.H = (A1 += R3.L * R6.H) (M, IS);
checkreg A1.w, 0x00dc9b56;
checkreg A1.x, 0xffffff9c;
checkreg ASTAT, (0x64a0cc80 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AZ);
dmm32 ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0xbfb4c632;
dmm32 A1.x, 0x00000044;
imm32 R1, 0x7fffffff;
imm32 R3, 0xf3e9182e;
imm32 R5, 0x3c94d844;
R5.H = (A1 += R1.L * R3.H) (M, IS);
checkreg R5, 0x7fffd844;
checkreg A1.w, 0xbfb3d249;
checkreg A1.x, 0x00000044;
checkreg ASTAT, (0x3c00ca90 | _VS | _V | _AV0S | _AC1 | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
dmm32 A1.w, 0x83144651;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x04d0ffff;
imm32 R4, 0x9dc8f8d8;
imm32 R7, 0x23180d75;
R3 = (A1 += R4.L * R7.L) (M, IS);
checkreg R3, 0x7fffffff;
checkreg A1.w, 0x82b3f909;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x48c0cc10 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,820 | sim/testsuite/bfin/cec-raise-reti.S | # Blackfin testcase for having RETI set correctly
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
start
# First mark all EVTs as fails (they shouldn't be activated)
imm32 P5, EVT0;
P1 = P5;
loadsym R1, fail_lvl
imm32 P2, 16
LSETUP (1f, 1f) LC0 = P2;
1: [P1++] = R1;
# We'll bounce up a few
set_evt 6, evt6;
set_evt 7, evt7;
set_evt 8, evt8;
set_evt 9, evt9;
# Lower ourselves down so we can RAISE up
set_evt 14, evt14;
loadsym R1, wait;
RETI = R1;
RAISE 14;
R7 = -1;
sti R7;
RTI;
wait:
jump wait;
evt14:
# Activate interrupt nesting early
[--SP] = RETI;
# We activate the interrupt here ...
loadsym R1, 1f;
RAISE 9;
# ... but we should RETI here
1: JUMP fail_lvl;
evt9:
R2 = RETI;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# We activate the interrupt here ...
loadsym R1, 1f;
RAISE 8;
[--SP] = RETI;
# ... but we should RETI here
1: JUMP fail_lvl;
evt8:
R2 = RETI;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# Activate interrupt nesting early
[--SP] = RETI;
# We activate the interrupt here ...
loadsym R1, 1f;
cli R7;
RAISE 7;
sti R7;
# ... but we should RETI here
1: JUMP fail_lvl;
evt7:
R2 = RETI;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# Activate interrupt nesting early
[--SP] = RETI;
# We activate the interrupt here ...
imm32 P0, IMASK
R7 = [P0];
R6 = 0;
[P0] = R6;
loadsym R1, 1f;
RAISE 6;
[P0] = R7;
# ... but we should RETI here
# don't jump to fail_lvl as the pipeline might advance
# the PC to the fail_lvl point before the ivg actually
# gets a chance to fire
1: JUMP 1b;
evt6:
R2 = RETI;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
dbg_pass
fail_lvl:
dbg_fail;
|
tactcomplabs/xbgas-binutils-gdb | 1,456 | sim/testsuite/bfin/a23.s | // Test ALU ABS accumulators
# mach: bfin
.include "testutils.inc"
start
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000001;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0xffffffff;
A0.w = R0;
R0 = 0xff (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
R0 = 0xfffffff0;
A0.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfff0 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A1 = ABS A0;
R4 = A1.w;
R5 = A1.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
R0 = 0x00000002;
A1.w = R0;
R0 = 0x80 (X);
A1.x = R0;
A1 = ABS A1, A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R4 = A1.w;
R5 = A1.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,136 | sim/testsuite/bfin/c_dsp32alu_rh_rnd12_p.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_p/c_dsp32alu_rh_rnd12_p.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x45678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xf4445515;
imm32 r3, 0x46667717;
imm32 r4, 0xe678891b;
imm32 r5, 0x6f89ab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x8666b777;
R0.H = R0 + R0 (RND12);
R1.H = R0 + R1 (RND12);
R2.H = R0 + R2 (RND12);
R3.H = R0 + R3 (RND12);
R4.H = R0 + R4 (RND12);
R5.H = R0 + R5 (RND12);
R6.H = R0 + R6 (RND12);
R7.H = R0 + R7 (RND12);
CHECKREG r0, 0x7FFF8911;
CHECKREG r1, 0x7fffAB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x7fff7717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fffD515;
CHECKREG r7, 0x6664B777;
imm32 r0, 0xd5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xa4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5b78891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74e45515;
imm32 r7, 0x86a6b777;
R0.H = R1 + R0 (RND12);
R1.H = R1 + R1 (RND12);
R2.H = R1 + R2 (RND12);
R3.H = R1 + R3 (RND12);
R4.H = R1 + R4 (RND12);
R5.H = R1 + R5 (RND12);
R6.H = R1 + R6 (RND12);
R7.H = R1 + R7 (RND12);
CHECKREG r0, 0xcf138911;
CHECKREG r1, 0x7FFFAB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x7fff7717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x6A66B777;
imm32 r0, 0xa5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xb4445515;
imm32 r3, 0x46667717;
imm32 r4, 0xd678891b;
imm32 r5, 0x6e89ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86967777;
R0.H = R2 + R0 (RND12);
R1.H = R2 + R1 (RND12);
R2.H = R2 + R2 (RND12);
R3.H = R2 + R3 (RND12);
R4.H = R2 + R4 (RND12);
R5.H = R2 + R5 (RND12);
R6.H = R2 + R6 (RND12);
R7.H = R2 + R7 (RND12);
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x80007777;
CHECKREG r4, 0x8000891B;
CHECKREG r5, 0x8000AB1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x80007777;
imm32 r0, 0x35678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0xd4445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0xeab9ab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x866e777f;
R0.H = R3 + R0 (RND12);
R1.H = R3 + R1 (RND12);
R2.H = R3 + R2 (RND12);
R3.H = R3 + R3 (RND12);
R4.H = R3 + R4 (RND12);
R5.H = R3 + R5 (RND12);
R6.H = R3 + R6 (RND12);
R7.H = R3 + R7 (RND12);
CHECKREG r0, 0x7FFF8911;
CHECKREG r1, 0x7FFFAB1D;
CHECKREG r2, 0x7FFF5515;
CHECKREG r3, 0x7FFF7717;
CHECKREG r4, 0x7fff891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x66df777F;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5675891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xa4465515;
imm32 r7, 0x8b66e777;
R0.H = R4 + R0 (RND12);
R1.H = R4 + R1 (RND12);
R2.H = R4 + R2 (RND12);
R3.H = R4 + R3 (RND12);
R4.H = R4 + R4 (RND12);
R5.H = R4 + R5 (RND12);
R6.H = R4 + R6 (RND12);
R7.H = R4 + R7 (RND12);
CHECKREG r0, 0x7FFF8911;
CHECKREG r1, 0x7FFFAB1D;
CHECKREG r2, 0x7FFF5515;
CHECKREG r3, 0x7FFF7717;
CHECKREG r4, 0x7FFF891B;
CHECKREG r5, 0x7fffAB1D;
CHECKREG r6, 0x7fff5515;
CHECKREG r7, 0x7fffE777;
imm32 r0, 0x35678111;
imm32 r1, 0x2789a21d;
imm32 r2, 0x3e445535;
imm32 r3, 0x46667757;
imm32 r4, 0xe6f8891b;
imm32 r5, 0x6789db7d;
imm32 r6, 0xf44a5595;
imm32 r7, 0x866b7770;
R0.H = R5 + R0 (RND12);
R1.H = R5 + R1 (RND12);
R2.H = R5 + R2 (RND12);
R3.H = R5 + R3 (RND12);
R4.H = R5 + R4 (RND12);
R5.H = R5 + R5 (RND12);
R6.H = R5 + R6 (RND12);
R7.H = R5 + R7 (RND12);
CHECKREG r0, 0x7FFF8111;
CHECKREG r1, 0x7FFFA21D;
CHECKREG r2, 0x7fff5535;
CHECKREG r3, 0x7FFF7757;
CHECKREG r4, 0x7FFF891B;
CHECKREG r5, 0x7FFFDB7D;
CHECKREG r6, 0x7fff5595;
CHECKREG r7, 0x66b57770;
imm32 r0, 0xb5678911;
imm32 r1, 0xc789ab1d;
imm32 r2, 0x3ab45515;
imm32 r3, 0x466b7717;
imm32 r4, 0x4678e91b;
imm32 r5, 0x6789af1d;
imm32 r6, 0xf4445515;
imm32 r7, 0x86e6f777;
R0.H = R6 + R0 (RND12);
R1.H = R6 + R1 (RND12);
R2.H = R6 + R2 (RND12);
R3.H = R6 + R3 (RND12);
R4.H = R6 + R4 (RND12);
R5.H = R6 + R5 (RND12);
R6.H = R6 + R6 (RND12);
R7.H = R6 + R7 (RND12);
CHECKREG r0, 0x80008911;
CHECKREG r1, 0x8000AB1D;
CHECKREG r2, 0x7fff5515;
CHECKREG r3, 0x7FFF7717;
CHECKREG r4, 0x7FFFE91B;
CHECKREG r5, 0x7FFFAF1D;
CHECKREG r6, 0x80005515;
CHECKREG r7, 0x8000F777;
imm32 r0, 0xab678021;
imm32 r1, 0x2c89a33d;
imm32 r2, 0x34d45575;
imm32 r3, 0x466e7797;
imm32 r4, 0x567f89fb;
imm32 r5, 0x6789abdd;
imm32 r6, 0x744e5515;
imm32 r7, 0x8666ab87;
R0.H = R7 + R0 (RND12);
R1.H = R7 + R1 (RND12);
R2.H = R7 + R2 (RND12);
R3.H = R7 + R3 (RND12);
R4.H = R7 + R4 (RND12);
R5.H = R7 + R5 (RND12);
R6.H = R7 + R6 (RND12);
R7.H = R7 + R7 (RND12);
CHECKREG r0, 0x80008021;
CHECKREG r1, 0x8000A33D;
CHECKREG r2, 0x80005575;
CHECKREG r3, 0x80007797;
CHECKREG r4, 0x800089FB;
CHECKREG r5, 0x8000ABDD;
CHECKREG r6, 0xab505515;
CHECKREG r7, 0x8000AB87;
imm32 r0, 0x15678901;
imm32 r1, 0x2789ab2d;
imm32 r2, 0x34445535;
imm32 r3, 0x46667747;
imm32 r4, 0x56788915;
imm32 r5, 0x6789ab6d;
imm32 r6, 0x74445518;
imm32 r7, 0x86667797;
R6.H = R2 + R3 (RND12);
R1.H = R4 + R5 (RND12);
R5.H = R7 + R2 (RND12);
R3.H = R0 + R0 (RND12);
R0.H = R3 + R4 (RND12);
R2.H = R5 + R7 (RND12);
R7.H = R6 + R7 (RND12);
R4.H = R1 + R6 (RND12);
CHECKREG r0, 0x7fff8901;
CHECKREG r1, 0x7FFFAB2D;
CHECKREG r2, 0x80005535;
CHECKREG r3, 0x7FFF7747;
CHECKREG r4, 0x7fff8915;
CHECKREG r5, 0x8000AB6D;
CHECKREG r6, 0x7FFF5518;
CHECKREG r7, 0x665D7797;
imm32 r0, 0x35678911;
imm32 r1, 0x2489ab1d;
imm32 r2, 0x34545565;
imm32 r3, 0x4d6677b7;
imm32 r4, 0x567889db;
imm32 r5, 0x67beab1d;
imm32 r6, 0x7b445595;
imm32 r7, 0x86d6e707;
R3.H = R4 + R0 (RND12);
R1.H = R6 + R3 (RND12);
R4.H = R3 + R2 (RND12);
R6.H = R7 + R1 (RND12);
R2.H = R5 + R4 (RND12);
R7.H = R2 + R7 (RND12);
R0.H = R1 + R6 (RND12);
R5.H = R0 + R5 (RND12);
CHECKREG r0, 0x7fff8911;
CHECKREG r1, 0x7fffAB1D;
CHECKREG r2, 0x7FFF5565;
CHECKREG r3, 0x7FFF77B7;
CHECKREG r4, 0x7fff89DB;
CHECKREG r5, 0x7FFFAB1D;
CHECKREG r6, 0x6d695595;
CHECKREG r7, 0x6D64E707;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,277 | sim/testsuite/bfin/c_ldst_ld_d_p_mm.s | //Original:testcases/core/c_ldst_ld_d_p_mm/c_ldst_ld_d_p_mm.dsp
// Spec Reference: c_ldst ld d [p--]
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
R0 = [ P5 -- ];
R1 = [ P1 -- ];
R2 = [ P2 -- ];
R3 = [ P3 -- ];
R4 = [ P4 -- ];
R5 = [ FP -- ];
R6 = [ SP -- ];
CHECKREG r0, 0x11223344;
CHECKREG r1, 0x91929394;
CHECKREG r2, 0xC9CACBCD;
CHECKREG r3, 0xEBECEDEE;
CHECKREG r4, 0x0F101213;
CHECKREG r5, 0x20212223;
CHECKREG r6, 0xA0A1A2A3;
R1 = [ P5 -- ];
R2 = [ P1 -- ];
R3 = [ P2 -- ];
R4 = [ P3 -- ];
R5 = [ P4 -- ];
R6 = [ FP -- ];
R7 = [ SP -- ];
CHECKREG r0, 0x11223344;
CHECKREG r1, 0x1C1D1E1F;
CHECKREG r2, 0x3C3D3E3F;
CHECKREG r3, 0xC5C6C7C8;
CHECKREG r4, 0x7C7D7E7F;
CHECKREG r5, 0x9C9D9E9F;
CHECKREG r6, 0x1C1D1E1F;
CHECKREG r7, 0x9C9D9E9F;
R2 = [ P5 -- ];
R3 = [ P1 -- ];
R4 = [ P2 -- ];
R5 = [ P3 -- ];
R6 = [ P4 -- ];
R7 = [ FP -- ];
R0 = [ SP -- ];
CHECKREG r0, 0x98999A9B;
CHECKREG r1, 0x1C1D1E1F;
CHECKREG r2, 0x18191A1B;
CHECKREG r3, 0x38393A3B;
CHECKREG r4, 0x58595A5B;
CHECKREG r5, 0x78797A7B;
CHECKREG r6, 0x98999A9B;
CHECKREG r7, 0x18191A1B;
R3 = [ P5 -- ];
R4 = [ P1 -- ];
R5 = [ P2 -- ];
R6 = [ P3 -- ];
R7 = [ P4 -- ];
R0 = [ FP -- ];
R1 = [ SP -- ];
CHECKREG r0, 0x14151617;
CHECKREG r1, 0x94959697;
CHECKREG r2, 0x18191A1B;
CHECKREG r3, 0x14151617;
CHECKREG r4, 0x34353637;
CHECKREG r5, 0x54555657;
CHECKREG r6, 0x74757677;
CHECKREG r7, 0x94959697;
R4 = [ P5 -- ];
R5 = [ P1 -- ];
R6 = [ P2 -- ];
R7 = [ P3 -- ];
R0 = [ P4 -- ];
R1 = [ FP -- ];
R2 = [ SP -- ];
CHECKREG r0, 0x90919293;
CHECKREG r1, 0x10111213;
CHECKREG r2, 0x90919293;
CHECKREG r3, 0x14151617;
CHECKREG r4, 0x10111213;
CHECKREG r5, 0x30313233;
CHECKREG r6, 0x50515253;
CHECKREG r7, 0x70717273;
R5 = [ P5 -- ];
R6 = [ P1 -- ];
R7 = [ P2 -- ];
R0 = [ P3 -- ];
R1 = [ P4 -- ];
R2 = [ FP -- ];
R3 = [ SP -- ];
CHECKREG r0, 0x6C6D6E6F;
CHECKREG r1, 0x8C8D8E8F;
CHECKREG r2, 0x0C0D0E0F;
CHECKREG r3, 0x8C8D8E8F;
CHECKREG r4, 0x10111213;
CHECKREG r5, 0x0C0D0E0F;
CHECKREG r6, 0x2C2D2E2F;
CHECKREG r7, 0x4C4D4E4F;
R6 = [ P5 -- ];
R7 = [ P1 -- ];
R0 = [ P2 -- ];
R1 = [ P3 -- ];
R2 = [ P4 -- ];
R3 = [ FP -- ];
R4 = [ SP -- ];
CHECKREG r0, 0x48494A4B;
CHECKREG r1, 0x68696A6B;
CHECKREG r2, 0x88898A8B;
CHECKREG r3, 0x08090A0B;
CHECKREG r4, 0x88898A8B;
CHECKREG r5, 0x0C0D0E0F;
CHECKREG r6, 0x08090A0B;
CHECKREG r7, 0x28292A2B;
R7 = [ P5 -- ];
R0 = [ P1 -- ];
R1 = [ P2 -- ];
R2 = [ P3 -- ];
R3 = [ P4 -- ];
R4 = [ FP -- ];
R5 = [ SP -- ];
CHECKREG r0, 0x24252627;
CHECKREG r1, 0x44454647;
CHECKREG r2, 0x64656667;
CHECKREG r3, 0x84858687;
CHECKREG r4, 0x04050607;
CHECKREG r5, 0x84858687;
CHECKREG r6, 0x08090A0B;
CHECKREG r7, 0x04050607;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,839 | sim/testsuite/bfin/c_dsp32mac_dr_a0_i.s | //Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp
// Spec Reference: dsp32mac dr a0 i (signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0x9dbcfec7;
imm32 r2, 0xc9248679;
imm32 r3, 0xd0969007;
imm32 r4, 0xefb94569;
imm32 r5, 0xcd35900b;
imm32 r6, 0xe00c890d;
imm32 r7, 0xf78e909f;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS);
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS);
R3 = A0.w;
A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS);
R5 = A0.w;
A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS);
R7 = A0.w;
CHECKREG r0, 0xA3548000;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0xC9247FFF;
CHECKREG r3, 0x17FEBFFC;
CHECKREG r4, 0xEFB97FFF;
CHECKREG r5, 0x1B398649;
CHECKREG r6, 0xE00C7FFF;
CHECKREG r7, 0x174CF613;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x68548abd;
imm32 r1, 0x7d8cfec7;
imm32 r2, 0xa1285679;
imm32 r3, 0xb0068007;
imm32 r4, 0xcfbc4869;
imm32 r5, 0xd235c08b;
imm32 r6, 0xe00ca008;
imm32 r7, 0x678e700f;
R0.L = ( A0 -= R1.L * R0.L ) (IS);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (IS);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.L ) (IS);
R5 = A0.w;
R6.L = ( A0 -= R6.H * R7.H ) (IS);
R7 = A0.w;
CHECKREG r0, 0x68547FFF;
CHECKREG r1, 0x16BD9728;
CHECKREG r2, 0xA1288000;
CHECKREG r3, 0xFBB9CDFE;
CHECKREG r4, 0xCFBC7FFF;
CHECKREG r5, 0x0BF6CB14;
CHECKREG r6, 0xE00C7FFF;
CHECKREG r7, 0x18E3B06C;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x7b54babd;
imm32 r1, 0xb7bcdec7;
imm32 r2, 0x7b7be679;
imm32 r3, 0x80b77007;
imm32 r4, 0x9fbb7569;
imm32 r5, 0xa235b70b;
imm32 r6, 0xb00c3b7d;
imm32 r7, 0xc78ea0b7;
R0.L = ( A0 = R1.L * R0.L ) (IS);
R1 = A0.w;
R2.L = ( A0 -= R2.H * R3.L ) (IS);
R3 = A0.w;
R4.L = ( A0 = R4.H * R5.H ) (IS);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (IS);
R7 = A0.w;
CHECKREG r0, 0x7B547FFF;
CHECKREG r1, 0x08FD0EEB;
CHECKREG r2, 0x7B7B8000;
CHECKREG r3, 0xD2F3DE8E;
CHECKREG r4, 0x9FBB7FFF;
CHECKREG r5, 0x234567B7;
CHECKREG r6, 0xB00C7FFF;
CHECKREG r7, 0x1627920D;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xe3545abd;
imm32 r1, 0x5ebcfec7;
imm32 r2, 0x71e45679;
imm32 r3, 0x900e0007;
imm32 r4, 0xafbce569;
imm32 r5, 0xd2359e0b;
imm32 r6, 0xc00ca0ed;
imm32 r7, 0x678ed00e;
A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IS);
R3 = A0.w;
A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (IS);
R7 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (IS);
R5 = A0.w;
A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IS);
R1 = A0.w;
CHECKREG r0, 0xE3547FFF;
CHECKREG r1, 0x2E5AD9ED;
CHECKREG r2, 0x71E47FFF;
CHECKREG r3, 0x15B8A0F8;
CHECKREG r4, 0xAFBC7FFF;
CHECKREG r5, 0x0E5B99EC;
CHECKREG r6, 0xC00C7FFF;
CHECKREG r7, 0x3FFFCC18;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,744 | sim/testsuite/bfin/c_ldimmhalf_h_ibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp
// Spec Reference: ldimmhalf h ibml
# mach: bfin
.include "testutils.inc"
start
INIT_I_REGS -1;
INIT_L_REGS -1;
INIT_B_REGS -1;
INIT_M_REGS -1;
I0.H = 0x2000;
I1.H = 0x2002;
I2.H = 0x2004;
I3.H = 0x2006;
L0.H = 0x2008;
L1.H = 0x200a;
L2.H = 0x200c;
L3.H = 0x200e;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x2000ffff;
CHECKREG r1, 0x2002ffff;
CHECKREG r2, 0x2004ffff;
CHECKREG r3, 0x2006ffff;
CHECKREG r4, 0x2008ffff;
CHECKREG r5, 0x200affff;
CHECKREG r6, 0x200cffff;
CHECKREG r7, 0x200effff;
I0.H = 0x0111;
I1.H = 0x1111;
I2.H = 0x2222;
I3.H = 0x3333;
L0.H = 0x4444;
L1.H = 0x5555;
L2.H = 0x6666;
L3.H = 0x7777;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x0111ffff;
CHECKREG r1, 0x1111ffff;
CHECKREG r2, 0x2222ffff;
CHECKREG r3, 0x3333ffff;
CHECKREG r4, 0x4444ffff;
CHECKREG r5, 0x5555ffff;
CHECKREG r6, 0x6666ffff;
CHECKREG r7, 0x7777ffff;
I0.H = 0x8888;
I1.H = 0x9aaa;
I2.H = 0xabbb;
I3.H = 0xbccc;
L0.H = 0xcddd;
L1.H = 0xdeee;
L2.H = 0xefff;
L3.H = 0xf111;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x8888ffff;
CHECKREG r1, 0x9aaaffff;
CHECKREG r2, 0xabbbffff;
CHECKREG r3, 0xbcccffff;
CHECKREG r4, 0xcdddffff;
CHECKREG r5, 0xdeeeffff;
CHECKREG r6, 0xefffffff;
CHECKREG r7, 0xf111ffff;
B0.H = 0x3000;
B1.H = 0x3002;
B2.H = 0x3004;
B3.H = 0x3006;
M0.H = 0x3008;
M1.H = 0x300a;
M2.H = 0x300c;
M3.H = 0x300e;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x3000ffff;
CHECKREG r1, 0x3002ffff;
CHECKREG r2, 0x3004ffff;
CHECKREG r3, 0x3006ffff;
CHECKREG r4, 0x3008ffff;
CHECKREG r5, 0x300Affff;
CHECKREG r6, 0x300cffff;
CHECKREG r7, 0x300effff;
B0.H = 0x0110;
B1.H = 0x1110;
B2.H = 0x2220;
B3.H = 0x3330;
M0.H = 0x4440;
M1.H = 0x5550;
M2.H = 0x6660;
M3.H = 0x7770;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x0110FFFF;
CHECKREG r1, 0x1110FFFF;
CHECKREG r2, 0x2220FFFF;
CHECKREG r3, 0x3330FFFF;
CHECKREG r4, 0x4440FFFF;
CHECKREG r5, 0x5550FFFF;
CHECKREG r6, 0x6660FFFF;
CHECKREG r7, 0x7770FFFF;
B0.H = 0xf880;
B1.H = 0xfaa0;
B2.H = 0xfbb0;
B3.H = 0xfcc0;
M0.H = 0xfdd0;
M1.H = 0xfee0;
M2.H = 0xfff0;
M3.H = 0xf110;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xf880ffff;
CHECKREG r1, 0xfaa0ffff;
CHECKREG r2, 0xfbb0ffff;
CHECKREG r3, 0xfcc0ffff;
CHECKREG r4, 0xfdd0ffff;
CHECKREG r5, 0xfee0ffff;
CHECKREG r6, 0xfff0ffff;
CHECKREG r7, 0xf110ffff;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,574 | sim/testsuite/bfin/s16.s | // reg-based SHIFT test program.
# mach: bfin
.include "testutils.inc"
start
// Test FDEP with no sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x123f );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c04; // pos=12 len=4
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c05; // pos=12 len=5
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x1235 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0010; // pos=0 len=16
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0011; // pos=0 len=17
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0114; // pos=1 len=20
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1235 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x001f; // pos=0 len=31
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x1234 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x1c04; // pos=28 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdead );
DBGA ( R7.H , 0xf234 );
R0.L = 0xdead;
R0.H = 0x0234;
R1.L = 0x1d04; // pos=29 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdead );
DBGA ( R7.H , 0xe234 );
R0.L = 0xdead;
R0.H = 0x0234;
R1.L = 0x1f04; // pos=31 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdead );
DBGA ( R7.H , 0x8234 );
R0.L = 0xdead;
R0.H = 0x0234;
R1.L = 0x2004; // pos=32 len=4, same as pos=0 len=4
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 );
DBGA ( R7.L , 0xdeaf );
DBGA ( R7.H , 0x0234 );
// Test FDEP with sign extension
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x00ff;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdead;
R0.H = 0x1234;
R1.L = 0x0c08; // pos=12 len=8
R1.H = 0x007f;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfead );
DBGA ( R7.H , 0x0007 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0110; // pos=1 len=16
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfffe );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0101; // pos=1 len=1
R1.H = 0xffff;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0xfffe );
DBGA ( R7.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0102; // pos=1 len=2
R1.H = 0x0001;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0x0002 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0002; // pos=0 len=2
R1.H = 0x0001;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xdea0;
R0.H = 0x1234;
R1.L = 0x0000; // pos=0 len=0
R1.H = 0x000f;
R7 = DEPOSIT( R0, R1 ) (X);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,692 | sim/testsuite/bfin/c_dsp32alu_rrppmm_sft_x.s | //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft_x/c_dsp32alu_rrppmm_sft_x.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, << X
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x95679911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34945515;
imm32 r3, 0x46967717;
imm32 r4, 0x5597891b;
imm32 r5, 0x6989ab1d;
imm32 r6, 0x94445515;
imm32 r7, 0x96667777;
R0 = R0 +|+ R0, R7 = R0 -|- R0 (CO , ASR);
R1 = R0 +|+ R1, R6 = R0 -|- R1 (CO , ASL);
R2 = R0 +|+ R2, R5 = R0 -|- R2 (CO , ASR);
R3 = R0 +|+ R3, R4 = R0 -|- R3 (CO , ASR);
R4 = R0 +|+ R4, R3 = R0 -|- R4 (CO , ASL);
R5 = R0 +|+ R5, R2 = R0 -|- R5 (CO , ASR);
R6 = R0 +|+ R6, R1 = R0 -|- R6 (CO , ASL);
R7 = R0 +|+ R7, R0 = R0 -|- R7 (CO , ASR);
CHECKREG r0, 0xcC88cAB3;
CHECKREG r1, 0x7AAA72FE;
CHECKREG r2, 0xf454f9B4;
CHECKREG r3, 0xe35208D4;
CHECKREG r4, 0x4CC880F2;
CHECKREG r5, 0x9BB2a4BD;
CHECKREG r6, 0xE29EE99A;
CHECKREG r7, 0xcAB3cC88;
imm32 r0, 0x11678911;
imm32 r1, 0xa719ab1d;
imm32 r2, 0x3a415515;
imm32 r3, 0x46a67717;
imm32 r4, 0x556a891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0 = R1 +|+ R0, R7 = R1 -|- R0 (CO , ASR);
R1 = R1 +|+ R1, R6 = R1 -|- R1 (CO , ASR);
R2 = R1 +|+ R2, R5 = R1 -|- R2 (CO , ASL);
R3 = R1 +|+ R3, R4 = R1 -|- R3 (CO , ASR);
R4 = R1 +|+ R4, R3 = R1 -|- R4 (CO , ASR);
R5 = R1 +|+ R5, R2 = R1 -|- R5 (CO , ASR);
R6 = R1 +|+ R6, R1 = R1 -|- R6 (CO , ASL);
R7 = R1 +|+ R7, R0 = R1 -|- R7 (CO , ASR);
CHECKREG r0, 0x41AC229A;
CHECKREG r1, 0x563A4E32;
CHECKREG r2, 0xe8B6fD84;
CHECKREG r3, 0xfD72068B;
CHECKREG r4, 0xa08EaDAB;
CHECKREG r5, 0xa994c266;
CHECKREG r6, 0x4E32563A;
CHECKREG r7, 0x33A00C85;
imm32 r0, 0xb567891b;
imm32 r1, 0x2b89abbd;
imm32 r2, 0x34b45b15;
imm32 r3, 0x466bb717;
imm32 r4, 0x556bb91b;
imm32 r5, 0x67b9ab1d;
imm32 r6, 0x7b4455b5;
imm32 r7, 0xb666777b;
R0 = R2 +|+ R0, R7 = R2 -|- R0 (CO , ASR);
R1 = R2 +|+ R1, R6 = R2 -|- R1 (CO , ASR);
R2 = R2 +|+ R2, R5 = R2 -|- R2 (CO , ASR);
R3 = R2 +|+ R3, R4 = R2 -|- R3 (CO , ASL);
R4 = R2 +|+ R4, R3 = R2 -|- R4 (CO , ASR);
R5 = R2 +|+ R5, R2 = R2 -|- R5 (CO , ASR);
R6 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASL);
R7 = R2 +|+ R7, R0 = R2 -|- R7 (CO , ASR);
CHECKREG r0, 0xED5Ae246;
CHECKREG r1, 0x2B8AaBBC;
CHECKREG r2, 0x2D8A1A5A;
CHECKREG r3, 0x3F41F65C;
CHECKREG r4, 0x3E581BD3;
CHECKREG r5, 0x1A5A2D8A;
CHECKREG r6, 0x0A6C3DDE;
CHECKREG r7, 0x4B432D00;
imm32 r0, 0xbc678c11;
imm32 r1, 0x27c9cb1d;
imm32 r2, 0x344c5515;
imm32 r3, 0x46c6c717;
imm32 r4, 0x55678c1b;
imm32 r5, 0x6c89abcd;
imm32 r6, 0x7444551c;
imm32 r7, 0x8c667777;
R0 = R3 +|+ R0, R7 = R3 -|- R0 (CO , ASL);
R1 = R3 +|+ R1, R6 = R3 -|- R1 (CO , ASR);
R2 = R3 +|+ R2, R5 = R3 -|- R2 (CO , ASR);
R3 = R3 +|+ R3, R4 = R3 -|- R3 (CO , ASR);
R4 = R3 +|+ R4, R3 = R3 -|- R4 (CO , ASL);
R5 = R3 +|+ R5, R2 = R3 -|- R5 (CO , ASR);
R6 = R3 +|+ R6, R1 = R3 -|- R6 (CO , ASR);
R7 = R3 +|+ R7, R0 = R3 -|- R7 (CO , ASL);
CHECKREG r0, 0xF19C3044;
CHECKREG r1, 0xbF07C818;
CHECKREG r2, 0xC227eA96;
CHECKREG r3, 0x8E2E8D8C;
CHECKREG r4, 0x8D8C8E2E;
CHECKREG r5, 0xa397CB64;
CHECKREG r6, 0xC615CE85;
CHECKREG r7, 0x08744494;
imm32 r0, 0xd56789d1;
imm32 r1, 0x2d89abdd;
imm32 r2, 0x34d455d5;
imm32 r3, 0x4d667717;
imm32 r4, 0x5dd7891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0xd44d5515;
imm32 r7, 0xd666d777;
R0 = R4 +|+ R0, R7 = R4 -|- R0 (CO , ASR);
R1 = R4 +|+ R1, R6 = R4 -|- R1 (CO , ASR);
R2 = R4 +|+ R2, R5 = R4 -|- R2 (CO , ASR);
R3 = R4 +|+ R3, R4 = R4 -|- R3 (CO , ASL);
R4 = R4 +|+ R4, R3 = R4 -|- R4 (CO , ASR);
R5 = R4 +|+ R5, R2 = R4 -|- R5 (CO , ASL);
R6 = R4 +|+ R6, R1 = R4 -|- R6 (CO , ASR);
R7 = R4 +|+ R7, R0 = R4 -|- R7 (CO , ASR);
CHECKREG r0, 0xeE551231;
CHECKREG r1, 0x045D1AB4;
CHECKREG r2, 0x18C214CA;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x240820E2;
CHECKREG r5, 0x7B566AC6;
CHECKREG r6, 0x09531C84;
CHECKREG r7, 0x11D6328D;
imm32 r0, 0xc567a911;
imm32 r1, 0x278aab1d;
imm32 r2, 0x3c445515;
imm32 r3, 0x46a67717;
imm32 r4, 0x55c7891b;
imm32 r5, 0x6a8cab1d;
imm32 r6, 0x7444c515;
imm32 r7, 0xa6667c77;
R0 = R5 +|+ R0, R7 = R5 -|- R0 (CO , ASR);
R1 = R5 +|+ R1, R6 = R5 -|- R1 (CO , ASL);
R2 = R5 +|+ R2, R5 = R5 -|- R2 (CO , ASR);
R3 = R5 +|+ R3, R4 = R5 -|- R3 (CO , ASR);
R4 = R5 +|+ R4, R3 = R5 -|- R4 (CO , ASR);
R5 = R5 +|+ R5, R2 = R5 -|- R5 (CO , ASL);
R6 = R5 +|+ R6, R1 = R5 -|- R6 (CO , ASR);
R7 = R5 +|+ R7, R0 = R5 -|- R7 (CO , ASR);
CHECKREG r0, 0x04FFD585;
CHECKREG r1, 0x6B46D608;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x327AeD7F;
CHECKREG r4, 0xbD85e4A9;
CHECKREG r5, 0xAC105C90;
CHECKREG r6, 0xD608F14A;
CHECKREG r7, 0xD68B5791;
imm32 r0, 0xd5678911;
imm32 r1, 0x2ddddd1d;
imm32 r2, 0x34ddd515;
imm32 r3, 0x46d67717;
imm32 r4, 0x5d6d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0xd66677d7;
R0 = R6 +|+ R0, R7 = R6 -|- R0 (CO , ASR);
R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASR);
R2 = R6 +|+ R2, R5 = R6 -|- R2 (CO , ASR);
R3 = R6 +|+ R3, R4 = R6 -|- R3 (CO , ASL);
R4 = R6 +|+ R4, R3 = R6 -|- R4 (CO , ASR);
R5 = R6 +|+ R5, R2 = R6 -|- R5 (CO , ASR);
R6 = R6 +|+ R6, R1 = R6 -|- R6 (CO , ASL);
R7 = R6 +|+ R7, R0 = R6 -|- R7 (CO , ASR);
CHECKREG r0, 0x9EAFcAF7;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x0ED20C76;
CHECKREG r3, 0x1873F3E2;
CHECKREG r4, 0x4C1A0ABF;
CHECKREG r5, 0x33851461;
CHECKREG r6, 0xFFF08CCC;
CHECKREG r7, 0x34F9eE1D;
imm32 r0, 0xf567a911;
imm32 r1, 0x2f8aab1d;
imm32 r2, 0x34a45515;
imm32 r3, 0x4a6f7717;
imm32 r4, 0x5567f91b;
imm32 r5, 0xa789af1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677f7;
R0 = R7 +|+ R0, R7 = R7 -|- R0 (CO , ASR);
R1 = R7 +|+ R1, R6 = R7 -|- R1 (CO , ASL);
R2 = R7 +|+ R2, R5 = R7 -|- R2 (CO , ASR);
R3 = R7 +|+ R3, R4 = R7 -|- R3 (CO , ASR);
R4 = R7 +|+ R4, R3 = R7 -|- R4 (CO , ASL);
R5 = R7 +|+ R5, R2 = R7 -|- R5 (CO , ASL);
R6 = R7 +|+ R6, R1 = R7 -|- R6 (CO , ASR);
R7 = R7 +|+ R7, R0 = R7 -|- R7 (CO , ASL);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xaC561657;
CHECKREG r2, 0x5E305B7C;
CHECKREG r3, 0x73FA7D7E;
CHECKREG r4, 0x204EaE02;
CHECKREG r5, 0x4250c3CC;
CHECKREG r6, 0x511B1C28;
CHECKREG r7, 0x9DCC21FC;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x46667717;
imm32 r4, 0x556e891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444e515;
imm32 r7, 0x86667e77;
R4 = R2 +|+ R5, R3 = R2 -|- R5 (CO , ASR);
R0 = R5 +|+ R3, R5 = R5 -|- R3 (CO , ASL);
R2 = R6 +|+ R2, R0 = R6 -|- R2 (CO , ASL);
R3 = R4 +|+ R0, R2 = R4 -|- R0 (CO , ASR);
R7 = R7 +|+ R6, R6 = R7 -|- R6 (CO , ASL);
R6 = R1 +|+ R7, R1 = R1 -|- R7 (CO , ASL);
R5 = R0 +|+ R4, R7 = R0 -|- R4 (CO , ASR);
R1 = R3 +|+ R1, R4 = R3 -|- R1 (CO , ASR);
CHECKREG r0, 0x20007EC0;
CHECKREG r1, 0xfF9258EB;
CHECKREG r2, 0xC0AC171B;
CHECKREG r3, 0x371B3F6C;
CHECKREG r4, 0xE6813788;
CHECKREG r5, 0x371B3F6C;
CHECKREG r6, 0x47BAE46A;
CHECKREG r7, 0x3F53e8E5;
imm32 r0, 0xd5678911;
imm32 r1, 0xff89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x46667717;
imm32 r4, 0x556f891b;
imm32 r5, 0x6789fb1d;
imm32 r6, 0x74445f15;
imm32 r7, 0x866677f7;
R4 = R3 +|+ R3, R5 = R3 -|- R3 (CO , ASR);
R1 = R6 +|+ R1, R6 = R6 -|- R1 (CO , ASL);
R6 = R1 +|+ R4, R4 = R1 -|- R4 (CO , ASL);
R7 = R4 +|+ R2, R0 = R4 -|- R2 (CO , ASR);
R2 = R2 +|+ R6, R1 = R2 -|- R6 (CO , ASR);
R3 = R5 +|+ R5, R7 = R5 -|- R5 (CO , ASL);
R5 = R7 +|+ R7, R3 = R7 -|- R7 (CO , ASL);
R0 = R0 +|+ R0, R2 = R0 -|- R0 (CO , ASR);
CHECKREG r0, 0xF6A902D3;
CHECKREG r1, 0x1F0FEC7A;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x3A9A4268;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x5C0016F6;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,098 | sim/testsuite/bfin/c_dsp32shift_ahh.s | //Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp
// Spec Reference: dsp32shift ashift/ashift
# mach: bfin
.include "testutils.inc"
start
// ashift/ashift : positive data, count (+)=left (half reg)
// d_reg = ashift/ashift (d BY d_lo)
// Rx by RLx
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5 = ASHIFT R0 BY R0.L (V);
R0 = ASHIFT R1 BY R0.L (V);
R1 = ASHIFT R2 BY R0.L (V);
R2 = ASHIFT R3 BY R0.L (V);
R3 = ASHIFT R4 BY R0.L (V);
R4 = ASHIFT R5 BY R0.L (V);
R7 = ASHIFT R6 BY R0.L (V);
R6 = ASHIFT R7 BY R0.L (V);
CHECKREG r0, 0x12345678;
CHECKREG r1, 0x00230067;
CHECKREG r2, 0x00340078;
CHECKREG r3, 0x0045FF89;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x01230000;
CHECKREG r6, 0x0000FFFF;
CHECKREG r7, 0x0067FFAB;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 5;
R2 = ASHIFT R0 BY R1.L (V);
R3 = ASHIFT R1 BY R1.L (V);
R4 = ASHIFT R2 BY R1.L (V);
R5 = ASHIFT R3 BY R1.L (V);
R6 = ASHIFT R4 BY R1.L (V);
R7 = ASHIFT R5 BY R1.L (V);
R0 = ASHIFT R6 BY R1.L (V);
R1 = ASHIFT R7 BY R1.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x24600040;
CHECKREG r3, 0x468000A0;
CHECKREG r4, 0x8C000800;
CHECKREG r5, 0xD0001400;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x00008000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2 = 15;
R3 = ASHIFT R0 BY R2.L (V);
R4 = ASHIFT R1 BY R2.L (V);
R5 = ASHIFT R2 BY R2.L (V);
R6 = ASHIFT R3 BY R2.L (V);
R7 = ASHIFT R4 BY R2.L (V);
R0 = ASHIFT R5 BY R2.L (V);
R1 = ASHIFT R6 BY R2.L (V);
R2 = ASHIFT R7 BY R2.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R4 = ASHIFT R0 BY R3.L (V);
R5 = ASHIFT R1 BY R3.L (V);
R6 = ASHIFT R2 BY R3.L (V);
R7 = ASHIFT R3 BY R3.L (V);
R0 = ASHIFT R4 BY R3.L (V);
R1 = ASHIFT R5 BY R3.L (V);
R2 = ASHIFT R6 BY R3.L (V);
R3 = ASHIFT R7 BY R3.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R0 = ASHIFT R0 BY R4.L (V);
R1 = ASHIFT R1 BY R4.L (V);
R2 = ASHIFT R2 BY R4.L (V);
R3 = ASHIFT R3 BY R4.L (V);
R4 = ASHIFT R4 BY R4.L (V);
R5 = ASHIFT R5 BY R4.L (V);
R6 = ASHIFT R6 BY R4.L (V);
R7 = ASHIFT R7 BY R4.L (V);
CHECKREG r0, 0x00910001;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A233C4;
CHECKREG r3, 0x1A2B3C4D;
CHECKREG r4, 0x22B3FFFF;
CHECKREG r5, 0x2B3CCD5E;
CHECKREG r6, 0x33C4D5E6;
CHECKREG r7, 0x3C4DDE6F;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -6;
R6 = ASHIFT R0 BY R5.L (V);
R7 = ASHIFT R1 BY R5.L (V);
R0 = ASHIFT R2 BY R5.L (V);
R1 = ASHIFT R3 BY R5.L (V);
R2 = ASHIFT R4 BY R5.L (V);
R3 = ASHIFT R5 BY R5.L (V);
R4 = ASHIFT R6 BY R5.L (V);
R5 = ASHIFT R7 BY R5.L (V);
CHECKREG r0, 0x008D019E;
CHECKREG r1, 0x00D101E2;
CHECKREG r2, 0x0115FE26;
CHECKREG r3, 0x0159FFFF;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00010005;
CHECKREG r6, 0x00040000;
CHECKREG r7, 0x00480159;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R7 = ASHIFT R0 BY R6.L (V);
R0 = ASHIFT R1 BY R6.L (V);
R1 = ASHIFT R2 BY R6.L (V);
R2 = ASHIFT R3 BY R6.L (V);
R3 = ASHIFT R4 BY R6.L (V);
R4 = ASHIFT R5 BY R6.L (V);
R5 = ASHIFT R6 BY R6.L (V);
R6 = ASHIFT R7 BY R6.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x0000FFFF;
CHECKREG r4, 0x0000FFFF;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = ASHIFT R0 BY R7.L (V);
R1 = ASHIFT R1 BY R7.L (V);
R2 = ASHIFT R2 BY R7.L (V);
R3 = ASHIFT R3 BY R7.L (V);
R4 = ASHIFT R4 BY R7.L (V);
R5 = ASHIFT R5 BY R7.L (V);
R6 = ASHIFT R6 BY R7.L (V);
R7 = ASHIFT R7 BY R7.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0000FFFF;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x0000FFFF;
CHECKREG r7, 0x0000FFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0.L = 4;
//r0 = ashift/ashift (r0 by rl0);
R1 = ASHIFT R1 BY R0.L (V);
R2 = ASHIFT R2 BY R0.L (V);
R3 = ASHIFT R3 BY R0.L (V);
R4 = ASHIFT R4 BY R0.L (V);
R5 = ASHIFT R5 BY R0.L (V);
R6 = ASHIFT R6 BY R0.L (V);
R7 = ASHIFT R7 BY R0.L (V);
CHECKREG r0, 0x01230004;
CHECKREG r1, 0x23406780;
CHECKREG r2, 0x34507890;
CHECKREG r3, 0x456089A0;
CHECKREG r4, 0x56709AB0;
CHECKREG r5, 0x6780ABC0;
CHECKREG r6, 0x7890BCD0;
CHECKREG r7, 0x89A0CDE0;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 6;
R0 = ASHIFT R0 BY R1.L (V);
//r1 = ashift/ashift (r1 by rl1);
R2 = ASHIFT R2 BY R1.L (V);
R3 = ASHIFT R3 BY R1.L (V);
R4 = ASHIFT R4 BY R1.L (V);
R5 = ASHIFT R5 BY R1.L (V);
R6 = ASHIFT R6 BY R1.L (V);
R7 = ASHIFT R7 BY R1.L (V);
CHECKREG r0, 0x48C00080;
CHECKREG r1, 0x12340006;
CHECKREG r2, 0xD140E240;
CHECKREG r3, 0x15802680;
CHECKREG r4, 0x59C06AC0;
CHECKREG r5, 0x9E00AF00;
CHECKREG r6, 0xE240F340;
CHECKREG r7, 0x26803780;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 15;
R0 = ASHIFT R0 BY R2.L (V);
R1 = ASHIFT R1 BY R2.L (V);
//r2 = ashift/ashift (r2 by rl2);
R3 = ASHIFT R3 BY R2.L (V);
R4 = ASHIFT R4 BY R2.L (V);
R5 = ASHIFT R5 BY R2.L (V);
R6 = ASHIFT R6 BY R2.L (V);
R7 = ASHIFT R7 BY R2.L (V);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x2345000F;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R3.L = 16;
R0 = ASHIFT R0 BY R3.L (V);
R1 = ASHIFT R1 BY R3.L (V);
R2 = ASHIFT R2 BY R3.L (V);
//r3 = ashift/ashift (r3 by rl3);
R4 = ASHIFT R4 BY R3.L (V);
R5 = ASHIFT R5 BY R3.L (V);
R6 = ASHIFT R6 BY R3.L (V);
R7 = ASHIFT R7 BY R3.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x34560010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -9;
R0 = ASHIFT R0 BY R4.L (V);
R1 = ASHIFT R1 BY R4.L (V);
R2 = ASHIFT R2 BY R4.L (V);
R3 = ASHIFT R3 BY R4.L (V);
//r4 = ashift/ashift (r4 by rl4);
R5 = ASHIFT R5 BY R4.L (V);
R6 = ASHIFT R6 BY R4.L (V);
R7 = ASHIFT R7 BY R4.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0009002B;
CHECKREG r2, 0x00110033;
CHECKREG r3, 0x001A003C;
CHECKREG r4, 0x4567FFF7;
CHECKREG r5, 0x002BFFCD;
CHECKREG r6, 0x0033FFD5;
CHECKREG r7, 0x003CFFDE;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -14;
R0 = ASHIFT R0 BY R5.L (V);
R1 = ASHIFT R1 BY R5.L (V);
R2 = ASHIFT R2 BY R5.L (V);
R3 = ASHIFT R3 BY R5.L (V);
R4 = ASHIFT R4 BY R5.L (V);
//r5 = ashift/ashift (r5 by rl5);
R6 = ASHIFT R6 BY R5.L (V);
R7 = ASHIFT R7 BY R5.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x0001FFFE;
CHECKREG r5, 0x5678FFF2;
CHECKREG r6, 0x0001FFFE;
CHECKREG r7, 0x0001FFFE;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R0 = ASHIFT R0 BY R6.L (V);
R1 = ASHIFT R1 BY R6.L (V);
R2 = ASHIFT R2 BY R6.L (V);
R3 = ASHIFT R3 BY R6.L (V);
R4 = ASHIFT R4 BY R6.L (V);
R5 = ASHIFT R5 BY R6.L (V);
//r6 = ashift/ashift (r6 by rl6);
R7 = ASHIFT R7 BY R6.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0000FFFF;
CHECKREG r5, 0x0000FFFF;
CHECKREG r6, 0x6789FFF1;
CHECKREG r7, 0x0000FFFF;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -16;
R0 = ASHIFT R0 BY R7.L (V);
R1 = ASHIFT R1 BY R7.L (V);
R2 = ASHIFT R2 BY R7.L (V);
R3 = ASHIFT R3 BY R7.L (V);
R4 = ASHIFT R4 BY R7.L (V);
R5 = ASHIFT R5 BY R7.L (V);
R6 = ASHIFT R6 BY R7.L (V);
R7 = ASHIFT R7 BY R7.L (V);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,386 | sim/testsuite/bfin/c_dsp32shift_ahalf_rn_s.s | //Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp
// Spec Reference: dsp32shift ashift s
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
//rl0 = ashift (rl0 by rl0);
R1.L = ASHIFT R1.L BY R0.L (S);
R2.L = ASHIFT R2.L BY R0.L (S);
R3.L = ASHIFT R3.L BY R0.L (S);
R4.L = ASHIFT R4.L BY R0.L (S);
R5.L = ASHIFT R5.L BY R0.L (S);
R6.L = ASHIFT R6.L BY R0.L (S);
R7.L = ASHIFT R7.L BY R0.L (S);
//CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c000;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
R1.L = -1;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R1.L (S);
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L (S);
R3.L = ASHIFT R3.L BY R1.L (S);
R4.L = ASHIFT R4.L BY R1.L (S);
R5.L = ASHIFT R5.L BY R1.L (S);
R6.L = ASHIFT R6.L BY R1.L (S);
R7.L = ASHIFT R7.L BY R1.L (S);
CHECKREG r0, 0x0000c000;
//CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
R2.L = -15;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R2.L (S);
R1.L = ASHIFT R1.L BY R2.L (S);
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L (S);
R4.L = ASHIFT R4.L BY R2.L (S);
R5.L = ASHIFT R5.L BY R2.L (S);
R6.L = ASHIFT R6.L BY R2.L (S);
R7.L = ASHIFT R7.L BY R2.L (S);
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
//CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x0000ffff;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
R3.L = -16;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R3.L (S);
R1.L = ASHIFT R1.L BY R3.L (S);
R2.L = ASHIFT R2.L BY R3.L (S);
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L (S);
R5.L = ASHIFT R5.L BY R3.L (S);
R6.L = ASHIFT R6.L BY R3.L (S);
R7.L = ASHIFT R7.L BY R3.L (S);
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
CHECKREG r2, 0x0000ffff;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R0.L (S);
R1.L = ASHIFT R1.H BY R0.L (S);
R2.L = ASHIFT R2.H BY R0.L (S);
R3.L = ASHIFT R3.H BY R0.L (S);
R4.L = ASHIFT R4.H BY R0.L (S);
R5.L = ASHIFT R5.H BY R0.L (S);
R6.L = ASHIFT R6.H BY R0.L (S);
R7.L = ASHIFT R7.H BY R0.L (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x80018001;
CHECKREG r2, 0x80028002;
CHECKREG r3, 0x80038003;
CHECKREG r4, 0x80048004;
CHECKREG r5, 0x80058005;
CHECKREG r6, 0x80068006;
CHECKREG r7, 0x80078007;
imm32 r0, 0x80010000;
R1.L = -1;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R1.L (S);
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L (S);
R3.L = ASHIFT R3.H BY R1.L (S);
R4.L = ASHIFT R4.H BY R1.L (S);
R5.L = ASHIFT R5.H BY R1.L (S);
R6.L = ASHIFT R6.H BY R1.L (S);
R7.L = ASHIFT R7.H BY R1.L (S);
CHECKREG r0, 0x8001c000;
//CHECKREG r1, 0x00010001;
CHECKREG r2, 0x8002c001;
CHECKREG r3, 0x8003c001;
CHECKREG r4, 0x8004c002;
CHECKREG r5, 0x8005c002;
CHECKREG r6, 0x8006c003;
CHECKREG r7, 0x8007c003;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
R2.L = -15;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L (S);
R1.L = ASHIFT R1.H BY R2.L (S);
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L (S);
R4.L = ASHIFT R4.H BY R2.L (S);
R5.L = ASHIFT R5.H BY R2.L (S);
R6.L = ASHIFT R6.H BY R2.L (S);
R7.L = ASHIFT R7.H BY R2.L (S);
CHECKREG r0, 0xa001ffff;
CHECKREG r1, 0xa001ffff;
//CHECKREG r2, 0x2002000f;
CHECKREG r3, 0xa003ffff;
CHECKREG r4, 0xa004ffff;
CHECKREG r5, 0xa005ffff;
CHECKREG r6, 0xa006ffff;
CHECKREG r7, 0xa007ffff;
imm32 r0, 0xb0010001;
imm32 r1, 0xb0010001;
imm32 r2, 0xb0020002;
R3.L = -16;
imm32 r4, 0xb0040004;
imm32 r5, 0xb0050005;
imm32 r6, 0xb0060006;
imm32 r7, 0xb0070007;
R0.L = ASHIFT R0.H BY R3.L (S);
R1.L = ASHIFT R1.H BY R3.L (S);
R2.L = ASHIFT R2.H BY R3.L (S);
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L (S);
R5.L = ASHIFT R5.H BY R3.L (S);
R6.L = ASHIFT R6.H BY R3.L (S);
R7.L = ASHIFT R7.H BY R3.L (S);
CHECKREG r0, 0xb001ffff;
CHECKREG r1, 0xb001ffff;
CHECKREG r2, 0xb002ffff;
//CHECKREG r3, 0x30030010;
CHECKREG r4, 0xb004ffff;
CHECKREG r5, 0xb005ffff;
CHECKREG r6, 0xb006ffff;
CHECKREG r7, 0xb007ffff;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000000;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R4.L (S);
R1.H = ASHIFT R1.L BY R4.L (S);
R2.H = ASHIFT R2.L BY R4.L (S);
R3.H = ASHIFT R3.L BY R4.L (S);
//rh4 = ashift (rl4 by rl4);
R5.H = ASHIFT R5.L BY R4.L (S);
R6.H = ASHIFT R6.L BY R4.L (S);
R7.H = ASHIFT R7.L BY R4.L (S);
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
//CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
R5.L = -1;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = ASHIFT R0.L BY R5.L (S);
R1.H = ASHIFT R1.L BY R5.L (S);
R2.H = ASHIFT R2.L BY R5.L (S);
R3.H = ASHIFT R3.L BY R5.L (S);
R4.H = ASHIFT R4.L BY R5.L (S);
//rh5 = ashift (rl5 by rl5);
R6.H = ASHIFT R6.L BY R5.L (S);
R7.H = ASHIFT R7.L BY R5.L (S);
CHECKREG r0, 0xc0008001;
CHECKREG r1, 0xc0008001;
CHECKREG r2, 0xc0018002;
CHECKREG r3, 0xc0018003;
CHECKREG r4, 0xc0028004;
//CHECKREG r5, 0x00020005;
CHECKREG r6, 0xc0038006;
CHECKREG r7, 0xc0038007;
imm32 r0, 0x00009001;
imm32 r1, 0x00009001;
imm32 r2, 0x00009002;
imm32 r3, 0x00009003;
imm32 r4, 0x00009004;
imm32 r5, 0x00009005;
R6.L = -15;
imm32 r7, 0x00009007;
R0.H = ASHIFT R0.L BY R6.L (S);
R1.H = ASHIFT R1.L BY R6.L (S);
R2.H = ASHIFT R2.L BY R6.L (S);
R3.H = ASHIFT R3.L BY R6.L (S);
R4.H = ASHIFT R4.L BY R6.L (S);
R5.H = ASHIFT R5.L BY R6.L (S);
//rh6 = ashift (rl6 by rl6);
R7.H = ASHIFT R7.L BY R6.L;
CHECKREG r0, 0xffff9001;
CHECKREG r1, 0xffff9001;
CHECKREG r2, 0xffff9002;
CHECKREG r3, 0xffff9003;
CHECKREG r4, 0xffff9004;
CHECKREG r5, 0xffff9005;
//CHECKREG r6, 0x00006006;
CHECKREG r7, 0xffff9007;
imm32 r0, 0x0000a001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000a002;
imm32 r3, 0x0000a003;
imm32 r4, 0x0000a004;
imm32 r5, 0x0000a005;
imm32 r6, 0x0000a006;
R7.L = -16;
R0.H = ASHIFT R0.L BY R7.L (S);
R1.H = ASHIFT R1.L BY R7.L (S);
R2.H = ASHIFT R2.L BY R7.L (S);
R3.H = ASHIFT R3.L BY R7.L (S);
R4.H = ASHIFT R4.L BY R7.L (S);
R5.H = ASHIFT R5.L BY R7.L (S);
R6.H = ASHIFT R6.L BY R7.L (S);
R7.H = ASHIFT R7.L BY R7.L (S);
CHECKREG r0, 0xffffa001;
CHECKREG r1, 0xffffa001;
CHECKREG r2, 0xffffa002;
CHECKREG r3, 0xffffa003;
CHECKREG r4, 0xffffa004;
CHECKREG r5, 0xffffa005;
CHECKREG r6, 0xffffa006;
//CHECKREG r7, 0x00007007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
R4.L = -1;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R4.L (S);
R1.H = ASHIFT R1.H BY R4.L (S);
R2.H = ASHIFT R2.H BY R4.L (S);
R3.H = ASHIFT R3.H BY R4.L (S);
//rh4 = ashift (rh4 by rl4);
R5.H = ASHIFT R5.H BY R4.L (S);
R6.H = ASHIFT R6.H BY R4.L (S);
R7.H = ASHIFT R7.H BY R4.L (S);
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
//CHECKREG r4, 0x00020000;
CHECKREG r5, 0xc0020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
R5.L = -1;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R5.L (S);
R1.H = ASHIFT R1.H BY R5.L (S);
R2.H = ASHIFT R2.H BY R5.L (S);
R3.H = ASHIFT R3.H BY R5.L (S);
R4.H = ASHIFT R4.H BY R5.L (S);
//rh5 = ashift (rh5 by rl5);
R6.H = ASHIFT R6.H BY R5.L (S);
R7.H = ASHIFT R7.H BY R5.L (S);
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
CHECKREG r4, 0xc0020000;
//CHECKREG r5, 0x28020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030000;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
R6.L = -15;
imm32 r7, 0xd0070000;
R0.L = ASHIFT R0.H BY R6.L (S);
R1.L = ASHIFT R1.H BY R6.L (S);
R2.L = ASHIFT R2.H BY R6.L (S);
R3.L = ASHIFT R3.H BY R6.L (S);
R4.L = ASHIFT R4.H BY R6.L (S);
R5.L = ASHIFT R5.H BY R6.L (S);
//rl6 = ashift (rh6 by rl6);
R7.L = ASHIFT R7.H BY R6.L;
CHECKREG r0, 0xd001ffff;
CHECKREG r1, 0xd001ffff;
CHECKREG r2, 0xd002ffff;
CHECKREG r3, 0xd003ffff;
CHECKREG r4, 0xd004ffff;
CHECKREG r5, 0xd005ffff;
//CHECKREG r6, 0x60060000;
CHECKREG r7, 0xd007ffff;
imm32 r0, 0xe0010000;
imm32 r1, 0xe0010000;
imm32 r2, 0xe0020000;
imm32 r3, 0xe0030000;
imm32 r4, 0xe0040000;
imm32 r5, 0xe0050000;
imm32 r6, 0xe0060000;
R7.L = -16;
R0.H = ASHIFT R0.H BY R7.L (S);
R1.H = ASHIFT R1.H BY R7.L (S);
R2.H = ASHIFT R2.H BY R7.L (S);
R3.H = ASHIFT R3.H BY R7.L (S);
R4.H = ASHIFT R4.H BY R7.L (S);
R5.H = ASHIFT R5.H BY R7.L (S);
R6.H = ASHIFT R6.H BY R7.L (S);
//rh7 = ashift (rh7 by rl7);
CHECKREG r0, 0xffff0000;
CHECKREG r1, 0xffff0000;
CHECKREG r2, 0xffff0000;
CHECKREG r3, 0xffff0000;
CHECKREG r4, 0xffff0000;
CHECKREG r5, 0xffff0000;
CHECKREG r6, 0xffff0000;
//CHECKREG r7, -16;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,350 | sim/testsuite/bfin/c_ldimmhalf_lzhi_ibml.s | //Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: ldimmhalf lzhi ibml
I0 = 0x2001 (Z);
I0.H = 0x2000;
I1 = 0x2003 (Z);
I1.H = 0x2002;
I2 = 0x2005 (Z);
I2.H = 0x2004;
I3 = 0x2007 (Z);
I3.H = 0x2006;
L0 = 0x2009 (Z);
L0.H = 0x2008;
L1 = 0x200b (Z);
L1.H = 0x200a;
L2 = 0x200d (Z);
L2.H = 0x200c;
L3 = 0x200f (Z);
L3.H = 0x200e;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x20002001;
CHECKREG r1, 0x20022003;
CHECKREG r2, 0x20042005;
CHECKREG r3, 0x20062007;
CHECKREG r4, 0x20082009;
CHECKREG r5, 0x200a200b;
CHECKREG r6, 0x200c200d;
CHECKREG r7, 0x200e200f;
I0 = 0x0111 (Z);
I0.H = 0x1000;
I1 = 0x1111 (Z);
I1.H = 0x1000;
I2 = 0x2222 (Z);
I2.H = 0x2000;
I3 = 0x3333 (Z);
I3.H = 0x3000;
L0 = 0x4444 (Z);
L0.H = 0x4000;
L1 = 0x5555 (Z);
L1.H = 0x5000;
L2 = 0x6666 (Z);
L2.H = 0x6000;
L3 = 0x7777 (Z);
L3.H = 0x7000;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x10000111;
CHECKREG r1, 0x10001111;
CHECKREG r2, 0x20002222;
CHECKREG r3, 0x30003333;
CHECKREG r4, 0x40004444;
CHECKREG r5, 0x50005555;
CHECKREG r6, 0x60006666;
CHECKREG r7, 0x70007777;
I0 = 0x8888 (Z);
I0.H = 0x8000;
I1 = 0x9aaa (Z);
I1.H = 0x9000;
I2 = 0xabbb (Z);
I2.H = 0xa000;
I3 = 0xbccc (Z);
I3.H = 0xb000;
L0 = 0xcddd (Z);
L0.H = 0xc000;
L1 = 0xdeee (Z);
L1.H = 0xd000;
L2 = 0xefff (Z);
L2.H = 0xe000;
L3 = 0xf111 (Z);
L3.H = 0xf000;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x80008888;
CHECKREG r1, 0x90009aaa;
CHECKREG r2, 0xa000abbb;
CHECKREG r3, 0xb000bccc;
CHECKREG r4, 0xc000cddd;
CHECKREG r5, 0xd000deee;
CHECKREG r6, 0xe000efff;
CHECKREG r7, 0xf000f111;
B0 = 0x3001 (Z);
B0.H = 0x3000;
B1 = 0x3003 (Z);
B1.H = 0x3002;
B2 = 0x3005 (Z);
B2.H = 0x3004;
B3 = 0x3007 (Z);
B3.H = 0x3006;
M0 = 0x3009 (Z);
M0.H = 0x3008;
M1 = 0x300b (Z);
M1.H = 0x300a;
M2 = 0x300d (Z);
M2.H = 0x300c;
M3 = 0x300f (Z);
M3.H = 0x300e;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x30003001;
CHECKREG r1, 0x30023003;
CHECKREG r2, 0x30043005;
CHECKREG r3, 0x30063007;
CHECKREG r4, 0x30083009;
CHECKREG r5, 0x300A300B;
CHECKREG r6, 0x300c300d;
CHECKREG r7, 0x300e300f;
B0 = 0x0110 (Z);
B0.H = 0x1000;
B1 = 0x1110 (Z);
B1.H = 0x1000;
B2 = 0x2220 (Z);
B2.H = 0x2000;
B3 = 0x3330 (Z);
B3.H = 0x3000;
M0 = 0x4440 (Z);
M0.H = 0x4000;
M1 = 0x5550 (Z);
M1.H = 0x5000;
M2 = 0x6660 (Z);
M2.H = 0x6000;
M3 = 0x7770 (Z);
M3.H = 0x7000;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x10000110;
CHECKREG r1, 0x10001110;
CHECKREG r2, 0x20002220;
CHECKREG r3, 0x30003330;
CHECKREG r4, 0x40004440;
CHECKREG r5, 0x50005550;
CHECKREG r6, 0x60006660;
CHECKREG r7, 0x70007770;
B0 = 0xf880 (Z);
B0.H = 0x8000;
B1 = 0xfaa0 (Z);
B1.H = 0xa000;
B2 = 0xfbb0 (Z);
B2.H = 0xb000;
B3 = 0xfcc0 (Z);
B3.H = 0xc000;
M0 = 0xfdd0 (Z);
M0.H = 0xd000;
M1 = 0xfee0 (Z);
M1.H = 0xe000;
M2 = 0xfff0 (Z);
M2.H = 0xf000;
M3 = 0xf110 (Z);
M3.H = 0x1000;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x8000f880;
CHECKREG r1, 0xa000faa0;
CHECKREG r2, 0xb000fbb0;
CHECKREG r3, 0xc000fcc0;
CHECKREG r4, 0xd000fdd0;
CHECKREG r5, 0xe000fee0;
CHECKREG r6, 0xf000fff0;
CHECKREG r7, 0x1000f110;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,175 | sim/testsuite/bfin/c_ccmv_cc_pr_pr.s | //Original:/proj/frio/dv/testcases/core/c_ccmv_cc_pr_pr/c_ccmv_cc_pr_pr.dsp
// Spec Reference: ccmv cc preg = preg
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 p1, 0xd0021053;
imm32 p2, 0x2f041405;
imm32 p3, 0x60b61507;
imm32 p4, 0x50487609;
imm32 p5, 0x3005900b;
imm32 sp, 0x2a0c660d;
imm32 fp, 0xd90e108f;
IF CC P3 = P3;
IF CC P1 = P3;
IF CC P2 = P5;
IF CC P3 = P2;
CC = ! CC;
IF CC P4 = SP;
IF CC P5 = P1;
IF CC SP = FP;
CC = ! CC;
IF CC FP = P4;
CHECKREG p1, 0xD0021053;
CHECKREG p2, 0x2F041405;
CHECKREG p3, 0x60B61507;
CHECKREG p4, 0x2A0C660D;
CHECKREG p5, 0xD0021053;
CHECKREG sp, 0xD90E108F;
CHECKREG fp, 0xD90E108F;
imm32 p1, 0xd4023053;
imm32 p2, 0x2f041405;
imm32 p3, 0x60f61507;
imm32 p4, 0xd0487f09;
imm32 p5, 0x300b900b;
imm32 sp, 0x2a0cd60d;
imm32 fp, 0xd90e189f;
IF CC P4 = P3;
IF CC P5 = FP;
IF CC SP = P1;
IF CC FP = P2;
CC = ! CC;
IF CC P3 = SP;
IF CC P1 = P5;
IF CC P2 = P4;
CC = ! CC;
IF CC P3 = P2;
CHECKREG p1, 0x300B900B;
CHECKREG p2, 0xD0487F09;
CHECKREG p3, 0x2A0CD60D;
CHECKREG p4, 0xD0487F09;
CHECKREG p5, 0x300B900B;
CHECKREG sp, 0x2A0CD60D;
CHECKREG fp, 0xD90E189F;
imm32 p1, 0xd8021053;
imm32 p2, 0x2f041405;
imm32 p3, 0x65b61507;
imm32 p4, 0x59487609;
imm32 p5, 0x3005900b;
imm32 sp, 0x2abc660d;
imm32 fp, 0xd90e108f;
IF CC P3 = P2;
IF CC P1 = P3;
CC = ! CC;
IF CC P2 = P5;
IF CC P3 = FP;
CC = ! CC;
IF CC P4 = P1;
IF CC P5 = P4;
IF CC SP = FP;
IF CC FP = SP;
CHECKREG p1, 0xD8021053;
CHECKREG p2, 0x3005900B;
CHECKREG p3, 0xD90E108F;
CHECKREG p4, 0x59487609;
CHECKREG p5, 0x3005900B;
CHECKREG sp, 0x2ABC660D;
CHECKREG fp, 0xD90E108F;
imm32 p1, 0xdb021053;
imm32 p2, 0x2f041405;
imm32 p3, 0x64b61507;
imm32 p4, 0x50487609;
imm32 p5, 0x30f5900b;
imm32 sp, 0x2a4c660d;
imm32 fp, 0x895e108f;
IF CC P4 = P3;
IF CC P5 = FP;
CC = ! CC;
IF CC SP = P2;
IF CC FP = SP;
CC = ! CC;
IF CC P3 = P1;
IF CC P1 = P2;
IF CC P2 = P3;
IF CC P3 = P4;
CHECKREG p1, 0xDB021053;
CHECKREG p2, 0x2F041405;
CHECKREG p3, 0x64B61507;
CHECKREG p4, 0x50487609;
CHECKREG p5, 0x30F5900B;
CHECKREG sp, 0x2F041405;
CHECKREG fp, 0x2F041405;
pass
|
tactcomplabs/xbgas-binutils-gdb | 13,726 | sim/testsuite/bfin/se_loop_mv2lc.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lc/se_loop_mv2lc.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
// Loop 0
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LT0 = r0;
LB0 = r1;
LC0 = P0;
NOP;
JUMP.S 2;
JUMP.S 6;
NOP;
LC0 = P0;
LC0 = P1;
L0T:R2 += 3;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
L0B:R7 += 8;
// Loop 1
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LT1 = r0;
LB1 = r1;
LC1 = P0;
NOP;
JUMP.S 2;
JUMP.S 6;
NOP;
LC1 = P0;
LC1 = P1;
L1T:R2 += 3;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
L1B:R7 += 8;
// Loop 0
LSETUP ( L2T , L2T ) LC0 = P0;
NOP;
NOP;
NOP;
LC0 = P1;
L2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
L2B:R7 += 6;
LC0 = P1;
NOP;
NOP;
NOP;
LSETUP ( L3T , L3T ) LC0 = P0;
L3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
L3B:R7 += 6;
LSETUP ( L4T , L4B ) LC0 = P0;
NOP;
NOP;
LC0 = P1;
L4T:R2 += 1;
L4B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
NOP;
LSETUP ( L5T , L5B ) LC0 = P0;
L5T:R2 += 1;
L5B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( L6T , L6B ) LC0 = P0;
NOP;
LC0 = P1;
L6T:R2 += 1;
R3 += 2;
L6B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
LSETUP ( L7T , L7B ) LC0 = P0;
L7T:R2 += 1;
R3 += 2;
L7B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( L8T , L8B ) LC0 = P0;
LC0 = P1;
L8T:R2 += 1;
R3 += 2;
R4 += 3;
L8B:R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
LSETUP ( L9T , L9B ) LC0 = P0;
L9T:R2 += 1;
R3 += 2;
R4 += 3;
L9B:R5 += 4;
R6 += 5;
R7 += 6;
// Loop 1
LSETUP ( M2T , M2T ) LC1 = P0;
NOP;
NOP;
NOP;
LC1 = P1;
M2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
M2B:R7 += 6;
LC1 = P1;
NOP;
NOP;
NOP;
LSETUP ( M3T , M3T ) LC1 = P0;
M3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
M3B:R7 += 6;
LSETUP ( M4T , M4B ) LC1 = P0;
NOP;
NOP;
LC1 = P1;
M4T:R2 += 1;
M4B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
NOP;
LSETUP ( M5T , M5B ) LC1 = P0;
M5T:R2 += 1;
M5B:R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( M6T , M6B ) LC1 = P0;
NOP;
LC1 = P1;
M6T:R2 += 1;
R3 += 2;
M6B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
LSETUP ( M7T , M7B ) LC1 = P0;
M7T:R2 += 1;
R3 += 2;
M7B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( M8T , M8B ) LC1 = P0;
LC1 = P1;
M8T:R2 += 1;
R3 += 2;
R4 += 3;
M8B:R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
LSETUP ( M9T , M9B ) LC1 = P0;
M9T:R2 += 1;
R3 += 2;
R4 += 3;
M9B:R5 += 4;
R6 += 5;
R7 += 6;
// Loop 0
LSETUP ( N2T , N2B ) LC0 = P0 >> 1;
NOP;
NOP;
NOP;
LC0 = P1;
N2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
N2B:R7 += 6;
LC0 = P1;
NOP;
NOP;
NOP;
LSETUP ( N3T , N3B ) LC0 = P0 >> 1;
N3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
N3B:R7 += 6;
LSETUP ( N4T , N4B ) LC0 = P0 >> 1;
NOP;
NOP;
LC0 = P1;
N4T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
N4B:R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
NOP;
LSETUP ( N5T , N5B ) LC0 = P0 >> 1;
N5T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
N5B:R6 += 5;
R7 += 6;
LSETUP ( N6T , N6B ) LC0 = P0 >> 1;
NOP;
LC0 = P1;
N6T:R2 += 1;
R3 += 2;
R4 += 3;
N6B:R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
NOP;
LSETUP ( N7T , N7B ) LC0 = P0 >> 1;
N7T:R2 += 1;
R3 += 2;
R4 += 3;
N7B:R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( N8T , N8T ) LC0 = P0 >> 1;
LC0 = P1;
N8T:R2 += 1;
R3 += 2;
N8B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC0 = P1;
LSETUP ( N9T , N9T ) LC0 = P0 >> 1;
N9T:R2 += 1;
R3 += 2;
N9B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
// Loop 1
LSETUP ( O2T , O2B ) LC1 = P0 >> 1;
NOP;
NOP;
NOP;
LC1 = P1;
O2T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
O2B:R7 += 6;
LC1 = P1;
NOP;
NOP;
NOP;
LSETUP ( O3T , O3B ) LC1 = P0 >> 1;
O3T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
R6 += 5;
O3B:R7 += 6;
LSETUP ( O4T , O4B ) LC1 = P0 >> 1;
NOP;
NOP;
LC1 = P1;
O4T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
O4B:R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
NOP;
LSETUP ( O5T , O5B ) LC1 = P0 >> 1;
O5T:R2 += 1;
R3 += 2;
R4 += 3;
R5 += 4;
O5B:R6 += 5;
R7 += 6;
LSETUP ( O6T , O6B ) LC1 = P0 >> 1;
NOP;
LC1 = P1;
O6T:R2 += 1;
R3 += 2;
R4 += 3;
O6B:R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
NOP;
LSETUP ( O7T , O7B ) LC1 = P0 >> 1;
O7T:R2 += 1;
R3 += 2;
R4 += 3;
O7B:R5 += 4;
R6 += 5;
R7 += 6;
LSETUP ( O8T , O8T ) LC1 = P0 >> 1;
LC1 = P1;
O8T:R2 += 1;
R3 += 2;
O8B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
LC1 = P1;
LSETUP ( O9T , O9T ) LC1 = P0 >> 1;
O9T:R2 += 1;
R3 += 2;
O9B:R4 += 3;
R5 += 4;
R6 += 5;
R7 += 6;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 6,225 | sim/testsuite/bfin/c_dsp32mult_dr_is.s | //Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp
// Spec Reference: dsp32mult single dr is
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x98ba5127;
imm32 r2, 0xa3846725;
imm32 r3, 0x00080027;
imm32 r4, 0xb0ab8d29;
imm32 r5, 0x10ace82b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467028;
R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2);
R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (ISS2);
R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (ISS2);
R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (ISS2);
R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (ISS2);
R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (ISS2);
R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (ISS2);
R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (ISS2);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x7FFF8000;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0x9923a635;
imm32 r1, 0x6f995137;
imm32 r2, 0x1324b735;
imm32 r3, 0x99060037;
imm32 r4, 0x809bcd39;
imm32 r5, 0xb0a99f3b;
imm32 r6, 0xa00c093d;
imm32 r7, 0x12467093;
R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2);
R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (ISS2);
R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (ISS2);
R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (ISS2);
R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (ISS2);
R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (ISS2);
R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (ISS2);
R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (ISS2);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x7FFF7FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x80007FFF;
CHECKREG r7, 0x80008000;
imm32 r0, 0x19235655;
imm32 r1, 0xc9ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x0a060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00a005d;
imm32 r7, 0x1246a05f;
R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2);
R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (ISS2);
R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (ISS2);
R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (ISS2);
R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (ISS2);
R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (ISS2);
R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (ISS2);
R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (ISS2);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x7FFF8000;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80008000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x7FFF7FFF;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xe0060066;
imm32 r4, 0x9eab9d69;
imm32 r5, 0x10ecef6b;
imm32 r6, 0x800ee06d;
imm32 r7, 0x12467e6f;
// test the unsigned U=1
R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (ISS2);
R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (ISS2);
R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (ISS2);
R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (ISS2);
R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (ISS2);
R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (ISS2);
R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (ISS2);
R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (ISS2);
CHECKREG r0, 0x7FFF7FFF;
CHECKREG r1, 0x80008000;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x7FFF7FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x7FFF7FFF;
CHECKREG r7, 0x7FFF7FFF;
// mix order
imm32 r0, 0xac23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13c46705;
imm32 r3, 0x00060007;
imm32 r4, 0x90accd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000cc00d;
imm32 r7, 0x1246fc0f;
R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (ISS2);
R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (ISS2);
R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (ISS2);
R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (ISS2);
R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (ISS2);
R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (ISS2);
R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (ISS2);
R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (ISS2);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80008000;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80008000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x80007FFF;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0xdd246905;
imm32 r3, 0x00d6d007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10aceddb;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (ISS2);
R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (ISS2);
R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (ISS2);
R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (ISS2);
R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (ISS2);
R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (ISS2);
R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (ISS2);
R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (ISS2);
CHECKREG r0, 0x80007FFF;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x80007FFF;
CHECKREG r3, 0x80007FFF;
CHECKREG r4, 0x7FFF7FFF;
CHECKREG r5, 0x80007FFF;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x7FFF8000;
imm32 r0, 0xfb235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13f46705;
imm32 r3, 0x000f0007;
imm32 r4, 0x90abfd09;
imm32 r5, 0x10acefdb;
imm32 r6, 0x000c00fd;
imm32 r7, 0x1246700f;
R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (ISS2);
R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (ISS2);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (ISS2);
R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (ISS2);
R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (ISS2);
R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (ISS2);
R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (ISS2);
R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (ISS2);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF8000;
CHECKREG r6, 0x80008000;
CHECKREG r7, 0x80007FFF;
imm32 r0, 0xab2d5675;
imm32 r1, 0xcfbad127;
imm32 r2, 0x13246d05;
imm32 r3, 0x000600d7;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a9efdb;
imm32 r6, 0x000c500d;
imm32 r7, 0x1246760f;
R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (ISS2);
R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (ISS2);
R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (ISS2);
R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (ISS2);
R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (ISS2);
R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (ISS2);
R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (ISS2);
R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (ISS2);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x80007FFF;
CHECKREG r2, 0x7FFF7FFF;
CHECKREG r3, 0x80008000;
CHECKREG r4, 0x80008000;
CHECKREG r5, 0x7FFF7FFF;
CHECKREG r6, 0x14287FFF;
CHECKREG r7, 0x80007FFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,363 | sim/testsuite/bfin/c_dsp32shift_lmix.s | //Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp
// Spec Reference: dsp32shift lshift: mix
# mach: bfin
.include "testutils.inc"
start
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// lshift : positive data, count (+)=left (half reg)
imm32 r0, 0x00010001;
imm32 r1, 1;
imm32 r2, 0x00020002;
imm32 r3, 2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
CHECKREG r4, 0x00020002;
CHECKREG r5, 0x00080008;
CHECKREG r6, 0x00020002;
CHECKREG r7, 0x00080008;
// lshift : (full reg)
imm32 r1, 3;
imm32 r3, 4;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
R7 = LSHIFT R2 BY R3.L;
CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
CHECKREG r7, 0x00200020;
A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
R5 = A0.w; /* r5 = 0x00080008 */
CHECKREG r5, 0x00080008;
imm32 r4, 0x30000003;
imm32 r1, 1;
R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */
imm32 r1, 2;
R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
CHECKREG r6, 0x60000006;
CHECKREG r7, 0xc000000c;
// lshift : count (-)=right (half reg)
imm32 r0, 0x10001000;
imm32 r1, -1;
imm32 r2, 0x10001000;
imm32 r3, -2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
CHECKREG r4, 0x08000800;
CHECKREG r5, 0x04000400;
CHECKREG r6, 0x08000800;
CHECKREG r7, 0x04000400;
// lshift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */
CHECKREG r6, 0x02000200;
CHECKREG r7, 0x01000100;
// NEGATIVE
// lshift : NEGATIVE data, count (+)=left (half reg)
imm32 r0, 0xc00f800f;
imm32 r1, 1;
imm32 r2, 0xe00fe00f;
imm32 r3, 2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
CHECKREG r4, 0x801e001e;
CHECKREG r5, 0x803c803c;
imm32 r0, 0xc80fe00f;
imm32 r2, 0xe40fe00f;
imm32 r1, 4;
imm32 r3, 5;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
imm32 r0, 0xf80fe00f;
imm32 r2, 0xfc0fe00f;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
CHECKREG r6, 0x80fe00f0;
CHECKREG r7, 0x81fc01e0;
// lshift : NEGATIVE data, count (-)=right (half reg) Working ok
imm32 r0, 0x80f080f0;
imm32 r1, -1;
imm32 r2, 0x80f080f0;
imm32 r3, -2;
R4.H = LSHIFT R0.H BY R1.L;
R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */
R5.H = LSHIFT R2.H BY R3.L;
R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */
CHECKREG r4, 0x40784078;
CHECKREG r5, 0x203c203c;
R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */
R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */
CHECKREG r6, 0x40784078;
CHECKREG r7, 0x203c203c;
// lshift : (full reg)
imm32 r1, -3;
imm32 r3, -4;
R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */
R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */
CHECKREG r6, 0x101e101e;
CHECKREG r7, 0x080f080f;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,683 | sim/testsuite/bfin/max_min_flags.s | // Check Flag Settings for MAX/MIN
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
r0=1;
r1= -1;
r2=min(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=min(r0,r1);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=max(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x0);
r2=max(r0,r1);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x0);
r0.h=1;
r2=min(r1,r0) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=min(r0,r1) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x2);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0xffff);
dbga (r2.h, 0xffff);
r2=max(r1,r0) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x1);
r2=max(r0,r1) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x0);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x1);
dbga (r2.h, 0x1);
r0=0;
r2=max(r1,r0);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x1);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x0);
dbga (r2.h, 0x0);
r0.h=1;
r2=max(r1,r0) (v);
_DBG ASTAT;
//r3=ASTAT;
//dbga (r3.l, 0x1);
//dbga (r3.h, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
dbga (r2.l, 0x0);
dbga (r2.h, 0x1);
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,624 | sim/testsuite/bfin/c_ldimmhalf_lz_ibml.s | //Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: ldimmhalf lz ibml
I0 = 0x2001 (Z);
I1 = 0x2003 (Z);
I2 = 0x2005 (Z);
I3 = 0x2007 (Z);
L0 = 0x2009 (Z);
L1 = 0x200b (Z);
L2 = 0x200d (Z);
L3 = 0x200f (Z);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x00002001;
CHECKREG r1, 0x00002003;
CHECKREG r2, 0x00002005;
CHECKREG r3, 0x00002007;
CHECKREG r4, 0x00002009;
CHECKREG r5, 0x0000200b;
CHECKREG r6, 0x0000200d;
CHECKREG r7, 0x0000200f;
I0 = 0x0111 (Z);
I1 = 0x1111 (Z);
I2 = 0x2222 (Z);
I3 = 0x3333 (Z);
L0 = 0x4444 (Z);
L1 = 0x5555 (Z);
L2 = 0x6666 (Z);
L3 = 0x7777 (Z);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x00000111;
CHECKREG r1, 0x00001111;
CHECKREG r2, 0x00002222;
CHECKREG r3, 0x00003333;
CHECKREG r4, 0x00004444;
CHECKREG r5, 0x00005555;
CHECKREG r6, 0x00006666;
CHECKREG r7, 0x00007777;
I0 = 0x8888 (Z);
I1 = 0x9aaa (Z);
I2 = 0xabbb (Z);
I3 = 0xbccc (Z);
L0 = 0xcddd (Z);
L1 = 0xdeee (Z);
L2 = 0xefff (Z);
L3 = 0xf111 (Z);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0x00008888;
CHECKREG r1, 0x00009aaa;
CHECKREG r2, 0x0000abbb;
CHECKREG r3, 0x0000bccc;
CHECKREG r4, 0x0000cddd;
CHECKREG r5, 0x0000deee;
CHECKREG r6, 0x0000efff;
CHECKREG r7, 0x0000f111;
B0 = 0x3001 (Z);
B1 = 0x3003 (Z);
B2 = 0x3005 (Z);
B3 = 0x3007 (Z);
M0 = 0x3009 (Z);
M1 = 0x300b (Z);
M2 = 0x300d (Z);
M3 = 0x300f (Z);
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00003001;
CHECKREG r1, 0x00003003;
CHECKREG r2, 0x00003005;
CHECKREG r3, 0x00003007;
CHECKREG r4, 0x00003009;
CHECKREG r5, 0x0000300B;
CHECKREG r6, 0x0000300d;
CHECKREG r7, 0x0000300f;
B0 = 0x0110 (Z);
B1 = 0x1110 (Z);
B2 = 0x2220 (Z);
B3 = 0x3330 (Z);
M0 = 0x4440 (Z);
M1 = 0x5550 (Z);
M2 = 0x6660 (Z);
M3 = 0x7770 (Z);
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00000110;
CHECKREG r1, 0x00001110;
CHECKREG r2, 0x00002220;
CHECKREG r3, 0x00003330;
CHECKREG r4, 0x00004440;
CHECKREG r5, 0x00005550;
CHECKREG r6, 0x00006660;
CHECKREG r7, 0x00007770;
B0 = 0xf880 (Z);
B1 = 0xfaa0 (Z);
B2 = 0xfbb0 (Z);
B3 = 0xfcc0 (Z);
M0 = 0xfdd0 (Z);
M1 = 0xfee0 (Z);
M2 = 0xfff0 (Z);
M3 = 0xf110 (Z);
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x0000f880;
CHECKREG r1, 0x0000faa0;
CHECKREG r2, 0x0000fbb0;
CHECKREG r3, 0x0000fcc0;
CHECKREG r4, 0x0000fdd0;
CHECKREG r5, 0x0000fee0;
CHECKREG r6, 0x0000fff0;
CHECKREG r7, 0x0000f110;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,114 | sim/testsuite/bfin/cec-system-call.S | # Blackfin testcase for returning to the right place while bouncing between
# multiple CEC levels (like in a Linux system call)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
# This test keeps P5 as the base of the EVT table
.macro set_evt lvl:req, sym:req
loadsym R1, \sym;
[P5 + 4 * \lvl\()] = R1;
.endm
start
# First mark all EVTs as fails (they shouldn't be activated)
imm32 P5, EVT0;
P1 = P5;
loadsym R1, fail_lvl
imm32 P2, 16
LSETUP (1f, 1f) LC0 = P2;
1: [P1++] = R1;
# The OS exception handler
set_evt 3, _evx;
# The OS system call handler
set_evt 15, _evt15;
# Lower ourselves to userspace
loadsym R1, _user;
loadsym R2, _next_user;
RETI = R1;
R7 = -1;
sti R7;
RTI;
_user:
EXCPT 0;
_next_user:
dbg_pass
_evx:
# RETX should be pointing to the right place
R1 = RETX;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# Lower ourselves to the system call handler
RAISE 15;
RTX;
_evt15:
# RETI should be pointing to the right place
R1 = RETI;
CC = R1 == R2;
IF !CC JUMP fail_lvl;
# Return to userspace now
RTI;
fail_lvl:
dbg_fail
|
tactcomplabs/xbgas-binutils-gdb | 3,583 | sim/testsuite/bfin/c_alu2op_conv_mix.s | //Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp
// Spec Reference: alu2op convert mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.B (X);
R1 = R1.L (X);
R2 = R2.L (Z);
R3 = R3.B (X);
R4 = R4.B (Z);
R5 = - R5;
R6 = ~ R6;
R7 = R7.L (X);
CHECKREG r0, 0xFFFFFFBC;
CHECKREG r1, 0x00005678;
CHECKREG r2, 0x00006789;
CHECKREG r3, 0xFFFFFF9A;
CHECKREG r4, 0x000000AB;
CHECKREG r5, 0x69876544;
CHECKREG r6, 0x58765432;
CHECKREG r7, 0xFFFFBCDE;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R6 = R0.B (X);
R7 = R1.L (X);
R0 = R2.L (Z);
R1 = R3.B (X);
R2 = R4.B (Z);
R3 = - R5;
R4 = ~ R6;
R5 = R7.L (X);
CHECKREG r0, 0x00006789;
CHECKREG r1, 0xFFFFFF9A;
CHECKREG r2, 0x000000AB;
CHECKREG r3, 0x39876544;
CHECKREG r4, 0xFFFFFFFD;
CHECKREG r5, 0x00004659;
CHECKREG r6, 0x00000002;
CHECKREG r7, 0x00004659;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x91203450;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0x789abcde;
R5 = R0.B (X);
R6 = R1.L (X);
R7 = R2.L (Z);
R0 = R3.B (X);
R1 = R4.B (Z);
R2 = - R5;
R3 = ~ R6;
R4 = R7.L (X);
CHECKREG r0, 0xFFFFFF9A;
CHECKREG r1, 0x000000AB;
CHECKREG r2, 0xFFFFFFFE;
CHECKREG r3, 0xFFFFA987;
CHECKREG r4, 0x00003450;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00005678;
CHECKREG r7, 0x00003450;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R4 = R0.B (X);
R5 = R1.L (X);
R6 = R2.L (Z);
R7 = R3.B (X);
R0 = R4.B (Z);
R1 = - R5;
R2 = ~ R6;
R3 = R7.L (X);
CHECKREG r0, 0x00000002;
CHECKREG r1, 0xFFFFA988;
CHECKREG r2, 0xFFFF9876;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00005678;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x00000000;
imm32 r0, 0xadf00001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R3 = R0.B (X);
R4 = R1.L (X);
R5 = R2.L (Z);
R6 = R3.B (X);
R7 = R4.B (Z);
R0 = - R5;
R1 = ~ R6;
R2 = R7.L (X);
CHECKREG r0, 0xFFFF9877;
CHECKREG r1, 0xFFFFFFFE;
CHECKREG r2, 0x00000078;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00005678;
CHECKREG r5, 0x00006789;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x54238900;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R2 = R0.B (X);
R3 = R1.L (X);
R4 = R2.L (Z);
R5 = R3.B (X);
R6 = R4.B (Z);
R7 = - R5;
R0 = ~ R6;
R1 = R7.L (X);
CHECKREG r0, 0xFFFFFFFD;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000002;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R1 = R0.B (X);
R2 = R1.L (X);
R3 = R2.L (Z);
R4 = R3.B (X);
R5 = R4.B (Z);
R6 = - R5;
R0 = ~ R6;
R7 = R7.L (X);
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000002;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0xFFFFFFFE;
CHECKREG r7, 0xFFFFBCDE;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,932 | sim/testsuite/bfin/c_dsp32shift_ahalf_rn.s | //Original:/testcases/core/c_dsp32shift_ahalf_rn/c_dsp32shift_ahalf_rn.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=right (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
R0.L = -1;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
//rl0 = ashift (rl0 by rl0);
R1.L = ASHIFT R1.L BY R0.L;
R2.L = ASHIFT R2.L BY R0.L;
R3.L = ASHIFT R3.L BY R0.L;
R4.L = ASHIFT R4.L BY R0.L;
R5.L = ASHIFT R5.L BY R0.L;
R6.L = ASHIFT R6.L BY R0.L;
R7.L = ASHIFT R7.L BY R0.L;
//CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c000;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
R1.L = -1;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R1.L;
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L;
R3.L = ASHIFT R3.L BY R1.L;
R4.L = ASHIFT R4.L BY R1.L;
R5.L = ASHIFT R5.L BY R1.L;
R6.L = ASHIFT R6.L BY R1.L;
R7.L = ASHIFT R7.L BY R1.L;
CHECKREG r0, 0x0000c000;
//CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000c001;
CHECKREG r3, 0x0000c001;
CHECKREG r4, 0x0000c002;
CHECKREG r5, 0x0000c002;
CHECKREG r6, 0x0000c003;
CHECKREG r7, 0x0000c003;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
R2.L = -15;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R2.L;
R1.L = ASHIFT R1.L BY R2.L;
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L;
R4.L = ASHIFT R4.L BY R2.L;
R5.L = ASHIFT R5.L BY R2.L;
R6.L = ASHIFT R6.L BY R2.L;
R7.L = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
//CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x0000ffff;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
R3.L = -16;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.L = ASHIFT R0.L BY R3.L;
R1.L = ASHIFT R1.L BY R3.L;
R2.L = ASHIFT R2.L BY R3.L;
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L;
R5.L = ASHIFT R5.L BY R3.L;
R6.L = ASHIFT R6.L BY R3.L;
R7.L = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x0000ffff;
CHECKREG r1, 0x0000ffff;
CHECKREG r2, 0x0000ffff;
//CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000ffff;
CHECKREG r5, 0x0000ffff;
CHECKREG r6, 0x0000ffff;
CHECKREG r7, 0x0000ffff;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R0.L;
R1.L = ASHIFT R1.H BY R0.L;
R2.L = ASHIFT R2.H BY R0.L;
R3.L = ASHIFT R3.H BY R0.L;
R4.L = ASHIFT R4.H BY R0.L;
R5.L = ASHIFT R5.H BY R0.L;
R6.L = ASHIFT R6.H BY R0.L;
R7.L = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x80018001;
CHECKREG r2, 0x80028002;
CHECKREG r3, 0x80038003;
CHECKREG r4, 0x80048004;
CHECKREG r5, 0x80058005;
CHECKREG r6, 0x80068006;
CHECKREG r7, 0x80078007;
imm32 r0, 0x80010000;
R1.L = -1;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.L = ASHIFT R0.H BY R1.L;
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L;
R3.L = ASHIFT R3.H BY R1.L;
R4.L = ASHIFT R4.H BY R1.L;
R5.L = ASHIFT R5.H BY R1.L;
R6.L = ASHIFT R6.H BY R1.L;
R7.L = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x8001c000;
//CHECKREG r1, 0x00010001;
CHECKREG r2, 0x8002c001;
CHECKREG r3, 0x8003c001;
CHECKREG r4, 0x8004c002;
CHECKREG r5, 0x8005c002;
CHECKREG r6, 0x8006c003;
CHECKREG r7, 0x8007c003;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
R2.L = -15;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0xa001ffff;
CHECKREG r1, 0xa001ffff;
//CHECKREG r2, 0x2002000f;
CHECKREG r3, 0xa003ffff;
CHECKREG r4, 0xa004ffff;
CHECKREG r5, 0xa005ffff;
CHECKREG r6, 0xa006ffff;
CHECKREG r7, 0xa007ffff;
imm32 r0, 0xb0010001;
imm32 r1, 0xb0010001;
imm32 r2, 0xb0020002;
R3.L = -16;
imm32 r4, 0xb0040004;
imm32 r5, 0xb0050005;
imm32 r6, 0xb0060006;
imm32 r7, 0xb0070007;
R0.L = ASHIFT R0.H BY R3.L;
R1.L = ASHIFT R1.H BY R3.L;
R2.L = ASHIFT R2.H BY R3.L;
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L;
R5.L = ASHIFT R5.H BY R3.L;
R6.L = ASHIFT R6.H BY R3.L;
R7.L = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0xb001ffff;
CHECKREG r1, 0xb001ffff;
CHECKREG r2, 0xb002ffff;
//CHECKREG r3, 0x30030010;
CHECKREG r4, 0xb004ffff;
CHECKREG r5, 0xb005ffff;
CHECKREG r6, 0xb006ffff;
CHECKREG r7, 0xb007ffff;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000001;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000000;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R4.L;
R1.H = ASHIFT R1.L BY R4.L;
R2.H = ASHIFT R2.L BY R4.L;
R3.H = ASHIFT R3.L BY R4.L;
//rh4 = ashift (rl4 by rl4);
R5.H = ASHIFT R5.L BY R4.L;
R6.H = ASHIFT R6.L BY R4.L;
R7.H = ASHIFT R7.L BY R4.L;
CHECKREG r0, 0x00010001;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
//CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x00008001;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
R5.L = -1;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = ASHIFT R0.L BY R5.L;
R1.H = ASHIFT R1.L BY R5.L;
R2.H = ASHIFT R2.L BY R5.L;
R3.H = ASHIFT R3.L BY R5.L;
R4.H = ASHIFT R4.L BY R5.L;
//rh5 = ashift (rl5 by rl5);
R6.H = ASHIFT R6.L BY R5.L;
R7.H = ASHIFT R7.L BY R5.L;
CHECKREG r0, 0xc0008001;
CHECKREG r1, 0xc0008001;
CHECKREG r2, 0xc0018002;
CHECKREG r3, 0xc0018003;
CHECKREG r4, 0xc0028004;
//CHECKREG r5, 0x00020005;
CHECKREG r6, 0xc0038006;
CHECKREG r7, 0xc0038007;
imm32 r0, 0x00009001;
imm32 r1, 0x00009001;
imm32 r2, 0x00009002;
imm32 r3, 0x00009003;
imm32 r4, 0x00009004;
imm32 r5, 0x00009005;
R6.L = -15;
imm32 r7, 0x00009007;
R0.H = ASHIFT R0.L BY R6.L;
R1.H = ASHIFT R1.L BY R6.L;
R2.H = ASHIFT R2.L BY R6.L;
R3.H = ASHIFT R3.L BY R6.L;
R4.H = ASHIFT R4.L BY R6.L;
R5.H = ASHIFT R5.L BY R6.L;
//rh6 = ashift (rl6 by rl6);
R7.H = ASHIFT R7.L BY R6.L;
CHECKREG r0, 0xffff9001;
CHECKREG r1, 0xffff9001;
CHECKREG r2, 0xffff9002;
CHECKREG r3, 0xffff9003;
CHECKREG r4, 0xffff9004;
CHECKREG r5, 0xffff9005;
//CHECKREG r6, 0x00006006;
CHECKREG r7, 0xffff9007;
imm32 r0, 0x0000a001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000a002;
imm32 r3, 0x0000a003;
imm32 r4, 0x0000a004;
imm32 r5, 0x0000a005;
imm32 r6, 0x0000a006;
R7.L = -16;
R0.H = ASHIFT R0.L BY R7.L;
R1.H = ASHIFT R1.L BY R7.L;
R2.H = ASHIFT R2.L BY R7.L;
R3.H = ASHIFT R3.L BY R7.L;
R4.H = ASHIFT R4.L BY R7.L;
R5.H = ASHIFT R5.L BY R7.L;
R6.H = ASHIFT R6.L BY R7.L;
R7.H = ASHIFT R7.L BY R7.L;
CHECKREG r0, 0xffffa001;
CHECKREG r1, 0xffffa001;
CHECKREG r2, 0xffffa002;
CHECKREG r3, 0xffffa003;
CHECKREG r4, 0xffffa004;
CHECKREG r5, 0xffffa005;
CHECKREG r6, 0xffffa006;
//CHECKREG r7, 0x00007007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
R4.L = -1;
imm32 r5, 0x80050000;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R4.L;
R1.H = ASHIFT R1.H BY R4.L;
R2.H = ASHIFT R2.H BY R4.L;
R3.H = ASHIFT R3.H BY R4.L;
//rh4 = ashift (rh4 by rl4);
R5.H = ASHIFT R5.H BY R4.L;
R6.H = ASHIFT R6.H BY R4.L;
R7.H = ASHIFT R7.H BY R4.L;
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
//CHECKREG r4, 0x00020000;
CHECKREG r5, 0xc0020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0x80010000;
imm32 r1, 0x80010000;
imm32 r2, 0x80020000;
imm32 r3, 0x80030000;
imm32 r4, 0x80040000;
R5.L = -1;
imm32 r6, 0x80060000;
imm32 r7, 0x80070000;
R0.H = ASHIFT R0.H BY R5.L;
R1.H = ASHIFT R1.H BY R5.L;
R2.H = ASHIFT R2.H BY R5.L;
R3.H = ASHIFT R3.H BY R5.L;
R4.H = ASHIFT R4.H BY R5.L;
//rh5 = ashift (rh5 by rl5);
R6.H = ASHIFT R6.H BY R5.L;
R7.H = ASHIFT R7.H BY R5.L;
CHECKREG r0, 0xc0000000;
CHECKREG r1, 0xc0000000;
CHECKREG r2, 0xc0010000;
CHECKREG r3, 0xc0010000;
CHECKREG r4, 0xc0020000;
//CHECKREG r5, 0x28020000;
CHECKREG r6, 0xc0030000;
CHECKREG r7, 0xc0030000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030000;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
R6.L = -15;
imm32 r7, 0xd0070000;
R0.L = ASHIFT R0.H BY R6.L;
R1.L = ASHIFT R1.H BY R6.L;
R2.L = ASHIFT R2.H BY R6.L;
R3.L = ASHIFT R3.H BY R6.L;
R4.L = ASHIFT R4.H BY R6.L;
R5.L = ASHIFT R5.H BY R6.L;
//rl6 = ashift (rh6 by rl6);
R7.L = ASHIFT R7.H BY R6.L;
CHECKREG r0, 0xd001ffff;
CHECKREG r1, 0xd001ffff;
CHECKREG r2, 0xd002ffff;
CHECKREG r3, 0xd003ffff;
CHECKREG r4, 0xd004ffff;
CHECKREG r5, 0xd005ffff;
//CHECKREG r6, 0x60060000;
CHECKREG r7, 0xd007ffff;
imm32 r0, 0xe0010000;
imm32 r1, 0xe0010000;
imm32 r2, 0xe0020000;
imm32 r3, 0xe0030000;
imm32 r4, 0xe0040000;
imm32 r5, 0xe0050000;
imm32 r6, 0xe0060000;
R7.L = -16;
R0.H = ASHIFT R0.H BY R7.L;
R1.H = ASHIFT R1.H BY R7.L;
R2.H = ASHIFT R2.H BY R7.L;
R3.H = ASHIFT R3.H BY R7.L;
R4.H = ASHIFT R4.H BY R7.L;
R5.H = ASHIFT R5.H BY R7.L;
R6.H = ASHIFT R6.H BY R7.L;
//rh7 = ashift (rh7 by rl7);
CHECKREG r0, 0xffff0000;
CHECKREG r1, 0xffff0000;
CHECKREG r2, 0xffff0000;
CHECKREG r3, 0xffff0000;
CHECKREG r4, 0xffff0000;
CHECKREG r5, 0xffff0000;
CHECKREG r6, 0xffff0000;
//CHECKREG r7, -16;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,579 | sim/testsuite/bfin/c_ldst_st_p_d_pp_h.s | //Original:/testcases/core/c_ldst_st_p_d_pp_h/c_ldst_st_p_d_pp_h.dsp
// Spec Reference: c_ldst st_p++/p-- h half
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// half word 16-bit store incremented by 2
W [ P5 ++ ] = R0;
W [ P1 ++ ] = R1;
W [ P2 ++ ] = R2;
W [ P4 ++ ] = R4;
W [ FP ++ ] = R5;
W [ P5 ++ ] = R1;
W [ P1 ++ ] = R2;
W [ P2 ++ ] = R3;
W [ P4 ++ ] = R5;
W [ FP ++ ] = R6;
W [ P5 ++ ] = R2;
W [ P1 ++ ] = R3;
W [ P2 ++ ] = R4;
W [ P4 ++ ] = R6;
W [ FP ++ ] = R7;
W [ P5 ++ ] = R3;
W [ P1 ++ ] = R4;
W [ P2 ++ ] = R5;
W [ P4 ++ ] = R7;
W [ FP ++ ] = R0;
W [ P5 ++ ] = R4;
W [ P1 ++ ] = R5;
W [ P2 ++ ] = R6;
W [ P4 ++ ] = R0;
W [ FP ++ ] = R1;
W [ P5 ++ ] = R5;
W [ P1 ++ ] = R6;
W [ P2 ++ ] = R7;
W [ P4 ++ ] = R1;
W [ FP ++ ] = R2;
W [ P5 ++ ] = R6;
W [ P1 ++ ] = R7;
W [ P2 ++ ] = R0;
W [ P4 ++ ] = R2;
W [ FP ++ ] = R3;
W [ P5 ++ ] = R7;
W [ P1 ++ ] = R0;
W [ P2 ++ ] = R1;
W [ P4 ++ ] = R3;
W [ FP ++ ] = R4;
// Read back and check
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
CHECKREG r0, 0x37292618;
CHECKREG r1, 0x483A3729;
CHECKREG r3, 0x6A5C594B;
CHECKREG r4, 0x26181507;
CHECKREG r5, 0x7B6D6A5C;
CHECKREG r7, 0x719A8C7E;
R1 = [ P1 ++ ];
R2 = [ P2 ++ ];
R4 = [ P4 ++ ];
R5 = [ P5 ++ ];
R6 = [ FP ++ ];
CHECKREG r0, 0x37292618;
CHECKREG r1, 0x594B483A;
CHECKREG r2, 0x6A5C594B;
CHECKREG r4, 0x8C7E7B6D;
CHECKREG r5, 0x483A3729;
CHECKREG r6, 0x15078C7E;
R2 = [ P1 ++ ];
R3 = [ P2 ++ ];
R5 = [ P4 ++ ];
R6 = [ P5 ++ ];
R7 = [ FP ++ ];
CHECKREG r1, 0x594B483A;
CHECKREG r2, 0x7B6D6A5C;
CHECKREG r3, 0x8C7E7B6D;
CHECKREG r5, 0x26181507;
CHECKREG r6, 0x6A5C594B;
CHECKREG r7, 0x37292618;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 5,188 | sim/testsuite/bfin/c_dsp32mac_a1a0.s | //Original:/testcases/core/c_dsp32mac_a1a0/c_dsp32mac_a1a0.dsp
// Spec Reference: dsp32mac a1 a0
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
imm32 r0, 0x00000000;
A0 = 0;
A1 = 0;
ASTAT = r0;
// test the default (signed fraction : left )
imm32 r0, 0x12345678;
imm32 r1, 0x33456789;
imm32 r2, 0x5556789a;
imm32 r3, 0x75678912;
imm32 r4, 0x86789123;
imm32 r5, 0xa7891234;
imm32 r6, 0xc1234567;
imm32 r7, 0xf1234567;
A1 = R0.L * R1.L, A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.L * R5.L, A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.L * R7.L, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x45F11C70;
CHECKREG r1, 0x45F11C70;
CHECKREG r2, 0xB48EEC5C;
CHECKREG r3, 0x8FF1C9A8;
CHECKREG r4, 0xEEB780C0;
CHECKREG r5, 0x802DABE0;
CHECKREG r6, 0xF6043652;
CHECKREG r7, 0xA5CF0AC2;
imm32 r0, 0x12245618;
imm32 r1, 0x23256719;
imm32 r2, 0x3426781a;
imm32 r3, 0x45278912;
imm32 r4, 0x56289113;
imm32 r5, 0x67291214;
imm32 r6, 0xa1234517;
imm32 r7, 0xc1234517;
A1 = R0.L * R1.H, A0 += R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.H, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.L * R5.H, A0 += R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 = R6.L * R7.H, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x3B5C5702;
CHECKREG r1, 0x17A372F0;
CHECKREG r2, 0x7C3EF2EE;
CHECKREG r3, 0x40E29BEC;
CHECKREG r4, 0x886A092E;
CHECKREG r5, 0xA699C216;
CHECKREG r6, 0xB700DEC0;
CHECKREG r7, 0xDE11924A;
imm32 r0, 0x15245648;
imm32 r1, 0x25256749;
imm32 r2, 0x3526784a;
imm32 r3, 0x45278942;
imm32 r4, 0x55389143;
imm32 r5, 0x65391244;
imm32 r6, 0xa5334547;
imm32 r7, 0xc5334547;
A1 += R0.H * R1.H, A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 += R2.H * R3.H, A0 = R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 += R4.H * R5.H, A0 = R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.H, A0 = R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x459F2510;
CHECKREG r1, 0xE43416B2;
CHECKREG r2, 0x40FC8A8C;
CHECKREG r3, 0x00EAC446;
CHECKREG r4, 0x0C2925C0;
CHECKREG r5, 0x444EE736;
CHECKREG r6, 0x29B65052;
CHECKREG r7, 0x6E053788;
imm32 r0, 0x13245628;
imm32 r1, 0x23256729;
imm32 r2, 0x3326782a;
imm32 r3, 0x43278922;
imm32 r4, 0x56389123;
imm32 r5, 0x67391224;
imm32 r6, 0xa1334527;
imm32 r7, 0xc1334527;
A1 += R0.H * R1.L, A0 += R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.H * R3.L, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 = R4.H * R5.L, A0 += R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 = R6.H * R7.L, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x6F261922;
CHECKREG r1, 0x7D725110;
CHECKREG r2, 0xAE30B1EE;
CHECKREG r3, 0xD0804218;
CHECKREG r4, 0xBA68D1AE;
CHECKREG r5, 0x0C381FC0;
CHECKREG r6, 0xE8EBF200;
CHECKREG r7, 0xCCC89B8A;
imm32 r0, 0x01340678;
imm32 r1, 0x02450789;
imm32 r2, 0x0356089a;
imm32 r3, 0x04670912;
imm32 r4, 0x05780123;
imm32 r5, 0x06890234;
imm32 r6, 0x07230567;
imm32 r7, 0x00230567;
A1 -= R0.L * R1.L, A0 = R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 = R2.L * R3.L, A0 -= R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.L * R5.L, A0 -= R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 -= R6.L * R7.L, A0 += R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x00617C70;
CHECKREG r1, 0xCC671F1A;
CHECKREG r2, 0x0015C084;
CHECKREG r3, 0x009C09A8;
CHECKREG r4, 0xFFFDA7C4;
CHECKREG r5, 0x00970770;
CHECKREG r6, 0xFFFF9B56;
CHECKREG r7, 0x005CA88E;
imm32 r0, 0x00245618;
imm32 r1, 0x01256719;
imm32 r2, 0x0226781a;
imm32 r3, 0x03278912;
imm32 r4, 0x06489113;
imm32 r5, 0x05291214;
imm32 r6, 0x01634517;
imm32 r7, 0x02234517;
A1 += R0.L * R1.H, A0 -= R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 -= R2.L * R3.H, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.L * R5.H, A0 -= R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.L * R7.H, A0 -= R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xBAA77AA6;
CHECKREG r1, 0x0121BB7E;
CHECKREG r2, 0xBD9CAE92;
CHECKREG r3, 0xFE2C8792;
CHECKREG r4, 0xBCB99352;
CHECKREG r5, 0x02A5517C;
CHECKREG r6, 0xBCB3A640;
CHECKREG r7, 0x03CC91C6;
imm32 r0, 0x10240648;
imm32 r1, 0x25156749;
imm32 r2, 0x3526084a;
imm32 r3, 0x45238942;
imm32 r4, 0x51381143;
imm32 r5, 0x62392244;
imm32 r6, 0xa3333547;
imm32 r7, 0xc4334547;
A1 += R0.H * R1.H, A0 -= R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 -= R2.H * R3.H, A0 -= R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.H * R5.H, A0 += R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.H, A0 -= R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0xB7A22130;
CHECKREG r1, 0x08799FAE;
CHECKREG r2, 0xB327F8F4;
CHECKREG r3, 0xEBC49B4A;
CHECKREG r4, 0xC8E5FEB4;
CHECKREG r5, 0xAD71905A;
CHECKREG r6, 0x9D8AE062;
CHECKREG r7, 0xD8CCAEAC;
imm32 r0, 0x10245628;
imm32 r1, 0x23056729;
imm32 r2, 0x3320782a;
imm32 r3, 0x43270922;
imm32 r4, 0x56389023;
imm32 r5, 0x67391024;
imm32 r6, 0x21334507;
imm32 r7, 0x11334520;
A1 += R0.H * R1.L, A0 -= R0.L * R1.L;
R0 = A0.w;
R1 = A1.w;
A1 -= R2.H * R3.L, A0 += R2.L * R3.H;
R2 = A0.w;
R3 = A1.w;
A1 -= R4.H * R5.L, A0 -= R4.H * R5.L;
R4 = A0.w;
R5 = A1.w;
A1 += R6.H * R7.L, A0 -= R6.H * R7.H;
R6 = A0.w;
R7 = A1.w;
CHECKREG r0, 0x581B1792;
CHECKREG r1, 0xE5CED234;
CHECKREG r2, 0x9725B05E;
CHECKREG r3, 0xE228FDB4;
CHECKREG r4, 0x8C46709E;
CHECKREG r5, 0xD749BDF4;
CHECKREG r6, 0x87D0704C;
CHECKREG r7, 0xE93788B4;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,417 | sim/testsuite/bfin/c_dsp32alu_rm.s | //Original:/testcases/core/c_dsp32alu_rm/c_dsp32alu_rm.dsp
// Spec Reference: dsp32alu
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x35678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34345515;
imm32 r3, 0x46637717;
imm32 r4, 0x5567391b;
imm32 r5, 0x6789a31d;
imm32 r6, 0x744455a5;
imm32 r7, 0x866677a7;
R0 = R0 - R0 (NS);
R1 = R0 - R1 (NS);
R2 = R0 - R2 (NS);
R3 = R0 - R3 (NS);
R4 = R0 - R4 (NS);
R5 = R0 - R5 (NS);
R6 = R0 - R6 (NS);
R7 = R0 - R7 (NS);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xDC7654E3;
CHECKREG r2, 0xCBCBAAEB;
CHECKREG r3, 0xB99C88E9;
CHECKREG r4, 0xAA98C6E5;
CHECKREG r5, 0x98765CE3;
CHECKREG r6, 0x8BBBAA5B;
CHECKREG r7, 0x79998859;
imm32 r0, 0xa5678911;
imm32 r1, 0x4a89ab1d;
imm32 r2, 0x54a45515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5567a91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445a15;
imm32 r7, 0x866677a7;
R0 = R1 - R0 (NS);
R1 = R1 - R1 (NS);
R2 = R1 - R2 (NS);
R3 = R1 - R3 (NS);
R4 = R1 - R4 (NS);
R5 = R1 - R5 (NS);
R6 = R1 - R6 (NS);
R7 = R1 - R7 (NS);
CHECKREG r0, 0xA522220C;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xAB5BAAEB;
CHECKREG r3, 0xB99588E9;
CHECKREG r4, 0xAA9856E5;
CHECKREG r5, 0x987654E3;
CHECKREG r6, 0x8BBBA5EB;
CHECKREG r7, 0x79998859;
imm32 r0, 0xda678911;
imm32 r1, 0x27c9ab1d;
imm32 r2, 0x344c5515;
imm32 r3, 0x4666c717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x744455b5;
imm32 r7, 0x8666777b;
R0 = R2 - R0 (NS);
R1 = R2 - R1 (NS);
R2 = R2 - R2 (NS);
R3 = R2 - R3 (NS);
R4 = R2 - R4 (NS);
R5 = R2 - R5 (NS);
R6 = R2 - R6 (NS);
R7 = R2 - R7 (NS);
CHECKREG r0, 0x59E4CC04;
CHECKREG r1, 0x0C82A9F8;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xB99938E9;
CHECKREG r4, 0xAA9876E5;
CHECKREG r5, 0x987654E3;
CHECKREG r6, 0x8BBBAA4B;
CHECKREG r7, 0x79998885;
imm32 r0, 0x65678911;
imm32 r1, 0x7289ab1d;
imm32 r2, 0x84345515;
imm32 r3, 0x96647717;
imm32 r4, 0x5567591b;
imm32 r5, 0x6789a61d;
imm32 r6, 0x744d5515;
imm32 r7, 0x8666b777;
R0 = R3 - R0 (NS);
R1 = R3 - R1 (NS);
R2 = R3 - R2 (NS);
R3 = R3 - R3 (NS);
R4 = R3 - R4 (NS);
R5 = R3 - R5 (NS);
R6 = R3 - R6 (NS);
R7 = R3 - R7 (NS);
CHECKREG r0, 0x30FCEE06;
CHECKREG r1, 0x23DACBFA;
CHECKREG r2, 0x12302202;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xAA98A6E5;
CHECKREG r5, 0x987659E3;
CHECKREG r6, 0x8BB2AAEB;
CHECKREG r7, 0x79994889;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = R4 - R0 (NS);
R1 = R4 - R1 (NS);
R2 = R4 - R2 (NS);
R3 = R4 - R3 (NS);
R4 = R4 - R4 (NS);
R5 = R4 - R5 (NS);
R6 = R4 - R6 (NS);
R7 = R4 - R7 (NS);
CHECKREG r0, 0x4000000A;
CHECKREG r1, 0x2DDDDDFE;
CHECKREG r2, 0x21233406;
CHECKREG r3, 0x0F011204;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x987654E3;
CHECKREG r6, 0x8BBBAAEB;
CHECKREG r7, 0x79998889;
imm32 r0, 0x95678911;
imm32 r1, 0x8789ab1d;
imm32 r2, 0x74445515;
imm32 r3, 0x36667717;
imm32 r4, 0x3567891b;
imm32 r5, 0x6e89ab1d;
imm32 r6, 0x74e45515;
imm32 r7, 0x866e7777;
R0 = R5 - R0 (NS);
R1 = R5 - R1 (NS);
R2 = R5 - R2 (NS);
R3 = R5 - R3 (NS);
R4 = R5 - R4 (NS);
R5 = R5 - R5 (NS);
R6 = R5 - R6 (NS);
R7 = R5 - R7 (NS);
CHECKREG r0, 0xD922220C;
CHECKREG r1, 0xE7000000;
CHECKREG r2, 0xFA455608;
CHECKREG r3, 0x38233406;
CHECKREG r4, 0x39222202;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x8B1BAAEB;
CHECKREG r7, 0x79918889;
imm32 r0, 0x5a678911;
imm32 r1, 0x67c9ab1d;
imm32 r2, 0x744d5515;
imm32 r3, 0x8666b717;
imm32 r4, 0x9567891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445f15;
imm32 r7, 0x866677f7;
R0 = R6 - R0 (NS);
R1 = R6 - R1 (NS);
R2 = R6 - R2 (NS);
R3 = R6 - R3 (NS);
R4 = R6 - R4 (NS);
R5 = R6 - R5 (NS);
R6 = R6 - R6 (NS);
R7 = R6 - R7 (NS);
CHECKREG r0, 0x19DCD604;
CHECKREG r1, 0x0C7AB3F8;
CHECKREG r2, 0xFFF70A00;
CHECKREG r3, 0xEDDDA7FE;
CHECKREG r4, 0xDEDCD5FA;
CHECKREG r5, 0x0CBA83F8;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x79998809;
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x3a455515;
imm32 r3, 0x46d66717;
imm32 r4, 0x556b891b;
imm32 r5, 0x6789cb1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0 = R7 - R0 (NS);
R1 = R7 - R1 (NS);
R2 = R7 - R2 (NS);
R3 = R7 - R3 (NS);
R4 = R7 - R4 (NS);
R5 = R7 - R5 (NS);
R6 = R7 - R6 (NS);
R7 = R7 - R7 (NS);
CHECKREG r0, 0x60FEEE66;
CHECKREG r1, 0x62DCCC5A;
CHECKREG r2, 0x4C212262;
CHECKREG r3, 0x3F901060;
CHECKREG r4, 0x30FAEE5C;
CHECKREG r5, 0x1EDCAC5A;
CHECKREG r6, 0x12222262;
CHECKREG r7, 0x00000000;
imm32 r0, 0xd5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34f45515;
imm32 r3, 0x466b7717;
imm32 r4, 0x5567c91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445115;
imm32 r7, 0x866a7d77;
R3 = R1 - R4 (S);
R7 = R4 - R6 (S);
R2 = R7 - R7 (S);
R4 = R5 - R0 (S);
R5 = R3 - R1 (S);
R6 = R2 - R3 (S);
R0 = R0 - R2 (S);
R1 = R6 - R5 (S);
CHECKREG r0, 0xD5678911;
CHECKREG r1, 0x7C45E719;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xD921E202;
CHECKREG r4, 0x7FFFFFFF;
CHECKREG r5, 0xAA9836E5;
CHECKREG r6, 0x26DE1DFE;
CHECKREG r7, 0xE1237806;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5567891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R3 = R3 - R3 (S);
R1 = R7 - R6 (S);
R4 = R1 - R2 (S);
R7 = R4 - R0 (S);
R5 = R6 - R4 (S);
R2 = R5 - R5 (S);
R6 = R2 - R1 (S);
R0 = R0 - R7 (S);
CHECKREG r0, 0x7FFFFFFF;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x80000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,791 | sim/testsuite/bfin/c_mmr_interr_ctl.s | # Blackfin testcase for the CEC
# mach: bfin
# sim: --environment operating
.include "testutils.inc"
start
INIT_R_REGS 0;
INIT_P_REGS 0;
INIT_I_REGS 0;
INIT_M_REGS 0;
INIT_L_REGS 0;
INIT_B_REGS 0;
CLI R1; // inhibit events during MMR writes
loadsym sp, USTACK; // setup the user stack pointer
usp = sp; // and frame pointer
loadsym sp, KSTACK; // setup the stack pointer
fp = sp; // and frame pointer
imm32 p0, 0xFFE02000;
loadsym r0, EHANDLE; // Emulation Handler (Int0)
[p0++] = r0;
loadsym r0, RHANDLE; // Reset Handler (Int1)
[p0++] = r0;
loadsym r0, NHANDLE; // NMI Handler (Int2)
[p0++] = r0;
loadsym r0, XHANDLE; // Exception Handler (Int3)
[p0++] = r0;
[p0++] = r0; // EVT4 not used global Interr Enable (INT4)
loadsym r0, HWHANDLE; // HW Error Handler (Int5)
[p0++] = r0;
loadsym r0, THANDLE; // Timer Handler (Int6)
[p0++] = r0;
loadsym r0, I7HANDLE; // IVG7 Handler
[p0++] = r0;
loadsym r0, I8HANDLE; // IVG8 Handler
[p0++] = r0;
loadsym r0, I9HANDLE; // IVG9 Handler
[p0++] = r0;
loadsym r0, I10HANDLE;// IVG10 Handler
[p0++] = r0;
loadsym r0, I11HANDLE;// IVG11 Handler
[p0++] = r0;
loadsym r0, I12HANDLE;// IVG12 Handler
[p0++] = r0;
loadsym r0, I13HANDLE;// IVG13 Handler
[p0++] = r0;
loadsym r0, I14HANDLE;// IVG14 Handler
[p0++] = r0;
loadsym r0, I15HANDLE;// IVG15 Handler
[p0++] = r0;
imm32 p0, 0xFFE02100 // EVT_OVERRIDE
r0 = 0;
[p0++] = r0;
r1 = -1; // Change this to mask interrupts (*)
csync; // wait for MMR writes to finish
sti r1; // sync and reenable events (implicit write to IMASK)
imm32 p0, 0xFFE02104;
r0 = [p0];
// ckeck that sti allows the lower 5 bits of imask to be written
CHECKREG r0, 0xffff;
DUMMY:
r0 = 0 (z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
loadsym r0, STARTUSER;// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
loadsym p1, BEGIN;
imm32 p0, (0xFFE02000 + 4 * 15);
CLI R1; // inhibit events during write to MMR
[p0] = p1; // IVG15 (General) handler (Int 15) load with start
csync; // wait for it
sti r1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
// *********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[--sp] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// EVTx
// wrt-rd EVT0: 0 bits, rw=0 = 0xFFE02000
imm32 p0, 0xFFE02000;
imm32 r0, 0x00000000
[p0] = r0;
// wrt-rd EVT1: 32 bits, rw=0 = 0xFFE02004
imm32 p0, 0xFFE02004;
imm32 r0, 0x00000000
[p0] = r0;
// wrt-rd EVT2 = 0xFFE02008
imm32 p0, 0xFFE02008
imm32 r0, 0xE1DE5D1C
[p0] = r0;
// wrt-rd EVT3 = 0xFFE0200C
imm32 p0, 0xFFE0200C
imm32 r0, 0x9CC20332
[p0] = r0;
// wrt-rd EVT4 = 0xFFE02010
imm32 p0, 0xFFE02010
imm32 r0, 0x00000000
[p0] = r0;
// wrt-rd EVT5 = 0xFFE02014
imm32 p0, 0xFFE02014
imm32 r0, 0x55552345
[p0] = r0;
// wrt-rd EVT6 = 0xFFE02018
imm32 p0, 0xFFE02018
imm32 r0, 0x66663456
[p0] = r0;
// wrt-rd EVT7 = 0xFFE0201C
imm32 p0, 0xFFE0201C
imm32 r0, 0x77774567
[p0] = r0;
// wrt-rd EVT8 = 0xFFE02020
imm32 p0, 0xFFE02020
imm32 r0, 0x88885678
[p0] = r0;
// wrt-rd EVT9 = 0xFFE02024
imm32 p0, 0xFFE02024
imm32 r0, 0x99996789
[p0] = r0;
// wrt-rd EVT10 = 0xFFE02028
imm32 p0, 0xFFE02028
imm32 r0, 0xaaaa1234
[p0] = r0;
// wrt-rd EVT11 = 0xFFE0202C
imm32 p0, 0xFFE0202C
imm32 r0, 0xBBBBABC6
[p0] = r0;
// wrt-rd EVT12 = 0xFFE02030
imm32 p0, 0xFFE02030
imm32 r0, 0xCCCCABC6
[p0] = r0;
// wrt-rd EVT13 = 0xFFE02034
imm32 p0, 0xFFE02034
imm32 r0, 0xDDDDABC6
[p0] = r0;
// wrt-rd EVT14 = 0xFFE02038
imm32 p0, 0xFFE02038
imm32 r0, 0xEEEEABC6
[p0] = r0;
// wrt-rd EVT15 = 0xFFE0203C
imm32 p0, 0xFFE0203C
imm32 r0, 0xFFFFABC6
[p0] = r0;
// wrt-rd EVT_OVERRIDE:9 bits = 0xFFE02100
imm32 p0, 0xFFE02100
imm32 r0, 0x000001ff
[p0] = r0;
// wrt-rd IMASK: 16 bits = 0xFFE02104
imm32 p0, 0xFFE02104
imm32 r0, 0x00000fff
[p0] = r0;
// wrt-rd IPEND: 16 bits, rw=0 = 0xFFE02108
imm32 p0, 0xFFE02108
imm32 r0, 0x00000000
//[p0] = r0;
raise 12;
raise 13;
// wrt-rd ILAT: 16 bits, rw=0 = 0xFFE0210C
imm32 p0, 0xFFE0210C
imm32 r0, 0x00000000
//[p0] = r0;
csync;
// *** read ops
imm32 p0, 0xFFE02000
r0 = [p0];
CHECKREG r0, 0;
imm32 p0, 0xFFE02004
r1 = [p0];
CHECKREG r1, 0;
imm32 p0, 0xFFE02008
r2 = [p0];
CHECKREG r2, 0xE1DE5D1C;
imm32 p0, 0xFFE0200C
r3 = [p0];
CHECKREG r3, 0x9CC20332;
imm32 p0, 0xFFE02014
r4 = [p0];
imm32 p0, 0xFFE02018
r5 = [p0];
imm32 p0, 0xFFE0201C
r6 = [p0];
imm32 p0, 0xFFE02020 /* EVT8 */
r7 = [p0];
CHECKREG r0, 0x00000000;
//CHECKREG(r1, 0x00000000); /// mismatch = 00
CHECKREG r2, 0xE1DE5D1C;
CHECKREG r3, 0x9CC20332;
CHECKREG r4, 0x55552345;
CHECKREG r5, 0x66663456;
CHECKREG r6, 0x77774567;
CHECKREG r7, 0x88885678;
imm32 p0, 0xFFE02024 /* EVT9 */
r0 = [p0];
imm32 p0, 0xFFE02028 /* EVT10 */
r1 = [p0];
imm32 p0, 0xFFE0202C /* EVT11 */
r2 = [p0];
imm32 p0, 0xFFE02030 /* EVT12 */
r3 = [p0];
imm32 p0, 0xFFE02034 /* EVT13 */
r4 = [p0];
imm32 p0, 0xFFE02038 /* EVT14 */
r5 = [p0];
imm32 p0, 0xFFE0203C /* EVT15 */
r6 = [p0];
CHECKREG r0, 0x99996789;
CHECKREG r1, 0xaaaa1234;
CHECKREG r2, 0xBBBBABC6;
CHECKREG r3, 0xCCCCABC6;
CHECKREG r4, 0xDDDDABC6;
CHECKREG r5, 0xEEEEABC6;
CHECKREG r6, 0xFFFFABC6;
imm32 p0, 0xFFE02100 /* EVT_OVERRIDE */
r0 = [p0];
imm32 p0, 0xFFE02104 /* IMASK */
r1 = [p0];
imm32 p0, 0xFFE02108 /* IPEND */
r2 = [p0];
imm32 p0, 0xFFE0210C /* ILAT */
r3 = [p0];
CHECKREG r0, 0x000001ff;
CHECKREG r1, 0x00000fff; /* XXX: original had 0xfe0 ?? */
CHECKREG r2, 0x00008000;
CHECKREG r3, 0x00003000;
dbg_pass;
// *********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
r0 = 2;
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
r2 = 5;
RTI;
THANDLE: // Timer Handler 6
r3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
r4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
r5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
r6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
r7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
r0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
r1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
r2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
r3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
r4 = 15;
RTI;
nop;nop;nop;nop;nop;nop;nop; // needed for icache bug
//
// Data Segment
//
.data
// Stack Segments (Both Kernel and User)
.rep 0x10
.byte 0
.endr
KSTACK:
.rep 0x10
.byte 0
.endr
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 2,682 | sim/testsuite/bfin/c_dsp32shift_vmaxvmax.s | //Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp
// Spec Reference: dsp32shift vmax / vmax
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x11002001;
imm32 r1, 0x12001001;
imm32 r2, 0x11301302;
imm32 r3, 0x43001003;
imm32 r4, 0x11601604;
imm32 r5, 0x71001705;
imm32 r6, 0x81008006;
imm32 r7, 0x1900b007;
A0 = R3;
R1 = VIT_MAX( R1 , R0 ) (ASL);
R2 = VIT_MAX( R2 , R1 ) (ASL);
R3 = VIT_MAX( R3 , R2 ) (ASL);
R4 = VIT_MAX( R4 , R3 ) (ASL);
R5 = VIT_MAX( R5 , R4 ) (ASL);
R6 = VIT_MAX( R6 , R5 ) (ASL);
R7 = VIT_MAX( R7 , R6 ) (ASL);
R0 = VIT_MAX( R0 , R7 ) (ASL);
CHECKREG r0, 0x20018100;
CHECKREG r1, 0x12002001;
CHECKREG r2, 0x13022001;
CHECKREG r3, 0x43002001;
CHECKREG r4, 0x16044300;
CHECKREG r5, 0x71004300;
CHECKREG r6, 0x81007100;
CHECKREG r7, 0x19008100;
imm32 r0, 0x11002001;
imm32 r1, 0xd2001001;
imm32 r2, 0x14301302;
imm32 r3, 0x43001003;
imm32 r4, 0x11f01604;
imm32 r5, 0xb1001705;
imm32 r6, 0xd1008006;
imm32 r7, 0x39056707;
R1 = VIT_MAX( R1 , R3 ) (ASL);
R2 = VIT_MAX( R2 , R4 ) (ASL);
R3 = VIT_MAX( R3 , R6 ) (ASL);
R4 = VIT_MAX( R4 , R5 ) (ASL);
R5 = VIT_MAX( R5 , R7 ) (ASL);
R6 = VIT_MAX( R6 , R0 ) (ASL);
R7 = VIT_MAX( R7 , R1 ) (ASL);
R0 = VIT_MAX( R0 , R2 ) (ASL);
CHECKREG r0, 0x20011604;
CHECKREG r1, 0x10014300;
CHECKREG r2, 0x14301604;
CHECKREG r3, 0x4300D100;
CHECKREG r4, 0x16041705;
CHECKREG r5, 0x17056707;
CHECKREG r6, 0xD1002001;
CHECKREG r7, 0x67074300;
imm32 r0, 0xa1011001;
imm32 r1, 0x1b002001;
imm32 r2, 0x81c01302;
imm32 r3, 0x910d1403;
imm32 r4, 0x2100e504;
imm32 r5, 0x31007f65;
imm32 r6, 0x41007006;
imm32 r7, 0x15001801;
R1 = VIT_MAX( R1 , R0 ) (ASR);
R2 = VIT_MAX( R2 , R1 ) (ASR);
R3 = VIT_MAX( R3 , R2 ) (ASR);
R4 = VIT_MAX( R4 , R3 ) (ASR);
R5 = VIT_MAX( R5 , R4 ) (ASR);
R6 = VIT_MAX( R6 , R5 ) (ASR);
R7 = VIT_MAX( R7 , R6 ) (ASR);
R0 = VIT_MAX( R0 , R7 ) (ASR);
CHECKREG r0, 0x1001910D;
CHECKREG r1, 0x20011001;
CHECKREG r2, 0x81C02001;
CHECKREG r3, 0x910D81C0;
CHECKREG r4, 0x2100910D;
CHECKREG r5, 0x7F65910D;
CHECKREG r6, 0x7006910D;
CHECKREG r7, 0x1801910D;
imm32 r0, 0xe1011001;
imm32 r1, 0x4b002001;
imm32 r2, 0x8fc01302;
imm32 r3, 0x910d1403;
imm32 r4, 0xb100e504;
imm32 r5, 0x41007f65;
imm32 r6, 0xaf007006;
imm32 r7, 0x16001801;
R0 = VIT_MAX( R4 , R0 ) (ASR);
R1 = VIT_MAX( R5 , R1 ) (ASR);
R2 = VIT_MAX( R6 , R2 ) (ASR);
R3 = VIT_MAX( R7 , R3 ) (ASR);
R4 = VIT_MAX( R0 , R4 ) (ASR);
R5 = VIT_MAX( R1 , R5 ) (ASR);
R6 = VIT_MAX( R2 , R6 ) (ASR);
R7 = VIT_MAX( R3 , R7 ) (ASR);
CHECKREG r0, 0xE5041001;
CHECKREG r1, 0x7F654B00;
CHECKREG r2, 0xAF008FC0;
CHECKREG r3, 0x1801910D;
CHECKREG r4, 0x1001E504;
CHECKREG r5, 0x7F657F65;
CHECKREG r6, 0xAF00AF00;
CHECKREG r7, 0x910D1801;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,086 | sim/testsuite/bfin/c_mmr_ppop_illegal_adr.S | //Original:/proj/frio/dv/testcases/core/c_mmr_ppop_illegal_adr/c_mmr_ppop_illegal_adr.dsp
// Spec Reference: mmr ppop illegal address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we set the processor operating modes, initialize registers
// etc.)
//
BOOT:
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP; // and frame pointer
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used global Interr Enable (INT4)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
LD32(r0, 0206037020);
LD32(r1, 0x10070030);
LD32(r2, 0xe2000043);
LD32(r3, 0x30305050);
LD32(r4, 0x0f040860);
LD32(r5, 0x0a0050d0);
LD32(r6, 0x00000000);
LD32(r7, 0x0f060071);
// LD32(sp, 0xFFE02104);
// [--sp] = (r7-r6);
[ -- SP ] = R7;
[ -- SP ] = R6;
.dd 0xffff
R1 += 2;
CHECKREG(r1, 0x10070034);
CHECKREG(r2, 0xE2000046);
CHECKREG(r3, 0x30305054);
CHECKREG(r4, 0x0f040865);
CHECKREG(r5, 0x0a0050d6);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x0f060079);
R7 = [ SP ++ ];
CHECKREG(r7, 0x00000000);
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 = 2;
RTN;
XHANDLE: // Exception Handler 3
R0 = RETX; // error handler:RETX has the address of the same Illegal instr
R1 += 2;
R2 += 3;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
R0 += 2; // we have to add 2 to point to next instr after return (16-bit illegal instr)
RETX = R0;
NOP; NOP; NOP; NOP;
RTX;
HWHANDLE: // HW Error Handler 5
R2 = 5;
RTI;
THANDLE: // Timer Handler 6
R3 = 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 = 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 = 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 = 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.section MEM_DATA_ADDR_1,"aw"
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.dd 0x000f0005
.dd 0x00100006
.dd 0x00200007
.dd 0x00300008
.dd 0x00400009
.dd 0x0050000a
.dd 0x0060000b
.dd 0x0070000c
.dd 0x0080000d
.dd 0x0090000e
.dd 0x0100000f
.dd 0x02000010
.dd 0x03000011
.dd 0x04000012
.dd 0x05000013
.dd 0x06000014
.dd 0x001a0000
.dd 0x001b0001
.dd 0x001c0002
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 8,772 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_lp/c_dsp32shiftim_ahalf_lp.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : positive data, count (+)=left (half reg)
// d_lo = ashift (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x01010100;
imm32 r1, 0x01020101;
imm32 r2, 0x01030102;
imm32 r3, 0x01040103;
imm32 r4, 0x01050104;
imm32 r5, 0x01060105;
imm32 r6, 0x01070106;
imm32 r7, 0x01080107;
R0.L = R0.L << 0;
R1.L = R1.L << 1;
R2.L = R2.L << 2;
R3.L = R3.L << 3;
R4.L = R4.L << 4;
R5.L = R5.L << 5;
R6.L = R6.L << 6;
R7.L = R7.L << 7;
CHECKREG r0, 0x01010100;
CHECKREG r1, 0x01020202;
CHECKREG r2, 0x01030408;
CHECKREG r3, 0x01040818;
CHECKREG r4, 0x01051040;
CHECKREG r5, 0x010620A0;
CHECKREG r6, 0x01074180;
CHECKREG r7, 0x01088380;
imm32 r0, 0x00090201;
imm32 r1, 0x00100201;
imm32 r2, 0x00110202;
imm32 r3, 0x00120203;
imm32 r4, 0x00130204;
imm32 r5, 0x00140205;
imm32 r6, 0x00150206;
imm32 r7, 0x00160207;
R7.L = R0.L << 8;
R6.L = R1.L << 9;
R5.L = R2.L << 10;
R4.L = R3.L << 11;
R3.L = R4.L << 12;
R2.L = R5.L << 13;
R1.L = R6.L << 14;
R0.L = R7.L << 15;
CHECKREG r1, 0x00100000;
CHECKREG r0, 0x00090000;
CHECKREG r2, 0x00110000;
CHECKREG r3, 0x00120000;
CHECKREG r4, 0x00131800;
CHECKREG r5, 0x00140800;
CHECKREG r6, 0x00150200;
CHECKREG r7, 0x00160100;
imm32 r0, 0x00170401;
imm32 r1, 0x00180401;
imm32 r2, 0x0019040f;
imm32 r3, 0x00200403;
imm32 r4, 0x00210404;
imm32 r5, 0x00220405;
imm32 r6, 0x00230406;
imm32 r7, 0x00244407;
R6.L = R0.L << 15;
R5.L = R1.L << 15;
R4.L = R2.L << 15;
R3.L = R3.L << 15;
R2.L = R4.L << 15;
R1.L = R5.L << 15;
R0.L = R6.L << 15;
R7.L = R7.L << 15;
CHECKREG r0, 0x00170000;
CHECKREG r1, 0x00180000;
CHECKREG r2, 0x00190000;
CHECKREG r3, 0x00208000;
CHECKREG r4, 0x00218000;
CHECKREG r5, 0x00228000;
CHECKREG r6, 0x00238000;
CHECKREG r7, 0x00248000;
imm32 r0, 0x00005001;
imm32 r1, 0x00005001;
imm32 r2, 0x00005002;
imm32 r3, 0x00005010;
imm32 r4, 0x00005004;
imm32 r5, 0x00005005;
imm32 r6, 0x00000506;
imm32 r7, 0x00000507;
R5.L = R0.L << 13;
R6.L = R1.L << 13;
R7.L = R2.L << 13;
R0.L = R3.L << 13;
R1.L = R4.L << 13;
R2.L = R5.L << 13;
R3.L = R6.L << 13;
R4.L = R7.L << 13;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00002000;
CHECKREG r6, 0x00002000;
CHECKREG r7, 0x00004000;
// RHx by RLx
imm32 r0, 0x00006010;
imm32 r1, 0x00016020;
imm32 r2, 0x00026030;
imm32 r3, 0x00036040;
imm32 r4, 0x00046050;
imm32 r5, 0x00056060;
imm32 r6, 0x00066070;
imm32 r7, 0x00076080;
R0.L = R0.H << 10;
R1.L = R1.H << 10;
R2.L = R2.H << 10;
R3.L = R3.H << 10;
R4.L = R4.H << 10;
R5.L = R5.H << 10;
R6.L = R6.H << 10;
R7.L = R7.H << 10;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010400;
CHECKREG r2, 0x00020800;
CHECKREG r3, 0x00030C00;
CHECKREG r4, 0x00041000;
CHECKREG r5, 0x00051400;
CHECKREG r6, 0x00061800;
CHECKREG r7, 0x00071C00;
imm32 r0, 0x00010090;
imm32 r1, 0x00010111;
imm32 r2, 0x00020120;
imm32 r3, 0x00030130;
imm32 r4, 0x00040140;
imm32 r5, 0x00050150;
imm32 r6, 0x00060160;
imm32 r7, 0x00070170;
R1.L = R0.H << 1;
R2.L = R1.H << 1;
R3.L = R2.H << 1;
R4.L = R3.H << 1;
R5.L = R4.H << 1;
R6.L = R5.H << 1;
R7.L = R6.H << 1;
R0.L = R7.H << 1;
CHECKREG r1, 0x00010002;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030004;
CHECKREG r4, 0x00040006;
CHECKREG r5, 0x00050008;
CHECKREG r6, 0x0006000A;
CHECKREG r7, 0x0007000C;
CHECKREG r0, 0x0001000E;
imm32 r0, 0x0a010000;
imm32 r1, 0x0b010000;
imm32 r2, 0x0c02000f;
imm32 r3, 0x0d030000;
imm32 r4, 0x0e040000;
imm32 r5, 0x0f050000;
imm32 r6, 0x01060000;
imm32 r7, 0x02070000;
R2.L = R0.H << 12;
R3.L = R1.H << 12;
R4.L = R2.H << 12;
R5.L = R3.H << 12;
R6.L = R4.H << 12;
R7.L = R5.H << 12;
R0.L = R6.H << 12;
R1.L = R7.H << 12;
CHECKREG r0, 0x0A016000;
CHECKREG r1, 0x0B017000;
CHECKREG r2, 0x0C021000;
CHECKREG r3, 0x0D031000;
CHECKREG r4, 0x0E042000;
CHECKREG r5, 0x0F053000;
CHECKREG r6, 0x01064000;
CHECKREG r7, 0x02075000;
imm32 r0, 0x01010001;
imm32 r1, 0x02010001;
imm32 r2, 0x03020002;
imm32 r3, 0x04030010;
imm32 r4, 0x05040004;
imm32 r5, 0x06050005;
imm32 r6, 0x07060006;
imm32 r7, 0x08070007;
R3.L = R0.H << 13;
R4.L = R1.H << 13;
R5.L = R2.H << 13;
R6.L = R3.H << 13;
R7.L = R4.H << 13;
R0.L = R5.H << 13;
R1.L = R6.H << 13;
R2.L = R7.H << 13;
CHECKREG r0, 0x0101A000;
CHECKREG r1, 0x0201C000;
CHECKREG r2, 0x0302E000;
CHECKREG r3, 0x04032000;
CHECKREG r4, 0x05042000;
CHECKREG r5, 0x06054000;
CHECKREG r6, 0x07066000;
CHECKREG r7, 0x08078000;
// RLx by RLx
imm32 r0, 0xa0000400;
imm32 r1, 0xbb000401;
imm32 r2, 0xc0000402;
imm32 r3, 0xd0000403;
imm32 r4, 0xe0000404;
imm32 r5, 0xf0000405;
imm32 r6, 0x10000406;
imm32 r7, 0x20000407;
R0.H = R0.L << 14;
R1.H = R1.L << 14;
R2.H = R2.L << 14;
R3.H = R3.L << 14;
R4.H = R4.L << 14;
R5.H = R5.L << 14;
R6.H = R6.L << 14;
R7.H = R7.L << 14;
CHECKREG r0, 0x00000400;
CHECKREG r1, 0x40000401;
CHECKREG r2, 0x80000402;
CHECKREG r3, 0xC0000403;
CHECKREG r4, 0x00000404;
CHECKREG r5, 0x40000405;
CHECKREG r6, 0x80000406;
CHECKREG r7, 0xC0000407;
imm32 r0, 0x0a000001;
imm32 r1, 0x0b000001;
imm32 r2, 0x0cd00002;
imm32 r3, 0x0d000003;
imm32 r4, 0x0e000004;
imm32 r5, 0x0f000005;
imm32 r6, 0x03000006;
imm32 r7, 0x04000007;
R1.H = R0.L << 15;
R2.H = R1.L << 15;
R3.H = R2.L << 15;
R4.H = R3.L << 15;
R5.H = R4.L << 15;
R6.H = R5.L << 15;
R7.H = R6.L << 15;
R0.H = R7.L << 15;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x80000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x80000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x80000006;
CHECKREG r7, 0x00000007;
CHECKREG r0, 0x80000001;
imm32 r0, 0x10000001;
imm32 r1, 0x02000001;
imm32 r2, 0x0300000f;
imm32 r3, 0x04000003;
imm32 r4, 0x05000004;
imm32 r5, 0x06000005;
imm32 r6, 0x07000006;
imm32 r7, 0x00800007;
R2.H = R0.L << 2;
R3.H = R1.L << 2;
R4.H = R2.L << 2;
R5.H = R3.L << 2;
R6.H = R4.L << 2;
R7.H = R5.L << 2;
R0.H = R6.L << 2;
R1.H = R7.L << 2;
CHECKREG r0, 0x00180001;
CHECKREG r1, 0x001C0001;
CHECKREG r2, 0x0004000F;
CHECKREG r3, 0x00040003;
CHECKREG r4, 0x003C0004;
CHECKREG r5, 0x000C0005;
CHECKREG r6, 0x00100006;
CHECKREG r7, 0x00140007;
imm32 r0, 0x00000801;
imm32 r1, 0x00000801;
imm32 r2, 0x00000802;
imm32 r3, 0x00000810;
imm32 r4, 0x00000804;
imm32 r5, 0x00000805;
imm32 r6, 0x00000806;
imm32 r7, 0x00000807;
R3.H = R0.L << 3;
R4.H = R1.L << 3;
R5.H = R2.L << 3;
R6.H = R3.L << 3;
R7.H = R4.L << 3;
R0.H = R5.L << 3;
R1.H = R6.L << 3;
R2.H = R7.L << 3;
CHECKREG r0, 0x40280801;
CHECKREG r1, 0x40300801;
CHECKREG r2, 0x40380802;
CHECKREG r3, 0x40080810;
CHECKREG r4, 0x40080804;
CHECKREG r5, 0x40100805;
CHECKREG r6, 0x40800806;
CHECKREG r7, 0x40200807;
// RHx by RLx
imm32 r0, 0x00000400;
imm32 r1, 0x00010500;
imm32 r2, 0x00020060;
imm32 r3, 0x00030070;
imm32 r4, 0x00040800;
imm32 r5, 0x00050090;
imm32 r6, 0x00060d00;
imm32 r7, 0x00070a00;
R7.H = R0.H << 10;
R6.H = R1.H << 10;
R5.H = R2.H << 10;
R4.H = R3.H << 10;
R3.H = R4.H << 10;
R2.H = R5.H << 10;
R1.H = R6.H << 10;
R0.H = R7.H << 10;
CHECKREG r1, 0x00000500;
CHECKREG r2, 0x00000060;
CHECKREG r3, 0x00000070;
CHECKREG r4, 0x0C000800;
CHECKREG r5, 0x08000090;
CHECKREG r6, 0x04000D00;
CHECKREG r7, 0x00000A00;
CHECKREG r0, 0x00000400;
imm32 r0, 0x00010000;
imm32 r1, 0x00010001;
imm32 r2, 0x00020001;
imm32 r3, 0x00030002;
imm32 r4, 0x00040003;
imm32 r5, 0x00050004;
imm32 r6, 0x00060005;
imm32 r7, 0x00070006;
R6.H = R0.H << 11;
R5.H = R1.H << 11;
R4.H = R2.H << 11;
R3.H = R3.H << 11;
R2.H = R4.H << 11;
R1.H = R5.H << 11;
R7.H = R6.H << 11;
R0.H = R7.H << 11;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x18000002;
CHECKREG r4, 0x10000003;
CHECKREG r5, 0x08000004;
CHECKREG r6, 0x08000005;
CHECKREG r7, 0x00000006;
CHECKREG r0, 0x00000000;
imm32 r0, 0x00010060;
imm32 r1, 0x00010060;
imm32 r2, 0x0002006f;
imm32 r3, 0x00030060;
imm32 r4, 0x00040060;
imm32 r5, 0x00050060;
imm32 r6, 0x00060060;
imm32 r7, 0x00070060;
R4.H = R0.H << 12;
R5.H = R1.H << 12;
R6.H = R2.H << 12;
R7.H = R3.H << 12;
R0.H = R4.H << 12;
R1.H = R5.H << 12;
R2.H = R6.H << 12;
R3.H = R7.H << 12;
CHECKREG r0, 0x00000060;
CHECKREG r1, 0x00000060;
CHECKREG r2, 0x0000006F;
CHECKREG r3, 0x00000060;
CHECKREG r4, 0x10000060;
CHECKREG r5, 0x10000060;
CHECKREG r6, 0x20000060;
CHECKREG r7, 0x30000060;
imm32 r0, 0x12010070;
imm32 r1, 0x23010070;
imm32 r2, 0x34020070;
imm32 r3, 0x45030070;
imm32 r4, 0x56040070;
imm32 r5, 0x67050070;
imm32 r6, 0x78060070;
imm32 r7, 0x09070070;
R4.H = R0.H << 3;
R5.H = R1.H << 3;
R6.H = R2.H << 3;
R7.H = R3.H << 3;
R0.H = R4.H << 3;
R1.H = R5.H << 3;
R2.H = R6.H << 3;
R3.H = R7.H << 3;
CHECKREG r0, 0x80400070;
CHECKREG r1, 0xC0400070;
CHECKREG r2, 0x00800070;
CHECKREG r3, 0x40C00070;
CHECKREG r4, 0x90080070;
CHECKREG r5, 0x18080070;
CHECKREG r6, 0xA0100070;
CHECKREG r7, 0x28180070;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,912 | sim/testsuite/bfin/c_ldst_ld_d_p_pp_h.s | //Original:/testcases/core/c_ldst_ld_d_p_pp_h/c_ldst_ld_d_p_pp_h.dsp
// Spec Reference: c_ldst ld d [p++] h
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_4;
.endif
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = W [ P5 ++ ] (Z);
R1 = W [ P1 ++ ] (Z);
R2 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R3 = W [ P3 ++ ] (Z);
.endif
R4 = W [ P4 ++ ] (Z);
R5 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00002223;
CHECKREG r2, 0x00004243;
.ifndef BFIN_HOST
CHECKREG r3, 0x00006263;
.endif
CHECKREG r4, 0x00008283;
CHECKREG r5, 0x00000203;
R1 = W [ P5 ++ ] (Z);
R2 = W [ P1 ++ ] (Z);
R3 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R4 = W [ P3 ++ ] (Z);
.endif
R5 = W [ P4 ++ ] (Z);
R6 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000203;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00002021;
CHECKREG r3, 0x00004041;
.ifndef BFIN_HOST
CHECKREG r4, 0x00006061;
.endif
CHECKREG r5, 0x00008081;
CHECKREG r6, 0x00000001;
R2 = W [ P5 ++ ] (Z);
R3 = W [ P1 ++ ] (Z);
R4 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R5 = W [ P3 ++ ] (Z);
.endif
R6 = W [ P4 ++ ] (Z);
R7 = W [ FP ++ ] (Z);
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00002627;
CHECKREG r4, 0x00004647;
.ifndef BFIN_HOST
CHECKREG r5, 0x00006667;
.endif
CHECKREG r6, 0x00008687;
CHECKREG r7, 0x00000607;
R3 = W [ P5 ++ ] (Z);
R4 = W [ P1 ++ ] (Z);
R5 = W [ P2 ++ ] (Z);
.ifndef BFIN_HOST
R6 = W [ P3 ++ ] (Z);
.endif
R7 = W [ P4 ++ ] (Z);
R0 = W [ FP ++ ] (Z);
CHECKREG r0, 0x00000405;
CHECKREG r2, 0x00000607;
CHECKREG r3, 0x00000405;
CHECKREG r4, 0x00002425;
.ifndef BFIN_HOST
CHECKREG r5, 0x00004445;
CHECKREG r6, 0x00006465;
.endif
CHECKREG r7, 0x00008485;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 7,126 | sim/testsuite/bfin/c_seq_ex1_j_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_j_mv_pop/c_seq_ex1_j_mv_pop.dsp
// Spec Reference: sequencer stage ex1 (jump + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
// RAISE 2; // RTN
JUMP.S LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// RAISE 6; // RTI
JUMP.S LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
// RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// RAISE 8; // RTI
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
// RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 10,550 | sim/testsuite/bfin/c_ldst_st_p_d_mm.s | //Original:testcases/core/c_ldst_st_p_d_mm/c_ldst_st_p_d_mm.dsp
// Spec Reference: c_ldst st_p++/p--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
imm32 r0, 0x0a231507;
imm32 r1, 0x1b342618;
imm32 r2, 0x2c453729;
imm32 r3, 0x3d56483a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f786a5c;
imm32 r6, 0x60897b6d;
imm32 r7, 0x719a8c7e;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
loadsym i3, DATA_ADDR_7;
P3 = I1; SP = I3;
[ P5 ++ ] = R0;
[ P1 ++ ] = R1;
[ P2 ++ ] = R2;
[ P3 ++ ] = R3;
[ P4 ++ ] = R4;
[ FP ++ ] = R5;
[ SP ++ ] = R6;
[ P5 ++ ] = R2;
[ P1 ++ ] = R3;
[ P2 ++ ] = R4;
[ P3 ++ ] = R5;
[ P4 ++ ] = R6;
[ FP ++ ] = R7;
[ SP ++ ] = R0;
[ P5 ++ ] = R5;
[ P1 ++ ] = R6;
[ P2 ++ ] = R7;
[ P3 ++ ] = R0;
[ P4 ++ ] = R1;
[ FP ++ ] = R2;
[ SP ++ ] = R3;
[ P5 ++ ] = R7;
[ P1 ++ ] = R0;
[ P2 ++ ] = R1;
[ P3 ++ ] = R2;
[ P4 ++ ] = R3;
[ FP ++ ] = R4;
[ SP ++ ] = R5;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
loadsym i3, DATA_ADDR_7;
P3 = I1; SP = I3;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R2 = [ P3 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
R6 = [ SP ++ ];
CHECKREG r0, 0x1B342618;
CHECKREG r1, 0x2C453729;
CHECKREG r2, 0x3D56483A;
CHECKREG r3, 0x4E67594B;
CHECKREG r4, 0x0A231507;
CHECKREG r5, 0x5F786A5C;
CHECKREG r6, 0x60897B6D;
CHECKREG r7, 0x719A8C7E;
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R2 = [ P3 ++ ];
R3 = [ P4 ++ ];
R4 = [ P5 ++ ];
R5 = [ FP ++ ];
R6 = [ SP ++ ];
CHECKREG r0, 0x3D56483A;
CHECKREG r1, 0x4E67594B;
CHECKREG r2, 0x5F786A5C;
CHECKREG r3, 0x60897B6D;
CHECKREG r4, 0x2C453729;
CHECKREG r5, 0x719A8C7E;
CHECKREG r6, 0x0A231507;
CHECKREG r7, 0x719A8C7E;
R1 = [ P1 ++ ];
R2 = [ P2 ++ ];
R3 = [ P3 ++ ];
R4 = [ P4 ++ ];
R5 = [ P5 ++ ];
R6 = [ FP ++ ];
R7 = [ SP ++ ];
CHECKREG r0, 0x3D56483A;
CHECKREG r1, 0x60897B6D;
CHECKREG r2, 0x719A8C7E;
CHECKREG r3, 0x0A231507;
CHECKREG r4, 0x1B342618;
CHECKREG r5, 0x5F786A5C;
CHECKREG r6, 0x2C453729;
CHECKREG r7, 0x3D56483A;
R3 = [ P1 ++ ];
R4 = [ P2 ++ ];
R5 = [ P3 ++ ];
R6 = [ P4 ++ ];
R7 = [ P5 ++ ];
R0 = [ FP ++ ];
R1 = [ SP ++ ];
CHECKREG r0, 0x4E67594B;
CHECKREG r1, 0x5F786A5C;
CHECKREG r2, 0x719A8C7E;
CHECKREG r3, 0x0A231507;
CHECKREG r4, 0x1B342618;
CHECKREG r5, 0x2C453729;
CHECKREG r6, 0x3D56483A;
CHECKREG r7, 0x719A8C7E;
// reset values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
[ P5 -- ] = R0;
[ P1 -- ] = R1;
[ P2 -- ] = R2;
[ P3 -- ] = R3;
[ P4 -- ] = R4;
[ FP -- ] = R5;
[ SP -- ] = R6;
[ P5 -- ] = R2;
[ P1 -- ] = R3;
[ P2 -- ] = R4;
[ P3 -- ] = R5;
[ P4 -- ] = R6;
[ FP -- ] = R7;
[ SP -- ] = R0;
[ P5 -- ] = R5;
[ P1 -- ] = R6;
[ P2 -- ] = R7;
[ P3 -- ] = R0;
[ P4 -- ] = R1;
[ FP -- ] = R2;
[ SP -- ] = R3;
[ P5 -- ] = R6;
[ P1 -- ] = R7;
[ P2 -- ] = R0;
[ P3 -- ] = R1;
[ P4 -- ] = R2;
[ FP -- ] = R3;
[ SP -- ] = R4;
[ P1 -- ] = R0;
[ P2 -- ] = R1;
[ P3 -- ] = R2;
[ P4 -- ] = R3;
[ FP -- ] = R4;
[ SP -- ] = R5;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x20;
loadsym p1, DATA_ADDR_2, 0x20;
loadsym p2, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym p4, DATA_ADDR_5, 0x20;
loadsym fp, DATA_ADDR_6, 0x20;
loadsym i3, DATA_ADDR_7, 0x20;
P3 = I1; SP = I3;
R0 = [ P1 -- ];
R1 = [ P2 -- ];
R2 = [ P3 -- ];
R3 = [ P4 -- ];
R4 = [ P5 -- ];
R5 = [ FP -- ];
R6 = [ SP -- ];
CHECKREG r0, 0x5F786A5C;
CHECKREG r1, 0x719A8C7E;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x4E67594B;
CHECKREG r5, 0x2C453729;
CHECKREG r6, 0x3D56483A;
CHECKREG r7, 0x719A8C7E;
R2 = [ P1 -- ];
R3 = [ P2 -- ];
R4 = [ P3 -- ];
R5 = [ P4 -- ];
R6 = [ P5 -- ];
R7 = [ FP -- ];
R0 = [ SP -- ];
CHECKREG r0, 0x4E67594B;
CHECKREG r1, 0x719A8C7E;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x2C453729;
CHECKREG r5, 0x3D56483A;
CHECKREG r6, 0x719A8C7E;
R3 = [ P1 -- ];
R4 = [ P2 -- ];
R5 = [ P3 -- ];
R6 = [ P4 -- ];
R7 = [ P5 -- ];
R0 = [ FP -- ];
R1 = [ SP -- ];
CHECKREG r0, 0x719A8C7E;
CHECKREG r1, 0x0A231507;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x3D56483A;
CHECKREG r4, 0x719A8C7E;
CHECKREG r5, 0x4E67594B;
CHECKREG r6, 0x5F786A5C;
CHECKREG r7, 0x2C453729;
R5 = [ P1 -- ];
R6 = [ P2 -- ];
R7 = [ P3 -- ];
R0 = [ P4 -- ];
R1 = [ P5 -- ];
R2 = [ FP -- ];
R3 = [ SP -- ];
CHECKREG r0, 0x719A8C7E;
CHECKREG r1, 0x3D56483A;
CHECKREG r2, 0x0A231507;
CHECKREG r3, 0x1B342618;
CHECKREG r4, 0x719A8C7E;
CHECKREG r5, 0x719A8C7E;
CHECKREG r6, 0x4E67594B;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 8,575 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_ln/c_dsp32shiftim_ahalf_ln.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5)
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x1000c000;
imm32 r1, 0x1000c001;
imm32 r2, 0x1000c002;
imm32 r3, 0x1000c003;
imm32 r4, 0x1000c004;
imm32 r5, 0x1000c005;
imm32 r6, 0x1000c006;
imm32 r7, 0x1000c007;
R0.L = R0.L << 1;
R1.L = R1.L << 1;
R2.L = R2.L << 1;
R3.L = R3.L << 1;
R4.L = R4.L << 1;
R5.L = R5.L << 1;
R6.L = R6.L << 1;
R7.L = R7.L << 1;
CHECKREG r0, 0x10008000;
CHECKREG r1, 0x10008002;
CHECKREG r2, 0x10008004;
CHECKREG r3, 0x10008006;
CHECKREG r4, 0x10008008;
CHECKREG r5, 0x1000800A;
CHECKREG r6, 0x1000800C;
CHECKREG r7, 0x1000800E;
imm32 r0, 0x20008001;
imm32 r1, 0x20000001;
imm32 r2, 0x2000d002;
imm32 r3, 0x2000e003;
imm32 r4, 0x2000f004;
imm32 r5, 0x2000c005;
imm32 r6, 0x2000d006;
imm32 r7, 0x2000e007;
R7.L = R0.L << 1;
R6.L = R1.L << 1;
R5.L = R2.L << 1;
R4.L = R3.L << 1;
R3.L = R4.L << 1;
R2.L = R5.L << 1;
R1.L = R6.L << 1;
R0.L = R7.L << 1;
imm32 r0, 0x3000c001;
imm32 r1, 0x3000d001;
imm32 r2, 0x3000000f;
imm32 r3, 0x3000e003;
imm32 r4, 0x3000f004;
imm32 r5, 0x3000f005;
imm32 r6, 0x3000f006;
imm32 r7, 0x3000f007;
R6.L = R0.L << 12;
R7.L = R1.L << 12;
R5.L = R2.L << 12;
R4.L = R3.L << 12;
R3.L = R4.L << 12;
R2.L = R5.L << 12;
R1.L = R6.L << 12;
R0.L = R7.L << 12;
CHECKREG r1, 0x30000000;
CHECKREG r0, 0x30000000;
CHECKREG r2, 0x30000000;
CHECKREG r3, 0x30000000;
CHECKREG r4, 0x30003000;
CHECKREG r5, 0x3000F000;
CHECKREG r6, 0x30001000;
CHECKREG r7, 0x30001000;
imm32 r0, 0x40009001;
imm32 r1, 0x4000a001;
imm32 r2, 0x4000b002;
imm32 r3, 0x40000010;
imm32 r4, 0x4000c004;
imm32 r5, 0x4000d005;
imm32 r6, 0x4000e006;
imm32 r7, 0x4000f007;
R5.L = R0.L << 13;
R6.L = R1.L << 13;
R7.L = R2.L << 13;
R0.L = R3.L << 13;
R1.L = R4.L << 13;
R2.L = R5.L << 13;
R3.L = R6.L << 13;
R4.L = R7.L << 13;
CHECKREG r0, 0x40000000;
CHECKREG r1, 0x40008000;
CHECKREG r2, 0x40000000;
CHECKREG r3, 0x40000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x40002000;
CHECKREG r6, 0x40002000;
CHECKREG r7, 0x40004000;
imm32 r0, 0x00005000;
imm32 r1, 0x00015000;
imm32 r2, 0x00025000;
imm32 r3, 0x00035000;
imm32 r4, 0x00045000;
imm32 r5, 0x00055000;
imm32 r6, 0x00065000;
imm32 r7, 0x00075500;
R0.L = R0.H << 10;
R1.L = R1.H << 10;
R2.L = R2.H << 10;
R3.L = R3.H << 10;
R4.L = R4.H << 10;
R5.L = R5.H << 10;
R6.L = R6.H << 10;
R7.L = R7.H << 10;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010400;
CHECKREG r2, 0x00020800;
CHECKREG r3, 0x00030C00;
CHECKREG r4, 0x00041000;
CHECKREG r5, 0x00051400;
CHECKREG r6, 0x00061800;
CHECKREG r7, 0x00071C00;
imm32 r0, 0x90010000;
imm32 r1, 0x90010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R2.L = R0.H << 11;
R3.L = R1.H << 11;
R4.L = R2.H << 11;
R5.L = R3.H << 11;
R6.L = R4.H << 11;
R7.L = R5.H << 11;
R0.L = R6.H << 11;
R1.L = R7.H << 11;
CHECKREG r0, 0x90013000;
CHECKREG r1, 0x90013800;
CHECKREG r2, 0x90020800;
CHECKREG r3, 0x90030800;
CHECKREG r4, 0x90041000;
CHECKREG r5, 0x90051800;
CHECKREG r6, 0x90062000;
CHECKREG r7, 0x90072800;
imm32 r0, 0xa0010600;
imm32 r1, 0xa0010600;
imm32 r2, 0xa002060f;
imm32 r3, 0xa0030600;
imm32 r4, 0xa0040600;
imm32 r5, 0xa0050600;
imm32 r6, 0xa0060600;
imm32 r7, 0xa0070600;
R0.L = R0.H << 12;
R1.L = R1.H << 12;
R2.L = R2.H << 12;
R3.L = R3.H << 12;
R4.L = R4.H << 12;
R5.L = R5.H << 12;
R6.L = R6.H << 12;
R7.L = R7.H << 12;
CHECKREG r0, 0xA0011000;
CHECKREG r1, 0xA0011000;
CHECKREG r2, 0xA0022000;
CHECKREG r3, 0xA0033000;
CHECKREG r4, 0xA0044000;
CHECKREG r5, 0xA0055000;
CHECKREG r6, 0xA0066000;
CHECKREG r7, 0xA0077000;
imm32 r0, 0xc0010701;
imm32 r1, 0xc0010701;
imm32 r2, 0xc0020702;
imm32 r3, 0xc0030710;
imm32 r4, 0xc0040704;
imm32 r5, 0xc0050705;
imm32 r6, 0xc0060706;
imm32 r7, 0xc0070707;
R0.L = R0.H << 13;
R1.L = R1.H << 13;
R2.L = R2.H << 13;
R3.L = R3.H << 13;
R4.L = R4.H << 13;
R5.L = R5.H << 13;
R6.L = R6.H << 13;
R7.L = R7.H << 13;
CHECKREG r0, 0xC0012000;
CHECKREG r1, 0xC0012000;
CHECKREG r2, 0xC0024000;
CHECKREG r3, 0xC0036000;
CHECKREG r4, 0xC0048000;
CHECKREG r5, 0xC005A000;
CHECKREG r6, 0xC006C000;
CHECKREG r7, 0xC007E000;
imm32 r0, 0x00008000;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = R0.L << 0;
R1.H = R1.L << 1;
R2.H = R2.L << 2;
R3.H = R3.L << 3;
R4.H = R4.L << 4;
R5.H = R5.L << 5;
R6.H = R6.L << 6;
R7.H = R7.L << 7;
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x00028001;
CHECKREG r2, 0x00088002;
CHECKREG r3, 0x00188003;
CHECKREG r4, 0x00408004;
CHECKREG r5, 0x00A08005;
CHECKREG r6, 0x01808006;
CHECKREG r7, 0x03808007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R2.H = R0.L << 8;
R3.H = R1.L << 9;
R4.H = R2.L << 10;
R5.H = R3.L << 11;
R6.H = R4.L << 12;
R7.H = R5.L << 13;
R0.H = R6.L << 14;
R1.H = R7.L << 15;
CHECKREG r0, 0x8000D001;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x0100D002;
CHECKREG r3, 0x0200D003;
CHECKREG r4, 0x0800D004;
CHECKREG r5, 0x1800D005;
CHECKREG r6, 0x4000D006;
CHECKREG r7, 0xA000D007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = R0.L << 12;
R1.H = R1.L << 12;
R2.H = R2.L << 12;
R3.H = R3.L << 12;
R4.H = R4.L << 12;
R5.H = R5.L << 12;
R6.H = R6.L << 12;
R7.H = R7.L << 12;
CHECKREG r0, 0x1000E001;
CHECKREG r1, 0x1000E001;
CHECKREG r2, 0xF000000F;
CHECKREG r3, 0x3000E003;
CHECKREG r4, 0x4000E004;
CHECKREG r5, 0x5000E005;
CHECKREG r6, 0x6000E006;
CHECKREG r7, 0x7000E007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R5.H = R0.L << 13;
R6.H = R1.L << 13;
R7.H = R2.L << 13;
R0.H = R3.L << 13;
R1.H = R4.L << 13;
R2.H = R5.L << 13;
R3.H = R6.L << 13;
R4.H = R7.L << 13;
CHECKREG r0, 0x0000F001;
CHECKREG r1, 0x8000F001;
CHECKREG r2, 0xA000F002;
CHECKREG r3, 0xC0000010;
CHECKREG r4, 0xE000F004;
CHECKREG r5, 0x2000F005;
CHECKREG r6, 0x2000F006;
CHECKREG r7, 0x4000F007;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x90000000;
imm32 r1, 0x90010000;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R4.H = R0.H << 10;
R5.H = R1.H << 10;
R6.H = R2.H << 10;
R7.H = R3.H << 10;
R0.H = R4.H << 10;
R1.H = R5.H << 10;
R2.H = R6.H << 10;
R3.H = R7.H << 10;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x04000000;
CHECKREG r6, 0x08000000;
CHECKREG r7, 0x0C000000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R7.H = R0.H << 11;
R0.H = R1.H << 11;
R1.H = R2.H << 11;
R2.H = R3.H << 11;
R3.H = R4.H << 11;
R4.H = R5.H << 11;
R5.H = R6.H << 11;
R6.H = R7.H << 11;
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x10000001;
CHECKREG r2, 0x18000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x28000000;
CHECKREG r5, 0x30000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x08000000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R6.H = R0.H << 12;
R7.H = R1.H << 12;
R0.H = R2.H << 12;
R1.H = R3.H << 12;
R2.H = R4.H << 12;
R3.H = R5.H << 12;
R4.H = R6.H << 12;
R5.H = R7.H << 12;
CHECKREG r0, 0x20000000;
CHECKREG r1, 0x30000000;
CHECKREG r2, 0x4000000F;
CHECKREG r3, 0x50000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x10000000;
CHECKREG r7, 0x10000000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R5.H = R0.H << 3;
R6.H = R1.H << 3;
R7.H = R2.H << 3;
R0.H = R3.H << 3;
R1.H = R4.H << 3;
R2.H = R5.H << 3;
R3.H = R6.H << 3;
R4.H = R7.H << 3;
CHECKREG r0, 0x80180000;
CHECKREG r1, 0x80200000;
CHECKREG r2, 0x00400000;
CHECKREG r3, 0x00400010;
CHECKREG r4, 0x00800000;
CHECKREG r5, 0x80080000;
CHECKREG r6, 0x80080000;
CHECKREG r7, 0x80100000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,922 | sim/testsuite/bfin/c_ldst_ld_d_p_b.s | //Original:/testcases/core/c_ldst_ld_d_p_b/c_ldst_ld_d_p_b.dsp
// Spec Reference: c_ldst ld d [p] b
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
// load 8 bits from memory, and zero extend into 32-bit reg
R0 = B [ P1 ] (Z);
R1 = B [ P2 ] (Z);
.ifndef BFIN_HOST
R2 = B [ P3 ] (Z);
.else
R2 = 0x43 (Z);
.endif
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ P5 ] (Z);
R6 = B [ FP ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000083;
CHECKREG r6, 0x00000003;
R1 = B [ P2 ] (Z);
.ifndef BFIN_HOST
R2 = B [ P3 ] (Z);
.else
R2 = 0x43 (Z);
.endif
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ FP ] (Z);
R7 = B [ P1 ] (Z);
CHECKREG r0, 0x00000003;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
CHECKREG r7, 0x00000003;
.ifndef BFIN_HOST
R2 = B [ P3 ] (Z);
.else
R2 = 0x43 (Z);
.endif
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ FP ] (Z);
R7 = B [ P1 ] (Z);
R0 = B [ P2 ] (Z);
CHECKREG r0, 0x00000023;
CHECKREG r1, 0x00000023;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
CHECKREG r7, 0x00000003;
R3 = B [ P4 ] (Z);
R4 = B [ P5 ] (Z);
R5 = B [ FP ] (Z);
R7 = B [ P1 ] (Z);
R0 = B [ P2 ] (Z);
.ifndef BFIN_HOST
R1 = B [ P3 ] (Z);
.else
R1 = 0x43;
.endif
CHECKREG r0, 0x00000023;
CHECKREG r1, 0x00000043;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000063;
CHECKREG r4, 0x00000083;
CHECKREG r5, 0x00000003;
CHECKREG r7, 0x00000003;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,952 | sim/testsuite/bfin/c_ldimmhalf_lzhi_pr.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_lzhi_pr/c_ldimmhalf_lzhi_pr.dsp
// Spec Reference: ldimmhalf lzhi preg
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Preg
//lz(p0)=0x0001;
//h(p0) =0x0000;
P1 = 0x0003 (Z);
P1.H = 0x0002;
P2 = 0x0005 (Z);
P2.H = 0x0004;
P3 = 0x0007 (Z);
P3.H = 0x0006;
P4 = 0x0009 (Z);
P4.H = 0x0008;
P5 = 0x000b (Z);
P5.H = 0x000a;
FP = 0x000d (Z);
FP.H = 0x000c;
SP = 0x000f (Z);
SP.H = 0x000e;
CHECKREG p1, 0x00020003;
CHECKREG p2, 0x00040005;
CHECKREG p3, 0x00060007;
CHECKREG p4, 0x00080009;
CHECKREG p5, 0x000a000b;
CHECKREG fp, 0x000c000d;
CHECKREG sp, 0x000e000f;
P1 = 0x0030 (Z);
P1.H = 0x0020;
P2 = 0x0050 (Z);
P2.H = 0x0040;
P3 = 0x0070 (Z);
P3.H = 0x0060;
P4 = 0x0090 (Z);
P4.H = 0x0080;
P5 = 0x00b0 (Z);
P5.H = 0x00a0;
FP = 0x00d0 (Z);
FP.H = 0x00c0;
SP = 0x00f0 (Z);
SP.H = 0x00e0;
//CHECKREG p0, 0x00000010;
CHECKREG p1, 0x00200030;
CHECKREG p2, 0x00400050;
CHECKREG p3, 0x00600070;
CHECKREG p4, 0x00800090;
CHECKREG p5, 0x00a000b0;
CHECKREG fp, 0x00c000d0;
CHECKREG sp, 0x00e000f0;
P1 = 0x0300 (Z);
P1.H = 0x0200;
P2 = 0x0500 (Z);
P2.H = 0x0400;
P3 = 0x0700 (Z);
P3.H = 0x0600;
P4 = 0x0900 (Z);
P4.H = 0x0800;
P5 = 0x0b00 (Z);
P5.H = 0x0a00;
FP = 0x0d00 (Z);
FP.H = 0x0c00;
SP = 0x0f00 (Z);
SP.H = 0x0e00;
CHECKREG p1, 0x02000300;
CHECKREG p2, 0x04000500;
CHECKREG p3, 0x06000700;
CHECKREG p4, 0x08000900;
CHECKREG p5, 0x0a000b00;
CHECKREG fp, 0x0c000d00;
CHECKREG sp, 0x0e000f00;
P1 = 0x3000 (Z);
P1.H = 0x2000;
P2 = 0x5000 (Z);
P2.H = 0x4000;
P3 = 0x7000 (Z);
P3.H = 0x6000;
P4 = 0x9000 (Z);
P4.H = 0x8000;
P5 = 0xb000 (Z);
P5.H = 0xa000;
FP = 0xd000 (Z);
FP.H = 0xc000;
SP = 0xf000 (Z);
SP.H = 0xe000;
CHECKREG p1, 0x20003000;
CHECKREG p2, 0x40005000;
CHECKREG p3, 0x60007000;
CHECKREG p4, 0x80009000;
CHECKREG p5, 0xa000b000;
CHECKREG fp, 0xc000d000;
CHECKREG sp, 0xe000f000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,822 | sim/testsuite/bfin/c_dsp32mac_dr_a0_t.s | //Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp
// Spec Reference: dsp32mac dr a0 t (truncation)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (T);
R1 = A0.w;
A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (T);
R3 = A0.w;
A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (T);
R5 = A0.w;
A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0xA354FF22;
CHECKREG r1, 0xFF221DD6;
CHECKREG r2, 0xC12436FD;
CHECKREG r3, 0x36FD0FF8;
CHECKREG r4, 0xEFBC3D71;
CHECKREG r5, 0x3D716BD0;
CHECKREG r6, 0xE00C45E2;
CHECKREG r7, 0x45E2903C;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0xb0069007;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.L = ( A0 = R1.L * R0.L ) (T);
R1 = A0.w;
R2.L = ( A0 += R2.L * R3.H ) (T);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.L ) (T);
R5 = A0.w;
R6.L = ( A0 = R6.H * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0x6354011E;
CHECKREG r1, 0x011EBDD6;
CHECKREG r2, 0xA124CB17;
CHECKREG r3, 0xCB172B82;
CHECKREG r4, 0xCFBCB2F9;
CHECKREG r5, 0xB2F9515A;
CHECKREG r6, 0xE00CE626;
CHECKREG r7, 0xE6263550;
// The result accumulated in A , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.L = ( A0 -= R1.L * R0.L ) (T);
R1 = A0.w;
R2.L = ( A0 = R2.H * R3.L ) (T);
R3 = A0.w;
R4.L = ( A0 -= R4.H * R5.H ) (T);
R5 = A0.w;
R6.L = ( A0 += R6.L * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0x5354D42C;
CHECKREG r1, 0xD42C177A;
CHECKREG r2, 0x71246305;
CHECKREG r3, 0x6305AFF8;
CHECKREG r4, 0x9FBC1C7B;
CHECKREG r5, 0x1C7B9C20;
CHECKREG r6, 0xB00C074B;
CHECKREG r7, 0x074B208C;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
A1 = R1.L * R0.L (M), R0.L = ( A0 += R1.L * R0.L ) (T);
R1 = A0.w;
A1 += R2.L * R3.H (M), R2.L = ( A0 -= R2.H * R3.L ) (T);
R3 = A0.w;
A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (T);
R5 = A0.w;
A1 -= R6.H * R7.H (M), R6.L = ( A0 += R6.L * R7.H ) (T);
R7 = A0.w;
CHECKREG r0, 0x3354066D;
CHECKREG r1, 0x066D3E62;
CHECKREG r2, 0x71240667;
CHECKREG r3, 0x06670E6A;
CHECKREG r4, 0xAFBC1CB7;
CHECKREG r5, 0x1CB733D8;
CHECKREG r6, 0xC00CCF17;
CHECKREG r7, 0xCF173844;
pass
|
tactcomplabs/xbgas-binutils-gdb | 14,760 | sim/testsuite/bfin/c_logi2op_bittst.s | //Original:/testcases/core/c_logi2op_bittst/c_logi2op_bittst.dsp
// Spec Reference: Logi2op functions: bittst
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// bit(0-7) tst set clr toggle
CC = BITTST ( R0 , 0 ); /* cc = 0 */
BITSET( R0 , 0 ); /* r0 = 0x00000001 */
R1 = CC;
CC = BITTST ( R0 , 0 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 0 ); /* r0 = 0x00000000 */
CC = BITTST ( R0 , 0 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 0 ); /* r0 = 0x00000001 */
CC = BITTST ( R0 , 0 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CC = BITTST ( R1 , 1 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 1 ); /* r1 = 0x00000002 */
CC = BITTST ( R1 , 1 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 1 ); /* r1 = 0x00000000 */
CC = BITTST ( R1 , 1 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 1 ); /* r1 = 0x00000002 */
CC = BITTST ( R1 , 1 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CC = BITTST ( R2 , 2 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 2 ); /* r2 = 0x00000004 */
CC = BITTST ( R2 , 2 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 2 ); /* r2 = 0x00000000 */
CC = BITTST ( R2 , 2 ); /* cc = 1 */
R5 = CC;
BITTGL( R2 , 2 ); /* r2 = 0x00000004 */
CC = BITTST ( R2 , 2 ); /* cc = 1 */
R6 = CC;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CC = BITTST ( R3 , 3 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 3 ); /* r3 = 0x00000008 */
CC = BITTST ( R3 , 3 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 3 ); /* r3 = 0x00000000 */
CC = BITTST ( R3 , 3 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 3 ); /* r3 = 0x00000008 */
CC = BITTST ( R3 , 3 ); /* cc = 1 */
R7 = CC;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000008;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CC = BITTST ( R4 , 4 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 4 ); /* r4 = 0x00000010 */
CC = BITTST ( R4 , 4 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 4 ); /* r4 = 0x00000000 */
CC = BITTST ( R4 , 4 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 4 ); /* r4 = 0x00000010 */
CC = BITTST ( R4 , 4 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CC = BITTST ( R5 , 5 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 5 ); /* r5 = 0x00000020 */
CC = BITTST ( R5 , 5 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 5 ); /* r5 = 0x00000000 */
CC = BITTST ( R5 , 5 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 5 ); /* r5 = 0x00000020 */
CC = BITTST ( R5 , 5 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CC = BITTST ( R6 , 6 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 6 ); /* r6 = 0x00000040 */
CC = BITTST ( R6 , 6 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 6 ); /* r6 = 0x00000000 */
CC = BITTST ( R6 , 6 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 6 ); /* r6 = 0x00000040 */
CC = BITTST ( R6 , 6 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x00000040;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CC = BITTST ( R7 , 7 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 7 ); /* r7 = 0x00000080 */
CC = BITTST ( R7 , 7 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 7 ); /* r7 = 0x00000000 */
CC = BITTST ( R7 , 7 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 7 ); /* r7 = 0x00000080 */
CC = BITTST ( R7 , 7 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000040;
CHECKREG r7, 0x00000080;
// bit(8-15) tst set clr toggle
CC = BITTST ( R0 , 8 ); /* cc = 0 */
R1 = CC;
BITSET( R0 , 8 ); /* r0 = 0x00000101 */
CC = BITTST ( R0 , 8 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 8 ); /* r0 = 0x00000000 */
CC = BITTST ( R0 , 8 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 8 ); /* r0 = 0x00000101 */
CC = BITTST ( R0 , 8 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x00000100;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CC = BITTST ( R1 , 9 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 9 ); /* r1 = 0x00000200 */
CC = BITTST ( R1 , 9 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 9 ); /* r1 = 0x00000000 */
CC = BITTST ( R1 , 9 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 9 ); /* r1 = 0x00000200 */
CC = BITTST ( R1 , 9 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x00000200;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CC = BITTST ( R2 , 10 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 10 ); /* r2 = 0x00000400 */
CC = BITTST ( R2 , 10 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 10 ); /* r2 = 0x00000000 */
CC = BITTST ( R2 , 10 ); /* cc = 1 */
R5 = CC;
BITTGL( R2 , 10 ); /* r2 = 0x00000400 */
CC = BITTST ( R2 , 10 ); /* cc = 1 */
R6 = CC;
CHECKREG r2, 0x00000400;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CC = BITTST ( R3 , 11 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 11 ); /* r3 = 0x00000800 */
CC = BITTST ( R3 , 11 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 11 ); /* r3 = 0x00000000 */
CC = BITTST ( R3 , 11 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 11 ); /* r3 = 0x00000800 */
CC = BITTST ( R3 , 11 ); /* cc = 1 */
R7 = CC;
CHECKREG r3, 0x00000800;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CC = BITTST ( R4 , 12 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 12 ); /* r4 = 0x00001000 */
CC = BITTST ( R4 , 12 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 12 ); /* r4 = 0x00000000 */
CC = BITTST ( R4 , 12 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 12 ); /* r4 = 0x00001000 */
CC = BITTST ( R4 , 12 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x00001000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CC = BITTST ( R5 , 13 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 13 ); /* r5 = 0x00002000 */
CC = BITTST ( R5 , 13 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 13 ); /* r5 = 0x00000000 */
CC = BITTST ( R5 , 13 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 13 ); /* r5 = 0x00002000 */
CC = BITTST ( R5 , 13 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x00002000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CC = BITTST ( R6 , 14 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 14 ); /* r6 = 0x00004000 */
CC = BITTST ( R6 , 14 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 14 ); /* r6 = 0x00000000 */
CC = BITTST ( R6 , 14 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 14 ); /* r6 = 0x00004000 */
CC = BITTST ( R6 , 14 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x00004000;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CC = BITTST ( R7 , 15 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 15 ); /* r7 = 0x00008000 */
CC = BITTST ( R7 , 15 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 15 ); /* r7 = 0x00000000 */
CC = BITTST ( R7 , 15 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 15 ); /* r7 = 0x00008000 */
CC = BITTST ( R7 , 15 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00001000;
CHECKREG r5, 0x00002000;
CHECKREG r6, 0x00004000;
CHECKREG r7, 0x00008000;
// bit(16-23) tst set clr toggle
CC = BITTST ( R0 , 16 ); /* cc = 0 */
R1 = CC;
BITSET( R0 , 16 ); /* r0 = 0x00010000 */
CC = BITTST ( R0 , 16 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 16 ); /* r0 = 0x00000000 */
CC = BITTST ( R0 , 16 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 16 ); /* r0 = 0x00010000 */
CC = BITTST ( R0 , 16 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x00010000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CC = BITTST ( R1 , 17 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 17 ); /* r1 = 0x00020000 */
CC = BITTST ( R1 , 17 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 17 ); /* r1 = 0x00000000 */
CC = BITTST ( R1 , 17 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 17 ); /* r1 = 0x00020000 */
CC = BITTST ( R1 , 17 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x00020000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CC = BITTST ( R2 , 18 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 18 ); /* r2 = 0x00020000 */
CC = BITTST ( R2 , 18 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 18 ); /* r2 = 0x00000000 */
CC = BITTST ( R2 , 18 ); /* cc = 1 */
R4 = CC;
BITTGL( R2 , 18 ); /* r2 = 0x00020000 */
CC = BITTST ( R2 , 18 ); /* cc = 1 */
R5 = CC;
CHECKREG r2, 0x00040000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00004000;
CC = BITTST ( R3 , 19 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 19 ); /* r3 = 0x00080000 */
CC = BITTST ( R3 , 19 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 19 ); /* r3 = 0x00000000 */
CC = BITTST ( R3 , 19 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 19 ); /* r3 = 0x00080000 */
CC = BITTST ( R3 , 19 ); /* cc = 1 */
R7 = CC;
CHECKREG r3, 0x00080000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CC = BITTST ( R4 , 20 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 20 ); /* r4 = 0x00100000 */
CC = BITTST ( R4 , 20 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 20 ); /* r4 = 0x00000000 */
CC = BITTST ( R4 , 20 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 20 ); /* r4 = 0x00100000 */
CC = BITTST ( R4 , 20 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x00100000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CC = BITTST ( R5 , 21 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 21 ); /* r5 = 0x00200000 */
CC = BITTST ( R5 , 21 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 21 ); /* r5 = 0x00000000 */
CC = BITTST ( R5 , 21 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 21 ); /* r5 = 0x00200000 */
CC = BITTST ( R5 , 21 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x00200000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CC = BITTST ( R6 , 22 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 22 ); /* r6 = 0x00400000 */
CC = BITTST ( R6 , 22 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 22 ); /* r6 = 0x00000000 */
CC = BITTST ( R6 , 22 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 22 ); /* r6 = 0x00400000 */
CC = BITTST ( R6 , 22 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x00400000;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CC = BITTST ( R7 , 23 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 23 ); /* r7 = 0x00800000 */
CC = BITTST ( R7 , 23 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 23 ); /* r7 = 0x00000000 */
CC = BITTST ( R7 , 23 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 23 ); /* r7 = 0x00800000 */
CC = BITTST ( R7 , 23 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00100000;
CHECKREG r5, 0x00200000;
CHECKREG r6, 0x00400000;
CHECKREG r7, 0x00800000;
// bit(24-31) tst set clr toggle
CC = BITTST ( R0 , 24 ); /* cc = 0 */
R1 = CC;
BITSET( R0 , 24 ); /* r0 = 0x00000101 */
CC = BITTST ( R0 , 24 ); /* cc = 1 */
R2 = CC;
BITCLR( R0 , 24 ); /* r0 = 0x01000000 */
CC = BITTST ( R0 , 24 ); /* cc = 1 */
R3 = CC;
BITTGL( R0 , 24 ); /* r0 = 0x01000000 */
CC = BITTST ( R0 , 24 ); /* cc = 1 */
R4 = CC;
CHECKREG r0, 0x01000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CC = BITTST ( R1 , 25 ); /* cc = 0 */
R2 = CC;
BITSET( R1 , 25 ); /* r1 = 0x02000000 */
CC = BITTST ( R1 , 25 ); /* cc = 1 */
R3 = CC;
BITCLR( R1 , 25 ); /* r1 = 0x00000000 */
CC = BITTST ( R1 , 25 ); /* cc = 1 */
R4 = CC;
BITTGL( R1 , 25 ); /* r1 = 0x02000000 */
CC = BITTST ( R1 , 25 ); /* cc = 1 */
R5 = CC;
CHECKREG r1, 0x02000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CC = BITTST ( R2 , 26 ); /* cc = 0 */
R3 = CC;
BITSET( R2 , 26 ); /* r2 = 0x04000000 */
CC = BITTST ( R2 , 26 ); /* cc = 1 */
R4 = CC;
BITCLR( R2 , 26 ); /* r2 = 0x00000000 */
CC = BITTST ( R2 , 26 ); /* cc = 1 */
R5 = CC;
BITTGL( R2 , 26 ); /* r2 = 0x04000000 */
CC = BITTST ( R2 , 26 ); /* cc = 1 */
R6 = CC;
CHECKREG r2, 0x04000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CC = BITTST ( R3 , 27 ); /* cc = 0 */
R4 = CC;
BITSET( R3 , 27 ); /* r3 = 0x08000000 */
CC = BITTST ( R3 , 27 ); /* cc = 1 */
R5 = CC;
BITCLR( R3 , 27 ); /* r3 = 0x00000000 */
CC = BITTST ( R3 , 27 ); /* cc = 1 */
R6 = CC;
BITTGL( R3 , 27 ); /* r3 = 0x08000000 */
CC = BITTST ( R3 , 27 ); /* cc = 1 */
R7 = CC;
CHECKREG r3, 0x08000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CC = BITTST ( R4 , 28 ); /* cc = 0 */
R5 = CC;
BITSET( R4 , 28 ); /* r4 = 0x10000000 */
CC = BITTST ( R4 , 28 ); /* cc = 1 */
R6 = CC;
BITCLR( R4 , 28 ); /* r4 = 0x00000000 */
CC = BITTST ( R4 , 28 ); /* cc = 1 */
R7 = CC;
BITTGL( R4 , 28 ); /* r4 = 0x10000000 */
CC = BITTST ( R4 , 28 ); /* cc = 1 */
R0 = CC;
CHECKREG r4, 0x10000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CC = BITTST ( R5 , 29 ); /* cc = 0 */
R6 = CC;
BITSET( R5 , 29 ); /* r5 = 0x20000000 */
CC = BITTST ( R5 , 29 ); /* cc = 1 */
R7 = CC;
BITCLR( R5 , 29 ); /* r5 = 0x00000000 */
CC = BITTST ( R5 , 29 ); /* cc = 1 */
R0 = CC;
BITTGL( R5 , 29 ); /* r5 = 0x20000000 */
CC = BITTST ( R5 , 29 ); /* cc = 1 */
R1 = CC;
CHECKREG r5, 0x20000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CC = BITTST ( R6 , 30 ); /* cc = 0 */
R7 = CC;
BITSET( R6 , 30 ); /* r6 = 0x40000000 */
CC = BITTST ( R6 , 30 ); /* cc = 1 */
R0 = CC;
BITCLR( R6 , 30 ); /* r6 = 0x00000000 */
CC = BITTST ( R6 , 30 ); /* cc = 1 */
R1 = CC;
BITTGL( R6 , 30 ); /* r6 = 0x40000000 */
CC = BITTST ( R6 , 30 ); /* cc = 1 */
R2 = CC;
CHECKREG r6, 0x40000000;
CHECKREG r7, 0x00000000;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000001;
CC = BITTST ( R7 , 31 ); /* cc = 0 */
R0 = CC;
BITSET( R7 , 31 ); /* r7 = 0x80000000 */
CC = BITTST ( R7 , 31 ); /* cc = 1 */
R1 = CC;
BITCLR( R7 , 31 ); /* r7 = 0x00000000 */
CC = BITTST ( R7 , 31 ); /* cc = 1 */
R2 = CC;
BITTGL( R7 , 31 ); /* r7 = 0x80000000 */
CC = BITTST ( R7 , 31 ); /* cc = 1 */
R3 = CC;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x10000000;
CHECKREG r5, 0x20000000;
CHECKREG r6, 0x40000000;
CHECKREG r7, 0x80000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,070 | sim/testsuite/bfin/c_dsp32shift_ahalf_ln.s | //Original:/testcases/core/c_dsp32shift_ahalf_ln/c_dsp32shift_ahalf_ln.dsp
// Spec Reference: dsp32shift ashift
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x0000c001;
imm32 r2, 0x0000c002;
imm32 r3, 0x0000c003;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000c006;
imm32 r7, 0x0000c007;
R0.L = ASHIFT R0.L BY R0.L;
R1.L = ASHIFT R1.L BY R0.L;
R2.L = ASHIFT R2.L BY R0.L;
R3.L = ASHIFT R3.L BY R0.L;
R4.L = ASHIFT R4.L BY R0.L;
R5.L = ASHIFT R5.L BY R0.L;
R6.L = ASHIFT R6.L BY R0.L;
R7.L = ASHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x0000c001;
CHECKREG r2, 0x0000c002;
CHECKREG r3, 0x0000c003;
CHECKREG r4, 0x0000c004;
CHECKREG r5, 0x0000c005;
CHECKREG r6, 0x0000c006;
CHECKREG r7, 0x0000c007;
imm32 r0, 0x00008001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000c005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000e007;
R0.L = ASHIFT R0.L BY R1.L;
//rl1 = ashift (rl1 by rl1);
R2.L = ASHIFT R2.L BY R1.L;
R3.L = ASHIFT R3.L BY R1.L;
R4.L = ASHIFT R4.L BY R1.L;
R5.L = ASHIFT R5.L BY R1.L;
R6.L = ASHIFT R6.L BY R1.L;
R7.L = ASHIFT R7.L BY R1.L;
//CHECKREG r0, 0x00008002; /* why fail with real data R0 = 0x00000002 */
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x0000a004;
CHECKREG r3, 0x0000c006;
CHECKREG r4, 0x0000e008;
CHECKREG r5, 0x0000800a;
CHECKREG r6, 0x0000a00c;
CHECKREG r7, 0x0000c00e;
imm32 r0, 0x0000c001;
imm32 r1, 0x0000d001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.L = ASHIFT R0.L BY R2.L;
R1.L = ASHIFT R1.L BY R2.L;
//rl2 = ashift (rl2 by rl2);
R3.L = ASHIFT R3.L BY R2.L;
R4.L = ASHIFT R4.L BY R2.L;
R5.L = ASHIFT R5.L BY R2.L;
R6.L = ASHIFT R6.L BY R2.L;
R7.L = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x00008000;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x00008000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00008000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00008000;
imm32 r0, 0x00009001;
imm32 r1, 0x0000a001;
imm32 r2, 0x0000b002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000c004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000f007;
R0.L = ASHIFT R0.L BY R3.L;
R1.L = ASHIFT R1.L BY R3.L;
R2.L = ASHIFT R2.L BY R3.L;
//rl3 = ashift (rl3 by rl3);
R4.L = ASHIFT R4.L BY R3.L;
R5.L = ASHIFT R5.L BY R3.L;
R6.L = ASHIFT R6.L BY R3.L;
R7.L = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.L = ASHIFT R0.H BY R0.L;
R1.L = ASHIFT R1.H BY R0.L;
R2.L = ASHIFT R2.H BY R0.L;
R3.L = ASHIFT R3.H BY R0.L;
R4.L = ASHIFT R4.H BY R0.L;
R5.L = ASHIFT R5.H BY R0.L;
R6.L = ASHIFT R6.H BY R0.L;
R7.L = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x90010000;
imm32 r1, 0x00010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R0.L = ASHIFT R0.H BY R1.L;
//rl1 = ashift (rh1 by rl1);
R2.L = ASHIFT R2.H BY R1.L;
R3.L = ASHIFT R3.H BY R1.L;
R4.L = ASHIFT R4.H BY R1.L;
R5.L = ASHIFT R5.H BY R1.L;
R6.L = ASHIFT R6.H BY R1.L;
R7.L = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x90012002;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x90022004;
CHECKREG r3, 0x90032006;
CHECKREG r4, 0x90042008;
CHECKREG r5, 0x9005200a;
CHECKREG r6, 0x9006200c;
CHECKREG r7, 0x9007200e;
imm32 r0, 0xa0010000;
imm32 r1, 0xa0010000;
imm32 r2, 0xa002000f;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0xa0018000;
CHECKREG r1, 0xa0018000;
CHECKREG r2, 0xa002000f;
CHECKREG r3, 0xa0038000;
CHECKREG r4, 0xa0040000;
CHECKREG r5, 0xa0058000;
CHECKREG r6, 0xa0060000;
CHECKREG r7, 0xa0078000;
imm32 r0, 0xc0010001;
imm32 r1, 0xc0010001;
imm32 r2, 0xc0020002;
imm32 r3, 0xc0030010;
imm32 r4, 0xc0040004;
imm32 r5, 0xc0050005;
imm32 r6, 0xc0060006;
imm32 r7, 0xc0070007;
R0.L = ASHIFT R0.H BY R3.L;
R1.L = ASHIFT R1.H BY R3.L;
R2.L = ASHIFT R2.H BY R3.L;
//rl3 = ashift (rh3 by rl3);
R4.L = ASHIFT R4.H BY R3.L;
R5.L = ASHIFT R5.H BY R3.L;
R6.L = ASHIFT R6.H BY R3.L;
R7.L = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0xc0010000;
CHECKREG r1, 0xc0010000;
CHECKREG r2, 0xc0020000;
CHECKREG r3, 0xc0030010;
CHECKREG r4, 0xc0040000;
CHECKREG r5, 0xc0050000;
CHECKREG r6, 0xc0060000;
CHECKREG r7, 0xc0070000;
// d_hi = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
R0.H = ASHIFT R0.L BY R0.L;
R1.H = ASHIFT R1.L BY R0.L;
R2.H = ASHIFT R2.L BY R0.L;
R3.H = ASHIFT R3.L BY R0.L;
R4.H = ASHIFT R4.L BY R0.L;
R5.H = ASHIFT R5.L BY R0.L;
R6.H = ASHIFT R6.L BY R0.L;
R7.H = ASHIFT R7.L BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010001;
CHECKREG r2, 0x00020002;
CHECKREG r3, 0x00030003;
CHECKREG r4, 0x00040004;
CHECKREG r5, 0x00050005;
CHECKREG r6, 0x00060006;
CHECKREG r7, 0x00070007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R0.H = ASHIFT R0.L BY R1.L;
R1.H = ASHIFT R1.L BY R1.L;
R2.H = ASHIFT R2.L BY R1.L;
R3.H = ASHIFT R3.L BY R1.L;
R4.H = ASHIFT R4.L BY R1.L;
R5.H = ASHIFT R5.L BY R1.L;
R6.H = ASHIFT R6.L BY R1.L;
R7.H = ASHIFT R7.L BY R1.L;
CHECKREG r0, 0xa002d001;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0xa004d002;
CHECKREG r3, 0xa006d003;
CHECKREG r4, 0xa008d004;
CHECKREG r5, 0xa00ad005;
CHECKREG r6, 0xa00cd006;
CHECKREG r7, 0xa00ed007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = ASHIFT R0.L BY R2.L;
R1.H = ASHIFT R1.L BY R2.L;
//rh2 = ashift (rl2 by rl2);
R3.H = ASHIFT R3.L BY R2.L;
R4.H = ASHIFT R4.L BY R2.L;
R5.H = ASHIFT R5.L BY R2.L;
R6.H = ASHIFT R6.L BY R2.L;
R7.H = ASHIFT R7.L BY R2.L;
CHECKREG r0, 0x8000e001;
CHECKREG r1, 0x8000e001;
CHECKREG r2, 0x0000000f;
CHECKREG r3, 0x8000e003;
CHECKREG r4, 0x0000e004;
CHECKREG r5, 0x8000e005;
CHECKREG r6, 0x0000e006;
CHECKREG r7, 0x8000e007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R0.H = ASHIFT R0.L BY R3.L;
R1.H = ASHIFT R1.L BY R3.L;
R2.H = ASHIFT R2.L BY R3.L;
R3.H = ASHIFT R3.L BY R3.L;
R4.H = ASHIFT R4.L BY R3.L;
R5.H = ASHIFT R5.L BY R3.L;
R6.H = ASHIFT R6.L BY R3.L;
R7.H = ASHIFT R7.L BY R3.L;
CHECKREG r0, 0x0000f001;
CHECKREG r1, 0x0000f001;
CHECKREG r2, 0x0000f002;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x0000f004;
CHECKREG r5, 0x0000f005;
CHECKREG r6, 0x0000f006;
CHECKREG r7, 0x0000f007;
// d_lo = ashft (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x00000000;
imm32 r1, 0x00010000;
imm32 r2, 0x00020000;
imm32 r3, 0x00030000;
imm32 r4, 0x00040000;
imm32 r5, 0x00050000;
imm32 r6, 0x00060000;
imm32 r7, 0x00070000;
R0.H = ASHIFT R0.H BY R0.L;
R1.H = ASHIFT R1.H BY R0.L;
R2.H = ASHIFT R2.H BY R0.L;
R3.H = ASHIFT R3.H BY R0.L;
R4.H = ASHIFT R4.H BY R0.L;
R5.H = ASHIFT R5.H BY R0.L;
R6.H = ASHIFT R6.H BY R0.L;
R7.H = ASHIFT R7.H BY R0.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010000;
CHECKREG r2, 0x00020000;
CHECKREG r3, 0x00030000;
CHECKREG r4, 0x00040000;
CHECKREG r5, 0x00050000;
CHECKREG r6, 0x00060000;
CHECKREG r7, 0x00070000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R0.H = ASHIFT R0.H BY R1.L;
R1.H = ASHIFT R1.H BY R1.L;
R2.H = ASHIFT R2.H BY R1.L;
R3.H = ASHIFT R3.H BY R1.L;
R4.H = ASHIFT R4.H BY R1.L;
R5.H = ASHIFT R5.H BY R1.L;
R6.H = ASHIFT R6.H BY R1.L;
R7.H = ASHIFT R7.H BY R1.L;
CHECKREG r0, 0x40020000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x40040000;
CHECKREG r3, 0x40060000;
CHECKREG r4, 0x40080000;
CHECKREG r5, 0x400a0000;
CHECKREG r6, 0x400c0000;
CHECKREG r7, 0x400e0000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R0.L = ASHIFT R0.H BY R2.L;
R1.L = ASHIFT R1.H BY R2.L;
//rl2 = ashift (rh2 by rl2);
R3.L = ASHIFT R3.H BY R2.L;
R4.L = ASHIFT R4.H BY R2.L;
R5.L = ASHIFT R5.H BY R2.L;
R6.L = ASHIFT R6.H BY R2.L;
R7.L = ASHIFT R7.H BY R2.L;
CHECKREG r0, 0xb0018000;
CHECKREG r1, 0xb0018000;
CHECKREG r2, 0xb002000f;
CHECKREG r3, 0xb0038000;
CHECKREG r4, 0xb0040000;
CHECKREG r5, 0xb0058000;
CHECKREG r6, 0xb0060000;
CHECKREG r7, 0xb0078000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R0.H = ASHIFT R0.H BY R3.L;
R1.H = ASHIFT R1.H BY R3.L;
R2.H = ASHIFT R2.H BY R3.L;
R3.H = ASHIFT R3.H BY R3.L;
R4.H = ASHIFT R4.H BY R3.L;
R5.H = ASHIFT R5.H BY R3.L;
R6.H = ASHIFT R6.H BY R3.L;
R7.H = ASHIFT R7.H BY R3.L;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000010;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,521 | sim/testsuite/bfin/c_ldstii_st_dr_h.s | //Original:/testcases/core/c_ldstii_st_dr_h/c_ldstii_st_dr_h.dsp
// Spec Reference: c_ldstii store dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_1;
loadsym fp, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym sp, DATA_ADDR_3;
.endif
W [ P1 + 2 ] = R0;
W [ P1 + 4 ] = R1;
W [ P1 + 6 ] = R2;
W [ P1 + 8 ] = R3;
W [ P2 + 10 ] = R4;
W [ P2 + 12 ] = R5;
W [ P2 + 14 ] = R6;
W [ P2 + 16 ] = R7;
R6 = W [ P1 + 2 ] (Z);
R5 = W [ P1 + 4 ] (Z);
R4 = W [ P1 + 6 ] (Z);
R3 = W [ P1 + 8 ] (Z);
R2 = W [ P2 + 10 ] (Z);
R7 = W [ P2 + 12 ] (Z);
R0 = W [ P2 + 14 ] (Z);
R1 = W [ P2 + 16 ] (Z);
CHECKREG r0, 0x0000B0A6;
CHECKREG r1, 0x0000C0A7;
CHECKREG r2, 0x000090A4;
CHECKREG r3, 0x000080A3;
CHECKREG r4, 0x000070A2;
CHECKREG r5, 0x000060A1;
CHECKREG r6, 0x000050A0;
CHECKREG r7, 0x0000A0A5;
.ifndef BFIN_HOST
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
W [ P3 + 18 ] = R0;
W [ P3 + 20 ] = R1;
W [ P3 + 22 ] = R2;
W [ P3 + 24 ] = R3;
W [ P4 + 26 ] = R4;
W [ P4 + 28 ] = R5;
W [ P4 + 30 ] = R6;
W [ P4 + 32 ] = R7;
R3 = W [ P3 + 18 ] (Z);
R4 = W [ P3 + 20 ] (Z);
R0 = W [ P3 + 22 ] (Z);
R1 = W [ P3 + 24 ] (Z);
R2 = W [ P4 + 26 ] (Z);
R5 = W [ P4 + 28 ] (Z);
R6 = W [ P4 + 30 ] (Z);
R7 = W [ P4 + 32 ] (Z);
CHECKREG r0, 0x000070B2;
CHECKREG r1, 0x000080B3;
CHECKREG r2, 0x000090B4;
CHECKREG r3, 0x000050B0;
CHECKREG r4, 0x000060B1;
CHECKREG r5, 0x0000A0B5;
CHECKREG r6, 0x0000B0B6;
CHECKREG r7, 0x0000C0B7;
.endif
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
W [ P5 + 34 ] = R0;
W [ P5 + 36 ] = R1;
W [ P5 + 38 ] = R2;
W [ P5 + 40 ] = R3;
.ifndef BFIN_HOST
W [ SP + 42 ] = R4;
W [ SP + 44 ] = R5;
W [ SP + 46 ] = R6;
W [ SP + 48 ] = R7;
.endif
R6 = W [ P5 + 34 ] (Z);
R5 = W [ P5 + 36 ] (Z);
R4 = W [ P5 + 38 ] (Z);
R3 = W [ P5 + 40 ] (Z);
.ifndef BFIN_HOST
R2 = W [ SP + 42 ] (Z);
R0 = W [ SP + 44 ] (Z);
R7 = W [ SP + 46 ] (Z);
R1 = W [ SP + 48 ] (Z);
CHECKREG r0, 0x0000A0C5;
CHECKREG r1, 0x0000C0C7;
CHECKREG r2, 0x000090C4;
.endif
CHECKREG r3, 0x000080C3;
CHECKREG r4, 0x000070C2;
CHECKREG r5, 0x000060C1;
CHECKREG r6, 0x000050C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
W [ FP + 50 ] = R0;
W [ FP + 52 ] = R1;
W [ FP + 54 ] = R2;
W [ FP + 56 ] = R3;
W [ FP + 58 ] = R4;
W [ FP + 60 ] = R5;
W [ FP + 62 ] = R6;
W [ FP + 64 ] = R7;
R3 = W [ FP + 50 ] (Z);
R4 = W [ FP + 52 ] (Z);
R0 = W [ FP + 54 ] (Z);
R1 = W [ FP + 56 ] (Z);
R2 = W [ FP + 58 ] (Z);
R5 = W [ FP + 60 ] (Z);
R6 = W [ FP + 62 ] (Z);
R7 = W [ FP + 64 ] (Z);
CHECKREG r0, 0x000070D2;
CHECKREG r1, 0x000080D3;
CHECKREG r2, 0x000090D4;
CHECKREG r3, 0x000050D0;
CHECKREG r4, 0x000060D1;
CHECKREG r5, 0x0000A0D5;
CHECKREG r6, 0x0000B0D6;
CHECKREG r7, 0x0000C0D7;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,204 | sim/testsuite/bfin/issue205.s | # mach: bfin
.include "testutils.inc"
start
R0 = 0; R1 = 0; R2 = 0; R3 = 0; R4 = 0; R5 = 0; R6 = 0; R7 = 0;
P0 = 0; P1 = 0; P2 = 0; P4 = 0; P5 = 0;
I0 = 0 (X); I1 = 0 (X); I2 = 0 (X); I3 = 0 (X);
M0 = 0 (X); M1 = 0 (X); M2 = 0 (X); M3 = 0 (X);
L0 = 0 (X); L1 = 0 (X); L2 = 0 (X); L3 = 0 (X);
B0 = 0 (X); B1 = 0 (X); B2 = 0 (X); B3 = 0 (X);
R0 = -1;
R1 = 0x1234 (X);
R2 = -2000 (X);
R3 = 2000 (X);
R4 = 0;
R5 = 1;
R6 = 5555 (X);
R7 = -1000 (X);
loadsym P1, tmp0;
loadsym P2, tmp1;
loadsym P4, tmp2;
I1 = P1;
I2 = P2;
I3 = P4;
R0.L = 0x0017;
R0.H = 0xffff;
R0.L = EXPADJ( R2 , R1.L ) || [ P2 ] = R0 || NOP;
R6 = [ P2 ];
DBGA ( R6.L , 0x17 );
DBGA ( R6.H , 0xffff );
DBGA ( R0.L , 0x1234 );
DBGA ( R0.H , 0xffff );
pass
.data
tmp0:
.dd 0x12345678 // 0x1000
.dd 0x10101010 // 0x1004
.dd 0x55555555 // 0x1008
.dd 0xaaaaaaaa // 0x100c
.dd 0xffffffff // 0x1010
.data
tmp1:
.dd 0xabcdefef // 0x2000
.dd 0x12121212 // 0x2004
.dd 0x45454545 // 0x2008
.dd 0xabababab // 0x200c
.dd 0x0f0f0f0f // 0x2010
.data
tmp2:
.dd 0xff00ff00 // 0x3000
.dd 0x02020202 // 0x3004
.dd 0x4f4f4f45 // 0x3008
.dd 0xafafafaf // 0x300c
.dd 0x1f1f1f1f // 0x3010
|
tactcomplabs/xbgas-binutils-gdb | 2,796 | sim/testsuite/bfin/push-pop-multiple.s | # Blackfin testcase for push/pop multiples instructions
# mach: bfin
.include "testutils.inc"
# Tests follow the pattern:
# - do the push multiple
# - write a garbage value to all registers pushed
# - do the pop multiple
# - check all registers popped against known values
start
# Repeat the same operation multiple times, so this:
# do_x moo, R, 1
# becomes this:
# moo R1, 0x11111111
# moo R0, 0x00000000
.macro _do_x func:req, reg:req, max:req, x:req
.ifle (\max - \x)
\func \reg\()\x, 0x\x\x\x\x\x\x\x\x
.endif
.endm
.macro do_x func:req, reg:req, max:req
.ifc \reg, R
_do_x \func, \reg, \max, 7
_do_x \func, \reg, \max, 6
.endif
_do_x \func, \reg, \max, 5
_do_x \func, \reg, \max, 4
_do_x \func, \reg, \max, 3
_do_x \func, \reg, \max, 2
_do_x \func, \reg, \max, 1
_do_x \func, \reg, \max, 0
.endm
# Keep the garbage value in I0
.macro loadi reg:req, val:req
\reg = I0;
.endm
imm32 I0, 0xAABCDEFF
#
# Test push/pop multiples with (R7:x) syntax
#
_push_r_tests:
# initialize all Rx regs with a known value
do_x imm32, R, 0
.macro checkr tochk:req, val:req
P0 = \tochk;
imm32 P1, \val
CC = P0 == P1;
IF !CC JUMP 8f;
.endm
.macro pushr maxr:req
_push_r\maxr:
[--SP] = (R7:\maxr);
do_x loadi, R, \maxr
(R7:\maxr) = [SP++];
do_x checkr, R, \maxr
# need to do a long jump to avoid PCREL issues
jump 9f;
8: jump.l 1f;
9:
.endm
pushr 7
pushr 6
pushr 5
pushr 4
pushr 3
pushr 2
pushr 1
pushr 0
#
# Test push/pop multiples with (P5:x) syntax
#
_push_p_tests:
# initialize all Px regs with a known value
do_x imm32, P, 0
.macro checkp tochk:req, val:req
R0 = \tochk;
imm32 R1, \val
CC = R0 == R1;
IF !CC JUMP 8f;
.endm
.macro pushp maxp:req
_push_p\maxp:
[--SP] = (P5:\maxp);
do_x loadi, P, \maxp
(P5:\maxp) = [SP++];
do_x checkp, P, \maxp
# need to do a long jump to avoid PCREL issues
jump 9f;
8: jump.l 1f;
9:
.endm
# checkp func clobbers R0/R1
L0 = R0;
L1 = R1;
pushp 5
pushp 4
pushp 3
pushp 2
pushp 1
pushp 0
R0 = L0;
R1 = L1;
#
# Test push/pop multiples with (R7:x, P5:x) syntax
#
_push_rp_tests:
.macro _pushrp maxr:req, maxp:req
_push_r\maxr\()_p\maxp:
[--SP] = (R7:\maxr, P5:\maxp);
do_x loadi, R, \maxr
do_x loadi, P, \maxp
(R7:\maxr, P5:\maxp) = [SP++];
# checkr func clobbers P0/P1
L0 = P0;
L1 = P1;
do_x checkr, R, \maxr
P1 = L1;
P0 = L0;
# checkp func clobbers R0/R1
L0 = R0;
L1 = R1;
do_x checkp, P, \maxp
R0 = L0;
R1 = L1;
# need to do a long jump to avoid PCREL issues
jump 9f;
8: jump.l 1f;
9:
.endm
.macro pushrp maxr:req
_pushrp \maxr, 5
_pushrp \maxr, 4
_pushrp \maxr, 3
_pushrp \maxr, 2
_pushrp \maxr, 1
_pushrp \maxr, 0
.endm
pushrp 7
pushrp 6
pushrp 5
pushrp 4
pushrp 3
pushrp 2
pushrp 1
pushrp 0
pass
1:
fail
|
tactcomplabs/xbgas-binutils-gdb | 2,085 | sim/testsuite/bfin/s5.s | // Test r4 = ROT (r2 by r3);
# mach: bfin
.include "testutils.inc"
start
R0.L = 0x0001;
R0.H = 0x8000;
// rot
// left by 1
// 8000 0001 -> 0000 0002 cc=1
R7 = 0;
CC = R7;
R1 = 1;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right by -1
// 8000 0001 -> 4000 0000 cc=1
R7 = 0;
CC = R7;
R1.L = 0xffff; // check alternate mechanism for immediates
R1.H = 0xffff;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot
// right by largest positive magnitude of 31
// 8000 0001 -> a000 0000 cc=0
R7 = 0;
CC = R7;
R1 = 31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0xa000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by largest positive magnitude of 31 with cc=1
// 8000 0001 cc=1 -> a000 0000 cc=0
R7 = 1;
CC = R7;
R1 = 31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0xe000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by largest negative magnitude of -31
// 8000 0001 -> 0000 0005 cc=0
R7 = 0;
CC = R7;
R1 = -31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0005 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// right by largest negative magnitude of -31 with cc=1
// 8000 0001 cc=1 -> 0000 0007 cc=0
R7 = 1;
CC = R7;
R1 = -31;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0007 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot
// left by 7
// 8000 0001 cc=1 -> 0000 00e0 cc=0
R7 = 1;
CC = R7;
R1 = 7;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x00e0 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0000 );
// rot by zero
// 8000 0001 -> 8000 0000
R7 = 1;
CC = R7;
R1 = 0;
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0x8000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
// rot by 0b1100 0001 is the same as by 1 (mask 6 bits)
// 8000 0001 -> 0000 0002 cc=1
R7 = 0;
CC = R7;
R1 = 0xc1 (X);
R6 = ROT R0 BY R1.L;
DBGA ( R6.L , 0x0002 );
DBGA ( R6.H , 0x0000 );
R7 = CC;
DBGA ( R7.L , 0x0001 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,355 | sim/testsuite/bfin/random_0021.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x5c604280 | _VS | _AV1S | _AV0S);
imm32 R3, 0xfe0103fe;
imm32 R5, 0x1e53cdd8;
R3.H = R5.L * R3.H (M, IU);
checkreg R3, 0x800003fe;
checkreg ASTAT, (0x5c604280 | _VS | _V | _AV1S | _AV0S | _V_COPY);
dmm32 ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN);
imm32 R4, 0xfffeffff;
imm32 R5, 0x174e174e;
R5.H = R4.L * R5.H (M, IU);
checkreg R5, 0xe8b2174e;
checkreg ASTAT, (0x74a04c00 | _VS | _AV1S | _CC | _AN);
dmm32 ASTAT, (0x34308890 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AN);
imm32 R3, 0x7fffffff;
imm32 R4, 0x077b8000;
imm32 R7, 0x03bd03bd;
R3.H = R4.L * R7.H (M, IU);
checkreg R3, 0x8000ffff;
checkreg ASTAT, (0x34308890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x58700a90 | _VS | _AV1S | _AC1 | _AQ | _CC | _AN);
imm32 R1, 0x58978212;
imm32 R3, 0x62b5775a;
imm32 R6, 0x4c9c9ee3;
R6.H = R1.L * R3.L (M, IU);
checkreg R6, 0x80009ee3;
checkreg ASTAT, (0x58700a90 | _VS | _V | _AV1S | _AC1 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x40204e00 | _VS | _AV1S | _AV0S | _CC | _AN);
imm32 R3, 0x297fee00;
imm32 R5, 0x79aa9d21;
imm32 R6, 0xfffe7484;
R6.H = R5.L * R3.L (M, IU);
checkreg R6, 0x80007484;
checkreg ASTAT, (0x40204e00 | _VS | _V | _AV1S | _AV0S | _CC | _V_COPY | _AN);
pass
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