repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 6,264 | sim/testsuite/bfin/c_dspldst_st_drhi_ipp.s | //Original:testcases/core/c_dspldst_st_drhi_ipp/c_dspldst_st_drhi_ipp.dsp
// Spec Reference: c_dspldst st_drhi_ipp
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
// Half reg 16 bit mem store
imm32 r0, 0x0a123456;
imm32 r1, 0x11b12345;
imm32 r2, 0x222c1234;
imm32 r3, 0x3344d012;
imm32 r4, 0x5566e012;
imm32 r5, 0x789abf01;
imm32 r6, 0xabcd0123;
imm32 r7, 0x01234567;
// initial values
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
W [ I0 ++ ] = R0.H;
W [ I1 ++ ] = R1.H;
W [ I2 ++ ] = R2.H;
W [ I3 ++ ] = R3.H;
W [ I0 ++ ] = R1.H;
W [ I1 ++ ] = R2.H;
W [ I2 ++ ] = R3.H;
W [ I3 ++ ] = R4.H;
W [ I0 ++ ] = R3.H;
W [ I1 ++ ] = R4.H;
W [ I2 ++ ] = R5.H;
W [ I3 ++ ] = R6.H;
W [ I0 ++ ] = R4.H;
W [ I1 ++ ] = R5.H;
W [ I2 ++ ] = R6.H;
W [ I3 ++ ] = R7.H;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x11B10A12;
CHECKREG r1, 0x222C11B1;
CHECKREG r2, 0x3344222C;
CHECKREG r3, 0x55663344;
CHECKREG r4, 0x55663344;
CHECKREG r5, 0x789A5566;
CHECKREG r6, 0xABCD789A;
CHECKREG r7, 0x0123ABCD;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x08090A0B;
CHECKREG r1, 0x28292A2B;
CHECKREG r2, 0x48494A4B;
CHECKREG r3, 0x68696A6B;
CHECKREG r4, 0x0C0D0E0F;
CHECKREG r5, 0x2C2D2E2F;
CHECKREG r6, 0x4C4D4E4F;
CHECKREG r7, 0x6C6D6E6F;
// initial values
imm32 r0, 0x01b2c3d4;
imm32 r1, 0x10145618;
imm32 r2, 0xa2016729;
imm32 r3, 0xbb30183a;
imm32 r4, 0xdec4014b;
imm32 r5, 0x5f7d501c;
imm32 r6, 0x3089eb01;
imm32 r7, 0x719abf70;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
W [ I0 -- ] = R0.H;
W [ I1 -- ] = R1.H;
W [ I2 -- ] = R2.H;
W [ I3 -- ] = R3.H;
W [ I0 -- ] = R1.H;
W [ I1 -- ] = R2.H;
W [ I2 -- ] = R3.H;
W [ I3 -- ] = R4.H;
W [ I0 -- ] = R3.H;
W [ I1 -- ] = R4.H;
W [ I2 -- ] = R5.H;
W [ I3 -- ] = R6.H;
W [ I0 -- ] = R4.H;
W [ I1 -- ] = R5.H;
W [ I2 -- ] = R6.H;
W [ I3 -- ] = R7.H;
loadsym i0, DATA_ADDR_3, 0x20;
loadsym i1, DATA_ADDR_4, 0x20;
loadsym i2, DATA_ADDR_5, 0x20;
loadsym i3, DATA_ADDR_6, 0x20;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0x000001B2;
CHECKREG r1, 0x00001014;
CHECKREG r2, 0x0000A201;
CHECKREG r3, 0x0000BB30;
CHECKREG r4, 0x1014BB30;
CHECKREG r5, 0xA201DEC4;
CHECKREG r6, 0xBB305F7D;
CHECKREG r7, 0xDEC43089;
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0xDEC41A1B;
CHECKREG r1, 0x5F7D3A3B;
CHECKREG r2, 0x30895A5B;
CHECKREG r3, 0x719A7A7B;
CHECKREG r4, 0x14151617;
CHECKREG r5, 0x34353637;
CHECKREG r6, 0x54555657;
CHECKREG r7, 0x74757677;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,869 | sim/testsuite/bfin/m5.s | // Test result extraction of mac instructions.
// Test basic edge values
// SIGNED FRACTIONAL mode into SINGLE destination register
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// simple extraction with no saturation
// 0x7fff * 0x7fff = 0x007ffe0002 -> 0x7ffe
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L);
DBGA ( R5.L , 0x7ffe );
DBGA ( R5.H , 0x7ffe );
_DBG ASTAT;
R7 = ASTAT;
DBGA (R7.H, 0x0);
DBGA (R7.L, 0x0);
// positive saturation at 32 bits
// 0x0 * 0x0 + 0x7ff0000000 -> 0x7fff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.x = R3.L;
A0.w = R2;
R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L);
_DBG A1;
_DBG A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
_DBG ASTAT;
R7 = ASTAT;
_DBG R7;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x8);
// positive saturation at 32 bits
// 0x7fff * 0x7fff + 0x7ff0000000 -> 0x7fff
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R3.L;
A0.w = R2;
A0.x = R3.L;
R5.H = (A1 += R0.L * R1.L), R5.L = (A0 += R0.L * R1.L);
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
_DBG ASTAT;
R7 = ASTAT;
DBGA (R7.H, 0x30f);
DBGA (R7.L, 0x8);
// negative saturation at 32 bits
// 0x0 * 0x0 + 0x80f0000000 -> 0x8000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R4.L;
A0.w = R2;
A0.x = R4.L;
R5.H = (A1 += R0.L * R2.L), R5.L = (A0 += R0.L * R2.L);
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x8000 );
_DBG A1;
_DBG A0;
_DBG ASTAT;
R7=ASTAT;
_DBG R7;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x0008);
// negative saturation at 32 bits
// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A1.w = R2;
A1.x = R4.L;
A0.w = R2;
A0.x = R4.L;
R5.H = (A1 += R0.H * R1.L), R5.L = (A0 += R0.H * R1.L);
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x8000 );
R7=ASTAT;
_DBG ASTAT;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x0008);
// negative saturation at 32 bits on MAC only
// 0x7fff * 0x8000 + 0x80f0000000 -> 0x8000
R7 = 0;
ASTAT = R7;
A1 = A0 = 0;
A0.w = R2;
A0.x = R4.L;
_DBG ASTAT;
R5.H = A1, R5.L = (A0 += R0.H * R1.L);
_DBG A0;
DBGA ( R5.L , 0x8000 );
DBGA ( R5.H , 0x0000 );
R7=ASTAT;
_DBG ASTAT;
DBGA (R7.H, 0x300);
DBGA (R7.L, 0x0009);
// 0x0100 * 0x0100 = 0x00020000 -> 0x0002
R7 = 0;
ASTAT = R7;
R0.L = 0x0100;
R1.L = 0x0100;
A1 = A0 = 0;
R5.H = (A1 = R0.L * R1.L), R5.L = (A0 = R0.L * R1.L) (T);
DBGA ( R5.L , 0x0002 );
DBGA ( R5.H , 0x0002 );
R7 = ASTAT;
DBGA (R7.H, 0x000);
DBGA (R7.L, 0x000);
pass
.data
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 5,457 | sim/testsuite/bfin/c_ldst_ld_p_p_pp.s | //Original:/testcases/core/c_ldst_ld_p_p_pp/c_ldst_ld_p_p_pp.dsp
// Spec Reference: c_ldst ld p [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
P2 = [ P1 ++ ];
P1 += 4;
P4 = [ P1 ++ ];
P5 = [ P1 ++ ];
P1 += 4;
FP = [ P1 ++ ];
CHECKREG p2, 0x78910213;
CHECKREG p4, 0x08090A0B;
CHECKREG p5, 0x0C0D0E0F;
CHECKREG fp, 0x14151617;
loadsym p2, DATA_ADDR_2;
P1 = [ P2 ++ ];
P2 += 4;
P4 = [ P2 ++ ];
P5 = [ P2 ++ ];
P2 += 4;
FP = [ P2 ++ ];
CHECKREG p1, 0x20212223;
CHECKREG p4, 0x28292A2B;
CHECKREG p5, 0x2C2D2E2F;
CHECKREG fp, 0x34353637;
loadsym p4, DATA_ADDR_4;
P1 = [ P4 ++ ];
P2 = [ P4 ++ ];
P4 += 4;
P5 = [ P4 ++ ];
P4 += 4;
FP = [ P4 ++ ];
CHECKREG p1, 0x60616263;
CHECKREG p2, 0x64656667;
CHECKREG p5, 0x6C6D6E6F;
CHECKREG fp, 0x74757677;
loadsym p5, DATA_ADDR_5;
P1 = [ P5 ++ ];
P2 = [ P5 ++ ];
P5 += 4;
P4 = [ P5 ++ ];
P5 += 4;
FP = [ P5 ++ ];
CHECKREG p1, 0x8A8B8C8D;
CHECKREG p2, 0x84858687;
CHECKREG p4, 0x8C8D8E8F;
CHECKREG fp, 0x94959697;
loadsym fp, DATA_ADDR_7;
P1 = [ FP ++ ];
P2 = [ FP ++ ];
FP += 4;
P4 = [ FP ++ ];
P5 = [ FP ++ ];
CHECKREG p1, 0x80818283;
CHECKREG p2, 0x84858687;
CHECKREG p4, 0x8C8D8E8F;
CHECKREG p5, 0x90919293;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x78910213
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x8A8B8C8D
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,158 | sim/testsuite/bfin/c_dsp32shiftim_lf.s | //Original:/testcases/core/c_dsp32shiftim_lf/c_dsp32shiftim_lf.dsp
# mach: bfin
.include "testutils.inc"
start
// Spec Reference: dsp32shiftimm lshift: lshift
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R0 = R0 << 0;
R1 = R1 << 3;
R2 = R2 << 7;
R3 = R3 << 8;
R4 = R4 << 15;
R5 = R5 << 24;
R6 = R6 << 31;
R7 = R7 << 20;
CHECKREG r0, 0xA1230001;
CHECKREG r1, 0xD9A2B3C0;
CHECKREG r2, 0xE2B3C480;
CHECKREG r3, 0xD6789A00;
CHECKREG r4, 0xC4D58000;
CHECKREG r5, 0xBC000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0xCDE00000;
imm32 r0, 0xa1230001;
imm32 r1, 0x1b345678;
imm32 r2, 0x23c56789;
imm32 r3, 0x34d6789a;
imm32 r4, 0x85a789ab;
imm32 r5, 0x967c9abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb8912cde;
R6 = R0 >> 1;
R7 = R1 >> 3;
R0 = R2 >> 7;
R1 = R3 >> 8;
R2 = R4 >> 15;
R3 = R5 >> 24;
R4 = R6 >> 31;
R5 = R7 >> 20;
CHECKREG r0, 0x00478ACF;
CHECKREG r1, 0x0034D678;
CHECKREG r2, 0x00010B4F;
CHECKREG r3, 0x00000096;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000036;
CHECKREG r6, 0x50918000;
CHECKREG r7, 0x03668ACF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 23,178 | sim/testsuite/bfin/random_0025.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x10cfffff;
imm32 R6, 0x06a1ea20;
R0.H = R6.H >>> 0x1b;
checkreg R0, 0xd420ffff;
checkreg ASTAT, (0x74f00490 | _VS | _V | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY);
imm32 R3, 0x80007fff;
R3.L = R3.L >>> 0x1f;
checkreg R3, 0x8000fffe;
checkreg ASTAT, (0x78704000 | _VS | _V | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x5ce08c00 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN);
imm32 R3, 0xef9f04f4;
imm32 R6, 0x11037fff;
R3.L = R6.H >>> 0x1d;
checkreg R3, 0xef9f8818;
checkreg ASTAT, (0x5ce08c00 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R2, 0x00af03a2;
imm32 R7, 0x0b470440;
R7.L = R2.L >>> 0x1a;
checkreg R7, 0x0b47e880;
checkreg ASTAT, (0x14904890 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3040ca00 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN);
imm32 R1, 0x3bd8d8ef;
imm32 R7, 0x7b15ffff;
R1.H = R7.H >>> 0x1f;
checkreg R1, 0xf62ad8ef;
checkreg ASTAT, (0x3040ca00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AZ);
imm32 R0, 0xfffffffc;
imm32 R1, 0x7ffffffe;
R0.H = R1.H >>> 0x1f;
checkreg R0, 0xfffefffc;
checkreg ASTAT, (0x68404600 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AN);
dmm32 ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R1, 0x30b38b8d;
imm32 R3, 0x1c830bb1;
R1.H = R3.L >>> 0x1c;
checkreg R1, 0xbb108b8d;
checkreg ASTAT, (0x54108890 | _VS | _V | _AV1S | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x3cc00e80 | _VS | _AV1S | _AC0);
imm32 R6, 0x1b42549c;
R6.L = R6.L >>> 0x1f;
checkreg R6, 0x1b42a938;
checkreg ASTAT, (0x3cc00e80 | _VS | _V | _AV1S | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY);
imm32 R0, 0x0b040a99;
imm32 R6, 0x2716ffff;
R6.H = R0.L >>> 0x1c;
checkreg R6, 0xa990ffff;
checkreg ASTAT, (0x1ca04490 | _VS | _V | _AV0S | _AC1 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x14800880 | _VS | _AC0 | _AN | _AZ);
imm32 R2, 0x7fff7fff;
imm32 R7, 0x0a014f10;
R7 = R2 >>> 0x1f (V);
checkreg R7, 0xfffefffe;
checkreg ASTAT, (0x14800880 | _VS | _V | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AZ);
imm32 R7, 0x7fffffff;
R7 = R7 >>> 0x10 (V);
checkreg R7, 0x0000ffff;
checkreg ASTAT, (0x04a08000 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY);
imm32 R2, 0x00030003;
imm32 R6, 0x2c962c96;
R6 = R2 >>> 0x10 (V);
checkreg R6, 0x00000000;
checkreg ASTAT, (0x4c204090 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY);
imm32 R0, 0x3a567ee8;
imm32 R4, 0x7e163337;
R0 = R4 >>> 0x10 (V);
checkreg R0, 0x00000000;
checkreg ASTAT, (0x14400e00 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AQ | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x30200a10 | _VS | _AN);
imm32 R2, 0xffff0f44;
R2 = R2 >>> 0x1c (V);
checkreg R2, 0xfff0f440;
checkreg ASTAT, (0x30200a10 | _VS | _V | _V_COPY | _AN);
dmm32 ASTAT, (0x10c0c080 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
imm32 R1, 0x1d4571f3;
imm32 R2, 0x1d45ffff;
R2 = R1 >>> 0x10 (V);
checkreg R2, 0x00000000;
checkreg ASTAT, (0x10c0c080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC);
imm32 R2, 0x8000ffff;
imm32 R3, 0x0f757fff;
R3 = R2 >>> 0x10 (V);
checkreg R3, 0xffffffff;
checkreg ASTAT, (0x4cd08c90 | _VS | _AV1S | _AV0S | _CC | _AN);
dmm32 ASTAT, (0x68004a00 | _VS | _AV0S | _AQ | _AN);
imm32 R6, 0x366a7fff;
imm32 R7, 0xe4ca366a;
R7 = R6 >>> 0x1f (V);
checkreg R7, 0x6cd4fffe;
checkreg ASTAT, (0x68004a00 | _VS | _V | _AV0S | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R6, 0x3468e405;
imm32 R7, 0x0fd2ee59;
R7 = R6 >>> 0x10 (V);
checkreg R7, 0x0000ffff;
checkreg ASTAT, (0x14c0ca80 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
imm32 R3, 0x2b8ffe22;
imm32 R4, 0x2f17d9d2;
R4 = R3 >>> 0x1e (V);
checkreg R4, 0xae3cf888;
checkreg ASTAT, (0x1460cc90 | _VS | _V | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC);
imm32 R1, 0x3afe2bd0;
imm32 R4, 0x57e37450;
R4 = R1 >>> 0x10 (V);
checkreg R4, 0x00000000;
checkreg ASTAT, (0x30d04290 | _VS | _AC1 | _AQ | _CC | _AZ);
dmm32 ASTAT, (0x04600600 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
imm32 R0, 0xedbbfffe;
imm32 R4, 0x169330ac;
R0 = R4 >>> 0x1e (V);
checkreg R0, 0x5a4cc2b0;
checkreg ASTAT, (0x04600600 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY | _AN);
dmm32 ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AN);
imm32 R1, 0x788b2d30;
imm32 R6, 0x78f61ce9;
R6 = R1 >>> 0x10 (V);
checkreg R6, 0x00000000;
checkreg ASTAT, (0x64c0c290 | _VS | _AV1 | _AV0S | _AV0 | _AC0 | _CC | _AZ);
dmm32 ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY);
imm32 R0, 0x0b7d1dc6;
imm32 R7, 0x3d27f3e5;
R7 = R0 >>> 0x10 (V);
checkreg R7, 0x00000000;
checkreg ASTAT, (0x74d04680 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC);
imm32 R5, 0xffc70074;
imm32 R7, 0xf49916ce;
R5 = R7 >>> 0x10 (V);
checkreg R5, 0xffff0000;
checkreg ASTAT, (0x74900000 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC | _AN | _AZ);
dmm32 ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN);
imm32 R0, 0x1e0287a7;
imm32 R4, 0x30aa2286;
R0 = R4 >>> 0x10 (V);
checkreg R0, 0x00000000;
checkreg ASTAT, (0x6ca0c400 | _VS | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x10204a00 | _VS | _CC | _AN);
imm32 R5, 0xa6b04dd0;
imm32 R6, 0xfedb4cd8;
R5 = R6 >>> 0x1f (V);
checkreg R5, 0xfdb699b0;
checkreg ASTAT, (0x10204a00 | _VS | _V | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x30e04290 | _VS | _V | _AV1S | _AV0S | _AC1 | _V_COPY);
imm32 R2, 0x0c55766f;
imm32 R3, 0x28c00004;
R2 = R3 >>> 0x10 (V);
checkreg R2, 0x00000000;
checkreg ASTAT, (0x30e04290 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x34b0c410 | _VS | _AQ | _CC);
imm32 R7, 0x0f7b2928;
R7 = R7 >>> 0x1e (V);
checkreg R7, 0x3deca4a0;
checkreg ASTAT, (0x34b0c410 | _VS | _V | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY);
imm32 R4, 0x0baad54f;
imm32 R7, 0x05bf0c50;
R4 = R7 >>> 0x10 (V);
checkreg R4, 0x00000000;
checkreg ASTAT, (0x18504800 | _VS | _AV1S | _AC1 | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x2cd04290 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _V_COPY | _AC0_COPY);
imm32 R0, 0x1199ca48;
imm32 R7, 0x4ee24366;
R7 = R0 >>> 0x10 (V);
checkreg R7, 0x0000ffff;
checkreg ASTAT, (0x2cd04290 | _VS | _AV1S | _AV0S | _AV0 | _AC0 | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC);
imm32 R3, 0x528af4b6;
imm32 R6, 0x18d26b4a;
R3 = R6 >>> 0x10 (V);
checkreg R3, 0x00000000;
checkreg ASTAT, (0x24304c90 | _VS | _AV0S | _AC1 | _AC0 | _CC | _AZ);
dmm32 ASTAT, (0x70504200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
imm32 R1, 0x255f0000;
imm32 R4, 0x96e0e654;
imm32 R6, 0x255fd442;
R4 = ASHIFT R1 BY R6.L;
checkreg R4, 0x957c0000;
checkreg ASTAT, (0x70504200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x13f865f4;
A1 = ASHIFT A1 BY R3.L;
checkreg ASTAT, (0x10004210 | _VS | _AV1S | _AC1 | _AQ | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R3, 0x13f865f4;
dmm32 ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x00000000;
A0 = ASHIFT A0 BY R3.L;
checkreg ASTAT, (0x1c90c400 | _VS | _AV0S | _AC1 | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R3, 0x00000000;
dmm32 ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN);
dmm32 A1.w, 0x00000001;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x4a4a7fff;
A1 = LSHIFT A1 BY R3.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x4820c280 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ);
dmm32 ASTAT, (0x1c20cc10 | _VS | _AC1 | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
A1 = LSHIFT A1 BY R0.L;
checkreg ASTAT, (0x1c20cc10 | _VS | _AC1 | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R0, 0x00000000;
dmm32 ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _AC0_COPY | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R4, 0x10cb0000;
A0 = ASHIFT A0 BY R4.L;
checkreg ASTAT, (0x1c608e90 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R4, 0x10cb0000;
dmm32 ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x00000000;
A1 = LSHIFT A1 BY R4.L;
checkreg ASTAT, (0x6870ce00 | _VS | _AC1 | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R4, 0x00000000;
dmm32 ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x00000000;
A0 = LSHIFT A0 BY R2.L;
checkreg ASTAT, (0x04200290 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R2, 0x00000000;
dmm32 ASTAT, (0x0c404e80 | _VS | _V | _V_COPY);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R7, 0xc400e200;
A0 = ASHIFT A0 BY R7.L;
checkreg ASTAT, (0x0c404e80 | _VS | _V | _V_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R7, 0xc400e200;
dmm32 ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0xe603ffff;
A0 = LSHIFT A0 BY R0.L;
checkreg ASTAT, (0x04e00800 | _VS | _AV1S | _AV0S | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R0, 0xe603ffff;
dmm32 ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R6, 0x00000000;
A1 = LSHIFT A1 BY R6.L;
checkreg ASTAT, (0x40904090 | _VS | _AV0S | _AC1 | _CC | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R6, 0x00000000;
dmm32 ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0x023d0ac0;
dmm32 A0.x, 0x00000000;
imm32 R2, 0xfffe05e0;
A0 = ASHIFT A0 BY R2.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x24f04c10 | _VS | _V | _AC1 | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x00000000;
A1 = ASHIFT A1 BY R4.L;
checkreg ASTAT, (0x2860c410 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R4, 0x00000000;
dmm32 ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN);
imm32 R2, 0x4e59ffff;
imm32 R6, 0x2c450001;
R6 = ASHIFT R2 BY R6.L (V);
checkreg R6, 0x9cb2fffe;
checkreg ASTAT, (0x40000a00 | _VS | _V | _AV0S | _AV0 | _AQ | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x3c700410 | _VS | _V | _AV0S | _AV0 | _V_COPY | _AC0_COPY | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R6, 0x0d1144c0;
A0 = LSHIFT A0 BY R6.L;
checkreg ASTAT, (0x3c700410 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R6, 0x0d1144c0;
dmm32 ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN | _AZ);
dmm32 A1.w, 0x80000000;
dmm32 A1.x, 0x00000000;
imm32 R7, 0x472d2397;
A1 = LSHIFT A1 BY R7.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x5c10ca80 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x10004c00 | _VS | _AQ | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R2, 0x80000000;
A1 = LSHIFT A1 BY R2.L;
checkreg ASTAT, (0x10004c00 | _VS | _AQ | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R2, 0x80000000;
dmm32 ASTAT, (0x30308480 | _VS | _AV0S | _AQ);
dmm32 A0.w, 0x19b289d0;
dmm32 A0.x, 0x00000000;
imm32 R6, 0xffff0ce2;
A0 = LSHIFT A0 BY R6.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x30308480 | _VS | _AV0S | _AQ | _AZ);
dmm32 ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY);
dmm32 A0.w, 0x3f050000;
dmm32 A0.x, 0x00000000;
imm32 R6, 0xc0fb081a;
A0 = LSHIFT A0 BY R6.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x28708280 | _VS | _AV1S | _AC1 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _CC | _AN);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R3, 0xeca83337;
A0 = LSHIFT A0 BY R3.L;
checkreg ASTAT, (0x18708280 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R3, 0xeca83337;
dmm32 ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R5, 0x00000000;
A1 = ASHIFT A1 BY R5.L;
checkreg ASTAT, (0x78b0c010 | _VS | _AV1S | _AC1 | _AC0 | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R5, 0x00000000;
dmm32 ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x05600000;
A1 = LSHIFT A1 BY R3.L;
checkreg ASTAT, (0x50d00680 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R3, 0x05600000;
dmm32 ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 A0.w, 0x046b40e7;
dmm32 A0.x, 0x00000000;
imm32 R3, 0x20a220a2;
A0 = ASHIFT A0 BY R3.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x04108880 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AZ);
dmm32 ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AV0 | _AC0_COPY | _AN);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R1, 0x623d1bad;
A0 = ASHIFT A0 BY R1.L;
checkreg ASTAT, (0x6850cc80 | _VS | _AV1S | _AV0S | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R1, 0x623d1bad;
dmm32 ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x211b1629;
A1 = LSHIFT A1 BY R4.L;
checkreg ASTAT, (0x44d04a80 | _VS | _AC1 | _AC0 | _AQ | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg R4, 0x211b1629;
dmm32 ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R1, 0xffffa0e5;
A0 = ASHIFT A0 BY R1.L;
checkreg ASTAT, (0x1c304480 | _VS | _AV1S | _AV0S | _AC1 | _AQ | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R1, 0xffffa0e5;
dmm32 ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ);
dmm32 A1.w, 0x01cdbb21;
dmm32 A1.x, 0x00000000;
imm32 R7, 0x696f3de3;
A1 = ASHIFT A1 BY R7.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x54c00c90 | _VS | _AV0S | _AC1 | _CC | _AZ);
dmm32 ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AN);
dmm32 A1.w, 0x00007400;
dmm32 A1.x, 0x00000000;
imm32 R4, 0x6fc3cc21;
A1 = LSHIFT A1 BY R4.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x7c30c690 | _VS | _AV1S | _AV0S | _AC1 | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x1c404200 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AN);
imm32 R2, 0x1e000001;
imm32 R4, 0x037b7038;
imm32 R5, 0x57beffff;
R4.L = ASHIFT R5.H BY R2.L;
checkreg R4, 0x037baf7c;
checkreg ASTAT, (0x1c404200 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AN);
dmm32 ASTAT, (0x24e08c80 | _VS | _AV1S | _CC);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R6, 0x11f23024;
A0 = LSHIFT A0 BY R6.L;
checkreg ASTAT, (0x24e08c80 | _VS | _AV1S | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R6, 0x11f23024;
dmm32 ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x00000000;
A0 = ASHIFT A0 BY R2.L;
checkreg ASTAT, (0x3ce04080 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg R2, 0x00000000;
dmm32 ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x00000000;
A0 = LSHIFT A0 BY R0.L;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x28800280 | _VS | _AV1S | _AV0S | _CC | _AZ);
dmm32 ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV1 | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A1.w, 0x80000000;
dmm32 A1.x, 0xffffffea;
imm32 R2, 0x0121e8d9;
A1 = ASHIFT A1 BY R2.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x68708810 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x1b9411f4;
A1 = LSHIFT A1 BY R0.L;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x24c00890 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x4480ce00 | _VS | _AC1);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
A1 = A1 << 0x5;
checkreg ASTAT, (0x4480ce00 | _VS | _AC1 | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
dmm32 ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x3b;
checkreg ASTAT, (0x6cf0cc10 | _VS | _AC0 | _AQ | _CC | _AC0_COPY | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
dmm32 ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AN);
dmm32 A1.w, 0x028ab5f4;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x1f;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x50d00a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0x0001f0f0;
dmm32 A1.x, 0x00000000;
A1 = A1 >> 0x14;
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x14c00490 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AN);
dmm32 A0.w, 0x000fc1a6;
dmm32 A0.x, 0x00000000;
A0 = A0 >> 0x1f;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x14808a80 | _VS | _AV1S | _AV0S | _AC1 | _AZ);
dmm32 ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ);
dmm32 A1.w, 0x00000000;
dmm32 A1.x, 0x00000000;
A1 = A1 >>> 0x1e;
checkreg ASTAT, (0x3c80ca90 | _VS | _AV0S | _AC0 | _AQ | _CC | _AZ);
checkreg A1.w, 0x00000000;
checkreg A1.x, 0x00000000;
dmm32 ASTAT, (0x4c200c90 | _VS | _AV1S | _AV0S | _AV0 | _AC1 | _AQ);
imm32 R2, 0xf1815f1a;
imm32 R7, 0x0a917fff;
R7.L = R2.L >>> 0x13;
checkreg R7, 0x0a914000;
checkreg ASTAT, (0x4c200c90 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC1 | _AQ | _V_COPY);
dmm32 ASTAT, (0x0cf0cc80 | _VS | _AV0S | _AC0_COPY | _AZ);
imm32 R0, 0x000081ad;
imm32 R2, 0x00000000;
R2.H = R0.L >>> 0x19;
checkreg R2, 0xd6800000;
checkreg ASTAT, (0x0cf0cc80 | _VS | _V | _AV0S | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x04304c10 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
imm32 R1, 0x33dd7fff;
imm32 R7, 0xae86a2f4;
R1 = R7 >>> 0x13 (V);
checkreg R1, 0xc0008000;
checkreg ASTAT, (0x04304c10 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x7850c800 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
imm32 R4, 0x0000fffe;
imm32 R7, 0x5906fc4f;
R4.L = R7.H >>> 0x15;
checkreg R4, 0x00003000;
checkreg ASTAT, (0x7850c800 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _V_COPY);
dmm32 ASTAT, (0x64804c90 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
imm32 R1, 0x000009e3;
imm32 R4, 0x44418b70;
R1.H = R4.L >>> 0x17;
checkreg R1, 0xe00009e3;
checkreg ASTAT, (0x64804c90 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x2c508410 | _VS | _AV1 | _AV0S | _AC0 | _AQ | _AC0_COPY | _AZ);
imm32 R0, 0x43d731e2;
imm32 R4, 0x60995f48;
R0.L = R4.H >>> 0x17;
checkreg R0, 0x43d73200;
checkreg ASTAT, (0x2c508410 | _VS | _V | _AV1 | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN);
dmm32 A0.w, 0x00000000;
dmm32 A0.x, 0x00000000;
A0 = A0 >>> 0xc;
checkreg ASTAT, (0x0c900010 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AZ);
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
dmm32 ASTAT, (0x40c00e80 | _VS | _AV1 | _AV0S | _CC | _AN | _AZ);
imm32 R1, 0x0bf14680;
imm32 R3, 0x1875266d;
R3.H = R1.L >>> 0x1d;
checkreg R3, 0x3400266d;
checkreg ASTAT, (0x40c00e80 | _VS | _V | _AV1 | _AV0S | _CC | _V_COPY);
dmm32 ASTAT, (0x78100a00 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AC0_COPY | _AN);
imm32 R4, 0x67c0a470;
imm32 R7, 0x000026c0;
R4 = R7 >>> 0x1d (V);
checkreg R4, 0x00003600;
checkreg ASTAT, (0x78100a00 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AC0_COPY | _AZ);
dmm32 ASTAT, (0x6cd04610 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY);
imm32 R0, 0x0f9535a6;
imm32 R5, 0x31018b62;
R0 = R5 >>> 0x12 (V);
checkreg R0, 0x40008000;
checkreg ASTAT, (0x6cd04610 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
imm32 R2, 0x023cffff;
imm32 R6, 0x0d6d8000;
R6.L = R2.H >>> 0x18;
checkreg R6, 0x0d6d3c00;
checkreg ASTAT, (0x58a08800 | _VS | _V | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
imm32 R2, 0xa9d7c2fd;
imm32 R4, 0xfffed266;
R2.L = R4.L >>> 0x12;
checkreg R2, 0xa9d78000;
checkreg ASTAT, (0x5cc00600 | _VS | _V | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x5c900400 | _VS | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
imm32 R1, 0xf37e61a8;
imm32 R4, 0x5522a41c;
R4 = R1 >>> 0x12 (V);
checkreg R4, 0x80000000;
checkreg ASTAT, (0x5c900400 | _VS | _V | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN | _AZ);
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,725 | sim/testsuite/bfin/brcc.s | # mach: bfin
.include "testutils.inc"
start
/* Stall tests */
r0 = 0;
r1 = 1;
loadsym p0, foo;
p1 = p0;
pass_1:
cc = r0;
nop;
nop;
if cc jump _fail_1;
[p0++] = p0;
[p0++] = p0;
r7 = p0;
r5 = CC;
P1 += 8;
r6 = p1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if !cc jump over;
_fail_1:
[p0++] = p0;
[p0++] = p0;
back:
if !cc jump skip(bp);
_fail_2:
[p0++] = p0;
[p0++] = p0;
over:
if cc jump _fail_3(bp);
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5=cc;
P1 += 8;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
CC = R5;
if !cc jump back(bp);
_fail_3:
[p0++] = p0;
[p0++] = p0;
skip:
[p0++] = p0;
[p0++] = p0;
[p0++] = p0;
r7=p0;
P1 += 0xc;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
next:
[p0++] = p0;
r7=p0;
P1 += 4;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
pass_2:
cc = r1;
nop;
nop;
if !cc jump _fail_4;
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5 = cc;
P1 += 8;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if cc jump over_2;
_fail_4:
[p0++] = p0;
[p0++] = p0;
P1 += 8;
back_2:
if cc jump skip_2 (bp);
_fail_5:
[p0++] = p0;
[p0++] = p0;
P1 += 8;
over_2:
if !cc jump _fail_6 (bp);
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5 = cc;
P1 += 8;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if cc jump back_2 (bp);
_fail_6:
[p0++] = p0;
[p0++] = p0;
skip_2:
[p0++] = p0;
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5 = cc;
P1 += 0xc;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = r5;
if cc jump next_2 (bp);
next_2:
[p0++] = p0;
[p0++] = p0;
P1 += 8;
r7=p0;
r6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = r0;
_halt:
pass;
_fail_7:
[p0++] = p0;
_failure:
fail;
.data
foo:
.space (0x100)
|
tactcomplabs/xbgas-binutils-gdb | 5,030 | sim/testsuite/bfin/s13.s | // Test rl3 = ashift (rh0 by r5;
// Test rl3 = lshift (rh0 by r5);
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
R0 = 0;
ASTAT = R0;
R0.L = 0x1;
R0.H = 0x1;
R5.L = 4;
R7.L = ASHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0010 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R0.L = 0x8000;
R0.H = 0x1;
R5.L = -4;
R5.H = 0;
R7.L = ASHIFT R0.L BY R5.L;
DBGA ( R7.L , 0xf800 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R0.L = 0x0;
R0.H = 0x1;
R5.L = 0;
R5.H = 0;
R7.L = ASHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x8000;
R5.L = -4;
R5.H = 0;
R7.H = ASHIFT R0.H BY R5.L;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0xf800 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x8000;
R5.L = -4;
R5.H = 0;
R7.L = ASHIFT R0.H BY R5.L;
DBGA ( R7.L , 0xf800 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0xffff;
R5.L = 31; // should accept mag of +31
R5.H = 0;
R7.L = ASHIFT R0.H BY R5.L;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x0100;
R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked
R5.H = 0;
R7.L = ASHIFT R0.H BY R5.L;
DBGA ( R7.L , 0x0080 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// logic shifts
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x8000;
R5.L = -4;
R5.H = 0;
R7.L = LSHIFT R0.H BY R5.L;
DBGA ( R7.L , 0x0800 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 0;
R0.L = 0x1;
R0.H = 0x1;
R5.L = 4;
R5.H = 0;
R7.H = LSHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 1;
R0.L = 0x0;
R0.H = 0x0;
R5.L = 0;
R5.H = 0;
R7.L = LSHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 1;
R0.L = 0x1;
R0.H = 0x0;
R5.L = 15;
R5.H = 0;
R7.L = LSHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 1;
R0.L = 0x0100;
R0.H = 0x0;
R5.L = 63; // mag of 63 will appear as -1 since 6 bits are masked
R5.H = 0;
R7.L = LSHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0080 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0 = 0;
ASTAT = R0;
R7 = 1;
R0.L = 0x0100;
R0.H = 0x0;
R5.L = 31; // should accept mag of +31
R5.H = 0;
R7.L = LSHIFT R0.L BY R5.L;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,844 | sim/testsuite/bfin/c_dsp32mult_dr_m_i.s | //Original:/testcases/core/c_dsp32mult_dr_m_i/c_dsp32mult_dr_m_i.dsp
// Spec Reference: dsp32mult single dr munop i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xfb235625;
imm32 r1, 0x9fba5127;
imm32 r2, 0xa3ff6725;
imm32 r3, 0x0006f027;
imm32 r4, 0xb0abcd29;
imm32 r5, 0x1facef2b;
imm32 r6, 0xc0fc002d;
imm32 r7, 0xd24f702f;
R4.L = R0.H * R0.L (IS);
R5.H = R0.L * R1.L (IS);
R6.L = R1.L * R0.H (IS);
R7.L = R1.L * R1.L (IS);
R0.H = R0.L * R0.L (IS);
R1.L = R0.L * R1.L (IS);
R2.L = R1.H * R0.L (IS);
R3.H = R1.L * R1.L (IS);
CHECKREG r0, 0x7FFF5625;
CHECKREG r1, 0x9FBA7FFF;
CHECKREG r2, 0xA3FF8000;
CHECKREG r3, 0x7FFFF027;
CHECKREG r4, 0xB0AB8000;
CHECKREG r5, 0x7FFFEF2B;
CHECKREG r6, 0xC0FC8000;
CHECKREG r7, 0xD24F7FFF;
imm32 r0, 0xeb23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b7e5;
imm32 r3, 0x9e060037;
imm32 r4, 0x80ebcd39;
imm32 r5, 0xb0aeef3b;
imm32 r6, 0xa00ce03d;
imm32 r7, 0x12467e03;
R5.H = R2.L * R2.L (IS);
R6.L = R2.L * R3.H (IS);
R7.L = R3.H * R2.L (IS);
R0.H = R3.L * R3.L (IS);
R1.H = R2.L * R2.H (IS);
R2.L = R2.H * R3.H (IS);
R3.H = R3.L * R2.L (IS);
R4.L = R3.L * R3.L (IS);
CHECKREG r0, 0x0BD1A635;
CHECKREG r1, 0x80005137;
CHECKREG r2, 0x13248000;
CHECKREG r3, 0x80000037;
CHECKREG r4, 0x80EB0BD1;
CHECKREG r5, 0x7FFFEF3B;
CHECKREG r6, 0xA00C7FFF;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0xdd235655;
imm32 r1, 0xc4dd5157;
imm32 r2, 0x6324d755;
imm32 r3, 0x00060055;
imm32 r4, 0x90dbc509;
imm32 r5, 0x10adef5b;
imm32 r6, 0xb00cd05d;
imm32 r7, 0x12467d5f;
R0.L = R4.L * R4.H (IS);
R1.H = R4.H * R5.L (IS);
R2.L = R5.H * R4.L (IS);
R3.L = R5.L * R5.L (IS);
R4.H = R4.L * R4.H (IS);
R5.L = R4.L * R5.H (IS);
R6.H = R5.H * R4.H (IS);
R7.L = R5.H * R5.H (IS);
CHECKREG r0, 0xDD237FFF;
CHECKREG r1, 0x7FFF5157;
CHECKREG r2, 0x63248000;
CHECKREG r3, 0x00067FFF;
CHECKREG r4, 0x7FFFC509;
CHECKREG r5, 0x10AD8000;
CHECKREG r6, 0x7FFFD05D;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0xcb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x1c248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90cb9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cc06d;
imm32 r7, 0x12467c6f;
// test the unsigned U=1
R0.L = R6.L * R6.L (IS);
R1.H = R6.H * R7.L (IS);
R2.L = R7.L * R6.L (IS);
R3.L = R7.L * R7.L (IS);
R6.H = R6.H * R6.H (IS);
R7.L = R6.L * R7.L (IS);
R4.H = R7.H * R6.H (IS);
R5.L = R7.L * R7.L (IS);
CHECKREG r0, 0xCB237FFF;
CHECKREG r1, 0x80005166;
CHECKREG r2, 0x1C248000;
CHECKREG r3, 0xF0067FFF;
CHECKREG r4, 0x7FFF9D69;
CHECKREG r5, 0x10AC7FFF;
CHECKREG r6, 0x7FFFC06D;
CHECKREG r7, 0x12468000;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0xe0060007;
imm32 r4, 0x9eabcd09;
imm32 r5, 0x10ecdfdb;
imm32 r6, 0x000e000d;
imm32 r7, 0x1246e00f;
R0.H = R0.L * R7.H (IS);
R1.L = R1.H * R6.H (IS);
R2.L = R2.L * R5.L (IS);
R3.H = R3.H * R4.H (IS);
R4.L = R4.L * R3.H (IS);
R5.L = R5.H * R2.H (IS);
R6.H = R6.H * R1.L (IS);
R7.L = R7.L * R0.H (IS);
CHECKREG r0, 0x8000A675;
CHECKREG r1, 0xCFBA8000;
CHECKREG r2, 0x13248000;
CHECKREG r3, 0x7FFF0007;
CHECKREG r4, 0x9EAB8000;
CHECKREG r5, 0x10EC7FFF;
CHECKREG r6, 0x8000000D;
CHECKREG r7, 0x12467FFF;
imm32 r0, 0x9b235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x93246905;
imm32 r3, 0x09060007;
imm32 r4, 0x909bcd09;
imm32 r5, 0x10a9e9db;
imm32 r6, 0x000c9d0d;
imm32 r7, 0x1246790f;
R0.L = R7.L * R0.H (IS);
R1.L = R6.L * R1.L (IS);
R2.H = R5.L * R2.L (IS);
R3.L = R4.H * R3.L (IS);
R4.L = R3.H * R4.H (IS);
R5.H = R2.H * R5.L (IS);
R6.L = R1.H * R6.L (IS);
R7.L = R0.L * R7.L (IS);
CHECKREG r0, 0x9B238000;
CHECKREG r1, 0xCFBA8000;
CHECKREG r2, 0x80006905;
CHECKREG r3, 0x09068000;
CHECKREG r4, 0x909B8000;
CHECKREG r5, 0x7FFFE9DB;
CHECKREG r6, 0x000C7FFF;
CHECKREG r7, 0x12468000;
imm32 r0, 0xa9235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x08060007;
imm32 r4, 0x908bcd09;
imm32 r5, 0x10a88fdb;
imm32 r6, 0x000c080d;
imm32 r7, 0x1246708f;
R2.L = R0.L * R6.L (IS);
R3.L = R1.H * R7.L (IS);
R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS);
R1.H = R3.L * R1.L (IS);
R4.L = R4.H * R2.L (IS);
R5.L = R5.L * R3.L (IS);
R6.L = R6.L * R4.L (IS);
R7.H = R7.H * R5.L (IS);
CHECKREG r0, 0x7FFF8000;
CHECKREG r1, 0x80005127;
CHECKREG r2, 0x13247FFF;
CHECKREG r3, 0x08068000;
CHECKREG r4, 0x908B8000;
CHECKREG r5, 0x10A87FFF;
CHECKREG r6, 0x000C8000;
CHECKREG r7, 0x7FFF708F;
imm32 r0, 0x7b235675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x17246705;
imm32 r3, 0x00760007;
imm32 r4, 0x907bcd09;
imm32 r5, 0x10a7efdb;
imm32 r6, 0x000c700d;
imm32 r7, 0x1246770f;
R4.L = R5.L * R2.L (IS);
R6.L = R6.L * R3.H (IS);
R0.H = R7.L * R4.H (IS);
R1.L = R0.H * R5.L (IS);
R2.L = R1.L * R6.L (IS);
R5.L = R2.L * R7.H (IS);
R3.H = R3.H * R0.L (IS);
R7.L = R4.H * R1.H (IS);
CHECKREG r0, 0x80005675;
CHECKREG r1, 0xCFBA7FFF;
CHECKREG r2, 0x17247FFF;
CHECKREG r3, 0x7FFF0007;
CHECKREG r4, 0x907B8000;
CHECKREG r5, 0x10A77FFF;
CHECKREG r6, 0x000C7FFF;
CHECKREG r7, 0x12467FFF;
pass
|
tactcomplabs/xbgas-binutils-gdb | 8,283 | sim/testsuite/bfin/c_interr_timer.S | //Original:/proj/frio/dv/testcases/core/c_interr_timer/c_interr_timer.dsp
// Spec Reference: interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
BOOT :
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
// CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
//.code 0x200
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR(0) (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
// WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TCOUNT, 0x00000000, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1))
CSYNC; // TIMER interrupt
RD_MMR(TCOUNT, p0, r3);
CSYNC;
CHECKREG(r3, 0x00000000);
CHECKREG(r7, 0x00000001);
WR_MMR(TCNTL, 0x00000001, p0, r0); // enable Timer (TMPWR(0), TMREN(1)=0)
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR(0), TMREN(1))
CSYNC;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Power, EN -> interr
CSYNC;
CHECKREG(r7, 0x00000003); // 3 interr already happened
R7 = 0; // reset r7
WR_MMR(TPERIOD, 0x00000040, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auto load
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000040);
// CHECKREG(r7, 0x00000002);
CC = R7 == 0;
IF !CC JUMP LABEL1;
WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE
LABEL1:
NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
RD_MMR(TCNTL , p0, r3);
CHECKREG(r3, 0x0000000F);
WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer
CSYNC;
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000040);
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
RD_MMR(TCOUNT, p0, r4);
CHECKREG(r4, 0x00000000);
RD_MMR(TCNTL, p0, r5);
CHECKREG(r5, 0x0000000B);
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
WR_MMR(TPERIOD, 0x00000060, p0, r0);
CSYNC;
NOP;
RD_MMR(TPERIOD, p0, r6);
CHECKREG(r6, 0x00000060);
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_DATA_ADDR_1,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
tactcomplabs/xbgas-binutils-gdb | 9,178 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_lp_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00100a00;
imm32 r1, 0x00100a01;
imm32 r2, 0x00100a02;
imm32 r3, 0x00100a03;
imm32 r4, 0x00100a04;
imm32 r5, 0x00100a05;
imm32 r6, 0x00100a06;
imm32 r7, 0x00100a07;
R7.L = R0.L << 0 (S);
R0.L = R1.L << 1 (S);
R1.L = R2.L << 2 (S);
R2.L = R3.L << 3 (S);
R3.L = R4.L << 4 (S);
R4.L = R5.L << 5 (S);
R5.L = R6.L << 6 (S);
R6.L = R7.L << 7 (S);
CHECKREG r1, 0x00102808;
CHECKREG r0, 0x00101402;
CHECKREG r2, 0x00105018;
CHECKREG r3, 0x00107FFF;
CHECKREG r4, 0x00107FFF;
CHECKREG r5, 0x00107FFF;
CHECKREG r6, 0x00107FFF;
CHECKREG r7, 0x00100A00;
imm32 r0, 0x00200018;
imm32 r1, 0x00200019;
imm32 r2, 0x0020001a;
imm32 r3, 0x0020001b;
imm32 r4, 0x0020001c;
imm32 r5, 0x0020001d;
imm32 r6, 0x0020001e;
imm32 r7, 0x0020001f;
R2.L = R0.L << 8 (S);
R3.L = R1.L << 9 (S);
R4.L = R2.L << 10 (S);
R5.L = R3.L << 11 (S);
R6.L = R4.L << 12 (S);
R7.L = R5.L << 13 (S);
R0.L = R6.L << 14 (S);
R1.L = R7.L << 15 (S);
CHECKREG r0, 0x00207FFF;
CHECKREG r1, 0x00207FFF;
CHECKREG r2, 0x00201800;
CHECKREG r3, 0x00203200;
CHECKREG r4, 0x00207FFF;
CHECKREG r5, 0x00207FFF;
CHECKREG r6, 0x00207FFF;
CHECKREG r7, 0x00207FFF;
imm32 r0, 0x05002001;
imm32 r1, 0x05002001;
imm32 r2, 0x0500000f;
imm32 r3, 0x05002003;
imm32 r4, 0x05002004;
imm32 r5, 0x05002005;
imm32 r6, 0x05002006;
imm32 r7, 0x05002007;
R3.L = R0.L << 0 (S);
R4.L = R1.L << 1 (S);
R5.L = R2.L << 2 (S);
R6.L = R3.L << 3 (S);
R7.L = R4.L << 4 (S);
R0.L = R5.L << 5 (S);
R1.L = R6.L << 6 (S);
R2.L = R7.L << 7 (S);
CHECKREG r0, 0x05000780;
CHECKREG r1, 0x05007FFF;
CHECKREG r2, 0x05007FFF;
CHECKREG r3, 0x05002001;
CHECKREG r4, 0x05004002;
CHECKREG r5, 0x0500003C;
CHECKREG r6, 0x05007FFF;
CHECKREG r7, 0x05007FFF;
imm32 r0, 0x03000031;
imm32 r1, 0x03000031;
imm32 r2, 0x03000032;
imm32 r3, 0x03000030;
imm32 r4, 0x03000034;
imm32 r5, 0x03000035;
imm32 r6, 0x03000036;
imm32 r7, 0x03000037;
R4.L = R0.L << 8 (S);
R5.L = R1.L << 9 (S);
R6.L = R2.L << 10 (S);
R7.L = R3.L << 11 (S);
R0.L = R4.L << 12 (S);
R1.L = R5.L << 13 (S);
R2.L = R6.L << 14 (S);
R3.L = R7.L << 15 (S);
CHECKREG r0, 0x03007FFF;
CHECKREG r1, 0x03007FFF;
CHECKREG r2, 0x03007FFF;
CHECKREG r3, 0x03007FFF;
CHECKREG r4, 0x03003100;
CHECKREG r5, 0x03006200;
CHECKREG r6, 0x03007FFF;
CHECKREG r7, 0x03007FFF;
// RHx by RLx
imm32 r0, 0x03000000;
imm32 r1, 0x03000000;
imm32 r2, 0x03000000;
imm32 r3, 0x03000000;
imm32 r4, 0x03003100;
imm32 r5, 0x03006200;
imm32 r6, 0x0300C800;
imm32 r7, 0x03008000;
R5.L = R0.H << 0 (S);
R6.L = R1.H << 1 (S);
R7.L = R2.H << 2 (S);
R0.L = R3.H << 3 (S);
R1.L = R4.H << 4 (S);
R2.L = R5.H << 5 (S);
R3.L = R6.H << 6 (S);
R4.L = R7.H << 7 (S);
CHECKREG r0, 0x03001800;
CHECKREG r1, 0x03003000;
CHECKREG r2, 0x03006000;
CHECKREG r3, 0x03007FFF;
CHECKREG r4, 0x03007FFF;
CHECKREG r5, 0x03000300;
CHECKREG r6, 0x03000600;
CHECKREG r7, 0x03000C00;
imm32 r0, 0x05018000;
imm32 r1, 0x05018001;
imm32 r2, 0x05028000;
imm32 r3, 0x05038000;
imm32 r4, 0x05048000;
imm32 r5, 0x05058000;
imm32 r6, 0x05068000;
imm32 r7, 0x05078000;
R6.L = R0.H << 8 (S);
R7.L = R1.H << 9 (S);
R0.L = R2.H << 10 (S);
R1.L = R3.H << 11 (S);
R2.L = R4.H << 12 (S);
R3.L = R5.H << 13 (S);
R4.L = R6.H << 14 (S);
R5.L = R7.H << 15 (S);
CHECKREG r0, 0x05017FFF;
CHECKREG r1, 0x05017FFF;
CHECKREG r2, 0x05027FFF;
CHECKREG r3, 0x05037FFF;
CHECKREG r4, 0x05047FFF;
CHECKREG r5, 0x05057FFF;
CHECKREG r6, 0x05067FFF;
CHECKREG r7, 0x05077FFF;
imm32 r0, 0x60019000;
imm32 r1, 0x60019000;
imm32 r2, 0x6002900f;
imm32 r3, 0x60039000;
imm32 r4, 0x60049000;
imm32 r5, 0x60059000;
imm32 r6, 0x60069000;
imm32 r7, 0x60079000;
R7.L = R0.H << 0 (S);
R0.L = R1.H << 1 (S);
R1.L = R2.H << 2 (S);
R2.L = R3.H << 3 (S);
R3.L = R4.H << 4 (S);
R4.L = R5.H << 5 (S);
R5.L = R6.H << 6 (S);
R6.L = R7.H << 7 (S);
CHECKREG r0, 0x60017FFF;
CHECKREG r1, 0x60017FFF;
CHECKREG r2, 0x60027FFF;
CHECKREG r3, 0x60037FFF;
CHECKREG r4, 0x60047FFF;
CHECKREG r5, 0x60057FFF;
CHECKREG r6, 0x60067FFF;
CHECKREG r7, 0x60076001;
imm32 r0, 0x70010001;
imm32 r1, 0x70010001;
imm32 r2, 0x70020002;
imm32 r3, 0x77030010;
imm32 r4, 0x70040004;
imm32 r5, 0x70050005;
imm32 r6, 0x70060006;
imm32 r7, 0x70070007;
R0.L = R0.H << 8 (S);
R1.L = R1.H << 9 (S);
R2.L = R2.H << 10 (S);
R3.L = R3.H << 11 (S);
R4.L = R4.H << 12 (S);
R5.L = R5.H << 13 (S);
R6.L = R6.H << 14 (S);
R7.L = R7.H << 15 (S);
CHECKREG r0, 0x70017FFF;
CHECKREG r1, 0x70017FFF;
CHECKREG r2, 0x70027FFF;
CHECKREG r3, 0x77037FFF;
CHECKREG r4, 0x70047FFF;
CHECKREG r5, 0x70057FFF;
CHECKREG r6, 0x70067FFF;
CHECKREG r7, 0x70077FFF;
// d_hi = lshft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0xa8000000;
imm32 r1, 0xa8000001;
imm32 r2, 0xa8000002;
imm32 r3, 0xa8000003;
imm32 r4, 0xa8000004;
imm32 r5, 0xa8000005;
imm32 r6, 0xa8000006;
imm32 r7, 0xa8000007;
R0.H = R0.L << 0 (S);
R1.H = R1.L << 1 (S);
R2.H = R2.L << 2 (S);
R3.H = R3.L << 3 (S);
R4.H = R4.L << 4 (S);
R5.H = R5.L << 5 (S);
R6.H = R6.L << 6 (S);
R7.H = R7.L << 7 (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00020001;
CHECKREG r2, 0x00080002;
CHECKREG r3, 0x00180003;
CHECKREG r4, 0x00400004;
CHECKREG r5, 0x00A00005;
CHECKREG r6, 0x01800006;
CHECKREG r7, 0x03800007;
imm32 r0, 0xf0090001;
imm32 r1, 0xf0090001;
imm32 r2, 0xf0090002;
imm32 r3, 0xf0090003;
imm32 r4, 0xf0090004;
imm32 r5, 0xf0090005;
imm32 r6, 0xf0000006;
imm32 r7, 0xf0000007;
R1.H = R0.L << 8 (S);
R2.H = R1.L << 9 (S);
R3.H = R2.L << 10 (S);
R4.H = R3.L << 11 (S);
R5.H = R4.L << 12 (S);
R6.H = R5.L << 13 (S);
R7.H = R6.L << 14 (S);
R0.H = R7.L << 15 (S);
CHECKREG r1, 0x01000001;
CHECKREG r2, 0x02000002;
CHECKREG r3, 0x08000003;
CHECKREG r4, 0x18000004;
CHECKREG r5, 0x40000005;
CHECKREG r6, 0x7FFF0006;
CHECKREG r7, 0x7FFF0007;
CHECKREG r0, 0x7FFF0001;
imm32 r0, 0x07000001;
imm32 r1, 0x07000001;
imm32 r2, 0x0700000f;
imm32 r3, 0x07000003;
imm32 r4, 0x07000004;
imm32 r5, 0x07000005;
imm32 r6, 0x07000006;
imm32 r7, 0x07000007;
R3.H = R0.L << 0 (S);
R4.H = R1.L << 1 (S);
R5.H = R2.L << 2 (S);
R6.H = R3.L << 3 (S);
R7.H = R4.L << 4 (S);
R0.H = R5.L << 5 (S);
R1.H = R6.L << 6 (S);
R2.H = R7.L << 7 (S);
CHECKREG r0, 0x00A00001;
CHECKREG r1, 0x01800001;
CHECKREG r2, 0x0380000F;
CHECKREG r3, 0x00010003;
CHECKREG r4, 0x00020004;
CHECKREG r5, 0x003C0005;
CHECKREG r6, 0x00180006;
CHECKREG r7, 0x00400007;
imm32 r0, 0x00000501;
imm32 r1, 0x00000501;
imm32 r2, 0x00000502;
imm32 r3, 0x00000510;
imm32 r4, 0x00000504;
imm32 r5, 0x00000505;
imm32 r6, 0x00000506;
imm32 r7, 0x00000507;
R4.H = R0.L << 8 (S);
R5.H = R1.L << 9 (S);
R6.H = R2.L << 10 (S);
R7.H = R3.L << 11 (S);
R0.H = R4.L << 12 (S);
R1.H = R5.L << 13 (S);
R2.H = R6.L << 14 (S);
R3.H = R7.L << 15 (S);
CHECKREG r0, 0x7FFF0501;
CHECKREG r1, 0x7FFF0501;
CHECKREG r2, 0x7FFF0502;
CHECKREG r3, 0x7FFF0510;
CHECKREG r4, 0x7FFF0504;
CHECKREG r5, 0x7FFF0505;
CHECKREG r6, 0x7FFF0506;
CHECKREG r7, 0x7FFF0507;
imm32 r0, 0x00a00800;
imm32 r1, 0x00a10800;
imm32 r2, 0x00a20800;
imm32 r3, 0x00a30800;
imm32 r4, 0x00a40800;
imm32 r5, 0x00a50800;
imm32 r6, 0x00a60800;
imm32 r7, 0x00a70800;
R5.H = R0.H << 0 (S);
R6.H = R1.H << 1 (S);
R7.H = R2.H << 2 (S);
R0.H = R3.H << 3 (S);
R1.H = R4.H << 4 (S);
R2.H = R5.H << 5 (S);
R3.H = R6.H << 6 (S);
R4.H = R7.H << 7 (S);
CHECKREG r0, 0x05180800;
CHECKREG r1, 0x0A400800;
CHECKREG r2, 0x14000800;
CHECKREG r3, 0x50800800;
CHECKREG r4, 0x7FFF0800;
CHECKREG r5, 0x00A00800;
CHECKREG r6, 0x01420800;
CHECKREG r7, 0x02880800;
imm32 r0, 0x0c010000;
imm32 r1, 0x0c010001;
imm32 r2, 0x0c020000;
imm32 r3, 0x0c030000;
imm32 r4, 0x0c040000;
imm32 r5, 0x0c050000;
imm32 r6, 0x0c060000;
imm32 r7, 0x0c070000;
R6.H = R0.H << 8 (S);
R7.H = R1.H << 9 (S);
R0.H = R2.H << 10 (S);
R1.H = R3.H << 11 (S);
R2.H = R4.H << 12 (S);
R3.H = R5.H << 13 (S);
R4.H = R6.H << 14 (S);
R5.H = R7.H << 15 (S);
CHECKREG r0, 0x7FFF0000;
CHECKREG r1, 0x7FFF0001;
CHECKREG r2, 0x7FFF0000;
CHECKREG r3, 0x7FFF0000;
CHECKREG r4, 0x7FFF0000;
CHECKREG r5, 0x7FFF0000;
CHECKREG r6, 0x7FFF0000;
CHECKREG r7, 0x7FFF0000;
imm32 r0, 0x00b10000;
imm32 r1, 0x00b10000;
imm32 r2, 0x00b2000f;
imm32 r3, 0x00b30000;
imm32 r4, 0x00b40000;
imm32 r5, 0x00b50000;
imm32 r6, 0x00b60000;
imm32 r7, 0x00b70000;
R7.L = R0.H << 0 (S);
R0.L = R1.H << 1 (S);
R1.L = R2.H << 2 (S);
R2.L = R3.H << 3 (S);
R3.L = R4.H << 4 (S);
R4.L = R5.H << 5 (S);
R5.L = R6.H << 6 (S);
R6.L = R7.H << 7 (S);
CHECKREG r0, 0x00B10162;
CHECKREG r1, 0x00B102C8;
CHECKREG r2, 0x00B20598;
CHECKREG r3, 0x00B30B40;
CHECKREG r4, 0x00B416A0;
CHECKREG r5, 0x00B52D80;
CHECKREG r6, 0x00B65B80;
CHECKREG r7, 0x00B700B1;
imm32 r0, 0x0a010700;
imm32 r1, 0x0a010700;
imm32 r2, 0x0a020700;
imm32 r3, 0x0a030710;
imm32 r4, 0x0a040700;
imm32 r5, 0x0a050700;
imm32 r6, 0x0a060700;
imm32 r7, 0x0a070700;
R0.H = R0.H << 8 (S);
R1.H = R1.H << 9 (S);
R2.H = R2.H << 10 (S);
R3.H = R3.H << 11 (S);
R4.H = R4.H << 12 (S);
R5.H = R5.H << 13 (S);
R6.H = R6.H << 14 (S);
R7.H = R7.H << 15 (S);
CHECKREG r0, 0x7FFF0700;
CHECKREG r1, 0x7FFF0700;
CHECKREG r2, 0x7FFF0700;
CHECKREG r3, 0x7FFF0710;
CHECKREG r4, 0x7FFF0700;
CHECKREG r5, 0x7FFF0700;
CHECKREG r6, 0x7FFF0700;
CHECKREG r7, 0x7FFF0700;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,524 | sim/testsuite/bfin/c_dsp32mult_pair_u.s | //Original:/testcases/core/c_dsp32mult_pair_u/c_dsp32mult_pair_u.dsp
// Spec Reference: dsp32mult pair u
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L (FU);
R3 = R0.L * R1.L, R2 = R0.L * R1.H (FU);
R5 = R1.L * R0.L, R4 = R1.H * R0.L (FU);
R7 = R1.L * R1.L, R6 = R1.H * R1.H (FU);
CHECKREG r0, 0x1CFCE159;
CHECKREG r1, 0x1CFCE159;
CHECKREG r2, 0x19838F9C;
CHECKREG r3, 0xC65D90F1;
CHECKREG r4, 0x19838F9C;
CHECKREG r5, 0xC65D90F1;
CHECKREG r6, 0x03481810;
CHECKREG r7, 0xC65D90F1;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L (FU);
R3 = R2.L * R3.L, R2 = R2.L * R3.H (FU);
R5 = R3.L * R2.L, R4 = R3.H * R2.L (FU);
R7 = R3.L * R3.L, R6 = R3.H * R3.H (FU);
CHECKREG r0, 0x831CD0F9;
CHECKREG r1, 0x831CD0F9;
CHECKREG r2, 0x67121B3E;
CHECKREG r3, 0x95026C63;
CHECKREG r4, 0x0FDB4C7C;
CHECKREG r5, 0x0B88B0FA;
CHECKREG r6, 0x56BB5404;
CHECKREG r7, 0x2DE3AE49;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L (FU);
R3 = R4.L * R5.L, R2 = R4.L * R5.H (FU);
R5 = R5.L * R4.L, R4 = R5.H * R4.L (FU);
R7 = R5.L * R5.L, R6 = R5.H * R5.H (FU);
CHECKREG r0, 0x97A6DA51;
CHECKREG r1, 0x97A6DA51;
CHECKREG r2, 0x0CD4F20C;
CHECKREG r3, 0xB8397133;
CHECKREG r4, 0x0CD4F20C;
CHECKREG r5, 0xB8397133;
CHECKREG r6, 0x8491FCB1;
CHECKREG r7, 0x320E1029;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L (FU);
R3 = R6.L * R7.L, R2 = R6.L * R7.H (FU);
R5 = R7.L * R6.L, R4 = R7.H * R6.L (FU);
R7 = R7.L * R7.L, R6 = R7.H * R7.H (FU);
CHECKREG r0, 0x81FF2A69;
CHECKREG r1, 0x81FF2A69;
CHECKREG r2, 0x0D058BCE;
CHECKREG r3, 0x502A3013;
CHECKREG r4, 0x0D058BCE;
CHECKREG r5, 0x502A3013;
CHECKREG r6, 0x014DEB24;
CHECKREG r7, 0x316F5F01;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (FU);
R3 = R1.L * R0.H, R2 = R1.H * R0.L (FU);
R5 = R7.H * R4.L, R4 = R7.H * R4.L (FU);
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (FU);
CHECKREG r0, 0x000085FC;
CHECKREG r1, 0x0002D123;
CHECKREG r2, 0x00010BF8;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x0EA2B276;
CHECKREG r5, 0x0EA2B276;
CHECKREG r6, 0x0000BE3A;
CHECKREG r7, 0xFFFC0FFE;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H (FU);
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (FU);
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (FU);
R7 = R2.H * R7.L, R6 = R2.H * R7.L (FU);
CHECKREG r0, 0x0464B4BB;
CHECKREG r1, 0xB8ADBDCD;
CHECKREG r2, 0x00E2F57C;
CHECKREG r3, 0x0C6F8A4F;
CHECKREG r4, 0x71489715;
CHECKREG r5, 0xD7646535;
CHECKREG r6, 0x0062E7F2;
CHECKREG r7, 0x0062E7F2;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H (FU);
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (FU);
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (FU);
R1 = R2.H * R7.L, R0 = R2.L * R7.H (FU);
CHECKREG r0, 0x04A2FAE8;
CHECKREG r1, 0x00043554;
CHECKREG r2, 0x00092EBC;
CHECKREG r3, 0x000AEA44;
CHECKREG r4, 0xB7AF5568;
CHECKREG r5, 0x4A43345C;
CHECKREG r6, 0x00030A1D;
CHECKREG r7, 0x196677B4;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L (FU);
R3 = R2.L * R5.L, R2 = R2.L * R5.H (FU);
R5 = R3.H * R6.L, R4 = R3.L * R6.L (FU);
R7 = R4.L * R0.H, R6 = R4.H * R0.L (FU);
CHECKREG r0, 0xBF69768A;
CHECKREG r1, 0xBF69768A;
CHECKREG r2, 0x06B5875C;
CHECKREG r3, 0x601EC747;
CHECKREG r4, 0x00B87CBB;
CHECKREG r5, 0x0058FBC6;
CHECKREG r6, 0x00553330;
CHECKREG r7, 0x5D42ADB3;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,095 | sim/testsuite/bfin/c_interr_nmi.S | //Original:/proj/frio/dv/testcases/core/c_interr_nmi/c_interr_nmi.dsp
// Spec Reference: progctrl raise rti rtn
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC;
RAISE 15; // after we RTI, INT 15 should be taken
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// Can't Raise 0, 3, or 4
// Raise 1 requires some intelligence so the test
// doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD)
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
RAISE 2; // RTN
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
RAISE 15; // RTI
CHECKREG(r0, 0x0000000B);
CHECKREG(r1, 0x0000001A);
CHECKREG(r2, 0x00000024);
CHECKREG(r3, 0x00000028);
CHECKREG(r4, 0x0000000E);
CHECKREG(r5, 0x00000010);
CHECKREG(r6, 0x00000012);
CHECKREG(r7, 0x00000014);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
CHECKREG(r0, 0x0000000B);
CHECKREG(r1, 0x0000000E);
CHECKREG(r2, 0x00000017);
CHECKREG(r3, 0x0000001A);
CHECKREG(r4, 0x0000000E);
( R7:0 ) = [ SP ++ ]; // pop
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
CHECKREG(r4, 0x00000000);
CHECKREG(r5, 0x00000000);
CHECKREG(r6, 0x00000000);
CHECKREG(r7, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
R0 += 1;
R1 += 2;
RAISE 5; // RTI
RAISE 6; // RTI
RAISE 7; // RTI
RAISE 8; // RTI
RAISE 9; // RTI
RAISE 10; // RTI
RAISE 11; // RTI
RAISE 12; // RTI
RAISE 13; // RTI
RAISE 14; // RTI
RAISE 15; // RTI
[ -- SP ] = ( R7:0 ); // push
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
R2 += 5;
RTI;
THANDLE: // Timer Handler 6
R3 += 6;
RTI;
I7HANDLE: // IVG 7 Handler
R4 += 7;
RTI;
I8HANDLE: // IVG 8 Handler
R5 += 8;
RTI;
I9HANDLE: // IVG 9 Handler
R6 += 9;
RTI;
I10HANDLE: // IVG 10 Handler
R7 += 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 += 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 += 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 += 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 += 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 6,338 | sim/testsuite/bfin/c_progctrl_clisti_interr.S | //Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp
// Spec Reference: CLI STI interrupt on HW TIMER
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Include Files
//
include(std.inc)
include(selfcheck.inc)
// Defines
#ifndef TCNTL
#define TCNTL 0xFFE03000
#endif
#ifndef TPERIOD
#define TPERIOD 0xFFE03004
#endif
#ifndef TSCALE
#define TSCALE 0xFFE03008
#endif
#ifndef TCOUNT
#define TCOUNT 0xFFE0300c
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203c
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0x000FF000
#endif
#ifndef PROGRAM_STACK
#define PROGRAM_STACK 0x000FF100
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000300
#endif
// Boot code
INIT_R_REGS(0); // Initialize Dregs
INIT_P_REGS(0); // Initialize Pregs
//CHECK_INIT(p5, 0xE0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
BOOT :
LD32(sp, 0x000FF200);
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
LD32_LABEL(p1, START);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
LD32_LABEL(r7, START);
RETI = r7;
NOP; // Workaround for Bug 217
RTI;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
DUMMY:
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
START :
R7 = 0x0;
R6 = 0x1;
[ -- SP ] = RETI; // Enable Nested Interrupts
CLI R1; // stop interrupt
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
WR_MMR(TPERIOD, 0x00000050, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000000, p0, r0);
CSYNC;
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000050);
// RD_MMR(TCOUNT, p0, r3);
// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
CSYNC;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
NOP; NOP; NOP;
RD_MMR(TPERIOD, p0, r4);
CHECKREG(r4, 0x00000050);
// RD_MMR(TCNTL, p0, r5);
// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP;
WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
WR_MMR(TPERIOD, 0x00000015, p0, r0);
WR_MMR(TCOUNT, 0x00000013, p0, r0);
WR_MMR(TSCALE, 0x00000002, p0, r0);
WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1)
CSYNC;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
JUMP.S label4;
R4.L = 0x1111; // Will be killed
R4.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
label5: R5.H = 0x7777;
R5.L = 0x7888;
JUMP.S label6;
R5.L = 0x1111; // Will be killed
R5.H = 0x1111; // Will be killed
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
label4: R4.H = 0x5555;
R4.L = 0x6666;
NOP;
JUMP.S label5;
R5.L = 0x2222; // Will be killed
R5.H = 0x2222; // Will be killed
NOP;
NOP;
NOP;
NOP;
label6: R3.H = 0x7999;
R3.L = 0x7aaa;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
// With auto reload
// Read the contents of the Timer
RD_MMR(TPERIOD, p0, r2);
CHECKREG(r2, 0x00000015);
// RD_MMR(TCNTL , p0, r3);
// CHECKREG(r3, 0x0000000F);
NOP;
CHECKREG(r7, 0x00000000); // no interrupt being serviced
NOP;
STI R1;
NOP; NOP; NOP;
NOP; NOP; NOP;
WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
CSYNC;
NOP; NOP; NOP;
dbg_pass; // Call Endtest Macro
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
R7 = R7 + R6;
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
R5 = RETI;
P0 = R5;
JUMP ( P0 );
RTI;
.section MEM_PROGRAM_STACK,"aw"
.space (STACKSIZE);
STACK:
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
|
tactcomplabs/xbgas-binutils-gdb | 7,454 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_u.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_u/c_dsp32mac_pair_a1a0_u.dsp
// Spec Reference: dsp32mac pair a1a0 U
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ), R6 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ), R0 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R4.L ), R2 = ( A0 += R7.H * R4.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ), R4 = ( A0 += R6.L * R5.H ) (FU);
FP = A1.w;
CHECKREG r0, 0x00049ABC;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x549454CC;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x55A3F173;
CHECKREG r5, 0x07CFA619;
CHECKREG r6, 0x5A4E0EEB;
CHECKREG r7, 0x5A4E0EEB;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0x5A4E0EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0x00049ABC;
CHECKREG p5, 0x00000000;
CHECKREG sp, 0x549454CC;
CHECKREG fp, 0x07CFA619;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R1.L * R0.H ), R4 = ( A0 -= R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 -= R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (FU);
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R4.L * R5.H ), R2 = ( A0 += R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R7.H ), R0 = ( A0 += R6.L * R7.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x089013D8;
CHECKREG r1, 0x6C5ACAC6;
CHECKREG r2, 0x088458C2;
CHECKREG r3, 0x6C4F0FB0;
CHECKREG r4, 0x0E2DB488;
CHECKREG r5, 0x9996A1D3;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x9996A1D3;
CHECKREG p2, 0x00032564;
CHECKREG p3, 0x99964B8A;
CHECKREG p4, 0x00032564;
CHECKREG p5, 0x6C4F0FB0;
CHECKREG sp, 0x088458C2;
CHECKREG fp, 0x089013D8;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 -= R2.H * R3.L ), R6 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.H * R7.L ), R4 = ( A0 -= R6.L * R7.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x1A2AB610;
CHECKREG r1, 0x24F02BB4;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x0BE761C4;
CHECKREG r5, 0x24F2761C;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x9B11C378;
CHECKREG p1, 0x9B14DB04;
CHECKREG p2, 0x2B2D030B;
CHECKREG p3, 0x9B11C378;
CHECKREG p5, 0x24F02BB4;
CHECKREG p4, 0x0003178C;
CHECKREG sp, 0x1A2AB610;
CHECKREG fp, 0x0BE761C4;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 -= R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 -= R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (FU);
P5 = A1.w;
SP = A0.w;
R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x0003F74D;
CHECKREG r1, 0xD0349621;
CHECKREG r2, 0x63278394;
CHECKREG r3, 0x46B1FE11;
CHECKREG r4, 0x6328BB2E;
CHECKREG r5, 0x46B0C677;
CHECKREG r6, 0x6CB2D756;
CHECKREG r7, 0x4BBE7457;
CHECKREG p1, 0xD0349621;
CHECKREG p2, 0x0003F74D;
CHECKREG p3, 0x46B1FE11;
CHECKREG p4, 0x63278394;
CHECKREG p5, 0x46B0C677;
CHECKREG sp, 0x6328BB2E;
CHECKREG fp, 0x6CB2D756;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 -= R6.L * R5.L ) (M), R4 = ( A0 -= R6.L * R5.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x00049ABC;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x46897C84;
CHECKREG r3, 0x316C7D3D;
CHECKREG r4, 0x4579DFDD;
CHECKREG r5, 0x299CD724;
CHECKREG r6, 0x5A4E0EEB;
CHECKREG r7, 0x4B4F8342;
CHECKREG p1, 0x4B4F8342;
CHECKREG p2, 0x5A4E0EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0x00049ABC;
CHECKREG p5, 0x316C7D3D;
CHECKREG sp, 0x46897C84;
CHECKREG fp, 0x4579DFDD;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 -= R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 -= R6.L * R7.H ) (FU);
FP = A1.w;
CHECKREG r0, 0x5304CE59;
CHECKREG r1, 0x299CD724;
CHECKREG r2, 0x5310896F;
CHECKREG r3, 0x299CD724;
CHECKREG r4, 0x47763CEB;
CHECKREG r5, 0x299CD724;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x299CD724;
CHECKREG p2, 0x47763CEB;
CHECKREG p3, 0x299CD724;
CHECKREG p4, 0x47731787;
CHECKREG p5, 0x299CD724;
CHECKREG sp, 0x5310896F;
CHECKREG fp, 0x299CD724;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R2.H * R3.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 -= R4.H * R5.H ) (FU);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R6.L * R7.H ) (FU);
FP = A1.w;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x2706223A;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x01B8DC2C;
CHECKREG r5, 0x2706223A;
CHECKREG r6, 0x0003178C;
CHECKREG r7, 0x12B9E762;
CHECKREG p1, 0x12B9E762;
CHECKREG p2, 0x2B2D030B;
CHECKREG p3, 0x12B9E762;
CHECKREG p4, 0x0003178C;
CHECKREG p5, 0x2706223A;
CHECKREG sp, 0x00000000;
CHECKREG fp, 0x2706223A;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 -= R5.L * R3.L ) (FU);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (FU);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (FU);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (FU);
FP = A0.w;
CHECKREG r0, 0x01B4E4DF;
CHECKREG r1, 0x2706223A;
CHECKREG r2, 0x169AF688;
CHECKREG r3, 0xF2C00278;
CHECKREG r4, 0x174BDCA0;
CHECKREG r5, 0x00B0E618;
CHECKREG r6, 0x228A5420;
CHECKREG r7, 0x00B0E618;
CHECKREG p1, 0x2706223A;
CHECKREG p2, 0x01B4E4DF;
CHECKREG p3, 0xF2C00278;
CHECKREG p4, 0x169AF688;
CHECKREG p5, 0x174BDCA0;
CHECKREG sp, 0x00B0E618;
CHECKREG fp, 0x228A5420;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,885 | sim/testsuite/bfin/c_cactrl_iflush_pr_pp.s | //Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp
// Spec Reference: c_cactrl iflush_pr [p++]
# mach: bfin
.include "testutils.inc"
start
loadsym p2, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg half
R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R3.H = A1 , A0 = R7.H * R6.L (T);
// begin of iflush
IFLUSH [ P2 ++ ]; // p2 = 0x448
R7 = 0;
ASTAT = R7;
IF !CC JUMP SUBR1;
JBACK:
R6 = 0;
//r4 = (a1 = l*h) M, a0 = h*l (r3,r2);
//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS;
CHECKREG r2, 0xFFD15679;
CHECKREG r3, 0xFFD00007;
CHECKREG r4, 0x00074569;
CHECKREG r5, 0x12358000;
//CHECKREG p2, 0x00000468;
pass
//.code 0x448
//.code CODE_ADDR_1
SUBR1:
R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
IF !CC JUMP JBACK;
NOP; NOP; NOP; NOP; NOP;
// Pre-load memory witb known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
|
tactcomplabs/xbgas-binutils-gdb | 2,422 | sim/testsuite/bfin/c_cc_flagdreg_mvbrsft_s1.s | //Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_s1/c_cc_flagdreg_mvbrsft_s1.dsp
// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
# mach: bfin
.include "testutils.inc"
start
INIT_P_REGS 0;
imm32 r0, 0xa08d2311;
imm32 r1, 0x10120040;
imm32 r2, 0x62b61557;
imm32 r3, 0x07300007;
imm32 r4, 0x00740088;
imm32 r5, 0x609950aa;
imm32 r6, 0x20bb06cc;
imm32 r7, 0xd90e108f;
ASTAT = R0;
CC = R1; // cc2dreg
R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac
IF CC R1 = R3; // ccmov
CC = ! CC; // cc2dreg
R4.H = R1.L + R0.L (S); // dsp32alu
IF CC R3 = R2; // ccmov
CC = R0 < R1; // ccflag
R4.L = R5.L << 1; // dsp32shiftimm
IF CC R4 = R5; // ccmov
CC = R2 == R3; // ccflag
R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
IF !CC JUMP LABEL1; // branch on
CC = ! CC; // cc2dreg
P1.L = 0x3000; // ldimmhalf
IF !CC JUMP LABEL2 (BP); // branch
LABEL1:
R6 = R6 + R2;
JUMP.S END;
LABEL2:
R7 = R5 - R7;
CC = R0 < R1; // ccflag
P2 = A0.w;
IF CC JUMP END (BP); // branch
P3 = A1.w;
R5 = R5 + R7;
END:
CHECKREG r0, 0xA08D2311;
CHECKREG r1, 0x07300007;
CHECKREG r2, 0x00011557;
CHECKREG r3, 0x07300007;
CHECKREG r4, 0x609950AA;
CHECKREG r5, 0x609950AA;
CHECKREG r6, 0x056C9760;
CHECKREG r7, 0x6094E75E;
CHECKREG p1, 0x00003000;
CHECKREG p2, 0x01382894;
CHECKREG p3, 0x00000000;
imm32 r0, 0x408d2711;
imm32 r1, 0x15124040;
imm32 r2, 0x62661557;
imm32 r3, 0x073b0007;
imm32 r4, 0x01f49088;
imm32 r5, 0x6e2959aa;
imm32 r6, 0xa0b506cc;
imm32 r7, 0x00000002;
CC = R1; // cc2dreg
R2 = ROT R2 BY 1; // dsp32shiftim_rot
CC = ! CC; // cc2dreg
R3 >>= R7; // alu2op sft
R3 = ROT R0 BY -3; // dsp32shiftim_rot
CC = R0 < R1; // ccflag
R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
R6 = ROT R4 BY 5; // dsp32shiftim_rot
CC = R2 == R3; // ccflag
P1 = R1; // regmv
IF CC R4 = R5; // ccmov
CC = R0; // cc2dreg
R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
R7 = ROT R6 BY R7.L; // dsp32shiftim_rot
CHECKREG r0, 0x408D2711;
CHECKREG r1, 0x2ACFF368;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xFFFC8440;
CHECKREG r4, 0x01F49088;
CHECKREG r5, 0x6E2959AA;
CHECKREG r6, 0x15BD33A8;
CHECKREG r7, 0x56F4CEA2;
CHECKREG p1, 0x15124040;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,193 | sim/testsuite/bfin/c_ldst_ld_d_p.s | //Original:/testcases/core/c_ldst_ld_d_p/c_ldst_ld_d_p.dsp
// Spec Reference: c_ldst ld d [p]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P1 ];
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ P5 ];
R6 = [ FP ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x80818283;
CHECKREG r6, 0x00010203;
R1 = [ P2 ];
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
CHECKREG r0, 0x20212223;
CHECKREG r1, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R3 = [ P4 ];
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
CHECKREG r0, 0x20212223;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R4 = [ P5 ];
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R5 = [ FP ];
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
R3 = [ P5 ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x80818283;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
R3 = [ P5 ];
R4 = [ FP ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x80818283;
CHECKREG r4, 0x00010203;
CHECKREG r5, 0x00010203;
CHECKREG r7, 0x00010203;
R7 = [ P1 ];
R0 = [ P2 ];
R2 = [ P4 ];
R3 = [ P5 ];
R4 = [ FP ];
CHECKREG r0, 0x20212223;
CHECKREG r2, 0x60616263;
CHECKREG r3, 0x80818283;
CHECKREG r4, 0x00010203;
CHECKREG r6, 0x00010203;
CHECKREG r7, 0x00010203;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,559 | sim/testsuite/bfin/random_0010.S | # Test logical left shift (vector) insns with larger shift values
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN);
imm32 R5, 0xb0b40000;
imm32 R6, 0xf43a5d3c;
R6 = R5 << 0x19 (V, S);
checkreg R6, 0xff610000;
checkreg ASTAT, (0x30400e90 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ);
dmm32 ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
imm32 R2, 0xff2abd08;
imm32 R5, 0xf610ffff;
R2 = R5 << 0x11 (V, S);
checkreg R2, 0xffffffff;
checkreg ASTAT, (0x34104410 | _VS | _AV1S | _AV0S | _AC1 | _AC0 | _AN);
dmm32 ASTAT, (0x6cd0c680 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R0, 0x760ecf8e;
imm32 R1, 0x3f5c8af5;
R0 = R1 << 0x17 (V, S);
checkreg R0, 0x001fffc5;
checkreg ASTAT, (0x6cd0c680 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC);
imm32 R4, 0x520cb3d4;
imm32 R6, 0x67141e28;
R6 = R4 << 0x14 (V, S);
checkreg R6, 0x0005fffb;
checkreg ASTAT, (0x44a04280 | _AV1S | _AV1 | _AC1 | _AC0 | _CC | _AN);
dmm32 ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN);
imm32 R3, 0x40407f7e;
imm32 R4, 0xc081e040;
R3 = R4 << 0x1a (V, S);
checkreg R3, 0xff02ff81;
checkreg ASTAT, (0x14600c10 | _VS | _AV1S | _AC1 | _AC0 | _AN);
dmm32 ASTAT, (0x04f00490 | _VS | _V | _AV0S | _AC1 | _AQ | _V_COPY);
imm32 R5, 0x63654235;
imm32 R7, 0x00008000;
R5 = R7 << 0x18 (V, S);
checkreg R5, 0x0000ff80;
checkreg ASTAT, (0x04f00490 | _VS | _AV0S | _AC1 | _AQ | _AN | _AZ);
dmm32 ASTAT, (0x3830ca90 | _VS | _V | _AV1S | _AV0S | _AC1 | _CC | _V_COPY | _AN);
imm32 R1, 0x40000000;
imm32 R2, 0x7fffffff;
R1 = R2 << 0x16 (V, S);
checkreg R1, 0x001fffff;
checkreg ASTAT, (0x3830ca90 | _VS | _AV1S | _AV0S | _AC1 | _CC | _AN);
dmm32 ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ);
imm32 R2, 0xfffe0000;
imm32 R3, 0xd9d90000;
R2 = R3 << 0x19 (V, S);
checkreg R2, 0xffb30000;
checkreg ASTAT, (0x24e08890 | _VS | _AV0S | _AC1 | _CC | _AN | _AZ);
dmm32 ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AZ);
imm32 R0, 0x32590000;
imm32 R2, 0x708bb53f;
R0 = R2 << 0x1c (V, S);
checkreg R0, 0x0708fb53;
checkreg ASTAT, (0x30f0c200 | _VS | _AV1S | _AQ | _CC | _AC0_COPY | _AN);
dmm32 ASTAT, (0x4cc00080 | _VS | _V | _AC1 | _AQ | _V_COPY | _AC0_COPY | _AN);
imm32 R3, 0x3563cfa3;
imm32 R7, 0x027e2255;
R7 = R3 << 0x1f (V, S);
checkreg R7, 0x1ab1e7d1;
checkreg ASTAT, (0x4cc00080 | _VS | _AC1 | _AQ | _AC0_COPY | _AN);
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,635 | sim/testsuite/bfin/se_misaligned_fetch.S | //Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp
// Description: attempt to fetch code from misaligned address
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
CLI R0; // hold off nonmaskables while writing EVTs
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC; // wait for MMR writes
STI R0; // reenable events
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
// JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
// [--sp] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
LD32_LABEL(p1, TARGET);
P1 += 1; // cause access to be misaligned
JUMP ( P1 ); // should cause misaligned
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
R1 += 1;
TARGET:
NOP;
NOP;
NOP;
// PUT YOUR TEST HERE!
END:
CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
[ -- SP ] = ASTAT; // save what we damage
[ -- SP ] = ( R7:6 );
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access
CC = r7 == r6;
IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave
dbg_pass; // if the EXCAUSE is wrong the test will infinite loop
IFETCHMISALIGNED:
R7 = P1; // Fix up return address
BITCLR(r7, 0); // Strip off errant LSB
RETX = r7; // and put back in RETX
R5 = -1; // set flag to indicate success
OUT:
( R7:6 ) = [ SP ++ ];
ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 2,751 | sim/testsuite/bfin/abs_acc.s | // ACP 5.7 ABS(A1) sets AV0
# mach: bfin
.include "testutils.inc"
start
r1=0x80 (z);
A0=0;
A0.x=r1;
A0=abs A0;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x3);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
r6=A0.x;
dbga (r6.l, 0x7f);
r1=0x80 (z);
A1=0;
A1.x=r1;
A1=abs A1;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0xf);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 1);
cc = av1s;
r7 = cc;
dbga( r7.l, 1);
r6=A1.x;
dbga (r6.l, 0x7f);
r7=0;
astat=r7;
r1=0x80 (z);
A1=0;
A1.x=r1;
A0 = abs A1;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x3);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
r6=A0.x;
dbga (r6.l, 0x7f);
r7=0;
astat=r7;
r1=0x80 (z);
A0=0;
A0.x=r1;
A1 = abs A0;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0xc);
//dbga (r7.l, 0x0);
cc = az;
r3 = cc;
dbga( r3.l, 0);
cc = an;
r3 = cc;
dbga( r3.l, 0);
cc = av0;
r3 = cc;
dbga( r3.l, 0);
cc = av0s;
r3 = cc;
dbga( r3.l, 0);
cc = av1;
r3 = cc;
dbga( r3.l, 1);
cc = av1s;
r3 = cc;
dbga( r3.l, 1);
r6=A1.x;
dbga (r6.l, 0x7f);
r7=0;
astat=r7;
r1=0x80 (z);
A1=0;
A1.x=r1;
A0.x=r6;
_DBG A1;
_DBG A0;
A1=abs A1, A0=abs A0;
_DBG ASTAT;
//r7=astat;
//dbga (r7.h, 0xc);
//dbga (r7.l, 0x0);
cc = az;
r4 = cc;
dbga( r4.l, 0);
cc = an;
r4 = cc;
dbga( r4.l, 0);
cc = av0;
r4 = cc;
dbga( r4.l, 0);
cc = av0s;
r4 = cc;
dbga( r4.l, 0);
cc = av1;
r4 = cc;
dbga( r4.l, 1);
cc = av1s;
r4 = cc;
dbga( r4.l, 1);
r7=0;
astat=r7;
r1=0x80 (z);
A1=0;
A1.x=r1;
A0 = A1;
A1=abs A1, A0=abs A0;
_DBG ASTAT;
//r7=astat;
//dbga (r7.h, 0xf);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 1);
cc = av1s;
r7 = cc;
dbga( r7.l, 1);
// ACP 5.8 ABS sometimes sets AN
r7=0;
astat=r7;
r0=1;
r1=abs r0;
_DBG r0;
_DBG r1;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x0);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
pass;
|
tactcomplabs/xbgas-binutils-gdb | 2,492 | sim/testsuite/bfin/c_logi2op_bitclr.s | //Original:/testcases/core/c_logi2op_bitclr/c_logi2op_bitclr.dsp
// Spec Reference: Logi2op functions: bitclr
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0xffffffff;
imm32 r1, 0xffffffff;
imm32 r2, 0xffffffff;
imm32 r3, 0xffffffff;
imm32 r4, 0xffffffff;
imm32 r5, 0xffffffff;
imm32 r6, 0xffffffff;
imm32 r7, 0xffffffff;
// bit clr
BITCLR( R0 , 0 ); /* r0 = 0x00000001 */
BITCLR( R1 , 1 ); /* r1 = 0x00000002 */
BITCLR( R2 , 2 ); /* r2 = 0x00000004 */
BITCLR( R3 , 3 ); /* r3 = 0x00000008 */
BITCLR( R4 , 4 ); /* r4 = 0x00000010 */
BITCLR( R5 , 5 ); /* r5 = 0x00000020 */
BITCLR( R6 , 6 ); /* r6 = 0x00000040 */
BITCLR( R7 , 7 ); /* r7 = 0x00000080 */
CHECKREG r0, 0xfffffffe;
CHECKREG r1, 0xfffffffd;
CHECKREG r2, 0xfffffffb;
CHECKREG r3, 0xfffffff7;
CHECKREG r4, 0xffffffef;
CHECKREG r5, 0xffffffdf;
CHECKREG r6, 0xffffffbf;
CHECKREG r7, 0xffffff7f;
// bit clr
BITCLR( R0 , 8 ); /* r0 = 0x00000100 */
BITCLR( R1 , 9 ); /* r1 = 0x00000200 */
BITCLR( R2 , 10 ); /* r2 = 0x00000400 */
BITCLR( R3 , 11 ); /* r3 = 0x00000800 */
BITCLR( R4 , 12 ); /* r4 = 0x00001000 */
BITCLR( R5 , 13 ); /* r5 = 0x00002000 */
BITCLR( R6 , 14 ); /* r6 = 0x00004000 */
BITCLR( R7 , 15 ); /* r7 = 0x00008000 */
CHECKREG r0, 0xfffffefe;
CHECKREG r1, 0xfffffdfd;
CHECKREG r2, 0xfffffbfb;
CHECKREG r3, 0xfffff7f7;
CHECKREG r4, 0xffffefef;
CHECKREG r5, 0xffffdfdf;
CHECKREG r6, 0xffffbfbf;
CHECKREG r7, 0xffff7f7f;
// bit clr
BITCLR( R0 , 16 ); /* r0 = 0x00000100 */
BITCLR( R1 , 17 ); /* r1 = 0x00000200 */
BITCLR( R2 , 18 ); /* r2 = 0x00000400 */
BITCLR( R3 , 19 ); /* r3 = 0x00000800 */
BITCLR( R4 , 20 ); /* r4 = 0x00001000 */
BITCLR( R5 , 21 ); /* r5 = 0x00002000 */
BITCLR( R6 , 22 ); /* r6 = 0x00004000 */
BITCLR( R7 , 23 ); /* r7 = 0x00008000 */
CHECKREG r0, 0xfffefefe;
CHECKREG r1, 0xfffdfdfd;
CHECKREG r2, 0xfffbfbfb;
CHECKREG r3, 0xfff7f7f7;
CHECKREG r4, 0xffefefef;
CHECKREG r5, 0xffdfdfdf;
CHECKREG r6, 0xffbfbfbf;
CHECKREG r7, 0xff7f7f7f;
// bit clr
BITCLR( R0 , 24 ); /* r0 = 0x00000100 */
BITCLR( R1 , 25 ); /* r1 = 0x00000200 */
BITCLR( R2 , 26 ); /* r2 = 0x00000400 */
BITCLR( R3 , 27 ); /* r3 = 0x00000800 */
BITCLR( R4 , 28 ); /* r4 = 0x00001000 */
BITCLR( R5 , 29 ); /* r5 = 0x00002000 */
BITCLR( R6 , 30 ); /* r6 = 0x00004000 */
BITCLR( R7 , 31 ); /* r7 = 0x00008000 */
CHECKREG r0, 0xfefefefe;
CHECKREG r1, 0xfdfdfdfd;
CHECKREG r2, 0xfbfbfbfb;
CHECKREG r3, 0xf7f7f7f7;
CHECKREG r4, 0xefefefef;
CHECKREG r5, 0xdfdfdfdf;
CHECKREG r6, 0xbfbfbfbf;
CHECKREG r7, 0x7f7f7f7f;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,057 | sim/testsuite/bfin/c_brcc_bp2.s | //Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,798 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_m.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_m/c_dsp32mac_pair_a1a0_m.dsp
// Spec Reference: dsp32mac pair a1a0 M MNOP
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R0.L * R1.L ) (M), R6 = ( A0 = R0.L * R1.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R3.L * R2.L ) (M), R0 = ( A0 = R3.H * R2.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 -= R7.L * R6.L ) (M), R2 = ( A0 += R7.H * R6.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R5.L * R4.L ) (M), R4 = ( A0 += R5.L * R4.H ) (IS);
FP = A0.w;
CHECKREG r0, 0x002D4356;
CHECKREG r1, 0x00025D4F;
CHECKREG r2, 0x00061B84;
CHECKREG r3, 0xFF23D196;
CHECKREG r4, 0x07C7B86C;
CHECKREG r5, 0xCED42319;
CHECKREG r6, 0xFF910EEB;
CHECKREG r7, 0x5A4E0EEB;
CHECKREG p1, 0x5A4E0EEB;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0x002D4356;
CHECKREG p5, 0xFF23D196;
CHECKREG sp, 0x00061B84;
CHECKREG fp, 0x07C7B86C;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R3.L * R1.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 -= R0.H * R5.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R2.H * R7.H ) (IS);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 -= R4.L * R6.H ) (IS);
FP = A1.w;
CHECKREG r0, 0xE7CEC8D1;
CHECKREG r1, 0xCED42319;
CHECKREG r2, 0xE7CC2775;
CHECKREG r3, 0xCED42319;
CHECKREG r4, 0xFFFFC7E3;
CHECKREG r5, 0xCED42319;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xCED42319;
CHECKREG p2, 0xFFFFC7E3;
CHECKREG p3, 0xCED42319;
CHECKREG p4, 0x0E31C25D;
CHECKREG p5, 0xCED42319;
CHECKREG sp, 0xE7CC2775;
CHECKREG fp, 0xCED42319;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R4.H * R3.L ) (M), R4 = ( A0 = R4.L * R3.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R5.H * R0.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R2.H * R6.L ) (M), R0 = ( A0 += R2.H * R6.H ) (IS);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R7.L * R1.H ) (IS);
FP = A1.w;
CHECKREG r0, 0xECB84AE7;
CHECKREG r1, 0x5091B70C;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0xD3A83F94;
CHECKREG r5, 0x5091B70C;
CHECKREG r6, 0xF2A0B667;
CHECKREG r7, 0xCED3B05D;
CHECKREG p1, 0xCED3B05D;
CHECKREG p2, 0x000095DF;
CHECKREG p3, 0xCED3B05D;
CHECKREG p4, 0xF2A0B667;
CHECKREG p5, 0x5091B70C;
CHECKREG sp, 0xECB84AE7;
CHECKREG fp, 0x5091B70C;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 = R5.L * R2.L ) (IS);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R3.H * R1.H ) (M), R2 = ( A0 -= R3.H * R1.L ) (IS);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (IS);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (IS);
FP = A0.w;
CHECKREG r0, 0xDA854033;
CHECKREG r1, 0x5091B70C;
CHECKREG r2, 0xCD00D267;
CHECKREG r3, 0xF1127221;
CHECKREG r4, 0xBDCBD4BD;
CHECKREG r5, 0x58A90256;
CHECKREG r6, 0xBB976699;
CHECKREG r7, 0x58A90256;
CHECKREG p1, 0x5091B70C;
CHECKREG p2, 0xDA854033;
CHECKREG p3, 0xF1127221;
CHECKREG p4, 0xCD00D267;
CHECKREG p5, 0xBDCBD4BD;
CHECKREG sp, 0x58A90256;
CHECKREG fp, 0xBB976699;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,167 | sim/testsuite/bfin/c_regmv_dr_dep_nostall.s | //Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp
// Spec Reference: regmv dr-dep no stall
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x00110001;
imm32 r2, 0x00220002;
imm32 r3, 0x00330003;
imm32 r4, 0x00440004;
imm32 r5, 0x00550005;
imm32 r6, 0x00660006;
imm32 r7, 0x00770007;
// R-reg to R-reg: no stall
R0 = R0;
R1 = R0;
R2 = R1;
R3 = R2;
R4 = R3;
R5 = R4;
R6 = R5;
R7 = R6;
R0 = R7;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
//imm32 p0, 0x00001111;
imm32 p1, 0x22223333;
imm32 p2, 0x44445555;
imm32 p3, 0x66667777;
imm32 p4, 0x88889999;
imm32 p5, 0xaaaabbbb;
imm32 fp, 0xccccdddd;
imm32 sp, 0xeeeeffff;
// P-reg to R-reg to I,M reg: no stall
R0 = P0;
I0 = R0;
R1 = P1;
I1 = R1;
R2 = P2;
I2 = R2;
R3 = P3;
I3 = R3;
R4 = P4;
M0 = R4;
R5 = P5;
M1 = R5;
R6 = FP;
M2 = R6;
R7 = SP;
M3 = R7;
CHECKREG r1, 0x22223333;
CHECKREG r2, 0x44445555;
CHECKREG r3, 0x66667777;
CHECKREG r4, 0x88889999;
CHECKREG r5, 0xAAAABBBB;
CHECKREG r6, 0xCCCCDDDD;
CHECKREG r7, 0xEEEEFFFF;
R0 = M3;
R1 = M2;
R2 = M1;
R3 = M0;
R4 = I3;
R5 = I2;
R6 = I1;
R7 = I0;
CHECKREG r0, 0xEEEEFFFF;
CHECKREG r1, 0xCCCCDDDD;
CHECKREG r2, 0xAAAABBBB;
CHECKREG r3, 0x88889999;
CHECKREG r4, 0x66667777;
CHECKREG r5, 0x44445555;
CHECKREG r6, 0x22223333;
imm32 i0, 0x00001111;
imm32 i1, 0x22223333;
imm32 i2, 0x44445555;
imm32 i3, 0x66667777;
imm32 m0, 0x88889999;
imm32 m0, 0xaaaabbbb;
imm32 m0, 0xccccdddd;
imm32 m0, 0xeeeeffff;
// I,M-reg to R-reg to P-reg: no stall
R0 = I0;
P1 = R0;
R1 = I1;
P1 = R1;
R2 = I2;
P2 = R2;
R3 = I3;
P3 = R3;
R4 = M0;
P4 = R4;
R5 = M1;
P5 = R5;
R6 = M2;
SP = R6;
R7 = M3;
FP = R7;
CHECKREG p1, 0x22223333;
CHECKREG p2, 0x44445555;
CHECKREG p3, 0x66667777;
CHECKREG p4, 0xEEEEFFFF;
CHECKREG p5, 0xAAAABBBB;
CHECKREG sp, 0xCCCCDDDD;
CHECKREG fp, 0xEEEEFFFF;
imm32 i0, 0x10001111;
imm32 i1, 0x12221333;
imm32 i2, 0x14441555;
imm32 i3, 0x16661777;
imm32 m0, 0x18881999;
imm32 m1, 0x1aaa1bbb;
imm32 m2, 0x1ccc1ddd;
imm32 m3, 0x1eee1fff;
// I,M-reg to R-reg to L,B reg: no stall
R0 = I0;
L0 = R0;
R1 = I1;
L1 = R1;
R2 = I2;
L2 = R2;
R3 = I3;
L3 = R3;
R4 = M0;
B0 = R4;
R5 = M1;
B1 = R5;
R6 = M2;
B2 = R6;
R7 = M3;
B3 = R7;
CHECKREG r0, 0x10001111;
CHECKREG r1, 0x12221333;
CHECKREG r2, 0x14441555;
CHECKREG r3, 0x16661777;
CHECKREG r4, 0x18881999;
CHECKREG r5, 0x1AAA1BBB;
CHECKREG r6, 0x1CCC1DDD;
CHECKREG r7, 0x1EEE1FFF;
R0 = L3;
R1 = L2;
R2 = L1;
R3 = L0;
R4 = B3;
R5 = B2;
R6 = B1;
R7 = B0;
CHECKREG r0, 0x16661777;
CHECKREG r1, 0x14441555;
CHECKREG r2, 0x12221333;
CHECKREG r3, 0x10001111;
CHECKREG r4, 0x1EEE1FFF;
CHECKREG r5, 0x1CCC1DDD;
CHECKREG r6, 0x1AAA1BBB;
CHECKREG r7, 0x18881999;
imm32 l0, 0x20003111;
imm32 l1, 0x22223333;
imm32 l2, 0x24443555;
imm32 l3, 0x26663777;
imm32 b0, 0x28883999;
imm32 b0, 0x2aaa3bbb;
imm32 b0, 0x2ccc3ddd;
imm32 b0, 0x2eee3fff;
// L,B-reg to R-reg to I,M reg: no stall
R0 = L0;
I0 = R0;
R1 = L1;
I1 = R1;
R2 = L2;
I2 = R2;
R3 = L3;
I3 = R3;
R4 = B0;
M0 = R4;
R5 = B1;
M1 = R5;
R6 = B2;
M2 = R6;
R7 = B3;
M3 = R7;
R0 = M3;
R1 = M2;
R2 = M1;
R3 = M0;
R4 = I3;
R5 = I2;
R6 = I1;
R7 = I0;
CHECKREG r0, 0x1EEE1FFF;
CHECKREG r1, 0x1CCC1DDD;
CHECKREG r2, 0x1AAA1BBB;
CHECKREG r3, 0x2EEE3FFF;
CHECKREG r4, 0x26663777;
CHECKREG r5, 0x24443555;
CHECKREG r6, 0x22223333;
CHECKREG r7, 0x20003111;
imm32 r0, 0x00000030;
imm32 r1, 0x00000031;
imm32 r2, 0x00000003;
imm32 r3, 0x00330003;
imm32 r4, 0x00440004;
imm32 r5, 0x00550005;
imm32 r6, 0x00660006;
imm32 r7, 0x00770007;
// R-reg to R-reg to sysreg to Reg: no stall
R3 = R0;
ASTAT = R3;
R6 = ASTAT;
R4 = R1;
RETS = R4;
R7 = RETS;
CHECKREG r0, 0x00000030;
CHECKREG r1, 0x00000031;
CHECKREG r2, 0x00000003;
CHECKREG r3, 0x00000030;
CHECKREG r4, 0x00000031;
CHECKREG r5, 0x00550005;
CHECKREG r6, 0x00000030;
CHECKREG r7, 0x00000031;
pass
|
tactcomplabs/xbgas-binutils-gdb | 11,110 | sim/testsuite/bfin/se_loop_kill_01.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_01/se_loop_kill_01.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
P2 = 0x0200 (Z);
P2.H = 0x00F0;
[ -- SP ] = P0;
[ -- SP ] = P0;
SSYNC;
LD32_LABEL(r0, l0t);
LD32_LABEL(r1, l0b);
[ -- SP ] = R0;
[ -- SP ] = R1;
SSYNC;
LB0 = [sp++];
EXCPT 0x5; // Will kill mv2lc in EX3
LC0 = P0;
LT0 = [sp++];
l0t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l0b:R2 += 2;
LD32_LABEL(r0, l2t);
LD32_LABEL(r1, l2b);
LT0 = r0;
LB0 = r1;
EXCPT 0x5; // Will kill mv2lc in EX3 when stalled
LC0 = [ SP ++ ];
l2t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l2b:R2 += 2;
LD32_LABEL(r0, l1t);
LD32_LABEL(r1, l1b);
LT1 = r0;
LB1 = r1;
EXCPT 0x5; // Will kill mv2lc in EX3 when stalled
LC1 = [ SP ++ ];
l1t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l1b:R2 += 2;
LD32_LABEL(r0, l3t);
LD32_LABEL(r1, l3b);
LT1 = r0;
LB1 = r1;
EXCPT 0x5; // Will kill mv2lc in EX3
NOP;
LC1 = P0;
l3t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l3b:R2 += 2;
EXCPT 0x6; // Will kill Lsetup in EX2
NOP;
NOP;
LSETUP ( l1e , l1e ) LC0 = P1;
l1e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX2
NOP;
NOP;
LSETUP ( m1e , m1e ) LC1 = P1;
m1e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1
NOP;
NOP;
NOP;
LSETUP ( l2e , l2e ) LC0 = P1;
l2e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1
NOP;
NOP;
NOP;
LSETUP ( m2e , m2e ) LC1 = P1;
m2e:R7 += 1;
NOP;
NOP;
NOP;
EXCPT 0x6; // Will kill Lsetup in EX2 when stalled
R0 = [ P2 ++ ];
LSETUP ( l3e , l3e ) LC0 = P1;
l3e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX2 when stalled
R0 = [ P2 ++ ];
LSETUP ( m3e , m3e ) LC1 = P1;
m3e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1 when stalled
R0 = [ P2 ++ ];
NOP;
LSETUP ( l4e , l4e ) LC0 = P1;
l4e:R7 += 1;
EXCPT 0x6; // Will kill Lsetup in EX1 when stalled
R0 = [ P2 ++ ];
NOP;
LSETUP ( m4e , m4e ) LC1 = P1;
m4e:R7 += 1;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_0x00F00200,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 4,049 | sim/testsuite/bfin/random_0034.S | # Verify sign extension behavior with simultaneous acc additions, and
# verify that no ASTAT bits get changed as a result
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
dmm32 A0.w, 0x589145b7;
dmm32 A0.x, 0xffffffee;
dmm32 A1.w, 0x0b247b05;
dmm32 A1.x, 0x0000005a;
imm32 R3, 0x1e414332;
imm32 R4, 0x351715b7;
R3 = A1.L + A1.H, R4 = A0.L + A0.H;
checkreg R3, 0x00008629;
checkreg R4, 0x00009e48;
checkreg ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
dmm32 ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 A0.w, 0xb2c58001;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xe999dc28;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0xe58d5ffa;
imm32 R4, 0x7fff7fff;
R0 = A1.L + A1.H, R4 = A0.L + A0.H;
checkreg R0, 0xffffc5c1;
checkreg R4, 0xffff32c6;
checkreg ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 A0.w, 0xeff48350;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0x5a3f623a;
dmm32 A1.x, 0xffffffff;
imm32 R4, 0xffff152f;
imm32 R6, 0xdd13218a;
R4 = A1.L + A1.H, R6 = A0.L + A0.H;
checkreg R4, 0x0000bc79;
checkreg R6, 0xffff7344;
checkreg ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC);
dmm32 ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
dmm32 A0.w, 0x6da679bb;
dmm32 A0.x, 0xffffff96;
dmm32 A1.w, 0x1f5fb024;
dmm32 A1.x, 0x00000000;
imm32 R3, 0x3ebf8000;
imm32 R6, 0x025f2e8c;
R6 = A1.L + A1.H, R3 = A0.L + A0.H;
checkreg R3, 0x0000e761;
checkreg R6, 0xffffcf83;
checkreg ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
dmm32 ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ);
dmm32 A0.w, 0x59abaa84;
dmm32 A0.x, 0xffffffe1;
dmm32 A1.w, 0x71541efe;
dmm32 A1.x, 0x00000009;
imm32 R0, 0x2c41e797;
imm32 R5, 0x7bfa5e8a;
R0 = A1.L + A1.H, R5 = A0.L + A0.H;
checkreg R0, 0x00009052;
checkreg R5, 0x0000042f;
checkreg ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ);
dmm32 ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN);
dmm32 A0.w, 0xffffffff;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0xc49ca8db;
dmm32 A1.x, 0xffffffff;
imm32 R3, 0x0f62ffff;
imm32 R4, 0x09505188;
R4 = A1.L + A1.H, R3 = A0.L + A0.H;
checkreg R3, 0xfffffffe;
checkreg R4, 0xffff6d77;
checkreg ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN);
dmm32 ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ);
dmm32 A0.w, 0xd827823e;
dmm32 A0.x, 0xffffffff;
dmm32 A1.w, 0x303d11ba;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x80007fff;
imm32 R6, 0xffc4feb3;
R6 = A1.L + A1.H, R1 = A0.L + A0.H;
checkreg R1, 0xffff5a65;
checkreg R6, 0x000041f7;
checkreg ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ);
dmm32 ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN);
dmm32 A0.w, 0x97049850;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0xffffa014;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0x04828378;
imm32 R5, 0x3d9effff;
R0 = A1.L + A1.H, R5 = A0.L + A0.H;
checkreg R0, 0xffffa013;
checkreg R5, 0xffff2f54;
checkreg ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN);
dmm32 ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ);
dmm32 A0.w, 0xac43c455;
dmm32 A0.x, 0x00000000;
dmm32 A1.w, 0x03de6f39;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x5bbfd2d1;
imm32 R3, 0x22425ebc;
R3 = A1.L + A1.H, R0 = A0.L + A0.H;
checkreg R0, 0xffff7098;
checkreg R3, 0x00007317;
checkreg ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ);
dmm32 ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
dmm32 A0.w, 0xb63ac8f5;
dmm32 A0.x, 0xffffffe0;
dmm32 A1.w, 0x358b94e8;
dmm32 A1.x, 0x00000000;
imm32 R1, 0x80007fff;
imm32 R6, 0x4f4a8883;
R6 = A1.L + A1.H, R1 = A0.L + A0.H;
checkreg R1, 0xffff7f2f;
checkreg R6, 0xffffca73;
checkreg ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,164 | sim/testsuite/bfin/c_dsp32mac_pair_a1_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_is/c_dsp32mac_pair_a1_is.dsp
// Spec Reference: dsp32mac pair a1 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x89bcfec7;
imm32 r2, 0xa8945679;
imm32 r3, 0x00890007;
imm32 r4, 0xefb89569;
imm32 r5, 0x1235890b;
imm32 r6, 0x000c089d;
imm32 r7, 0x678e0089;
R7 = ( A1 += R5.L * R0.L ), A0 = R5.L * R0.L (ISS2);
P1 = A1.w;
R1 = ( A1 = R4.L * R3.L ), A0 = R4.H * R3.L (ISS2);
P2 = A1.w;
R3 = ( A1 = R7.L * R2.L ), A0 += R7.H * R2.H (ISS2);
P3 = A1.w;
R5 = ( A1 += R6.L * R1.L ), A0 += R6.L * R1.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x93545ABD;
CHECKREG r1, 0xFFFA2BBE;
CHECKREG r2, 0xA8945679;
CHECKREG r3, 0x0F06AE9C;
CHECKREG r4, 0xEFB89569;
CHECKREG r5, 0x11F835A8;
CHECKREG r6, 0x000C089D;
CHECKREG r7, 0xABAC163E;
CHECKREG p1, 0xD5D60B1F;
CHECKREG p2, 0xFFFD15DF;
CHECKREG p3, 0x0783574E;
CHECKREG p4, 0x08FC1AD4;
imm32 r0, 0x98464abd;
imm32 r1, 0xa1b5f4c7;
imm32 r2, 0xa1146649;
imm32 r3, 0x00010805;
imm32 r4, 0xefbc1599;
imm32 r5, 0x12350100;
imm32 r6, 0x200c001d;
imm32 r7, 0x628e0001;
R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (ISS2);
P1 = A1.w;
R1 = ( A1 -= R5.L * R3.H ), A0 = R5.H * R3.L (ISS2);
P2 = A1.w;
R3 = ( A1 -= R4.L * R2.H ), A0 += R4.H * R2.H (ISS2);
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x98464ABD;
CHECKREG r1, 0x2B2A1FC8;
CHECKREG r2, 0xA1146649;
CHECKREG r3, 0x2B13CB9C;
CHECKREG r4, 0xEFBC1599;
CHECKREG r5, 0x1B10627C;
CHECKREG r6, 0x200C001D;
CHECKREG r7, 0x628E0001;
CHECKREG p1, 0x0D88313E;
CHECKREG p2, 0x0D87CEC2;
CHECKREG p3, 0x1589E5CE;
CHECKREG p4, 0x15950FE4;
imm32 r0, 0x713a459d;
imm32 r1, 0xabd6aec7;
imm32 r2, 0x7a145a79;
imm32 r3, 0x08a100a7;
imm32 r4, 0xef9a156a;
imm32 r5, 0x1225a10b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0a61;
R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (ISS2);
P1 = A1.w;
R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L (ISS2);
P2 = A1.w;
R1 = ( A1 = R7.H * R5.L ), A0 += R7.H * R5.H (ISS2);
P3 = A1.w;
R5 = ( A1 += R6.H * R4.L ), A0 += R6.L * R4.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x713A459D;
CHECKREG r1, 0xFE604820;
CHECKREG r2, 0x7A145A79;
CHECKREG r3, 0x08A100A7;
CHECKREG r4, 0xEF9A156A;
CHECKREG r5, 0xFE60C89C;
CHECKREG r6, 0x0003401D;
CHECKREG r7, 0xFCC4FA2C;
CHECKREG p1, 0xFEB22022;
CHECKREG p2, 0xFE627D16;
CHECKREG p3, 0xFF302410;
CHECKREG p4, 0xFF30644E;
imm32 r0, 0x773489bd;
imm32 r1, 0x917cfec7;
imm32 r2, 0xa9177679;
imm32 r3, 0xd0910777;
imm32 r4, 0xedb91579;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d077999;
imm32 r7, 0x677e0709;
R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (ISS2);
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ), A0 = R2.H * R1.L (ISS2);
P2 = A1.w;
R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (ISS2);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x773489BD;
CHECKREG r1, 0x0F5908A6;
CHECKREG r2, 0xA9177679;
CHECKREG r3, 0xF59443FE;
CHECKREG r4, 0xEDB91579;
CHECKREG r5, 0x953314CE;
CHECKREG r6, 0x0D077999;
CHECKREG r7, 0x9356DEEC;
CHECKREG p1, 0x07AC8453;
CHECKREG p2, 0xFACA21FF;
CHECKREG p3, 0xCA998A67;
CHECKREG p4, 0xC9AB6F76;
imm32 r0, 0x83547abd;
imm32 r1, 0x88bc8ec7;
imm32 r2, 0xa8895679;
imm32 r3, 0x00080007;
imm32 r4, 0xe6b86569;
imm32 r5, 0x1A35860b;
imm32 r6, 0x000c896d;
imm32 r7, 0x67Be0096;
R7 = ( A1 += R1.L * R0.L ) (ISS2);
P1 = A1.w;
R1 = ( A1 = R2.H * R3.L ) (ISS2);
P2 = A1.w;
R3 = ( A1 -= R7.L * R4.H ) (ISS2);
P3 = A1.w;
R5 = ( A1 += R6.H * R5.H ) (ISS2);
P4 = A1.w;
CHECKREG r0, 0x83547ABD;
CHECKREG r1, 0xFFFB377E;
CHECKREG r2, 0xA8895679;
CHECKREG r3, 0xFFFB377E;
CHECKREG r4, 0xE6B86569;
CHECKREG r5, 0xFFFDAC76;
CHECKREG r6, 0x000C896D;
CHECKREG r7, 0x80000000;
CHECKREG p1, 0x9362AE61;
CHECKREG p2, 0xFFFD9BBF;
CHECKREG p3, 0xFFFD9BBF;
CHECKREG p4, 0xFFFED63B;
imm32 r0, 0x9aa64abd;
imm32 r1, 0xa1baf4c7;
imm32 r2, 0xb114a649;
imm32 r3, 0x0b010005;
imm32 r4, 0xefbcdb69;
imm32 r5, 0x123501bb;
imm32 r6, 0x000c0d1b;
imm32 r7, 0x678e0d01;
R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (ISS2);
P1 = A1.w;
R1 = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (ISS2);
P2 = A1.w;
R3 = ( A1 = R4.L * R5.H ) (M), A0 += R4.H * R5.H (ISS2);
P3 = A1.w;
R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0x9AA64ABD;
CHECKREG r1, 0xC54D5630;
CHECKREG r2, 0xB114A649;
CHECKREG r3, 0xBAB3123C;
CHECKREG r4, 0xEFBCDB69;
CHECKREG r5, 0xF26E8A8A;
CHECKREG r6, 0x000C0D1B;
CHECKREG r7, 0x678E0D01;
CHECKREG p1, 0xF9374545;
CHECKREG p2, 0xFD127BFC;
CHECKREG p3, 0xDD59891E;
CHECKREG p4, 0xE2A6AB18;
imm32 r0, 0xd136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0xdd010007;
imm32 r4, 0xeddc1569;
imm32 r5, 0x122d010b;
imm32 r6, 0x00e3d01d;
imm32 r7, 0x678e0d61;
R5 = A1 , A0 -= R1.L * R0.L (ISS2);
P1 = A1.w;
R7 = A1 , A0 = R2.H * R3.L (ISS2);
P2 = A1.w;
R1 = A1 , A0 += R4.H * R5.H (ISS2);
P3 = A1.w;
R5 = A1 , A0 += R6.L * R7.H (ISS2);
P4 = A1.w;
CHECKREG r0, 0xD136459D;
CHECKREG r1, 0xC54D5630;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0xDD010007;
CHECKREG r4, 0xEDDC1569;
CHECKREG r5, 0xC54D5630;
CHECKREG r6, 0x00E3D01D;
CHECKREG r7, 0xC54D5630;
CHECKREG p1, 0xE2A6AB18;
CHECKREG p2, 0xE2A6AB18;
CHECKREG p3, 0xE2A6AB18;
CHECKREG p4, 0xE2A6AB18;
imm32 r0, 0x125489bd;
imm32 r1, 0x91b5fec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910507;
imm32 r4, 0x34567859;
imm32 r5, 0xd2359105;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ) (M,ISS2);
P1 = A1.w;
R3 = ( A1 = R2.H * R1.H ) (M,ISS2);
P2 = A1.w;
R5 = ( A1 -= R7.H * R0.H ) (M,ISS2);
P3 = A1.w;
R7 = ( A1 += R4.H * R6.H ) (M,ISS2);
P4 = A1.w;
CHECKREG r0, 0x125489BD;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0xA9145679;
CHECKREG r3, 0xA9140000;
CHECKREG r4, 0x34567859;
CHECKREG r5, 0x9A349E50;
CHECKREG r6, 0x0D0C0999;
CHECKREG r7, 0x9F8A4260;
CHECKREG p1, 0xBD57CB1D;
CHECKREG p2, 0xD48A0000;
CHECKREG p3, 0xCD1A4F28;
CHECKREG p4, 0xCFC52130;
pass
|
tactcomplabs/xbgas-binutils-gdb | 12,214 | sim/testsuite/bfin/se_cc2stat_haz.S | //Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp
// Description:
// Verify CC hazards under the following condition:
//
// (1a) cc2stat (that modifies CC) followed by that uses CC
// (1b) same as (1a) but kill cc2stat instruction in WB
//
// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted)
// (2b) same as (2a) but kill cc2stat instruction in WB
//
// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted)
// (3b) same as (3a) but kill cc2stat instruction in WB
//
// (4a) cc2stat (that modifies CC) followed by testset
// (4b) same as (4a) but kill cc2stat instruction in WB
//
// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC
// (5b) same as (5a) but kill cc2stat instruction in WB
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
// ----------------------------------------------------------------
// Include Files
// ----------------------------------------------------------------
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
// ----------------------------------------------------------------
// Defines
// ----------------------------------------------------------------
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_1 //
#endif
// ----------------------------------------------------------------
// Reset ISR
// - set the processor operating modes
// - initialize registers
// - etc ...
// ----------------------------------------------------------------
RST_ISR:
// Initialize data registers
//INIT_R_REGS(0);
R7 = 0;
R6 = 0;
R5 = 0;
R4 = 0;
R3 = 0;
R2 = 0;
R1 = 0;
R0 = 0;
// Initialize pointer registers
INIT_P_REGS(0);
// Initialize address registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the address of the checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Inhibit events during MMR writes
CLI R1;
// Setup user stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup kernel stack
LD32_LABEL(sp, KSTACK);
// Setup frame pointer
FP = SP;
// Setup event vector table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // EVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Set the EVT_OVERRIDE MMR
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
// Disable L1 data cache
WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0);
// Mask interrupts (*)
R1 = -1;
// Wait for MMR writes to finish
CSYNC;
// Re-enable events
STI R1;
// Reset accumulator registers
A0 = 0;
A1 = 0;
// Reset loop counters to deterministic values
R0 = 0 (Z);
LT0 = R0;
LB0 = R0;
LC0 = R0;
LT1 = R0;
LB1 = R0;
LC1 = R0;
// Reset other internal regs
ASTAT = R0;
SYSCFG = R0;
RETS = R0;
// Setup the test to run in USER mode
LD32_LABEL(r0, USER_CODE);
RETI = R0;
// Setup the test to run in SUPERVISOR mode
// Comment the following line for a USER mode test
JUMP.S SUPERVISOR_CODE;
RTI;
SUPERVISOR_CODE:
// Load IVG15 general handler (Int15) with MAIN_CODE
LD32_LABEL(p1, MAIN_CODE);
LD32(p0, EVT15);
CLI R1;
[ P0 ] = P1;
CSYNC;
STI R1;
// Take Int15 which branch to MAIN_CODE after RTI
RAISE 15;
RTI;
USER_CODE:
// Setup the stack pointer and the frame pointer
LD32_LABEL(sp, USTACK);
FP = SP;
JUMP.S MAIN_CODE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// ISR Table
// ----------------------------------------------------------------
// ----------------------------------------------------------------
// EMU ISR
// ----------------------------------------------------------------
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// NMI ISR
// ----------------------------------------------------------------
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// EXC ISR
// ----------------------------------------------------------------
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// HWE ISR
// ----------------------------------------------------------------
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// TMR ISR
// ----------------------------------------------------------------
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV7 ISR
// ----------------------------------------------------------------
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV8 ISR
// ----------------------------------------------------------------
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV9 ISR
// ----------------------------------------------------------------
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV10 ISR
// ----------------------------------------------------------------
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV11 ISR
// ----------------------------------------------------------------
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV12 ISR
// ----------------------------------------------------------------
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV13 ISR
// ----------------------------------------------------------------
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV14 ISR
// ----------------------------------------------------------------
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// IGV15 ISR
// ----------------------------------------------------------------
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
// ----------------------------------------------------------------
// Main Code
// ----------------------------------------------------------------
MAIN_CODE:
// Enable interrupts in SUPERVISOR mode
// Comment the following line for a USER mode test
[ -- SP ] = RETI;
// Start of the program code
R0 = 0;
R1 = 1;
R2 = 2;
// Verify CC hazards under the following condition:
//
// (1a) cc2stat (that modifies CC) followed by that uses CC
A0 = 0;
A1 = R1;
CC = R0 < R2;
CC = AV0;
A0 = BXORSHIFT( A0 , A1, CC );
R7 = CC; CHECKREG(R7, 0);
R6 = A0; CHECKREG(R6, 0);
R6 = A0.X; CHECKREG(R6, 0);
R7 = A1; CHECKREG(R7, 1);
R7 = A1.X; CHECKREG(R7, 0);
// (1b) same as (1a) but kill cc2stat instruction in WB
A0 = R1;
A1 = R1;
CC = R0 < R2;
EXCPT 3;
CC = AV0;
A0 = BXORSHIFT( A0 , A1, CC );
R7 = CC; CHECKREG(R7, 0);
R6 = A0; CHECKREG(R6, 3);
R6 = A0.X; CHECKREG(R6, 0);
R7 = A1; CHECKREG(R7, 1);
R7 = A1.X; CHECKREG(R7, 0);
// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted)
R3 = 0;
A0 = 0;
A1 = R1;
CC = R0 < R2;
CC = AV0;
IF !CC JUMP INC_R3_TO_10 (BP);
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
INC_R3_TO_10:
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
// (2b) same as (2a) but kill cc2stat instruction in WB
A0 = 0;
A1 = R1;
CC = R0 < R2;
EXCPT 3;
CC = AV0;
IF !CC JUMP INC_R3_TO_20 (BP);
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
INC_R3_TO_20:
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
R3 += 1;
// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted)
A0 = 0;
A1 = R1;
CC = R0 < R2;
CC = AV0;
IF CC JUMP INC_R3_TO_20 (BP);
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
// (3b) same as (3a) but kill cc2stat instruction in WB
A0 = 0;
A1 = R1;
CC = R0 < R2;
EXCPT 3;
CC = AV0;
IF CC JUMP INC_R3_TO_20 (BP);
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
R3 += 2;
CHECKREG(r3, 60);
dbg_pass;
// (4a) cc2stat (that modifies CC) followed by testset
LD32(p0, DATA_ADDR_3); //LD32(p0, 0xff000000);
LD32(p1, DATA_ADDR_2); //LD32(p1, 0xffe00000);
[ P0 ] = R0;
A0 = 0;
A1 = R1;
CC = R0 < R2;
CC = AV0;
QUERY_0:
TESTSET ( P0 );
IF !CC JUMP QUERY_0;
[ P0 ] = R1;
CHECKMEM32(DATA_ADDR_3, 1); //CHECKMEM32(0xff000000, 1);
[ P0 ] = R0;
CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0);
// (4b) same as (4a) but kill cc2stat instruction in WB
A0 = 0;
A1 = R1;
CC = R0 < R2;
EXCPT 3;
CC = AV0;
QUERY_1:
TESTSET ( P0 );
IF !CC JUMP QUERY_1;
[ P0 ] = R2;
CHECKMEM32(DATA_ADDR_3, 2); //CHECKMEM32(0xff000000, 2);
[ P0 ] = R0;
CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0);
// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC
A0 = 0;
A1 = R1;
CC = R0 < R2;
CC = AV0;
CC = P0 < P1;
// (5b) same as (5a) but kill cc2stat instruction in WB
A0 = 0;
A1 = R1;
CC = R0 < R2;
EXCPT 3;
CC = AV0;
CC = P0 < P1;
END:
dbg_pass;
// ----------------------------------------------------------------
// Data Segment
// - define kernel and user stacks
// ----------------------------------------------------------------
.data
DATA:
.space (STACKSIZE);
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 1,775 | sim/testsuite/bfin/c_regmv_pr_pr.s | //Original:/testcases/core/c_regmv_pr_pr/c_regmv_pr_pr.dsp
// Spec Reference: regmv preg-to-preg
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P1;
P2 = P1;
P4 = P1;
P5 = P1;
FP = P1;
CHECKREG p1, 0x20021003;
CHECKREG p2, 0x20021003;
CHECKREG p4, 0x20021003;
CHECKREG p5, 0x20021003;
CHECKREG fp, 0x20021003;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P2;
P2 = P2;
P4 = P2;
P5 = P2;
FP = P2;
CHECKREG p1, 0x20041005;
CHECKREG p2, 0x20041005;
CHECKREG p4, 0x20041005;
CHECKREG p5, 0x20041005;
CHECKREG fp, 0x20041005;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P4;
P2 = P4;
P4 = P4;
P5 = P4;
FP = P4;
CHECKREG p1, 0x20081009;
CHECKREG p2, 0x20081009;
CHECKREG p4, 0x20081009;
CHECKREG p5, 0x20081009;
CHECKREG fp, 0x20081009;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = P5;
P2 = P5;
P4 = P5;
P5 = P5;
FP = P5;
CHECKREG p1, 0x200a100b;
CHECKREG p2, 0x200a100b;
CHECKREG p4, 0x200a100b;
CHECKREG p5, 0x200a100b;
CHECKREG fp, 0x200a100b;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 fp, 0x200e100f;
P1 = FP;
P2 = FP;
P4 = FP;
P5 = FP;
FP = FP;
CHECKREG p1, 0x200e100f;
CHECKREG p2, 0x200e100f;
CHECKREG p4, 0x200e100f;
CHECKREG p5, 0x200e100f;
CHECKREG fp, 0x200e100f;
pass
|
tactcomplabs/xbgas-binutils-gdb | 11,635 | sim/testsuite/bfin/se_popkill.S | //Original:/proj/frio/dv/testcases/seq/se_popkill/se_popkill.dsp
// Description: Kill pops to sysregs in WB
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_RST_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_RST_2 //
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
/////////////////////////////////////////////////////////////////////////////
//////////////////////// CPLB Setup /////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Setup CPLB for Data Memory starting at 0x00F0_0000;
WR_MMR(DCPLB_DATA0, DATA_ADDR_1, p0, r0);
//WR_MMR(DCPLB_DATA0, 0x00031005, p0, r0); // Page Size = 4MB
// CPLB_L1_CHLB = 1
// CPLB_USER_RD = 1
// CPLB_VALID = 1
//
// Setup CPLB Address to point to 0x00F0_0000
WR_MMR(DCPLB_ADDR0, DATA_ADDR_2, p0, r0);
//WR_MMR(DCPLB_ADDR0, 0x00F00000, p0, r0);
// Enable CPLB's
WR_MMR(DMEM_CONTROL, DATA_ADDR_3, p0, r0);
//WR_MMR(DMEM_CONTROL, 0x0000000f, p0, r0); // ENDM = 1
// ENDCPLB = 1
// DMC = 11
// Sync it!
CSYNC;
// Return to Supervisor Code
RAISE 15;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
R3 = SEQSTAT;
R4 = RETX;
R4 += 8;
RETX = R4;
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
NOP;
ASTAT = R7;
RETS = R7;
LC0 = R7;
LB0 = R7;
LT0 = R7;
LC1 = R7;
LB1 = R7;
LT1 = R7;
CYCLES = R7;
CYCLES2 = R7;
SYSCFG = R7;
RETN = R7;
RETX = R7;
RETE = R7;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
EXCPT 1;
ASTAT = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 2;
RETS = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 3;
LC0 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 4;
LT0 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 5;
LB0 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 6;
LC1 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 7;
LB1 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 8;
LT1 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 9;
CYCLES = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 10;
CYCLES2 = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 11;
SYSCFG = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 12;
RETI = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 13;
RETX = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 14;
RETN = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
EXCPT 15;
RETE = [ SP ++ ];
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Define Kernal Stack
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
.section MEM_DATA_ADDR_2 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
.dd 0xdeadbeef;
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 8,524 | sim/testsuite/bfin/c_regmv_dr_imlb.s | //Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp
// Spec Reference: regmv dreg-to-imlb
# mach: bfin
.include "testutils.inc"
start
// check DR-reg to imlb-reg move
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R0;
I1 = R0;
I2 = R0;
I3 = R0;
M0 = R0;
M1 = R0;
M2 = R0;
M3 = R0;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R1;
I1 = R1;
I2 = R1;
I3 = R1;
M0 = R1;
M1 = R1;
M2 = R1;
M3 = R1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00020003;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00020003;
CHECKREG r4, 0x00020003;
CHECKREG r5, 0x00020003;
CHECKREG r6, 0x00020003;
CHECKREG r7, 0x00020003;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R2;
I1 = R2;
I2 = R2;
I3 = R2;
M0 = R2;
M1 = R2;
M2 = R2;
M3 = R2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00040005;
CHECKREG r1, 0x00040005;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00040005;
CHECKREG r4, 0x00040005;
CHECKREG r5, 0x00040005;
CHECKREG r6, 0x00040005;
CHECKREG r7, 0x00040005;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R3;
I1 = R3;
I2 = R3;
I3 = R3;
M0 = R3;
M1 = R3;
M2 = R3;
M3 = R3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00060007;
CHECKREG r1, 0x00060007;
CHECKREG r2, 0x00060007;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00060007;
CHECKREG r5, 0x00060007;
CHECKREG r6, 0x00060007;
CHECKREG r7, 0x00060007;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R4;
I1 = R4;
I2 = R4;
I3 = R4;
M0 = R4;
M1 = R4;
M2 = R4;
M3 = R4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00080009;
CHECKREG r1, 0x00080009;
CHECKREG r2, 0x00080009;
CHECKREG r3, 0x00080009;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x00080009;
CHECKREG r6, 0x00080009;
CHECKREG r7, 0x00080009;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R5;
I1 = R5;
I2 = R5;
I3 = R5;
M0 = R5;
M1 = R5;
M2 = R5;
M3 = R5;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000a000b;
CHECKREG r1, 0x000a000b;
CHECKREG r2, 0x000a000b;
CHECKREG r3, 0x000a000b;
CHECKREG r4, 0x000a000b;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000a000b;
CHECKREG r7, 0x000a000b;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R6;
I1 = R6;
I2 = R6;
I3 = R6;
M0 = R6;
M1 = R6;
M2 = R6;
M3 = R6;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000c000d;
CHECKREG r1, 0x000c000d;
CHECKREG r2, 0x000c000d;
CHECKREG r3, 0x000c000d;
CHECKREG r4, 0x000c000d;
CHECKREG r5, 0x000c000d;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000c000d;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
I0 = R7;
I1 = R7;
I2 = R7;
I3 = R7;
M0 = R7;
M1 = R7;
M2 = R7;
M3 = R7;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000e000f;
CHECKREG r1, 0x000e000f;
CHECKREG r2, 0x000e000f;
CHECKREG r3, 0x000e000f;
CHECKREG r4, 0x000e000f;
CHECKREG r5, 0x000e000f;
CHECKREG r6, 0x000e000f;
CHECKREG r7, 0x000e000f;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R0;
L1 = R0;
L2 = R0;
L3 = R0;
B0 = R0;
B1 = R0;
B2 = R0;
B3 = R0;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R1;
L1 = R1;
L2 = R1;
L3 = R1;
B0 = R1;
B1 = R1;
B2 = R1;
B3 = R1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00020003;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00020003;
CHECKREG r4, 0x00020003;
CHECKREG r5, 0x00020003;
CHECKREG r6, 0x00020003;
CHECKREG r7, 0x00020003;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R2;
L1 = R2;
L2 = R2;
L3 = R2;
B0 = R2;
B1 = R2;
B2 = R2;
B3 = R2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00040005;
CHECKREG r1, 0x00040005;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00040005;
CHECKREG r4, 0x00040005;
CHECKREG r5, 0x00040005;
CHECKREG r6, 0x00040005;
CHECKREG r7, 0x00040005;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R3;
L1 = R3;
L2 = R3;
L3 = R3;
B0 = R3;
B1 = R3;
B2 = R3;
B3 = R3;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00060007;
CHECKREG r1, 0x00060007;
CHECKREG r2, 0x00060007;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00060007;
CHECKREG r5, 0x00060007;
CHECKREG r6, 0x00060007;
CHECKREG r7, 0x00060007;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R4;
L1 = R4;
L2 = R4;
L3 = R4;
B0 = R4;
B1 = R4;
B2 = R4;
B3 = R4;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00080009;
CHECKREG r1, 0x00080009;
CHECKREG r2, 0x00080009;
CHECKREG r3, 0x00080009;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x00080009;
CHECKREG r6, 0x00080009;
CHECKREG r7, 0x00080009;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R5;
L1 = R5;
L2 = R5;
L3 = R5;
B0 = R5;
B1 = R5;
B2 = R5;
B3 = R5;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000a000b;
CHECKREG r1, 0x000a000b;
CHECKREG r2, 0x000a000b;
CHECKREG r3, 0x000a000b;
CHECKREG r4, 0x000a000b;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000a000b;
CHECKREG r7, 0x000a000b;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R6;
L1 = R6;
L2 = R6;
L3 = R6;
B0 = R6;
B1 = R6;
B2 = R6;
B3 = R6;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000c000d;
CHECKREG r1, 0x000c000d;
CHECKREG r2, 0x000c000d;
CHECKREG r3, 0x000c000d;
CHECKREG r4, 0x000c000d;
CHECKREG r5, 0x000c000d;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000c000d;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
L0 = R7;
L1 = R7;
L2 = R7;
L3 = R7;
B0 = R7;
B1 = R7;
B2 = R7;
B3 = R7;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000e000f;
CHECKREG r1, 0x000e000f;
CHECKREG r2, 0x000e000f;
CHECKREG r3, 0x000e000f;
CHECKREG r4, 0x000e000f;
CHECKREG r5, 0x000e000f;
CHECKREG r6, 0x000e000f;
CHECKREG r7, 0x000e000f;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,518 | sim/testsuite/bfin/c_seq_ex2_raise_mmrj_mvpop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex2_raise_mmrj_mvpop/c_seq_ex2_raise_mmrj_mvpop.dsp
// Spec Reference: sequencer stage ex2 (raise+ mmr + jump+ regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
LD32(r0, 0x55552345);
RAISE 2; // RTN
[ P1 ] = R0;
JUMP.S LABEL1;
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
CSYNC;
// wrt-rd EVT5 = 0xFFE02034
LD32(p1, 0xFFE02034); // wrt-rd EVT13 = 0xFFE02034
RAISE 6; // RTI
R0 = [ P1 ];
JUMP.S LABEL2;
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
CHECKREG(r0, 0x55552345);
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x55552345);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// wrt-rd EVT13 = 0xFFE02034
LD32(p1, 0xFFE02034);
RAISE 8; // RTI
R0 = [ P1 ];
JUMP.S LABEL3;
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
CHECKREG(r0, 0x55552345);
RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 2,470 | sim/testsuite/bfin/dsp_a4.s | /* ALU test program.
* Test instructions
* r3= + (r0,r0);
* r3= + (r0,r0) s;
* r3= - (r0,r0);
* r3= - (r0,r0) s;
*/
# mach: bfin
.include "testutils.inc"
start
// overflow positive
R0.L = 0xffff;
R0.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0xffff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative
R0.L = 0x0000;
R0.H = 0x8000;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// zero
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3 = R1 + R0 (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive
R0.L = 0;
R0.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (S);
DBGA ( R3.L , 0xffff );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative
R0.L = 0;
R0.H = 0x8000;
R7 = 0;
ASTAT = R7;
R3 = R0 + R0 (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with subtraction
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = 0;
ASTAT = R7;
R3 = R1 - R0 (S);
DBGA ( R3.L , 0xffff );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative with subtraction
R0.L = 0x1;
R0.H = 0x0;
R1.L = 0x0000;
R1.H = 0x8000;
R7 = 0;
ASTAT = R7;
R3 = R1 - R0 (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,470 | sim/testsuite/bfin/m9.s | // Test extraction from accumulators:
// ROUND/TRUNCATE in SIGNED FRACTIONAL mode
// test ops: "+="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x7ffef000
// load r1=0x7ffff000
// load r2=0x00008000
// load r3=0x00018000
// load r4=0x0000007f
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// round
// 0x007ffef00 -> 0x7fff
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// round with ovflw
// 0x007ffff00 -> 0x7fff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// trunc
// 0x007ffef00 -> 0x7ffe
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R5.H = A1, R5.L = A0 (T);
DBGA ( R5.L , 0x7ffe );
DBGA ( R5.H , 0x7ffe );
// round with ovflw
// 0x7f7ffff00 -> 0x7fff
A1 = A0 = 0;
A1.w = R1;
A1.x = R4.L;
A0.w = R1;
A0.x = R4.L;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x7fff );
DBGA ( R5.H , 0x7fff );
// round, nearest even is zero
// 0x0000008000 -> 0x0000
A1 = A0 = 0;
A1.w = R2;
A0.w = R2;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x0 );
DBGA ( R5.H , 0x0 );
// round, nearest even is 2
// 0x00000018000 -> 0x0002
A1 = A0 = 0;
A1.w = R3;
A0.w = R3;
R5.H = A1, R5.L = A0;
DBGA ( R5.L , 0x2 );
DBGA ( R5.H , 0x2 );
pass
.data
data0:
.dw 0xf000
.dw 0x7ffe
.dw 0xf000
.dw 0x7ffe
.dw 0x8000
.dw 0x0000
.dw 0x8000
.dw 0x0001
.dw 0x007f
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 7,235 | sim/testsuite/bfin/c_seq_ex1_brcc_mv_pop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp
// Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
R0 = 0;
ASTAT = R0;
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
[ -- SP ] = ( R7:0 );
// RAISE 2; // RTN
IF !CC JUMP LABEL1 (BP);
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
LABEL1:
// RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:0 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
// RAISE 6; // RTI
IF !CC JUMP LABEL2 (BP);
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:0 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
LABEL2:
// RAISE 7; // RTI
IF CC JUMP LABEL4; // SHOULD NOT EXECUTE
P4 = R4;
R5 = P4;
( R7:0 ) = [ SP ++ ];
LABEL4:
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000003);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
// RAISE 8; // RTI
IF !CC JUMP LABEL3 (BP);
P1 = R5;
R6 = P1;
( R7:0 ) = [ SP ++ ];
//CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
//CHECKREG(r1, 0x000000b2); // so they cannot appear here
//CHECKREG(r2, 0x000000c3);
//CHECKREG(r3, 0x000000d4);
//CHECKREG(r4, 0x000000e5);
//CHECKREG(r5, 0x000000f6);
//CHECKREG(r6, 0x00000017);
//CHECKREG(r7, 0x00000028);
R0 = 12;
R1 = 13;
R2 = 14;
R3 = 15;
R4 = 16;
R5 = 17;
R6 = 18;
R7 = 19;
LABEL3:
// RAISE 9; // RTI
P2 = R6;
R7 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000003);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000000);
CHECKREG(r3, 0x00000000);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 4,171 | sim/testsuite/bfin/c_alu2op_log_l_sft.s | //Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp
// Spec Reference: alu2op logical left
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
R1 <<= R0;
R2 <<= R0;
R3 <<= R0;
R4 <<= R0;
R5 <<= R0;
R6 <<= R0;
R7 <<= R0;
R4 <<= R0;
R0 <<= R0;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x468ACF12;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x159E26AC;
CHECKREG r5, 0x2CF13578;
CHECKREG r6, 0x4F13579A;
CHECKREG r7, 0x713579BC;
CHECKREG r0, 0x00000002;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 <<= R1;
R2 <<= R1;
R3 <<= R1;
R4 <<= R1;
R5 <<= R1;
R6 <<= R1;
R7 <<= R1;
R1 <<= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 <<= R2;
R1 <<= R2;
R3 <<= R2;
R4 <<= R2;
R5 <<= R2;
R6 <<= R2;
R7 <<= R2;
R2 <<= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 <<= R3;
R1 <<= R3;
R2 <<= R3;
R4 <<= R3;
R5 <<= R3;
R6 <<= R3;
R7 <<= R3;
R3 <<= R3;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 <<= R4;
R2 <<= R4;
R3 <<= R4;
R0 <<= R4;
R5 <<= R4;
R6 <<= R4;
R7 <<= R4;
R4 <<= R4;
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x2B3C0000;
CHECKREG r2, 0xB3C48000;
CHECKREG r3, 0x3C4D0000;
CHECKREG r4, 0x00078000;
CHECKREG r5, 0x4D5E0000;
CHECKREG r6, 0xD5E68000;
CHECKREG r7, 0x5E6F0000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 <<= R5;
R1 <<= R5;
R2 <<= R5;
R3 <<= R5;
R4 <<= R5;
R6 <<= R5;
R7 <<= R5;
R5 <<= R5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 <<= R6;
R1 <<= R6;
R2 <<= R6;
R3 <<= R6;
R4 <<= R6;
R5 <<= R6;
R7 <<= R6;
R6 <<= R6;
CHECKREG r0, 0x02000000;
CHECKREG r1, 0x78000000;
CHECKREG r2, 0x90000000;
CHECKREG r3, 0x9A000000;
CHECKREG r4, 0xAB000000;
CHECKREG r5, 0xBC000000;
CHECKREG r6, 0x18000000;
CHECKREG r7, 0xDE000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 <<= R7;
R1 <<= R7;
R2 <<= R7;
R3 <<= R7;
R4 <<= R7;
R5 <<= R7;
R6 <<= R7;
R7 <<= R7;
CHECKREG r0, 0x00;
CHECKREG r1, 0x00;
CHECKREG r2, 0x00;
CHECKREG r3, 0x00;
CHECKREG r4, 0x00;
CHECKREG r5, 0x00;
CHECKREG r6, 0x00;
CHECKREG r7, 0x00;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,118 | sim/testsuite/bfin/cir1.s | # Blackfin testcase for circular buffers
# mach: bfin
.include "testutils.inc"
.macro daginit i:req, b:req, l:req, m:req
imm32 I0, \i
imm32 B0, \b
imm32 L0, \l
imm32 M0, \m
.endm
.macro dagcheck newi:req
DBGA ( I0.L, \newi & 0xFFFF );
DBGA ( I0.H, \newi >> 16 );
.endm
.macro dagadd i:req, b:req, l:req, m:req, newi:req
daginit \i, \b, \l, \m
I0 += M0;
dagcheck \newi
.endm
.macro dagsub i:req, b:req, l:req, m:req, newi:req
daginit \i, \b, \l, \m
I0 -= M0;
dagcheck \newi
.endm
.macro dag i:req, b:req, l:req, m:req, addi:req, subi:req
daginit \i, \b, \l, \m
I0 += M0;
dagcheck \addi
imm32 I0, \i
I0 -= M0;
dagcheck \subi
.endm
start
init_l_regs 0
init_i_regs 0
init_b_regs 0
init_m_regs 0
_zero_len:
dag 0, 0, 0, 0, 0, 0
dag 100, 0, 0, 0, 100, 100
dag 100, 0, 0, 11, 111, 89
dag 100, 0xaa00ff00, 0, 0, 100, 100
dag 100, 0xaa00ff00, 0, 11, 111, 89
_zero_base:
dag 0, 0, 100, 10, 10, 90
dag 50, 0, 100, 10, 60, 40
dag 99, 0, 100, 10, 9, 89
dag 50, 0, 100, 50, 0, 0
dag 50, 0, 100, 100, 50, 50
dag 50, 0, 100, 200, 150, -50
dag 50, 0, 100, 2100, 2050, -1950
dag 1000, 0, 100, 0, 900, 1000
dag 1000, 0, 1000, 0, 0, 1000
dag 0xffff1000, 0, 0x1000, 0, 0xffff0000, 0xffff1000
dag 0xaaaa1000, 0, 0xaaa1000, 0, 0xa0000000, 0xaaaa1000
dag 0xaaaa1000, 0, 0xaaa1000, 0x1000, 0xa0001000, 0xaaaa0000
dag 0xffff1000, 0, 0xffff0000, 0xffffff, 0x1000fff, 0xfeff1001
_positive_base:
dag 0, 100, 100, 10, 10, 90
dag 90, 100, 100, 10, 100, 180
dag 90, 100, 100, 2100, 2090, -1910
dag 100, 100, 100, 100, 100, 100
dag 0xfffff000, 0xffffff00, 0x10, 0xffff, 0xefef, 0xfffef011
_large_base_len:
dag 0, 0xffffff00, 0xffffff00, 0x00000100, 0x00000200, 0xfffffe00
dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0x88888887, 0x77777779
dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x4ccccccc, 0x91111111, 0x6eeeeeef
dag 0, 0xaaaaaaaa, 0xbbbbbbbb, 0x00000000, 0x44444445, 0xbbbbbbbb
dag 0, 0xdddddddd, 0x7bbbbbbb, 0xcccccccc, 0xcccccccc, 0xb7777779
dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x4ccccccc, 0x4ccccccc, 0xb3333334
dag 0, 0xbbbbbbbb, 0x7bbbbbbb, 0x00000000, 0x84444445, 0x7bbbbbbb
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,503 | sim/testsuite/bfin/c_dsp32mult_dr_m.s | //Original:/testcases/core/c_dsp32mult_dr_m/c_dsp32mult_dr_m.dsp
// Spec Reference: dsp32mult single dr (mix) MUNOP
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x34235625;
imm32 r1, 0x9f7a5127;
imm32 r2, 0xa3286725;
imm32 r3, 0x00069027;
imm32 r4, 0xb0abc029;
imm32 r5, 0x10acef2b;
imm32 r6, 0xc00c00de;
imm32 r7, 0xd246712f;
R4.L = R0.L * R0.L;
R5.L = R0.L * R1.H;
R6.L = R1.H * R0.L;
R7.L = R1.H * R1.H;
R0.L = R0.L * R0.L;
R1.L = R0.L * R1.H;
R2.L = R1.H * R0.L;
R3.L = R1.H * R1.H;
CHECKREG r0, 0x342339FA;
CHECKREG r1, 0x9F7AD448;
CHECKREG r2, 0xA328D448;
CHECKREG r3, 0x000648CA;
CHECKREG r4, 0xB0AB39FA;
CHECKREG r5, 0x10ACBF0A;
CHECKREG r6, 0xC00CBF0A;
CHECKREG r7, 0xD24648CA;
imm32 r0, 0x5b23a635;
imm32 r1, 0x6fba5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x90060037;
imm32 r4, 0x80abcd39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c003d;
imm32 r7, 0x12467003;
R4.L = R2.H * R2.L;
R5.L = R2.H * R3.H;
R6.L = R3.L * R2.L;
R7.L = R3.L * R3.H;
R0.L = R2.H * R2.L;
R1.L = R2.H * R3.H;
R2.L = R3.L * R2.L;
R3.L = R3.L * R3.H;
CHECKREG r0, 0x5B23F51D;
CHECKREG r1, 0x6FBAEF41;
CHECKREG r2, 0x1324FFE1;
CHECKREG r3, 0x9006FFD0;
CHECKREG r4, 0x80ABF51D;
CHECKREG r5, 0xB0ACEF41;
CHECKREG r6, 0xA00CFFE1;
CHECKREG r7, 0x1246FFD0;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x43246755;
imm32 r3, 0x05060055;
imm32 r4, 0x906bc509;
imm32 r5, 0x10a7ef5b;
imm32 r6, 0xb00c805d;
imm32 r7, 0x1246795f;
R0.L = R4.L * R4.L;
R1.L = R4.L * R5.H;
R2.L = R5.H * R4.L;
R3.L = R5.H * R5.H;
R4.L = R4.L * R4.L;
R5.L = R4.L * R5.H;
R6.L = R5.H * R4.L;
R7.L = R5.H * R5.H;
CHECKREG r0, 0x1B231B2A;
CHECKREG r1, 0xC4BAF854;
CHECKREG r2, 0x4324F854;
CHECKREG r3, 0x0506022B;
CHECKREG r4, 0x906B1B2A;
CHECKREG r5, 0x10A70389;
CHECKREG r6, 0xB00C0389;
CHECKREG r7, 0x1246022B;
imm32 r0, 0xbb235666;
imm32 r1, 0xefba5166;
imm32 r2, 0x13248766;
imm32 r3, 0xf0060066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10acef6b;
imm32 r6, 0x800cb06d;
imm32 r7, 0x1246706f;
// test the unsigned U=1
R0.L = R6.L * R6.L;
R1.L = R6.L * R7.H;
R2.L = R7.H * R6.L;
R3.L = R7.H * R7.H;
R4.L = R6.L * R6.L;
R5.L = R6.L * R7.H;
R6.L = R7.H * R6.L;
R7.L = R7.H * R7.H;
CHECKREG r0, 0xBB233178;
CHECKREG r1, 0xEFBAF4A4;
CHECKREG r2, 0x1324F4A4;
CHECKREG r3, 0xF006029C;
CHECKREG r4, 0x90AB3178;
CHECKREG r5, 0x10ACF4A4;
CHECKREG r6, 0x800CF4A4;
CHECKREG r7, 0x1246029C;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R0.L = R0.H * R7.L;
R1.L = R1.H * R6.H;
R2.L = R2.L * R5.L;
R3.L = R3.H * R4.H;
R4.L = R4.L * R3.H;
R5.L = R5.H * R2.L;
R6.L = R6.L * R1.L;
R7.L = R7.H * R0.L;
CHECKREG r0, 0xAB230A92;
CHECKREG r1, 0xCFBAFFFB;
CHECKREG r2, 0x1324E621;
CHECKREG r3, 0x0006FFFB;
CHECKREG r4, 0x90ABFFFE;
CHECKREG r5, 0x10ACFCA1;
CHECKREG r6, 0x000C0000;
CHECKREG r7, 0x12460182;
imm32 r0, 0xab235a75;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246905;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d0d;
imm32 r7, 0x1246700f;
R0.H = R7.H * R0.H;
R1.H = R6.H * R1.H;
R2.H = R5.H * R2.L;
R3.H = R4.H * R3.H;
R4.H = R3.L * R4.H;
R5.H = R2.H * R5.L;
R6.H = R1.H * R6.H;
R7.H = R0.L * R7.H;
CHECKREG r0, 0xF3E35A75;
CHECKREG r1, 0xFFFB5127;
CHECKREG r2, 0x0DAE6905;
CHECKREG r3, 0xFFFB0007;
CHECKREG r4, 0xFFFACD09;
CHECKREG r5, 0xFDA2E9DB;
CHECKREG r6, 0x00000D0D;
CHECKREG r7, 0x0CEA700F;
imm32 r0, 0x9b235675;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946705;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c009d;
imm32 r7, 0x12467009;
R2.H = R0.L * R6.L;
R3.H = R1.H * R7.L;
R0.H = R2.L * R0.L;
R1.H = R3.L * R1.H;
R4.H = R4.H * R2.H;
R5.H = R5.L * R3.H;
R6.H = R6.H * R4.L;
R7.H = R7.L * R5.H;
CHECKREG r0, 0x45965675;
CHECKREG r1, 0xFFFD5127;
CHECKREG r2, 0x006A6705;
CHECKREG r3, 0xD07F0007;
CHECKREG r4, 0xFFA49D09;
CHECKREG r5, 0x0838E9DB;
CHECKREG r6, 0xFFF7009D;
CHECKREG r7, 0x07327009;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R4.H = R5.L * R2.L;
R6.H = R6.H * R3.H;
R0.H = R7.H * R4.L;
R1.H = R0.H * R5.L;
R2.H = R1.H * R6.H;
R5.H = R2.H * R7.L;
R3.H = R3.H * R0.L;
R7.H = R4.L * R1.H;
CHECKREG r0, 0xFD4B5675;
CHECKREG r1, 0x005D5127;
CHECKREG r2, 0x00006705;
CHECKREG r3, 0x00090007;
CHECKREG r4, 0xF234ED09;
CHECKREG r5, 0x0000EEDB;
CHECKREG r6, 0x000000ED;
CHECKREG r7, 0xFFF2700E;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,139 | sim/testsuite/bfin/c_ldst_ld_d_p_mm_b.s | //Original:testcases/core/c_ldst_ld_d_p_mm_b/c_ldst_ld_d_p_mm_b.dsp
// Spec Reference: c_ldst ld d [p--] b
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_I_REGS -1;
INIT_R_REGS 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs -1;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p5, DATA_ADDR_1, 0x14;
loadsym p1, DATA_ADDR_2, 0x14;
loadsym p2, DATA_ADDR_3, 0x14;
loadsym i1, DATA_ADDR_4, 0x14;
loadsym p4, DATA_ADDR_5, 0x14;
loadsym fp, DATA_ADDR_6, 0x14;
loadsym i3, DATA_ADDR_7, 0x14;
P3 = I1; SP = I3;
R0 = B [ P5 -- ] (Z);
R1 = B [ P1 -- ] (Z);
R2 = B [ P2 -- ] (Z);
R3 = B [ P3 -- ] (Z);
R4 = B [ P4 -- ] (Z);
R5 = B [ FP -- ] (Z);
R6 = B [ SP -- ] (Z);
CHECKREG r0, 0x00000017;
CHECKREG r1, 0x00000037;
CHECKREG r2, 0x00000057;
CHECKREG r3, 0x00000077;
CHECKREG r4, 0x00000097;
CHECKREG r5, 0x00000017;
CHECKREG r6, 0x00000097;
R1 = B [ P5 -- ] (Z);
R2 = B [ P1 -- ] (Z);
R3 = B [ P2 -- ] (Z);
R4 = B [ P3 -- ] (Z);
R5 = B [ P4 -- ] (Z);
R6 = B [ FP -- ] (Z);
R7 = B [ SP -- ] (Z);
CHECKREG r0, 0x00000017;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000030;
CHECKREG r3, 0x00000050;
CHECKREG r4, 0x00000070;
CHECKREG r5, 0x00000090;
CHECKREG r6, 0x00000010;
CHECKREG r7, 0x00000090;
R2 = B [ P5 -- ] (Z);
R3 = B [ P1 -- ] (Z);
R4 = B [ P2 -- ] (Z);
R5 = B [ P3 -- ] (Z);
R6 = B [ P4 -- ] (Z);
R7 = B [ FP -- ] (Z);
R0 = B [ SP -- ] (Z);
CHECKREG r0, 0x00000091;
CHECKREG r1, 0x00000010;
CHECKREG r2, 0x00000011;
CHECKREG r3, 0x00000031;
CHECKREG r4, 0x00000051;
CHECKREG r5, 0x00000071;
CHECKREG r6, 0x00000091;
CHECKREG r7, 0x00000011;
R3 = B [ P5 -- ] (Z);
R4 = B [ P1 -- ] (Z);
R5 = B [ P2 -- ] (Z);
R6 = B [ P3 -- ] (Z);
R7 = B [ P4 -- ] (Z);
R0 = B [ FP -- ] (Z);
R1 = B [ SP -- ] (Z);
CHECKREG r0, 0x00000012;
CHECKREG r1, 0x00000092;
CHECKREG r2, 0x00000011;
CHECKREG r3, 0x00000012;
CHECKREG r4, 0x00000032;
CHECKREG r5, 0x00000052;
CHECKREG r6, 0x00000072;
CHECKREG r7, 0x00000092;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,772 | sim/testsuite/bfin/c_dspldst_st_drlo_i.s | //Original:/testcases/core/c_dspldst_st_drlo_i/c_dspldst_st_drlo_i.dsp
// Spec Reference: c_dspldst st_drlo_i
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
W [ I0 ] = R0.L;
W [ I1 ] = R1.L;
W [ I2 ] = R2.L;
W [ I3 ] = R3.L;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x00014507;
CHECKREG r5, 0x20215618;
CHECKREG r6, 0x40416729;
CHECKREG r7, 0x6061783A;
W [ I0 ] = R3.L;
W [ I1 ] = R2.L;
W [ I2 ] = R1.L;
W [ I3 ] = R0.L;
R4 = [ I0 ];
R5 = [ I1 ];
R6 = [ I2 ];
R7 = [ I3 ];
CHECKREG r4, 0x0001783A;
CHECKREG r5, 0x20216729;
CHECKREG r6, 0x40415618;
CHECKREG r7, 0x60614507;
imm32 r0, 0x1a334507;
imm32 r1, 0x12345618;
imm32 r2, 0x2c3e6729;
imm32 r3, 0x3d54f83a;
imm32 r4, 0x4e67594b;
imm32 r5, 0x5f789c5c;
imm32 r6, 0x6089ad7d;
imm32 r7, 0x739abc88;
W [ I0 ] = R4.L;
W [ I1 ] = R5.L;
W [ I2 ] = R6.L;
W [ I3 ] = R7.L;
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
CHECKREG r0, 0x0001594B;
CHECKREG r1, 0x20219C5C;
CHECKREG r2, 0x4041AD7D;
CHECKREG r3, 0x6061BC88;
W [ I0 ] = R7.L;
W [ I1 ] = R6.L;
W [ I2 ] = R5.L;
W [ I3 ] = R4.L;
R0 = [ I0 ];
R1 = [ I1 ];
R2 = [ I2 ];
R3 = [ I3 ];
CHECKREG r0, 0x0001BC88;
CHECKREG r1, 0x2021AD7D;
CHECKREG r2, 0x40419C5C;
CHECKREG r3, 0x6061594B;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,068 | sim/testsuite/bfin/c_brcc_bp4.s | //Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2 (BP); // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,417 | sim/testsuite/bfin/m15.s | // Test extraction from accumulators:
// SIGNED FRACTIONAL and SIGNED INT mode into register PAIR with SCALE
# mach: bfin
.include "testutils.inc"
start
// load r0=0x0ffffff0
// load r1=0x7ffffff0
// load r2=0x0fffffff
// load r3=0x80100000
// load r4=0x000000ff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
// extract
// 0x000ffffff0 -> 0x1ffffffe0
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R7 = A1, R6 = A0 (S2RND);
DBGA ( R7.L , 0xffe0 );
DBGA ( R7.H , 0x1fff );
DBGA ( R6.L , 0xffe0 );
DBGA ( R6.H , 0x1fff );
// extract (saturate)
// 0x007ffffff0 -> 0x7ffffffff
A1 = A0 = 0;
A1.w = R1;
A0.w = R1;
R7 = A1, R6 = A0 (S2RND);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0x7fff );
// extract (saturate negative)
// 0xff0ffffff0 -> 0x80000000
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
A1.x = R4.L;
A0.x = R4.L;
R7 = A1, R6 = A0 (S2RND);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x8000 );
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x8000 );
// extract int
// 0x000ffffff0 -> 0x1ffffffe0
A1 = A0 = 0;
A1.w = R0;
A0.w = R0;
R7 = A1, R6 = A0 (ISS2);
DBGA ( R7.L , 0xffe0 );
DBGA ( R7.H , 0x1fff );
DBGA ( R6.L , 0xffe0 );
DBGA ( R6.H , 0x1fff );
pass
.data
data0:
.dw 0xfff0
.dw 0x0fff
.dw 0xfff0
.dw 0x7fff
.dw 0xffff
.dw 0x0fff
.dw 0x0000
.dw 0x8010
.dw 0x00ff
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 2,424 | sim/testsuite/bfin/cc-astat-bits.s | # Blackfin testcase for setting all ASTAT bits via CC
# mach: bfin
# We encode the opcodes directly since we test reserved bits
# which lack an insn in the ISA for it. It's a 16bit insn;
# the low 8 bits are always 0x03 while the encoding for the
# high 8 bits are:
# bit 7 - direction
# 0: CC=...;
# 1: ...=CC;
# bit 6/5 - operation
# 0: = assignment
# 1: | bit or
# 2: & bit and
# 3: ^ bit xor
# bit 4-0 - the bit in ASTAT to access
.include "testutils.inc"
.macro _do dir:req, op:req, bit:req, bit_in:req, cc_in:req, bg_val:req, bit_out:req, cc_out:req
/* CC = CC; is invalid, so skip it */
.if \bit != 5
/* Calculate the before and after ASTAT values */
imm32 R1, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_in << \bit) | (\cc_in << 5);
imm32 R3, (\bg_val & ~((1 << \bit) | (1 << 5))) | (\bit_out << \bit) | (\cc_out << 5);
/* Test the actual opcode */
ASTAT = R1;
.byte (\dir << 7) | (\op << 5) | \bit
.byte 0x03
R2 = ASTAT;
/* Make sure things line up */
CC = R3 == R2;
IF !CC JUMP 1f;
JUMP 2f;
1: fail
2:
.endif
/* Recurse through all the bits */
.if \bit > 0
_do \dir, \op, \bit - 1, \bit_in, \cc_in, \bg_val, \bit_out, \cc_out
.endif
.endm
/* Test different background fields on ASTAT */
.macro do dir:req, op:req, bit_in:req, cc_in:req, bit_out:req, cc_out:req
_do \dir, \op, 31, \bit_in, \cc_in, 0, \bit_out, \cc_out
_do \dir, \op, 31, \bit_in, \cc_in, -1, \bit_out, \cc_out
.endm
start
nop;
_cc_eq_bit: /* CC = bit */
do 0, 0, 0, 0, 0, 0
do 0, 0, 0, 1, 0, 0
do 0, 0, 1, 0, 1, 1
do 0, 0, 1, 1, 1, 1
_bit_eq_cc: /* bit = CC */
do 1, 0, 0, 0, 0, 0
do 1, 0, 0, 1, 1, 1
do 1, 0, 1, 0, 0, 0
do 1, 0, 1, 1, 1, 1
_cc_or_bit: /* CC |= bit */
do 0, 1, 0, 0, 0, 0
do 0, 1, 0, 1, 0, 1
do 0, 1, 1, 0, 1, 1
do 0, 1, 1, 1, 1, 1
_bit_or_cc: /* bit |= CC */
do 1, 1, 0, 0, 0, 0
do 1, 1, 0, 1, 1, 1
do 1, 1, 1, 0, 1, 0
do 1, 1, 1, 1, 1, 1
_cc_and_bit: /* CC &= bit */
do 0, 2, 0, 0, 0, 0
do 0, 2, 0, 1, 0, 0
do 0, 2, 1, 0, 1, 0
do 0, 2, 1, 1, 1, 1
_bit_and_cc: /* bit &= CC */
do 1, 2, 0, 0, 0, 0
do 1, 2, 0, 1, 0, 1
do 1, 2, 1, 0, 0, 0
do 1, 2, 1, 1, 1, 1
_cc_xor_bit: /* CC ^= bit */
do 0, 3, 0, 0, 0, 0
do 0, 3, 0, 1, 0, 1
do 0, 3, 1, 0, 1, 1
do 0, 3, 1, 1, 1, 0
_bit_xor_cc: /* bit ^= CC */
do 1, 3, 0, 0, 0, 0
do 1, 3, 0, 1, 1, 1
do 1, 3, 1, 0, 1, 0
do 1, 3, 1, 1, 0, 1
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,645 | sim/testsuite/bfin/c_ldstidxl_ld_dr_xb.s | //Original:testcases/core/c_ldstidxl_ld_dr_xb/c_ldstidxl_ld_dr_xb.dsp
// Spec Reference: c_ldstidxl load dreg XB (ld with indexed addressing)
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym p1, DATA_ADDR_1, 0x00;
loadsym p2, DATA_ADDR_2, 0xA0;
loadsym i1, DATA_ADDR_1, 0x70;
loadsym p4, DATA_ADDR_2, 0x70;
loadsym p5, DATA_ADDR_1, 0x70;
loadsym fp, DATA_ADDR_2, 0x70;
loadsym i3, DATA_ADDR_1, 0x70;
P3 = I1; SP = I3;
R0 = B [ P1 + 151 ] (X);
R1 = B [ P1 + 83 ] (X);
R2 = B [ P1 + 45 ] (X);
R3 = B [ P1 + 17 ] (X);
R4 = B [ P1 + 39 ] (X);
R5 = B [ P1 + 21 ] (X);
R6 = B [ P1 + 123 ] (X);
R7 = B [ P1 + 155 ] (X);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000018;
CHECKREG r2, 0x00000076;
CHECKREG r3, 0x00000012;
CHECKREG r4, 0x00000055;
CHECKREG r5, 0x00000016;
CHECKREG r6, 0x00000058;
CHECKREG r7, 0x00000004;
R0 = B [ P2 + -121 ] (X);
R1 = B [ P2 + -113 ] (X);
R2 = B [ P2 + -35 ] (X);
R3 = B [ P2 + -27 ] (X);
R4 = B [ P2 + -49 ] (X);
R5 = B [ P2 + -5 ] (X);
R6 = B [ P2 + -51 ] (X);
R7 = B [ P2 + -147 ] (X);
CHECKREG r0, 0xFFFFFFCF;
CHECKREG r1, 0xFFFFFFD7;
CHECKREG r2, 0x00000056;
CHECKREG r3, 0x00000064;
CHECKREG r4, 0xFFFFFF94;
CHECKREG r5, 0x0000004C;
CHECKREG r6, 0xFFFFFF99;
CHECKREG r7, 0x0000004E;
R0 = B [ P3 + 56 ] (X);
R1 = B [ P3 + 62 ] (X);
R2 = B [ P3 + -63 ] (X);
R3 = B [ P3 + 61 ] (X);
R4 = B [ P3 + -59 ] (X);
R5 = B [ P3 + 11 ] (X);
R6 = B [ P3 + -23 ] (X);
R7 = B [ P3 + -111 ] (X);
CHECKREG r0, 0x00000017;
CHECKREG r1, 0x00000019;
CHECKREG r2, 0xFFFFFF84;
CHECKREG r3, 0x0000001A;
CHECKREG r4, 0xFFFFFF88;
CHECKREG r5, 0x00000058;
CHECKREG r6, 0x00000028;
CHECKREG r7, 0x00000002;
R0 = B [ P4 + 47 ] (X);
R1 = B [ P4 + -41 ] (X);
R2 = B [ P4 + 38 ] (X);
R3 = B [ P4 + -31 ] (X);
R4 = B [ P4 + 28 ] (X);
R5 = B [ P4 + 26 ] (X);
R6 = B [ P4 + -22 ] (X);
R7 = B [ P4 + 105 ] (X);
CHECKREG r0, 0x00000050;
CHECKREG r1, 0xFFFFFF93;
CHECKREG r2, 0x00000049;
CHECKREG r3, 0xFFFFFF99;
CHECKREG r4, 0x00000043;
CHECKREG r5, 0x00000067;
CHECKREG r6, 0xFFFFFFE8;
CHECKREG r7, 0xFFFFFF99;
R0 = B [ P5 + -14 ] (X);
R1 = B [ P5 + 12 ] (X);
R2 = B [ P5 + -6 ] (X);
R3 = B [ P5 + 4 ] (X);
R4 = B [ P5 + 0 ] (X);
R5 = B [ P5 + -2 ] (X);
R6 = B [ P5 + 8 ] (X);
R7 = B [ P5 + -107 ] (X);
CHECKREG r0, 0x00000035;
CHECKREG r1, 0x00000065;
CHECKREG r2, 0x00000043;
CHECKREG r3, 0x00000057;
CHECKREG r4, 0x00000053;
CHECKREG r5, 0x00000047;
CHECKREG r6, 0x00000061;
CHECKREG r7, 0x00000006;
R0 = B [ FP + 99 ] (X);
R1 = B [ FP + -15 ] (X);
R2 = B [ FP + 41 ] (X);
R3 = B [ FP + -65 ] (X);
R4 = B [ FP + 25 ] (X);
R5 = B [ FP + -34 ] (X);
R6 = B [ FP + 37 ] (X);
R7 = B [ FP + -97 ] (X);
CHECKREG r0, 0xFFFFFF93;
CHECKREG r1, 0xFFFFFF99;
CHECKREG r2, 0x0000004E;
CHECKREG r3, 0xFFFFFFD7;
CHECKREG r4, 0x00000068;
CHECKREG r5, 0xFFFFFFE8;
CHECKREG r6, 0x0000004A;
CHECKREG r7, 0x0000004C;
R0 = B [ SP + 46 ] (X);
R1 = B [ SP + -41 ] (X);
R2 = B [ SP + 48 ] (X);
R3 = B [ SP + 51 ] (X);
R4 = B [ SP + -102 ] (X);
R5 = B [ SP + 89 ] (X);
R6 = B [ SP + 62 ] (X);
R7 = B [ SP + 43 ] (X);
CHECKREG r0, 0x00000009;
CHECKREG r1, 0x00000005;
CHECKREG r2, 0x0000000F;
CHECKREG r3, 0x0000000C;
CHECKREG r4, 0x00000009;
CHECKREG r5, 0xFFFFFF88;
CHECKREG r6, 0x00000019;
CHECKREG r7, 0x00000004;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
DATA_ADDR_2:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 5,502 | sim/testsuite/bfin/c_logi2op_arith_shft.s | //Original:/testcases/core/c_logi2op_arith_shft/c_logi2op_arith_shft.dsp
// Spec Reference: Logi2op >>>=
# mach: bfin
.include "testutils.inc"
start
// Arithmetic >>>= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81111111;
imm32 r6, 0x81111111;
imm32 r7, 0x81111111;
R0 >>>= 0; /* r0 = 0x81111111 */
R1 >>>= 1; /* r1 = 0xC0888888 */
R2 >>>= 2; /* r2 = 0xE0444444 */
R3 >>>= 3; /* r3 = 0xF0222222 */
R4 >>>= 4; /* r4 = 0xF8111111 */
R5 >>>= 5; /* r5 = 0xFC088888 */
R6 >>>= 6; /* r6 = 0xFE044444 */
R7 >>>= 7; /* r7 = 0xFF022222 */
CHECKREG r0, 0x81111111;
CHECKREG r1, 0xC0888888;
CHECKREG r2, 0xE0444444;
CHECKREG r3, 0xF0222222;
CHECKREG r4, 0xF8111111;
CHECKREG r5, 0xFC088888;
CHECKREG r6, 0xFE044444;
CHECKREG r7, 0xFF022222;
// bit 8-15
imm32 r0, 0x82222222;
imm32 r1, 0x82222222;
imm32 r2, 0x82222222;
imm32 r3, 0x82222222;
imm32 r4, 0x82222222;
imm32 r5, 0x82222222;
imm32 r6, 0x82222222;
imm32 r7, 0x82222222;
R0 >>>= 8; /* r0 = 0xFF822222 */
R1 >>>= 9; /* r1 = 0xFFC11111 */
R2 >>>= 10; /* r2 = 0xFFE08888 */
R3 >>>= 11; /* r3 = 0xFFF04444 */
R4 >>>= 12; /* r4 = 0xFFF82222 */
R5 >>>= 13; /* r5 = 0xFFFC1111 */
R6 >>>= 14; /* r6 = 0xFFFE0888 */
R7 >>>= 15; /* r7 = 0xFFFF0444 */
CHECKREG r0, 0xFF822222;
CHECKREG r1, 0xFFC11111;
CHECKREG r2, 0xFFE08888;
CHECKREG r3, 0xFFF04444;
CHECKREG r4, 0xFFF82222;
CHECKREG r5, 0xFFFC1111;
CHECKREG r6, 0xFFFE0888;
CHECKREG r7, 0xFFFF0444;
// bit 16-23
imm32 r0, 0x83333333;
imm32 r1, 0x83333333;
imm32 r2, 0x83333333;
imm32 r3, 0x83333333;
imm32 r4, 0x83333333;
imm32 r5, 0x83333333;
imm32 r6, 0x83333333;
imm32 r7, 0x83333333;
R0 >>>= 16; /* r0 = 0xFFFF8333 */
R1 >>>= 17; /* r1 = 0xFFFFC199 */
R2 >>>= 18; /* r2 = 0xFFFFE0CC */
R3 >>>= 19; /* r3 = 0xFFFFF066 */
R4 >>>= 20; /* r4 = 0xFFFFF833 */
R5 >>>= 21; /* r5 = 0xFFFFFC19 */
R6 >>>= 22; /* r6 = 0xFFFFFE0C */
R7 >>>= 23; /* r7 = 0xFFFFFF06 */
CHECKREG r0, 0xFFFF8333;
CHECKREG r1, 0xFFFFC199;
CHECKREG r2, 0xFFFFE0CC;
CHECKREG r3, 0xFFFFF066;
CHECKREG r4, 0xFFFFF833;
CHECKREG r5, 0xFFFFFC19;
CHECKREG r6, 0xFFFFFE0C;
CHECKREG r7, 0xFFFFFF06;
// bit 24-31
imm32 r0, 0x84444444;
imm32 r1, 0x84444444;
imm32 r2, 0x84444444;
imm32 r3, 0x84444444;
imm32 r4, 0x84444444;
imm32 r5, 0x84444444;
imm32 r6, 0x84444444;
imm32 r7, 0x84444444;
R0 >>>= 24; /* r0 = 0xFFFFFF84 */
R1 >>>= 25; /* r1 = 0xFFFFFFC2 */
R2 >>>= 26; /* r2 = 0xFFFFFFE1 */
R3 >>>= 27; /* r3 = 0xFFFFFFF0 */
R4 >>>= 28; /* r4 = 0xFFFFFFF8 */
R5 >>>= 29; /* r5 = 0xFFFFFFFC */
R6 >>>= 30; /* r6 = 0xFFFFFFFE */
R7 >>>= 31; /* r7 = 0xFFFFFFFF */
CHECKREG r0, 0xFFFFFF84;
CHECKREG r1, 0xFFFFFFC2;
CHECKREG r2, 0xFFFFFFE1;
CHECKREG r3, 0xFFFFFFF0;
CHECKREG r4, 0xFFFFFFF8;
CHECKREG r5, 0xFFFFFFFC;
CHECKREG r6, 0xFFFFFFFE;
CHECKREG r7, 0xFFFFFFFF;
// Arithmetic >>>= : positive data
// bit 0-7
imm32 r0, 0x41111111;
imm32 r1, 0x41111111;
imm32 r2, 0x41111111;
imm32 r3, 0x41111111;
imm32 r4, 0x41111111;
imm32 r5, 0x41111111;
imm32 r6, 0x41111111;
imm32 r7, 0x41111111;
R0 >>>= 0; /* r0 = 0x41111111 */
R1 >>>= 1; /* r1 = 0x20888888 */
R2 >>>= 2; /* r2 = 0x10444444 */
R3 >>>= 3; /* r3 = 0x08222222 */
R4 >>>= 4; /* r4 = 0x04111111 */
R5 >>>= 5; /* r5 = 0x02088888 */
R6 >>>= 6; /* r6 = 0x01044444 */
R7 >>>= 7; /* r7 = 0x00822222 */
CHECKREG r0, 0x41111111;
CHECKREG r1, 0x20888888;
CHECKREG r2, 0x10444444;
CHECKREG r3, 0x08222222;
CHECKREG r4, 0x04111111;
CHECKREG r5, 0x02088888;
CHECKREG r6, 0x01044444;
CHECKREG r7, 0x00822222;
// bit 8-15
imm32 r0, 0x42222222;
imm32 r1, 0x42222222;
imm32 r2, 0x42222222;
imm32 r3, 0x42222222;
imm32 r4, 0x42222222;
imm32 r5, 0x42222222;
imm32 r6, 0x42222222;
imm32 r7, 0x42222222;
R0 >>>= 8; /* r0 = 0x00422222 */
R1 >>>= 9; /* r1 = 0x00211111 */
R2 >>>= 10; /* r2 = 0x00108888 */
R3 >>>= 11; /* r3 = 0x00084444 */
R4 >>>= 12; /* r4 = 0x00042222 */
R5 >>>= 13; /* r5 = 0x00021111 */
R6 >>>= 14; /* r6 = 0x00010888 */
R7 >>>= 15; /* r7 = 0x00008444 */
CHECKREG r0, 0x00422222;
CHECKREG r1, 0x00211111;
CHECKREG r2, 0x00108888;
CHECKREG r3, 0x00084444;
CHECKREG r4, 0x00042222;
CHECKREG r5, 0x00021111;
CHECKREG r6, 0x00010888;
CHECKREG r7, 0x00008444;
// bit 16-23
imm32 r0, 0x43333333;
imm32 r1, 0x43333333;
imm32 r2, 0x43333333;
imm32 r3, 0x43333333;
imm32 r4, 0x43333333;
imm32 r5, 0x43333333;
imm32 r6, 0x43333333;
imm32 r7, 0x43333333;
R0 >>>= 16; /* r0 = 0x00004333 */
R1 >>>= 17; /* r1 = 0x00002199 */
R2 >>>= 18; /* r2 = 0x000010CC */
R3 >>>= 19; /* r3 = 0x00000866 */
R4 >>>= 20; /* r4 = 0x00000433 */
R5 >>>= 21; /* r5 = 0x00000219 */
R6 >>>= 22; /* r6 = 0x0000010C */
R7 >>>= 23; /* r7 = 0x00000086 */
CHECKREG r0, 0x00004333;
CHECKREG r1, 0x00002199;
CHECKREG r2, 0x000010CC;
CHECKREG r3, 0x00000866;
CHECKREG r4, 0x00000433;
CHECKREG r5, 0x00000219;
CHECKREG r6, 0x0000010C;
CHECKREG r7, 0x00000086;
// bit 24-31
imm32 r0, 0x44444444;
imm32 r1, 0x44444444;
imm32 r2, 0x44444444;
imm32 r3, 0x44444444;
imm32 r4, 0x44444444;
imm32 r5, 0x44444444;
imm32 r6, 0x44444444;
imm32 r7, 0x44444444;
R0 >>>= 24; /* r0 = 0x00000044 */
R1 >>>= 25; /* r1 = 0x00000022 */
R2 >>>= 26; /* r2 = 0x00000011 */
R3 >>>= 27; /* r3 = 0x00000008 */
R4 >>>= 28; /* r4 = 0x00000004 */
R5 >>>= 29; /* r5 = 0x00000002 */
R6 >>>= 30; /* r6 = 0x00000001 */
R7 >>>= 31; /* r7 = 0x00000000 */
CHECKREG r0, 0x00000044;
CHECKREG r1, 0x00000022;
CHECKREG r2, 0x00000011;
CHECKREG r3, 0x00000008;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,609 | sim/testsuite/bfin/c_dspldst_ld_drhi_ipp.s | //Original:/testcases/core/c_dspldst_ld_drhi_ipp/c_dspldst_ld_drhi_ipp.dsp
// Spec Reference: c_dspldst ld_drhi_i++/--
# mach: bfin
.include "testutils.inc"
start
// set all regs
INIT_R_REGS 0;
// initial values
//i0=0x3000;
//i1=0x4000;
//i2=0x5000;
//i3=0x6000;
loadsym I0, DATA_ADDR_3;
loadsym I1, DATA_ADDR_4;
loadsym I2, DATA_ADDR_5;
loadsym I3, DATA_ADDR_6;
// Load Upper half of Dregs
R0.H = W [ I0 ++ ];
R1.H = W [ I1 ++ ];
R2.H = W [ I2 ++ ];
R3.H = W [ I3 ++ ];
R4.H = W [ I0 ++ ];
R5.H = W [ I1 ++ ];
R6.H = W [ I2 ++ ];
R7.H = W [ I3 ++ ];
CHECKREG r0, 0x02030000;
CHECKREG r1, 0x22230000;
CHECKREG r2, 0x42430000;
CHECKREG r3, 0x62630000;
CHECKREG r4, 0x00010000;
CHECKREG r5, 0x20210000;
CHECKREG r6, 0x40410000;
CHECKREG r7, 0x60610000;
R1.H = W [ I0 ++ ];
R2.H = W [ I1 ++ ];
R3.H = W [ I2 ++ ];
R4.H = W [ I3 ++ ];
R5.H = W [ I0 ++ ];
R6.H = W [ I1 ++ ];
R7.H = W [ I2 ++ ];
R0.H = W [ I3 ++ ];
CHECKREG r0, 0x64650000;
CHECKREG r1, 0x06070000;
CHECKREG r2, 0x26270000;
CHECKREG r3, 0x46470000;
CHECKREG r4, 0x66670000;
CHECKREG r5, 0x04050000;
CHECKREG r6, 0x24250000;
CHECKREG r7, 0x44450000;
R2.H = W [ I0 ++ ];
R3.H = W [ I1 ++ ];
R4.H = W [ I2 ++ ];
R5.H = W [ I3 ++ ];
R6.H = W [ I0 ++ ];
R7.H = W [ I1 ++ ];
R0.H = W [ I2 ++ ];
R1.H = W [ I3 ++ ];
CHECKREG r0, 0x48490000;
CHECKREG r1, 0x68690000;
CHECKREG r2, 0x0A0B0000;
CHECKREG r3, 0x2A2B0000;
CHECKREG r4, 0x4A4B0000;
CHECKREG r5, 0x6A6B0000;
CHECKREG r6, 0x08090000;
CHECKREG r7, 0x28290000;
R3.H = W [ I0 ++ ];
R4.H = W [ I1 ++ ];
R5.H = W [ I2 ++ ];
R6.H = W [ I3 ++ ];
R7.H = W [ I0 ++ ];
R0.H = W [ I1 ++ ];
R1.H = W [ I2 ++ ];
R2.H = W [ I3 ++ ];
CHECKREG r0, 0x2C2D0000;
CHECKREG r1, 0x4C4D0000;
CHECKREG r2, 0x6C6D0000;
CHECKREG r3, 0x0E0F0000;
CHECKREG r4, 0x2E2F0000;
CHECKREG r5, 0x4E4F0000;
CHECKREG r6, 0x6E6F0000;
CHECKREG r7, 0x0C0D0000;
// reverse to minus mninus i--
// Load Upper half of Dregs
R0.H = W [ I0 -- ];
R1.H = W [ I1 -- ];
R2.H = W [ I2 -- ];
R3.H = W [ I3 -- ];
R4.H = W [ I0 -- ];
R5.H = W [ I1 -- ];
R6.H = W [ I2 -- ];
R7.H = W [ I3 -- ];
CHECKREG r0, 0x12130000;
CHECKREG r1, 0x32330000;
CHECKREG r2, 0x52530000;
CHECKREG r3, 0x72730000;
CHECKREG r4, 0x0C0D0000;
CHECKREG r5, 0x2C2D0000;
CHECKREG r6, 0x4C4D0000;
CHECKREG r7, 0x6C6D0000;
R1.H = W [ I0 -- ];
R2.H = W [ I1 -- ];
R3.H = W [ I2 -- ];
R4.H = W [ I3 -- ];
R5.H = W [ I0 -- ];
R6.H = W [ I1 -- ];
R7.H = W [ I2 -- ];
R0.H = W [ I3 -- ];
CHECKREG r0, 0x68690000;
CHECKREG r1, 0x0E0F0000;
CHECKREG r2, 0x2E2F0000;
CHECKREG r3, 0x4E4F0000;
CHECKREG r4, 0x6E6F0000;
CHECKREG r5, 0x08090000;
CHECKREG r6, 0x28290000;
CHECKREG r7, 0x48490000;
R2.H = W [ I0 -- ];
R3.H = W [ I1 -- ];
R4.H = W [ I2 -- ];
R5.H = W [ I3 -- ];
R6.H = W [ I0 -- ];
R7.H = W [ I1 -- ];
R0.H = W [ I2 -- ];
R1.H = W [ I3 -- ];
CHECKREG r0, 0x44450000;
CHECKREG r1, 0x64650000;
CHECKREG r2, 0x0A0B0000;
CHECKREG r3, 0x2A2B0000;
CHECKREG r4, 0x4A4B0000;
CHECKREG r5, 0x6A6B0000;
CHECKREG r6, 0x04050000;
CHECKREG r7, 0x24250000;
R3.H = W [ I0 -- ];
R4.H = W [ I1 -- ];
R5.H = W [ I2 -- ];
R6.H = W [ I3 -- ];
R7.H = W [ I0 -- ];
R0.H = W [ I1 -- ];
R1.H = W [ I2 -- ];
R2.H = W [ I3 -- ];
CHECKREG r0, 0x20210000;
CHECKREG r1, 0x40410000;
CHECKREG r2, 0x60610000;
CHECKREG r3, 0x06070000;
CHECKREG r4, 0x26270000;
CHECKREG r5, 0x46470000;
CHECKREG r6, 0x66670000;
CHECKREG r7, 0x00010000;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xBC0DBE26
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,844 | sim/testsuite/bfin/conv_enc_gen.s | # mach: bfin
// GENERIC CONVOLUTIONAL ENCODER
// This a generic rate 1/n convolutional encoder. It computes n output
// bits for each input bit, based on n generic polynomials.
// It uses the set of BXOR_CC instructions to compute bit XOR
// reduction from a state masked by a polynomial. For an alternate
// solution based on assembling several partial words, as in
// the BDT benchmark, see file conv_enc.c. The solution presented
// here is slower than conv_enc.c, but more generic.
//
// Forward Shift Register
// -----------------------
// This solution implements the XOR function by shifting the state
// left by one, applying a mask to the state, and reducing
// the result with a bit XOR reduction function.
// ----- XOR------------> G0
// | | | |
// +------------------------------+
// | b0 b1 b2 b3 b14 b15 | <- in
// +------------------------------+
// | | | | |
// ----- XOR------------> G1
// Instruction BXOR computes the bit G0 or G1 and stores it into CC
// and also into a destination reg half. Here, we take CC and rotate it
// into an output register.
// However, one can also store the output bit directly by storing
// the register half where this bit is placed. This would result
// in an output structure similar to the one in the original function
// Convolutional_Encode(), where an entire half word holds a bit.
// The resulting execution speed would be roughly twice as fast,
// since there is no need to rotate output bit via CC.
.include "testutils.inc"
start
loadsym P0, input;
loadsym P1, output;
R1 = 0; R2 = 0;R3 = 0;
R2.L = 0;
R2.H = 0xa01d; // polynom 0
R3.L = 0;
R3.H = 0x12f4; // polynom 1
// load and CurrentState to upper half of A0
A1 = A0 = 0;
R0 = 0x0000;
A0.w = R0;
A0 = A0 << 16;
// l-loop counter is in P4
P4 = 2(Z);
// **** START l-LOOP *****
l$0:
// insert 16 bits of input into lower half of A0
// and advance input pointer
R0 = W [ P0 ++ ] (Z);
A0.L = R0.L;
P5 = 2 (Z);
LSETUP ( m$0 , m$0end ) LC0 = P5; // **** BEGIN m-LOOP *****
m$0:
P5 = 8 (Z);
LSETUP ( i$1 , i$1end ) LC1 = P5; // **** BEGIN i-LOOP *****
i$1:
R4.L = CC = BXORSHIFT( A0 , R2 ); // polynom0 -> CC
R1 = ROT R1 BY 1; // CC -> R1
R4.L = CC = BXOR( A0 , R3 ); // polynom1 -> CC
i$1end:
R1 = ROT R1 BY 1; // CC -> R1
// store 16 bits of outdata RL1
m$0end:
W [ P1 ++ ] = R1;
P4 += -1;
CC = P4 == 0;
IF !CC JUMP l$0; // **** END l-LOOP *****
// Check results
loadsym I2, output;
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x8c62 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x262e );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5b4d );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x834f );
pass
.data
input:
.dw 0x999f
.dw 0x1999
output:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000
|
tactcomplabs/xbgas-binutils-gdb | 4,017 | sim/testsuite/bfin/c_cc2stat_cc_an.s | //Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp
// Spec Reference: cc2stat cc an
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AN 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC = AN; //
R0 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC = AN; //
R1 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
CC = AN; //
R2 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC = AN; //
R3 = CC; //
// test cc |= AN (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC |= AN; //
R4 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC |= AN; //
R5 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 0
CC |= AN; //
R6 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC |= AN; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000001;
// test CC &= AN (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC &= AN; //
R4 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC &= AN; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
CC &= AN; //
R6 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC &= AN; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000001;
// test CC ^= AN (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
CC ^= AN; //
R4 = CC; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
CC ^= AN; //
R5 = CC; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
CC ^= AN; //
R6 = CC; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
CC ^= AN; //
R7 = CC; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
// test AN = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN = CC; //
R0 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN = CC; //
R1 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN = CC; //
R2 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN = CC; //
R3 = ASTAT; //
// test AN |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN |= CC; //
R4 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN |= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN |= CC; //
R6 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN |= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000022;
// test AN &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN &= CC; //
R4 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN &= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN &= CC; //
R6 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN &= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000020;
CHECKREG r7, 0x00000022;
// test AN ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AN = 0
AN ^= CC; //
R4 = ASTAT; //
R7 = 0x02;
ASTAT = R7; // cc = 0, AN = 1
AN ^= CC; //
R5 = ASTAT; //
R7 = 0x20;
ASTAT = R7; // cc = 1, AN = 0
AN ^= CC; //
R6 = ASTAT; //
R7 = 0x22;
ASTAT = R7; // cc = 1, AN = 1
AN ^= CC; //
R7 = ASTAT; //
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000022;
CHECKREG r3, 0x00000022;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00000022;
CHECKREG r7, 0x00000020;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,359 | sim/testsuite/bfin/se_loop_disable.S | //Original:/proj/frio/dv/testcases/seq/se_loop_disable/se_loop_disable.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
LSETUP ( 1f , 1f ) LC0 = P1;
1:R7 += 1;
LSETUP ( 1f , 1f ) LC0 = P1;
1:R6 += 1;
LC0 = P0;
LD32_LABEL(r0, l0t);
LD32_LABEL(r1, l0b);
LT0 = r0;
LB0 = r1;
l0t:R3 += 3;
R1 += 1;
R4 += 4;
R5 += 5;
R6 += 6;
l0b:R2 += 2;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_3 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_( DATA_ADDR_3 + 100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.section MEM_( DATA_ADDR_3 + 110) //.data 0x00F00210,"aw"
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 1,898 | sim/testsuite/bfin/c_cactrl_iflush_pr.s | //Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp
// Spec Reference: c_cactrl iflush_pr
# mach: bfin
.include "testutils.inc"
start
// initial values
//p1=0x448;
//imm32 p1, CODE_ADDR_1;
loadsym p1, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg half
R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R3.H = A1 , A0 = R7.H * R6.L (T);
// begin of iflush
IFLUSH [ P1 ]; // p1 = 0xf00
R7 = 0;
ASTAT = R7;
IF !CC JUMP SUBR1;
JBACK:
R6 = 0;
//r4 = (a1 = l*h) M, a0 = h*l (r3,r2);
//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS;
CHECKREG r2, 0xFFD15679;
CHECKREG r3, 0xFFD00007;
CHECKREG r4, 0x00074569;
CHECKREG r5, 0x12358000;
pass
//.code 0x448
//.code CODE_ADDR_1
SUBR1:
R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
IF !CC JUMP JBACK;
NOP; NOP; NOP; NOP; NOP;
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
|
tactcomplabs/xbgas-binutils-gdb | 1,667 | sim/testsuite/bfin/c_br_preg_killed_ac.s | //Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
P4 = 4;
P2 = 2;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
JUMP ( PC + P4 ); //brf LABEL2; // (bp);
CC = ! CC;
LABEL2:
JUMP ( PC + P4 ); //brf LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
JUMP ( PC + P4 ); //brf LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
JUMP ( PC + P4 ); //brf LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
JUMP ( PC + P4 ); //brf LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
JUMP ( PC + P4 ); //brf LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
JUMP ( PC + P4 ); //brf LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
JUMP ( PC + P4 ); //brf LABEL9;
JUMP ( PC + P2 ); //BAD1; // UJUMP killed
LABEL9:
JUMP ( PC + P4 ); //brf LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103
|
tactcomplabs/xbgas-binutils-gdb | 1,458 | sim/testsuite/bfin/c_dsp32alu_r_lh_a0pa1.s | //Original:/testcases/core/c_dsp32alu_r_lh_a0pa1/c_dsp32alu_r_lh_a0pa1.dsp
// Spec Reference: dsp32alu r(lh) = ( a0 += a1)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x15678911;
imm32 r1, 0x0125ab2d;
imm32 r2, 0x04445535;
imm32 r3, 0x00567747;
imm32 r4, 0x0566895b;
imm32 r5, 0x07897b6d;
imm32 r6, 0x04445875;
imm32 r7, 0x06667797;
A0 = R0;
A1 = R1;
R0 = ( A0 += A1 );
R1 = ( A0 += A1 );
R2 = ( A0 += A1 );
R3 = ( A0 += A1 );
R4 = ( A0 += A1 );
R5 = ( A0 += A1 );
R6 = ( A0 += A1 );
R7 = ( A0 += A1 );
CHECKREG r0, 0x168D343E;
CHECKREG r1, 0x17B2DF6B;
CHECKREG r2, 0x18D88A98;
CHECKREG r3, 0x19FE35C5;
CHECKREG r4, 0x1B23E0F2;
CHECKREG r5, 0x1C498C1F;
CHECKREG r6, 0x1D6F374C;
CHECKREG r7, 0x1E94E279;
imm32 r0, 0x068D343E;
imm32 r1, 0x02B2DF6B;
imm32 r2, 0x48388A98;
imm32 r3, 0x59F435C5;
imm32 r4, 0x6B25E0F2;
imm32 r5, 0x7C496C1F;
imm32 r6, 0x886F374C;
imm32 r7, 0x9E94E279;
A0 = R0;
A1 = R1;
R0.L = ( A0 += A1 );
R0.H = ( A0 += A1 );
R1.L = ( A0 += A1 );
R1.H = ( A0 += A1 );
R2.L = ( A0 += A1 );
R2.H = ( A0 += A1 );
R3.L = ( A0 += A1 );
R3.H = ( A0 += A1 );
R4.L = ( A0 += A1 );
R4.H = ( A0 += A1 );
R5.L = ( A0 += A1 );
R5.H = ( A0 += A1 );
R6.L = ( A0 += A1 );
R6.H = ( A0 += A1 );
R7.L = ( A0 += A1 );
R7.H = ( A0 += A1 );
CHECKREG r0, 0x0BF30940;
CHECKREG r1, 0x11590EA6;
CHECKREG r2, 0x16BE140C;
CHECKREG r3, 0x1C241971;
CHECKREG r4, 0x218A1ED7;
CHECKREG r5, 0x26F0243D;
CHECKREG r6, 0x2C5529A3;
CHECKREG r7, 0x31BB2F08;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,498 | sim/testsuite/bfin/c_dsp32mac_dr_a1_iu.s | //Original:/testcases/core/c_dsp32mac_dr_a1_iu/c_dsp32mac_dr_a1_iu.dsp
// Spec Reference: dsp32mac dr_a1 iu (unsigned integer)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x93545abd;
imm32 r1, 0x7890afc7;
imm32 r2, 0x52248679;
imm32 r3, 0xd5069007;
imm32 r4, 0xef5c4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c500d;
imm32 r7, 0xf78e950f;
R0.H = ( A1 = R1.L * R0.L ), A0 += R1.L * R0.L (IU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ), A0 = R2.H * R3.L (IU);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ), A0 += R4.H * R5.H (IU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ), A0 -= R6.L * R7.H (IU);
R7 = A1.w;
CHECKREG r0, 0xFFFF5ABD;
CHECKREG r1, 0x3E4DBBEB;
CHECKREG r2, 0xFFFF8679;
CHECKREG r3, 0xAE338FC1;
CHECKREG r4, 0xFFFF4569;
CHECKREG r5, 0xF90A98B5;
CHECKREG r6, 0xFFFF500D;
CHECKREG r7, 0x2062BE0D;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0xd3548abd;
imm32 r1, 0x9dbcfec7;
imm32 r2, 0xa9d45679;
imm32 r3, 0xb09d9007;
imm32 r4, 0xcfb9d569;
imm32 r5, 0xd2359d0b;
imm32 r6, 0xe00ca90d;
imm32 r7, 0x678e709f;
R0.H = ( A1 += R1.L * R0.L ) (IU);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (IU);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (IU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (IU);
R7 = A1.w;
CHECKREG r0, 0xFFFF8ABD;
CHECKREG r1, 0xAA761CF8;
CHECKREG r2, 0xFFFF5679;
CHECKREG r3, 0x6ECDE4C3;
CHECKREG r4, 0xFFFFD569;
CHECKREG r5, 0x7F6D61F3;
CHECKREG r6, 0xFFFFA90D;
CHECKREG r7, 0x24CC474B;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0xa354babd;
imm32 r1, 0x9abcdec7;
imm32 r2, 0x77a4e679;
imm32 r3, 0x805a7007;
imm32 r4, 0x9fb3a569;
imm32 r5, 0xa2352a0b;
imm32 r6, 0xb00c10ad;
imm32 r7, 0x9876a10a;
R0.H = A1 , A0 -= R1.L * R0.L (IU);
R1 = A1.w;
R2.H = A1 , A0 += R2.H * R3.L (IU);
R3 = A1.w;
R4.H = A1 , A0 = R4.H * R5.H (IU);
R5 = A1.w;
R6.H = A1 , A0 -= R6.L * R7.H (IU);
R7 = A1.w;
CHECKREG r0, 0xFFFFBABD;
CHECKREG r1, 0x24CC474B;
CHECKREG r2, 0xFFFFE679;
CHECKREG r3, 0x24CC474B;
CHECKREG r4, 0xFFFFA569;
CHECKREG r5, 0x24CC474B;
CHECKREG r6, 0xFFFF10AD;
CHECKREG r7, 0x24CC474B;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x9dbcfec7;
imm32 r2, 0x81245679;
imm32 r3, 0x97060007;
imm32 r4, 0xaf6c4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00c400d;
imm32 r7, 0x678ed30f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (IU);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M), A0 = R2.H * R3.L (IU);
R3 = A1.w;
R4.H = ( A1 = R4.H * R5.L ) (M), A0 -= R4.H * R5.H (IU);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IU);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0xCC8DA915;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xD2A949A4;
CHECKREG r6, 0x8000400D;
CHECKREG r7, 0xB8CAA44C;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0xe2005ABD;
imm32 r1, 0x0e300000;
imm32 r2, 0x56e49679;
imm32 r3, 0x30Ae5000;
imm32 r4, 0xa000e669;
imm32 r5, 0x01000e70;
imm32 r6, 0xdf4560eD;
imm32 r7, 0x1234567e;
R0.H = ( A1 -= R1.L * R0.L ) (M,IU);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M,IU);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,IU);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (M,IU);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xB8CAA44C;
CHECKREG r2, 0x80009679;
CHECKREG r3, 0xA4B99A8A;
CHECKREG r4, 0x8000E669;
CHECKREG r5, 0xAA239A8A;
CHECKREG r6, 0x800060ED;
CHECKREG r7, 0xAC776686;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,386 | sim/testsuite/bfin/a10.s | // ALU test program.
// Test dual 16 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0002;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0002 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger
R0.L = 0x0000;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// one operand larger, one smaller.
R0.L = 0x000a;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x000a );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x8001;
R0.H = 0xffff;
R1.L = 0x8000;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x8001 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x8000;
R0.H = 0xffff;
R1.L = 0x8000;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// MIN
// second operand is smaller
R0.L = 0x0001;
R0.H = 0x0004;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller
R0.L = 0xffff;
R0.H = 0x8001;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x8001 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// one of each
R0.L = 0xffff;
R0.H = 0x0034;
R1.L = 0x0999;
R1.H = 0x0010;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x0999;
R1.H = 0x0010;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// ABS
R0.L = 0x0001;
R0.H = 0x8001;
R7 = ABS R0 (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x7fff );
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0001;
R0.H = 0x8000;
R7 = ABS R0 (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0xffff;
R7 = ABS R0 (V);
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0001 );
CC = VS; R6 = CC; DBGA ( R6.L, 0x1 );
CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,744 | sim/testsuite/bfin/c_ldimmhalf_l_ibml.s | //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp
// Spec Reference: ldimmhalf l ibml
# mach: bfin
.include "testutils.inc"
start
INIT_I_REGS -1;
INIT_L_REGS -1;
INIT_M_REGS -1;
INIT_B_REGS -1;
I0.L = 0x2001;
I1.L = 0x2003;
I2.L = 0x2005;
I3.L = 0x2007;
L0.L = 0x2009;
L1.L = 0x200b;
L2.L = 0x200d;
L3.L = 0x200f;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0xffff2001;
CHECKREG r1, 0xffff2003;
CHECKREG r2, 0xffff2005;
CHECKREG r3, 0xffff2007;
CHECKREG r4, 0xffff2009;
CHECKREG r5, 0xffff200b;
CHECKREG r6, 0xffff200d;
CHECKREG r7, 0xffff200f;
I0.L = 0x0111;
I1.L = 0x1111;
I2.L = 0x2222;
I3.L = 0x3333;
L0.L = 0x4444;
L1.L = 0x5555;
L2.L = 0x6666;
L3.L = 0x7777;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0xffff0111;
CHECKREG r1, 0xffff1111;
CHECKREG r2, 0xffff2222;
CHECKREG r3, 0xffff3333;
CHECKREG r4, 0xffff4444;
CHECKREG r5, 0xffff5555;
CHECKREG r6, 0xffff6666;
CHECKREG r7, 0xffff7777;
I0.L = 0x8888;
I1.L = 0x9aaa;
I2.L = 0xabbb;
I3.L = 0xbccc;
L0.L = 0xcddd;
L1.L = 0xdeee;
L2.L = 0xefff;
L3.L = 0xf111;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = L0;
R5 = L1;
R6 = L2;
R7 = L3;
CHECKREG r0, 0xffff8888;
CHECKREG r1, 0xffff9aaa;
CHECKREG r2, 0xffffabbb;
CHECKREG r3, 0xffffbccc;
CHECKREG r4, 0xffffcddd;
CHECKREG r5, 0xffffdeee;
CHECKREG r6, 0xffffefff;
CHECKREG r7, 0xfffff111;
B0.L = 0x3001;
B1.L = 0x3003;
B2.L = 0x3005;
B3.L = 0x3007;
M0.L = 0x3009;
M1.L = 0x300b;
M2.L = 0x300d;
M3.L = 0x300f;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xffff3001;
CHECKREG r1, 0xffff3003;
CHECKREG r2, 0xffff3005;
CHECKREG r3, 0xffff3007;
CHECKREG r4, 0xffff3009;
CHECKREG r5, 0xffff300B;
CHECKREG r6, 0xffff300d;
CHECKREG r7, 0xffff300f;
B0.L = 0x0110;
B1.L = 0x1110;
B2.L = 0x2220;
B3.L = 0x3330;
M0.L = 0x4440;
M1.L = 0x5550;
M2.L = 0x6660;
M3.L = 0x7770;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xffff0110;
CHECKREG r1, 0xffff1110;
CHECKREG r2, 0xffff2220;
CHECKREG r3, 0xffff3330;
CHECKREG r4, 0xffff4440;
CHECKREG r5, 0xffff5550;
CHECKREG r6, 0xffff6660;
CHECKREG r7, 0xffff7770;
B0.L = 0xf880;
B1.L = 0xfaa0;
B2.L = 0xfbb0;
B3.L = 0xfcc0;
M0.L = 0xfdd0;
M1.L = 0xfee0;
M2.L = 0xfff0;
M3.L = 0xf110;
R0 = B0;
R1 = B1;
R2 = B2;
R3 = B3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0xfffff880;
CHECKREG r1, 0xfffffaa0;
CHECKREG r2, 0xfffffbb0;
CHECKREG r3, 0xfffffcc0;
CHECKREG r4, 0xfffffdd0;
CHECKREG r5, 0xfffffee0;
CHECKREG r6, 0xfffffff0;
CHECKREG r7, 0xfffff110;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,978 | sim/testsuite/bfin/se_loop_nest_ppm.S | //Original:/proj/frio/dv/testcases/seq/se_loop_nest_ppm/se_loop_nest_ppm.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x4 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
LSETUP ( l0s , l0s ) LC1 = P1;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l1s , l1e ) LC0 = P0;
LSETUP ( l1e , l1e ) LC1 = P1;
l1s:R5 += 1;
l1e:[ -- SP ] = ( R7:5 );
LSETUP ( l2s , l2e ) LC0 = P0;
LSETUP ( l2e , l2e ) LC1 = P1;
l2s:R5 += 1;
R6 += 2;
l2e:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
LSETUP ( l3e , l3e ) LC1 = P1;
l3s:R5 += 1;
R6 += 2;
R7 += 3;
l3e:[ -- SP ] = ( R7:5 );
LSETUP ( l4s , l4e ) LC0 = P0;
LSETUP ( l4e , l4e ) LC1 = P1;
l4s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
l4e:[ -- SP ] = ( R7:4 );
LSETUP ( l5s , l5e ) LC0 = P0;
LSETUP ( l5e , l5e ) LC1 = P1;
l5s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
l5e:[ -- SP ] = ( R7:4 );
LSETUP ( l6s , l6e ) LC0 = P0;
LSETUP ( l6e , l6e ) LC1 = P1;
l6s:R5 += 1;
R6 += 2;
R7 += 3;
R4 += 4;
R5 += 3;
R7 += 5;
l6e:[ -- SP ] = ( R7:4 );
NOP;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 2,538 | sim/testsuite/bfin/s30.s | // Test signbits40
# mach: bfin
.include "testutils.inc"
start
// positive value in accum, smaller than 1.0
A1 = A0 = 0;
R0.L = 0xffff;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0x8000 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// neg value in accum, larger than -1.0
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0xffff;
A0.w = R0;
R0.L = 0x00ff;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
// positive value in accum, larger than 1.0
A1 = A0 = 0;
R0.L = 0xffff;
R0.H = 0xffff;
A0.w = R0;
R0.L = 0x000f;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// negative value in accum, smaller than -1.0
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
// no normalization
A1 = A0 = 0;
R0.L = 0xfffa;
R0.H = 0x7fff;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x7fff ); DBGA ( R4.L , 0xfffa );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// no normalization (-1.0)
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x8000;
A0.w = R0;
R0.L = 0x00ff;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
// norm by 1
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x8000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x4000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
// norm by 1
A1 = A0 = 0;
R0.L = 0x0000;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x00ff;
A0.x = R0;
R5.L = SIGNBITS A0;
_DBG R5;
A0 = ASHIFT A0 BY R5.L;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x8000 ); DBGA ( R4.L , 0x0000 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,827 | sim/testsuite/bfin/dsp_d1.s | /* DAG test program.
* Test circular buffers
*/
# mach: bfin
.include "testutils.inc"
start
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x10 (X);
M1 = 8 (X);
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x10 (X);
M1 = -4 (X);
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x000c );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2
DBGA ( R1.L , 0x0008 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 ++ M1 ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x000c );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x8 (X);
R0 = [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0 = [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x8 (X);
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0002 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0006 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0.L = W [ I0 ++ ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0002 );
loadsym I0, foo;
loadsym B0, foo;
loadsym R2, foo;
L0 = 0x8 (X);
R0 = [ I0 -- ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
R0 = [ I0 -- ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0000 );
R0 = [ I0 -- ];
R7 = I0;
R1 = R7 - R2;
DBGA ( R1.L , 0x0004 );
pass
.data
foo:
.space (0x10);
|
tactcomplabs/xbgas-binutils-gdb | 3,002 | sim/testsuite/bfin/c_dsp32shift_bxor.s | //Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp
// Spec Reference: dsp32shift bxor
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
R1 = 58;
A0 = R1;
ASTAT = R0;
imm32 r0, 0x12345678;
imm32 r1, 0x22334455;
imm32 r2, 0x66778890;
imm32 r3, 0xaabbccdd;
imm32 r4, 0x34567890;
imm32 r5, 0xa2d3d5f6;
imm32 r6, 0x456bda06;
imm32 r7, 0x56789abc;
R0.L = CC = BXORSHIFT( A0 , R0 );
R1.L = CC = BXORSHIFT( A0 , R1 );
R2.L = CC = BXORSHIFT( A0 , R2 );
R3.L = CC = BXORSHIFT( A0 , R3 );
R4.L = CC = BXORSHIFT( A0 , R4 );
R5.L = CC = BXORSHIFT( A0 , R5 );
R6.L = CC = BXORSHIFT( A0 , R6 );
R7.L = CC = BXORSHIFT( A0 , R7 );
CHECKREG r0, 0x12340001;
CHECKREG r1, 0x22330001;
CHECKREG r2, 0x66770000;
CHECKREG r3, 0xAABB0001;
CHECKREG r4, 0x34560000;
CHECKREG r5, 0xA2D30000;
CHECKREG r6, 0x456B0000;
CHECKREG r7, 0x56780001;
imm32 r0, 0xa1001001;
imm32 r1, 0x1b001001;
imm32 r2, 0x11c01002;
imm32 r3, 0x110d1003;
imm32 r4, 0x1100e004;
imm32 r5, 0x11001f05;
imm32 r6, 0x11001006;
imm32 r7, 0x11001001;
R5.L = CC = BXORSHIFT( A0 , R0 );
R4.L = CC = BXORSHIFT( A0 , R1 );
R2.L = CC = BXORSHIFT( A0 , R2 );
R7.L = CC = BXORSHIFT( A0 , R3 );
R0.L = CC = BXORSHIFT( A0 , R4 );
R1.L = CC = BXORSHIFT( A0 , R5 );
R3.L = CC = BXORSHIFT( A0 , R6 );
R6.L = CC = BXORSHIFT( A0 , R7 );
CHECKREG r0, 0xA1000000;
CHECKREG r1, 0x1B000000;
CHECKREG r2, 0x11C00001;
CHECKREG r3, 0x110D0000;
CHECKREG r4, 0x11000000;
CHECKREG r5, 0x11000001;
CHECKREG r6, 0x11000000;
CHECKREG r7, 0x11000001;
imm32 r0, 0xa2001001;
imm32 r1, 0x1b341001;
imm32 r2, 0x71c01002;
imm32 r3, 0x810d1003;
imm32 r4, 0x1600e004;
imm32 r5, 0x41001405;
imm32 r6, 0x31003006;
imm32 r7, 0x21004671;
R2.L = CC = BXOR( A0 , R0 );
R3.L = CC = BXOR( A0 , R1 );
R5.L = CC = BXOR( A0 , R2 );
R6.L = CC = BXOR( A0 , R3 );
R0.L = CC = BXOR( A0 , R4 );
R1.L = CC = BXOR( A0 , R5 );
R7.L = CC = BXOR( A0 , R6 );
R4.L = CC = BXOR( A0 , R7 );
CHECKREG r0, 0xA2000000;
CHECKREG r1, 0x1B340000;
CHECKREG r2, 0x71C00000;
CHECKREG r3, 0x810D0000;
CHECKREG r4, 0x16000000;
CHECKREG r5, 0x41000000;
CHECKREG r6, 0x31000001;
CHECKREG r7, 0x21000000;
imm32 r0, 0x4a502001;
imm32 r1, 0x6b343001;
imm32 r2, 0x71c04002;
imm32 r3, 0x810d5003;
imm32 r4, 0x5600e004;
imm32 r5, 0x47001405;
imm32 r6, 0x91003006;
imm32 r7, 0xa1004671;
A1 = R3;
R0.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R1.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R2.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R3.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R4.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R5.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R6.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
R7.L = CC = BXOR( A0 , A1, CC );
A0 = BXORSHIFT( A0 , A1, CC );
CHECKREG r0, 0x4A500001;
CHECKREG r1, 0x6B340000;
CHECKREG r2, 0x71C00000;
CHECKREG r3, 0x810D0000;
CHECKREG r4, 0x56000001;
CHECKREG r5, 0x47000000;
CHECKREG r6, 0x91000001;
CHECKREG r7, 0xA1000001;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,103 | sim/testsuite/bfin/c_dsp32shiftim_ahalf_ln_s.s | //Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp
// Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated
# mach: bfin
.include "testutils.inc"
start
// Ashift : neg data, count (+)=left (half reg)
// d_lo = ashft (d_lo BY d_lo)
// RLx by RLx
imm32 r0, 0x1000c000;
imm32 r1, 0x1000c001;
imm32 r2, 0x1000c002;
imm32 r3, 0x1000c003;
imm32 r4, 0x1000c004;
imm32 r5, 0x1000c005;
imm32 r6, 0x1000c006;
imm32 r7, 0x1000c007;
R0.L = R0.L << 1 (S);
R1.L = R1.L << 1 (S);
R2.L = R2.L << 1 (S);
R3.L = R3.L << 1 (S);
R4.L = R4.L << 1 (S);
R5.L = R5.L << 1 (S);
R6.L = R6.L << 1 (S);
R7.L = R7.L << 1 (S);
CHECKREG r0, 0x10008000;
CHECKREG r1, 0x10008002;
CHECKREG r2, 0x10008004;
CHECKREG r3, 0x10008006;
CHECKREG r4, 0x10008008;
CHECKREG r5, 0x1000800A;
CHECKREG r6, 0x1000800C;
CHECKREG r7, 0x1000800E;
imm32 r0, 0x20008001;
imm32 r1, 0x20000001;
imm32 r2, 0x2000d002;
imm32 r3, 0x2000e003;
imm32 r4, 0x2000f004;
imm32 r5, 0x2000c005;
imm32 r6, 0x2000d006;
imm32 r7, 0x2000e007;
R7.L = R0.L << 1 (S);
R6.L = R1.L << 1 (S);
R5.L = R2.L << 1 (S);
R4.L = R3.L << 1 (S);
R3.L = R4.L << 1 (S);
R2.L = R5.L << 1 (S);
R1.L = R6.L << 1 (S);
R0.L = R7.L << 1 (S);
imm32 r0, 0x3000c001;
imm32 r1, 0x3000d001;
imm32 r2, 0x3000000f;
imm32 r3, 0x3000e003;
imm32 r4, 0x3000f004;
imm32 r5, 0x3000f005;
imm32 r6, 0x3000f006;
imm32 r7, 0x3000f007;
R6.L = R0.L << 12 (S);
R7.L = R1.L << 12 (S);
R5.L = R2.L << 12 (S);
R4.L = R3.L << 12 (S);
R3.L = R4.L << 12 (S);
R2.L = R5.L << 12 (S);
R1.L = R6.L << 12 (S);
R0.L = R7.L << 12 (S);
CHECKREG r1, 0x30008000;
CHECKREG r0, 0x30008000;
CHECKREG r2, 0x30007FFF;
CHECKREG r3, 0x30008000;
CHECKREG r4, 0x30008000;
CHECKREG r5, 0x30007FFF;
CHECKREG r6, 0x30008000;
CHECKREG r7, 0x30008000;
imm32 r0, 0x40009001;
imm32 r1, 0x4000a001;
imm32 r2, 0x4000b002;
imm32 r3, 0x40000010;
imm32 r4, 0x4000c004;
imm32 r5, 0x4000d005;
imm32 r6, 0x4000e006;
imm32 r7, 0x4000f007;
R5.L = R0.L << 13 (S);
R6.L = R1.L << 13 (S);
R7.L = R2.L << 13 (S);
R0.L = R3.L << 13 (S);
R1.L = R4.L << 13 (S);
R2.L = R5.L << 13 (S);
R3.L = R6.L << 13 (S);
R4.L = R7.L << 13 (S);
CHECKREG r0, 0x40007FFF;
CHECKREG r1, 0x40008000;
CHECKREG r2, 0x40008000;
CHECKREG r3, 0x40008000;
CHECKREG r4, 0x40008000;
CHECKREG r5, 0x40008000;
CHECKREG r6, 0x40008000;
CHECKREG r7, 0x40008000;
imm32 r0, 0x00005000;
imm32 r1, 0x00015000;
imm32 r2, 0x00025000;
imm32 r3, 0x00035000;
imm32 r4, 0x00045000;
imm32 r5, 0x00055000;
imm32 r6, 0x00065000;
imm32 r7, 0x00075500;
R0.L = R0.H << 10 (S);
R1.L = R1.H << 10 (S);
R2.L = R2.H << 10 (S);
R3.L = R3.H << 10 (S);
R4.L = R4.H << 10 (S);
R5.L = R5.H << 10 (S);
R6.L = R6.H << 10 (S);
R7.L = R7.H << 10 (S);
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00010400;
CHECKREG r2, 0x00020800;
CHECKREG r3, 0x00030C00;
CHECKREG r4, 0x00041000;
CHECKREG r5, 0x00051400;
CHECKREG r6, 0x00061800;
CHECKREG r7, 0x00071C00;
imm32 r0, 0x90010000;
imm32 r1, 0x90010001;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R2.L = R0.H << 11 (S);
R3.L = R1.H << 11 (S);
R4.L = R2.H << 11 (S);
R5.L = R3.H << 11 (S);
R6.L = R4.H << 11 (S);
R7.L = R5.H << 11 (S);
R0.L = R6.H << 11 (S);
R1.L = R7.H << 11 (S);
CHECKREG r0, 0x90018000;
CHECKREG r1, 0x90018000;
CHECKREG r2, 0x90028000;
CHECKREG r3, 0x90038000;
CHECKREG r4, 0x90048000;
CHECKREG r5, 0x90058000;
CHECKREG r6, 0x90068000;
CHECKREG r7, 0x90078000;
imm32 r0, 0xa0010600;
imm32 r1, 0xa0010600;
imm32 r2, 0xa002060f;
imm32 r3, 0xa0030600;
imm32 r4, 0xa0040600;
imm32 r5, 0xa0050600;
imm32 r6, 0xa0060600;
imm32 r7, 0xa0070600;
R0.L = R0.H << 12 (S);
R1.L = R1.H << 12 (S);
R2.L = R2.H << 12 (S);
R3.L = R3.H << 12 (S);
R4.L = R4.H << 12 (S);
R5.L = R5.H << 12 (S);
R6.L = R6.H << 12 (S);
R7.L = R7.H << 12 (S);
CHECKREG r0, 0xA0018000;
CHECKREG r1, 0xA0018000;
CHECKREG r2, 0xA0028000;
CHECKREG r3, 0xA0038000;
CHECKREG r4, 0xA0048000;
CHECKREG r5, 0xA0058000;
CHECKREG r6, 0xA0068000;
CHECKREG r7, 0xA0078000;
imm32 r0, 0xc0010701;
imm32 r1, 0xc0010701;
imm32 r2, 0xc0020702;
imm32 r3, 0xc0030710;
imm32 r4, 0xc0040704;
imm32 r5, 0xc0050705;
imm32 r6, 0xc0060706;
imm32 r7, 0xc0070707;
R0.L = R0.H << 13 (S);
R1.L = R1.H << 13 (S);
R2.L = R2.H << 13 (S);
R3.L = R3.H << 13 (S);
R4.L = R4.H << 13 (S);
R5.L = R5.H << 13 (S);
R6.L = R6.H << 13 (S);
R7.L = R7.H << 13 (S);
CHECKREG r0, 0xC0018000;
CHECKREG r1, 0xC0018000;
CHECKREG r2, 0xC0028000;
CHECKREG r3, 0xC0038000;
CHECKREG r4, 0xC0048000;
CHECKREG r5, 0xC0058000;
CHECKREG r6, 0xC0068000;
CHECKREG r7, 0xC0078000;
imm32 r0, 0x00008000;
imm32 r1, 0x00008001;
imm32 r2, 0x00008002;
imm32 r3, 0x00008003;
imm32 r4, 0x00008004;
imm32 r5, 0x00008005;
imm32 r6, 0x00008006;
imm32 r7, 0x00008007;
R0.H = R0.L << 0 (S);
R1.H = R1.L << 1 (S);
R2.H = R2.L << 2 (S);
R3.H = R3.L << 3 (S);
R4.H = R4.L << 4 (S);
R5.H = R5.L << 5 (S);
R6.H = R6.L << 6 (S);
R7.H = R7.L << 7 (S);
CHECKREG r0, 0x80008000;
CHECKREG r1, 0x80008001;
CHECKREG r2, 0x80008002;
CHECKREG r3, 0x80008003;
CHECKREG r4, 0x80008004;
CHECKREG r5, 0x80008005;
CHECKREG r6, 0x80008006;
CHECKREG r7, 0x80008007;
imm32 r0, 0x0000d001;
imm32 r1, 0x00000001;
imm32 r2, 0x0000d002;
imm32 r3, 0x0000d003;
imm32 r4, 0x0000d004;
imm32 r5, 0x0000d005;
imm32 r6, 0x0000d006;
imm32 r7, 0x0000d007;
R2.H = R0.L << 8 (S);
R3.H = R1.L << 9 (S);
R4.H = R2.L << 10 (S);
R5.H = R3.L << 11 (S);
R6.H = R4.L << 12 (S);
R7.H = R5.L << 13 (S);
R0.H = R6.L << 14 (S);
R1.H = R7.L << 15 (S);
CHECKREG r0, 0x8000D001;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x8000D002;
CHECKREG r3, 0x0200D003;
CHECKREG r4, 0x8000D004;
CHECKREG r5, 0x8000D005;
CHECKREG r6, 0x8000D006;
CHECKREG r7, 0x8000D007;
imm32 r0, 0x0000e001;
imm32 r1, 0x0000e001;
imm32 r2, 0x0000000f;
imm32 r3, 0x0000e003;
imm32 r4, 0x0000e004;
imm32 r5, 0x0000e005;
imm32 r6, 0x0000e006;
imm32 r7, 0x0000e007;
R0.H = R0.L << 12 (S);
R1.H = R1.L << 12 (S);
R2.H = R2.L << 12 (S);
R3.H = R3.L << 12 (S);
R4.H = R4.L << 12 (S);
R5.H = R5.L << 12 (S);
R6.H = R6.L << 12 (S);
R7.H = R7.L << 12 (S);
CHECKREG r0, 0x8000E001;
CHECKREG r1, 0x8000E001;
CHECKREG r2, 0x7FFF000F;
CHECKREG r3, 0x8000E003;
CHECKREG r4, 0x8000E004;
CHECKREG r5, 0x8000E005;
CHECKREG r6, 0x8000E006;
CHECKREG r7, 0x8000E007;
imm32 r0, 0x0000f001;
imm32 r1, 0x0000f001;
imm32 r2, 0x0000f002;
imm32 r3, 0x00000010;
imm32 r4, 0x0000f004;
imm32 r5, 0x0000f005;
imm32 r6, 0x0000f006;
imm32 r7, 0x0000f007;
R5.H = R0.L << 13 (S);
R6.H = R1.L << 13 (S);
R7.H = R2.L << 13 (S);
R0.H = R3.L << 13 (S);
R1.H = R4.L << 13 (S);
R2.H = R5.L << 13 (S);
R3.H = R6.L << 13 (S);
R4.H = R7.L << 13 (S);
CHECKREG r0, 0x7FFFF001;
CHECKREG r1, 0x8000F001;
CHECKREG r2, 0x8000F002;
CHECKREG r3, 0x80000010;
CHECKREG r4, 0x8000F004;
CHECKREG r5, 0x8000F005;
CHECKREG r6, 0x8000F006;
CHECKREG r7, 0x8000F007;
// d_lo = ashift (d_hi BY d_lo)
// RHx by RLx
imm32 r0, 0x90000000;
imm32 r1, 0x90010000;
imm32 r2, 0x90020000;
imm32 r3, 0x90030000;
imm32 r4, 0x90040000;
imm32 r5, 0x90050000;
imm32 r6, 0x90060000;
imm32 r7, 0x90070000;
R4.H = R0.H << 10 (S);
R5.H = R1.H << 10 (S);
R6.H = R2.H << 10 (S);
R7.H = R3.H << 10 (S);
R0.H = R4.H << 10 (S);
R1.H = R5.H << 10 (S);
R2.H = R6.H << 10 (S);
R3.H = R7.H << 10 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xa0010000;
imm32 r1, 0x00010001;
imm32 r2, 0xa0020000;
imm32 r3, 0xa0030000;
imm32 r4, 0xa0040000;
imm32 r5, 0xa0050000;
imm32 r6, 0xa0060000;
imm32 r7, 0xa0070000;
R7.H = R0.H << 11 (S);
R0.H = R1.H << 11 (S);
R1.H = R2.H << 11 (S);
R2.H = R3.H << 11 (S);
R3.H = R4.H << 11 (S);
R4.H = R5.H << 11 (S);
R5.H = R6.H << 11 (S);
R6.H = R7.H << 11 (S);
CHECKREG r0, 0x08000000;
CHECKREG r1, 0x80000001;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R6.H = R0.H << 12 (S);
R7.H = R1.H << 12 (S);
R0.H = R2.H << 12 (S);
R1.H = R3.H << 12 (S);
R2.H = R4.H << 12 (S);
R3.H = R5.H << 12 (S);
R4.H = R6.H << 12 (S);
R5.H = R7.H << 12 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x8000000F;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
imm32 r0, 0xd0010000;
imm32 r1, 0xd0010000;
imm32 r2, 0xd0020000;
imm32 r3, 0xd0030010;
imm32 r4, 0xd0040000;
imm32 r5, 0xd0050000;
imm32 r6, 0xd0060000;
imm32 r7, 0xd0070000;
R5.H = R0.H << 3 (S);
R6.H = R1.H << 3 (S);
R7.H = R2.H << 3 (S);
R0.H = R3.H << 3 (S);
R1.H = R4.H << 3 (S);
R2.H = R5.H << 3 (S);
R3.H = R6.H << 3 (S);
R4.H = R7.H << 3 (S);
CHECKREG r0, 0x80000000;
CHECKREG r1, 0x80000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x80000010;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,056 | sim/testsuite/bfin/c_dsp32alu_sgn.s | //Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp
// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x456789ab;
imm32 r1, 0x6689abcd;
imm32 r2, 0x47445555;
imm32 r3, 0x68667777;
R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L;
R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L;
R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L;
R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L;
CHECKREG r4, 0xCF12CF12;
CHECKREG r5, 0x12561256;
CHECKREG r6, 0x9C999C99;
CHECKREG r7, 0xDFDDDFDD;
imm32 r0, 0x496789ab;
imm32 r1, 0x6489abcd;
imm32 r2, 0x4b445555;
imm32 r3, 0x6c647777;
imm32 r4, 0x8d889999;
imm32 r5, 0xaeaa4bbb;
imm32 r6, 0xcfccd44d;
imm32 r7, 0xe1eefff4;
R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L;
R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L;
R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L;
R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L;
CHECKREG r0, 0x27212721;
CHECKREG r1, 0xFA65FA65;
CHECKREG r2, 0xA419A419;
CHECKREG r3, 0xE1E2E1E2;
pass
|
tactcomplabs/xbgas-binutils-gdb | 3,544 | sim/testsuite/bfin/c_dsp32mac_dr_a1_is.s | //Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp
// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int)
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0xa3545abd;
imm32 r1, 0xbdbcfec7;
imm32 r2, 0xc1248679;
imm32 r3, 0xd0069007;
imm32 r4, 0xefbc4569;
imm32 r5, 0xcd35500b;
imm32 r6, 0xe00c800d;
imm32 r7, 0xf78e900f;
R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2);
R3 = A1.w;
R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x80008679;
CHECKREG r3, 0xE8CA9815;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xE3B4A529;
CHECKREG r6, 0x8000800D;
CHECKREG r7, 0xE4C27FD1;
// The result accumulated in A1, and stored to a reg half (MNOP)
imm32 r0, 0x63548abd;
imm32 r1, 0x7dbcfec7;
imm32 r2, 0xC5885679;
imm32 r3, 0xC5880000;
imm32 r4, 0xcfbc4569;
imm32 r5, 0xd235c00b;
imm32 r6, 0xe00ca00d;
imm32 r7, 0x678e700f;
R0.H = ( A1 = R1.L * R0.L ) (ISS2);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (ISS2);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (ISS2);
R5 = A1.w;
R6.H = ( A1 -= R6.H * R7.H ) (ISS2);
R7 = A1.w;
CHECKREG r0, 0x7FFF8ABD;
CHECKREG r1, 0x008F5EEB;
CHECKREG r2, 0x80005679;
CHECKREG r3, 0xECCF6C33;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xE0C07F1F;
CHECKREG r6, 0x8000A00D;
CHECKREG r7, 0xEDAD6477;
// The result accumulated in A1 , and stored to a reg half (MNOP)
imm32 r0, 0x5354babd;
imm32 r1, 0x6dbcdec7;
imm32 r2, 0x7124e679;
imm32 r3, 0x80067007;
imm32 r4, 0x9fbc4569;
imm32 r5, 0xa235900b;
imm32 r6, 0xb00c300d;
imm32 r7, 0xc78ea00f;
R0.H = A1 , A0 -= R1.L * R0.L (ISS2);
R1 = A1.w;
R2.H = A1 , A0 += R2.H * R3.L (ISS2);
R3 = A1.w;
R4.H = A1 , A0 -= R4.H * R5.H (ISS2);
R5 = A1.w;
R6.H = A1 , A0 = R6.L * R7.H (ISS2);
R7 = A1.w;
CHECKREG r0, 0x8000BABD;
CHECKREG r1, 0xEDAD6477;
CHECKREG r2, 0x8000E679;
CHECKREG r3, 0xEDAD6477;
CHECKREG r4, 0x80004569;
CHECKREG r5, 0xEDAD6477;
CHECKREG r6, 0x8000300D;
CHECKREG r7, 0xEDAD6477;
// The result accumulated in A1 , and stored to a reg half
imm32 r0, 0x33545abd;
imm32 r1, 0x5dbcfec7;
imm32 r2, 0x71245679;
imm32 r3, 0x90060007;
imm32 r4, 0xafbc4569;
imm32 r5, 0xd235900b;
imm32 r6, 0xc00ca00d;
imm32 r7, 0x678ed00f;
R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2);
R1 = A1.w;
R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2);
R5 = A1.w;
R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2);
R7 = A1.w;
CHECKREG r0, 0x80005ABD;
CHECKREG r1, 0xFF910EEB;
CHECKREG r2, 0x7FFF5679;
CHECKREG r3, 0x303725C1;
CHECKREG r4, 0x7FFF4569;
CHECKREG r5, 0x5D60D8AD;
CHECKREG r6, 0x7FFFA00D;
CHECKREG r7, 0x43823355;
// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
imm32 r0, 0x92005ABD;
imm32 r1, 0x09300000;
imm32 r2, 0x56749679;
imm32 r3, 0x30A95000;
imm32 r4, 0xa0009669;
imm32 r5, 0x01000970;
imm32 r6, 0xdf45609D;
imm32 r7, 0x12345679;
R0.H = ( A1 += R1.L * R0.L ) (M,ISS2);
R1 = A1.w;
R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2);
R3 = A1.w;
R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2);
R5 = A1.w;
R6.H = ( A1 = R6.H * R7.H ) (M,ISS2);
R7 = A1.w;
CHECKREG r0, 0x7FFF5ABD;
CHECKREG r1, 0x43823355;
CHECKREG r2, 0x7FFF9679;
CHECKREG r3, 0x57912D74;
CHECKREG r4, 0x7FFF9669;
CHECKREG r5, 0x5B1B2D74;
CHECKREG r6, 0x8000609D;
CHECKREG r7, 0xFDAC3404;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,640 | sim/testsuite/bfin/c_alu2op_shadd_1.s | //Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp
// Spec Reference: alu2op shadd 1
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R1 = ( R1 + R0 ) << 1;
R2 = ( R2 + R0 ) << 1;
R3 = ( R3 + R0 ) << 1;
R4 = ( R4 + R0 ) << 1;
R5 = ( R5 + R0 ) << 1;
R6 = ( R6 + R0 ) << 1;
R7 = ( R7 + R0 ) << 1;
R0 = ( R0 + R0 ) << 1;
CHECKREG r0, 0x0D05E640;
CHECKREG r1, 0x2AE5A010;
CHECKREG r2, 0x4D05C232;
CHECKREG r3, 0x6F25E454;
CHECKREG r4, 0x11460676;
CHECKREG r5, 0x33662898;
CHECKREG r6, 0x55864ABA;
CHECKREG r7, 0x77A66CDC;
imm32 r0, 0x03457290;
imm32 r1, 0x12345278;
imm32 r2, 0x23456289;
imm32 r3, 0x3456729a;
imm32 r4, 0x856782ab;
imm32 r5, 0x967892bc;
imm32 r6, 0xa789a2cd;
imm32 r7, 0xb89ab2de;
R0 = ( R0 + R1 ) << 1;
R2 = ( R2 + R1 ) << 1;
R3 = ( R3 + R1 ) << 1;
R4 = ( R4 + R1 ) << 1;
R5 = ( R5 + R1 ) << 1;
R6 = ( R6 + R1 ) << 1;
R7 = ( R7 + R1 ) << 1;
R1 = ( R1 + R1 ) << 1;
CHECKREG r0, 0x2AF38A10;
CHECKREG r1, 0x48D149E0;
CHECKREG r2, 0x6AF36A02;
CHECKREG r3, 0x8D158A24;
CHECKREG r4, 0x2F37AA46;
CHECKREG r5, 0x5159CA68;
CHECKREG r6, 0x737BEA8A;
CHECKREG r7, 0x959E0AAC;
imm32 r0, 0x03457930;
imm32 r1, 0x12345638;
imm32 r2, 0x23456739;
imm32 r3, 0x3456783a;
imm32 r4, 0x8567893b;
imm32 r5, 0x96789a3c;
imm32 r6, 0xa789ab3d;
imm32 r7, 0xb89abc3e;
R0 = ( R0 + R2 ) << 1;
R1 = ( R1 + R2 ) << 1;
R3 = ( R3 + R2 ) << 1;
R4 = ( R4 + R2 ) << 1;
R5 = ( R5 + R2 ) << 1;
R6 = ( R6 + R2 ) << 1;
R7 = ( R7 + R2 ) << 1;
R2 = ( R2 + R2 ) << 1;
CHECKREG r0, 0x4D15C0D2;
CHECKREG r1, 0x6AF37AE2;
CHECKREG r2, 0x8D159CE4;
CHECKREG r3, 0xAF37BEE6;
CHECKREG r4, 0x5159E0E8;
CHECKREG r5, 0x737C02EA;
CHECKREG r6, 0x959E24EC;
CHECKREG r7, 0xB7C046EE;
imm32 r0, 0x04457990;
imm32 r1, 0x14345678;
imm32 r2, 0x24456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x846789ab;
imm32 r5, 0x94789abc;
imm32 r6, 0xa489abcd;
imm32 r7, 0xb49abcde;
R0 = ( R0 + R3 ) << 1;
R1 = ( R1 + R3 ) << 1;
R2 = ( R2 + R3 ) << 1;
R4 = ( R4 + R3 ) << 1;
R5 = ( R5 + R3 ) << 1;
R6 = ( R6 + R3 ) << 1;
R7 = ( R7 + R3 ) << 1;
R3 = ( R3 + R3 ) << 1;
CHECKREG r0, 0x7137E454;
CHECKREG r1, 0x91159E24;
CHECKREG r2, 0xB137C046;
CHECKREG r3, 0xD159E268;
CHECKREG r4, 0x717C048A;
CHECKREG r5, 0x919E26AC;
CHECKREG r6, 0xB1C048CE;
CHECKREG r7, 0xD1E26AF0;
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R0 = ( R0 + R4 ) << 1;
R1 = ( R1 + R4 ) << 1;
R2 = ( R2 + R4 ) << 1;
R3 = ( R3 + R4 ) << 1;
R5 = ( R5 + R4 ) << 1;
R6 = ( R6 + R4 ) << 1;
R7 = ( R7 + R4 ) << 1;
R4 = ( R4 + R4 ) << 1;
CHECKREG r0, 0x11460676;
CHECKREG r1, 0x2F25C046;
CHECKREG r2, 0x5145E268;
CHECKREG r3, 0x7366048A;
CHECKREG r4, 0x158626AC;
CHECKREG r5, 0x37A648CE;
CHECKREG r6, 0x59C66AF0;
CHECKREG r7, 0x7BE68D12;
imm32 r0, 0x03457290;
imm32 r1, 0x12345278;
imm32 r2, 0x23456289;
imm32 r3, 0x3456729a;
imm32 r4, 0x856782ab;
imm32 r5, 0x967892bc;
imm32 r6, 0xa789a2cd;
imm32 r7, 0xb89ab2de;
R0 = ( R0 + R5 ) << 1;
R1 = ( R1 + R5 ) << 1;
R2 = ( R2 + R5 ) << 1;
R3 = ( R3 + R5 ) << 1;
R4 = ( R4 + R5 ) << 1;
R6 = ( R6 + R5 ) << 1;
R7 = ( R7 + R5 ) << 1;
R5 = ( R5 + R5 ) << 1;
CHECKREG r0, 0x337C0A98;
CHECKREG r1, 0x5159CA68;
CHECKREG r2, 0x737BEA8A;
CHECKREG r3, 0x959E0AAC;
CHECKREG r4, 0x37C02ACE;
CHECKREG r5, 0x59E24AF0;
CHECKREG r6, 0x7C046B12;
CHECKREG r7, 0x9E268B34;
imm32 r0, 0x03457930;
imm32 r1, 0x12345638;
imm32 r2, 0x23456739;
imm32 r3, 0x3456783a;
imm32 r4, 0x8567893b;
imm32 r5, 0x96789a3c;
imm32 r6, 0xa789ab3d;
imm32 r7, 0xb89abc3e;
R0 = ( R0 + R6 ) << 1;
R1 = ( R1 + R6 ) << 1;
R2 = ( R2 + R6 ) << 1;
R3 = ( R3 + R6 ) << 1;
R4 = ( R4 + R6 ) << 1;
R5 = ( R5 + R6 ) << 1;
R7 = ( R7 + R6 ) << 1;
R6 = ( R6 + R6 ) << 1;
CHECKREG r0, 0x559E48DA;
CHECKREG r1, 0x737C02EA;
CHECKREG r2, 0x959E24EC;
CHECKREG r3, 0xB7C046EE;
CHECKREG r4, 0x59E268F0;
CHECKREG r5, 0x7C048AF2;
CHECKREG r6, 0x9E26ACF4;
CHECKREG r7, 0xC048CEF6;
imm32 r0, 0x04457990;
imm32 r1, 0x14345678;
imm32 r2, 0x24456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x846789ab;
imm32 r5, 0x94789abc;
imm32 r6, 0xa489abcd;
imm32 r7, 0xb49abcde;
R0 = ( R0 + R7 ) << 1;
R1 = ( R1 + R7 ) << 1;
R2 = ( R2 + R7 ) << 1;
R3 = ( R3 + R7 ) << 1;
R4 = ( R4 + R7 ) << 1;
R5 = ( R5 + R7 ) << 1;
R6 = ( R6 + R7 ) << 1;
R7 = ( R7 + R7 ) << 1;
CHECKREG r0, 0x71C06CDC;
CHECKREG r1, 0x919E26AC;
CHECKREG r2, 0xB1C048CE;
CHECKREG r3, 0xD1E26AF0;
CHECKREG r4, 0x72048D12;
CHECKREG r5, 0x9226AF34;
CHECKREG r6, 0xB248D156;
CHECKREG r7, 0xD26AF378;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,134 | sim/testsuite/bfin/c_alu2op_conv_xh.s | //Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp
// Spec Reference: alu2op convert xh
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.L (X);
R1 = R0.L (X);
R2 = R0.L (X);
R3 = R0.L (X);
R4 = R0.L (X);
R5 = R0.L (X);
R6 = R0.L (X);
R7 = R0.L (X);
CHECKREG r0, 0xFFFF9ABC;
CHECKREG r1, 0xFFFF9ABC;
CHECKREG r2, 0xFFFF9ABC;
CHECKREG r3, 0xFFFF9ABC;
CHECKREG r4, 0xFFFF9ABC;
CHECKREG r5, 0xFFFF9ABC;
CHECKREG r6, 0xFFFF9ABC;
CHECKREG r7, 0xFFFF9ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.L (X);
R2 = R1.L (X);
R3 = R1.L (X);
R4 = R1.L (X);
R5 = R1.L (X);
R6 = R1.L (X);
R7 = R1.L (X);
R1 = R1.L (X);
CHECKREG r0, 0x00004659;
CHECKREG r1, 0x00004659;
CHECKREG r2, 0x00004659;
CHECKREG r3, 0x00004659;
CHECKREG r4, 0x00004659;
CHECKREG r5, 0x00004659;
CHECKREG r6, 0x00004659;
CHECKREG r7, 0x00004659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.L (X);
R1 = R2.L (X);
R3 = R2.L (X);
R4 = R2.L (X);
R5 = R2.L (X);
R6 = R2.L (X);
R7 = R2.L (X);
R2 = R2.L (X);
CHECKREG r0, 0x00006789;
CHECKREG r1, 0x00006789;
CHECKREG r2, 0x00006789;
CHECKREG r3, 0x00006789;
CHECKREG r4, 0x00006789;
CHECKREG r5, 0x00006789;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x00006789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.L (X);
R1 = R3.L (X);
R2 = R3.L (X);
R4 = R3.L (X);
R5 = R3.L (X);
R6 = R3.L (X);
R7 = R3.L (X);
R3 = R3.L (X);
CHECKREG r0, 0x0000789A;
CHECKREG r1, 0x0000789A;
CHECKREG r2, 0x0000789A;
CHECKREG r3, 0x0000789A;
CHECKREG r4, 0x0000789A;
CHECKREG r5, 0x0000789A;
CHECKREG r6, 0x0000789A;
CHECKREG r7, 0x0000789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.L (X);
R1 = R4.L (X);
R2 = R4.L (X);
R3 = R4.L (X);
R4 = R4.L (X);
R5 = R4.L (X);
R6 = R4.L (X);
R7 = R4.L (X);
CHECKREG r0, 0xFFFFA9AB;
CHECKREG r1, 0xFFFFA9AB;
CHECKREG r2, 0xFFFFA9AB;
CHECKREG r3, 0xFFFFA9AB;
CHECKREG r4, 0xFFFFA9AB;
CHECKREG r5, 0xFFFFA9AB;
CHECKREG r6, 0xFFFFA9AB;
CHECKREG r7, 0xFFFFA9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.L (X);
R1 = R5.L (X);
R2 = R5.L (X);
R3 = R5.L (X);
R4 = R5.L (X);
R6 = R5.L (X);
R7 = R5.L (X);
R5 = R5.L (X);
CHECKREG r0, 0xFFFF9FBC;
CHECKREG r1, 0xFFFF9FBC;
CHECKREG r2, 0xFFFF9FBC;
CHECKREG r3, 0xFFFF9FBC;
CHECKREG r4, 0xFFFF9FBC;
CHECKREG r5, 0xFFFF9FBC;
CHECKREG r6, 0xFFFF9FBC;
CHECKREG r7, 0xFFFF9FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.L (X);
R1 = R6.L (X);
R2 = R6.L (X);
R3 = R6.L (X);
R4 = R6.L (X);
R5 = R6.L (X);
R7 = R6.L (X);
R6 = R6.L (X);
CHECKREG r0, 0xFFFFAECD;
CHECKREG r1, 0xFFFFAECD;
CHECKREG r2, 0xFFFFAECD;
CHECKREG r3, 0xFFFFAECD;
CHECKREG r4, 0xFFFFAECD;
CHECKREG r5, 0xFFFFAECD;
CHECKREG r6, 0xFFFFAECD;
CHECKREG r7, 0xFFFFAECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.L (X);
R1 = R7.L (X);
R2 = R7.L (X);
R3 = R7.L (X);
R4 = R7.L (X);
R5 = R7.L (X);
R6 = R7.L (X);
R7 = R7.L (X);
CHECKREG r0, 0xFFFFBC88;
CHECKREG r1, 0xFFFFBC88;
CHECKREG r2, 0xFFFFBC88;
CHECKREG r3, 0xFFFFBC88;
CHECKREG r4, 0xFFFFBC88;
CHECKREG r5, 0xFFFFBC88;
CHECKREG r6, 0xFFFFBC88;
CHECKREG r7, 0xFFFFBC88;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,753 | sim/testsuite/bfin/lmu_excpt_illaddr.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp
// Description: LMU illegal address exceptions
// Illegal core MMR: addr[19:16] != 0
// Illegal core MMR: Illegal peripheral
// Illegal core MMR: Illegal addr in peripheral
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
#ifndef SR_BASE
#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs
#endif
#ifndef A_SRAM_BASE
#define A_SRAM_BASE SR_BASE
#endif
#ifndef B_SRAM_BASE
#define B_SRAM_BASE SR_BASE + 0x100000
#endif
#ifndef I_SRAM_BASE
#define I_SRAM_BASE SR_BASE + 0x200000
#endif
#ifndef SCRATCH_SRAM_BASE
#define SCRATCH_SRAM_BASE SR_BASE + 0x300000
#endif
#ifndef A_SRAM_SIZE
#define A_SRAM_SIZE 0x4000
#endif
#ifndef B_SRAM_SIZE
#define B_SRAM_SIZE 0x4000
#endif
#ifndef I_SRAM_SIZE
#define I_SRAM_SIZE 0x4000
#endif
#ifndef SCRATCH_SRAM_SIZE
#define SCRATCH_SRAM_SIZE 0x1000
#endif
CHECK_INIT(p5, 0xE0000000);
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
WR_MMR_LABEL(EVT15, int15, p0, r1);
WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
// Set up CPLB
WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable
WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable
WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable
WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0);
CSYNC;
// Write fault addr MMR to known state
WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
// But first raise interrupt 15 so we will run in supervisor mode.
RAISE 15;
NOP;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
int15:
NOP;NOP;NOP;NOP;NOP;
//-------------------------------------------------------
// First do stores
//-------------------------------------------------------
//
// illegal core MMR: addr[19] !=0
LD32(p1, 0xFFE80000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X01: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: addr[18] !=0
LD32(p1, 0xFFE40000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X02: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: addr[17] !=0
LD32(p1, 0xFFE20000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X03: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: addr[16] !=0
LD32(p1, 0xFFE10000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X04: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal periperal (addr[15:12] > 8)
LD32(p1, 0xFFE09000);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X10: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 00
LD32(p1, 0xFFE00408);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X20: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 01
LD32(p1, 0xFFE01408);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X21: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 02
LD32(p1, 0xFFE02114);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X22: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 03
LD32(p1, 0xFFE03010);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X23: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 04
LD32(p1, 0xFFE04008);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X24: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 05
LD32(p1, 0xFFE05010);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X25: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 06
LD32(p1, 0xFFE06104);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X26: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 07
LD32(p1, 0xFFE07204);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X27: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!)
//-------------------------------------------------------
// illegal core MMR: illegal addr in peripheral 08
LD32(p1, 0xFFE08108);
LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X28: [ P1 ] = R1; // Exception should occur here
CHECKREG(r5,0x2e); // supv and EXCPT_PROT
CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address
CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!)
//-------------------------------------------------------
User:
dbg_pass;
//-------------------------------------------------------
handler:
R5 = SEQSTAT; // Get exception cause
// read and check fail addr (addr_which_causes_exception)
// should not be set for alignment exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
R7 = RETX; // get address of excepting instruction
// align the offending address
P1 = P2;
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
|
tactcomplabs/xbgas-binutils-gdb | 1,462 | sim/testsuite/bfin/stk3.s | // load up some registers.
// setup up a global pointer table and load some state.
// save the machine state and clear some of the values.
// then restore and assert some of the values to ensure that
// we maintain consitent machine state.
# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R1 = 2;
R2 = 3;
R3 = -7;
R4 = 4;
R5 = 5;
R6 = 6;
R7 = 7;
loadsym P0, a;
P1.L = 0x1000;
_DBG P0;
_DBG P1;
SP = P0;
FP = P0;
CALL try;
P1 = [ P0 ++ ];
P2 = [ P0 ++ ];
P0 += 4;
P4 = [ P0 ++ ];
P5 = [ P0 ++ ];
[ -- SP ] = ( R7:0, P5:0 );
_DBG SP;
_DBG FP;
R0 = R0 ^ R0;
R1 = R1 ^ R1;
R2 = R2 ^ R2;
R4 = R4 ^ R4;
R5 = R5 ^ R5;
R6 = R6 ^ R6;
R7 = R7 ^ R7;
( R7:0, P5:0 ) = [ SP ++ ];
DBGA ( R0.L , 1 );
DBGA ( R1.L , 2 );
DBGA ( R2.L , 3 );
DBGA ( R3.L , 0xfff9);
DBGA ( R4.L , 4 );
DBGA ( R5.L , 5 );
DBGA ( R6.L , 6 );
DBGA ( R7.L , 7 );
R0 = SP;
loadsym R1, a;
CC = R0 == R1;
IF !CC JUMP abrt;
R0 = FP;
CC = R0 == R1;
CC = R0 == R1;
IF !CC JUMP abrt;
pass
abrt:
fail;
try:
LINK 0;
[ -- SP ] = ( R7:0, P5:0 );
R7 = 0x1234 (X);
[ -- SP ] = R7;
CALL bar;
SP += 4;
( R7:0, P5:0 ) = [ SP ++ ];
UNLINK;
RTS;
bar:
LINK 0;
[ -- SP ] = ( R7:0, P5:0 );
R0 = [ FP + 8 ];
DBGA ( R0.L , 0x1234 );
( R7:0, P5:0 ) = [ SP ++ ];
UNLINK;
RTS;
.data
_gptab:
.dw 0x200
.dw 0x000
.dw 0x300
.dw 0x400
.dw 0x500
.dw 0x600
.space (0x100)
a:
.dw 1
.dw 2
.dw 3
.dw 4
.dw 5
.dw 6
.dw 7
.dw 8
.dw 9
.dw 0xa
|
tactcomplabs/xbgas-binutils-gdb | 6,835 | sim/testsuite/bfin/c_seq_ac_raise_mv_ppop.S | //Original:/proj/frio/dv/testcases/core/c_seq_ac_raise_mv_ppop/c_seq_ac_raise_mv_ppop.dsp
// Spec Reference: sequencer stage AC (raise + regmv + pushpopmultiple)
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(std.inc)
include(selfcheck.inc)
include(gen_int.inc)
INIT_R_REGS(0);
INIT_P_REGS(0);
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
//CHECK_INIT(p5, 0xe0000000);
include(symtable.inc)
CHECK_INIT_DEF(p5);
#ifndef STACKSIZE
#define STACKSIZE 0x10
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT15
#define EVT15 0xFFE0203C
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef ITABLE
#define ITABLE DATA_ADDR_1
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
//
BOOT:
// in reset mode now
LD32_LABEL(sp, KSTACK); // setup the stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT); // Setup Event Vectors and Handlers
LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R0 = -1; // Change this to mask interrupts (*)
[ P0 ] = R0; // IMASK
CSYNC;
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
// SUPERVISOR MODE & go to different RAISE in supervisor mode
// until the end of the test.
NOP; // Workaround for Bug 217
RTI;
//
// The Main Program
//
STARTUSER:
LD32_LABEL(sp, USTACK); // setup the stack pointer
FP = SP; // set frame pointer
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// PUT YOUR TEST HERE!
// PUSH
R0 = 0x01;
R1 = 0x02;
R2 = 0x03;
R3 = 0x04;
R4 = 0x05;
R5 = 0x06;
R6 = 0x07;
R7 = 0x08;
LD32(p1, 0x12345678);
LD32(p2, 0x05612496);
LD32(p3, 0xab5fd490);
LD32(p4, 0xa581bd94);
RAISE 2; // RTN
P1 = R1;
R2 = P1;
[ -- SP ] = ( R7:0 );
R1 = 0x12;
R2 = 0x13;
R3 = 0x14;
R4 = 0x15;
R5 = 0x16;
R6 = 0x17;
R7 = 0x18;
RAISE 5; // RTI
P2 = R2;
R3 = P2;
[ -- SP ] = ( R7:1 );
R2 = 0x23;
R3 = 0x24;
R4 = 0x25;
R5 = 0x26;
R6 = 0x27;
R7 = 0x28;
RAISE 6; // RTI
P3 = R3;
R4 = P3;
[ -- SP ] = ( R7:2 );
// POP
R0 = 0x00;
R1 = 0x00;
R2 = 0x00;
R3 = 0x00;
R4 = 0x00;
R5 = 0x00;
R6 = 0x00;
R7 = 0x00;
RAISE 7; // RTI
P4 = R4;
R5 = P4;
( R7:2 ) = [ SP ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000000);
CHECKREG(r2, 0x00000023);
CHECKREG(r3, 0x00000024);
CHECKREG(r4, 0x00000024);
CHECKREG(r5, 0x00000026);
CHECKREG(r6, 0x00000027);
CHECKREG(r7, 0x00000028);
RAISE 8; // RTI
P1 = R1;
R5 = P1;
( R7:1 ) = [ SP ++ ];
CHECKREG(r0, 0x00000000);
CHECKREG(r1, 0x00000012);
CHECKREG(r2, 0x00000013);
CHECKREG(r3, 0x00000013);
CHECKREG(r4, 0x00000015);
CHECKREG(r5, 0x00000016);
CHECKREG(r6, 0x00000017);
CHECKREG(r7, 0x00000018);
RAISE 9; // RTI
P2 = R2;
R5 = P2;
( R7:0 ) = [ SP ++ ];
CHECKREG(r0, 0x00000001);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000004);
CHECKREG(r4, 0x00000005);
CHECKREG(r5, 0x00000006);
CHECKREG(r6, 0x00000007);
CHECKREG(r7, 0x00000008);
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
CHECKREG(r0, 0x00000006);
CHECKREG(r1, 0x00000002);
CHECKREG(r2, 0x00000002);
CHECKREG(r3, 0x00000002);
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
EHANDLE: // Emulation Handler 0
RTE;
RHANDLE: // Reset Handler 1
RTI;
NHANDLE: // NMI Handler 2
I0 += 2;
RTN;
XHANDLE: // Exception Handler 3
R1 = 3;
RTX;
HWHANDLE: // HW Error Handler 5
I1 += 2;
RTI;
THANDLE: // Timer Handler 6
I2 += 2;
RTI;
I7HANDLE: // IVG 7 Handler
I3 += 2;
RTI;
I8HANDLE: // IVG 8 Handler
I0 += 2;
RTI;
I9HANDLE: // IVG 9 Handler
I0 += 2;
RTI;
I10HANDLE: // IVG 10 Handler
R7 = 10;
RTI;
I11HANDLE: // IVG 11 Handler
I0 = R0;
I1 = R1;
I2 = R2;
I3 = R3;
M0 = R4;
R0 = 11;
RTI;
I12HANDLE: // IVG 12 Handler
R1 = 12;
RTI;
I13HANDLE: // IVG 13 Handler
R2 = 13;
RTI;
I14HANDLE: // IVG 14 Handler
R3 = 14;
RTI;
I15HANDLE: // IVG 15 Handler
R4 = 15;
RTI;
NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 54,870 | sim/testsuite/bfin/se_undefinedinstruction2.S | //Original:/proj/frio/dv/testcases/seq/se_undefinedinstruction2/se_undefinedinstruction2.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
A0 = 0; // reset accumulators
A1 = 0;
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
r4 = p1;
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// count of UI's will be in r5, which was initialized to 0 by header
// 16 bit special cases COUNT = 830
.dw 0x10E ;
.dw 0x124 ;
.ifndef BFIN_HW
// XXX: hardware doesnt trigger illegal exception ?
.dw 0x125 ;
.endif
.dw 0x164 ;
.ifndef BFIN_HW
// XXX: hardware doesnt trigger illegal exception ?
.dw 0x165 ;
.endif
.dw 0x128 ;
.dw 0x129 ;
.dw 0x12A ;
.dw 0x12B ;
.dw 0x12C ;
.dw 0x12D ;
.dw 0x12E ;
.dw 0x12F ;
.dw 0x168 ;
.dw 0x169 ;
.dw 0x16A ;
.dw 0x16B ;
.dw 0x16C ;
.dw 0x16D ;
.dw 0x16E ;
.dw 0x16F ;
#if 0
// EMUDAT = [SP++]; is valid
.dw 0x13F ;
// [SP++] = EMUDAT; is valid
.dw 0x17F ;
#endif
.dw 0x486 ;
.dw 0x487 ;
.dw 0x210 ;
.dw 0x211 ;
.dw 0x212 ;
.dw 0x213 ;
.dw 0x214 ;
.dw 0x215 ;
.dw 0x216 ;
.dw 0x217 ;
.dw 0x305 ;
#if 0
// Not documented, but hardware takes them
// CC = <reserved astat>
.dw 0x307 ;
.dw 0x308 ;
.dw 0x309 ;
.dw 0x30A ;
.dw 0x30B ;
.dw 0x30C ;
.dw 0x30D ;
.dw 0x30E ;
.dw 0x30F ;
.dw 0x310 ;
.dw 0x311 ;
.dw 0x312 ;
.dw 0x313 ;
.dw 0x314 ;
.dw 0x315 ;
.dw 0x316 ;
.dw 0x317 ;
.dw 0x318 ;
.dw 0x319 ;
.dw 0x31A ;
.dw 0x31B ;
.dw 0x31C ;
.dw 0x31D ;
.dw 0x31E ;
.dw 0x31F ;
#endif
.dw 0x325 ;
#if 0
// Not documented, but hardware takes them
// CC |= <reserved astat>
.dw 0x327 ;
.dw 0x328 ;
.dw 0x329 ;
.dw 0x32A ;
.dw 0x32B ;
.dw 0x32C ;
.dw 0x32D ;
.dw 0x32E ;
.dw 0x32F ;
.dw 0x330 ;
.dw 0x331 ;
.dw 0x332 ;
.dw 0x333 ;
.dw 0x334 ;
.dw 0x335 ;
.dw 0x336 ;
.dw 0x337 ;
.dw 0x338 ;
.dw 0x339 ;
.dw 0x33A ;
.dw 0x33B ;
.dw 0x33C ;
.dw 0x33D ;
.dw 0x33E ;
.dw 0x33F ;
#endif
.dw 0x345 ;
#if 0
// Not documented, but hardware takes them
// CC &= <reserved astat>
.dw 0x347 ;
.dw 0x348 ;
.dw 0x349 ;
.dw 0x34A ;
.dw 0x34B ;
.dw 0x34C ;
.dw 0x34D ;
.dw 0x34E ;
.dw 0x34F ;
.dw 0x350 ;
.dw 0x351 ;
.dw 0x352 ;
.dw 0x353 ;
.dw 0x354 ;
.dw 0x355 ;
.dw 0x356 ;
.dw 0x357 ;
.dw 0x358 ;
.dw 0x359 ;
.dw 0x35A ;
.dw 0x35B ;
.dw 0x35C ;
.dw 0x35D ;
.dw 0x35E ;
.dw 0x35F ;
#endif
.dw 0x365 ;
#if 0
// Not documented, but hardware takes them
// CC ^= <reserved astat>
.dw 0x367 ;
.dw 0x368 ;
.dw 0x369 ;
.dw 0x36A ;
.dw 0x36B ;
.dw 0x36C ;
.dw 0x36D ;
.dw 0x36E ;
.dw 0x36F ;
.dw 0x370 ;
.dw 0x371 ;
.dw 0x372 ;
.dw 0x373 ;
.dw 0x374 ;
.dw 0x375 ;
.dw 0x376 ;
.dw 0x377 ;
.dw 0x378 ;
.dw 0x379 ;
.dw 0x37A ;
.dw 0x37B ;
.dw 0x37C ;
.dw 0x37D ;
.dw 0x37E ;
.dw 0x37F ;
#endif
.dw 0x385 ;
#if 0
// Not documented, but hardware takes them
// <reserved astat> = CC
.dw 0x387 ;
.dw 0x388 ;
.dw 0x389 ;
.dw 0x38A ;
.dw 0x38B ;
.dw 0x38C ;
.dw 0x38D ;
.dw 0x38E ;
.dw 0x38F ;
.dw 0x390 ;
.dw 0x391 ;
.dw 0x392 ;
.dw 0x393 ;
.dw 0x394 ;
.dw 0x395 ;
.dw 0x396 ;
.dw 0x397 ;
.dw 0x398 ;
.dw 0x399 ;
.dw 0x39A ;
.dw 0x39B ;
.dw 0x39C ;
.dw 0x39D ;
.dw 0x39E ;
.dw 0x39F ;
#endif
.dw 0x3A5 ;
#if 0
// Not documented, but hardware takes them
// <reserved astat> |= CC
.dw 0x3A7 ;
.dw 0x3A8 ;
.dw 0x3A9 ;
.dw 0x3AA ;
.dw 0x3AB ;
.dw 0x3AC ;
.dw 0x3AD ;
.dw 0x3AE ;
.dw 0x3AF ;
.dw 0x3B0 ;
.dw 0x3B1 ;
.dw 0x3B2 ;
.dw 0x3B3 ;
.dw 0x3B4 ;
.dw 0x3B5 ;
.dw 0x3B6 ;
.dw 0x3B7 ;
.dw 0x3B8 ;
.dw 0x3B9 ;
.dw 0x3BA ;
.dw 0x3BB ;
.dw 0x3BC ;
.dw 0x3BD ;
.dw 0x3BE ;
.dw 0x3BF ;
#endif
.dw 0x3C5 ;
#if 0
// Not documented, but hardware takes them
// <reserved astat> &= CC
.dw 0x3C7 ;
.dw 0x3C8 ;
.dw 0x3C9 ;
.dw 0x3CA ;
.dw 0x3CB ;
.dw 0x3CC ;
.dw 0x3CD ;
.dw 0x3CE ;
.dw 0x3CF ;
.dw 0x3D0 ;
.dw 0x3D1 ;
.dw 0x3D2 ;
.dw 0x3D3 ;
.dw 0x3D4 ;
.dw 0x3D5 ;
.dw 0x3D6 ;
.dw 0x3D7 ;
.dw 0x3D8 ;
.dw 0x3D9 ;
.dw 0x3DA ;
.dw 0x3DB ;
.dw 0x3DC ;
.dw 0x3DD ;
.dw 0x3DE ;
.dw 0x3DF ;
#endif
.dw 0x3E5 ;
#if 0
// Not documented, but hardware takes them
// <reserved astat> ^= CC
.dw 0x3E7 ;
.dw 0x3E8 ;
.dw 0x3E9 ;
.dw 0x3EA ;
.dw 0x3EB ;
.dw 0x3EC ;
.dw 0x3ED ;
.dw 0x3EE ;
.dw 0x3EF ;
.dw 0x3F0 ;
.dw 0x3F1 ;
.dw 0x3F2 ;
.dw 0x3F3 ;
.dw 0x3F4 ;
.dw 0x3F5 ;
.dw 0x3F6 ;
.dw 0x3F7 ;
.dw 0x3F8 ;
.dw 0x3F9 ;
.dw 0x3FA ;
.dw 0x3FB ;
.dw 0x3FC ;
.dw 0x3FD ;
.dw 0x3FE ;
.dw 0x3FF ;
#endif
.dw 0x3A00 ;
.dw 0x3A01 ;
.dw 0x3A02 ;
.dw 0x3A03 ;
.dw 0x3A04 ;
.dw 0x3A05 ;
.dw 0x3A06 ;
.dw 0x3A07 ;
.dw 0x3A08 ;
.dw 0x3A09 ;
.dw 0x3A0A ;
.dw 0x3A0B ;
.dw 0x3A0C ;
.dw 0x3A0D ;
.dw 0x3A0E ;
.dw 0x3A0F ;
.dw 0x3A10 ;
.dw 0x3A11 ;
.dw 0x3A12 ;
.dw 0x3A13 ;
.dw 0x3A14 ;
.dw 0x3A15 ;
.dw 0x3A16 ;
.dw 0x3A17 ;
.dw 0x3A18 ;
.dw 0x3A19 ;
.dw 0x3A1A ;
.dw 0x3A1B ;
.dw 0x3A1C ;
.dw 0x3A1D ;
.dw 0x3A1E ;
.dw 0x3A1F ;
.dw 0x3A20 ;
.dw 0x3A21 ;
.dw 0x3A22 ;
.dw 0x3A23 ;
.dw 0x3A24 ;
.dw 0x3A25 ;
.dw 0x3A26 ;
.dw 0x3A27 ;
.dw 0x3A28 ;
.dw 0x3A29 ;
.dw 0x3A2A ;
.dw 0x3A2B ;
.dw 0x3A2C ;
.dw 0x3A2D ;
.dw 0x3A2E ;
.dw 0x3A2F ;
.dw 0x3A30 ;
.dw 0x3A31 ;
.dw 0x3A32 ;
.dw 0x3A33 ;
.dw 0x3A34 ;
.dw 0x3A35 ;
.dw 0x3A36 ;
.dw 0x3A37 ;
.dw 0x3A38 ;
.dw 0x3A39 ;
.dw 0x3A3A ;
.dw 0x3A3B ;
.dw 0x3A3C ;
.dw 0x3A3D ;
.dw 0x3A3E ;
.dw 0x3A3F ;
.dw 0x3A40 ;
.dw 0x3A41 ;
.dw 0x3A42 ;
.dw 0x3A43 ;
.dw 0x3A44 ;
.dw 0x3A45 ;
.dw 0x3A46 ;
.dw 0x3A47 ;
.dw 0x3A48 ;
.dw 0x3A49 ;
.dw 0x3A4A ;
.dw 0x3A4B ;
.dw 0x3A4C ;
.dw 0x3A4D ;
.dw 0x3A4E ;
.dw 0x3A4F ;
.dw 0x3A50 ;
.dw 0x3A51 ;
.dw 0x3A52 ;
.dw 0x3A53 ;
.dw 0x3A54 ;
.dw 0x3A55 ;
.dw 0x3A56 ;
.dw 0x3A57 ;
.dw 0x3A58 ;
.dw 0x3A59 ;
.dw 0x3A5A ;
.dw 0x3A5B ;
.dw 0x3A5C ;
.dw 0x3A5D ;
.dw 0x3A5E ;
.dw 0x3A5F ;
.dw 0x3A60 ;
.dw 0x3A61 ;
.dw 0x3A62 ;
.dw 0x3A63 ;
.dw 0x3A64 ;
.dw 0x3A65 ;
.dw 0x3A66 ;
.dw 0x3A67 ;
.dw 0x3A68 ;
.dw 0x3A69 ;
.dw 0x3A6A ;
.dw 0x3A6B ;
.dw 0x3A6C ;
.dw 0x3A6D ;
.dw 0x3A6E ;
.dw 0x3A6F ;
.dw 0x3A70 ;
.dw 0x3A71 ;
.dw 0x3A72 ;
.dw 0x3A73 ;
.dw 0x3A74 ;
.dw 0x3A75 ;
.dw 0x3A76 ;
.dw 0x3A77 ;
.dw 0x3A78 ;
.dw 0x3A79 ;
.dw 0x3A7A ;
.dw 0x3A7B ;
.dw 0x3A7C ;
.dw 0x3A7D ;
.dw 0x3A7E ;
.dw 0x3A7F ;
.dw 0x3A80 ;
.dw 0x3A81 ;
.dw 0x3A82 ;
.dw 0x3A83 ;
.dw 0x3A84 ;
.dw 0x3A85 ;
.dw 0x3A86 ;
.dw 0x3A87 ;
.dw 0x3A88 ;
.dw 0x3A89 ;
.dw 0x3A8A ;
.dw 0x3A8B ;
.dw 0x3A8C ;
.dw 0x3A8D ;
.dw 0x3A8E ;
.dw 0x3A8F ;
.dw 0x3A90 ;
.dw 0x3A91 ;
.dw 0x3A92 ;
.dw 0x3A93 ;
.dw 0x3A94 ;
.dw 0x3A95 ;
.dw 0x3A96 ;
.dw 0x3A97 ;
.dw 0x3A98 ;
.dw 0x3A99 ;
.dw 0x3A9A ;
.dw 0x3A9B ;
.dw 0x3A9C ;
.dw 0x3A9D ;
.dw 0x3A9E ;
.dw 0x3A9F ;
.dw 0x3AA0 ;
.dw 0x3AA1 ;
.dw 0x3AA2 ;
.dw 0x3AA3 ;
.dw 0x3AA4 ;
.dw 0x3AA5 ;
.dw 0x3AA6 ;
.dw 0x3AA7 ;
.dw 0x3AA8 ;
.dw 0x3AA9 ;
.dw 0x3AAA ;
.dw 0x3AAB ;
.dw 0x3AAC ;
.dw 0x3AAD ;
.dw 0x3AAE ;
.dw 0x3AAF ;
.dw 0x3AB0 ;
.dw 0x3AB1 ;
.dw 0x3AB2 ;
.dw 0x3AB3 ;
.dw 0x3AB4 ;
.dw 0x3AB5 ;
.dw 0x3AB6 ;
.dw 0x3AB7 ;
.dw 0x3AB8 ;
.dw 0x3AB9 ;
.dw 0x3ABA ;
.dw 0x3ABB ;
.dw 0x3ABC ;
.dw 0x3ABD ;
.dw 0x3ABE ;
.dw 0x3ABF ;
.dw 0x3AC0 ;
.dw 0x3AC1 ;
.dw 0x3AC2 ;
.dw 0x3AC3 ;
.dw 0x3AC4 ;
.dw 0x3AC5 ;
.dw 0x3AC6 ;
.dw 0x3AC7 ;
.dw 0x3AC8 ;
.dw 0x3AC9 ;
.dw 0x3ACA ;
.dw 0x3ACB ;
.dw 0x3ACC ;
.dw 0x3ACD ;
.dw 0x3ACE ;
.dw 0x3ACF ;
.dw 0x3AD0 ;
.dw 0x3AD1 ;
.dw 0x3AD2 ;
.dw 0x3AD3 ;
.dw 0x3AD4 ;
.dw 0x3AD5 ;
.dw 0x3AD6 ;
.dw 0x3AD7 ;
.dw 0x3AD8 ;
.dw 0x3AD9 ;
.dw 0x3ADA ;
.dw 0x3ADB ;
.dw 0x3ADC ;
.dw 0x3ADD ;
.dw 0x3ADE ;
.dw 0x3ADF ;
.dw 0x3AE0 ;
.dw 0x3AE1 ;
.dw 0x3AE2 ;
.dw 0x3AE3 ;
.dw 0x3AE4 ;
.dw 0x3AE5 ;
.dw 0x3AE6 ;
.dw 0x3AE7 ;
.dw 0x3AE8 ;
.dw 0x3AE9 ;
.dw 0x3AEA ;
.dw 0x3AEB ;
.dw 0x3AEC ;
.dw 0x3AED ;
.dw 0x3AEE ;
.dw 0x3AEF ;
.dw 0x3AF0 ;
.dw 0x3AF1 ;
.dw 0x3AF2 ;
.dw 0x3AF3 ;
.dw 0x3AF4 ;
.dw 0x3AF5 ;
.dw 0x3AF6 ;
.dw 0x3AF7 ;
.dw 0x3AF8 ;
.dw 0x3AF9 ;
.dw 0x3AFA ;
.dw 0x3AFB ;
.dw 0x3AFC ;
.dw 0x3AFD ;
.dw 0x3AFE ;
.dw 0x3AFF ;
.dw 0x3B00 ;
.dw 0x3B01 ;
.dw 0x3B02 ;
.dw 0x3B03 ;
.dw 0x3B04 ;
.dw 0x3B05 ;
.dw 0x3B06 ;
.dw 0x3B07 ;
.dw 0x3B08 ;
.dw 0x3B09 ;
.dw 0x3B0A ;
.dw 0x3B0B ;
.dw 0x3B0C ;
.dw 0x3B0D ;
.dw 0x3B0E ;
.dw 0x3B0F ;
.dw 0x3B10 ;
.dw 0x3B11 ;
.dw 0x3B12 ;
.dw 0x3B13 ;
.dw 0x3B14 ;
.dw 0x3B15 ;
.dw 0x3B16 ;
.dw 0x3B17 ;
.dw 0x3B18 ;
.dw 0x3B19 ;
.dw 0x3B1A ;
.dw 0x3B1B ;
.dw 0x3B1C ;
.dw 0x3B1D ;
.dw 0x3B1E ;
.dw 0x3B1F ;
.dw 0x3B20 ;
.dw 0x3B21 ;
.dw 0x3B22 ;
.dw 0x3B23 ;
.dw 0x3B24 ;
.dw 0x3B25 ;
.dw 0x3B26 ;
.dw 0x3B27 ;
.dw 0x3B28 ;
.dw 0x3B29 ;
.dw 0x3B2A ;
.dw 0x3B2B ;
.dw 0x3B2C ;
.dw 0x3B2D ;
.dw 0x3B2E ;
.dw 0x3B2F ;
.dw 0x3B30 ;
.dw 0x3B31 ;
.dw 0x3B32 ;
.dw 0x3B33 ;
.dw 0x3B34 ;
.dw 0x3B35 ;
.dw 0x3B36 ;
.dw 0x3B37 ;
.dw 0x3B38 ;
.dw 0x3B39 ;
.dw 0x3B3A ;
.dw 0x3B3B ;
.dw 0x3B3C ;
.dw 0x3B3D ;
.dw 0x3B3E ;
.dw 0x3B3F ;
.dw 0x3B40 ;
.dw 0x3B41 ;
.dw 0x3B42 ;
.dw 0x3B43 ;
.dw 0x3B44 ;
.dw 0x3B45 ;
.dw 0x3B46 ;
.dw 0x3B47 ;
.dw 0x3B48 ;
.dw 0x3B49 ;
.dw 0x3B4A ;
.dw 0x3B4B ;
.dw 0x3B4C ;
.dw 0x3B4D ;
.dw 0x3B4E ;
.dw 0x3B4F ;
.dw 0x3B50 ;
.dw 0x3B51 ;
.dw 0x3B52 ;
.dw 0x3B53 ;
.dw 0x3B54 ;
.dw 0x3B55 ;
.dw 0x3B56 ;
.dw 0x3B57 ;
.dw 0x3B58 ;
.dw 0x3B59 ;
.dw 0x3B5A ;
.dw 0x3B5B ;
.dw 0x3B5C ;
.dw 0x3B5D ;
.dw 0x3B5E ;
.dw 0x3B5F ;
.dw 0x3B60 ;
.dw 0x3B61 ;
.dw 0x3B62 ;
.dw 0x3B63 ;
.dw 0x3B64 ;
.dw 0x3B65 ;
.dw 0x3B66 ;
.dw 0x3B67 ;
.dw 0x3B68 ;
.dw 0x3B69 ;
.dw 0x3B6A ;
.dw 0x3B6B ;
.dw 0x3B6C ;
.dw 0x3B6D ;
.dw 0x3B6E ;
.dw 0x3B6F ;
.dw 0x3B70 ;
.dw 0x3B71 ;
.dw 0x3B72 ;
.dw 0x3B73 ;
.dw 0x3B74 ;
.dw 0x3B75 ;
.dw 0x3B76 ;
.dw 0x3B77 ;
.dw 0x3B78 ;
.dw 0x3B79 ;
.dw 0x3B7A ;
.dw 0x3B7B ;
.dw 0x3B7C ;
.dw 0x3B7D ;
.dw 0x3B7E ;
.dw 0x3B7F ;
.dw 0x3B80 ;
.dw 0x3B81 ;
.dw 0x3B82 ;
.dw 0x3B83 ;
.dw 0x3B84 ;
.dw 0x3B85 ;
.dw 0x3B86 ;
.dw 0x3B87 ;
.dw 0x3B88 ;
.dw 0x3B89 ;
.dw 0x3B8A ;
.dw 0x3B8B ;
.dw 0x3B8C ;
.dw 0x3B8D ;
.dw 0x3B8E ;
.dw 0x3B8F ;
.dw 0x3B90 ;
.dw 0x3B91 ;
.dw 0x3B92 ;
.dw 0x3B93 ;
.dw 0x3B94 ;
.dw 0x3B95 ;
.dw 0x3B96 ;
.dw 0x3B97 ;
.dw 0x3B98 ;
.dw 0x3B99 ;
.dw 0x3B9A ;
.dw 0x3B9B ;
.dw 0x3B9C ;
.dw 0x3B9D ;
.dw 0x3B9E ;
.dw 0x3B9F ;
.dw 0x3BA0 ;
.dw 0x3BA1 ;
.dw 0x3BA2 ;
.dw 0x3BA3 ;
.dw 0x3BA4 ;
.dw 0x3BA5 ;
.dw 0x3BA6 ;
.dw 0x3BA7 ;
.dw 0x3BA8 ;
.dw 0x3BA9 ;
.dw 0x3BAA ;
.dw 0x3BAB ;
.dw 0x3BAC ;
.dw 0x3BAD ;
.dw 0x3BAE ;
.dw 0x3BAF ;
.dw 0x3BB0 ;
.dw 0x3BB1 ;
.dw 0x3BB2 ;
.dw 0x3BB3 ;
.dw 0x3BB4 ;
.dw 0x3BB5 ;
.dw 0x3BB6 ;
.dw 0x3BB7 ;
.dw 0x3BB8 ;
.dw 0x3BB9 ;
.dw 0x3BBA ;
.dw 0x3BBB ;
.dw 0x3BBC ;
.dw 0x3BBD ;
.dw 0x3BBE ;
.dw 0x3BBF ;
.dw 0x3BC0 ;
.dw 0x3BC1 ;
.dw 0x3BC2 ;
.dw 0x3BC3 ;
.dw 0x3BC4 ;
.dw 0x3BC5 ;
.dw 0x3BC6 ;
.dw 0x3BC7 ;
.dw 0x3BC8 ;
.dw 0x3BC9 ;
.dw 0x3BCA ;
.dw 0x3BCB ;
.dw 0x3BCC ;
.dw 0x3BCD ;
.dw 0x3BCE ;
.dw 0x3BCF ;
.dw 0x3BD0 ;
.dw 0x3BD1 ;
.dw 0x3BD2 ;
.dw 0x3BD3 ;
.dw 0x3BD4 ;
.dw 0x3BD5 ;
.dw 0x3BD6 ;
.dw 0x3BD7 ;
.dw 0x3BD8 ;
.dw 0x3BD9 ;
.dw 0x3BDA ;
.dw 0x3BDB ;
.dw 0x3BDC ;
.dw 0x3BDD ;
.dw 0x3BDE ;
.dw 0x3BDF ;
.dw 0x3BE0 ;
.dw 0x3BE1 ;
.dw 0x3BE2 ;
.dw 0x3BE3 ;
.dw 0x3BE4 ;
.dw 0x3BE5 ;
.dw 0x3BE6 ;
.dw 0x3BE7 ;
.dw 0x3BE8 ;
.dw 0x3BE9 ;
.dw 0x3BEA ;
.dw 0x3BEB ;
.dw 0x3BEC ;
.dw 0x3BED ;
.dw 0x3BEE ;
.dw 0x3BEF ;
.dw 0x3BF0 ;
.dw 0x3BF1 ;
.dw 0x3BF2 ;
.dw 0x3BF3 ;
.dw 0x3BF4 ;
.dw 0x3BF5 ;
.dw 0x3BF6 ;
.dw 0x3BF7 ;
.dw 0x3BF8 ;
.dw 0x3BF9 ;
.dw 0x3BFA ;
.dw 0x3BFB ;
.dw 0x3BFC ;
.dw 0x3BFD ;
.dw 0x3BFE ;
.dw 0x3BFF ;
.dw 0x3140 ;
.dw 0x3141 ;
.dw 0x3142 ;
.dw 0x3143 ;
.dw 0x3144 ;
.dw 0x3145 ;
.dw 0x3146 ;
.dw 0x3147 ;
.dw 0x3148 ;
.dw 0x3149 ;
.dw 0x314A ;
.dw 0x314B ;
.dw 0x314C ;
.dw 0x314D ;
.dw 0x314E ;
.dw 0x314F ;
.dw 0x3150 ;
.dw 0x3151 ;
.dw 0x3152 ;
.dw 0x3153 ;
.dw 0x3154 ;
.dw 0x3155 ;
.dw 0x3156 ;
.dw 0x3157 ;
.dw 0x3158 ;
.dw 0x3159 ;
.dw 0x315A ;
.dw 0x315B ;
.dw 0x315C ;
.dw 0x315D ;
.dw 0x315E ;
.dw 0x315F ;
.dw 0x3160 ;
.dw 0x3161 ;
.dw 0x3162 ;
.dw 0x3163 ;
.dw 0x3164 ;
.dw 0x3165 ;
.dw 0x3166 ;
.dw 0x3167 ;
.dw 0x3168 ;
.dw 0x3169 ;
.dw 0x316A ;
.dw 0x316B ;
.dw 0x316C ;
.dw 0x316D ;
.dw 0x316E ;
.dw 0x316F ;
.dw 0x3170 ;
.dw 0x3171 ;
.dw 0x3172 ;
.dw 0x3173 ;
.dw 0x3174 ;
.dw 0x3175 ;
.dw 0x3176 ;
.dw 0x3177 ;
.dw 0x3178 ;
.dw 0x3179 ;
.dw 0x317A ;
.dw 0x317B ;
.dw 0x317C ;
.dw 0x317D ;
.dw 0x317E ;
.dw 0x317F ;
.dw 0x3340 ;
.dw 0x3341 ;
.dw 0x3342 ;
.dw 0x3343 ;
.dw 0x3344 ;
.dw 0x3345 ;
.dw 0x3346 ;
.dw 0x3347 ;
.dw 0x3348 ;
.dw 0x3349 ;
.dw 0x334A ;
.dw 0x334B ;
.dw 0x334C ;
.dw 0x334D ;
.dw 0x334E ;
.dw 0x334F ;
.dw 0x3350 ;
.dw 0x3351 ;
.dw 0x3352 ;
.dw 0x3353 ;
.dw 0x3354 ;
.dw 0x3355 ;
.dw 0x3356 ;
.dw 0x3357 ;
.dw 0x3358 ;
.dw 0x3359 ;
.dw 0x335A ;
.dw 0x335B ;
.dw 0x335C ;
.dw 0x335D ;
.dw 0x335E ;
.dw 0x335F ;
.dw 0x3360 ;
.dw 0x3361 ;
.dw 0x3362 ;
.dw 0x3363 ;
.dw 0x3364 ;
.dw 0x3365 ;
.dw 0x3366 ;
.dw 0x3367 ;
.dw 0x3368 ;
.dw 0x3369 ;
.dw 0x336A ;
.dw 0x336B ;
.dw 0x336C ;
.dw 0x336D ;
.dw 0x336E ;
.dw 0x336F ;
.dw 0x3370 ;
.dw 0x3371 ;
.dw 0x3372 ;
.dw 0x3373 ;
.dw 0x3374 ;
.dw 0x3375 ;
.dw 0x3376 ;
.dw 0x3377 ;
.dw 0x3378 ;
.dw 0x3379 ;
.dw 0x337A ;
.dw 0x337B ;
.dw 0x337C ;
.dw 0x337D ;
.dw 0x337E ;
.dw 0x337F ;
.dw 0x3540 ;
.dw 0x3541 ;
.dw 0x3542 ;
.dw 0x3543 ;
.dw 0x3544 ;
.dw 0x3545 ;
.dw 0x3546 ;
.dw 0x3547 ;
.dw 0x3548 ;
.dw 0x3549 ;
.dw 0x354A ;
.dw 0x354B ;
.dw 0x354C ;
.dw 0x354D ;
.dw 0x354E ;
.dw 0x354F ;
.dw 0x3550 ;
.dw 0x3551 ;
.dw 0x3552 ;
.dw 0x3553 ;
.dw 0x3554 ;
.dw 0x3555 ;
.dw 0x3556 ;
.dw 0x3557 ;
.dw 0x3558 ;
.dw 0x3559 ;
.dw 0x355A ;
.dw 0x355B ;
.dw 0x355C ;
.dw 0x355D ;
.dw 0x355E ;
.dw 0x355F ;
.dw 0x3560 ;
.dw 0x3561 ;
.dw 0x3562 ;
.dw 0x3563 ;
.dw 0x3564 ;
.dw 0x3565 ;
.dw 0x3566 ;
.dw 0x3567 ;
.dw 0x3568 ;
.dw 0x3569 ;
.dw 0x356A ;
.dw 0x356B ;
.dw 0x356C ;
.dw 0x356D ;
.dw 0x356E ;
.dw 0x356F ;
.dw 0x3570 ;
.dw 0x3571 ;
.dw 0x3572 ;
.dw 0x3573 ;
.dw 0x3574 ;
.dw 0x3575 ;
.dw 0x3576 ;
.dw 0x3577 ;
.dw 0x3578 ;
.dw 0x3579 ;
.dw 0x357A ;
.dw 0x357B ;
.dw 0x357C ;
.dw 0x357D ;
.dw 0x357E ;
.dw 0x357F ;
.dw 0x3740 ;
.dw 0x3741 ;
.dw 0x3742 ;
.dw 0x3743 ;
.dw 0x3744 ;
.dw 0x3745 ;
.dw 0x3746 ;
.dw 0x3747 ;
.dw 0x3748 ;
.dw 0x3749 ;
.dw 0x374A ;
.dw 0x374B ;
.dw 0x374C ;
.dw 0x374D ;
.dw 0x374E ;
.dw 0x374F ;
.dw 0x3750 ;
.dw 0x3751 ;
.dw 0x3752 ;
.dw 0x3753 ;
.dw 0x3754 ;
.dw 0x3755 ;
.dw 0x3756 ;
.dw 0x3757 ;
.dw 0x3758 ;
.dw 0x3759 ;
.dw 0x375A ;
.dw 0x375B ;
.dw 0x375C ;
.dw 0x375D ;
.dw 0x375E ;
.dw 0x375F ;
.dw 0x3760 ;
.dw 0x3761 ;
.dw 0x3762 ;
.dw 0x3763 ;
.dw 0x3764 ;
.dw 0x3765 ;
.dw 0x3766 ;
.dw 0x3767 ;
.dw 0x3768 ;
.dw 0x3769 ;
.dw 0x376A ;
.dw 0x376B ;
.dw 0x376C ;
.dw 0x376D ;
.dw 0x376E ;
.dw 0x376F ;
.dw 0x3770 ;
.dw 0x3771 ;
.dw 0x3772 ;
.dw 0x3773 ;
.dw 0x3774 ;
.dw 0x3775 ;
.dw 0x3776 ;
.dw 0x3777 ;
.dw 0x3778 ;
.dw 0x3779 ;
.dw 0x377A ;
.dw 0x377B ;
.dw 0x377C ;
.dw 0x377D ;
.dw 0x377E ;
.dw 0x377F ;
.dw 0x3940 ;
.dw 0x3941 ;
.dw 0x3942 ;
.dw 0x3943 ;
.dw 0x3944 ;
.dw 0x3945 ;
.dw 0x3946 ;
.dw 0x3947 ;
.dw 0x3948 ;
.dw 0x3949 ;
.dw 0x394A ;
.dw 0x394B ;
.dw 0x394C ;
.dw 0x394D ;
.dw 0x394E ;
.dw 0x394F ;
.dw 0x3950 ;
.dw 0x3951 ;
.dw 0x3952 ;
.dw 0x3953 ;
.dw 0x3954 ;
.dw 0x3955 ;
.dw 0x3956 ;
.dw 0x3957 ;
.dw 0x3958 ;
.dw 0x3959 ;
.dw 0x395A ;
.dw 0x395B ;
.dw 0x395C ;
.dw 0x395D ;
.dw 0x395E ;
.dw 0x395F ;
.dw 0x3960 ;
.dw 0x3961 ;
.dw 0x3962 ;
.dw 0x3963 ;
.dw 0x3964 ;
.dw 0x3965 ;
.dw 0x3966 ;
.dw 0x3967 ;
.dw 0x3968 ;
.dw 0x3969 ;
.dw 0x396A ;
.dw 0x396B ;
.dw 0x396C ;
.dw 0x396D ;
.dw 0x396E ;
.dw 0x396F ;
.dw 0x3970 ;
.dw 0x3971 ;
.dw 0x3972 ;
.dw 0x3973 ;
.dw 0x3974 ;
.dw 0x3975 ;
.dw 0x3976 ;
.dw 0x3977 ;
.dw 0x3978 ;
.dw 0x3979 ;
.dw 0x397A ;
.dw 0x397B ;
.dw 0x397C ;
.dw 0x397D ;
.dw 0x397E ;
.dw 0x397F ;
.dw 0x3D40 ;
.dw 0x3D41 ;
.dw 0x3D42 ;
.dw 0x3D43 ;
.dw 0x3D44 ;
.dw 0x3D45 ;
.dw 0x3D46 ;
.dw 0x3D47 ;
.dw 0x3D48 ;
.dw 0x3D49 ;
.dw 0x3D4A ;
.dw 0x3D4B ;
.dw 0x3D4C ;
.dw 0x3D4D ;
.dw 0x3D4E ;
.dw 0x3D4F ;
.dw 0x3D50 ;
.dw 0x3D51 ;
.dw 0x3D52 ;
.dw 0x3D53 ;
.dw 0x3D54 ;
.dw 0x3D55 ;
.dw 0x3D56 ;
.dw 0x3D57 ;
.dw 0x3D58 ;
.dw 0x3D59 ;
.dw 0x3D5A ;
.dw 0x3D5B ;
.dw 0x3D5C ;
.dw 0x3D5D ;
.dw 0x3D5E ;
.dw 0x3D5F ;
.dw 0x3D60 ;
.dw 0x3D61 ;
.dw 0x3D62 ;
.dw 0x3D63 ;
.dw 0x3D64 ;
.dw 0x3D65 ;
.dw 0x3D66 ;
.dw 0x3D67 ;
.dw 0x3D68 ;
.dw 0x3D69 ;
.dw 0x3D6A ;
.dw 0x3D6B ;
.dw 0x3D6C ;
.dw 0x3D6D ;
.dw 0x3D6E ;
.dw 0x3D6F ;
.dw 0x3D70 ;
.dw 0x3D71 ;
.dw 0x3D72 ;
.dw 0x3D73 ;
.dw 0x3D74 ;
.dw 0x3D75 ;
.dw 0x3D76 ;
.dw 0x3D77 ;
.dw 0x3D78 ;
.dw 0x3D79 ;
.dw 0x3D7A ;
.dw 0x3D7B ;
.dw 0x3D7C ;
.dw 0x3D7D ;
.dw 0x3D7E ;
.dw 0x3D7F ;
.dw 0x3F40 ;
.dw 0x3F41 ;
.dw 0x3F42 ;
.dw 0x3F43 ;
.dw 0x3F44 ;
.dw 0x3F45 ;
.dw 0x3F46 ;
.dw 0x3F47 ;
.dw 0x3F48 ;
.dw 0x3F49 ;
.dw 0x3F4A ;
.dw 0x3F4B ;
.dw 0x3F4C ;
.dw 0x3F4D ;
.dw 0x3F4E ;
.dw 0x3F4F ;
.dw 0x3F50 ;
.dw 0x3F51 ;
.dw 0x3F52 ;
.dw 0x3F53 ;
.dw 0x3F54 ;
.dw 0x3F55 ;
.dw 0x3F56 ;
.dw 0x3F57 ;
.dw 0x3F58 ;
.dw 0x3F59 ;
.dw 0x3F5A ;
.dw 0x3F5B ;
.dw 0x3F5C ;
.dw 0x3F5D ;
.dw 0x3F5E ;
.dw 0x3F5F ;
.dw 0x3F60 ;
.dw 0x3F61 ;
.dw 0x3F62 ;
.dw 0x3F63 ;
.dw 0x3F64 ;
.dw 0x3F65 ;
.dw 0x3F66 ;
.dw 0x3F67 ;
.dw 0x3F68 ;
.dw 0x3F69 ;
.dw 0x3F6A ;
.dw 0x3F6B ;
.dw 0x3F6C ;
.dw 0x3F6D ;
.dw 0x3F6E ;
.dw 0x3F6F ;
.dw 0x3F70 ;
.dw 0x3F71 ;
.dw 0x3F72 ;
.dw 0x3F73 ;
.dw 0x3F74 ;
.dw 0x3F75 ;
.dw 0x3F76 ;
.dw 0x3F77 ;
.dw 0x3F78 ;
.dw 0x3F79 ;
.dw 0x3F7A ;
.dw 0x3F7B ;
.dw 0x3F7C ;
.dw 0x3F7D ;
.dw 0x3F7E ;
.dw 0x3F7F ;
.dw 0x3104 ;
.dw 0x3105 ;
.dw 0x310C ;
.dw 0x310D ;
.dw 0x3114 ;
.dw 0x3115 ;
.dw 0x311C ;
.dw 0x311D ;
.dw 0x3124 ;
.dw 0x3125 ;
.dw 0x312C ;
.dw 0x312D ;
.dw 0x3134 ;
.dw 0x3135 ;
.dw 0x313C ;
.dw 0x313D ;
.dw 0x3304 ;
.dw 0x3305 ;
.dw 0x330C ;
.dw 0x330D ;
.dw 0x3314 ;
.dw 0x3315 ;
.dw 0x331C ;
.dw 0x331D ;
.dw 0x3324 ;
.dw 0x3325 ;
.dw 0x332C ;
.dw 0x332D ;
.dw 0x3334 ;
.dw 0x3335 ;
.dw 0x333C ;
.dw 0x333D ;
.dw 0x3504 ;
.dw 0x3505 ;
.dw 0x350C ;
.dw 0x350D ;
.dw 0x3514 ;
.dw 0x3515 ;
.dw 0x351C ;
.dw 0x351D ;
.dw 0x3524 ;
.dw 0x3525 ;
.dw 0x352C ;
.dw 0x352D ;
.dw 0x3534 ;
.dw 0x3535 ;
.dw 0x353C ;
.dw 0x353D ;
.dw 0x3704 ;
.dw 0x3705 ;
.dw 0x370C ;
.dw 0x370D ;
.dw 0x3714 ;
.dw 0x3715 ;
.dw 0x371C ;
.dw 0x371D ;
.dw 0x3724 ;
.dw 0x3725 ;
.dw 0x372C ;
.dw 0x372D ;
.dw 0x3734 ;
.dw 0x3735 ;
.dw 0x373C ;
.dw 0x373D ;
.dw 0x3904 ;
.dw 0x3905 ;
.dw 0x390C ;
.dw 0x390D ;
.dw 0x3914 ;
.dw 0x3915 ;
.dw 0x391C ;
.dw 0x391D ;
.dw 0x3924 ;
.dw 0x3925 ;
.dw 0x392C ;
.dw 0x392D ;
.dw 0x3934 ;
.dw 0x3935 ;
.dw 0x393C ;
.dw 0x393D ;
.dw 0x3D04 ;
.dw 0x3D05 ;
.dw 0x3D0C ;
.dw 0x3D0D ;
.dw 0x3D14 ;
.dw 0x3D15 ;
.dw 0x3D1C ;
.dw 0x3D1D ;
.dw 0x3D24 ;
.dw 0x3D25 ;
.dw 0x3D2C ;
.dw 0x3D2D ;
.dw 0x3D34 ;
.dw 0x3D35 ;
.dw 0x3D3C ;
.dw 0x3D3D ;
.dw 0x3F04 ;
.dw 0x3F05 ;
.dw 0x3F0C ;
.dw 0x3F0D ;
.dw 0x3F14 ;
.dw 0x3F15 ;
.dw 0x3F1C ;
.dw 0x3F1D ;
.dw 0x3F24 ;
.dw 0x3F25 ;
.dw 0x3F2C ;
.dw 0x3F2D ;
.dw 0x3F34 ;
.dw 0x3F35 ;
.dw 0x3F3C ;
.dw 0x3F3D ;
.dw 0x3820 ;
.dw 0x3821 ;
.dw 0x3822 ;
.dw 0x3823 ;
.dw 0x3824 ;
.dw 0x3825 ;
.dw 0x3826 ;
.dw 0x3827 ;
.dw 0x3828 ;
.dw 0x3829 ;
.dw 0x382A ;
.dw 0x382B ;
.dw 0x382C ;
.dw 0x382D ;
.dw 0x382E ;
.dw 0x382F ;
.dw 0x3860 ;
.dw 0x3861 ;
.dw 0x3862 ;
.dw 0x3863 ;
.dw 0x3864 ;
.dw 0x3865 ;
.dw 0x3866 ;
.dw 0x3867 ;
.dw 0x3868 ;
.dw 0x3869 ;
.dw 0x386A ;
.dw 0x386B ;
.dw 0x386C ;
.dw 0x386D ;
.dw 0x386E ;
.dw 0x386F ;
.dw 0x38A0 ;
.dw 0x38A1 ;
.dw 0x38A2 ;
.dw 0x38A3 ;
.dw 0x38A4 ;
.dw 0x38A5 ;
.dw 0x38A6 ;
.dw 0x38A7 ;
.dw 0x38A8 ;
.dw 0x38A9 ;
.dw 0x38AA ;
.dw 0x38AB ;
.dw 0x38AC ;
.dw 0x38AD ;
.dw 0x38AE ;
.dw 0x38AF ;
.dw 0x38E0 ;
.dw 0x38E1 ;
.dw 0x38E2 ;
.dw 0x38E3 ;
.dw 0x38E4 ;
.dw 0x38E5 ;
.dw 0x38E6 ;
.dw 0x38E7 ;
.dw 0x38E8 ;
.dw 0x38E9 ;
.dw 0x38EA ;
.dw 0x38EB ;
.dw 0x38EC ;
.dw 0x38ED ;
.dw 0x38EE ;
.dw 0x38EF ;
.dw 0x3920 ;
.dw 0x3921 ;
.dw 0x3922 ;
.dw 0x3923 ;
.dw 0x3924 ;
.dw 0x3925 ;
.dw 0x3926 ;
.dw 0x3927 ;
.dw 0x3928 ;
.dw 0x3929 ;
.dw 0x392A ;
.dw 0x392B ;
.dw 0x392C ;
.dw 0x392D ;
.dw 0x392E ;
.dw 0x392F ;
.dw 0x39A0 ;
.dw 0x39A1 ;
.dw 0x39A2 ;
.dw 0x39A3 ;
.dw 0x39A4 ;
.dw 0x39A5 ;
.dw 0x39A6 ;
.dw 0x39A7 ;
.dw 0x39A8 ;
.dw 0x39A9 ;
.dw 0x39AA ;
.dw 0x39AB ;
.dw 0x39AC ;
.dw 0x39AD ;
.dw 0x39AE ;
.dw 0x39AF ;
.dw 0x39E0 ;
.dw 0x39E1 ;
.dw 0x39E2 ;
.dw 0x39E3 ;
.dw 0x39E4 ;
.dw 0x39E5 ;
.dw 0x39E6 ;
.dw 0x39E7 ;
.dw 0x39E8 ;
.dw 0x39E9 ;
.dw 0x39EA ;
.dw 0x39EB ;
.dw 0x39EC ;
.dw 0x39ED ;
.dw 0x39EE ;
.dw 0x39EF ;
#if 0
// EMUDAT = Dreg; is valid
.dw 0x3E38 ;
.dw 0x3E39 ;
.dw 0x3E3A ;
.dw 0x3E3B ;
.dw 0x3E3C ;
.dw 0x3E3D ;
.dw 0x3E3E ;
.dw 0x3E3F ;
// EMUDAT = Preg; is valid
.dw 0x3E78 ;
.dw 0x3E79 ;
.dw 0x3E7A ;
.dw 0x3E7B ;
.dw 0x3E7C ;
.dw 0x3E7D ;
.dw 0x3E7E ;
.dw 0x3E7F ;
// EMUDAT = Ireg; is valid
.dw 0x3EB8 ;
.dw 0x3EB9 ;
.dw 0x3EBA ;
.dw 0x3EBB ;
// EMUDAT = Mreg; is valid
.dw 0x3EBC ;
.dw 0x3EBD ;
.dw 0x3EBE ;
.dw 0x3EBF ;
// EMUDAT = Breg; is valid
.dw 0x3EF8 ;
.dw 0x3EF9 ;
.dw 0x3EFA ;
.dw 0x3EFB ;
// EMUDAT = Lreg; is valid
.dw 0x3EFC ;
.dw 0x3EFD ;
.dw 0x3EFE ;
.dw 0x3EFF ;
// EMUDAT = Areg; is valid
.dw 0x3F38 ;
.dw 0x3F39 ;
.dw 0x3F3A ;
.dw 0x3F3B ;
#endif
.dw 0x3F3C ;
.dw 0x3F3D ;
#if 0
// EMUDAT = ASTAT; is valid
.dw 0x3F3E ;
// EMUDAT = RETS; is valid
.dw 0x3F3F ;
// EMUDAT = loopregs; is valid
.dw 0x3FB8 ;
.dw 0x3FB9 ;
.dw 0x3FBA ;
.dw 0x3FBB ;
.dw 0x3FBC ;
.dw 0x3FBD ;
// EMUDAT = cycles; is valid
.dw 0x3FBE ;
.dw 0x3FBF ;
// EMUDAT = USP; is valid
.dw 0x3FF8 ;
// EMUDAT = SEQSTAT; is valid
.dw 0x3FF9 ;
// EMUDAT = SYSCFG; is valid
.dw 0x3FFA ;
// EMDUAT = RET[IXNE]; is valid
.dw 0x3FFB ;
.dw 0x3FFC ;
.dw 0x3FFD ;
.dw 0x3FFE ;
// EMUDAT = EMUDAT; is valid
.dw 0x3FFF ;
// Dreg = EMUDAT; is valid
.dw 0x31C7 ;
.dw 0x31CF ;
.dw 0x31D7 ;
.dw 0x31DF ;
#if 0
// R4 = EMUDAT; breaks the test
.dw 0x31E7 ;
// R5 = EMUDAT; breaks the test
.dw 0x31EF ;
#endif
.dw 0x31F7 ;
.dw 0x31FF ;
// Preg = EMUDAT; is valid
.dw 0x33C7 ;
.dw 0x33CF ;
.dw 0x33D7 ;
.dw 0x33DF ;
.dw 0x33E7 ;
.dw 0x33EF ;
.dw 0x33F7 ;
.dw 0x33FF ;
// Ireg = EMUDAT; is valid
.dw 0x35C7 ;
.dw 0x35CF ;
.dw 0x35D7 ;
.dw 0x35DF ;
// Mreg = EMUDAT; is valid
.dw 0x35E7 ;
.dw 0x35EF ;
.dw 0x35F7 ;
.dw 0x35FF ;
// EMUDAT = Breg; is valid
.dw 0x37C7 ;
.dw 0x37CF ;
.dw 0x37D7 ;
.dw 0x37DF ;
// EMUDAT = Lreg; is valid
.dw 0x37E7 ;
.dw 0x37EF ;
.dw 0x37F7 ;
.dw 0x37FF ;
#endif
.dw 0x39C7 ;
.dw 0x39CF ;
.dw 0x39D7 ;
.dw 0x39DF ;
.dw 0x39E7 ;
.dw 0x39EF ;
#if 0
// ASTAT = EMUDAT; is valid
.dw 0x39F7 ;
// RETS = EMUDAT; is valid
.dw 0x39FF ;
// loopregs = EMUDAT; is valid
.dw 0x3DC7 ;
.dw 0x3DCF ;
.dw 0x3DD7 ;
.dw 0x3DDF ;
.dw 0x3DE7 ;
.dw 0x3DEF ;
// cycles = EMUDAT; is valid
.dw 0x3DF7 ;
.dw 0x3DFF ;
// USP = EMUDAT; is valid
.dw 0x3FC7 ;
// SEQSTAT = EMUDAT; is valid
.dw 0x3FCF ;
// SYSCFG = EMUDAT; is valid
.dw 0x3FD7 ;
// RET[IXNE] = EMUDAT; is valid
.dw 0x3FDF ;
.dw 0x3FE7 ;
.dw 0x3FEF ;
.dw 0x3FF7 ;
// EMUDAT = EMUDAT; is valid
.dw 0x3FFF ;
#endif
.dw 0x3D80 ;
.dw 0x3D81 ;
.dw 0x3D82 ;
.dw 0x3D83 ;
.dw 0x3D84 ;
.dw 0x3D85 ;
.dw 0x3D86 ;
.dw 0x3D87 ;
.dw 0x3D88 ;
.dw 0x3D89 ;
.dw 0x3D8A ;
.dw 0x3D8B ;
.dw 0x3D8C ;
.dw 0x3D8D ;
.dw 0x3D8E ;
.dw 0x3D8F ;
.dw 0x3D90 ;
.dw 0x3D91 ;
.dw 0x3D92 ;
.dw 0x3D93 ;
.dw 0x3D94 ;
.dw 0x3D95 ;
.dw 0x3D96 ;
.dw 0x3D97 ;
.dw 0x3D98 ;
.dw 0x3D99 ;
.dw 0x3D9A ;
.dw 0x3D9B ;
.dw 0x3D9C ;
.dw 0x3D9D ;
.dw 0x3D9E ;
.dw 0x3D9F ;
.dw 0x3DA0 ;
.dw 0x3DA1 ;
.dw 0x3DA2 ;
.dw 0x3DA3 ;
.dw 0x3DA4 ;
.dw 0x3DA5 ;
.dw 0x3DA6 ;
.dw 0x3DA7 ;
.dw 0x3DA8 ;
.dw 0x3DA9 ;
.dw 0x3DAA ;
.dw 0x3DAB ;
.dw 0x3DAC ;
.dw 0x3DAD ;
.dw 0x3DAE ;
.dw 0x3DAF ;
.dw 0x3DB0 ;
.dw 0x3DB1 ;
.dw 0x3DB2 ;
.dw 0x3DB3 ;
.dw 0x3DB4 ;
.dw 0x3DB5 ;
.dw 0x3DB6 ;
.dw 0x3DB7 ;
.dw 0x3DB8 ;
.dw 0x3DB9 ;
.dw 0x3DBA ;
.dw 0x3DBB ;
.dw 0x3DBC ;
.dw 0x3DBD ;
.dw 0x3DBE ;
.dw 0x3DBF ;
.dw 0x3DC1 ;
.dw 0x3DC2 ;
.dw 0x3DC3 ;
.dw 0x3DC4 ;
.dw 0x3DC5 ;
.dw 0x3DC6 ;
#if 0
// loopregs = EMUDAT; is valid
.dw 0x3DC7 ;
#endif
.dw 0x3DC9 ;
.dw 0x3DCA ;
.dw 0x3DCB ;
.dw 0x3DCC ;
.dw 0x3DCD ;
.dw 0x3DCE ;
#if 0
// loopregs = EMUDAT; is valid
.dw 0x3DCF ;
#endif
.dw 0x3DD1 ;
.dw 0x3DD2 ;
.dw 0x3DD3 ;
.dw 0x3DD4 ;
.dw 0x3DD5 ;
.dw 0x3DD6 ;
#if 0
// loopregs = EMUDAT; is valid
.dw 0x3DD7 ;
#endif
.dw 0x3DD9 ;
.dw 0x3DDA ;
.dw 0x3DDB ;
.dw 0x3DDC ;
.dw 0x3DDD ;
.dw 0x3DDE ;
#if 0
// loopregs = EMUDAT; is valid
.dw 0x3DDF ;
#endif
.dw 0x3DE1 ;
.dw 0x3DE2 ;
.dw 0x3DE3 ;
.dw 0x3DE4 ;
.dw 0x3DE5 ;
.dw 0x3DE6 ;
#if 0
// loopregs = EMUDAT; is valid
.dw 0x3DE7 ;
#endif
.dw 0x3DE9 ;
.dw 0x3DEA ;
.dw 0x3DEB ;
.dw 0x3DEC ;
.dw 0x3DED ;
.dw 0x3DEE ;
#if 0
// loopregs = EMUDAT; is valid
.dw 0x3DEF ;
#endif
.dw 0x3DF1 ;
.dw 0x3DF2 ;
.dw 0x3DF3 ;
.dw 0x3DF4 ;
.dw 0x3DF5 ;
.dw 0x3DF6 ;
#if 0
// cycles = EMUDAT; is valid
.dw 0x3DF7 ;
#endif
.dw 0x3DF9 ;
.dw 0x3DFA ;
.dw 0x3DFB ;
.dw 0x3DFC ;
.dw 0x3DFD ;
.dw 0x3DFE ;
#if 0
// cycles = EMUDAT; is valid
.dw 0x3DFF ;
#endif
.dw 0x3F88 ;
.dw 0x3F89 ;
.dw 0x3F8A ;
.dw 0x3F8B ;
.dw 0x3F8C ;
.dw 0x3F8D ;
.dw 0x3F8E ;
.dw 0x3F8F ;
.dw 0x3F90 ;
.dw 0x3F91 ;
.dw 0x3F92 ;
.dw 0x3F93 ;
.dw 0x3F94 ;
.dw 0x3F95 ;
.dw 0x3F96 ;
.dw 0x3F97 ;
.dw 0x3F98 ;
.dw 0x3F99 ;
.dw 0x3F9A ;
.dw 0x3F9B ;
.dw 0x3F9C ;
.dw 0x3F9D ;
.dw 0x3F9E ;
.dw 0x3F9F ;
.dw 0x3FA0 ;
.dw 0x3FA1 ;
.dw 0x3FA2 ;
.dw 0x3FA3 ;
.dw 0x3FA4 ;
.dw 0x3FA5 ;
.dw 0x3FA6 ;
.dw 0x3FA7 ;
.dw 0x3FA8 ;
.dw 0x3FA9 ;
.dw 0x3FAA ;
.dw 0x3FAB ;
.dw 0x3FAC ;
.dw 0x3FAD ;
.dw 0x3FAE ;
.dw 0x3FAF ;
.dw 0x3FB0 ;
.dw 0x3FB1 ;
.dw 0x3FB2 ;
.dw 0x3FB3 ;
.dw 0x3FB4 ;
.dw 0x3FB5 ;
.dw 0x3FB6 ;
.dw 0x3FB7 ;
#if 0
// EMUDAT = loopregs; is valid
.dw 0x3FB8 ;
.dw 0x3FB9 ;
.dw 0x3FBA ;
.dw 0x3FBB ;
.dw 0x3FBC ;
.dw 0x3FBD ;
// EMUDAT = cycles; is valid
.dw 0x3FBE ;
.dw 0x3FBF ;
#endif
.dw 0x3FC9 ;
.dw 0x3FCA ;
.dw 0x3FCB ;
.dw 0x3FCC ;
.dw 0x3FCD ;
.dw 0x3FCE ;
#if 0
// SEQSTAT = EMUDAT; is valid
.dw 0x3FCF ;
#endif
.dw 0x3FD1 ;
.dw 0x3FD2 ;
.dw 0x3FD3 ;
.dw 0x3FD4 ;
.dw 0x3FD5 ;
.dw 0x3FD6 ;
#if 0
// SYSCFG = EMUDAT; is valid
.dw 0x3FD7 ;
#endif
.dw 0x3FD9 ;
.dw 0x3FDA ;
.dw 0x3FDB ;
.dw 0x3FDC ;
.dw 0x3FDD ;
.dw 0x3FDE ;
#if 0
// RET[IXNE] = EMUDAT; is valid
.dw 0x3FDF ;
#endif
.dw 0x3FE1 ;
.dw 0x3FE2 ;
.dw 0x3FE3 ;
.dw 0x3FE4 ;
.dw 0x3FE5 ;
.dw 0x3FE6 ;
#if 0
// RET[IXNE] = EMUDAT; is valid
.dw 0x3FE7 ;
#endif
.dw 0x3FE9 ;
.dw 0x3FEA ;
.dw 0x3FEB ;
.dw 0x3FEC ;
.dw 0x3FED ;
.dw 0x3FEE ;
#if 0
// RET[IXNE] = EMUDAT; is valid
.dw 0x3FEF ;
#endif
.dw 0x3FF1 ;
.dw 0x3FF2 ;
.dw 0x3FF3 ;
.dw 0x3FF4 ;
.dw 0x3FF5 ;
.dw 0x3FF6 ;
#if 0
// RET[IXNE] = EMUDAT; is valid
.dw 0x3FF7 ;
// EMUDAT = SEQSTAT; is valid
.dw 0x3FF9 ;
// EMUDAT = SYSCFG; is valid
.dw 0x3FFA ;
// EMDUAT = RET[IXNE]; is valid
.dw 0x3FFB ;
.dw 0x3FFC ;
.dw 0x3FFD ;
.dw 0x3FFE ;
// EMUDAT = EMUDAT; is valid
.dw 0x3FFF ;
#endif
.dw 0x39B0 ;
.dw 0x39B1 ;
.dw 0x39B2 ;
.dw 0x39B3 ;
.dw 0x39B4 ;
.dw 0x39B5 ;
.dw 0x39B6 ;
.dw 0x39B7 ;
.dw 0x39B8 ;
.dw 0x39B9 ;
.dw 0x39BA ;
.dw 0x39BB ;
.dw 0x39BC ;
.dw 0x39BD ;
.dw 0x39BE ;
.dw 0x39BF ;
.dw 0x39F1 ;
.dw 0x39F2 ;
.dw 0x39F3 ;
.dw 0x39F4 ;
.dw 0x39F5 ;
.dw 0x39F6 ;
#if 0
// ASTAT = EMUDAT; is valid
.dw 0x39F7 ;
#endif
.dw 0x39F9 ;
.dw 0x39FA ;
.dw 0x39FB ;
.dw 0x39FC ;
.dw 0x39FD ;
.dw 0x39FE ;
#if 0
// RETS = EMUDAT; is valid
.dw 0x39FF ;
#endif
.dw 0x3D06 ;
.dw 0x3D07 ;
.dw 0x3D0E ;
.dw 0x3D0F ;
.dw 0x3D16 ;
.dw 0x3D17 ;
.dw 0x3D1E ;
.dw 0x3D1F ;
.dw 0x3D26 ;
.dw 0x3D27 ;
.dw 0x3D2E ;
.dw 0x3D2F ;
.dw 0x3D36 ;
.dw 0x3D37 ;
.dw 0x3D3E ;
.dw 0x3D3F ;
.dw 0x3F0E ;
.dw 0x3F0F ;
.dw 0x3F16 ;
.dw 0x3F17 ;
.dw 0x3F1E ;
.dw 0x3F1F ;
.dw 0x3F26 ;
.dw 0x3F27 ;
.dw 0x3F2E ;
.dw 0x3F2F ;
.dw 0x3F36 ;
.dw 0x3F37 ;
#if 0
// EMUDAT = ASTAT; is valid
.dw 0x3F3E ;
// EMUDAT = RETS; is valid
.dw 0x3F3F ;
#endif
.dw 0x3936 ;
.dw 0x3937 ;
.dw 0x393E ;
.dw 0x393F ;
.dw 0x3C80 ;
.dw 0x3C81 ;
.dw 0x3C82 ;
.dw 0x3C83 ;
.dw 0x3C84 ;
.dw 0x3C85 ;
.dw 0x3C86 ;
.dw 0x3C87 ;
.dw 0x3C88 ;
.dw 0x3C89 ;
.dw 0x3C8A ;
.dw 0x3C8B ;
.dw 0x3C8C ;
.dw 0x3C8D ;
.dw 0x3C8E ;
.dw 0x3C8F ;
.dw 0x3C90 ;
.dw 0x3C91 ;
.dw 0x3C92 ;
.dw 0x3C93 ;
.dw 0x3C94 ;
.dw 0x3C95 ;
.dw 0x3C96 ;
.dw 0x3C97 ;
.dw 0x3C98 ;
.dw 0x3C99 ;
.dw 0x3C9A ;
.dw 0x3C9B ;
.dw 0x3C9C ;
.dw 0x3C9D ;
.dw 0x3C9E ;
.dw 0x3C9F ;
.dw 0x3CA0 ;
.dw 0x3CA1 ;
.dw 0x3CA2 ;
.dw 0x3CA3 ;
.dw 0x3CA4 ;
.dw 0x3CA5 ;
.dw 0x3CA6 ;
.dw 0x3CA7 ;
.dw 0x3CA8 ;
.dw 0x3CA9 ;
.dw 0x3CAA ;
.dw 0x3CAB ;
.dw 0x3CAC ;
.dw 0x3CAD ;
.dw 0x3CAE ;
.dw 0x3CAF ;
.dw 0x3CB0 ;
.dw 0x3CB1 ;
.dw 0x3CB2 ;
.dw 0x3CB3 ;
.dw 0x3CB4 ;
.dw 0x3CB5 ;
.dw 0x3CB6 ;
.dw 0x3CB7 ;
.dw 0x3CB8 ;
.dw 0x3CB9 ;
.dw 0x3CBA ;
.dw 0x3CBB ;
.dw 0x3CBC ;
.dw 0x3CBD ;
.dw 0x3CBE ;
.dw 0x3CBF ;
.dw 0x3CC0 ;
.dw 0x3CC1 ;
.dw 0x3CC2 ;
.dw 0x3CC3 ;
.dw 0x3CC4 ;
.dw 0x3CC5 ;
.dw 0x3CC6 ;
.dw 0x3CC7 ;
.dw 0x3CC8 ;
.dw 0x3CC9 ;
.dw 0x3CCA ;
.dw 0x3CCB ;
.dw 0x3CCC ;
.dw 0x3CCD ;
.dw 0x3CCE ;
.dw 0x3CCF ;
.dw 0x3CD0 ;
.dw 0x3CD1 ;
.dw 0x3CD2 ;
.dw 0x3CD3 ;
.dw 0x3CD4 ;
.dw 0x3CD5 ;
.dw 0x3CD6 ;
.dw 0x3CD7 ;
.dw 0x3CD8 ;
.dw 0x3CD9 ;
.dw 0x3CDA ;
.dw 0x3CDB ;
.dw 0x3CDC ;
.dw 0x3CDD ;
.dw 0x3CDE ;
.dw 0x3CDF ;
.dw 0x3CE0 ;
.dw 0x3CE1 ;
.dw 0x3CE2 ;
.dw 0x3CE3 ;
.dw 0x3CE4 ;
.dw 0x3CE5 ;
.dw 0x3CE6 ;
.dw 0x3CE7 ;
.dw 0x3CE8 ;
.dw 0x3CE9 ;
.dw 0x3CEA ;
.dw 0x3CEB ;
.dw 0x3CEC ;
.dw 0x3CED ;
.dw 0x3CEE ;
.dw 0x3CEF ;
.dw 0x3CF0 ;
.dw 0x3CF1 ;
.dw 0x3CF2 ;
.dw 0x3CF3 ;
.dw 0x3CF4 ;
.dw 0x3CF5 ;
.dw 0x3CF6 ;
.dw 0x3CF7 ;
.dw 0x3CF8 ;
.dw 0x3CF9 ;
.dw 0x3CFA ;
.dw 0x3CFB ;
.dw 0x3CFC ;
.dw 0x3CFD ;
.dw 0x3CFE ;
.dw 0x3CFF ;
.dw 0x3E88 ;
.dw 0x3E89 ;
.dw 0x3E8A ;
.dw 0x3E8B ;
.dw 0x3E8C ;
.dw 0x3E8D ;
.dw 0x3E8E ;
.dw 0x3E8F ;
.dw 0x3E90 ;
.dw 0x3E91 ;
.dw 0x3E92 ;
.dw 0x3E93 ;
.dw 0x3E94 ;
.dw 0x3E95 ;
.dw 0x3E96 ;
.dw 0x3E97 ;
.dw 0x3E98 ;
.dw 0x3E99 ;
.dw 0x3E9A ;
.dw 0x3E9B ;
.dw 0x3E9C ;
.dw 0x3E9D ;
.dw 0x3E9E ;
.dw 0x3E9F ;
.dw 0x3EA0 ;
.dw 0x3EA1 ;
.dw 0x3EA2 ;
.dw 0x3EA3 ;
.dw 0x3EA4 ;
.dw 0x3EA5 ;
.dw 0x3EA6 ;
.dw 0x3EA7 ;
.dw 0x3EA8 ;
.dw 0x3EA9 ;
.dw 0x3EAA ;
.dw 0x3EAB ;
.dw 0x3EAC ;
.dw 0x3EAD ;
.dw 0x3EAE ;
.dw 0x3EAF ;
.dw 0x3EB0 ;
.dw 0x3EB1 ;
.dw 0x3EB2 ;
.dw 0x3EB3 ;
.dw 0x3EB4 ;
.dw 0x3EB5 ;
.dw 0x3EB6 ;
.dw 0x3EB7 ;
#if 0
// EMUDAT = Ireg; is valid
.dw 0x3EB8 ;
.dw 0x3EB9 ;
.dw 0x3EBA ;
.dw 0x3EBB ;
// EMUDAT = Mreg; is valid
.dw 0x3EBC ;
.dw 0x3EBD ;
.dw 0x3EBE ;
.dw 0x3EBF ;
#endif
.dw 0x3EC8 ;
.dw 0x3EC9 ;
.dw 0x3ECA ;
.dw 0x3ECB ;
.dw 0x3ECC ;
.dw 0x3ECD ;
.dw 0x3ECE ;
.dw 0x3ECF ;
.dw 0x3ED0 ;
.dw 0x3ED1 ;
.dw 0x3ED2 ;
.dw 0x3ED3 ;
.dw 0x3ED4 ;
.dw 0x3ED5 ;
.dw 0x3ED6 ;
.dw 0x3ED7 ;
.dw 0x3ED8 ;
.dw 0x3ED9 ;
.dw 0x3EDA ;
.dw 0x3EDB ;
.dw 0x3EDC ;
.dw 0x3EDD ;
.dw 0x3EDE ;
.dw 0x3EDF ;
.dw 0x3EE0 ;
.dw 0x3EE1 ;
.dw 0x3EE2 ;
.dw 0x3EE3 ;
.dw 0x3EE4 ;
.dw 0x3EE5 ;
.dw 0x3EE6 ;
.dw 0x3EE7 ;
.dw 0x3EE8 ;
.dw 0x3EE9 ;
.dw 0x3EEA ;
.dw 0x3EEB ;
.dw 0x3EEC ;
.dw 0x3EED ;
.dw 0x3EEE ;
.dw 0x3EEF ;
.dw 0x3EF0 ;
.dw 0x3EF1 ;
.dw 0x3EF2 ;
.dw 0x3EF3 ;
.dw 0x3EF4 ;
.dw 0x3EF5 ;
.dw 0x3EF6 ;
.dw 0x3EF7 ;
#if 0
// EMUDAT = Breg; is valid
.dw 0x3EF8 ;
.dw 0x3EF9 ;
.dw 0x3EFA ;
.dw 0x3EFB ;
// EMUDAT = Lreg; is valid
.dw 0x3EFC ;
.dw 0x3EFD ;
.dw 0x3EFE ;
.dw 0x3EFF ;
#endif
.dw 0x38B0 ;
.dw 0x38B1 ;
.dw 0x38B2 ;
.dw 0x38B3 ;
.dw 0x38B4 ;
.dw 0x38B5 ;
.dw 0x38B6 ;
.dw 0x38B7 ;
.dw 0x38B8 ;
.dw 0x38B9 ;
.dw 0x38BA ;
.dw 0x38BB ;
.dw 0x38BC ;
.dw 0x38BD ;
.dw 0x38BE ;
.dw 0x38BF ;
.dw 0x38F0 ;
.dw 0x38F1 ;
.dw 0x38F2 ;
.dw 0x38F3 ;
.dw 0x38F4 ;
.dw 0x38F5 ;
.dw 0x38F6 ;
.dw 0x38F7 ;
.dw 0x38F8 ;
.dw 0x38F9 ;
.dw 0x38FA ;
.dw 0x38FB ;
.dw 0x38FC ;
.dw 0x38FD ;
.dw 0x38FE ;
.dw 0x38FF ;
#if 0
// Preg = sysreg; is valid
.dw 0x3380 ;
.dw 0x3381 ;
.dw 0x3382 ;
.dw 0x3383 ;
.dw 0x3384 ;
.dw 0x3385 ;
.dw 0x3386 ;
.dw 0x3387 ;
.dw 0x3388 ;
.dw 0x3389 ;
.dw 0x338A ;
.dw 0x338B ;
.dw 0x338C ;
.dw 0x338D ;
.dw 0x338E ;
.dw 0x338F ;
.dw 0x3390 ;
.dw 0x3391 ;
.dw 0x3392 ;
.dw 0x3393 ;
.dw 0x3394 ;
.dw 0x3395 ;
.dw 0x3396 ;
.dw 0x3397 ;
.dw 0x3398 ;
.dw 0x3399 ;
.dw 0x339A ;
.dw 0x339B ;
.dw 0x339C ;
.dw 0x339D ;
.dw 0x339E ;
.dw 0x339F ;
.dw 0x33A0 ;
.dw 0x33A1 ;
.dw 0x33A2 ;
.dw 0x33A3 ;
.dw 0x33A4 ;
.dw 0x33A5 ;
.dw 0x33A6 ;
.dw 0x33A7 ;
.dw 0x33A8 ;
.dw 0x33A9 ;
.dw 0x33AA ;
.dw 0x33AB ;
.dw 0x33AC ;
.dw 0x33AD ;
.dw 0x33AE ;
.dw 0x33AF ;
.dw 0x33B0 ;
.dw 0x33B1 ;
.dw 0x33B2 ;
.dw 0x33B3 ;
.dw 0x33B4 ;
.dw 0x33B5 ;
.dw 0x33B6 ;
.dw 0x33B7 ;
.dw 0x33B8 ;
.dw 0x33B9 ;
.dw 0x33BA ;
.dw 0x33BB ;
.dw 0x33BC ;
.dw 0x33BD ;
.dw 0x33BE ;
.dw 0x33BF ;
.dw 0x33C1 ;
.dw 0x33C2 ;
.dw 0x33C3 ;
.dw 0x33C4 ;
.dw 0x33C5 ;
.dw 0x33C6 ;
.dw 0x33C7 ;
.dw 0x33C9 ;
.dw 0x33CA ;
.dw 0x33CB ;
.dw 0x33CC ;
.dw 0x33CD ;
.dw 0x33CE ;
.dw 0x33CF ;
.dw 0x33D1 ;
.dw 0x33D2 ;
.dw 0x33D3 ;
.dw 0x33D4 ;
.dw 0x33D5 ;
.dw 0x33D6 ;
.dw 0x33D7 ;
.dw 0x33D9 ;
.dw 0x33DA ;
.dw 0x33DB ;
.dw 0x33DC ;
.dw 0x33DD ;
.dw 0x33DE ;
.dw 0x33DF ;
.dw 0x33E1 ;
.dw 0x33E2 ;
.dw 0x33E3 ;
.dw 0x33E4 ;
.dw 0x33E5 ;
.dw 0x33E6 ;
.dw 0x33E7 ;
.dw 0x33E9 ;
.dw 0x33EA ;
.dw 0x33EB ;
.dw 0x33EC ;
.dw 0x33ED ;
.dw 0x33EE ;
.dw 0x33EF ;
.dw 0x33F1 ;
.dw 0x33F2 ;
.dw 0x33F3 ;
.dw 0x33F4 ;
.dw 0x33F5 ;
.dw 0x33F6 ;
.dw 0x33F7 ;
.dw 0x33F9 ;
.dw 0x33FA ;
.dw 0x33FB ;
.dw 0x33FC ;
.dw 0x33FD ;
.dw 0x33FE ;
.dw 0x33FF ;
.dw 0x3306 ;
.dw 0x3307 ;
.dw 0x330E ;
.dw 0x330F ;
.dw 0x3316 ;
.dw 0x3317 ;
.dw 0x331E ;
.dw 0x331F ;
.dw 0x3326 ;
.dw 0x3327 ;
.dw 0x332E ;
.dw 0x332F ;
.dw 0x3336 ;
.dw 0x3337 ;
.dw 0x333E ;
.dw 0x333F ;
#endif
.dw 0x3580 ;
.dw 0x3581 ;
.dw 0x3582 ;
.dw 0x3583 ;
.dw 0x3584 ;
.dw 0x3585 ;
.dw 0x3586 ;
.dw 0x3587 ;
.dw 0x3588 ;
.dw 0x3589 ;
.dw 0x358A ;
.dw 0x358B ;
.dw 0x358C ;
.dw 0x358D ;
.dw 0x358E ;
.dw 0x358F ;
.dw 0x3590 ;
.dw 0x3591 ;
.dw 0x3592 ;
.dw 0x3593 ;
.dw 0x3594 ;
.dw 0x3595 ;
.dw 0x3596 ;
.dw 0x3597 ;
.dw 0x3598 ;
.dw 0x3599 ;
.dw 0x359A ;
.dw 0x359B ;
.dw 0x359C ;
.dw 0x359D ;
.dw 0x359E ;
.dw 0x359F ;
.dw 0x35A0 ;
.dw 0x35A1 ;
.dw 0x35A2 ;
.dw 0x35A3 ;
.dw 0x35A4 ;
.dw 0x35A5 ;
.dw 0x35A6 ;
.dw 0x35A7 ;
.dw 0x35A8 ;
.dw 0x35A9 ;
.dw 0x35AA ;
.dw 0x35AB ;
.dw 0x35AC ;
.dw 0x35AD ;
.dw 0x35AE ;
.dw 0x35AF ;
.dw 0x35B0 ;
.dw 0x35B1 ;
.dw 0x35B2 ;
.dw 0x35B3 ;
.dw 0x35B4 ;
.dw 0x35B5 ;
.dw 0x35B6 ;
.dw 0x35B7 ;
.dw 0x35B8 ;
.dw 0x35B9 ;
.dw 0x35BA ;
.dw 0x35BB ;
.dw 0x35BC ;
.dw 0x35BD ;
.dw 0x35BE ;
.dw 0x35BF ;
.dw 0x35C1 ;
.dw 0x35C2 ;
.dw 0x35C3 ;
.dw 0x35C4 ;
.dw 0x35C5 ;
.dw 0x35C6 ;
#if 0
// Ireg = EMUDAT; is valid
.dw 0x35C7 ;
#endif
.dw 0x35C9 ;
.dw 0x35CA ;
.dw 0x35CB ;
.dw 0x35CC ;
.dw 0x35CD ;
.dw 0x35CE ;
#if 0
// Ireg = EMUDAT; is valid
.dw 0x35CF ;
#endif
.dw 0x35D1 ;
.dw 0x35D2 ;
.dw 0x35D3 ;
.dw 0x35D4 ;
.dw 0x35D5 ;
.dw 0x35D6 ;
#if 0
// Ireg = EMUDAT; is valid
.dw 0x35D7 ;
#endif
.dw 0x35D9 ;
.dw 0x35DA ;
.dw 0x35DB ;
.dw 0x35DC ;
.dw 0x35DD ;
.dw 0x35DE ;
#if 0
// Ireg = EMUDAT; is valid
.dw 0x35DF ;
#endif
.dw 0x35E1 ;
.dw 0x35E2 ;
.dw 0x35E3 ;
.dw 0x35E4 ;
.dw 0x35E5 ;
.dw 0x35E6 ;
#if 0
// Mreg = EMUDAT; is valid
.dw 0x35E7 ;
#endif
.dw 0x35E9 ;
.dw 0x35EA ;
.dw 0x35EB ;
.dw 0x35EC ;
.dw 0x35ED ;
.dw 0x35EE ;
#if 0
// Mreg = EMUDAT; is valid
.dw 0x35EF ;
#endif
.dw 0x35F1 ;
.dw 0x35F2 ;
.dw 0x35F3 ;
.dw 0x35F4 ;
.dw 0x35F5 ;
.dw 0x35F6 ;
#if 0
// Mreg = EMUDAT; is valid
.dw 0x35F7 ;
#endif
.dw 0x35F9 ;
.dw 0x35FA ;
.dw 0x35FB ;
.dw 0x35FC ;
.dw 0x35FD ;
.dw 0x35FE ;
#if 0
// Mreg = EMUDAT; is valid
.dw 0x35FF ;
#endif
.dw 0x3780 ;
.dw 0x3781 ;
.dw 0x3782 ;
.dw 0x3783 ;
.dw 0x3784 ;
.dw 0x3785 ;
.dw 0x3786 ;
.dw 0x3787 ;
.dw 0x3788 ;
.dw 0x3789 ;
.dw 0x378A ;
.dw 0x378B ;
.dw 0x378C ;
.dw 0x378D ;
.dw 0x378E ;
.dw 0x378F ;
.dw 0x3790 ;
.dw 0x3791 ;
.dw 0x3792 ;
.dw 0x3793 ;
.dw 0x3794 ;
.dw 0x3795 ;
.dw 0x3796 ;
.dw 0x3797 ;
.dw 0x3798 ;
.dw 0x3799 ;
.dw 0x379A ;
.dw 0x379B ;
.dw 0x379C ;
.dw 0x379D ;
.dw 0x379E ;
.dw 0x379F ;
.dw 0x37A0 ;
.dw 0x37A1 ;
.dw 0x37A2 ;
.dw 0x37A3 ;
.dw 0x37A4 ;
.dw 0x37A5 ;
.dw 0x37A6 ;
.dw 0x37A7 ;
.dw 0x37A8 ;
.dw 0x37A9 ;
.dw 0x37AA ;
.dw 0x37AB ;
.dw 0x37AC ;
.dw 0x37AD ;
.dw 0x37AE ;
.dw 0x37AF ;
.dw 0x37B0 ;
.dw 0x37B1 ;
.dw 0x37B2 ;
.dw 0x37B3 ;
.dw 0x37B4 ;
.dw 0x37B5 ;
.dw 0x37B6 ;
.dw 0x37B7 ;
.dw 0x37B8 ;
.dw 0x37B9 ;
.dw 0x37BA ;
.dw 0x37BB ;
.dw 0x37BC ;
.dw 0x37BD ;
.dw 0x37BE ;
.dw 0x37BF ;
.dw 0x37C1 ;
.dw 0x37C2 ;
.dw 0x37C3 ;
.dw 0x37C4 ;
.dw 0x37C5 ;
.dw 0x37C6 ;
#if 0
// EMUDAT = Breg; is valid
.dw 0x37C7 ;
#endif
.dw 0x37C9 ;
.dw 0x37CA ;
.dw 0x37CB ;
.dw 0x37CC ;
.dw 0x37CD ;
.dw 0x37CE ;
#if 0
// EMUDAT = Breg; is valid
.dw 0x37CF ;
#endif
.dw 0x37D1 ;
.dw 0x37D2 ;
.dw 0x37D3 ;
.dw 0x37D4 ;
.dw 0x37D5 ;
.dw 0x37D6 ;
#if 0
// EMUDAT = Breg; is valid
.dw 0x37D7 ;
#endif
.dw 0x37D9 ;
.dw 0x37DA ;
.dw 0x37DB ;
.dw 0x37DC ;
.dw 0x37DD ;
.dw 0x37DE ;
#if 0
// EMUDAT = Breg; is valid
.dw 0x37DF ;
#endif
.dw 0x37E1 ;
.dw 0x37E2 ;
.dw 0x37E3 ;
.dw 0x37E4 ;
.dw 0x37E5 ;
.dw 0x37E6 ;
#if 0
// EMUDAT = Lreg; is valid
.dw 0x37E7 ;
#endif
.dw 0x37E9 ;
.dw 0x37EA ;
.dw 0x37EB ;
.dw 0x37EC ;
.dw 0x37ED ;
.dw 0x37EE ;
#if 0
// EMUDAT = Lreg; is valid
.dw 0x37EF ;
#endif
.dw 0x37F1 ;
.dw 0x37F2 ;
.dw 0x37F3 ;
.dw 0x37F4 ;
.dw 0x37F5 ;
.dw 0x37F6 ;
#if 0
// EMUDAT = Lreg; is valid
.dw 0x37F7 ;
#endif
.dw 0x37F9 ;
.dw 0x37FA ;
.dw 0x37FB ;
.dw 0x37FC ;
.dw 0x37FD ;
.dw 0x37FE ;
#if 0
// EMUDAT = Lreg; is valid
.dw 0x37FF ;
#endif
.dw 0x3506 ;
.dw 0x3507 ;
.dw 0x350E ;
.dw 0x350F ;
.dw 0x3516 ;
.dw 0x3517 ;
.dw 0x351E ;
.dw 0x351F ;
.dw 0x3526 ;
.dw 0x3527 ;
.dw 0x352E ;
.dw 0x352F ;
.dw 0x3536 ;
.dw 0x3537 ;
.dw 0x353E ;
.dw 0x353F ;
.dw 0x3706 ;
.dw 0x3707 ;
.dw 0x370E ;
.dw 0x370F ;
.dw 0x3716 ;
.dw 0x3717 ;
.dw 0x371E ;
.dw 0x371F ;
.dw 0x3726 ;
.dw 0x3727 ;
.dw 0x372E ;
.dw 0x372F ;
.dw 0x3736 ;
.dw 0x3737 ;
.dw 0x373E ;
.dw 0x373F ;
.dw 0x4180 ;
.dw 0x4181 ;
.dw 0x4182 ;
.dw 0x4183 ;
.dw 0x4184 ;
.dw 0x4185 ;
.dw 0x4186 ;
.dw 0x4187 ;
.dw 0x4188 ;
.dw 0x4189 ;
.dw 0x418A ;
.dw 0x418B ;
.dw 0x418C ;
.dw 0x418D ;
.dw 0x418E ;
.dw 0x418F ;
.dw 0x4190 ;
.dw 0x4191 ;
.dw 0x4192 ;
.dw 0x4193 ;
.dw 0x4194 ;
.dw 0x4195 ;
.dw 0x4196 ;
.dw 0x4197 ;
.dw 0x4198 ;
.dw 0x4199 ;
.dw 0x419A ;
.dw 0x419B ;
.dw 0x419C ;
.dw 0x419D ;
.dw 0x419E ;
.dw 0x419F ;
.dw 0x41A0 ;
.dw 0x41A1 ;
.dw 0x41A2 ;
.dw 0x41A3 ;
.dw 0x41A4 ;
.dw 0x41A5 ;
.dw 0x41A6 ;
.dw 0x41A7 ;
.dw 0x41A8 ;
.dw 0x41A9 ;
.dw 0x41AA ;
.dw 0x41AB ;
.dw 0x41AC ;
.dw 0x41AD ;
.dw 0x41AE ;
.dw 0x41AF ;
.dw 0x41B0 ;
.dw 0x41B1 ;
.dw 0x41B2 ;
.dw 0x41B3 ;
.dw 0x41B4 ;
.dw 0x41B5 ;
.dw 0x41B6 ;
.dw 0x41B7 ;
.dw 0x41B8 ;
.dw 0x41B9 ;
.dw 0x41BA ;
.dw 0x41BB ;
.dw 0x41BC ;
.dw 0x41BD ;
.dw 0x41BE ;
.dw 0x41BF ;
.dw 0x41C0 ;
.dw 0x41C1 ;
.dw 0x41C2 ;
.dw 0x41C3 ;
.dw 0x41C4 ;
.dw 0x41C5 ;
.dw 0x41C6 ;
.dw 0x41C7 ;
.dw 0x41C8 ;
.dw 0x41C9 ;
.dw 0x41CA ;
.dw 0x41CB ;
.dw 0x41CC ;
.dw 0x41CD ;
.dw 0x41CE ;
.dw 0x41CF ;
.dw 0x41D0 ;
.dw 0x41D1 ;
.dw 0x41D2 ;
.dw 0x41D3 ;
.dw 0x41D4 ;
.dw 0x41D5 ;
.dw 0x41D6 ;
.dw 0x41D7 ;
.dw 0x41D8 ;
.dw 0x41D9 ;
.dw 0x41DA ;
.dw 0x41DB ;
.dw 0x41DC ;
.dw 0x41DD ;
.dw 0x41DE ;
.dw 0x41DF ;
.dw 0x41E0 ;
.dw 0x41E1 ;
.dw 0x41E2 ;
.dw 0x41E3 ;
.dw 0x41E4 ;
.dw 0x41E5 ;
.dw 0x41E6 ;
.dw 0x41E7 ;
.dw 0x41E8 ;
.dw 0x41E9 ;
.dw 0x41EA ;
.dw 0x41EB ;
.dw 0x41EC ;
.dw 0x41ED ;
.dw 0x41EE ;
.dw 0x41EF ;
.dw 0x41F0 ;
.dw 0x41F1 ;
.dw 0x41F2 ;
.dw 0x41F3 ;
.dw 0x41F4 ;
.dw 0x41F5 ;
.dw 0x41F6 ;
.dw 0x41F7 ;
.dw 0x41F8 ;
.dw 0x41F9 ;
.dw 0x41FA ;
.dw 0x41FB ;
.dw 0x41FC ;
.dw 0x41FD ;
.dw 0x41FE ;
.dw 0x41FF ;
.ifndef BFIN_HW
// XXX: These cause double fault on hardware when run in IVG15 !?
.dw 0x9040 ;
.dw 0x9049 ;
.dw 0x9052 ;
.dw 0x905B ;
.dw 0x9064 ;
.dw 0x906D ;
.dw 0x9076 ;
.dw 0x907F ;
.dw 0x90C0 ;
.dw 0x90C9 ;
.dw 0x90D2 ;
.dw 0x90DB ;
.dw 0x90E4 ;
.dw 0x90ED ;
.dw 0x90F6 ;
.dw 0x90FF ;
.endif
.dw 0x9180 ;
// Starting 32bit s section COUNT = 3481
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x21;
.ifndef BFIN_HW
CHECKREG(r5, 2651 - 507); // count of all 16 bit UI's.
.else
CHECKREG(r5, 2651 - 524); // count of all 16 bit UI's.
.endif
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 16 bit illegal opcode handler - skips bad instruction
// handler MADE LEAN and destructive so test runs more quckly
// se_undefinedinstruction1.dsp tests using a "nice" handler
// [--sp] = ASTAT; // save what we damage
// [--sp] = (r7 - r6);
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
R6 = 0x22; // Also accept illegal insn combo
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
dbg_fail;
UNDEFINEDINSTRUCTION:
R7 = RETX; // Fix up return address
r4 += 2;
CC = r4 == r7;
if !CC jump fail;
R7 += 2; // skip offending 16 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
// (r7 - r6) = [sp++];
// ASTAT = [sp++];
RTX;
fail:
dbg_fail;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 6,307 | sim/testsuite/bfin/c_ldst_ld_d_p_pp.s | //Original:/testcases/core/c_ldst_ld_d_p_pp/c_ldst_ld_d_p_pp.dsp
// Spec Reference: c_ldst ld d [p++]
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym p5, DATA_ADDR_1;
loadsym p1, DATA_ADDR_2;
loadsym p2, DATA_ADDR_3;
loadsym p4, DATA_ADDR_5;
loadsym fp, DATA_ADDR_6;
R0 = [ P5 ++ ];
R1 = [ P1 ++ ];
R2 = [ P2 ++ ];
R4 = [ P4 ++ ];
R5 = [ FP ++ ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r2, 0x40414243;
CHECKREG r4, 0x80818283;
CHECKREG r5, 0x00010203;
R1 = [ P5 ++ ];
R2 = [ P1 ++ ];
R3 = [ P2 ++ ];
R5 = [ P4 ++ ];
R6 = [ FP ++ ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x04050607;
CHECKREG r2, 0x24252627;
CHECKREG r3, 0x44454647;
CHECKREG r5, 0x84858687;
CHECKREG r6, 0x04050607;
R2 = [ P5 ++ ];
R3 = [ P1 ++ ];
R4 = [ P2 ++ ];
R6 = [ P4 ++ ];
R7 = [ FP ++ ];
CHECKREG r1, 0x04050607;
CHECKREG r2, 0x08090A0B;
CHECKREG r3, 0x28292A2B;
CHECKREG r4, 0x48494A4B;
CHECKREG r6, 0x88898A8B;
CHECKREG r7, 0x08090A0B;
R3 = [ P5 ++ ];
R4 = [ P1 ++ ];
R5 = [ P2 ++ ];
R7 = [ P4 ++ ];
R0 = [ FP ++ ];
CHECKREG r0, 0x0C0D0E0F;
CHECKREG r2, 0x08090A0B;
CHECKREG r3, 0x0C0D0E0F;
CHECKREG r4, 0x2C2D2E2F;
CHECKREG r5, 0x4C4D4E4F;
CHECKREG r7, 0x8C8D8E8F;
R4 = [ P5 ++ ];
R5 = [ P1 ++ ];
R6 = [ P2 ++ ];
R0 = [ P4 ++ ];
R1 = [ FP ++ ];
CHECKREG r0, 0x90919293;
CHECKREG r1, 0x10111213;
CHECKREG r3, 0x0C0D0E0F;
CHECKREG r4, 0x10111213;
CHECKREG r5, 0x30313233;
CHECKREG r6, 0x50515253;
R5 = [ P5 ++ ];
R6 = [ P1 ++ ];
R7 = [ P2 ++ ];
R1 = [ P4 ++ ];
R2 = [ FP ++ ];
CHECKREG r1, 0x94959697;
CHECKREG r2, 0x14151617;
CHECKREG r4, 0x10111213;
CHECKREG r5, 0x14151617;
CHECKREG r6, 0x34353637;
CHECKREG r7, 0x54555657;
R6 = [ P5 ++ ];
R7 = [ P1 ++ ];
R0 = [ P2 ++ ];
R2 = [ P4 ++ ];
R3 = [ FP ++ ];
CHECKREG r0, 0x58595A5B;
CHECKREG r2, 0x98999A9B;
CHECKREG r3, 0x18191A1B;
CHECKREG r5, 0x14151617;
CHECKREG r6, 0x18191A1B;
CHECKREG r7, 0x38393A3B;
R7 = [ P5 ++ ];
R0 = [ P1 ++ ];
R1 = [ P2 ++ ];
R3 = [ P4 ++ ];
R4 = [ FP ++ ];
CHECKREG r0, 0x3C3D3E3F;
CHECKREG r1, 0xC5C6C7C8;
CHECKREG r3, 0x9C9D9E9F;
CHECKREG r4, 0x1C1D1E1F;
CHECKREG r6, 0x18191A1B;
CHECKREG r7, 0x1C1D1E1F;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 4,737 | sim/testsuite/bfin/c_dspldst_st_dr_ippm.s | //Original:/testcases/core/c_dspldst_st_dr_ippm/c_dspldst_st_dr_ippm.dsp
// Spec Reference: c_dspldst st_dr_ippm
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0a234507;
imm32 r1, 0x1b345618;
imm32 r2, 0x2c456729;
imm32 r3, 0x3d56783a;
imm32 r4, 0x4e67894b;
imm32 r5, 0x5f789a5c;
imm32 r6, 0x6089ab6d;
imm32 r7, 0x719abc7e;
M0 = 4 (X);
M1 = 0x4 (X);
M2 = 0x4 (X);
M3 = 0x4 (X);
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
[ I0 ++ M0 ] = R0;
[ I1 ++ M1 ] = R1;
[ I2 ++ M2 ] = R2;
[ I3 ++ M3 ] = R3;
[ I0 ++ M1 ] = R1;
[ I1 ++ M2 ] = R2;
[ I2 ++ M3 ] = R3;
[ I3 ++ M0 ] = R4;
[ I0 ++ M2 ] = R3;
[ I1 ++ M3 ] = R4;
[ I2 ++ M0 ] = R5;
[ I3 ++ M1 ] = R6;
[ I0 ++ M3 ] = R4;
[ I1 ++ M0 ] = R5;
[ I2 ++ M1 ] = R6;
[ I3 ++ M2 ] = R7;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ M0 ];
R1 = [ I1 ++ M1 ];
R2 = [ I2 ++ M2 ];
R3 = [ I3 ++ M3 ];
R4 = [ I0 ++ M1 ];
R5 = [ I1 ++ M2 ];
R6 = [ I2 ++ M3 ];
R7 = [ I3 ++ M0 ];
CHECKREG r0, 0x0A234507;
CHECKREG r1, 0x1B345618;
CHECKREG r2, 0x2C456729;
CHECKREG r3, 0x3D56783A;
CHECKREG r4, 0x1B345618;
CHECKREG r5, 0x2C456729;
CHECKREG r6, 0x3D56783A;
CHECKREG r7, 0x4E67894B;
R0 = [ I0 ++ M2 ];
R1 = [ I1 ++ M3 ];
R2 = [ I2 ++ M0 ];
R3 = [ I3 ++ M1 ];
R4 = [ I0 ++ M3 ];
R5 = [ I1 ++ M0 ];
R6 = [ I2 ++ M1 ];
R7 = [ I3 ++ M2 ];
CHECKREG r0, 0x3D56783A;
CHECKREG r1, 0x4E67894B;
CHECKREG r2, 0x5F789A5C;
CHECKREG r3, 0x6089AB6D;
CHECKREG r4, 0x4E67894B;
CHECKREG r5, 0x5F789A5C;
CHECKREG r6, 0x6089AB6D;
CHECKREG r7, 0x719ABC7E;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 17,518 | sim/testsuite/bfin/se_loop_kill_dcr.S | //Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr/se_loop_kill_dcr.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x1 (Z);
P1 = 0x2 (Z);
P2 = 0x3 (Z);
P3 = 0x4 (Z);
P4 = 0x5 (Z);
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (with Kill WB)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in WB
LSETUP ( L0T , L0T ) LC0 = P0;
EXCPT 0x5;
L0T:R0 += 5;
// Kill Valid Dcr in EX3
LSETUP ( L1T , L1B ) LC0 = P0;
EXCPT 0x5;
L1T:R0 += 5;
L1B:R1 += 4;
// Kill Valid Dcr in EX2
LSETUP ( L2T , L2B ) LC0 = P0;
EXCPT 0x5;
L2T:R0 += 5;
R1 += 4;
L2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( L3T , L3B ) LC0 = P0;
EXCPT 0x5;
L3T:R0 += 5;
R1 += 4;
R2 += 3;
L3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( L4T , L4B ) LC0 = P0;
EXCPT 0x5;
L4T:R0 += 5;
R1 += 4;
R2 += 3;
R3 += 2;
L4B:R4 += 1;
// Kill Valid Dcr in WB, EX3
LSETUP ( L5T , L5T ) LC0 = P1;
EXCPT 0x5;
L5T:R1 += 5;
// Kill Valid Dcr in EX3, EX2
LSETUP ( L6T , L6T ) LC0 = P1;
EXCPT 0x5;
NOP;
L6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( L7T , L7T ) LC0 = P1;
EXCPT 0x5;
NOP;
NOP;
L7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( L8T , L8T ) LC0 = P1;
EXCPT 0x5;
NOP;
NOP;
NOP;
L8T:R4 += 5;
// Kill Valid Dcr in WB, EX3, EX2
LSETUP ( L9T , L9T ) LC0 = P2;
EXCPT 0x5;
L9T:R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( LAT , LAT ) LC0 = P2;
EXCPT 0x5;
NOP;
LAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( LBT , LBT ) LC0 = P2;
EXCPT 0x5;
NOP;
NOP;
LBT:
R5 += 5;
// Kill Valid Dcr in WB, EX3, EX2, EX1
LSETUP ( LCT , LCT ) LC0 = P3;
EXCPT 0x5;
LCT:
R7 += 7;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( LDT , LDT ) LC0 = P3;
EXCPT 0x5;
NOP;
LDT:
R0 += 7;
// Kill Valid Dcr in WB, EX3, EX2, EX1, AC
LSETUP ( LET , LET ) LC0 = P4;
EXCPT 0x5;
LET:
R1 += 1;
// Kill Valid Dcr in WB, EX2
LSETUP ( LFT , LFB ) LC0 = P1;
LFT:
EXCPT 0x5;
LFB:
R1 += 2;
// Kill Valid Dcr in WB, EX1
LSETUP ( LGT , LGB ) LC0 = P1;
LGT:
R2 += 3;
EXCPT 0x5;
LGB:
R1 += 2;
// Kill Valid Dcr in WB, AC
LSETUP ( LHT , LHB ) LC0 = P1;
LHT:
R2 += 3;
R3 += 4;
EXCPT 0x5;
LHB:
R1 += 2;
// Kill Valid Dcr in EX3, EX1
LSETUP ( LIT , LIB ) LC0 = P1;
EXCPT 0x5;
LIT:
R2 += 1;
LIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( LJT , LJB ) LC0 = P1;
LJT:
EXCPT 0x5;
R2 += 1;
LJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( LKT , LKB ) LC0 = P1;
EXCPT 0x5;
NOP;
LKT:
R2 += 1;
LKB:
R1 += 2;
// Kill Valid Dcr in WB, EX2, AC
LSETUP ( LLT , LLB ) LC0 = P2;
LLT:
EXCPT 0x5;
LLB:
R2 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (with Kill WB)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in WB
LSETUP ( M0T , M0T ) LC1 = P0;
EXCPT 0x5;
M0T:R0 += 5;
// Kill Valid Dcr in EX3
LSETUP ( M1T , M1B ) LC1 = P0;
EXCPT 0x5;
M1T:R0 += 5;
M1B:R1 += 4;
// Kill Valid Dcr in EX2
LSETUP ( M2T , M2B ) LC1 = P0;
EXCPT 0x5;
M2T:R0 += 5;
R1 += 4;
M2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( M3T , M3B ) LC1 = P0;
EXCPT 0x5;
M3T:R0 += 5;
R1 += 4;
R2 += 3;
M3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( M4T , M4B ) LC1 = P0;
EXCPT 0x5;
M4T:R0 += 5;
R1 += 4;
R2 += 3;
R3 += 2;
M4B:R4 += 1;
// Kill Valid Dcr in WB, EX3
LSETUP ( M5T , M5T ) LC1 = P1;
EXCPT 0x5;
M5T:R1 += 5;
// Kill Valid Dcr in EX3, EX2
LSETUP ( M6T , M6T ) LC1 = P1;
EXCPT 0x5;
NOP;
M6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( M7T , M7T ) LC1 = P1;
EXCPT 0x5;
NOP;
NOP;
M7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( M8T , M8T ) LC1 = P1;
EXCPT 0x5;
NOP;
NOP;
NOP;
M8T:R4 += 5;
// Kill Valid Dcr in WB, EX3, EX2
LSETUP ( M9T , M9T ) LC1 = P2;
EXCPT 0x5;
M9T:R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( MAT , MAT ) LC1 = P2;
EXCPT 0x5;
NOP;
MAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( MBT , MBT ) LC1 = P2;
EXCPT 0x5;
NOP;
NOP;
MBT:
R5 += 5;
// Kill Valid Dcr in WB, EX3, EX2, EX1
LSETUP ( MCT , MCT ) LC1 = P3;
EXCPT 0x5;
MCT:
R7 += 7;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( MDT , MDT ) LC1 = P3;
EXCPT 0x5;
NOP;
MDT:
R0 += 7;
// Kill Valid Dcr in WB, EX3, EX2, EX1, AC
LSETUP ( MET , MET ) LC1 = P4;
EXCPT 0x5;
MET:
R1 += 1;
// Kill Valid Dcr in WB, EX2
LSETUP ( MFT , MFB ) LC1 = P1;
MFT:
EXCPT 0x5;
MFB:
R1 += 2;
// Kill Valid Dcr in WB, EX1
LSETUP ( MGT , MGB ) LC1 = P1;
MGT:
R2 += 3;
EXCPT 0x5;
MGB:
R1 += 2;
// Kill Valid Dcr in WB, AC
LSETUP ( MHT , MHB ) LC1 = P1;
MHT:
R2 += 3;
R3 += 4;
EXCPT 0x5;
MHB:
R1 += 2;
// Kill Valid Dcr in EX3, EX1
LSETUP ( MIT , MIB ) LC1 = P1;
EXCPT 0x5;
MIT:
R2 += 1;
MIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( MJT , MJB ) LC1 = P1;
MJT:
EXCPT 0x5;
R2 += 1;
MJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( MKT , MKB ) LC1 = P1;
EXCPT 0x5;
NOP;
MKT:
R2 += 1;
MKB:
R1 += 2;
// Kill Valid Dcr in WB, EX2, AC
LSETUP ( MLT , MLB ) LC1 = P2;
MLT:
EXCPT 0x5;
MLB:
R2 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (with Kill EX3)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in EX3
LSETUP ( N1T , N1T ) LC0 = P0;
CSYNC;
N1T:R0 += 5;
// Kill Valid Dcr in EX2
LSETUP ( N2T , N2B ) LC0 = P0;
CSYNC;
N2T:R0 += 5;
N2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( N3T , N3B ) LC0 = P0;
CSYNC;
N3T:R0 += 5;
R2 += 3;
N3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( N4T , N4B ) LC0 = P0;
CSYNC;
N4T:R0 += 5;
R2 += 3;
R3 += 2;
N4B:R4 += 1;
// Kill Valid Dcr in EX3, EX2
LSETUP ( N6T , N6T ) LC0 = P1;
CSYNC;
N6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( N7T , N7T ) LC0 = P1;
CSYNC;
NOP;
N7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( N8T , N8T ) LC0 = P1;
CSYNC;
NOP;
NOP;
N8T:R4 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( NAT , NAT ) LC0 = P2;
CSYNC;
NAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( NBT , NBT ) LC0 = P2;
CSYNC;
NOP;
NBT:
R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( NDT , NDT ) LC0 = P3;
CSYNC;
NDT:
R0 += 7;
// Kill Valid Dcr in EX3, EX1
LSETUP ( NIT , NIB ) LC0 = P1;
NIT:
CSYNC;
NIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( NJT , NJB ) LC0 = P1;
NJT:
R2 += 1;
CSYNC;
NJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( NKT , NKB ) LC0 = P1;
CSYNC;
NKT:
R2 += 1;
NKB:
R1 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (with Kill EX3)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in EX3
LSETUP ( O1T , O1T ) LC1 = P0;
CSYNC;
O1T:R0 += 5;
// Kill Valid Dcr in EX2
LSETUP ( O2T , O2B ) LC1 = P0;
CSYNC;
O2T:R0 += 5;
O2B:R2 += 3;
// Kill Valid Dcr in EX1
LSETUP ( O3T , O3B ) LC1 = P0;
CSYNC;
O3T:R0 += 5;
R2 += 3;
O3B:R3 += 2;
// Kill Valid Dcr in AC
LSETUP ( O4T , O4B ) LC1 = P0;
CSYNC;
O4T:R0 += 5;
R2 += 3;
R3 += 2;
O4B:R4 += 1;
// Kill Valid Dcr in EX3, EX2
LSETUP ( O6T , O6T ) LC1 = P1;
CSYNC;
O6T:R2 += 5;
// Kill Valid Dcr in EX2, EX1
LSETUP ( O7T , O7T ) LC1 = P1;
CSYNC;
NOP;
O7T:R3 += 5;
// Kill Valid Dcr in EX1, AC
LSETUP ( O8T , O8T ) LC1 = P1;
CSYNC;
NOP;
NOP;
O8T:R4 += 5;
// Kill Valid Dcr in EX3, EX2, EX1
LSETUP ( OAT , OAT ) LC1 = P2;
CSYNC;
OAT:
R6 += 6;
// Kill Valid Dcr in EX2, EX1, AC
LSETUP ( OBT , OBT ) LC1 = P2;
CSYNC;
NOP;
OBT:
R5 += 5;
// Kill Valid Dcr in EX3, EX2, EX1, AC
LSETUP ( ODT , ODT ) LC1 = P3;
CSYNC;
ODT:
R0 += 7;
// Kill Valid Dcr in EX3, EX1
LSETUP ( OIT , OIB ) LC1 = P1;
OIT:
CSYNC;
OIB:
R1 += 2;
// Kill Valid Dcr in EX3, AC
LSETUP ( OJT , OJB ) LC1 = P1;
OJT:
R2 += 1;
CSYNC;
OJB:
R1 += 2;
// Kill Valid Dcr in EX2, AC
LSETUP ( OKT , OKB ) LC1 = P1;
CSYNC;
OKT:
R2 += 1;
OKB:
R1 += 2;
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (with Kill AC)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in AC
LSETUP ( P4T , P4T ) LC0 = P0;
JUMP.S 2;
P4T:R0 += 5;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (with Kill AC)
/////////////////////////////////////////////////////////////////////////////
// Kill Valid Dcr in AC
LSETUP ( Q4T , Q4T ) LC1 = P0;
JUMP.S 2;
Q4T:R0 += 5;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 11,801 | sim/testsuite/bfin/se_loop_mv2lb_stall.S | //Original:/proj/frio/dv/testcases/seq/se_loop_mv2lb_stall/se_loop_mv2lb_stall.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE 0x00000500
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
#ifndef EVT
#define EVT 0xFFE02000
#endif
#ifndef EVT_OVERRIDE
#define EVT_OVERRIDE 0xFFE02100
#endif
#ifndef IMASK
#define IMASK 0xFFE02104
#endif
#ifndef DMEM_CONTROL
#define DMEM_CONTROL 0xFFE00004
#endif
#ifndef DCPLB_ADDR0
#define DCPLB_ADDR0 0xFFE00100
#endif
#ifndef DCPLB_DATA0
#define DCPLB_DATA0 0xFFE00200
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0x3 (Z);
P2 = 0x0100 (Z);
P2.H = 0x00f0;
// Loop 0
LD32_LABEL(r0, L0T);
LD32_LABEL(r1, L0B);
LC0 = p1;
LT0 = r0;
R0 = [ P2 ++ ];
LB0 = r1;
L0T:R3 += 4;
R2 += 3;
R4 += 5;
R5 += 6;
R6 += 7;
L0B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L1T);
LD32_LABEL(r1, L1B);
LT0 = r0;
LC0 = p1;
R0 = [ P2 ++ ];
NOP;
LB0 = r1;
L1T:R4 += 5;
R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
L1B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L2T);
LD32_LABEL(r1, L2B);
LT0 = r0;
LC0 = p1;
R0 = [ P2 ++ ];
NOP;
NOP;
LB0 = r1;
L2T:R5 += 6;
R2 += 3;
R3 += 4;
R4 += 5;
R6 += 7;
L2B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L3T);
LD32_LABEL(r1, L3B);
LT0 = r0;
LC0 = p1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
LB0 = r1;
L3T:R2 += 3;
R5 += 6;
R6 += 7;
R3 += 4;
R4 += 5;
L3B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L4T);
LD32_LABEL(r1, L4B);
LT0 = r0;
LC0 = p1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LB0 = r1;
L4T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
L4B:R7 += 8;
// Loop 0
LD32_LABEL(r0, L5T);
LD32_LABEL(r1, L5B);
[ -- SP ] = R1;
SSYNC;
LT0 = r0;
LC0 = p0;
R0 = [ P2 ++ ];
LB0 = [sp++];
L5T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
L5B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M0T);
LD32_LABEL(r1, M0B);
LT1 = r0;
LC1 = p1;
R0 = [ P2 ++ ];
LB1 = r1;
M0T:R3 += 4;
R2 += 3;
R4 += 5;
R5 += 6;
R6 += 7;
M0B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M1T);
LD32_LABEL(r1, M1B);
LT1 = r0;
LC1 = p1;
R0 = [ P2 ++ ];
NOP;
LB1 = r1;
M1T:R4 += 5;
R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
M1B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M2T);
LD32_LABEL(r1, M2B);
LT1 = r0;
LC1 = p1;
R0 = [ P2 ++ ];
NOP;
NOP;
LB1 = r1;
M2T:R5 += 6;
R2 += 3;
R3 += 4;
R4 += 5;
R6 += 7;
M2B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M3T);
LD32_LABEL(r1, M3B);
LT1 = r0;
LC1 = p1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
LB1 = r1;
M3T:R2 += 3;
R5 += 6;
R6 += 7;
R3 += 4;
R4 += 5;
M3B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M4T);
LD32_LABEL(r1, M4B);
LT1 = r0;
LC1 = p1;
R0 = [ P2 ++ ];
NOP;
NOP;
NOP;
NOP;
LB1 = r1;
M4T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
M4B:R7 += 8;
// Loop 1
LD32_LABEL(r0, M5T);
LD32_LABEL(r1, M5B);
[ -- SP ] = R1;
SSYNC;
LT1 = r0;
LC1 = p0;
R0 = [ P2 ++ ];
LB1 = [sp++];
M5T:R2 += 3;
R3 += 4;
R5 += 6;
R6 += 7;
R4 += 5;
M5B:R7 += 8;
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_0x00F00100,"aw"
.dd 0x01010101;
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
.dd 0x05050505;
.dd 0x06060606;
.dd 0x07070707;
.dd 0x08080808;
.dd 0x09090909;
.dd 0x0a0a0a0a;
.dd 0x0b0b0b0b;
.dd 0x0c0c0c0c;
.dd 0x0d0d0d0d;
.dd 0x0e0e0e0e;
.dd 0x0f0f0f0f;
// Define Kernal Stack
.section MEM_0x00F00210,"aw"
.space (STACKSIZE);
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 3,329 | sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s | //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_sft_2_1/c_ptr2op_pr_sft_2_1.dsp
// Spec Reference: ptr2op preg = preg << 2 (>>2, >> 1)
# mach: bfin
.include "testutils.inc"
start
// check p-reg to p-reg move
imm32 p1, 0xf0921203;
imm32 p2, 0xbe041305;
imm32 p3, 0xd0d61407;
imm32 p4, 0xa00a1089;
imm32 p5, 0x400a300b;
imm32 sp, 0xe07c180d;
imm32 fp, 0x206e109f;
P1 = P1 << 2;
P2 = P1 >> 2;
P3 = P1 << 2;
P4 = P1 >> 1;
P5 = P1 >> 2;
SP = P1 << 2;
FP = P1 >> 1;
CHECKREG p1, 0xC248480C;
CHECKREG p2, 0x30921203;
CHECKREG p3, 0x09212030;
CHECKREG p4, 0x61242406;
CHECKREG p5, 0x30921203;
CHECKREG sp, 0x09212030;
CHECKREG fp, 0x61242406;
imm32 p1, 0x50021003;
imm32 p2, 0x26041005;
imm32 p3, 0x60761007;
imm32 p4, 0x20081009;
imm32 p5, 0xf00a900b;
imm32 sp, 0xb00c1a0d;
imm32 fp, 0x200e10bf;
P1 = P2;
P2 = P2;
P3 = P2;
P4 = P2;
P5 = P2;
SP = P2;
FP = P2;
CHECKREG p1, 0x26041005;
CHECKREG p2, 0x26041005;
CHECKREG p3, 0x26041005;
CHECKREG p4, 0x26041005;
CHECKREG p5, 0x26041005;
CHECKREG sp, 0x26041005;
CHECKREG fp, 0x26041005;
imm32 p1, 0x20021003;
imm32 p2, 0x20041005;
imm32 p3, 0x20061007;
imm32 p4, 0x20081009;
imm32 p5, 0x200a100b;
imm32 sp, 0x200c100d;
imm32 fp, 0x200e100f;
P1 = P3 << 2;
P2 = P3 >> 1;
P3 = P3 >> 2;
P4 = P3 << 2;
P5 = P3 << 2;
SP = P3 >> 1;
FP = P3 << 2;
CHECKREG p1, 0x8018401C;
CHECKREG p2, 0x10030803;
CHECKREG p3, 0x08018401;
CHECKREG p4, 0x20061004;
CHECKREG p5, 0x20061004;
CHECKREG sp, 0x0400C200;
CHECKREG fp, 0x20061004;
imm32 p1, 0xa0021003;
imm32 p2, 0x2c041005;
imm32 p3, 0x40b61007;
imm32 p4, 0x250d1009;
imm32 p5, 0x260ae00b;
imm32 sp, 0x700c110d;
imm32 fp, 0x900e104f;
P1 = P4 >> 1;
P2 = P4 << 2;
P3 = P4 << 2;
P4 = P4 >> 2;
P5 = P4 << 2;
SP = P4 >> 2;
FP = P4 << 2;
CHECKREG p1, 0x12868804;
CHECKREG p2, 0x94344024;
CHECKREG p3, 0x94344024;
CHECKREG p4, 0x09434402;
CHECKREG p5, 0x250D1008;
CHECKREG sp, 0x0250D100;
CHECKREG fp, 0x250D1008;
imm32 p1, 0x10021003;
imm32 p2, 0x22041005;
imm32 p3, 0x20361007;
imm32 p4, 0x20041009;
imm32 p5, 0x200aa00b;
imm32 sp, 0x200c1b0d;
imm32 fp, 0x200e10cf;
P1 = P5 << 2;
P2 = P5 >> 2;
P3 = P5 << 2;
P4 = P5 << 2;
P5 = P5 >> 1;
SP = P5 >> 2;
FP = P5 << 2;
CHECKREG p1, 0x802A802C;
CHECKREG p2, 0x0802A802;
CHECKREG p3, 0x802A802C;
CHECKREG p4, 0x802A802C;
CHECKREG p5, 0x10055005;
CHECKREG sp, 0x04015401;
CHECKREG fp, 0x40154014;
imm32 p1, 0x50021003;
imm32 p2, 0x62041005;
imm32 p3, 0x70e61007;
imm32 p4, 0x290f1009;
imm32 p5, 0x700ab00b;
imm32 sp, 0x2a0c1d0d;
imm32 fp, 0xb00e1e0f;
P1 = SP << 2;
P2 = SP << 2;
P3 = SP >> 2;
P4 = SP << 2;
P5 = SP >> 2;
SP = SP >> 1;
FP = SP >> 2;
CHECKREG p1, 0xA8307434;
CHECKREG p2, 0xA8307434;
CHECKREG p3, 0x0A830743;
CHECKREG p4, 0xA8307434;
CHECKREG p5, 0x0A830743;
CHECKREG sp, 0x15060E86;
CHECKREG fp, 0x054183A1;
imm32 p1, 0x32002003;
imm32 p2, 0x24004005;
imm32 p3, 0x20506007;
imm32 p4, 0x20068009;
imm32 p5, 0x200ae00b;
imm32 sp, 0x200c1f0d;
imm32 fp, 0x200e10bf;
P1 = FP >> 2;
P2 = FP >> 1;
P3 = FP << 2;
P4 = FP >> 2;
P5 = FP << 2;
SP = FP >> 2;
FP = FP << 2;
CHECKREG p1, 0x0803842F;
CHECKREG p2, 0x1007085F;
CHECKREG p3, 0x803842FC;
CHECKREG p4, 0x0803842F;
CHECKREG p5, 0x803842FC;
CHECKREG sp, 0x0803842F;
CHECKREG fp, 0x803842FC;
pass
|
tactcomplabs/xbgas-binutils-gdb | 11,276 | sim/testsuite/bfin/c_dsp32shift_bitmux.s | //Original:/testcases/core/c_dsp32shift_bitmux/c_dsp32shift_bitmux.dsp
// Spec Reference: dsp32shift bitmux
# mach: bfin
.include "testutils.inc"
start
A0 = 0;
imm32 r0, 0x01230000;
imm32 r1, 0x12340678;
imm32 r2, 0x23450089;
imm32 r3, 0x3456089a;
imm32 r4, 0x456709ab;
imm32 r5, 0x56780abc;
imm32 r6, 0x67890bcd;
imm32 r7, 0x789a0cde;
//r0, r0, a0 >>= bitmux; invalid now
BITMUX( R0 , R1, A0) (ASR);
BITMUX( R0 , R2, A0) (ASR);
BITMUX( R0 , R3, A0) (ASR);
BITMUX( R0 , R4, A0) (ASR);
BITMUX( R0 , R5, A0) (ASR);
BITMUX( R0 , R6, A0) (ASR);
BITMUX( R0 , R7, A0) (ASR);
CHECKREG r1, 0x091A033C;
CHECKREG r0, 0x00024600;
CHECKREG r2, 0x11A28044;
CHECKREG r3, 0x1A2B044D;
CHECKREG r4, 0x22B384D5;
CHECKREG r5, 0x2B3C055E;
CHECKREG r6, 0x33C485E6;
CHECKREG r7, 0x3C4D066F;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x20000000;
CHECKREG r1, 0x00000022;
imm32 r0, 0x01231001;
imm32 r1, 0x12341678;
imm32 r2, 0x13451789;
imm32 r3, 0x1456189a;
imm32 r4, 0x156711ab;
imm32 r5, 0x16781abc;
imm32 r6, 0x17891bcd;
imm32 r7, 0x189a1cde;
BITMUX( R1 , R0, A0) (ASR);
//r1, r1, a0 >>= bitmux;
BITMUX( R1 , R2, A0) (ASR);
BITMUX( R1 , R3, A0) (ASR);
BITMUX( R1 , R4, A0) (ASR);
BITMUX( R1 , R5, A0) (ASR);
BITMUX( R1 , R6, A0) (ASR);
BITMUX( R1 , R7, A0) (ASR);
CHECKREG r0, 0x00918800;
CHECKREG r1, 0x0024682C;
CHECKREG r2, 0x09A28BC4;
CHECKREG r3, 0x0A2B0C4D;
CHECKREG r4, 0x0AB388D5;
CHECKREG r5, 0x0B3C0D5E;
CHECKREG r6, 0x0BC48DE6;
CHECKREG r7, 0x0C4D0E6F;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x28888000;
CHECKREG r1, 0x00000077;
imm32 r0, 0x31232002;
imm32 r1, 0x22342678;
imm32 r2, 0x23452789;
imm32 r3, 0x2456289a;
imm32 r4, 0x256729ab;
imm32 r5, 0x26782abc;
imm32 r6, 0x27892bcd;
imm32 r7, 0x289a2cde;
BITMUX( R2 , R0, A0) (ASR);
BITMUX( R2 , R1, A0) (ASR);
//r2, r2, a0 >>= bitmux;
BITMUX( R2 , R3, A0) (ASR);
BITMUX( R2 , R4, A0) (ASR);
BITMUX( R2 , R5, A0) (ASR);
BITMUX( R2 , R6, A0) (ASR);
BITMUX( R2 , R7, A0) (ASR);
CHECKREG r0, 0x18919001;
CHECKREG r1, 0x111A133C;
CHECKREG r2, 0x00468A4F;
CHECKREG r3, 0x122B144D;
CHECKREG r4, 0x12B394D5;
CHECKREG r5, 0x133C155E;
CHECKREG r6, 0x13C495E6;
CHECKREG r7, 0x144D166F;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x05DCA222;
CHECKREG r1, 0x00000023;
imm32 r0, 0x31230003;
imm32 r1, 0x32345378;
imm32 r2, 0x33456389;
imm32 r3, 0x3456739a;
imm32 r4, 0x356783ab;
imm32 r5, 0x367893bc;
imm32 r6, 0x3789a3cd;
imm32 r7, 0x389ab3de;
BITMUX( R3 , R0, A0) (ASR);
BITMUX( R3 , R1, A0) (ASR);
BITMUX( R3 , R2, A0) (ASR);
//r3, r3, a0 >>= bitmux;
BITMUX( R3 , R4, A0) (ASR);
BITMUX( R3 , R5, A0) (ASR);
BITMUX( R3 , R6, A0) (ASR);
BITMUX( R3 , R7, A0) (ASR);
CHECKREG r0, 0x18918001;
CHECKREG r1, 0x191A29BC;
CHECKREG r2, 0x19A2B1C4;
CHECKREG r3, 0x0068ACE7;
CHECKREG r4, 0x1AB3C1D5;
CHECKREG r5, 0x1B3C49DE;
CHECKREG r6, 0x1BC4D1E6;
CHECKREG r7, 0x1C4D59EF;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x988C1772;
CHECKREG r1, 0x00000027;
imm32 r0, 0x41230044;
imm32 r1, 0x42345648;
imm32 r2, 0x43456749;
imm32 r3, 0x4456784a;
imm32 r4, 0x4567894b;
imm32 r5, 0x46789a4c;
imm32 r6, 0x4789ab4d;
imm32 r7, 0x489abc44;
BITMUX( R4 , R0, A0) (ASR);
BITMUX( R4 , R1, A0) (ASR);
BITMUX( R4 , R2, A0) (ASR);
BITMUX( R4 , R3, A0) (ASR);
//r4, r4, a0 >>= bitmux;
BITMUX( R4 , R5, A0) (ASR);
BITMUX( R4 , R6, A0) (ASR);
BITMUX( R4 , R7, A0) (ASR);
CHECKREG r0, 0x20918022;
CHECKREG r1, 0x211A2B24;
CHECKREG r2, 0x21A2B3A4;
CHECKREG r3, 0x222B3C25;
CHECKREG r4, 0x008ACF12;
CHECKREG r5, 0x233C4D26;
CHECKREG r6, 0x23C4D5A6;
CHECKREG r7, 0x244D5E22;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x949E6230;
CHECKREG r1, 0x00000061;
imm32 r0, 0x51235005;
imm32 r1, 0x52345678;
imm32 r2, 0x53455789;
imm32 r3, 0x5456589a;
imm32 r4, 0x556759ab;
imm32 r5, 0x56785abc;
imm32 r6, 0x57895bcd;
imm32 r7, 0x589a5cde;
BITMUX( R5 , R0, A0) (ASR);
BITMUX( R5 , R1, A0) (ASR);
BITMUX( R5 , R2, A0) (ASR);
BITMUX( R5 , R3, A0) (ASR);
BITMUX( R5 , R4, A0) (ASR);
//r5, r5, a0 >>= bitmux;
BITMUX( R5 , R6, A0) (ASR);
BITMUX( R5 , R7, A0) (ASR);
CHECKREG r0, 0x2891A802;
CHECKREG r1, 0x291A2B3C;
CHECKREG r2, 0x29A2ABC4;
CHECKREG r3, 0x2A2B2C4D;
CHECKREG r4, 0x2AB3ACD5;
CHECKREG r5, 0x00ACF0B5;
CHECKREG r6, 0x2BC4ADE6;
CHECKREG r7, 0x2C4D2E6F;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0xC9865279;
CHECKREG r1, 0x0000003D;
imm32 r0, 0x61260006;
imm32 r1, 0x62365678;
imm32 r2, 0x63466789;
imm32 r3, 0x6456789a;
imm32 r4, 0x656689ab;
imm32 r5, 0x66786abc;
imm32 r6, 0x6786abcd;
imm32 r7, 0x6896bcde;
BITMUX( R6 , R0, A0) (ASR);
BITMUX( R6 , R1, A0) (ASR);
BITMUX( R6 , R2, A0) (ASR);
BITMUX( R6 , R3, A0) (ASR);
BITMUX( R6 , R4, A0) (ASR);
BITMUX( R6 , R5, A0) (ASR);
//r6, r6, a0 >>= bitmux;
BITMUX( R6 , R7, A0) (ASR);
CHECKREG r0, 0x30930003;
CHECKREG r1, 0x311B2B3C;
CHECKREG r2, 0x31A333C4;
CHECKREG r3, 0x322B3C4D;
CHECKREG r4, 0x32B344D5;
CHECKREG r5, 0x333C355E;
CHECKREG r6, 0x00CF0D57;
CHECKREG r7, 0x344B5E6F;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0xC4F72619;
CHECKREG r1, 0x00000049;
imm32 r0, 0x71730007;
imm32 r1, 0x72745678;
imm32 r2, 0x73756789;
imm32 r3, 0x7476789a;
imm32 r4, 0x757789ab;
imm32 r5, 0x76789abc;
imm32 r6, 0x7779abcd;
imm32 r7, 0x777abcde;
BITMUX( R7 , R0, A0) (ASR);
BITMUX( R7 , R1, A0) (ASR);
BITMUX( R7 , R2, A0) (ASR);
BITMUX( R7 , R3, A0) (ASR);
BITMUX( R7 , R4, A0) (ASR);
BITMUX( R7 , R5, A0) (ASR);
BITMUX( R7 , R6, A0) (ASR);
//r7, r7, a0 >>= bitmux;
CHECKREG r0, 0x38B98003;
CHECKREG r1, 0x393A2B3C;
CHECKREG r2, 0x39BAB3C4;
CHECKREG r3, 0x3A3B3C4D;
CHECKREG r4, 0x3ABBC4D5;
CHECKREG r5, 0x3B3C4D5E;
CHECKREG r6, 0x3BBCD5E6;
CHECKREG r7, 0x00EEF579;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0xD92713DC;
CHECKREG r1, 0xFFFFFFCD;
imm32 r0, 0x08230080;
imm32 r1, 0x18345688;
imm32 r2, 0x28456789;
imm32 r3, 0x3856788a;
imm32 r4, 0x4867898b;
imm32 r5, 0x58789a8c;
imm32 r6, 0x6889ab8d;
imm32 r7, 0x789abc8e;
//r0, r0, a0 <<= bitmux;
BITMUX( R0 , R1, A0) (ASL);
BITMUX( R0 , R2, A0) (ASL);
BITMUX( R0 , R3, A0) (ASL);
BITMUX( R0 , R4, A0) (ASL);
BITMUX( R0 , R5, A0) (ASL);
BITMUX( R0 , R6, A0) (ASL);
BITMUX( R0 , R7, A0) (ASL);
CHECKREG r1, 0x3068AD10;
CHECKREG r0, 0x11804000;
CHECKREG r2, 0x508ACF12;
CHECKREG r3, 0x70ACF114;
CHECKREG r4, 0x90CF1316;
CHECKREG r5, 0xB0F13518;
CHECKREG r6, 0xD113571A;
CHECKREG r7, 0xF135791C;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0xC4F70010;
CHECKREG r1, 0x00000049;
imm32 r0, 0x09230009;
imm32 r1, 0x19345679;
imm32 r2, 0x29456789;
imm32 r3, 0x39567899;
imm32 r4, 0x496789a9;
imm32 r5, 0x59789ab9;
imm32 r6, 0x6989abc9;
imm32 r7, 0x799abcd9;
BITMUX( R1 , R0, A0) (ASL);
//r1, r1, a0 <<= bitmux;
BITMUX( R1 , R2, A0) (ASL);
BITMUX( R1 , R3, A0) (ASL);
BITMUX( R1 , R4, A0) (ASL);
BITMUX( R1 , R5, A0) (ASL);
BITMUX( R1 , R6, A0) (ASL);
BITMUX( R1 , R7, A0) (ASL);
CHECKREG r0, 0x12460012;
CHECKREG r1, 0x9A2B3C80;
CHECKREG r2, 0x528ACF12;
CHECKREG r3, 0x72ACF132;
CHECKREG r4, 0x92CF1352;
CHECKREG r5, 0xB2F13572;
CHECKREG r6, 0xD3135792;
CHECKREG r7, 0xF33579B2;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0xC0040050;
CHECKREG r1, 0x0000003D;
imm32 r0, 0x0a23000a;
imm32 r1, 0x1a34567a;
imm32 r2, 0x2a45678a;
imm32 r3, 0x3a56789a;
imm32 r4, 0x4a6789aa;
imm32 r5, 0x5aa89aba;
imm32 r6, 0x6a89abca;
imm32 r7, 0x7a9abcda;
BITMUX( R2 , R0, A0) (ASL);
BITMUX( R2 , R1, A0) (ASL);
//r2, r2, a0 <<= bitmux;
BITMUX( R2 , R3, A0) (ASL);
BITMUX( R2 , R4, A0) (ASL);
BITMUX( R2 , R5, A0) (ASL);
BITMUX( R2 , R6, A0) (ASL);
BITMUX( R2 , R7, A0) (ASL);
CHECKREG r0, 0x14460014;
CHECKREG r1, 0x3468ACF4;
CHECKREG r2, 0x22B3C500;
CHECKREG r3, 0x74ACF134;
CHECKREG r4, 0x94CF1354;
CHECKREG r5, 0xB5513574;
CHECKREG r6, 0xD5135794;
CHECKREG r7, 0xF53579B4;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x00140111;
CHECKREG r1, 0x00000001;
imm32 r0, 0x01b300b3;
imm32 r1, 0x12b456b8;
imm32 r2, 0x23b567b9;
imm32 r3, 0x34b678ba;
imm32 r4, 0x45b789bb;
imm32 r5, 0x56b89abc;
imm32 r6, 0x67b9abbd;
imm32 r7, 0x78babcbe;
BITMUX( R3 , R0, A0) (ASL);
BITMUX( R3 , R1, A0) (ASL);
BITMUX( R3 , R2, A0) (ASL);
//r3, r3, a0 <<= bitmux;
BITMUX( R3 , R4, A0) (ASL);
BITMUX( R3 , R5, A0) (ASL);
BITMUX( R3 , R6, A0) (ASL);
BITMUX( R3 , R7, A0) (ASL);
CHECKREG r0, 0x03660166;
CHECKREG r1, 0x2568AD70;
CHECKREG r2, 0x476ACF72;
CHECKREG r3, 0x5B3C5D00;
CHECKREG r4, 0x8B6F1376;
CHECKREG r5, 0xAD713578;
CHECKREG r6, 0xCF73577A;
CHECKREG r7, 0xF175797C;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x00444144;
CHECKREG r1, 0x00000005;
imm32 r0, 0x012300c4;
imm32 r1, 0x123456c8;
imm32 r2, 0x234567c9;
imm32 r3, 0x345678ca;
imm32 r4, 0x456789cb;
imm32 r5, 0x56789acc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcce;
BITMUX( R4 , R0, A0) (ASL);
BITMUX( R4 , R1, A0) (ASL);
BITMUX( R4 , R2, A0) (ASL);
BITMUX( R4 , R3, A0) (ASL);
//r4, r4, a0 <<= bitmux;
BITMUX( R4 , R5, A0) (ASL);
BITMUX( R4 , R6, A0) (ASL);
BITMUX( R4 , R7, A0) (ASL);
CHECKREG r0, 0x02460188;
CHECKREG r1, 0x2468AD90;
CHECKREG r2, 0x468ACF92;
CHECKREG r3, 0x68ACF194;
CHECKREG r4, 0xB3C4E580;
CHECKREG r5, 0xACF13598;
CHECKREG r6, 0xCF13579A;
CHECKREG r7, 0xF135799C;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x10510404;
CHECKREG r1, 0x00000011;
imm32 r0, 0x0c230d05;
imm32 r1, 0x1c345d78;
imm32 r2, 0x2c456d89;
imm32 r3, 0x3c567d9a;
imm32 r4, 0x4c678dab;
imm32 r5, 0x5c789dbc;
imm32 r6, 0x6c89adcd;
imm32 r7, 0x7c9abdde;
BITMUX( R5 , R0, A0) (ASL);
BITMUX( R5 , R1, A0) (ASL);
BITMUX( R5 , R2, A0) (ASL);
BITMUX( R5 , R3, A0) (ASL);
BITMUX( R5 , R4, A0) (ASL);
//r5, r5, a0 <<= bitmux;
BITMUX( R5 , R6, A0) (ASL);
BITMUX( R5 , R7, A0) (ASL);
CHECKREG r0, 0x18461A0A;
CHECKREG r1, 0x3868BAF0;
CHECKREG r2, 0x588ADB12;
CHECKREG r3, 0x78ACFB34;
CHECKREG r4, 0x98CF1B56;
CHECKREG r5, 0x3C4EDE00;
CHECKREG r6, 0xD9135B9A;
CHECKREG r7, 0xF9357BBC;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x41010454;
CHECKREG r1, 0x00000014;
imm32 r0, 0x0d230e06;
imm32 r1, 0x1d345e78;
imm32 r2, 0x2d456e89;
imm32 r3, 0x3d567e9a;
imm32 r4, 0x4d678eab;
imm32 r5, 0x5d789ebc;
imm32 r6, 0x6d89aecd;
imm32 r7, 0x7d9abede;
BITMUX( R6 , R0, A0) (ASL);
BITMUX( R6 , R1, A0) (ASL);
BITMUX( R6 , R2, A0) (ASL);
BITMUX( R6 , R3, A0) (ASL);
BITMUX( R6 , R4, A0) (ASL);
BITMUX( R6 , R5, A0) (ASL);
//r6, r6, a0 <<= bitmux;
BITMUX( R6 , R7, A0) (ASL);
CHECKREG r0, 0x1A461C0C;
CHECKREG r1, 0x3A68BCF0;
CHECKREG r2, 0x5A8ADD12;
CHECKREG r3, 0x7AACFD34;
CHECKREG r4, 0x9ACF1D56;
CHECKREG r5, 0xBAF13D78;
CHECKREG r6, 0xC4D76680;
CHECKREG r7, 0xFB357DBC;
R0 = A0.w;
R1 = A0.x;
CHECKREG r0, 0x41150514;
CHECKREG r1, 0x00000040;
imm32 r0, 0x01230007;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
BITMUX( R7 , R0, A0) (ASL);
BITMUX( R7 , R1, A0) (ASL);
BITMUX( R7 , R2, A0) (ASL);
BITMUX( R7 , R3, A0) (ASL);
BITMUX( R7 , R4, A0) (ASL);
BITMUX( R7 , R5, A0) (ASL);
BITMUX( R7 , R6, A0) (ASL);
//r7, r7, a0 <<= bitmux;
CHECKREG r0, 0x0246000E;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x468ACF12;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x8ACF1356;
CHECKREG r5, 0xACF13578;
CHECKREG r6, 0xCF13579A;
CHECKREG r7, 0x4D5E6F00;
pass
|
tactcomplabs/xbgas-binutils-gdb | 10,162 | sim/testsuite/bfin/lmu_excpt_align.S | //Original:/proj/frio/dv/testcases/lmu/lmu_excpt_align/lmu_excpt_align.dsp
// Description: LMU data alignment exceptions
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
CHECK_INIT(p5, 0xE0000000);
// test address for DAG0
// test address for DAG1
// setup interrupt controller with exception handler address
WR_MMR_LABEL(EVT3, handler, p0, r1);
// Write fault addr MMR to known state
WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
//nop;nop;nop;nop;nop; // in lieu of CSYNC
CSYNC;
A0 = 0;
// go to user mode. and enable exceptions
LD32_LABEL(r0, User);
RETI = R0;
RTI;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
User:
NOP;NOP;NOP;NOP;NOP;
//-------------------------------------------------------
// First do stores
//-------------------------------------------------------
// 16-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X01: W [ I1 ] = R1.L; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X02: [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X03: [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X04: [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 16-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X05: A0 = 0 || NOP || W [ I1 ] = R1.L; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X05, r0); // RETX should be value of X05 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X06: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X06, r0); // RETX should be value of X06 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X07: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X07, r0); // RETX should be value of X07 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X08: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X08, r0); // RETX should be value of X08 (HARDCODED ADDR!!)
//-------------------------------------------------------
// Now repeat for Loads
//-------------------------------------------------------
// 16-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X11: R1.L = W [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X11, r0); // RETX should be value of X11 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X12: R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X12, r0); // RETX should be value of X12 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X13: R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X13, r0); // RETX should be value of X13 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG0
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X14: R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X14, r0); // RETX should be value of X14 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 16-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFE)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X15: A0 = 0 || NOP || R1.L = W [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X15, r0); // RETX should be value of X15 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 1)));
LD32(p2, ((0x1000 + 1) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 1)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 2)));
LD32(p2, ((0x1000 + 2) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X17: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 2)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X17, r0); // RETX should be value of X17 (HARDCODED ADDR!!)
//-------------------------------------------------------
// 32-bit alignment, DAG1
LD32(i1, ((0x1000 + 3)));
LD32(p2, ((0x1000 + 3) & 0xFFFFFFFC)); // Aligned version
LD32(r1, 0xDEADBEEF);
R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
X18: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here
CHECKREG(r5,0x24); // supv and EXCPT_ALIGN
CHECKREG(r6, (0x1000 + 3)); // FAULT_ADDR should contain fail address
CHECKREG_SYM(r7, X18, r0); // RETX should be value of X18 (HARDCODED ADDR!!)
//-------------------------------------------------------
dbg_pass;
handler:
R5 = SEQSTAT; // Get exception cause
// read and check fail addr (addr_which_causes_exception)
// should not be set for alignment exception
RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
R7 = RETX; // get address of excepting instruction
// align the offending address
I1 = P2;
RTX;
// Nops to work around ICache bug
NOP;NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;NOP;
.section MEM_0x1000,"aw"
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
.dd 0x00000000
|
tactcomplabs/xbgas-binutils-gdb | 10,840 | sim/testsuite/bfin/c_ldstii_st_dreg.s | //Original:/testcases/core/c_ldstii_st_dreg/c_ldstii_st_dreg.dsp
// Spec Reference: c_ldstii store dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x105f50a0;
imm32 r1, 0x204e60a1;
imm32 r2, 0x300370a2;
imm32 r3, 0x402c80a3;
imm32 r4, 0x501b90a4;
imm32 r5, 0x600aa0a5;
imm32 r6, 0x7019b0a6;
imm32 r7, 0xd028c0a7;
loadsym p1, DATA_ADDR_1;
loadsym p2, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym p3, DATA_ADDR_3;
.endif
loadsym p4, DATA_ADDR_4;
loadsym p5, DATA_ADDR_1;
loadsym fp, DATA_ADDR_2;
.ifndef BFIN_HOST
loadsym sp, DATA_ADDR_3;
.endif
[ P1 + 4 ] = R0;
[ P1 + 8 ] = R1;
[ P1 + 12 ] = R2;
[ P1 + 16 ] = R3;
[ P2 + 20 ] = R4;
[ P2 + 24 ] = R5;
[ P2 + 28 ] = R6;
[ P2 + 32 ] = R7;
R6 = [ P1 + 4 ];
R5 = [ P1 + 8 ];
R4 = [ P1 + 12 ];
R3 = [ P1 + 16 ];
R2 = [ P2 + 20 ];
R7 = [ P2 + 24 ];
R0 = [ P2 + 28 ];
R1 = [ P2 + 32 ];
CHECKREG r0, 0x7019B0A6;
CHECKREG r1, 0xD028C0A7;
CHECKREG r2, 0x501B90A4;
CHECKREG r3, 0x402C80A3;
CHECKREG r4, 0x300370A2;
CHECKREG r5, 0x204E60A1;
CHECKREG r6, 0x105F50A0;
CHECKREG r7, 0x600AA0A5;
.ifndef BFIN_HOST
imm32 r0, 0x10bf50b0;
imm32 r1, 0x20be60b1;
imm32 r2, 0x30bd70b2;
imm32 r3, 0x40bc80b3;
imm32 r4, 0x55bb90b4;
imm32 r5, 0x60baa0b5;
imm32 r6, 0x70b9b0b6;
imm32 r7, 0x80b8c0b7;
[ P3 + 36 ] = R0;
[ P3 + 40 ] = R1;
[ P3 + 44 ] = R2;
[ P3 + 48 ] = R3;
[ P4 + 52 ] = R4;
[ P4 + 56 ] = R5;
[ P4 + 60 ] = R6;
[ P4 + 64 ] = R7;
R3 = [ P3 + 36 ];
R4 = [ P3 + 40 ];
R0 = [ P3 + 44 ];
R1 = [ P3 + 48 ];
R2 = [ P4 + 52 ];
R5 = [ P4 + 56 ];
R6 = [ P4 + 60 ];
R7 = [ P4 + 64 ];
CHECKREG r0, 0x30BD70B2;
CHECKREG r1, 0x40BC80B3;
CHECKREG r2, 0x55BB90B4;
CHECKREG r3, 0x10BF50B0;
CHECKREG r4, 0x20BE60B1;
CHECKREG r5, 0x60BAA0B5;
CHECKREG r6, 0x70B9B0B6;
CHECKREG r7, 0x80B8C0B7;
.endif
// initial values
imm32 r0, 0x10cf50c0;
imm32 r1, 0x20ce60c1;
imm32 r2, 0x30c370c2;
imm32 r3, 0x40cc80c3;
imm32 r4, 0x50cb90c4;
imm32 r5, 0x60caa0c5;
imm32 r6, 0x70c9b0c6;
imm32 r7, 0xd0c8c0c7;
[ P5 + 4 ] = R0;
[ P5 + 8 ] = R1;
[ P5 + 12 ] = R2;
[ P5 + 16 ] = R3;
.ifndef BFIN_HOST
[ SP + 20 ] = R4;
[ SP + 24 ] = R5;
[ SP + 28 ] = R6;
[ SP + 32 ] = R7;
.endif
R6 = [ P5 + 4 ];
R5 = [ P5 + 8 ];
R4 = [ P5 + 12 ];
R3 = [ P5 + 16 ];
.ifndef BFIN_HOST
R2 = [ SP + 20 ];
R0 = [ SP + 24 ];
R7 = [ SP + 28 ];
R1 = [ SP + 32 ];
CHECKREG r0, 0x60CAA0C5;
CHECKREG r1, 0xD0C8C0C7;
CHECKREG r2, 0x50CB90C4;
.endif
CHECKREG r3, 0x40CC80C3;
CHECKREG r4, 0x30C370C2;
CHECKREG r5, 0x20CE60C1;
CHECKREG r6, 0x10CF50C0;
// initial values
imm32 r0, 0x60df50d0;
imm32 r1, 0x70de60d1;
imm32 r2, 0x80dd70d2;
imm32 r3, 0x90dc80d3;
imm32 r4, 0xa0db90d4;
imm32 r5, 0xb0daa0d5;
imm32 r6, 0xc0d9b0d6;
imm32 r7, 0xd0d8c0d7;
[ FP + 36 ] = R0;
[ FP + 40 ] = R1;
[ FP + 44 ] = R2;
[ FP + 48 ] = R3;
[ FP + 52 ] = R4;
[ FP + 56 ] = R5;
[ FP + 60 ] = R6;
[ FP + 64 ] = R7;
R3 = [ FP + 36 ];
R4 = [ FP + 40 ];
R0 = [ FP + 44 ];
R1 = [ FP + 48 ];
R2 = [ FP + 52 ];
R5 = [ FP + 56 ];
R6 = [ FP + 60 ];
R7 = [ FP + 64 ];
CHECKREG r0, 0x80DD70D2;
CHECKREG r1, 0x90DC80D3;
CHECKREG r2, 0xA0DB90D4;
CHECKREG r3, 0x60DF50D0;
CHECKREG r4, 0x70DE60D1;
CHECKREG r5, 0xB0DAA0D5;
CHECKREG r6, 0xC0D9B0D6;
CHECKREG r7, 0xD0D8C0D7;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
DATA_ADDR_6:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 6,227 | sim/testsuite/bfin/se_bug_ui.S | //Original:/proj/frio/dv/testcases/seq/se_bug_ui/se_bug_ui.dsp
// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
//
// Constants and Defines
//
include(gen_int.inc)
include(selfcheck.inc)
include(std.inc)
include(mmrs.inc)
include(symtable.inc)
#ifndef STACKSIZE
#define STACKSIZE 0x10 // change for how much stack you need
#endif
#ifndef ITABLE
#define ITABLE 0xF0000000
#endif
GEN_INT_INIT(ITABLE) // set location for interrupt table
//
// Reset/Bootstrap Code
// (Here we should set the processor operating modes, initialize registers,
// etc.)
//
BOOT:
INIT_R_REGS(0); // initialize general purpose regs
INIT_P_REGS(0); // initialize the pointers
INIT_I_REGS(0); // initialize the dsp address regs
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
CLI R1; // inhibit events during MMR writes
LD32_LABEL(sp, USTACK); // setup the user stack pointer
USP = SP;
LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
FP = SP; // and frame pointer
LD32(p0, EVT0); // Setup Event Vectors and Handlers
P0 += 4; // EVT0 not used (Emulation)
P0 += 4; // EVT1 not used (Reset)
LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
[ P0 ++ ] = R0;
P0 += 4; // EVT4 not used (Global Interrupt Enable)
LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
[ P0 ++ ] = R0;
LD32(p0, EVT_OVERRIDE);
R0 = 0;
[ P0 ++ ] = R0;
R1 = -1; // Change this to mask interrupts (*)
CSYNC; // wait for MMR writes to finish
STI R1; // sync and reenable events (implicit write to IMASK)
DUMMY:
R0 = 0 (Z);
LT0 = r0; // set loop counters to something deterministic
LB0 = r0;
LC0 = r0;
LT1 = r0;
LB1 = r0;
LC1 = r0;
ASTAT = r0; // reset other internal regs
SYSCFG = r0;
RETS = r0; // prevent X's breaking LINK instruction
// The following code sets up the test for running in USER mode
LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
// ReturnFromInterrupt (RTI)
RETI = r0; // We need to load the return address
// Comment the following line for a USER Mode test
JUMP STARTSUP; // jump to code start for SUPERVISOR mode
RTI;
STARTSUP:
LD32_LABEL(p1, BEGIN);
LD32(p0, EVT15);
CLI R1; // inhibit events during write to MMR
[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
CSYNC; // wait for it
STI R1; // reenable events with proper imask
RAISE 15; // after we RTI, INT 15 should be taken
RTI;
//
// The Main Program
//
STARTUSER:
LINK 0; // change for how much stack frame space you need.
JUMP BEGIN;
//*********************************************************************
BEGIN:
// COMMENT the following line for USER MODE tests
[ -- SP ] = RETI; // enable interrupts in supervisor mode
// **** YOUR CODE GOES HERE ****
// count of UI's will be in r5, which was initialized to 0 by header
.dw 0x41FD ;
.dw 0x41FE ;
.dw 0x41FF ;
.dw 0x9040 ;
.dw 0x9049 ;
.dw 0x9052 ;
.dw 0x905B ;
.dw 0x9064 ;
.dw 0x906D ;
.dw 0x9076 ;
.dw 0x907F ;
.dw 0x90C0 ;
.dw 0x90C9 ;
.dw 0x90D2 ;
.dw 0x90DB ;
.dw 0x90E4 ;
.dw 0x90ED ;
.dw 0x90F6 ;
.dw 0x90FF ;
.dw 0x9180 ;
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
// Xhandler counts all EXCAUSE = 0x21;
CHECKREG(r5, 20); // count of all 16 bit UI's.
END:
dbg_pass; // End the test
//*********************************************************************
//
// Handlers for Events
//
NHANDLE: // NMI Handler 2
RTN;
XHANDLE: // Exception Handler 3
// 16 bit illegal opcode handler - skips bad instruction
// handler MADE LEAN and destructive so test runs more quckly
// se_undefinedinstruction1.dsp tests using a "nice" handler
// [--sp] = ASTAT; // save what we damage
// [--sp] = (r7 - r6);
R7 = SEQSTAT;
R7 <<= 26;
R7 >>= 26; // only want EXCAUSE
R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
R6 = 0x22; // Also accept illegal insn combo
CC = r7 == r6;
IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
dbg_fail;
UNDEFINEDINSTRUCTION:
R7 = RETX; // Fix up return address
R7 += 2; // skip offending 16 bit instruction
RETX = r7; // and put back in RETX
R5 += 1; // Increment global counter
OUT:
// (r7 - r6) = [sp++];
// ASTAT = [sp++];
RTX;
HWHANDLE: // HW Error Handler 5
RTI;
THANDLE: // Timer Handler 6
RTI;
I7HANDLE: // IVG 7 Handler
RTI;
I8HANDLE: // IVG 8 Handler
RTI;
I9HANDLE: // IVG 9 Handler
RTI;
I10HANDLE: // IVG 10 Handler
RTI;
I11HANDLE: // IVG 11 Handler
RTI;
I12HANDLE: // IVG 12 Handler
RTI;
I13HANDLE: // IVG 13 Handler
RTI;
I14HANDLE: // IVG 14 Handler
RTI;
I15HANDLE: // IVG 15 Handler
RTI;
// padding for the icache
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
//
// Data Segment
//
.data
DATA:
.space (0x10);
// Stack Segments (Both Kernel and User)
.space (STACKSIZE);
KSTACK:
.space (STACKSIZE);
USTACK:
|
tactcomplabs/xbgas-binutils-gdb | 1,131 | sim/testsuite/bfin/se_all64bitg2opcodes.S | /*
* Blackfin testcase for testing illegal/legal 64-bit opcodes (group 2)
* from userspace. we track all instructions which cause some sort of
* exception when run from userspace, this is normally EXCAUSE :
* - 0x22 : illegal instruction combination
* and walk every instruction from 0x0000 to 0xffff
*/
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
#define SE_ALL_BITS 16
#include "se_allopcodes.h"
.macro se_all_load_insn
R2 = W[P5 + 6];
R0 = R2;
.endm
.macro se_all_next_insn
/* increment, and go again. */
R0 = R2;
R0 += 1;
/* finish once we hit the 32bit limit */
imm32 R1, 0x10000;
CC = R1 == R0;
IF CC JUMP pass_lvl;
W[P5 + 6] = R0;
.endm
.macro se_all_insn_init
MNOP || NOP || NOP;
.endm
.macro se_all_insn_table
/* this table must be sorted, and end with zero */
/* start end SEQSTAT */
.dw 0x0001, 0x9bff, 0x22
.dw 0x9c60, 0x9c7f, 0x22
.dw 0x9ce0, 0x9cff, 0x22
.dw 0x9d60, 0x9d7f, 0x22
.dw 0x9e60, 0x9e7f, 0x22
.dw 0x9ee0, 0x9eff, 0x22
.dw 0x9f60, 0x9f7f, 0x22
.dw 0xa000, 0xffff, 0x22
.dw 0x0000, 0x0000, 0x00
.endm
se_all_test
|
tactcomplabs/xbgas-binutils-gdb | 5,570 | sim/testsuite/bfin/a9.s | // ALU test program.
// Test 32 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, so AN=1
R0.L = 0x0000;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is larger, check correct output with overflow
R0.L = 0xffff;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0xffff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, no overflow here
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, overflow
R0.L = 0xffff;
R0.H = 0x800f;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 );
// both operands equal
R0.L = 0x0080;
R0.H = 0x8000;
R1.L = 0x0080;
R1.H = 0x8000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0080 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// MIN
// second operand is smaller
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller, overflow
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0000;
R1.H = 0x0ff0;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// equal operands
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0001;
R1.H = 0x8000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// ABS
R0.L = 0x0001;
R0.H = 0x8000;
R7 = ABS R0;
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0001;
R0.H = 0x0000;
R7 = ABS R0;
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0x8000;
R7 = ABS R0;
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0xffff;
R7 = ABS R0;
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0x0000;
R7 = ABS R0;
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = VS; R6 = CC; DBGA (R6.L, 0x1);
CC = AZ; R6 = CC; DBGA (R6.L, 0x1);
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,487 | sim/testsuite/bfin/se_loop_ppm_int.S | //Original:/proj/frio/dv/testcases/seq/se_loop_ppm_int/se_loop_ppm_int.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Sync it!
CSYNC;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
NOP;NOP;NOP;NOP;
P0 = 0x5 (Z);
LSETUP ( l0s , l0s ) LC0 = P0;
CSYNC;
l0s:[ -- SP ] = ( R7:5 );
LSETUP ( l3s , l3e ) LC0 = P0;
l3s:[ -- SP ] = ( R7:5 );
R6 += 2;
R7 += 3;
NOP;
CSYNC;
NOP;
NOP;
NOP;
l3e:R5 += 1;
NOP;
LSETUP ( m0s , m0s ) LC1 = P0;
CSYNC;
m0s:[ -- SP ] = ( R7:5 );
LSETUP ( m3s , m3e ) LC1 = P0;
m3s:[ -- SP ] = ( R7:5 );
R6 += 2;
R7 += 3;
NOP;
CSYNC;
NOP;
NOP;
NOP;
m3e:R5 += 1;
NOP;
NOP;
NOP;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 2,919 | sim/testsuite/bfin/random_0023.S | # mach: bfin
#include "test.h"
.include "testutils.inc"
start
dmm32 ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 A1.w, 0xf41fbf3f;
dmm32 A1.x, 0x00000000;
imm32 R5, 0xd8d95310;
imm32 R6, 0xd0457fff;
R5.H = (A1 -= R6.L * R6.H) (M, FU);
checkreg R5, 0x7fff5310;
checkreg A1.w, 0x8bfe0f84;
checkreg A1.x, 0x00000000;
checkreg ASTAT, (0x60608a90 | _VS | _V | _AV1S | _AV0S | _AQ | _V_COPY | _AC0_COPY);
dmm32 ASTAT, (0x54b0ca90 | _VS | _AV1S | _AC1 | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0xf88288c8;
dmm32 A1.x, 0xffffffff;
imm32 R0, 0xfffe6736;
imm32 R2, 0x8000f882;
imm32 R3, 0xffff8391;
R0.H = (A1 += R3.L * R2.L) (M, FU);
checkreg R0, 0x80006736;
checkreg A1.w, 0x7fb7d06a;
checkreg A1.x, 0xffffffff;
checkreg ASTAT, (0x54b0ca90 | _VS | _V | _AV1S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x1c500480 | _VS | _AV1S | _AV0S | _AC0 | _CC | _AC0_COPY | _AN);
dmm32 A1.w, 0x9083dd08;
dmm32 A1.x, 0x00000000;
imm32 R0, 0x00000000;
imm32 R4, 0x00002492;
R4.H = (A1 += R4.L * R0.H) (M, FU);
checkreg R4, 0x7fff2492;
checkreg ASTAT, (0x1c500480 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY | _AN);
dmm32 ASTAT, (0x7c00c810 | _AV1S | _AC1 | _AC0);
dmm32 A1.w, 0x69e86d3f;
dmm32 A1.x, 0xffffffc2;
imm32 R1, 0x64f42c5b;
imm32 R3, 0x4128529d;
R3 = (A1 -= R3.L * R1.L) (M, FU);
checkreg R3, 0x80000000;
checkreg A1.w, 0x5b981370;
checkreg A1.x, 0xffffffc2;
checkreg ASTAT, (0x7c00c810 | _VS | _V | _AV1S | _AC1 | _AC0 | _V_COPY);
dmm32 ASTAT, (0x5cc0c480 | _VS | _AQ | _CC);
dmm32 A1.w, 0x34bbe964;
dmm32 A1.x, 0x00000036;
imm32 R1, 0x7fffffff;
imm32 R5, 0x7fff427e;
A1 -= R5.L * R1.L (M, FU);
checkreg A1.w, 0xf23e2be2;
checkreg A1.x, 0x00000035;
checkreg ASTAT, (0x5cc0c480 | _VS | _AQ | _CC);
# here the result is zero, and the _V bit is set
dmm32 ASTAT, 0x0;
dmm32 A0.w, 0x00008492;
dmm32 A0.x, 0x00000000;
imm32 R2, 0x7fff0002;
imm32 R3, 0xfa6e8492;
imm32 R6, 0xffff0002;
R6 = (A0 -= R3.L * R2.L) (FU);
checkreg R6, 0x00000000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, ( _VS | _V | _AV0S | _AV0 | _V_COPY);
# here the result is zero, and the _V bit is not set
dmm32 ASTAT, (_V | _V_COPY);
dmm32 A0.w, 0x1fffc000;
dmm32 A0.x, 0x00000000;
imm32 R0, 0x80004000;
imm32 R4, 0x1fffffff;
imm32 R6, 0x80000000;
R4.L = (A0 -= R0.L * R6.H) (FU);
checkreg R4, 0x1fff0000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (_AV0S | _AV0);
dmm32 ASTAT, (0x0c108610 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
dmm32 A0.w, 0x0000eaf0;
dmm32 A0.x, 0x00000000;
imm32 R1, 0x00010000;
imm32 R6, 0xfbf10001;
R1.L = (A0 -= R6.H * R1.H) (FU);
checkreg R1, 0x00010000;
checkreg A0.w, 0x00000000;
checkreg A0.x, 0x00000000;
checkreg ASTAT, (0x0c108610 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AC0_COPY | _AN);
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,914 | sim/testsuite/bfin/c_dsp32alu_rl_m.s | //Original:/testcases/core/c_dsp32alu_rl_m/c_dsp32alu_rl_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x55678911;
imm32 r1, 0x2759ab1d;
imm32 r2, 0x34455515;
imm32 r3, 0x46665717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789a51d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R0.L - R0.L (NS);
R1.L = R0.L - R1.H (NS);
R2.L = R0.H - R2.L (NS);
R3.L = R0.H - R3.H (NS);
R4.L = R0.L - R4.L (NS);
R5.L = R0.L - R5.H (NS);
R6.L = R0.H - R6.L (NS);
R7.L = R0.H - R7.H (NS);
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440052;
CHECKREG r7, 0x8666CF01;
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440052;
CHECKREG r7, 0x8666CF01;
imm32 r0, 0x44678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x344d5515;
imm32 r3, 0x4666d717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789cc1d;
imm32 r6, 0x74445c15;
imm32 r7, 0x86667c77;
R0.L = R1.L - R0.L (NS);
R1.L = R1.L - R1.H (NS);
R2.L = R1.H - R2.L (NS);
R3.L = R1.H - R3.H (NS);
R4.L = R1.L - R4.L (NS);
R5.L = R1.L - R5.H (NS);
R6.L = R1.H - R6.L (NS);
R7.L = R1.H - R7.H (NS);
CHECKREG r4, 0x5678FA79;
CHECKREG r5, 0x67891C0B;
CHECKREG r6, 0x7444CB74;
CHECKREG r7, 0x8666A123;
CHECKREG r4, 0x5678FA79;
CHECKREG r5, 0x67891C0B;
CHECKREG r6, 0x7444CB74;
CHECKREG r7, 0x8666A123;
imm32 r0, 0xcc678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34c45515;
imm32 r3, 0x466c7717;
imm32 r4, 0x5678c91b;
imm32 r5, 0x6789ac1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677c7;
R0.L = R2.L - R0.L (NS);
R1.L = R2.L - R1.H (NS);
R2.L = R2.H - R2.L (NS);
R3.L = R2.H - R3.H (NS);
R4.L = R2.L - R4.L (NS);
R5.L = R2.L - R5.H (NS);
R6.L = R2.H - R6.L (NS);
R7.L = R2.H - R7.H (NS);
CHECKREG r4, 0x56781694;
CHECKREG r5, 0x67897826;
CHECKREG r6, 0x7444DFAF;
CHECKREG r7, 0x8666AE5E;
CHECKREG r4, 0x56781694;
CHECKREG r5, 0x67897826;
CHECKREG r6, 0x7444DFAF;
CHECKREG r7, 0x8666AE5E;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R0.L = R3.L - R0.L (NS);
R1.L = R3.L - R1.H (NS);
R2.L = R3.H - R2.L (NS);
R3.L = R3.H - R3.H (NS);
R4.L = R3.L - R4.L (NS);
R5.L = R3.L - R5.H (NS);
R6.L = R3.H - R6.L (NS);
R7.L = R3.H - R7.H (NS);
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x7444F151;
CHECKREG r7, 0x8666C000;
CHECKREG r4, 0x567876E5;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x7444F151;
CHECKREG r7, 0x8666C000;
imm32 r0, 0xe5678911;
imm32 r1, 0x2e89ab1d;
imm32 r2, 0x34e45515;
imm32 r3, 0x466e7717;
imm32 r4, 0x5678e91b;
imm32 r5, 0x6789ae1d;
imm32 r6, 0x744455e5;
imm32 r7, 0x8666777e;
R0.L = R4.L - R0.L (NS);
R1.L = R4.L - R1.H (NS);
R2.L = R4.H - R2.L (NS);
R3.L = R4.H - R3.H (NS);
R4.L = R4.L - R4.L (NS);
R5.L = R4.L - R5.H (NS);
R6.L = R4.H - R6.L (NS);
R7.L = R4.H - R7.H (NS);
CHECKREG r4, 0x56780000;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440093;
CHECKREG r7, 0x8666D012;
CHECKREG r4, 0x56780000;
CHECKREG r5, 0x67899877;
CHECKREG r6, 0x74440093;
CHECKREG r7, 0x8666D012;
imm32 r0, 0xdd678911;
imm32 r1, 0xd789ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46d67717;
imm32 r4, 0x567d891b;
imm32 r5, 0x6789db1d;
imm32 r6, 0x74445d15;
imm32 r7, 0x866677d7;
R0.L = R5.L - R0.L (NS);
R1.L = R5.L - R1.H (NS);
R2.L = R5.H - R2.L (NS);
R3.L = R5.H - R3.H (NS);
R4.L = R5.L - R4.L (NS);
R5.L = R5.L - R5.H (NS);
R6.L = R5.H - R6.L (NS);
R7.L = R5.H - R7.H (NS);
CHECKREG r4, 0x567D5202;
CHECKREG r5, 0x67897394;
CHECKREG r6, 0x74440A74;
CHECKREG r7, 0x8666E123;
CHECKREG r4, 0x567D5202;
CHECKREG r5, 0x67897394;
CHECKREG r6, 0x74440A74;
CHECKREG r7, 0x8666E123;
imm32 r0, 0x85678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x38445515;
imm32 r3, 0x46667717;
imm32 r4, 0x568a891b;
imm32 r5, 0x67a9ab1d;
imm32 r6, 0x744a5515;
imm32 r7, 0x8666aa77;
R0.L = R6.L - R0.L (NS);
R1.L = R6.L - R1.H (NS);
R2.L = R6.H - R2.L (NS);
R3.L = R6.H - R3.H (NS);
R4.L = R6.L - R4.L (NS);
R5.L = R6.L - R5.H (NS);
R6.L = R6.H - R6.L (NS);
R7.L = R6.H - R7.H (NS);
CHECKREG r4, 0x568ACBFA;
CHECKREG r5, 0x67A9ED6C;
CHECKREG r6, 0x744A1F35;
CHECKREG r7, 0x8666EDE4;
CHECKREG r4, 0x568ACBFA;
CHECKREG r5, 0x67A9ED6C;
CHECKREG r6, 0x744A1F35;
CHECKREG r7, 0x8666EDE4;
imm32 r0, 0x35678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34845515;
imm32 r3, 0x466a7717;
imm32 r4, 0x5678a91b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445b15;
imm32 r7, 0x866677b7;
R0.L = R7.L - R0.L (NS);
R1.L = R7.L - R1.H (NS);
R2.L = R7.H - R2.L (NS);
R3.L = R7.H - R3.H (NS);
R4.L = R7.L - R4.L (NS);
R5.L = R7.L - R5.H (NS);
R6.L = R7.H - R6.L (NS);
R7.L = R7.H - R7.H (NS);
CHECKREG r4, 0x5678CE9C;
CHECKREG r5, 0x6789102E;
CHECKREG r6, 0x74442B51;
CHECKREG r7, 0x86660000;
CHECKREG r4, 0x5678CE9C;
CHECKREG r5, 0x6789102E;
CHECKREG r6, 0x74442B51;
CHECKREG r7, 0x86660000;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86667777;
R6.L = R2.L - R3.L (S);
R1.L = R4.L - R5.H (S);
R5.L = R7.H - R2.L (S);
R3.L = R0.H - R0.H (S);
R0.L = R3.L - R4.L (S);
R2.L = R5.L - R7.H (S);
R7.L = R6.H - R7.L (S);
R4.L = R1.H - R6.H (S);
CHECKREG r4, 0x5678B345;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x7444DDFE;
CHECKREG r7, 0x8666FCCD;
CHECKREG r4, 0x5678B345;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x7444DDFE;
CHECKREG r7, 0x8666FCCD;
imm32 r0, 0x1d678911;
imm32 r1, 0x27d9ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x466d7717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789dd1d;
imm32 r6, 0x74445515;
imm32 r7, 0x866677d7;
R3.L = R4.L - R0.L (S);
R1.L = R6.L - R3.H (S);
R4.L = R3.H - R2.L (S);
R6.L = R7.H - R1.H (S);
R2.L = R5.L - R4.L (S);
R7.L = R2.L - R7.H (S);
R0.L = R1.H - R6.L (S);
R5.L = R0.H - R5.H (S);
CHECKREG r4, 0x5678F158;
CHECKREG r5, 0x6789B5DE;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x8666655F;
CHECKREG r4, 0x5678F158;
CHECKREG r5, 0x6789B5DE;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x8666655F;
pass
|
tactcomplabs/xbgas-binutils-gdb | 9,699 | sim/testsuite/bfin/c_dsp32shift_rot_mix.s | //Original:/proj/frio/dv/testcases/core/c_dsp32shift_rot_mix/c_dsp32shift_rot_mix.dsp
// Spec Reference: dsp32shift rot
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x01230000;
imm32 r1, 0x12345678;
imm32 r2, 0x83456789;
imm32 r3, 0x9456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb6789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0xd89abcde;
R1 = ROT R0 BY R0.L;
R2 = ROT R1 BY R0.L;
R3 = ROT R2 BY R0.L;
R4 = ROT R3 BY R0.L;
R5 = ROT R4 BY R0.L;
R6 = ROT R5 BY R0.L;
R7 = ROT R6 BY R0.L;
R0 = ROT R7 BY R0.L;
CHECKREG r0, 0x01230000;
CHECKREG r1, 0x01230000;
CHECKREG r2, 0x01230000;
CHECKREG r3, 0x01230000;
CHECKREG r4, 0x01230000;
CHECKREG r5, 0x01230000;
CHECKREG r6, 0x01230000;
CHECKREG r7, 0x01230000;
A0 = 0;
A0.L = R0.L;
A0.H = R0.H;
A0 = ROT A0 BY R1.L;
R6 = A0.w;
imm32 r4, 0x30003000;
imm32 r1, 5;
R7 = ROT R4 BY R1.L;
CHECKREG r6, 0x01230000;
CHECKREG r7, 0x00060003;
imm32 r0, 0x11230001;
imm32 r1, 0xc2345678;
imm32 r2, 0xd3456789;
imm32 r3, 0xb456789a;
imm32 r4, 0x056789ab;
imm32 r5, 0x36789abc;
imm32 r6, 0x1789abcd;
imm32 r7, 0x189abcde;
R1.L = 5;
R2 = ROT R0 BY R1.L;
R3 = ROT R1 BY R1.L;
R4 = ROT R2 BY R1.L;
R5 = ROT R3 BY R1.L;
R6 = ROT R4 BY R1.L;
R7 = ROT R5 BY R1.L;
R0 = ROT R6 BY R1.L;
R1 = ROT R7 BY R1.L;
CHECKREG r0, 0x00108908;
CHECKREG r1, 0x005613A0;
CHECKREG r2, 0x24600021;
CHECKREG r3, 0x468000AC;
CHECKREG r4, 0x8C000422;
CHECKREG r5, 0xD0001584;
CHECKREG r6, 0x80008448;
CHECKREG r7, 0x0002B09D;
imm32 r0, 0x01230002;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x8456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0x789abcde;
R2 = 15;
R3 = ROT R0 BY R2.L;
R4 = ROT R1 BY R2.L;
R5 = ROT R2 BY R2.L;
R6 = ROT R3 BY R2.L;
R7 = ROT R4 BY R2.L;
R0 = ROT R5 BY R2.L;
R1 = ROT R6 BY R2.L;
R2 = ROT R7 BY R2.L;
CHECKREG r0, 0xC0000001;
CHECKREG r1, 0x10006009;
CHECKREG r2, 0x45678891;
CHECKREG r3, 0x80010048;
CHECKREG r4, 0x2B3C448D;
CHECKREG r5, 0x00078000;
CHECKREG r6, 0x80242000;
CHECKREG r7, 0x22468ACF;
imm32 r0, 0x21230003;
imm32 r1, 0x22345678;
imm32 r2, 0x23456789;
imm32 r3, 0x2456789a;
imm32 r4, 0x256789ab;
imm32 r5, 0x26789abc;
imm32 r6, 0x2789abcd;
imm32 r7, 0x289abcde;
R3.L = 24;
R4 = ROT R0 BY R3.L;
R5 = ROT R1 BY R3.L;
R6 = ROT R2 BY R3.L;
R7 = ROT R3 BY R3.L;
R0 = ROT R4 BY R3.L;
R1 = ROT R5 BY R3.L;
R2 = ROT R6 BY R3.L;
R3 = ROT R7 BY R3.L;
CHECKREG r0, 0x8001C848;
CHECKREG r1, 0x2BBC088D;
CHECKREG r2, 0xB34488D1;
CHECKREG r3, 0x000C4915;
CHECKREG r4, 0x03909180;
CHECKREG r5, 0x78111A2B;
CHECKREG r6, 0x8911A2B3;
CHECKREG r7, 0x18922B00;
imm32 r0, 0x01230004;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -1;
R0 = ROT R0 BY R4.L;
R1 = ROT R1 BY R4.L;
R2 = ROT R2 BY R4.L;
R3 = ROT R3 BY R4.L;
R4 = ROT R4 BY R4.L;
R5 = ROT R5 BY R4.L;
R6 = ROT R6 BY R4.L;
R7 = ROT R7 BY R4.L;
CHECKREG r0, 0x80918002;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A2B3C4;
CHECKREG r3, 0x9A2B3C4D;
CHECKREG r4, 0x22B3FFFF;
CHECKREG r5, 0xAB3C4D5E;
CHECKREG r6, 0x33C4D5E6;
CHECKREG r7, 0xBC4D5E6F;
imm32 r0, 0x01230005;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -6;
R6 = ROT R0 BY R5.L;
R7 = ROT R1 BY R5.L;
R0 = ROT R2 BY R5.L;
R1 = ROT R3 BY R5.L;
R2 = ROT R4 BY R5.L;
R3 = ROT R5 BY R5.L;
R4 = ROT R6 BY R5.L;
R5 = ROT R7 BY R5.L;
CHECKREG r0, 0x4C8D159E;
CHECKREG r1, 0xD0D159E2;
CHECKREG r2, 0x59159E26;
CHECKREG r3, 0xD559E3FF;
CHECKREG r4, 0x04A01230;
CHECKREG r5, 0xCB012345;
CHECKREG r6, 0x28048C00;
CHECKREG r7, 0xC048D159;
imm32 r0, 0x01230006;
imm32 r1, 0x82345678;
imm32 r2, 0x73456789;
imm32 r3, 0x3456789a;
imm32 r4, 0xd56789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0xc789abcd;
imm32 r7, 0x789abcde;
R6.L = -15;
R7 = ROT R0 BY R6.L;
R0 = ROT R1 BY R6.L;
R1 = ROT R2 BY R6.L;
R2 = ROT R3 BY R6.L;
R3 = ROT R4 BY R6.L;
R4 = ROT R5 BY R6.L;
R5 = ROT R6 BY R6.L;
R6 = ROT R7 BY R6.L;
CHECKREG r0, 0x59E10468;
CHECKREG r1, 0x9E26E68A;
CHECKREG r2, 0xE26A68AC;
CHECKREG r3, 0x26AFAACF;
CHECKREG r4, 0x6AF0ACF1;
CHECKREG r5, 0xFFC58F13;
CHECKREG r6, 0x091A0030;
CHECKREG r7, 0x00180246;
imm32 r0, 0x01230007;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R7.L = -27;
R0 = ROT R0 BY R7.L;
R1 = ROT R1 BY R7.L;
R2 = ROT R2 BY R7.L;
R3 = ROT R3 BY R7.L;
R4 = ROT R4 BY R7.L;
R5 = ROT R5 BY R7.L;
R6 = ROT R6 BY R7.L;
R7 = ROT R7 BY R7.L;
CHECKREG r0, 0x48C001C0;
CHECKREG r1, 0x8D159E02;
CHECKREG r2, 0xD159E244;
CHECKREG r3, 0x159E2686;
CHECKREG r4, 0x59E26AE8;
CHECKREG r5, 0x9E26AF2A;
CHECKREG r6, 0xE26AF36C;
CHECKREG r7, 0x26BFF96F;
imm32 r0, 0x01230008;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R0.L = 7;
//r0 = rot (r0 by rl0);
R1 = ROT R1 BY R0.L;
R2 = ROT R2 BY R0.L;
R3 = ROT R3 BY R0.L;
R4 = ROT R4 BY R0.L;
R5 = ROT R5 BY R0.L;
R6 = ROT R6 BY R0.L;
R7 = ROT R7 BY R0.L;
CHECKREG r0, 0x01230007;
CHECKREG r1, 0x1A2B3C04;
CHECKREG r2, 0xA2B3C4C8;
CHECKREG r3, 0x2B3C4D4D;
CHECKREG r4, 0xB3C4D591;
CHECKREG r5, 0x3C4D5E15;
CHECKREG r6, 0xC4D5E6D9;
CHECKREG r7, 0x4D5E6F5E;
imm32 r0, 0x01230009;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R1.L = 16;
R0 = ROT R0 BY R1.L;
//r1 = rot (r1 by rl1);
R2 = ROT R2 BY R1.L;
R3 = ROT R3 BY R1.L;
R4 = ROT R4 BY R1.L;
R5 = ROT R5 BY R1.L;
R6 = ROT R6 BY R1.L;
R7 = ROT R7 BY R1.L;
CHECKREG r0, 0x00090091;
CHECKREG r1, 0x12340010;
CHECKREG r2, 0x678991A2;
CHECKREG r3, 0x789A9A2B;
CHECKREG r4, 0x89AB22B3;
CHECKREG r5, 0x9ABCAB3C;
CHECKREG r6, 0xABCD33C4;
CHECKREG r7, 0xBCDEBC4D;
imm32 r0, 0x0123000a;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 = ROT R0 BY R2.L;
R1 = ROT R1 BY R2.L;
//r2 = rot (r2 by rl2);
R3 = ROT R3 BY R2.L;
R4 = ROT R4 BY R2.L;
R5 = ROT R5 BY R2.L;
R6 = ROT R6 BY R2.L;
R7 = ROT R7 BY R2.L;
CHECKREG r0, 0x0048C002;
CHECKREG r1, 0x448D159E;
CHECKREG r2, 0x2345001F;
CHECKREG r3, 0x0D159E26;
CHECKREG r4, 0xD159E26A;
CHECKREG r5, 0x559E26AF;
CHECKREG r6, 0x99E26AF3;
CHECKREG r7, 0x1E26AF37;
imm32 r0, 0x0123000b;
imm32 r1, 0x92345678;
imm32 r2, 0x93456789;
imm32 r3, 0xc456789a;
imm32 r4, 0xa56789ab;
imm32 r5, 0xb6789abc;
imm32 r6, 0xe789abcd;
imm32 r7, 0xf89abcde;
R3.L = 33;
R0 = ROT R0 BY R3.L;
R1 = ROT R1 BY R3.L;
R2 = ROT R2 BY R3.L;
//r3 = rot (r3 by rl3);
R4 = ROT R4 BY R3.L;
R5 = ROT R5 BY R3.L;
R6 = ROT R6 BY R3.L;
R7 = ROT R7 BY R3.L;
CHECKREG r0, 0x048C002E;
CHECKREG r1, 0x48D159E1;
CHECKREG r2, 0x4D159E25;
CHECKREG r3, 0xC4560021;
CHECKREG r4, 0x959E26AD;
CHECKREG r5, 0xD9E26AF1;
CHECKREG r6, 0x9E26AF35;
CHECKREG r7, 0xE26AF37B;
imm32 r0, 0x0123000c;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R4.L = -2;
R0 = ROT R0 BY R4.L;
R1 = ROT R1 BY R4.L;
R2 = ROT R2 BY R4.L;
R3 = ROT R3 BY R4.L;
//r4 = rot (r4 by rl4);
R5 = ROT R5 BY R4.L;
R6 = ROT R6 BY R4.L;
R7 = ROT R7 BY R4.L;
CHECKREG r0, 0x4048C003;
CHECKREG r1, 0x048D159E;
CHECKREG r2, 0x88D159E2;
CHECKREG r3, 0x0D159E26;
CHECKREG r4, 0x4567FFFE;
CHECKREG r5, 0x559E26AF;
CHECKREG r6, 0x99E26AF3;
CHECKREG r7, 0x1E26AF37;
imm32 r0, 0x0123000d;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R5.L = -14;
R0 = ROT R0 BY R5.L;
R1 = ROT R1 BY R5.L;
R2 = ROT R2 BY R5.L;
R3 = ROT R3 BY R5.L;
R4 = ROT R4 BY R5.L;
//r5 = rot (r5 by rl5);
R6 = ROT R6 BY R5.L;
R7 = ROT R7 BY R5.L;
CHECKREG r0, 0x006C048C;
CHECKREG r1, 0xB3C048D1;
CHECKREG r2, 0x3C488D15;
CHECKREG r3, 0xC4D4D159;
CHECKREG r4, 0x4D5D159E;
CHECKREG r5, 0x5678FFF2;
CHECKREG r6, 0x5E699E26;
CHECKREG r7, 0xE6F5E26A;
imm32 r0, 0x0123000e;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x456789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R6.L = -16;
R0 = ROT R0 BY R6.L;
R1 = ROT R1 BY R6.L;
R2 = ROT R2 BY R6.L;
R3 = ROT R3 BY R6.L;
R4 = ROT R4 BY R6.L;
R5 = ROT R5 BY R6.L;
//r6 = rot (r6 by rl6);
R7 = ROT R7 BY R6.L;
CHECKREG r0, 0x001D0123;
CHECKREG r1, 0xACF01234;
CHECKREG r2, 0xCF122345;
CHECKREG r3, 0xF1343456;
CHECKREG r4, 0x13564567;
CHECKREG r5, 0x35795678;
CHECKREG r6, 0x6789FFF0;
CHECKREG r7, 0x79BD789A;
imm32 r0, 0x0123000f;
imm32 r1, 0x12345678;
imm32 r2, 0x83456789;
imm32 r3, 0x3456789a;
imm32 r4, 0xd56789ab;
imm32 r5, 0x56789abc;
imm32 r6, 0x9789abcd;
imm32 r7, 0x789abcde;
R7.L = -32;
R0 = ROT R0 BY R7.L;
R1 = ROT R1 BY R7.L;
R2 = ROT R2 BY R7.L;
R3 = ROT R3 BY R7.L;
R4 = ROT R4 BY R7.L;
R5 = ROT R5 BY R7.L;
R6 = ROT R6 BY R7.L;
R7 = ROT R7 BY R7.L;
CHECKREG r0, 0x0246001f;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x068ACF12;
CHECKREG r3, 0x68ACF135;
CHECKREG r4, 0xAACF1356;
CHECKREG r5, 0xACF13579;
CHECKREG r6, 0x2F13579A;
CHECKREG r7, 0xF135FFC1;
pass
|
tactcomplabs/xbgas-binutils-gdb | 6,197 | sim/testsuite/bfin/c_dspldst_ld_dr_ipp.s | //Original:/testcases/core/c_dspldst_ld_dr_ipp/c_dspldst_ld_dr_ipp.dsp
// Spec Reference: c_dspldst ld_dr_i++/--
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
loadsym i0, DATA_ADDR_3;
loadsym i1, DATA_ADDR_4;
loadsym i2, DATA_ADDR_5;
loadsym i3, DATA_ADDR_6;
R0 = [ I0 ++ ];
R1 = [ I1 ++ ];
R2 = [ I2 ++ ];
R3 = [ I3 ++ ];
R4 = [ I0 ++ ];
R5 = [ I1 ++ ];
R6 = [ I2 ++ ];
R7 = [ I3 ++ ];
CHECKREG r0, 0x00010203;
CHECKREG r1, 0x20212223;
CHECKREG r2, 0x40414243;
CHECKREG r3, 0x60616263;
CHECKREG r4, 0x04050607;
CHECKREG r5, 0x24252627;
CHECKREG r6, 0x44454647;
CHECKREG r7, 0x64656667;
R1 = [ I0 ++ ];
R2 = [ I1 ++ ];
R3 = [ I2 ++ ];
R4 = [ I3 ++ ];
R5 = [ I0 ++ ];
R6 = [ I1 ++ ];
R7 = [ I2 ++ ];
R0 = [ I3 ++ ];
CHECKREG r0, 0x6C6D6E6F;
CHECKREG r1, 0x08090A0B;
CHECKREG r2, 0x28292A2B;
CHECKREG r3, 0x48494A4B;
CHECKREG r4, 0x68696A6B;
CHECKREG r5, 0x0C0D0E0F;
CHECKREG r6, 0x2C2D2E2F;
CHECKREG r7, 0x4C4D4E4F;
R2 = [ I0 ++ ];
R3 = [ I1 ++ ];
R4 = [ I2 ++ ];
R5 = [ I3 ++ ];
R6 = [ I0 ++ ];
R7 = [ I1 ++ ];
R0 = [ I2 ++ ];
R1 = [ I3 ++ ];
CHECKREG r0, 0x54555657;
CHECKREG r1, 0x74757677;
CHECKREG r2, 0x10111213;
CHECKREG r3, 0x30313233;
CHECKREG r4, 0x50515253;
CHECKREG r5, 0x70717273;
CHECKREG r6, 0x14151617;
CHECKREG r7, 0x34353637;
R3 = [ I0 ++ ];
R4 = [ I1 ++ ];
R5 = [ I2 ++ ];
R6 = [ I3 ++ ];
R7 = [ I0 ++ ];
R0 = [ I1 ++ ];
R1 = [ I2 ++ ];
R2 = [ I3 ++ ];
CHECKREG r0, 0x3C3D3E3F;
CHECKREG r1, 0xC5C6C7C8;
CHECKREG r2, 0x7C7D7E7F;
CHECKREG r3, 0x18191A1B;
CHECKREG r4, 0x38393A3B;
CHECKREG r5, 0x58595A5B;
CHECKREG r6, 0x78797A7B;
CHECKREG r7, 0x1C1D1E1F;
// reverse to minus mninus i--
R0 = [ I0 -- ];
R1 = [ I1 -- ];
R2 = [ I2 -- ];
R3 = [ I3 -- ];
R4 = [ I0 -- ];
R5 = [ I1 -- ];
R6 = [ I2 -- ];
R7 = [ I3 -- ];
CHECKREG r0, 0x11223344;
CHECKREG r1, 0x91929394;
CHECKREG r2, 0xC9CACBCD;
CHECKREG r3, 0xEBECEDEE;
CHECKREG r4, 0x1C1D1E1F;
CHECKREG r5, 0x3C3D3E3F;
CHECKREG r6, 0xC5C6C7C8;
CHECKREG r7, 0x7C7D7E7F;
R1 = [ I0 -- ];
R2 = [ I1 -- ];
R3 = [ I2 -- ];
R4 = [ I3 -- ];
R5 = [ I0 -- ];
R6 = [ I1 -- ];
R7 = [ I2 -- ];
R0 = [ I3 -- ];
CHECKREG r0, 0x74757677;
CHECKREG r1, 0x18191A1B;
CHECKREG r2, 0x38393A3B;
CHECKREG r3, 0x58595A5B;
CHECKREG r4, 0x78797A7B;
CHECKREG r5, 0x14151617;
CHECKREG r6, 0x34353637;
CHECKREG r7, 0x54555657;
R2 = [ I0 -- ];
R3 = [ I1 -- ];
R4 = [ I2 -- ];
R5 = [ I3 -- ];
R6 = [ I0 -- ];
R7 = [ I1 -- ];
R0 = [ I2 -- ];
R1 = [ I3 -- ];
CHECKREG r0, 0x4C4D4E4F;
CHECKREG r1, 0x6C6D6E6F;
CHECKREG r2, 0x10111213;
CHECKREG r3, 0x30313233;
CHECKREG r4, 0x50515253;
CHECKREG r5, 0x70717273;
CHECKREG r6, 0x0C0D0E0F;
CHECKREG r7, 0x2C2D2E2F;
R3 = [ I0 -- ];
R4 = [ I1 -- ];
R5 = [ I2 -- ];
R6 = [ I3 -- ];
R7 = [ I0 -- ];
R0 = [ I1 -- ];
R1 = [ I2 -- ];
R2 = [ I3 -- ];
CHECKREG r0, 0x24252627;
CHECKREG r1, 0x44454647;
CHECKREG r2, 0x64656667;
CHECKREG r3, 0x08090A0B;
CHECKREG r4, 0x28292A2B;
CHECKREG r5, 0x48494A4B;
CHECKREG r6, 0x68696A6B;
CHECKREG r7, 0x04050607;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_3:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
DATA_ADDR_4:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
DATA_ADDR_5:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
DATA_ADDR_6:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
.dd 0xAB0CAD0E
DATA_ADDR_7:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xBC0DBE26
DATA_ADDR_8:
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 1,066 | sim/testsuite/bfin/c_brcc_brf_bp.s | //Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp
// Spec Reference: brcc brf bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
IF !CC JUMP good1 (BP); // branch on false (should branch)
CC = ! CC; // set cc=1
R1 = 1; // if go here, error
good1: IF !CC JUMP good2 (BP); // branch on false (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF !CC JUMP bad2 (BP); // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP end; // branch on true (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,632 | sim/testsuite/bfin/a7.s | # mach: bfin
.include "testutils.inc"
start
R1 = 0;
R0 = 0;
R0 = R1 ^ R0;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 1 );
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R0 = R1 | R0;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 1 );
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R0 = 0;
R1 = 1;
CC = R0 == R1;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 2 );
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
CC = BITTST ( R1 , 1 );
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 2 );
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
CC = ! BITTST( R1 , 1 );
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 0x22 );
r7 = cc;
dbga( r7.l, 1);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R0.L = 0;
R0.H = 0x8000;
R0 >>>= 1;
_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 0x22 );
cc = az;
r6 = cc;
dbga( r6.l, 0);
cc = an;
r6 = cc;
dbga( r6.l, 1);
cc = av0;
r6 = cc;
dbga( r6.l, 0);
cc = av0s;
r6 = cc;
dbga( r6.l, 0);
cc = av1;
r6 = cc;
dbga( r6.l, 0);
cc = av1s;
r6 = cc;
dbga( r6.l, 0);
R0.L = 17767; R0.H = 291;
R1.L = 52719; R1.H = -30293;
R2.L = 39612; R2.H = 22136;
R3.L = 4660; R3.H = -8464;
R4.L = 26777; R4.H = 9029;
R5.L = 9029; R5.H = 30865;
R6.L = 21554; R6.H = -26506;
R7.L = 22136; R7.H = 4660;
R0 = R0 + R0;
R1 = R0 - R1;
R2 = R0 & R2;
R3 = R0 | R3;
R4 = R0 & R4;
R5 = R0 & R5;
R6 = R0 | R6;
R7 = R0 & R7;
DBGA ( R0.l , 35534 ); DBGA( R0.h , 582 );
DBGA( R1.l , 48351 ); DBGA ( R1.h , 30874 );
DBGA ( R2.l , 35468 ); DBGA ( R2.h , 576 );
DBGA ( R3.l , 39678 ); DBGA ( R3.h , 0xdef6);
DBGA ( R4.l , 2184 ); DBGA ( R4.h , 580 );
DBGA ( R5.l , 580 ); DBGA( R5.h , 0 );
DBGA ( R6.l, 57086 ); DBGA ( R6.h , 0x9a76 );
DBGA ( R7.l , 584 ); DBGA ( R7.h , 516 );
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,744 | sim/testsuite/bfin/double_prec_mult.s | # mach: bfin
.include "testutils.inc"
start
// This function computes an integer 32x32 multiply,
// and returns the upper 32 bits of the result.
// If the complete 64 bit result is required, one must
// write the partial results as they are computed.
// To change this code for a fractional 32x32, one needs
// to adjust the shifts for magnitude of -15, and use a
// fractional multiply at the end for the upper word halves
// (instead of the integer one).
loadsym P0, input_a;
loadsym P1, input_b;
loadsym P2, output;
P4 = 10;
LSETUP ( loop1 , loop1end ) LC0 = P4;
loop1:
R0 = [ P0 ++ ];
R1 = [ P1 ++ ];
// begin integer double precision routine
// 32 x 32 -> 32
A1 = R0.H * R1.L (M), A0 = R0.L * R1.L (FU);
A1 += R1.H * R0.L (M,IS);
A0 = A0 >>> 16;
A0 += A1;
A0 = A0 >>> 16;
A0 += R0.H * R1.H (IS);
R7 = A0.w;
loop1end:
[ P2 ++ ] = R7; // store 32 bit output
// test results
loadsym P1, output;
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xab6b );
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa627 );
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0xa0e3 );
R0 = [ P1 ++ ]; DBGA ( R0.H , 0xfeae ); DBGA ( R0.L , 0x9b9f );
pass
.data
input_a:
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.dw 0x0000
.dw 0xfabc
.align 4;
input_b:
.dw 0x1000
.dw 0x4010
.dw 0x1000
.dw 0x4011
.dw 0x1000
.dw 0x4012
.dw 0x1000
.dw 0x4013
.dw 0x1000
.dw 0x4014
.dw 0x1000
.dw 0x4015
.dw 0x1000
.dw 0x4016
.dw 0x1000
.dw 0x4017
.dw 0x1000
.dw 0x4018
.dw 0x1000
.dw 0x4019
.align 4;
output:
.space (40);
|
tactcomplabs/xbgas-binutils-gdb | 8,708 | sim/testsuite/bfin/c_ldstiifp_ld_preg.s | //Original:testcases/core/c_ldstiifp_ld_preg/c_ldstiifp_ld_preg.dsp
// Spec Reference: c_ldstiifp load preg
# mach: bfin
.include "testutils.inc"
start
// set all regs
init_i_regs 0;
init_b_regs 0;
init_l_regs 0;
init_m_regs 0;
INIT_R_REGS 0;
I0 = P3;
I2 = SP;
// initial values
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P3 = I1; SP = I3;
p1 = [ fp + 0 ];
P2 = [ FP + -4 ];
P3 = [ FP + -8 ];
P4 = [ FP + -12 ];
P5 = [ FP + -16 ];
SP = [ FP + -20 ];
FP = [ FP + -24 ];
CHECKREG p1, 0x86878889;
CHECKREG p2, 0x82838485;
CHECKREG p3, 0x74757677;
CHECKREG p4, 0x99717273;
CHECKREG p5, 0x55667788;
CHECKREG sp, 0x11223344;
CHECKREG fp, 0x1C1D1E1F;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -28 ];
P2 = [ FP + -32 ];
P3 = [ FP + -36 ];
P4 = [ FP + -40 ];
P5 = [ FP + -44 ];
SP = [ FP + -48 ];
FP = [ FP + -52 ];
CHECKREG p1, 0x18191A1B;
CHECKREG p2, 0x14151617;
CHECKREG p3, 0x10111213;
CHECKREG p4, 0x0C0D0E0F;
CHECKREG p5, 0x08090A0B;
CHECKREG sp, 0x04050607;
CHECKREG fp, 0x00010203;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -56 ];
P2 = [ FP + -60 ];
P3 = [ FP + -64 ];
P4 = [ FP + -68 ];
P5 = [ FP + -72 ];
SP = [ FP + -76 ];
FP = [ FP + -80 ];
CHECKREG p1, 0x76676867;
CHECKREG p2, 0x72636467;
CHECKREG p3, 0x78596067;
CHECKREG p4, 0x74555657;
CHECKREG p5, 0x66676869;
CHECKREG sp, 0x62636465;
CHECKREG fp, 0x58596061;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -84 ];
P2 = [ FP + -88 ];
P3 = [ FP + -92 ];
P4 = [ FP + -96 ];
P5 = [ FP + -100 ];
SP = [ FP + -104 ];
FP = [ FP + -108 ];
CHECKREG p1, 0x54555657;
CHECKREG p2, 0x50515253;
CHECKREG p3, 0x46474849;
CHECKREG p4, 0x42434445;
CHECKREG p5, 0x38394041;
CHECKREG sp, 0x34353637;
CHECKREG fp, 0x30313233;
I1 = P3; P3 = I0; I3 = SP; SP = I2;
loadsym fp, DATA_ADDR_1, 0xc8;
P3 = I1; SP = I3;
P1 = [ FP + -112 ];
P2 = [ FP + -116 ];
P3 = [ FP + -120 ];
P4 = [ FP + -124 ];
P5 = [ FP + -128 ];
SP = [ FP + -4 ];
FP = [ FP + -8 ];
CHECKREG p1, 0x26272829;
CHECKREG p2, 0x22232425;
CHECKREG p3, 0x18192021;
CHECKREG p4, 0x14151617;
CHECKREG p5, 0x09101112;
CHECKREG sp, 0x82838485;
CHECKREG fp, 0x74757677;
P3 = I0; SP = I2;
pass
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x11223344
.dd 0x55667788
.dd 0x99717273
.dd 0x74757677
.dd 0x82838485
.dd 0x86878889
.dd 0x80818283
.dd 0x84858687
.dd 0x01020304
.dd 0x05060708
.dd 0x09101112
.dd 0x14151617
.dd 0x18192021
.dd 0x22232425
.dd 0x26272829
.dd 0x30313233
.dd 0x34353637
.dd 0x38394041
.dd 0x42434445
.dd 0x46474849
.dd 0x50515253
.dd 0x54555657
.dd 0x58596061
.dd 0x62636465
.dd 0x66676869
.dd 0x74555657
.dd 0x78596067
.dd 0x72636467
.dd 0x76676867
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x91929394
.dd 0x95969798
.dd 0x99A1A2A3
.dd 0xA5A6A7A8
.dd 0xA9B0B1B2
.dd 0xB3B4B5B6
.dd 0xB7B8B9C0
.dd 0x70717273
.dd 0x74757677
.dd 0x78798081
.dd 0x82838485
.dd 0x86C283C4
.dd 0x81C283C4
.dd 0x82C283C4
.dd 0x83C283C4
.dd 0x84C283C4
.dd 0x85C283C4
.dd 0x86C283C4
.dd 0x87C288C4
.dd 0x88C283C4
.dd 0x89C283C4
.dd 0x80C283C4
.dd 0x81C283C4
.dd 0x82C288C4
.dd 0x94555659
.dd 0x98596069
.dd 0x92636469
.dd 0x96676869
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0xC5C6C7C8
.dd 0xC9CACBCD
.dd 0xCFD0D1D2
.dd 0xD3D4D5D6
.dd 0xD7D8D9DA
.dd 0xDBDCDDDE
.dd 0xDFE0E1E2
.dd 0xE3E4E5E6
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x97E899EA
.dd 0x98E899EA
.dd 0x99E899EA
.dd 0x91E899EA
.dd 0x92E899EA
.dd 0x93E899EA
.dd 0x94E899EA
.dd 0x95E899EA
.dd 0x96E899EA
.dd 0x977899EA
.dd 0xa455565a
.dd 0xa859606a
.dd 0xa263646a
.dd 0xa667686a
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0xEBECEDEE
.dd 0xF3F4F5F6
.dd 0xF7F8F9FA
.dd 0xFBFCFDFE
.dd 0xFF000102
.dd 0x03040506
.dd 0x0708090A
.dd 0x0B0CAD0E
.dd 0xAB0CAD01
.dd 0xAB0CAD02
.dd 0xAB0CAD03
.dd 0xAB0CAD04
.dd 0xAB0CAD05
.dd 0xAB0CAD06
.dd 0xAB0CAA07
.dd 0xAB0CAD08
.dd 0xAB0CAD09
.dd 0xA00CAD1E
.dd 0xA10CAD2E
.dd 0xA20CAD3E
.dd 0xA30CAD4E
.dd 0xA40CAD5E
.dd 0xA50CAD6E
.dd 0xA60CAD7E
.dd 0xB455565B
.dd 0xB859606B
.dd 0xB263646B
.dd 0xB667686B
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0x0F101213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0xBC0DBE21
.dd 0xBC1DBE22
.dd 0xBC2DBE23
.dd 0xBC3DBE24
.dd 0xBC4DBE65
.dd 0xBC5DBE27
.dd 0xBC6DBE28
.dd 0xBC7DBE29
.dd 0xBC8DBE2F
.dd 0xBC9DBE20
.dd 0xBCADBE21
.dd 0xBCBDBE2F
.dd 0xBCCDBE23
.dd 0xBCDDBE24
.dd 0xBCFDBE25
.dd 0xC455565C
.dd 0xC859606C
.dd 0xC263646C
.dd 0xC667686C
.dd 0xCC0DBE2C
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F
.dd 0xA0A1A2A3
.dd 0xA4A5A6A7
.dd 0xA8A9AAAB
.dd 0xACADAEAF
.dd 0xB0B1B2B3
.dd 0xB4B5B6B7
.dd 0xB8B9BABB
.dd 0xBCBDBEBF
.dd 0xC0C1C2C3
.dd 0xC4C5C6C7
.dd 0xC8C9CACB
.dd 0xCCCDCECF
.dd 0xD0D1D2D3
.dd 0xD4D5D6D7
.dd 0xD8D9DADB
.dd 0xDCDDDEDF
.dd 0xE0E1E2E3
.dd 0xE4E5E6E7
.dd 0xE8E9EAEB
.dd 0xECEDEEEF
.dd 0xF0F1F2F3
.dd 0xF4F5F6F7
.dd 0xF8F9FAFB
.dd 0xFCFDFEFF
|
tactcomplabs/xbgas-binutils-gdb | 2,474 | sim/testsuite/bfin/c_logi2op_bitset.s | //Original:/testcases/core/c_logi2op_bitset/c_logi2op_bitset.dsp
// Spec Reference: Logi2op
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// bit set
BITSET( R0 , 0 ); /* r0 = 0x00000001 */
BITSET( R1 , 1 ); /* r1 = 0x00000002 */
BITSET( R2 , 2 ); /* r2 = 0x00000004 */
BITSET( R3 , 3 ); /* r3 = 0x00000008 */
BITSET( R4 , 4 ); /* r4 = 0x00000010 */
BITSET( R5 , 5 ); /* r5 = 0x00000020 */
BITSET( R6 , 6 ); /* r6 = 0x00000040 */
BITSET( R7 , 7 ); /* r7 = 0x00000080 */
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000004;
CHECKREG r3, 0x00000008;
CHECKREG r4, 0x00000010;
CHECKREG r5, 0x00000020;
CHECKREG r6, 0x00000040;
CHECKREG r7, 0x00000080;
// bit set
BITSET( R0 , 8 ); /* r0 = 0x00000100 */
BITSET( R1 , 9 ); /* r1 = 0x00000200 */
BITSET( R2 , 10 ); /* r2 = 0x00000400 */
BITSET( R3 , 11 ); /* r3 = 0x00000800 */
BITSET( R4 , 12 ); /* r4 = 0x00001000 */
BITSET( R5 , 13 ); /* r5 = 0x00002000 */
BITSET( R6 , 14 ); /* r6 = 0x00004000 */
BITSET( R7 , 15 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00000101;
CHECKREG r1, 0x00000202;
CHECKREG r2, 0x00000404;
CHECKREG r3, 0x00000808;
CHECKREG r4, 0x00001010;
CHECKREG r5, 0x00002020;
CHECKREG r6, 0x00004040;
CHECKREG r7, 0x00008080;
// bit set
BITSET( R0 , 16 ); /* r0 = 0x00000100 */
BITSET( R1 , 17 ); /* r1 = 0x00000200 */
BITSET( R2 , 18 ); /* r2 = 0x00000400 */
BITSET( R3 , 19 ); /* r3 = 0x00000800 */
BITSET( R4 , 20 ); /* r4 = 0x00001000 */
BITSET( R5 , 21 ); /* r5 = 0x00002000 */
BITSET( R6 , 22 ); /* r6 = 0x00004000 */
BITSET( R7 , 23 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x00010101;
CHECKREG r1, 0x00020202;
CHECKREG r2, 0x00040404;
CHECKREG r3, 0x00080808;
CHECKREG r4, 0x00101010;
CHECKREG r5, 0x00202020;
CHECKREG r6, 0x00404040;
CHECKREG r7, 0x00808080;
// bit set
BITSET( R0 , 24 ); /* r0 = 0x00000100 */
BITSET( R1 , 25 ); /* r1 = 0x00000200 */
BITSET( R2 , 26 ); /* r2 = 0x00000400 */
BITSET( R3 , 27 ); /* r3 = 0x00000800 */
BITSET( R4 , 28 ); /* r4 = 0x00001000 */
BITSET( R5 , 29 ); /* r5 = 0x00002000 */
BITSET( R6 , 30 ); /* r6 = 0x00004000 */
BITSET( R7 , 31 ); /* r7 = 0x00008000 */
CHECKREG r0, 0x01010101;
CHECKREG r1, 0x02020202;
CHECKREG r2, 0x04040404;
CHECKREG r3, 0x08080808;
CHECKREG r4, 0x10101010;
CHECKREG r5, 0x20202020;
CHECKREG r6, 0x40404040;
CHECKREG r7, 0x80808080;
pass
|
tactcomplabs/xbgas-binutils-gdb | 7,512 | sim/testsuite/bfin/c_dsp32mac_pair_a1a0_is.s | //Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1a0_is/c_dsp32mac_pair_a1a0_is.dsp
// Spec Reference: dsp32mac pair a1a0 IS
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
// The result accumulated in A , and stored to a reg half
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R4.L * R0.L ), R6 = ( A0 = R4.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R3.L * R1.L ), R0 = ( A0 = R3.H * R1.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R2.L ), R2 = ( A0 += R7.H * R2.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R5.L * R6.L ), R4 = ( A0 += R5.L * R6.H ) (ISS2);
FP = A1.w;
CHECKREG r0, 0xFFFEB854;
CHECKREG r1, 0xFFFFEEE2;
CHECKREG r2, 0xCECAD1AC;
CHECKREG r3, 0xB509D374;
CHECKREG r4, 0x8A4CA32E;
CHECKREG r5, 0x1EC2C250;
CHECKREG r6, 0x47E3910A;
CHECKREG r7, 0x47E3910A;
CHECKREG p1, 0x23F1C885;
CHECKREG p2, 0x23F1C885;
CHECKREG p3, 0xFFFFF771;
CHECKREG p4, 0xFFFF5C2A;
CHECKREG p5, 0xDA84E9BA;
CHECKREG sp, 0xE76568D6;
CHECKREG fp, 0x0F616128;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = ( A1 += R4.L * R0.H ), R4 = ( A0 = R4.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.H ), R0 = ( A0 = R2.H * R3.L ) (ISS2);
P2 = A0.w;
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R5.H ), R2 = ( A0 += R7.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R1 = ( A1 += R6.L * R1.H ), R0 = ( A0 += R6.L * R1.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0x0ADC2224;
CHECKREG r1, 0x00001AE2;
CHECKREG r2, 0x0ADC2224;
CHECKREG r3, 0x00001AE2;
CHECKREG r4, 0x0C80510A;
CHECKREG r5, 0x0D712F1C;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0x06B8978E;
CHECKREG p2, 0xFFFE2564;
CHECKREG p3, 0x00005649;
CHECKREG p4, 0xFFFE2564;
CHECKREG p5, 0x00000D71;
CHECKREG sp, 0x056E1112;
CHECKREG fp, 0x056E1112;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ), R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R7 = ( A1 = R6.H * R3.L ), R6 = ( A0 = R6.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ), R0 = ( A0 += R4.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R2.H * R7.L ), R4 = ( A0 += R2.L * R7.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0x12E88AAA;
CHECKREG r1, 0xE779EB80;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x12E88AAA;
CHECKREG r5, 0xE79F0610;
CHECKREG r6, 0x0000002A;
CHECKREG r7, 0x0000002A;
CHECKREG p1, 0xE91D1DAF;
CHECKREG p2, 0xE590030B;
CHECKREG p3, 0x00000015;
CHECKREG p5, 0xF3BCF5C0;
CHECKREG p4, 0x00000015;
CHECKREG sp, 0x09744555;
CHECKREG fp, 0x09744555;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = ( A1 += R5.H * R3.H ), R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ), R2 = ( A0 = R2.H * R1.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ), R4 = ( A0 += R7.H * R0.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R7 = ( A1 += R4.H * R6.H ), R6 = ( A0 += R4.L * R6.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0xF897461A;
CHECKREG r2, 0xD0654810;
CHECKREG r3, 0x05083598;
CHECKREG r4, 0xD05F99EC;
CHECKREG r5, 0xFFFA51DC;
CHECKREG r6, 0xC5F8000C;
CHECKREG r7, 0xFB1F80C4;
CHECKREG p1, 0xFC4BA30D;
CHECKREG p2, 0xFFFCF74D;
CHECKREG p3, 0x02841ACC;
CHECKREG p4, 0xE832A408;
CHECKREG p5, 0xFFFD28EE;
CHECKREG sp, 0xE82FCCF6;
CHECKREG fp, 0xE2FC0006;
imm32 r0, 0x63545abd;
imm32 r1, 0x86bcfec7;
imm32 r2, 0xa8645679;
imm32 r3, 0x00860007;
imm32 r4, 0xefb86569;
imm32 r5, 0x1235860b;
imm32 r6, 0x000c086d;
imm32 r7, 0x678e0086;
R7 = ( A1 += R1.L * R0.L ) (M), R6 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = ( A1 = R2.L * R3.L ) (M), R0 = ( A0 = R2.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R3 = ( A1 = R7.L * R4.L ) (M), R2 = ( A0 += R7.H * R4.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = ( A1 += R6.L * R5.L ) (M), R4 = ( A0 += R6.L * R5.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0xFFFB3578;
CHECKREG r1, 0x0004BA9E;
CHECKREG r2, 0x00B650E8;
CHECKREG r3, 0xB2D59E54;
CHECKREG r4, 0x04F4C384;
CHECKREG r5, 0xD21436B8;
CHECKREG r6, 0xFF221DD6;
CHECKREG r7, 0xFA419E9A;
CHECKREG p1, 0xFD20CF4D;
CHECKREG p2, 0xFF910EEB;
CHECKREG p3, 0x00025D4F;
CHECKREG p4, 0xFFFD9ABC;
CHECKREG p5, 0xD96ACF2A;
CHECKREG sp, 0x005B2874;
CHECKREG fp, 0x027A61C2;
imm32 r0, 0x98764abd;
imm32 r1, 0xa1bcf4c7;
imm32 r2, 0xa1145649;
imm32 r3, 0x00010005;
imm32 r4, 0xefbc1569;
imm32 r5, 0x1235010b;
imm32 r6, 0x000c001d;
imm32 r7, 0x678e0001;
R5 = A1, R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R1 = A1, R0 = ( A0 = R4.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R3 = A1, R2 = ( A0 += R2.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R1 = A1, R0 = ( A0 += R6.L * R7.H ) (ISS2);
FP = A1.w;
CHECKREG r0, 0x22252FC0;
CHECKREG r1, 0xD21436B8;
CHECKREG r2, 0x220DB994;
CHECKREG r3, 0xD21436B8;
CHECKREG r4, 0xF97279D6;
CHECKREG r5, 0xD21436B8;
CHECKREG r6, 0x000C001D;
CHECKREG r7, 0x678E0001;
CHECKREG p1, 0xE90A1B5C;
CHECKREG p2, 0xFCB93CEB;
CHECKREG p3, 0xE90A1B5C;
CHECKREG p4, 0xFFFFDF3A;
CHECKREG p5, 0xE90A1B5C;
CHECKREG sp, 0x1106DCCA;
CHECKREG fp, 0xE90A1B5C;
imm32 r0, 0x7136459d;
imm32 r1, 0xabd69ec7;
imm32 r2, 0x71145679;
imm32 r3, 0x08010007;
imm32 r4, 0xef9c1569;
imm32 r5, 0x1225010b;
imm32 r6, 0x0003401d;
imm32 r7, 0x678e0561;
R5 = ( A1 += R1.H * R0.L ) (M), R4 = ( A0 = R1.L * R0.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R7 = A1, R6 = ( A0 = R2.H * R3.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R1 = ( A1 = R4.H * R5.L ) (M), R0 = ( A0 += R4.H * R5.H ) (ISS2);
P5 = A1.w;
SP = A0.w;
R5 = A1, R4 = ( A0 += R6.L * R7.H ) (ISS2);
FP = A1.w;
CHECKREG r0, 0x25E6F698;
CHECKREG r1, 0xDBFA4500;
CHECKREG r2, 0x71145679;
CHECKREG r3, 0x08010007;
CHECKREG r4, 0x042A6938;
CHECKREG r5, 0xDBFA4500;
CHECKREG r6, 0x00062F18;
CHECKREG r7, 0xA44E5734;
CHECKREG p1, 0xD2272B9A;
CHECKREG p2, 0xE590030B;
CHECKREG p3, 0xD2272B9A;
CHECKREG p4, 0x0003178C;
CHECKREG p5, 0xEDFD2280;
CHECKREG sp, 0x12F37B4C;
CHECKREG fp, 0xEDFD2280;
imm32 r0, 0x123489bd;
imm32 r1, 0x91bcfec7;
imm32 r2, 0xa9145679;
imm32 r3, 0xd0910007;
imm32 r4, 0xedb91569;
imm32 r5, 0xd235910b;
imm32 r6, 0x0d0c0999;
imm32 r7, 0x67de0009;
R1 = A1, R0 = ( A0 = R5.L * R3.L ) (ISS2);
P1 = A1.w;
P2 = A0.w;
R3 = ( A1 = R2.H * R1.H ) (M), R2 = ( A0 = R2.H * R1.L ) (ISS2);
P3 = A1.w;
P4 = A0.w;
R5 = ( A1 = R7.H * R0.H ) (M), R4 = ( A0 += R7.H * R0.H ) (ISS2);
P5 = A0.w;
SP = A1.w;
R7 = A1, R6 = ( A0 += R4.L * R6.H ) (ISS2);
FP = A0.w;
CHECKREG r0, 0xFFF9EE9A;
CHECKREG r1, 0xDBFA4500;
CHECKREG r2, 0xD124C800;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xD11F19DC;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0xD3C1DE7C;
CHECKREG r7, 0x7FFFFFFF;
CHECKREG p1, 0xEDFD2280;
CHECKREG p2, 0xFFFCF74D;
CHECKREG p3, 0xB54F3988;
CHECKREG p4, 0xE8926400;
CHECKREG p5, 0xE88F8CEE;
CHECKREG sp, 0x67DB28EE;
CHECKREG fp, 0xE9E0EF3E;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,700 | sim/testsuite/bfin/c_dsp32mac_pair_mix.s | //Original:/testcases/core/c_dsp32mac_pair_mix/c_dsp32mac_pair_mix.dsp
// Spec Reference: dsp32mac pair mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00060007;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
A0 = 0;
ASTAT = R0;
// The result accumulated in A0 and A1, and stored to a reg pair
imm32 r0, 0x00120034;
imm32 r1, 0x00050006;
R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R5 = ( A1 = R1.L * R0.H );
R7 = ( A1 = R1.L * R0.H ) (M), A0 = R1.H * R0.L;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x000000d8;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x000000d8;
CHECKREG r6, 0x000C000D;
CHECKREG r7, 0x0000006c;
A1 = R1.L * R0.H, R2 = ( A0 += R1.H * R0.L );
A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L );
CHECKREG r2, 0x00000410;
CHECKREG r3, 0x000000d8;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x000000d8;
CHECKREG r6, 0x00000208;
CHECKREG r7, 0x0000006c;
R3 = ( A1 = R1.L * R0.H ), R2 = ( A0 += R1.H * R0.L ) (S2RND);
R5 = ( A1 = R1.L * R0.H ) (M), R4 = ( A0 -= R1.H * R0.L ) (S2RND);
CHECKREG r2, 0x00000820;
CHECKREG r3, 0x000001B0;
CHECKREG r4, 0x00000410;
CHECKREG r5, 0x000000D8;
imm32 r0, 0x12345678;
imm32 r1, 0x34567897;
imm32 r2, 0x0acb1234;
imm32 r3, 0x456acb07;
imm32 r4, 0x421dbc09;
imm32 r5, 0x89acbd0b;
imm32 r6, 0x5adbcd0d;
imm32 r7, 0x9abc230f;
A1 += R7.L * R5.H, R2 = ( A0 = R7.H * R5.L );
A1 -= R1.H * R2.L (M), R6 = ( A0 += R1.L * R2.H ) (S2RND);
CHECKREG r0, 0x12345678;
CHECKREG r1, 0x34567897;
CHECKREG r2, 0x34F8E428;
CHECKREG r3, 0x456ACB07;
CHECKREG r4, 0x421DBC09;
CHECKREG r5, 0x89ACBD0B;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x9ABC230F;
pass
|
tactcomplabs/xbgas-binutils-gdb | 1,452 | sim/testsuite/bfin/c_ldimmhalf_drhi.s | //Original:/testcases/core/c_ldimmhalf_drhi/c_ldimmhalf_drhi.dsp
// Spec Reference: ldimmhalf dreg hi
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS -1;
// test Dreg
R0.H = 0x0001;
R1.H = 0x0003;
R2.H = 0x0005;
R3.H = 0x0007;
R4.H = 0x0009;
R5.H = 0x000b;
R6.H = 0x000d;
R7.H = 0x000f;
CHECKREG r0, 0x0001FFFF;
CHECKREG r1, 0x0003FFFF;
CHECKREG r2, 0x0005FFFF;
CHECKREG r3, 0x0007FFFF;
CHECKREG r4, 0x0009FFFF;
CHECKREG r5, 0x000bFFFF;
CHECKREG r6, 0x000dFFFF;
CHECKREG r7, 0x000fFFFF;
R0.H = 0x0020;
R1.H = 0x0040;
R2.H = 0x0060;
R3.H = 0x0080;
R4.H = 0x00a0;
R5.H = 0x00b0;
R6.H = 0x00c0;
R7.H = 0x00d0;
CHECKREG r0, 0x0020FFFF;
CHECKREG r1, 0x0040FFFF;
CHECKREG r2, 0x0060FFFF;
CHECKREG r3, 0x0080FFFF;
CHECKREG r4, 0x00a0FFFF;
CHECKREG r5, 0x00b0FFFF;
CHECKREG r6, 0x00c0FFFF;
CHECKREG r7, 0x00d0FFFF;
R0.H = 0x0100;
R1.H = 0x0200;
R2.H = 0x0300;
R3.H = 0x0400;
R4.H = 0x0500;
R5.H = 0x0600;
R6.H = 0x0700;
R7.H = 0x0800;
CHECKREG r0, 0x0100FFFF;
CHECKREG r1, 0x0200FFFF;
CHECKREG r2, 0x0300FFFF;
CHECKREG r3, 0x0400FFFF;
CHECKREG r4, 0x0500FFFF;
CHECKREG r5, 0x0600FFFF;
CHECKREG r6, 0x0700FFFF;
CHECKREG r7, 0x0800FFFF;
R0 = 0;
R1 = 0;
R2 = 0;
R3 = 0;
R4 = 0;
R5 = 0;
R6 = 0;
R7 = 0;
R0.H = 0x7fff;
R1.H = 0x7ffe;
R2.H = 32767;
R3.H = 32766;
R4.H = -32768;
R5.H = -32767;
CHECKREG r0, 0x7fff0000;
CHECKREG r1, 0x7ffe0000;
CHECKREG r2, 0x7fff0000;
CHECKREG r3, 0x7ffe0000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x80010000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,199 | sim/testsuite/bfin/c_logi2op_log_l_shft.s | //Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp
// Spec Reference: Logi2op <<=
# mach: bfin
.include "testutils.inc"
start
// Logical <<= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81111111;
imm32 r6, 0x81111111;
imm32 r7, 0x81111111;
R0 <<= 0; /* r0 = 0x81111111 */
R1 <<= 1; /* r1 = 0x40888888 */
R2 <<= 2; /* r2 = 0x20444444 */
R3 <<= 3; /* r3 = 0x10222222 */
R4 <<= 4; /* r4 = 0x08111111 */
R5 <<= 5; /* r5 = 0x04088888 */
R6 <<= 6; /* r6 = 0x02044444 */
R7 <<= 7; /* r7 = 0x01022222 */
CHECKREG r0, 0x81111111;
CHECKREG r1, 0x02222222;
CHECKREG r2, 0x04444444;
CHECKREG r3, 0x08888888;
CHECKREG r4, 0x11111110;
CHECKREG r5, 0x22222220;
CHECKREG r6, 0x44444440;
CHECKREG r7, 0x88888880;
// bit 8-15
imm32 r0, 0x82222222;
imm32 r1, 0x82222222;
imm32 r2, 0x82222222;
imm32 r3, 0x82222222;
imm32 r4, 0x82222222;
imm32 r5, 0x82222222;
imm32 r6, 0x82222222;
imm32 r7, 0x82222222;
R0 <<= 8;
R1 <<= 9;
R2 <<= 10;
R3 <<= 11;
R4 <<= 12;
R5 <<= 13;
R6 <<= 14;
R7 <<= 15;
CHECKREG r0, 0x22222200;
CHECKREG r1, 0x44444400;
CHECKREG r2, 0x88888800;
CHECKREG r3, 0x11111000;
CHECKREG r4, 0x22222000;
CHECKREG r5, 0x44444000;
CHECKREG r6, 0x88888000;
CHECKREG r7, 0x11110000;
// bit 16-23
imm32 r0, 0x83333333;
imm32 r1, 0x83333333;
imm32 r2, 0x83333333;
imm32 r3, 0x83333333;
imm32 r4, 0x83333333;
imm32 r5, 0x83333333;
imm32 r6, 0x83333333;
imm32 r7, 0x83333333;
R0 <<= 16;
R1 <<= 17;
R2 <<= 18;
R3 <<= 19;
R4 <<= 20;
R5 <<= 21;
R6 <<= 22;
R7 <<= 23;
CHECKREG r0, 0x33330000;
CHECKREG r1, 0x66660000;
CHECKREG r2, 0xCCCC0000;
CHECKREG r3, 0x99980000;
CHECKREG r4, 0x33300000;
CHECKREG r5, 0x66600000;
CHECKREG r6, 0xCCC00000;
CHECKREG r7, 0x99800000;
// bit 24-31
imm32 r0, 0x84444444;
imm32 r1, 0x84444444;
imm32 r2, 0x84444444;
imm32 r3, 0x84444444;
imm32 r4, 0x84444444;
imm32 r5, 0x84444444;
imm32 r6, 0x84444444;
imm32 r7, 0x84444444;
R0 <<= 24;
R1 <<= 25;
R2 <<= 26;
R3 <<= 27;
R4 <<= 28;
R5 <<= 29;
R6 <<= 30;
R7 <<= 31;
CHECKREG r0, 0x44000000;
CHECKREG r1, 0x88000000;
CHECKREG r2, 0x10000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
// Arithmetic <<= : positive data
// bit 0-7
imm32 r0, 0x41111111;
imm32 r1, 0x41111111;
imm32 r2, 0x41111111;
imm32 r3, 0x41111111;
imm32 r4, 0x41111111;
imm32 r5, 0x41111111;
imm32 r6, 0x41111111;
imm32 r7, 0x41111111;
R0 <<= 0;
R1 <<= 1;
R2 <<= 2;
R3 <<= 3;
R4 <<= 4;
R5 <<= 5;
R6 <<= 6;
R7 <<= 7;
CHECKREG r0, 0x41111111;
CHECKREG r1, 0x82222222;
CHECKREG r2, 0x04444444;
CHECKREG r3, 0x08888888;
CHECKREG r4, 0x11111110;
CHECKREG r5, 0x22222220;
CHECKREG r6, 0x44444440;
CHECKREG r7, 0x88888880;
// bit 8-15
imm32 r0, 0x42222222;
imm32 r1, 0x42222222;
imm32 r2, 0x42222222;
imm32 r3, 0x42222222;
imm32 r4, 0x42222222;
imm32 r5, 0x42222222;
imm32 r6, 0x42222222;
imm32 r7, 0x42222222;
R0 <<= 8;
R1 <<= 9;
R2 <<= 10;
R3 <<= 11;
R4 <<= 12;
R5 <<= 13;
R6 <<= 14;
R7 <<= 15;
CHECKREG r0, 0x22222200;
CHECKREG r1, 0x44444400;
CHECKREG r2, 0x88888800;
CHECKREG r3, 0x11111000;
CHECKREG r4, 0x22222000;
CHECKREG r5, 0x44444000;
CHECKREG r6, 0x88888000;
CHECKREG r7, 0x11110000;
// bit 16-23
imm32 r0, 0x43333333;
imm32 r1, 0x43333333;
imm32 r2, 0x43333333;
imm32 r3, 0x43333333;
imm32 r4, 0x43333333;
imm32 r5, 0x43333333;
imm32 r6, 0x43333333;
imm32 r7, 0x43333333;
R0 <<= 16;
R1 <<= 17;
R2 <<= 18;
R3 <<= 19;
R4 <<= 20;
R5 <<= 21;
R6 <<= 22;
R7 <<= 23;
CHECKREG r0, 0x33330000;
CHECKREG r1, 0x66660000;
CHECKREG r2, 0xCCCC0000;
CHECKREG r3, 0x99980000;
CHECKREG r4, 0x33300000;
CHECKREG r5, 0x66600000;
CHECKREG r6, 0xCCC00000;
CHECKREG r7, 0x99800000;
// bit 24-31
imm32 r0, 0x44444444;
imm32 r1, 0x44444444;
imm32 r2, 0x44444444;
imm32 r3, 0x44444444;
imm32 r4, 0x44444444;
imm32 r5, 0x44444444;
imm32 r6, 0x44444444;
imm32 r7, 0x44444444;
R0 <<= 24;
R1 <<= 25;
R2 <<= 26;
R3 <<= 27;
R4 <<= 28;
R5 <<= 29;
R6 <<= 30;
R7 <<= 31;
CHECKREG r0, 0x44000000;
CHECKREG r1, 0x88000000;
CHECKREG r2, 0x10000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,760 | sim/testsuite/bfin/c_dsp32shift_fdepx.s | //Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp
// Spec Reference: dsp32shift fdep x
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000001;
imm32 r1, 0x01000801;
imm32 r2, 0x08200802;
imm32 r3, 0x08030803;
imm32 r4, 0x08004804;
imm32 r5, 0x08000505;
imm32 r6, 0x08000866;
imm32 r7, 0x08000807;
R1 = DEPOSIT( R1, R0 );
R2 = DEPOSIT( R2, R0 );
R3 = DEPOSIT( R3, R0 );
R4 = DEPOSIT( R4, R0 ) (X);
R5 = DEPOSIT( R5, R0 );
R6 = DEPOSIT( R6, R0 );
R7 = DEPOSIT( R7, R0 ) (X);
R0 = DEPOSIT( R0, R0 );
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x01000800;
CHECKREG r2, 0x08200802;
CHECKREG r3, 0x08030802;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x08000504;
CHECKREG r6, 0x08000866;
CHECKREG r7, 0x00000000;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000002;
imm32 r2, 0x09000002;
imm32 r3, 0x09100003;
imm32 r4, 0x09020004;
imm32 r5, 0x09003005;
imm32 r6, 0x09000406;
imm32 r7, 0x09000057;
R0 = DEPOSIT( R0, R1 );
R2 = DEPOSIT( R2, R1 );
R3 = DEPOSIT( R3, R1 );
R4 = DEPOSIT( R4, R1 );
R5 = DEPOSIT( R5, R1 ) (X);
R6 = DEPOSIT( R6, R1 );
R7 = DEPOSIT( R7, R1 ) (X);
R1 = DEPOSIT( R1, R1 );
CHECKREG r0, 0x0900D000;
CHECKREG r1, 0x09000000;
CHECKREG r2, 0x09000000;
CHECKREG r3, 0x09100000;
CHECKREG r4, 0x09020004;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x09000404;
CHECKREG r7, 0x00000000;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a000010;
imm32 r4, 0x0a00e004;
imm32 r5, 0x0a00e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0a00e007;
R0 = DEPOSIT( R0, R2 );
R1 = DEPOSIT( R1, R2 );
R3 = DEPOSIT( R3, R2 );
R4 = DEPOSIT( R4, R2 );
R5 = DEPOSIT( R5, R2 );
R6 = DEPOSIT( R6, R2 );
R7 = DEPOSIT( R7, R2 );
R2 = DEPOSIT( R2, R2 );
CHECKREG r0, 0x0A008A00;
CHECKREG r1, 0x0A008A00;
CHECKREG r2, 0x0A000A00;
CHECKREG r3, 0x0A000A00;
CHECKREG r4, 0x0A008A00;
CHECKREG r5, 0x0A008A00;
CHECKREG r6, 0x0A008A00;
CHECKREG r7, 0x0A008A00;
imm32 r0, 0x4b00f001;
imm32 r1, 0x5b00f001;
imm32 r2, 0x6b00f002;
imm32 r3, 0x9f000010;
imm32 r4, 0x8b00f004;
imm32 r5, 0x0900f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x0b0af007;
R0 = DEPOSIT( R0, R3 );
R1 = DEPOSIT( R1, R3 );
R2 = DEPOSIT( R2, R3 ) (X);
R4 = DEPOSIT( R4, R3 );
R5 = DEPOSIT( R5, R3 );
R6 = DEPOSIT( R6, R3 ) (X);
R7 = DEPOSIT( R7, R3 );
R3 = DEPOSIT( R3, R3 );
CHECKREG r0, 0x4B009F00;
CHECKREG r1, 0x5B009F00;
CHECKREG r2, 0xFFFF9F00;
CHECKREG r3, 0x9F009F00;
CHECKREG r4, 0x8B009F00;
CHECKREG r5, 0x09009F00;
CHECKREG r6, 0xFFFF9F00;
CHECKREG r7, 0x0B0A9F00;
imm32 r0, 0x0c0000c0;
imm32 r1, 0x0c0100c0;
imm32 r2, 0x0c0200c0;
imm32 r3, 0x0c0300c0;
imm32 r4, 0x0c04000c;
imm32 r5, 0x0c0500c0;
imm32 r6, 0x0c0600c0;
imm32 r7, 0x0c0700c0;
R0 = DEPOSIT( R0, R4 );
R1 = DEPOSIT( R1, R4 );
R2 = DEPOSIT( R2, R4 );
R3 = DEPOSIT( R3, R4 );
R5 = DEPOSIT( R5, R4 ) (X);
R6 = DEPOSIT( R6, R4 );
R7 = DEPOSIT( R7, R4 );
R4 = DEPOSIT( R4, R4 );
CHECKREG r0, 0x0C000C04;
CHECKREG r1, 0x0C010C04;
CHECKREG r2, 0x0C020C04;
CHECKREG r3, 0x0C030C04;
CHECKREG r4, 0x0C040C04;
CHECKREG r5, 0xFFFFFC04;
CHECKREG r6, 0x0C060C04;
CHECKREG r7, 0x0C070C04;
imm32 r0, 0xa00100d0;
imm32 r1, 0xa00100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa0050007;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R5 = DEPOSIT( R0, R5 );
R6 = DEPOSIT( R1, R5 ) (X);
R7 = DEPOSIT( R2, R5 );
R0 = DEPOSIT( R3, R5 );
R1 = DEPOSIT( R4, R5 ) (X);
R2 = DEPOSIT( R6, R5 );
R3 = DEPOSIT( R7, R5 );
R4 = DEPOSIT( R5, R5 );
CHECKREG r0, 0xA00300C1;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0xA00200C1;
CHECKREG r4, 0xA0010081;
CHECKREG r5, 0xA0010085;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0xA00200C1;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0x00237809;
imm32 r7, 0xb0070000;
R0 = DEPOSIT( R0, R6 );
R1 = DEPOSIT( R1, R6 );
R2 = DEPOSIT( R2, R6 );
R3 = DEPOSIT( R3, R6 ) (X);
R4 = DEPOSIT( R4, R6 );
R5 = DEPOSIT( R5, R6 );
R6 = DEPOSIT( R6, R6 );
R7 = DEPOSIT( R7, R6 );
CHECKREG r0, 0x23010000;
CHECKREG r1, 0x23010000;
CHECKREG r2, 0x2302000F;
CHECKREG r3, 0x23030000;
CHECKREG r4, 0x23040000;
CHECKREG r5, 0x23050000;
CHECKREG r6, 0x23237809;
CHECKREG r7, 0x23070000;
imm32 r0, 0xd00100e0;
imm32 r1, 0xd00100e0;
imm32 r2, 0xd00200e0;
imm32 r3, 0xd00300e0;
imm32 r4, 0xd00400e0;
imm32 r5, 0xd00500e0;
imm32 r6, 0xd00600e0;
imm32 r7, 0x00012345;
R1 = DEPOSIT( R0, R7 );
R2 = DEPOSIT( R1, R7 );
R3 = DEPOSIT( R2, R7 );
R4 = DEPOSIT( R3, R7 );
R5 = DEPOSIT( R4, R7 ) (X);
R6 = DEPOSIT( R5, R7 );
R7 = DEPOSIT( R6, R7 ) (X);
R0 = DEPOSIT( R7, R7 );
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xD0010008;
CHECKREG r2, 0xD0010008;
CHECKREG r3, 0xD0010008;
CHECKREG r4, 0xD0010008;
CHECKREG r5, 0x00000008;
CHECKREG r6, 0x00000008;
CHECKREG r7, 0x00000008;
pass
|
tactcomplabs/xbgas-binutils-gdb | 4,621 | sim/testsuite/bfin/c_dsp32mult_pair_s.s | //Original:/testcases/core/c_dsp32mult_pair_s/c_dsp32mult_pair_s.dsp
// Spec Reference: dsp32mult pair s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x8b235625;
imm32 r1, 0x93ba5127;
imm32 r2, 0xa3446725;
imm32 r3, 0x00050027;
imm32 r4, 0xb0ab6d29;
imm32 r5, 0x10ace72b;
imm32 r6, 0xc00c008d;
imm32 r7, 0xd2467029;
R1 = R0.L * R0.L, R0 = R0.L * R0.L (S2RND);
R3 = R0.L * R1.L, R2 = R0.L * R1.H (S2RND);
R5 = R1.L * R0.L, R4 = R1.H * R0.L (S2RND);
R7 = R1.L * R1.L, R6 = R1.H * R1.H (S2RND);
CHECKREG r0, 0x73F38564;
CHECKREG r1, 0x73F38564;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x7FFFFFFF;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x7FFFFFFF;
CHECKREG r6, 0x7FFFFFFF;
CHECKREG r7, 0x7FFFFFFF;
imm32 r0, 0x5b33a635;
imm32 r1, 0x6fbe5137;
imm32 r2, 0x1324b735;
imm32 r3, 0x9006d037;
imm32 r4, 0x80abcb39;
imm32 r5, 0xb0acef3b;
imm32 r6, 0xa00c00dd;
imm32 r7, 0x12469003;
R1 = R2.L * R2.L, R0 = R2.L * R2.L (S2RND);
R3 = R2.L * R3.L, R2 = R2.L * R3.H (S2RND);
R5 = R3.L * R2.L, R4 = R3.H * R2.L (S2RND);
R7 = R3.L * R3.L, R6 = R3.H * R3.H (S2RND);
CHECKREG r0, 0x52CB43E4;
CHECKREG r1, 0x52CB43E4;
CHECKREG r2, 0x7F5C6CF8;
CHECKREG r3, 0x3659B18C;
CHECKREG r4, 0x5C88C8E0;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x2E26ABC4;
CHECKREG r7, 0x602B9240;
imm32 r0, 0x1b235655;
imm32 r1, 0xc4ba5157;
imm32 r2, 0x63246755;
imm32 r3, 0x00060055;
imm32 r4, 0x90abc509;
imm32 r5, 0x10acef5b;
imm32 r6, 0xb00c005d;
imm32 r7, 0x1246705f;
R1 = R4.L * R4.L, R0 = R4.L * R4.L (S2RND);
R3 = R4.L * R5.L, R2 = R4.L * R5.H (S2RND);
R5 = R5.L * R4.L, R4 = R5.H * R4.L (S2RND);
R7 = R5.L * R5.L, R6 = R5.H * R5.H (S2RND);
CHECKREG r0, 0x36536944;
CHECKREG r1, 0x36536944;
CHECKREG r2, 0xF0A3C830;
CHECKREG r3, 0x0F55C4CC;
CHECKREG r4, 0xF0A3C830;
CHECKREG r5, 0x0F55C4CC;
CHECKREG r6, 0x03AC48E4;
CHECKREG r7, 0x36C40A40;
imm32 r0, 0xab235666;
imm32 r1, 0xeaba5166;
imm32 r2, 0x13d48766;
imm32 r3, 0xf00b0066;
imm32 r4, 0x90ab9d69;
imm32 r5, 0x10ac5f6b;
imm32 r6, 0x800cb66d;
imm32 r7, 0x1246707f;
R1 = R6.L * R6.L, R0 = R6.L * R6.L (S2RND);
R3 = R6.L * R7.L, R2 = R6.L * R7.H (S2RND);
R5 = R7.L * R6.L, R4 = R7.H * R6.L (S2RND);
R7 = R7.L * R7.L, R6 = R7.H * R7.H (S2RND);
CHECKREG r0, 0x5494A9A4;
CHECKREG r1, 0x5494A9A4;
CHECKREG r2, 0xEAFE2F38;
CHECKREG r3, 0x80000000;
CHECKREG r4, 0xEAFE2F38;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x0537AC90;
CHECKREG r7, 0x7FFFFFFF;
// mix order
imm32 r0, 0xab23a675;
imm32 r1, 0xcfba5127;
imm32 r2, 0x13246705;
imm32 r3, 0x00060007;
imm32 r4, 0x90abcd09;
imm32 r5, 0x10acdfdb;
imm32 r6, 0x000c000d;
imm32 r7, 0x1246f00f;
R1 = R3.L * R2.L (M), R0 = R3.L * R2.H (S2RND);
R3 = R1.L * R0.H, R2 = R1.H * R0.L (S2RND);
R5 = R7.H * R4.L, R4 = R7.H * R4.L (S2RND);
R7 = R5.L * R6.L (M), R6 = R5.H * R6.L (S2RND);
CHECKREG r0, 0x000217F0;
CHECKREG r1, 0x0005A246;
CHECKREG r2, 0x0001DEC0;
CHECKREG r3, 0xFFFD1230;
CHECKREG r4, 0xF172C9D8;
CHECKREG r5, 0xF172C9D8;
CHECKREG r6, 0xFFFD0B28;
CHECKREG r7, 0xFFFA7FF0;
imm32 r0, 0x9b235a75;
imm32 r1, 0xc9ba5127;
imm32 r2, 0x13946905;
imm32 r3, 0x00090007;
imm32 r4, 0x90ab9d09;
imm32 r5, 0x10ace9db;
imm32 r6, 0x000c0d9d;
imm32 r7, 0x12467009;
R3 = R6.L * R5.L, R2 = R6.L * R5.H (S2RND);
R1 = R3.L * R0.H (M), R0 = R3.H * R0.L (S2RND);
R5 = R1.L * R4.L (M), R4 = R1.H * R4.L (S2RND);
R7 = R2.H * R7.L, R6 = R2.H * R7.L (S2RND);
CHECKREG r0, 0xF9577348;
CHECKREG r1, 0x31F9EE68;
CHECKREG r2, 0x038BD5F0;
CHECKREG r3, 0xFB4A293C;
CHECKREG r4, 0xB2B9DB04;
CHECKREG r5, 0xEA6A5350;
CHECKREG r6, 0x0633BF8C;
CHECKREG r7, 0x0633BF8C;
imm32 r0, 0x8b235675;
imm32 r1, 0xc8ba5127;
imm32 r2, 0x13846705;
imm32 r3, 0x00080007;
imm32 r4, 0x90ab8d09;
imm32 r5, 0x10ace8db;
imm32 r6, 0x000c008d;
imm32 r7, 0x12467008;
R3 = R6.H * R5.L, R2 = R6.L * R5.H (S2RND);
R7 = R2.L * R0.H (M), R6 = R2.H * R0.L (S2RND);
R5 = R1.L * R3.L (M), R4 = R1.H * R3.L (S2RND);
R1 = R2.H * R7.L, R0 = R2.L * R7.H (S2RND);
CHECKREG r0, 0x510340C0;
CHECKREG r1, 0xFFDAAA00;
CHECKREG r2, 0x0024BAF0;
CHECKREG r3, 0xFFFBA910;
CHECKREG r4, 0x4B155680;
CHECKREG r5, 0x6B2FA2E0;
CHECKREG r6, 0x0030A1D0;
CHECKREG r7, 0xB4EDBDA0;
imm32 r0, 0xeb235675;
imm32 r1, 0xceba5127;
imm32 r2, 0x13e46705;
imm32 r3, 0x000e0007;
imm32 r4, 0x90abed09;
imm32 r5, 0x10aceedb;
imm32 r6, 0x000c00ed;
imm32 r7, 0x1246700e;
R1 = R1.H * R4.L, R0 = R1.H * R4.L (S2RND);
R3 = R2.L * R5.L, R2 = R2.L * R5.H (S2RND);
R5 = R3.H * R6.L, R4 = R3.L * R6.L (S2RND);
R7 = R4.L * R0.H, R6 = R4.H * R0.L (S2RND);
CHECKREG r0, 0x0E99DA28;
CHECKREG r1, 0x0E99DA28;
CHECKREG r2, 0x1AD61D70;
CHECKREG r3, 0xE4671D1C;
CHECKREG r4, 0x006BCBB0;
CHECKREG r5, 0xFF99CD6C;
CHECKREG r6, 0xFFC0BAE0;
CHECKREG r7, 0xF41170C0;
pass
|
tactcomplabs/xbgas-binutils-gdb | 2,626 | sim/testsuite/bfin/m3.s | // MAC test program.
// Test basic edge values
// UNSIGNED FRACTIONAL mode U
// test ops: "+=" "-="
# mach: bfin
.include "testutils.inc"
start
// load r0=0x80007fff
// load r1=0x80007fff
// load r2=0xf0000000
// load r3=0x0000007f
// load r4=0x00000080
// load r5=0xffffffff
loadsym P0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
R5 = [ P0 ++ ];
dbga(r0.h, 0x8000);
dbga(r0.l, 0x7fff);
dbga(r1.h, 0x8000);
dbga(r1.l, 0x7fff);
dbga(r2.h, 0xf000);
dbga(r2.l, 0);
// 0x8000 * 0x7fff = 0x003fff8000
A1 = A0 = 0;
A1 += R0.H * R1.L, A0 += R0.H * R1.L (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x8000 );
DBGA ( R6.H , 0x3fff );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x8000 );
DBGA ( R6.H , 0x3fff );
DBGA ( R7.L , 0x0000 );
// 0x8000 * 0x8000 = 0x0040000000
A1 = A0 = 0;
A1 += R0.H * R1.H, A0 += R0.H * R1.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x4000 );
DBGA ( R7.L , 0x0000 );
// 0xffff * 0xffff = 0x00fffe0001
A1 = A0 = 0;
A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0xfffe );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0001 );
DBGA ( R6.H , 0xfffe );
DBGA ( R7.L , 0x0000 );
// saturate high by first loading large value into accums
// expected value is 0xffffffffff
A1 = A0 = 0;
A1.w = R5;
A1.x = R5.L;
A0.w = R5;
A0.x = R5.L;
A1 += R5.H * R5.H, A0 += R5.H * R5.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0xffff );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0xffff );
DBGA ( R6.H , 0xffff );
DBGA ( R7.L , 0xffff );
// saturate low with "-="
// expected value is 0x0000000000
A1 = A0 = 0;
A1 -= R4.L * R4.L, A0 -= R4.L * R4.L (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
// saturate low with "-="
// expected value is 0x0000000000
A1 = A0 = 0;
A1 -= R1.H * R0.H, A0 -= R1.H * R0.H (FU);
R6 = A1.w;
R7.L = A1.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
R6 = A0.w;
R7.L = A0.x;
DBGA ( R6.L , 0x0000 );
DBGA ( R6.H , 0x0000 );
DBGA ( R7.L , 0x0000 );
pass
.data
data0:
.dw 0x7fff
.dw 0x8000
.dw 0x7fff
.dw 0x8000
.dw 0x0000
.dw 0xf000
.dw 0x007f
.dw 0x0000
.dw 0x0080
.dw 0x0000
.dw 0xffff
.dw 0xffff
|
tactcomplabs/xbgas-binutils-gdb | 1,555 | sim/testsuite/bfin/x1.s | # mach: bfin
.include "testutils.inc"
start
// 0.5
imm32 r0, 0x40004000;
imm32 r1, 0x40004000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x40004000;
checkreg r3, 0;
imm32 r1, 0x10001000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x28002800;
checkreg r3, 0x18001800;
R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
checkreg r0, 0x20002000;
checkreg r1, 0x08000800;
R0 = 1;
R0 <<= 15;
R1 = R0 << 16;
R0 = R0 | R1;
R1 = R0;
checkreg r0, 0x80008000;
checkreg r1, 0x80008000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
checkreg r2, 0x80008000;
checkreg r3, 0x0;
R4 = 0;
R2 = R2 +|+ R4, R3 = R2 -|- R4 (S , ASR);
checkreg r2, 0xc000c000;
checkreg r3, 0xc000c000;
R2 = R2 +|+ R3, R3 = R2 -|- R3 (S , ASR);
checkreg r2, 0xc000c000;
checkreg r3, 0x0;
R4 = R2 +|+ R2, R5 = R2 -|- R2 (ASL);
checkreg r4, 0x0
checkreg r5, 0x0
R2 = R2 +|+ R2, R3 = R2 -|- R2 (S , ASL);
checkreg r2, 0x80008000;
checkreg r3, 0x0;
imm32 r0, 0x50004000;
imm32 r1, 0x40005000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
checkreg r2, 0x7fff7fff;
checkreg r3, 0x2000e000;
R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL);
checkreg r4, 0x20002000
checkreg r5, 0x2000e000
imm32 r0, 0x30001000;
imm32 r1, 0x10003000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
checkreg r2, 0x7fff7fff;
checkreg r3, 0x4000c000;
R4 = R0 +|+ R1, R5 = R0 -|- R1 (ASL);
checkreg r4, 0x80008000
checkreg r5, 0x4000c000
imm32 r0, 0x20001fff;
imm32 r1, 0x1fff2000;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S, ASL);
checkreg r2, 0x7ffe7ffe;
checkreg r3, 0x0002fffe;
pass
|
tactcomplabs/xbgas-binutils-gdb | 14,785 | sim/testsuite/bfin/se_lsetup_kill.S | //Original:/proj/frio/dv/testcases/seq/se_lsetup_kill/se_lsetup_kill.dsp
# mach: bfin
# sim: --environment operating
#include "test.h"
.include "testutils.inc"
start
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Include Files /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
include(std.inc)
include(selfcheck.inc)
include(symtable.inc)
include(mmrs.inc)
/////////////////////////////////////////////////////////////////////////////
///////////////////////// Defines /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
#ifndef USER_CODE_SPACE
#define USER_CODE_SPACE CODE_ADDR_1 //
#endif
#ifndef STACKSIZE
#define STACKSIZE 0x00000010
#endif
#ifndef ITABLE
#define ITABLE CODE_ADDR_2 //
#endif
/////////////////////////////////////////////////////////////////////////////
///////////////////////// RESET ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
RST_ISR :
// Initialize Dregs
INIT_R_REGS(0);
// Initialize Pregs
INIT_P_REGS(0);
// Initialize ILBM Registers
INIT_I_REGS(0);
INIT_M_REGS(0);
INIT_L_REGS(0);
INIT_B_REGS(0);
// Initialize the Address of the Checkreg data segment
// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
// Setup User Stack
LD32_LABEL(sp, USTACK);
USP = SP;
// Setup Kernel Stack
LD32_LABEL(sp, KSTACK);
// Setup Frame Pointer
FP = SP;
// Setup Event Vector Table
LD32(p0, EVT0);
LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
[ P0 ++ ] = R0;
LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
[ P0 ++ ] = R0;
LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
[ P0 ++ ] = R0;
LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
[ P0 ++ ] = R0;
[ P0 ++ ] = R0; // IVT4 not used
LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
[ P0 ++ ] = R0;
LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
[ P0 ++ ] = R0;
LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
[ P0 ++ ] = R0;
// Setup the EVT_OVERRIDE MMR
R0 = 0;
LD32(p0, EVT_OVERRIDE);
[ P0 ] = R0;
// Setup Interrupt Mask
R0 = -1;
LD32(p0, IMASK);
[ P0 ] = R0;
// Return to Supervisor Code
RAISE 15;
NOP;
LD32_LABEL(r0, USER_CODE);
RETI = R0;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EMU ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EMU_ISR :
RTE;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// NMI ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
NMI_ISR :
RTN;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// EXC ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
EXC_ISR :
RTX;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// HWE ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
HWE_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// TMR ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
TMR_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV7 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV7_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV8 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV8_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV9 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV9_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV10 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV10_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV11 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV11_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV12 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV12_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV13 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV13_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV14 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV14_ISR :
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// IGV15 ISR /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
IGV15_ISR :
P0 = 0x5 (Z);
P1 = 0xa (Z);
NOP;
NOP;
RTI;
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
.dw 0xFFFF
/////////////////////////////////////////////////////////////////////////////
///////////////////////// USER CODE /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
USER_CODE :
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (Kill Lsetup in WB)
/////////////////////////////////////////////////////////////////////////////
EXCPT 0x5;
LSETUP ( L0T , L0T ) LC0 = P0;
L0T:R0 += 5;
EXCPT 0x5;
LSETUP ( L1T , L1B ) LC0 = P0;
L1T:R0 += 5;
L1B:R1 += 4;
EXCPT 0x5;
LSETUP ( L2T , L2B ) LC0 = P0;
L2T:R0 += 5;
R1 += 4;
L2B:R2 += 3;
EXCPT 0x5;
LSETUP ( L3T , L3B ) LC0 = P0;
L3T:R0 += 5;
R1 += 4;
R2 += 3;
L3B:R3 += 2;
EXCPT 0x5;
LSETUP ( L4T , L4B ) LC0 = P0;
L4T:R0 += 5;
R1 += 4;
R2 += 3;
R3 += 2;
L4B:R4 += 1;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (Kill Lsetup in WB)
/////////////////////////////////////////////////////////////////////////////
EXCPT 0x5;
LSETUP ( M0T , M0T ) LC1 = P0;
M0T:R0 += 5;
EXCPT 0x5;
LSETUP ( M1T , M1B ) LC1 = P0;
M1T:R0 += 5;
M1B:R1 += 4;
EXCPT 0x5;
LSETUP ( M2T , M2B ) LC1 = P0;
M2T:R0 += 5;
R1 += 4;
M2B:R2 += 3;
EXCPT 0x5;
LSETUP ( M3T , M3B ) LC1 = P0;
M3T:R0 += 5;
R1 += 4;
R2 += 3;
M3B:R3 += 2;
EXCPT 0x5;
LSETUP ( M4T , M4B ) LC1 = P0;
M4T:R0 += 5;
R1 += 4;
R2 += 3;
R3 += 2;
M4B:R4 += 1;
/////////////////////////////////////////////////////////////////////////////
// Loop 0 (Kill during the last iteration at each pipe stage)
/////////////////////////////////////////////////////////////////////////////
LSETUP ( N0T , N0B ) LC0 = P1;
NOP;
N0T:R0 = LC0;
CC = R0 == 1;
IF !CC JUMP N0B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
N0B:R2 += 3;
LSETUP ( N1T , N1B ) LC0 = P1;
NOP;
N1T:R0 = LC0;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP N1B (BP);
EXCPT 0x5;
N1B:R2 += 3;
LSETUP ( N2T , N2B ) LC0 = P1;
NOP;
N2T:R0 = LC0;
CC = R0 == 1;
IF !CC JUMP N2B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
N2B:R2 += 3;
LSETUP ( N3T , N3B ) LC0 = P1;
NOP;
N3T:R0 = LC0;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP N3B (BP);
EXCPT 0x5;
R3 += 4;
N3B:R2 += 3;
LSETUP ( N4T , N4B ) LC0 = P1;
NOP;
N4T:R0 = LC0;
CC = R0 == 1;
IF !CC JUMP N4B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
N4B:R2 += 3;
LSETUP ( N5T , N5B ) LC0 = P1;
NOP;
N5T:R0 = LC0;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP N5B (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
N5B:R2 += 3;
LSETUP ( N6T , N6B ) LC0 = P1;
NOP;
N6T:R0 = LC0;
CC = R0 == 1;
IF !CC JUMP N6B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
N6B:R2 += 3;
LSETUP ( N7T , N7B ) LC0 = P1;
NOP;
N7T:R0 = LC0;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP N7B (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
N7B:R2 += 3;
LSETUP ( N8T , N8B ) LC0 = P1;
NOP;
N8T:R0 = LC0;
CC = R0 == 1;
IF !CC JUMP N8B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
N8B:R2 += 3;
LSETUP ( N9T , N9B ) LC0 = P1;
NOP;
N9T:R0 = LC0;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP N9B (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
N9B:R2 += 3;
LSETUP ( NAT , NAB ) LC0 = P1;
NOP;
NAT:
R0 = LC0;
CC = R0 == 1;
IF !CC JUMP NAB (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
NAB:
R2 += 3;
LSETUP ( NBT , NBB ) LC0 = P1;
NOP;
NBT:
R0 = LC0;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP NBB (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
NBB:
R2 += 3;
/////////////////////////////////////////////////////////////////////////////
// Loop 1 (Kill during the last iteration at each pipe stage)
/////////////////////////////////////////////////////////////////////////////
LSETUP ( O0T , O0B ) LC1 = P1;
NOP;
O0T:R0 = LC1;
CC = R0 == 1;
IF !CC JUMP O0B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
O0B:R2 += 3;
LSETUP ( O1T , O1B ) LC1 = P1;
NOP;
O1T:R0 = LC1;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP O1B (BP);
EXCPT 0x5;
O1B:R2 += 3;
LSETUP ( O2T , O2B ) LC1 = P1;
NOP;
O2T:R0 = LC1;
CC = R0 == 1;
IF !CC JUMP O2B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
O2B:R2 += 3;
LSETUP ( O3T , O3B ) LC1 = P1;
NOP;
O3T:R0 = LC1;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP O3B (BP);
EXCPT 0x5;
R3 += 4;
O3B:R2 += 3;
LSETUP ( O4T , O4B ) LC1 = P1;
NOP;
O4T:R0 = LC1;
CC = R0 == 1;
IF !CC JUMP O4B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
O4B:R2 += 3;
LSETUP ( O5T , O5B ) LC1 = P1;
NOP;
O5T:R0 = LC1;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP O5B (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
O5B:R2 += 3;
LSETUP ( O6T , O6B ) LC1 = P1;
NOP;
O6T:R0 = LC1;
CC = R0 == 1;
IF !CC JUMP O6B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
O6B:R2 += 3;
LSETUP ( O7T , O7B ) LC1 = P1;
NOP;
O7T:R0 = LC1;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP O7B (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
O7B:R2 += 3;
LSETUP ( O8T , O8B ) LC1 = P1;
NOP;
O8T:R0 = LC1;
CC = R0 == 1;
IF !CC JUMP O8B (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
O8B:R2 += 3;
LSETUP ( O9T , O9B ) LC1 = P1;
NOP;
O9T:R0 = LC1;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP O9B (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
O9B:R2 += 3;
LSETUP ( OAT , OAB ) LC1 = P1;
NOP;
OAT:
R0 = LC1;
CC = R0 == 1;
IF !CC JUMP OAB (BP);
R0 += 1;
R1 += 2;
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
OAB:
R2 += 3;
LSETUP ( OBT , OBB ) LC1 = P1;
NOP;
OBT:
R0 = LC1;
R0 += 1;
R1 += 2;
CC = R0 == 1;
IF !CC JUMP OBB (BP);
EXCPT 0x5;
R3 += 4;
R4 += 5;
R5 += 6;
R6 += 7;
R7 += 8;
OBB:
R2 += 3;
NOP;
NOP;
NOP;
dbg_pass; // Call Endtest Macro
/////////////////////////////////////////////////////////////////////////////
///////////////////////// DATA MEMRORY /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
.dd 0xdeadbeef;
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
.dd 0x02020202;
.dd 0x03030303;
.dd 0x04040404;
// Define Kernal Stack
.data
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
KSTACK :
.space (STACKSIZE);
USTACK :
/////////////////////////////////////////////////////////////////////////////
///////////////////////// END OF TEST /////////////////////////////
/////////////////////////////////////////////////////////////////////////////
|
tactcomplabs/xbgas-binutils-gdb | 4,520 | sim/testsuite/bfin/c_comp3op_dr_mix.s | //Original:/testcases/core/c_comp3op_dr_mix/c_comp3op_dr_mix.dsp
// Spec Reference: comp3op dregs mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x01234567;
imm32 r1, 0x89abcdef;
imm32 r2, 0x56789abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23456899;
imm32 r5, 0x78912345;
imm32 r6, 0x98765432;
imm32 r7, 0x12345678;
R0 = R0 + R0;
R1 = R0 - R1;
R2 = R0 & R2;
R3 = R0 | R3;
R4 = R0 & R4;
R5 = R0 & R5;
R6 = R0 | R6;
R7 = R0 & R7;
CHECKREG r0, 0x02468ACE;
CHECKREG r1, 0x789ABCDF;
CHECKREG r2, 0x02408A8C;
CHECKREG r3, 0xDEF69AFE;
CHECKREG r4, 0x02440888;
CHECKREG r5, 0x00000244;
CHECKREG r6, 0x9A76DEFE;
CHECKREG r7, 0x02040248;
imm32 r0, 0x01231567;
imm32 r1, 0x89ab1def;
imm32 r2, 0x56781abc;
imm32 r3, 0xdef01234;
imm32 r4, 0x23451899;
imm32 r5, 0x78911345;
imm32 r6, 0x98761432;
imm32 r7, 0x12341678;
R0 = R1 + R0;
R1 = R1 - R1;
R2 = R1 & R2;
R3 = R1 | R3;
R4 = R1 & R4;
R5 = R1 & R5;
R6 = R1 | R6;
R7 = R1 & R7;
CHECKREG r0, 0x8ACE3356;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0xDEF01234;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x98761432;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01234527;
imm32 r1, 0x89abcd2f;
imm32 r2, 0x56789a2c;
imm32 r3, 0xdef01224;
imm32 r4, 0x23456829;
imm32 r5, 0x78912325;
imm32 r6, 0x98765422;
imm32 r7, 0x12345628;
R0 = R2 + R0;
R1 = R2 - R1;
R2 = R2 & R2;
R3 = R2 | R3;
R4 = R2 & R4;
R5 = R2 & R5;
R6 = R2 | R6;
R7 = R2 & R7;
CHECKREG r0, 0x579BDF53;
CHECKREG r1, 0xCCCCCCFD;
CHECKREG r2, 0x56789A2C;
CHECKREG r3, 0xDEF89A2C;
CHECKREG r4, 0x02400828;
CHECKREG r5, 0x50100224;
CHECKREG r6, 0xDE7EDE2E;
CHECKREG r7, 0x12301228;
imm32 r0, 0x01234563;
imm32 r1, 0x89abcde3;
imm32 r2, 0x56789ab3;
imm32 r3, 0xdef01233;
imm32 r4, 0x23456893;
imm32 r5, 0x78912343;
imm32 r6, 0x98765433;
imm32 r7, 0x12345673;
R0 = R3 + R0;
R1 = R3 - R1;
R2 = R3 & R2;
R3 = R3 | R3;
R4 = R3 & R4;
R5 = R3 - R5;
R6 = R3 | R6;
R7 = R3 & R7;
CHECKREG r0, 0xE0135796;
CHECKREG r1, 0x55444450;
CHECKREG r2, 0x56701233;
CHECKREG r3, 0xDEF01233;
CHECKREG r4, 0x02400013;
CHECKREG r5, 0x665EEEF0;
CHECKREG r6, 0xDEF65633;
CHECKREG r7, 0x12301233;
imm32 r0, 0x41234567;
imm32 r1, 0x49abcdef;
imm32 r2, 0x46789abc;
imm32 r3, 0x4ef01234;
imm32 r4, 0x43456899;
imm32 r5, 0x48912345;
imm32 r6, 0x48765432;
imm32 r7, 0x42345678;
R0 = R4 + R0;
R1 = R4 - R1;
R2 = R4 & R2;
R3 = R4 | R3;
R4 = R4 & R4;
R5 = R4 & R5;
R6 = R4 | R6;
R7 = R4 & R7;
CHECKREG r0, 0x8468AE00;
CHECKREG r1, 0xF9999AAA;
CHECKREG r2, 0x42400898;
CHECKREG r3, 0x4FF57ABD;
CHECKREG r4, 0x43456899;
CHECKREG r5, 0x40012001;
CHECKREG r6, 0x4B777CBB;
CHECKREG r7, 0x42044018;
imm32 r0, 0x05234567;
imm32 r1, 0x85abcdef;
imm32 r2, 0x55789abc;
imm32 r3, 0xd5f01234;
imm32 r4, 0x25456899;
imm32 r5, 0x75912345;
imm32 r6, 0x95765432;
imm32 r7, 0x15345678;
R0 = R5 + R0;
R1 = R5 - R1;
R2 = R5 & R2;
R3 = R5 | R3;
R4 = R5 & R4;
R5 = R5 & R5;
R6 = R5 | R6;
R7 = R5 & R7;
CHECKREG r0, 0x7AB468AC;
CHECKREG r1, 0xEFE55556;
CHECKREG r2, 0x55100204;
CHECKREG r3, 0xF5F13375;
CHECKREG r4, 0x25012001;
CHECKREG r5, 0x75912345;
CHECKREG r6, 0xF5F77777;
CHECKREG r7, 0x15100240;
imm32 r0, 0x01264567;
imm32 r1, 0x89a6cdef;
imm32 r2, 0x56769abc;
imm32 r3, 0xdef61234;
imm32 r4, 0x23466899;
imm32 r5, 0x78962345;
imm32 r6, 0x98765432;
imm32 r7, 0x12365678;
R0 = R6 + R0;
R1 = R6 - R1;
R2 = R6 & R2;
R3 = R6 | R3;
R4 = R6 & R4;
R5 = R6 & R5;
R6 = R6 | R6;
R7 = R6 & R7;
CHECKREG r0, 0x999C9999;
CHECKREG r1, 0x0ECF8643;
CHECKREG r2, 0x10761030;
CHECKREG r3, 0xDEF65636;
CHECKREG r4, 0x00464010;
CHECKREG r5, 0x18160000;
CHECKREG r6, 0x98765432;
CHECKREG r7, 0x10365430;
imm32 r0, 0x01237567;
imm32 r1, 0x89ab7def;
imm32 r2, 0x56787abc;
imm32 r3, 0xdef07234;
imm32 r4, 0x23457899;
imm32 r5, 0x78917345;
imm32 r6, 0x98767432;
imm32 r7, 0x12345678;
R0 = R7 + R0;
R1 = R7 - R1;
R2 = R7 & R2;
R3 = R7 | R3;
R4 = R7 & R4;
R5 = R7 - R5;
R6 = R7 | R6;
R7 = R7 & R7;
CHECKREG r0, 0x1357CBDF;
CHECKREG r1, 0x8888D889;
CHECKREG r2, 0x12305238;
CHECKREG r3, 0xDEF4767C;
CHECKREG r4, 0x02045018;
CHECKREG r5, 0x99A2E333;
CHECKREG r6, 0x9A76767A;
CHECKREG r7, 0x12345678;
imm32 r0, 0x00000001;
imm32 r1, 0x00020003;
imm32 r2, 0x00040005;
imm32 r3, 0x00060007;
imm32 r4, 0x00080009;
imm32 r5, 0x000a000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x000e000f;
R0 = R1 + R2;
R1 = R3 - R2;
R2 = R4 & R3;
R3 = R5 | R4;
R4 = R6 & R7;
CHECKREG r0, 0x00060008;
CHECKREG r1, 0x00020002;
CHECKREG r2, 0x00000001;
CHECKREG r3, 0x000A000B;
CHECKREG r4, 0x000C000D;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000e000f;
pass
|
tactcomplabs/xbgas-binutils-gdb | 5,243 | sim/testsuite/bfin/c_dsp32shift_expexp_r.s | //Original:/testcases/core/c_dsp32shift_expexp_r/c_dsp32shift_expexp_r.dsp
// Spec Reference: dsp32shift expadj / expadj r
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x0800d001;
imm32 r1, 0x08000001;
imm32 r2, 0x0800d002;
imm32 r3, 0x0800d003;
imm32 r4, 0x0800d004;
imm32 r5, 0x0800d005;
imm32 r6, 0x0800d006;
imm32 r7, 0x0800d007;
R1.L = EXPADJ( R1 , R0.L ) (V);
R2.L = EXPADJ( R2 , R0.L ) (V);
R3.L = EXPADJ( R3 , R0.L ) (V);
R4.L = EXPADJ( R4 , R0.L ) (V);
R5.L = EXPADJ( R5 , R0.L ) (V);
R6.L = EXPADJ( R6 , R0.L ) (V);
R7.L = EXPADJ( R7 , R0.L ) (V);
R0.L = EXPADJ( R0 , R0.L ) (V);
CHECKREG r0, 0x0800D001;
CHECKREG r1, 0x0800D001;
CHECKREG r2, 0x0800D001;
CHECKREG r3, 0x0800D001;
CHECKREG r4, 0x0800D001;
CHECKREG r5, 0x0800D001;
CHECKREG r6, 0x0800D001;
CHECKREG r7, 0x0800D001;
imm32 r0, 0x0900d001;
imm32 r1, 0x09000001;
imm32 r2, 0x0900d002;
imm32 r3, 0x0900d003;
imm32 r4, 0x0900d004;
imm32 r5, 0x0900d005;
imm32 r6, 0x0900d006;
imm32 r7, 0x0900d007;
R0.L = EXPADJ( R0 , R1.L ) (V);
R1.L = EXPADJ( R1 , R1.L ) (V);
R2.L = EXPADJ( R2 , R1.L ) (V);
R3.L = EXPADJ( R3 , R1.L ) (V);
R4.L = EXPADJ( R4 , R1.L ) (V);
R5.L = EXPADJ( R5 , R1.L ) (V);
R6.L = EXPADJ( R6 , R1.L ) (V);
R7.L = EXPADJ( R7 , R1.L ) (V);
CHECKREG r0, 0x09000001;
CHECKREG r1, 0x09000001;
CHECKREG r2, 0x09000001;
CHECKREG r3, 0x09000001;
CHECKREG r4, 0x09000001;
CHECKREG r5, 0x09000001;
CHECKREG r6, 0x09000001;
CHECKREG r7, 0x09000001;
imm32 r0, 0x0a00e001;
imm32 r1, 0x0a00e001;
imm32 r2, 0x0a00000f;
imm32 r3, 0x0a00e003;
imm32 r4, 0x0a00e004;
imm32 r5, 0x0a00e005;
imm32 r6, 0x0a00e006;
imm32 r7, 0x0a00e007;
R0.L = EXPADJ( R0 , R2.L ) (V);
R1.L = EXPADJ( R1 , R2.L ) (V);
R3.L = EXPADJ( R3 , R2.L ) (V);
R4.L = EXPADJ( R4 , R2.L ) (V);
R5.L = EXPADJ( R5 , R2.L ) (V);
R6.L = EXPADJ( R6 , R2.L ) (V);
R7.L = EXPADJ( R7 , R2.L ) (V);
R2.L = EXPADJ( R2 , R2.L ) (V);
CHECKREG r0, 0x0A000002;
CHECKREG r1, 0x0A000002;
CHECKREG r2, 0x0A000003;
CHECKREG r3, 0x0A000002;
CHECKREG r4, 0x0A000002;
CHECKREG r5, 0x0A000002;
CHECKREG r6, 0x0A000002;
CHECKREG r7, 0x0A000002;
imm32 r0, 0x0b00f001;
imm32 r1, 0x0b00f001;
imm32 r2, 0x0b00f002;
imm32 r3, 0x0b000010;
imm32 r4, 0x0b00f004;
imm32 r5, 0x0b00f005;
imm32 r6, 0x0b00f006;
imm32 r7, 0x0b00f007;
R0.L = EXPADJ( R0 , R3.L ) (V);
R1.L = EXPADJ( R1 , R3.L ) (V);
R2.L = EXPADJ( R2 , R3.L ) (V);
R3.L = EXPADJ( R3 , R3.L ) (V);
R4.L = EXPADJ( R4 , R3.L ) (V);
R5.L = EXPADJ( R5 , R3.L ) (V);
R6.L = EXPADJ( R6 , R3.L ) (V);
R7.L = EXPADJ( R7 , R3.L ) (V);
CHECKREG r0, 0x0B000010;
CHECKREG r1, 0x0B000010;
CHECKREG r2, 0x0B000010;
CHECKREG r3, 0x0B000010;
CHECKREG r4, 0x0B000010;
CHECKREG r5, 0x0B000010;
CHECKREG r6, 0x0B000010;
CHECKREG r7, 0x0B000010;
imm32 r0, 0x0c0000c0;
imm32 r1, 0x0c0100c0;
imm32 r2, 0x0c0200c0;
imm32 r3, 0x0c0300c0;
imm32 r4, 0x0c0400c0;
imm32 r5, 0x0c0500c0;
imm32 r6, 0x0c0600c0;
imm32 r7, 0x0c0700c0;
R0.L = EXPADJ( R0 , R4.L ) (V);
R1.L = EXPADJ( R1 , R4.L ) (V);
R2.L = EXPADJ( R2 , R4.L ) (V);
R3.L = EXPADJ( R3 , R4.L ) (V);
R4.L = EXPADJ( R4 , R4.L ) (V);
R5.L = EXPADJ( R5 , R4.L ) (V);
R6.L = EXPADJ( R6 , R4.L ) (V);
R7.L = EXPADJ( R7 , R4.L ) (V);
CHECKREG r0, 0x0C0000C0;
CHECKREG r1, 0x0C0100C0;
CHECKREG r2, 0x0C0200C0;
CHECKREG r3, 0x0C0300C0;
CHECKREG r4, 0x0C0400C0;
CHECKREG r5, 0x0C0500C0;
CHECKREG r6, 0x0C0600C0;
CHECKREG r7, 0x0C0700C0;
imm32 r0, 0xa00100d0;
imm32 r1, 0x000100d1;
imm32 r2, 0xa00200d0;
imm32 r3, 0xa00300d0;
imm32 r4, 0xa00400d0;
imm32 r5, 0xa00500d0;
imm32 r6, 0xa00600d0;
imm32 r7, 0xa00700d0;
R0.L = EXPADJ( R0 , R5.L ) (V);
R1.L = EXPADJ( R1 , R5.L ) (V);
R2.L = EXPADJ( R2 , R5.L ) (V);
R3.L = EXPADJ( R3 , R5.L ) (V);
R4.L = EXPADJ( R4 , R5.L ) (V);
R5.L = EXPADJ( R5 , R5.L ) (V);
R6.L = EXPADJ( R6 , R5.L ) (V);
R7.L = EXPADJ( R7 , R5.L ) (V);
CHECKREG r0, 0xA00100D0;
CHECKREG r1, 0x000100D0;
CHECKREG r2, 0xA00200D0;
CHECKREG r3, 0xA00300D0;
CHECKREG r4, 0xA00400D0;
CHECKREG r5, 0xA00500D0;
CHECKREG r6, 0xA00600D0;
CHECKREG r7, 0xA00700D0;
imm32 r0, 0xb0010000;
imm32 r1, 0xb0010000;
imm32 r2, 0xb002000f;
imm32 r3, 0xb0030000;
imm32 r4, 0xb0040000;
imm32 r5, 0xb0050000;
imm32 r6, 0xb0060000;
imm32 r7, 0xb0070000;
R0.L = EXPADJ( R0 , R6.L ) (V);
R1.L = EXPADJ( R1 , R6.L ) (V);
R2.L = EXPADJ( R2 , R6.L ) (V);
R3.L = EXPADJ( R3 , R6.L ) (V);
R4.L = EXPADJ( R4 , R6.L ) (V);
R5.L = EXPADJ( R5 , R6.L ) (V);
R6.L = EXPADJ( R6 , R6.L ) (V);
R7.L = EXPADJ( R7 , R6.L ) (V);
CHECKREG r0, 0xB0010000;
CHECKREG r1, 0xB0010000;
CHECKREG r2, 0xB0020000;
CHECKREG r3, 0xB0030000;
CHECKREG r4, 0xB0040000;
CHECKREG r5, 0xB0050000;
CHECKREG r6, 0xB0060000;
CHECKREG r7, 0xB0070000;
imm32 r0, 0xd00102e7;
imm32 r1, 0xd00104e7;
imm32 r2, 0xd00206e7;
imm32 r3, 0xd00308e7;
imm32 r4, 0xd0040ae7;
imm32 r5, 0xd0050ce7;
imm32 r6, 0xd0060ee7;
imm32 r7, 0xd00707e7;
R0.L = EXPADJ( R0 , R7.L ) (V);
R1.L = EXPADJ( R1 , R7.L ) (V);
R2.L = EXPADJ( R2 , R7.L ) (V);
R3.L = EXPADJ( R3 , R7.L ) (V);
R4.L = EXPADJ( R4 , R7.L ) (V);
R5.L = EXPADJ( R5 , R7.L ) (V);
R6.L = EXPADJ( R6 , R7.L ) (V);
R7.L = EXPADJ( R7 , R7.L ) (V);
CHECKREG r0, 0xD0010001;
CHECKREG r1, 0xD0010001;
CHECKREG r2, 0xD0020001;
CHECKREG r3, 0xD0030001;
CHECKREG r4, 0xD0040001;
CHECKREG r5, 0xD0050001;
CHECKREG r6, 0xD0060001;
CHECKREG r7, 0xD0070001;
pass
|
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