repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/read_req_wrapper.v | 5,982 | module MODULE1(
input clk,
input rst,
input VAR18, VAR20
input [4:0] VAR21,
input [31:0] VAR27,
input VAR16,
input [4:0] VAR26,
input [31:0] VAR19,
input VAR31,
input [4:0] VAR5,
output [31:0] VAR14,
input VAR29, output [31:0] VAR2,
output VAR22
);
reg VAR9;
reg [4:0] VAR25;
reg [31:0] VAR6;
reg [4:0] VAR3;
wire [4:0] ... | bsd-2-clause |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1.v | 24,858 | module MODULE1 #
(
parameter VAR169= 0 )
(
VAR54,
VAR144,
VAR228,
VAR90,
VAR53,
VAR215,
VAR74,
VAR11,
VAR136,
VAR214,
VAR147,
VAR101,
VAR68,
VAR123,
VAR111,
VAR23,
VAR243,
VAR174,
VAR166,
VAR105,
VAR161,
VAR121,
VAR142,
VAR107,
VAR148,
VAR162
);
input [0:63] VAR54;
input VAR144;
output VAR228;
output [0:63] VAR90;
outp... | gpl-3.0 |
tinkercnc/linuxcnc-mirror-old | src/hal/drivers/pluto_step_firmware/main.v | 5,166 | module MODULE1(clk, VAR50, VAR16, VAR1, VAR49, VAR11, VAR56, VAR32,
VAR15, dout, din, VAR52, VAR10);
parameter VAR18=10;
parameter VAR6=11;
parameter VAR26=4;
input clk;
output VAR50, VAR16;
inout [7:0] VAR49;
input VAR11;
output VAR56;
input VAR32, VAR15, VAR1;
input [15:0] din;
reg VAR9;
reg[13:0] VAR37; output [13:0... | gpl-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_08_a/hdl/verilog/user_logic.v | 31,339 | /* VAR236 VAR117:
module MODULE1
(
VAR39,
VAR57,
VAR160,
VAR14,
VAR12,
VAR105,
VAR153,
VAR126,
VAR182,
VAR52,
VAR123,
VAR49,
VAR93,
VAR241,
VAR205,
VAR41,
VAR100,
VAR152,
VAR121,
VAR2,
VAR69,
VAR85,
VAR145,
VAR55,
VAR193,
VAR77,
VAR224,
VAR36,
VAR80,
VAR5,
VAR111,
VAR45,
VAR75,
VAR64,
VAR116,
VAR190,
VAR231,
VAR17,
VAR... | bsd-2-clause |
fpgasystems/Centaur | rtl/fthread/fthread.v | 10,384 | module MODULE1 #(parameter VAR39 = VAR69,
parameter VAR36 = 2,
parameter VAR47 = VAR34,
parameter VAR48 = VAR34,
parameter VAR37 = 1,
parameter VAR42 = 1) (
input wire clk,
input wire VAR62,
input wire VAR18,
input wire VAR61,
input wire [VAR60-1:0] VAR64,
output wire VAR10,
output wire VAR7,
output wire [67:0] VAR31,
... | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/FPU_Add_Subtract_Function.v | 12,621 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR126,
input wire VAR154,
input wire [VAR64-1:0] VAR11,
input wire [VAR64-1:0] VAR69,
input wire VAR62,
input wire [1:0] VAR151,
output wire VAR8,
output wire VAR67,
output wire ready,
output wire [VAR64-1:0] VAR149
);
wire VAR96,VAR105;
wire [VAR64-2:0] VAR7... | gpl-3.0 |
Madh93/scpu | modules/vga_adapter/vga_controller.v | 8,424 | module MODULE1( VAR17, VAR39, VAR26, VAR20,
VAR9, VAR5, VAR24,
VAR8, VAR38, VAR42,
VAR3, VAR37);
parameter VAR40 = 1;
parameter VAR31 = "VAR16";
parameter VAR25 = "320x240";
parameter VAR32 = "VAR35";
parameter VAR19 = 11'd480;
parameter VAR28 = 11'd493;
parameter VAR12 = 11'd494; parameter VAR18 = 11'd525;
parameter V... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/controller/mig_7series_v2_0_col_mach.v | 16,639 | module MODULE1 #
(
parameter VAR104 = 100,
parameter VAR48 = 3,
parameter VAR24 = "8",
parameter VAR34 = 12,
parameter VAR101 = 4,
parameter VAR30 = 8,
parameter VAR3 = 1,
parameter VAR13 = 0,
parameter VAR107 = 8,
parameter VAR11 = "VAR58",
parameter VAR109 = "VAR66",
parameter VAR85 = "VAR66",
parameter VAR74 = 31,
p... | bsd-2-clause |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/capture/signal_source.v | 4,303 | module MODULE1
parameter VAR1 = 1<<VAR25, parameter VAR11 = VAR1-1, parameter VAR4 = VAR25-2, parameter VAR26 = VAR4-1, parameter VAR22 = 1<<VAR4, parameter VAR21 = VAR22-1,
parameter VAR17 = 0,
parameter VAR16 = 0, parameter VAR14 = 3) (
input VAR19, input VAR10,
input VAR23, input [VAR7:0] VAR6, input [VAR2:0] VAR8, ... | lgpl-3.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkAXI4_Deburster_A.v | 49,644 | module MODULE1(VAR20,
VAR54,
VAR22,
VAR135,
VAR166,
VAR59,
VAR230,
VAR6,
VAR75,
VAR249,
VAR214,
VAR13,
VAR104,
VAR167,
VAR287,
VAR115,
VAR10,
VAR193,
VAR198,
VAR18,
VAR204,
VAR62,
VAR296,
VAR85,
VAR158,
VAR270,
VAR138,
VAR15,
VAR65,
VAR185,
VAR273,
VAR267,
VAR288,
VAR206,
VAR218,
VAR60,
VAR111,
VAR205,
VAR106,
VAR43,
V... | apache-2.0 |
josemonsalve2/cpeg324_calculator | vivado/hdl/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,432 | module MODULE1(VAR4, VAR6, VAR5, VAR3, VAR1, VAR2)
;
input VAR4;
input VAR6;
input [0:0]VAR5;
input [7:0]VAR3;
input [7:0]VAR1;
output [7:0]VAR2;
endmodule | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/generic_cntr_regs.v | 11,749 | module MODULE1
parameter VAR53 = 2,
parameter VAR1 = 0, parameter VAR49 = 5, parameter VAR8 = 8, parameter VAR26 = 0, parameter VAR58 = 1, parameter VAR35 = 8, parameter VAR61 = VAR40, parameter VAR46 = 0,
parameter VAR22 = VAR26 + VAR8, parameter VAR39 = VAR26 * VAR58, parameter VAR43 = VAR22 * VAR58 )
(
input VAR16,
... | apache-2.0 |
azonenberg/antikernel-ipcores | math/CRC32_Ethernet_x32.v | 18,321 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR2,
input wire[31:0] din,
output wire[31:0] VAR5);
reg[31:0] VAR3 = 0;
wire[31:0] VAR1 = ~VAR3;
assign VAR5 =
{
VAR1[24], VAR1[25], VAR1[26], VAR1[27],
VAR1[28], VAR1[29], VAR1[30], VAR1[31],
VAR1[16], VAR1[17], VAR1[18], VAR1[19],
VAR1[20], VAR1[21], VAR1[... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v | 182,347 | module MODULE1 #(parameter VAR9(VAR54)
,VAR50 =VAR1(VAR54)
,VAR2 = 1'b0
,VAR53 = 1'b0
,VAR33 = 1'b0)
(input VAR7
, input VAR44
, input VAR35
, input [VAR54-1:0] VAR61
, output logic [VAR54-1:0] VAR41
, output logic [VAR54-1:0] VAR62
, output VAR31 , output logic [VAR50-1:0] VAR36 , input VAR21 );
logic [VAR50-1:0] VAR1... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v | 2,987 | module MODULE1 #( parameter VAR40(VAR13 )
, parameter VAR40(VAR2 )
, parameter VAR23 = 0
)
( input VAR36
, input VAR35
, input VAR5
, output VAR7
, input [VAR13-1:0] VAR45
, output VAR31
, output [VAR13-1:0] VAR28
, input VAR1
);
wire VAR4 = VAR1;
wire VAR11;
assign VAR31 = VAR11;
wire VAR27;
logic VAR26;
if (VAR23)
be... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_2.behavioral.pp.v | 2,914 | module MODULE1( VAR5, VAR3, VAR27, VAR12, VAR16, VAR18 );
input VAR3, VAR5, VAR27;
inout VAR16, VAR18;
output VAR12;
reg VAR23;
VAR2 VAR15(.VAR5(VAR5),.VAR3(VAR3),.VAR27(VAR27),.VAR12(VAR12),.VAR16(VAR16),.VAR18(VAR18),.VAR23(VAR23));
VAR2 VAR28(.VAR5(VAR5),.VAR3(VAR3),.VAR27(VAR27),.VAR12(VAR12),.VAR16(VAR16),.VAR18(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.behavioral.pp.v | 2,044 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR1 ,
VAR2 ,
VAR11 ,
VAR3,
VAR16,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
input VAR11 ;
input VAR3;
input VAR16;
input VAR7 ;
input VAR4 ;
wire VAR15 ;
wire VAR6 ;
wire VAR14;
and VAR8 (VAR15 , VAR9, VAR1 );
nor VAR13 (VAR6 , VAR15, VAR2, VAR11 );
VAR17 VAR12 ... | apache-2.0 |
jmahler/mips-cpu | cla_adder_4bit.v | 1,112 | module MODULE1(
input wire [3:0] VAR13,
input wire [3:0] VAR9,
input wire VAR3,
output wire [3:0] VAR12,
output wire VAR5);
wire [4:0] VAR11;
wire [3:0] VAR4, VAR2;
assign VAR11[0] = VAR3;
assign VAR5 = VAR11[4];
VAR1 VAR10(.VAR13(VAR13[0]), .VAR9(VAR9[0]), .VAR11(VAR11[0]),
.VAR4(VAR4[0]), .VAR2(VAR2[0]), .VAR12(VAR12... | gpl-3.0 |
qmn/riscv-invicta | hardware/src/memory_system.v | 5,775 | module MODULE1 (
input clk,
input reset,
output VAR77,
input VAR70,
input [31:0] VAR4,
input VAR21,
input [31:0] VAR45,
input VAR27,
output VAR18,
input [31:0] VAR73,
input [31:0] VAR80,
input [3:0] VAR35,
input VAR50,
input VAR64,
output VAR84,
output [31:0] VAR5
);
localparam VAR62 = 2'd0;
localparam VAR54 = 2'd1;
lo... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.behavioral.v | 1,547 | module MODULE1 (
VAR3 ,
VAR9,
VAR6,
VAR10,
VAR5
);
output VAR3 ;
input VAR9;
input VAR6;
input VAR10;
input VAR5;
supply1 VAR11;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR12 ;
wire VAR1;
and VAR2 (VAR12 , VAR9, VAR6 );
or VAR13 (VAR1, VAR12, VAR5, VAR10);
buf VAR14 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.pp.blackbox.v | 1,226 | module MODULE1 (
VAR3,
VAR2,
VAR4 ,
VAR1
);
input VAR3;
input VAR2;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb.blackbox.v | 1,338 | module MODULE1 (
VAR7 ,
VAR2,
VAR3,
VAR9 ,
VAR1
);
output VAR7 ;
input VAR2;
input VAR3;
input VAR9 ;
input VAR1 ;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.functional.pp.v | 2,471 | module MODULE1 (
VAR19 ,
VAR13 ,
VAR15 ,
VAR9 ,
VAR20 ,
VAR1,
VAR6 ,
VAR3 ,
VAR14 ,
VAR16
);
output VAR19 ;
input VAR13 ;
input VAR15 ;
input VAR9 ;
input VAR20 ;
input VAR1;
input VAR6 ;
input VAR3 ;
input VAR14 ;
input VAR16 ;
wire VAR8 ;
wire VAR21 ;
wire VAR7 ;
wire VAR18;
not VAR23 (VAR21 , VAR1 );
VAR11 VAR2 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a_2.v | 2,348 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR7 ,
VAR8 ,
VAR9 ,
VAR5,
VAR11,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR11;
input VAR3 ;
input VAR1 ;
VAR10 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.behavioral.pp.v | 2,199 | module MODULE1 (
VAR13 ,
VAR17 ,
VAR16 ,
VAR14 ,
VAR6 ,
VAR15 ,
VAR12,
VAR9,
VAR5 ,
VAR4
);
output VAR13 ;
input VAR17 ;
input VAR16 ;
input VAR14 ;
input VAR6 ;
input VAR15 ;
input VAR12;
input VAR9;
input VAR5 ;
input VAR4 ;
wire VAR7 ;
wire VAR1 ;
wire VAR18 ;
wire VAR11;
or VAR20 (VAR7 , VAR6, VAR14 );
or VAR19 (VA... | apache-2.0 |
tommythorn/yari | Icarus/rtl/toplevel.v | 10,262 | module MODULE1( input wire VAR61 ,output wire VAR59 ,input wire VAR57 ,input wire VAR51
,output wire [7:0] VAR16 ,output wire [7:0] VAR101 ,output wire [7:0] VAR112 ,output wire VAR36 ,output wire VAR97 ,output wire VAR82 ,output wire VAR18 ,output wire VAR74 ,output wire VAR33 ,output wire VAR19
,output VAR96 ,inout V... | gpl-2.0 |
hakehuang/pycpld | ips/ip/i2c_master/I2C_MASTER.v | 2,775 | module MODULE1(clk,VAR12,VAR13,VAR7,VAR9,VAR16,VAR18
);
input clk;
input VAR12;
input VAR9;
input VAR16;
reg VAR1,VAR14;
output VAR7;
output VAR18;
inout VAR13;
reg VAR8;
reg VAR18;
reg[7:0] VAR6;
reg[7:0] VAR4;
wire[7:0] VAR2;
reg[7:0] VAR11;
wire ack;
reg[7:0] VAR15[31:0];
reg[7:0] VAR5[31:0];
always @(posedge clk or... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a_2.v | 2,411 | module MODULE2 (
VAR6 ,
VAR11 ,
VAR8 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR3,
VAR10,
VAR12 ,
VAR1
);
output VAR6 ;
input VAR11 ;
input VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR3;
input VAR10;
input VAR12 ;
input VAR1 ;
VAR5 VAR2 (
.VAR6(VAR6),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.v | 2,458 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR8 ,
VAR10 ,
VAR6 ,
VAR2 ,
VAR9,
VAR11,
VAR1 ,
VAR5
);
output VAR3 ;
input VAR12 ;
input VAR8 ;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR9;
input VAR11;
input VAR1 ;
input VAR5 ;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp.behavioral.v | 2,597 | module MODULE1 (
VAR8 ,
VAR17,
VAR25 ,
VAR16 ,
VAR2,
VAR28
);
output VAR8 ;
input VAR17;
input VAR25 ;
input VAR16 ;
input VAR2;
input VAR28;
supply1 VAR27;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR21 ;
wire VAR11 ;
reg VAR24 ;
wire VAR23 ;
wire VAR22 ;
wire VAR29;
wire VAR14;
wire VAR3;
wire VAR20 ;
wire VAR5 ;
wire VA... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97_graycounter.v | 1,184 | module MODULE1
(output reg [VAR4-1:0] VAR6,
input wire VAR1, input wire VAR5,
input wire VAR3);
reg [VAR4-1:0] VAR2;
always @ (posedge VAR3)
if (VAR5) begin
VAR2 <= {VAR4{1'VAR7 0}} + 1; VAR6 <= {VAR4{1'VAR7 0}}; end
else if (VAR1) begin
VAR2 <= VAR2 + 1;
VAR6 <= {VAR2[VAR4-1],
VAR2[VAR4-2:0] ^ VAR2[VAR4-1:1]};
end
end... | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/intra/ram_lcu_column_32x64.v | 4,128 | module MODULE1 (
VAR17 ,
VAR13 ,
VAR16 ,
VAR9 ,
VAR1 ,
VAR3 ,
VAR14 ,
VAR18 ,
VAR11 ,
VAR12 ,
VAR5 ,
VAR10 ,
VAR8 ,
VAR19
);
parameter VAR4=32;
parameter VAR2=6;
input VAR17; input VAR13; input VAR16; input VAR9; input [VAR2-1:0] VAR1; input [VAR4-1:0] VAR14; output [VAR4-1:0] VAR3;
input VAR18; input VAR11; input VAR1... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/nf2/reference_core/src/nf2_reg_grp.v | 10,643 | module MODULE1 (
input VAR30, output reg VAR10,
input VAR23,
input [VAR64-1:0] VAR47,
input [VAR27-1:0] VAR39,
output reg [VAR27-1:0] VAR53,
output reg VAR43,
output wire VAR15,
output reg VAR61,
output reg VAR9,
output reg [VAR11-1:0] VAR48,
output reg [VAR27-1:0] VAR49,
input VAR36,
input [VAR27-1:0] VAR50,
output re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.blackbox.v | 1,252 | module MODULE1 (
VAR3,
VAR2,
VAR4,
VAR1
);
output VAR3;
input VAR2;
input VAR4;
input VAR1;
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/tlu_prencoder16.v | 2,927 | module MODULE1 (din, dout);
input [14:0] din ;
output [3:0] dout ;
wire [14:0] VAR1 ;
assign VAR1[14] = din[14] ;
assign VAR1[13] = din[13] & ~din[14] ;
assign VAR1[12] = din[12] & ~(|din[14:13]) ;
assign VAR1[11] = din[11] & ~(|din[14:12]) ;
assign VAR1[10] = din[10] & ~(|din[14:11]) ;
assign VAR1[9] = din[9] & ~(|din... | gpl-2.0 |
stevenmburns/chisel-edit-distance | sw4d/top_diff.v | 5,516 | module MODULE2(
input [15:0] VAR17,
input [15:0] VAR2,
output [15:0] VAR5
);
assign VAR5 = ( VAR2 > VAR17) ? VAR2 : VAR17;
endmodule
module MODULE3(
input [7:0] VAR17,
input [7:0] VAR2,
output [7:0] VAR5
);
assign VAR5 = ( VAR2 > VAR17) ? VAR2 : VAR17;
endmodule
module MODULE6(
input [3:0] VAR17,
input [3:0] VAR2,
outp... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_list.v | 7,579 | module MODULE1
parameter
VAR11 = 3, VAR3 = 8,
VAR10 = "VAR1", VAR8 = "VAR4" )
(
VAR9,
VAR12,
VAR2,
VAR5,
VAR14,
VAR13,
VAR19,
VAR21,
VAR16
);
input VAR9;
input VAR12;
input VAR5;
output VAR2;
output [VAR11-1:0] VAR14;
output [VAR3-1:0] VAR13;
output VAR21;
input VAR19;
input [VAR11-1:0] VAR16;
reg VAR2;
wire VAR5;
reg ... | gpl-3.0 |
PyLCARS/PythonUberHDL | PYNQLearn/FabricOnly/top.v | 1,650 | module MODULE1 (
clk,
VAR12
);
input clk;
output [3:0] VAR12;
wire [3:0] VAR12;
wire [7:0] VAR2;
reg [7:0] VAR11 = 0;
wire [7:0] VAR4;
reg [7:0] VAR13 = 0;
wire [7:0] VAR17;
reg [7:0] VAR5 = 0;
wire [7:0] VAR15;
reg [7:0] VAR6 = 0;
reg VAR9 [0:4-1];
VAR10 begin: VAR14
integer VAR3;
for(VAR3=0; VAR3<4; VAR3=VAR3+1) begi... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxtp/sky130_fd_sc_hs__dfxtp_4.v | 2,001 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR7 ,
VAR5,
VAR4
);
input VAR1 ;
input VAR2 ;
output VAR7 ;
input VAR5;
input VAR4;
VAR3 VAR6 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR2 ,
VAR7
);
input VAR1;
input VAR2 ;
output VAR7 ;
supply1 VAR5;
supply0 VAR4;
VAR3 VAR6 ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/phy/phy_read.v | 10,010 | module MODULE1 #
(
parameter VAR30 = 100, parameter VAR36 = 2, parameter VAR17 = 3333, parameter VAR20 = 300.0, parameter VAR49 = 8, parameter VAR23 = 64, parameter VAR47 = 8, parameter VAR54 = "VAR46", parameter VAR14 = 4, parameter VAR44 = 4, parameter VAR33 = 0, parameter VAR9 = 0, parameter VAR40 = 32'h03020100, pa... | lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_reset.v | 22,134 | module MODULE1 #
(
parameter VAR78 = "VAR16", parameter VAR61 = "VAR41",
parameter VAR79 = "VAR1", parameter VAR43 = "VAR71", parameter VAR2 = "VAR16", parameter VAR31 = 1, parameter VAR74 = 6'd63, parameter VAR28 = 1
)
(
input VAR76,
input VAR50,
input VAR58,
input VAR20,
input [VAR31-1:0] VAR37,
input [VAR31-1:0] VAR... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axis_oscilloscope_v1_0/src/axis_oscilloscope.v | 2,952 | module MODULE1 #
(
parameter integer VAR12 = 32,
parameter integer VAR13 = 12
)
(
input wire VAR17,
input wire VAR4,
input wire VAR1,
input wire VAR19,
input wire [VAR13-1:0] VAR11,
input wire [VAR13-1:0] VAR16,
output wire [VAR13:0] VAR18,
output wire VAR21,
input wire [VAR12-1:0] VAR2,
input wire VAR3,
output wire [V... | gpl-3.0 |
mammenx/pegasus | wxp/dgn/rtl/l2/mac/peg_l2_mac_tx.v | 3,435 | module MODULE1 #(
parameter VAR15 = 8,
parameter VAR9 = 16
)
(
input clk,
input VAR2,
input VAR11,
VAR12(VAR10,,VAR15)
);
VAR6 #(
.VAR15(VAR15),
.VAR9(VAR9)
)
VAR7
(
.clk (clk),
.VAR2 (VAR2),
.VAR1 (),
.VAR13 (),
.VAR14 (),
.VAR4 (),
.VAR8 (),
.VAR5 (),
.VAR3 (),
.VAR11 (VAR11),
);
endmodule | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_spigpioport_2.v | 5,329 | module MODULE1(
input VAR3,
input reset,
input VAR79,
output VAR45,
input VAR4,
input VAR59,
output VAR22,
input VAR23,
input VAR38,
output VAR30,
input VAR31,
input VAR70,
output VAR68,
input VAR54,
input VAR29,
input VAR64,
input VAR56,
output VAR42,
output VAR74,
output VAR77,
output VAR72,
output VAR5,
input VAR62,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.functional.v | 1,511 | module MODULE1 (
VAR11 ,
VAR7,
VAR8,
VAR6,
VAR1
);
output VAR11 ;
input VAR7;
input VAR8;
input VAR6;
input VAR1;
wire VAR3 ;
wire VAR4 ;
wire VAR9;
or VAR12 (VAR3 , VAR8, VAR7 );
or VAR10 (VAR4 , VAR1, VAR6 );
and VAR2 (VAR9, VAR3, VAR4);
buf VAR5 (VAR11 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.symbol.v | 1,386 | module MODULE1 (
input VAR8,
input VAR9,
input VAR6 ,
input VAR7 ,
output VAR1
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/cache_d_bb.v | 8,645 | module MODULE1 (
VAR1,
VAR10,
VAR7,
VAR4,
VAR3,
VAR6,
VAR9,
VAR2,
VAR5,
VAR8);
input [11:0] VAR1;
input [10:0] VAR10;
input VAR7;
input VAR4;
input [7:0] VAR3;
input [15:0] VAR6;
input VAR9;
input VAR2;
output [7:0] VAR5;
output [15:0] VAR8;
tri1 VAR7;
tri0 VAR9;
tri0 VAR2;
endmodule | gpl-3.0 |
ssabogal/nocturnal | noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_auto_pc_0/synth/sys_auto_pc_0.v | 13,142 | module MODULE1 (
VAR27,
VAR5,
VAR51,
VAR39,
VAR2,
VAR49,
VAR71,
VAR48,
VAR54,
VAR14,
VAR6,
VAR89,
VAR38,
VAR86,
VAR73,
VAR43,
VAR55,
VAR63,
VAR41,
VAR79,
VAR15,
VAR52,
VAR9,
VAR77,
VAR56,
VAR7,
VAR84,
VAR24,
VAR20,
VAR34,
VAR96,
VAR112,
VAR35,
VAR110,
VAR81,
VAR66,
VAR18,
VAR67,
VAR107,
VAR80,
VAR85,
VAR13,
VAR65,
VAR2... | mit |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_top.v | 52,187 | module MODULE1 #
(
parameter VAR134 = "VAR180",
parameter integer VAR39 = 0,
parameter integer VAR4 = 1,
parameter integer VAR115 = 0,
parameter integer VAR24 = 32,
parameter integer VAR7 = 32,
parameter integer VAR5 = 64,
parameter integer VAR57 = 1,
parameter integer VAR156 = 1,
parameter integer VAR148 = 0,
paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp.pp.blackbox.v | 1,455 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR9 ,
VAR8 ,
VAR11 ,
VAR1 ,
VAR3 ,
VAR5,
VAR7,
VAR6 ,
VAR10
);
output VAR2 ;
output VAR4 ;
input VAR9 ;
input VAR8 ;
input VAR11 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR7;
input VAR6 ;
input VAR10 ;
endmodule | apache-2.0 |
grindars/bfcore | DRAM.v | 1,276 | module MODULE1 (
VAR5,
VAR10,
VAR11,
VAR1,
VAR3,
VAR8
);
parameter VAR9 = 11;
parameter VAR4 = 8;
parameter VAR6 = (1 << VAR9);
input VAR5;
input [VAR9 - 1:0] VAR10;
input [VAR4 - 1:0] VAR11;
output reg [VAR4 - 1:0] VAR1;
input VAR3;
input VAR8;
reg [7:0] VAR7 [0:VAR6 - 1];
always @ (posedge VAR5)
if(VAR3)
begin
if(VAR... | gpl-3.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodR2R_v1_0/src/PmodR2R.v | 9,715 | module MODULE1
(VAR59,
VAR121,
VAR39,
VAR30,
VAR152,
VAR71,
VAR158,
VAR139,
VAR113,
VAR120,
VAR25,
VAR109,
VAR43,
VAR44,
VAR125,
VAR49,
VAR153,
VAR37,
VAR163,
VAR94,
VAR52,
VAR67,
VAR22,
VAR81,
VAR110,
VAR132,
VAR140,
VAR2,
VAR7,
VAR15,
VAR69,
VAR128,
VAR20,
VAR6,
VAR100,
VAR17,
VAR13,
VAR136,
VAR129,
VAR34,
VAR86,
VAR... | bsd-3-clause |
Jam-G/MIPS | ID.v | 10,223 | module MODULE2(
input clk,
input [5:0] VAR5,
input [4:0] VAR41,
input [4:0] VAR28,
input [4:0] VAR49,
input [4:0] VAR43,
input [5:0] VAR33,
input [3:0] VAR46,
input [3:0] VAR27,
input [3:0] VAR31,
input [31:0] VAR8,
output [31:0] VAR47,
output [31:0] VAR1,
output [31:0] VAR30,
output [2:0] VAR29,
output VAR17,
output V... | lgpl-3.0 |
golfit/QcmMasterController | stateEncoder.v | 8,879 | module MODULE1(clk, state, enable, out);
parameter VAR2=4'b0111; parameter VAR4=3'b110;
parameter VAR10=2'b11; parameter VAR9=2'b10;
input clk; input [VAR2-1:0] state; reg [VAR2-1:0] VAR11;
input enable;
output out; reg VAR6;
reg [4:0] VAR12; reg VAR1, VAR7, VAR8, VAR3; reg [3:0] VAR5; | mit |
ueliem/literate-broccoli | fpga_top.v | 3,084 | module MODULE1(
input clk,
input [VAR20*VAR25*VAR14*12-1:0] VAR1,
input [(VAR20-1)*(VAR25-1)*(VAR14*VAR14*12)-1:0] VAR38,
input [VAR25*VAR20*VAR10-1:0] VAR9,
input [VAR20*2*VAR14-1:0] VAR35,
input [VAR20*2*VAR14-1:0] VAR19,
input [VAR25*2*VAR14-1:0] VAR17,
input [VAR25*2*VAR14-1:0] VAR24,
inout [VAR20-1:0] VAR13, VAR41... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv.symbol.v | 1,246 | module MODULE1 (
input VAR3,
output VAR6
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.blackbox.v | 1,368 | module MODULE1 (
VAR8 ,
VAR2,
VAR6,
VAR7,
VAR3
);
output VAR8 ;
input VAR2;
input VAR6;
input VAR7;
input VAR3;
supply1 VAR9;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ptracton/Picoblaze | PicoBlaze_GPIO_Example/PicoBlaze_GPIO_Example.srcs/sources_1/imports/PicoBlaze_GPIO_Example/basic.v | 3,497 | module MODULE1 (
VAR3, VAR4,
VAR21, VAR18
) ;
input VAR21;
input VAR18;
inout [7:0] VAR3;
inout [7:0] VAR4;
wire [7:0] VAR13;
wire [7:0] VAR4;
wire [7:0] VAR24;
wire [7:0] VAR2;
wire [7:0] VAR23;
wire [7:0] VAR16;
wire VAR9; wire VAR6;
VAR11 VAR20(
.VAR9 (VAR9),
.VAR6 (VAR6),
.VAR21 (VAR21),
.VAR18 (VAR18));
VAR10 VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp.behavioral.pp.v | 2,334 | module MODULE1 (
VAR1 ,
VAR6,
VAR9 ,
VAR3 ,
VAR14 ,
VAR4 ,
VAR12 ,
VAR5
);
output VAR1 ;
input VAR6;
input VAR9 ;
input VAR3 ;
input VAR14 ;
input VAR4 ;
input VAR12 ;
input VAR5 ;
wire VAR21 ;
reg VAR22 ;
wire VAR17 ;
wire VAR20 ;
wire VAR18 ;
wire VAR16;
wire VAR7 ;
wire VAR10 ;
wire VAR11 ;
wire VAR2 ;
not VAR13 (VA... | apache-2.0 |
os-cillation/easyfpga-soc | easy_cores/gpio/gpio_top.v | 30,388 | module MODULE1(
VAR6, VAR28, VAR37, VAR50, VAR51, VAR92, VAR48, VAR61,
VAR41, VAR11, VAR64, VAR30,
VAR63,
VAR33, VAR66, VAR88
, VAR91
);
parameter VAR80 = 32;
parameter VAR46 = VAR2+1; parameter VAR77 = VAR16; input VAR6; input VAR28; input VAR37; input [VAR46-1:0] VAR50; input [VAR80-1:0] VAR51; input [3:0] VAR92; inp... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syn/src/noisegen.v | 1,632 | module MODULE1 (VAR3, VAR1,VAR2);
output [1:0] VAR1;
input [7:0] VAR3;
input [7:0] VAR2;
reg [1:0] VAR1;
always@(VAR3)
begin
if (VAR3 < VAR2)
VAR1 = VAR3[1:0];
end
else
VAR1 = 2'b00;
end
endmodule | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_freeze.v | 8,294 | module MODULE1(
clk, rst,
VAR4, VAR5, VAR20, VAR8, VAR14,
VAR15, VAR16, VAR10,
VAR12,
VAR2, VAR3, VAR17, VAR1, VAR11,
VAR19, VAR18
);
input clk;
input rst;
input [VAR6-1:0] VAR4;
input VAR5;
input VAR20;
input VAR8;
input VAR14;
input VAR15;
input VAR12;
input VAR16;
input VAR10;
output VAR2;
output VAR3;
output VAR17;... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_controlFlagsIn.v | 2,193 | module MODULE1 (
address,
VAR6,
clk,
VAR3,
VAR7,
VAR9,
VAR5,
VAR1
)
;
output [ 1: 0] VAR5;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR3;
input VAR7;
input [ 31: 0] VAR9;
wire VAR8;
reg [ 1: 0] VAR4;
wire [ 1: 0] VAR5;
wire [ 1: 0] VAR2;
wire [ 31: 0] VAR1;
assign VAR8 = 1;
assign VAR2 ... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/cnet_dma_bus_master.v | 19,592 | module MODULE1
(
output reg [15:0] VAR93, input VAR15, input [3:0] VAR35,
output [31:0] VAR63, input VAR85,
output reg [15:0] VAR2,
output VAR32, output VAR71, output reg VAR79, output reg VAR92,
input VAR89,
input [31:0] VAR3, input VAR26, output VAR36,
output reg [1:0] VAR18,
output reg [3:0] VAR80,
input [1:0] VAR5,... | mit |
alexforencich/verilog-wishbone | rtl/wb_async_reg.v | 7,789 | module MODULE1 #
(
parameter VAR55 = 32, parameter VAR36 = 32, parameter VAR19 = (VAR55/8) )
(
input wire VAR29,
input wire VAR46,
input wire [VAR36-1:0] VAR24, input wire [VAR55-1:0] VAR11, output wire [VAR55-1:0] VAR52, input wire VAR2, input wire [VAR19-1:0] VAR20, input wire VAR37, output wire VAR18, output wire VA... | mit |
olajep/oh | src/adi/hdl/library/common/ad_csc_RGB2CrYCb.v | 3,510 | module MODULE1 #(
parameter VAR9 = 16) (
input clk,
input [VAR6:0] VAR15,
input [23:0] VAR11,
output [VAR6:0] VAR8,
output [23:0] VAR5);
localparam VAR6 = VAR9 - 1;
VAR7 #(.VAR9(VAR9)) VAR4 (
.clk (clk),
.sync (VAR15),
.VAR1 (VAR11),
.VAR2 (17'h00707),
.VAR13 (17'h105e2),
.VAR10 (17'h10124),
.VAR14 (25'h0080000),
.VAR1... | mit |
mrehkopf/sd2snes | verilog/sd2snes_sa1/address.v | 4,318 | module MODULE1(
input VAR11,
input [15:0] VAR10, input [2:0] VAR14, input [23:0] VAR33, input [7:0] VAR12, input VAR1, output [23:0] VAR22, output VAR24, output VAR25, output VAR13, output VAR23, input [23:0] VAR6,
input [23:0] VAR3,
output VAR5,
input [4:0] VAR28,
input VAR34,
input [11:0] VAR2,
input [3:0] VAR30,
out... | gpl-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_jtag_uart_0.v | 16,670 | module MODULE5 (
clk,
VAR19,
VAR31,
VAR16,
VAR55,
VAR15,
VAR33
)
;
output VAR16;
output [ 7: 0] VAR55;
output VAR15;
output [ 5: 0] VAR33;
input clk;
input [ 7: 0] VAR19;
input VAR31;
wire VAR16;
wire [ 7: 0] VAR55;
wire VAR15;
wire [ 5: 0] VAR33;
always @(posedge clk)
begin
if (VAR31)
("%VAR1", VAR19);
end
assign VAR3... | gpl-2.0 |
jotego/jt12 | hdl/adpcm/jt10_cen_burst.v | 1,640 | module MODULE1 #(parameter VAR2=3'd6, VAR4=3)(
input VAR10,
input clk,
input VAR1, input VAR3,
input VAR9,
output VAR11
);
reg [VAR4-1:0] VAR7;
reg VAR8;
reg VAR6;
always @(posedge clk or negedge VAR10)
if( !VAR10 ) begin
VAR7 <= {VAR4{1'b1}};
VAR6 <= 1'b0;
end else if(VAR1) begin
VAR8 <= VAR3;
if( VAR3 && VAR9 ) begin... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.functional.v | 1,752 | module MODULE1 (
VAR2 ,
VAR5,
VAR7 ,
VAR9,
VAR10
);
output VAR2 ;
input VAR5;
input VAR7 ;
input VAR9;
input VAR10;
wire VAR3 ;
wire VAR12;
VAR6 VAR8 (VAR12, VAR7, VAR9, VAR10 );
VAR11 VAR13 VAR1 (VAR3 , VAR12, VAR5 );
buf VAR4 (VAR2 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf_1.v | 2,034 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR4,
VAR1,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR7 ;
input VAR3 ;
VAR6 VAR8 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
supply1 VAR4;
supply0 VAR1;... | apache-2.0 |
litex-hub/pythondata-cpu-lm32 | pythondata_cpu_lm32/verilog/rtl/lm32_debug.v | 12,303 | module MODULE1 (
VAR53,
VAR49,
VAR35,
VAR59,
VAR24,
VAR2,
VAR61,
VAR21,
VAR14,
VAR46,
VAR45,
VAR6,
VAR5,
VAR25,
VAR18,
VAR36,
VAR41,
VAR12,
VAR50,
VAR19,
VAR48,
VAR38
);
parameter VAR1 = 0; parameter VAR42 = 0;
input VAR53; input VAR49;
input [VAR44] VAR35; input VAR59; input VAR24; input [VAR3] VAR2; input VAR61; inpu... | epl-1.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ip/mult_gen_0/mult_gen_0_stub.v | 1,247 | module MODULE1(VAR3, VAR2, VAR1)
;
input [32:0]VAR3;
input [13:0]VAR2;
output [53:0]VAR1;
endmodule | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/packet_dispatcher36_x4.v | 12,000 | module MODULE1
parameter VAR56 = 0
)
(
input clk, input rst, input VAR25,
input VAR92, input [7:0] VAR81, input [31:0] VAR83,
input [35:0] VAR54, input VAR79, output VAR31,
output [35:0] VAR66, output VAR2, input VAR95,
output [35:0] VAR57, output VAR3, input VAR77,
output [35:0] VAR17, output VAR70, input VAR5,
output... | gpl-2.0 |
Ribeiro/sd2snes | verilog/sd2snes/upd77c25.v | 18,652 | module MODULE1(
input [7:0] VAR43,
output [7:0] VAR40,
input VAR21,
input enable,
input VAR59,
input VAR22,
input VAR105,
input VAR70,
input VAR11,
input VAR74,
input [23:0] VAR52,
input [10:0] VAR90,
input VAR103,
input [15:0] VAR108,
input [10:0] VAR48,
input VAR78,
input [10:0] VAR28,
input [15:0] VAR15,
output [15:... | gpl-2.0 |
benreynwar/fpga-sdrlib | verilog/flter/qa_filterbank.v | 1,127 | module MODULE1
parameter VAR8 = 32,
parameter VAR17 = 1
)
(
input wire clk,
input wire VAR11,
input wire [VAR8-1:0] VAR7,
input wire VAR4,
input wire [VAR17-1:0] VAR14,
input wire [VAR3-1:0] VAR2,
input wire VAR6,
output wire [VAR8-1:0] VAR13,
output wire VAR1,
output wire [VAR17-1:0] VAR16,
output wire [VAR3-1:0] VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a.pp.blackbox.v | 1,389 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR9 ,
VAR3,
VAR2,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR2;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.functional.v | 1,514 | module MODULE1 (
VAR7 ,
VAR5,
VAR11,
VAR6,
VAR2,
VAR9
);
output VAR7 ;
input VAR5;
input VAR11;
input VAR6;
input VAR2;
input VAR9;
wire VAR1 ;
wire VAR10;
or VAR4 (VAR1 , VAR11, VAR5 );
nand VAR3 (VAR10, VAR2, VAR6, VAR9, VAR1);
buf VAR8 (VAR7 , VAR10 );
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/clock_board_config_v1_05_a/hdl/verilog/clock_board_config.v | 30,283 | module MODULE1 (
VAR28,
VAR92,
VAR33,
VAR63,
VAR21,
VAR25,
VAR27,
VAR70,
VAR44,
VAR12,
VAR56,
VAR83,
VAR22
);
parameter VAR75 = 120000000;
parameter VAR49 = 1'b0;
parameter VAR20 = 1'b0;
parameter VAR68 = 1'b0;
parameter VAR64 = 1'b0;
parameter VAR88 = 16'h01ff; parameter VAR19 = 16'h1eff; parameter VAR71 = 16'h1eff; p... | bsd-2-clause |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_route.v | 2,919 | function automatic bit VAR2;
input integer VAR6;
input integer VAR1;
bit valid;
begin
valid=1'b1;
if (VAR6==VAR28) begin
if (VAR1>=VAR9) valid=1'b0;
end
VAR2=valid;
end
endfunction
function automatic bit VAR22;
input VAR29 VAR7;
input VAR29 VAR26;
bit valid;
begin
valid=1'b1;
if (VAR7==VAR26) valid=1'b0;
if (((VAR7==VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlclkp/sky130_fd_sc_hd__dlclkp.blackbox.v | 1,259 | module MODULE1 (
VAR4,
VAR1,
VAR2
);
output VAR4;
input VAR1;
input VAR2 ;
supply1 VAR3;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de/ded_pix_cache.v | 36,589 | module MODULE1
(
input VAR225, input VAR174, input VAR227, input [27:0] VAR254, input [27:0] VAR22, input [27:0] VAR229, input [11:0] VAR72, input [11:0] VAR60, input [11:0] VAR66, input VAR91,
input [3:0] VAR173, input VAR243,
input VAR210, input VAR256, input VAR7, input [31:0] VAR125, input [31:0] VAR115, input VAR3... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pipe_drp.v | 38,878 | module MODULE1 #
(
parameter VAR49 = "VAR139", parameter VAR170 = "3.0", parameter VAR30 = "VAR50", parameter VAR14 = "VAR154", parameter VAR34 = "VAR161", parameter VAR108 = "VAR50", parameter VAR99 = "VAR161", parameter VAR78 = 0, parameter VAR142 = 0, parameter VAR88 = 2'd1, parameter VAR131 = 5'd21
)
(
input VAR55,... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/hpdmc_banktimer.v | 1,552 | module MODULE1(
input VAR3,
input VAR4,
input VAR5,
input [1:0] VAR2,
input read,
input write,
output reg VAR1
);
reg [2:0] counter;
always @(posedge VAR3) begin
if(VAR4) begin
counter <= 3'd0;
VAR1 <= 1'b1;
end else begin
if(read) begin
counter <= 3'd4;
VAR1 <= 1'b0;
end else if(write) begin
counter <= {1'b1, VAR2};
V... | lgpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_pd.v | 15,824 | module MODULE1( clk, rst,
VAR73, VAR12, VAR42, VAR15,
VAR48, VAR5, VAR6, VAR7,
VAR29, VAR55, VAR10, VAR18,
VAR30, VAR71, VAR26, VAR36,
VAR57, VAR87, VAR86, VAR84,
VAR81,
VAR39, VAR11, VAR66, VAR83,
VAR34,
VAR23, VAR65, VAR8, VAR9,
VAR67
);
input clk, rst;
input [7:0] VAR73;
input VAR12, VAR42, VAR15;
output VAR48, VAR5... | gpl-2.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/if_reg.v | 2,142 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR17] VAR13,
input wire VAR4, input wire VAR1, input wire [VAR7] VAR12, input wire VAR9, input wire [VAR7] VAR5,
output reg [VAR7] VAR6, output reg [VAR17] VAR16, output reg VAR2 );
always @(posedge clk or VAR14 reset) begin
if (reset == VAR11) begin
VAR6 ... | mit |
SymbiFlow/yosys | techlibs/intel/common/brams_map_m9k.v | 4,319 | module \VAR39 (VAR30, VAR73, VAR7, VAR38, VAR36, VAR44, VAR56, VAR5);
parameter VAR41 = 8;
parameter VAR66 = 36;
parameter VAR19 = 1;
parameter VAR3 = 1;
parameter VAR64 = 1;
parameter VAR1 = 1;
input VAR30;
input VAR73;
output [VAR66-1:0] VAR38;
input [VAR41-1:0] VAR7;
input VAR36;
output [VAR66-1:0] VAR56;
input [VAR... | isc |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_gt_rx_valid_filter_7x.v | 9,131 | module MODULE1 #(
parameter VAR9 = 28,
parameter VAR11 = 1
)
(
output [1:0] VAR5,
output [15:0] VAR6,
output VAR21,
output VAR3,
output [ 2:0] VAR30,
output VAR43,
input [1:0] VAR41,
input [15:0] VAR45,
input VAR14,
input VAR15,
input [ 2:0] VAR19,
input VAR31,
input VAR38,
input VAR18,
input VAR44,
input VAR2
);
local... | mit |
gigglesninja/digital-system-design | newuart/uart.v | 2,867 | module MODULE1(
input clk,
input reset,
input VAR27,
output VAR25,
output [7:0] VAR22
);
wire [7:0] VAR2;
wire [1:0] VAR25;
reg [2:0] addr, VAR11, VAR18;
reg [1:0] VAR33;
reg [3:0] din;
reg [7:0] VAR35, VAR10;
reg VAR28, VAR24, VAR17, VAR16, VAR12, VAR5;
VAR38 #(.VAR9(8'h0C)) VAR6(
.clk (clk),
.reset (reset),
.VAR23 (V... | gpl-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_Leds/picoblze/embedded_kcpsm3.v | 4,140 | module MODULE1(
VAR6,
VAR5,
VAR3,
VAR4,
VAR7,
interrupt,
VAR2,
reset,
clk);
output[7:0] VAR6;
output VAR5;
output VAR3;
output[7:0] VAR4;
input[7:0] VAR7;
input interrupt;
output VAR2;
input reset;
input clk;
wire [7:0] VAR6;
wire VAR5;
wire VAR3;
wire [7:0] VAR4;
wire [7:0] VAR7;
wire interrupt;
wire VAR2;
wire reset;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.pp.blackbox.v | 1,348 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR3 ,
VAR5 ,
VAR4,
VAR7,
VAR2 ,
VAR6
);
output VAR8 ;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR7;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
andygikling/BBot | Source Code/BBotFPGA/BBot HDL Source Code/BBotFPGA_TopLevel.v | 18,824 | module MODULE1(
input VAR4,
input VAR71,
output VAR23,
output VAR170,
output VAR95,
output VAR112,
output VAR51,
output VAR117,
output VAR21,
output VAR149,
input VAR12,
input VAR27,
input VAR141,
input VAR44,
input VAR114,
input VAR62,
input VAR172,
input VAR162,
input VAR50, output VAR96, input VAR32, input VAR40, in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.symbol.v | 1,381 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR7
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/ALLBUTCU/BarrelShifter.v | 4,748 | module MODULE1(input [31:0] VAR1,VAR7,VAR4,input VAR12,output VAR10,output [31:0] VAR5);
reg [31:0] VAR8,VAR11;
reg [1:0] VAR9;
always@(VAR4 or VAR7 or VAR1 or VAR12)
begin
case(VAR4[27:25])
3'b000:
begin
if(!VAR4[4]) begin
VAR8 = VAR7;
VAR11 = VAR4[11:7];
VAR9 = VAR4[6:5];
end
else
begin
VAR8 = VAR7;
VAR11 = VAR1[5:0]... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/prog_counter2a.v | 1,202 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst)
begin
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.pp.blackbox.v | 1,401 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR5 ,
VAR3,
VAR6 ,
VAR7 ,
VAR2 ,
VAR1
);
output VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR3;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi_1.v | 2,277 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR10 ,
VAR1 ,
VAR3,
VAR5,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR3;
input VAR5;
input VAR9 ;
input VAR8 ;
VAR2 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
m-labs/milkymist | cores/tmu2/rtl/tmu2.v | 18,802 | module MODULE1 #(
parameter VAR188 = 4'h0,
parameter VAR38 = 26,
parameter VAR159 = 15,
parameter VAR104 = 5,
parameter VAR235 = 4,
parameter VAR167 = 4
) (
input VAR58,
input VAR263,
input [13:0] VAR72,
input VAR198,
input [31:0] VAR130,
output [31:0] VAR259,
output irq,
output [31:0] VAR224,
output [2:0] VAR122,
outp... | lgpl-3.0 |
aj-michael/Digital-Systems | Lab6-Part2/ShiftRegisterI2C2015fall.v | 1,224 | module MODULE1(VAR12,VAR6,VAR9,VAR11,VAR7,VAR8,VAR10,VAR1,VAR5);
input [7:0] VAR12;
input VAR6;
input VAR5;
input VAR9;
input VAR11;
input VAR7;
input VAR8;
output reg [7:0] VAR10;
output reg VAR1;
wire VAR3;
VAR2 VAR4(VAR5, VAR3, VAR9, VAR6) ;
always @ (posedge VAR6)
if (VAR9 == 1) begin VAR1 <= 0; VAR10 <= 8'b0; end
... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/uart_tfifo.v | 9,182 | module MODULE1 (clk,
VAR27, VAR16, VAR3,
VAR26, VAR23, VAR7,
VAR13,
VAR4,
VAR1
);
parameter VAR18 = VAR15;
parameter VAR19 = VAR17;
parameter VAR6 = VAR5;
parameter VAR20 = VAR22;
input clk;
input VAR27;
input VAR26;
input VAR23;
input [VAR18-1:0] VAR16;
input VAR4;
input VAR1;
output [VAR18-1:0] VAR3;
output VAR7;
out... | apache-2.0 |
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