repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_006.v | 1,515 | module MODULE1 (
VAR4,
VAR11
);
input [31:0] VAR4;
output [31:0]
VAR11;
wire [31:0]
VAR8,
VAR7,
VAR1,
VAR12,
VAR9,
VAR5,
VAR6,
VAR14,
VAR10;
assign VAR8 = VAR4;
assign VAR9 = VAR12 - VAR1;
assign VAR12 = VAR1 << 3;
assign VAR7 = VAR8 << 9;
assign VAR1 = VAR8 + VAR7;
assign VAR5 = VAR8 << 6;
assign VAR6 = VAR8 + VAR5;
a... | mit |
julioamerico/prj_crc_ip | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/amba_bfm/bfm_ahbslave.v | 2,062 | module
MODULE1
(
VAR21
,
VAR30
,
VAR24
,
VAR31
,
VAR35
,
VAR12
,
VAR16
,
VAR26
,
VAR32
,
VAR28
,
VAR6
,
VAR27
,
VAR15
,
VAR36
,
VAR4
)
;
parameter
VAR14
=
10
;
parameter
VAR20
=
256
;
parameter
VAR2
=
" "
;
parameter
VAR5
=
0
;
parameter
VAR17
=
0
;
parameter
VAR18
=
1
;
parameter
VAR1
=
-
1
;
localparam
VAR10
=
0
;
lo... | gpl-3.0 |
neale/CS-program | 474-VLSI/UART/db/ADC_PLL_altpll.v | 4,532 | module MODULE1
(
VAR5,
clk,
VAR6,
VAR2) ;
input VAR5;
output [4:0] clk;
input [1:0] VAR6;
output VAR2;
tri0 VAR5;
tri0 [1:0] VAR6;
reg VAR4;
wire [4:0] VAR7;
wire VAR1;
wire VAR3; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.blackbox.v | 1,568 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR1
);
output VAR4 ;
input VAR5 ;
input VAR1;
supply1 VAR8 ;
supply0 VAR3 ;
supply1 VAR7;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_tq.v | 12,747 | module MODULE1 (
clk ,
VAR29 ,
VAR18 ,
VAR38 ,
VAR20 ,
VAR2 ,
VAR16 ,
VAR14 ,
VAR25 ,
VAR27 ,
VAR24 ,
VAR19 ,
VAR9 ,
VAR7 ,
VAR26 ,
VAR39 ,
VAR11 ,
VAR43 ,
VAR12 ,
VAR28 ,
VAR40
);
input [1-1:0] clk ; input [1-1:0] VAR29 ; input [1-1:0] VAR18 ; input [2-1:0] VAR38 ; output [1-1:0] VAR20 ; input [42-1:0] VAR2 ; output [... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/sipo.v | 5,890 | module MODULE1(VAR11, VAR9, VAR7, VAR3, VAR6, clk);
output [7:0] VAR11;
output VAR9;
input VAR7;
input clk;
input VAR6;
input VAR3;
reg VAR9; reg [7:0] VAR11; reg [7:0] VAR2; reg VAR5; reg VAR8; reg VAR1; reg VAR10; reg VAR4; reg VAR14; reg VAR12; reg VAR13;
always @(~VAR6)
begin
VAR9<=1'd0;
VAR11<=8'd0;
VAR2<=8'd0;
VA... | mit |
aaiijmrtt/JUCSE | VeryLargeScaleIntegration/mux.v | 1,580 | module MODULE5(in, VAR1, out);
input wire[3: 0] in;
input wire[1: 0] VAR1;
output wire out;
assign out = in[VAR1];
endmodule
module MODULE3(in, VAR1, out);
input wire[3: 0] in;
input wire[1: 0] VAR1;
output wire out;
assign out = VAR1 == 2'b00 ? in[0] : VAR1 == 2'b01 ? in[1] : VAR1 == 2'b10 ? in[2] : VAR1 == 2'b11 ? in... | mit |
cpulabs/mist1032isa | src/core/execute/divider/div_pipelined_latch.v | 1,630 | module MODULE1 #(
parameter VAR21 = 4
)(
input wire VAR5,
input wire VAR9,
input wire VAR13,
input wire VAR8,
output wire VAR14,
input wire VAR12,
input wire [31:0] VAR1,
input wire [31:0] VAR6,
input wire [VAR21-1:0] VAR17,
input wire [30:0] VAR7,
output wire VAR15,
input wire VAR18,
output wire VAR2,
output wire [31:... | bsd-2-clause |
lynxis/lpc_sniffer | lpc.v | 3,266 | module MODULE1(
input [3:0] VAR14,
input VAR17,
input VAR5,
input VAR13,
input reset,
output [3:0] VAR7,
output [31:0] VAR6,
output [7:0] VAR11,
output VAR9,
output reg VAR8);
reg [3:0] state = 0;
localparam VAR2 = 0, VAR16 = 1, VAR1 = 2, address = 3, VAR15 = 4, sync = 5, VAR4 = 6, VAR3 = 7;
reg [3:0] counter;
reg [3:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai.functional.v | 1,586 | module MODULE1 (
VAR10 ,
VAR4,
VAR11,
VAR1 ,
VAR7
);
output VAR10 ;
input VAR4;
input VAR11;
input VAR1 ;
input VAR7 ;
wire VAR3 ;
wire VAR12 ;
wire VAR2;
nand VAR5 (VAR3 , VAR11, VAR4 );
or VAR6 (VAR12 , VAR7, VAR1 );
nand VAR8 (VAR2, VAR3, VAR12);
buf VAR9 (VAR10 , VAR2 );
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/synth/ghrd_10as066n2_fpga_m.v | 2,060 | module MODULE1 (
input wire VAR5, input wire VAR6, output wire [31:0] VAR3, input wire [31:0] VAR9, output wire VAR1, output wire VAR15, output wire [31:0] VAR10, input wire VAR4, input wire VAR7, output wire [3:0] VAR12, output wire VAR2 );
VAR14 #(
.VAR13 (0),
.VAR16 (50000),
.VAR11 (2)
) VAR8 (
.VAR5 (VAR5), .VAR6 (... | mit |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_arb_wr.v | 3,958 | module MODULE1(
VAR23,
VAR25,
VAR21,
VAR22,
VAR29,
VAR4,
VAR8,
VAR5,
VAR12,
VAR2,
VAR19,
VAR9,
VAR10,
VAR20,
VAR1,
VAR3,
VAR15,
VAR18,
VAR17,
VAR11
);
input VAR23, VAR25;
input [VAR27-1:0] VAR21,VAR22;
input [VAR7-1:0] VAR8,VAR5;
input [VAR14-1:0] VAR12,VAR2;
input [VAR28:0] VAR19,VAR9;
input VAR29, VAR4, VAR11;
output... | mit |
lvd2/zxevo | unsupported/solegstar/fpga/current/vga/example.v | 3,713 | module MODULE1 (
VAR3,VAR13,VAR19,
VAR23,VAR15,request,
VAR10,VAR8,VAR16,VAR11,VAR14,VAR25,VAR9,
VAR21,VAR1);
input [9:0] VAR3,VAR13,VAR19;
output [9:0] VAR23;
output [9:0] VAR15;
output request;
output [9:0] VAR10, VAR8, VAR16;
output VAR11, VAR14, VAR25, VAR9;
input VAR21, VAR1;
parameter VAR20 = 16; parameter VAR29 ... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/i2c/rtl/i2c_cpx_cnt.v | 3,923 | module MODULE1 (
VAR3,
VAR6, clk, VAR11, VAR8
);
input VAR6;
input clk;
input VAR11;
input VAR8;
output VAR3;
wire VAR12;
wire VAR13;
wire [1:0] VAR1;
wire [1:0] VAR9;
wire [1:0] VAR7;
reg [1:0] VAR2;
wire VAR3;
assign VAR12 = VAR11 & ~VAR8;
assign VAR13 = VAR8 & ~VAR11;
assign VAR1 = VAR7 + 2'b01;
assign VAR9 = VAR7 -... | gpl-2.0 |
ultraembedded/altor32 | rtl/cpu/altor32_ram_sp.v | 3,243 | module MODULE1
parameter [31:0] VAR7 = 8,
parameter [31:0] VAR1 = 14
)
(
input VAR10 ,
output [(VAR7 - 1):0] VAR8 ,
input [(VAR7 - 1):0] VAR3 ,
input [(VAR1 - 1):0] VAR9 ,
input VAR6
);
reg [(VAR7 - 1):0] VAR5 [((2<< (VAR1-1)) - 1):0] ;
reg [(VAR1 - 1):0] VAR4;
always @ (posedge VAR10)
begin
if (VAR6 == 1'b1)
VAR5[VAR9... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo_2.v | 2,191 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR2 ,
VAR6,
VAR3,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR6;
input VAR3;
input VAR7;
VAR4 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR1 ,
VAR8 ,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR8 ;
input VAR2 ... | apache-2.0 |
ridecore/ridecore | src/fpga/multiplier.v | 1,588 | module MODULE2(
input wire [1:0] sel,
input wire [2*VAR16-1:0] VAR2,
input wire [2*VAR16-1:0] VAR6,
input wire [2*VAR16-1:0] VAR14,
input wire [2*VAR16-1:0] VAR17,
output reg [2*VAR16-1:0] out
);
always @(*) begin
case(sel)
0: begin
out = VAR2;
end
1: begin
out = VAR6;
end
2: begin
out = VAR14;
end
3: begin
out = VAR17... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3.behavioral.v | 1,716 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR10 ,
VAR5 ,
VAR7,
VAR6
);
output VAR2 ;
input VAR9 ;
input VAR10 ;
input VAR5 ;
input VAR7;
input VAR6;
wire VAR8 ;
wire VAR3;
xnor VAR11 (VAR8 , VAR9, VAR10, VAR5 );
VAR4 VAR12 (VAR3, VAR8, VAR7, VAR6);
buf VAR1 (VAR2 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap_4.v | 1,870 | module MODULE2 (
VAR5,
VAR1,
VAR4 ,
VAR2
);
input VAR5;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR3 VAR6 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR5;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
VAR3 VAR6 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf.blackbox.v | 1,202 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR4;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.behavioral.pp.v | 1,402 | module MODULE1( VAR7, VAR1, VAR8, VAR4, VAR2, VAR10, VAR9 );
input VAR2, VAR4, VAR7, VAR8;
inout VAR10, VAR9;
output VAR1;
VAR6 VAR3(.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR10(VAR10),.VAR9(VAR9));
VAR6 VAR5(.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR10(VAR10),.VAR9(VAR9)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.behavioral.pp.v | 7,224 | module MODULE1( VAR3, VAR10, VAR7, VAR8, VAR9, VAR2, VAR1, VAR11, VAR5 );
input VAR1, VAR2, VAR7, VAR9, VAR10, VAR3;
inout VAR11, VAR5;
output VAR8;
VAR4 VAR12(.VAR3(VAR3),.VAR10(VAR10),.VAR7(VAR7),.VAR8(VAR8),.VAR9(VAR9),.VAR2(VAR2),.VAR1(VAR1),.VAR11(VAR11),.VAR5(VAR5));
VAR4 VAR6(.VAR3(VAR3),.VAR10(VAR10),.VAR7(VAR7... | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/bench/verilog/uart_device_utilities.v | 11,409 | module MODULE1;
task VAR1;
input [3:0] VAR12;
begin
end
endtask
task VAR2;
begin
end
endtask
task VAR11;
begin
end
endtask
task VAR38;
begin
end
endtask
task VAR17;
begin
end
endtask
task VAR43;
begin
end
endtask
task VAR7;
input VAR35;
begin
if (~VAR35)
begin
end
begin
end
else
begin
end
... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/tse_mac1_loopback.v | 3,192 | module MODULE1 (
VAR3,
VAR4,
VAR1
);
output VAR3;
input VAR4;
output VAR1;
reg VAR2; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn.behavioral.v | 1,947 | module MODULE1 (
VAR13 ,
VAR16 ,
VAR5
);
output VAR13 ;
input VAR16 ;
input VAR5;
supply1 VAR11;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR3 ;
wire VAR1 ;
wire VAR2;
wire VAR17 ;
reg VAR6 ;
wire VAR10 ;
not VAR15 (VAR3 , VAR2 );
VAR12 VAR14 (VAR1 , VAR17, VAR3, VAR6, VAR11, VAR4);
buf VAR9 (VAR13 , VAR1 );
as... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_vga_char_buffer.v | 13,444 | module MODULE1 (
clk,
reset,
VAR30,
VAR77,
VAR17,
VAR61,
VAR73,
VAR79,
VAR48,
VAR58,
VAR25,
VAR97,
VAR31,
VAR53,
VAR55,
VAR49,
VAR78,
VAR100,
VAR18,
VAR4,
VAR57,
VAR87,
VAR5
);
parameter VAR37 = 8;
parameter VAR99 = 0;
parameter VAR47 = 13;
parameter VAR60 = 8192;
parameter VAR46 = 640;
parameter VAR111 = 480;
input cl... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.symbol.v | 1,513 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR4 ,
input VAR2 ,
input VAR7,
input VAR6 ,
input VAR1
);
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_106.v | 1,551 | module MODULE2 (
VAR12,
VAR8
);
input [31:0] VAR12;
output [31:0]
VAR8;
wire [31:0]
VAR6,
VAR14,
VAR9,
VAR1,
VAR7,
VAR11,
VAR5,
VAR4,
VAR13,
VAR15;
assign VAR6 = VAR12;
assign VAR11 = VAR6 << 1;
assign VAR14 = VAR6 << 8;
assign VAR9 = VAR6 + VAR14;
assign VAR1 = VAR9 << 4;
assign VAR5 = VAR7 - VAR11;
assign VAR7 = VAR9... | mit |
tmatsuya/milkymist-ml401 | boards/xilinx-ml401/rtl/vga.v | 2,083 | module MODULE1 #(
parameter VAR20 = 4'h0,
parameter VAR6 = 26
) (
input VAR4,
input VAR14,
input [13:0] VAR7,
input VAR16,
input [31:0] VAR28,
output [31:0] VAR9,
output [VAR6-1:0] VAR19,
output VAR17,
input VAR15,
input [63:0] VAR18,
output VAR12,
output [VAR6-1:0] VAR24,
input [63:0] VAR22,
input VAR27,
output VAR11,... | lgpl-3.0 |
ultraembedded/riscv | top_cache_axi/src_v/dcache.v | 12,743 | module MODULE1
parameter VAR160 = 0
)
(
input VAR187
,input VAR169
,input [ 31:0] VAR109
,input [ 31:0] VAR123
,input VAR22
,input [ 3:0] VAR125
,input VAR139
,input [ 10:0] VAR80
,input VAR130
,input VAR182
,input VAR118
,input VAR183
,input VAR24
,input VAR49
,input [ 1:0] VAR88
,input [ 3:0] VAR15
,input VAR159
,inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4_1.v | 2,115 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR1 ,
VAR4 ,
VAR8 ,
VAR5,
VAR9
);
output VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR5;
input VAR9;
VAR2 VAR6 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR3,
VAR7,
VAR1,
VAR4,
VAR8
);
... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_mm_interconnect_0.v | 19,278 | module MODULE1 (
input wire VAR13, input wire VAR2, input wire VAR45, input wire VAR37, input wire [29:0] VAR46, output wire VAR43, input wire [4:0] VAR8, input wire [31:0] VAR82, input wire VAR69, output wire [255:0] VAR26, output wire VAR77, input wire VAR36, input wire [255:0] VAR96, output wire [29:0] VAR21, output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.blackbox.v | 1,334 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR8 ,
VAR5,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR4;
supply1 VAR6;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/source/pcie_soft_int.v | 6,052 | module MODULE1
(
input wire clk,
input wire VAR23,
input wire VAR13,
input wire VAR22,
input wire [31:0] VAR21,
input wire VAR30,
output [3:0] VAR8,
output wire VAR24,
input wire VAR11,
output wire VAR18,
input wire VAR10,
input wire VAR5,
input wire [7:0] VAR32,
output [2:0] VAR26,
output [7:0] VAR7,
output VAR20,
inp... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.symbol.v | 1,482 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7 ,
input VAR5 ,
input VAR3,
input VAR6 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.functional.pp.v | 1,200 | module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR4
);
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o_4.v | 2,248 | module MODULE2 (
VAR10 ,
VAR9 ,
VAR3 ,
VAR5 ,
VAR2,
VAR7,
VAR6 ,
VAR8
);
output VAR10 ;
input VAR9 ;
input VAR3 ;
input VAR5 ;
input VAR2;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR1 VAR4 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
Elphel/x393_sata | ahci/axi_ahci_regs.v | 28,710 | module MODULE1#(
parameter VAR69 = 10, parameter VAR163 = 9, parameter VAR86 = 1 )(
input VAR176, input VAR54,
input [31:0] VAR83, input VAR93, output VAR136, input [11:0] VAR63, input [ 3:0] VAR122, input [ 1:0] VAR9, input [ 1:0] VAR177, input [31:0] VAR80, input VAR151, output VAR183, input [11:0] VAR121, input VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.symbol.v | 1,420 | module MODULE1 (
input VAR7 ,
output VAR5 ,
input VAR1
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
SymbiFlow/symbiflow-arch-defs | xc/xc7/techmap/clean_carry_map.v | 2,436 | module MODULE2(input VAR24, input VAR23, input VAR11, input VAR16, output VAR26);
parameter VAR14 = 1'b0;
assign VAR26 = VAR24;
endmodule
module MODULE3(input VAR24, input VAR23, input VAR11, input VAR16, output VAR26);
parameter VAR14 = 1'b0;
generate if(VAR14)
VAR15 #(.VAR5(8'b01110100)) VAR21 (.VAR22(VAR23), .VAR4(V... | isc |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/alt_mem_ddrx_wdata_path.v | 53,451 | module MODULE1
parameter
VAR123 = 16,
VAR203 = 8,
VAR245 = 1,
VAR154 = 5,
VAR252 = 4,
VAR141 = 1,
VAR94 = 1,
VAR125 = 8,
VAR210 = 10,
VAR209 = 2,
VAR107 = 1,
VAR127 = 0,
VAR187 = 1,
VAR175 = 8,
VAR117 = 5,
VAR227 = 1,
VAR51 = 1,
VAR163 = 1,
VAR90 = 1,
VAR88 = 8,
VAR131 = 0
)
(
VAR192,
VAR190,
VAR80,
VAR188,
VAR13,
VAR7... | gpl-2.0 |
jotego/jt12 | hdl/mixer/jt12_interpol.v | 2,753 | module MODULE1 #(parameter VAR6=18, VAR11=16,
VAR8=2, VAR4=1, VAR21=2 )(
input rst,
input clk,
input VAR19,
input VAR5,
input signed [VAR11-1:0] VAR17,
output reg signed [VAR11-1:0] VAR24
);
reg signed [VAR6-1:0] VAR3;
wire signed [VAR6-1:0] VAR18, VAR7;
localparam VAR12 = VAR6 - VAR11;
generate
genvar VAR2;
wire [VAR6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a.behavioral.v | 1,658 | module MODULE1 (
VAR11 ,
VAR9,
VAR16,
VAR14 ,
VAR6
);
output VAR11 ;
input VAR9;
input VAR16;
input VAR14 ;
input VAR6 ;
supply1 VAR8;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR13 ;
wire VAR2 ;
wire VAR15 ;
wire VAR12;
nand VAR4 (VAR2 , VAR16, VAR9 );
or VAR5 (VAR15 , VAR6, VAR14 );
and VAR3 (VAR12, VAR2, VAR15);
buf VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b.blackbox.v | 1,266 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR1;
supply1 VAR4;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.behavioral.pp.v | 1,245 | module MODULE1 (
VAR2,
VAR1,
VAR3 ,
VAR4
);
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.functional.pp.v | 2,050 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1,
VAR7 ,
VAR12 ,
VAR8
);
output VAR5 ;
input VAR6 ;
input VAR1;
input VAR7 ;
input VAR12 ;
input VAR8 ;
wire VAR4;
wire VAR9 ;
VAR11 VAR10 (VAR4, VAR6, VAR1, VAR12 );
buf VAR3 (VAR9 , VAR4 );
VAR11 VAR2 (VAR5 , VAR9, VAR7, VAR12);
endmodule | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/top_mdio/top_mido.v | 1,610 | module MODULE1(
input reset,
input clk,
output VAR4, inout VAR14,
output [3:0] VAR8
);
wire VAR10; wire [1:0] VAR11; wire [4:0] VAR7; wire [4:0] VAR12; wire [15:0] VAR1;
wire VAR6; wire [15:0] VAR3;
wire VAR5;
VAR9 VAR9(
.reset(reset),
.clk(clk),
.VAR4(VAR4),.VAR14(VAR14),
.VAR10(VAR10),.VAR11(VAR11), .VAR7(VAR7),.VAR1... | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter_001.v | 6,176 | module MODULE1 #(
parameter VAR18 = 34,
parameter VAR16 = 0,
parameter VAR11 = 34,
parameter VAR21 = 0,
parameter VAR12 = 0,
parameter VAR10 = 0,
parameter VAR19 = 1,
parameter VAR20 = 1,
parameter VAR14 = 0,
parameter VAR2 = 34,
parameter VAR1 = 0,
parameter VAR25 = 1,
parameter VAR8 = 0,
parameter VAR4 = 1,
parameter... | mit |
Canaan-Creative/MM | verilog/superkdf9/components/alink/rx_phy.v | 3,448 | module MODULE1(
input clk ,
input rst ,
input VAR16 ,
input VAR6 ,
input VAR2 ,
input [31:0] VAR8 ,
input [31:0] VAR19 ,
input [31:0] VAR13 ,
output VAR4 ,
output VAR7 ,
output VAR5 ,
output [31:0] VAR9 ,
input VAR14 ,
input VAR15
);
parameter VAR17 = 32'd0 ;
reg [3:0] VAR21 ;
reg [3:0] VAR22 ;
always@(posedge clk or p... | unlicense |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/axi_basic_rx_pipeline.v | 26,811 | module MODULE1 #(
parameter VAR14 = 128, parameter VAR19 = "VAR18", parameter VAR6 = 1,
parameter VAR17 = (VAR14 == 128) ? 2 : 1, parameter VAR7 = VAR14 / 8 ) (
output reg [VAR14-1:0] VAR13, output reg VAR32, input VAR30, output [VAR7-1:0] VAR71, output VAR27, output reg [21:0] VAR59,
input [VAR14-1:0] VAR73, input VAR... | lgpl-3.0 |
monotone-RK/FACE | MCSoC-15/4-way_4-parallel/ise/ipcore_dir/dram/example_design/rtl/traffic_gen/mig_7series_v1_9_vio_init_pattern_bram.v | 13,203 | module MODULE1 #
(
parameter VAR33 = 100,
parameter VAR50 = 32'h00000000,
parameter VAR26 = 8,
parameter VAR30 = 4,
parameter VAR36 = 16,
parameter VAR1 = 8,
parameter VAR46 = VAR1
)
(
input VAR43,
input VAR47,
input VAR35,
input [31:0] VAR55, input VAR29, input [3:0] VAR59, input [31:0] VAR13, input [31:0] VAR45, inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf.functional.v | 1,231 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
wire VAR4;
buf VAR1 (VAR4, VAR2 );
buf VAR3 (VAR5 , VAR4 );
endmodule | apache-2.0 |
toyoshim/tvcl | FourDigitSevenSegmentLED.v | 2,268 | module MODULE1(
clk,
VAR11,
VAR7,
VAR32,
VAR6,
VAR5,
VAR14,
VAR29,
VAR28,
VAR8,
VAR31,
VAR35,
VAR23,
VAR22,
VAR15,
VAR33,
VAR3,
VAR18,
VAR34,
VAR21);
input clk;
input VAR11;
input [3:0] VAR7;
input [3:0] VAR32;
input [3:0] VAR6;
input [3:0] VAR5;
input VAR14;
input VAR29;
input VAR28;
input VAR8;
output VAR31;
output V... | bsd-3-clause |
origintfj/riscv | rv32i/rtl/merlin_id_stage.v | 18,184 | module MODULE1
(
input wire VAR28,
input wire VAR113,
input wire VAR109, output wire VAR119, output reg [1:0] VAR89, input wire [VAR50] VAR96, input wire [31:0] VAR21, input wire VAR110, input wire [VAR39-1:0] VAR74, output reg [VAR39-1:0] VAR7,
output reg VAR65,
input wire VAR9,
output reg [VAR50] VAR103,
output reg [... | apache-2.0 |
donnaware/AGC | rtl/de0/modules/SEG7_OUT4.v | 1,366 | module MODULE2(
input [15:0] VAR7,
output [ 6:0] VAR10,
output [ 6:0] VAR1,
output [ 6:0] VAR6,
output [ 6:0] VAR5
);
MODULE1 MODULE1(VAR7[ 3: 0], VAR10);
MODULE1 MODULE3(VAR7[ 7: 4], VAR1);
MODULE1 MODULE4(VAR7[11: 8], VAR6);
MODULE1 MODULE2(VAR7[15:12], VAR5);
endmodule
module MODULE1(
input [3:0] VAR7,
output reg [6... | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_log_double.v | 247,725 | module MODULE1
(
VAR4,
VAR1,
VAR6,
VAR12,
VAR14,
VAR2) ;
input VAR4;
input VAR1;
input VAR6;
input [63:0] VAR12;
input [5:0] VAR14;
output [63:0] VAR2;
tri0 VAR4;
tri1 VAR1;
tri0 VAR6;
reg [0:0] VAR5;
reg [63:0] VAR7;
wire [6:0] VAR10;
wire VAR8;
wire [31:0] VAR3;
wire [447:0] VAR13;
wire [5:0] VAR11;
wire [383:0] VAR9... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_stub.v | 1,186 | module MODULE1(VAR2, VAR1, reset)
;
input VAR2;
output VAR1;
input reset;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2.functional.v | 1,768 | module MODULE1 (
VAR8,
VAR7,
VAR2 ,
VAR6 ,
VAR10 ,
VAR1
);
input VAR8;
input VAR7;
output VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR1 ;
wire VAR4 ;
wire VAR11;
VAR5 VAR9 (VAR4 , VAR6, VAR10, VAR1 );
VAR13 VAR12 (VAR11, VAR4, VAR8, VAR7);
buf VAR3 (VAR2 , VAR11 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/traffic_gen/afifo.v | 6,916 | module MODULE1 #
(
parameter VAR22 = 100,
parameter VAR13 = 32,
parameter VAR1 = 16,
parameter VAR8 = 4,
parameter VAR42 = 1 )
(
input VAR6,
input rst,
input VAR19,
input [VAR13-1:0] VAR14,
input VAR28,
input VAR31,
output [VAR13-1:0] VAR20,
output reg VAR9,
output reg VAR27,
output reg VAR16
);
reg [VAR13-1:0] VAR25 [... | lgpl-3.0 |
alexforencich/verilog-ethernet | rtl/axis_baser_rx_64.v | 19,244 | module MODULE1 #
(
parameter VAR5 = 64,
parameter VAR17 = (VAR5/8),
parameter VAR20 = 2,
parameter VAR3 = 4'h6,
parameter VAR16 = 16'h6666,
parameter VAR1 = 0,
parameter VAR11 = 96,
parameter VAR10 = (VAR1 ? VAR11 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR14,
input wire [VAR20-1:0] VAR9,
out... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/cccfdc3350413fa5/zqynq_lab_1_design_system_ila_0_0_stub.v | 1,328 | module MODULE1(clk, VAR1)
;
input clk;
input [0:0]VAR1;
endmodule | mit |
545/Atari7800 | lab3sound/lab3sound.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_stub.v | 1,493 | module MODULE1(VAR2, VAR1, VAR5, VAR9, VAR4, VAR3, VAR7, VAR8, VAR6)
;
input VAR2;
input VAR1;
input [0:0]VAR5;
input [17:0]VAR9;
input [15:0]VAR4;
input VAR3;
input VAR7;
input [17:0]VAR8;
output [15:0]VAR6;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.functional.pp.v | 2,008 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR17 ,
VAR10 ,
VAR9 ,
VAR7,
VAR15,
VAR5 ,
VAR14
);
output VAR13 ;
input VAR4 ;
input VAR17 ;
input VAR10 ;
input VAR9 ;
input VAR7;
input VAR15;
input VAR5 ;
input VAR14 ;
wire VAR12 ;
wire VAR6 ;
wire VAR11;
not VAR3 (VAR12 , VAR9 );
nor VAR8 (VAR6 , VAR4, VAR17, VAR10, VAR12 );
VAR1 V... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/iobs_hard_wired.v | 12,550 | module MODULE1 (
VAR13,
VAR93, VAR108,
VAR114,
VAR32,
VAR69,
VAR107,
VAR6,
VAR10,
VAR56,
VAR65,
VAR110,
VAR118,
VAR88,
VAR49,
VAR22,
VAR5,
VAR9,
VAR7,
VAR44,
VAR30,
VAR66,
VAR83,
VAR52,
VAR45,
VAR20,
VAR117
);
parameter VAR19 = 16;
parameter VAR61 = 13;
parameter VAR58 = 2;
parameter VAR97 = VAR19 / VAR58 - 1;
input VA... | lgpl-3.0 |
rellermeyer/99tsp | verilog/sa/src/mojo_top.v | 3,456 | module MODULE1(
input clk,
input VAR36,
input VAR10,
output[7:0]VAR3,
output VAR32,
input VAR21,
input VAR6,
input VAR13,
output [3:0] VAR18,
input VAR42, output VAR28, input VAR45 );
wire rst = ~VAR36;
wire [7:0] VAR23;
wire VAR48, VAR47;
reg [7:0] VAR33, VAR12;
reg VAR35, VAR51;
VAR34 VAR34 (
.clk(clk),
.rst(rst),
.V... | bsd-3-clause |
dvanmali/Superscalar_Pipeline_Processor | pipeem.v | 1,104 | module MODULE1(clk,VAR13,VAR12,VAR9,VAR24,VAR19,VAR2,VAR17,VAR1,
VAR15,VAR14,VAR11,VAR22,VAR25,VAR5,VAR10,VAR21,
VAR4,VAR7,VAR8,VAR6,VAR20,VAR26,VAR23,VAR16,VAR18,VAR3);
input clk;
input [4:0] VAR13,VAR12;
input [31:0] VAR9,VAR19,VAR24,VAR2;
input VAR17,VAR1,VAR15,VAR14,VAR11,VAR22,VAR18,VAR3;
output reg VAR25,VAR10,VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.blackbox.v | 1,295 | module MODULE1 (
VAR5 ,
VAR6,
VAR7,
VAR1
);
output VAR5 ;
output VAR6;
input VAR7;
input VAR1 ;
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_dyn_N16_M4_syn.v | 8,372 | module MODULE1 ( VAR95, VAR107, VAR48, VAR179, VAR237, VAR114, VAR111
);
input [15:0] VAR95;
input [15:0] VAR107;
input [2:0] VAR48;
input [1:0] VAR237;
input [2:0] VAR114;
output [16:0] VAR111;
input VAR179;
wire VAR238, VAR233, VAR110, VAR125, VAR62, VAR211, VAR277, VAR88, VAR26, VAR240, VAR39, VAR186, VAR4, VAR232,
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.behavioral.v | 1,802 | module MODULE1( VAR1, VAR8, VAR3, VAR6, VAR7 );
input VAR8, VAR1, VAR6, VAR7;
output VAR3;
VAR4 VAR2(.VAR1(VAR1),.VAR8(VAR8),.VAR3(VAR3),.VAR6(VAR6),.VAR7(VAR7));
VAR4 VAR5(.VAR1(VAR1),.VAR8(VAR8),.VAR3(VAR3),.VAR6(VAR6),.VAR7(VAR7)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/temac_v6_v1_5/example_design/v6_emac_v1_5_block.v | 11,997 | module MODULE1
(
VAR8,
VAR38,
VAR47,
VAR15,
VAR49,
VAR4,
VAR10,
VAR30,
VAR48,
VAR34,
VAR3,
VAR9,
VAR39,
VAR70,
VAR11,
VAR22,
VAR53,
VAR19,
VAR21,
VAR36,
VAR24,
VAR43,
VAR44,
VAR45,
VAR33,
VAR41,
VAR28,
VAR26,
VAR51,
VAR37,
VAR69,
VAR42,
VAR60,
VAR35
);
output VAR8;
input VAR38;
output [7:0] VAR47;
output VAR15;
output ... | lgpl-3.0 |
adamgreig/bladeRF | hdl/fpga/ip/opencores/i2c/bench/verilog/tst_bench_top.v | 14,491 | module MODULE1();
reg clk;
reg VAR64;
wire [31:0] VAR59;
wire [ 7:0] VAR37, VAR60, VAR14, VAR8;
wire VAR7;
wire VAR56;
wire VAR52;
wire ack;
wire VAR48;
reg [7:0] VAR67, VAR65;
wire VAR53, VAR26, VAR21, VAR49, VAR29;
wire VAR66, VAR54, VAR28, VAR19, VAR33;
parameter VAR10 = 3'b000;
parameter VAR32 = 3'b001;
parameter V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.pp.symbol.v | 1,228 | module MODULE1 (
input VAR3 ,
input VAR4,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.behavioral.pp.v | 2,286 | module MODULE1 (
VAR17,
VAR3 ,
VAR14,
VAR19 ,
VAR18,
VAR2,
VAR20 ,
VAR16
);
output VAR17;
input VAR3 ;
input VAR14;
input VAR19 ;
input VAR18;
input VAR2;
input VAR20 ;
input VAR16 ;
wire VAR11 ;
wire VAR7 ;
wire VAR4 ;
wire VAR6 ;
wire VAR12 ;
wire VAR10 ;
wire VAR1;
reg VAR8 ;
not VAR13 (VAR7 , VAR11 );
not VAR5 (VAR... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_s0.v | 38,048 | module MODULE1 (
input wire VAR211, input wire VAR226, input wire VAR30, input wire VAR142, output wire [4:0] VAR158, output wire [5:0] VAR161, output wire [5:0] VAR70, output wire [0:0] VAR10, output wire [0:0] VAR222, output wire [0:0] VAR107, output wire VAR249, output wire VAR62, output wire VAR95, output wire [31:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2_2.v | 1,948 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR2 ,
VAR7,
VAR3
);
output VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR7;
input VAR3;
VAR1 VAR6 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4,
VAR5,
VAR2
);
output VAR4;
input VAR5;
input VAR2;
supply1 VAR7;
supply0 VAR3;
VAR1 VAR6 (
.... | apache-2.0 |
camacazio/icestick_JSTK2_ORGB | source/Main_Control(CMOD).v | 5,240 | module MODULE1(
VAR27,
VAR32,
VAR36,
VAR1,
VAR23,
VAR28,
VAR24,
VAR9,
VAR31,
VAR2,
VAR42,
VAR21,
VAR41,
VAR39
);
input VAR27; input VAR32;
output [4:0] VAR36;
output VAR1;
output VAR23;
output VAR28;
output VAR24;
output VAR9;
output VAR31;
output VAR2;
input VAR41; output VAR42; output VAR21; output VAR39;
wire VAR38;... | gpl-3.0 |
ZiCog/P8X32A_Emulation | P8X32A_DE0_Nano/cog_alu.v | 7,000 | module MODULE1
(
input [5:0] VAR19,
input [31:0] VAR12,
input [31:0] VAR21,
input [8:0] VAR14,
input VAR11,
input VAR13,
input VAR9,
input [31:0] VAR17,
input VAR8,
output wr,
output [31:0] VAR29,
output VAR24,
output VAR1
);
wire [31:0] VAR28 = { VAR21[0], VAR21[1], VAR21[2], VAR21[3], VAR21[4], VAR21[5], VAR21[6], VA... | gpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/2-instruction_decode/registers_memory.v | 3,567 | module MODULE1
parameter VAR20=32, VAR1=5 )
(
input wire clk, input wire reset,
input wire VAR41, input wire [VAR1-1:0] VAR10, VAR39, VAR42,
input wire [VAR20-1:0] VAR17,
output wire [VAR20-1:0] VAR23, VAR36,
output wire [VAR20-1:0] VAR16,
output wire [VAR20-1:0] VAR34,
output wire [VAR20-1:0] VAR27,
output wire [VAR20... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkTLPCM.v | 6,315 | module MODULE1(VAR30,
VAR11,
VAR52,
VAR54,
VAR53,
VAR56,
VAR18,
VAR39,
VAR13,
VAR1,
VAR32,
VAR4,
VAR46,
VAR16,
VAR48,
VAR44,
VAR14,
VAR2,
VAR31,
VAR41,
VAR40);
input [13 : 0] VAR30;
input VAR11;
input VAR52;
input VAR54;
output [152 : 0] VAR53;
output VAR56;
input [152 : 0] VAR18;
input VAR39;
output VAR13;
input [152 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn_2.v | 2,312 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR9 ,
VAR2,
VAR7 ,
VAR5 ,
VAR6 ,
VAR8
);
output VAR3 ;
output VAR10 ;
input VAR9 ;
input VAR2;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR8 ;
VAR4 VAR1 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MOD... | apache-2.0 |
brabect1/risc8 | hdl/verilog/cpu.v | 28,041 | module MODULE1 (
clk,
reset,
VAR145,
VAR23,
VAR78,
VAR138,
VAR108,
VAR164,
VAR171,
VAR179,
VAR109,
VAR13,
VAR41,
VAR56,
VAR121,
VAR154
);
input clk;
input reset;
output [10:0] VAR145;
input [11:0] VAR23;
input [7:0] VAR78;
output [7:0] VAR138;
output [7:0] VAR108;
input [7:0] VAR164; output [7:0] VAR171; output [6:0] V... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_jtaggpioport.v | 3,585 | module MODULE1(
input VAR32,
input reset,
output VAR9,
output VAR10,
output VAR18,
input VAR20,
output VAR29,
input VAR8,
input VAR12,
output VAR11,
output VAR26,
output VAR3,
output VAR30,
output VAR36,
input VAR25,
output VAR19,
output VAR1,
output VAR21,
output VAR17,
output VAR15,
input VAR34,
output VAR27,
output ... | apache-2.0 |
rohit21122012/CPU | ALU/Logic/LSHIFTER/LSHIFTER_32bit.v | 2,920 | module MODULE1(VAR13, VAR35, VAR71);
input [31:0] VAR35;
input VAR71;
output [31:0] VAR13;
wire VAR39;
wire [61:0]VAR63;
not VAR50(VAR39,VAR71);
and VAR61 (VAR63[0], VAR35[0],VAR71);
and VAR59 (VAR13[0], VAR35[1],VAR39);
and VAR72 (VAR63[2], VAR35[1],VAR71);
and VAR47 (VAR63[3], VAR35[2],VAR39);
and VAR14 (VAR63[4], VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf_16.v | 2,040 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR1,
VAR6,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR5 ;
input VAR8 ;
VAR7 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR1;
supply0 VAR6;... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/verilog/HLS_accel_fcmp_32ns_32ns_1_1.v | 2,474 | module MODULE1
VAR35 = 4,
VAR19 = 1,
VAR12 = 32,
VAR8 = 32,
VAR23 = 1
)(
input wire [VAR12-1:0] VAR31,
input wire [VAR8-1:0] VAR41,
input wire [4:0] VAR32,
output wire [VAR23-1:0] dout
);
localparam [4:0]
VAR24 = 5'b00001,
VAR14 = 5'b00010,
VAR36 = 5'b00011,
VAR28 = 5'b00100,
VAR1 = 5'b00101,
VAR27 = 5'b00110,
VAR6 = 5... | mit |
freecores/sha3 | high_throughput_core/rtl/padder1.v | 1,164 | module MODULE1(in, VAR1, out);
input [63:0] in;
input [2:0] VAR1;
output reg [63:0] out;
always @ (*)
case (VAR1)
0: out = 64'h0100000000000000;
1: out = {in[63:56], 56'h01000000000000};
2: out = {in[63:48], 48'h010000000000};
3: out = {in[63:40], 40'h0100000000};
4: out = {in[63:32], 32'h01000000};
5: out = {in[63:24]... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/utils/generic_regs/src/generic_cntr_regs.v | 12,168 | module MODULE1
parameter VAR58 = 2,
parameter VAR32 = 0, parameter VAR20 = 5, parameter VAR40 = 8, parameter VAR5 = 0, parameter VAR8 = 1, parameter VAR47 = 8, parameter VAR16 = VAR64, parameter VAR3 = 0,
parameter VAR62 = VAR5 + VAR40, parameter VAR21 = VAR5 * VAR8, parameter VAR17 = VAR62 * VAR8 )
(
input VAR66,
inpu... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_RVT_SS_210930.v | 242,184 | module MODULE1 (VAR13, VAR1, VAR9, VAR3, VAR5, VAR6);
output VAR13;
input VAR1, VAR9, VAR3, VAR5, VAR6;
wire VAR11, VAR10, VAR8;
wire VAR12, VAR2, VAR4;
wire VAR7;
not (VAR2, VAR6);
not (VAR12, VAR5);
not (VAR8, VAR3);
and (VAR4, VAR8, VAR12);
not (VAR10, VAR9);
not (VAR11, VAR1);
and (VAR7, VAR11, VAR10, VAR12);
or (V... | bsd-3-clause |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_cpu_jtag_debug_module_sysclk.v | 6,785 | module MODULE1 (
clk,
VAR28,
VAR20,
VAR3,
VAR19,
VAR12,
VAR21,
VAR27,
VAR33,
VAR16,
VAR7,
VAR31,
VAR29,
VAR11,
VAR5,
VAR25,
VAR1,
VAR26,
VAR8
)
;
output [ 37: 0] VAR12;
output VAR21;
output VAR27;
output VAR33;
output VAR16;
output VAR7;
output VAR31;
output VAR29;
output VAR11;
output VAR5;
output VAR25;
output VAR1;
... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_hstl_drv.v | 2,942 | module MODULE1(
VAR10,
VAR7, VAR8, VAR6, VAR11,
VAR3, VAR4, VAR9, VAR2, VAR5 );
output VAR10;
input [8:1] VAR9;
input [8:1] VAR2;
input VAR7;
input VAR8;
input VAR6;
input VAR11;
input VAR3;
input VAR4;
inout VAR5;
reg out;
always @(VAR4 or VAR3 or VAR6 or VAR8 or VAR11
or VAR7) begin
if (VAR11 == 1'b1) out = 1'VAR1;
e... | gpl-2.0 |
origintfj/riscv | rv32i/rtl/merlin_int_regs.v | 2,251 | module MODULE1
(
input wire VAR5,
input wire VAR11,
input wire VAR4,
input wire [4:0] VAR17,
input wire [VAR13-1:0] VAR10,
input wire VAR9,
input wire [4:0] VAR8,
input wire [VAR13-1:0] VAR6,
input wire VAR3,
input wire [4:0] VAR14,
output reg [VAR13-1:0] VAR1,
input wire VAR15,
input wire [4:0] VAR12,
output reg [VAR1... | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/jtag_master/jtag_master_core.v | 12,259 | module MODULE1 #(
parameter VAR65 = 16,
parameter VAR40 = 16
) (
input wire VAR66,
input wire VAR24,
input wire [VAR65-1:0] VAR9,
input wire [7:0] VAR58,
input wire VAR82,
input wire VAR33,
output reg [7:0] VAR78,
input wire VAR56,
output wire VAR22, input wire VAR96, output reg VAR97, output reg VAR5,
output reg VAR23... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a_4.v | 2,317 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR8,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR8;
input VAR7;
VAR9 VAR4 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODUL... | apache-2.0 |
jobisoft/jTDC | modules/output_shaper.v | 3,689 | module MODULE2 (
input wire VAR3,
input wire [3:0] VAR15,
input wire [3:0] VAR13,
input wire VAR19,
output wire pulse,
input wire reset);
wire VAR1;
MODULE1 MODULE1 (
.VAR3(VAR3 && ~VAR1),
.VAR15(VAR15),
.VAR13(VAR13),
.VAR19(VAR19),
.pulse(pulse),
.reset(reset),
.VAR1(VAR1));
endmodule
module MODULE1 (
input wire VAR3... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.functional.pp.v | 1,611 | module MODULE1( VAR13, VAR14, VAR1, VAR4, VAR18, VAR5 );
input VAR14, VAR13, VAR1;
inout VAR18, VAR5;
output VAR4;
wire VAR8;
not VAR2( VAR8, VAR1 );
wire VAR7;
and VAR17( VAR7, VAR8, VAR14, VAR13 );
wire VAR20;
not VAR11( VAR20, VAR13 );
wire VAR9;
and VAR10( VAR9, VAR20, VAR14, VAR1 );
wire VAR16;
not VAR21( VAR16, V... | apache-2.0 |
plindstroem/oh | emailbox/hdl/emailbox.v | 5,375 | module MODULE1 (
VAR14, VAR17, VAR24,
reset, VAR25, VAR22, VAR23, VAR7, VAR15, VAR19,
VAR32, VAR35
);
parameter VAR2 = 32; parameter VAR18 = 32; parameter VAR8 = 104; parameter VAR9 = 6; parameter VAR20 = 12'h000;
parameter VAR34 = 104;
parameter VAR37 = 16;
input reset; input VAR25; input VAR22;
input VAR23;
input [VA... | gpl-3.0 |
OpenSoCPlus/hight_crypto_core | rtl/SKG.v | 15,828 | module MODULE1(
VAR20 ,
VAR13 ,
VAR1 ,
VAR8 ,
VAR17 ,
VAR2 ,
VAR5
);
input VAR20 ;
input[4:0] VAR13 ;
input[127:0] VAR1 ;
output[7:0] VAR8 ;
output[7:0] VAR17 ;
output[7:0] VAR2 ;
output[7:0] VAR5 ;
wire[7:0] VAR31 = VAR1[127:120];
wire[7:0] VAR19 = VAR1[119:112];
wire[7:0] VAR14 = VAR1[111:104];
wire[7:0] VAR34 = VAR1... | lgpl-2.1 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/3ff41c2a70d99e06/mul16_16_stub.v | 1,311 | module MODULE1(VAR2, VAR1, VAR3, VAR4)
;
input VAR2;
input [15:0]VAR1;
input [15:0]VAR3;
output [15:0]VAR4;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.pp.symbol.v | 1,347 | module MODULE1 (
input VAR8 ,
input VAR2 ,
output VAR7 ,
input VAR6 ,
input VAR3 ,
input VAR4,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.functional.pp.v | 1,066 | module MODULE1( VAR3, VAR9, VAR2, VAR10, VAR1 );
input VAR2, VAR3;
inout VAR10, VAR1;
output VAR9;
wire VAR6;
not VAR4( VAR6, VAR2 );
wire VAR8;
not VAR5( VAR8, VAR3 );
and VAR7( VAR9, VAR6, VAR8 );
endmodule | apache-2.0 |
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