repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio/sky130_fd_io__top_sio.functional.pp.v | 9,475 | module MODULE1 (VAR4, VAR57, VAR41, VAR64, VAR15, VAR19, VAR49,
VAR5, VAR36, VAR11, VAR63, VAR66, VAR52, VAR44, VAR58,
VAR9, VAR8, VAR62, VAR55, VAR31,
VAR22
,VAR7, VAR59, VAR42, VAR24, VAR20, VAR32, VAR68
);
output VAR4;
inout VAR57;
inout VAR41;
input [2:0] VAR64;
input VAR15;
input VAR19;
output VAR49;
input VAR5;
i... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/CLK_DIV2.v | 3,529 | module MODULE1 (
input VAR3,
input VAR2,
output reg VAR1
);
always @ (posedge VAR2 or posedge VAR3)
if (VAR3)
VAR1 <=0;
else
VAR1 <=!VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.pp.blackbox.v | 3,314 | module MODULE1 (
VAR5 ,
VAR21 ,
VAR19 ,
VAR13 ,
VAR4 ,
VAR3 ,
VAR37,
VAR24 ,
VAR7 ,
VAR30 ,
VAR27 ,
VAR12 ,
VAR32 ,
VAR22 ,
VAR17 ,
VAR28 ,
VAR36 ,
VAR10 ,
VAR16 ,
VAR20 ,
VAR33 ,
VAR29 ,
VAR6 ,
VAR9 ,
VAR34 ,
VAR26 ,
VAR35 ,
VAR25 ,
VAR8 ,
VAR31 ,
VAR11 ,
VAR14 ,
VAR23 ,
VAR1 ,
VAR15 ,
VAR18 ,
VAR2
);
input VAR5 ;
inp... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_eclbyplog_rs1.v | 7,785 | module MODULE1 (
VAR54, VAR14, VAR42, VAR47,
VAR28, VAR55, VAR22,
VAR8, VAR58, VAR48,
VAR50, VAR52,
VAR44, VAR1,
VAR7, VAR4,
VAR59, VAR62,
VAR61,
VAR23, VAR63, VAR51, VAR29, VAR32, VAR11, VAR26,
VAR18, VAR17, VAR39, VAR19,
VAR36, VAR43, VAR3, VAR57,
VAR5, VAR2, VAR25, VAR12,
VAR34, VAR10, VAR35, VAR37,
VAR13
) ;
input ... | gpl-2.0 |
ridecore/ridecore | src/fpga/reorderbuf.v | 5,028 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR49,
input wire [VAR40-1:0] VAR42,
input wire [VAR64-1:0] VAR25,
input wire VAR32,
input wire VAR15,
input wire [VAR45-1:0] VAR4,
input wire [VAR48-1:0] VAR38,
input wire VAR62,
input wire VAR39,
input wire [VAR40-1:0] VAR60,
input wire [VAR64-1:0] VAR55,
... | bsd-3-clause |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_button_pio.v | 3,760 | module MODULE1 (
address,
VAR10,
clk,
VAR5,
VAR2,
VAR14,
VAR11,
irq,
VAR3
)
;
output irq;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR10;
input clk;
input [ 1: 0] VAR5;
input VAR2;
input VAR14;
input [ 31: 0] VAR11;
wire VAR8;
reg [ 1: 0] VAR9;
reg [ 1: 0] VAR12;
wire [ 1: 0] VAR15;
reg [ 1: 0] VAR1;
wire VAR... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_tielo.v | 1,630 | if (VAR4 && (VAR8==VAR3)) \
begin: VAR2 \
VAR15 VAR14 (.VAR6); \
end
module MODULE1 #(parameter VAR1(VAR8)
, parameter VAR4=1
)
(output [VAR8-1:0] VAR6
);
begin :VAR5
assign VAR6 = { VAR8 {1'b0} };
end
VAR13 assert(VAR4==0) else ("## %VAR16 VAR11 VAR7 VAR12 VAR9 VAR10 VAR2");
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a_4.v | 2,322 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR5 ,
VAR4 ,
VAR1 ,
VAR6,
VAR7,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR7;
input VAR2 ;
input VAR8 ;
VAR11 VAR9 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_iwb_biu.v | 15,504 | module MODULE1(
clk, rst, VAR9,
VAR31, VAR28, VAR24, VAR27, VAR46, VAR16,
VAR47, VAR29, VAR49, VAR11, VAR10, VAR1,
VAR42,
VAR13, VAR20,
VAR41, VAR6, VAR30, VAR2, VAR23, VAR43, VAR25,
VAR32, VAR3, VAR18
);
parameter VAR45 = VAR33;
parameter VAR38 = VAR33;
input clk; input rst; input [1:0] VAR9;
input VAR31; input VAR28;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.behavioral.pp.v | 1,186 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/bram_common.v | 8,107 | module MODULE1 #
(
parameter VAR59 = 16,
parameter VAR41 = 13,
parameter VAR52 = 3,
parameter VAR19 = 1,
parameter VAR48 = 0,
parameter VAR42 = 0,
parameter VAR75 = 0,
parameter VAR44 = 1 )
(
input VAR55, input VAR13, input VAR76, input [63:0] VAR61, output [63:0] VAR33, input [VAR41 - 1:0] VAR45, input VAR46, input VA... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ip_top/iodelay_ctrl.v | 7,545 | module MODULE1 #
(
parameter VAR27 = 100, parameter VAR34 = "VAR33", parameter VAR7 = "VAR30", parameter VAR20 = 1 )
(
input VAR6,
input VAR10,
input VAR37,
input VAR18,
output VAR31
);
localparam VAR5 = 15;
wire VAR29;
wire VAR3;
wire VAR17;
reg [VAR5-1:0] VAR24 ;
wire VAR8;
wire VAR23;
assign VAR23 = VAR20 ? ~VAR18: ... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/yacc/shifter.v | 6,135 | module
MODULE1(input [31:0] VAR10,
output reg [31:0] VAR8,
input [1:0] VAR3,
input [4:0] VAR1);
localparam [1:0] VAR5=VAR2,
VAR7=VAR4,
VAR6=VAR9;
always @ (*) begin if (!VAR3[1] ) begin
case (VAR1[4:0] )
5'b00000: VAR8=VAR10;
5'b00001: VAR8={VAR10[30:0],1'b0};
5'b00010: VAR8={VAR10[29:0],2'b00};
5'b00011: VAR8={VAR10[2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.pp.blackbox.v | 1,306 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR4 ,
VAR1,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/system_mm_interconnect_1.v | 16,432 | module MODULE1 (
input wire VAR93, input wire VAR85, input wire [29:0] VAR103, output wire VAR86, input wire [0:0] VAR91, input wire [7:0] VAR23, input wire VAR3, output wire [63:0] VAR75, output wire VAR48, input wire VAR88, input wire [63:0] VAR4, input wire VAR96, output wire [3:0] VAR60, output wire VAR7, output wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b_2.v | 2,127 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR6 ,
VAR8,
VAR2,
VAR5 ,
VAR7
);
output VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR5 ;
input VAR7 ;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR9 ,
VAR3 ,
VAR6
);
output VAR9... | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/synth/axi_traffic_gen_0.v | 15,178 | module MODULE1 (
VAR36,
VAR186,
VAR99,
VAR134,
VAR104,
VAR272,
VAR296,
VAR74,
VAR240,
VAR204,
VAR270,
VAR295,
VAR263,
VAR15,
VAR32
);
input wire VAR36;
input wire VAR186;
output wire [31 : 0] VAR99;
output wire [2 : 0] VAR134;
output wire VAR104;
input wire VAR272;
output wire [31 : 0] VAR296;
output wire [3 : 0] VAR74... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_statisticalInformation_1.v | 2,313 | module MODULE1 (
address,
VAR6,
clk,
VAR1,
VAR4,
VAR3,
VAR2,
VAR8
)
;
output [ 7: 0] VAR2;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR1;
input VAR4;
input [ 31: 0] VAR3;
wire VAR7;
reg [ 7: 0] VAR9;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR5;
wire [ 31: 0] VAR8;
assign VAR7 = 1;
assign VAR5 ... | gpl-3.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/sync_block.v | 3,601 | module MODULE1 #(
parameter VAR8 = 2'b00
)
(
input clk, input VAR5, output VAR9 );
wire VAR3;
wire VAR12;
VAR4 #(
.VAR10 (VAR8[0])
) VAR6 (
.VAR1 (clk),
.VAR11 (VAR5),
.VAR2 (VAR3)
);
VAR4 #(
.VAR10 (VAR8[1])
) VAR7 (
.VAR1 (clk),
.VAR11 (VAR3),
.VAR2 (VAR12)
);
assign VAR9 = VAR12;
endmodule | mit |
Rmin1995/NoC | mux1024to1.v | 55,011 | module MODULE1(output [0:VAR5-1]VAR3,
input [0:9]select,
input [0:VAR2-1]VAR4
);
genvar VAR1;
assign VAR3 = (
select[0:9] == 10'd0 ? VAR6[0] :
select[0:9] == 10'd1 ? VAR6[1] :
select[0:9] == 10'd2 ? VAR6[2] :
select[0:9] == 10'd3 ? VAR6[3] :
select[0:9] == 10'd4 ? VAR6[4] :
select[0:9] == 10'd5 ? VAR6[5] :
select[0:9] ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.functional.v | 1,778 | module MODULE1( VAR18, VAR21, VAR4, VAR5, VAR6 );
input VAR6, VAR5, VAR21, VAR18;
output VAR4;
wire VAR14;
not VAR3( VAR14, VAR6 );
wire VAR1;
not VAR2( VAR1, VAR21 );
wire VAR10;
and VAR8( VAR10, VAR14, VAR1 );
wire VAR16;
not VAR22( VAR16, VAR18 );
wire VAR7;
and VAR20( VAR7, VAR14, VAR16 );
wire VAR19;
not VAR15( VA... | apache-2.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/LUT_SHIFT.v | 2,010 | module MODULE1 #(parameter VAR5 = 5) (
input wire VAR3,
input wire VAR2,
input wire [4:0] VAR1,
output reg [VAR5-1:0] VAR4
);
always @(posedge VAR3)
if (VAR2)
case (VAR1)
5'b00000: VAR4 <= 5'b00001;
5'b00001: VAR4 <= 5'b00010;
5'b00010: VAR4 <= 5'b00011;
5'b00011: VAR4 <= 5'b00100;
5'b00100: VAR4 <= 5'b00100;
5'b00101:... | gpl-3.0 |
nlsynth/nli | lib/fp/fp16bmul.v | 1,808 | module MODULE1(
input clk,
input rst,
input [15:0] VAR20,
input [15:0] VAR19,
output VAR9,
output [7:0] VAR25,
output [7:0] VAR13,
output [8:0] VAR27);
wire VAR8;
wire VAR14;
wire [7:0] VAR16;
wire [7:0] VAR6;
wire [6:0] VAR24;
wire [6:0] VAR26;
wire [7:0] VAR15;
wire [7:0] VAR18;
wire [15:0] VAR10;
wire [8:0] VAR7;
as... | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_circular_packetizer_v1_0/axis_circular_packetizer.v | 4,218 | module MODULE1 #
(
parameter integer VAR13 = 32,
parameter integer VAR14 = 32,
parameter VAR29 = "VAR19",
parameter VAR21 = "VAR19"
)
(
input wire VAR20,
input wire VAR3,
input wire [VAR14-1:0] VAR30,
output wire [VAR14-1:0] VAR31,
input wire VAR7,
output wire VAR12,
output wire VAR33,
output wire VAR15,
input wire [VA... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.behavioral.pp.v | 1,160 | module MODULE1 ( VAR14, VAR12, VAR4
, VAR16, VAR7, VAR3, VAR5,VAR9, VAR13, VAR10, VAR15, VAR6, VAR17, VAR8, VAR11, VAR2, VAR1
);
inout VAR14;
inout VAR12;
inout VAR4;
inout VAR3;
inout VAR7;
inout VAR5;
inout VAR16;
inout VAR17;
inout VAR15;
inout VAR13;
inout VAR8;
inout VAR10;
inout VAR6;
inout VAR9;
inout VAR2;
inou... | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/mips/PC_Next.v | 1,184 | module MODULE1
(
clk,
rst,
VAR5,
VAR6,
VAR7,
VAR3,
VAR2,
VAR8
);
input clk;
input rst;
input [31:2] VAR5;
input VAR6;
input [25:0] VAR7;
input [1:0] VAR3;
output [31:2] VAR2;
output [31:2] VAR8;
reg [31:2] VAR4;
reg [31:2] VAR9;
assign VAR2=VAR4;
assign VAR8=VAR4+1;
wire [31:2] VAR1;
assign VAR1 = VAR4+{{14{VAR7[15]}},... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.behavioral.pp.v | 2,199 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR20 ,
VAR2 ,
VAR15 ,
VAR7 ,
VAR11,
VAR4,
VAR3 ,
VAR10
);
output VAR8 ;
input VAR1 ;
input VAR20 ;
input VAR2 ;
input VAR15 ;
input VAR7 ;
input VAR11;
input VAR4;
input VAR3 ;
input VAR10 ;
wire VAR16 ;
wire VAR18 ;
wire VAR14 ;
wire VAR6;
or VAR12 (VAR16 , VAR15, VAR2 );
or VAR5 (VAR18... | apache-2.0 |
tanelikaivola/blinkenlichten | fpga/asic.v | 7,357 | module MODULE1(
input VAR1,
input VAR5,
input [2:0] VAR3,
output [3:0] VAR2,
output VAR4,
output [255:0] VAR6,
output [7:0] VAR7
);
nand(VAR4,VAR6[240],VAR6[242]);
nand(VAR2[0],VAR6[9],VAR6[9]);
nand(VAR2[1],VAR6[8],VAR6[8]);
nand(VAR2[2],VAR6[6],VAR6[6]);
nand(VAR2[3],VAR6[2],VAR6[2]);
nand(VAR6[0],VAR5,VAR5);
nand(VA... | mit |
silent-observer/RCPU | CPU/source/InstrROM.v | 6,872 | module MODULE1 (
address,
VAR31,
VAR9);
input [9:0] address;
input VAR31;
output [15:0] VAR9;
tri1 VAR31;
wire [15:0] VAR37;
wire [15:0] VAR9 = VAR37[15:0];
VAR10 VAR51 (
.VAR52 (address),
.VAR48 (VAR31),
.VAR45 (VAR37),
.VAR33 (1'b0),
.VAR3 (1'b0),
.VAR49 (1'b1),
.VAR8 (1'b0),
.VAR19 (1'b0),
.VAR41 (1'b1),
.VAR29 (1'b... | mit |
freecores/altor32 | rtl/cpu/altor32_regfile_alt.v | 5,547 | module MODULE1
(
input VAR42 ,
input VAR24 ,
input VAR20 ,
input [4:0] VAR41 ,
input [4:0] VAR34 ,
input [4:0] VAR36 ,
output reg [31:0] VAR21 ,
output reg [31:0] VAR30 ,
input [31:0] VAR19
);
parameter VAR32 = "VAR33";
wire VAR39;
wire [31:0] VAR3;
wire [31:0] VAR16;
wire VAR13;
reg [4:0] VAR14;
reg [31:0] VAR10;
wire... | lgpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_altpll_0.v | 10,346 | module MODULE1
(
VAR8,
VAR4,
VAR9,
VAR7) ;
input VAR8;
input VAR4;
input [0:0] VAR9;
output [0:0] VAR7;
tri0 VAR8;
tri1 VAR4;
reg [0:0] VAR10;
reg [0:0] VAR5;
reg [0:0] VAR3;
wire VAR1;
wire VAR2;
wire VAR6; | gpl-2.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v | 6,164 | module MODULE1 #(
parameter VAR25 = 34,
parameter VAR14 = 0,
parameter VAR9 = 34,
parameter VAR5 = 0,
parameter VAR24 = 0,
parameter VAR18 = 0,
parameter VAR12 = 1,
parameter VAR23 = 1,
parameter VAR15 = 0,
parameter VAR13 = 34,
parameter VAR10 = 0,
parameter VAR16 = 1,
parameter VAR3 = 0,
parameter VAR22 = 1,
paramete... | mit |
545/Atari7800 | maria/maria.srcs/sources_1/ip/clock_divider/clock_divider_clk_wiz.v | 6,303 | module MODULE1
( input VAR58,
output VAR70,
output VAR54,
output VAR27,
input reset,
output VAR44
);
VAR68 VAR55
(.VAR7 (VAR20),
.VAR34 (VAR58));
wire [15:0] VAR31;
wire VAR40;
wire VAR29;
wire VAR49;
wire VAR13;
wire VAR32;
wire VAR64;
wire VAR47;
wire VAR33;
wire VAR53;
wire VAR63;
wire VAR60;
wire VAR4;
wire VAR5;
V... | gpl-2.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/Verilog_Xilinx_Port/sources/hdl/main_pll.v | 3,244 | module MODULE1(VAR49,
VAR34,
VAR20,
VAR32,
VAR48,
VAR19,
VAR70,
VAR10,
VAR52);
input VAR49;
input VAR34;
input VAR20;
input VAR32;
output VAR48;
output VAR19;
output VAR70;
output VAR10;
output VAR52;
wire VAR67;
wire VAR56;
wire VAR37;
wire VAR24;
wire VAR12;
wire VAR71;
wire VAR18;
assign VAR71 = 0;
assign VAR18 = 1;... | gpl-3.0 |
jakubfi/mera400f | src/t.v | 1,150 | module MODULE1(
input VAR8,
input 0t,
input VAR2,
input VAR1,
input VAR5,
input VAR6,
input VAR4,
input VAR3,
input VAR9,
input [0:39] VAR10,
input VAR7,
output reg [-1:39] MODULE1
);
always @ (posedge VAR8, posedge 0t) begin
if (0t) MODULE1[0:15] <= 0;
end
else if (VAR6) case ({~VAR1, ~VAR2})
2'b00: MODULE1[0:15] <= M... | gpl-2.0 |
hhuang25/uwaterloo_ece224 | ANT - Copy/lcd_display.v | 2,035 | module MODULE1 (
address,
VAR4,
read,
write,
VAR7,
VAR2,
VAR6,
VAR5,
VAR3,
VAR8
)
;
output VAR2;
output VAR6;
output VAR5;
inout [ 7: 0] VAR3;
output [ 7: 0] VAR8;
input [ 1: 0] address;
input VAR4;
input read;
input write;
input [ 7: 0] VAR7;
wire VAR2;
wire VAR6;
wire VAR5;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR8;
assig... | mit |
lsnow/mips32 | decode.v | 12,159 | module MODULE1(
clk, VAR34, VAR58, VAR26, VAR11, VAR17,
VAR115, VAR116, VAR75,VAR78,VAR46,VAR4,VAR18,VAR2, VAR69,VAR28, VAR41, VAR113, VAR105, rd,
VAR44, VAR21, VAR112, VAR72, VAR99, VAR66, VAR23, VAR35, VAR16, VAR40, VAR114, VAR6);
input clk;
input VAR34;
input [31:0] VAR58;
reg [31:0] VAR68;
input [31:0] VAR26, VAR11... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab0-1v2/fsm.v | 1,588 | module MODULE1(VAR6, VAR5, clk, reset, VAR3);
input wire VAR6, clk, reset;
output wire VAR5;
output wire [2:0] VAR3;
reg [2:0] VAR10;
reg [2:0] VAR12;
localparam VAR11 = 3'b000,
VAR13 = 3'b001,
VAR9 = 3'b010,
VAR1 = 3'b011,
VAR2 = 3'b100,
VAR4 = 3'b101,
VAR8 = 3'b110,
VAR7 = 3'b111;
always @(posedge clk) begin
if (rese... | mit |
marqs85/ossc | rtl/ir_rcv.v | 5,867 | module MODULE1 (
input VAR8,
input VAR3,
input VAR11,
output reg [15:0] VAR14,
output reg VAR20,
output reg [7:0] VAR5
);
parameter VAR23 = 200000; parameter VAR15 = 100000; parameter VAR22 = 160000; parameter VAR7 = 54000; parameter VAR13 = 3240000; parameter VAR19 = 27000; parameter VAR12 = 7628; parameter VAR16 = 14... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/dev_tx_cmd_fifo.v | 9,581 | module MODULE1 # (
parameter VAR64 = 30,
parameter VAR55 = 4
)
(
input VAR24,
input VAR13,
input VAR67,
input [VAR64-1:0] VAR51,
output VAR27,
input VAR18,
input VAR52,
input VAR59,
output [VAR64-1:0] VAR14,
output VAR9
);
localparam VAR12 = 1;
localparam VAR21 = 3'b001;
localparam VAR58 = 3'b010;
localparam VAR7 = 3'b... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR9 ,
input VAR3 ,
output VAR2 ,
input VAR5 ,
input VAR4,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
marqs85/de2-vd | rtl/linebuf.v | 9,189 | module MODULE1 (
VAR39,
VAR43,
VAR13,
VAR40,
VAR32,
VAR41,
VAR17);
input [23:0] VAR39;
input [11:0] VAR43;
input VAR13;
input [11:0] VAR40;
input VAR32;
input VAR41;
output [23:0] VAR17;
tri1 VAR32;
tri0 VAR41;
wire [23:0] VAR3;
wire [23:0] VAR17 = VAR3[23:0];
VAR33 VAR58 (
.VAR34 (VAR40),
.VAR4 (VAR43),
.VAR14 (VAR32)... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/pcie_data_sender.v | 4,415 | module MODULE1 #(parameter VAR22 = 128, VAR7 = 8) (
input clk,
input rst,
output VAR19,
input VAR4,
input[7:0] VAR27,
output VAR8,
input VAR1,
output VAR11,
output[VAR16 - 1:0] VAR9,
output[30:0] VAR5,
output[VAR22 - 1:0] VAR24,
output reg VAR26,
input VAR14,
input[VAR16 - 1:0] VAR10,
output VAR6,
input en
);
localpara... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/HPS/HPS_bb.v | 2,103 | module MODULE1 (
VAR24,
VAR11,
VAR3,
VAR27,
VAR34,
VAR21,
VAR25,
VAR4,
VAR26,
VAR9,
VAR30,
VAR36,
VAR32,
VAR31,
VAR17,
VAR5,
VAR6,
VAR22,
VAR20,
VAR7,
VAR14,
VAR8,
VAR16,
VAR29,
VAR12,
VAR19,
VAR33,
VAR2,
VAR15,
VAR10,
VAR35,
VAR28,
VAR23,
VAR13,
VAR18,
VAR1);
output [14:0] VAR24;
output [2:0] VAR11;
output VAR3;
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.symbol.v | 1,339 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.pp.blackbox.v | 1,374 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR4 ,
VAR2 ,
VAR7,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR7;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn.pp.symbol.v | 1,341 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR2,
input VAR1 ,
input VAR4 ,
input VAR7 ,
input VAR3
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/lsu_non_aligned_write.v | 11,877 | module MODULE1
(
clk, VAR4, reset, VAR22, VAR75, VAR25, VAR56, VAR38, VAR1, VAR41,
VAR20, VAR36, VAR57, VAR43, VAR60, VAR21, VAR65,
VAR70, VAR17
);
parameter VAR42=32; parameter VAR35=4; parameter VAR67=32; parameter VAR18=2; parameter VAR62=32; parameter VAR31=32;
parameter VAR68=6; parameter VAR16=0; parameter VAR27=... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_gtp_pipe_rate.v | 16,176 | module MODULE1 #
(
parameter VAR22 = "VAR25", parameter VAR39 = 4'd15
)
(
input VAR34,
input VAR10,
input [ 1:0] VAR50,
input VAR18,
input VAR9,
input VAR55,
input VAR12,
input VAR17,
input VAR48,
output VAR23,
output VAR4,
output VAR29,
output [ 2:0] VAR46,
output VAR11,
output VAR33,
output VAR6,
output [ 4:0] VAR54
... | lgpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/msu.v | 5,513 | module MODULE1(
input VAR16,
input enable,
input [13:0] VAR41,
input [7:0] VAR12,
input VAR14,
input [2:0] VAR46,
input [7:0] VAR9,
output [7:0] VAR11,
input VAR39,
input VAR5,
input VAR23,
output [7:0] VAR4,
output [7:0] VAR22,
output VAR45,
output [31:0] VAR36,
output [15:0] VAR27,
input [5:0] VAR10,
input [5:0] VAR3... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/up_hdmi_tx.v | 12,180 | module MODULE1 #(
parameter VAR44 = 0) (
input VAR87,
output VAR62,
output VAR31,
output VAR82,
output [ 1:0] VAR81,
output [23:0] VAR26,
output [15:0] VAR28,
output [15:0] VAR3,
output [15:0] VAR22,
output [15:0] VAR8,
output [15:0] VAR43,
output [15:0] VAR80,
output [15:0] VAR61,
output [15:0] VAR27,
output [15:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai.pp.blackbox.v | 1,340 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR7 ,
VAR4 ,
VAR2 ,
VAR6,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.functional.pp.v | 1,988 | module MODULE1 (
VAR16 ,
VAR12 ,
VAR13 ,
VAR11 ,
VAR3 ,
VAR6,
VAR15,
VAR17 ,
VAR9
);
output VAR16 ;
input VAR12 ;
input VAR13 ;
input VAR11 ;
input VAR3 ;
input VAR6;
input VAR15;
input VAR17 ;
input VAR9 ;
wire VAR2 ;
wire VAR4 ;
wire VAR5;
not VAR7 (VAR2 , VAR12 );
and VAR1 (VAR4 , VAR2, VAR13, VAR11, VAR3 );
VAR8 VA... | apache-2.0 |
ThotIP/async_fifo | src/vlog/wptr_full.v | 2,702 | module MODULE1
parameter VAR1 = 4
)(
input wire VAR13,
input wire VAR11,
input wire VAR6,
input wire [VAR1 :0] VAR4,
output reg VAR2,
output reg VAR15,
output wire [VAR1-1:0] VAR8,
output reg [VAR1 :0] VAR7
);
reg [VAR1:0] VAR5;
wire [VAR1:0] VAR3, VAR12, VAR14;
wire VAR9, VAR10;
always @(posedge VAR13 or negedge VAR11... | apache-2.0 |
hls-fpga-machine-learning/hls-fpga-machine-learning | hls4ml/templates/vivado_accelerator/alveo/krnl_rtl_src/krnl_rtl_control_s_axi.v | 12,999 | module MODULE1
VAR2 = 6,
VAR66 = 32
)(
input wire VAR6,
input wire VAR5,
input wire VAR71,
input wire [VAR2-1:0] VAR68,
input wire VAR53,
output wire VAR21,
input wire [VAR66-1:0] VAR8,
input wire [VAR66/8-1:0] VAR72,
input wire VAR38,
output wire VAR10,
output wire [1:0] VAR20,
output wire VAR28,
input wire VAR51,
inp... | gpl-3.0 |
dingzh/piplined-MIPS-CPU | src/LAB5/eueau.v | 1,403 | module MODULE1;
reg VAR2;
reg VAR3;
reg [4:0] VAR1;
reg [4:0] VAR4;
reg [4:0] VAR6;
reg [31:0] VAR5;
reg reset;
wire [31:0] VAR10;
wire [31:0] VAR8;
VAR7 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.reset(reset),
.VAR10(VAR10),
.VAR8(VAR8)
); | gpl-3.0 |
lbl-cal/StanfordNoC | router/src/vcr_sw_alloc_wf.v | 16,096 | module MODULE1
(clk, reset, VAR92, VAR29, VAR48, VAR40,
VAR56, VAR7, VAR19, VAR26, VAR16);
parameter VAR34 = 4;
parameter VAR18 = 5;
parameter VAR73 = VAR82;
parameter VAR96 = VAR39;
parameter VAR67 = VAR77;
parameter VAR24 = VAR88;
input clk;
input reset;
input [0:VAR18-1] VAR92;
input [0:VAR18*VAR34*VAR18-1] VAR29;
i... | bsd-2-clause |
karatekid/ultrasonic-fountain | hardware/src/mojo_top.v | 2,508 | module MODULE1(
input clk,
input VAR10,
input VAR6,
output[7:0]VAR42,
output VAR29,
input VAR34,
input VAR1,
input VAR13,
output [3:0] VAR21,
input VAR50, output VAR30, input VAR24,
output VAR54, input VAR17, output VAR25, input VAR20, input VAR52, input VAR18,
input [VAR55-1:0] VAR47, output [VAR55-1:0] VAR53 );
wire ... | gpl-3.0 |
linuxbest/lzs | encode/rtl/verilog/encode_dp.v | 5,792 | module MODULE1(
VAR23, VAR28, VAR40, VAR17, VAR32,
VAR18, VAR30, VAR25, VAR4, VAR7, VAR21,
VAR11, VAR35,
clk, rst, VAR38, VAR9, VAR39, VAR37, VAR13, VAR1
);
parameter VAR8 = 20;
input clk, rst, VAR38, VAR9;
input [63:0] VAR39;
input VAR37, VAR13;
output VAR23;
output VAR28;
reg VAR28;
parameter [2:0]
VAR20 = 3'b000,
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.blackbox.v | 1,326 | module MODULE1 (
VAR1 ,
VAR7,
VAR4,
VAR3,
VAR2
);
output VAR1 ;
input VAR7;
input VAR4;
input VAR3;
input VAR2;
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
jameshegarty/rigel | platform/axi/conf.v | 6,138 | module MODULE1(
input wire VAR72,
input wire VAR29,
input wire [31:0] VAR26,
input wire [11:0] VAR79,
output wire VAR48,
input wire VAR77,
input wire [31:0] VAR74,
input wire [11:0] VAR44,
output wire VAR13,
input wire VAR56,
output wire [11:0] VAR3,
input wire VAR4,
output wire [1:0] VAR67,
output wire VAR70,
output w... | mit |
idgaf/Verilog_codes | Ex9/FrameTrans.v | 1,872 | module MODULE1(VAR7,VAR9,VAR13,VAR10,VAR11);
input VAR7;
input VAR9;
input [1:0] VAR13;
output VAR10;
output reg VAR11;
reg [31:0] VAR16;
reg VAR2;
reg [7:0] VAR6;
reg [1:0] VAR19;
reg VAR3;
reg VAR5;
wire VAR1;
parameter VAR4 = 5;
parameter VAR20 = 8'b10011011;
parameter VAR15 = 8'b10001001;
assign VAR10 = VAR2;
alway... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/Barrel_shifter_v2.v | 1,733 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR2,
input wire [VAR26-1:0] VAR30,
input wire [VAR20-1:0] VAR10,
input wire VAR11,
input wire VAR13,
output wire [VAR20-1:0] VAR8
);
wire [VAR20-1:0] VAR28[VAR26+1:0];
genvar VAR1;
VAR6 #(.VAR20(VAR20)) VAR27(
.VAR29(VAR10),
.VAR4(VAR11),
.VAR22(VAR28 [0][VAR... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_tlwidthwidget_qspi.v | 15,734 | module MODULE1(
input VAR108,
input reset,
output VAR94,
input VAR197,
input [2:0] VAR102,
input [2:0] VAR130,
input [2:0] VAR133,
input [1:0] VAR164,
input [29:0] VAR28,
input [3:0] VAR214,
input [31:0] VAR154,
input VAR10,
output VAR95,
output [2:0] VAR236,
output [1:0] VAR258,
output [2:0] VAR22,
output [1:0] VAR157... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_2.behavioral.v | 1,098 | module MODULE1( VAR1, VAR5 );
input VAR1;
output VAR5;
VAR2 VAR4(.VAR1(VAR1),.VAR5(VAR5));
VAR2 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_061.v | 1,540 | module MODULE2 (
VAR4,
VAR8
);
input [31:0] VAR4;
output [31:0]
VAR8;
wire [31:0]
VAR12,
VAR2,
VAR3,
VAR14,
VAR10,
VAR6,
VAR11,
VAR9,
VAR7;
assign VAR12 = VAR4;
assign VAR6 = VAR12 << 10;
assign VAR9 = VAR11 << 2;
assign VAR14 = VAR12 << 8;
assign VAR7 = VAR11 + VAR9;
assign VAR3 = VAR2 - VAR12;
assign VAR2 = VAR12 << ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.behavioral.pp.v | 2,044 | module MODULE1 (
VAR9 ,
VAR14 ,
VAR8 ,
VAR2 ,
VAR12 ,
VAR6,
VAR16,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR14 ;
input VAR8 ;
input VAR2 ;
input VAR12 ;
input VAR6;
input VAR16;
input VAR7 ;
input VAR4 ;
wire VAR15 ;
wire VAR1 ;
wire VAR10;
and VAR17 (VAR15 , VAR14, VAR8 );
nor VAR5 (VAR1 , VAR15, VAR2, VAR12 );
VAR11 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.behavioral.v | 1,259 | module MODULE1 ();
supply1 VAR4 ;
supply1 VAR1;
supply0 VAR2 ;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/sasc_brg.v | 1,150 | module MODULE1(
VAR7, VAR5,
clk, VAR6
);
output VAR7; output VAR5;
input clk;
input VAR6;
reg VAR7;
reg VAR5;
parameter VAR2 = 103;
reg [6:0] VAR1;
reg [1:0] VAR4;
always @ (posedge clk or negedge VAR6)
if (~VAR6)
VAR1 <= 0;
else if (VAR3)
VAR1 <= 0;
else
VAR1 <= VAR1 + 1'b1;
always @ (posedge clk or negedge VAR6)
if (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.pp.blackbox.v | 1,368 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR3,
VAR6,
VAR8 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR6;
input VAR8 ;
input VAR2 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cic_decim.v | 2,530 | module MODULE1
(input VAR20,
input reset,
input enable,
input [7:0] VAR7,
input VAR17,
input VAR13,
input [VAR2-1:0] VAR18,
output reg [VAR2-1:0] VAR4);
localparam VAR3 = VAR5 * VAR9;
wire [VAR2+VAR3-1:0] VAR19;
reg [VAR2+VAR3-1:0] VAR1 [0:VAR5-1];
reg [VAR2+VAR3-1:0] VAR15 [0:VAR5-1];
reg [VAR2+VAR3-1:0] VAR8 [0:VAR5-... | gpl-2.0 |
esonghori/TinyGarbled | circuit_synthesis/stable_match/stable_match.v | 14,705 | module MODULE1
parameter VAR65 =8,
parameter VAR33 =8,
parameter VAR43 =8,
parameter VAR57 =8
)
(
clk,
rst,
VAR44,
VAR82,
VAR8
);
function integer VAR35;
input [31:0] VAR64;
reg [31:0] VAR3;
begin
VAR3 = VAR64 - 1;
for (VAR35=0; VAR3>0; VAR35=VAR35+1)
VAR3 = VAR3>>1;
end
endfunction
localparam VAR7 = VAR35(VAR43);
loca... | gpl-3.0 |
secworks/mkmif | src/rtl/mkmif_core.v | 9,150 | module MODULE1(
input wire clk,
input wire VAR6,
output wire VAR45,
output wire VAR47,
input wire VAR7,
output wire VAR11,
input wire VAR4,
input wire VAR34,
input wire VAR8,
output wire ready,
output wire valid,
input wire [15 : 0] VAR35,
input wire [15 : 0] addr,
input wire [31 : 0] VAR33,
output wire [31 : 0] VAR40
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor2/sky130_fd_sc_hd__xor2.functional.pp.v | 1,814 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR12 ,
VAR7,
VAR11,
VAR9 ,
VAR4
);
output VAR13 ;
input VAR8 ;
input VAR12 ;
input VAR7;
input VAR11;
input VAR9 ;
input VAR4 ;
wire VAR6 ;
wire VAR2;
xor VAR5 (VAR6 , VAR12, VAR8 );
VAR10 VAR3 (VAR2, VAR6, VAR7, VAR11);
buf VAR1 (VAR13 , VAR2 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_124.v | 1,465 | module MODULE1 (
VAR11,
VAR10
);
input [31:0] VAR11;
output [31:0]
VAR10;
wire [31:0]
VAR3,
VAR6,
VAR5,
VAR13,
VAR7,
VAR4,
VAR9,
VAR8;
assign VAR3 = VAR11;
assign VAR8 = VAR9 << 2;
assign VAR9 = VAR4 - VAR7;
assign VAR4 = VAR5 << 9;
assign VAR6 = VAR3 << 2;
assign VAR13 = VAR5 << 3;
assign VAR7 = VAR5 + VAR13;
assign V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_4.behavioral.v | 1,495 | module MODULE1( VAR6, VAR2, VAR4, VAR1 );
input VAR4, VAR2, VAR1;
output VAR6;
VAR7 VAR3(.VAR6(VAR6),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR5(.VAR6(VAR6),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_m.v | 2,181 | module MODULE2 (
VAR10,
VAR7 ,
VAR1 ,
VAR3 ,
VAR2,
VAR6,
VAR9 ,
VAR5
);
output VAR10;
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR2;
input VAR6;
input VAR9 ;
input VAR5 ;
VAR8 VAR4 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2... | apache-2.0 |
grantae/uart | src/uart_clock.v | 2,002 | module MODULE1(
input VAR4,
output VAR3,
output VAR5
);
reg [14:0] VAR2 = 15'h0000;
always @(posedge VAR4) begin
VAR2 <= VAR2[13:0] + 453;
end
assign VAR5 = VAR2[14];
reg [3:0] VAR1 = 4'h0;
always @(posedge VAR4) begin
VAR1 <= (VAR5) ? VAR1 + 1'b1 : VAR1;
end
assign VAR3 = (VAR5==1'b1 && (VAR1 == 4'b1111));
endmodule | mit |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_fpga_only_master.v | 21,672 | module MODULE1 #(
parameter VAR8 = 0,
parameter VAR31 = 50000,
parameter VAR6 = 2
) (
input wire VAR5, input wire VAR27, output wire [31:0] VAR36, input wire [31:0] VAR41, output wire VAR16, output wire VAR34, output wire [31:0] VAR14, input wire VAR10, input wire VAR35, output wire [3:0] VAR7, output wire VAR26 );
wir... | gpl-3.0 |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,424 | module MODULE1(VAR5, VAR4, VAR1, VAR6, VAR3, VAR7, VAR2)
;
input VAR5;
input [0:0]VAR4;
input [18:0]VAR1;
input [3:0]VAR6;
input VAR3;
input [18:0]VAR7;
output [3:0]VAR2;
endmodule | mit |
bsteinsbo/DE1-SoC-Sound | cores/i2s/i2s_shift_out.v | 3,954 | module MODULE1 (
input clk, input VAR14, input [31:0] VAR4, input [31:0] VAR17, input VAR15, output reg VAR6,
input enable, input VAR16, input VAR7, output VAR18 );
reg VAR5;
always @(posedge clk or negedge VAR14)
begin
if (~VAR14)
begin
VAR5 <= 0;
end
else
begin
VAR5 <= VAR16;
end
end
wire VAR11 = VAR16 & ~VAR5;
wire ... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.blackbox.v | 1,228 | module MODULE1 (
VAR1,
VAR4,
VAR6,
VAR3
);
output VAR1;
input VAR4;
input VAR6;
input VAR3;
supply1 VAR2;
supply0 VAR5;
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/led_capture/captuer_tx.v | 1,055 | module MODULE1(
clk,VAR2,VAR12,VAR6,VAR7,VAR13,counter,VAR9
);
input clk;
input VAR2;
input VAR6;
input [31:0] counter;
input VAR9;
input[31:0] VAR7;
output VAR12;
output [7:0] VAR13;
reg VAR12;
reg[7:0] VAR13;
always @ (posedge clk or negedge VAR2) begin
if (!VAR2)begin
VAR12 <= 1'b1;
VAR13 <= 'VAR4;
end
else if(VAR6)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.symbol.v | 1,400 | module MODULE1 (
input VAR7 ,
output VAR4 ,
input VAR2
);
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/altera_mult_add_e9u2.v | 15,369 | module MODULE1
(
VAR69,
VAR135,
VAR227,
VAR271,
VAR280) ;
input VAR69;
input VAR135;
input [15:0] VAR227;
input [15:0] VAR271;
output [31:0] VAR280;
tri0 VAR69;
tri1 VAR135;
tri0 [15:0] VAR227;
tri0 [15:0] VAR271;
wire [31:0] VAR258;
VAR61 VAR117
(
.VAR69(VAR69),
.VAR24(),
.VAR135(VAR135),
.VAR227(VAR227),
.VAR271(VAR2... | gpl-2.0 |
open-fpga-nvm/open-nvm-source | fpga/NAND/Top_NAND.v | 36,863 | module MODULE1(
input VAR10,
input rst,
input VAR49,
output VAR105, output VAR32, output VAR68, output VAR122, output VAR25, output VAR66, output VAR93, input VAR86, output VAR6, inout [7:0] VAR28,
output VAR127,
input VAR36,
output [7:0] VAR48,
output [7:0] VAR120,
output [3:0] VAR67
);
reg [1:0] VAR15; reg [4:0] VAR7... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.symbol.v | 1,602 | module MODULE1 (
input VAR4 ,
output VAR12 ,
input VAR11 ,
input VAR2 ,
input VAR3 ,
input VAR9 ,
input VAR6
);
supply1 VAR1;
supply1 VAR8 ;
supply0 VAR10 ;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaReadDwordReg.v | 2,411 | module MODULE1
(
input wire reset, input wire VAR17, input wire VAR19, input wire [31:0] in,
input wire [11:0] VAR21, inout wire [7:0] VAR11
);
parameter VAR12 = 0;
wire [7:0] VAR3;
wire [7:0] VAR10;
wire [7:0] VAR14;
wire [7:0] VAR13;
wire VAR16 = (VAR12 == VAR21[11:4]);
wire read = VAR16 & VAR21[3];
wire enable = VAR... | gpl-2.0 |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_pi.v | 3,548 | module MODULE1 (
output [7:0] VAR76, VAR29, VAR122, VAR5, VAR50, VAR78, VAR19, VAR85,
VAR67, VAR17, VAR28, VAR89, VAR125, VAR90, VAR12, VAR66,
VAR43, VAR21, VAR101, VAR10, VAR14, VAR108, VAR44, VAR112,
VAR71, VAR46, VAR68, VAR34, VAR11, VAR63, VAR58, VAR103,
VAR106, VAR97, VAR127, VAR105, VAR109, VAR87, VAR128, VAR120,... | mit |
sh-chris110/chris | FPGA/chris/Qsys/soc_design/synthesis/submodules/soc_design_mm_interconnect_0_avalon_st_adapter_008.v | 6,176 | module MODULE1 #(
parameter VAR6 = 18,
parameter VAR3 = 0,
parameter VAR12 = 18,
parameter VAR20 = 0,
parameter VAR15 = 0,
parameter VAR10 = 0,
parameter VAR1 = 1,
parameter VAR11 = 1,
parameter VAR22 = 0,
parameter VAR5 = 18,
parameter VAR23 = 0,
parameter VAR4 = 1,
parameter VAR7 = 0,
parameter VAR13 = 1,
parameter V... | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/bram_fifo/bram_fifo_core.v | 4,902 | module MODULE1 #(
parameter VAR43 = 32'h8000,
parameter VAR28 = 95, parameter VAR36 = 5, parameter VAR41 = 32
) (
input wire VAR14,
input wire VAR1,
input wire [VAR41-1:0] VAR39,
input wire [7:0] VAR31,
input wire VAR9,
input wire VAR6,
output reg [7:0] VAR33,
input wire VAR38,
output reg [31:0] VAR5,
input wire VAR40,... | bsd-3-clause |
asicguy/gplgpu | hdl/de_temp/der_top.v | 18,280 | module MODULE1
(
input VAR63, input VAR99, input VAR141, input VAR40, input [31:0] VAR3, input [8:2] VAR59, input [8:2] VAR23, input VAR33, input [3:0] VAR100, input VAR125, input [15:0] VAR37, input [53:0] VAR84, input [4:0] VAR90, input VAR54, input VAR105, input VAR50, input VAR121, input VAR81, input VAR144, input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtn/sky130_fd_sc_hdll__sdfrtn.behavioral.pp.v | 3,017 | module MODULE1 (
VAR29 ,
VAR6 ,
VAR13 ,
VAR21 ,
VAR26 ,
VAR19,
VAR30 ,
VAR16 ,
VAR17 ,
VAR20
);
output VAR29 ;
input VAR6 ;
input VAR13 ;
input VAR21 ;
input VAR26 ;
input VAR19;
input VAR30 ;
input VAR16 ;
input VAR17 ;
input VAR20 ;
wire VAR2 ;
wire VAR31 ;
wire VAR24 ;
wire VAR18 ;
reg VAR9 ;
wire VAR15 ;
wire VAR4 ... | apache-2.0 |
eda-globetrotter/PicenoDecoders | viterbi/pipe2.v | 6,994 | module MODULE1 (in,out,VAR5,reset);
output [1:0] out;
input [1:0] in; input VAR5; input reset;
reg [1:0] out;
reg [1:0] o1; reg [1:0] o2; reg [1:0] o3; reg [1:0] o4; reg [1:0] o5; reg [1:0] o6; reg [1:0] o7; reg [1:0] VAR7; reg [1:0] VAR2; reg [1:0] o10; reg [1:0] o11; reg [1:0] o12; reg [1:0] o13; reg [1:0] o14;
reg [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.behavioral.pp.v | 1,819 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR5 ,
VAR14 ,
VAR3,
VAR9,
VAR10 ,
VAR13
);
output VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR14 ;
input VAR3;
input VAR9;
input VAR10 ;
input VAR13 ;
wire VAR12 ;
wire VAR8;
nand VAR2 (VAR12 , VAR5, VAR7, VAR14 );
VAR6 VAR11 (VAR8, VAR12, VAR3, VAR9);
buf VAR1 (VAR4 , VAR8 );
endmodule | apache-2.0 |
valkwarble/finalProject | BWIMAGE/ntsc2zbt.v | 5,770 | module MODULE1(clk, VAR3, VAR5, VAR33, din, VAR14, VAR21, VAR4, VAR9);
input clk; input VAR3; input [2:0] VAR5;
input VAR33;
input [7:0] din;
output [18:0] VAR14;
output [35:0] VAR21;
output VAR4; input VAR9;
parameter VAR19 = 10'd30;
parameter VAR8 = 10'd30;
reg [9:0] VAR25 = 0;
reg [9:0] VAR7 = 0;
reg [7:0] VAR16 = 0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.symbol.v | 1,456 | module MODULE1 (
input VAR3 ,
output VAR5 ,
output VAR1 ,
input VAR6,
input VAR9
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
megari/sd2snes | verilog/sd2snes_obc1/mcu_cmd.v | 12,203 | module MODULE1(
input clk,
input VAR43,
input VAR16,
input [7:0] VAR2,
input [7:0] VAR28,
output [2:0] VAR14,
output reg VAR42 = 0,
output VAR45,
output reg VAR52 = 0,
input VAR41,
output [7:0] VAR23,
input [7:0] VAR11,
output [7:0] VAR38,
input [31:0] VAR46,
input [2:0] VAR20,
output [23:0] VAR1,
output [23:0] VAR48,
... | gpl-2.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/configuration.v | 4,066 | module MODULE1(
input [31:0] VAR10,
input [31:0] VAR11,
input VAR18,
input VAR1,
output reg VAR14,
output reg [31:0]VAR19,
input clk,
input reset,
output reg VAR15
);
reg [2:0]VAR7,VAR17;
localparam VAR6=0,
VAR5=1;
always@(posedge clk)
if(reset)
VAR7<=0;
else VAR7<=VAR17;
always@
if(reset)
VAR14=0;
else if(VAR7==VAR5)
... | lgpl-2.1 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Add-Subt/FPU_Add_Subtract_Function.v | 12,640 | module MODULE1
parameter VAR7=26, parameter VAR31 = 5)
wire [VAR7-1:0] VAR8;
assign VAR8 = ~VAR14;
VAR34 #(.VAR7(VAR7),.VAR31(VAR31)) VAR17 (
.clk(clk),
.rst(VAR15),
.VAR20(VAR5),
.VAR33(VAR8),
.VAR3(VAR32)
);
VAR37 VAR1(
.clk(clk),
.VAR9(VAR27[1:0]),
.VAR2(VAR4),
.VAR16(VAR19),
.VAR28(VAR35)
);
VAR26 #(.VAR24(VAR24),.... | gpl-3.0 |
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