repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
cr88192/bgbtech_bjx1core | bjx1core32/MemAlu.v | 1,092 | module MODULE1(
clk,
VAR1,
VAR6,
VAR11,
VAR12,
VAR7
);
input clk;
input[2:0] VAR1;
input[31:0] VAR6;
input[31:0] VAR11;
input[31:0] VAR12;
output[31:0] VAR7;
reg[31:0] VAR13;
reg[31:0] VAR10;
parameter[2:0] VAR8 = 3'b000;
parameter[2:0] VAR15 = 3'b001;
parameter[2:0] VAR4 = 3'b010;
parameter[2:0] VAR14 = 3'b011;
parame... | mit |
masc-ucsc/cmpe220fall16 | rtl/fflop_understand.v | 2,316 | module MODULE1 (
input clk,
input reset,
input [15:0] VAR11,
input VAR35,
output VAR15,
output [15:0] VAR23,
output VAR29,
input VAR1
);
logic [15:0] VAR2;
logic VAR12;
logic VAR25;
logic [15:0] VAR17;
logic VAR19;
logic VAR7;
assign VAR2 = VAR11;
assign VAR12 = VAR35;
assign VAR15 = VAR25;
logic [15:0] VAR26;
logic VA... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_xbar_1/synth/design_1_xbar_1.v | 15,860 | module MODULE1 (
VAR111,
VAR88,
VAR41,
VAR100,
VAR85,
VAR10,
VAR40,
VAR15,
VAR7,
VAR92,
VAR93,
VAR74,
VAR1,
VAR95,
VAR16,
VAR48,
VAR12,
VAR91,
VAR37,
VAR128,
VAR26,
VAR90,
VAR51,
VAR132,
VAR42,
VAR103,
VAR98,
VAR62,
VAR78,
VAR55,
VAR120,
VAR76,
VAR35,
VAR80,
VAR22,
VAR122,
VAR27,
VAR9,
VAR101,
VAR79
);
input wire VAR11... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo.symbol.v | 1,388 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR2,
output VAR4
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/uart16550/rtl/verilog/uart_sync_flops.v | 5,666 | module MODULE1
(
VAR6,
VAR8,
VAR2,
VAR3,
VAR9,
VAR10
);
parameter VAR5 = 1;
parameter VAR7 = 1;
parameter VAR4 = 1'b0;
input VAR6; input VAR8; input VAR2; input VAR3; input [VAR7-1:0] VAR9; output [VAR7-1:0] VAR10;
reg [VAR7-1:0] VAR10;
reg [VAR7-1:0] VAR1;
always @ (posedge VAR8 or posedge VAR6)
begin
if (VAR6)
VAR1 <... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v | 2,308 | if (VAR8 == VAR6 && VAR15 == VAR33) \
begin: VAR22 \
VAR3 VAR11 \
( \
.VAR13 (VAR18 ) \
,.VAR10 (VAR24) \
,.VAR9(~(~VAR1&VAR23)) \
,.VAR31 (VAR4) \
\
,.VAR28(VAR18 ) \
,.VAR36(~(VAR1&VAR23)) \
,.VAR26(~VAR20) \
,.VAR35 (VAR24) \
,.VAR12 (VAR27) \
); \
end
module MODULE1 #(parameter VAR30(VAR15)
, parameter VAR30(VAR8)
... | bsd-3-clause |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/main.v | 2,870 | module MODULE1(VAR59, VAR5, VAR73, VAR12, VAR27, VAR75);
input VAR59;
input VAR5[3:0];
output [17:0] VAR73;
input [17:0] VAR12;
input VAR27;
output VAR75;
integer VAR37;
reg [7:0] VAR57, VAR4;
reg [10:0] VAR62[8:0];
reg [3:0] VAR52[1:0];
wire [31:0] VAR78, VAR54;
wire [7:0] VAR64, VAR36;
wire VAR71, VAR26, VAR30, VAR47... | mit |
olofk/oh | elink/hdl/esaxi.v | 17,092 | module MODULE1 (
VAR49, VAR27, VAR18, VAR11, VAR67,
VAR107, VAR78, VAR41, VAR70, VAR28,
VAR64, VAR77, VAR69, VAR98, VAR54,
VAR4,
VAR87, VAR50, VAR32, VAR57, VAR75,
VAR85, VAR72, VAR81, VAR6,
VAR86, VAR37, VAR100, VAR44,
VAR91, VAR99, VAR1, VAR35, VAR2,
VAR73, VAR48, VAR39, VAR102,
VAR40, VAR3, VAR8, VAR9,
VAR56, VAR97,... | gpl-3.0 |
ByronPhung/hardware-accelerated-dna-matching-and-variation-detection | Hardware/Verilog/Search.v | 1,721 | module MODULE1(
input VAR3,
input reset,
input [511:0] VAR19,
input [511:0] VAR20,
output reg VAR2
);
reg [511:0] VAR16;
reg [510:0] VAR22;
reg [509:0] VAR8;
reg [508:0] VAR12;
wire [63:0] VAR11, VAR14, VAR18, VAR17;
reg VAR4, VAR15, VAR9, VAR10;
reg VAR1 = 113;
reg [6:0] counter;
VAR13 VAR6
(
.VAR3(VAR3),
.VAR19(VAR16... | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/KeyboardCtrl_0/src/Ps2Interface.v | 23,076 | module MODULE1#(
parameter VAR35 = 100000000
)(
VAR56,
VAR53,
clk,
rst,
VAR18,
VAR51,
VAR4,
VAR26,
VAR2,
VAR1
);
inout VAR56, VAR53;
input clk, rst;
input [7:0] VAR18;
input VAR51;
output reg [7:0] VAR4;
output reg VAR26;
output VAR2;
output reg VAR1;
parameter VAR33 = (100*1000) / (1000000000/VAR35);
parameter VAR3 = ... | gpl-3.0 |
velizarefremov/MIPS | Part 3/Verilog Code/Program Counter/signex_param.v | 1,100 | module MODULE1
parameter VAR1 = 16,
parameter VAR6 = 0)
(output [VAR3-1:0] VAR2,
input [VAR1-1:0] in
);
localparam VAR4 = 0, VAR7 = 1;
generate
if(VAR6 == VAR4) begin :VAR8
assign VAR2[VAR3-1:0] = { {(VAR3-VAR1){in[VAR1-1]}}, in[VAR1-1:0]};
end
endgenerate
generate
if(VAR6 == VAR7) begin :VAR5
assign VAR2[VAR3-1:0] = {... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand3/sky130_fd_sc_hvl__nand3.behavioral.v | 1,391 | module MODULE1 (
VAR11,
VAR2,
VAR8,
VAR1
);
output VAR11;
input VAR2;
input VAR8;
input VAR1;
supply1 VAR10;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR7;
nand VAR4 (VAR7, VAR8, VAR2, VAR1 );
buf VAR6 (VAR11 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi.pp.symbol.v | 1,394 | module MODULE1 (
input VAR4 ,
input VAR8 ,
input VAR6,
output VAR2 ,
input VAR3 ,
input VAR7,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/KeyBoard_ctrl.v | 2,999 | module MODULE1(VAR11, VAR17, VAR1, VAR13, VAR16);
input VAR13;
input VAR16;
input [3:0] VAR1;
output [3:0] VAR11;
output [3:0] VAR17;
reg [3:0] VAR11;
reg [3:0] VAR9;
reg [3:0] VAR4;
reg [3:0] VAR6;
reg [3:0] VAR2;
reg [3:0] VAR10;
reg [3:0] VAR3;
reg [3:0] VAR12;
reg [14:0] VAR14;
reg VAR7;
wire VAR8;
wire VAR15;
wire... | mit |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syn/src/spd.v | 5,474 | module MODULE1 (VAR63, VAR41, VAR79, VAR45, VAR84, VAR17, VAR65, VAR50, out, clk, reset);
output out;
input VAR63, VAR41, VAR79, VAR45;
input [3:0] VAR84, VAR17, VAR65, VAR50;
input clk, reset;
wire out;
wire VAR75, VAR68;
wire VAR32, VAR74, VAR8, VAR49;
wire VAR51, VAR31, VAR78, VAR87;
wire VAR72, VAR33, VAR6, VAR64;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1_2.v | 1,787 | module MODULE2 (
VAR4,
VAR2
);
input VAR4;
input VAR2;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR4;
supply0 VAR2;
VAR3 VAR1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn_2.v | 2,374 | module MODULE2 (
VAR5 ,
VAR6,
VAR8 ,
VAR2 ,
VAR1 ,
VAR7 ,
VAR9 ,
VAR3
);
output VAR5 ;
input VAR6;
input VAR8 ;
input VAR2 ;
input VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR3 ;
VAR4 VAR10 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2... | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_top.v | 18,298 | module MODULE1 (
input wire VAR212,
input wire VAR248,
input wire VAR24, input wire VAR275, input wire VAR106, input wire [31:0] VAR56,
input wire [3:0] VAR200,
input wire [1:0] VAR215,
output wire [31:0] VAR186,
output wire [3:0] VAR105,
output wire VAR80,
output wire VAR224,
output wire VAR50,
output wire VAR238,
out... | isc |
cr88192/bgbtech_bjx1core | bjx1c32b/FpuFpD_Mul.v | 1,447 | module MODULE1(
clk,
enable,
VAR15,
VAR10,
VAR5
);
input clk;
input enable;
input[63:0] VAR15;
input[63:0] VAR10;
output[63:0] VAR5;
reg VAR1;
reg VAR4;
reg VAR6;
reg[12:0] VAR11;
reg[12:0] VAR7;
reg[12:0] VAR3;
reg[105:0] VAR9;
reg[105:0] VAR12;
reg[105:0] VAR14;
reg[63:0] VAR2;
reg[63:0] VAR9;
reg[63:0] VAR12;
reg[63... | mit |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/mig_v3_4.v | 26,408 | module MODULE1 #
(
parameter VAR81 = 2,
parameter VAR134 = 1,
parameter VAR94 = 2,
parameter VAR90 = 10,
parameter VAR122 = 1,
parameter VAR78 = 2,
parameter VAR92 = 0,
parameter VAR27 = 4,
parameter VAR114 = 32,
parameter VAR10 = 8,
parameter VAR39 = 4,
parameter VAR129 = 5,
parameter VAR22 = 2,
parameter VAR89 = 2,
p... | lgpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sf_camera/rtl/sf_camera_controller.v | 2,283 | module MODULE1 (
input clk,
input rst,
output VAR11,
output VAR9,
input VAR2,
output VAR12,
input VAR14,
input VAR15,
input VAR3,
input VAR4,
output VAR6,
output VAR5,
output VAR1,
output VAR10
);
VAR7 VAR16(
.clk (clk ),
.rst (rst ),
.VAR8 (VAR6 ),
.VAR13 (VAR12 )
);
assign VAR9 = (VAR14) ? VAR2:
VAR15;
assign VAR11 =... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_toggle_detect.v | 4,134 | module MODULE1
parameter VAR7=13, parameter VAR3=10 )
(
input logic clk,
input logic VAR9,
input logic valid,
input logic [VAR7-1:0] VAR2,
output logic [VAR3-1:0] VAR6[VAR7+1]
);
logic [VAR7-1:0] VAR10;
logic [VAR7-1:0] VAR11;
logic VAR8;
always@(posedge clk or negedge VAR9)
if (!VAR9)
VAR10<={VAR7{1'b0}};
else if (val... | mit |
osrf/wandrr | firmware/motor_controller/fpga/foc_cmd.v | 5,007 | module MODULE1
(input VAR56,
input VAR76,
input [31:0] VAR15,
input [31:0] VAR47,
input VAR73,
input [31:0] VAR39,
input [31:0] VAR52,
input VAR7,
input VAR45,
input [7:0] VAR1,
input VAR59,
input VAR55,
output [31:0] VAR29,
output [31:0] VAR20,
output [31:0] VAR71,
output VAR2,
output VAR30);
wire [7:0] VAR49;
wire [3... | apache-2.0 |
zKarp/Karpentium-Processor | src/verilog/Karpentium_Processor_III.v | 1,239 | module MODULE1(clk,VAR39,in,out,en);
input clk,VAR39,en;
input [15:0]in;
output [15:0]out;
reg [15:0]VAR10; reg [15:0]out;
wire [2:0]VAR4;
wire [3:0]VAR16;
wire [5:0]VAR19,VAR31,VAR9;
wire [1:0]VAR35,VAR15;
wire VAR7,VAR5,VAR3; wire [15:0]VAR38,VAR37;
wire [15:0]VAR33;
VAR23 VAR41(clk,VAR39,VAR16,VAR35,VAR7,VAR5,VAR3,V... | gpl-2.0 |
secworks/blake2 | src/rtl/blake2.v | 8,099 | module MODULE1(
input wire clk,
input wire VAR12,
input wire VAR20,
input wire VAR19,
input wire [7 : 0] address,
input wire [31 : 0] VAR22,
output wire [31 : 0] VAR17
);
localparam VAR32 = 8'h00;
localparam VAR43 = 8'h01;
localparam VAR10 = 8'h02;
localparam VAR28 = 8'h08;
localparam VAR24 = 0;
localparam VAR39 = 1;
l... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.pp.symbol.v | 1,368 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR4 ,
input VAR5 ,
output VAR1 ,
input VAR8 ,
input VAR7,
input VAR9,
input VAR2
);
endmodule | apache-2.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/vdu.v | 13,699 | module MODULE2 (
input VAR88, input VAR68, input [15:0] VAR78,
output reg [15:0] VAR79,
input [19:1] VAR42,
input VAR22,
input VAR23,
input [ 1:0] VAR34,
input VAR65,
input VAR77,
output VAR90,
output reg [ 1:0] VAR18, output reg [ 1:0] VAR86,
output reg [ 1:0] VAR4,
output reg VAR54,
output reg VAR17
);
parameter VAR5... | gpl-3.0 |
timofonic/fpga_nes | hw/src/wram.v | 2,352 | module MODULE1
(
input wire VAR10, input wire VAR6, input wire VAR9, input wire [10:0] VAR13, input wire [ 7:0] din, output wire [ 7:0] dout );
wire VAR3;
wire [7:0] VAR7;
VAR8 #(.VAR1(11),
.VAR14(8)) VAR11(
.clk(VAR10),
.VAR4(VAR3),
.VAR12(VAR13),
.VAR5(din),
.VAR2(VAR7)
);
assign VAR3 = (VAR6) ? ~VAR9 : 1'b0;
assign ... | bsd-2-clause |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_sync_flops.v | 5,761 | module MODULE1
(
VAR9,
VAR4,
VAR8,
VAR6,
VAR3,
VAR1
);
parameter VAR5 = 1;
parameter VAR2 = 1;
parameter VAR7 = 1'b0;
input VAR9; input VAR4; input VAR8; input VAR6; input [VAR2-1:0] VAR3; output [VAR2-1:0] VAR1;
reg [VAR2-1:0] VAR1;
reg [VAR2-1:0] VAR10;
always @ (posedge VAR4 or posedge VAR9)
begin
if (VAR9)
VAR10 <=... | lgpl-2.1 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/Audio_0.v | 1,569 | module MODULE1 (
input wire VAR3, output wire VAR10, output wire VAR4, output wire VAR13, output wire VAR14, input wire VAR7, input wire [15:0] VAR8, input wire VAR6, output wire [15:0] VAR15, input wire VAR12 );
VAR2 #(
.VAR9 (18432000),
.VAR11 (48000),
.VAR1 (16),
.VAR5 (2)
) VAR16 (
.VAR3 (VAR3), .VAR10 (VAR10), .VA... | gpl-3.0 |
drichmond/riffa | fpga/xilinx/kc705/KC705_Gen1x8If64/hdl/KC705_Gen1x8If64.v | 20,969 | module MODULE1
parameter VAR124 = 8,
parameter VAR178 = 64,
parameter VAR184 = 256,
parameter VAR17 = 5
)
(output [(VAR124 - 1) : 0] VAR102,
output [(VAR124 - 1) : 0] VAR29,
input [(VAR124 - 1) : 0] VAR63,
input [(VAR124 - 1) : 0] VAR171,
output [3:0] VAR93,
input VAR123,
input VAR127,
input VAR179
);
wire VAR49;
wire ... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.functional.pp.v | 1,066 | module MODULE1( VAR3, VAR2, VAR8, VAR9, VAR7 );
input VAR8, VAR2;
inout VAR9, VAR7;
output VAR3;
wire VAR10;
not VAR1( VAR10, VAR8 );
wire VAR4;
not VAR5( VAR4, VAR2 );
and VAR6( VAR3, VAR10, VAR4 );
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/FSM_upload_flit.v | 7,853 | module MODULE1( clk,
rst,
VAR36,
VAR31,
VAR26,
VAR39,
VAR37,
VAR42,
VAR28,
VAR35,
VAR17,
VAR10,
VAR11,
VAR16,
VAR15,
VAR23,
VAR22,
VAR5,
VAR18,
VAR38,
VAR13,
VAR27
);
input clk;
input rst;
input VAR31; input VAR36; input VAR26;
input VAR39;
input [15:0] VAR37;
input [3:0] VAR42;
input [1:0] VAR28;
input VAR35;
output V... | apache-2.0 |
jas0n1ee/THU-DSD | FB/ip/Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v | 3,547 | module MODULE1 ( VAR24,
VAR57,
VAR70,
VAR26,
VAR33,
VAR62,
VAR47,
VAR49, VAR13,
VAR6,
VAR29,
VAR48,
VAR41,
VAR23,
VAR30,
VAR60,
VAR43 );
parameter VAR46 = 19'h4B000;
output [15:0] VAR57;
input [15:0] VAR24;
input [18:0] VAR70;
input VAR26,VAR33,VAR62;
input VAR49,VAR47;
reg [15:0] VAR57;
output [9:0] VAR13;
output [9:0... | mit |
oceanborn-mx/sirius | src.verilog/Multiplicacion_Matricial_Hipercubica/Multiplicacion_Matricial_Hipercubica/src/hipercubo.v | 2,930 | module MODULE1 (
input VAR8, input VAR52, input[3:0] VAR84,VAR85, input[3:0] VAR24,VAR37,
input[3:0] VAR72,VAR104, input[3:0] VAR10,VAR90,
input[7:0] VAR45, input[7:0] VAR106, input[7:0] VAR87, input[7:0] VAR74, output[7:0] VAR102,VAR27, output[7:0] VAR71,VAR32
);
wire[3:0] VAR48,VAR2,VAR91,VAR98;
wire[3:0] VAR107,VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi.behavioral.pp.v | 1,977 | module MODULE1 (
VAR12,
VAR9,
VAR8 ,
VAR10 ,
VAR13 ,
VAR16 ,
VAR14 ,
VAR1
);
input VAR12;
input VAR9;
output VAR8 ;
input VAR10 ;
input VAR13 ;
input VAR16 ;
input VAR14 ;
input VAR1 ;
wire VAR14 VAR2 ;
wire VAR3 ;
wire VAR7;
and VAR5 (VAR2 , VAR16, VAR10, VAR13 );
nor VAR15 (VAR3 , VAR2, VAR14, VAR1 );
VAR6 VAR4 (VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.functional.pp.v | 2,162 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR1 ,
VAR2 ,
VAR10 ,
VAR11,
VAR17,
VAR12 ,
VAR6
);
output VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR10 ;
input VAR11;
input VAR17;
input VAR12 ;
input VAR6 ;
wire VAR13 ;
wire VAR14 ;
wire VAR18 ;
wire VAR7;
and VAR4 (VAR13 , VAR2, VAR10 );
and VAR15 (VAR14 , VAR5, VAR1 );
o... | apache-2.0 |
puroh/Procesador_monociclo | control.v | 1,482 | module MODULE1(VAR5,VAR7,clk,VAR11,VAR10,VAR4,VAR1,VAR8,VAR3,VAR2,VAR6);
input [5:0]VAR7;
input clk;
output wire VAR11;
output wire VAR10;
output wire VAR4;
output wire VAR1;
output wire [1:0]VAR8;
output wire VAR3;
output wire VAR2;
output wire VAR6;
output wire VAR5;
reg [9:0]VAR12;
always @ (*)
begin
case(VAR7)
6'b0... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and3/gf180mcu_fd_sc_mcu7t5v0__and3_4.behavioral.pp.v | 1,316 | module MODULE1( VAR3, VAR2, VAR5, VAR9, VAR8, VAR7 );
input VAR5, VAR2, VAR3;
inout VAR8, VAR7;
output VAR9;
VAR6 VAR4(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7));
VAR6 VAR1(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai.behavioral.v | 1,654 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR8 ,
VAR13
);
output VAR6 ;
input VAR12 ;
input VAR8 ;
input VAR13;
supply1 VAR4;
supply0 VAR9;
supply1 VAR10 ;
supply0 VAR15 ;
wire VAR2 ;
wire VAR5 ;
wire VAR14;
not VAR3 (VAR2 , VAR13 );
or VAR7 (VAR5 , VAR8, VAR12 );
nand VAR11 (VAR14, VAR2, VAR5 );
buf VAR1 (VAR6 , VAR14 );
endmod... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a.symbol.v | 1,386 | module MODULE1 (
input VAR8,
input VAR2,
input VAR4 ,
input VAR6 ,
output VAR1
);
supply1 VAR3;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axis_dwidth_converter_1_1/axis_infrastructure_v1_1/hdl/verilog/axis_infrastructure_v1_1_mux_enc.v | 9,826 | module MODULE1 #
(
parameter VAR22 = "VAR37",
parameter integer VAR13 = 4,
parameter integer VAR1 = 2,
parameter integer VAR18 = 1
)
(
input wire [VAR1-1:0] VAR9,
input wire [VAR13*VAR18-1:0] VAR39,
output wire [VAR18-1:0] VAR4,
input wire VAR17
);
wire [VAR18-1:0] VAR19;
genvar VAR10;
function [VAR18-1:0] VAR15
(
inpu... | bsd-2-clause |
vipinkmenon/scas | hw/fpga/source/enet_if/reset_sync.v | 3,571 | module MODULE1 #(
parameter VAR3 = 2'b11
)
(
input VAR14,
input clk,
input enable,
output VAR8
);
wire VAR7;
wire VAR5;
VAR2 #(
.VAR6 (VAR3[0])
) VAR12 (
.VAR13 (clk),
.VAR1 (enable),
.VAR10(VAR14),
.VAR9 (1'b0),
.VAR11 (VAR7)
);
VAR2 #(
.VAR6 (VAR3[1])
) VAR4 (
.VAR13 (clk),
.VAR1 (enable),
.VAR10(VAR14),
.VAR9 (VAR7)... | mit |
toyoshim/tvcl | sample/LED2_spartan-3-starterkit.v | 4,306 | module MODULE1(
VAR23,
VAR27,
VAR7,
VAR55,
VAR11,
VAR66,
VAR25,
VAR69,
VAR3,
VAR15,
VAR14,
VAR42,
VAR57,
VAR34,
VAR60,
VAR49,
VAR24,
VAR18,
VAR47,
VAR44,
VAR67,
VAR65,
VAR22,
VAR59,
VAR30,
VAR13,
VAR38,
VAR9,
VAR5,
VAR56,
VAR1,
VAR32,
VAR16,
VAR46,
VAR52,
VAR28,
VAR41,
VAR21,
VAR8);
input VAR23;
input VAR27;
output [17... | bsd-3-clause |
keith-epidev/VHDL-lib | top/lab_2/part_2/ip/clk_video/clk_video_stub.v | 1,178 | module MODULE1(VAR3, VAR2, VAR1)
;
input VAR3;
output VAR2;
output VAR1;
endmodule | gpl-2.0 |
rkrajnc/minimig-mist | rtl/soc/minimig_de1_top.v | 24,645 | module MODULE1 (
input wire [ 2-1:0] VAR74, input wire [ 2-1:0] VAR65, input wire VAR79, input wire VAR320, input wire VAR325, input wire VAR242, input wire VAR265, output wire VAR2, input wire [ 4-1:0] VAR204, input wire [ 10-1:0] VAR352, output wire [ 7-1:0] VAR267, output wire [ 7-1:0] VAR274, output wire [ 7-1:0] V... | gpl-3.0 |
dimitdim/pineapple | veriloge/ShiftRegister.v | 3,188 | module MODULE1(clk, VAR3, VAR6, VAR4, VAR1, VAR7, VAR12,VAR9);
parameter VAR10 = 8;
input clk;
input VAR3;
input VAR9;
input VAR6;
output[VAR10-1:0] VAR7;
output VAR12;
input[VAR10-1:0] VAR4;
input VAR1;
reg[VAR10-1:0] VAR5;
assign VAR12=VAR5[VAR10-1];
assign VAR7=VAR5;
always @(posedge VAR3) begin
VAR5 <= {VAR5[VAR10-... | gpl-2.0 |
sehugg/8bitworkshop | presets/verilog/framebuf_vpu.v | 4,066 | module MODULE1(clk, reset, VAR40, VAR44, VAR6, VAR23,
VAR10, VAR17, VAR25, VAR37
, output [7:0] VAR21
, output [7:0] VAR26
, output [7:0] VAR27
, output VAR16
, output VAR14
,VAR7
);
input clk, reset;
input VAR6, VAR23;
output VAR40, VAR44;
wire VAR39;
wire [8:0] VAR13;
wire [8:0] VAR34;
assign VAR27 = VAR11.VAR27;
ass... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_dma_control_slave.v | 7,795 | module MODULE1 (
clk,
reset,
address,
VAR9,
read,
write,
VAR6,
VAR11,
VAR12,
VAR8
);
parameter VAR5 = 32'h00000000;
parameter VAR10 = 32'h00000000;
parameter VAR13 = 640; parameter VAR14 = 480;
parameter VAR7 = 16'h0809;
parameter VAR16 = 4'h7; parameter VAR2 = 2'h2; parameter VAR4 = 1'b1;
input clk;
input reset;
input... | gpl-2.0 |
siamumar/TinyGarbled | circuit_synthesis/a23/a23_mem.v | 6,029 | module MODULE1
(
parameter VAR4 = 64 , parameter VAR17 = 64 , parameter VAR19 = 64 , parameter VAR15 = 64 , parameter VAR21 = 64 )
(
input VAR24,
input VAR2,
input [VAR4*32-1:0] VAR5,
input [VAR17 *32-1:0] VAR27,
input [VAR19 *32-1:0] VAR13,
output [VAR15 *32-1:0] VAR11,
input [31:0] VAR26,
input [31:0] VAR8,
input VAR... | gpl-3.0 |
darrylring/SDRdrum | fpga/rtl/framer.v | 10,192 | module MODULE1 (
input wire VAR25,
input wire VAR18,
input wire [255:0] VAR28,
input wire VAR26,
output wire VAR11,
output wire [31:0] VAR9,
output wire VAR20,
input wire VAR13,
output wire [31:0] VAR30,
output wire [3:0] VAR35,
output wire VAR29,
input wire VAR27,
input wire [1:0] VAR5,
input wire VAR4,
output wire VA... | gpl-3.0 |
jodfedlet/TrabalhosDeSistemas | TrabalhosDeSistemas/triangulo.v | 2,197 | module MODULE2(
input [11:0] VAR2,
input [11:0] VAR10,
input [11:0] VAR22,
input [11:0] VAR29,
input [11:0] VAR26,
input [11:0] VAR8,
output VAR28
);
wire signed [11:0] VAR7;
wire signed [11:0] VAR1;
wire signed [11:0] VAR20;
wire signed [11:0] VAR5;
wire signed [22:0] VAR14;
wire signed [22:0] VAR19;
wire signed [22:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.functional.pp.v | 1,971 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR6 ,
VAR12 ,
VAR11,
VAR1,
VAR10 ,
VAR9
);
output VAR14 ;
input VAR5 ;
input VAR6 ;
input VAR12 ;
input VAR11;
input VAR1;
input VAR10 ;
input VAR9 ;
wire VAR4 ;
wire VAR7 ;
wire VAR16;
not VAR15 (VAR4 , VAR5 );
nand VAR2 (VAR7 , VAR6, VAR4, VAR12 );
VAR3 VAR13 (VAR16, VAR7, VAR11, VAR1... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/txc_engine_ultrascale.v | 24,775 | module MODULE2
parameter VAR82 = 1,
parameter VAR57 = 1,
parameter VAR79 = 10,
parameter VAR21 = 256)
( input VAR118,
input VAR60, input VAR18, output VAR48,
input [VAR172-1:0] VAR4,
input VAR158,
output VAR182,
output VAR91,
output [VAR113-1:0] VAR101,
output [(VAR113/32)-1:0] VAR90,
output [VAR70-1:0] VAR99,
input VA... | gpl-3.0 |
jhennessy/parallella-hw-old | boards/archive/gen1.1/fpga/hdl/ewrapper_link_rxi.v | 22,651 | module MODULE1 (
VAR28, VAR118, VAR106, VAR115,
VAR120, VAR91, VAR52,
VAR98,
reset, VAR7, VAR30, VAR69, VAR117, VAR51
);
input reset;
input [63:0] VAR7; input VAR30; input [7:0] VAR69;
input VAR117;
input VAR51;
output VAR28;
output VAR118;
output VAR106;
output [1:0] VAR115;
output [3:0] VAR120;
output [31:0] VAR91;
o... | gpl-3.0 |
hcabrera-/lancetfish | RTL/shared/verif/packet_generator.v | 12,113 | module MODULE1 #(
parameter VAR53 = VAR29,
parameter VAR52 = 5,
parameter VAR9 = 1,
parameter VAR15 = 1,
parameter VAR49 = 2,
parameter VAR45 = 2
)();
reg VAR10 VAR17;
reg [2:0] VAR23 = 3'b000;
reg [2:0] VAR4 = 3'b000;
reg [2:0] VAR3 = 3'b000;
reg [2:0] VAR40 = 3'b000;
integer VAR39 = 0;
reg [7:0] VAR28;
task VAR18;
in... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | DIV27_19_bb.v | 3,729 | module MODULE1 (
VAR5,
VAR4,
VAR1,
VAR3,
VAR2);
input VAR5;
input [34:0] VAR4;
input [42:0] VAR1;
output [42:0] VAR3;
output [34:0] VAR2;
endmodule | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/altera_avalon_pio_171/synth/ghrd_10as066n2_dipsw_pio_altera_avalon_pio_171_67u3hiq.v | 4,794 | module MODULE1 (
address,
VAR8,
clk,
VAR10,
VAR9,
VAR13,
VAR7,
irq,
VAR6
)
;
output irq;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR8;
input clk;
input [ 3: 0] VAR10;
input VAR9;
input VAR13;
input [ 31: 0] VAR7;
wire VAR14;
reg [ 3: 0] VAR1;
reg [ 3: 0] VAR4;
wire [ 3: 0] VAR2;
reg [ 3: 0] VAR15;
wire VAR5;... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/acquire/dram_prefetch.v | 3,578 | module MODULE1
parameter VAR16 = VAR12-1,
parameter VAR9 = 3)
( input VAR19,
input VAR13,
input VAR11,
output reg VAR5 = 1'b0,
input [VAR16:0] VAR18,
input VAR14,
output reg [VAR16:0] VAR8 = {VAR12{1'b0}}
);
reg [23:0] VAR4 = 24'b0;
reg [1:0] VAR2 = VAR10;
always @(posedge VAR19)
if (VAR13)
VAR2 <= VAR10;
else
case (VA... | lgpl-3.0 |
tgiv014/ECE441_Proj3 | clock_divider.v | 1,834 | module MODULE1(clk, VAR7, VAR8, VAR4);
parameter VAR3 = 26;
parameter VAR1 = 26'd50000000;
parameter VAR9 = 15;
parameter VAR2 = 15'd25000;
input clk, VAR7;
output reg VAR8, VAR4;
reg [VAR3-1:0] VAR5; reg [VAR9-1:0] VAR6;
always @ (posedge clk or negedge VAR7)
begin
if(~VAR7) begin
VAR5 <= 0; VAR6 <= 0;
VAR8 <= 0;
VAR4... | mit |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_i2f.v | 1,562 | module MODULE1(
input VAR10,
input VAR19,
input [31:0] VAR2,
input VAR12,
output [31:0] VAR5,
output VAR18
);
reg VAR16;
reg VAR8;
reg [30:0] VAR11;
reg VAR15;
always @(posedge VAR10) begin
if(VAR19)
VAR16 <= 1'b0;
end
else
VAR16 <= VAR12;
VAR8 <= VAR2[31];
if(VAR2[31])
VAR11 <= 31'd0 - VAR2[30:0];
else
VAR11 <= VAR2[3... | lgpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rxr_engine_ultrascale.v | 21,869 | module MODULE1
parameter VAR45=10)
( input VAR51,
input VAR93, input VAR42, output VAR17,
input VAR58,
input VAR115,
input [VAR81-1:0] VAR75,
input [(VAR81/32)-1:0] VAR104,
input [VAR25-1:0] VAR66,
output VAR112,
output [VAR81-1:0] VAR26,
output VAR41,
output [(VAR81/32)-1:0] VAR129,
output VAR30,
output [VAR13(VAR81/3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi_4.v | 2,439 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR6 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR10,
VAR9,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR12 ;
input VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
input VAR10;
input VAR9;
input VAR7 ;
input VAR4 ;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_4.behavioral.v | 2,148 | module MODULE1( VAR1, VAR8, VAR11 );
input VAR1, VAR8;
output VAR11;
reg VAR4;
VAR10 VAR2(.VAR1(VAR1),.VAR8(VAR8),.VAR11(VAR11),.VAR4(VAR4));
VAR10 VAR3(.VAR1(VAR1),.VAR8(VAR8),.VAR11(VAR11),.VAR4(VAR4));
not VAR5(VAR7,VAR8);
buf VAR6(VAR9,VAR8); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.pp.blackbox.v | 1,318 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR1 ,
VAR2 ,
VAR3,
VAR5,
VAR4 ,
VAR8
);
output VAR7 ;
output VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai_4.v | 2,134 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR5,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR5;
input VAR1;
VAR8 VAR4 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7,
VAR3,
VAR2
);
output VAR6 ;
input VAR7;
input VAR3;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3.behavioral.v | 1,371 | module MODULE1 (
VAR8,
VAR6,
VAR11,
VAR7
);
output VAR8;
input VAR6;
input VAR11;
input VAR7;
supply1 VAR4;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
wire VAR9;
and VAR1 (VAR9, VAR7, VAR6, VAR11 );
buf VAR10 (VAR8 , VAR9 );
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/minimac/rtl/minimac_ctlif.v | 5,949 | module MODULE1 #(
parameter VAR38 = 4'h0
) (
input VAR37,
input VAR29,
input [13:0] VAR3,
input VAR32,
input [31:0] VAR40,
output reg [31:0] VAR11,
output reg VAR47,
output reg VAR21,
output reg VAR17,
output reg VAR46,
output VAR25,
output [29:0] VAR34,
input VAR41,
input VAR27,
input VAR9,
input VAR4,
output VAR22,
o... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf_8.v | 2,046 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR3,
VAR8,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR1 ;
VAR6 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR4
);
output VAR7;
input VAR4;
supply1 VAR3;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i_2.v | 2,087 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR5,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR5;
input VAR4;
VAR2 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8 ,
VAR3,
VAR7,
VAR6
);
output VAR8 ;
input VAR3;
input VAR7;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpio_ovtv2/sky130_fd_io__top_gpio_ovtv2.functional.pp.v | 34,077 | module MODULE1 ( VAR129, VAR71, VAR59, VAR126, VAR82,
VAR89, VAR123, VAR38, VAR156, VAR56,
VAR150, VAR90,VAR110, VAR66, VAR145, VAR83, VAR46, VAR61, VAR58, VAR103,
VAR137, VAR125, VAR52, VAR108, VAR53, VAR157, VAR42, VAR73, VAR81, VAR30,
VAR151, VAR63, VAR41, VAR87, VAR17, VAR72, VAR102, VAR70, VAR124, VAR79 );
input V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_psa_pp_pkg_sn/sky130_fd_sc_hs__udp_dlatch_psa_pp_pkg_sn.blackbox.v | 1,613 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR9 ,
VAR3 ,
VAR1 ,
VAR5,
VAR7 ,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR5;
input VAR7 ;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
bunnie/novena-gpbb-fpga | novena-gpbb.srcs/sources_1/ip/clk_dll/clk_dll/example_design/clk_dll_exdes.v | 6,168 | module MODULE1
parameter VAR37 = 100
)
( input VAR16,
input VAR30,
output [3:1] VAR3,
output [3:1] VAR23,
input VAR22,
output VAR32
);
localparam VAR27 = 16;
localparam VAR5 = 3;
genvar VAR34;
wire VAR35 = !VAR32 || VAR22 || VAR30;
reg [VAR5:1] VAR31;
reg [VAR5:1] VAR4;
reg [VAR5:1] VAR10;
reg [VAR5:1] VAR19;
wire [VAR... | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_dc_tag.v | 4,203 | module MODULE1(
clk, rst,
VAR18, VAR1, VAR5,
addr, en, VAR11, VAR15, VAR9, VAR13
);
parameter VAR10 = VAR7;
parameter VAR2 = VAR3;
input clk;
input rst;
input [VAR2-1:0] addr;
input en;
input VAR11;
input [VAR10-1:0] VAR15;
output VAR9;
output [VAR10-2:0] VAR13;
input VAR18;
input [VAR14 - 1:0] VAR5;
output VAR1;
assig... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_072.v | 1,558 | module MODULE1 (
VAR14,
VAR8
);
input [31:0] VAR14;
output [31:0]
VAR8;
wire [31:0]
VAR13,
VAR3,
VAR6,
VAR7,
VAR12,
VAR9,
VAR4,
VAR10,
VAR2,
VAR5;
assign VAR13 = VAR14;
assign VAR7 = VAR13 << 7;
assign VAR9 = VAR13 << 4;
assign VAR12 = VAR6 - VAR7;
assign VAR4 = VAR12 + VAR9;
assign VAR2 = VAR4 + VAR10;
assign VAR3 = V... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_custom_mul_op_double.v | 11,399 | module MODULE1 (
VAR49, VAR69,
VAR38, VAR25, VAR32,
VAR42, VAR79, VAR3,
VAR20,
VAR76,
VAR75,
VAR28, VAR73, VAR27, VAR16,
enable);
parameter VAR2 = 1;
parameter VAR54 = 0;
parameter VAR34 = 1;
parameter VAR70 = 1;
parameter VAR46 = 1;
input VAR49, VAR69;
input [55:0] VAR38;
input [11:0] VAR25;
input VAR32;
input [55:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.blackbox.v | 1,311 | module MODULE1 (
VAR4 ,
VAR6,
VAR3,
VAR1,
VAR7
);
output VAR4 ;
input VAR6;
input VAR3;
input VAR1;
input VAR7;
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2.functional.v | 1,313 | module MODULE1 (
VAR1,
VAR6,
VAR4
);
output VAR1;
input VAR6;
input VAR4;
wire VAR2;
xnor VAR5 (VAR2, VAR6, VAR4 );
buf VAR3 (VAR1 , VAR2 );
endmodule | apache-2.0 |
benreynwar/fpga-sdrlib | verilog/uhd/dut_qa_contents.v | 1,098 | module MODULE1;
reg clk;
reg VAR4;
reg [VAR7-1:0] VAR1;
reg VAR5;
reg [VAR3-1:0] VAR2;
reg [VAR12-1:0] VAR8;
reg VAR10;
wire [VAR7-1:0] VAR6;
wire VAR14;
wire [VAR3-1:0] VAR15;
wire [VAR12-1:0] VAR9;
wire VAR11;
wire VAR13; | mit |
binderclip/BCOpenMIPS | cpu-code/id.v | 30,923 | module MODULE1 (
input wire rst,
input wire[VAR52] VAR39,
input wire VAR4,
input wire[VAR64] VAR61,
input wire[VAR48] VAR40,
input wire[VAR48] VAR29,
input wire[VAR66] VAR17,
input wire VAR7,
input wire[VAR48] VAR10,
input wire VAR59,
input wire[VAR42] VAR6,
input wire[VAR66] VAR55,
input wire VAR44,
input wire[VAR48] ... | mit |
cliffordwolf/yosys | techlibs/intel/common/altpll_bb.v | 14,302 | module MODULE1
( VAR191,
VAR4,
VAR21,
VAR315,
VAR281,
VAR236,
VAR242,
VAR261,
VAR112,
VAR206,
VAR95,
VAR85,
VAR117,
VAR189,
VAR62,
VAR228,
VAR210,
VAR29,
VAR246,
clk,
VAR249,
VAR309,
VAR114,
VAR23,
VAR311,
VAR158,
VAR50,
VAR151,
VAR5,
VAR302,
VAR183,
VAR269,
VAR260,
VAR127,
VAR268,
VAR126,
VAR278,
VAR305,
VAR15,
VAR307... | isc |
jameshegarty/rigel | platform/camera1x/vsrc/DramWriter.v | 3,823 | module MODULE1(
input VAR28,
input VAR15,
output VAR26,
output reg [31:0] VAR11,
input VAR22,
output reg VAR9,
output [63:0] VAR18,
output [7:0] VAR19,
input VAR1,
output VAR7,
output VAR23,
input [1:0] VAR27,
input VAR33,
output VAR21,
output [3:0] VAR37,
output [1:0] VAR3,
output [1:0] VAR34,
input VAR10,
output reg ... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/PIO_EP_MEM_ACCESS.v | 12,517 | module MODULE1 (
clk,
VAR43,
VAR36, VAR67, VAR20,
VAR37, VAR60, VAR63, VAR22, VAR41
);
input clk;
input VAR43;
input [10:0] VAR36;
input [3:0] VAR67;
output [31:0] VAR20;
input [10:0] VAR37;
input [7:0] VAR60;
input [31:0] VAR63;
input VAR22;
output VAR41;
wire [31:0] VAR20;
reg [31:0] VAR75;
wire [31:0] VAR38, VAR31, ... | lgpl-3.0 |
SymbiFlow/yosys | techlibs/achronix/speedster22i/cells_arith.v | 2,704 | module MODULE1(
module 80alteramax10alu (VAR4, VAR17, VAR20, VAR31, VAR27, VAR14, VAR28);
parameter VAR26 = 0;
parameter VAR5 = 0;
parameter VAR36 = 1;
parameter VAR30 = 1;
parameter VAR16 = 1;
input [VAR36-1:0] VAR4;
input [VAR30-1:0] VAR17;
output [VAR16-1:0] VAR27, VAR14;
input VAR20, VAR31;
output VAR28;
wire VAR15... | isc |
alan4186/ParCNN | Hardware/v/FFN/np_matrix_mult_ctrl.v | 1,419 | module MODULE1(
input VAR3,
input reset,
input VAR10,
output reg [VAR11:0] addr,
output reg [VAR4:0] VAR5,
output reg VAR2,
output reg VAR6
);
always @(posedge VAR3 or negedge reset) begin
if (reset == 1'b0) begin
addr <= VAR1'd0;
VAR5 <= VAR8'd0;
end else begin
if (VAR10) begin
addr <= VAR1'd0;
VAR5 <= VAR8'd0;
end el... | mit |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_ocd_samp.v | 11,489 | module MODULE1 #
(parameter VAR30 = 4,
parameter VAR43 = 2,
parameter VAR5 = 95,
parameter VAR31 = 100,
parameter VAR16 = "VAR3")
(
VAR26, VAR8, VAR39, VAR28,
VAR14, clk, rst, VAR13,
VAR49, VAR18, VAR47, VAR45
);
function integer VAR23 (input integer VAR41); begin
VAR41 = VAR41 - 1;
for (VAR23=1; VAR41>1; VAR23=VAR23+1... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/Exp_operation_m.v | 2,490 | module MODULE1
input wire clk, input wire rst, input wire VAR32, input wire VAR15, input wire VAR25, input wire [VAR8:0] VAR13,
input wire [VAR8:0] VAR9,
input wire VAR4,
output wire [VAR8:0] VAR3,
output wire VAR18,
output wire VAR11
);
wire [VAR8:0] VAR20;
wire VAR16;
wire VAR26;
wire VAR1;
wire [VAR8:0] VAR7;
VAR24 ... | gpl-3.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/misc_ip/multiplier.v | 4,419 | module MODULE1 (
VAR10,
VAR2,
VAR17);
input wire [15:0] VAR10;
input wire [15:0] VAR2;
output wire [31:0] VAR17;
VAR18 VAR14 (
.VAR10 (VAR10),
.VAR2 (VAR2),
.VAR17 (VAR17),
.VAR9 (1'b0),
.VAR6 (1'b1),
.VAR5 (1'b0),
.VAR11 (1'b0),
.sum (1'b0));
VAR14.VAR4 = "VAR12=5",
VAR14.VAR1 = "VAR8",
VAR14.VAR16 = "VAR7",
VAR14.VA... | gpl-2.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_pl_buffers.v | 1,775 | module MODULE1 (VAR1, VAR5, VAR13,
VAR9, VAR8,
clk, VAR10);
parameter VAR6 = 3;
parameter VAR12 = 4;
input [VAR12-1:0] VAR1;
input [VAR12-1:0] VAR5;
input VAR11 VAR13 [VAR12-1:0];
output VAR11 VAR9 [VAR12-1:0];
output VAR4 VAR8 [VAR12-1:0];
input clk, VAR10;
genvar VAR2;
generate
for (VAR2=0; VAR2<VAR12; VAR2++) begin:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv.functional.pp.v | 1,672 | module MODULE1 (
VAR2,
VAR3,
VAR8 ,
VAR1
);
input VAR2;
input VAR3;
output VAR8 ;
input VAR1 ;
wire VAR6 ;
wire VAR4;
not VAR10 (VAR6 , VAR1 );
VAR5 VAR9 (VAR4, VAR6, VAR2, VAR3);
buf VAR7 (VAR8 , VAR4 );
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/gpio/gpio.v | 1,463 | module MODULE1
(
input VAR11,
input VAR12,
input VAR5,
input [7:0] VAR6,
input VAR7,
input VAR4,
input VAR10,
input [2:0] VAR13,
input [1:0] VAR15,
output reg [7:0] VAR9,
output reg VAR1,
output VAR14,
output VAR8,
input [7:0] VAR3,
output reg [7:0] VAR16,
output reg [7:0] VAR2
);
always @(posedge VAR11)
if (VAR12)
VAR... | gpl-2.0 |
mistryalok/Zedboard | learning/training/Microsystem/les6/ip_repo/myip_1.0/hdl/myip_v1_0_S00_AXI.v | 13,785 | module MODULE1 #
(
parameter integer VAR10 = 32,
parameter integer VAR38 = 4
)
(
input wire VAR16,
input wire VAR3,
input wire [VAR38-1 : 0] VAR28,
input wire [2 : 0] VAR33,
input wire VAR11,
output wire VAR43,
input wire [VAR10-1 : 0] VAR20,
input wire [(VAR10/8)-1 : 0] VAR36,
input wire VAR24,
output wire VAR7,
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a_4.v | 2,339 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR10,
VAR9,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR10;
input VAR9;
input VAR8 ;
input VAR4 ;
VAR5 VAR11 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_psa_pp_sn/sky130_fd_sc_hs__udp_dlatch_psa_pp_sn.symbol.v | 1,499 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR4 ,
input VAR2 ,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
ptracton/wb_dsp | rtl/wb_daq_channel.v | 3,706 | module MODULE1 (
VAR15, VAR14, VAR29, VAR40,
VAR38, VAR20, VAR33, VAR31, VAR43, VAR4,
VAR16, VAR7
) ;
parameter VAR44 = 32;
parameter VAR10 = 8;
parameter VAR39 = "";
input VAR38;
input VAR20;
input VAR33;
input VAR31;
input [VAR44-1:0] VAR43;
input VAR4;
input [5:0] VAR16;
output wire [VAR44-1:0] VAR15;
output wire [V... | mit |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/tuner_slice_1k.v | 2,043 | module MODULE1 #(
parameter VAR2 = 10,
VAR3 = 12
)
(
input clk, reset, VAR9,
input signed [VAR2-1:0] in,
input [VAR3-1:0] VAR6,
output reg signed [VAR2-1:0] out
);
wire [1:0] VAR5 = VAR6[VAR3-1:VAR3-2] + {1'b0,VAR9};
reg [1:0] VAR1;
reg [VAR3-3:0] addr;
reg VAR7;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR1... | mit |
pradeep9676/pradeep_9676 | LZD_48bit.v | 2,116 | module MODULE1(in, out, valid
);
input [47:0]in;
output reg [5:0]out;
output reg valid;
wire VAR2,VAR1;
wire [4:0]VAR3;
wire [3:0]VAR4;
begin
begin
begin
end
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.functional.pp.v | 1,832 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6,
VAR9,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR7 ;
input VAR3 ;
wire VAR12 ;
wire VAR10;
buf VAR11 (VAR12 , VAR1 );
VAR8 VAR4 (VAR10, VAR12, VAR6, VAR9);
buf VAR5 (VAR2 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.behavioral.v | 1,821 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR7;
supply1 VAR4;
supply0 VAR14;
supply1 VAR3 ;
supply0 VAR8 ;
wire VAR11 ;
wire VAR10;
wire VAR12 ;
reg VAR9 ;
wire VAR13 ;
VAR2 VAR15 (VAR11 , VAR12, VAR10, VAR9, VAR4, VAR14);
buf VAR6 (VAR5 , VAR11 );
assign VAR13 = ( VAR4 === 1'b1 );
endmodu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv_12.v | 2,058 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4,
VAR8,
VAR7 ,
VAR3
);
output VAR5 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR7 ;
input VAR3 ;
VAR6 VAR1 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
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