repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.functional.v | 2,123 | module MODULE1 (
VAR8,
VAR16,
VAR1 ,
VAR5,
VAR15,
VAR2 ,
VAR17
);
input VAR8;
input VAR16;
output VAR1 ;
input VAR5;
input VAR15;
input VAR2 ;
input VAR17 ;
wire VAR17 VAR14 ;
wire VAR17 VAR6 ;
wire VAR3 ;
wire VAR13;
and VAR10 (VAR14 , VAR2, VAR17 );
nor VAR11 (VAR6 , VAR5, VAR15 );
or VAR4 (VAR3 , VAR6, VAR14 );
VAR1... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_jesd.v | 27,687 | module MODULE1 (
VAR1,
VAR123,
VAR69,
VAR21,
VAR41,
VAR54,
VAR49,
VAR176,
VAR45,
VAR86,
VAR117,
VAR15,
VAR55,
VAR32,
VAR42,
VAR56,
VAR80,
VAR16,
VAR103,
VAR141,
VAR185,
VAR142,
VAR195,
VAR133,
VAR12,
VAR125,
VAR144,
VAR162,
VAR118,
VAR194,
VAR46,
VAR25,
VAR10,
VAR83,
VAR116,
VAR70,
VAR102,
VAR157,
VAR173,
VAR17,
VAR85,... | mit |
vvk/sysrek | skin_color_segm/divider_28_20.v | 1,991 | module MODULE1 #
(
parameter VAR2=8,
parameter VAR18=28,
parameter VAR5=20,
parameter VAR25=28
)
(
input clk,
input VAR19,
input [VAR18-1:0]VAR20,
input [VAR5-1:0]VAR13,
output [VAR25-1:0]VAR21,
output VAR17
);
reg [VAR18-1:0] VAR7 = 0;
reg [VAR5-1:0] VAR22 = 0;
reg [VAR25-1:0]VAR14=0;
wire [VAR5+VAR25-1:0]VAR10;
reg [... | gpl-2.0 |
P3Stor/P3Stor | pcie/app/BMD_TO_CTRL.v | 2,379 | module MODULE1 (
clk,
VAR1,
VAR2,
VAR4,
VAR6,
VAR5
);
input clk;
input VAR1;
input VAR2;
input VAR4;
input VAR6;
output VAR5;
reg VAR3;
reg VAR5;
always @ ( posedge clk ) begin
if (!VAR1 ) begin
VAR3 <= 0;
end else begin
if (!VAR3 && VAR2)
VAR3 <= 1'b1;
end
else if (VAR4)
VAR3 <= 1'b0;
end
end
always @ ( posedge clk ) ... | gpl-2.0 |
omicronns/studies-sys-rek | de1-soc/src/rgb2gray/rgb2gray.v | 2,644 | module MODULE1(
input VAR27,
input [7:0] VAR34,
input [7:0] VAR16,
input [7:0] VAR19,
input VAR21,
input VAR37,
input VAR28,
input VAR23,
output [7:0] VAR38,
output VAR2,
output VAR30,
output VAR10,
output VAR1
);
VAR3 #(
.VAR15(5),
.VAR17(4)
) VAR5 (
.VAR25(1),
.rst(0),
.clk(VAR27),
.in({VAR21, VAR37, VAR28, VAR23}),
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.behavioral.pp.v | 2,243 | module MODULE1 (
VAR1 ,
VAR21 ,
VAR6 ,
VAR14,
VAR20 ,
VAR8 ,
VAR13 ,
VAR17
);
output VAR1 ;
input VAR21 ;
input VAR6 ;
input VAR14;
input VAR20 ;
input VAR8 ;
input VAR13 ;
input VAR17 ;
wire VAR19 ;
wire VAR16 ;
reg VAR2 ;
wire VAR5 ;
wire VAR11;
wire VAR15 ;
wire VAR18 ;
wire VAR9 ;
wire VAR7 ;
not VAR10 (VAR16 , VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o_8.v | 2,264 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR9,
VAR4,
VAR8 ,
VAR10
);
output VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR9;
input VAR4;
input VAR8 ;
input VAR10 ;
VAR6 VAR1 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a.behavioral.v | 1,662 | module MODULE1 (
VAR15 ,
VAR1,
VAR11,
VAR6,
VAR13,
VAR17
);
output VAR15 ;
input VAR1;
input VAR11;
input VAR6;
input VAR13;
input VAR17;
supply1 VAR16;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR9 ;
wire VAR4 ;
wire VAR2 ;
wire VAR5;
or VAR12 (VAR4 , VAR13, VAR6 );
or VAR14 (VAR2 , VAR11, VAR1 );
and VAR3 (VAR5, VAR4, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.behavioral.v | 1,439 | module MODULE1 (
VAR5,
VAR9
);
output VAR5;
input VAR9;
supply1 VAR6;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR4;
buf VAR3 (VAR4, VAR9 );
buf VAR8 (VAR5 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3.functional.pp.v | 1,828 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR7 ,
VAR1 ,
VAR10,
VAR5,
VAR14 ,
VAR3
);
output VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR10;
input VAR5;
input VAR14 ;
input VAR3 ;
wire VAR9 ;
wire VAR2;
xnor VAR13 (VAR9 , VAR8, VAR7, VAR1 );
VAR11 VAR12 (VAR2, VAR9, VAR10, VAR5);
buf VAR6 (VAR4 , VAR2 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/ipcore_dir/v6_emac_v2_2_blank.v | 2,947 | module MODULE1 (
VAR31, VAR30, VAR23, VAR27, VAR13, VAR6, VAR7, VAR3, VAR20, VAR33, VAR19,
VAR35, VAR34, VAR17, VAR22, VAR5, VAR16, VAR29, VAR8,
VAR15, VAR11, VAR10, VAR18, VAR9, VAR2, VAR26, VAR12, VAR14, VAR32,
VAR1, VAR24, VAR21, VAR25, VAR4, VAR28
);
input VAR31;
input VAR30;
output VAR23;
input VAR27;
input VAR13;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.functional.v | 1,806 | module MODULE1 (
VAR6 ,
VAR1,
VAR4 ,
VAR5
);
output VAR6 ;
input VAR1;
input VAR4 ;
input VAR5 ;
wire VAR3 ;
wire VAR8;
wire VAR10 ;
not VAR2 (VAR3 , VAR1 );
not VAR7 (VAR8, VAR5 );
VAR9 VAR11 VAR12 (VAR10 , VAR4, VAR8, VAR3);
buf VAR13 (VAR6 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.symbol.v | 1,349 | module MODULE1 (
input VAR4,
input VAR7,
input VAR3,
output VAR6
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var22_multi.v | 39,261 | module MODULE1(VAR5, VAR4, VAR10, VAR20, VAR17, VAR16, VAR22, VAR7, VAR9, VAR3, VAR6, VAR13, VAR15, VAR18, VAR11, VAR14, VAR1, VAR19, VAR8, VAR12, VAR2, VAR21, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wire 0013... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai_4.v | 2,345 | module MODULE2 (
VAR6 ,
VAR10 ,
VAR1 ,
VAR4,
VAR8,
VAR5,
VAR7 ,
VAR3
);
output VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR4;
input VAR8;
input VAR5;
input VAR7 ;
input VAR3 ;
VAR9 VAR2 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 ... | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v | 1,838 | module MODULE1 #(
parameter VAR22 = 16'h0000,
parameter VAR6 = 16'h0000,
parameter VAR29 = 16,
parameter [1:0] VAR19 = 0,
parameter [0:0] VAR17 = 0
) (
input wire VAR9,
input wire [13:0] VAR12,
input wire VAR27,
input wire VAR11,
input wire VAR3,
output wire VAR4,
output wire [31:0] VAR8,
input wire VAR13,
input wire V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.pp.symbol.v | 1,410 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR1,
input VAR6 ,
input VAR5 ,
input VAR4 ,
input VAR7
);
endmodule | apache-2.0 |
hoglet67/opc | system/blackice/memory_controller_3_wait_states.v | 3,372 | module MODULE1
(
VAR21,
VAR11,
VAR19,
VAR1,
VAR7,
VAR9,
VAR16,
VAR13,
VAR18,
VAR3,
VAR20,
VAR4,
VAR6,
VAR15,
VAR10
);
parameter VAR17 = 32;
parameter VAR2 = 20;
input VAR21;
input VAR11;
input VAR19;
input VAR1;
output VAR7;
input [VAR2-1:0] VAR9;
input [VAR17-1:0] VAR16;
output [VAR17-1:0] VAR13;
output VAR18;
output ... | gpl-3.0 |
d16-processor/d16 | verilog/src/pc_unit.v | 2,706 | module MODULE1(
clk,
en,
rst,
VAR4,
VAR5,
VAR3
);
input clk;
input en;
input rst;
input [15:0] VAR4;
input [1:0] VAR5;
input [15:0] VAR4;
input [1:0] VAR5;
output [15:0] VAR3;
wire clk;
wire en;
wire [15:0] VAR4;
wire [1:0] VAR5;
wire [15:0] VAR3;
reg [15:0] VAR6 = 16'VAR1 0000;
assign VAR3 = VAR6;
always @(posedge clk... | mit |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_bypass.v | 45,623 | module MODULE1 #
( parameter
VAR95 = 2,
VAR182 = 4,
VAR73 = 16, VAR160 = 3,
VAR180 = 1,
VAR119 = 4,
VAR50 = 8
)
(
VAR96,
VAR194,
VAR142,
VAR64,
VAR11,
VAR159,
VAR10,
VAR51,
VAR102,
VAR164,
VAR109,
VAR83,
VAR144,
VAR135,
VAR39,
VAR90,
VAR178,
VAR133,
VAR46,
VAR2,
VAR30,
VAR173,
VAR117,
VAR34,
VAR69,
VAR49,
VAR116,
VAR59... | gpl-3.0 |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/ext_de1_sram.v | 3,781 | module MODULE1(
input clk,
input [VAR7-1:0] VAR12,
input VAR13,
input [1:0] VAR2,
input [15:0] VAR8,
output reg [15:0] VAR1,
inout [15:0] VAR10,
output reg [17:0] VAR15,
output reg VAR6,
output reg VAR9,
output reg VAR11,
output reg VAR17,
output reg VAR16
);
parameter VAR7 = 9;
reg [15:0] VAR5;
reg VAR3; reg VAR4;
alw... | bsd-3-clause |
sabertazimi/hust-lab | verilog/labs/lab5/src/Mealy_FSM.v | 1,985 | module MODULE1(
input VAR4,
input reset,
input VAR6,
output reg [3:0] VAR7,
output reg VAR9
);
reg [1:0] state, VAR1;
parameter VAR10 = 0, VAR8 = 1, VAR5 = 2, VAR2 = 3;
always @(posedge VAR4) begin
if(reset) begin
state <= VAR10;
VAR7 <= 0;
end
else begin
state <= VAR1;
if (VAR1 != state) VAR7 <= VAR7 + 1;
end
end
alwa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb_4.v | 2,334 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR1,
VAR5,
VAR3 ,
VAR2
);
output VAR8 ;
input VAR11 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR9 VAR6 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/RecursiveKOA_Weighted.v | 6,482 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR7,
input wire [VAR2-1:0] VAR22,
input wire [VAR2-1:0] VAR20,
output wire [2*VAR2-1:0] VAR5
);
wire [1:0] VAR10;
wire [3:0] VAR16;
assign VAR10 = 2'b00;
assign VAR16 = 4'b0000;
wire [VAR2/2-1:0] VAR21;
wire [VAR2/2:0] VAR9;
wire [VAR2/2-3:0] VAR33;
wire [VAR... | gpl-3.0 |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/div.v | 3,037 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR18,
input wire[31:0] VAR21,
input wire[31:0] VAR17,
input wire VAR2,
input wire VAR3,
output reg[63:0] VAR14,
output reg VAR22
);
wire[32:0] VAR8;
reg[5:0] VAR4;
reg[64:0] VAR12;
reg[1:0] state;
reg[31:0] VAR1;
reg[31:0] VAR16;
reg[31:0] VAR15;
assign VAR8 =... | gpl-3.0 |
disaderp/automatic-chainsaw | GPU/TXT.v | 3,750 | module MODULE1 (
input clk, input reset,
output [9:0] VAR3, output [9:0] VAR10,
output reg[11:0] VAR5, input [7:0] VAR7,
output reg VAR1,
output reg VAR8, output reg VAR6,
output VAR9, output VAR15
);
VAR4 VAR12 (
.clk (clk),
.VAR14 (VAR3),
.VAR2 (VAR10),
.VAR9(VAR9),
.VAR15(VAR15)
);
reg [7:0] VAR11; reg [11:0] VAR16 ... | gpl-3.0 |
piranna/wasmachine | src/genrom.v | 4,039 | module MODULE1 #( parameter VAR13 = 4, parameter VAR3 = 8, parameter VAR5 = 4
)
( input clk, input wire [ VAR13 :0] addr, input wire [ VAR5-1:0] VAR2, input wire [ VAR13 :0] VAR4,
input wire [ VAR13 :0] VAR12,
output reg [2**VAR5*VAR3-1:0] VAR8=0, output reg VAR7=0 );
parameter VAR6 = "VAR1.VAR10";
localparam VAR9 = 1 ... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkOCApp4B.v | 52,366 | module MODULE1(VAR259,
VAR145,
VAR403,
VAR11,
VAR383,
VAR227,
VAR310,
VAR338,
VAR115,
VAR88,
VAR339,
VAR185,
VAR22,
VAR240,
VAR273,
VAR323,
VAR256,
VAR254,
VAR153,
VAR367,
VAR264,
VAR260,
VAR27,
VAR94,
VAR319,
VAR101,
VAR387,
VAR261,
VAR130,
VAR267,
VAR296,
VAR347,
VAR220,
VAR16,
VAR179,
VAR41,
VAR55,
VAR282,
VAR89,
VA... | lgpl-3.0 |
dagrende/rpi_fpga_stepper | rpi_fpga_stepper.v | 6,936 | module MODULE1(clk, VAR42, VAR28, VAR25, VAR16, VAR51, VAR2, VAR18, dout, din, VAR52, VAR4);
parameter VAR19=10;
parameter VAR39=11;
parameter VAR10=4;
input clk;
input VAR42, VAR16, VAR28, VAR51;
output VAR25, VAR18 = 1'VAR17;
output VAR2;
input [15:0] din;
assign VAR18 = VAR51;
reg VAR5;
reg[13:0] VAR40; output [13:0... | gpl-2.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/or_32.v | 2,011 | module MODULE1(
input [31:0] VAR2, input [31:0] VAR1,
output [31:0] out );
assign out[0] = VAR2[0] | VAR1[0];
assign out[1] = VAR2[1] | VAR1[1];
assign out[2] = VAR2[2] | VAR1[2];
assign out[3] = VAR2[3] | VAR1[3];
assign out[4] = VAR2[4] | VAR1[4];
assign out[5] = VAR2[5] | VAR1[5];
assign out[6] = VAR2[6] | VAR1[6];
... | gpl-3.0 |
sarchar/vga_de0_nano | pixel_clock_bb.v | 10,948 | module MODULE1 (
VAR2,
VAR1);
input VAR2;
output VAR1;
endmodule | mit |
liqimai/ZPC | PersonalComputer/Adder64.v | 1,352 | module MODULE1(
input [63:0] VAR15,
input [63:0] VAR5,
input VAR10,
output [3:0] VAR20,
output [3:0] VAR26,
output [63:0] sum,
output VAR19,
output VAR12,
output VAR11,
output VAR6,
output VAR24
);
wire[15:0] VAR8,VAR2;
wire[4:0] VAR22;
wire[3:0] VAR4,VAR18,VAR25,VAR16,VAR13;
VAR21 VAR21(VAR8,VAR2,VAR20,VAR26);
VAR23 V... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_DeglitchShiftRegister.v | 1,817 | module MODULE1(
input VAR11,
input reset,
input VAR9,
output VAR7
);
reg VAR5;
reg [31:0] VAR10;
reg VAR3;
reg [31:0] VAR6;
reg sync;
reg [31:0] VAR1;
reg VAR8;
reg [31:0] VAR2;
wire VAR4;
assign VAR7 = VAR4;
assign VAR4 = sync & VAR8;
always @(posedge VAR11) begin VAR5 <= VAR9;
VAR3 <= VAR5;
sync <= VAR3;
VAR8 <= sync... | apache-2.0 |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_decerr_slave.v | 10,445 | module MODULE1 #
(
parameter integer VAR27 = 1,
parameter integer VAR30 = 32,
parameter integer VAR54 = 1,
parameter integer VAR41 = 1,
parameter integer VAR36 = 0,
parameter integer VAR47 = 2'b11,
parameter integer VAR44 = 0
)
(
input wire VAR19,
input wire VAR46,
input wire [(VAR27-1):0] VAR3,
input wire VAR42,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o_4.v | 2,469 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR7 ,
VAR11 ,
VAR10 ,
VAR5 ,
VAR9,
VAR4,
VAR3 ,
VAR8
);
output VAR12 ;
input VAR6 ;
input VAR7 ;
input VAR11 ;
input VAR10 ;
input VAR5 ;
input VAR9;
input VAR4;
input VAR3 ;
input VAR8 ;
VAR1 VAR2 (
.VAR12(VAR12),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR5(VAR5),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.blackbox.v | 1,320 | module MODULE1 (
VAR2 ,
VAR8,
VAR1 ,
VAR3 ,
VAR4
);
output VAR2 ;
input VAR8;
input VAR1 ;
input VAR3 ;
input VAR4 ;
supply1 VAR5;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
vivier/SCSI2SD | software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v | 14,974 | module MODULE1 (
output [7:0] VAR55, output VAR40, input VAR24, input [7:0] VAR44, input VAR17, input VAR43, input VAR16, input clk,
output VAR2,
output VAR35,
output VAR56
);
wire VAR76;
VAR75 #(.VAR9(VAR48)) VAR36
(
.VAR81(clk),
.enable(1'b1),
.VAR14(VAR76)
);
localparam VAR54 = 1'b1;
localparam VAR45 = 1'b0;
localpa... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/hpdmc_ctlif.v | 3,780 | module MODULE1 #(
parameter VAR10 = 4'h0
) (
input VAR24,
input VAR2,
input [13:0] VAR27,
input VAR19,
input [31:0] VAR6,
output reg [31:0] VAR32,
output reg VAR20,
output reg VAR3,
output reg VAR25,
output reg VAR15,
output reg VAR11,
output reg VAR4,
output reg VAR13,
output reg [12:0] VAR16,
output reg [1:0] VAR5,
o... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_2.behavioral.pp.v | 2,990 | module MODULE1( VAR7, VAR6, VAR3, VAR24, VAR23, VAR9 );
input VAR6, VAR7, VAR3;
inout VAR23, VAR9;
output VAR24;
reg VAR22;
VAR26 VAR21(.VAR7(VAR7),.VAR6(VAR6),.VAR3(VAR3),.VAR24(VAR24),.VAR23(VAR23),.VAR9(VAR9),.VAR22(VAR22));
VAR26 VAR18(.VAR7(VAR7),.VAR6(VAR6),.VAR3(VAR3),.VAR24(VAR24),.VAR23(VAR23),.VAR9(VAR9),.VAR... | apache-2.0 |
subailong/miaow | src/verilog/rtl/issue/mem_wait.v | 1,421 | module MODULE1
(
VAR20,
clk, rst, VAR11, VAR8, VAR17,
VAR22, VAR15, VAR16
);
input clk,rst;
input VAR11, VAR8, VAR17;
input [5:0] VAR22, VAR15, VAR16;
output [VAR18-1:0] VAR20;
wire [VAR18-1:0] VAR21, VAR2,
VAR13,
VAR7, VAR12;
VAR9 VAR19
(
.VAR6(VAR22),
.out(VAR21),
.en(VAR11)
);
VAR9 VAR4
(
.VAR6(VAR15),
.out(VAR2),
.... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.blackbox.v | 1,420 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3 ,
VAR5,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR5;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.blackbox.v | 1,354 | module MODULE1 (
VAR2 ,
VAR6,
VAR5 ,
VAR3
);
output VAR2 ;
input VAR6;
input VAR5 ;
input VAR3 ;
supply1 VAR7;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
SymbiFlow/yosys | techlibs/ecp5/cells_map.v | 14,437 | module \VAR62 (input VAR26, VAR10, output VAR5);
parameter VAR2 = 1'VAR79;
generate if (VAR2 === 1'b1)
VAR61 #(.VAR59("VAR22"), .VAR103("1"), .VAR85("VAR34"), .VAR6("VAR18"), .VAR78("VAR42")) VAR80 (.VAR57(VAR10), .VAR18(1'b0), .VAR4(VAR26), .VAR5(VAR5));
else
VAR61 #(.VAR59("VAR22"), .VAR103("1"), .VAR85("VAR34"), .VA... | isc |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/sdram_control/sdram_pll0.v | 17,188 | module MODULE1 (
input wire VAR2, input wire rst, output wire VAR6, output wire VAR4, output wire VAR1 );
VAR5 VAR3 (
.VAR2 (VAR2), .rst (rst), .VAR6 (VAR6), .VAR4 (VAR4), .VAR1 (VAR1) );
endmodule | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_ldexp_hc.v | 3,007 | module MODULE1(VAR5, VAR11, VAR20, VAR14, VAR6, VAR10, VAR7, VAR3, VAR17);
input VAR5, VAR11;
input [31:0] VAR20;
input [31:0] VAR14;
input VAR6, VAR7;
output VAR10, VAR3;
output [31:0] VAR17;
wire [7:0] VAR8 = VAR20[30:23];
wire [22:0] VAR15 = VAR20[22:0];
wire VAR19 = VAR20[31];
wire [31:0] VAR4 = VAR14;
wire [31:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.pp.symbol.v | 1,352 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR6,
output VAR4 ,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp.behavioral.v | 2,848 | module MODULE1 (
VAR15 ,
VAR20 ,
VAR5 ,
VAR13 ,
VAR23 ,
VAR6 ,
VAR25
);
output VAR15 ;
output VAR20 ;
input VAR5 ;
input VAR13 ;
input VAR23 ;
input VAR6 ;
input VAR25;
supply1 VAR11;
supply0 VAR14;
supply1 VAR26 ;
supply0 VAR10 ;
wire VAR30 ;
wire VAR22 ;
wire VAR31 ;
reg VAR19 ;
wire VAR27 ;
wire VAR18 ;
wire VAR24 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2_1.v | 1,950 | module MODULE1 (
VAR4,
VAR5,
VAR6 ,
VAR3
);
input VAR4;
input VAR5;
input VAR6 ;
input VAR3 ;
VAR2 VAR1 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
VAR2 VAR1 ();
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latsnq/gf180mcu_fd_sc_mcu9t5v0__latsnq_4.behavioral.v | 2,924 | module MODULE1( VAR26, VAR8, VAR16, VAR7 );
input VAR8, VAR26, VAR16;
output VAR7;
reg VAR12;
VAR13 VAR5(.VAR26(VAR26),.VAR8(VAR8),.VAR16(VAR16),.VAR7(VAR7),.VAR12(VAR12));
VAR13 VAR3(.VAR26(VAR26),.VAR8(VAR8),.VAR16(VAR16),.VAR7(VAR7),.VAR12(VAR12));
buf VAR19(VAR15,VAR16);
not VAR21(VAR14,VAR8);
and VAR18(VAR10,VAR16... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b.pp.symbol.v | 1,309 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR5 ,
output VAR2 ,
input VAR4 ,
input VAR7,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.functional.pp.v | 1,850 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR5,
VAR10,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR12 ;
input VAR5;
input VAR10;
input VAR7 ;
input VAR6 ;
wire VAR3 ;
wire VAR1;
buf VAR4 (VAR3 , VAR12 );
VAR9 VAR11 (VAR1, VAR3, VAR5, VAR10);
buf VAR2 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o_1.v | 2,448 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR11 ,
VAR8 ,
VAR10,
VAR9,
VAR7 ,
VAR12
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR11 ;
input VAR8 ;
input VAR10;
input VAR9;
input VAR7 ;
input VAR12 ;
VAR2 VAR1 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR10(... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/boardSynchroniser.v | 1,600 | module MODULE1(
input clk,
input VAR8,
input VAR2,
input [1:0] VAR13,
input [1:0] VAR10,
input VAR3,
output reg VAR9 = 1'b0,
inout VAR1
);
reg VAR12 = 1'b0, VAR7 = 1'b0, VAR4 = 1'b0;
reg [1:0] VAR6 = 2'b00;
reg VAR5 = 1'b0;
always @(posedge clk) begin
VAR12 <= VAR2;
VAR7 <= VAR12;
VAR4 <= VAR12 & ~VAR7;
if (VAR4) begin... | gpl-3.0 |
Elphel/x393_sata | host/oob_ctrl.v | 10,614 | module MODULE1 #(
parameter VAR31 = 4,
parameter VAR11 = 1 )
(
input wire clk, input wire rst, input wire VAR14, output wire [11:0] VAR22, input wire VAR37, input wire VAR15, input wire VAR13, output wire VAR25, output wire VAR9, output wire VAR1, output wire VAR33, input wire VAR35, output wire VAR29, input wire VAR26... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3.functional.v | 1,291 | module MODULE1 (
VAR2,
VAR4,
VAR5,
VAR7
);
output VAR2;
input VAR4;
input VAR5;
input VAR7;
wire VAR3;
nand VAR6 (VAR3, VAR5, VAR4, VAR7 );
buf VAR1 (VAR2 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.pp.symbol.v | 1,357 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR1 ,
input VAR3,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_clocks.v | 10,931 | module MODULE1
(
VAR3,
VAR1,
VAR10,
VAR7) ;
input VAR3;
input VAR1;
input [0:0] VAR10;
output [0:0] VAR7;
tri0 VAR3;
tri1 VAR1;
reg [0:0] VAR4;
reg [0:0] VAR8;
reg [0:0] VAR6;
wire VAR2;
wire VAR9;
wire VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.functional.v | 1,207 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
buf VAR1 (VAR2 , VAR3 );
endmodule | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/i2c_master_bit_ctrl.v | 16,890 | module MODULE1(
clk, rst,
VAR3, VAR28, VAR37, VAR2, VAR45, VAR12, din, dout,
VAR6, VAR14, VAR41, VAR18, VAR31, VAR20
);
input clk;
input rst;
input VAR28;
input [15:0] VAR3;
input [3:0] VAR37;
output VAR2; reg VAR2;
output VAR45; reg VAR45;
output VAR12; reg VAR12;
input din;
output dout;
reg dout;
input VAR6; output V... | gpl-2.0 |
boylansr/Prop_Muse | P1V/P8X32A_Emulation/P8X32A_DE2_115/cog_ctr.v | 2,947 | module MODULE1
(
input VAR11,
input VAR18,
input VAR1,
input VAR9,
input VAR3,
input VAR16,
input [31:0] VAR14,
input [31:0] VAR7,
output reg [32:0] VAR5,
output [31:0] VAR19,
output VAR22
);
reg [31:0] VAR20;
reg [31:0] VAR6;
always @(posedge VAR11 or negedge VAR1)
if (!VAR1)
VAR20 <= 32'b0;
else if (VAR9)
VAR20 <= VA... | gpl-3.0 |
everskar2013/PentiumX | Hardware/Code/uart_new_2.v | 5,241 | module MODULE1 #(
parameter VAR47 = 100000000,
parameter VAR15 = 115200
) (
input [31:0] VAR35,
input [31:0] VAR39,
input VAR13,
input VAR43,
output reg [31:0] VAR46,
output VAR7,
input VAR32,
input VAR41,
output VAR44,
output VAR29,
input VAR12,
output VAR10,
input VAR26
);
reg [15:0] VAR27;
wire [7:0] VAR2;
wire [7:0... | mit |
horia141/bachelor-thesis | prj/components/ROMMatrix/ROMMatrix.v | 4,359 | module MODULE1(VAR8,reset,VAR1,VAR15,out,VAR24,VAR4);
parameter VAR27 = 8;
parameter VAR26 = 8;
parameter VAR18 = 8;
input wire VAR8;
input wire reset;
input wire [11:0] VAR1;
input wire VAR15;
output wire [VAR18-1:0] out;
output wire [15:0] VAR24;
input wire [VAR18-1:0] VAR4;
reg [1:0] VAR19;
reg [7:0] VAR7;
reg [7:0]... | mit |
dagrende/quad_stepper | qsfpga/spi_slave.v | 1,198 | module MODULE1(clk, VAR13, VAR5, VAR16, VAR19, VAR6, VAR3, VAR7);
parameter VAR2 = 32;
input clk, VAR16;
input VAR19; input VAR13;
output VAR5; output [VAR2 - 1:0] VAR3;
input [VAR2 - 1:0] VAR6;
output VAR7;
reg [VAR2 - 1:0] VAR17;
reg [2:0] VAR11, VAR14;
always @(posedge clk) begin
VAR11 <= {VAR16, VAR11[2:1]};
VAR14 ... | apache-2.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox2.v | 3,320 | module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd15;
4'd1: VAR2 = 4'd1;
4'd2: VAR2 = 4'd8;
4'd3: VAR2 = 4'd14;
4'd4: VAR2 = 4'd6;
4'd5: VAR2 = 4'd11;
4'd6: VAR2 = 4'd3;
4'd7: VAR2 = 4'd4;
4'd8: VAR2 = 4'd9;
4'd9: VAR2 = 4'd7;
... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_avalon_video_vga_timing.v | 11,320 | module MODULE1 (
clk,
reset,
VAR20,
VAR18,
VAR9,
VAR10,
VAR5,
VAR21,
VAR40,
VAR31, VAR15, VAR12, VAR7, VAR25, VAR35, VAR3, VAR22, VAR1 );
parameter VAR26 = 9;
parameter VAR14 = 640;
parameter VAR34 = 16;
parameter VAR8 = 96;
parameter VAR11 = 48;
parameter VAR16 = 800;
parameter VAR6 = 480;
parameter VAR24 = 10;
parame... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_12.behavioral.v | 1,175 | module MODULE1( VAR3, VAR1, VAR2 );
input VAR3, VAR1;
output VAR2;
VAR5 VAR4(.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2));
VAR5 VAR6(.VAR3(VAR3),.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_dac_4d_2c.v | 16,732 | module MODULE1 (
VAR55,
VAR104,
VAR99,
VAR85,
VAR66,
VAR93,
VAR49,
VAR39,
VAR14,
VAR31,
VAR45,
VAR75,
VAR25,
VAR108,
VAR29,
VAR34,
VAR56,
VAR13,
VAR23,
VAR105,
VAR7,
VAR38,
VAR101,
VAR46,
VAR103,
VAR109,
VAR59,
VAR60,
VAR69,
VAR94,
VAR97,
VAR22,
VAR11);
parameter VAR51 = 0;
input [ 7:0] VAR55;
input VAR104;
input VAR99... | mit |
asicguy/gplgpu | hdl/de3d/des_smline_3d.v | 10,702 | module MODULE1
(
input VAR1,
input VAR34,
input VAR2,
input VAR23,
input VAR57,
input [15:0] VAR36,
input [15:0] VAR25,
input [15:0] VAR27,
input [15:0] VAR54,
input VAR20,
output reg VAR29,
output reg VAR28,
output reg VAR17,
output reg VAR7, output reg signed [15:0] VAR50, output reg signed [15:0] VAR16, output reg V... | gpl-3.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,155 | module MODULE1(
VAR30,
VAR25,
VAR16,
VAR23,
VAR21,
VAR31,
VAR7,
VAR27,
VAR29,
VAR4
);
parameter VAR2 = 1;
parameter VAR8 = 8;
parameter VAR28 = 2;
parameter VAR11 = 2;
parameter VAR20 = 1;
localparam VAR24 = VAR2 * VAR8;
input VAR30;
input VAR25;
output VAR16;
input VAR23;
input [VAR24-1:0] VAR21;
input VAR31;
input VA... | mit |
plindstroem/oh | elink/hdl/erx_core.v | 13,291 | module MODULE1 (
VAR59, VAR23, VAR40, VAR69, VAR36,
VAR47, VAR41, VAR94, VAR27, VAR76,
VAR66,
reset, clk, VAR15, VAR60, VAR86, VAR59, VAR25,
VAR23, VAR28, VAR11
);
parameter VAR64 = 32;
parameter VAR88 = 32;
parameter VAR18 = 104;
parameter VAR4 = 6;
parameter VAR48 = 12'h800;
input reset;
input clk;
input [VAR18-1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.symbol.v | 1,322 | module MODULE1 (
input VAR5,
output VAR1
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/zet/zet/zet_decode.v | 4,311 | module MODULE1 (
input clk,
input rst,
input [7:0] VAR33,
input [7:0] VAR11,
input VAR39,
input VAR3,
input VAR41,
input VAR51,
input VAR21,
input VAR6,
input VAR35,
output VAR7,
output VAR8,
output VAR20,
output VAR31,
output VAR40,
output VAR42,
input [2:0] VAR26,
input VAR30,
input VAR48,
output VAR23,
output reg VA... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/CAM_monitor_ipv4.v | 9,434 | module MODULE1
(
input clk,
input VAR45,
input [3:0] VAR17,
input [11:0] VAR6,
input VAR11,
input reset,
output VAR12,
input VAR24,
input [3:0] VAR10,
input [31:0] VAR22,
input VAR14,
output VAR28,
output VAR13,
input VAR4,
input VAR47
);
parameter VAR40 = VAR7;
wire [11:0] VAR26;
wire [3:0] VAR23;
reg VAR43;
reg VAR20... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/packet_buffer_bypass.v | 3,854 | module MODULE1(
input clk,
input reset,
output [239:0] VAR48,
input [63:0] VAR13,
input [23:0] VAR25,
input VAR33,
output reg VAR24,
input VAR20,
output reg VAR41,
output reg [63:0] VAR29,
output reg [23:0] VAR9,
output reg VAR14,
output reg VAR17,
input VAR47,
output reg [1:0] VAR15,
output reg VAR4,
output reg VAR39,... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/arb_select.v | 20,532 | module MODULE1 #
(
parameter VAR123 = 100,
parameter VAR124 = "1T",
parameter VAR96 = 11,
parameter VAR104 = 3,
parameter VAR129 = "8",
parameter VAR125 = 4,
parameter VAR99 = 5,
parameter VAR17 = 31,
parameter VAR140 = 8,
parameter VAR43 = "VAR25",
parameter VAR84 = "VAR63",
parameter VAR91 = "VAR63",
parameter VAR138... | lgpl-3.0 |
Xilinx/PYNQ | boards/ip/mux_vector_1.0/mux_vector.v | 1,725 | module MODULE1 #(parameter VAR6 = 4 , VAR7 = 3, VAR12=2)(
input wire [VAR6-1:0] VAR5,
input wire [VAR6-1:0] VAR1,
input wire [VAR6-1:0] VAR11,
input wire [VAR6-1:0] VAR8,
input wire [VAR6-1:0] VAR9,
input wire [VAR6-1:0] VAR4,
input wire [VAR6-1:0] VAR3,
input wire [VAR6-1:0] VAR2,
input wire [2:0] sel,
output wire [VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.functional.v | 1,110 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_int_div32u.v | 4,762 | module MODULE1 (
enable,
VAR20,
VAR11,
VAR16,
VAR13,
VAR9);
input enable;
input VAR20;
input [31:0] VAR11;
input [31:0] VAR16;
output [31:0] VAR13;
output [31:0] VAR9;
wire [31:0] VAR7;
wire [31:0] VAR1;
wire [31:0] VAR9 = VAR7[31:0];
wire [31:0] VAR13 = VAR1[31:0];
VAR2 VAR12 (
.VAR20 (VAR20),
.VAR17 (enable),
.VAR11 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi_4.v | 2,261 | module MODULE2 (
VAR5 ,
VAR10 ,
VAR9 ,
VAR3 ,
VAR1,
VAR8,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR3 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR2 ;
VAR6 VAR7 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_reg2mem.v | 4,372 | module MODULE1(addr, VAR4, VAR9, VAR11);
parameter VAR5 = VAR10;
input [1:0] addr;
input [VAR7-1:0] VAR4;
input [VAR5-1:0] VAR9;
output [VAR5-1:0] VAR11;
reg [7:0] VAR13;
reg [7:0] VAR3;
reg [7:0] VAR12;
reg [7:0] VAR6;
assign VAR11 = {VAR13, VAR3, VAR12, VAR6};
always @(VAR4 or addr or VAR9) begin
casex({VAR4, addr[1:... | gpl-3.0 |
sonyxperiadev/CDB-Assist | Firmware-v3/CDBAssistNextGen.cydsn/DitherPWM/DitherPWM.v | 10,266 | module MODULE1 (
output VAR54,
input VAR33,
input reset
);
localparam VAR57 = 2'd0;
localparam VAR66 = 2'd1;
localparam VAR21 = 2'd2;
localparam VAR61 = 2'd3;
localparam VAR46 = 8'h7;
localparam VAR2 = 8'h1;
localparam VAR62 = 8'h0;
localparam VAR17 = VAR60;
localparam VAR25 = VAR73;
localparam VAR69 = VAR20;
parameter... | gpl-3.0 |
ptracton/Picoblaze | library/uart_pb/uart_tx6.v | 11,699 | module MODULE1 (
input [7:0] VAR85,
input VAR45,
input VAR13,
input VAR52,
output VAR15,
output VAR37,
output VAR72,
output VAR88,
input clk );
wire [7:0] VAR4;
wire [7:0] VAR46;
wire [3:0] VAR69;
wire [3:0] VAR74;
wire VAR56;
wire VAR38;
wire VAR27;
wire VAR78;
wire VAR16;
wire [3:0] VAR7;
wire [3:0] VAR70;
wire [3:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o.pp.blackbox.v | 1,355 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR6 ,
VAR7,
VAR5,
VAR1 ,
VAR8
);
output VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR7;
input VAR5;
input VAR1 ;
input VAR8 ;
endmodule | apache-2.0 |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s349.v | 8,966 | module MODULE1 (VAR129,VAR188,VAR42);
input VAR129,VAR42;
output VAR188;
wire VAR103,VAR328;
trireg VAR89,VAR210;
nmos VAR164 (VAR210,VAR42,VAR328);
not VAR63 (VAR103,VAR210);
nmos VAR350 (VAR89,VAR103,VAR129);
not VAR253 (VAR188,VAR89);
not VAR163 (VAR328,VAR129);
endmodule
module MODULE2(VAR36,VAR141,VAR129,VAR8,VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.pp.symbol.v | 1,372 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR9 ,
input VAR2 ,
output VAR8 ,
input VAR5 ,
input VAR6,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/STEUER_MISC.v | 47,175 | module MODULE3 ( VAR58, VAR91, VAR51, VAR5, VAR152, VAR85, VAR100, VAR96, VAR31, VAR40, VAR174, VAR56, VAR144,
VAR179, VAR82, VAR165, VAR43, VAR108, VAR129, VAR122, VAR12, VAR35);
input VAR58,VAR91;
input VAR51; input [3:0] VAR5; input VAR152; input [1:0] VAR85; input [2:0] VAR100; input [31:0] VAR96; input VAR31,VAR40... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.behavioral.pp.v | 1,865 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR4,
VAR1,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR7 ;
input VAR4;
input VAR1;
input VAR8 ;
input VAR2 ;
wire VAR10 ;
wire VAR9;
buf VAR12 (VAR10 , VAR7 );
VAR5 VAR6 (VAR9, VAR10, VAR4, VAR1);
buf VAR11 (VAR3 , VAR9 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_engine_ultrascale.v | 12,340 | module MODULE1
parameter VAR24 = 1,
parameter VAR48 = 0,
parameter VAR4 = 64)
( input VAR38,
input VAR10, input VAR71, output VAR77,
output VAR82,
input [VAR2-1:0] VAR27,
input VAR33,
output VAR34,
output VAR35,
output [VAR45-1:0] VAR19,
output [(VAR45/32)-1:0] VAR84,
output [VAR62-1:0] VAR52,
input VAR65,
input [VAR45... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.functional.pp.v | 1,469 | module MODULE1( VAR18, VAR5, VAR10, VAR6, VAR2, VAR14, VAR16 );
input VAR10, VAR18, VAR6, VAR2;
inout VAR14, VAR16;
output VAR5;
wire VAR12;
not VAR11( VAR12, VAR10 );
wire VAR3;
not VAR8( VAR3, VAR18 );
wire VAR7;
and VAR9( VAR7, VAR12, VAR3 );
wire VAR4;
not VAR1( VAR4, VAR6 );
wire VAR13;
not VAR15( VAR13, VAR2 );
o... | apache-2.0 |
kactus2/ipxactexamplelib | tut.fi/communication.template/wb_master/1.0/wb_master.v | 9,452 | module MODULE1 #(
parameter VAR28 = 16, parameter VAR31 = 8, parameter VAR24 = 32, parameter VAR30 = 'h0F00, parameter VAR18 = 0 ) (
input VAR32, input [VAR24-1:0] VAR20, input VAR2, output reg [VAR28-1:0] VAR11, output reg VAR14, output reg [VAR24-1:0] VAR10, output reg VAR8, output reg VAR22,
input VAR13, input VAR1,... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_video_dma_to_memory.v | 4,698 | module MODULE1 (
clk,
reset,
VAR9,
VAR12,
VAR6,
VAR10,
VAR16,
VAR15,
VAR7,
VAR14,
VAR13,
VAR5,
VAR4
);
parameter VAR1 = 15; parameter VAR2 = 0;
parameter VAR11 = 15;
input clk;
input reset;
input [VAR1: 0] VAR9;
input VAR12;
input VAR6;
input [VAR2: 0] VAR10;
input VAR16;
input VAR15;
output VAR7;
output VAR14;
output ... | mit |
alexforencich/verilog-ethernet | example/ZCU106/fpga/rtl/eth_xcvr_phy_wrapper.v | 9,016 | module MODULE1 #
(
parameter VAR10 = 1,
parameter VAR105 = 64,
parameter VAR125 = (VAR105/8),
parameter VAR93 = 2,
parameter VAR119 = 0,
parameter VAR43 = 0,
parameter VAR121 = 0,
parameter VAR4 = 1,
parameter VAR38 = 8,
parameter VAR131 = 125000/6.4
)
(
input wire VAR64,
input wire VAR41,
output wire VAR31,
input wire... | mit |
silent-observer/RCPU | CPU/source/StackRAM.v | 7,341 | module MODULE1 (
address,
VAR56,
VAR27,
VAR6,
VAR46,
VAR10);
input [9:0] address;
input [1:0] VAR56;
input VAR27;
input [15:0] VAR6;
input VAR46;
output [15:0] VAR10;
tri1 [1:0] VAR56;
tri1 VAR27;
wire [15:0] VAR38;
wire [15:0] VAR10 = VAR38[15:0];
VAR40 VAR34 (
.VAR32 (address),
.VAR26 (VAR56),
.VAR42 (VAR27),
.VAR55 ... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/new/led_controller.v | 2,883 | module MODULE1(
input clk,
input [7 : 0] VAR18,
output reg [10 : 0] VAR19 = 0,
output reg [7 : 0] VAR10 = 0,
output reg VAR8 = 0,
output VAR7,
output VAR9,
output VAR3
);
assign VAR3 = VAR17;
reg VAR17 = 0;
reg VAR15 = 0;
reg VAR11 = 0;
reg [15 : 0] VAR14 = 0;
reg [7 : 0] VAR6 = 8'h0;
reg VAR4 = 0;
wire VAR2;
VAR13 VAR... | mit |
devinacker/sd2snes | verilog/sd2snes_obc1/dac.v | 6,918 | module MODULE1(
input VAR28,
input VAR33,
input VAR43,
input[10:0] VAR4,
input[7:0] VAR19,
input[7:0] VAR49,
input VAR8,
input [2:0] VAR17,
input VAR25,
input reset,
input VAR14,
output VAR6,
output VAR35,
output VAR48,
output VAR1,
output VAR51
);
reg[8:0] VAR10;
reg[8:0] VAR32;
wire[8:0] VAR45 = VAR32;
wire[31:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap.pp.blackbox.v | 1,215 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/tc_top.v | 41,632 | module MODULE1 (
VAR236,
VAR256,
VAR40,
VAR42,
VAR146,
VAR187,
VAR16,
VAR79,
VAR228,
VAR66,
VAR264,
VAR41,
VAR248,
VAR206,
VAR110,
VAR50,
VAR184,
VAR203,
VAR235,
VAR78,
VAR141,
VAR220,
VAR43,
VAR273,
VAR247,
VAR152,
VAR32,
VAR194,
VAR159,
VAR6,
VAR45,
VAR227,
VAR260,
VAR281,
VAR209,
VAR154,
VAR60,
VAR10,
VAR145,
VAR37,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.pp.symbol.v | 1,553 | module MODULE1 (
input VAR8 ,
output VAR11 ,
output VAR10 ,
input VAR2,
input VAR3 ,
input VAR5 ,
input VAR1 ,
input VAR4 ,
input VAR7 ,
input VAR9 ,
input VAR6
);
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_video_character_buffer_with_dma_0.v | 13,415 | module MODULE1 (
clk,
reset,
VAR52,
VAR97,
VAR101,
VAR100,
VAR69,
VAR92,
VAR7,
VAR21,
VAR98,
VAR10,
VAR36,
VAR95,
VAR99,
VAR76,
VAR31,
VAR60,
VAR87,
VAR26,
VAR57,
VAR8,
VAR28
);
parameter VAR68 = 8;
parameter VAR35 = 0;
parameter VAR56 = 13;
parameter VAR33 = 8192;
parameter VAR5 = 640;
parameter VAR96 = 480;
input clk... | gpl-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_zones.v | 13,266 | module MODULE1 (
VAR123,
VAR13,
VAR173,
VAR176,
VAR12,
VAR164,
VAR174,
VAR177,
VAR71,
VAR121,
VAR101,
VAR77,
VAR99,
VAR5,
VAR153,
VAR180,
VAR126,
VAR100,
VAR51,
VAR9,
VAR8,
VAR152,
VAR139,
VAR129,
VAR81,
VAR14,
VAR90,
VAR105,
VAR165,
VAR179,
VAR117,
VAR18,
VAR158,
VAR145,
VAR111,
VAR150,
VAR43,
VAR192,
VAR191,
VAR6,
VA... | apache-2.0 |
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