repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/limbus_bb.v | 1,398 | module MODULE1 (
VAR5,
VAR1,
VAR12,
VAR9,
VAR7,
VAR6,
VAR17,
VAR8,
VAR16,
VAR10,
VAR14,
VAR18,
VAR15,
VAR13,
VAR3,
VAR11,
VAR2,
VAR4,
VAR19);
input VAR5;
input VAR1;
inout [15:0] VAR12;
output [18:0] VAR9;
output [0:0] VAR7;
output [0:0] VAR6;
output [1:0] VAR17;
output [0:0] VAR8;
output [17:0] VAR16;
output VAR10;
in... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_rx.v | 11,552 | module MODULE1 (
VAR4,
VAR28,
VAR91,
VAR70,
VAR86,
VAR78,
VAR26,
VAR41,
VAR17,
VAR7,
VAR2,
VAR62,
VAR34,
VAR33,
VAR61,
VAR6,
VAR81,
VAR73,
VAR90,
VAR9,
VAR38,
VAR50,
VAR51,
VAR94,
VAR10,
VAR55,
VAR93,
VAR67,
VAR11,
VAR77,
VAR47,
VAR43,
VAR18,
VAR69,
VAR29,
VAR74,
VAR89,
VAR37,
VAR31,
VAR23);
parameter VAR16 = 0;
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb_2.v | 2,341 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR2,
VAR3,
VAR6 ,
VAR4
);
output VAR11 ;
input VAR9 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR3;
input VAR6 ;
input VAR4 ;
VAR10 VAR7 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR... | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_button_pio.v | 3,962 | module MODULE1 (
address,
VAR12,
clk,
VAR7,
VAR14,
VAR11,
VAR3,
VAR13
)
;
output [ 31: 0] VAR13;
input [ 1: 0] address;
input VAR12;
input clk;
input [ 3: 0] VAR7;
input VAR14;
input VAR11;
input [ 31: 0] VAR3;
wire VAR10;
reg [ 3: 0] VAR8;
reg [ 3: 0] VAR5;
wire [ 3: 0] VAR9;
reg [ 3: 0] VAR1;
wire VAR2;
wire [ 3: 0] ... | gpl-3.0 |
Koheron/zynq-sdk | fpga/cores/edge_detector_v1_0/edge_detector.v | 1,065 | module MODULE1 #
(
parameter integer VAR3 = 1
)
(
input wire din,
input wire clk,
output wire dout
);
reg VAR6;
always @(posedge clk) begin
VAR6 <= din;
end
generate
if (VAR3 == 1)
begin : VAR4
assign dout = !VAR6 && din;
end
if (VAR3 > 1)
begin : VAR7
function integer VAR2 (input integer VAR9);
for(VAR2 = 0; VAR9 > 0;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.functional.pp.v | 1,245 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR2
);
input VAR1;
input VAR3;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/user_data_path/udp_reg_master/src/udp_reg_master.v | 4,949 | module MODULE1
parameter VAR10 = 0,
parameter VAR15 = 127,
parameter VAR20 = 'VAR32 VAR26,
parameter VAR18 = 2
)
(
input VAR11,
output reg VAR9,
input VAR19,
input [VAR23 - 1:0] VAR6,
output reg [VAR13 - 1:0]VAR2,
input [VAR13 - 1:0] VAR14,
output reg VAR27,
output reg VAR30,
output reg VAR1,
output reg [VAR23 - 1:0] V... | mit |
asicguy/gplgpu | hdl/vga/txt_time.v | 12,323 | module MODULE1
(
input VAR16,
input VAR11,
input VAR23, input VAR13, input VAR47, input [15:0] VAR69, input [5:0] VAR4, input VAR26,
input VAR57, input VAR49,
input VAR36, input VAR73,
input VAR5, input VAR52, input VAR33,
input VAR61, input [7:0] VAR48,
output [7:0] VAR9,
output reg [7:0] VAR20,
output [7:0] VAR40,
ou... | gpl-3.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_sysid_qsys_0.v | 1,413 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1502149608 : 0;
endmodule | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/ppu/rgb_generator.v | 7,627 | module MODULE1 #(
parameter VAR9 = 32,
parameter VAR24 = 32
)(
input clk, input rst,
output [9:0] VAR8,
output [9:0] VAR1,
output VAR20,
output VAR16,
output [2:0] VAR6, output [2:0] VAR11, output [1:0] VAR26,
input [5:0] VAR29,
output [9:0] VAR4, output [9:0] VAR21, output [9:0] VAR14, output reg VAR19, output VAR2 );... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cic_strober.v | 1,435 | module MODULE1
( input VAR3,
input reset,
input enable,
input [VAR1-1:0] VAR5, input VAR6,
output wire VAR2 );
reg [VAR1-1:0] counter;
wire VAR4 = (counter==1);
assign VAR2 = VAR4 && enable && VAR6;
always @(posedge VAR3)
if(reset)
counter <= 0;
else if (~enable)
counter <= VAR5;
else if(VAR6)
if(VAR4)
counter <= VAR5;... | gpl-2.0 |
hoglet67/CoPro6502 | src/zet/zet/zet_micro_data.v | 3,610 | module MODULE1 (
input [VAR14-1:0] VAR22,
input [15:0] VAR2,
input [15:0] VAR31,
input [ 3:0] VAR35,
input [ 3:0] VAR41,
input [ 3:0] VAR11,
input [ 3:0] VAR7,
input [ 1:0] VAR3,
input [ 2:0] VAR36,
output VAR30,
output VAR43,
output [VAR8-1:0] VAR1,
output [15:0] VAR39,
output [15:0] VAR13
);
wire [VAR18-1:0] VAR5;
wi... | gpl-3.0 |
amrmorsey/Digital-Design-Project | clockdivider.v | 1,200 | module MODULE1(
input clk,
input rst,
input select,
output reg [31:0] VAR3,
output reg [31:0] VAR5,
output VAR1,
output VAR2,
output VAR4
);
always @ (posedge clk or posedge rst)
begin
if (rst)
VAR3<=32'd0;
end
else
if (VAR3 == 32'd50000000)
VAR3<=32'd0;
else
VAR3 <= VAR3 + 1;
end
always @ (posedge clk or posedge rst)
... | gpl-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/clk_divider.v | 5,635 | module MODULE1
( input VAR47,
output VAR4,
input VAR34,
output VAR35
);
VAR27 VAR44
(.VAR17 (VAR36),
.VAR25 (VAR47));
wire VAR1;
wire VAR48;
wire [7:0] VAR7;
wire VAR5;
wire VAR28;
wire VAR30;
VAR21
.VAR18 (1),
.VAR41 (4),
.VAR11 ("VAR29"),
.VAR43 (10.0),
.VAR31 ("VAR40"),
.VAR8 ("1X"),
.VAR6 ("VAR39"),
.VAR33 (0),
.VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.pp.blackbox.v | 1,562 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR11 ,
VAR1 ,
VAR12 ,
VAR2,
VAR8 ,
VAR10 ,
VAR7 ,
VAR9
);
output VAR6 ;
output VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR11 ;
input VAR1 ;
input VAR12 ;
input VAR2;
input VAR8 ;
input VAR10 ;
input VAR7 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.pp.symbol.v | 1,364 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR7,
input VAR5 ,
input VAR2 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
thurday/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_gen.v | 5,224 | module MODULE1(
input clk,
input rst,
input VAR4,
input [63:0] VAR24,
input [31:0] VAR20,
input [31:0] VAR10,
input VAR15,
input VAR11,
input [63:0] VAR27,
input [2:0] VAR22,
input [15:0] VAR25,
output VAR6,
output [63:0] VAR14,
output VAR13,
input VAR19,
input [7:0] VAR29,
output [4:0] VAR18,
output [31:0] VAR1,
outpu... | bsd-2-clause |
Raamakrishnan/MyProc | MyProc2/MEM.v | 1,716 | module MODULE1 (
input wire clk, input wire VAR11,
input wire [VAR17 - 1:0] VAR13,
input wire [VAR17 - 3:0] VAR4,
input wire [VAR17 - 1:0] VAR5,
input wire [VAR17 - 1:0] VAR8,
output wire [VAR17 - 1:0] VAR15,
output wire [VAR17 - 3:0] VAR3,
output wire [VAR17 - 1:0] VAR16
,input wire VAR21
);
wire [5:0] VAR6;
assign VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s.functional.pp.v | 1,868 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR12,
VAR10,
VAR9 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR12;
input VAR10;
input VAR9 ;
input VAR3 ;
wire VAR6 ;
wire VAR7;
buf VAR11 (VAR6 , VAR8 );
VAR5 VAR1 (VAR7, VAR6, VAR12, VAR10);
buf VAR4 (VAR2 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.pp.blackbox.v | 1,465 | module MODULE1 (
VAR7 ,
VAR3,
VAR1,
VAR9 ,
VAR5 ,
VAR4,
VAR6,
VAR2 ,
VAR8
);
output VAR7 ;
input VAR3;
input VAR1;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR8 ;
endmodule | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless/crossbar.v | 8,517 | module MODULE1 (
input VAR31 VAR46,
input VAR31 VAR10,
input VAR31 VAR22,
input VAR31 VAR14,
input VAR31 VAR20,
input VAR36 VAR1,
input VAR36 VAR4,
input VAR36 VAR13,
input VAR36 VAR34,
input VAR36 VAR27,
input VAR18 VAR7,
input clk,
input rst,
output reg VAR31 VAR2,
output reg VAR31 VAR28,
output reg VAR31 VAR32,
outp... | mit |
Beck-Sisyphus/EE471 | Lab3/sourceCode/shiftll.v | 1,291 | module MODULE1 (VAR9, VAR14, sel);
output [31:0] VAR9;
input [31:0] VAR14, sel;
wire [31:0] VAR5, VAR16;
genvar VAR4, VAR18, VAR11;
VAR2 VAR3(VAR9[0], VAR5[0], 0, sel[0]);
generate
for(VAR4 = 1; VAR4 < 32; VAR4 = VAR4+1) begin: VAR21
VAR2 VAR15(VAR9[VAR4], VAR5[VAR4], VAR5[VAR4-1], sel[0]);
end
endgenerate
VAR2 VAR8(VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.symbol.v | 1,446 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR4 ,
input VAR3,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrbp/sky130_fd_sc_ls__dfrbp.functional.v | 1,759 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR10 ,
VAR11 ,
VAR12
);
output VAR2 ;
output VAR5 ;
input VAR10 ;
input VAR11 ;
input VAR12;
wire VAR1;
wire VAR9;
not VAR4 (VAR9 , VAR12 );
VAR8 VAR6 VAR13 (VAR1 , VAR11, VAR10, VAR9 );
buf VAR3 (VAR2 , VAR1 );
not VAR7 (VAR5 , VAR1 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/wram.v | 10,575 | module MODULE1 (
VAR29,
VAR9,
VAR6,
VAR36,
VAR43,
VAR10,
VAR40,
VAR47,
VAR34);
input [12:0] VAR29;
input [12:0] VAR9;
input VAR6;
input [7:0] VAR36;
input [7:0] VAR43;
input VAR10;
input VAR40;
output [7:0] VAR47;
output [7:0] VAR34;
tri1 VAR6;
tri0 VAR10;
tri0 VAR40;
wire [7:0] VAR12;
wire [7:0] VAR14;
wire [7:0] VAR4... | gpl-2.0 |
finnball/igloo | infra/hdl/clks.v | 1,968 | module MODULE1(
input VAR24,
output VAR13
);
parameter VAR11 = 0;
parameter VAR10 = 0;
parameter VAR31 = 4'b0000;
parameter VAR4 = 7'b0111111;
parameter VAR9 = 3'b011;
parameter VAR16 = 1;
reg VAR20 = 0;
wire VAR37;
reg [VAR38(VAR16) - 1 : 0] VAR36 = 0;
generate
if (VAR10 == 1)
begin: VAR21
VAR6 VAR33 (
.VAR23(VAR20),
... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_linkStatus.v | 1,842 | module MODULE1 (
address,
clk,
VAR4,
VAR3,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input [ 15: 0] VAR4;
input VAR3;
wire VAR5;
wire [ 15: 0] VAR1;
wire [ 15: 0] VAR2;
reg [ 31: 0] VAR6;
assign VAR5 = 1;
assign VAR2 = {16 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR3)
begin
if (... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/efc/rtl/bw_clk_cl_efc_jbus.v | 4,445 | module MODULE1 (
VAR12, VAR4, VAR6, VAR9,
VAR5, VAR1, VAR10, VAR13, VAR8, VAR7, VAR2,
VAR11
);
output VAR12;
output VAR4;
output VAR6;
output VAR9;
input VAR5;
input VAR1;
input VAR10;
input VAR13;
input VAR8;
input VAR7;
input VAR2;
input VAR11;
VAR3 VAR3 (
.VAR12(VAR12),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9 (VAR9),
.VAR5(... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai_1.v | 2,361 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR11 ,
VAR1,
VAR8,
VAR9 ,
VAR2
);
output VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR11 ;
input VAR1;
input VAR8;
input VAR9 ;
input VAR2 ;
VAR7 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.... | apache-2.0 |
amrmorsey/Digital-Design-Project | one_iteration.v | 1,975 | module MODULE1(
clk,
rst,
VAR47,
VAR25,
VAR5,
VAR27,
VAR15
);
input clk;
input rst;
input [32:1] VAR47;
input [32:1] VAR25;
input [48:1] VAR5;
output reg [32:1] VAR27;
output reg [32:1] VAR15;
wire [48:1] VAR11;
VAR21 VAR13 ( VAR25, VAR11);
wire [48:1] VAR18;
VAR38 VAR48(VAR11, VAR5, VAR18);
wire [6:1] b1,VAR37,VAR36,V... | gpl-2.0 |
d16-processor/d16 | verilog/src/top.v | 5,615 | module MODULE1(input VAR51, input [1:0] VAR49, output [7:0] VAR43,
output VAR31, input VAR37, output [3:0] VAR10, input [3:0] VAR22,
output [12:0] VAR36,
output [1:0] VAR45,
output VAR14,
output VAR16,
output VAR25,
output VAR46,
inout [15:0] VAR17,
output [1:0] VAR9,
output VAR54,
output VAR60
);
wire [31:0] VAR1; wir... | mit |
strigeus/fpganes | src/vga.v | 2,111 | module MODULE1(input clk,
output reg VAR11, output reg VAR4,
output reg [3:0] VAR3, output reg[3:0] VAR10, output reg[3:0] VAR21,
output [9:0] VAR7,
output [9:0] VAR5,
output [9:0] VAR8, input [14:0] VAR14, input sync,
input VAR2);
reg [9:0] VAR18, VAR16;
wire VAR22 = (VAR18 < 512); wire VAR9 = (VAR18 == 512 + 23 + 35)... | gpl-3.0 |
SymbiFlow/prjxray-experiments-archive-2017 | clb_ram/top.v | 8,412 | module MODULE11(input clk, VAR12, VAR48, output do);
localparam integer VAR46 = 256;
localparam integer VAR65 = 256;
reg [VAR46-1:0] din;
wire [VAR65-1:0] dout;
reg [VAR46-1:0] VAR30;
reg [VAR65-1:0] VAR13;
always @(posedge clk) begin
VAR30 <= {VAR30, VAR48};
VAR13 <= {VAR13, VAR30[VAR46-1]};
if (VAR12) begin
din <= VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.blackbox.v | 1,397 | module MODULE1 (
VAR3 ,
VAR9,
VAR6,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR9;
input VAR6;
input VAR5 ;
input VAR1 ;
supply1 VAR4;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/core/pipeline_control/exception_manager.v | 24,182 | module MODULE1(
input wire VAR142,
input wire VAR105,
input wire [5:0] VAR24,
input wire VAR143,
input wire [31:0] VAR4,
output wire VAR82,
output wire VAR73,
output wire [5:0] VAR137,
output wire VAR12,
output wire [31:0] VAR68,
output wire VAR152,
output wire [31:0] VAR69,
output wire VAR124,
output wire VAR3,
output... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fa/sky130_fd_sc_ls__fa.symbol.v | 1,291 | module MODULE1 (
input VAR4 ,
input VAR8 ,
input VAR6 ,
output VAR2,
output VAR1
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/altera_up_avalon_video_vga_timing.v | 11,320 | module MODULE1 (
clk,
reset,
VAR4,
VAR40,
VAR13,
VAR1,
VAR28,
VAR24,
VAR8,
VAR27, VAR2, VAR33, VAR29, VAR14, VAR17, VAR3, VAR21, VAR36 );
parameter VAR41 = 9;
parameter VAR19 = 640;
parameter VAR37 = 16;
parameter VAR9 = 96;
parameter VAR30 = 48;
parameter VAR5 = 800;
parameter VAR23 = 480;
parameter VAR32 = 10;
parame... | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pll/example_design/pll_exdes.v | 5,945 | module MODULE1
parameter VAR29 = 100
)
( input VAR21,
input VAR28,
output [4:1] VAR14,
output [4:1] VAR35,
input VAR33,
output VAR8
);
localparam VAR7 = 16;
localparam VAR22 = 4;
genvar VAR6;
wire VAR13 = !VAR8 || VAR33 || VAR28;
reg [VAR22:1] VAR19;
reg [VAR22:1] VAR12;
reg [VAR22:1] VAR31;
reg [VAR22:1] VAR25;
wire [... | gpl-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/ik_swift.v | 51,468 | module MODULE1 (
input wire VAR378, input wire VAR316, output wire [14:0] VAR215, output wire [2:0] VAR149, output wire VAR226, output wire VAR71, output wire VAR52, output wire VAR348, output wire VAR332, output wire VAR357, output wire VAR97, output wire VAR381, inout wire [31:0] VAR37, inout wire [3:0] VAR404, inout... | mit |
SymbiFlow/yosys | techlibs/xilinx/abc9_model.v | 1,495 | module \VAR8 (output VAR3, input VAR4, VAR2, VAR1, VAR6, VAR7, VAR5);
assign VAR3 = VAR5 ? (VAR7 ? VAR6 : VAR1)
: (VAR7 ? VAR2 : VAR4); | isc |
anderson1008/NOCulator | hring/hw/buffered/src/c_err_rpt.v | 2,962 | module MODULE1
(clk, reset, VAR5, VAR6);
parameter VAR1 = 1;
parameter VAR2 = VAR12;
parameter VAR8 = VAR10;
input clk;
input reset;
input [0:VAR1-1] VAR5;
output [0:VAR1-1] VAR6;
wire [0:VAR1-1] VAR6;
generate
if(VAR2 != VAR9)
begin
wire [0:VAR1-1] VAR7, VAR11;
case(VAR2)
begin
assign VAR7 = VAR5;
end
begin
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.functional.v | 1,945 | module MODULE1 (
VAR11,
VAR6,
VAR8 ,
VAR10 ,
VAR15 ,
VAR2 ,
VAR9 ,
VAR3
);
input VAR11;
input VAR6;
output VAR8 ;
input VAR10 ;
input VAR15 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
wire VAR9 VAR12 ;
wire VAR4 ;
wire VAR5;
or VAR1 (VAR12 , VAR15, VAR10, VAR2 );
and VAR16 (VAR4 , VAR12, VAR9, VAR3 );
VAR13 VAR7 (VAR5, VA... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pcie_bram_7x.v | 8,920 | module MODULE1
parameter [3:0] VAR20 = 4'h1, parameter [5:0] VAR1 = 6'h08, parameter VAR22 = "VAR14", parameter VAR28 = 0, parameter VAR4 = 0 )
(
input VAR26, input VAR25,
input VAR7, input [12:0] VAR27, input [VAR4 - 1:0] VAR29,
input VAR24, input VAR6, input [12:0] VAR11,
output [VAR4 - 1:0] VAR5 );
localparam VAR2 =... | gpl-2.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ps2_dual_ref_v1_00_a/hdl/verilog/opb_ipif_slv_ps2_reg_dual.v | 10,075 | module MODULE1 (
VAR30, VAR41, VAR13, VAR2, VAR22, VAR20, VAR16, VAR31, VAR38, VAR26, VAR17, VAR10, VAR12, VAR33, VAR35, VAR32, VAR8, VAR18, VAR36, VAR19, VAR37, VAR23, VAR28, VAR14, VAR11, VAR24, VAR40, VAR29, VAR25 );
input [0:31] VAR30;
input [0:3] VAR41;
input VAR13;
input [0:31] VAR2;
input VAR22;
input VAR20;
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and3/sky130_fd_sc_hvl__and3.pp.symbol.v | 1,284 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR5 ,
output VAR6 ,
input VAR8 ,
input VAR1,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/dps/dps_irq.v | 3,225 | module MODULE1(
input wire VAR2,
input wire VAR13,
input wire VAR10,
input wire [1:0] VAR8, input wire VAR19,
input wire VAR3,
input wire [1:0] VAR1,
input wire VAR24, output wire VAR11,
input wire VAR20,
output wire VAR7,
output wire VAR23,
output wire VAR9,
input wire VAR25
);
integer VAR21;
reg VAR5[0:3];
reg VAR4[0... | bsd-2-clause |
Cognoscan/BoostLogic | verilog/src/primitives/SmallSerializer.v | 1,984 | module MODULE1 #(
parameter VAR36 = "VAR27", parameter VAR26 = "VAR21", parameter VAR15 = "VAR21", parameter integer VAR20 = 2, parameter VAR6 = "VAR34", parameter VAR25 = "VAR9", parameter integer VAR16 = 0 )
(
input wire VAR3,
input wire VAR32,
input wire VAR38,
input wire VAR23,
input wire VAR37,
input wire VAR24,
i... | apache-2.0 |
peteg944/music-fpga | Experimental/Zedboard UART/ADAU1761Top.v | 3,613 | module MODULE1(
input clk,
input VAR6,
input VAR17,
input VAR3,
input VAR33,
output VAR18,
output VAR8,
output VAR28,
output VAR9,
output VAR32,
inout VAR10,
input [3:0] VAR30,
output [2:0] VAR5,
output [2:0] VAR13,
output [3:0] VAR23,
output VAR7,
output VAR31,
output VAR34,
output VAR14,
output VAR21,
output VAR1,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.symbol.v | 1,460 | module MODULE1 (
input VAR9,
input VAR3,
input VAR4 ,
input VAR1 ,
output VAR2
);
supply1 VAR8;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_lsu.v | 9,864 | module MODULE1(
clk, rst,
VAR24, VAR43, VAR28, VAR12,
VAR38, VAR26,
VAR35, VAR11,
VAR20,
VAR29, VAR8,
VAR36,
VAR19,
VAR27,
VAR46, VAR39,
VAR40, VAR13, VAR22, VAR21, VAR45,
VAR2, VAR25, VAR41
);
parameter VAR4 = VAR15;
input clk;
input rst;
input [31:0] VAR43;
input [31:0] VAR28;
input VAR12;
input [VAR4-1:0] VAR38;
inp... | gpl-2.0 |
audiocircuit/NCSU-Low-Power-RFID | clock.v | 1,067 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR3,
output reg VAR4,
output reg VAR2
);
reg [8:0] VAR5;
reg [8:0] VAR6;
reg [8:0] VAR1;
always@(posedge clk or negedge reset)
begin
if( ~reset )
begin
VAR4 <= 1;
VAR2 <= 0;
VAR5 <= 0;
VAR6 <= 63;
VAR1 <= 127;
end
else if( VAR3 )
begin
VAR1 <= VAR1;
if( VAR5... | gpl-3.0 |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/axi_slave_wr.v | 15,054 | module MODULE1 (
VAR42, VAR18, VAR30, VAR50, VAR93, VAR16,
VAR84, VAR54, VAR46,
VAR2, VAR29, VAR75,
VAR80, VAR43, reset, VAR98, VAR82, VAR27, VAR85, VAR60, VAR64,
VAR102, VAR57, VAR10, VAR68, VAR14, VAR41, VAR65, VAR35, VAR71,
VAR44
);
parameter VAR92 = 12; parameter VAR94 = 32; parameter VAR63 = 32; parameter VAR5 = 8... | lgpl-3.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s1_jtag_debug_module_wrapper.v | 10,200 | module MODULE1 (
VAR36,
VAR12,
clk,
VAR35,
VAR50,
VAR7,
VAR1,
VAR55,
VAR41,
VAR19,
VAR4,
VAR53,
VAR30,
VAR43,
VAR18,
VAR20,
VAR44,
VAR23,
VAR34,
VAR51,
VAR26,
VAR3,
VAR33,
VAR39,
VAR59,
VAR21,
VAR28,
VAR17,
VAR56,
VAR37,
VAR48,
VAR8,
VAR2,
VAR6,
VAR52,
VAR25
)
;
output [ 37: 0] VAR26;
output VAR3;
output VAR33;
output ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi_4.v | 2,457 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR10 ,
VAR9 ,
VAR3 ,
VAR11 ,
VAR7,
VAR4,
VAR6 ,
VAR8
);
output VAR12 ;
input VAR2 ;
input VAR10 ;
input VAR9 ;
input VAR3 ;
input VAR11 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR8 ;
VAR5 VAR1 (
.VAR12(VAR12),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR11(VAR11),
.VA... | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/xilinx/CLK_DIV2.v | 3,598 | module MODULE1 (
input VAR3,
input VAR1,
output reg VAR2
);
always @ (posedge VAR1 or posedge VAR3)
if (VAR3)
VAR2 <=0;
else
VAR2 <=!VAR2;
endmodule | apache-2.0 |
jakubfi/mera400f | src/fps.v | 8,641 | module MODULE1(
input VAR42,
input VAR133,
input VAR129,
output VAR72,
output VAR144,
output VAR160,
output VAR134,
input VAR97,
input VAR114,
input VAR44,
input VAR67, input VAR93,
input VAR68,
input VAR107,
output VAR139, output VAR171, output 0f,
input VAR117,
input VAR64,
input VAR165,
input VAR21,
output 0t,
outpu... | gpl-2.0 |
plindstroem/oh | elink/hdl/etx_remap.v | 1,785 | module MODULE1 (
VAR11, VAR13,
clk, reset, VAR5, VAR2, VAR8,
VAR3, VAR12, VAR10
);
parameter VAR16 = 32;
parameter VAR7 = 32;
parameter VAR15 = 104;
parameter VAR4 = 12'h808;
input clk;
input reset;
input VAR5;
input [VAR15-1:0] VAR2;
input VAR8; input VAR3;
output VAR11;
output [VAR15-1:0] VAR13;
input VAR12;
input VA... | gpl-3.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/altera_up_rs232_out_serializer.v | 8,121 | module MODULE1 (
clk,
reset,
VAR29,
VAR22,
VAR31,
VAR10
);
parameter VAR30 = 9; parameter VAR2 = 433;
parameter VAR27 = 216;
parameter VAR18 = 11; parameter VAR25 = 9;
input clk;
input reset;
input [VAR25: 0] VAR29;
input VAR22;
output reg [ 7: 0] VAR31;
output reg VAR10;
wire VAR24;
wire VAR17;
wire VAR11;
wire VAR16;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.functional.pp.v | 1,971 | module MODULE1 (
VAR13,
VAR14,
VAR7 ,
VAR9 ,
VAR15 ,
VAR1 ,
VAR2 ,
VAR4
);
input VAR13;
input VAR14;
output VAR7 ;
input VAR9 ;
input VAR15 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
wire VAR2 VAR3 ;
wire VAR16 ;
wire VAR8;
and VAR10 (VAR3 , VAR9, VAR15 );
or VAR5 (VAR16 , VAR2, VAR1, VAR3, VAR4 );
VAR11 VAR6 (VAR8, VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.behavioral.v | 1,433 | module MODULE1 (
VAR5,
VAR4,
VAR9,
VAR1,
VAR7
);
output VAR5;
input VAR4;
input VAR9;
input VAR1;
input VAR7;
supply1 VAR10;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR12 ;
wire VAR11;
nor VAR2 (VAR11, VAR4, VAR9, VAR1, VAR7 );
buf VAR8 (VAR5 , VAR11 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.behavioral.v | 3,096 | module MODULE1( VAR7, VAR6, VAR4, VAR8, VAR2 );
input VAR6, VAR8, VAR4;
output VAR2, VAR7;
VAR1 VAR3(.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2));
VAR1 VAR5(.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
DeadWitcher/amber-de0-nano | hw/vlog/ethmac/eth_miim.v | 15,965 | module MODULE1
(
VAR7,
VAR10,
VAR35,
VAR1,
VAR43,
VAR57,
VAR62,
VAR49,
VAR2,
VAR6,
VAR13,
VAR17,
VAR21,
VAR59,
VAR45,
VAR37,
VAR4,
VAR46,
VAR60,
VAR14,
VAR55
);
input VAR7; input VAR10; input [7:0] VAR35; input [15:0] VAR43; input [4:0] VAR57; input [4:0] VAR62; input VAR1; input VAR49; input VAR2; input VAR6; input VA... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.symbol.v | 1,288 | module MODULE1 (
input VAR3,
input VAR4,
input VAR9,
input VAR2,
output VAR5
);
supply1 VAR6;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/vga512x256/vga.v | 2,286 | module MODULE1 (
input wire clk,
input wire rst,
output wire [12:0] VAR5, input wire [15:0] VAR17, output wire VAR8,
output wire VAR10,
output wire VAR12,
output wire VAR7,
output wire VAR6);
parameter VAR3 = 50; parameter VAR13 = 92; parameter VAR15 = 512; parameter VAR16 = 36;
parameter VAR1 = 4; parameter VAR9 = 61;... | apache-2.0 |
adbrant/zuma-fpga | verilog/platforms/xilinx/lut_xilinx.v | 5,482 | VAR42
module MODULE1(
VAR41,
VAR2,
VAR23,
clk,
VAR47,
VAR27);
input [VAR42-1 : 0] VAR41;
input [0 : 0] VAR2;
input [VAR42-1 : 0] VAR23;
input clk;
input VAR47;
output [0 : 0] VAR27;
VAR9 #(
.VAR8(6),
.VAR30("0"),
.VAR3(64),
.VAR55("VAR19"),
.VAR13(1),
.VAR1(1),
.VAR12(1),
.VAR37(1),
.VAR7(0),
.VAR46(0),
.VAR24(0),
.VAR... | bsd-2-clause |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_ic_mem_router.v | 5,808 | module MODULE1 #(
parameter integer VAR8 = 256,
parameter integer VAR10 = 6,
parameter integer VAR43 = 32,
parameter integer VAR9 = VAR8 / 8,
parameter integer VAR5 = 2
)
(
input logic VAR31,
input logic VAR41,
input logic [VAR5-1:0] VAR36,
input logic VAR27,
input logic VAR26,
input logic VAR34,
input logic VAR32,
inp... | mit |
petrmikheev/miksys | verilog/STARTUP_bb.v | 4,990 | module MODULE1 (
address,
VAR2,
VAR1);
input [8:0] address;
input VAR2;
output [31:0] VAR1;
tri1 VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.behavioral.pp.v | 1,200 | module MODULE1 (
VAR5,
VAR2 ,
VAR1 ,
VAR4 ,
VAR3
);
input VAR5;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.behavioral.pp.v | 1,768 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR11,
VAR12,
VAR9 ,
VAR2
);
output VAR1 ;
input VAR6 ;
input VAR11;
input VAR12;
input VAR9 ;
input VAR2 ;
wire VAR3 ;
wire VAR4;
buf VAR5 (VAR3 , VAR6 );
VAR8 VAR7 (VAR4, VAR3, VAR11, VAR12);
buf VAR10 (VAR1 , VAR4 );
endmodule | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/cmd_fifo.v | 13,795 | module MODULE1(
clk,
rst,
din,
VAR81,
VAR370,
dout,
VAR9,
VAR256
);
input clk;
input rst;
input [7 : 0] din;
input VAR81;
input VAR370;
output [7 : 0] dout;
output VAR9;
output VAR256;
VAR293 #(
.VAR33(0),
.VAR96(0),
.VAR272(0),
.VAR282(0),
.VAR398(0),
.VAR338(0),
.VAR36(0),
.VAR217(32),
.VAR191(1),
.VAR260(1),
.VAR180... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi_1.v | 2,361 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR6 ,
VAR9 ,
VAR3 ,
VAR8,
VAR10,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR10;
input VAR7 ;
input VAR4 ;
VAR2 VAR11 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR... | apache-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/impl/verilog/contact_discovery_AXILiteS_s_axi.v | 25,762 | module MODULE1
VAR140 = 15,
VAR141 = 32
)(
input wire VAR21,
input wire VAR98,
input wire VAR85,
input wire [VAR140-1:0] VAR122,
input wire VAR106,
output wire VAR71,
input wire [VAR141-1:0] VAR107,
input wire [VAR141/8-1:0] VAR54,
input wire VAR125,
output wire VAR79,
output wire [1:0] VAR34,
output wire VAR26,
input ... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_impctl_ddr_uprcn.v | 3,300 | module MODULE1(VAR28 ,VAR2 ,VAR48 ,VAR41 ,VAR34 ,VAR51 ,VAR27 ,
VAR18 ,clk ,VAR32 ,VAR3 );
input [8:1] VAR27 ;
output VAR41 ;
output VAR34 ;
output VAR18 ;
input VAR28 ;
input VAR2 ;
input VAR48 ;
input VAR51 ;
input clk ;
input VAR32 ;
input VAR3 ;
supply1 VAR11 ;
supply0 VAR9 ;
wire VAR33 ;
wire VAR45 ;
wire VAR20 ;
... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.v | 3,216 | if ( VAR28 == VAR1 && VAR15 == VAR10 \
&& VAR32 == VAR12 && VAR27 == VAR6 && VAR11 == VAR29) \
begin : VAR24 \
VAR23 VAR31 (.*); \
end
module MODULE1 #(parameter [31:0] VAR1=1
,parameter VAR10=0
,parameter VAR12=0
,parameter VAR6=0
,parameter VAR29=0
)
( input [4:0][2:0] VAR19
, input VAR9
, input [VAR1-1:0][3:0][1:0] ... | bsd-3-clause |
sirchuckalot/zet | cores/zet/rtl/zet_micro_rom.v | 1,217 | module MODULE1 (
input [VAR1-1:0] addr,
output [VAR3-1:0] VAR4
);
reg [VAR3-1:0] VAR2[0:2**VAR1-1];
assign VAR4 = VAR2[addr]; | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/pcie_data_receiver.v | 5,339 | module MODULE1 #(parameter VAR34 = 128, VAR8 = 8) (
input clk,
input rst,
input VAR28,
output reg VAR3,
output VAR22,
input VAR16,
input[VAR34 - 1:0] VAR19,
input[VAR31 - 1:0] VAR2,
input VAR24,
output[VAR34 - 1:0] VAR12,
output VAR17,
output reg VAR35,
output reg[VAR34 - 1:0] VAR9,
output reg[VAR31 - 1:0] VAR26,
input... | gpl-3.0 |
marqs85/de2-vd | rtl/videoproc.v | 7,319 | module MODULE1(
input VAR102,
input [3:0] VAR79,
input [17:0] VAR33,
input VAR73,
inout VAR59,
inout VAR115,
output VAR43,
inout [7:0] VAR16,
output VAR28,
output VAR62,
output VAR12,
output VAR55,
input [7:0] VAR37,
input [7:0] VAR22,
input [7:0] VAR31,
input VAR66,
input VAR121,
input VAR38,
input VAR20,
output [7:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4.behavioral.pp.v | 1,870 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR13 ,
VAR3 ,
VAR4 ,
VAR7,
VAR6,
VAR11 ,
VAR1
);
output VAR10 ;
input VAR9 ;
input VAR13 ;
input VAR3 ;
input VAR4 ;
input VAR7;
input VAR6;
input VAR11 ;
input VAR1 ;
wire VAR14 ;
wire VAR5;
nor VAR12 (VAR14 , VAR9, VAR13, VAR3, VAR4 );
VAR15 VAR2 (VAR5, VAR14, VAR7, VAR6);
buf VAR8 (V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_4.behavioral.v | 8,879 | module MODULE1( VAR54, VAR32, VAR79, VAR3, VAR1 );
input VAR54, VAR32, VAR3, VAR79;
output VAR1;
reg VAR61;
VAR73 VAR87(.VAR54(VAR54),.VAR32(VAR32),.VAR79(VAR79),.VAR3(VAR3),.VAR1(VAR1),.VAR61(VAR61));
VAR73 VAR28(.VAR54(VAR54),.VAR32(VAR32),.VAR79(VAR79),.VAR3(VAR3),.VAR1(VAR1),.VAR61(VAR61));
not VAR85(VAR20,VAR32);
... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/xilinx_ddr2.v | 11,112 | module MODULE1
(
input [31:0] VAR20,
input [1:0] VAR92,
input [2:0] VAR28,
input VAR147,
input [31:0] VAR157,
input [3:0] VAR140,
input VAR54,
input VAR169,
output VAR57,
output VAR65,
output VAR163,
output [31:0] VAR175,
input [31:0] VAR76,
input [1:0] VAR181,
input [2:0] VAR170,
input VAR58,
input [31:0] VAR146,
inpu... | gpl-2.0 |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/uart.v | 2,074 | module MODULE1 #(
parameter VAR22 = 4'h0,
parameter VAR18 = 50000000,
parameter VAR8 = 115200
) (
input VAR2,
input VAR24,
input [13:0] VAR10,
input VAR11,
input [31:0] VAR4,
output reg [31:0] VAR13,
output VAR16,
output VAR5,
input VAR19,
output VAR14
);
reg [15:0] VAR15;
wire [7:0] VAR3;
wire [7:0] VAR25;
wire VAR23;... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/fifo/afifo16.v | 2,251 | module MODULE1 (
VAR4,
VAR15,
VAR5,
VAR13,
VAR9,
VAR19,
VAR10,
VAR14,
VAR12
);
parameter VAR1 = 16;
input VAR4;
input VAR15;
input VAR5;
output [VAR1-1:0] VAR13;
input VAR9;
input VAR19;
input [VAR1-1:0] VAR10;
output VAR14;
output VAR12;
VAR2 #(VAR1,4,16) VAR16 (
.VAR6 (VAR15),
.VAR18 (VAR9),
.rst (VAR4),
.VAR11 (1'b0... | lgpl-3.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/ip_dram/controller/mig_7series_v2_3_bank_compare.v | 10,847 | module MODULE1 #
(parameter VAR26 = 3,
parameter VAR29 = 100,
parameter VAR72 = "8",
parameter VAR2 = 12,
parameter VAR1 = 8,
parameter VAR37 = "VAR7",
parameter VAR59 = 2,
parameter VAR36 = 4,
parameter VAR19 = 16)
(
VAR82, VAR34, VAR41, VAR81,
VAR23, VAR46, VAR5, VAR13, VAR55,
VAR49, VAR11, VAR63, VAR75, VAR45,
VAR24... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/synth/design_1_xbar_0.v | 20,753 | module MODULE1 (
VAR114,
VAR84,
VAR77,
VAR34,
VAR97,
VAR45,
VAR66,
VAR93,
VAR121,
VAR39,
VAR54,
VAR109,
VAR48,
VAR126,
VAR4,
VAR79,
VAR102,
VAR52,
VAR63,
VAR25,
VAR89,
VAR29,
VAR41,
VAR1,
VAR15,
VAR112,
VAR56,
VAR31,
VAR38,
VAR35,
VAR127,
VAR6,
VAR85,
VAR27,
VAR117,
VAR96,
VAR110,
VAR8,
VAR95,
VAR20,
VAR44,
VAR12,
VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3.pp.symbol.v | 1,286 | module MODULE1 (
input VAR1 ,
input VAR5 ,
input VAR7 ,
output VAR8 ,
input VAR3 ,
input VAR6,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp.blackbox.v | 1,489 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR1 ,
VAR7 ,
VAR5 ,
VAR9 ,
VAR10
);
output VAR2 ;
output VAR6 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR9 ;
input VAR10;
supply1 VAR11;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_2.behavioral.pp.v | 8,974 | module MODULE1( VAR43, VAR90, VAR73, VAR31, VAR89, VAR14, VAR83 );
input VAR31, VAR73, VAR43, VAR90;
inout VAR14, VAR83;
output VAR89;
reg VAR80;
VAR3 VAR30(.VAR43(VAR43),.VAR90(VAR90),.VAR73(VAR73),.VAR31(VAR31),.VAR89(VAR89),.VAR14(VAR14),.VAR83(VAR83),.VAR80(VAR80));
VAR3 VAR88(.VAR43(VAR43),.VAR90(VAR90),.VAR73(VAR... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_addr_cmd_wrap.v | 55,196 | module MODULE1
VAR19 = 2,
VAR30 = 2, VAR212 = 16, VAR113 = 16, VAR72 = 12, VAR171 = 3, VAR51 = 1,
VAR60 = 3,
VAR202 = 2,
VAR186 = 2,
VAR173 = 8,
VAR53 = 4,
VAR1 = 4,
VAR175 = 1,
VAR62 = 2,
VAR147 = 5,
VAR157 = 5,
VAR84 = 5,
VAR56 = 4,
VAR23 = 4,
VAR5 = 2
)
(
VAR86,
VAR10,
VAR29,
VAR9,
VAR38,
VAR177,
VAR158,
VAR167,
VAR... | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pipe_sync.v | 27,149 | module MODULE1 #
(
parameter VAR3 = "VAR4", parameter VAR25 = "VAR108", parameter VAR73 = "VAR9", parameter VAR109 = 0, parameter VAR87 = 0, parameter VAR30 = 1, parameter VAR86 = 3, parameter VAR72 = 0, parameter VAR40 = 0
)
(
input VAR24,
input VAR13,
input VAR76,
input VAR60,
input VAR20,
input VAR65,
input VAR80,
i... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_top.v | 54,010 | module MODULE1 #
(
parameter VAR235 = 100,
parameter VAR42 = 2, parameter VAR255 = 3333, parameter VAR89 = 300.0, parameter VAR95 = "VAR63", parameter [7:0] VAR273 = 8'b00000001,
parameter [7:0] VAR20 = 8'b00000000,
parameter VAR176 = 2, parameter VAR3 = 1, parameter VAR94 = 10, parameter VAR217 = 1, parameter VAR212 =... | mit |
gralco/mojo-ide | Mojo IDE/build/shared/base/mojo-v2/source/avr_interface.v | 2,237 | module MODULE1(
input clk,
input rst,
input VAR7,
output VAR45,
input VAR9,
input VAR1,
input VAR15,
output [3:0] VAR46,
output VAR25,
input VAR47,
input [3:0] VAR41,
output VAR22,
output [9:0] VAR10,
output [3:0] VAR42,
input [7:0] VAR43,
input VAR27,
output VAR29,
input VAR28,
output [7:0] VAR2,
output VAR37
);
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1.functional.v | 1,759 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR3,
VAR4
);
output VAR9 ;
input VAR10 ;
input VAR3;
input VAR4;
wire VAR5 ;
wire VAR1;
not VAR8 (VAR5 , VAR10 );
VAR7 VAR2 (VAR1, VAR5, VAR3, VAR4);
buf VAR6 (VAR9 , VAR1 );
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/submodules/ik_swift_master_0.v | 19,029 | module MODULE1 #(
parameter VAR15 = 0,
parameter VAR37 = 50000,
parameter VAR11 = 2
) (
input wire VAR26, input wire VAR29, output wire [31:0] VAR4, input wire [31:0] VAR39, output wire VAR31, output wire VAR2, output wire [31:0] VAR8, input wire VAR5, input wire VAR21, output wire [3:0] VAR1, output wire VAR47 );
wire... | mit |
azonenberg/openfpga | hdl/xc2c-model/XC2CAndArrayJIT.v | 2,488 | module MODULE1(VAR3, VAR1, VAR2);
input wire VAR3;
input wire VAR1;
input wire VAR2;
endmodule | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.symbol.v | 1,414 | module MODULE1 (
input VAR8 ,
output VAR6 ,
input VAR5,
input VAR7,
input VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v | 8,787 | module MODULE1 #
(
parameter VAR23 = "none",
parameter integer VAR12 = 1,
parameter integer VAR18 = 32,
parameter integer VAR40 = 32,
parameter integer VAR41 = 0,
parameter integer VAR16 = 1,
parameter integer VAR9 = 1,
parameter integer VAR10 = 1
)
(
input wire VAR6,
input wire VAR24,
input wire VAR27,
input wire VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.behavioral.v | 1,854 | module MODULE1 (
VAR1 ,
VAR15 ,
VAR3 ,
VAR4 ,
VAR9 ,
VAR8 ,
VAR13 ,
VAR2,
VAR14
);
output VAR1 ;
input VAR15 ;
input VAR3 ;
input VAR4 ;
input VAR9 ;
input VAR8 ;
input VAR13 ;
input VAR2;
input VAR14;
wire VAR11 ;
wire VAR12;
VAR16 VAR7 (VAR11 , VAR15, VAR3, VAR4, VAR9, VAR8, VAR13 );
VAR5 VAR6 (VAR12, VAR11, VAR2, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.functional.v | 1,468 | module MODULE1 (
VAR3 ,
VAR5,
VAR6,
VAR2,
VAR4
);
output VAR3 ;
input VAR5;
input VAR6;
input VAR2;
input VAR4;
wire VAR10 ;
wire VAR1;
or VAR8 (VAR10 , VAR6, VAR5 );
nand VAR9 (VAR1, VAR4, VAR10, VAR2);
buf VAR7 (VAR3 , VAR1 );
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Mat2AXIvideo.v | 44,777 | module MODULE1 (
VAR50,
VAR45,
VAR56,
VAR72,
VAR38,
VAR147,
VAR67,
VAR30,
VAR97,
VAR6,
VAR128,
VAR143,
VAR73,
VAR37,
VAR11,
VAR124,
VAR145,
VAR12,
VAR156,
VAR105,
VAR65,
VAR75,
VAR121,
VAR24,
VAR141,
VAR59,
VAR153,
VAR113,
VAR104,
VAR62,
VAR61
);
parameter VAR1 = 4'd1;
parameter VAR84 = 4'd2;
parameter VAR58 = 4'd4;
pa... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/io/rom/rtl/rom.v | 1,576 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR5, input wire VAR11, input wire [VAR9] addr, output wire [VAR6] VAR3, output reg VAR12 );
VAR10 VAR10 (
.VAR14 (clk), .VAR1 (addr), .VAR4 (VAR3) );
always @(posedge clk or VAR8 reset) begin
if (reset == VAR2) begin
VAR12 <= VAR13;
end else begin
if ((VAR5... | apache-2.0 |
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