repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
HeberthVG/papiGB | rtl/VgaController.v | 5,269 | module MODULE1
(
input wire VAR26,
input wire VAR25,
output wire [3:0] VAR30,VAR37,VAR3,
output wire VAR38, output wire VAR1, output wire [15:0] VAR51,VAR53
);
wire VAR44,VAR2,VAR21,VAR6;
parameter VAR10 = 1024;
parameter VAR39 = 24;
parameter VAR14 = 136;
parameter VAR4 = 48;
parameter VAR19 = 1344;
parameter VAR31 = ... | gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_PRE_FIFO.v | 13,451 | module MODULE1(
rst,
VAR62,
VAR285,
din,
VAR241,
VAR304,
dout,
VAR77,
VAR61,
valid
);
input rst;
input VAR62;
input VAR285;
input [7 : 0] din;
input VAR241;
input VAR304;
output [63 : 0] dout;
output VAR77;
output VAR61;
output valid;
VAR110 #(
.VAR85(0),
.VAR265(0),
.VAR240(0),
.VAR384(0),
.VAR353(0),
.VAR141(0),
.VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap.functional.pp.v | 1,197 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/select/select.v | 1,250 | module MODULE1
parameter VAR12 =128,
parameter VAR9 =7
)
(
clk,
rst,
VAR1,
VAR8,
VAR18,
VAR10,
VAR17,
VAR5,
VAR14,
VAR15,
VAR16,
VAR7,
VAR2
);
function integer VAR13;
input [31:0] VAR11;
reg [31:0] VAR4;
begin
VAR4 = VAR11 - 1;
for (VAR13=0; VAR4>0; VAR13=VAR13+1)
VAR4 = VAR4>>1;
end
endfunction
localparam VAR19 = VAR1... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/parse/IPv6_LISP/parser_pkt_disp.v | 7,496 | module MODULE1(
input clk,
input reset,
input VAR26,
input [138:0] VAR13,
input VAR28,
input [138:0] VAR3,
input VAR44,
input [359:0] VAR18,
output reg VAR31,
output reg [138:0] VAR46,
input [7:0] VAR12,
output reg VAR47,
output reg [359:0] VAR9,
output reg [138:0] VAR30,
output reg VAR22,
input [7:0] VAR16,
output reg... | apache-2.0 |
lvd2/ngs | fpga/pgmflash/top.v | 4,255 | module MODULE1(
input wire VAR8, input wire VAR42,
output wire VAR56, output wire VAR77,
input wire VAR70,
inout wire [ 7:0] VAR68, output wire [15:0] VAR81,
input wire VAR48, input wire VAR26, input wire VAR80, input wire VAR54, input wire VAR16, output wire VAR9, output wire VAR29, output wire VAR47, input wire VAR35... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/mmio_if/mmio_if_bb.v | 1,032 | module MODULE1 (
VAR13,
VAR5,
VAR1,
VAR7,
VAR6,
VAR19,
VAR3,
VAR21,
VAR17,
VAR8,
VAR15,
VAR9,
VAR11,
VAR22,
VAR14,
VAR20,
VAR10,
VAR18,
VAR4,
VAR2,
VAR12,
VAR16);
input VAR13;
output [14:0] VAR5;
output [2:0] VAR1;
output VAR7;
output VAR6;
output VAR19;
output VAR3;
output VAR21;
output VAR17;
output VAR8;
output VAR1... | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/prcfg/default/prcfg_dac.v | 3,354 | module MODULE1(
clk,
VAR8,
VAR9,
VAR2,
VAR6,
VAR3,
VAR1,
VAR5,
VAR7
);
localparam VAR4 = 8'hA0;
parameter VAR10 = 0;
input clk;
input [31:0] VAR8;
output [31:0] VAR9;
output VAR2;
input [15:0] VAR6;
output VAR3;
input VAR1;
output [15:0] VAR5;
input VAR7;
reg VAR2;
reg VAR3;
reg [15:0] VAR5;
assign VAR9 = {24'h0, VAR4}... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/DE2-115/fpga/rtl/hex_display.v | 2,106 | module MODULE1 #(
parameter VAR1 = 0
)
(
input wire [3:0] in,
input wire enable,
output wire [6:0] out
);
reg [6:0] VAR2;
always @* begin
VAR2 <= 7'b0000000;
if (enable) begin
case (in)
4'h0: VAR2 <= 7'b0111111;
4'h1: VAR2 <= 7'b0000110;
4'h2: VAR2 <= 7'b1011011;
4'h3: VAR2 <= 7'b1001111;
4'h4: VAR2 <= 7'b1100110;
4'h5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.blackbox.v | 1,308 | module MODULE1 (
VAR2,
VAR6,
VAR5,
VAR3,
VAR8
);
output VAR2;
input VAR6;
input VAR5;
input VAR3;
input VAR8;
supply1 VAR1;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
cliffordwolf/yosys | techlibs/nexus/dsp_map.v | 1,671 | module \VAR20 (input [35:0] VAR3, input [35:0] VAR19, output [71:0] VAR2);
parameter VAR13 = 36;
parameter VAR7 = 36;
parameter VAR24 = 72;
parameter VAR14 = 0;
parameter VAR11 = 0;
VAR9 #(
.VAR15("VAR8"),
.VAR23("VAR8"),
.VAR22("VAR8")
) VAR21 (
.VAR3(VAR3), .VAR19(VAR19),
.VAR1(VAR14 ? 1'b1 : 1'b0),
.VAR18(VAR11 ? 1'... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.pp.blackbox.v | 1,408 | module MODULE1 (
VAR5 ,
VAR9,
VAR6,
VAR4 ,
VAR8 ,
VAR3,
VAR7,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR9;
input VAR6;
input VAR4 ;
input VAR8 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/dma2eth_intercon/src/dma_axis_control_if.v | 3,188 | module MODULE1
parameter VAR20 = 32,
parameter VAR1 = 32,
parameter VAR7 = 32,
parameter VAR29 = 32,
parameter VAR28 = 32,
parameter VAR18 = 32,
parameter VAR31 = 1
)
(
input VAR19,
input VAR25,
input VAR2,
input [11:0] VAR23,
input VAR6,
input VAR35,
input VAR3,
output VAR39,
input [VAR29-1 : 0] VAR26,
input [(VAR29/8... | lgpl-2.1 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/hci/hci_back.v | 23,503 | module MODULE1
(
input wire clk, input wire rst, input wire VAR73, output wire VAR31,
input wire VAR38, output wire [15:0] VAR82, input wire [ 7:0] VAR72, output reg [ 7:0] VAR6, output reg VAR34,
output wire VAR22, output reg VAR84, output reg [ 3:0] VAR83, output reg [ 7:0] VAR78, input wire [ 7:0] VAR52,
output reg ... | mit |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkCSR_MIP.v | 9,941 | module MODULE1(VAR38,
VAR5,
VAR70,
VAR64,
VAR35,
VAR50,
VAR34,
VAR46,
VAR54,
VAR20,
VAR23,
VAR24,
VAR7,
VAR65,
VAR60,
VAR31,
VAR39);
input VAR38;
input VAR5;
input VAR70;
output [63 : 0] VAR64;
input [27 : 0] VAR35;
input [63 : 0] VAR50;
input VAR34;
output [63 : 0] VAR46;
output [63 : 0] VAR54;
input [27 : 0] VAR20;
i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.pp.symbol.v | 1,330 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR8 ,
input VAR9 ,
output VAR6 ,
input VAR4 ,
input VAR2,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axis_infrastructure_v1_1/hdl/verilog/axis_infrastructure_v1_1_util_axis2vector.v | 7,848 | module MODULE1 #
(
parameter integer VAR42 = 32,
parameter integer VAR30 = 1,
parameter integer VAR31 = 1,
parameter integer VAR3 = 1,
parameter integer VAR11 = 44,
parameter [31:0] VAR33 = 32'hFF
)
(
input wire [VAR42-1:0] VAR1,
input wire [VAR42/8-1:0] VAR6,
input wire [VAR42/8-1:0] VAR21,
input wire VAR27,
input wir... | gpl-3.0 |
eecsninja/duinocube-core | altera/tilemap_ram_4Kx16.v | 11,476 | module MODULE1 (
VAR1,
VAR18,
VAR26,
VAR46,
VAR27,
VAR24,
VAR56,
VAR32,
VAR39,
VAR36,
VAR60,
VAR62,
VAR33);
input [11:0] VAR1;
input [11:0] VAR18;
input [1:0] VAR26;
input VAR46;
input VAR27;
input [15:0] VAR24;
input [15:0] VAR56;
input VAR32;
input VAR39;
input VAR36;
input VAR60;
output [15:0] VAR62;
output [15:0] V... | gpl-3.0 |
kyzhai/NUNY | src/hardware/pizza_bb.v | 4,976 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp_macc_r.v | 4,810 | module MODULE1(
VAR9, VAR18, VAR29,
VAR22, VAR14, VAR30,
VAR2, VAR28, VAR12,
VAR20, VAR8, VAR4, VAR7, VAR34
);
output [149:0] VAR9; output VAR18;
output VAR29;
input VAR22; input VAR14; input VAR30; input VAR2; input VAR28; input [149:0] VAR12; input [149:0] VAR20;
input [149:0] VAR8;
input VAR4;
input VAR7;
input VAR3... | gpl-2.0 |
devdraweat/computer_processor | register_file/register_file.v | 6,262 | module MODULE4(in, enable, out);
input [31:0] in;
input enable;
output [31:0] out;
wire [31:0] in, out;
wire enable;
assign out = (enable) ? in : 32'VAR14;
endmodule
module MODULE2(in, enable, VAR20, reset, out);
input in, enable, VAR20, reset;
output out;
reg out;
always @ (posedge VAR20 or posedge reset) begin
if (re... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/Tenth_Phase.v | 2,495 | module MODULE1
(
input wire clk, input wire rst, input wire VAR8,
input wire VAR9, input wire VAR22, input wire VAR33, input wire [VAR30-1:0] VAR25, input wire [VAR5-1:0] VAR26, output wire [VAR32-1:0] VAR21 );
wire [VAR5-1:0] VAR24;
wire [VAR30-1:0] VAR6;
wire VAR28;
wire [VAR32-1:0] VAR16;
wire VAR12;
wire [VAR30-1:0... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/phyIniCommand1_and.v | 1,183 | module MODULE1
(
input [(VAR1-1):0] VAR3,
input [(VAR5-1):0] addr,
input VAR2, clk,
output [(VAR1-1):0] VAR4
);
reg [VAR1-1:0] VAR6[2**VAR5-1:0];
reg [VAR5-1:0] VAR7;
begin | gpl-3.0 |
darekb74/WSIZ_SW_Projekt1 | Maszyna_do_kawy.srcs/sources_1/new/counter.v | 3,939 | module MODULE1(clk, VAR4, VAR2, VAR19);
input clk;
input [3:0] VAR4;
output reg VAR2;
output wire [6:0]VAR19;
reg [22:0] VAR5 = 0; parameter VAR10 = 20; integer VAR9 = 1000000/VAR10;
assign VAR19 = VAR5/VAR9;
always @(VAR4)
begin
case (VAR4)
VAR2 <= VAR6;
VAR5 <= 0;
end
VAR2 = VAR7;
VAR5 = VAR3*VAR9;
end
VAR2 = VAR7;
V... | gpl-3.0 |
Chapna/TTCache | src/set_t.v | 1,097 | module MODULE1;
reg [0:15] VAR1;
reg [0:4] VAR5;
reg enable;
reg write;
reg [0:1] word;
reg VAR4;
reg VAR6;
reg rst;
wire [0:15] VAR2;
wire [0:4] VAR3;
wire VAR7;
wire VAR8;
wire valid;
wire ack; | gpl-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_1/affine_block_ieee754_fp_to_uint_0_1_stub.v | 1,322 | module MODULE1(VAR1, VAR2)
;
input [31:0]VAR1;
output [9:0]VAR2;
endmodule | mit |
mda-ut/SubZero | fpga/fpga_hw/top_level/SONAR/ShiftRegisterWEnableSixteen.v | 1,284 | module MODULE1(clk, VAR1, enable, VAR14, VAR5);
input clk;
input VAR1;
input enable;
input VAR14;
output [15:0] VAR5;
VAR15 VAR8(clk, VAR1, enable, VAR14, VAR5[0]);
VAR15 VAR19(clk, VAR1, enable, VAR5[0], VAR5[1]);
VAR15 VAR20(clk, VAR1, enable, VAR5[1], VAR5[2]);
VAR15 VAR3(clk, VAR1, enable, VAR5[2], VAR5[3]);
VAR15 ... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/bytefifo.v | 7,679 | module MODULE1 (
VAR8,
VAR4,
VAR15,
VAR16,
VAR14,
VAR2,
VAR19,
VAR12
);
input VAR8;
input VAR4;
input [7:0] VAR15;
output [7:0] VAR16;
input VAR14;
input VAR2;
output [3:0] VAR19;
output [3:0] VAR12;
reg [7:0] VAR6, VAR11, VAR18, VAR10, VAR17, VAR3, VAR7, VAR1;
reg [3:0] counter;
reg [7:0] VAR16;
wire [3:0] VAR19;
wire... | mit |
lsnow/mips32 | addsub.v | 1,347 | module MODULE1(
VAR2,VAR3,
VAR6, VAR1, VAR4, MODULE1
);
input [31:0] VAR6;
input [31:0] VAR1;
input VAR4;
input MODULE1;
output VAR3;
reg [32:0] VAR5;
output reg [31:0] VAR2;
always @(MODULE1 or VAR6 or VAR1 or VAR4) begin
case ({MODULE1, VAR4})
00:
VAR5 <= {VAR6[31], VAR6} + {VAR1[31], VAR1};
01:
VAR5[31:0] <= VAR6 + ... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_dtcm_ram.v | 2,560 | module MODULE1(
input VAR8,
input VAR15,
input VAR11,
input VAR14,
input VAR16,
input [VAR1-1:0] addr,
input [VAR7-1:0] VAR2,
input [VAR13-1:0] din,
output [VAR13-1:0] dout,
input VAR9,
input clk
);
VAR10 #(
.VAR17(1), .VAR5(VAR18),
.VAR6(VAR13),
.VAR12(VAR7),
.VAR3(VAR1)
) VAR4(
.VAR8 (VAR8 ),
.VAR15 (VAR15 ),
.VAR11 ... | apache-2.0 |
MegabytePhreak/Verilog-Perl | verilog/parser_bugs.v | 10,731 | module MODULE2 ();
wire [0:3] VAR1;
wire VAR6 = VAR1[2];
endmodule
module MODULE1 ();
assign VAR4 = {1'b0,VAR6} +{1'b0,VAR1};
VAR5 VAR3 (.VAR4(VAR4),.VAR6(VAR2),.VAR1(VAR2)); | artistic-2.0 |
eda-globetrotter/PicenoDecoders | andy/design/commschannel.v | 11,728 | module MODULE1();
wire VAR11; wire [1:0] VAR9; wire [1:0] VAR28; wire VAR5; wire [1:0] VAR30;
reg VAR25[0:255];
reg VAR32;
reg [7:0] VAR27;
reg VAR35;
reg VAR10;
reg [7:0] VAR4;
reg [1:0] VAR20;
reg [7:0] VAR21;
wire [1:0] VAR12;
wire [1:0] VAR3;
reg VAR17;
reg [7:0] VAR13;
reg [1:0] VAR15;
reg [1:0] VAR6;
reg VAR7;
re... | mit |
bgelb/digilite_zl | rtl/zl_dvb_s_core.v | 4,949 | module MODULE1
(
input clk,
input VAR54,
input [7:0] VAR41,
input VAR9,
output VAR19,
output VAR16,
output VAR14,
output VAR39,
input VAR60
);
wire VAR62;
wire VAR34;
wire [7:0] VAR52;
VAR33 #
(
.VAR50(8),
.VAR58(8) )
VAR11
(
.clk(clk),
.VAR54(VAR54),
.VAR35(VAR9),
.VAR64(VAR19),
.VAR43(VAR41),
.VAR27(VAR62),
.VAR20(VA... | bsd-2-clause |
pseudoincorrect/FPGA_MCU_wifi | FPGA/src/DPRAM_modules/fifo_spi_DPRAM.v | 8,009 | module MODULE1 (clk, VAR15, VAR44, din, dout, VAR4, VAR18);
input clk;
input VAR15;
input VAR44;
input [31:0] din;
output dout;
output VAR4;
output reg VAR18;
parameter VAR26 = 4'd0;
parameter VAR43 = 4'd1;
parameter VAR46 = 4'd2;
parameter VAR7 = 4'd3;
parameter VAR32 = 4'd4;
parameter VAR24 = 4'd5;
parameter VAR60 = ... | mit |
zhijian-liu/mips-cpu | src/ram.v | 1,306 | module MODULE1(
input VAR11 ,
input VAR10 ,
input VAR8 ,
input [31:0] VAR13 ,
output reg [31:0] VAR2 ,
input VAR7 ,
input [31:0] VAR1,
input [ 3:0] VAR6 ,
input [31:0] VAR5
);
reg [31:0] VAR4[0:1024];
always @ (*) begin
if (VAR10 == VAR12 && VAR8 == VAR9) begin
VAR2 <= VAR4[VAR13[18:2]];
end
else begin
VAR2 <= 32'b0;
e... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv.pp.symbol.v | 1,231 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_sym_gen.v | 10,932 | module MODULE1
(
VAR31,
VAR13,
VAR21,
VAR28,
VAR14,
VAR5,
VAR25,
VAR7,
VAR3,
VAR27,
VAR26,
VAR1,
VAR20,
VAR17,
VAR8,
VAR30
);
input VAR31; input VAR13; input VAR21; input [0:15] VAR28; input VAR14; input VAR5;
input VAR25; input [0:1] VAR7; input [0:1] VAR3; input [0:1] VAR27;
input VAR26; input [0:1] VAR1; input [0:1]... | gpl-2.0 |
velizarefremov/Rijndael | mixColumns.v | 3,565 | module MODULE1(
output [31:0] VAR26, input [31:0] VAR32, input clk, input VAR3 );
wire [31:0] VAR31;
wire [31:0] VAR40;
wire [7:0] VAR7 [0:3]; wire [7:0] VAR37 [0:3]; wire [7:0] VAR25 [0:3];
reg [7:0] VAR8;
reg [7:0] VAR48;
reg [7:0] VAR13;
reg [7:0] VAR11;
reg [7:0] VAR45;
reg [7:0] VAR44;
reg [7:0] VAR38;
reg [7:0] V... | gpl-2.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_vc_arbiter.v | 2,129 | module MODULE1 (request,
VAR2,
VAR24,
VAR9,
clk, VAR20);
parameter VAR7=5;
parameter VAR18=4;
parameter VAR8=2;
parameter VAR5=0;
input [VAR7-1:0][VAR18-1:0][VAR7-1:0] request;
input VAR13 VAR2 [VAR7-1:0][VAR18-1:0];
output [VAR7-1:0][VAR18-1:0][VAR7-1:0] VAR24;
input [VAR7-1:0] VAR9;
input clk, VAR20;
wire [VAR7*VAR18... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2b/sky130_fd_sc_hd__and2b.pp.symbol.v | 1,290 | module MODULE1 (
input VAR2 ,
input VAR6 ,
output VAR7 ,
input VAR3 ,
input VAR1,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_mem_2r1w.v | 2,832 | if (VAR5 == VAR21 && VAR27 == VAR32) \
begin: VAR30 \
wire [VAR5-1:0] VAR33 = (VAR14 << VAR22); \
wire [VAR5-1:0] VAR23 = (VAR10 << VAR19); \
wire [VAR5-1:0] VAR38 = (VAR20 << VAR15); \
\
VAR31 VAR41 \
( .VAR3(VAR7) \
,.VAR35(VAR24) \
,.VAR29(VAR33) \
,.VAR42 ({VAR38,VAR23}) \
,.VAR2({VAR6,VAR1}) \
); \
end
module MODU... | bsd-3-clause |
SiLab-Bonn/basil | basil/firmware/modules/utils/flag_domain_crossing.v | 1,139 | module MODULE1(
input wire VAR3,
input wire VAR6,
input wire VAR9,
output wire VAR5
);
reg VAR7;
VAR4 VAR7 = 0;
always @(posedge VAR3)
begin
if (VAR9)
begin
VAR7 <= ~VAR7;
end
end
reg VAR2;
reg VAR8;
reg VAR1;
always @(posedge VAR6) begin
VAR2 <= VAR7;
end
always @(posedge VAR6) begin
VAR8 <= VAR2;
end
always @(posedge... | bsd-3-clause |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_SMP_CORE_hps_io.v | 1,934 | module MODULE1 (
output wire [12:0] VAR7, output wire [2:0] VAR2, output wire VAR11, output wire VAR18, output wire VAR12, output wire VAR10, output wire VAR15, output wire VAR17, output wire VAR4, output wire VAR6, inout wire [7:0] VAR13, inout wire VAR5, inout wire VAR3, output wire VAR8, output wire VAR1, input wire... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi_1.v | 2,483 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR9,
VAR12,
VAR11 ,
VAR4
);
output VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR9;
input VAR12;
input VAR11 ;
input VAR4 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(V... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_auto_pc_1/synth/gcd_block_design_auto_pc_1.v | 14,706 | module MODULE1 (
VAR38,
VAR3,
VAR110,
VAR8,
VAR36,
VAR85,
VAR37,
VAR45,
VAR5,
VAR49,
VAR26,
VAR89,
VAR51,
VAR76,
VAR92,
VAR109,
VAR61,
VAR59,
VAR100,
VAR57,
VAR93,
VAR16,
VAR12,
VAR75,
VAR15,
VAR23,
VAR79,
VAR78,
VAR107,
VAR31,
VAR64,
VAR112,
VAR40,
VAR69,
VAR4,
VAR35,
VAR41,
VAR63,
VAR111,
VAR6,
VAR97,
VAR18,
VAR32,
V... | mit |
AngelTerrones/MUSB | Hardware/musb/musb_div.v | 4,377 | module MODULE1(
input clk, input rst, input VAR12, input VAR9, input [31:0] VAR1, input [31:0] VAR10, output [31:0] VAR6, output [31:0] VAR8, output VAR4 );
reg VAR14; reg VAR3; reg [4:0] VAR11; reg [31:0] VAR5; reg [31:0] VAR13; reg [31:0] VAR7;
wire [32:0] VAR2;
assign VAR6 = !VAR3 ? VAR5 : -VAR5;
assign VAR8 = VAR7;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.blackbox.v | 1,204 | module MODULE1 (
VAR2 ,
VAR4,
VAR3,
VAR1
);
output VAR2 ;
input VAR4;
input VAR3;
input VAR1 ;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/ecc_buf.v | 6,156 | module MODULE1
parameter VAR46 = 100,
parameter VAR42 = 64,
parameter VAR44 = 4,
parameter VAR35 = 1,
parameter VAR5 = 64
)
(
VAR24,
clk, rst, VAR19, VAR11, VAR16,
VAR20, VAR37, VAR14
);
input clk;
input rst;
input [VAR44-1:0] VAR19;
input [VAR35-1:0] VAR11;
wire [4:0] VAR45;
input [VAR44-1:0] VAR16;
input [VAR35-1:0] ... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/periferico_SD/spi.v | 1,125 | module MODULE1
parameter VAR11=500)
(
input [VAR3-1:0] VAR6,
input en,
input reset,
input clk,
input VAR2,
output reg [VAR3-1:0] VAR8,
output reg VAR10,
output reg VAR4,
output reg VAR12,
output reg VAR5
);
integer VAR13=0;
integer VAR9=0;
reg [VAR3-1:0] VAR1=0;
reg [VAR3-1:0] VAR7=0;
reg VAR14=0;
always @(posedge clk)... | gpl-3.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_tristate_conduit_pin_sharer_0.v | 6,423 | module MODULE1 (
input wire VAR12, input wire VAR16, output wire request, input wire VAR11, output wire [21:0] VAR30, output wire [0:0] VAR13, output wire [0:0] VAR36, output wire [7:0] VAR26, input wire [7:0] VAR28, output wire VAR34, output wire [0:0] VAR31, input wire VAR20, output wire VAR5, input wire [21:0] VAR25... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b_2.v | 2,046 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR4 ,
VAR2,
VAR3
);
output VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR2;
input VAR3;
VAR1 VAR7 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR5 ;
input VAR4;
supply1 VAR2;
supply0 VAR3;
VAR1 VAR7... | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes_obc1/obc1.v | 2,255 | module MODULE1(
input clk,
input enable,
input [7:0] VAR29,
output [7:0] VAR2,
input [12:0] VAR17,
input VAR15
);
reg [7:0] VAR18 [7:0];
wire [6:0] VAR21 = VAR18[6][6:0];
wire VAR27 = VAR18[5][0];
wire VAR30 = enable & ((VAR17 & 13'h1a00) == 13'h1800);
wire VAR26 = enable & ((VAR17 & 13'h1a00) == 13'h1a00);
wire VAR1 =... | gpl-2.0 |
yahniukov/FIFO_Verilog | src/design/rd_memory.v | 1,338 | module MODULE1 ( VAR8, VAR5,
VAR2, VAR1, VAR3, VAR9,
reset );
parameter VAR7 = 1;
parameter VAR10 = 2;
parameter VAR4 = 4;
input wire [VAR4 - 1 : 0] VAR8;
input wire VAR5;
output reg [VAR7 - 1 : 0] VAR2;
input wire [VAR10 - 1 : 0] VAR9;
input wire VAR1, VAR3;
input wire reset;
reg [VAR7 - 1 : 0] memory [VAR4 - 1 : 0];
... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/uart_rx.v | 1,629 | module MODULE1 (input VAR2, input VAR4);
reg [8:0] VAR5 = 9'b0;
reg [3:0] VAR1 = 4'b0;
wire VAR6 = VAR2;
always @(posedge VAR6)
VAR5 <= { VAR4, VAR5[8:1] };
reg [3:0] state = 0;
always @(posedge VAR6)
case(state)
0 :
if(~VAR5[8] & VAR5[7]) state <= 1;
1, 2, 3, 4, 5, 6, 7, 8 :
state <= state + 1;
9 :
begin
state <= 0;
(... | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/logicblock_mul.v | 2,294 | module MODULE1(VAR13, VAR9,
VAR17, VAR21, VAR18,
VAR20, VAR2, VAR24,
VAR27, VAR8, VAR26);
parameter VAR19 = 32;
parameter VAR6 = 64;
input VAR13, VAR9;
input [VAR19-1:0] VAR17;
input [VAR19-1:0] VAR20;
input VAR21, VAR2;
output VAR18, VAR24;
output [VAR19-1:0] VAR27;
output VAR8;
input VAR26;
wire [VAR19-1:0] VAR12;
wi... | mit |
mbus/mbus | mbus/verilog/mbus_ctrl.v | 5,267 | module MODULE1(
input VAR30,
input VAR22,
input VAR38,
output VAR25,
input VAR27,
output reg VAR40,
input [VAR39-1:0] VAR32
);
parameter VAR4 = 0;
parameter VAR13 = 3;
parameter VAR5 = 4;
parameter VAR17 = 1;
parameter VAR10 = 2;
parameter VAR35 = 5;
parameter VAR20 = 7;
parameter VAR33 = 6;
parameter VAR36 = 8;
parame... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_rfram_generic.v | 8,486 | module MODULE1(
clk, rst,
VAR15, VAR7, VAR9,
VAR4, VAR5, VAR8,
VAR13, VAR6, VAR2, VAR10
);
parameter VAR1 = VAR17;
parameter VAR14 = VAR16;
input clk;
input rst;
input VAR15;
input [VAR14-1:0] VAR7;
output [VAR1-1:0] VAR9;
input VAR4;
input [VAR14-1:0] VAR5;
output [VAR1-1:0] VAR8;
input VAR13;
input VAR6;
input [VAR14... | gpl-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/ramdac.v | 20,903 | module MODULE1
(
input VAR97, input VAR28, input VAR150, input VAR112, input VAR63, input VAR65, input [2:0] VAR114, input [7:0] VAR159, input VAR224, input VAR169, input VAR60, input VAR178, input [23:0] VAR76, input VAR111, input VAR140, input VAR93,
output [1:0] VAR187, output VAR14, output VAR202, output VAR6, outp... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/rtl/iop_fpga.v | 3,766 | module MODULE1(VAR11, VAR37,
VAR18,
VAR7,
VAR43,
VAR19,
VAR1,
VAR9
);
output [4:0] VAR18;
output VAR7;
output [123:0] VAR43;
input [4:0] VAR19;
input VAR1;
input [144:0] VAR9;
input VAR11;
input VAR37;
wire VAR29;
wire VAR30;
wire VAR12;
wire VAR14;
wire VAR26;
wire VAR22;
wire VAR33;
wire [3:0] VAR6 = 4'b0000;
wire [7... | gpl-2.0 |
blackmesalabs/sump2 | deep_sump.v | 13,913 | module MODULE1 #
(
parameter VAR43 = 65536,
parameter VAR22 = 16
)
(
input wire reset,
input wire VAR52,
input wire VAR31,
input wire VAR5,
input wire [31:0] VAR37,
input wire [5:0] VAR40,
input wire [5:0] VAR12,
input wire VAR27,
input wire VAR49,
input wire [31:0] VAR55,
output reg [31:0] VAR35,
output reg VAR29,
out... | gpl-3.0 |
hakehuang/pycpld | quartus-II/top_twrkv58/uart_tx.v | 2,784 | module MODULE1(VAR11, VAR12, VAR4, VAR7, VAR10, VAR3, VAR9, VAR1);
input VAR11;
input VAR12;
input VAR4;
input[7:0] VAR7;
output VAR10;
output VAR3;
output VAR9;
output VAR1;
reg VAR13;
always @ (negedge VAR4 or negedge VAR5 or negedge VAR11)
begin
if (!VAR11)
begin
VAR13 <= 1'b0;
end
else if (!VAR5)
VAR13 <= 1'b0;
end... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_burst_gen.v | 68,287 | module MODULE1 #
( parameter
VAR65 = 4,
VAR22 = "VAR163",
VAR50 = 0,
VAR80 = 1,
VAR72 = 1,
VAR126 = 3,
VAR92 = 13,
VAR33 = 10,
VAR57 = 10,
VAR20 = 10,
VAR38 = 4,
VAR82 = 2,
VAR124 = 3,
VAR144 = 5,
VAR49 = 4,
VAR112 = 1,
VAR136 = 1,
VAR94 = 0
)
(
VAR9,
VAR152,
VAR75,
VAR91,
VAR113,
VAR30,
VAR52,
VAR45,
VAR81,
VAR12,
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.v | 2,226 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR9,
VAR10 ,
VAR2 ,
VAR7,
VAR5 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR9;
input VAR10 ;
input VAR2 ;
input VAR7;
input VAR5 ;
input VAR1 ;
VAR8 VAR6 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
SymbiFlow/prjxray | experiments/example/design.v | 2,068 | module MODULE1(input clk, din, VAR34, output dout);
reg [41:0] VAR2;
wire [78:0] VAR1;
reg [41:0] VAR4;
reg [78:0] VAR11;
always @(posedge clk) begin
if (VAR34) begin
VAR2 <= VAR4;
VAR11 <= VAR1;
end else begin
VAR4 <= {VAR4, din};
VAR11 <= {VAR11, VAR4[41]};
end
end
assign dout = VAR11[78];
MODULE2 MODULE2 (
.clk(clk)... | isc |
alexforencich/xfcp | example/S10MX_DK/fpga/rtl/fpga.v | 11,166 | module MODULE1 (
input wire VAR210,
input wire VAR189,
output wire [3:0] VAR98,
output wire [3:0] VAR67,
input wire [3:0] VAR99,
input wire VAR217,
output wire VAR16,
output wire VAR40,
input wire VAR148,
output wire VAR86,
input wire VAR197,
output wire [3:0] VAR108,
input wire [3:0] VAR45,
input wire VAR43,
output wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.pp.symbol.v | 1,324 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/c_and_nto1.v | 2,269 | module MODULE1
(VAR1, VAR3);
parameter VAR9 = 2;
parameter VAR8 = 1;
input [0:VAR8*VAR9-1] VAR1;
output [0:VAR8-1] VAR3;
wire [0:VAR8-1] VAR3;
generate
genvar VAR4;
for(VAR4 = 0; VAR4 < VAR8; VAR4 = VAR4 + 1)
begin:VAR5
wire [0:VAR9-1] VAR6;
genvar VAR2;
for(VAR2 = 0; VAR2 < VAR9; VAR2 = VAR2 + 1)
begin:VAR7
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o_1.v | 2,221 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR2,
VAR5
);
output VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR2;
input VAR5;
VAR6 VAR8 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR9 ,
VAR1,
VAR3,
VAR4,
VAR7
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp.behavioral.pp.v | 2,352 | module MODULE1 (
VAR14 ,
VAR11,
VAR3 ,
VAR19 ,
VAR12 ,
VAR13 ,
VAR9 ,
VAR17
);
output VAR14 ;
input VAR11;
input VAR3 ;
input VAR19 ;
input VAR12 ;
input VAR13 ;
input VAR9 ;
input VAR17 ;
wire VAR5 ;
reg VAR20 ;
wire VAR15 ;
wire VAR21 ;
wire VAR2 ;
wire VAR16;
wire VAR22 ;
wire VAR6 ;
wire VAR1 ;
wire VAR10 ;
not VAR... | apache-2.0 |
lsnow/mips32 | ID_stage.v | 2,944 | module MODULE1(
clk, rst, VAR21, VAR25, VAR24, VAR3,
VAR10, VAR5, VAR28, VAR1,
VAR27, VAR2, VAR17, VAR19,
VAR4, VAR12, VAR16, VAR11,
VAR8, VAR14, VAR9,
VAR18, VAR22, VAR26, VAR15, VAR13, VAR20,
VAR7, VAR23, VAR6);
input clk;
input rst;
input VAR21;
input VAR25;
input VAR24;
input [4:0] VAR3;
input [31:0] VAR10, VAR5, V... | gpl-2.0 |
Microsoft/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX.v | 13,846 | module MODULE4(VAR32, VAR41, VAR17, VAR12, VAR4, VAR27, VAR57, VAR42, VAR45);
input VAR32, VAR41;
input [31:0] VAR17;
output [31:0] VAR12;
output VAR42;
output VAR45;
input VAR4, VAR27, VAR57;
wire [31:0] VAR17;
wire [7:0] VAR20;
wire [7:0] VAR24;
wire [7:0] VAR30;
wire [7:0] VAR5;
MODULE1 MODULE6 (
.VAR32(VAR32), .VAR... | bsd-2-clause |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_mmcm_drp.v | 8,050 | module MODULE1 #(
parameter VAR106 = 0,
parameter VAR41 = 1.667,
parameter VAR52 = 1.667,
parameter VAR48 = 6,
parameter VAR12 = 12.000,
parameter VAR93 = 2.000,
parameter VAR78 = 0.000,
parameter VAR82 = 6,
parameter VAR30 = 0.000,
parameter VAR69 = 2.000,
parameter VAR49 = 0.000) (
input clk,
input VAR28,
input VAR63... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/tlu_hyperv.v | 108,432 | module MODULE1 (
VAR298, VAR181, VAR237, VAR456,
VAR131, VAR326, VAR403,
VAR339, VAR42, VAR60, VAR356, VAR381,
VAR3, VAR262, VAR321, VAR169,
VAR412, VAR210, VAR24, VAR345,
VAR55, VAR354, VAR409,
VAR65, VAR461, VAR12, VAR239,
VAR282, VAR102, VAR318, VAR391,
VAR430, VAR419, VAR400, VAR233, VAR133,
VAR79, VAR269, VAR226, ... | gpl-2.0 |
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner | projects/X6000_ztex_comm4/hdl/fpgaminer_top.v | 5,072 | module MODULE1 (
input VAR37
);
localparam VAR49 = 100;
localparam VAR13 = 200;
localparam VAR50 = 50;
localparam VAR48 = 250;
wire VAR21;
VAR36 VAR8 ( .VAR14 (VAR37), .VAR28 (VAR21));
reg [255:0] VAR45 = 0;
reg [95:0] VAR51 = 0;
reg [31:0] VAR38 = 32'd253, VAR53 = 32'd0;
wire VAR57;
wire VAR27, VAR44, VAR11;
VAR24 # (... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_milfsm.v | 13,982 | module MODULE1(
VAR16, VAR53, VAR43, VAR48,
VAR35, VAR31, VAR36,
VAR61, VAR27, VAR56,
VAR19, VAR41,
VAR54, VAR2,
VAR7, VAR17, VAR3,
VAR15, VAR10, VAR39,
VAR22, VAR4,
VAR34, clk, VAR63, VAR20, reset, VAR29
);
input VAR54,
VAR2;
input VAR7;
input VAR17;
input VAR3;
input [1:0] VAR15;
input VAR10;
input VAR39;
input VAR22... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fa/sky130_fd_sc_hs__fa_2.v | 2,151 | module MODULE2 (
VAR9,
VAR5 ,
VAR3 ,
VAR6 ,
VAR1 ,
VAR2,
VAR4
);
output VAR9;
output VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR2;
input VAR4;
VAR8 VAR7 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR9,
VAR5 ,
VAR3 ,
VAR6 ,
VAR1
)... | apache-2.0 |
efabless/openlane | designs/jpeg_encoder/src/fdct.v | 9,750 | module MODULE1(clk, VAR48, rst, VAR92, din, dout, VAR162);
parameter VAR137 = 11;
parameter VAR115 = 8;
parameter VAR11 = 12;
input clk; input VAR48; input rst;
input VAR92; input [VAR115-1:0] din;
output [VAR11-1:0] dout;
output VAR162;
wire VAR46;
wire [VAR11 -1:0] VAR5, VAR78, VAR53, VAR74, VAR116, VAR153, VAR28, VA... | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_alu_0_0/RAT_alu_0_0_stub.v | 1,358 | module MODULE1(VAR5, VAR2, VAR4, VAR3, VAR6, VAR1, VAR7)
;
input [7:0]VAR5;
input [7:0]VAR2;
input VAR4;
input [3:0]VAR3;
output [7:0]VAR6;
output VAR1;
output VAR7;
endmodule | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_itu_656_decoder.v | 7,493 | module MODULE1 (
clk,
reset,
VAR25,
ready,
VAR7,
VAR3,
VAR16,
valid
);
input clk;
input reset;
input [ 7: 0] VAR25;
input ready;
output [15: 0] VAR7;
output VAR3;
output VAR16;
output valid;
wire VAR6;
wire VAR12;
wire VAR14;
wire [ 7: 0] VAR9;
reg [ 7: 0] VAR29;
reg [ 7: 0] VAR27 [ 5: 1];
reg VAR11;
reg [ 6: 1] VAR20;... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/FxP_ABS_Function.v | 1,126 | module MODULE1
parameter VAR2 = 16
)
(
input [VAR2-1:0] VAR1,
output [VAR2-1:0] VAR3
);
assign VAR3 = VAR1[VAR2-1] ? ~VAR1 + 1'b1 : VAR1;
endmodule | mit |
dekuNukem/FAP_Z80 | FAP_modules/video_card/FPGA_code/src/pc_vga_8x16_00_7F.v | 7,015 | module MODULE1 (
input clk,
input [6:0] VAR34,
input [3:0] VAR8,
input [2:0] VAR63,
output wire VAR13
);
VAR24 VAR67 (
.VAR22(clk),
.VAR50(1'b1),
.VAR45(1'b0),
.VAR47({VAR34[6:1], ~VAR34[0], VAR8, ~VAR63}),
.VAR41(1'b0),
.VAR60(1'b0),
.VAR65(VAR13)
);
endm... | mit |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/ServoController_vlg_tst.v | 1,300 | module MODULE1();
reg clk;
reg enable;
reg [7:0] VAR5;
wire VAR3;
VAR1 #(.VAR4(8)) VAR2 ( .VAR6( VAR3 ), .VAR7( VAR5 ), .VAR8( enable ), .clk( clk ) );
begin | gpl-3.0 |
MForever78/CPUFly | ipcore_dir/Video_Memory.v | 4,088 | module MODULE1(
VAR28,
VAR32,
VAR43,
clk,
VAR2,
VAR37,
VAR18
);
input [11 : 0] VAR28;
input [15 : 0] VAR32;
input [11 : 0] VAR43;
input clk;
input VAR2;
output [15 : 0] VAR37;
output [15 : 0] VAR18;
VAR22 #(
.VAR24(12),
.VAR26("0"),
.VAR4(2400),
.VAR58("VAR20"),
.VAR51(1),
.VAR1(1),
.VAR29(1),
.VAR23(1),
.VAR50(0),
.VA... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly3_16.v | 3,569 | module MODULE1(
enable,
VAR21,
VAR2,
VAR4,
VAR7,
VAR27,
VAR1,
VAR28,
VAR25,
VAR30,
VAR11,
VAR13,
VAR26,
VAR19,
VAR15,
VAR24,
VAR22,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR3 ,
VAR9 ,
o10,
o11,
o12,
o13,
o14,
o15
);
input enable;
input signed [27:0] VAR21;
input signed [27:0] VAR2;
input signed [27:0] VAR4;
input signed [27:... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/micron/ddr_sdram/ddr2.v | 130,498 | module MODULE1 (
VAR109,
VAR43,
VAR75,
VAR102,
VAR42,
VAR73,
VAR134,
VAR44,
VAR3,
addr,
VAR133,
VAR150,
VAR72,
VAR93,
VAR52
);
parameter VAR111 = 2500; parameter VAR159 = 100; parameter VAR167 = 100; parameter VAR88 = 200; parameter VAR107 = 150; parameter VAR15 = 175; parameter VAR85 = 200; parameter VAR105 = 200; par... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_jesd_align_2.v | 3,759 | module MODULE1 (
VAR2,
VAR10,
VAR4,
VAR9,
VAR5,
VAR8,
VAR1);
input VAR2;
input [ 3:0] VAR10;
input [ 3:0] VAR4;
input [ 3:0] VAR9;
input [31:0] VAR5;
output VAR8;
output [31:0] VAR1;
reg [ 7:0] VAR6 = 'd0;
reg VAR8 = 'd0;
reg [31:0] VAR1 = 'd0;
wire [ 3:0] VAR7;
wire VAR3;
assign VAR7 = ~VAR4;
assign VAR3 = ((VAR10 == ... | mit |
alexforencich/verilog-wishbone | rtl/wb_mux_2.v | 5,440 | module MODULE1 #
(
parameter VAR38 = 32, parameter VAR15 = 32, parameter VAR18 = (VAR38/8) )
(
input wire clk,
input wire rst,
input wire [VAR15-1:0] VAR26, input wire [VAR38-1:0] VAR25, output wire [VAR38-1:0] VAR4, input wire VAR2, input wire [VAR18-1:0] VAR3, input wire VAR17, output wire VAR35, output wire VAR5, ou... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_cnt_lead0_lvl3.v | 2,512 | module MODULE1 (
VAR3,
VAR10,
VAR5,
VAR6,
VAR9,
VAR11,
VAR12,
VAR2,
VAR7,
VAR8,
VAR4,
VAR1
);
input VAR3; input VAR10; input VAR5; input VAR6; input VAR9; input VAR11; input VAR12; input VAR2;
output VAR7; output VAR8; output VAR4; output VAR1;
wire VAR7;
wire VAR8;
wire VAR4;
wire VAR1;
assign VAR7= VAR9 && VAR3;
assi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi_2.v | 2,499 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR8 ,
VAR12 ,
VAR2 ,
VAR6 ,
VAR3,
VAR1,
VAR10 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR12 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR1;
input VAR10 ;
input VAR4 ;
VAR11 VAR9 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2.functional.v | 1,306 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR3;
bufif0 VAR2 (VAR4 , VAR1, VAR3 );
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_ifu.v | 9,235 | module MODULE1(
output[VAR56-1:0] VAR55,
output VAR32,
input VAR50,
input [VAR56-1:0] VAR2,
input [VAR37-1:0] VAR65,
output VAR53, input VAR62, output [VAR28-1:0] VAR51,
input VAR10, output VAR6, input VAR58, input [VAR17-1:0] VAR1,
input VAR52, output VAR18, input VAR39, input [VAR67-1:0] VAR20,
output [VAR34-1:0] VAR... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_tx.v | 9,992 | module MODULE1 #(
parameter VAR28 = 128, parameter VAR46 = "VAR33", parameter VAR20 = "VAR13", parameter VAR26 = "VAR13", parameter VAR27 = 1,
parameter VAR45 = (VAR28 == 128) ? 2 : 1, parameter VAR1 = VAR28 / 8 ) (
input [VAR28-1:0] VAR31, input VAR4, output VAR34, input [VAR1-1:0] VAR17, input VAR47, input [3:0] VAR2... | mit |
jmassucco17/full_mips | processor/SingleCycleDatapath/ControlUnit.v | 5,080 | module MODULE1(input[5:0] VAR14,
input[5:0] VAR1,
output reg VAR15,
output reg VAR2,
output reg[1:0] VAR8,
output reg[3:0] VAR16,
output reg VAR13,
output reg VAR12,
output reg VAR9,
output reg VAR10,
output reg VAR4,
output reg VAR3,
output reg VAR5);
always @(VAR14, VAR1) begin
VAR15 = 1'VAR11;
VAR2 = 1'VAR11;
VAR8 =... | mit |
freeelectron-ro/zynq | vivado/division.srcs/top.v | 1,615 | module MODULE1( input clk,
output reg [3:0] VAR6,
input [3:0] VAR7,
input [3:0] VAR3 );
reg [7:0] VAR2;
reg [3:0] VAR9;
wire [3:0] VAR8;
wire [3:0] VAR4;
VAR5 VAR1( .clk(clk),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4)
);
always @(posedge clk)
begin
if(VAR7[3]) VAR2[7:4] <= VAR3[3:0];
if(VAR7[2]) VAR2[3:0] <= V... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/d5e322d2745b1271/zynq_design_1_axi_bram_ctrl_0_1_stub.v | 4,089 | module MODULE1(VAR33, VAR7, VAR27,
VAR47, VAR4, VAR25, VAR46, VAR44, VAR41,
VAR1, VAR19, VAR34, VAR43, VAR48, VAR49,
VAR28, VAR8, VAR30, VAR37, VAR13, VAR10, VAR2,
VAR45, VAR42, VAR24, VAR31, VAR23, VAR21,
VAR22, VAR35, VAR26, VAR5, VAR38, VAR15, VAR18,
VAR11, VAR6, VAR40, VAR3, VAR50, VAR14, VAR9,
VAR17, VAR39, VAR29,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2.pp.symbol.v | 1,292 | module MODULE1 (
input VAR6 ,
input VAR1 ,
output VAR4 ,
input VAR5 ,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2b/sky130_fd_sc_hd__nand2b.symbol.v | 1,297 | module MODULE1 (
input VAR7,
input VAR5 ,
output VAR6
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
jncronin/jca | cpu/timer.v | 2,048 | module MODULE1(clk, rst, VAR3, addr, VAR4, VAR1, VAR2, interrupt);
input clk;
input rst;
inout [7:0] VAR3;
input [7:0] addr;
input VAR4;
input VAR1;
input VAR2;
output interrupt;
reg [7:0] VAR5[0:7];
assign VAR3 = (~VAR4 & ~VAR1) ? VAR5[addr] : 8'VAR6; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2.symbol.v | 1,322 | module MODULE1 (
input VAR8,
input VAR6,
output VAR4 ,
input VAR7
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai_0.v | 2,261 | module MODULE2 (
VAR8 ,
VAR1 ,
VAR9 ,
VAR10 ,
VAR3,
VAR2,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR5 ;
VAR7 VAR6 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.