code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module changestartscene (
clk,
rst,
h_cnt,
v_cnt,
state
);
input clk, rst;
input [9:0] h_cnt, v_cnt;
output [1:0] state;
reg [1:0] state, nextstate;
reg [29:0] cnt, nextcnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 30'd0;
state <= 2'b10;
end else begin
... | 6.753678 |
module change_calculator (
input [13:0] price,
input [9:0] count_coin_user_500,
input [9:0] count_coin_user_100,
input [9:0] count_coin_user_50,
input [9:0] count_coin_user_10,
input [13:0] count_coin_stock_500,
input [13:0] count_coin_stock_100,
input [13:0] count_coin_stock_50,
inp... | 6.651349 |
module clocked_wire (
rstn,
clk,
in,
out
);
parameter size = 1;
input rstn;
input clk;
input [size-1:0] in;
output [size-1:0] out;
reg [size-1:0] inC;
reg [size-1:0] inCC;
assign out = inCC;
always @(posedge clk) begin
if (!rstn) begin
inC <= 0;
inCC <= 0;
en... | 7.803973 |
module change_clock (
in_rstn,
out_rstn,
in_clk,
out_clk,
in_data,
in_strobe,
in_ready,
out_data,
out_strobe,
out_ready
);
parameter size = 32;
input in_rstn;
input in_clk;
input out_rstn;
input out_clk;
input [size-1:0] in_data;
output in_ready;
input in_strob... | 6.795894 |
module change_delayer (
input clk,
input [13:0] change_in,
input sale_done,
output reg [13:0] change_out
);
reg [27:0] count;
reg out;
initial begin
count = 0;
out = 0;
end
always @(posedge clk) begin
if (sale_done) begin
out = 1;
count = 1;
end else if (ou... | 6.99389 |
module change_det (
rst,
clk,
ce,
i,
cd
);
parameter WID = 32;
input rst; // reset
input clk; // clock
input ce; // clock enable
input [WID:1] i; // input signal
output cd; // change detected
reg [WID:1] hold;
always @(posedge clk)
if (rst) hold <= i;
else if (ce) hold... | 7.247471 |
module change_detector (
input wire clk,
input wire in,
output reg out
);
reg last;
wire out_next = (in != last);
initial begin
last = 0;
out = 0;
end
always @(posedge clk) begin
last <= in;
out <= out_next;
end
endmodule
| 7.459719 |
module change_mem_wr (
input [3:0] dmem_we,
input [31:0] in_data,
output reg [31:0] out_data
);
always @(*) begin
out_data = 32'b0;
case (dmem_we)
4'b1111: out_data = in_data;
4'b0011: out_data = {16'b0, in_data[15:0]};
4'b0110: out_data = {8'b0, in_data[15:0], 8'b0};
4'b1... | 7.874104 |
module change_oper_by_button (
input clk,
input [7:0] button,
input rst,
output reg [7:0] oper //
);
always @(posedge clk) begin
if (rst) oper = 8'b0;
else begin
if (button[0] == 1) oper = 8'b00110001;
if (button[1] == 1) oper = 8'b00110010;
if (button[2] == 1) oper = 8'b001... | 6.685795 |
module change_oper_by_color (
input rst,
input [7:0] r,
input [7:0] g,
input [7:0] b,
input clk,
output reg [7:0] oper
);
always @(posedge clk) begin
if (r + g + b < 3 * 241 / 8 / 2) oper = 8'b00110001;
else if (r + g + b < 3 * 241 * 2 / 8 / 2) oper = 8'b00110010;
else if (r + g + ... | 6.685795 |
module Change_ram (
input clk,
input rst,
input change_ram,
input ram_busy,
output ram_change, //ӳram_adjı仯ram_adj仯Ϊ1Ϊ0
output reg ram_adj
);
reg a1_ram_adj, a2_ram_adj; //ڼram_adj½
wire pos_change_ram;
reg change_ram_r1; //
reg change_ram_r2;
reg hold_change; //лָ
al... | 6.749151 |
module change_state (
index,
done,
decrement,
counter,
reset,
clock
);
output [6:0] index;
output reg done;
output reg decrement;
input [15:0] counter; // 2 digits of ascii.
input reset;
input clock;
parameter FIRST_CHAR = 7'h00,
FIRST_CHAR_NO_TENS = 7'h01,
... | 6.983274 |
module ChangingLED (
input clk_24M,
output wire led_r,
output wire led_g,
output wire led_b,
input wire btn_a_i,
input wire btn_b_i
);
// clk_100K
wire clk_100K;
SlowClock #(
.HALFPERIOD(24000000 / 100000) // 100K
) clock_100K (
.clk (clk_24M),
.clk_o(clk_100K)
)... | 6.880926 |
module changing_waves (
input clk,
input rst_n,
input [2:0] s0, //输入选择数据
input [2:0] s1,
input [1:0] s2,
output [10:0] dout,
d1 //输出波形
);
wire [7:0] address;
frequency_generator fg ( // 频率改变
.clk(clk),
.rst_n(rst_n),
.data_in(s1),
// .data_in(3'b001),
... | 6.794763 |
module ChannelModel_top (
clk,
reset,
addr,
VthAfterRTN
);
input clk;
input reset;
input [13:0] addr;
output [15:0] VthAfterRTN;
wire [15:0] output_Vth;
InputData inputRom (
.clka (clk),
.addra(addr),
.douta(output_Vth)
);
RTN_distortion RTN_uut (
.clk(clk),
... | 6.796548 |
module ChannelModel_top3 (
clk,
reset,
VoltageLevel,
InitialVth
);
input clk;
input reset;
input [1:0] VoltageLevel;
output [15:0] InitialVth;
VoltageProgram programProcess (
.VoltageLevel(VoltageLevel),
.clk(clk),
.reset(reset),
.InitialVoltage(InitialVth)
);
e... | 6.796548 |
module BaselineSubtractorAndThresholdCut (
RSTb,
CLK,
ENABLE_BASE_SUB,
DATA_IN,
FIFO_DATA_RD,
EVENT_PRESENT,
MEAN,
THRESHOLD_ADDRESS,
THRESHOLD_DATA,
CH_ID,
FIFO_DATA_OUT,
OUT_FIFO_RD,
FIFO_EMPTY,
FIFO_FULL,
FIFO_USED_WORDS,
END_PROCESSING,
MODULE_ID
)... | 6.629945 |
module FiveBitCounter (
RSTb,
CLK,
INC,
NON_ZERO,
DEC
);
input RSTb, CLK, INC, DEC;
output NON_ZERO;
reg [4:0] cnt;
reg NON_ZERO;
always @(posedge CLK or negedge RSTb) begin
if (RSTb == 0) begin
cnt <= 0;
NON_ZERO <= 0;
end else begin
NON_ZERO <= (cnt != 0) ? 1 ... | 7.300882 |
module SReg (
CK,
RSTb,
CLR,
SET,
OUT
);
input CK, RSTb, CLR, SET;
output OUT;
reg OUT;
always @(posedge CK or negedge RSTb) begin
if (RSTb == 0) OUT <= 0;
else begin
if (CLR == 1) OUT <= 0;
else if (SET == 1) OUT <= 1;
end
end
endmodule
| 6.938831 |
module channel_2_note_sequencer (
input wire i_clk,
input wire i_tick_stb,
input wire i_note_stb,
output wire [ 7:0] o_top,
output wire o_top_valid,
output wire [31:0] o_phase_delta,
output wire [ 8:0] o_envelope
);
`include "note_length_table.vh"
reg [4:0] r_duration_count = 0... | 6.770376 |
module channel_2_pulse (
input wire i_clk,
input wire i_tick_stb,
input wire i_note_stb,
output wire [8:0] o_output,
output wire o_frame_pulse
);
wire [ 7:0] w_top;
wire w_top_valid;
wire [31:0] w_phase_delta;
wire w_compare_valid = 1;
wire [ 8:0] ... | 6.632467 |
module channel_3_triangle (
input wire i_clk,
input wire i_tick_stb,
input wire i_note_stb,
output wire [8:0] o_output,
output wire o_frame_pulse
);
wire [ 7:0] w_top;
wire w_top_valid;
wire [31:0] w_phase_delta;
wire w_compare_valid = 1;
channel_3... | 6.984553 |
module channel_4_note_sequencer #(
parameter NOISE_TABLE_FILE = ""
) (
input wire i_clk,
input wire i_rst,
input wire i_tick_stb,
input wire i_note_stb,
output wire [7:0] o_top,
output wire o_top_valid,
output wire [31:0] o_phase_delta,
output wire [8:0]... | 7.092242 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empt... | 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
... | 7.813216 |
module Channel_Data_Reorder_Buffer_tb;
reg inclk;
reg outclk;
reg rst_n;
reg FIFO_ready_mask;
reg [ 15:0] FIFO_rd_data;
wire FIFO_rd_request;
wire BRAM_ready_mask;
wire [255:0] DRAM_wr_data;
reg BRAM_rd_request;
/* Loop Variables */
re... | 6.853218 |
module channel_demux #(
parameter NUM_CHAN = 2
) ( //usb Side
input [31:0] usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel
);
/* Parse header and forward to ... | 6.738518 |
module channel_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q
);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [31:0] q;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire empty = sub_wir... | 6.713623 |
module axis_mux2 #(
parameter DATA_WIDTH = 8
) (
input wire aresetn,
input wire [DATA_WIDTH-1:0] s0_axis_tdata,
input wire s0_axis_tvalid,
output wire s0_axis_tready,
input wire s0_axis_tlast,
input wire [DATA_WIDTH-1:0] s1_axis_tdata,
input wire s1_axis_tvalid,
output wire s1_axis_t... | 7.693029 |
module axis_demux2 #(
parameter DATA_WIDTH = 8
) (
input wire aresetn,
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
output wire [DATA_WIDTH-1:0] m0_axis_tdata,
output wire m0_axis_tvalid,
input wire m0_axis_tr... | 7.583739 |
module channel_merge (
input logic [31:0] y_jpeg,
cb_jpeg,
cr_jpeg,
input logic y_valid,
cb_valid,
cr_valid,
input logic clk,
img_rst,
output logic [31:0] jpeg_bitstream,
output logic [1:0] data_valid
);
logic [1:0] mux_sel, mux_sel_1;
logic y_read_req, cb_read_req, cr_read... | 6.501455 |
module channel_ram ( // System
input txclk,
input reset,
// USB side
input [31:0] datain,
input WR,
input WR_done,
output have_space,
// Reader side
output [31:0] dataout,
input RD,
input RD_done,
output packet_waiting
);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which... | 6.769144 |
module channel_synchronizer (
clk,
reset,
input_signal,
output_signal
);
input clk, reset, input_signal;
output output_signal;
reg output_signal, ff1_output;
always @(posedge clk or posedge reset)
if (reset) output_signal = 1'b1;
else output_signal = ff1_output;
always @(posedge clk... | 6.533529 |
module used to display the characters.
When en = 1, pacman_orientation is specified, reset was turned from 1 to 0,
clock_50 is set to the 50mhz clock; vga_color, vga_plot, vga_x, vga_y goes to VGA adapter;
char_x, char_y, and character_type goes to the CharacterRegisters,
It will iterate through all the character... | 6.94206 |
module characterMovement (
clock,
resetn,
enable,
jump,
left_blocked,
right_blocked,
up_blocked,
down_blocked,
x_position,
y_position,
jumping_Q,
jumping_D,
jump_factor
);
//------------------------------------------
// Inputs
//---------------------------------... | 9.544089 |
module characterROM (
address,
clock,
q
);
input [3:0] address;
input clock;
output [24:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [24:0] sub_wire0;
wire [24:0] q = sub_wire0[24:0];
alts... | 6.526692 |
module character_counter(
input wire count,
input wire carry_in,
input wire[7:0] prg_numchars,
input wire[8*127-1:0] prg_charlist,
input wire enable,
input wire program,
output reg carry_out,
output reg[7:0] char
);
reg[7:0] counter=0;
reg[7:0] numchars =0;
reg[8*127:0] charlist;
always @(posedge count)
... | 6.715525 |
module should just be dedicated to hex decoding... need to move everything else over to a shared bus architecture....
module character_decoder(
input [7:0] in_char,
input in_char_valid,
output is_hex_char,
output [3:0] hex_decode,
output reg is_cmd,
output reg [3:0] cmd,
output is_eol
);
assign is_hex_char = ... | 7.486222 |
module character_encoder (
input [7:0] char_in,
input which_hex_char,
output [7:0] out
);
//This module just hex-encodes an input character
wire [3:0] bin = (which_hex_char) ? char_in[3:0] : char_in[7:4];
assign out = (bin >= 4'hA) ? (8'h37 + bin) : (8'h30 + bin);
endmodule
| 8.340662 |
module character_match (
input pixelclk,
input reset_n,
input i_vs,
input [ 1:0] frame_cnt,
input [39:0] char1,
input [39:0] char2,
input [39:0] char3,
input [39:0] char4,
input [39:0] char5,
input [39:0] char6,
input [39:0] char7,
input [... | 6.689519 |
module pixeldata (
input clk,
input newline,
input advance,
input [7:0] line,
output [11:0] pixel,
input [7:0] vram_data,
output [10:0] vram_addr
);
reg [7:0] pattern_rom[0:1023];
`ifdef HEX_PATHS
initial $readmemh("hdl/vga/prom.txt", pattern_rom);
`else
initial $readmemh("prom.txt",... | 7.395694 |
module test_ram1_top (
input wire clk,
input wire reset,
output wire hsync,
output wire vsync,
output wire [2:0] rgb
);
wire display_on;
wire [15:0] hpos;
wire [15:0] vpos;
wire [9:0] ram_addr;
wire [7:0] ram_read;
reg [7:0] ram_write;
reg ram_writeenable = 0;
// RAM to hold 32x32... | 7.648978 |
module chargen_tb;
`test_init(clk);
reg clk, n_rst, ready_n, valid_n;
reg [7:0] port;
chargen #(.LASTCHAR(`STR(c))) chargen0 (.*);
initial begin : logging
`define HEADER(s) \
if (s != "") $display(s); \
$display("# time x nRST nRDY nVLD OUT")
$monitor("%6t %1b %4b %4b %4b %3c", $time, `... | 6.613678 |
module chargepump (
input clk,
input resetn,
input [7:0] period,
output chargepump_pin
);
reg [7:0] cp_counter;
reg chargepump;
assign chargepump_pin = chargepump;
always @(posedge clk) begin
if (!resetn) begin
cp_counter <= 0;
chargepump <= 0;
end else begin
cp_... | 7.244683 |
module to control (PINCOUNT * (PINCOUNT-1)) LEDs
* via PINCOUNT outputs that may be tristated or pulled to VCC or GND.
*
* in: LED to enable (index number from 0 .. PINCOUNT*(PINCOUNT-1)-1)
* enable: global enable switch for tristateable outputs
* out_en: flags indicating that an output shall be dr... | 7.497741 |
module charlieplex_display (
input wire pixelclock,
input wire enable,
input wire [PIXELCOUNT-1:0] pixelstate,
output wire [PINCOUNT-1:0] out_en,
output wire [PINCOUNT-1:0] out_value
);
parameter PIXELCOUNT = 12;
localparam PINCOUNT = $rtoi($ceil((1.0 + $sqrt(1.0 + 4.0 * PIXELCOUNT)) / 2));
l... | 6.921276 |
module char_box (
input [11:0] gray,
input [15:0] iX_Cont,
input [15:0] iY_Cont,
output [11:0] g
);
wire box;
assign box = (iX_Cont == 16'd300) & (iY_Cont <= 16'd328) & (iY_Cont >= 16'd300) |
(iX_Cont == 16'd328) & (iY_Cont <= 16'd328) & (iY_Cont >= 16'd300) |
(iY_Cont == 16'd300) & (iX... | 7.32689 |
module char_buffer #(
parameter BUF_SIZE = 1920,
parameter ADDR_BITS = 11
) (
input wire clk,
input wire [7:0] din,
input wire [ADDR_BITS-1:0] waddr,
input wire wen,
input wire [ADDR_BITS-1:0] raddr,
output reg [7:0] dout
);
reg [7:0] mem[BUF_SIZE-1:0];
initial begin
//$readme... | 7.071207 |
module CHAR_GEN (
// control
reset,
// write side
char_write_addr,
char_write_data,
char_write_enable,
char_write_clock,
// read side
char_address,
subchar_line,
subchar_pixel,
pixel_clock,
pixel_on
);
input pixel_clock;
input reset;
input [2:0] subchar_line; ... | 6.789065 |
module char_generator (
input _OE,
input [7:0] CHAR,
input [3:0] ROW,
output [7:0] DATA
);
reg [7:0] char_rom[4095:0]; // 256 characters with 16 rows
initial begin
$readmemh("CP437.F16.hex", char_rom);
end
assign DATA = _OE ? 8'b11111111 : char_rom[(CHAR*16)+ROW];
endmodule
| 6.516485 |
module char_lcd_cont (
lcd_cnt,
char00,
char01,
char02,
char03,
char04,
char05,
char06,
char07,
char08,
char09,
char0A,
char0B,
char0C,
char0D,
char0E,
char0F,
char10,
char11,
char12,
char13,
char14,
char15,
char16,
char... | 6.984561 |
module char_m (
out,
in
);
output reg [6:0] out;
input [2:0] in;
always @(*) begin
case (in)
0: out = 7'b0000000;
1: out = 7'b1011111;
2: out = 7'b1100111;
3: out = 7'b1011111;
4: out = 7'b0000000;
default: out = 7'b1111111;
endcase
end
endmodule
| 6.619355 |
module char_mem (
input [4:0] addr,
output [7:0] bus
);
parameter LINES = 2;
parameter CHARS_PER_LINE = 16;
parameter BITS_PER_CHAR = 8;
parameter STR_SIZE = LINES * CHARS_PER_LINE * BITS_PER_CHAR;
parameter [0:STR_SIZE-1] str = " Hello, world! Spartan-3E LCD ";
assign bus = str[{addr[4:0], 3'... | 7.412747 |
module char_rom_tb();
// Inputs
reg clk = 0;
reg rst = 1;
wire [11 : 0] addr;
// Outputs
wire [15 : 0] DO;
// Generate clk
always #5 clk <= ~clk;
reg [3 : 0] line_addr = 15;
always @( posedge clk )
begin
if (line_addr == 0)
line_addr <= 15;
... | 7.780431 |
module char_row_counter (
glyph_row,
char_row,
cur_char,
v_en,
valid,
vert_c,
CLK,
RST
);
output reg [11:0] cur_char; //Current character from 0 to 4800
output reg [3:0] glyph_row; //From row 0 to 15 of each glyph
output reg [2:0] char_row; //From 0 to 7 across each char row
... | 6.542684 |
module char_to_int (
input [`CHAR_BITES] char,
output reg [`ATTRIBUTE_VAL_BITES] int_out
);
always @(*) begin
if (char > 47 && char < 58) begin
int_out[`ATTRIBUTE_VAL_BITES] = char - 8'd48;
end else begin
int_out = 0;
end
end
endmodule
| 6.598437 |
module char_video_out (
input PIXCLK,
input [7:0] DATA,
input [7:0] ATTR,
input [2:0] PIXEL,
input BLANK,
output reg [2:0] RED,
output reg [2:0] GREEN,
output reg [1:0] BLUE
);
reg [7:0] clut[15:0];
initial begin
clut[0] = 8'b000_000_00;
clut[1] = 8'b000_000_10;
clut[2... | 6.673301 |
module char_wrapper (
input [9:0] x_pos,
input [9:0] y_pos,
input [6:0] char_sel,
input [7:0] back_red,
input [7:0] back_green,
input [7:0] back_blue,
input [7:0] char_red,
input [7:0] char_green,
input [7:0] char_blue,
input pix_clk,
input rst,
output HS_out,
output ... | 8.444912 |
module char_wrapper_tb ();
reg clk = 0;
reg rst = 0;
wire [7:0] char_data;
char_wrapper uut (
.clk(clk),
.rst(rst),
.char_data_out(char_data)
);
always #5 clk = ~clk;
initial begin
#10000;
$finish;
end
endmodule
| 7.22378 |
module chattering (
input wire rst_n,
input wire clk,
input wire bin_n,
output reg bout
);
reg [17:0] r_cnt;
wire en40hz = (r_cnt == 250000 - 1);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) r_cnt <= 18'd0;
else if (en40hz) r_cnt <= 18'd0;
else r_cnt <= r_cnt + 18'd1... | 7.459093 |
module chdr_16sc_to_12sc_tb ();
reg clk = 0;
reg reset = 1;
//generate clock
always #10 clk = ~clk;
initial $dumpfile("chdr_16sc_to_12sc_tb.vcd");
initial $dumpvars(0, chdr_16sc_to_12sc_tb);
//tells when to finish
initial begin
#50 reset = 0;
#50000;
$finish;
end
//setting registers ... | 6.768253 |
module chdr_16sc_to_32f #(
parameter BASE = 0
) (
input clk,
input reset,
input set_stb,
input [ 7:0] set_addr,
input [31:0] set_data,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output reg [63:0] o... | 6.768253 |
module chdr_16sc_to_32f_tb ();
reg clk = 0;
reg reset = 1;
//generate clock
always #10 clk = ~clk;
initial $dumpfile("chdr_16sc_to_32f_tb.vcd");
initial $dumpvars(0, chdr_16sc_to_32f_tb);
//tells when to finish
initial begin
#50 reset = 0;
#50000;
$finish;
end
//setting registers an... | 6.768253 |
module chdr_16sc_to_8sc_tb ();
reg clk = 0;
reg reset = 1;
//generate clock
always #10 clk = ~clk;
initial $dumpfile("chdr_16sc_to_8sc_tb.vcd");
initial $dumpvars(0, chdr_16sc_to_8sc_tb);
//tells when to finish
initial begin
#50 reset = 0;
#50000;
$finish;
end
//setting registers and... | 6.768253 |
module chdr_32f_to_16sc #(
parameter BASE = 0
) (
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input clk,
input reset,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output reg [63:0] o_tdata,
... | 6.848788 |
module chdr_32f_to_16sc_tb ();
reg clk = 0;
reg reset = 1;
//generate clock
always #10 clk = ~clk;
initial $dumpfile("chdr_32f_to_16sc_tb.vcd");
initial $dumpvars(0, chdr_32f_to_16sc_tb);
//tells when to finish
initial begin
#50 reset = 0;
#50000;
$finish;
end
//setting registers a... | 6.848788 |
module chdr_32f_to_16s_tb ();
reg clk = 0;
reg reset = 1;
//generate clock
always #10 clk = ~clk;
initial $dumpfile("chdr_32f_to_16s_tb.vcd");
initial $dumpvars(0, chdr_32f_to_16s_tb);
//tells when to finish
initial begin
#50 reset = 0;
#50000;
$finish;
end
//setting registers and ... | 6.848788 |
module chdr_8sc_to_16sc #(
parameter BASE = 0
) (
input clk,
input reset,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output reg [63:0] o_tdata,
output o_tlast,
output ... | 6.770088 |
module chdr_8sc_to_16sc_tb ();
reg clk = 0;
reg reset = 1;
//generate clock
always #10 clk = ~clk;
initial $dumpfile("chdr_8sc_to_16sc_tb.vcd");
initial $dumpvars(0, chdr_8sc_to_16sc_tb);
//tells when to finish
initial begin
#50 reset = 0;
#50000;
$finish;
end
//setting registers and... | 6.770088 |
module chdr_8s_to_16s #(
parameter BASE = 0
) (
input clk,
input rst,
// axi4 stream slave interface
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
// axi4 stream master interface
output reg [63:0] o_tdata,
output o_... | 7.83297 |
module. error is asserted if a packet is larger than the quantum
// error can be reset by asserting reset or clear.
`default_nettype none
module chdr_chunker # (
parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF,
HOLD_ERROR = 1'b1 // If high, hold error until reset, else pulse
) (
input wire clk,... | 6.554729 |
module chdr_dechunker #(
parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF
) (
input clk,
input reset,
input clear,
input [15:0] frame_size,
input [63:0] i_tdata,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
o... | 7.298457 |
module
// samples at the output
// - FIXME Currently only 32-bit input widths are supported.
//
/////////////////////////////////////////////////////////////////////
module chdr_deframer_2clk #(
parameter WIDTH = 32
) (
input samp_clk, input samp_rst, input pkt_clk, input pkt_rst,
input [63:0] i_tdata, input... | 6.888253 |
module chdr_fifo_large #(
parameter SIZE = 12,
parameter DEVICE = "7SERIES"
) (
input clk,
input reset,
input clear,
input [63:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [63:0] o_tdata,
output o_tlast,
output ... | 6.700515 |
module chdr_framer_tb ();
reg clk, reset;
always #100 clk = ~clk;
initial $dumpfile("chdr_framer_tb.vcd");
initial $dumpvars(0, chdr_framer_tb);
reg [ 31:0] i_tdata;
reg [127:0] i_tuser;
reg i_tlast, i_tvalid;
wire i_tready;
wire [63:0] o_tdata;
wire o_tlast, o_tvalid;
reg o_tready = 0;
ch... | 6.678093 |
module chdr_ingress_fifo #(
parameter WIDTH = 64,
parameter SIZE = 12,
parameter DEVICE = "7SERIES"
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:... | 7.057656 |
module pads extra data on the AXI-Stream bus
// to the requested packet size. This module is for
// creating len-sized packets, for DMA engines that
// do not support partial transfers.
//
// Parameters:
// - CHDR_W: Width of the CHDR tdata bus in bits
//
// Signals:
// - s_axis_* : Input AXI-Stream CHDR bus
// -... | 6.755923 |
module chdr_to_chdr_data #(
parameter CHDR_W = 256
) (
// Clock, reset and settings
input wire axis_chdr_clk,
input wire axis_chdr_rst,
// CHDR in (AXI-Stream)
input wire [CHDR_W-1:0] s_axis_chdr_tdata,
input wire s_axis_chdr_tlast,
input wire ... | 7.309543 |
module trims any extra data on the AXI-Stream
// bus to the CHDR payload size. This ensures that the
// line with tlast is the actual last line of the packet
//
// Parameters:
// - CHDR_W: Width of the CHDR tdata bus in bits
// - USER_W: Width of the tuser bus in bits
//
// Signals:
// - s_axis_* : Input AXI-Strea... | 8.000016 |
module cheater_char_rom (
input wire [15:0] char_xy,
output reg [ 6:0] char_code // pixels of the character line
);
always @* begin
case (char_xy)
16'h0000: char_code = 7'h49;
16'h0100: char_code = 7'h20;
16'h0200: char_code = 7'h74;
16'h0300: char_code = 7'h68;
16'h0400:... | 7.004231 |
module Check4_4x (
input clock1,
input clock2,
input clock3,
input reset,
input [7:0] din,
input valid,
input [4:0] selector,
output [9:0] rowcount,
output [9:0] colcount,
output [7:0] dout,
output validout
);
wire [7:0] down_to_five_data;
wire down_to_five_blank;
... | 6.51611 |
module CheckBranch (
operator,
flags,
is_checked
);
input [7:0] flags;
input [3:0] operator;
output reg is_checked;
wire carry, overflow, zero, negative;
assign carry = flags[3];
assign overflow = flags[2];
assign zero = flags[1];
assign negative = flags[0];
always @*
case (operator)... | 7.732836 |
module can give a background 0 when recieved rst signal
module chk_1(
output [3:0] dat_out,
output [7:0] addr_out,
output w_en_out,rst_done,
input clk,en_in, rev_in
);
//Counter variable
integer i=0;
//Registers to manipulate outputs
reg [7:0] w_addr;
reg [3:0] w_data = 4'b1010;
reg... | 6.964794 |
module CheckCode (
input [7:0] datain,
output [8:0] dataout
);
assign dataout[8:1] = datain[7:0];
assign dataout[0] = datain[7]^datain[6]^datain[5]^datain[4]^datain[3]^datain[2]^datain[1]^datain[0];
endmodule
| 6.685067 |
module absoluteValue (
num,
absNum
);
parameter w = 8; //when setting width only specify the magnitude of the number, the sign bit will be automatically added in
//this implementation
input [w:0] num;
output reg [w:0] absNum;
always @(*) begin
if (num[w] == 1'b1) begin
absNum = -num;
e... | 7.074339 |
module checker #(parameter P_DATA_WIDTH = 32)
(
input clk,
input rst,
input [P_DATA_WIDTH-1:0] data_run,
input [P_DATA_WIDTH-1:0] data_done,
input run,
output reg busy=0,
input done,
output reg ran=0,
output reg ok=1
);
reg [P_DATA_WIDTH-1... | 6.864157 |
module checker2to2(
// Outputs from the strctural description
input out_s0,
input out_s1,
// Outputs from the behavioral description
input out_b0,
input out_b1,
input clk,
);
// If we compare out0 from each module and it doesn't match at the same time
// the test result is that the both... | 6.632486 |
module checker4to4
// Clok
input clk,
// Outputs from the structural description
input out_s0,
input out_s1,
input out_s2,
input out_s3,
// Outputs from the behavioral description
input out_b0,
input out_b1,
input out_b2,
input out_b3,
);
// If we compare out0 fr... | 7.228188 |
module watch_dog (
clk,
cyc_i,
ack_i,
adr_i
);
// parameters
parameter count = 1000;
// inputs
input clk;
input cyc_i;
input ack_i;
input [31:0] adr_i;
// variables
integer cnt;
// module body
always @(posedge clk)
if (!cyc_i || ack_i) cnt <= #1 count;
else begin
... | 6.801527 |
module Checker_BIST (
input Clock,
output GoNoGo,
Done
);
wire [7:0] Adr_Counter_SRAM;
wire WE_Counter_SRAM;
wire [3:0] Data_in_Counter_SRAM;
reg [10:0] Done_Counter = 0;
wire [3:0] Data_out_SRAM_Comp;
wire Comparator_output;
C_Counter Checker_Counter (
.clk(Clock),
.Counter_Addre... | 7.491753 |
module checkLineState (
clk,
initComplete,
rst,
usbRstDet,
wb_ack,
wb_addr,
wb_data_i,
wb_stb,
wb_we,
wbBusGnt,
wbBusReq
);
input clk;
input initComplete;
input rst;
input wb_ack;
input [7:0] wb_data_i;
input wbBusGnt;
output usbRstDet;
output [7:0] wb_addr;
... | 6.907309 |
module checkmem (
clk,
dout,
wen,
addr,
d
);
input clk, wen, d;
input [17:0] addr;
output [7:0] dout;
wire cl;
reg [7:0] data1 = 8'd213;
reg [7:0] data2 = 8'd143;
reg [7:0] data = 8'd65;
dram_512 dd (
.address(addr),
.clock(cl),
.data(data),
.wren(~wen),
... | 6.686676 |
module checkOddEven (
input [7:0] in,
output odd,
output even
);
assign odd = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4] ^ in[5] ^ in[6] ^ in[7];
assign even = ~odd;
endmodule
| 7.303407 |
module Parity_pitch_test;
reg start;
reg clk;
reg reset;
reg [15:0] pitch_index;
reg [15:0] parity;
//Outputs
wire done;
wire [31:0] readIn;
wire [15:0] sum;
integer i, j, k;
//I/O regs
reg [15:0] pitch_indexc[0:40000];
reg [15:0] parityc[0:40000];
reg [15:0] sumc[0:40000];
//file re... | 6.709028 |
module checksum_core #(
parameter p_WORD_LEN = 8,
parameter p_TWOS_COMPL = 0 // 1 for two's complement, 0 for one's complement
) (
input i_clk,
input i_reset,
input [p_WORD_LEN-1:0] i_data,
input i_en,
input i_calc,
output reg [p_WORD_LEN-1:0] o_checksum,
output o_rdy
);
//... | 7.281371 |
module checksum_tb;
reg clk, rst, checksum_add, checksum_clear;
reg [15:0] data_in;
wire checksum_check;
wire [15:0] checksum_out;
checksum dut (
.clk(clk),
.rst(rst),
.checksum_add(checksum_add),
.checksum_clear(checksum_clear),
.data_in(data_in),
.checksum_check(checksu... | 6.818998 |
module check_100_1000 (
rgmii_rx_clk, //rgmii_rx_clk 25MHzʱΪ100M125MHzʱΪ1000M
sys_clk, //125Mıʱ
sys_rst_n,
SPEED_IS_100_1000 //1100M 0:1000M
);
input rgmii_rx_clk;
input sys_clk;
input sys_rst_n;
output SPEED_IS_100_1000;
reg SPEED_IS_100_1000;
reg [6:0] timer;
reg rst_fifo;
reg wr... | 7.154055 |
module check_alarm (
input [3:0] minutes_ones,
load_minutes_ones,
input [2:0] minutes_tens,
load_minutes_tens,
input load_SW,
alarm_off_SW,
output reg play_sound
);
always @(*) begin
play_sound = 0;
if (~load_SW && ~alarm_off_SW)
if (minutes_ones == load_minutes_ones && minu... | 7.186765 |
module internal_module (
input clk,
input res,
output cnt_roll
);
reg [2:0] cnt;
always @(posedge clk, posedge res) begin
if (res) cnt <= 3'b0;
else cnt <= cnt + 1;
end
assign cnt_roll = (cnt == 3'b111);
endmodule
| 6.602994 |
module check_clock_gating (
input clk,
input res,
input [31:0] d,
output reg [31:0] val,
input en
);
always @(posedge clk, posedge res) begin
if (res) val <= 31'b0;
else if (en) val <= d;
end
endmodule
| 6.57428 |
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