code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module GG_7 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 7.126887 |
module GG_6 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 7.000066 |
module GP_2 (
P_CURRENT,
P_PREV,
P
);
input P_CURRENT, P_PREV;
output P;
AND2_X1 U1 (
.A1(P_PREV),
.A2(P_CURRENT),
.ZN(P)
);
endmodule
| 7.383575 |
module GG_5 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 6.655138 |
module GP_1 (
P_CURRENT,
P_PREV,
P
);
input P_CURRENT, P_PREV;
output P;
AND2_X1 U1 (
.A1(P_PREV),
.A2(P_CURRENT),
.ZN(P)
);
endmodule
| 7.197257 |
module GG_4 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 6.780106 |
module GG_3 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 7.142291 |
module GG_2 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 7.185372 |
module GG_1 (
G_CURRENT,
P_CURRENT,
G_PREV,
G
);
input G_CURRENT, P_CURRENT, G_PREV;
output G;
wire n3;
INV_X1 U1 (
.A (n3),
.ZN(G)
);
AOI21_X1 U2 (
.B1(P_CURRENT),
.B2(G_PREV),
.A (G_CURRENT),
.ZN(n3)
);
endmodule
| 6.69631 |
module RCA_NBIT4_0 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.740963 |
module RCA_NBIT4_14 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0]... | 7.934078 |
module RCA_NBIT4_13 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0]... | 7.780681 |
module CSB_NBIT4_0 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n7, n8, n9, n10, n11, n6;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_14 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0)
);... | 6.659237 |
module RCA_NBIT4_12 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0]... | 7.992663 |
module RCA_NBIT4_11 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0]... | 7.846434 |
module CSB_NBIT4_6 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n6, n12, n13, n14, n15, n16;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_12 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0)
... | 6.820512 |
module RCA_NBIT4_10 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0]... | 7.738482 |
module RCA_NBIT4_9 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.787699 |
module CSB_NBIT4_5 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n6, n12, n13, n14, n15, n16;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_10 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0)
... | 6.939997 |
module RCA_NBIT4_8 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.986719 |
module RCA_NBIT4_7 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.936123 |
module CSB_NBIT4_4 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n6, n12, n13, n14, n15, n16;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_8 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0)
... | 6.949805 |
module RCA_NBIT4_6 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.931223 |
module RCA_NBIT4_5 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 8.124965 |
module CSB_NBIT4_3 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n2, n3, n12, n13, n14, n15, n16;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_6 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0... | 6.679258 |
module RCA_NBIT4_4 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.974063 |
module RCA_NBIT4_3 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.787572 |
module CSB_NBIT4_2 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n2, n3, n12, n13, n14, n15, n16;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_4 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0... | 6.843705 |
module RCA_NBIT4_2 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.968296 |
module RCA_NBIT4_1 (
A,
B,
Ci,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Ci;
output Co;
wire \add_1_root_add_74_2/carry[3] , \add_1_root_add_74_2/carry[2] ,
\add_1_root_add_74_2/carry[1] ;
FA_X1 \add_1_root_add_74_2/U1_0 (
.A (A[0]),
.B (B[0])... | 7.874833 |
module CSB_NBIT4_1 (
A,
B,
Cin,
S,
Co
);
input [3:0] A;
input [3:0] B;
output [3:0] S;
input Cin;
output Co;
wire Co0, Co1, n1, n12, n13, n14, n15, n16;
wire [3:0] S0;
wire [3:0] S1;
RCA_NBIT4_2 U_RCA0 (
.A (A),
.B (B),
.Ci(1'b0),
.S (S0),
.Co(Co0)
... | 6.730586 |
module P4_ADDER_NBIT32 (
A,
B,
Cin,
S,
Cout
);
input [31:0] A;
input [31:0] B;
output [31:0] S;
input Cin;
output Cout;
wire n1;
wire [6:0] carry_gen_Co;
CARRY_GENERATOR_NBIT32_NBIT_PER_BLOCK4 U_CARRY_GENERATOR (
.A (A),
.B (B),
.CIN(Cin),
.CO ({Cout, carry... | 7.456858 |
module cfg_crc #(
parameter datw = 6,
parameter [datw - 1:0] coff = 6'b10_0101
) (
input clk,
rst,
input rst_syn,
input crc_en,
input dat_i,
output reg [datw - 2:0] dat_o
);
wire lsb = dat_i ^ dat_o[datw - 2];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) ... | 6.957708 |
module cfg_dprio_csr_reg_bit (
input wire clk, // clock
input wire csr_in, // CSR serial input
input wire csr_en, // CSR enable
output wire csr_out, // Gated CSR serial output
output wire csr_chain // Output to connect to CSR chain
);
//reg csr_reg;
wire csr_reg;
... | 8.286479 |
module cfg_dprio_csr_reg_nbits #(
parameter DATA_WIDTH = 16 // Data width
) (
input wire clk, // clock
input wire csr_in, // CSR serial in
input wire csr_en, // CSR enable
output wire csr_out, // CSR serial output
... | 8.286479 |
module cfg_dprio_csr_reg_nregs #(
parameter BINDEX = 0, // Base index
parameter SEGMENT = 0, // CSR segment
parameter DATA_WIDTH = 16, // Data width
parameter NUM_EXTRA_CSR_REG = 1, // Number of extra 16-bit register for CSR
parameter CSR_OUT_NEG_FF_EN = 0, // En... | 8.286479 |
module cfg_dprio_csr_test_mux (
input wire rst_n, // Active low hard reset
input wire clk, // Clock
input wire cbdin, // CSR configuration mode data input
input wire tcsrin, // CSR test/scan mode data input
input wire csrdin, // Previous CSR bit data output
input wire csr_seg... | 8.286479 |
module cfg_dprio_ctrl_reg_bit (
input wire clk, // clock
input wire dprio_in, // DPRIO input
input wire csr_in, // serial input
input wire dprio_sel, // 1'b1=choose csr_in
// 1'b0=choose dprio_in
input wire bit_en, // W... | 7.886581 |
module cfg_dprio_ctrl_reg_nbits #(
parameter DATA_WIDTH = 16, // Data width
parameter ADDR_WIDTH = 16 // Address width
) (
input wire clk, // clock
input wire write, // write enable input
input wire [ADDR_WIDTH-1:0] reg_addr, // address input
input wire [ADDR_WIDTH-1:0] target_addr, // ha... | 7.886581 |
module cfg_dprio_dis_ctrl_cvp #(
parameter CLK_FREQ_MHZ = 250, // Clock freq in MHz
parameter TOGGLE_TYPE = 1,
parameter VID = 1
) (
input wire rst_n, // reset
input wire clk, // clock
input wire dprio_dis_in, // dprio_dis in
input wire csr_cvp_en, // CSR enable
... | 6.925062 |
module cfg_dprio_readdata_mux #(
parameter DATA_WIDTH = 16, // Data width
parameter NUM_INPUT = 4 // Number of n-bit input
) (
input wire clk,
input wire rst_n,
input wire read,
input wire [ NUM_INPUT... | 8.493534 |
module cfg_dprio_readdata_mux_mod #(
parameter DATA_WIDTH = 16 // Data width
) (
input wire sel, // 1-hot selection input
input wire [DATA_WIDTH-1:0] data_in1, // data input
input wire [DATA_WIDTH-1:0] data_in0, // data input
output wire [DATA_WIDTH-1:0] data_out // data ... | 8.493534 |
module cfg_dprio_readdata_sel #(
parameter ADDR_WIDTH = 10 // Address width
) (
input wire [ADDR_WIDTH-1:0] reg_addr, // address input
input wire [ADDR_WIDTH-1:0] target_addr, // target address input
output wire readdata_sel // read select output
);
assign readdata_sel = (reg_addr == target_add... | 8.493534 |
module cfg_dprio_shadow_status_nregs #(
parameter DATA_WIDTH = 16, // Data width
parameter NUM_STATUS_REGS = 5, // Number of n-bit status registers
parameter CLK_FREQ_MHZ = 250, // Clock freq in MHz
parameter TOGGLE_TYPE = 1,
parameter VID = 1
) (
input wire [ ... | 8.124039 |
module cfg_dprio_shadow_status_regs #(
parameter DATA_WIDTH = 16, // Data width
parameter CLK_FREQ_MHZ = 250, // Clock freq in MHz
parameter TOGGLE_TYPE = 1,
parameter VID = 1
) (
input wire rst_n, // reset
input wire clk, // clo... | 8.124039 |
module cfg_dprio_status_reg_nbits #(
parameter DATA_WIDTH = 16, // Data width
parameter ADDR_WIDTH = 16 // Address width
) (
input wire rst_n, // reset
input wire clk, // clock
input wire read, // read enable input
inp... | 8.471151 |
module cfg_dprio_status_reg_nregs #(
parameter DATA_WIDTH = 16, // Data width
parameter ADDR_WIDTH = 16, // Address width
parameter NUM_STATUS_REGS = 10, // Number of n-bit status registers
parameter BYPASS_STAT_SYNC= 0, // Parameter to bypass the Synchronization SM in case of individual status bit... | 8.471151 |
module cfg_mem_sync #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
input soc_clk,
input soc_rstn,
input sys_clk,
output sys_rstn,
input [ADDR_WIDTH - 1 : 0] soc_addr,
input [DATA_WIDTH - 1 : 0] soc_wdata,
output [DATA_WIDTH - 1 : 0] soc_rdata,
output ... | 8.040885 |
module cfg_ram (
input clk200, // Clock signal
input [8:0] addr, // Address to read/write
input we, // Write-enable
input [7:0] wdata, // Data to write
output reg [7:0] rdata // Data read from RAM
);
reg [7:0] mem[511:0];
// Blocking Statement and ... | 6.996252 |
module cfg_ram_bf #(
parameter GROUP_ID = 0,
ADDR_WIDTH = 4,
DATA_DEPTH = 0,
DATA_WIDTH = 32,
RAM_INDEX = 0,
INIT_FILE = ""
) (
input clk,
// input rst ,
input [ADDR_WIDTH-1:0] addr_rd,
output reg [DATA_WIDTH-1:0] dout,
input [ 6:0] addr_wr,
... | 7.261798 |
module cfg_ram_ibf #(
parameter ADDR_WIDTH = 4,
DATA_DEPTH = 0,
DATA_WIDTH = 32,
RAM_INDEX = 0,
INIT_FILE = ""
) (
input clk,
// input rst ,
input [ADDR_WIDTH-1:0] addr_rd,
output [DATA_WIDTH-1:0] dout,
input [ 1:0] addr_wr,
input [ 7:0] sram_sel,
... | 6.861715 |
module cfg_ram_ibf_mux #(
parameter ADDR_WIDTH = 4,
DATA_DEPTH = 0,
DATA_WIDTH = 32,
RAM_INDEX = 0,
INIT_FILE = ""
) (
input clk,
// input rst ,
input [ADDR_WIDTH-1:0] addr_rd,
output [DATA_WIDTH-1:0] dout,
input [ 1:0] addr_wr,
input [ 3:0] sram_sel... | 6.931714 |
module cfg_ram_unit #(
parameter ADDR_WIDTH = 4,
DATA_DEPTH = 0,
DATA_WIDTH = 32,
RAM_INDEX = 0,
RAM_INDEX_IN_GROUP = 0,
INIT_FILE = ""
) (
input clk,
// input rst ,
input [ADDR_WIDTH-1:0] addr_rd,
output reg [DATA_WIDTH-1:0] dout,
input [ADDR_WI... | 7.453937 |
module cfg_shift_register (
input clk, // Clock
input din, // Clock Enable
output [0:31] q
);
always @(posedge clk) begin
q[1:31] <= q[0:30];
q[0] <= din;
end
endmodule
| 6.511086 |
module cfg_tag_tb ();
// double underscore __ separates test packet for each node
localparam test_vector_bits_lp = 319;
localparam test_vector_lp = 319'b0_0_001101010101_0_101010101001_0_110100000110_0_00000001_0_00111101_0_10__0_0_001001010101_0_101010101111_0_111100000000_0_00000001_0_00111101_0_10__0_0_0... | 7.008994 |
module cfg_test #(
parameter DATA_WIDTH = 32
) (
input clk,
input rstn,
input [DATA_WIDTH - 1 : 0] in_0_2,
input [DATA_WIDTH - 1 : 0] in_0_3,
input [DATA_WIDTH - 1 : 0] in_0_4,
input [DATA_WIDTH - 1 : 0] in_1_0,
input [DATA_WIDTH - 1 : 0] in_1_1,
input [DATA_WIDTH - 1 : 0] in_... | 8.205532 |
module cfg_test_top (
input clk,
input rstn,
input [32 - 1 : 0] addr,
input [32 - 1 : 0] wdata,
output [32 - 1 : 0] rdata,
output rdata_vld,
input wr,
input rd
);
wire [31:0] in_0_2;
wire [31:0] in_0_3;
wire [31:0] in_0_4;
wire [31:0]... | 6.646716 |
module cfg_wait ( /*AUTOARG*/
// Outputs
adio_in,
c_term,
c_ready,
// Inputs
reset,
CLK,
cfg_hit,
cfg_vld,
s_wrdn,
s_data,
s_data_vld,
addr,
adio_out
);
input reset;
input CLK;
input cfg_hit;
input cfg_vld;
input s_wrdn;
input s_data;
input s_data... | 7.032108 |
module cfi_ctrl_engine_bench ();
// Signal Bus
wire [ 8 - 1:0] DQ; // Data I/0 Bus
// Control Signal
wire WE_N; // Write Enable
wire RE_N; // Read Enable
wire CE_N; // Chip Enable
wire CLE; // Command Latch Enable
wire ... | 6.65001 |
module cfs_twi_slave #(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 32
) (
input wire clk_i,
input wire rstn_i,
// host bus
input wire wren_i,
input wire rden_i,
input wire [ADDR_WIDTH-1:0] addr_i,
input wire [DATA_WIDTH-1:0] data_i,
ou... | 8.201135 |
module cfulladder (
S,
cout,
a,
b,
cin
);
input a, b, cin;
wire my_xor1, my_and1, my_and2, my_not1, my_not2;
output S, cout;
//always
xor myXor1 (my_xor1, a, b);
not myNot1 (my_not1, a);
and myAnd1 (my_and1, my_not1, b);
xor myXor2 (S, my_xor1, cin);
not myNot2 (my_not2, my_xor1... | 6.738664 |
module cf_add (
// data_p = data_1 + data_2 + data_3 + data_4 (all the inputs are signed)
clk,
data_1,
data_2,
data_3,
data_4,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out
);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
... | 8.181215 |
module cf_csc_1_add (
// data_p = data_1 + data_2 + data_3 + data_4 (all the inputs are signed)
clk,
data_1,
data_2,
data_3,
data_4,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out
);
// delayed data bus width
parameter DELAY_DATA_WIDTH ... | 7.758929 |
module cf_csc_CrYCb2RGB (
// Cr-Y-Cb inputs
clk,
CrYCb_vs,
CrYCb_hs,
CrYCb_de,
CrYCb_data,
// R-G-B outputs
RGB_vs,
RGB_hs,
RGB_de,
RGB_data
);
// Cr-Y-Cb inputs
input clk;
input CrYCb_vs;
input CrYCb_hs;
input CrYCb_de;
input [23:0] CrYCb_data;
// R-G-B ... | 6.974668 |
module cf_csc_RGB2CrYCb (
// R-G-B inputs
clk,
RGB_vs,
RGB_hs,
RGB_de,
RGB_data,
// Cr-Y-Cb outputs
CrYCb_vs,
CrYCb_hs,
CrYCb_de,
CrYCb_data
);
// R-G-B inputs
input clk;
input RGB_vs;
input RGB_hs;
input RGB_de;
input [23:0] RGB_data;
// Cr-Y-Cb outputs
... | 6.874213 |
module cf_ddsv_intp_1 (
// data_s0 = delayed(data_a);
// data_s1 = scale_a * data_a + scale_b * data_b;
clk,
data_a,
data_b,
scale_a,
scale_b,
data_s0,
data_s1
);
// data_s0 = delayed(data_a);
// data_s1 = scale_a * data_a + scale_b * data_b;
input clk;
input [15:0] data_... | 6.616407 |
module cf_fir_3_8_8 (
clock_c,
reset_i,
data_i,
k0_i,
k1_i,
k2_i,
k3_i,
data_o
);
input clock_c;
input reset_i;
input [7:0] data_i;
input [7:0] k0_i;
input [7:0] k1_i;
input [7:0] k2_i;
input [7:0] k3_i;
output [17:0] data_o;
wire [17:0] n1;
cf_fir_3_8_8_1 s1 (
... | 6.55994 |
module cf_hdmi_16b_es (
// hdmi input (to vdma) interface
h2v_hdmi_clk,
h2v_hdmi_data,
// vdma clock
vdma_clk,
// vdma output (from hdmi) interface
h2v_vdma_fs,
h2v_vdma_fs_ret,
h2v_vdma_valid,
h2v_vdma_be,
h2v_vdma_data,
h2v_vdma_last,
h2v_vdma_ready,
// pr... | 7.329392 |
module cf_mem (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
parameter DW = 16;
parameter AW = 5;
input clka;
input wea;
input [AW-1:0] addra;
input [DW-1:0] dina;
input clkb;
input [AW-1:0] addrb;
output [DW-1:0] doutb;
reg [DW-1:0] m_ram [0:((2**AW)-1)];
reg [DW... | 7.571038 |
module cf_rca_16_32 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
i9,
i10,
i11,
i12,
i13,
i14,
i15,
i16,
i17,
i18,
o1
);
input [4:0] i1;
input [15:0] i2;
input [15:0] i3;
input [15:0] i4;
input [15:0] i5;
input [15:0] i6;
input [15:0] i7;
i... | 6.675712 |
module cf_rca_16_34 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
i9,
i10,
i11,
i12,
i13,
i14,
i15,
i16,
i17,
i18,
o1
);
input [4:0] i1;
input [15:0] i2;
input [15:0] i3;
input [15:0] i4;
input [15:0] i5;
input [15:0] i6;
input [15:0] i7;
i... | 6.529225 |
module cf_rca_16_37 (
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8,
o1
);
input [4:0] i1;
input [15:0] i2;
input [15:0] i3;
input [15:0] i4;
input [15:0] i5;
input [15:0] i6;
input [15:0] i7;
input [15:0] i8;
output [15:0] o1;
wire [4:0] n1;
wire n2;
wire [4:0] n3;
wire n... | 6.58131 |
module cf_spi (
spi_cs0n,
spi_cs1n,
spi_clk,
spi_sd_o,
spi_sd_i,
up_rstn,
up_clk,
up_spi_start,
up_spi_devsel,
up_spi_wdata_1,
up_spi_wdata_0,
up_spi_rdata,
up_spi_status,
debug_trigger,
debug_data
);
output spi_cs0n;
output spi_cs1n;
output spi_clk;... | 6.756871 |
module cf_ss_422to444 (
// 422 inputs
clk,
s422_vs,
s422_hs,
s422_de,
s422_data,
// 444 outputs
s444_vs,
s444_hs,
s444_de,
s444_data,
// change to switch Cr/Cb sel (0-> Cb first, 1-> Cr first)
Cr_Cb_sel_init
);
input clk;
input s422_vs;
input s422_hs;
i... | 6.870579 |
module cf_ss_444to422 (
// 444 inputs
clk,
s444_vs,
s444_hs,
s444_de,
s444_data,
// 422 outputs
s422_vs,
s422_hs,
s422_de,
s422_data,
// change to switch Cr/Cb sel (0-> Cb first, 1-> Cr first)
Cr_Cb_sel_init
);
input clk;
input s444_vs;
input s444_hs;
i... | 7.209077 |
module check_clock_gating (
clk,
res,
d,
val,
en
);
input [31:0] d;
output [31:0] val;
input clk, res, en;
wire n42, n43, n44;
sky130_fd_sc_hd__dfrtp_1 \val_reg[31] (
.D(d[31]),
.CLK(n43),
.RESET_B(n42),
.Q(val[31])
);
sky130_fd_sc_hd__dfrtp_1 \val_reg[30] (
... | 6.57428 |
module cg4 (
output co0l,
output co1l,
output co2l,
output g,
output p,
input cin,
input g0,
input g1,
input g2,
input g3,
input p0,
input p1,
input p2,
input p3
);
wire cinl;
wire co0t;
wire co1t0, co1t1;
wire co2t0, co2t1, co2t2;
wire gt0, gt1, gt2;
... | 6.954704 |
module cga_attrib (
input wire clk,
input wire [7:0] att_byte,
input wire [4:0] row_addr,
input wire [7:0] cga_color_reg,
input wire grph_mode,
input wire bw_mode,
input wire mode_640,
input wire tandy_16_mode,
input wire display_enable,
... | 8.244402 |
module cga_scandoubler (
input clk,
input line_reset,
input [3:0] video,
output reg dbl_hsync,
output [3:0] dbl_video
);
reg sclk = 1'b0;
reg [9:0] hcount_slow;
reg [9:0] hcount_fast;
reg line_reset_old = 1'b0;
wire [9:0] addr_a;
wire [9:0] addr_b;
reg [3:0] data_a;
reg [3:0] data... | 7.546447 |
module cga_sequencer (
input wire clk,
output wire [4:0] clk_seq,
output wire vram_read,
output wire vram_read_a0,
output wire vram_read_char,
output wire vram_read_att,
input wire hres_mode,
output wire crtc_clk,
output wire charrom_... | 7.679562 |
module cga_vram (
// Clock
input clk,
// Lines from other logic
// Port 0 is read/write
input [18:0] isa_addr,
input [7:0] isa_din,
output [7:0] isa_dout,
input isa_read,
input isa_write,
input isa_op_enable,
// Port 1 is read only
input [18:0] pixel_addr,
output re... | 7.487488 |
module cgen_memory_1rd_1wr #(
parameter BITS = 4,
SIZE = 128,
FWD = 1,
LATENCY_0 = 1,
WENSIZE = 1
) (
input clk
// RD PORT 0
, input [`log2(SIZE)-1:0] rd_addr_0
, input rd_enable_0
, output reg [ BITS-1:0] rd_dout_0
// WR PORT 0
, input... | 6.605734 |
module cgen_memory_1rd_2wr #(
parameter BITS = 4,
SIZE = 128,
FWD = 1,
LATENCY_0 = 1,
WENSIZE = 1
) (
input clock
, input [`log2(SIZE)-1:0] rd_addr_0
, input rd_enable_0
, output reg [ BITS-1:0] rd_dout_0
, input [`log2(SIZE)-1:0] wr_addr_0
... | 6.605734 |
module cgen_memory_2rd_1wr #(
parameter BITS = 4,
SIZE = 128,
FWD = 1,
LATENCY_0 = 1,
WENSIZE = 1
) (
input clock
, input [`log2(SIZE)-1:0] rd_addr_0
, input rd_enable_0
, output reg [ BITS-1:0] rd_dout_0
, input [`log2(SIZE)-1:0] rd_addr_... | 6.572293 |
module cgen_memory_2rd_2wr #(
parameter BITS = 4,
SIZE = 128,
FWD = 1,
LATENCY_0 = 1,
WENSIZE = 1
) (
input clock
, input [`log2(SIZE)-1:0] rd_addr_0
, input rd_enable_0
, output reg [ BITS-1:0] rd_dout_0
, input [`log2(SIZE)-1:0] rd_addr_... | 6.572293 |
module cgen_memory_3rd_1wr #(
parameter BITS = 4,
SIZE = 128,
FWD = 1,
LATENCY_0 = 1,
WENSIZE = 1
) (
input clock
, input [`log2(SIZE)-1:0] rd_addr_0
, input rd_enable_0
, output reg [ BITS-1:0] rd_dout_0
, input [`log2(SIZE)-1:0] rd_addr_... | 6.554907 |
module cgen_memory_3rd_2wr #(
parameter BITS = 4,
SIZE = 128,
FWD = 1,
LATENCY_0 = 1,
WENSIZE = 1
) (
input clock
, input [`log2(SIZE)-1:0] rd_addr_0
, input rd_enable_0
, output reg [ BITS-1:0] rd_dout_0
, input [`log2(SIZE)-1:0] rd_addr_... | 6.554907 |
module cgen_tb ();
reg clk = 0;
reg reset = 1;
initial begin
//$dumpfile("md5tb.vcd");
$dumpvars(0, clk);
$dumpvars(0, word_counter);
$dumpvars(0, valid);
$dumpvars(0, finished);
$dumpvars(0, char_offset);
$dumpvars(0, char_value);
#20000 $finish;
end
always #0.5 clk = !cl... | 6.942147 |
module, respectively
//g and p are the generating and propagating functions
//coming from the carry lookahead cells, respectively
`ifndef CGL4B_V
`define CGL4B_V
module cgl4b(cin, g, p, carry, G, P);
input[3:0] g, p;
input cin;
output[3:1] carry;
output G, P;
wire[3:0] g, p;
wire[3:1] carry;
wir... | 7.561722 |
module cgmiiFSM #(
parameter DATA_NBIT = 8,
parameter IDLE_NBIT = 5,
parameter TERM_NBIT = 3,
parameter DEBUG_NBIT = 4,
parameter N_STATES = 5
) (
input i_clock,
input i_reset,
input i_enable,
input [DEBUG_NBIT - 1:0] i_debug_pulse, //senial utilizada para forzar transiciones d... | 8.012539 |
module coreir_const #(
parameter value = 1,
parameter width = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module muxn_U12 (
input [1:0] in_data_0,
input [1:0] in_data_1,
input [0:0] in_sel,
output [1:0] out
);
// Instancing generated Module: coreir.mux(width:2)
wire [1:0] _join__in0;
wire [1:0] _join__in1;
wire [1:0] _join__out;
wire _join__sel;
coreir_mux #(
.width(2)
) _join (
... | 7.322571 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module coreir_or #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 | in1;
endmodule
| 8.25836 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module Decode18 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_1_8__out;
coreir_const #(
.value(8'h01),
.width(8)
) const_1_8 (
.out(const_1_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 6.99721 |
module Decode88 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_8_8__out;
coreir_const #(
.value(8'h08),
.width(8)
) const_8_8 (
.out(const_8_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.404897 |
module Decode118 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_11_8__out;
coreir_const #(
.value(8'h0b),
.width(8)
) const_11_8 (
.out(const_11_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir... | 6.977478 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.