code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module muxn_U10 (
input [31:0] in_data_0,
input [31:0] in_data_1,
input [ 0:0] in_sel,
output [31:0] out
);
// Instancing generated Module: coreir.mux(width:32)
wire [31:0] _join__in0;
wire [31:0] _join__in1;
wire [31:0] _join__out;
wire _join__sel;
coreir_mux #(
.width(32)
) _j... | 7.008917 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module Decode58 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_5_8__out;
coreir_const #(
.value(8'h05),
.width(8)
) const_5_8 (
.out(const_5_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.180848 |
module Mux2x32 (
input [31:0] I0,
input [31:0] I1,
output [31:0] O,
input S
);
// Instancing generated Module: commonlib.muxn(N:2, width:32)
wire [31:0] coreir_commonlib_mux2x32_inst0__in_data_0;
wire [31:0] coreir_commonlib_mux2x32_inst0__in_data_1;
wire [ 0:0] coreir_commonlib_mux2x32_inst0_... | 7.709369 |
module muxn_U11 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_sel,
output [0:0] out
);
// Instancing generated Module: coreir.mux(width:1)
wire [0:0] _join__in0;
wire [0:0] _join__in1;
wire [0:0] _join__out;
wire _join__sel;
coreir_mux #(
.width(1)
) _join (
... | 7.227802 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
output [0:0] O,
input S
);
// Instancing generated Module: commonlib.muxn(N:2, width:1)
wire [0:0] coreir_commonlib_mux2x1_inst0__in_data_0;
wire [0:0] coreir_commonlib_mux2x1_inst0__in_data_1;
wire [0:0] coreir_commonlib_mux2x1_inst0__in_... | 7.639545 |
module muxn_U13 (
input [4:0] in_data_0,
input [4:0] in_data_1,
input [0:0] in_sel,
output [4:0] out
);
// Instancing generated Module: coreir.mux(width:5)
wire [4:0] _join__in0;
wire [4:0] _join__in1;
wire [4:0] _join__out;
wire _join__sel;
coreir_mux #(
.width(5)
) _join (
... | 7.730691 |
module muxn_U31 (
input [15:0] in_data_0,
input [15:0] in_data_1,
input [ 0:0] in_sel,
output [15:0] out
);
// Instancing generated Module: coreir.mux(width:16)
wire [15:0] _join__in0;
wire [15:0] _join__in1;
wire [15:0] _join__out;
wire _join__sel;
coreir_mux #(
.width(16)
) _j... | 6.931789 |
module coreir_not #(
parameter width = 1
) (
input [width-1:0] in,
output [width-1:0] out
);
assign out = ~in;
endmodule
| 8.534147 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module MuxWrapper_1_1 (
input [0:0] I_0,
output [0:0] O
);
assign O[0:0] = I_0[0:0];
endmodule
| 6.716798 |
module coreir_reg_arst #(
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1,
parameter width = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
... | 8.40589 |
module muxn_U32 (
input [31:0] in_data_0,
input [31:0] in_data_1,
input [31:0] in_data_2,
input [31:0] in_data_3,
input [ 1:0] in_sel,
output [31:0] out
);
// Instancing generated Module: coreir.mux(width:32)
wire [31:0] _join__in0;
wire [31:0] _join__in1;
wire [31:0] _join__out;
... | 7.616307 |
module muxn_U16 (
input [15:0] in_data_0,
input [15:0] in_data_1,
input [15:0] in_data_2,
input [15:0] in_data_3,
input [ 1:0] in_sel,
output [15:0] out
);
// Instancing generated Module: coreir.mux(width:16)
wire [15:0] _join__in0;
wire [15:0] _join__in1;
wire [15:0] _join__out;
... | 7.571074 |
module muxn_U15 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_data_2,
input [0:0] in_data_3,
input [1:0] in_sel,
output [0:0] out
);
// Instancing generated Module: coreir.mux(width:1)
wire [0:0] _join__in0;
wire [0:0] _join__in1;
wire [0:0] _join__out;
wire _jo... | 7.997775 |
module muxn_U14 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_data_2,
input [1:0] in_sel,
output [0:0] out
);
// Instancing generated Module: coreir.mux(width:1)
wire [0:0] _join__in0;
wire [0:0] _join__in1;
wire [0:0] _join__out;
wire _join__sel;
coreir_mux #(
... | 8.10045 |
module muxn_U42 (
input [15:0] in_data_0,
input [15:0] in_data_1,
input [15:0] in_data_2,
input [15:0] in_data_3,
input [15:0] in_data_4,
input [15:0] in_data_5,
input [15:0] in_data_6,
input [15:0] in_data_7,
input [ 2:0] in_sel,
output [15:0] out
);
// Instancing g... | 7.762455 |
module muxn_U17 (
input [31:0] in_data_0,
input [31:0] in_data_1,
input [31:0] in_data_2,
input [31:0] in_data_3,
input [31:0] in_data_4,
input [31:0] in_data_5,
input [31:0] in_data_6,
input [31:0] in_data_7,
input [ 2:0] in_sel,
output [31:0] out
);
// Instancing g... | 7.798102 |
module muxn_U41 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_data_2,
input [0:0] in_data_3,
input [0:0] in_data_4,
input [0:0] in_data_5,
input [0:0] in_data_6,
input [0:0] in_data_7,
input [2:0] in_sel,
output [0:0] out
);
// Instancing generated M... | 8.283787 |
module muxn_U40 (
input [31:0] in_data_0,
input [31:0] in_data_1,
input [31:0] in_data_10,
input [31:0] in_data_11,
input [31:0] in_data_12,
input [31:0] in_data_13,
input [31:0] in_data_14,
input [31:0] in_data_15,
input [31:0] in_data_2,
input [31:0] in_data_3,
in... | 7.608344 |
module muxn_U39 (
input [15:0] in_data_0,
input [15:0] in_data_1,
input [15:0] in_data_10,
input [15:0] in_data_11,
input [15:0] in_data_12,
input [15:0] in_data_13,
input [15:0] in_data_14,
input [15:0] in_data_15,
input [15:0] in_data_2,
input [15:0] in_data_3,
in... | 6.944152 |
module muxn_U36 (
input [0:0] in_data_0,
input [0:0] in_data_1,
input [0:0] in_data_10,
input [0:0] in_data_11,
input [0:0] in_data_12,
input [0:0] in_data_13,
input [0:0] in_data_14,
input [0:0] in_data_15,
input [0:0] in_data_2,
input [0:0] in_data_3,
input [0:0]... | 7.306746 |
module muxn_U6 (
input [31:0] in_data_0,
input [31:0] in_data_1,
input [31:0] in_data_10,
input [31:0] in_data_11,
input [31:0] in_data_2,
input [31:0] in_data_3,
input [31:0] in_data_4,
input [31:0] in_data_5,
input [31:0] in_data_6,
input [31:0] in_data_7,
input ... | 7.94291 |
module test_pe (
input bit0,
input bit1,
input bit2,
input [7:0] cfg_a,
input [31:0] cfg_d,
input cfg_en,
input clk,
input clk_en,
input [15:0] data0,
input [15:0] data1,
output irq,
output [31:0] read_data,
output [15:0] res,
output res_p,
input rst
);
endmo... | 6.522693 |
module coreir_ult #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 < in1;
endmodule
| 7.861561 |
module Mux2xOutBits5 (
input [4:0] I0,
input [4:0] I1,
output [4:0] O,
input S
);
// Instancing generated Module: commonlib.muxn(N:2, width:5)
wire [4:0] coreir_commonlib_mux2x5_inst0__in_data_0;
wire [4:0] coreir_commonlib_mux2x5_inst0__in_data_1;
wire [0:0] coreir_commonlib_mux2x5_inst0__in_... | 7.657839 |
module Decode108 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_10_8__out;
coreir_const #(
.value(8'h0a),
.width(8)
) const_10_8 (
.out(const_10_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir... | 7.019666 |
module Decode08 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_0_8__out;
coreir_const #(
.value(8'h00),
.width(8)
) const_0_8 (
.out(const_0_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.031526 |
module Decode38 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_3_8__out;
coreir_const #(
.value(8'h03),
.width(8)
) const_3_8 (
.out(const_3_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.159744 |
module Decode28 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_2_8__out;
coreir_const #(
.value(8'h02),
.width(8)
) const_2_8 (
.out(const_2_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 6.517855 |
module Decode48 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_4_8__out;
coreir_const #(
.value(8'h04),
.width(8)
) const_4_8 (
.out(const_4_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.631193 |
module Decode68 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_6_8__out;
coreir_const #(
.value(8'h06),
.width(8)
) const_6_8 (
.out(const_6_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.244347 |
module Decode78 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_7_8__out;
coreir_const #(
.value(8'h07),
.width(8)
) const_7_8 (
.out(const_7_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 6.65526 |
module Decode98 (
input [7:0] I,
output O
);
// Instancing generated Module: coreir.const(width:8)
wire [7:0] const_9_8__out;
coreir_const #(
.value(8'h09),
.width(8)
) const_9_8 (
.out(const_9_8__out)
);
// Instancing generated Module: coreir.eq(width:8)
wire [7:0] coreir_eq_... | 7.014413 |
module Mux12x32 (
input [31:0] I0,
input [31:0] I1,
input [31:0] I10,
input [31:0] I11,
input [31:0] I2,
input [31:0] I3,
input [31:0] I4,
input [31:0] I5,
input [31:0] I6,
input [31:0] I7,
input [31:0] I8,
input [31:0] I9,
output [31:0] O,
input [ 3:... | 8.52603 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
input S
);
// Instancing generated Module: commonlib.muxn(N:2, width:2)
wire [1:0] coreir_commonlib_mux2x2_inst0__in_data_0;
wire [1:0] coreir_commonlib_mux2x2_inst0__in_data_1;
wire [0:0] coreir_commonlib_mux2x2_inst0__in_... | 7.816223 |
module ConfigRegister_2_8_32_6 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_7 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_16 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_4 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_5 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_9 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_10 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_18 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_17 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_13 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_0 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_14 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_11 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_19 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_15 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_8 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_1 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_12 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_2_8_32_3 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ConfigRegister_2_8_32_2 (
output [1:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_2_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module Mux3x1 (
input [0:0] I0,
input [0:0] I1,
input [0:0] I2,
output [0:0] O,
input [1:0] S
);
// Instancing generated Module: commonlib.muxn(N:3, width:1)
wire [0:0] coreir_commonlib_mux3x1_inst0__in_data_0;
wire [0:0] coreir_commonlib_mux3x1_inst0__in_data_1;
wire [0:0] coreir_comm... | 7.509488 |
module Mux4x1 (
input [0:0] I0,
input [0:0] I1,
input [0:0] I2,
input [0:0] I3,
output [0:0] O,
input [1:0] S
);
// Instancing generated Module: commonlib.muxn(N:4, width:1)
wire [0:0] coreir_commonlib_mux4x1_inst0__in_data_0;
wire [0:0] coreir_commonlib_mux4x1_inst0__in_data_1;
w... | 8.038083 |
module Mux4x16 (
input [15:0] I0,
input [15:0] I1,
input [15:0] I2,
input [15:0] I3,
output [15:0] O,
input [ 1:0] S
);
// Instancing generated Module: commonlib.muxn(N:4, width:16)
wire [15:0] coreir_commonlib_mux4x16_inst0__in_data_0;
wire [15:0] coreir_commonlib_mux4x16_inst0__in... | 7.810075 |
module Mux8x32 (
input [31:0] I0,
input [31:0] I1,
input [31:0] I2,
input [31:0] I3,
input [31:0] I4,
input [31:0] I5,
input [31:0] I6,
input [31:0] I7,
output [31:0] O,
input [ 2:0] S
);
// Instancing generated Module: commonlib.muxn(N:8, width:32)
wire [31:0] cor... | 8.392855 |
module MuxWrapper_0_1 (
input [0:0] I_0,
output [0:0] O
);
assign O[0:0] = I_0[0:0];
endmodule
| 6.963274 |
module MuxWrapper_0_16 (
input [15:0] I_0,
output [15:0] O
);
assign O[15:0] = I_0[15:0];
endmodule
| 6.963274 |
module MuxWrapper_1_16 (
input [15:0] I_0,
output [15:0] O
);
assign O[15:0] = I_0[15:0];
endmodule
| 6.716798 |
module MuxWithDefaultWrapper_8_32_8_0 (
input [ 0:0] EN,
input [31:0] I_0,
input [31:0] I_1,
input [31:0] I_2,
input [31:0] I_3,
input [31:0] I_4,
input [31:0] I_5,
input [31:0] I_6,
input [31:0] I_7,
output [31:0] O,
input [ 7:0] S
);
wire [31:0] MuxWrapper_2_3... | 8.218717 |
module Or5x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
output [7:0] O
);
// Instancing generated Module: coreir.orr(width:5)
wire [4:0] orr_inst0__in;
wire orr_inst0__out;
coreir_orr #(
.width(5)
) orr_inst0 (
.in (orr_inst0__i... | 7.318301 |
module PECore (
input [0:0] bit0,
input [0:0] bit1,
input [0:0] bit2,
input clk,
input [7:0] config_config_addr,
input [31:0] config_config_data,
input [0:0] config_read,
input [0:0] config_write,
input [15:0] data0,
input [15:0] data1,
output [31:0] read_config_data,
out... | 6.67118 |
module ConfigRegister_1_8_32_31 (
output [0:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_1_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_1_8_32_30 (
output [0:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_1_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_asyn... | 7.101033 |
module ConfigRegister_5_8_32_0 (
output [4:0] O,
input clk,
input [7:0] config_addr,
input [31:0] config_data,
input config_en,
input reset
);
wire Register_has_ce_True_has_reset_False_has_async_reset_True_type_Bits_n_5_inst0__ASYNCRESET;
wire Register_has_ce_True_has_reset_False_has_async... | 7.101033 |
module ZextWrapper_5_32 (
input [ 4:0] I,
output [31:0] O
);
wire bit_const_0_None__out;
corebit_const #(.value(0)) bit_const_0_None (.out(bit_const_0_None__out));
assign O[10] = bit_const_0_None__out;
assign O[11] = bit_const_0_None__out;
assign O[12] = bit_const_0_None__out;
assign O[13] = ... | 6.790158 |
module cgrom (
i_clk,
i_char_addr,
o_char_strip
);
parameter DATA_WIDTH = 8, ADDR_WIDTH = 10, CHAR_STRIPS = 656; // 41*16 = 656 * 8-bit strips
parameter [DATA_WIDTH-1:0] ROM_DEFLT_DATA = {DATA_WIDTH{1'b0}};
parameter [ADDR_WIDTH-1:0] ROM_END_ADDR = CHAR_STRIPS;
input i_clk;
input [ADDR_WIDTH-1:... | 7.154569 |
module ram_dual_port (
clk,
clken,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
byteena_a,
byteena_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
... | 8.296277 |
module rom_dual_port (
clk,
clken,
address_a,
address_b,
q_a,
q_b
);
parameter width_a = 1'd0;
parameter width_b = 1'd0;
parameter widthad_a = 1'd0;
parameter widthad_b = 1'd0;
parameter numwords_a = 1'd0;
parameter numwords_b = 1'd0;
parameter init_file = "UNUSED.mif";
paramete... | 7.576841 |
module ML605 (
USER_CLOCK,
KEY,
SW,
LED,
LEDG,
UART_RXD,
UART_TXD
);
input USER_CLOCK;
input [4:0] KEY;
input [7:0] SW;
output [7:0] LED;
output [7:0] LEDG;
wire CLOCK_50;
input UART_RXD;
output UART_TXD;
wire clk = CLOCK_50;
wire go = ~KEY[1];
wire reset = ~KEY[0... | 6.767428 |
module de4 (
OSC_50_BANK2,
BUTTON,
LED,
SEG0_D,
SEG1_D
);
input OSC_50_BANK2;
input [1:0] BUTTON;
output [6:0] SEG0_D;
output [6:0] SEG1_D;
output [7:0] LED;
de2 de2_inst (
.CLOCK_50(OSC_50_BANK2),
.LEDG(LED),
.KEY(BUTTON),
.SW(),
.HEX0(SEG0_D),
.HEX1... | 7.073756 |
module de2 (
CLOCK_50,
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
LEDG,
UART_RXD,
UART_TXD
);
input CLOCK_50;
input [3:0] KEY;
input [17:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [6:0] hex0, hex1, hex2, hex3,... | 7.759103 |
module chacha20_quarter (
input wire [31:0] ai,
bi,
ci,
di,
output reg [31:0] a,
b,
c,
d
);
always @(*) begin
a = ai;
b = bi;
c = ci;
d = di;
`define ROTL32(w, n) {w[31-n:0], w[31:32-n]}
a = a + b;
d = d ^ a;
d = `ROTL32(d, 16);
c = c + d;
b = ... | 6.922399 |
module chacha20_test;
parameter N = 5;
reg [$bits(N):0] i = 0;
reg [255:0] keys[N:0];
reg [63:0] nonces[N:0];
reg [63:0] indexes[N:0];
reg [511:0] outs[N:0];
initial begin
keys[0] = 256'h0000000000000000000000000000000000000000000000000000000000000000;
nonces[0] = 64'h0000000000000000;
index... | 6.948952 |
module to allow
// us to build versions of the cipher with 1, 2, 4 and even 8
// parallel qr functions.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions... | 7.487454 |
module chain_arbiter (
clk,
rst,
cin,
cin_status,
cin_vld,
local_done,
cout,
cout_status,
cout_vld,
dump_cmd
);
parameter CHAINS_IN = 1;
parameter CHAINS_OUT = 1;
localparam CIN_LIMIT = (CHAINS_IN == 0 ? 0 : CHAINS_IN - 1);
localparam CHAIN_BLOCKS = CHAINS_IN / CHAINS_O... | 6.597796 |
module chain_controller (
input clk,
input rst,
input [CHAINS_IN-1:0] cin_ready, // Chains in ready
input [CHAINS_IN-1:0] cin_done, // Chains in done dumping
input [CHAINS_IN-1:0] cin, // Chains in
output [CHAINS_IN-1:0] cin_en, // Chains in enable
input [CHAINS_OUT-1:0] cout_en, // C... | 6.7195 |
module: chain_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module chain_controller_tb;
localparam CHAINS_IN = 5;
localparam CHAINS_OUT = 3;
// Inputs
reg clk;
reg rst;
... | 6.972656 |
module chain_delay_adjust (
clk,
rst,
calibrate_a,
calibrate_b,
a_wins,
b_wins,
valid,
adjusting,
current_stats
);
parameter CALIBRATE_BITS = 4;
input clk, rst;
output [CALIBRATE_BITS-1:0] calibrate_a;
output [CALIBRATE_BITS-1:0] calibrate_b;
input a_wins, b_wins, valid;
... | 6.751818 |
module: chain_interpreter_tm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module chain_interpreter_tb;
// Inputs
reg clk;
reg rst;
reg [2:0] cin;
// Instantiate the Unit Under Tes... | 7.322468 |
module chain_interpreter_tm (
input clk,
input rst,
input [CHAINS_IN-1:0] cin
);
parameter CHAINS_IN = 1;
parameter CHAIN_DEPTH = 8;
genvar i;
generate
for (i = 0; i < CHAINS_IN; i = i + 1) begin : REGISTERS
wire [CHAIN_DEPTH-1:0] chain_reg;
dffr_ns #(CHAIN_DEPTH) shift_register (
... | 6.66503 |
module chain_test_assembly_tb;
localparam CHAINS_IN = 5;
localparam CHAINS_OUT = 3;
localparam SIZE = 8;
// Inputs
reg clk;
reg dclk1, dclk2;
reg rst;
reg c_en;
reg [SIZE-1:0] d_0, d_1, d_2, d_3, d_4;
reg [CHAINS_OUT-1:0] d_en;
// Outputs
wire [ CHAINS_IN-1:0] d_out;
wire [ CHAINS_IN-1:0]... | 7.086724 |
module challengeGen #(
parameter CHALLENGE_LENGTH = 32
) (
input clk,
input rst,
input pause,
output [CHALLENGE_LENGTH-1:0] out
);
reg LFSR_generateNext;
wire [CHALLENGE_LENGTH-1:0] LFSR_out;
wire [CHALLENGE_LENGTH-1:0] LFSR_seed;
// in implementation the LFSR should be replaced with a tru... | 7.714097 |
module challenge_gen #(
parameter N_CB = 64
) (
input wire clk,
input wire rst,
output reg [N_CB-1:0] C
);
parameter n = 3, N_RO = 32, logN = 5, N_RNG = 4;
wire [N_RNG-1:0] RAND;
genvar k;
generate
for (k = 0; k < N_RNG; k = k + 1) begin : TRNG
TRNG_RO #(n, N_RO, logN) TRNG_RO1 (
... | 6.821243 |
module chalmem (
// OUTPUTs
ram_dout, // RAM data output
// INPUTs
ram_addr, // RAM address
ram_cen, // RAM chip enable (low active)
ram_clk, // RAM clock
ram_din, // RAM data input
ram_wen // RAM write enable (low active)
);
// PARAMETERs
//============
parameter ADDR_MS... | 6.526431 |
module ChalShiftReg (
input wire clk,
input wire si,
input wire rstn,
output [127:0] c,
output wire so
);
reg [127:0] c;
// N-Bit shift register with scan in and scan out
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
c[127:0] <= 0;
end else begin
c[127:0] <... | 8.052252 |
module chamaDig ();
reg key1, key2;
wire [6:0] hex1, hex2;
wire [3:0] bcd1;
wire teste;
wire [3:0] d3;
digitos chamado (
.key1(key1),
.key2(key2),
.hex1(hex1),
.hex2(hex2),
.bcd1(bcd1),
.teste(teste),
.d3(d3)
);
endmodule
| 6.853954 |
module de0_nano_clock_gen (
input wire i_clk,
input wire i_rst,
output wire o_clk,
output wire o_rst
);
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked) r <= {r[8:0], 1'b0};
else r <= 10'b1111111111;
wire [5:0] clk;
assign o_clk = clk[0... | 7.220966 |
module change (
rst,
data_inP,
data_inN,
data_out,
clk
);
//二输入八输出模块，将PN信号转换为八位输出信号作为DAC的输入
input rst, clk, data_inP, data_inN;
output [7:0] data_out;
reg [7:0] data_out;
always @(posedge clk or negedge rst) begin
if (!rst) data_out <= 8'b10000000;
else if (data_inP == 1 && data_... | 8.215554 |
module changeAddr (
input clk100mhz,
input changeaddr,
output reg [18:0] addrBus1
);
always @(posedge clk100mhz) begin
if (changeaddr == 0) addrBus1 = 19'b100_0000_0000_0000_0000;
else if (changeaddr) addrBus1 = 19'b100_0000_0000_0000_0001;
end
endmodule
| 6.728355 |
module changeEndian #(
parameter WIDTH = 64
) (
input [WIDTH-1:0] in_bus,
output [WIDTH-1:0] out_bus
);
localparam PAD_WIDTH = ((WIDTH % 8) == 0) ? 0 : 8 - (WIDTH % 8);
// pad the input to make it an integer number of bytes
wire [WIDTH+PAD_WIDTH-1:0] padded_in_bus;
assign padded_in_bus = {{PAD_WI... | 9.056129 |
module controlMoles (
Reset_n,
Incr,
Decr,
ResetDP_n,
up,
enableCount,
enableStore,
clk
);
input Reset_n, Incr, Decr, clk;
output reg ResetDP_n, //resets datapath
up, //tells the datapath to increase or decrease the number of partciles/moles
enableCount, //enables counting
... | 7.264061 |
module datapathMoles (
Reset_n,
up,
enableCount,
enableStore,
clk,
numMoles
);
input Reset_n, up, enableCount, enableStore, clk;
reg wUp;
output [2:0] numMoles;
//Stores the new value of up assigned from the control path until the user hits the next button
always @(posedge clk) begi... | 6.64318 |
module ChangePw (
clk,
reset,
change,
pw0,
pw1,
pw2,
pw3,
key0,
key1,
key2,
key3
);
input clk;
input reset;
input change;
input [3:0] pw0;
input [3:0] pw1;
input [3:0] pw2;
input [3:0] pw3;
output reg [3:0] key0;
output reg [3:0] key1;
output reg [3:0] key... | 6.713007 |
module changesign (
datain,
dataout,
signout,
clk,
rst_n
);
input clk, rst_n;
input [31:0] datain;
output [31:0] dataout;
output signout;
reg [31:0] dataout;
reg signout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dataout <= 32'd0;
signout <= 0;
... | 7.743827 |
module changesign_h (
datain,
dataout,
signout,
clk,
rst_n
);
input clk, rst_n;
input [15:0] datain;
output [15:0] dataout;
output signout;
reg [15:0] dataout;
reg signout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dataout <= 16'd0;
signout <= 0;
... | 6.833705 |
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