code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module check_code (
input clk,
input res,
input d,
output reg q
);
always @(posedge clk, posedge res) begin
if (res) q <= d;
else q <= 1'b0;
end
endmodule
| 6.58287 |
module check_collision (
input wire [31:0] register,
input wire [31:0] data,
output reg out
);
reg [9:0] x1;
reg [9:0] y1;
reg [9:0] x2;
reg [9:0] y2;
reg [9:0] y_face_1;
reg [9:0] y_face_2;
reg [9:0] x_face_1;
reg [9:0] x_face_2;
/*----------Registers of results-----------*/
reg up... | 6.790372 |
module top_module ();
integer Value1;
parameter Value2 = Value1;
endmodule
| 6.627149 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[N:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[N][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:N];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[N:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:N] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][N:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[N][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[N][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:N];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][N:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:N] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module ();
integer Value2;
sub_module sub_module ();
defparam sub_module.Value1 = Value2;
endmodule
| 6.627149 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[N:0] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module ();
integer Value1;
integer Value2 = Value1;
endmodule
| 6.627149 |
module top_module ();
integer N;
(* attr = N *)
initial $display(N);
endmodule
| 6.627149 |
module top_module (
input wire [2:0] N,
input wire [7:N] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [N:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:N] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [N:0] Array[7:0];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module top_module (
input wire [2:0] N,
input wire [7:0] In,
output reg [7:0] Out
);
wire [7:0] Array[7:N];
assign Array[0][0] = In[0];
assign Array[0][7:1] = In[7:1];
initial begin
Out[0] = Array[0][0];
Out[7:1] = Array[0][7:1];
end
endmodule
| 7.203305 |
module Check_Data_SEG_SEL (
input [31:0] check_data_if,
input [31:0] check_data_id,
input [31:0] check_data_ex,
input [31:0] check_data_mem,
input [31:0] check_data_wb,
input [31:0] check_data_hzd,
input [ 2:0] check_addr,
output reg [31:0] check_data
);
always @(*) begin
ch... | 7.611563 |
module Check_Data_SEL (
input [31:0] pc_cur,
input [31:0] instruction,
input [ 4:0] rf_ra0,
input [ 4:0] rf_ra1,
input rf_re0,
input rf_re1,
input [31:0] rf_rd0_raw,
input [31:0] rf_rd1_raw,
input [31:0] rf_rd0,
input [31:0] rf_rd1,
input [ 4:0] rf_wa,
input... | 7.611563 |
module Check_Data_SEL_HZD (
input [ 4:0] rf_ra0_ex,
input [ 4:0] rf_ra1_ex,
input rf_re0_ex,
input rf_re1_ex,
input [ 1:0] pc_sel_ex,
input [ 4:0] rf_wa_mem,
input rf_we_mem,
input [ 1:0] rf_wd_sel_mem,
input [31:0] alu_ans_mem,
input [31:0] pc_add4_mem,
... | 7.611563 |
module check_eq (
in1,
in2,
out
);
output out;
input [15:0] in1, in2;
assign out = (in1 == in2);
endmodule
| 6.804293 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 4/9/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module check_fp_div_para (
startcheck,
clk,
rst,
in,
ans,
donecheck
);
//------------------------------------------------------------------
// -- Input/Output Declarations --
//------------------------------------------------------------------
paramet... | 6.931483 |
module check_horiz_sync (
OUT,
horiz_c,
CLK
);
output reg OUT;
input [9:0] horiz_c;
input CLK;
initial begin
OUT <= 0;
end
//Bring line low if we're between 0 and 96 (h sync time)
always @(posedge CLK) begin
if (horiz_c < 96) OUT <= 1;
else OUT <= 0;
end
endmodule
| 6.941999 |
module check_logic_sharing (
input a,
input b,
input c,
output x,
output y
);
assign x = a & b & c;
assign y = (a & b) | c;
endmodule
| 7.60855 |
module check_node_comp (
input wire [6:0] n1,
input wire [1:0] n1_index,
input wire [6:0] n2,
input wire [1:0] n2_index,
output reg [6:0] low,
output reg [1:0] low_index,
output reg [6:0] high,
output reg [1:0] high_index
);
always @(*) begin
if (n1[5:0] < n2[5:0]) begin
... | 7.034676 |
module check_sequence_1 (
input clk,
input rst_n,
input din,
output reg result
);
reg [2:0] state, next_state;
localparam IDLE = 3'b000, A = 3'b001, B = 3'b010, C = 3'b011, D = 3'b100, E = 3'b101, F = 3'b110;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= ID... | 7.341344 |
module check_sequence_2 (
input clk,
input rst_n,
input din,
output reg result
);
reg [2:0] state, next_state;
localparam IDLE = 3'b000, A = 3'b001, B = 3'b010, C = 3'b011, D = 3'b100, E = 3'b101, F = 3'b110;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= I... | 7.341344 |
module check_sequence_7 (
input clk,
input rst,
input [15:0] stage,
input [24:0] inp_seq,
input [24:0] correct_seq,
output reg [1:0] check_result
);
reg [0:0] M_result_d, M_result_q = 1'h0;
wire [16-1:0] M_alu_alu;
wire [ 1-1:0] M_alu_z;
wire [ 1-1:0] M_alu_v;
wire [ 1-1:0] M_alu_n... | 7.341344 |
module check_zero_tb ();
reg [26:0] in;
wire out;
is_zero27bits iz (
in,
out
);
initial begin
$monitor("%d %b", in, out);
in = 27'b0;
#500 $stop;
end
always #20 in = in + 1;
endmodule
| 7.662563 |
module cheng (
input [31:0] a,
input [31:0] b,
output [63:0] c
);
assign c = a * b;
endmodule
| 6.567411 |
module */
module rotator(clk,rst_n,xin,yin,ain,xout,yout,aout);
parameter ROTATE_TYPE = "ROTATE"; // ROTATE_TYPE = ROTATE OR VECTOR
parameter ITERATE_INDEX = 0;
parameter DATABITS = 17;
parameter signed [17:0] angle=0;
input clk;
input rst_n;
input signed [DATABITS-1:0] xin,yin;... | 6.605793 |
module */
module rotator(clk,rst_n,xin,yin,ain,xout,yout,aout);
parameter ROTATE_TYPE = "ROTATE"; // ROTATE_TYPE = ROTATE OR VECTOR
parameter ITERATE_INDEX = 0;
parameter DATABITS = 17;
parameter signed [18:0] angle=0;
input clk;
input rst_n;
input signed [DATABITS-1:0] xin,yin;... | 6.605793 |
module:chen_signed_div
* file name:chen_signed_div.v
* author: Chen Zhongyao
* date:2016-04-27
* description:
* This is a signed divider module, input ports is 16 bits signed integer, output ports only have quotient,
* which has 32bits containing a sign bit, 15 whole bits and 16 decimal bits.
* Port ... | 8.055137 |
module:chen_unsigned_div
* file name:chen_unsigned_div.v
* author: Chen Zhongyao
* date:2016-04-27
* description:
* This is a unsigned divider module, input ports is 32 bits unsigned integer, output ports have quotient and remainde,both are 32 bits
* Port divide_en and divide_done is the syn enable signal... | 7.737703 |
module shift_compute #(
parameter width = 64
) (
clk,
a_i,
b_i,
a_o,
b_o
);
input clk;
input [width-1:0] a_i, b_i;
output reg [width-1:0] a_o, b_o;
wire [width-1:0] temp_a, temp_b;
assign temp_a = {a_i[width-2:0], 1'b0};
assign temp_b = b_i;
always @(posedge clk) begin
if (te... | 7.821238 |
module chen_fifo (
clk,
rst,
data_en_i,
data_i,
data_en_o,
data_o
);
parameter DATA_WIDTH = 8;
parameter FRAME_LENGTH = 255;
parameter RAM_ADDR_WIDTH = 8;
input clk;
input rst;
input data_en_i;
input [DATA_WIDTH-1:0] data_i;
output data_en_o;
output [DATA_WIDTH-1:0] dat... | 7.133932 |
module chgdetector (
input wire i_clk,
input wire [31:0] i_data,
input wire i_busy,
output reg o_stb,
output reg [31:0] o_data
);
initial {o_stb, o_data} = 0;
always @(posedge i_clk)
if (!i_busy) begin
o_stb <= 0;
if (o_data != i_data) begin
o_stb <= 1'b1;
o_data... | 6.714227 |
module Div_tru8bit (
in1,
in2,
sub,
cout
); // in1 - in2 = {cout,sub}
input [8:0] in1, in2;
output [9:0] sub;
output cout;
wire [8:0] c;
Tru1bit T[8:0] (
.a(in1[8:0]),
.b(in2[8:0]),
.cin({c[7:0], 1'b0}),
.cout(c[8:0]),
.s(sub[8:0])
);
assign cout = c[8];
... | 7.81417 |
module Div_cong9bit (
in1,
in2,
sum,
cout
);
input [9:0] in1;
input [9:0] in2;
output [9:0] sum;
output cout;
wire [9:0] c;
FA_2 FA_111[9:0] (
.in1 (in1[9:0]),
.in2 (in2[9:0]),
.cin ({c[8:0], 1'b0}),
.cout(c[9:0]),
.sum (sum[9:0])
);
assign cout = c[9];
... | 6.628127 |
module FA_2 (
in1,
in2,
cin,
sum,
cout
); //cong1bit
input wire in1;
input wire in2;
input wire cin;
output wire sum;
output wire cout;
wire temp1, temp2, temp3;
xor (sum, in1, in2, cin);
and (temp1, in1, in2);
and (temp2, in1, cin);
and (temp3, in2, cin);
or (cout, temp1, te... | 7.130943 |
module mux2to1kq (
s,
in1,
in2,
out
); //s=0 out=in1 // s=1 out=in2
input wire s;
input wire [31:0] in1, in2;
output wire [31:0] out;
assign out = (s) ? in2 : in1;
endmodule
| 6.889513 |
module sosanhfrac (
a,
b,
C1
);
input [24:0] a, b;
output reg C1;
wire [24:0] d;
always @(*)
if (b > a) C1 <= 1'b0;
else C1 <= 1'b1;
endmodule
| 6.807756 |
module SpecCase(in,inf,NaN,zero,bt); // chi xet duong // ko xet dau
input wire [31:0]in;
output wire inf,NaN,zero,bt;
wire [7:0]mu;
wire [22:0]frac;
assign mu[7:0]=in[30:23];
assign frac[22:0]=in[22:0];
assign zero=(mu[7:0]==8'b0000_0000) ? 1'b1 : 1'b0;
assign inf=(mu[7:0]==8'b1111_1111) ? ((frac[22:0]==23'b0... | 7.04539 |
module FA1bit (
a,
b,
cin,
cout,
s
);
input a, b, cin;
output cout, s;
assign s = a ^ b ^ cin;
assign cout = a & b | (cin & (a ^ b));
endmodule
| 6.631825 |
module tru10bit (
in1,
in2,
sub,
cout
); // in1 - in2 = {cout,sub}
input [9:0] in1, in2;
output [9:0] sub;
output cout;
wire [9:0] c;
Tru1bit T[9:0] (
.a(in1[9:0]),
.b(in2[9:0]),
.cin({c[8:0], 1'b0}),
.cout(c[9:0]),
.s(sub[9:0])
);
assign cout = c[9];
endmod... | 7.819072 |
module chia_4bit (
input cp,
input [3:0] a,
output [3:0] b,
output c
);
wire [3:0] a1;
//assign a1=4'b0110;
assign a1 = (cp == 1'b1) ? (4'b0110) : (4'b0000);
FA FA[3:0] (
.a(a[3:0]),
.b(a1[3:0]),
.cin(1'b0),
.s(b),
.cout(c)
);
endmodule
| 7.155376 |
module rot_driver (
input clk,
input rot_a,
input rot_b,
output wire rot_dir,
output wire rot_event_out
);
reg rot_a_latch = 0, rot_b_latch = 0;
assign rot_dir = rot_b_latch, rot_event_out = rot_a_latch;
always @(posedge clk) begin
case ({
rot_a, rot_b
})
2'b00: rot_a_latc... | 7.247074 |
module btn_driver (
input clk,
input btn,
output reg sig = 0
);
parameter nskip = 'hfff;
integer counter = 0;
wire lock = counter ? 1 : 0;
always @(posedge clk) begin
if (counter) counter <= counter - 1;
if (!lock && sig != btn) begin
sig <= btn;
counter <= nskip;
end
end
... | 7.348595 |
module chip1 (
input clk,
input b1,
input b2,
input b3,
input b4,
input rot_a,
rot_b,
rot_center,
output [7:0] led,
output vga_red,
output vga_green,
output vga_blue,
output vga_hsync,
output vga_vsync,
output [3:0] j4,
input spi_miso,
output spi_mosi,... | 7.038376 |
module of your design, you cannot modify this module!!
`include "./RISCV_hasHazard2.v"
`include "./FORWARDING_UNIT.v"
`include "./HAZARD_DETECTION_UNIT.v"
`include "./cache_dm.v"
`include "./cache_ro.v"
`include "./DECOMPRESSIONUNIT.v"
module CHIP ( clk,
rst_n,
//----------for slow_memD------------
mem_read_D,
... | 8.453083 |
module top_module (
input p1a,
p1b,
p1c,
p1d,
p1e,
p1f,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
wire and1, and2, and3, and4;
assign and1 = p1a & p1c & p1b;
assign and2 = p1f & p1e & p1d;
assign and3 = p2a & p2b;
assign and4 = p2c & p2d;
assign {... | 7.203305 |
module pullup(output wire pin, output wire d_in);
SB_IO #(.PIN_TYPE(6'b1), .PULLUP(1'b1)) io(.PACKAGE_PIN(pin), .D_IN_0(d_in));
endmodule
| 6.646621 |
module top (
input wire CLK,
output wire LED,
// Turbo mode
input wire PIN_1,
// Keypad:
output wire PIN_22,
output wire PIN_21,
output wire PIN_20,
output wire PIN_19,
input wire PIN_18,
input wire PIN_17,
input wire PIN_16,
input wire PIN_15,
// OLED:
... | 7.233807 |
module ALU (
input wire [7:0] X,
input wire [7:0] Y,
input wire [2:0] operation,
output reg [7:0] out,
output reg carry_out
);
`include "alu_params.vh"
//calculate the logic operations
always @* begin
case (operation)
ALU_Y: begin
out = Y;
carry_out = 1'b0;
en... | 7.960621 |
module decoder (
input wire [15:0] opcode,
output wire [3:0] op_main,
output reg [3:0] op_sub,
output reg [3:0] x,
output reg [3:0] y,
output reg [11:0] nnn,
output reg [7:0] nn,
output reg [3:0] n,
output reg [2:0] alu_op,
output wire alu_switchxy //swap x and y if asserted
);
... | 7.018254 |
module chip8_ram (
input wire clk,
input wire [11:0] read_address,
input wire [7:0] d, //input data
input wire [11:0] write_address,
output reg [7:0] q, //output data
input wire we
);
reg [7:0] mem[0:4095];
initial begin
$readmemb("ram-chip8.txt", mem);
end
always @(posedge clk)... | 6.900907 |
module register_file (
input wire clk,
input wire reset,
input wire write_enable,
input wire [3:0] select_input,
input wire [7:0] input_data,
input wire [3:0] select_output1,
output wire [7:0] output1_data
);
//registers
reg [7:0] regs[15:0]; //V0..VF
integer i;
initial begin
... | 6.605344 |
module and2p_18_g (
y,
a,
b,
bb,
gnd_node
);
output y;
input a;
input b;
input bb;
input gnd_node;
reg y;
always @(a or b or bb or gnd_node) begin
if ((bb == 1'b1) && (b == 1'b0) && (gnd_node == 0)) y = 1'b0;
else if ((b == 1'b1) && (bb == 1'b0) && (gnd_node == 0)) y = a;
... | 6.576802 |
module anor21_18_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
assign Y = ~(C | (B * A));
endmodule
| 7.012558 |
module anor21_25 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(C | (B * A));
endmodule
| 7.251959 |
module anor21_25_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
assign Y = ~(C | (B * A));
endmodule
| 7.004077 |
module anor21_33 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(C | (B * A));
endmodule
| 7.02011 |
module anor21_33_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C or gnd_node) assign Y = ~(C | (B * A));
endmodule
| 6.575641 |
module anor21_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C or gnd_node) assign Y = ~(C | (B * A));
endmodule
| 6.575116 |
module anor21_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C) assign Y = ~(C | (B * A));
endmodule
| 6.919113 |
module anor21_hvt_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or C or gnd_node) assign Y = ~(C | (B * A));
endmodule
| 6.533019 |
module exor2_18 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 7.698422 |
module exor2_18_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
assign Y = (A & !B) | (!A & B);
endmodule
| 7.689026 |
module exor2_25 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.63069 |
module exor2_25_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.046077 |
module exor2_33 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 7.654382 |
module exor2_33_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
assign Y = (A & !B) | (!A & B);
endmodule
| 7.750721 |
module exor2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.22059 |
module exor2_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node) assign Y = (A & !B) | (!A & B);
endmodule
| 7.718141 |
module exor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = (A & !B) | (!A & B);
endmodule
| 9.259946 |
module exor2_hvt_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
assign Y = (A & !B) | (!A & B);
endmodule
| 8.545894 |
module inv_18 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.139984 |
module inv_18_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.154152 |
module inv_25 (Y, A);
output Y;
input A;
*/
module inv_25 ( OUT, G, Gb, IN, P, Pb );
output OUT;
input G, Gb, IN, P, Pb;
assign OUT = !IN;
endmodule
| 7.99951 |
module inv_25_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.78678 |
module inv_25_hv (
out,
in,
vhi
);
output out;
input in;
input vhi;
assign out = ~in;
endmodule
| 8.012627 |
module inv_33 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.176543 |
module inv_33_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.220746 |
module inv_33_hv (
out,
in,
vhi
);
output out;
input in;
input vhi;
assign out = ~in;
endmodule
| 7.597145 |
module inv (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.1601 |
module inv_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.514169 |
module inv_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.281121 |
module inv_hvt_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.56117 |
module inv_tri_2_25 (
Y,
A,
T,
Tb
);
output Y;
input A;
input T;
input Tb;
reg Y;
always @(A or T or Tb) begin
if ((T == 1) && (Tb == 0)) Y = !A;
else Y = 1'bz;
end
endmodule
| 7.094936 |
module inv_tri_2_25_g (
Y,
A,
T,
Tb,
gnd_node
);
output Y;
input A;
input T;
input Tb;
input gnd_node;
reg Y;
always @(A or T or Tb or gnd_node) begin
if ((T == 1) && (Tb == 0) && (gnd_node == 0)) Y = !A;
else Y = 1'bz;
end
endmodule
| 6.722643 |
module inv_tri_2_33 (
Y,
A,
T,
Tb
);
output Y;
input A;
input T;
input Tb;
reg Y;
always @(A or T or Tb) begin
if ((T == 1) && (Tb == 0)) Y = !A;
else Y = 1'bz;
end
endmodule
| 6.6963 |
module inv_w_pd_18 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 6.93581 |
module inv_w_pd_18_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.1415 |
module inv_w_pd_25 (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 8.364532 |
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