code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cdc_mcp #(
parameter SIZE = 1,
TPD = 0.5
) (
input wire a_rst,
a_clk,
input wire [SIZE-1:0] a_data,
input wire a_data_rdy,
input wire b_rst,
b_clk,
output reg [SIZE-1:0] b_data,
output reg b_data_ack
);
reg a_rdy;
wire... | 7.333609 |
module CDC_path (
input wire i_signal,
input wire i_clk1,
input wire i_clk2,
output wire o_signal_reg_clk1,
output wire o_signal
);
reg r_tmp0, r_tmp1, r_tmp2, r_tmp3;
always @(posedge i_clk1) begin
r_tmp0 <= i_signal;
end
always @(posedge i_clk2) begin
r_tmp1 <= r_tmp0;
r_... | 7.360635 |
module cdc_pulse (
input clk_a,
input data_a,
input clk_b,
output data_b
);
reg toggle_a = 0;
reg [2:0] sync_b = 0;
always @(posedge clk_a) toggle_a <= toggle_a ^ data_a;
always @(posedge clk_b) sync_b <= {sync_b[1:0], toggle_a};
assign data_b = (sync_b[2] ^ sync_b[1]);
endmodule
| 7.3413 |
module CDC_rdCtrl (
// input ports
clk,
rst,
rdPtr_gray,
wrPtr_gray,
nextrdPtr_gray,
readyForOut,
// output ports
infoOutValid,
fifoRe
);
parameter ADDR_WIDTH = 3;
// input ports
input clk;
wire clk;
input rst;
wire rst;
input [ADDR_WIDTH - 1:0] rdPtr_gray;
w... | 7.277956 |
module cdc_reg #(
parameter WIDTH = 128
) (
input wr_clk,
input [WIDTH-1:0] din,
input wr_en,
output reg full = 0,
input rd_clk,
output reg [WIDTH-1:0] dout = {WIDTH{1'b0}},
input rd_en,
output empty
);
always @(posedge wr_clk) begin
if (~full) begin
if (wr_en) begin
... | 8.593815 |
module cdc_reset (
input wire reset,
input wire clk_dst,
output wire dst_reset
); // module cdc_reset
xpm_cdc_async_rst #(
.DEST_SYNC_FF (4), // integer; range: 2-10
.RST_ACTIVE_HIGH(1), // integer; 0=Active Low Input, 1=Active High Input
.INIT_SYNC_FF (0) // integer; 0=Defa... | 7.160972 |
module cdc_synchronizer #(
parameter DATA_WIDTH = 8
) (
input clk_in,
input clk_out,
input [(DATA_WIDTH-1):0] data_in,
output [(DATA_WIDTH-1):0] data_out,
input reset_in
);
reg [(DATA_WIDTH-1):0] data_in_reg;
reg [(DATA_WIDTH-1):0... | 7.633914 |
module cdc_sync_strobe #(
parameter SIZE = 1
) (
input wire [SIZE-1:0] siga,
input wire rstb,
clkb,
strobe,
output reg [SIZE-1:0] sigb
);
reg [SIZE-1:0] q1;
always @(posedge clkb) begin
if (rstb) {sigb, q1} <= 2'b00;
else if (strobe) {sigb, q1} <= {q1, siga};
end
e... | 7.25407 |
module CDC_test;
reg clk;
reg [7:0] in;
CDC #(
.LENGTH(5),
.WIDTH (8)
) shiftregister (
.clk(clk),
.in (in)
);
initial begin
clk = 0;
in = 0;
#60 in = 4;
#20 in = 0;
#130 in = 7;
#20 in = 0;
end
always #25 clk = ~clk;
endmodule
| 6.640819 |
module CDC_wrCtrl (
// input ports
clk,
rst,
rdPtr_gray,
wrPtr_gray,
nextwrPtr_gray,
infoInValid,
// output ports
fifoWe,
readyForInfo
);
parameter ADDR_WIDTH = 3;
// input ports
input clk;
wire clk;
input rst;
wire rst;
input [ADDR_WIDTH - 1:0] rdPtr_gray;
w... | 6.906195 |
module cdd (
clock,
reset,
data,
out0,
out1,
out2,
out3,
out4,
out5,
ledr
);
// inputs
input clock;
input reset;
input [3:0] data;
// outputs
output reg [3:0] out0;
output reg [3:0] out1;
output reg [3:0] out2;
output reg [3:0] out3;
output reg [3:0] out4;
... | 6.533367 |
module cdda (
input CLK,
input nRESET,
input READ,
input WRITE,
input [15:0] DIN,
output WRITE_READY,
output reg [15:0] AUDIO_L,
output reg [15:0] AUDIO_R
);
localparam SECTOR_SIZE = 2352 * 8 / 32;
localparam BUFFER_AM... | 7.269455 |
module lbc_mux (
OUT,
SEL,
LEG0,
LEG1
);
input SEL;
input LEG0;
input LEG1;
output OUT;
assign OUT = SEL ? LEG1 : LEG0;
endmodule
| 7.297727 |
module CDEST (
input [31:0] ir,
output reg [4:0] ws,
output reg we
);
always @* begin
case (ir[31:26]) // rtype
6'b000000: begin
case (ir[5:0])
// jal jalr
6'b000011, 6'b001001: begin
ws = 5'd31;
end
default: ws = ir[15:11... | 6.502534 |
module cde_asyncdisable #(
parameter WIDTH = 1
) (
input wire reset,
input wire reset_n,
input wire atg_asyncdisable,
input wire [WIDTH - 1:0] sync_reset,
output wire [WIDTH - 1:0] reset_n_out,
output wire [WIDTH - 1:0] reset_out
);
assign reset_... | 8.549481 |
module cde_clk_diff_testmux (
input wire sel,
input wire clk_0,
input wire clk_1,
output wire clk_out,
output wire clk_out_n
);
assign clk_out = (clk_1 && sel) || (clk_0 && (!sel)) || (clk_1 && clk_0);
assign clk_out_n = (clk_1 && sel) || (!clk_0 && (!sel)) || (clk_1 && !clk_0);
endmod... | 7.005617 |
module cde_clk_gater (
input wire clk_in,
input wire enable,
input wire atg_clk_mode,
output wire clk_out
);
wire latch_enable;
reg latch_output;
assign latch_enable = enable | atg_clk_mode;
always @(latch_enable or clk_in) begin
if (~clk_in) latch_output = latch_enable;
else lat... | 6.69229 |
module cde_clk_testmux (
input wire sel,
input wire clk_0,
input wire clk_1,
output wire clk_out
);
assign clk_out = (clk_1 && sel) || (clk_0 && (!sel)) || (clk_1 && clk_0);
endmodule
| 6.837396 |
module cde_clock_sys #(
parameter FREQ = 48,
parameter MULT = 4
) (
input wire a_clk_pad_in,
input wire b_clk_pad_in,
input wire pwron_pad_in,
output wire ckOut,
output wire ckDivOut,
output reg one_usec,
output reg reset
);
reg [3:0] reset_cnt;
reg [6:0] counter;
alway... | 7.880461 |
module cde_divider #(
parameter SIZE = 4,
parameter SAMPLE = 0,
parameter RESET = 1
) (
input wire clk,
input wire reset,
input wire enable,
input wire [SIZE-1:0] divider_in,
output reg divider_out
);
reg [SIZE-1:0] divide_cnt;
al... | 7.74737 |
module cde_jtag_rpc_reg #(
parameter BITS = 16, // number of bits in the register (2 or more)
parameter RESET_VALUE = 'h0 // reset value of register
) (
input wire clk, // clock input
input wire reset, // async reset
input wire tdi, // scan-in of jtag_register
... | 7.738727 |
module cde_lifo #(
parameter WIDTH = 8,
parameter SIZE = 2, // DEPTH = 2 ^ SIZE
parameter WORDS = 4
) (
input wire clk,
input wire reset,
input wire push,
input wire [WIDTH-1:0] din,
input wire pop,
output wire [WIDTH-1:0] dout
... | 8.289491 |
module cde_pad_in_dig #(
parameter WIDTH = 1
) (
input wire [WIDTH-1:0] PAD,
output wire [WIDTH-1:0] pad_in
);
assign pad_in = PAD;
endmodule
| 7.793163 |
module cde_pad_out_dig #(
parameter WIDTH = 1
) (
output wire [WIDTH-1:0] PAD,
input wire [WIDTH-1:0] pad_out
);
assign PAD = pad_out;
endmodule
| 9.210571 |
module cde_pad_se_dig (
inout wire PAD,
output wire pad_in,
input wire pad_out,
input wire pad_oe
);
assign pad_in = PAD;
assign PAD = pad_oe ? pad_out : 1'bz;
endmodule
| 7.28641 |
module cde_pad_tri_dig (
inout wire PAD,
input wire pad_out,
input wire pad_oe
);
assign PAD = pad_oe ? pad_out : 1'bz;
endmodule
| 7.974425 |
module cde_prescale #(
parameter PRESCALE = 5'b01100,
parameter PRE_SIZE = 5
) (
input wire clk,
input wire reset,
output reg prescale_out
);
reg [PRE_SIZE-1:0] prescale_cnt;
always @(posedge clk)
if (reset) prescale_out <= 1'b1;
else prescale_out <= !(|prescale_cnt);
always @(... | 7.576814 |
module cde_reset #(
parameter WIDTH = 1, // width of reset bus
parameter DEPTH = 1 // depth of synchronizer
) (
input clk,
input async_reset_n,
input atg_asyncdisable,
input [WIDTH - 1:0] sync_reset, // signals to control resets
output [W... | 8.204287 |
module cde_sram #(
parameter ADDR = 10, // Bits in addr
parameter WIDTH = 8, // Bits in data
parameter WORDS = 1024, // Number of words
parameter WRITETHRU = 0, // 0 reads old data on same read/write, 1 reads new data
parameter DEFAULT =... | 7.753275 |
module cde_sram_be #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
input wire be,
input wire [ ADDR-1 : 0] addr,
i... | 7.353037 |
module cde_sram_def #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
... | 7.771816 |
module cde_sram_dp #(
parameter ADDR = 10,
WIDTH = 8,
WORDS = 1024,
WRITETHRU = 0,
DEFAULT = {WIDTH{1'b1}},
INIT_FILE = "NONE",
INSTANCE_NAME = "U1"
) (
input wire clk,
input wire cs,
input wire rd,
input wire wr,
... | 7.053007 |
module cde_sync #(
parameter WIDTH = 1,
parameter DEPTH = 2
) (
input wire clk,
input wire [WIDTH - 1:0] data_in,
output wire [WIDTH - 1:0] data_out
);
reg [WIDTH - 1:0] sync_data[DEPTH:0];
always @(*) begin
sync_data[0] = data_in;
end
integer i;
always @(pose... | 7.127679 |
module cde_sync_with_hysteresis #(
parameter WIDTH = 1,
parameter DEBOUNCE = 4,
parameter DEBOUNCE_DELAY = 4'b1111
) (
input wire clk,
input wire reset,
input wire [WIDTH - 1:0] data_in,
output reg [WIDTH - 1:0] data_out,
output reg [WIDTH - 1:0] data_rise,
output... | 7.756212 |
module cde_sync_with_reset #(
parameter WIDTH = 1,
parameter DEPTH = 2,
parameter RST_VAL = 1'b0
) (
input wire clk,
input wire reset_n,
input wire [WIDTH - 1:0] data_in,
output wire [WIDTH - 1:0] data_out
);
reg [WIDTH - 1:0] sync_data[DEPTH:0];
always @(*) begin
sync_d... | 7.756212 |
module cdiv (
input clkin,
input rst_n,
input enable,
output clkout
);
parameter DIVBY = 16'd20;
reg [15:0] count;
always @(posedge clkin or negedge rst_n) begin
if (!rst_n) count <= 0;
else begin
if (enable) begin
if (count < DIVBY - 1) count <= count + 1;
else ... | 7.777703 |
module cdpga_bx (
input clk_i,
output clk_o,
input rx,
output tx,
output reg tx_en
);
assign clk_o = ~clk_i;
wire clk_tmp = clk_o;
wire clk;
wire reset_n;
reg rst_sim = 0;
always @(posedge clk_tmp) rst_sim = 1;
cdpga_pll b2v_pll_m (
.REFERENCECLK(clk_tmp),
.... | 7.818374 |
module cdpga_h (
input clk,
output reg [20:0] out
);
reg rst_n = 0;
reg [2:0] reset_cnt = 0;
always @(posedge clk) begin
reset_cnt <= reset_cnt + 1;
if (reset_cnt == 3'b111) rst_n <= 1;
end
reg [20:0] counter;
//reg [4:0] counter;
always @(posedge clk or negedge rst_n)
if (!rst_n) ... | 6.911734 |
module cdpga_bx_tb;
reg clk;
reg rx;
wire tx;
wire tx_en;
initial begin
clk = 0;
rx = 0;
end
always #(`cycle / 2.0) clk = ~clk;
initial begin
rx = 1;
#20000;
$display($time, " tx: %b, tx_en: %b", tx, tx_en);
rx = 0;
#20000;
rx = 1;
$display($time, " tx: %b, ... | 7.79305 |
module cdq_rx_fifo_512x36 (
clk,
din,
rd_en,
rst,
wr_en,
almost_full,
dout,
empty,
full,
prog_full
);
input clk;
input [35 : 0] din;
input rd_en;
input rst;
input wr_en;
output almost_full;
output [35 : 0] dout;
output empty;
output full;
output prog_full;
... | 6.866393 |
module cdq_rx_fifo_512x36_to_72 (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
almost_full,
dout,
empty,
full,
prog_full
);
input [35 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output almost_full;
output [71 : 0] dout;
output emp... | 6.866393 |
module cdr (
input real d,
input wire clk0,
clk90,
clk180,
clk270,
input wire rst,
output wire clk,
clkb
);
wire e, l;
wire dclk, eclk;
wire clk_cont;
wire [1:0] ea, la;
wire comp, equal;
wire up, down;
reg [5:0] vs;
assign dclk = clk;
assign eclk = clkb;
pd pd1... | 7.131012 |
module cdrom_ctrl_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8
, parameter DEPTH = 4
, parameter ADDR_W = 2
)
//---------------------------------------------------------------... | 7.240802 |
module cdrom_data_fifo (
// Inputs
input clk_i
, input rst_i
, input [31:0] data_in_i
, input push_i
, input pop_i
, input flush_i
// Outputs
, output [31:0] data_out_o
, output accept_o
, output valid_o
);
//------------... | 6.949796 |
module cdrom_data_fifo_ram_dp_2048_10 (
// Inputs
input clk0_i
, input rst0_i
, input [ 9:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 9:0] addr1_i
, input [31:0] data1_i
, input wr1_i
... | 6.949796 |
module cds_alias (
out,
in
);
input in;
output out;
assign in = out;
endmodule
| 7.063869 |
module: cds_clk_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cds_clk_generator_tb;
// Inputs
reg clk;
reg reset;
reg trigger;
reg [0:15] cds_delay1;
reg [0:15] cd... | 7.418978 |
module: cds_strobe_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cds_strobe_generator_tb;
// Inputs
reg clk;
reg reset;
reg trigger;
reg [0:15] cds_delay1;
reg [0:... | 7.28179 |
module cdu_sim(
input wire clk,
input wire rst_n,
input wire real shaft_angle,
output wire real ATPCA,
output wire real cdux
);
`define M_PI 3.14159265359
localparam SIM_HZ = 23'd5120000;
wire real shaft_angle_rad;
assign shaft_angle_rad = shaft_angle * `M_PI / 180;
/*--------------------------... | 7.390497 |
module cd_rx_ram #(
parameter N_WIDTH = 3
) (
input clk,
input reset_n,
output [7:0] rd_byte,
input [7:0] rd_addr,
input rd_en,
input rd_done,
input rd_done_all,
output unread,
input [7:0] wr_byte,
input [7:0] wr_addr,
input wr_en,
... | 8.054958 |
module cd_sdpram #(
parameter A_WIDTH = 8,
parameter D_WIDTH = 8
) (
input clk,
input cen, // chip enable, active low
input [A_WIDTH-1:0] ra, // read addr
output reg [D_WIDTH-1:0] rd, // read data
input [A_WIDTH-1:0] wa, // write addr
input [D_WIDTH-1:0] wd, // write data
... | 8.433471 |
module cd_spram #(
parameter A_WIDTH = 8,
parameter D_WIDTH = 8
) (
input clk,
input cen, // chip enable, active low
input [A_WIDTH-1:0] addr, // address
output reg [D_WIDTH-1:0] rd, // read data
input [D_WIDTH-1:0] wd, // write data
input wen // write enable, activ... | 8.289242 |
module cd_tx_ram (
input clk,
input reset_n,
output [7:0] rd_byte,
input [7:0] rd_addr,
input rd_en,
input rd_done,
output unread,
input [7:0] wr_byte,
input [7:0] wr_addr,
input wr_en,
input switch
);
wire [7:0] rd_bytes[1:0];
wire [7:0] rw... | 6.995391 |
module dec38_case (
Q,
D
);
input [7:0] Q;
output [2:0] D;
reg [2:0] D;
always @(Q)
case (Q)
8'b00000000: D = 3'b000;
8'b00000001: D = 3'b001;
8'b00000010: D = 3'b010;
8'b00000100: D = 3'b011;
8'b00001000: D = 3'b100;
8'b00010000: D = 3'b101;
8'b00100000: D... | 8.043647 |
module has a latency of 7 clocks
module dq (clk, q, d);
input clk;
input [width-1:0] d;
output [width-1:0] q;
parameter width=8;
parameter depth=2;
integer i;
reg [width-1:0] delay_line [depth-1:0];
always @(posedge clk) begin
delay_line[0] <= d;
for(i=1; i<depth; i=i+1) begin
delay_line... | 6.771891 |
module ceiling #(
parameter DSIZE = 16,
parameter CSIZE = 4, //must smaller than DSIZE
parameter OSIZE = 8, //must not bigger than DSIZE-CSIZE
parameter SEQUENTIAL = "TRUE"
) (
input clock ,
input [DSIZE-1:0] indata ,
output[OSIZE-1:0] outdata
);
reg [OSIZE-1... | 7.716837 |
module ceiling_A1 #(
parameter DSIZE = 16,
parameter CSIZE = 4, //must smaller than DSIZE
parameter OSIZE = 8, //must not bigger than DSIZE-CSIZE
parameter SEQUENTIAL = "TRUE"
) (
input clock,
input rst_n,
input [DSIZE-1:0] indata,
outp... | 7.871061 |
module ceil_tb;
reg clk;
reg [31:0] ceil_a;
wire [31:0] ceil_z;
integer ceil_a_file;
integer ceil_z_file;
integer ceil_a_count;
integer ceil_z_count;
ceil ceil1 (
clk,
ceil_a,
ceil_z
);
initial begin
ceil_z_file = $fopen("stim/ceil_z");
ceil_a_file = $fopen("stim/ceil_a", ... | 6.781111 |
module u_AND2 (
input IN1,
input IN2,
output OUT
);
assign OUT = IN1 & IN2;
endmodule
| 8.549923 |
module u_AND3 (
input IN1,
input IN2,
input IN3,
output OUT
);
assign OUT = IN1 & IN2 & IN3;
endmodule
| 8.03339 |
module u_AND4 (
input IN1,
input IN2,
input IN3,
input IN4,
output OUT
);
assign OUT = IN1 & IN2 & IN3 & IN4;
endmodule
| 8.12467 |
module u_AND5 (
input IN1,
input IN2,
input IN3,
input IN4,
input IN5,
output OUT
);
assign OUT = IN1 & IN2 & IN3 & IN4 & IN5;
endmodule
| 7.505561 |
module XOR2 (
input IN1,
input IN2,
output OUT
);
assign OUT = ((~IN1) & IN2) | ((~IN2) & IN1);
endmodule
| 8.083658 |
module u_OR2 (
input IN1,
input IN2,
output OUT
);
assign OUT = IN1 | IN2;
endmodule
| 8.401235 |
module u_OR3 (
input IN1,
input IN2,
input IN3,
output OUT
);
assign OUT = IN1 | IN2 | IN3;
endmodule
| 8.057852 |
module u_OR4 (
input IN1,
input IN2,
input IN3,
input IN4,
output OUT
);
assign OUT = IN1 | IN2 | IN3 | IN4;
endmodule
| 7.801728 |
module u_OR5 (
input IN1,
input IN2,
input IN3,
input IN4,
input IN5,
output OUT
);
assign OUT = IN1 | IN2 | IN3 | IN4 | IN5;
endmodule
| 7.345129 |
module cellcalc_testbench ();
parameter common_factor = 1;
reg [130*common_factor-1:0] matrix_A, matrix_B;
reg a_stb, b_stb, a_ack, b_ack, z_ack, load_fp, load_2by2, result_ack, result_ack_2by2;
wire z_stb2, result_ready, result_ready_2by;
reg reset, clk;
reg [$clog2(common_factor)-1:0] select_matrix;
re... | 6.742845 |
module ConfMux (
input [2:0] io_selector,
input [5:0] io_mux_input,
output io_mux_output
);
wire inputs_0 = io_mux_input[0]; // @[ConfMux.scala 32:34]
wire inputs_1 = io_mux_input[1]; // @[ConfMux.scala 32:34]
wire inputs_2 = io_mux_input[2]; // @[ConfMux.scala 32:34]
wire inputs_3 = io_m... | 6.758398 |
module FR (
input [5:0] io_valid_in,
input [3:0] io_ready_out,
input [2:0] io_valid_mux_sel,
input [3:0] io_fork_mask,
output io_valid_out
);
wire [2:0] conf_mux_io_selector; // @[FR.scala 34:28]
wire [5:0] conf_mux_io_mux_input; // @[FR.scala 34:28]
wire conf_mux_io_mux_output; /... | 6.581084 |
module ConfMux_1 (
input [ 2:0] io_selector,
input [191:0] io_mux_input,
output [ 31:0] io_mux_output
);
wire [31:0] inputs_0 = io_mux_input[31:0]; // @[ConfMux.scala 32:34]
wire [31:0] inputs_1 = io_mux_input[63:32]; // @[ConfMux.scala 32:34]
wire [31:0] inputs_2 = io_mux_input[95:64]; // @[Con... | 6.725717 |
module RegEnable (
input clock,
input reset,
input [31:0] io_in,
input io_en,
output [31:0] io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [31:0] reg_; // @[RegEnable.scala 21:22]
assign io_out = reg_; // @[RegEnable.scala 2... | 6.779288 |
module RegEnable_2 (
input clock,
input reset,
input io_in,
input io_en,
output io_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[RegEnable.scala 21:22]
assign io_out = reg_; // @[RegEnable.scala 25:12]
always @(posedge clock) begin
... | 6.543778 |
module Join (
input [31:0] io_din_1,
input [31:0] io_din_2,
input io_dout_r,
input io_din_1_v,
input io_din_2_v,
output io_dout_v,
output io_din_1_r,
output io_din_2_r,
output [31:0] io_dout_1,
output [31:0] io_dout_2
);
assign io_... | 8.012501 |
module ALU (
input [31:0] io_din_1,
input [31:0] io_din_2,
input [ 3:0] io_op_config,
output [31:0] io_dout
);
wire [31:0] _io_dout_T_1 = io_din_1 + io_din_2; // @[ALU.scala 41:27]
wire [63:0] _io_dout_T_2 = io_din_1 * io_din_2; // @[ALU.scala 44:27]
wire [31:0] _io_dout_T_4 = io_din_1 - io_d... | 7.960621 |
module FS (
input [4:0] io_ready_out,
input [4:0] io_fork_mask,
output io_ready_in
);
wire aux_0 = ~io_fork_mask[0] | io_ready_out[0]; // @[FS.scala 28:39]
wire aux_1 = ~io_fork_mask[1] | io_ready_out[1]; // @[FS.scala 28:39]
wire aux_2 = ~io_fork_mask[2] | io_ready_out[2]; // @[FS.scala 28... | 7.689649 |
module and_cell (
input wire a,
input wire b,
output wire out
);
assign out = a & b;
endmodule
| 7.394401 |
module or_cell (
input wire a,
input wire b,
output wire out
);
assign out = a | b;
endmodule
| 8.088887 |
module xor_cell (
input wire a,
input wire b,
output wire out
);
assign out = a ^ b;
endmodule
| 8.443119 |
module nand_cell (
input wire a,
input wire b,
output wire out
);
assign out = !(a & b);
endmodule
| 6.987323 |
module not_cell (
input wire in,
output wire out
);
assign out = !in;
endmodule
| 7.521089 |
module mux_cell (
input wire a,
input wire b,
input wire sel,
output wire out
);
assign out = sel ? a : b;
endmodule
| 9.047946 |
module dff_cell (
input wire clk,
input wire d,
output reg q,
output wire notq
);
assign notq = !q;
always @(posedge clk) q <= d;
endmodule
| 6.814341 |
module _80_altera_max10_alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downt... | 6.766117 |
module JTAGG (
input TCK,
TMS,
TDI,
JTDO2,
JTDO1,
output TDO,
JTDI,
JTCK,
JRTI2,
JRTI1,
output JSHIFT,
JUPDATE,
JRSTN,
JCE2,
JCE1
);
parameter ER1 = "ENABLED";
parameter ER2 = "ENABLED";
endmodule
| 6.718338 |
module DELAYF (
input A,
LOADN,
MOVE,
DIRECTION,
output Z,
CFLAG
);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
endmodule
| 7.003421 |
module DELAYG (
input A,
output Z
);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
endmodule
| 7.027102 |
module DDRDLLA (
input CLK,
RST,
UDDCNTLN,
FREEZE,
output LOCK,
DDRDEL,
DCNTL7,
DCNTL6,
DCNTL5,
DCNTL4,
DCNTL3,
DCNTL2,
DCNTL1,
DCNTL0
);
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
endmodule
| 6.660684 |
module EXTREFB (
input REFCLKP,
REFCLKN,
output REFCLKO
);
parameter REFCK_PWDNB = "0b0";
parameter REFCK_RTERM = "0b0";
parameter REFCK_DCBIAS_EN = "0b0";
endmodule
| 6.736889 |
module \$__COUNT_ (
CE,
CLK,
OUT,
POUT,
RST,
UP
);
input wire CE;
input wire CLK;
output reg OUT;
output reg [WIDTH-1:0] POUT;
input wire RST;
input wire UP;
parameter COUNT_TO = 1;
parameter RESET_MODE = "RISING";
parameter RESET_TO_MAX = "1";
parameter HAS_POUT = 0;
par... | 7.532662 |
module adder_carry (
output wire sumout,
output wire cout,
input wire p,
input wire g,
input wire cin
);
assign sumout = p ^ cin;
assign cout = p ? cin : g;
specify
(p => sumout) = 0;
(g => sumout) = 0;
(cin => sumout) = 0;
(p => cout) = 0;
(g => cout) = 0;
(cin =... | 6.785774 |
module dff (
output reg Q,
input wire D, (* clkbuf_sink *)
input wire C
);
initial Q <= 1'b0;
always @(posedge C) Q <= D;
specify
(posedge C => (Q +: D)) = 0;
$setuphold(posedge C, D, 0, 0);
endspecify
endmodule
| 7.02102 |
module dffnsre (
output reg Q,
input wire D, (* clkbuf_sink *)
input wire C,
input wire E,
input wire R,
input wire S
);
initial Q <= 1'b0;
always @(negedge C or negedge S or negedge R)
if (!R) Q <= 1'b0;
else if (!S) Q <= 1'b1;
else if (E) Q <= D;
specify
(negedge ... | 6.825573 |
module sdffnsre (
output reg Q,
input wire D, (* clkbuf_sink *)
input wire C,
input wire E,
input wire R,
input wire S
);
initial Q <= 1'b0;
always @(negedge C)
if (!R) Q <= 1'b0;
else if (!S) Q <= 1'b1;
else if (E) Q <= D;
specify
(negedge C => (Q +: D)) = 0;
$... | 6.599271 |
module latchnsre (
output reg Q,
input wire S,
input wire R,
input wire D,
input wire G,
input wire E
);
initial Q <= 1'b0;
always @* begin
if (!R) Q <= 1'b0;
else if (!S) Q <= 1'b1;
else if (E && !G) Q <= D;
end
specify
(negedge G => (Q +: D)) = 0;
$setuphold... | 7.275808 |
module GP_ABUF (
input wire IN,
output wire OUT
);
assign OUT = IN;
//must be 1, 5, 20, 50
//values >1 only available with Vdd > 2.7V
parameter BANDWIDTH_KHZ = 1;
endmodule
| 7.801987 |
module GP_ACMP (
input wire PWREN,
input wire VIN,
input wire VREF,
output reg OUT
);
parameter BANDWIDTH = "HIGH";
parameter VIN_ATTEN = 1;
parameter VIN_ISRC_EN = 0;
parameter HYSTERESIS = 0;
initial OUT = 0;
endmodule
| 7.422397 |
module GP_DAC (
input [7:0] DIN,
input wire VREF,
output reg VOUT
);
initial VOUT = 0;
//analog hard IP is not supported for simulation
endmodule
| 7.690069 |
module GP_LFOSC (
input PWRDN,
output reg CLKOUT
);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;
initial CLKOUT = 0;
//auto powerdown not implemented for simulation
//output dividers not implemented for simulation
always begin
if (PWRDN) CLKOUT = 0;
else beg... | 7.875874 |
module GP_2LUT (
input IN0,
IN1,
output OUT
);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule
| 7.219006 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.