code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module for HPSDR MERCURY/QS1R Project
Copyright (C) 2007 Philip A. Covington, N8VB
The author can be reached at:
p.covington@gmail.com
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either... | 7.028669 |
module cbya32bit (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output cout,
output overflow
);
wire [4:0] c;
assign c[0] = 1'b0;
assign cout = c[4];
assign overflow = (a[31] ^ r[31]) & (b[31] ^ r[31]);
genvar i;
generate
for (i = 3; i >= 0; i = i - 1)
cbya8bit block (
... | 6.535772 |
module cbya8bit (
input [7:0] a,
input [7:0] b,
output [7:0] r,
input cin,
output cout
);
wire [7:0] p;
wire [8:0] c;
wire BP;
assign c[0] = cin;
// Pi=Ai^Bi (Propagate)
assign p = a ^ b; // bitwise xor all bits of A and B
assign BP = &p; // bitwise and all bits of P
assign cout = ... | 7.279603 |
module cc (
input dclk,
output dv,
output reg [15:0] data = 0
);
reg [31:0] counter = 0;
reg valid = 0;
reg [15:0] data_count = 0;
always @(posedge dclk) begin
counter <= counter + 1;
data_count <= data_count + 1;
if (counter < 16384) begin
valid <= 1;
data <= data_count;
... | 6.698317 |
module cc3200_test_model (
//input
input clk_in,
input reset_n,
input RX_Gate,
input Envelop,
//output
output reg [7:0] line_num,
output [1:0] focus_num
);
//wire
//reg
reg [5:0] clk_cnt;
reg clk_10M;
reg envelop_reg;
reg [1:0] Focus_Num... | 6.650359 |
module has been tested in the MachXO2-7000HE breakout board
* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
* Distributed under the terms of the Lesser GPL
*
* Implemented using diamond 2.1
*/
module CC3_top(
input wire clk40_i,
/* CPU Bus */
output wire cpuclk_o,
output wire reset_o,
output wire [18:0] ... | 7.824628 |
module CC3_top_x (
input clk32_i,
output mem_we_n,
output mem_oe_n,
output [15:0] mem_addr_o,
inout [7:0] mem_data_io
);
wire cpu_clk;
wire cpu_reset_n;
wire cpu_nmi_n;
wire cpu_irq_n;
wire cpu_firq_n;
wire cpu_state_o;
wire cpu_we_o;
wire cpu_oe_o;
wire [15:0] cpu_addr_o;
wire ... | 7.39145 |
module cc561 #(
parameter DW = 0
) (
input aclk,
input arst,
input [DW-1:0] adata,
input aen,
input bclk,
output reg [DW-1:0] bdata,
output reg ben
);
reg [DW-1:0] adata_r;
reg aen_r = 1'b0;
wire ... | 7.301417 |
module ccb_lock
(
clock,
lock,
reset,
lock_never,
lost_ever,
lost_cnt
`ifdef DEBUG_CCB_LOCK , lock_sm_dsp `endif
);
// Ports
input clock; // TMB main 40MHz clock
input lock; // Lock signal from TTC
input reset; // Reset FFs and counter
output lock_never; // Lock... | 7.261185 |
module ccc1 (
// Inputs
RCOSC_25_50MHZ,
// Outputs
GL0,
LOCK
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input RCOSC_25_50MHZ;
//--------------------------------------------------... | 7.09354 |
module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ccccc;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
co... | 7.040838 |
module parallel_clark #(
parameter N = 32,
parameter Q = 18
) (
input signed [N-1:0] ialpha,
ibeta,
output signed [N-1:0] ia,
ib,
ic
);
//Q17 format for parameters
localparam [17:0] a = 0.5; // 0.5
localparam [17:0] b = 18'b011011101101100100; //sqrt3/2
assign ia = ialpha; //... | 6.942952 |
module ccc_slow (
POWERDOWN,
CLKA,
LOCK,
GLA,
SDIN,
SCLK,
SSHIFT,
SUPDATE,
MODE,
SDOUT
);
input POWERDOWN;
input CLKA;
output LOCK;
output GLA;
input SDIN;
input SCLK;
input SSHIFT;
input SUPDATE;
input MODE;
output SDOUT;
wire VCC, GND;
wire GND_power_ne... | 6.564712 |
module CCD_Capture (
oDATA,
oDVAL,
oX_Cont,
oY_Cont,
oFrame_Cont,
iDATA,
iFVAL,
iLVAL,
iSTART,
iEND,
iCLK,
iRST
);
input [11:0] iDATA;
input iFVAL;
input iLVAL;
input iSTART;
input iEND;
input iCLK;
input iRST;
output [11:0] oDATA;
output [15:0] oX_Cont... | 8.717881 |
module ccd_drive(
input clk,
input rst_n,
input key_in,
// TCD1304 signal
output reg M,
output reg ICG,
output reg SH,
// Module interface
output reg signal,
output reg [3:0] led
);
parameter N = 5'd25; // 50 devider
parameter P = 20'd1000000; // 50Hz = 50MHz / 1000000
parameter K = 20'... | 7.039167 |
module ccd_dsp2mb (
input [210:0] DIN,
input WRCLK,
input RDCLK,
output [210:0] DOUT,
output FIFULL
);
wire wr_en;
ccd_fifo ccd_fifo_dsp2mb (
.rst (1'b0), // input rst
.wr_clk(WRCLK), // input wr_clk
.rd_clk(RDCLK), // input rd_clk
.din (DIN), // input [210 :... | 6.723483 |
module CCD_FIFO (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrfull
);
input aclr;
input [29:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [29:0] q;
output [9:0] rdusedw;
output wrfull;
wire sub_wire0;
wire [29:0] sub_wire1;
wi... | 6.512085 |
module ccd_register (
input reset, // asynchronous active-high reset
input clk_in, // write clock
input we, // active-high write enable
input [7:0] din, // 8-bit data-in
output busy, // active-high buffer full
input clk_out, // read clock
input re, // active-high read enable
ou... | 7.204239 |
module CECS301_Lab1_tb ();
//inputs
reg clk_100MHz, rst, SI;
reg [1:0] M;
reg [3:0] D;
//outputs
wire [3:0] Q;
//Instantitate the Unit Under Test
shift_reg4 uut (
.clk(clk_100MHz),
.rst(rst),
.SI (SI),
.M (M),
.D (D),
.Q (Q)
);
//Generate clock with a 10 ... | 6.657404 |
module cceip_kernel_m00_axi_input_buffer_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_styl... | 7.128692 |
module cceip_kernel_m00_axi_input_buffer (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [... | 7.128692 |
module cceip_kernel_m00_axi_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire ... | 7.128692 |
module cceip_kernel_m00_axi_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg ... | 7.128692 |
module cceip_kernel_m00_axi_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
... | 7.128692 |
module cceip_kernel_m00_axi_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 7.128692 |
module ccfilt #(
parameter dw = 32, // data width of mon_chan output:
// should be CIC input data width (18),
// plus 2 * log2(max sample period)
parameter outw = 20, // output data width
// comments below assume outw == 20
// outw must be 20 if using half-band filter
parameter shift_wi = ... | 7.467979 |
module ccfilt_wrap (
input clk, // timespec 9.2 ns
// unprocessed double-integrator output
input sr_out,
input [35:0] sr_val,
// semi-static configuration
input [3:0] shift, // controls scaling of result
// filtered and scale result, ready for storage
output reg [35:0] result,
ou... | 6.80199 |
module ccir656_tb;
reg clk27M;
reg rst;
reg [6:0] imgbtn;
wire [7:0] data;
wire led;
ccir656 ccir656_0 (
.clk27M(clk27M),
.rst(rst),
.imgbtn(imgbtn),
.data(data),
.led(led)
);
initial begin
clk27M = 0;
rst = 1;
#1000 imgbtn = 7'b101_1101;
#10 rst = 0;
en... | 7.149149 |
module ccmul #(
parameter W2 = 17, // Multiplier bit width
W1 = 9, // Bit width c+s sum
W = 8
) // Input bit width
(
input clk, // Clock for the output register
input signed [W-1:0] x_in,
y_in,
c_in, // Inputs
input signed [W1-1:0] cps_in,
cms_in, // Inputs
output reg sig... | 6.557338 |
module both stores the condition codes set by the previous instructions
* and evaluates the code requested by the current instruction.
* @input instr is the current instruction in full. Based on which instruction
* type it is, this module will either update its condition codes or use them to
* output a value which can ... | 7.469244 |
module ccp_fsm (
input wire clk,
input wire rst
);
// Channel 1
wire [ `MSG_WIDTH - 1 : 0] msg1_type;
wire [`DATA_WIDTH - 1 : 0] msg1_data;
wire [ `TAG_WIDTH - 1 : 0] msg1_tag;
wire [`OWNER_BITS - 1 : 0] msg1_source;
// Channel 2
wire [ `MSG_WIDTH - 1 : 0] msg2_type;
wire [`DATA_WIDTH - 1 : 0]... | 6.984897 |
module ccp_ila (
input wire clk,
input wire rst
);
// Channel 1
wire [ `MSG_WIDTH - 1 : 0] msg1_type;
wire [`DATA_WIDTH - 1 : 0] msg1_data;
wire [ `TAG_WIDTH - 1 : 0] msg1_tag;
wire [`OWNER_BITS - 1 : 0] msg1_source;
// Channel 2
wire [ `MSG_WIDTH - 1 : 0] msg2_type;
wire [`DATA_WIDTH - 1 : 0]... | 6.776744 |
module register1b(clk, out, in, write, reset); // Negedge-triggered 1 bit flipflop register for with active-low write signal and reset
output reg out;
input in;
input clk, write, reset;
always@(negedge clk) begin
if(reset==0) begin
out = 1'b0;
else if(write == 1'b0) begin
out = in;
end
end
endmo... | 6.928857 |
module CCreg (
input clk,
input wire [2:0] cc,
input wire [2:0] W_stat,
m_stat,
output reg zf,
of,
sf
);
always @(*) begin
if (W_stat == `OK && m_stat == `OK) begin
zf = cc[0];
of = cc[1];
sf = cc[2];
end
end
always @(*) begin
if(cc[0]===1'bx) //三个等号 是... | 6.673413 |
module ccu_10 (
output wire dv, // Sign test pulse for E order (jump if Acc >= 0), output to Accumulator.
output wire ep5, // End Pulse for transfers.
output wire jump_uc,
output wire stop_one_b, // Suppress SCT increment during transfers.
input wire c10, // G order.
input wire c25, // E o... | 6.659057 |
module ccu_3 (
output wire ep2, // Terminates shifts.
output wire g5, // Accumulator shifting gate.
output wire reset_shift_ff, // Resets a flipflop in CCU 8.
input wire clk,
input wire zero_d0,
input wire c6, // R, L shift orders.
input wire dy, // Resetting pulse after addition of pa... | 7.381057 |
module ccu_4 (
output wire ep3, // End pulse for addition and subtraction.
output wire g6_pos, // Used in Multiplicand Tank for gating.
input wire clk,
input wire c1, // A, S, C, V, N orders (although only A, S, C used).
input wire ev_d0,
input wire odd_d0,
input wire g8, // Inhibits a... | 7.034706 |
module ccu_5 (
output wire ep0, // End pulse terminating roundoff orders.
output wire ones4, // Signal to CCU 6 to add 1 at the appropriate place to round off.
input wire clk,
input wire c9, // X, Y order.
input wire c12, // X order.
input wire c13, // Y order.
input wire d18,
inpu... | 7.404985 |
module ccu_6 (
output wire ep,
output wire ccu_ones,
input wire ep0,
input wire ep1,
input wire ep2,
input wire ep3,
input wire ep4,
input wire ep5,
input wire ep6,
input wire ep7,
input wire ep8,
input wire ep9,
input wire ep10,
input wire ep11,
input wire o... | 7.283043 |
module ccu_8 (
output wire ep1, // End pulse for multiplication operation.
output wire g4_pos, // Complementer gate.
output wire g4_neg,
output wire ones2, // Sign propagation.
input wire seventy_d35,
input wire c11, // N order - multiply and subtract.
input wire c14, // V order - mult... | 7.206613 |
module ccu_9_11 (
output wire ep6, // End Pulse for store and clear.
output wire ep7, // End Pulse for store and retain.
output wire g9_neg, // Accumulator clear gate.
output wire g10_neg, // Multiplier clear gate.
output wire g11_neg, // Multiplicand clear gate.
input wire c18, // H orde... | 6.66443 |
module ccx2mb (
// Outputs
pcx_spc_grant_px,
pcx_fsl_m_control,
pcx_fsl_m_data,
pcx_fsl_m_write,
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2,
cpx_fsl_s_read,
// Inputs
gclk,
reset_l,
spc_pcx_data_pa,
spc_pcx_atom_pq,
spc_pcx_req_pq,
fsl_pcx_m_full,
fsl_cp... | 9.246973 |
module
module cc_1(
input rst,
input start,
input [15:0] m0,
input [15:0] m1,
input clk,
output reg [9:0] index,
output reg done,
output testing
);
localparam Idle = 2'b00;
localparam ReadInputs = 2'b01;
localparam Busy = 2'b10;
localparam Done = 2'b11;
reg... | 7.982286 |
module CC_2B_1SKP_DATA_PATH
(
input CLK,
input [27:0] DATA_IN,
input [1:0] SEL_0,
input [1:0] SEL_1,
input RST,
output [27:0] DATA_OUT
);
// Reg declarations
reg [13:0] data_s0_0 = 14'h0000;
reg [13:0] data... | 6.555767 |
module CC_2B_1SKP_PATTERN_MATCH #(
// Define the byte to detect
parameter CC_CHAR = 8'h1c
) (
input [27:0] DATA_IN,
output reg [ 1:0] DATA_OUT
);
// Wires declaration
wire [7:0] match_char;
// Main body of the code
assign match_char = CC_CHAR;
always @(DATA_IN, match_char) begin
/... | 7.398805 |
module CC_ALU #(
parameter DATAWIDTH_BUS = 8,
parameter DATAWIDTH_ALU_SELECTION = 4
) (
//////////// OUTPUTS //////////
CC_ALU_Overflow_OutLow,
CC_ALU_Carry_OutLow,
CC_ALU_Negative_OutLow,
CC_ALU_Zero_OutLow,
CC_ALU_DataBUS_Out,
//////////// INPUTS //////////
CC_ALU_DataBUSA_In,
... | 8.686972 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/cc_comb/cc_comb.opt (
a_pad,
b0_pad,
b_pad,
c0_pad,
c_pad,
d0_pad,
d_pad,
e0_pad,
e_pad,
f_pad,
g_pad,
h0_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l_pad,
m_pad,
... | 6.939825 |
module CC_COMPARATOR_LEVEL (
CC_COMPARATOR_LEVEL_BusIn,
CC_COMPARATOR_LEVEL_OutBus
);
//=======================================================
// PARAMETER declarations
//=======================================================
input [7:0] CC_COMPARATOR_LEVEL_BusIn;
output reg [1:0] CC_COMPARATO... | 7.910646 |
module CC_COMPARATOR_LOSE (
CC_COMPARATOR_LOSE_BusJoined,
CC_COMPARATOR_LOSE_BusNorm,
CC_COMPARATOR_LOSE_loseout
);
//=======================================================
// PARAMETER declarations
//=======================================================
//==================================... | 7.910646 |
module CC_decoder (
CBCLK,
CLRCLK,
CC_IN,
PTT_out,
clock_select,
OC,
ATTEN,
TX_relay,
Rout,
RX_relay,
frequency_HZ,
ATTRLY,
RAND,
DITHER
);
parameter ADDRESS = 4'b0; // Address for data
input wire CBCLK;
input wire CLRCLK;
input wire CC_IN;
output reg... | 7.096039 |
module CC (
in_n0,
in_n1,
in_n2,
in_n3,
in_n4,
in_n5,
opt,
equ,
out_n
);
input [3:0] in_n0;
input [3:0] in_n1;
input [3:0] in_n2;
input [3:0] in_n3;
input [3:0] in_n4;
input [3:0] in_n5;
input [2:0] opt;
input equ;
output [9:0] out_n;
//===========================... | 6.612946 |
module CC (
in_n0,
in_n1,
in_n2,
in_n3,
in_n4,
in_n5,
opt,
equ,
out_n
);
input [3:0] in_n0;
input [3:0] in_n1;
input [3:0] in_n2;
input [3:0] in_n3;
input [3:0] in_n4;
input [3:0] in_n5;
input [2:0] opt;
input equ;
output [9:0] out_n;
//===========================... | 6.612946 |
module CHECK_3_COLOR (
input [2:0] color0,
input [2:0] color1,
input [2:0] color2,
output out_score
);
assign out_score = ((color0 == color1) && (color1 == color2)) ? (color0 != 3'd7) ? 1 : 0 : 0;
endmodule
| 7.104749 |
module CC_JOINER (
CC_JOINER_car_fila0_bus_in,
CC_JOINER_environment_fila7_bus_in,
CC_JOINER_environment_fila6_bus_in,
CC_JOINER_environment_fila5_bus_in,
CC_JOINER_environment_fila4_bus_in,
CC_JOINER_environment_fila3_bus_in,
CC_JOINER_environment_fila2_bus_in,
CC_JOINER_environment_f... | 7.325996 |
module cc_logic (
op,
shamt,
d_in,
d_out,
do_next
); //cc logic
input [2:0] op; // 3bits input op
input [1:0] shamt; // 2bits input shamt
input [7:0] d_in; // 8bits input d_in
input [7:0] d_out; // 8bits input d_out
output [7:0] do_next; // 8bits output do_next
reg [7:0] do_next; ... | 6.938386 |
module CC_MUXX #(
parameter DATAWIDTH_MUX_SELECTION = 3,
parameter DATAWIDTH_BUS = 8
) (
//////////// OUTPUTS //////////
CC_MUX_DataBUS_Out,
//////////// INPUTS //////////
CC_MUX_DataBUS_In_0,
CC_MUX_DataBUS_In_1,
CC_MUX_DataBUS_In_2,
CC_MUX_DataBUS_In_3,
CC_MUX_DataBUS_In_4,
... | 8.342669 |
module cc_tb;
reg ld_cc = 0; // write enable
reg signed [15:0] data = 16'b0; // data bus
reg clk = 0; // clock
reg rst = 0; // reset
wire n; // negative condition
wire z; // zero condition
wire p; // positive condition
cc c (
ld_cc,
data,
clk,
rst,
n,
z,
... | 7.147037 |
module cc_test;
reg LD_CC;
reg signed [15:0] data;
wire N;
wire Z;
wire P;
LC3 cpu ();
CC test_cc (
cpu.clk,
LD_CC,
data,
N,
Z,
P
);
initial begin
#5 // Wait for CC initial
// Check initial state
if (N != 0 || Z != 0 || P != 0) begin
$display("... | 7.310466 |
module: cache_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CC_test_1;
// Inputs
reg start;
reg CC_clk;
reg read_en;
reg [7:0] address;
reg [2:0] write_select;
r... | 7.176271 |
module cd2ab (
rst,
clk,
cd,
ab
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟
input [1:0] cd; //输入的相对码数据
output [1:0] ab; //转换后的绝对码数据
reg [1:0] ef, a_b;
always @(posedge clk or posedge rst)
if (rst) begin
ef <= 2'd0;
end else begin
ef <= cd;
if (ef[0] != ef... | 7.180277 |
module CDBHelper (
input [2:0] requires,
output reg [2:0] accepts
);
always @(*) begin
if (requires[2]) accepts = 3'b100;
else if (requires[1]) accepts = 3'b010;
else if (requires[0]) accepts = 3'b001;
else accepts = 3'b000;
end
endmodule
| 6.563843 |
module cdce_command_controller (
input clk,
reset_n,
input enable,
input serial_ready,
input [3:0] command,
output [7:0] rom_address,
output start_transaction,
output done
);
// Controller commands from afe_command_rom
parameter COMMAND_TO_SEND = 4'b0001, SEQUENCE_DONE = 4'b0000;
... | 7.794673 |
module cdce_command_rom (
input clk,
reset_n,
input [7:0] address,
output [3:0] controller_command,
output [31:0] cdce_shift_data
);
// Memory variable
reg [35:0] rom[7:0];
reg [35:0] command_reg;
assign controller_command = command_reg[35:32];
assign cdce_shift_data = command_reg[31:0]... | 7.794673 |
module cdce_configure (
input clk,
reset_n,
input miso,
output pdn,
output cs_n,
output mosi,
output configure_done
);
// CDCE power down is active low, so disable it
assign pdn = 1'b1;
// Don't have an upstream reset before starting configuration (always be done)
wire reset_done... | 7.449767 |
module cdce_serial_out (
input clk,
reset_n,
input enable,
input start_transaction,
input [31:0] parallel_input,
output cs_n,
output mosi,
output transaction_done
);
// State machine parameterized states
parameter idle_state = 3'd0, load_state = 3'd1, shifting_state = 3'd2, delay_st... | 7.733042 |
module cdclib_bintogray #(
parameter WIDTH = 2 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in, // data in
// Outputs
output wire [WIDTH-1:0] data_out // data out
);
assign data_out = (data_in >> 1) ^ data_in;
endmodule
| 8.164842 |
module cdclib_bintogray_inc2 #(
parameter WIDTH = 2 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in, // data in
// Outputs
output wire [WIDTH-1:0] data_out // data out
);
assign data_out = {(data_in[WIDTH-1:1] >> 1) ^ data_in[WIDTH-1:1], 1'b0};
endmodule
| 8.164842 |
module cdclib_bintogray_inc8 #(
parameter WIDTH = 6 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in, // data in
// Outputs
output wire [WIDTH-1:0] data_out // data out
);
assign data_out = {(data_in[WIDTH-1:3] >> 1) ^ data_in[WIDTH-1:3], 3'b0};
endmodule
| 8.164842 |
module cdclib_bitsync #(
parameter DWIDTH = 1, // Sync Data input
parameter SYNCSTAGE = 2, // Sync stages
parameter RESET_VAL = 0, // Reset value
parameter CLK_FREQ_MHZ = 250 // Clock frequency (in MHz)
) (
input wire clk, // clock
input wire rst_n, //... | 8.680858 |
module cdclib_bitsync4 #(
parameter DWIDTH = 1, // Sync Data input
parameter RESET_VAL = 0, // Reset value
parameter CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz)
parameter TOGGLE_TYPE = 1, // Toggle type: 1 --> 5
parameter VID = 1 // 1: VID, 0: preVID
) (
... | 8.680858 |
module cdclib_graytobin #(
parameter WIDTH = 2 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in, // data in
// Outputs
output wire [WIDTH-1:0] data_out // data out
);
genvar i;
generate
for (i = 0; i <= WIDTH - 1; i = i + 1) begin : GREY_TO_BIN
assign data_out[i] = ^(... | 7.115826 |
module cdclib_graytobin_inc2 #(
parameter WIDTH = 2 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in, // data in
// Outputs
output wire [WIDTH-1:0] data_out // data out
);
genvar i;
assign data_out[0] = 1'b0;
generate
for (i = 1; i <= WIDTH - 1; i = i + 1) begin : GREY_TO... | 7.115826 |
module cdclib_graytobin_inc8 #(
parameter WIDTH = 6 // Data width
) (
// Inputs
input wire [WIDTH-1:0] data_in, // data in
// Outputs
output wire [WIDTH-1:0] data_out // data out
);
genvar i;
assign data_out[2:0] = 3'b000;
generate
for (i = 3; i <= WIDTH - 1; i = i + 1) begin : GRE... | 7.115826 |
module
//-----------------------------------------------------------------------------
module cdclib_lvlsync2
#(
parameter EN_PULSE_MODE = 0, // Enable Pulse mode i.e O/P data pulses for change in I/P
parameter DWIDTH = 1, // Sync Data input
parameter ACTIVE_LEVEL = 1, // 1: Acti... | 8.13663 |
module
//-----------------------------------------------------------------------------
module cdclib_lvlsync4
#(
parameter EN_PULSE_MODE = 0, // Enable Pulse mode i.e O/P data pulses for change in I/P
parameter DWIDTH = 1, // Sync Data input
parameter ACTIVE_LEVEL = 1, // 1: Activ... | 8.13663 |
module cdclib_pulse_stretch #(
parameter RESET_VAL = 0, // Reset value
parameter HIGH_PULSE = 1 // High or low pulse
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [1:0] r_num_stages, // number of stages required
input wire ... | 9.325088 |
module cdclib_rst_n_sync (
input wire rst_n, // Asynchronous reset
input wire rst_n_bypass, // PLD reset input in scan mode
input wire clk, // Clock to synchronize rst_n to
input wire scan_mode_n, // Scan mode control
output wire rst_n_sync // Synchronized rst_n deassert... | 9.079982 |
module cdclib_rst_n_sync_core (
input wire rst_n, // Asynchronous reset
input wire clk, // Clock to synchronize rst_n to
input wire tie_high, // Tie high input
output wire rst_n_sync // Synchronized rst_n deassertion output
);
//reg rst_n_sync1;
// Reset synchronizer
// Asser... | 9.079982 |
module cdclib_sync2_reset_type_l_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
... | 8.085623 |
module cdclib_sync2_reset_type_n_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
... | 8.085623 |
module cdclib_sync2_reset_type_w_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
... | 8.085623 |
module cdclib_sync2_set_type_l_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
da... | 8.085623 |
module cdclib_sync2_set_type_n_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
da... | 8.085623 |
module cdclib_sync2_set_type_w_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
da... | 8.085623 |
module cdclib_sync4_reset_type_l_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
reg data_in_sync3;
reg data_in_sync4;
always @(negedge rst_n or posedge clk)... | 8.131197 |
module cdclib_sync4_reset_type_w_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
reg data_in_sync3;
reg data_in_sync4;
always @(negedge rst_n or posedge clk)... | 8.131197 |
module cdclib_sync4_set_type_l_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
reg data_in_sync3;
reg data_in_sync4;
always @(negedge rst_n or posedge clk) b... | 8.131197 |
module cdclib_sync4_set_type_w_gate (
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
output wire data_out // data out
);
reg data_in_sync;
reg data_in_sync2;
reg data_in_sync3;
reg data_in_sync4;
always @(negedge rst_n or posedge clk) b... | 8.131197 |
module cdclib_vecsync2 #(
parameter DWIDTH = 2, // Sync Data input
parameter WR_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz)
parameter RD_CLK_FREQ_MHZ = 250, // Clock frequency (in MHz)
parameter VID = 1 // 1: VID, 0: preVID
) (
// Inputs
input wire ... | 8.620834 |
module cdclib_vecsync4 #(
parameter DWIDTH = 2, // Sync Data input
parameter WR_CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz)
parameter RD_CLK_FREQ_MHZ = 1000, // Clock frequency (in MHz)
parameter VID = 1 // 1: VID, 0: preVID
) (
// Inputs
input wire... | 8.620834 |
module cdctl_i2c (
input clk_i,
output wire clk_o,
input [1:0] addr_sel,
inout sda,
input scl,
input rx,
output tx,
output tx_en,
output int_n
);
assign clk_o = ~clk_i;
wire clk = clk_o;
reg rst_sim = 0;
always @(posedge clk) rst_sim = 1;
cdctl_pll b2v_pll_m (
... | 6.692245 |
module cdctl_pcie (
input gclk,
input rst_n,
input pcie_refclk,
input pcie_rx,
output wire pcie_tx,
output wire clkreq_n,
output reg led0,
inout wire [15:0] pio_0_pins
);
assign clkreq_n = 1'b0;
wire top_pll_50m;
wire top_pll_125m;
wire reconfig_busy;
wire [3:0] reconfig_togx... | 6.972835 |
module cdctl_spi (
input clk_i,
output wire clk_o,
input sdi,
output sdo,
input sck,
input nss,
input rx,
output tx,
output tx_en,
output int_n
);
assign clk_o = ~clk_i;
wire clk = clk_o;
reg rst_sim = 0;
always @(posedge clk) rst_sim = 1;
cdctl_pll b2v... | 6.875666 |
module cdc_axi_sync_tech (
input i_xslv_clk,
input i_xslv_nrst,
input types_amba_pkg::axi4_slave_in_type i_xslvi, // system clock
output types_amba_pkg::axi4_slave_out_type o_xslvo, // system clock
input i_xmst_clk,
input i_xmst_nrst,
output types_amba_pkg::axi4_slave_in_type o_xmsto, // ... | 6.906106 |
module cdc_event (
input clk,
input reset_n,
input src_event,
output busy,
input dst_clk,
input dst_reset_n,
output reg dst_event
);
reg req;
reg ack;
reg xack_pipe;
assign busy = req || ack;
reg xreq_pipe;
reg new_req;
reg last_req;
always @(posedge clk or negedge r... | 7.112696 |
module cdc_fifo #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 4,
parameter MAX_ITEMS = 13 // MAX_ITEMS < ((1 << ADDR_WIDTH) - 3)
) (
// -------- clock domain: read --------
input clk_cr,
input reset_cr,
output [DATA_WIDTH-1:0] data_cr,... | 6.951234 |
module CDC_grayCodeCounter #(
parameter bin_rstValue = 1,
parameter gray_rstValue = 0,
parameter integer n_bits = 4
) (
input wire clk,
input wire sysRst,
input wire syncRst,
input wire inc,
output wire syncRstOut,
output reg [n_bits-1:0] cntGray
);
reg [n_bits-1:0] cntBinary;
... | 7.946016 |
module cdc_handshake #(
parameter WIDTH = 1
) (
input wire src_clk,
input wire [WIDTH-1:0] src_data,
input wire src_valid,
output wire src_rcv,
input wire dest_clk,
output reg [WIDTH-1:0] dest_data,
output wire dest_valid
);
// XXX: Add async register property
reg [2:0] dest_sync_r... | 8.110463 |
module CDC #(
parameter DSIZE = 8,
parameter ASIZE = 4
) (
//Input Port
rst_n,
clk1,
clk2,
in_valid,
in_account,
in_A,
in_T,
//Output Port
ready,
out_valid,
out_account
);
//---------------------------------------------------------------------
// INPUT AND ... | 7.885246 |
module cdc_m
(
input wire clka ,
input wire signal_in ,
input wire clkb ,
input wire rst_n ,
output reg signal_out
);
reg signal_in_reg ;
reg cnt;
always@(posedge clka or negedge rst_n)
if(rst_n==1'b0)
signal_in_reg <= 1'b0;
else
signal_in_reg <= signal_in;
always@(posedge clkb or negedge r... | 6.951516 |
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