code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module SNPS_CLOCK_GATE_HIGH_WeightsBank_76 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_75 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_74 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_73 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_72 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_71 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_70 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_69 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_68 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_67 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_66 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_65 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_64 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_63 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_62 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_61 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_60 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_59 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_58 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_57 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_56 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_55 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_54 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_53 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_52 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_51 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_50 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_49 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_48 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_47 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_46 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_45 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_44 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_43 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_42 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_41 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_40 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_39 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_38 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_37 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_36 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_35 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_34 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_33 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_32 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_31 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_30 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_29 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_28 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_27 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_26 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_25 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_24 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_23 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_22 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_21 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_20 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_19 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_18 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_17 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_16 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_15 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_14 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_13 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_12 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_11 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_10 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLA... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_9 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_8 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_7 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_6 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_5 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_2 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_1 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module CAT_32 (
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [3:0] D,
input [3:0] E,
output reg [31:0] out
);
always @(*) begin
out = {E, D, C, B, A};
end
endmodule
| 7.483491 |
module cat_io_lvds #(
parameter INVERT_FRAME_RX = 0,
parameter INVERT_DATA_RX = 6'b00_0000,
parameter INVERT_FRAME_TX = 0,
parameter INVERT_DATA_TX = 6'b00_0000,
parameter INPUT_CLOCK_DELAY = 16,
parameter INPUT_DATA_DELAY = 0,
parameter OUTPUT_CLOCK_DELAY = 16,
parameter OUTPUT_DATA_DEL... | 7.442893 |
module Cause_list (
input in1,
input in2,
output [31:0] cause
);
reg [31:0] c;
always @(in1 or in2) begin
case ({
in1, in2
})
2'b00: c <= 32'b0000000000000000000000000100000;
2'b01: c <= 32'b0000000000000000000000000100100;
2'b10: c <= 32'b0000000000000000000000000... | 6.550614 |
module cav14_example (
clk
);
input wire clk;
reg [`WS1:0] X, Y;
initial begin
X = `W'd0;
Y = `W'd0;
end
always @(posedge clk) begin
X <= (Y > X) ? X : ((Y == X) || (X != `CNT_MAX)) ? (X + `W'd1) : Y;
Y <= (Y == X) ? (Y + `W'd1) : ((Y > X) || (X != `CNT_MAX)) ? Y : X;
end
wire prop... | 6.617639 |
module cav14_example (
clk
);
input wire clk;
reg [`WS1:0] X, Y;
initial begin
X = `W'd1;
Y = `W'd0;
end
always @(posedge clk) begin
X <= (Y > X) ? X : ((Y == X) || (X != `CNT_MAX)) ? (X + `W'd1) : Y;
Y <= (Y == X) ? (Y + `W'd1) : ((Y > X) || (X != `CNT_MAX)) ? Y : X;
end
wire prop... | 6.617639 |
module cavity (
input clk,
input signed [15:0] drive,
output signed [15:0] cav
);
// Goal is a 10 kHz bandwidth cavity, centered at 2/11 of f_clk.
// Thus time constant is 6e-4 of a clock period.
// s-plane pole at f_clk*(2/11*2*pi*i-6e-4) converts to a z-plane pole
// at 0.41517 + 0.90909i.
// P... | 6.987518 |
module cavity_tb;
reg clk;
integer cc;
integer debug=1;
reg trace;
initial begin
trace = $test$plusargs("trace");
for (cc=0; cc<1800; cc=cc+1) begin
clk=0; #5;
clk=1; #5;
end
$finish();
end
integer ccr;
real volt;
real theta = `M_TWO_PI*`RF_NUM/`COHERENT_DEN;
reg signed [15:0] d_in=0, temp;
always @(posedge c... | 6.762867 |
module cavlc_consumed_bits_decoding (
cavlc_decoder_state,
NumCoeffTrailingOnes_len,
TrailingOnes,
heading_one_pos,
levelSuffixSize,
total_zeros_len,
run_of_zeros_len,
cavlc_consumed_bits_len
);
input [3:0] cavlc_decoder_state;
input [4:0] NumCoeffTrailingOnes_len;
input [1:0] Trai... | 7.463766 |
module cavlc_fsm (
clk,
rst_n,
ena,
start,
max_coeff_num,
TotalCoeff,
TotalCoeff_comb,
TrailingOnes,
TrailingOnes_comb,
ZeroLeft,
state,
i,
idle,
valid
);
//------------------------
//ports
//------------------------
input clk;
input rst_n;
input ena;
... | 6.863611 |
module cavlc_ram_2p_36x120 (
clk,
wdata,
waddr,
we,
rd,
raddr,
rdata
);
// ********************************************
//
// Input/Output DECLARATION
//
// ***********... | 6.829542 |
module cav_freq (
input clk,
input signed [17:0] fine,
// getting the following control into the address map is the
// whole point of this module:
(* external *)
input signed [27:0] coarse_freq, // external
output signed [27:0] out
);
// valid range of df_scale is 0 to 9, but one has to ... | 8.121132 |
module top_tb ();
parameter period = 200000;
parameter WIDTH_A = 4;
parameter NUM_A = 21;
parameter OUTWIDTH = 2;
reg [WIDTH_A-1:0] at[NUM_A-1:0];
wire [NUM_A*WIDTH_A-1:0] inp;
wire [OUTWIDTH-1:0] out;
wire [WIDTH_A:0] r;
top DUT (
.inp (inp),
.predo(),
.out (out)
);
int... | 7.81622 |
module top_tb ();
parameter period = 200000;
parameter WIDTH_A = 4;
parameter NUM_A = 21;
parameter OUTWIDTH = 22;
reg [WIDTH_A-1:0] at[NUM_A-1:0];
wire [NUM_A*WIDTH_A-1:0] inp;
wire [OUTWIDTH-1:0] out;
wire [WIDTH_A:0] r;
top DUT (
.inp(inp),
.out(out)
);
integer inFile, outFil... | 7.81622 |
module top_tb ();
parameter period = 200000;
parameter WIDTH_A = 4;
parameter NUM_A = 21;
parameter OUTWIDTH = 2;
reg [WIDTH_A-1:0] at[NUM_A-1:0];
wire [NUM_A*WIDTH_A-1:0] inp;
wire [OUTWIDTH-1:0] out;
wire [WIDTH_A:0] r;
top DUT (
.inp (inp),
.predo(),
.out (out)
);
int... | 7.81622 |
module top_tb ();
parameter period = 200000;
parameter WIDTH_A = 4;
parameter NUM_A = 21;
parameter OUTWIDTH = 14;
reg [WIDTH_A-1:0] at[NUM_A-1:0];
wire [NUM_A*WIDTH_A-1:0] inp;
wire [OUTWIDTH-1:0] out;
wire [WIDTH_A:0] r;
top DUT (
.inp(inp),
.out(out)
);
integer inFile, outFil... | 7.81622 |
module CBA (
input [15:0] A,
B,
output [15:0] Sum,
output Cout
);
wire cout1, cout2, cin1;
RCA RCA_1 (
A[7:0],
B[7:0],
1'b0,
Sum[7:0],
cout1
);
SetupLogic U1 (
A[7:0],
B[7:0],
1'b0,
cout1,
cin1
);
RCA RCA_2 (
A[15:8],
... | 7.185436 |
module: CBA
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CBA_tb;
// Inputs
reg [15:0] A;
reg [15:0] B;
// Outputs
wire [15:0] Sum;
wire Cout;
integer i;
// Instantiate ... | 6.85324 |
module
----designed by Leo Tu
2015.5.20 11:03:34
-----------------------------------------------------------------------------------*/
module ctl_out(clk,
rst_n,
i_done,
i_full_fi... | 8.210043 |
module fulladder (
input A,
input B,
input cin,
output sum,
output cout
);
assign sum = A ^ B ^ cin;
assign cout = (A & B) | (B & cin) | (cin & A);
endmodule
| 7.454465 |
module rca32 #(
parameter n = 32
) (
input [n - 1:0] R,
input [n - 1:0] T,
input Cin,
output [n - 1:0] sum,
output Cout,
output OF
);
wire [n - 1 : 0] c;
genvar i;
fulladder fa0 (
R[0],
T[0],
Cin,
sum[0],
c[0]
);
generate
for (i = 1; i < n; i = i... | 7.840446 |
module cbpa #(
parameter n = 32
) (
input [n - 1:0] R,
input [n - 1:0] T,
input Cin,
output [n - 1:0] sum,
output Cout,
output OF
);
integer j;
wire [n - 1:0] p;
wire rippleCout;
wire sel;
rca32 #(n) rippleCarry (
R,
T,
Cin,
sum,
rippleCout,
OF
... | 8.353796 |
module cbrt (
input clk_i,
input rst_i,
input [7 : 0] a_bi,
output busy_o,
output reg [2 : 0] y_bo
);
localparam IDLE = 3'b000;
localparam STATE1 = 3'b001;
localparam STATE2 = 3'b010;
localparam STATE3 = 3'b011;
localparam STATE4 = 3'b100;
localparam STATE5 = 3'b101;
localparam STATE6... | 7.120453 |
module - quantise
* Project - CODEC2_ENCODE_2400
* Developer - Santhiya S
* Date - Mon Feb 04 16:14:44 2019
*
* Description - select data from the ROMs cb0 to cb9 based on the select input and address.
* Inputs - select : 0 to 9 , corresponds to cb0 to cb9.
*32 bits fixed point repr... | 7.396547 |
module CBuffer (
input wire i_write,
input wire i_read, // 10,11 read, 01 write , 00 keep
input wire [1:0] i_data,
output wire [1:0] o_data,
output wire [2:0] o_size
);
integer i;
reg [2:0] size;
reg [1:0] buff[7:0];
reg [2:0] head, tail;
reg [1:0] data;
assign o_size = size;
assig... | 6.81455 |
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