code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module GP_3LUT (
input IN0,
IN1,
IN2,
output OUT
);
parameter [7:0] INIT = 0;
assign OUT = INIT[{IN2, IN1, IN0}];
endmodule
| 6.909763 |
module GP_4LUT (
input wire IN0,
input wire IN1,
input wire IN2,
input wire IN3,
output wire OUT
);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
| 7.340487 |
module GP_CLKBUF (
input wire IN,
output wire OUT
);
assign OUT = IN;
endmodule
| 7.595703 |
module GP_COUNT14 (
input CLK,
input wire RST,
output reg OUT
);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
reg [13:0] count = COUNT_TO;
initial begin
if (CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not impl... | 6.673748 |
module GP_COUNT14_ADV (
input CLK,
input RST,
output reg OUT,
input UP,
input KEEP,
output reg [7:0] POUT
);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if (CLKIN_DIVIDE != 1) begin
... | 7.546164 |
module GP_COUNT8_ADV (
input CLK,
input RST,
output reg OUT,
input UP,
input KEEP,
output reg [7:0] POUT
);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
reg [7:0] count = COUNT_TO;
initial begin
if (CL... | 8.101498 |
module GP_COUNT8 (
input wire CLK,
input wire RST,
output reg OUT,
output reg [7:0] POUT
);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
initial begin
if (CLKIN_DIVIDE != 1) begin
$display("ERROR: CLKIN_DIVIDE values other than 1 not implem... | 7.671425 |
module GP_DCMPREF (
output reg [7:0] OUT
);
parameter [7:0] REF_VAL = 8'h00;
initial OUT = REF_VAL;
endmodule
| 6.816958 |
module GP_DCMPMUX (
input [1:0] SEL,
input [7:0] IN0,
input [7:0] IN1,
input [7:0] IN2,
input [7:0] IN3,
output reg [7:0] OUTA,
output reg [7:0] OUTB
);
always @(*) begin
case (SEL)
2'd00: begin
OUTA <= IN0;
OUTB <= IN3;
end
2'd01: begin
OUTA... | 6.731175 |
module GP_DFF (
input D,
CLK,
output reg Q
);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK) begin
Q <= D;
end
endmodule
| 7.096887 |
module GP_DFFR (
input D,
CLK,
nRST,
output reg Q
);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.759539 |
module GP_DFFRI (
input D,
CLK,
nRST,
output reg nQ
);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(posedge CLK, negedge nRST) begin
if (!nRST) nQ <= 1'b1;
else nQ <= ~D;
end
endmodule
| 6.972855 |
module GP_DLATCH (
input D,
input nCLK,
output reg Q
);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if (!nCLK) Q <= D;
end
endmodule
| 6.718253 |
module GP_DLATCHI (
input D,
input nCLK,
output reg nQ
);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if (!nCLK) nQ <= ~D;
end
endmodule
| 6.683808 |
module GP_DLATCHR (
input D,
input nCLK,
input nRST,
output reg Q
);
parameter [0:0] INIT = 1'bx;
initial Q = INIT;
always @(*) begin
if (!nRST) Q <= 1'b0;
else if (!nCLK) Q <= D;
end
endmodule
| 6.845035 |
module GP_DLATCHRI (
input D,
input nCLK,
input nRST,
output reg nQ
);
parameter [0:0] INIT = 1'bx;
initial nQ = INIT;
always @(*) begin
if (!nRST) nQ <= 1'b1;
else if (!nCLK) nQ <= ~D;
end
endmodule
| 6.983793 |
module GP_DLATCHSR (
input D,
input nCLK,
input nSR,
output reg Q
);
parameter [0:0] INIT = 1'bx;
parameter [0:0] SRMODE = 1'bx;
initial Q = INIT;
always @(*) begin
if (!nSR) Q <= SRMODE;
else if (!nCLK) Q <= D;
end
endmodule
| 6.771514 |
module GP_IBUF (
input IN,
output OUT
);
assign OUT = IN;
endmodule
| 7.420452 |
module GP_IOBUF (
input IN,
input OE,
output OUT,
inout IO
);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule
| 6.561822 |
module GP_INV (
input IN,
output OUT
);
assign OUT = ~IN;
endmodule
| 7.109173 |
module GP_PGEN (
input wire nRST,
input wire CLK,
output reg OUT
);
initial OUT = 0;
parameter PATTERN_DATA = 16'h0;
parameter PATTERN_LEN = 5'd16;
localparam COUNT_MAX = PATTERN_LEN - 1'h1;
reg [3:0] count = 0;
always @(posedge CLK, negedge nRST) begin
if (!nRST) count <= 0;
else... | 7.088546 |
module GP_SHREG (
input nRST,
input CLK,
input IN,
output OUTA,
output OUTB
);
parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0;
parameter OUTB_TAP = 1;
reg [15:0] shreg = 0;
always @(posedge CLK, negedge nRST) begin
if (!nRST) shreg = 0;
else shreg <= {shreg[14:0], IN};
... | 7.15926 |
module DFF (
output reg Q,
input CLK,
D
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK) Q <= D;
endmodule
| 7.63121 |
module DFFN (
output reg Q,
input CLK,
D
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(negedge CLK) Q <= D;
endmodule
| 7.59828 |
module DFFR (
output reg Q,
input D,
CLK,
RESET
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK) begin
if (RESET) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.750705 |
module GSR (
input GSRI
);
wire GSRO = GSRI;
endmodule
| 6.699202 |
module ALU (
input I0,
input I1,
input I3,
input CIN,
output COUT,
output SUM
);
parameter [3:0] ALU_MODE = 0; // default 0 = ADD
assign {COUT, SUM} = CIN + I1 + I0;
endmodule
| 7.960621 |
module RAM16S4 (
DO,
DI,
AD,
WRE,
CLK
);
parameter WIDTH = 4;
parameter INIT_0 = 16'h0000;
parameter INIT_1 = 16'h0000;
parameter INIT_2 = 16'h0000;
parameter INIT_3 = 16'h0000;
input [WIDTH-1:0] AD;
input [WIDTH-1:0] DI;
output [WIDTH-1:0] DO;
input CLK;
input WRE;
reg [15:0... | 7.830833 |
module SB_GB (
input USER_SIGNAL_TO_GLOBAL_BUFFER,
output GLOBAL_BUFFER_OUTPUT
);
assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
endmodule
| 6.516521 |
module SB_LUT4 (
output O,
input I0,
I1,
I2,
I3
);
parameter [15:0] LUT_INIT = 0;
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
| 6.615748 |
module SB_CARRY (
output CO,
input I0,
I1,
CI
);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
| 6.676196 |
module SB_DFF (
output `SB_DFF_REG,
input C,
D
);
always @(posedge C) Q <= D;
endmodule
| 7.118822 |
module SB_DFFSR (
output `SB_DFF_REG,
input C,
R,
D
);
always @(posedge C)
if (R) Q <= 0;
else Q <= D;
endmodule
| 6.571111 |
module SB_DFFR (
output `SB_DFF_REG,
input C,
R,
D
);
always @(posedge C, posedge R)
if (R) Q <= 0;
else Q <= D;
endmodule
| 6.507634 |
module SB_DFFSS (
output `SB_DFF_REG,
input C,
S,
D
);
always @(posedge C)
if (S) Q <= 1;
else Q <= D;
endmodule
| 6.580459 |
module SB_DFFS (
output `SB_DFF_REG,
input C,
S,
D
);
always @(posedge C, posedge S)
if (S) Q <= 1;
else Q <= D;
endmodule
| 6.638802 |
module SB_DFFESS (
output `SB_DFF_REG,
input C,
E,
S,
D
);
always @(posedge C)
if (E) begin
if (S) Q <= 1;
else Q <= D;
end
endmodule
| 6.585718 |
module SB_DFFN (
output `SB_DFF_REG,
input C,
D
);
always @(negedge C) Q <= D;
endmodule
| 7.178115 |
module ICESTORM_LC (
input I0,
I1,
I2,
I3,
CIN,
CLK,
CEN,
SR,
output LO,
O,
COUT
);
parameter [15:0] LUT_INIT = 0;
parameter [0:0] NEG_CLK = 0;
parameter [0:0] CARRY_ENABLE = 0;
parameter [0:0] DFF_ENABLE = 0;
parameter [0:0] SET_NORESET = 0;
parameter [0:0] ASY... | 7.4615 |
module SB_I2C (
input SBCLKI,
input SBRWI,
input SBSTBI,
input SBADRI7,
input SBADRI6,
input SBADRI5,
input SBADRI4,
input SBADRI3,
input SBADRI2,
input SBADRI1,
input SBADRI0,
input SBDATI7,
input SBDATI6,
input SBDATI5,
input SBDATI4,
input SBDATI3,
... | 7.790141 |
module SB_LEDDA_IP (
input LEDDCS,
input LEDDCLK,
input LEDDDAT7,
input LEDDDAT6,
input LEDDDAT5,
input LEDDDAT4,
input LEDDDAT3,
input LEDDDAT2,
input LEDDDAT1,
input LEDDDAT0,
input LEDDADDR3,
input LEDDADDR2,
input LEDDADDR1,
input LEDDADDR0,
... | 6.512452 |
module SB_IO_I3C (
inout PACKAGE_PIN,
input LATCH_INPUT_VALUE,
input CLOCK_ENABLE,
input INPUT_CLK,
input OUTPUT_CLK,
input OUTPUT_ENABLE,
input D_OUT_0,
input D_OUT_1,
output D_IN_0,
output D_IN_1,
input PU_ENB,
input WEAK_PU_ENB
);
parameter [5:0] PIN_TYPE =... | 6.652072 |
module GP_DCMP (
input [7:0] INP,
input [7:0] INN,
input CLK,
input PWRDN,
output reg GREATER,
output reg EQUAL
);
parameter PWRDN_SYNC = 1'b0;
parameter CLK_EDGE = "RISING";
parameter GREATER_OR_EQUAL = 1'b0;
//TODO implement power-down mode
initial GREATER = 0;
initial EQUAL = 0;... | 8.582023 |
module GP_RCOSC (
input PWRDN,
output reg CLKOUT_HARDIP,
output reg CLKOUT_FABRIC
);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
parameter OSC_FREQ = "25k";
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers no... | 7.510503 |
module GP_RINGOSC (
input PWRDN,
output reg CLKOUT_HARDIP,
output reg CLKOUT_FABRIC
);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter HARDIP_DIV = 1;
parameter FABRIC_DIV = 1;
initial CLKOUT_HARDIP = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation... | 7.21733 |
module GP_SPI (
input SCK,
inout SDAT,
input CSN,
input [7:0] TXD_HIGH,
input [7:0] TXD_LOW,
output reg [7:0] RXD_HIGH,
output reg [7:0] RXD_LOW,
output reg INT
);
initial RXD_HIGH = 0;
initial RXD_LOW = 0;
initial INT = 0;
parameter DATA_WIDTH = 8; //byte or word width
para... | 7.354284 |
module AND2SP1V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
and (OUT, IN1, IN2);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.11:0.11:0.11,
tphhl$IN1$OUT = 0.1:0.1:0.1,
tpllh$IN2$OUT = 0.12:0.12:0.12,
tphhl$IN2$OUT = 0.13:0.13:0.13;
... | 6.510809 |
module AND2SP2V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
and (OUT, IN1, IN2);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.096:0.096:0.096,
tphhl$IN1$OUT = 0.11:0.11:0.11,
tpllh$IN2$OUT = 0.087:0.087:0.087,
tphhl$IN2$OUT = 0.091:0.091... | 6.635796 |
module AND2SP8V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
and (OUT, IN1, IN2);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.095:0.095:0.095,
tphhl$IN1$OUT = 0.1:0.1:0.1,
tpllh$IN2$OUT = 0.1:0.1:0.1,
tphhl$IN2$OUT = 0.12:0.12:0.12;
... | 6.526913 |
module AND22NOR2SP1V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
and (I1_out, IN3, IN4);
or (I2_out, I0_out, I1_out);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.19... | 6.533418 |
module AND22NOR2SP2V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
and (I1_out, IN3, IN4);
or (I2_out, I0_out, I1_out);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.19... | 6.562974 |
module AND22NOR2SP4V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
and (I1_out, IN3, IN4);
or (I2_out, I0_out, I1_out);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.22... | 6.537009 |
module AND2I1SP1V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.13:0.13:0.13,
tphlh$IN1$OUT = 0.19:0.19:0.19,
tpllh$IN2$OUT = 0.12:0.12:0.12,
tphhl$I... | 6.802283 |
module AND2I1SP2V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.11:0.11:0.11,
tphlh$IN1$OUT = 0.15:0.15:0.15,
tpllh$IN2$OUT = 0.098:0.098:0.098,
tphh... | 6.874521 |
module AND2I1SP4V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.11:0.11:0.11,
tphlh$IN1$OUT = 0.14:0.14:0.14,
tpllh$IN2$OUT = 0.094:0.094:0.094,
tphh... | 6.758558 |
module AND2I1SP8V1_0 (
IN1,
IN2,
OUT
);
input IN1;
input IN2;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.12:0.12:0.12,
tphlh$IN1$OUT = 0.14:0.14:0.14,
tpllh$IN2$OUT = 0.1:0.1:0.1,
tphhl$IN2$... | 6.767576 |
module AND2NOR2SP1V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (I1_out, I0_out, IN3);
not (OUT, I1_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.16:0.16:0.16,
tphlh$IN1$OUT = 0.28:0.28:0.28,
... | 6.716808 |
module AND2NOR2SP2V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (I1_out, I0_out, IN3);
not (OUT, I1_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.17:0.17:0.17,
tphlh$IN1$OUT = 0.23:0.23:0.23,
... | 6.878394 |
module AND2NOR2SP4V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (I1_out, I0_out, IN3);
not (OUT, I1_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.2:0.2:0.2,
tphlh$IN1$OUT = 0.24:0.24:0.24,
... | 6.768853 |
module AND2NOR2SP8V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (I1_out, I0_out, IN3);
not (OUT, I1_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.25:0.25:0.25,
tphlh$IN1$OUT = 0.26:0.26:0.26,
... | 6.696706 |
module AND2NOR3SP1V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (I2_out, I0_out, IN3, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.17:0.17:0.17,
tphlh$... | 6.637354 |
module AND2NOR3SP2V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (I2_out, I0_out, IN3, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.17:0.17:0.17,
tphlh$... | 6.709666 |
module AND2NOR3SP4V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (I2_out, I0_out, IN3, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.2:0.2:0.2,
tphlh$IN1... | 6.538027 |
module AND2NOR3SP8V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (I2_out, I0_out, IN3, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.32:0.32:0.32,
tphlh$... | 6.549411 |
module AND2OR2SP1V1_0 (
IN1,
IN2,
OUT,
IN3
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.22:0.22:0.22,
tphhl$IN1$OUT = 0.27:0.27:0.27,
tpllh$IN2$OUT = 0.2... | 7.057068 |
module AND2OR2SP2V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.2:0.2:0.2,
tphhl$IN1$OUT = 0.26:0.26:0.26,
tpllh$IN2$OUT = 0.21:0... | 7.040034 |
module AND2OR2SP4V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.21:0.21:0.21,
tphhl$IN1$OUT = 0.26:0.26:0.26,
tpllh$IN2$OUT = 0.2... | 6.956991 |
module AND2OR2SP8V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.23:0.23:0.23,
tphhl$IN1$OUT = 0.29:0.29:0.29,
tpllh$IN2$OUT = 0.2... | 6.855563 |
module AND2OR3SP1V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3, IN4);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.23:0.23:0.23,
tphhl$IN1$OUT = 0.36:0.36:0.36,... | 6.619071 |
module AND2OR3SP2V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3, IN4);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.21:0.21:0.21,
tphhl$IN1$OUT = 0.33:0.33:0.33,... | 6.650864 |
module AND2OR3SP4V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I0_out, IN1, IN2);
or (OUT, I0_out, IN3, IN4);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.22:0.22:0.22,
tphhl$IN1$OUT = 0.33:0.33:0.33,... | 6.67431 |
module AND3SP1V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (OUT, IN1, IN2, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.14:0.14:0.14,
tphhl$IN1$OUT = 0.12:0.12:0.12,
tpllh$IN2$OUT = 0.16:0.16:0.16,
tphhl$... | 6.61135 |
module AND3SP2V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (OUT, IN1, IN2, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.12:0.12:0.12,
tphhl$IN1$OUT = 0.1:0.1:0.1,
tpllh$IN2$OUT = 0.13:0.13:0.13,
tphhl$IN2... | 6.720753 |
module AND3SP4V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
and (OUT, IN1, IN2, IN3);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.11:0.11:0.11,
tphhl$IN1$OUT = 0.098:0.098:0.098,
tpllh$IN2$OUT = 0.12:0.12:0.12,
tph... | 6.61097 |
module AND3I1SP1V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.14:0.14:0.14,
tphlh$IN1$OUT = 0.21:0.21:0.21,
tpllh$IN2$OUT = 0.1... | 6.706663 |
module AND3I1SP2V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.12:0.12:0.12,
tphlh$IN1$OUT = 0.17:0.17:0.17,
tpllh$IN2$OUT = 0.1... | 6.740252 |
module AND3I1SP4V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.12:0.12:0.12,
tphlh$IN1$OUT = 0.16:0.16:0.16,
tpllh$IN2$OUT = 0.1... | 6.715289 |
module AND3I1SP8V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
and (OUT, I0_out, IN2, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.13:0.13:0.13,
tphlh$IN1$OUT = 0.17:0.17:0.17,
tpllh$IN2$OUT = 0.1... | 6.502567 |
module AND3I2SP1V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
not (I1_out, IN2);
and (OUT, I0_out, I1_out, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.17:0.17:0.17,
tphlh$IN1$OUT = 0.23:0.23:0.23,
... | 6.535797 |
module AND3I2SP2V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
not (I1_out, IN2);
and (OUT, I0_out, I1_out, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.14:0.14:0.14,
tphlh$IN1$OUT = 0.21:0.21:0.21,
... | 6.667628 |
module AND3I2SP4V1_0 (
IN1,
IN2,
IN3,
OUT
);
input IN1;
input IN2;
input IN3;
output OUT;
not (I0_out, IN1);
not (I1_out, IN2);
and (OUT, I0_out, I1_out, IN3);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.15:0.15:0.15,
tphlh$IN1$OUT = 0.21:0.21:0.21,
... | 6.636557 |
module AND3NOR2SP1V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I1_out, IN1, IN2, IN3);
or (I2_out, I1_out, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.2:0.2:0.2,
tphlh$IN1... | 6.553672 |
module AND3NOR2SP2V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I1_out, IN1, IN2, IN3);
or (I2_out, I1_out, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.2:0.2:0.2,
tphlh$IN1... | 6.588794 |
module AND3NOR2SP4V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I1_out, IN1, IN2, IN3);
or (I2_out, I1_out, IN4);
not (OUT, I2_out);
specify
// delay parameters
specparam
tplhl$IN1$OUT = 0.23:0.23:0.23,
tphlh$... | 6.59758 |
module AND3OR2SP1V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I1_out, IN1, IN2, IN3);
or (OUT, I1_out, IN4);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.26:0.26:0.26,
tphhl$IN1$OUT = 0.29:0.29:0.29,... | 6.541581 |
module AND3OR2SP2V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I1_out, IN1, IN2, IN3);
or (OUT, I1_out, IN4);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.24:0.24:0.24,
tphhl$IN1$OUT = 0.28:0.28:0.28,... | 6.572004 |
module AND3OR2SP4V1_0 (
IN1,
IN2,
IN3,
IN4,
OUT
);
input IN1;
input IN2;
input IN3;
input IN4;
output OUT;
and (I1_out, IN1, IN2, IN3);
or (OUT, I1_out, IN4);
specify
// delay parameters
specparam
tpllh$IN1$OUT = 0.25:0.25:0.25,
tphhl$IN1$OUT = 0.28:0.28:0.28,... | 6.509391 |
module BUFSP2V1_0 (
IN,
OUT
);
input IN;
output OUT;
buf (OUT, IN);
specify
// delay parameters
specparam tpllh$IN$OUT = 0.071: 0.071: 0.071, tphhl$IN$OUT = 0.11: 0.11: 0.11;
// path delays
(IN *> OUT) = (tpllh$IN$OUT, tphhl$IN$OUT);
endspecify
endmodule
| 6.567705 |
module DFFDRSP1V1_0 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
P0001, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (P0002, P0001);
buf (Q, P0001);
not (QB, P0001);
specify
// delay parameters
... | 6.770406 |
module DFFDRSP1V1_1 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
P0003, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (P0002, P0003);
buf (Q, P0003);
not (QB, P0003);
specify
// delay parameters
... | 6.888057 |
module DFFDRSP2V1_1 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
P0003, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (P0002, P0003);
buf (Q, P0003);
not (QB, P0003);
specify
// delay parameters
... | 6.81586 |
module DFFDRSP4V1_0 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
P0000, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (P0001, P0000);
buf (Q, P0000);
not (QB, P0000);
specify
// delay parameters
... | 6.783884 |
module DFFDRSP4V1_1 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
P0002, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (NET22, P0002);
buf (Q, P0002);
not (QB, P0002);
specify
// delay parameters
... | 7.074233 |
module DFFDRSP8V1_0 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
NET159, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (P0000, NET159);
buf (Q, NET159);
not (QB, NET159);
specify
// delay parameters
... | 6.551676 |
module DFFDRSP8V1_1 (
CK,
D,
Q,
QB,
RB
);
input CK;
input D;
input RB;
output Q;
output QB;
reg NOTIFIER;
not (I0_CLEAR, RB);
udp_dff(
P0000, D, CK, I0_CLEAR, 1'B0, NOTIFIER
);
not (NET98, P0000);
buf (Q, P0000);
not (QB, P0000);
specify
// delay parameters
... | 7.005238 |
module DFFDSP4V1_1 (
CK,
D,
Q,
QB
);
input CK;
input D;
output Q;
output QB;
reg NOTIFIER;
udp_dff(
P0000, D, CK, 1'B0, 1'B0, NOTIFIER
);
not (P0001, P0000);
buf (Q, P0000);
not (QB, P0000);
specify
// delay parameters
specparam
tpllh$CK$Q = 0.23:0.23:0.23,
... | 6.586224 |
module DFFDSP8V1_1 (
CK,
D,
Q,
QB
);
input CK;
input D;
output Q;
output QB;
reg NOTIFIER;
udp_dff(
P0001, D, CK, 1'B0, 1'B0, NOTIFIER
);
not (P0000, P0001);
buf (Q, P0001);
not (QB, P0001);
specify
// delay parameters
specparam
tpllh$CK$Q = 0.27:0.27:0.27,
... | 6.779854 |
module DFFDSSP1V1_0 (
CK,
D,
Q,
QB,
SB
);
input CK;
input D;
input SB;
output Q;
output QB;
reg NOTIFIER;
not (I0_SET, SB);
udp_dff(
P0002, D, CK, 1'B0, I0_SET, NOTIFIER
);
not (P0003, P0002);
not (Q, P0003);
not (QB, P0002);
specify
// delay parameters
spec... | 6.884041 |
module DFFDSSP2V1_0 (
CK,
D,
Q,
QB,
SB
);
input CK;
input D;
input SB;
output Q;
output QB;
reg NOTIFIER;
not (I0_SET, SB);
udp_dff(
P0002, D, CK, 1'B0, I0_SET, NOTIFIER
);
not (P0003, P0002);
not (Q, P0003);
not (QB, P0002);
specify
// delay parameters
spec... | 6.66117 |
module DFFDSSP4V1_0 (
CK,
D,
Q,
QB,
SB
);
input CK;
input D;
input SB;
output Q;
output QB;
reg NOTIFIER;
not (I0_SET, SB);
udp_dff(
P0002, D, CK, 1'B0, I0_SET, NOTIFIER
);
not (P0003, P0002);
not (Q, P0003);
not (QB, P0002);
specify
// delay parameters
spec... | 6.78777 |
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