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H: What is the real and apparent power of these steel cutters?
The US market model of this steel cutter is 120 VAC, 13.0 Amp.
The NZ market model is 230 VAC, 1,100 W.
I am trying to wrap my head around whether 1,100 W is the real power and so whether the apparent power is 120×13 = 1,560 VA. That comes to the power factor 1100/1560 = 0.705.
Does that sound right for such a tool?
Or, maybe the 2 variants are a bit different in their power?
AI: The 1100 watt rating is very likely the real power for sustained operation. The specs seem to support that.
The 13 amp rating is likely the maximum momentary current. In operation, you would find that the saw is slowing down and losing cutting effectiveness when the current reaches that level. If you persist, the saw will overheat and likely trip the breaker in the service box. In the US, products are required to be marked with current ratings based on worst-case load on the distribution system.
The saw has a universal motor, so the power factor is likely higher than 0.7. |
H: VERILOG: why Xilinx AXI Slave declares all output signal as a wires and not reg?
I am reading the code for an AXI Slave provided by Xilinx (here below).
I am wondering why they declare all outputs as wire and then assign them to an internal register that is modified within always blocks (see for example the S_AXI_RVALID signal).
Why not declare them directly as registers? It seems to me that this would simplify the code and the actual implementation in the FPGA... is there any particular reason why they chose to do so?
Thanks a lot for your help!!!
module frequency_extractor_v2_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 2;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 6
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h4:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
3'h5:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0 : reg_data_out <= slv_reg0;
3'h1 : reg_data_out <= slv_reg1;
3'h2 : reg_data_out <= slv_reg2;
3'h3 : reg_data_out <= slv_reg3;
3'h4 : reg_data_out <= slv_reg4;
3'h5 : reg_data_out <= slv_reg5;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule```
AI: AXI devices can return data in the "same" cycle, so it can be latched by the requester on the next rising edge. For this to work, the outputs must be a combinatorial function of the inputs, with no register in between that would cause a delay.
Declaring them as wire will make the compiler check that the combinatorial circuit that does this is fully defined, and has no feedback path that behaves like a latch (i.e. it turns the "inferring latches" warning into an error).
These two things are largely unrelated, but when you're writing logic that needs to be purely combinatorial, the extra check is really useful. |
H: Are vehicle electrical components powered from the negative side?
still trying to get my head around electron flow as opposed to conventional current regarding automotive electrical circuits. There seems to be a ton of conflicting information/advice out there so I'm hoping to seek some clarity.
Basically I'm just wondering because electrons flow from the negative side of the battery to the positive, is the vehicle's entire electrical system essentially powered from the negative (earth) side then the current returns to the battery into the positive during the battery discharge cycle?
Would this then mean during battery recharge (alternator running) that the vehicle's electrical system is essentially powered by the alternator through its earth?
I made a picture to try and demonstrate this better:
Where I'm getting confused particularly is that I measured current flow with an amp clamp during discharge and recharge of the battery and it gave me a positive reading when the arrow was pointing in the direction of conventional current as opposed to electron flow.
There's that and the fact that a lot of people are saying electron flow goes from negative to positive but the energy goes from positive to negative, like, what energy? How is that "energy" measured?
EDIT: also regarding spark plug operation, do electrons supposedly flow backwards to the ignition coil? Very confusing.
I appreciate any help, thanks
AI: Where I'm getting confused particularly is that I measured current flow with an amp clamp during discharge and recharge of the battery and it gave me a positive reading when the arrow was pointing in the direction of conventional current as opposed to electron flow.
That's because the clamp meter is designed to show you the direction of conventional current flow.
There's that and the fact that a lot of people are saying electron flow goes from negative to positive ...
It does
... but the energy goes from positive to negative ...
No. Positive charges, if they were mobile, would flow from positive to negative. There are no mobile positive charges in copper wires, but in electrolyte solutions and plasmas, there are plenty of positively charged mobile species that move in that direction.
... like, what energy? How is that "energy" measured?
There are several ways to measure the energy. One is to measure the voltage across a load, and the current through it. The product is the power in watts, which when multiplied by the time of a period in seconds will give you the total energy in joules transferred in that period.
You'll note the voltage is between the two wires to the load, and the current is the same in each load wire. The energy is not 'flowing' in either the positive or the negative wire, it takes both to transfer the energy.
A more general treatment of energy flow uses the Poynting Vector, which at every point in space is at right angles to the voltage difference between the wires and the magnetic field caused by the current. You can interpret this as meaning the energy flows in free space around the wires, or that it's a fiction merely to calculate the energy flow in the wires. It needs both wires however.
During battery charge or discharge, energy flows into or out of it mediated by the current in both the positive and negative wires, and the voltage difference between them. There is no special role for just one of the wires, from a physics point of view.
From an automotive and commercial point of view, the two wires are very different, as one is bolted to the chassis. |
H: Problems casting a uint8_t array to a struct
I'm having problems casting an array of uint8_t to a struct in C using a Silicon Labs MCU (EFM32GG11B120F2048GQ64). The byte array is the received data from a UART, and I want to cast it to a struct representing the message structure.
When casting the array to the struct, report_type (uint8_t) is byte [0] in the array, as it should. But start_time (uint32_t) is not the value of bytes [1..4] as I would think, but rather bytes [4..7]. Bytes [1..3] are not used.
I tried adding a second uint8_t member report_type2, effectively moving start_time down one position. report_type2 gets the value of byte [1], but start_time still gets the value of bytes [4..7].
Anybody knows what's going on here and why this is?
Byte array:
05 29 68 58 3C 0E 10 02 44 0D D5 C3 3F 0F 5C 29 00 05 69 75 00 00 0A B8 07 25 A7 11 00 B5 01 02 4C 1D 00 1C 0A FF FF 00 00 00 0A 01 B9 06 00 09 07 25 A7 11 00 B5 01 02 4C 1D 00 1C 0A FF FF 00 00 00 0A 01 B9 06 00 09 07 25 A7 11 00 B5 01 02 4C 1D 00 1C
Struct:
typedef struct
{
uint8_t report_type;
uint32_t start_time;
uint16_t period_length;
uint8_t status_alarm_code;
float_union_t total;
float_union_t average;
subperiod_t subperiod_1;
subperiod_t subperiod_2;
subperiod_t subperiod_3;
subperiod_t subperiod_4;
subperiod_t subperiod_5;
subperiod_t subperiod_6;
subperiod_t subperiod_7;
subperiod_t subperiod_8;
subperiod_t subperiod_9;
subperiod_t subperiod_10;
}report_t;
Casting array to struct:
report_t *report = (report_t *)packet->data;
AI: You cannot do dirty casts like this in C. There are multiple problems:
The data you copy from might not be aligned.
The struct might have padding bytes to compensate for internal alignment that are not present in the data you copy from.
Dereferencing this struct pointer after the cast leads to a strict pointer aliasing violation, meaning it's undefined behavior bug which could result in incorrect machine code getting generated.
The safest and most portabile solution is write a function that does serialization/deserialization of the struct data. That is, a function writing to each member manually. This is slightly slower due to the overhead code but the most portable.
Less portable but probably faster is to memcpy the data. If you do this, you must be absolutely sure that the struct has no padding. Which you aren't, the struct you posted is very poorly designed by someone who has never heard of alignment, since it has padding gaps all over it. If you re-design the struct to ensure there's no padding, you could use memcpy or similar methods.
(Union type punning is yet another option.) |
H: ATSAMD11C SERCOM I2C Pin Assignment
I am planning on using the ATSAMD11C14 (SOIC14 package) for a project that requires USB, 2 I2C busses, and some GPIO.
The device has two SERCOMs, each has 4 pins assigned to it. When used in 2 wire I2C mode, only two pins are required for communications. Does this mean that the other two pins assigned to the SERCOM can be used as GPIO?
I took a look through the data sheet, but cannot find the information I am looking for. Apologies if it was there and I just missed it!
AI: As each GPIO pin must be separately configured anyway, and every SERCOM section warns that used pins must be configured for the alternative function of SERCOM, it means you can configure or leave other pins as GPIO. |
H: LM2576 unload state
I've seen something weird with the LM2576 diode waveform when I leave it without load and with the load. Here is the diode waveform when I put a 100ohm resistor as LM2576's load.
It seems the circuit and diode works fine. However, By removing the load I see this diode waveform:
I need to know why oscillation has been occured during the off time and where it comes from.
Thanks
AI: With no load, the operation of the switcher enters DCM (discontinuous conduction mode) where all the inductor's stored energy that can be fed to the output is transferred. The remaining (unusable) energy circulates round the MOSFET's parasitic drain-source capacitance and forms a resonant circuit with the inductor. This produces a decaying sinewave as seen on your 2nd oscilloscope screen shot: -
It's pretty normal so, no need to worry. |
H: Correct way of estimating delays in FPGAs
What is the correct way of estimating delays when doing operations in Verilog?
For example:
reg [31:0] a, b;
...
wire [31:0] res;
assing res = a + b;
The above + operator could lead to very different delays depending on if it is synthesized to a ripple-carry adder, a carry-look-ahead adder or a prefix adder.
How can I estimate the delay of that operation, so my simulations are closer to what the circuit will do in reality?
PD. Context
I'm designing a RISC-V processor in Verilog following a book. The book asks you to design different building blocks using logic gates, such as the adders mentioned above, shifters etc. In this case, one could estimate the delay of a logic gate (possibly oversize it) and implement all the required operators with gates, so the delay will be correct with regards to the estimation.
However, I have seen in the book's solutions to exercises that it uses a lot of operators (>>, +, -) directly without assigning delays. This will allow to test the design 'logic' is correct, but won't reveal anything about the maximum frequency allowed.
In addition, one cannot know what adder etc. the synthesizer will choose, so isn't it better to fix that from the beginning to test the design correctly?
Would it be valid to design an adder, calculate its delay and then assume that all the rest of the + operations will have this delay (maybe oversize it), instead of instantiate the mentioned adder again and again?
AI: Realistically commercial digital logic design treats "get logic correct" and "fix timing" as two entirely separate phases of work. It's even more extreme in ASIC design than FGPA, but as someone else has said the delay you get in FPGA can depend a lot on placement. You cannot realistically estimate delay without placement. Sizing tends to be less critical in FPGA as the LUTs tend to be "one size fits all" and the tooling inserts buffers for you as needed.
It may well be the case (and it would be fastest) that the tooling assigns your adder to a predefined "adder" block on the FPGA. |
H: Designation "2-" in a technical drawing of a component
What does the encircled "2-" designate in the technical drawing below? Is it some standardized/common designation of something? "R" stands for the radius, and the numbers refers to the values in mm.
The picture is an excerpt from the 6th page of this document. (I've added the red circles)
AI: It means that there are two objects with that dimension. The same shape exists on the right-hand side of the FFC without dimensions, so "2-" is letting you know that side is the same as the left. |
H: Driving parallel channels with 1 PWM signal
I am currently developing a protoboard for an LED driver having PWM control for dimming using a microcontroller. I plan to drive a number of parallel channels of LEDs ('n' number of RGB channels) and have it opto-isolated as well.
My question is, is it okay to drive these parallel strings using 'n' numbers of PWM channels to lessen the number of GPIOs needed for generating the PWM signals? My plan was to independently dim the three color channels using only three PWM outputs providing the PWM signals only dimming by color (say 3 RGB channels, 1 PWM signal for the three channels of red... and so on). What other factors must I consider such as how it may affect the duty cycles and other dimming/control variables if I plan to do such setup?
AI: As far as I understand, if I boil down the question, it will be "can I route one PWM signal to multiple components/devices"? If so, the answer is yes, you can.
There are minor caveats that limit your peak frequency, because the trace itself has non-zero capacitance, but if your PWM is in lower MHz - Arduino level frequencies, you don't have anything at all to worry about.
It would be a good idea to have a resistor on the PWM output, because the capacitance of the trace means you will be charging/discharging that trace like a tiny cap, and there will be high instantaneous currents. You don't want that (same thing as driving individual MOSFET gate with Arduino). It will probably work, but better put some 120 - 330 Ohm between PWM driver and everything else it connects to. For peace of mind.
Like here (random picture, just an illustration of a resistor on PWM output, picture source):
Also, you don't want to run multiple different PWM signals too close together in parallel, have a little distance between them so that they don't couple together. By "too close" I mean a few mm should already be enough. Obviously, without specifics regarding frequency (and PWM rise/fall time) I can't provide and specifics in this regard too, but all in all for a basic project it's probably not something you should worry about too much, just be aware that such thing exists, maybe do basic research on how switching noise is induced (rise time, fall time, etc.). |
H: Current source with MOSFET
In the circuits below, what does the 100R resistor do?
In my understanding the 1K along with the 200 pF create an integrator topology to provide some stability but how about the 100R that feeds the gate of the MOSFET?
What does it do?
Wouldn't that delay the on/off time of the MOSFET's channel?
Wouldn't we want the MOSFET to instantly respond to every fluctuation of the channel's current?
Can this resistor be larger? 1K or 3K?
AI: In my understanding the 1K along with the 200pF create an integrator
topology to provide some stability
Correct and, particularly when using a MOSFET in these configurations there can be a significant amount of gate-source capacitance (2 nF for the Si9430) that can cause stability problems hence, the output of the op-amp is "isolated" from that gate-source capacitance by using the 100 Ω resistor.
Wouldn't that delay the on/off time of the mosfet's channel?
Yes it will but, without that isolation, the localized feedback capacitor cannot create an integrator. This would leave you with the only option of reducing the DC gain with a localized feedback resistor and, of course, that ruins output current regulation.
Wouldn't we want the mosfet to instantly respond to every flactuation
of the channel's current?
That's not going to happen because of the necessity of the integrator.
Even though the MOSFET is used as a source follower, the gate-source capacitance (that is usually neutralized in an ideal MOSFET) still remains significantly high. BJTs are quite often used instead of MOSFETs and can be more easily made stable.
Can this resistor be larger? 1K or 3K?
The time constant of the integrator has to dominate the time constant of the gate resistor and residual gate-source capacitance so, probably not even worth trying. Of course, you might find a limited set of output currents where it might work but, if you want a generally half-decent constant current source, then no. |
H: synchronous buck simulation
I got confusing result from hspice simulation but I can't get it.
the voltage at "N1"should be 4V when W1 on,and be 0 when W0 on.
but result is always 0 and pulse of negative voltage.
below is the concept pic ,code,and waveform
AI: A synchronous buck converter can be easily simulated with two voltage-controlled switches across which a diode is connected. This diode is important for the low-side switch as it will immediately conduct the inductive current when the main switch opens. Then, after the deadtime is elapsed, the low-side switch is turned in zero-voltage switching (ZVS) mode:
I like the programming of the drive sources via a .VAR (in SIMPLIS) or a .PARAM statement in SPICE. You can change the duty ratio and frequency on the fly and the parameters will be automatically computed before the simulation starts:
The duty ratio is set slightly above 50% to compensate for the ohmic losses induced by the inductor equivalent series resistance (ESR) and the two switches drops. As a next step, you can replace the two sources by a proper pulse-width modulator (PWM) block with a dead time generator and start analyzing the frequency response. |
H: Is a current limiting resistor needed for dual opamp supply pins?
Consider the TL072 dual op amp that is supplied with +/- 12V. The datasheet says that the supply current for (each) amplifier is typically 1.4 mA, with maximum of 2.5 mA. If both amplifiers are operating, should the current be limited to 2.5 mA on each supply pin? So I would use ~4.8 ohm resistors in series with the supply pins to limit the current to a maximum of 2.5 mA. Is this the correct interpretation of the datasheet?
AI: The supply current stated is the maximum current the op amp will draw with no load. There is no need to current limit the input as in e.g. a LED, just make sure that whatever you're driving keeps output current and maximum supply current within datasheet values. More detailed discussion here. |
H: Open ended LM2937-5 outputs 12V
The LDO, LM2937-5, with 12V input voltage and nothing connected to the output terminal, outputs 12 V (measuring using voltmeter). As soon as I connected 100 uF capacitor, it shows 5V.
Datasheet clearly states that output capacitor is required, but it does not say about overvoltage, rather than about resulting oscillation. In addition, all the tables list minimal current of 5 mA.
Now imagine circuit with failed capacitors (all of them), and microcontroller consuming less than 1mA. Microcontroller will fry?
I have another device on hand TS2937, and when its output is open (no cap) it shows more or less 5V, and surely not 12V.
What do I miss here?
Update: 10 uF does the job too.
Update: the practical question - is it safe using this LDO at all? I have never experienced this behavior from LDO. And as I said in the condition above - will circuit fry?
Update: thanks all for the responses. This is a repair, therefore using 7805 is not an option (need SOT-223 package), and the original part was TS2937. There're two 10 uF caps on the rail (however for 6.3V rating, and I personally do not like this fact), and LED with 220 Ohm series resistor, therefore the circuit meets the requirements :)
AI: The datasheet mentions oscillation as a condition that can occur due to missing capacitance, but it does not need to give an exhaustive list. Simply put, the regulator is not operating in its rated/designed conditions, and its behavior is undefined -- a capacitor must be added.
The actual structure of the regulator is some control plus a PNP pass element:
If the PNP element is even slightly too-strongly-on without a significant load, then the output will get driven to 12 V (since the load of the feedback resistors is likely negligible). It is very plausible that there may be internal oscillations or dysregulation which manifests itself as the output being stuck at 12 V. It's also plausible that with a real load (but insufficient capacitance), the internal oscillations might actually appear as external oscillations of the output voltage.
Furthermore, it's plausible that different design or device parameters in TS2937 may make it somewhat stable without a capacitor, although it may still fail to meet its line/load regulation specification.
To answer the practical question - yes. Tons of circuits will do weird things when one deliberately ignores their datasheet requirements for input/output capacitance or their other requirements. If you have an issue with capacitors regularly failing open on your boards, you have bigger issues than the choice of regulator and attempt to prevent frying MCUs. |
H: Do I need RTC while I'm using NTP?
We know computer and another device like microcontroller is not accurate in ticking clock comparing to wall clock that using cesium atom.
I heard RTC module is purpose to making accurate the ticking.
But microcontroller that I used is Espressif family which they have built-in Wi-Fi module.
I mean, I can just syncron the time with using Network Time Protocol aka NTP for every few period for example syncroun every 1 hour. So that's mean the MCU will retrieve data from NTP server every 1 hours relative calculated with using millis() function.
So do I still need RTC module?
Yes the disadvantage of using NTP is need online while RTC still can be used in offline. But once the device is online, it will syncroun again following NTP server.
AI: Only talking about the ESP32:
The internal RTC is quite useful because it keeps running even when the ESP32 reboots (via any kind of software reset, watchdog reset, crashes,...).
It makes totally sense to combine RTC with NTP because the RTC is not that precise and should be adjusted once in a while (e.g. once a day).
NTP is also neccessary to initialize the RTC after power up, because the RTC time does not survive power cycles and hardware resets via the Reset button (aka "power-on reset"). |
H: What capacitor is this (part number)? Looking for the datasheet
I'm trying to find the datasheet for this 1.0F & 5.5V capacitor. Some identifying labels on it are "GC", "Japan", and "822". I haven't had luck in my googling, so does anyone know what part number this is?
AI: It seems consistent with Panasonic's discontinued stacked coin type of double layer capacitor. They refer to them as a "Gold Capacitor" which might explain the "GC" labeling. The country of origin for Panasonic electrolytic capacitors is Japan. Multiple part numbers match the 5.5V and 1F parameters. However, other manufacturers such as Nichicon or Rubycon might also match all of these criteria. (I don't know if they also use "gold capacitor" terminology; it seems to only be associated with Panasonic.)
Some similar part numbers but with leads attached are:
EECS5R5_105
EECS5R5_105N
Where the underscore is replaced by V or H depending on terminal style.
A possible better match might be EEC-F5R5H105N based on what I presume are radial leads on the side of the cap you didn't photograph.
In any case, without more information it's difficult to tell which series it is, what its temperature rating is, etc. |
H: Adjusting the drive strength of level-sensitive interrupt signal
In my current environment, the interrupt source comes from an FPGA on a daughter board and connects to a GPIO pin on an EVB:
daughter board (interrupt output signal from SD controller)--> EVB(GPIO pin with interrupt enabled).
The GPIO interrupt polarity is set as active-low. The GPIO pin's voltage is 3.3 V and the daughter board output signal is 0 V.
When I connect both signals, no interrupt is triggered.
If I connect the ground pin on the EVB to the GPIO pin, an interrupt can be triggered.
It seems that the daughter board output is not 'strong' enough to drive the GPIO pin to low.
I am not familiar with the details of electronics wrt GPIO interrupt level-sensitive trigger mechanism.
How is this possible?
What is a possible solution for it?
Update: Problem Now Solved
I have since resolved the issue.
The reason is that on the daughter board there is a switch (with a indicating LED) to turn on the pins. I was not aware of this switch until I report the issue to the FPGA engineer.
AI: This does not sound like a "drive strength" problem. Either...
Your signal grounds are not connected OR
You do not have a true low impedance path between your interrupt
source and interrupt destination. You can probably cross this one off quickly by measuring the resistance between the interrupt source and destination.
Your pinout/wiring is incorrect
If you want to keep the two boards electrically isolated you will need to use a digital isolator or similar. Note that you will have to connect both signal and ground for both the source and destination in order to implement this.
If isolation is not a requirement then, as stated in the comments, you should connect the grounds between the two boards and try your experiment again. If this still does not solve the problem, then I would double check your wiring and pinouts. |
H: Would appreciate some tips on designing simple OpAmp circuit
I've recently posted this question regarding input impedance when working with DC signal on HCPL-7840 Isolation Amplifier. The answers were very clarifying and helpful, but I've come to realize I need more specific help.
Just a disclaimer: I decided to use HCPL-7840 because it was the best option available on my chosen supplier that seems to fufil my needs.
My goal is to design a simple isolated amplifier for an NTC
NTC characteristics considered:
Resistance [kΩ]
Temperature [ºC]
10
30
15
20
20
10
25
0
HCPL-7840 characteristics considered:
The information on the "Recommended Operating Conditions" table of datasheet
Equivalent Input Impedance RIN — 500 — kΩ
Figures 12 and 14 of datasheet
Based on these informations, I designed the following simple circuit:
It's composed of a simple voltage divider, where R1 is fixed precise resistor, and R2 is the NTC.
As soon as I assembled the board and started making measurements, I noticed that the voltages on TP1 were not exactly what I expected to see
I was expecting a simple voltage divider between R1, R2
I figured the difference should be because of internal resistence of HCPL (Rin), between pins 2 and 3
This Rin is suposelly connected in parallel with R2 (between TP1 and GND iso)
I than started to conduct some experiments to empirically try and figure out the value of Rin. This way I could calculate adjusted values for R1 and R2 and keep the voltage on TP1 within the input limits of HCPL linear range
The experiment consists of trying different combinations of R1 and R2 and measuring the voltage at TP1.
The results of this experiments drive me crazy because different combinations of R1, R2 make me infer different values for Rin each time.
The following table summarizes the experiment results:
Index
Vdd [V]
R1 [Ω]
R2 [Ω]
V measured @ TP1 [V]
1
5.40
2150
100
0.213
2
5.45
2150
68
0.158
3
5.56
2150
40
0.101
4
5.55
246000
11600
0.186
5
5.70
246000
5800
0.119
6
5.77
717500
11600
0.082
7
5.79
717500
23500
0.113
8
5.84
717500
51300
0.142
Vdd and V measured @ TP1 were measured with osciloscope.
R1 and R2 were measured with Ohmmeter before the experiment.
Outcomes:
Given Vdd, R1 and V measured @ TP1, I was able to calculate what would be the "real R2" that the circuit is submited to.
This "real R2" would be the parallel between R2 (from the table) and Rin
Because I have R2, I'm able to calculate Rin
After this procedure I ended up with a lot of different values of Rin for each experiment case, and I don't know how to proceed!!!
Any help is appreciated.
Thanks!
AI: Figure 14 of the datasheet suggests that the input current into the HCPL-7840 should be fairly linear (resistor like) for input voltages in the range of -200mV to +200mV. But acconding to note 12 on page 18 of the datasheet the input stage is actually a "switched capacitor", not a real resistor, so there is going to be current spikes. I would suggest putting a 0.1uF ceramic capacitor across R2.
I would also suggest making changes that make your circuit less sensitive to input current on the HCPL-7840 input pins.
One option is to buffer the + input of the HCPL-7840 with another rail-to-rail op-amp configured as a voltage follower.
Alternatively, you could lower the values of R1 and R2 enough that the input current into the HCPL-7840 doesn't affect the measurement as much. |
H: Splitting of a differential signal
Can the Ethernet Tx and Rx signals (Using all 4 pairs; RGMII interface) be split into 2 so as to connect to 2 RJ-45 connectors, but only 1 will be used at a time. In general, can we split any differential signals for 2 outputs?
Edit:
Added a picture for better understanding of my question.
AI: In general, we cannot split any differential signal and use it on two outputs.
If we are careful, we can split a differential signal and measure the two lines individually as single ended signals.
A differential digital signal (ethernet, HDMI, SATA) will just plain not work if you connect only one of the pair of conductors to the other end. |
H: Linear power supply - overload protection circuit
Summary and context:
Several years ago I bought a linear power supply from Pyramid, model PS-3KX.
I would like to understand in detail how the overload protection really works, as said by Pyramid manufacturer (red box in the Specification part).
It seems the PS-3KX is capable of 2 A in continuous service (blue underline) but triggers the protection above 3 A (maximum current - purple line).
An AC component of the secondary transformer seems to be "detected" by the components marked in red (D5, R3&R4, D6&D7, C3, and Q1), which triggers Q2 through C4 and D8 - marked in purple.
Severe current overload reducing the stabilized Output voltage, or a short-circuit in the output, would lower the polarization voltage in Q1 (green makings) that would raise the voltage at C4, conducting Q2 and shutting down output through Q3 and Q4.
Voltage feedback regulation is obtained by the circuitry marked in blue, but I have concerns if the ripple detection (red and purple circuitries) would not worsen voltage stabilization or even induce a higher ripple.
UPDATE#2:
After studying the replies and simulation from recently accepted answer and the results of my "Update#1" (Waveforms in a PS transformer), I will comment with UP#2, certain paragraphs in my original post, to avoid misguiding future readers in EESE here.
TLDR: The simulated original circuit does not work as expected and the manufacturer's performance figures for protection could not be confirmed.
UPDATE #1:
I made a collage of the PS-3KX I have, to share the general view of the internals:
== Resuming Original Post ==
The user manual, which can be obtained here, shows:
Specification Summary, with some highlights for my PS model.
Circuit Diagram, with circuitry features color-marked:
Doubts and questions:
Based on the presented information, and assuming the actual PS-3KX unit is not available here for further testing, please help me to solve the following doubts and questions.
If I understood something inadequate or simply wrong or missed any hidden feature, please share your views:
{1} Short-circuit & Overload Protection #1 - Seems to be effective only if the output voltage is lower than 4.1 V. What happens if a higher current is required at higher voltages?
{1A} For example: Let's say, a high-powered LED array starts to conduct at 8 V and requires 4 A @ 12 V? The voltage could be high enough to not trigger green and Q1 circuitry.
{1B} Did I miss something for this circuitry feature?
{2} Overload of the Transformer - Protection #2 - An apparent ingenious circuitry, marked in red and purple, seems to detect higher frequency (harmonics) if the transformer core is overloaded.
{2A} These overload, magnetization, and higher frequency are the most intriguing features for me. I would like to understand properly/completely how this happens.
UP#2: Scoped waveforms in Update#1 and some simulation results (answer), made my mind that the red and purple-marked circuit, as it is, is NOT reliable overload protection. The overload protection circuit could be improved using Antonio51's answer and associated discussions as a guide and starting point.
{3} Effectiveness of the Transformer Protection #2 - This feature could be a feature we could use on an unknown power-supply transformer. Curiously, I have not seen this kind of circuit being used elsewhere.
UP#2: As mentioned above, the existing protection is not reliable/effective to protect either the electronics or any overload on the transformer.
{3A} Is it too good to be true? (UP#2: It is "Not True"...). What would be the hidden trade-offs?
{3B} Would it be problematic, eventually lowering the output voltage even when the current is within the continuous 2 A limit?
Please observe the ripple at this current is specified as 150 mV RMS (in the blue box).
{3C} It is specified the overload protection is +10% ~ 15% with auto-reset (see red box in spec).
I assume this would be above 3 A = maximum stated current.
How precise could this be as Pyramid's stated, if there is no current being directly measured?
{4} Semiconductor Protection - How safe is this schematic to protect the series-pass transistor and rectifier diodes from overcurrent?
{4A} Transformer Protection - How safe is it to avoid severe overload of transformer?
UP#2: Original circuit does not provide the specified protection.
A R_shunt and 1 or 2 BJTs working as a classic current limiting circuit, or working as hiccup protection (see answer) are necessary additions for PS protection.
I'm sure my description was a bit repetitive (or recursive); sorry about that, but see it as a shared brainstorming to understand the circuit and its potential problems.
UPDATE#1: Waveform in Linear Power Supply Transformer
After seeing simulation work made by Antonio51 (Thanks!) I decided to check how a Transformer inside a smaller power supply I made 40 years ago (CV = 1-25 V; CC = 0.13-1 A) would behave from:
No/Minimum Loading = 76.5 Vpp @ 0 A & 71.0 Vpp @ 0.13 A.
Average Loading = 58.5 Vpp @ 0.5 A
Light Overloading = 46.5 Vpp @ 0.94 A.
Severe Overloading = 11.5 Vpp @ 2~3 A.
The photo collage shows the tests and waveforms.
This test was made with a different linear PS, made with a repurposed car slot transformer (12+12 VAC, 2 A) ~ about the same VA magnitude of the PS-3KX. So I believe the transformer in the PS-3KX would behave similarly.
I did not see any unexpected spikes, just the sinusoid AC wave being flattened when able to charge the capacitor and be drained under constant current.
Even when the transformer is severely overloaded, the waveform is qualitatively similar to regular loading.
Conclusions (by UP#1 & UP#2):
Unless it is missed something, as my hobbyist Scope does not do FFT (it would be great to see), I did not find any transformer behavior in real life (not as model/simulation) that would justify the manufacturer's protection method to be effective or safe.
If any of you has a different view or had another experience, please let us know!
AI: I would like to understand in detail how the "OVER-LOAD PROTECTION" really works ...
Simulated that "thing", EE&O in the schematic ...
Some names BJT transistors changed, don't have searched for "equivalent".
Transformer parameters are "guessed", with no "non-linearities" ...
Made with free software microcap v12. Dropbox link1. Dropbox link2.
Done in three cases
normal use max 3 A, @ output = 13.8 V (it seems a power supply for "transceivers")
with "light" overload
with "big" overload (power supply "pumps").
Here, changed 2 BJT to BC109C, added windings resistors ... Quasi same behavior.
Conlusion: "Overload protection" is very a bit "strange" and "not efficient".
UPDATE: I have added some overload "protection" ... EE&O.
Sorry, the post is becoming "long" :-)
As asked by OP, I add the picture for severe overload.
The peak current is high, but the time of the first pulse is short, (about 500us), probably the "discharge time" of C6 (confirmed \$timePulse = fullLoad * C6 * 3 \$).
I guess the "modified protection" circuit will be ok. (in any case, need to check all voltages, currents, powers ...).
UPDATE 2: Changed R22 to 10 kOhm. Power supply functional after overloading disappears.
More interesting ... |
H: Why in this circuit the collector of Q2 is receiving negative voltage?
According to when we say the collector in a transistor is reverse bias and the base and emitter are forward bias, why in this circuit (since Q3 or Q4 are NPN, so the emitter should be connected to negative voltage) the collector of Q2 is receiving negative voltage? (Since Q2 is NPN, to have a reverse bias the collector should be connected to a positive voltage.)
AI: All potentials other than ground in this circuit are positive with respect to ground. What is important for analysing this circuit are the potential differences. For example, Q3 emitter as said before is not at a negative potential, but it is at a lower potential, thus more negative, than Q3 base. The base-emitter junction is therefore forward biased and conducting. The collector is at an even higher potential, so this transistor is working in active mode. The same logic can be applied to the other transistors in this circuit. |
H: Which part of this transistor model op amp represents pin 5?
In this op amp oscillator pin 5 is connected to an RC circuit:
I have a transistor model of that op amp and I want to connect an RC circuit to it like the above circuit:
Since pin 4 and 8 represents the voltage source of that ideal op amp, I am not sure that I should connect that RC circuit like this:
Which part of the transistor model op amp represents pin 5?
AI: Your op-amp oscillator is incorrectly drawn: -
You have the inputs swapped and it will no-longer behave like a relaxation oscillator. Regarding which pins are represented in your transistor circuit: -
But, it won't behave very well as a relaxation oscillator because the output node should be buffered and have a lower impedance output such that it can adequately drive the feedback components in the oscillator without gain or DC offset being unduly affected. |
H: RS-485 Network Topology with Backbone and Daisy-Chain Stubs
I am designing a RS-485 network and would like to know whether the configuration below would work. The transceiver I am using is the Maxim MAX485, with the master ad slaves hardwired to always transmit/receive respectively. My target bitrate is 1 MHz.
The master device would be living on a distribution PCB, the "backbone", with connectors for distributing the differential lines to each stub. The slave PCBs would be daisy-chained along a number of stubs (around 10 of them, which will be kept to a sensible length of about 20cm).
Note that for the sake of using input and output connectors as opposite to screw terminals, I would be routing the differential lines across each of the slave boards.
I am aware that the ideal topology for RS-485 would just be one long daisy chain, but I am trying to combine power injection and data transmission into one shielded twisted pair cable assembly and the topology above is what would work best mechanically for my application.
Do any more best practice design considerations come to mind when configuring such a network with bespoke circuit boards?
AI: The bus backbone is max 20cm and it has ten 1.5 meter stubs connected to it. That is basically a star topology, which is not how RS-485 is meant to be used. It is against best practices already, definitely not recommended, and in fact suggested to avoid.
Depending on your choice of connector you can make the bus linear so even if your physical arrangement is a star shape bus, the bus itself can go linearly via all devices on bus.
The MAX485 output slew rate is not limited so rise/fall times are between 3 to 40 ns, which translates to maximum stub length of 7 to 93 cm according to multiple RS485 appnotes.
Expect problems as you have 150cm stubs and you have basically 10 stubs lumped together.
If driving one unterminated cable looks like 100 ohm characteristic impedance, driving 10 unterminated cables in parallel looks like driving 10 ohms characteristic impedance, and all ten unterminated ends reflect their signal back.
It might be possible to make it work, but it is against suggestions anyway. |
H: Matlab: spectrum analyzer does not display the output from "Sample and hold block"
I try to use the Sample and Hold function, to show its output on the spectrum analyzer. But it gives me this error "Spectrum cannot be displayed for continuous or infinite sample times", while I dont have infinite, not continuous sample times. The scope shows the output just fine thought.
I want the output of my "Sample and hold" block to be shown on the spectrum analyzer.
EDIT:
@Tony Stewart EE75 is right. For some reason the pulse generator for the "Sample and hold" filter behaves like a real pin's output, and if a higher output frequency is used for the trigger, it starts losing its shape.
Here are the settings that can work the simulation just fine (I lowered the trigger frequency to 1900):
And here below one can notice two things:
that I have increased the frequency of the PWM output for the trigger, and the pulse is not square anymore.
Even though I have increased the frequency of the trigger, because I opened a new MATLAB window, the spectrum analyzer works now! So the previous window was bugged.
Someone who had the same issue as me: https://www.mathworks.com/matlabcentral/answers/296993-how-can-i-generate-a-high-frequency-signal-with-simulink
AI: You must have a setup error in Matlab for your external square wave or pulse clock frequency and duration of sample. You show 0 time which appears to be continuous.
The Scope will have a very fast S&H and ADC but you have shown a simple S&H but no specs for clock rate or sample duration.
I can demonstrate a different simulator with a variable 2f to 1kHz sampling clock with just an RC filter and variable sample duration.(d.f.)
Note that unless you over-sample by a great ratio, you will need a Nyquist (anti-alias) sampling-noise-blocking LPF filter. You can see why when the frequency slider is towards the left.
Note that I chose 100 Hz sine and 201 f-min so you could see amplitudes change (Max=...) as Nyquist rate of 2f only preserves 1f content exists but does not preserve amplitude or distortion products unless synchronized somehow in phase or peak detect with the signal.
The switch has a capacitance load so memory errors exist with a transient output on S&H. So it depends on how you do the S&H. This simple method obviously lacks a buffered hold value between samples.
This 2 stage S&H effectively works as another LPF on the spikes from the previous values during sampling. |
H: How to deal with one clock input at the IC when most crystals and oscillators have two pins?
I am having trouble in figuring out how to deal with an IC that only has a single input for the sleep clock. Does one pin of the clock go into the IC and the other to ground, or does configuration vary from device to device?
Datasheet for reference
AI: Don't confuse for example MCU crystals for oscillators. The crystal is part of the oscillator circuit, see for example this (source: wikipedia1))
On a typical MCU, the U1 part is internal and the rest of the components need to be provided by the PCB designer. Which is why MCUs have two pins for this. Some MCUs have an actual clock output as a separate 3rd pin.
So what you need to do is to provide a crystal oscillator with everything (except the caps) built-in and not just a crystal. They need supply & ground and give a single clock output, so typically 3 pins (or rather in practice 4 pins where one is dummy). The oscillator datasheet will state which cap values that are required. Connect the oscillator output to your IC's clock input and there you go.
1) By Original: Thann75 Vector: Omegatron - Own work based on:, CC BY-SA 3.0, https://commons.wikimedia.org/w/index.php?curid=2188865 |
H: I designing a pulse generation circuit using capacitor and resistor but my output is not coming as expected
I am designing a pulse circuit which I will be feeding to a comparator. I am using a combination of resistor capacitor and diode for generating positive edge triggered pulse as shown in the below figure (encircled in the yellow color). I want some guidance how to design such circuit to generate that kind of pulse.
AI: You don’t know how to design it, so how can you claim that you can design it just using a resistor, a capacitor, and a diode?
What does it mean that the circuit is edge-triggered? Please draw the. input to the circuit as well as the output you expect. Don’t just paste some 3rd party picture - draw it yourself, even by hand on paper, take a picture, and edit the question to include the information.
Generally, for edge triggering, you’ll want the functional equivalent of a flip-flop: once the flip-flop’s output goes high, it charges a capacitor through a resistor. Then the comparator triggers and re-sets the flip flop, as well as discharges the capacitor. All this is done in the 555 timer, so you can just use that IC.
As for constraining the end-of-charge threshold by a cycloid waveform (the “half circles” on your picture): that is an interesting problem to solve if you want to limit yourself to purely analog techniques. In the world of analog computing, this would be usually solved using a diode-based function generator block that takes “time” as an input voltage (ramp), and outputs the cycloid. You can get reasonable precision that way, even though it is an approximation.
Otherwise, you’d need an inverse-cosine function to convert time into angle, and feed that angle into a sine function to get the cycloïdal shape. This can be done precisely without approximation, but only in discrete time. First, time input is a voltage ramp. Then, a fast cosine waveform is synchronized to two sawtooth waves that represent the angle: one with 0 degree offset for cosine, another with -90 degree offset for sine. When the cosine matches the input ramp, the 0 degree ramp is sampled - that’s the inverse cosine, or the angle at a given point in time. Then when the inverse cosine sample matches the sine sawtooth, the cosine sample is taken - that’s the sine, or the vertical coordinate of the cycloid. This discrete-time sampled cycloid generator can be implemented rather simply using op-amps, comparators, and analog switches (or transistors), and with due care can be quite accurate - better than 0.1% error for sure. It’s not a trivial endeavor though, and it requires precision parts. |
H: BJT: definition of "edge of saturation"
The book Sedra/Smith (Microelectronic circuits) tells in chapter 5 the following:
My question: I found no statement on why the EOS is defined by the point where vc < (vb - 0.4V).
Seems like other books just define saturation at where vc < vb, and I even saw vc < (vb-0.7V) somewhere else.
Is the 0.4 volts just some value in the region between 0 and 0.7V of forward bias of the CB diode?
AI: It has to do with practical teaching vs theoretical, I suppose. For Silicon PN junctions, pretty much anything below a forward-biased magnitude of \$400\:\text{mV}\$ produces currents that are typically less than \$1\:\mu\text{A}\$. (You can work this out using the Shockley diode equation and a couple of DC parameters for it.) So for many practical circuits, the BC junction must be forward-biased by more than \$400\:\text{mV}\$ to produce a meaningful effect. However, technically, there is some forward-biased current even at a forward-biased voltage difference of
\$200\:\text{mV}\$ (and less.) So, if you want to get technical about it then saturation begins when the BC junction is forward-biased, at all. It's just that the effect isn't enough to worry about in most cases.
Where you draw the line will depend upon whom you are speaking to and the subject you are discussing. If you are discussing the impact on active-mode \$\beta\$, then you probably won't notice an effect on it until the forward-biased voltage difference is
\$\ge 400\:\text{mV}\$. So the DC biasing point won't be impacted much, either. So the operating mode of the BJT is still, for all intents, the same. Yet, from a more technical standpoint, the BJT is moving out of active-mode behavior and towards conditions that will look increasing like saturation behavior. And that fact may also be important to recognize and anticipate, should it "get worse."
In a CE stage design without the application of global NFB, I would tend towards making sure that the BJT's BC junction is always reverse-biased through-out its range of behavior over signal, sufficiently so that the CE voltage difference magnitude is \$\ge 2\:\text{V}\$. Because it's "healthier" to make sure you reserve some margin. (The linearity of active mode, assuming the local NFB due to an emitter resistor, starts to deteriorate the more you pare this margin, for example.) |
H: Why is high open loop gain needed for an Op-Amps virtual ground?
In books, I often see that they state that the op-amp has a virtual ground property when it has a high open-loop gain and in a negative feedback configuration.
First Question: The negative feedback part makes sense to me, but why is it necessary to have a high open loop gain to satisfy the virtual ground property?
Second Question: How does steady-state error from control theory tie into op-amps? Increasing open-loop gain improves the error? I'm trying to make a link between the two courses.
AI: Scenarios 1 and 2 below apply when the op-amp is either open-loop or closed-loop: -
If the open-loop voltage gain is only 100 (for instance) then the voltage difference between the two op-amp inputs needs to be 10 mV to produce 1 volt at the output. 100 mV is needed to produce 10 volts at the output.
If the open-loop voltage gain is 10,000 then the the voltage difference between the two op-amp inputs need only be 0.1 mV to produce 1 volt at the output. 1 mV is needed to produce 10 volts at the output.
In the second scenario, the difference between the op-amp inputs is mainly less than 1 mV and you would say that this is much more of a virtual earth/ground than the first scenario. And for many op-amps (at DC), the open-loop voltage gain is in the order of 100,000 to 1,000,000.
How does steady-state error from control theory tie into op-amps?
Increasing open-loop gain improves the error? I'm trying to make a
link between the two courses.
An op-amp is a control system and so it applies 100%. |
H: Why does MOSFET N back to back switch work?
Please consider an exemplary back-to-back MOSFET N driver IC (drew the body diodes of M1 and M2 for clarity):
I understand how is it possible to turn off the M1/M2 transistors from the gate voltage point of view (since its higher than VIN voltage due to the internal charge pump). What I do not grasp is why do the transistors turn on when the gate voltage goes high and VIN voltage appears, since the sources of the transistors are "floating". The sources potential is not fixed to voltage value (lower than the gate voltage) before the M1 starts conducting. Question is, why does it start conducting in the first place? How to understand this phenomena?
AI: FETs have a neat party trick: they can conduct in both directions. And, a bias on gate-to-drain will turn on the FET as well as the more customary gate-to-source.
In this circuit then, the left-hand FET will be on, bringing up the source for both: the two sources will be at the same voltage as the left-hand FET drain. So the right hand FET will also be on.
This slide deck gives more information about how FET biasing works. tl, dr: it’s about gate to substrate bias. https://alan.ece.gatech.edu/ECE3040/Lectures/Lecture24-MOS%20Transistors.pdf
One detail: the IC brings the gate voltage above both FET drain and source voltages since n-FETs are being used. This ensures that turn-on will occur, since Vgs is higher than threshold. |
H: What can this CAN bus like protocol be?
I am currently probing what seems to me the CAN bus twisted pair of my car. But the signals are not what I expect. One of the pair is like a typical CAN HI signal, however the idle state is a 0V and a logical high is 5V. The CAN LO signal on the other hand is idle at 5V and a logic high at 0V. Therefore, this is not the standard differential signal with 2.5V common mode. My oscilloscope can however correctly decode this as a CAN bus signal and read the packets etc.
My question is this some variant of the CAN bus protocol?
AI: The bus is likely ISO 11898-3 low-speed or fault-tolerant CAN bus, as the voltages and bit rates match the specifications for it. |
H: Power supply noise reduction
I am new to electrical Engineering and would like to know wich noise reduction filter ist better for use in audio equipment.
Some decalcifications:
VBUS --> 5V from usb-port
GND --> Ground from usb-port
INT_GROUND --> Internal ground I use for all my components (I just like to separate these two grounds)
Output Voltage is 15V
The first one is not my own design. I found it on the internett without description.
The second one was made by me using the datasheet of my NMA0515SC
Im also confused when to use polarized capacitors. Or does it even change something?
As @Fred Cailloux can't open the sheet i will upload a screenshot of the used page:
AI: To understand any filter design you need to have expectations of what is signal, noise, SNR, voltage, current, and Impedance in terms of amplitude and f. Then we can ask some better questions. But realize ceramics are better than e-caps but smaller in value due to lower density so work only at the HF range.
You need to learn/think about why and component properties to understand. I can't tell you everything here, so let's consider better questions. Search this site for clues on ESR, DCR for ceramics and e-caps
Why do you ask when Murata advertises this ?
Since the noise is ultrasonic, >=90 kHz in this +/-15V 1W case, why do we care about HF noise you can't hear when all we care about is SNR and THD?
This can be understood with training on impedance ratios vs frequency and component types. We know that faster rise times means higher bandwidth so for more low pass attenuation you want a bigger T=RC or smaller f cutoff.
If you ignore series and shunt resistor ratios for the moment and the resonant effects of high Q, (but expect the output resistance to be ~ <=1% of Vo/Imax) we can compare 1st order RC filters at some f with LC filters. We see that the dual 15V 1W regulators switch at 90kHz and expect current step pulse noise on both the input and output to exist at the frequency and decline for each f decade about this.
\$f_{-3dB}=\dfrac{1}{\sqrt{2\pi LC}}\$
\$f_{-3dB}=\dfrac{0.35}{RC}\$
We know that Ceramic caps have much higher bandwidth (lower ESR*C) than e-caps but e-caps have lower ESR with higher C or a constant RC=T within 1 family and lower ESR with larger size and voltage ratings.
You need to learn/think about why and component properties to understand. I can't tell you everything here, so let's consider better questions.
When the amplifier responds to higher frequency noise and has some distortion or non-linearity, then sum and difference frequencies occur and are called Inter-Modulation Distortion. (IMD) The difference frequencies you can hear between the harmonics of audio and the switcher frequency. How much, depends on your ear's sensitivity to distortion < 10% or < 1% or < 0.1% and sound quality you expect.
How does Murata get a 1W SMPS down to 8 mVpp typ., 15 mVpp max. output noise ? (for 15V version)
Answer: By additional filtering for Diff Mode (DM) Noise and eliminating measurement errors with common-mode noise (CM)
When you test for differential noise, all common mode noise must be blocked out. Murata's method adds some features not always needed but is perfect for this test.
The coax wrapped through a large ferrite ring acts as a BALUN or CM choke (T1) to reduce CM noise.
The series 450 ohm is optional but acts as a 10:1 attenuator. The series cap blocks DC to the 50 Ohms in DSO.
The added ceramic and tantalum cap lower the output impedance vs f.
When two low ESR caps with T=RC each are put in parallel C_equiv=2C and ESR_eq.=ESR/2 thus impedance is 50% lower but at the same breakpoint as we know within a family of parts T=ESR*C is fairly constant.
This is an improvement at the expense of more area on the board instead of height with bigger and usually more expensive parts.
Smaller and more parallel is better to keep the parasitic inductance low and Self-Resonant Frequency (SRF) higher than the noise range. But beware there are interactions that can produce high Q resonances with the wrong combinations of parts and trace inductance in higher power supplies. (nuf said)
Recommendation
Follow Murata's advice , not something else for no reason. 2.2mF is overkill and costs much more as a tradeoff for similar effect.
Here I ignore the ceramic which becomes effective in the 100k to > 1MHz region
(Warning you cannot afford a 2200 uF tanalum cap with 20m ESR. Tantalums are 0.5 ohm cost $164 but aluminum electrolytic are >$6 38 mohm. 25V 2.2mF )
We can't compress a book on EMI into 1 page, so I hope this raises some new questions for your searching for answers.
But remember this.
If you do not include ESR and DCR in your simulation, it won't be accurate.
This causes the impedance ratio plateau in the above .
Sanity check on cost vs T=ESR*C
Digikey $164.08 (1)
2200 µF Hermetically Sealed Tantalum Capacitors 25 V Axial, Can 500mOhm @ 120Hz
TDK ALum Cap $16 (1)
(overkill)
Ripple Current @ High Frequency 8.5 A @ 10 kHz Impedance 19 mOhms 65Vdc
BONUS
My Simulation with selectable filters with 4 switches and lots of combinations |
H: Is it better if each integrated circuit has a dedicated voltage regulator?
I have a circuit consisting of an ESP32 microcontroller and some integrated circuits. Is it better if each integrated circuit has its own voltage regulator?
Example:
Full circuit after modification :
AI: The only reason to do what you are doing is the current is too high for one linear regulator but you insist on using only linear regulators.
If your goal is noise, then using separate linear regulators is one step but sufficient on its own because the linear regulator's bandwidth, though higher than a switching regulator, is not nearly fast enough to respond to high frequency noise which will pass straight through the regulator in both directions. Filtering needs to be added as well in that case.
but wouldn't there be confusion between the integrated circuits as I differentiated the GND for each circuit as well
Unless the circuits are simply not interconnected or are connected through methods providing galvanic isolation, GND and AGND must connect together somewhere. The circuit will not work otherwise. The distinction between GND and AGND is more a matter of physical PCB layout than anything else.
For example, if you have noise sensitive circuitry using AGND, and noise insensitive circuitry using GND, the AGND and GND still need to be connected together somewhere unless the sensitive and insensitive circuits were not interconnected at all or only interconnected through galvanic isolators. Signals running between the two circuits over non-galvanically isolated connections require a return current path which they won't have if you leave GND and AGND disconnected.
But you don't want the GND currents of the insensitive circuitry flowing in the AGND currents of the sensitive circuitry so you clump the insensitive circuitry together and the sensitive circuitry together and connect the GND and AGND together. That way, insensitive circuitry can communicate amongst itself and the ground currents don't need to flow under or near the sensitive circuitry.
In practice when you do this, you don't usually make separate ground plane for GND and AGND with a small bridge in between to connect them. This is because if you run an interconnection over the gap in the ground planes, the signal must flow in a big loop to the bridge connection between ground planes to return. Big loops have high inductance and current flowing that way makes lots of noise.
So you must only route interconnections over the bridge where the planes connect, or more commonly, you just make one big plane but keeps the sensitive and insensitive circuits separated. |
H: Multiple voltage sources connected to Attiny85
I have a circuit with a Attiny85 micro controller that is powered by a solar cell and a capacitor (10F 3V8). When I want to change the code on the micro controller I have to attache a USB programmer that operates (and provides) 5V. Since the circuit will be soldered I wont be able to detach the capacitor.
My question is if it is possible to have multiple power sources in a circuit and what I should do to protect the capacitor when introducing the 5V power source to the circuit.
This is the circuit I'm talking about:
AI: Thank you for all your help. I found a solution that suits me based on your recommendations:
I use a USBtinyISP for programming and I can remove a jumper to prevent power delivery to the board. That means that as long as the capacitor is charged I can program the micro controller.
USBtinyISP [..] uses a level shifter so that if the jumper is not in place, it will use whatever the target voltage is [..]
While I have the hardware on a breadboard (or capacitor is empty) I use a USB to TTL adapter for 3.3V power delivery (and as connection for the serial monitor output).
Please let me know in case you think my solution has some flaw. I don't usually work with electronics. |
H: Snubber circuit for electromagnet
I have run into the same problem described here and here, when I added diode to electromagnet. Basically, the magnet still holds with about 20kg force several minutes after removing power. The mechanical solution of leaving air gap or adding a "peel-off" spring is not plausible due to design constraints. So, I need a snubber circuit that will protect relay contacts why still de-energize the magnet rapidly.
While looking for the solution I've stumbled upon this answer, listing many possible methods. Not having any experience with powerful electromagnets I can't decide which one would be the best for this particular setup (24V 14W magnet, 30V 10A SRD-05VDC-SL-C relay).
At this moment I am leaning towards either rectifier + zener or RC + MOV combination. Any advice, please?
UPDATE
I've confirmed that the problem is residual magnetization, not back EMF, just as @DKNguyen and others suggested. After disconnecting power I also disconnected diode and the magnet was still holding. Apparently the initial experiment without diode was done with heavy (~200kg) load that was enough to hide the magnetization.
So, I am going with RC snubber, hoping that oscillations will provide sufficient demagnetizing effect. Maybe combined with MOV if initial amplitude is too high.
AI: Snubbing is not a problem at all.
The core is magnetized. To turn such an electromagnet fully off, you need to apply a demagnetizing waveform.
Typically, you’d attach a capacitor in parallel with the coil, and then disconnect the power source, eg. using a small relay, vs. a mosfet or a transistor that would go into reverse conduction.
The current will decay as a sinusoidal waveform with exponential envelope. It will demagnetize the electromagnet. That’s how it’s typically done, and it’s very simple. |
H: Is this avalanche rugged MOSFET suitable for linear operation?
I would like to create an active load which draws current(4 to 6A) from a 12V battery. Unfortunately, the shipping costs and delivery times have prevented me from buying Linear FETs directly from well known manufacturers. Instead, I have found this interesting MOSFET in a local electronics shop; the SFH154 which is being advertised as an avalanche rugged advanced power FET. My question is, can this MOSFET be safely used as an active load ( with a feedback loop to prevent thermal runaway using a microcontroller DAC to provide VGS) or are there other factors to take into consideration? Also, would a CPU fan equipped heatsink be a suitable choice for cooling?
Note: this MOSFET is somewhat expensive and I would rather not see it turn to coal.
AI: The part is obsolete: no wonder it is expensive, you're buying old stock, or (worse) relabeled or recovered parts.
Yes, it could be used in linear mode, and your current and power are well within the listed limits. 14V*6A = 84W is less than the rated power (~100W). Less if the load voltage is more than ~ zero.
A high power FET is designed to spread the current across the FET body. Switching FETS are designed to do that only at full 'on' voltage, so their pulse current limit is much less when operated in linear mode. But when operated a low power with continuous current, the FET heats evenly, and the current spreads correctly. There is no indication that this old FET will fail at such low currents.
The junction-to-case thermal resistance is ~ 0.8. At 84W, that would be ~ 70C. Derating 204W at 1.34, the new power rating is around 100W, and you would need a large heatsink to keep the case temperature at 25C, and you need to be sure the FET mounting is good.
However, you still have a little room for junction-to-ambient. And if you aren't running the battery fully charged, it will be less than 14V, and if your load voltage is more than zero you have even more room. |
H: Understanding Spec sheet of IC
I'm having trouble understanding the spec sheet of this shift register. What I want to do is to connect a (generic red one, I don't have any specs) LED which will approximately use 15-35 mA to the IC.
I am currently doing this as seen in the first scheme. The output pins of the IC (\$Q_a\$ to \$Q_d\$) are each connected to NPN transistors, which then are each connected to LEDs.
The LEDs share a common resistor (850 Ohm). The power supply delivers 5V. I added the the transistors because the spec sheet states (page 6) the maximal "High-level output current" is -0.8 mA (and it states no minimal current). Since the LEDs need more than that, I added the transistors to augment the current.
My question is how to interpret the sign in -0.8 mA. Does this mean that I can push into the IC at most 0.8mA while its output is high (and that I can let out as much as I want), or does this mean that 0.8 mA is the most the IC can let out of this pin?
Am I correct that I could simplify my schematic into the second one (removing the transistors), should the first theory be right?
AI: When a datasheet specifies a current in that way it doesn't mean that is the maximum the chip capability. It means that is the test condition.
The negative sign does indicate the current flow direction. Minus means current flow out of the chip.
A standard TTL input as defined about 50 years ago required a worst case sinking current of 1.6mA and a sourcing current of 40uA. Typically outputs were designed to be able to drive 10 of those giving a test condition of 16mA for the output low condition and 400uA for output high at 2.4V. Some devices were designed for a larger drive output such as 20. Since the 70's the required current to drive a logic input has reduced greatly; first with low power bipolar devices to a few hundred microamps and then with CMOS to sub microamp levels. Even though the DC current needed is very low the capacitance of wiring and gate inputs can still require significant drive capability.
I would not recommending designing a circuit with such an old device. There are more modern equivalents such as the CD74HC194 or even directly from microcontroller outputs.
With your circuit description you don't need to drive 15-35mA anyway. With an 850 ohm (why 850 Ohm? that is non-standard) resistor to the 5V supply the current will only be about 3-4mA. That will illuminate a modern LED brightly. Normally I would use a 1k resistor for that application and drive directly from an MCU.
Also having a shared resistor implies that only one LED at a time is lit - is that what you want? A separate resistor for each will allow the LEDs to be controled individually. The shift register already allows independent control of the LEDs.
Lastly, unless there is a reason it is more common to connect the LED with resistor to the supply rail and use the logic device to drive its output low to illuminate the LED. Partly this is convention from when ICs could drive low more powerfully than they could drive high.
With separate resistors per LED it doesn't matter if the resistor or the LED connects to the supply. It may be more convenient to connect the LEDs to the supply as it allows a single wire to connect the LEDs back to the supply with separate wires for the other ends, 5 wires in total. If you connect the resistors to the supply you would need 8 wires. This is useful if the LEDs are mounted on a panel and not on the circuit board. |
H: Battery capacity and parallel vs. series battery connections
Say you have 4 200 Ah 12 V batteries connected in parallel, this as I’ve come to learn increases the amp-hour value and not the voltage, and say you have another system same as that but connected is series this time, this increases the voltage and not the amperage.
So for the first system you will be getting a total of 800 Ah at 12 V (I’m guessing this means you need a 12 V inverter right?)
And for the second one you will get 200 Ah at 48 V (and for this also I’m guessing you will need to have a 48 V inverter to run the batteries).
Now what is confusing me is why choose one over another?
If I have the first one the inverter is going to convert this to 220 V AC for me anyway and same for the second one, except for the second one as I’ve come to learn (btw I apologies and a newbie) you will be getting less battery runtime because the ah rating is lower but still that same 220 V AC power. I’ve been doing a lot of research and the terms themselves confused me a bit.
At the end I just need the basic knowledge of what works with what, why and how, a question of powering a house with 15 kW of load for 24 hours from just batteries? What would I need and what would be the best and most efficient way to acheive this and get the most out of the equipment and investment.
Sorry for the confusion.
AI: Why wire batteries in series vs parallel?
Series means higher voltage and lower current. Lower current is good because it means dramatically thinner wire on long distances, especially at low voltage. 2x voltage means 1/2x current for the same useful power. 4x voltage means 1/4x current for same useful power.
However, higher voltage means danger. DC voltage starts being rather feisty as voltage gets higher, so switching it becomes much more complicated and dangerous. 24V is manageable but 48V starts to get interesting. Like this and this. Once DC starts arcing, it cannot be reasoned with, it does not know pity or remorse or fear and absolutely will not stop, ever, unless killed at the source.
I’ve come to learn you will be getting less battery runtime because the ah rating is lower but still that same 220 V AC power.
No, useful power is volts x amps. If you double volts but halve amps, you have exactly the same useful power. (except for voltage drop of course).
Another way of thinking of it, a battery is a box that can hold so many watt-hours. So 12 volts x 200 amps = 2400 watt-hours. It doesn't matter how you stack them, the boxes hold the same amount. Four batteries is 9600 watt-hours, or 960 watts for 10 hours for instance.
...Except lead-acid batteries are rapidly degraded by deep cycling, so you'll destroy the batteries in a few dozen cycles if you dip them that deep. A lead-acid should only be drawn down to about 70% charge (i.e. from 100% to 70%, so 30% useful) which means 2880 useful watt-hours in your pack.
At the end I just need the basic knowledge of what works with what, why and how, a question of powering a house with 15 kW of load for 24 hours from just batteries?
15KW is 15,000 watts. Multiply by 24 hours and you have 360,000 watt-hours. Obviously that plan isn't going to work.
Now if you're politically anti-solar and rootin' for Putin, congratulations. You have proven that solar is totally impractical! Now you can shout down all those wrong people on the Internet who claim to be doing off-grid solar homes with great success. Fake news!
On the other hand if you're serious, let's figure out how they actually manage it. Because they actually do.
What would I need and what would be the best and most efficient way to acheive this and get the most out of the equipment and investment.
Well.
Here's the trick.
Everybody wants a green thing that just "plugs in" where the black thing went. The farmer wants to farm the same black way, but with organic fertilizers and organic pesticides and organic Roundup Ready seed. What organic farming actually is, is doing a lot of things in a different way so that stuff is not required.
So it's the same thing here. One wants to keep the horribly insulated house, the COP 1.0 electric baseboard heaters, the same "2.0 SEER" 1-hose portable A/C units in every room, inefficient dryer that ejects conditioned air out of the house, etc. All that crud is built to be cheap and assume utility power is cheap. But batteries aren't, so you have to consider the cost of stupid numbers of batteries to power all that wasteful crud, vs. better stuff.
First, you insulate the house for all it's worth, and if possible include passive solar design. Second, you use an efficient, 38 SEER heat pump for the air conditioning, increasing A/C efficiency by a factor of nineteen, that with the insulation means you are using 1/50 the electricity you used before for A/C. Even though the insulation and heat pump is expensive, it is cheaper than 50 times as much battery pack.
You go through an efficientify every single appliance. Resistive electric dryer, ejecting air outside? Nope, heat pump dryer because that unit is cheaper than buying more batteries to run the ratty old dryer. Refrigerator? Crunch the same math, maybe, maybe not. Cable box that sits there sucking 50 watts 24x7? Cut the cord.
Every single load gets rationalized... and suddenly you don't need 15,000 watts anymore, you need more like 500. And now battery is a player.
And then, forget the low-capacity short-life lead-acid batteries and go with electric vehicle batteries out of wrecks, such as a Tesla Model S blade, 5000 usable watt-hours for about $1000.
That is a bit of an up-front investment, but if you can't afford to replace an inefficient appliance, how do you expect to buy all the batteries you'd need to run it? |
H: I can't figure out what this circuit does
I'm an electrical engineering student.
The picture below shows a circuit that I found in some old notes but I cannot figure it out.
I have been at it for the last 2 days but to no avail.
Some things that are known for this circuit are:
Beta is close to infinity.
All transistors are the same.
All transistors are in the active region.
I reasoned that since beta is so large, the base current is almost 0. Therefore, it can be ignored. By that assumption the emitter current must equal the collector current. The problem is that I cannot express a relationship that ties Io and all the other currents together.
Could someone please help?
EDIT: Here's what I've done so far.
EDIT No 2: My reasoning on voltage drops.
AI: To Start
Let's start with your diagram and work outward from it.
I'll add a few thoughts:
Orange box around diode-connected \$Q_1\$. I'll call the voltage across it \$V_{_{\text{D}_1}}\$ to emphasize its diode-nature.
Orange box around diode-connected \$Q_2\$. I'll call the voltage across it \$V_{_{\text{D}_2}}\$ to emphasize its diode-nature.
\$I_{_{\text{R}_1}}\$: green-labeled current.
\$I_{_{\text{R}_\text{E}}}\$: blue-labeled current.
\$I_{_{\text{B}_3}}=0\:\text{A}\$: orange-labeled current. Obviously zero, since these are infinite \$\beta\$ BJTs.
Development
As \$I_{_{\text{R}_1}}\$ is the same current through \$Q_1\$ and \$Q_2\$ and \$R_2\$ (the green arrow), it follows therefore that \$V_{_{\text{D}}}=V_{_{\text{D}_1}}=V_{_{\text{D}_2}}\$ and \$I_{_{\text{R}_1}}=\frac{V_{_\text{CC}}-2\,V_{_{\text{D}}}}{R_1+R_2}\$.
Now, we know that the base voltage of \$Q_3\$ must be set by the base/collector voltage of \$Q_2\$, which is \$I_{_{\text{R}_1}}\,R_2+2\,V_{_{\text{D}}}\$. Therefore, it also follows that:
$$\begin{align*}
I_{_\text{O}}&=\frac{I_{_{\text{R}_1}}\,R_2+2\,V_{_{\text{D}}}-V_{_{\text{BE}_3}}}{R_{_{\text{E}}}}
\\\\
&= \frac{\frac{V_{_\text{CC}}-2\,V_{_{\text{D}}}}{R_1+R_2}\,R_2+2\,V_{_{\text{D}}}-V_{_{\text{BE}_3}}}{R_{_{\text{E}}}}
\\\\
&=\frac1{R_{_{\text{E}}}}\left[V_{_\text{CC}}\frac{R_2}{R_1+R_2}-2\,V_{_{\text{D}}}\frac{R_2}{R_1+R_2}+2\,V_{_{\text{D}}}-V_{_{\text{BE}_3}}\right]
\\\\
&=\frac1{R_{_{\text{E}}}}\left[V_{_\text{CC}}\frac{R_2}{R_1+R_2}+2\,V_{_{\text{D}}}\left(1-\frac{R_2}{R_1+R_2}\right)-V_{_{\text{BE}_3}}\right]
\end{align*}$$
Now, I've avoided a few details. The value of \$V_{_{\text{D}}}\$ is actually a function of its current and temperature. So it is really \${V_{_{\text{D}}}}_{\left(I_{_{\text{R}_1}},\,T\right)}\$. Similarly, since all the BJTs are identical, we can say that \$V_{_{\text{BE}_3}}={V_{_{\text{D}}}}_{\left(I_{_{\text{O}}},\,T\right)}\$.
So:
$$\begin{align*}
I_{_\text{O}}&=\frac1{R_{_{\text{E}}}}\left[V_{_\text{CC}}\frac{R_2}{R_1+R_2}+2\,{V_{_{\text{D}}}}_{\left(I_{_{\text{R}_1}},\,T\right)}\left(1-\frac{R_2}{R_1+R_2}\right)-{V_{_{\text{D}}}}_{\left(I_{_{\text{O}}},\,T\right)}\right]
\end{align*}$$
Sensitivity
The sensitivity equation comes from an easy to understand concept. You may want to know how much something changes when something else changes. But for engineering purposes, you really want to know how much something changes as a percent of its current value when something else changes by some percentage of its current value.
This is expressed mathematically as \$\frac{\%-\text{change}\: P}{\%-\text{change}\: Q}=\frac{\frac{\text{d}\, P}{P}}{\frac{\text{d}\, Q}{Q}}=\frac{\text{d}\, P}{\text{d}\, Q}\frac{Q}{P}\$.
If you know that, you can predict the sensitivity of your instrument. In this case, we'd like to know this: \$\frac{\%-\text{change}\: I_{_\text{O}}}{\%-\text{change}\: T}=\frac{\frac{\text{d}\, I_{_\text{O}}}{I_{_\text{O}}}}{\frac{\text{d}\, T}{T}}=\frac{\text{d}\, I_{_\text{O}}}{\text{d}\, T}\frac{T}{I_{_\text{O}}}\$.
For typical small signal BJTs, the variation of their BE junction voltage vs temperature is anywhere from \$-1.5\:\text{m}\frac{\text{V}}{\text{K}}\$ to \$-2.4\:\text{m}\frac{\text{V}}{\text{K}}\$ (this isn't constant over temperature for a specific device, by the way.) I honestly don't know if there is a standard symbol for this. But let's call it \$k_{_\text{be}}\$. This will have to be calibrated for any given BJT.
So, as an approximation we can say that \$\frac{\text{d}\,V_{_{\text{D}}}}{\text{d}\,T}=\frac{\text{d}\,{V_{_{\text{D}}}}_{\left(I_{_{\text{O}}},\,T\right)}}{\text{d}\,T}=\frac{\text{d}\,{V_{_{\text{D}}}}_{\left(I_{_{\text{R}_1}},\,T\right)}}{\text{d}\,T}\approx k_{_\text{be}}\$.
This allows us to say:
$$\begin{align*}
\frac{\text{d}\,I_{_\text{O}}}{\text{d}\,T}&\approx \frac1{R_{_{\text{E}}}}\left[k_{_\text{be}}\left(1-2\frac{R_2}{R_1+R_2}\right)\right]
\end{align*}$$
And if we set \$M=\frac{R_1}{R_2}\$, then the sensitivity expression is:
$$\begin{align*}
\approx k_{_\text{be}}\frac{T}{I_{_\text{O}}\,R_{_{\text{E}}}}\left[\frac{M-1}{M+1}\right]
\end{align*}$$
Worked Example
I just dumped in a model into LTspice and found that \$k_{_\text{be}}=1.75\:\text{m}\frac{\text{V}}{\text{K}}\$, examining temperatures going from \$300\:\text{K}\$ to \$303\:\text{k}\$, for a particular device I'd like to experiment with.
So, at \$300\:\text{K}\$ this works out to:
$$\begin{align*}
\approx \frac{525\:\text{mV}}{I_{_\text{O}}\,R_{_{\text{E}}}}\left[\frac{M-1}{M+1}\right]
\end{align*}$$
Let's assume that \$I_{_\text{O}}=I_{_{\text{R}_1}}\$ so that the base-emitter voltage differences are the same throughout the circuit. That's probably a helpful idea. And let's assume \$I_{_\text{O}}=1\:\text{mA}\$ and that the base-emitter voltage difference is then \$650\:\text{mV}\$. Finally, let's assume a sensitivity where the first factor (before applying \$M\$) is \$0.5\$, so that \$I_{_\text{O}}\,R_{_{\text{E}}}=1.05\:\text{V}\$ and therefore \$R_{_{\text{E}}}=1.05\:\text{k}\Omega\$. We can also then work out that \$R_2=400\:\Omega\$. (I won't worry, for now, about standard resistor values.)
With \$V_{_\text{CC}}=5\:\text{V}\$, I find that \$R_1=3.3\:\text{k}\Omega\$. This makes \$M\approx 8.25\$ and therefore the fully calculated sensitivity is now slightly less than \$0.5\$, or \$\approx 0.39\$. This means that I should expect to see, for a 1% change in temperature from \$300\:\text{K}\$ to \$303\:\text{K}\$, a change in current going from \$1\:\text{mA}\$ to \$1.0039\:\text{mA}\$. I'll use a collector resistor of \$2.2\:\text{k}\Omega\$. So I'd expect to see a change at the output of \$3.9\:\mu\text{A}\cdot 2.2\:\text{k}\Omega\approx 8.5\:\text{mV}\$.
Here's the LTspice schematic and output run:
The difference is about \$8.32\:\text{mV}\$, which is pretty close to prediction.
There's more to think about. But perhaps this gives a starting point?
I forget to check on the currents vs those used in designing the circuit. Let's look at the currents in the two legs, over temperature, versus the design line of \$1\:\text{mA}\$:
That also looks remarkably good. Keep in mind these are ideal BJTs. But, given that, things appear to work closely to what's expected. Also, note that the magenta curve shows that my estimate of \$650\:\text{mV}\$ is approached only at the higher temperature, \$303\:\text{K}\$, where the currents are exactly as designed. Had I designed for \$\approx 652.5\:\text{mV}\$, the currents would have crossed in the middle of the graph. |
H: VoltSecond equations for equivalent buck-boost of flyback
Here is the equivalent buck-boost of flyback converter:
I proved the Volt-Second in a switch-on mode that agrees with the book result (n=22.86.)
In switch-off mode (regarding the above table):
$$t_{off}=(1-D)/f=2.94us$$
$$V_{off}=V_{diode}+V_{OR}=n*V_{D}+n*V_{o}$$
Where \$V_{o}=5V\$
Thus:
If I assume (as we assumed the switch has no drop voltage) \$V_{D}=0V)=>Voff=n*V_{o}=114.3\$ and
\$Et=Voff*t_{off}=114.3*2.94us=336us\$ which is not equal to 473us.
If I assume \$V_{D}=1V=>Voff=n*V_{D}+n*V_{o}=22.86+114.3=137.16\$ and \$Et=Voff*t_{off}=137.16*2.94us=403us\$ which is not equal to 473us.
Where is my mistake?
AI: At equilibrium or steady-state and in CCM operation, the dc transfer characteristic of the isolated buck-boost converter is \$V_{out}=V_{in}\frac{ND}{1-D}\$. From there, you can extract the operating duty ratio and determine the volt-seconds linked to the on- and off-time duration. At steady-state, they should be equal:
In the equation, \$N\$ characterizes the transformer turns ratio \$1:N\$ and, if made 1, you can determine the values for buck-boost converter since the flyback derives from this structure. |
H: Coding and SNR gain
How does coding reduce the amount of SNR required to detect data for a certain modulation and at a certain bit error rate and does that imply that coding reduces noise power?
AI: How does coding reduce the amount of SNR required to detect data for a certain modulation and at a certain bit error rate
This is basically asking for an introduction to channel coding theory; since that's out of scope, and would be better researched with a basic textbook / website than asking here, I'll just give a very condensed look on it:
Coding makes \$k\$ bits become \$n\$ bits, with \$n>k\$. This means there's redundancy added to the data. This means you will push fewer actual data bits through the channel in the same time!
But: It means that from this redundancy, you can correct error that were made due to noise. So, you can live with more noise.
So, while you reduced the rate of bits going through the channel, a well-chosen code will increase the rate of bits that go through without error.
and does that imply that coding reduces noise power?
No. |
H: Negative to chassis or separate wire?
In automotive applications typically battery negative is connected to the chassis, right. This makes the chassis be at the same potential as battery negative, but when completing a circuit, ultimately the charge needs to return back to the battery. Bearing in mind that the chassis is made out of steel and the return path could be well within 4-5m range, does this increase the overall resistance of the circuit?
I'm assuming carmakers don't care about this since they have "unlimited" power, but in my case I'm running a 1kW electric motor (40+V) off of a (rather small 500Wh) battery, so would it make sense to run an additional copper trace to my motor negative instead of using the chassis?
AI: Bearing in mind that the chassis is made out of steel and the return path could be well within 4-5m range, does this increase the overall resistance of the circuit?
Yes. That's why for any electronics, you don't use the chassis as path but just lie an extra conductor (what's expensive about that is pulling the cable; the extra conductor core is relatively cheap, especially if that means you reduce possible sources of error and hence make your build more reliable).
I'm assuming carmakers don't care about this since they have "unlimited" power,
that'd be news to me,
but in my case I'm running a 1kW electric motor (40+V) off of a (rather small 500Wh) battery, so would it make sense to run an additional copper trace to my motor negative instead of using the chassis?
yes, ground shift due to resistive losses is a thing and problematic. A 1kW electric motor implies 1000/40 A = 25 A, that's not that little.
Problem to consider (if a bit out of scope here): Where do you get those 40V in an automotive application? Are you doing a DC/DC conversion from 12 or 24 V? In that case, having isolated output might have severe safety advantages, as you'd isolate what happens on the higher-voltage bus from the rest of the car. If so, can you maybe safely go even higher? At 220V, 1kW becomes very manageable with cheap cabling. |
H: How will I implement this function with decoder and multiplexer?
Inputs Output
A B F
0 0 C.D
0 1 C
1 0 C+D
1 1 C XOR D
According to the logic input-output relations
a-) Find the simple form of the F logic function.
b-) Implement the F logic function with the decoder.
c-) Implement the F logic function with the multiplexer.
Hello, I found examples on the implementation of the boolean function given on the internet. But I could not interpret this table. What are the C and D outputs, how will I find them and then I will simplify them.
I think it's easy to implement once you find a simple function.
AI: Here an example (case b) you should understand, EE&O.
Made with free microcap v12 |
H: Relation between number of RC networks and phase shift in RC phase shift oscillator
The generalized expression for the frequency of oscillations produced by a RC phase-shift oscillator is given by the formula below
$$f=\frac1{2\pi RC\sqrt{2N}}.$$
Here \$N\$ is the number of RC stages.
The link for the website I have referred is RC Phase Shift Oscillator.
I do not understand how we arrive at this equation. I would like to know the proof for this equation.
AI: There are many ways to determine the transfer function of a cascaded \$CR\$ networks such as the one you've shown. I am using the fast analytical circuits techniques or FACTs as described in my book on the subject. The principle is quite appealing since it describes a way to determine transfer functions with the least possible algebra. In some examples, you can even obtain the transfer function by inspection meaning you read the circuit and infer what its time constants are. This is the idea here, determine the time constants \$\tau=RC\$ (or \$\tau=\frac{L}{R}\$ if you had inductors) of the circuit in various conditions and assemble them to form a well-ordered polynomial expression.
Applying the method to a given circuit means splitting the network in a myriad of small individual sketches, each representing a certain combination. What is cool is that when you've identified a mistake somewhere, you can fix the guilty sketch alone and keep the rest intact. You could not do it with the classic brute-force approach. Let's how these sketches look like:
Once the sketches are done, just look at the resistance offered by each energy-storing element - capacitors in our case - and infer the time constants. You need to determine a certain set of combinations but this is easy to remember:
Then you check the transfer function you have determined with the FACTs against that of the brute-force approach:
To determine the oscillation frequency, cancel the imaginary part and find the formula you want for a 3-stage \$RC\$ network.
Finally, let's check if it works with a quick SPICE simulation where the gain of the amplifier corresponds to the insertion loss brought by the network at the calculated frequency. It is 1/29 in this example. If I amplify by that amount, I have exactly a 0-dB loop gain and a phase lag of 0° at the determined frequency: oscillations can be theoretically sustained according to the Barkhausen criterion. In this circuit, a .IC statement gives me the kick I need to crank oscillations: |
H: How can a DMM measure open circuit voltage?
This question has bugged me for some time now. How can a DMM measure open circuit voltage?
I have a general grasp of how ADCs work. How is an open circuit voltage measured when that should produce a voltage drop because of the battery's internal resistance?
AI: Let's have a look a multimeter mearuring the voltage from a battery:
simulate this circuit – Schematic created using CircuitLab
The battery contains a perfect voltage source and an internal resistance. The multimeter contains a perfect voltmeter (it draws no current) with a large resistor in parallel.
With typical values for the internal resistance of the battery and the internal resistance of the meter, there's no measurable drop across the battery's internal resistance - the measured voltage is the same as the voltage source to three decimal places.
If I change the resistances (quite) a bit, then you can see a voltage drop across the battery's internal resistance:
simulate this circuit
A small coin or button cell could easily have an internal resistance as high as 1000 ohms. Back in the old days when voltmeters were built with hand wound coils for the mechanical movement, it wouldn't be unusual to have a voltmeter with a resistance as low as 40000 ohms.
Those conditions make it obvious that a multimeter does have an effect on the measured voltage.
For modern meters and normal batteries, the effect is unnoticeable.
People speak of the open circuit voltage as the voltage measured with the voltmeter because the difference is too small to matter for most things.
Here's another example:
simulate this circuit
That's a modern multimeter measuring the voltage of a battery with a very high internal resistance.
Does that 1/1000 of a volt matter? Most of the time, no.
Maybe you are experimenting with nano batteries for your nanobots. Such small batteries would have a (very) high internal resistance - so high that a normal multimeter would distort the readings. In that case you'd reach for a (really expensive) specialist volt meter with an input resistance in the gigaohm range - and a specialist to help you make sure that your connections are properly made and shielded to let you measure things that finely.
The circuit diagrams are also simulator models. You can open them in your browser and change the values to see how things work. (The simulator won't work in a smartphone or tablet. You need a laptop or PC with a mouse to use it.) |
H: LLC resonant capacitor RMS voltage and output capacitor ESR calculation
I have a question about the TI LLC document.
On page 25, Select the Resonant Capacitor, I don't understand why it can use this formula to calculate the RMS value. Could someone tell me how to get this formula?
On Page 27, I don't understand why it can use (pi/4)Io2 to get Irect_peak. how to get this value?
AI: The rms value of a periodic voltage waveform affected by a dc (average) value and an ac ripple (rms) is determined by: \$V_{rms}=\sqrt{V_{ac}^2+V_{dc}^2}\$. You thus measure or determine the ac rms ripple value straddling around the dc offset and then apply the formula.
For the LLC, the author knows that the rms ac current in the cap. is 2.6 A. Multiply by the cap. impedance at the operating frequency (resonance) and you have the rms ac voltage ripple across the cap. At steady state, the dc voltage is \$\frac{V_{in}}{2}\$. Apply the definition of the rms voltage and you have your equation of \$V_{Cr,rms}\$:
For the current, at resonance, the dc current leaving the two diodes which splits between the cap. (ac) and the load (dc) is equal to \$I_o=\frac{2I_p}{\pi}\$. You derive this value easily or you can find ready-made formulas for full-wave rectification. From this value, you can extract the peak value. Then, considering a net zero dc current in the capacitor at steady-state, the ac current ripple in the cap is the total ac current minus the output current:
To test these values, I have run a simple example with the SIMPLIS demo. This is an open-loop LLC circuit part of the 60+ SIMPLIS templates you can download from my webpage and the circuit delivers 10 A from a 380-V dc source:
If you run the simulation, you can verify the calculated values with the formulas supplied in the application note: |
H: Op-Amp with current source input
In this op-amp circuit, the output is defined as \$v_o = - i_sR\$.
Question 1
I am slightly confused about how the current flows in this circuit. By the principle of virtual ground, the inverting input is at 0V. The output is at some negative voltage. Hence the current flows from the current source, into the 0V virtual ground, through R and to the negative Vo. Now, at this point - if I consider that the ideal op-amp output stage is just a VCVS with no resistance, then this current should be absorbed into the VCVS source, correct?
Question 2
If I put a resistive load to GND at the output
Will all of the \$i_s\$ current now flow through the load resistor? Or will the VCVS still absorb some current? I am having difficulty understanding that. I understand the VCVS is kind of setting the \$V_{out}\$, but I also know that voltage sources can absorb power. In the first case, the VCVS was taking all the current and absorbing the power, how come that will not happen here?
Question 3
Considering the same circuit with the load resistor at the output. Is the output voltage now defined by \$v_o = -i_ss*(R || R_L)\$?
\$R\$ is connected between virtual ground and \$v_o\$. \$R_L\$ is connected between real ground and \$v_o\$. Does that mean they are in parallel?
AI: if I consider that the ideal op-amp output stage is just a VCVS with no resistance
It means that this ideal model will be capable to provide any current, in any direction (sink or source).
The output voltage is defined by the negative feedback. In the ideal opamp, with no current at the inputs, all the input current goes through the feedback resistor. The output voltage will be whatever necessary to cause the current and keep the inverting pin at 0V.
If you connect the load resistor, this does not change the output voltage of the ideal opamp. So, the additional current for the output resistor must also be provided by the output, which is not a problem for an ideal VCVS. |
H: How do constant current constant voltage devices work?
First of all can a device that is constant current also be at the same time constant voltage? In my head I just could not grasp how this device can work.
Individually I understand how it works, constant current supplies adjust the voltage to sustain the target current, constant voltage supplies work by having some feedback loop circuit that tries to maintain the voltage most power supplies are these.
Now devices such as these XL4016 are said to be constant current constant voltage. They even have 2 potentiometers to adjust constant current and voltage. For constant current to happen, the voltage must be varied, but we cannot have that as we also need to have a constant voltage.
Assuming that it works, and I set it to 10V and 1A. what will happen if I place a 1k resistor on the output? Will 10V @ 1A will be forced into that resistor? No matter the resistance I placed 10W will always be on that load, which doesn't sound right.
How is this achieved, or am I being misled here?
AI: The devices work by not being constant current and constant voltage at the same time.
You set a voltage (V) for the output. You set a current (A)for the output.
It will supply constant V for any current up to A. When the current your circuit draws goes above A, then it will reduce the voltage to keep A at the value set.
Example:
V set to 10V
A set to 1A
If you connect a load of 1000 ohms, then you will measure 10V across it. It will deliver 0.01 amperes of current to the resistor - that's 0.1 watts.
If you connect a load of 1 ohm, then you will measure 1 ampere of current through the resistor. There will be 1 volt across the resistor. That's 1 watt of power.
It would be more accurate to call such power supplies "current limited constant voltage." |
H: Making a voltage range filter (or a voltage bandpass filter)
I have been trying to hack together a voltage range filter that will pass voltage to a load only when the input voltage is between 1-2V. My input source can range from 0-3V. (I don't want to scale the voltage with a divider, by the way. I want to filter out voltages between 0-1V and 2-3V into some shunt resistor or something).
I made a basic circuit like below; my intuition was that the first 2 diodes would drop voltage by 0.5V each (the forward voltage of the B520C), leading to 1V voltage drop, but I quickly realized this was not practical.
I've been trying recall my electrical engineering knowledge, but I feel like I am missing something -- I think the answer is to use opamps, maybe? where I use a comparator to check if the voltage is within my range, use an opamp to pass it with gain of 1? Or maybe transistors.
Any help in pointing me int he right direction (or even a solution!) would be much appreciated.
AI: this can't be done with just passive components -- you'll need some transistors and/or comparators.
With comparators, set one up to detect if VIN > 1 V, the other if VIN < 2 V. Then AND the 2 outputs together and use that signal to drive a pass transistor (PMOS FET, or even a PNP would work). |
H: Electric stove place thermostat so far from heater
I buy electric stove and found that thermostat placement doesn’t make any sense.
The thermostat used seem like one in iron, in that case, the iron heater connected directly to thermostat via ceramic ring.
In this electric stove seem like it regulate air temperature inside. At first I think this product is bad design but I found many product install thermostat the same way (at the case without direct contact to heater). At this point I wonder do I think the wrong way or whole product that sell in the market got wrong design.
AI: The thermostat used ...
It's not a thermostat. It's a power controller.
... seem like one in iron,
Correct. Clothes irons use the same type of power controller.
In this electric stove seem like it regulate air temperature inside.
Image source.
No. The contacts are initially closed applying heat to the load. A bimetallic strip then starts to bend and toggles open after a time switching off the load. It then cools and reconnects and the cycle starts again. The duty-cycle (and hence the average power) is adjusted by the knob which determines how far the bimetallic strip has to bend before toggling.
At this point I wonder do I think the wrong way or whole product that sell in the market got wrong design.
No, you seem to think that you cook in pots based on temperature. You don't. You cook based on power. For example, what temperature would you set the ring at to boil water? 100°C, 105°C, 125°C? The water in the pot will never get above 100°C. Instead you determine the rate of boiling (simmer, etc.) by controlling the power.
... and found that thermostat placement doesn’t make any sense.
It should be clear now that your initial premise was incorrect and that the design does make sense. Controlling the power is how gas cookers work too. There are no thermostats on the hob.
Note that an oven will use a proper thermostat - usually a bulb and capillary tube. The liquid in the tube expands and trips the switch at a temperature set by the rotation of the thermostat control knob. |
H: How can failure of Class Y capacitors lead to electric shock?
This article mentions "Due to the fact that equipment cases are usually grounded, Y caps require higher safety to avoid risks of electrical shocks to users"
How can an equipment with chassis grounded cause electric shock?
Even if Y capacitor shorts to GND (Fig 1), wouldn't the protective earth connection offer lower resistance than human body (Similar to Fig 2)
For a grid connected power supply, isn't neutral always grounded near distribution transformer- Then do we still need the Y capacitor for Neutral line?
AI: In an ideal world a Y-Capacitor failing short would trip a safety device, either a fuse or a GFCI will trip.
Sadly, your world is not ideal and a ground path has a lot of ways to be broken.
It's a chain of connections and a fault in a single one of them will break your earth connection. In normal operation you'll not notice that anything is wrong with your earth connection!
The connection inside the device between the case and the earth conductor of the cable (or the connector at the device)
The device cable itself could have a broken earth connection
The pin in the wall plug could be corroded, worn out or just disconnected
The conductor in the wall could be broken
The earth connection could be on a bad or corroded clamp in a junction box
The connection from your electrical panel to earth could be bad because of a loose screw terminal or corrosion
The chosen earth path could be too high impedance
And if only a single one of those cases is true, your device won't be correctly grounded anymore. I think in light of the fact that we can't guarantee a good earth connection all the time it's good to have an additional safety built in. |
H: Ethernet Switch and QoS Support
I'm going through the Ethernet Switch IC - Link
In the first page, under highlights section, it is mentioned as switch is QoS support.
When I tried to research on what QoS means on this Link, I found the below image:
But as I recall, Ethernet protocol was a baseband interface protocol (meaning that either video or audio will be taking up the entire bandwidth). But the above image suggests that Ethernet might be a broadband protocol(Video, audio and others are sharing the bandwidth).
What is this conflict about? Or am I misunderstanding it?
AI: QoS (Quality of Service) broadly refers to systems which allocate the available data rate among different data streams in some way other than the default. The picture does not represent different frequency bands; it represents fractions of the available data rate.
Without QoS packets are switched on something like a first-come-first-serve basis. With QoS you can (in principle) reserve 30% for video streaming, 20% for gaming services, and leave the rest for anything else. Video streaming gets a certain number of time slots where a video streaming packet will be sent if there is one.
Typically it doesn't actually reserve specific time slots, but rather gives priority to video streaming packets whenever they arrive, and also limits the fraction of video streaming packets to 30%. The effect is similar.
Note that in practice, identifying which packets are "video streaming packets" is quite difficult. |
H: Why are differential mode chokes (inductors) not generally coupled?
I understand there are both coupled and un-coupled versions of differential mode chokes as shown below.
Which one is better? I see most of the designs having un-coupled version. What is the reason?
Coupled differential mode inductors:
Un-Coupled differential mode inductors:
Picture source
AI: Coupled common mode choke real model includes stray inductances, and these inductances work as differential mode chokes and thus they help to tame the differential mode noise.
If these stray inductances are not enough the designer may want to put discrete inductors for better differential mode noise filtering (2nd image is a good example).
As a direct comparison, coupled ones generally have higher inductance in a smaller volume. |
H: What is the core material being used in CMC (Common mode choke) and DMC (Differential mode choke)?
The core symbol in below diagram indicates that it is an iron core material but Iam not sure whether it is correct. I see the same representation in many other circuit schematics as well.
Below ref says
"To prevent saturation, the differential mode inductor must be made with a core that has a low effective permeability (gapped ferrites or powder cores). The common mode inductor, however, can use a high permeability material and obtain a very high inductance on a relatively small core"
"For the most part, ferrites are the material of choice for common mode inductors"
Were all the diagrams just a loose non- rigorous representation? Or was there any meaning in that core representation?
AI: Depends on the working frequency range, of course. But for almost all applications, MnZn (Manganese Zinc) ferrites are used.
Sometimes symbols look confusing, yes. If you see a single inductor with two or three parallel lines on top it's an iron-core choke. If you see two inductors sharing the same parallel lines it means these two inductors are wound around the same core. For CMCs and DMCs there are different symbols such as two inductors having a Z (CM) or 90-degree-U (DM) or a circle in between with phase dots, etc. |
H: Can I power a router that requires 12V-DC via a 5,5mm input by using a powerbank that can output 12V DC over USB
I have a powerbank that can output 5V-3A/9V-2A/12V-1,5A over USB. The router I would like to power came with a 12V-1A adapter and uses less than 12W. If I were to buy a USB to 5,5mm adapter cable, would my powerbank be able to power this router? How would the powerbank know it has to output 12V? The powerbank is a MOJOGEAR XL MG-09.
Thanks in advance!
Gerjan
AI: You need some active device that will communicate with the USB-PD controller in the power bank, triggering it to output 12V.
I won't make any specific product recommendations, but if you search for "USB PD 12V trigger" using your favorite Internet search engine, you will find multiple devices that do this. |
H: Low Side Parallel MOSFET Drive
I'm doing a 12V to 230V push pull inverter design & need to drive it via two MOSFETs for each transformer tapping. Mosfets feeds by an optocoupler PC817. The frequency is 50Hz coming from a PIC microcontroller. Going to do as below.
Am I driving it correctly? Any improvements?
Thanks
AI: You probably want a push pull or totem pole method between OC1 and
your power MOSFETs. Direct opto drive might be insufficient for PWM
at 50Hz, It certainly would be in
I would omit OC1 and only have the aformentioned totem pole or push-pull driver. The opto does little and there aren't safety issues because the
transformer is low V on your primary.
sufficient at 1kHz+.
50Hz square wave would saturate your transformer I think because the
DC level is applied for too long.
You might want some form of snubbing to protect T1 and T2 from excessive voltage spikes.
The voltage labels at your transformer primary are incorrect. |
H: What are the d and q axes for induction machine?
What are the d and q axes for an induction machine (physical meaning)? I understand them for a synchronous machine but how are they defined for an IM?
AI: The same as synchronous machine. Physically they are not rotated in relation to the stator with rotor angle, but with rotor flux vector which has to be estimated using a mathematical model of the respective IM. |
H: Why is my LED flickering when it is connected to a variable resistor, and it's resistance is at the minimum value
I am doing a simple breadboard circuit, with an LED, 3.3V power supply (a microcontroller connected to the PC will be the voltage source), a potentiometer, and a Voltmeter connected across the LED.
This is the schematic of the circuit
When I put the slider at the bottom, the LED's brightness is dim, and the voltage across it will be (Voltmeter reading): 1.791 V
When I put the slider just below the top, the LED lights very bright, and the Voltage across it will be: 2.103 V
but when I put the slider at the top position, the Voltage across the LED decreases to 1.962 V, and the LED starts to flicker.
Can someone help me with this issue?
EDIT
I hope the picture is clear, I am connecting the Launch Pad to the PC, and using its 3V3 pin, and GND pin as a voltage source to my circuit, there is no code, or digital output pin involved (launch pad is just a fancy battery)
AI: There can be three reasons for this.
1, the slide pot is damaged or dirty at the top end. This could be dirt or something that is causing a physically bad connection, or the wiper of the pot is carrying too much current and causes it to flex. There is a maximum current it can carry before damage happens.
2, the led is drawing so much current it overheats and there is internal damage to the led die or bond wires and unstable flashing is a sign of this. At one end of the pot, it will be whatever resistance it should be, either 10k or whatever. The other end will be almost zero. So your overpowering that led.
3, the regulator is going into protection mode, along with reason 2, the led drawing too much current. So the regulator shuts itself off, then the led stops drawing power, then the regulator turns on, rinse lather repeat. This explains the lower voltage your meter is reading because it's happening too fast for the meter to get accurately, and the flashing. |
H: Source Transformation
Ok, I have modified my question again about the same circuit seen below:
I have to simplify the circuit using source transformation and then find the current ix.
I have attached my attempted solutions but I do not get the correct answer of ix = 0.9A ( I am getting 4.3 amps now).
What I suppose I would like to know is:
Is my circuit simplification correct or have I made a mistake somewhere?
Or could I have solved the current ix easily from any of the earlier steps I made in my circuit simplification? i.e. when would you guys stop performing source transformation and circuit simplification and start with circuit analysis to solve the current ix?
Thanks.
AI: 1) The far right is a voltage source with series resistance - it can be transformed, then combined with 9A. Then you can transform back into voltage.
2) Now you have only a single loop equation. |
H: USB 3.0 Length matching in PCB Layout
I'm doing PCB layout for a USB 3.0 connection and I'm curious about if there's a length match requirement between the unidirectional super speed pairs and the bidirectional high speed pair. This isn't for a specific USB 3.0 driver or receiver, but what is considered good practice for operation.
For clarity I'm going to refer to the bidirectional high speed lines as BI+ and BI- and the unidirectional super speed lines as TX+, TX-, RX+ and RX-. What I have seen so far is listed below:
TX+, TX- lines should be within 5 mils (0.13 mm) of each other.
RX+, RX- lines should be within 5 mils (0.13 mm) of each other.
BI+, BI- lines should be within 50 mils (1.25 mm) of each other.
The TX pair and RX pair don't have any length requirement with respect to each other.
The length matching requirements in pairs make sense, but I'm not confident that the TX pair and RX pair don't have a length mismatch requirement for all devices. I'm also not sure if the BI pair has any length requirement with respect to the TX and RX pairs. Are there any general rules of thumb to follow for matching the lengths of pairs to other pairs to avoid errors?
AI: The length matching within each pair is very stringent, but as you have observed, there is no requirement for matching between different pairs. It makes sense, because the three pairs are used for very different things that do not need to be synchronized to each other. Any coordination of the traffic on different pairs is handled at a much higher level than the physical level. |
H: What is a "reactor"?
Watching some of the restoration videos of old tube/valve devices by Mr. Carlson's Lab, I've heard him describe a circuit element called a "reactor" on several occasions - for instance here, where the circuit includes a "saturable reactor". So far, I have not come across a component of that name. What is a reactor, how does it work and what is it used for?
AI: A saturable reactor refers to a transformer in which the saturation of an AC waveform on one side is controlled by a DC current on the other. Inductance is often referred to as reactance, because it 'reacts' with the current. Before the transistor a saturable reactor was one of the best ways to amplify signals and was used to control V2 rockets. |
H: Necessary voltage to charge NiMH using Solar Panel
I'm trying to understand which voltage I need to charge my NiMH batteries so I can purchase the components to do this.
Actually I have 2x AA Ni-MH 1.2 V 1900 mAh and 4x Solar Panel 2 V 220 mA (0.44 W).
I read Solar Cell - Preventing overcharge of an NiMH battery and Voltage input for charging NiMH Batteries but I'm still confused as I'm not an expert in this field.
I gathered this information:
Batteries should not drop under 1 V or they will be damage also not go over 1.78 V;
Constant voltage doesn't work to recharge them (not sure).
I checked out some components to stabilize the current and I found a LM317 in order to stabilize the current to (C/10) 200 mAh and use a MAX471 to check out these values.
But the problem will be the voltage that during the day will drop or go up due to weather so the voltage will never be stable, it is a positive thing?
In the case I need a stable voltage I also found these components (M2578A, TL497A).
I hope to find somebody that can help me. I'm free to other solutions if this one doesn't fit my purpose.
AI: You must have at minimum a battery charge controller because you need a constant current mode. You also need something to make sure you don't overcharge the battery and start a fire. To adequately use a circuit like this you will also need something to stabilize the voltage from the solar panel called an MPPT tracker to make sure the voltage is constant.
Source: https://www.mpoweruk.com/chargers.htm |
H: What is the RGB value of Edison Light Bulbs?
I've been doing a little electrical engineering (outside of my lane a bit). I'm trying to get the RGB values for Edison light bulbs. Can anyone provide me with those?
AI: I used Firefox Web Developer Eyedropper to grab the RGB from a photo of an Edison Light Bulb.
#FACA08
(250,202,8)
A lighter pixel
This is very close to the color when a 2700K 97 CRI LED was reflected off bright white paper: #F4D4AB (244,212,171) just a little less blue.
#F5D483
(245, 212, 131)
I do not believe the LED actually illuminates using the color you see when viewing the filament. The filament LEDs are no different from other lighting LEDs. Many of these "Edison Lights" have Color Correlated Temperature (CCT, e.g. 3000K) and Color Rendering Index (CRI, e.g 80). With that you can get the CIE x,y chromaticity coordinates based on CCT and CRI. Both CCT and CRI are needed although CCT only will suffice. Once you have the x,y chromaticity coordinates they can be translated to RGB.
LED datasheets often have the CIE x,y chromaticity coordinates as shown here:
Using CIE x,y chromaticity coordinates from the datasheet of a 2700K CRI 90 LED (red x,y).
I wrote an SVG app to plot the x,y on a chromaticity diagram to compare two LEDs.
The red x,y are from a Citi CLU036-1205C1-273H5G3 2700K 90 CRI
The blue x,y are from a Citi CLU036-1205C1-30AL7G4 3000K 70 CRI
I used the eyedropper to grab the RGB off the chromaticity diagram for the 2700K 90 CRI.
#F7AF60
(244,175,90)
Using CIE x,y chromaticity coordinates from the datasheet of a 2700K CRI and using a CIE Color Calculator I get:
#FDAC5A
(253, 172, 90)
Some various CCT and CRI reflected off high grade bright white paper.
#F06F5C 1750K CRI 98
#E2CBAC 3000K CRI 80
#F4D4AB 2700K CRI 97 (244,212,171)
#E96C66 Luxeon Fresh Focus Red Meat
2700K is a very warm light. 97 CRI is very close to (natural) sunlight (CRI 100 = sunlight)
I'm asking for the closest RGB match to the golden glow that an Edison
bulb emits
There is no difference between a "Edison Bulb" and any other LED light bulb.
In my opinion a nice warm light is 2700K with a high CRI.
Grabbing the RGB with the eyedropper from the reflection of a 2700K 97 CRI LED off a bright white paper we get this:
Not a very "golden glow"
2700K CRI 97
Measured with a StellarNet BLUE-Wave Spectrometer
The PPFD is a measurement of the number of visible photons in µmols.
So this PPFD measurement shows exactly what wavelengths are being emitted (as a plant "sees") before they are adjusted for photopic luminous efficacy (human perception).
2700K CRI 97 Quantum µmol/m²/s (number of photons)
Slightly lower CRI, more green and less red.
2700K CRI 90 Quantum µmol/m²/s
When the number of photons are adjusted for photopic luminous efficacy it is not what most people would expect. This is exactly the same LED being measured (seconds later) with the same spectrometer as the first image with the measurement units flipped from PPFD to Lux.
2700K CRI 97 Photometric Lux
Examples of Low and High CRI |
H: Is there a difference between specialized audio amplifier and general op-amp silicon?
I've been doing some research into creating a DIY audio amplifier from line-level inputs to speaker level power. I found a guide centered around the LM386 Low Voltage Audio Power Amplifier on YouTube here.
I have a fairly large collection of DIP package TTL logic and alike that I inherited from my father, which I am hoping to make use of in this project. I did some research, and it appears that the LM386 is just a specialized op-amp with desirable characteristics for audio signal amplification.
I located an LM324N op-amp in my collection, which looks to my incredibly untrained eye to have similar characteristics to the LM386. However, seeing how I have a rudimentary understanding of circuit design, it is highly likely that I'm missing some critical information that would allow me to see that the LM324N wouldn't work for my application. Am I missing something, or would the LM324N work fine?
AI: The first clue about the LM324N comes from the datasheet title where it says "Low Power" in it. Your second clue about the LM324N is that it is a quad provided in a 14-pin TSSOP and plastic DIP. This will be a thermal resistance of about \$90-100\:\frac{^\circ\text{C}}{W}\$. Even if there was only \$250\:\text{mW}\$ dissipation per section, the part would be very hot. (Granted, the LM380 also comes in a 14-pin plastic DIP with similar thermal resistance. So it is only a clue. But also note there is only one section in the LM380.)
The actual answer comes from the following table. (The last column is for the LM324 device):
Here, you can see it only sinks or sources perhaps a few dozens of milliamps. This pretty much eliminates any idea that this is, or can be used as, an audio amplifier of any kind. (Note that the microamps shown in that snapshot from the datasheet you provided, as a sinking current compliance, is likely an error in the datasheet as glen_geek points out in a comment below this answer.)
The schematic itself on first blush might not be as clear, since it has a lot of the elements of a power amplifier. However, it also provides some added clues. Let's look at it in a side by side comparison with the LM380:
On the left is the LM324 schematic. You can see the green-circled current sources and sinks shown and you can easily notice the very small values for these currents. This suggests low-power. Especially the \$100\:\mu\text{A}\$ one that is providing base drive sourcing for the Darlington pair on the upper quadrant of the output, \$Q_5\$ and \$Q_6\$. Given something like an effective useful combined \$\beta\$ of about 500 or so, you can't expect more than about \$50\:\text{mA}\$ for sourcing. (Though \$Q_7\$ and \$R_\text{SC}\$ provide some kind of output current limiting circuit, too.)
On the right side, you can spot a few clues about it NOT being a general purpose opamp. \$R_4\$ and \$R_5\$ would be "parasitic" for the normal use of an opamp. You can see that they are not present on the left side, where the differential amplifier pair (Darlington structured) directly expose their bases to the (+) and (-) input pins. But they are added in the LM380 to provide some built-in DC path to ground and biasing. But most importantly, you can see \$R_2\$ providing direct negative feedback (NFB) from the output backwards to the input stage, where \$R_3\$ plays an additional role, as well. You don't build NFB like this into a general purpose opamp. You expect a designer to do that, externally. So you leave that option open to the designer in those cases. But for an audio amplifier IC? There, you can provide NFB -- especially in this case where the gain is fixed at \$34\:\text{dB}\$!
So there are a few clues:
"Low Power" in the title description for the LM324 vs "2.5W Audio Power Amplifier" in the title description for the LM380.
Built-in NFB for the LM380 and no built-in NFB in the LM324.
Fixed gain for the LM380. No fixed gain for the LM324.
Very low output current compliance specifications for the LM324, but where the LM380 claims up to \$1.3\:\text{A}\$ for the output on the first page of its datasheet.
Built-in DC bias path for the (+) and (-) inputs of the LM380 vs no such added bias path in the LM324.
Very low recombination currents being provided in the LM324, for use as base drive at the output stage (if nowhere else) also strongly suggests further limitations with respect to its being used as an audio output amplifier without added external circuitry.
Of course, the LM324 can be used as part of a larger external circuit that may be a useful audio amplifier. But it will at the very least require some kind of external output stage added to it in order to provide much higher output currents. Still, even then this particular LM324 opamp type has such small current sink compliances that I'd be very careful to only use it in a design where the sourcing capacity was in active use and where the sinking capacity isn't important (since it effectively has no ability to sink current.)
I also discuss the LM380 here and here, where you can find some expanded discussions about the LM380 audio amplifier IC.
There are similar substructures in the above schematics, though. So it's not always entirely obvious at a single glance. But if you see NFB in the schematic, that's one thing that's almost always a give-away. Of course, you could also just read the text in the schematic. If it is designed for audio, it's likely to specify operation into an \$8\:\Omega\$ load somewhere and to discuss "power" and likely even to have some discussion about how to design the "copper pour" that will help handle dissipated power from the IC. And general purpose opamps rarely specify an output current compliance much higher than about \$25-35\:\text{mA}\$. It's just not usually needed for general purpose use and the focus is often more on other important benefits. |
H: How are PWM IC's able to provide so many features in small footprints ?
If you look at the general pwm IC's for standard topologies (buck, boost etch) , they have tons of protection features such UVLO, overvoltage, cycle-cycle protection and overcurrent protection.
They are able to provide all these features in a very small footprint.
Take for example the NCV3843 chip (as many other chips).
https://www.onsemi.com/pub/Collateral/NCV3843BV-D.PDF
How are they able to provide all these functionality in such a small footprint?
and do they do this in a pure analog way or is there some a/d conversion happening first ?
I would like to believe the latter.
AI: Transistors are about 10 micron * 10 micron, allowing for aluminum metallization connections to other transistors or resistors or capacitors or diodes or to bondpads.
An analog comparator, to detect some flawed mode of operation, needs a diffpair (two transistors very close together, to have nearly the same doping and the same temperature), several current mirrors (two transistors very close together), and some method to set the operating current to 10microAmps or 100microAmps. The more current, the faster the analog comparator will operate. This analog comparator needs diffpair + (call it) 4 more current-mirrors, a total of 10 transistors. Its range of operation likely will not be rail-to-rail; double the # transistors (at least) to achieve rail-to-rail input operation.
So how did big is this rail-to-rail analog comparator? 20 transistors, each with 10*10micron area, or 2,000 square microns.
On older die, the bondpads (where the tiny 25 micron gold wires attach) are 100*100 = 10,000 square microns. Thus 5 analog comparators will fit into the area of where ONE bond wire goes.
These small transistors will NOT BE WELL matched (well, maybe if bipolar they will be matched) at that size, if old-CMOS process is used. But you may not need super-precision threshold detection, since you have to perform all the error-budgets, and you get to make all the tradeoffs.
Logic? CMOS NAND gates are about 10*10micron; Flipflops are about 10*50micron, in old processes.
Big power devices? High voltage devices (even if low-power)? very dependent on the process.
Here is schematic of a very simple analog comparator
simulate this circuit – Schematic created using CircuitLab
Notice the 4rth terminal of the transistor symbol (MOS body, bulk, well, substrate, backside; BIPOLAR has its collector tub) is not shown.
This simple analog comparator will not function down to GROUND on the input pins; that is, a precise comparison cannot be performed if both inputs are near or at or below GROUND. This is because both of the diffpairs will be turned OFF when their gates are taken that low.
Notice the extreme robustness of this design: you can replace the FET version with the bipolar version, using the exact same schematic. Your mileage will vary, your specs will vary.
===================================
One of the rules for signal processing is: if the analog signal does not contain the INFORMATION, then the ADC/digital-signal-processing will not be able to behave as needed BECAUSE THE INFORMATION IS GONE.
Hence attention to Electric Field interference, to Magnetic Field interference, to Power Supply trash, to Ground System trash, to bandwidth, to differential sensing, to Bolzmann Random Noise ----- become your design task. |
H: What should be the voltage rating of bootstrap capacitor?
BST_1P is the bootstrap capacitor connection pin for high-side gate driver of TAS6422.
In the datasheet it is suggested that, this capacitor should have minimum rated voltage of 16 V.
What is the factor deciding this rated voltage.
Consider the maximum supply voltage is 16 V.
AI: The boot-strap capacitor is switched from the output to either being at GVDD or GND.
In the datasheet, GVDD is specified to be 7V, but the maximum output is 14.4V. So 16V is probably they lowest they could recommend, though it probably also needs to be a larger case size part to not lose to much capacity to Vbias if ceramic.
Halfway through this page there is a nice drawing of a bootstrap NMOS H-Bridge. |
H: Operating a fan on UPS
A short, useless intro to the question, feel free to skip it:
I had a power outage in my home yesterday. Power outages aren't what they used to be - Back in the day, it rendered me completely unable to do anything, but nowadays I have my laptop, which is still connected to the internet via my phone, which is connected to a strong mobile recharger I have (10 Ah) - and I can hardly care less about the rest of the power.
Except for the part about my fan. It gets really hot where I live. And I currently simply have no solution for this. Small USB fans don't do the trick. And I just can't figure out how nobody I know has a solution for such a simple, supposedly common problem. Is mankind simply not advanced enough to take on such problems? Will we be able to operate fans during blackouts? What level on the Kardashev scale must we advance to before we can solve this?
[/end-rant/intro]
Is it possible to operate a normal, standing fan during a power outage? How?
Is connecting it to a UPS a good idea? I've read elsewhere that the waveform generated by UPS devices doesn't behave well with these sort of devices.
And how long is a fan expected to last on a standard UPS?
AI: A UPS as I understand it is an battery attached to an inverter. I have used portable fans on an inverter with no issues. Assuming they are designed for the same frequency. If you have a AC motor designed for 60 Hz and a inverter operating at 50 Hz it would just alter the speed of rotation.
One thing I don't recommend is plugging an electric digital clock into an inverter because a minute will pass every 30 seconds or so. If your laptop is OK with it then your fan will tolerate it OK. |
H: Why do shorted PSU probes stick together just a bit, even on very low power?
I'm using a standard bench power supply set to 3.6V and 0.5A. I also tried 0.05A.
I then bring the positive and negative terminals together in a short circuit, and I noticed there is a noticable sticking effect between them. I have to use slightly more force to separate them, than when the power supply is turned off.
Is this some kind of electromechanical phenomenon, or is there some degree of welding going on here?
AI: Yes, this is welding. Every PSU has a a sizable output capacitor (100 - 1000 uF), and when the leads are shorted, the cap gets discharged first, with much higher impulse of current than the PSU is set to, before the steady DC current regulation comes into effect. |
H: Why doesn't my bench PSU read current on a breadboard?
I've recently purchased a cheap eBay DPS3012 DC-DC converter supply. I intend to use it on breadboard projects.
The "problem" is that the meter reads a 5V output, with no current being drawn and therefore no power. However, the LEDs and ICs are working properly. I'm guessing it's something to do with breadboard characteristics.
I'm sure there's a relatively simple answer for this, I have done some research but haven't found a satisfactory answer.
Thanks for the help in advance!
AI: These cheap PSU usually have current / voltage reading but they are not by any mean accurate. They are more there to give a rough idea of what current is flowing.
An LED typically draws 10-20mA and your PSU, from the datasheet has a resolution of 0.01A (10mA).
Also the resolution is "what is displayed" and does not represent the actual accuracy of the device, which is probably on the range of 5 to 10% (EDIT in fact 33% measured by OP). At this price, is certainly not calibrated and you can see from the picture the current sense seems to actually be 2 copper wires used as shunt, which shunt value will change with soldering and small change in the wire thickness and length.
To answer your question, the current you are drawing is simply too small for the resolution and accuracy of this device, it probably has some offset, calibration drift, temperature dependencies and everything you can think off.
Try to hookup a 100ohm or less resistor and see if it displays anything. |
H: Contact pressure vs contact area
I'm learning to weld. I've realised my earth clamp is limited. The spring is weak and its contact area is small as it's tooth shaped.
Researching better clamps, I see clamps which have threaded bolts to clamp the jaws against the workpiece tightly. It is my understanding that unless you are clamping something malleable such as lead, increased clamping force wouldn't increase the contact area, unless such force is applied to leave indentations in the workpiece.
So I've been looking for clamps which have larger contact areas, and magnetic clamps seem to have large flat brass areas rather than pointed teeth which will be pressed against the workpiece with moderate spring pressure.
How does increasing clamp force increase conductivity, and is contact pressure really interchangeable with contact area size?
To be clear, I'm aware different clamp designs are more suited to different applications, but I'm specifically asking about the properties of electrical conductivity of a larger area being pressed lightly, vs a toothed (i.e, small) area being pressed very firmly.
Toothed clamp design:
Magnetic design with brass flat contactor:
AI: There is a proportionality between the pressure applied and the contact conductivity due the microscopic roughness of the contact surface that make the real contact surface much smaller. Applying a pressure flattens the surface increasing the contact area.
In some amount increasing the macroscopic area while keeping the same force doesn't increase the conductivity because the per square inch force will decrease proportionally.
See here a much detailed explanation. |
H: The 555 regulator that won't regulate
I made a 170V step up converter using a 555 timer for my Nixi project.
At first I tried to run it using 5v but could not reach a 170v output, so I opted for a 12V supply and put in an LM7809 regulator. I put a heatsink on it although it probably does not need one.
I was able to get 170V but found that this would change if I varied the input voltage (bypassing the 9V regulator that is)
But the main issue is that the voltage drops if I connect a load.
No load: I/P = 12V @ 100mA; O/P = 170V @ 0mA
1 neon load: I/P = 12V @ 200mA; O/P = 148V @ 0.82mA
2 neon load: I/P = 12V @ 200mA; O/P = 133V @ 1.3mA
Testing with 1 neon load:
By adjusting the variable resistor I can reduce the voltage, but cannot get it above 148V. It is as if my circuit is reaching saturation.
I had triggering issues on my scope but noticed that the square wave did change from no load to 1 neon load, but adding the 2nd neon did not "seem" to make a difference.
I checked the electrolytics = ok.
Coil = 100uH.
The 1k & 2K2 resistors were swapped around, but that made no difference.
I even replaced the 555.
I may have used an IN4004 diode instead of a UF4004 - is there a difference?
Checked for shorts, parts placement,.......
I did order a ready made supply which is currently on a slow boat from China, but would prefer to use my own build anyway. Although I did get the schematic off the net.
Any ideas where I failed or what I else I could test for?
Any help would be appreciated.
Thank you
Thank you for the feedback.
I will try to answer as many quetions as I can.
Neon tubes don't use much current, so I should be ok with the 12V 2A supply I intend to use. (tetsted with 4A bench supply)
Why a 555? Probably because I'm a bit nostalgic about these and because I had quite a few lying around.
(@Finbarr) I originally put in a 9V regulator because the output voltage would vary with the input voltage and I wanted a stable output.
If this issue is resolved once I get the circuit going, then I will remove it. I want to protect my precious Nixi tubes just in case I (or someone else) plugs in the wrong power supply. And then I read your next reply about the input voltage varying the frequency and duty cycle, so it looks like the 9v regualtor stays.
I used a 350V rated cap on the output.
I remember that component prfixes used to be manufacture specific, so TI would have a different prefix than Fairchild......
But I started to think about the diode more and more. Thank you for confirming this and I will pop off to the local elecronics supplier and pick up a UF4004. Fingers crossed!
AI: At first I tried to run it using 5v but could not reach a 170v output
I'm not surprised, at 5V the 555 will barely be able to turn the MOSFET on, let alone do it quickly enough. As it is, the 555 isn't great at driving a MOSFET well enough for this application, but the higher voltage gives it a better chance.
I opted for a 12V supply and put in an LM7809 regulator...because the output voltage would vary with the input voltage and I wanted a stable output.
That variation is happening because the rest of the circuit isn't working well enough for the feedback mechanism to become active and regulate the voltage. As well as reducing the drive to the MOSFET, the 7809 will have a current limiting effect which could stop the inductor being charged properly. With the rest of the circuit working it will be pointless.
I may have used an IN4004 diode instead of a UF4004 - is there a difference?
Yes, a big difference (components are usually specified for a reason). The UF4004 is a much faster diode than the 1N4004, which is crucial when you're building a switching supply running at about 30kHz.
Finally, the 200V rating on your output capacitor gives very little headroom. I'd use a part with a rating of at least 300V. Also pay particular attention to construction and possible arcing between the high voltage connections. |
H: Un-masked Copper Boundary across RF section
I have seen so many PCB which has an un-masked (without solder mask), copper boundary across RF sections. The boundary has via-stitching and there are also few openings in the boundary. Can someone explain their purpose? Please have a look at the picture below:
AI: You meant Via Stitching.
In RF application, you have a lot of current flows happening that behave quite differently than in non-RF application, and can take some really weird ways.
This is to reduce this effect.
The via stitching is there to reduce high frequency current flow going though the internal layers, don't forget a PCB is a dielectric, but still conduct somewhat electricity, or charges, especially in high frequency application.
The traces are uncovered for the same reason, avoiding having current flow flowing above the solder mask and messing with the rest of the circuit.
Probably on top of these ring, a metallic housing might be soldered, acting as a Faraday cage and avoiding having EMI being emited by the circuit.
Like this:
This doesn't apply to your question, but it is an interesting addition:
These types of uncovered rings are also sometimes used in acquisition when the signal carries nA level currents.
Called Guard trace, they usually feed a follower op-amp, and the ring is placed around the signal trace and connected to the output of the op-amp, bringing the ring to the same voltage as the trace and thus avoiding leakage current. The cutout are for the same reason |
H: Clock domain cross and metastablilty problem
I understand the problem of metastability and understand that we can't get a stable value in a bounded time so we need unbonded time but it is not practical,
so we put another flip flop with no logic to let a complete clock period be available to the metastable state to be stable state
But the metastable state is equally probable to be '0' or '1' as the mechanical analogy of a hill
so why after the ff synchronizer the stable value dout will be exactly equal to the input din ??
AI: TL;DR; The circuit doesn't prevent the first register (the one connected to din) from going metastable. What it does do is reduce the probability that metastable value from propagating into the rest of the circuit.
Let's start with a 1-flop synchroniser. The register will clock in the value of din and align it to the clock edge. All good? not quite.
If din is still changing when the clock occurs, the output may go into a metastable state. If the output of this register is connected to other circuitry, this metastable state will propagate through the connected circuitry. Not good - this can lead to concurrency issues if multiple registers are fed from the same metastable signal, to incorrect values being generated from combinational logic, to state machines entering the wrong state.
What happens if we add a second register? The metastable state of the first can still occur. However the second register always (*) clocks the value one clock cycle later. As such there is now a time gap between the first register and the rest of the circuit.
If the first register goes metastable, but resolves to either 1 or 0 (it could be either) in less than one clock cycle, then by the time the second clock cycle occurs, there is no metastable state when second register samples the value. The propagation of the metastable value to the rest of the circuit has been prevented. There will as a result be either 1 or 2 clock cycles of delay as a result of the second register depending on what value the metastable state resolves to.
This massively reduces the probability that a metastable state will propagate - there is a mean-time before failure (MTBF) that can be calculated based on probabilities - for one register it could be as low as 1 clock cycle, for two registers it can be as long as the age of the universe.
Adding additional registers can further reduce the probability of metastability by catching any metastable values in the second register (in case the first register didn't resolve within a clock cycle). However there is a law of diminishing returns, which is why in most general designs you will see 2-flop synchronisers, and 3-flop in mission critical designs.
(*) assuming the clock is routed with minimal skew. |
H: Calculating the oscillator frequency
I am trying to calculate the frequency of the internal oscillator, in order to go through the design procedure listed in the datasheet. The problem is that it gives me answers that contradict the 100kHz max f specification. Here is my calculation with the example values in the step-down converter example:
Here is the datasheet I am using:
http://www.ti.com/lit/ds/symlink/mc33063a-q1.pdf
To find the discharge time (tdis), I am using the following values:
C = 470pF (CT on figure 13)
dV = 0.5V (Section 7.4)
Idis = 200mA (Section 7.4)
I then calculate:
Idis = C * dv/dt ----> dt = C * dv/Idis
dt = 470pF * 0.5/200mA = 1ns
since the charge time is 6 times the discharge time, the period T is 7ns, which gives a frequency of approximately 143 MHz. What is happening here?
AI: Section 7.4 is wrong.
It says mA, but the actual tabular data is talking about µA. So there is an error of factor 1000 there.
With that you end up at 143 kHz. Calculating a bit more precisely, you end up with 128 kHz.
But there is some non ideality in this chip. If you look at Figure 1, for 500 pF you end up with 3 µs on and 20 µs off time, which results in 44 kHz. |
H: Having issues with using simultaneous timers [STM32]
In my nucleo L432KC, I have set Timer 1 for PWM generation, Timer 15 as a timer based interrupt and Timer 2 as PWM input mode. Timer 1 and Timer 15 works well until a point. My clock frequency is 2MHz. For example, I wanted a 50 kHz update event, so I set Timer 15 Precaler 0 and period 39. In that case, While(1) loop never executes, i.e, the program hangs.
When I start timer 2 as:
HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3);
HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4);
My timer 1 misbehaves. The program in general misbehaves. What could be happening here? It's like Timer 15 interrupt is taking all the control? Is something related with interrupts priorities? The purpose of Timer 15 is to fire an interrupt at 50 kHz. During this interrupt, I'm reading SPI data.
Pseudocode of interrupt routine:
Pull chip select down
Read SPI with HAL_SPI_Receive
Pull chip select up
AI: If you have an interrupt firing at a frequency of 50 kHz with a 2 MHz clock for your core, that leaves 40 clock cycles to do work between two interrupts.
That is quite few, it already takes some cycles to enter and leave the interrupt, so you get even less for actual work.
In the comment you stated that you are "simply" reading some SPI data. If it would be just transferring data out of the SPI data register, that might be fine - but then you would do that in an SPI interrupt. So I guess this reading involves more than that.
And with that I am pretty sure that you need more cycles in the interrupt routine than available. Which results in the next timer interrupt being queued up while still handling the old one.
In that case you are never going to leave the interrupt and the rest of the program will never get the chance to execute. Interrupt priorities might change this a bit (other interrupts will be handled) but you will not get to your main code.
To change this you either reduce the frequency of the interrupt or increase the clock frequency of the core. |
H: Pager system charging pin and socket
Does anyone know what these pins are called? This is a pager from paging system used in certain restaurants. I'd like to know what it's called as I want to use it in my device's design. I need to know what socket is used with it, but that would be easier to find if I can find the pin :)
AI: They appear to be what is know by the brand name "pogo-pins", which I believe are officially called "spring contact pin".
Quite a few manufacturers do them. They tend to be expensive and have a low current rating compared to other contacts, but are useful in that they are so versatile, as only exposed metal is all that's required as a mating half. Often small ones are used on on test pads of PCBs to do production line tests.
EDIT: just noticed you ask to find the mating half in your question. This type of contact often just contact to a bit of metal in some custom designed housing. But they are also used with a proper contacter, which as a profile to match the pin (in this instance the pin has sharp spike, so the official mating half would have suitable cone indent in it). |
H: ESD diode selection based on VCC of the IC
I have a question about TVS diode selection.
This kind of question is already discussed in previous questions.
ESD Diode - GPIO Microcontroller
Selecting a TVS for ESD protection
For protecting vcc line of a controller with nominal VCC = 5V, 5%, maximum vcc = 6V.
We normally choose esd diode with Vrwm=5V, for them Vbr = 5.8 to 7.8 and Vc = 12.5 to 15V (ESD9B5.0ST5G as a reference).
ESD diode manufacturer graphs also shows even though device is choosen from 5V operation, During testing, voltage across clamped can go up to ~50V(not sure can be lower but way higher than 5V), after some time they comes back to actual Vclamp voltage.
Is this ~50V clamping voltage is lethal to IC's(5V VCC pin)?
few answers i got it were first portion of ESD pulse where 8kV reaches is very low energy (few ns) and can't make much harm to IC's.
In addition to that most of the IC's have basic ESD protection (have esd protection diodes on all pins which will induct during high voltage events, designer's work is to limit the current passed to those diodes during transient event)
once this this high peak passed, higher pulse width portion comes which needs to be swallowed by esd diode.
we can't add series resisters in VCC pin of the IC, because it drops the voltage for the IC.
**
So, in those cases just connecting ESD diode across VCC line is worth?
**
AI: I think no one will be able to tell you if this 50V clamping voltage left over from the ESD diode is lethal to your IC's 5V VCC pin. It depends heavily on the duration (=energy) that reaches the pin and of course on the IC itself. You might have to test that with an ESD test setup.
But there's another thing to consider:
The diode should be placed in-between the ESD source and the IC and it should be spaced from the IC. If the diode is just a few millimeters away from the IC's VCC pin, then this trace distance acts like an inductor and thus the remaining 50V (very short) pulse will be filtered out by this trace inductance and the ESD diode will be able to absorb all energy of the pulse (together with the VCC supply capacitors). |
H: Increase Boost Converter Current
I'm building a portable charger for my phone using a large 2.7v supercapacitor, which uses a very simple boost converter to create 5v. I am not concerned about input current, however, when a load (my phone) is connected, the voltage falls to 4.53v, regardless of any changes I make to the duty cycle, frequency, or inductance. My best guess is that my phone only begins charging when the voltage increases over this point, but this causes the voltage to fall again and oscillate. My question is, how can I increase the amount of current that the boost converter can source, so that the output voltage will be nearer to 5v?
AI: I find this question close to me, as I some years ago I was doing the same kind of mistakes on a very similar project (basically getting a boost convertor on a breadboard, without the knowledge about the MANY pitfalls, as others have already mentioned). I asked in a forum and I got a lot of surprised looks from the elders, just like you :)
There are many things in this project that can be fixed with more reading and dedication, however I feel that a major hurdle that may stop you is the need to transfer it to a real PCB (best case) or at least very tightly packed prototype board (with a lots of caveats there). If you want to charge a phone, that is.
If my gut feeling is right, and you don't want to leave the convenience of the breadboard, may I suggest doing something slightly different, that will get you the most of the intuition about boost converters¹, but still be feasible on a breadboard, and with the added benefit of avoiding the risk of killing a potentially expensive equipment (the smartphone)?
How about boosting the supercap to power a bright white LED (the ones that require 3+ volts)?
You still need the boost converter (and you can demonstrate that the supercap alone doesn't light the LED even the tiniest bit), but the currents required will be within the capability of jellybeans like the BS170, and if your switching frequency is low enough², within the capabilities of breadboard.
¹ Sadly, to really get the hang of how boost converters work, it would be best if you can poke around with an oscilloscope. If you can get your hands on one, at least for a while - go for it!
² In general, stay below 100 kHz; less is not an issue, you just need larger caps and inductors. More, and you get into the area that makes breadboards inappropriate, and the MCU wouldn't cope with driving the MOSFET efficiently too. |
H: Ring around wire on diagram
If this is a repeated question, please let me know. I'm a hobbyist electronics person, and ran across symbols on a diagram I didn't recognize. I've attached the image below:
What I'm trying to figure out is what the different rings around the wires mean. For example, Earphone Pilot has a connection that shows a ring around one of the wires, and then that hits a T connection where all of them have rings around the wires, too. I've been trying to look it up, but I'm having a really hard time finding info. The full diagram is part of the wiring diagram for a Becker Avionics AR620X transceiver, and the diagram is on page 77 of the PDF here.
AI: That's shielded wire. The ring around it is the outer shield around the cable linking the two parts together. The shield also provides the low side of the signal, so it needs to be connected to the ICs as well; it's the other half of the complete circuit. That T connection you mention is just showing that the shields for all the wires are connected together. |
H: Is rated current supposed to vary based on voltage?
Recently I have been reading a lot of datasheets and noticed that many manufacturers specify a current rating for their products (especially connectors) without specifying at what voltage the current rating applies (except for a max voltage). This seems super counter intuitive for me as when the voltage increases you will have more power (watts) moving through the component that, in my mind, should affect the rated current. So at a lower voltage you should be able to pass more than the rated current.
Some examples of this:
https://www.molex.com/webdocs/datasheets/pdf/en-us/0475070010_PCB_HEADERS.pdf
https://www.vishay.com/docs/31017/rcwp99.pdf (this one specifies a rated power but that is just for the voltage drop across the jumper. What is the rated voltage at that current?)
https://www.hirose.com/product/en/download_file/key_name/FH34SRJ-10S-0.5SH%2850%29/category/Specification%20Sheet/doc_file_id/43118/?file_category_id=9&item_id=05801251550&is_series=
These datasheets make it seem as if there is a physical property that attenuates current flow no matter the voltage when I think it is based on voltage and current.
AI: There are two aspects to the maximum allowable voltage specification a given resistor has. One is the packages' power dissipation rating, which for a given value of resistance will have a maximum applicable voltage before heat dissipation values are exceeded: P=V^2/R
The second is a safety persective because the smaller the package the closer together the two terminals are. Eventually the electric field gradient between them becomes so strong that you can get electromigration effects, tracking, etc. that will cause a short across the terminals. There is a corollary in that post manufacture cleaning of boards becomes more critical as well, debris tends to become conductive over time with some soldering techniques.
In the case of the jumpers, Vishay RCCe3 series does have the voltage rating, could be the other datasheet is just missing the row (typos in datasheets happen all the time, most get caught some don't.) |
H: Wire to board connector for Test Jig
What's the best way to quickly connect/disconnect ~22 AWG wires to a test jig pcb? I would like to use a spring loaded connector that can easily release the wire after I'm done testing. Currently have these
However they're expensive and don't hold the wire the best. I would like something similar to a fuse clip like this.
Does anyone know of any connectors that can accommodate this?
AI: If you need a good hold for the wire you will need some clamping.
Have you considered speaker connectors?
Or banana binding posts (but they're expensive) |
H: Is it possible to make a lightbulb light up by wetting your hands?
I was recently watching an Electroboom video on free energy devices, but my question is not about any of that stuff. Here's the video. At about 5:50 he claims and seemingly shows that he can light up a light bulb using his muscles and by wetting his hands. Now this guy usually is pretty solid with his stuff, but when he did this, I was floored. Did he make this up, or is he (and maybe others) some kind of mutant or something? I tried it, and maybe I wasn't doing it quite the same way, but it didn't do anything. Has anyone ever heard of this trick, or this ability?
AI: It's a trick. The light bulb contains batteries, and all you need to do is create a conductive path between the contacts in order to turn it on. Wetting the fingers is key; the arm-flapping has nothing to do with it.
They've been marketed recently as "blackout-proof" bulbs. They charge themselves from the AC when it's available, and the cute thing is that the wall switch still switches them on and off (under certain conditions) even when the AC is off. |
H: Nichrome wire temprature
I have recently been working on a project in which a material, whose ignition temperature is 500 °C, is to be ignited.
So, what type of nichrome wire would be suitable for me, if I am using a 5 V power supply capable of 5-10 A and length of wire is about 1 cm?
AI: Normally I'd do a technical search, but "urgent" so, ok...
https://en.wikipedia.org/wiki/Nichrome#Table_2:Current(A)_vs._temperature_characteristics,_straight_wire.
Table 2, one thing to note, if the nichrome is in contact with material you may want to go for a slightly higher temperature, because of heat conduction into surroundings- this can be a critical thing in an open air environment (wind cooling effects). Increase in resistance is small, so the 5V supply shouldn't have a problem at 5A if the wire is 26AWG or so, 24AWG may be getting close to the 5A limit once it heats up but if you're supply can really output 10A it would be the better choice as it has more thermal mass. |
H: Are Cal Kit (SOLT) definitions unique by serial number?
I have an E5071B Network Analyzer and 85033E cal kit.
One of the standards is broken now and needs to be replaced. This is the Male OPEN standard (Part number 85033-60018).
Question:
Will the definition files (that come on the floppy disk, and are now installed in my VNA) still be valid after I replace the broken OPEN standard? Basically, are the definition files specific to each individual kit per serial number or is it just one set of definition files that works for all 85033E kits?
AI: It could be either way.
Some kits are characterized individually, some only by model number.
A high priced Keysight kit is probably characterized individually, but you could check with Keysight to be sure. If it is individually characterized, they should provide new characterization data with the replacement standard.
However, I was told by one cal kit vendor (not Keysight) that even though they charge more for an individually characterized kit, they actually think their EM modelling is more accurate than the equipment and references they use to do the cal kit characterization, so the generic characterization data provided with the lower-cost kits is actually better than the measurement-derived data provided with the individually characterized kits.
So your mileage may vary. |
H: Why does these capacitances have no effect on the output of this amplifier?
Below shows a piezoelectric sensor connected to a charge amplifier:
The text claims that the output voltage Uout is to a good approximation only charge q which is going to be measured divided by the feedback capacitor value Cf.
The text then says the amplification is independent of the capacitance of the sensor and the cable without explaining why.
I dont understand why Cg and Cc have no effect on the output. (?)
AI: When an op-amp is operating closed-loop with negative feedback within its linear region of operation (all input/output specifications met). The two input terminals will have an equal voltage due the feedback action of amplifier A. This action creates a virtual ground at the opposing input terminal of the amplifier.
With no potential being developed across the cable's terminals, no current flows through \$C_g\$ or \$C_c\$. All the signal current flows through the feedback network of amplifier A. |
H: advantages of PC-relative addressing
I have read somewhere:
"The advantage of using
relative mode over direct mode is that relative addressing is a code which is position-independent, i.e. it can
be loaded anywhere in memory without the need to adjust any addresses."
I can't understand this part. why we need to adjust addresses in direct mode but not in the relative mode.
and please give a brief explanation of this part:
"Also, relative addressing is
particularly useful in connection with jumps, because typical jumps are to
nearby instructions."
AI: One reason why PC-relative jumps are advantageous is that they require fewer bits. A relative offset might be just 8 or 10 bits while a full, absolute address might be 32 bits. So, relative jumps take less memory in the instruction code. Since typical jumps are nearby, using relative jumps also makes the code smaller in addition to the advantage of relocatability.
Also, the offset for relative jumps can be computed at compile time, while the address for an absolute (direct) jump needs to be computed at link time. This makes building code with relative jumps a little faster. |
H: Nmos trigerring in 4-20mA converter
Here is the circuit I am trying to understand:
It comes from the following application note from LT:
https://www.analog.com/media/en/technical-documentation/technical-articles/D61_EN-Convert.pdf
I am wondering how the Nmos will ever be triggered. Now from my point of view, the op-amp's negative input should track the voltage on the positive input, setting transistor M2's source voltage to Vin. Now since the op-amp is in the voltage follower configuration, the voltage at M2's gate would also be Vin.
Now that seems to me like Vgs would always be 0V and the FET would never turn on.
I am absolutely certain that my analysis is wrong, I am just not seeing where.
Thank you in advance for all advice.
AI: "Triggered" suggests something that will suddenly switch from one state to another. That's probably not the right word.
As this is an analog circuit we can expect M2 to turn on gradually under certain conditions. "Turned on" would be a better term.
Since the feedback is taken after M2 it means that the output of the op-amp will go as high as it needs to to turn on M2 enough to get the feedback voltage to match the input voltage.
simulate this circuit – Schematic created using CircuitLab
Figure 1. Running the CircuitLab DC Solver for 4 V in results in 8 V at NODE1. |
H: What is the purpose of a diode and resistor at the gate of a FET in this LED driver circuit?
I am trying to design a LED driver based the LM3409HV IC.
I am using the reference design from TI as a starting point.
The schematic in the datasheet has a diode (D2) and a resistor (R5) at the gate of the FET that switches current to the LED.
In the BOM, D2 is listed as "no load" and R5 is listed as having a 0 Ohm value. I have never seen this and can't understand what it means.
I have also seen other designs based on the same IC and the gate is connected straight to the IC, without any diode.
Can anyone explain to me why these components are included in the schematic, and if I can safely leave them out in my design ?
AI: It is normal to drive the gate of a MOSFET through a resistor (normally under 100R). It is also seen a diode exactly as connected in the schematic.
The reason is that the gate is a capacitive load to the driver. This means that is has to charge when turned on, and discharged when turned off. If there is no resistor, the driver has to be capable of providing the peak current to charge the capacitor. On the other hand, to turn off the MOSFET you want it to discharge as fast as possible (for a fast turn off), and not through a gate resistor.
Obviously if you short circuit the resistor, there is no need for the diode. I'd say that in this case it's a reserve in the PCB to allow for MOSFETS with higher capacitance in the gate. |
H: One resistor in series and two in parallel for LEDs
So I've read that using one resistor to limit current to two or more LED's in parallel is bad practice, so I wondered what about this kind of circuit:
Is this also bad practice?
Each LED has it's own current limiting resistor, but the current is being limited further by a resistor in series. Are there any differences compared to just having each LED connected in parallel directly to the voltage source with a 355Ω Resistor?
Also (just to double check I am doing my calculations right as I am still a student learning this stuff), assuming each LED has a forward voltage of 2V, is each LED drawing about 20mA here (7V across resistors, Rtotal = 355Ω so 7V / 355Ω = 0.0197 Amps)?
AI: simulate this circuit – Schematic created using CircuitLab
Figure 1. Equivalent circuits.
Your circuit is fine. The 270 Ω resistors will make up for any variation in forward voltages of the LEDs and prevent the one with the lower Vf from hogging the current.
Your 355 Ω calculation is wrong, however. The effective resistance for each LED is 710 Ω. The current is given by \$ I = \frac {V}{R} = \frac {7}{710} = 10 \ \mathrm {mA} \$. That will be quite bright for most modern LEDs. |
H: Discriminate MOS from BJT easily
I have a transistor for which no datasheet is available
the transistor is supposed to be NPN (which implies BJT).
(BD247C-Transistor-NPN, 100V 25A, 120W in TO220)
how can I find out easily if it's a MOS or if it's a BJT?
I have a Digital multi meter and a +5,+12V power supply.
AI: Google the part number. I just did, and while I didn't find a data sheet, I did find an NTE cross-reference (for an NPN). This indicates that it's an obsolete consumer part.
Measure each leg against the others with the meter in diode mode.
An NPN will show the base-emitter and base-collector junctions as one diode drop if the base is positive (and if it's a really old transistor you'll learn whether it's silicon or germanium).
A PNP will look like an NPN, only in reverse.
A typical MOSFET will look like an open-circuit from gate to either source or drain. It may look like a diode drop from source to drain (for an N-channel) or from drain to source (for a P-channel) or it may be open, or (if it's depletion mode) it may look like a resistor. If you really think it's a MOSFET you can try putting 10V or so on the suspected gate-source pins and see if the drain-source pins conduct.
A 3-terminal voltage regulator will just look odd |
H: If a circuit only has a current source and no voltage source where does the voltage come from to supply the circuit?
For example this circuit, A current source is something with would alter the voltage across it to meet a certain current.
But where is there a voltage source to do this or even have a voltage at Vx. How is this circuit functioning without even having a voltage supply?
I have looked here : Is current source also a voltage source?
To try to understand the difference between what a current source is and a voltage source but nothing helped answer this question.
Could in this case the current source act as a voltage supply?
Thanks
AI: An Ideal current source will produce whatever voltage is necessary to permit it to deliver its specified current.
An ideal voltage source will deliver whatever current the rest of the circuit requires when it is delivering its specified voltage.
Real current and voltage sources will have limits on the voltage (for a current source) or current (for a voltage source) that they can deliver. |
H: LED behavior during 24 VAC negative half cycle
I don't understand why the green portion of LED3 is able to conduct. Since the path marked in green represents the negative half-cycle of the 24VAC isn't the green LED reverse biased therefore no current flow. Isn't the red portion of LED3 FW bised- shouldn't it be lit? Or since this is AC does the "-" or "negative" have to do with current direction as seen here?
AI: Your schematic shows two basic topologies: one with and one without a resistor in parallel with the switch. For each of these topologies, there are four possible states: two with the switch closed and two with the switch open. So, altogether, there are eight situations to examine.
Let's start with the cases on the left, without the resistor in parallel with the switch:
simulate this circuit – Schematic created using CircuitLab
At the far left, you can see that there is only one path, through the RED LED, to complete the circuit. So for this half-cycle, the RED LED is activated and showing. But just to the right, with the AC reversed, there is NO path available. So both LEDs are off. So for the left two cases, with the switch open, only the RED LED can be lit. And only then, for one half-cycle. Given the 50-60 Hz frequency, this is sufficient for you to perceive the RED LED as "ON" and the GREEN LED as "OFF."
Now with the switch closed, you can see on the left side of this right-pair of cases, that the current flows through \$D_3\$ rather than through \$LED_{1_\text{R}}\$. This is simply because a "normal" diode has far less of a voltage drop than does an LED. So the current does NOT flow through the RED LED, despite the fact that it is oriented with the right polarity. \$D_3\$ effectively bypasses the RED LED here. So the RED LED is still "OFF" in this half-cycle. On the far right side, with the AC reversed again, the current cannot go through \$D_3\$ or the RED LED. It can only flow through the GREEN LED. Luckily, there is also \$D_2\$ to complete this circuit. So for the right two cases, with the switch closed, only the GREEN LED can be lit. And only then, for one half-cycle. Given the 50-60 Hz frequency, this is again sufficient for you to perceive the GREEN LED as "ON" and the RED LED as "OFF."
In your last case, with the added resistor in parallel to the switch, this only affects things for the case where the switch is open:
simulate this circuit
(I've removed the inactive diodes above.)
This will appear as a YELLOW/ORANGE color to your eye, since both colors are being emitted; one in each half-cycle.
In the case where the switch is closed, the new resistor is bypassed and the behavior will be as before (a GREEN LED lit.)
So here, you will have YELLOW or GREEN. But never RED, exactly.
The exact currents in this last case are a little more tricky. But it's not terribly important. The value of \$R_2\$ can be adjusted according to need, easily.
I've not addressed the details with respect to how many of these are series-chained. But that's another detail regarding the selection of \$24\:\text{VAC}\$ and isn't quite as important. Fewer sections will mean brighter LED emissions. More sections will mean dimmer. But otherwise, the logic remains similar.
This isn't a well-managed system in the sense of the voltage drops for each section stacking up always the same. But it's probably good enough for this use. They could add more circuitry, I suppose. But they felt it wasn't necessary. |
H: Bad Practice - Charging Lithium-ion Batteries while powering circuit?
I'm using a 2s BMC (Battery Management Control) to charge a 2s2p lithium-ion battery pack (7.4v, ~6Ah). The output of the charging circuit is the same as the input - they're not separate. As a result, when I want to charge the batteries, I just hook up 8.5v to the +P and -P terminals and let the BMC do its thing.
Is this bad practice? Is there any potential damage to the batteries if I am charging them AND the power from the charger is powering the circuit (the circuit normally powered by the batteries) at the same time?
I don't believe so off-hand, but I've heard that too much ripple on the voltage supply for the BMC can cause issues where it has a hard time detecting the charge status of the Li-Ions.
Thanks!
AI: The BMC measures and controls the voltage and current that is provided to the battery and do so quite precisely to improve the life of the battery (depends of the quality of the BMC of course).
If you connect a circuit, while charging, some of the current the BMC would think goes to the battery will actually go to your circuit.
This might create issue the BMC charging algorithm, especially to detect the end of charge of the battery, since you are still drawing current at a voltage the battery shouldn't.
There are different lithium chemistry, and charging profile also depends on the chemistry of the battery, some has some small fluctuation that the BMC will pick up to detect the end of charge.
To answer the question, it might depends on which battery/chemistry is used and what BMC is being used. In some case it will be no problem, in some case it might fail to detect the end of charge and go in fault.
In case of Li-ion and Li-po, it would probably not damage the battery as the end of charge is constant voltage.
A better solution would be to power your circuit from a source before the BMC, this usually can simply be done by adding a diode between the battery and the circuit, or better with an electronic switch. |
H: Impedance matching a dual frequencies
Does anyone know of any impedance matching techniques to match at two different frequencies? Where the impedance at both desired frequencies are different (both the real and imaginary components)?
Most of the papers regarding dual impedance matching assume that the impedance is constant across all frequencies.
AI: I think the confusion may be that usually when you have two bands RF engineers gravitate to 'diplexer' and there are a lot more questions to be answered, such as passband width, stop band attenuation, maximum acceptable insertion loss, transition band, etc.
With that said, there are several resources available on the web to get you started. You mentioned you need to fabricate one, but didn't mention your budget, so I'll approach it several ways.
The first is the old fashioned way, by using a Smith Chart, a decent intro is here:
http://www.antenna-theory.com/tutorial/smith/smithchartC.php
pros: Its' free, relatively easy, if a bit tedious.
cons: The optimization techniques are limited in terms of bandwidth. Did I say tedious?
The second is a computer-assisted matching and there is a plethora of software packages (from free to Rolls Royce pricing).
pros: much easier than the manual technique, various data import options, various matching optimization algorithms and options (especially on the $$$ ones).
There are some free or low priced packages out there such as:
https://imnlab.wordpress.com/
http://www.iowahills.com/9SmithChartPage.html
and more, I have no horse in this race BTW (as a disclaimer).
You can literally google "RF impedance matching software" and they pop out by the dozen, you may want to check reviews or send them an email to see if one would meet your specific tuning requirements.
cons:can be pricey, optimization controls can be limited for the cheaper programs, unlike the $$$ (Genesys eg).
But if you're not in the RF business where you're not trying to squeeze that last .02dB to beat the competition that may be enough.
There is a point of diminishing returns once the matching network becomes large, in that you're losing more signal than the matching network is allowing to pass (due to parasitic losses).
As a historical reference:
https://ethw.org/History_of_Broadband_Impedance_Matching |
H: 7 Segment Display Segment C Kmap Confusion
I am working on the Kmap for the Segment C on the 7 Segment Display.
The list of numbers that light up the 7 segment displays segment C are as follows:
The Kmap I came up with, without grouping yet, is as follows:
Then, when I start grouping, I came up with multiple variations. Some utilize the don't care conditions, and some don't. I'd like to know which one(s) are correct. It seems to me that they are all correct because I am following the grouping rules. If there isn't a single correct answer, then how do I know if the one I have is an acceptable answer?
Here is the list I came up with:
Finally, looking on the web, I encountered a site where they also have their version of the "solution". However, in one of their grouping, they have grouped 12 1s. One of the rules for grouping was that you can have only 2^n number of elements in a group. So, with that said, I don't know how their solution is correct. Here is the link that I am referring to:
other segment c kmap solution
Can somebody please clarify my confusions? Thanks!
AI: All of your solutions are correct. You have covered all the 1 cases in valid terms, and not covered any 0 cases.
However, of them, the last one is closest to optimal. It uses the fewest terms, and its terms are the simplest. It's possible to optimize it slightly by "expanding" one of the terms.
Specifically, the red term can be expanded to the left, changing it from b⋅c to simply b. This makes the formula b + c̅ + d. |
H: ESD/overvoltage protection with DM1231-02SO TVS array
I'm protecting a USB2.0 IC against ESD and overvoltage at the USB connector using a Diodes Incorporated DM1231-02SO TVS (dual) array. The datasheet labels the pins IN and OUT, but it's not 100% clear which of those should be on the USB connector side and which on the IC side. The datasheet refers to zapping at the OUT pins, which significantly implies that the OUT pins should be on the connector side.
My questions:
Is my assumption correct that the OUT pins should be connected to the USB connector pins (and that this is an appropriate device for USB2.0 protection)?
What is the electrical explanation for placing the device that way around?
AI: Your interpretation is correct (note that the datasheet under Features (page 1) indicates a 12kV rating on the OUT pins vs 4kV on the IN pins which makes the in/out characteristic non-symmetric.
The equivalent schematic looks suspect to me, though- check Texas Instruments TPD2S017 part, which is basically the same thing (with the in/out nomenclature irritatingly reversed).
The TI part has slightly lower ESD ratings, but makes no mention of a 12kV/4kV difference between the two ports. It does have a brief explanation of the reasoning behind the two stage ESD filter as does their slya014a document, but in a nutshell, the resistor/2nd stage diode forms a (relatively speaking) low pass filter with the diode capacitance, providing a little more protection from ultra-fast spikes (in comparison to USB signal rates anyway).
You may want to contact both of the manufacturers to get clarification on those datasheets. |
H: Interfacing an LPC2148 with a CAN module
I need to implement the CAN protocol to communicate between two LPC2148s. Now I am planning to use SPI for communication between a microcontroller and a CAN controller and then the CAN protocol for communication between two nodes.
Why do we need CAN transceivers? What does a CAN controller and a CAN transceiver do individually? Or in short, how does data from one node to another node flow?
I know this may be long answer, but I am not finding any resource on the Internet which can tell me all about communication from one node to another through SPI-CAN.
AI: The CAN controller handles the actual CAN traffic, including bus arbitration, synchronization, CRC calculation etc etc. It is the brain of the communication, so to speak.
The CAN transceiver only handles the physical signal levels: voltage levels and the translation to/from differential signals. It also contains a lot of protection circuits against transients, ESD, brown-outs, short-circuits etc. These are very rugged circuits that can take quite a beating.
As a simplification, we can think of the CAN transceiver as layer 1 of the OSI model and the controller as layer 2.
That being said, using external CAN controllers is mostly a thing of the past, unless you have very specific requirements. For the past 20 years or so, the CAN controller is most often integrated in the MCU. The benefits of this are many: less error-prone, easier to work with, faster real-time access, cheaper, less board space needed.
So do yourself a big favour and forget about your LPC2148, but instead pick a MCU with CAN controller on-chip. NXP for example, have plenty of those to pick from, like LPC11C or Kinetis. As a bonus, you get an upgrade from legacy ARM7 to Cortex M. |
H: Using PWM instead of real DC for VFD's 0-10V control input
There is a VFD which controls an AC motor through a 0-10V control. I know that this control voltage is DC voltage.
I'm wondering would a PWM work for this application? I mean instead of 2VDC, what happens if one applies 0-10V 500Hz pulse train with 20% duty cycle? In theory this corresponds to 2VDC but since it is PWM, I'm hesitating to even try.
AI: They may or may not have sufficient filtering in there for whatever PWM signal timebase you can generate.
As a guess, they probably would put some filtering that would handle mains ripple on the input line so if you had a PWM timebase in the kHz it might have low enough ripple to not cause issues.
Worst case will be 50% duty cycle and I would expect the effect of too much ripple would be a beating of frequencies (sampling vs. PWM) resulting in a modulation of RPM with time.
Since you have to generate the PWM anyway and likely have to boost the voltage from logic level to 10V, you may as well filter it and buffer it properly, in my opinion. The few parts (say an LM324 and a few resistors and capacitors) cost virtually nothing compared to playing around with this kind of thing. |
H: Elements' order in a circuit
I was reading about source transformations and came across an example where there was a change in the order of two series elements, is this always possible? The same for in parallel elements but that makes sens since they have the same voltage.
AI: Yes, you can always swap the order of two series elements and the circuit will still perform identically. |
H: Is this current clamp meter measuring correct according to its specs?
A 24V DC power supply is supplying around 2.4A to a pure resistive load.
The input voltage is 230Vrms. So I estimated the rms current drawn from the power network as:
P/230 = (24*2.4)/230 = 250mA.
And with a multimeter this current is measured as around 260mA.
So it was consistent.
But when I measured with a current clampmeter(which is very new with a calibration certificate),
the clampmeter shows around 430mA.
(I measure the rms value of the Line current in both multimeter and clampmeter cases)
Here is the manual of the clampmeter. And under the electrical specifications it provides the following:
And here is the part from the calibration certificate:
Given the electrical characteristics and the calibration information, is 430mA measurement for a 260mA current expected for the provided error range or something is wrong?
AI: You appear to be assuming 100 % efficiency in the power supply. If it is a linearly regulated supply, it will be well short of this. Even a switchmode might be only 70~80 %. The other thing to take into account is the power factor of the supply. A normal transformer/rectifier/capacitor supply may have a power factor of 0.66, at a guess. This would mean that the product of the input rms voltage and rms current will be about 50 % higher than the real power delivered. |
H: Vivado simulation stuck at 0 fs
I am trying to simulate a D flip flop using Vivado 2018.2.2.
But upon running the simulation a window pops up stating Current time: 0 fs. The program doesn't freeze, it just doesn't progress. Here is the code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY Dff IS
port (d, clk, rst: in std_logic;
q : out std_logic);
END ENTITY Dff;
ARCHITECTURE behav OF Dff IS
BEGIN
main : PROCESS
BEGIN
IF rst='1' THEN
q <= '0';
ELSIF rising_edge(clk) THEN
q <= d;
END IF;
END PROCESS main;
END ARCHITECTURE behav;
And the test bench:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY Dff_tb IS
END Dff_tb;
ARCHITECTURE behav OF Dff_tb IS
CONSTANT T : time := 10 ns;
CONSTANT N : INTEGER := 3;
COMPONENT Dff
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL q : std_logic;
SIGNAL sim_data : std_logic_vector (N downto 0) := "0011";
BEGIN
Dff_0 : Dff PORT MAP (d => d, clk => clk, rst=>rst, q => q);
clk_pr : PROCESS
BEGIN
clk <= '0';
WAIT FOR T/2;
clk <= '1';
WAIT FOR T/2;
END PROCESS clk_pr;
main_pr : PROCESS
VARIABLE i : INTEGER := 0;
BEGIN
rst <= '1';
wait for T*2;
rst <= '0';
d <= '0';
wait for T*2;
rst <= '0';
d <= '1';
wait;
END PROCESS main_pr;
END ARCHITECTURE behav;
I am new to VHDL so It is probably something obvious.
Any help is appreciated.
EDIT:
Following a comment, I edited my test bench code like this:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY Dff_tb IS
END Dff_tb;
ARCHITECTURE behav OF Dff_tb IS
CONSTANT T : time := 10 ns;
CONSTANT N : INTEGER := 3;
COMPONENT Dff
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic
);
END COMPONENT;
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL q : std_logic;
SIGNAL sim_data : std_logic_vector (N downto 0) := "0011";
SHARED VARIABLE sim_end : boolean := false;
BEGIN
Dff_0 : Dff PORT MAP (d => d, clk => clk, rst=>rst, q => q);
clk_pr : PROCESS
BEGIN
IF sim_end = false THEN
clk <= '0';
WAIT FOR T/2;
clk <= '1';
WAIT FOR T/2;
ELSE
WAIT;
END IF;
END PROCESS clk_pr;
main_pr : PROCESS
VARIABLE i : INTEGER := 0;
BEGIN
rst <= '1';
wait for T*2;
rst <= '0';
d <= '0';
wait for T*2;
rst <= '0';
d <= '1';
sim_end := true;
wait;
END PROCESS main_pr;
END ARCHITECTURE behav;
But the problem stil persists.
AI: EDIT: Besides the problem mentioned below, I found the problem in the Dff entity itself (I was focused on the testbench, sorry for that): The main process hasn't any wait statement of any sort. Either add a sensitivity list to main process:
main : PROCESS (clk, rst)
Or add a wait statement inside main process:
wait on clk, rst;
That should fix it.
Your simulation doesn't terminate since the clk_pr process will run forever. Here's a simple solution:
--- clock generator
clk <= not clk after 50 ns when finished /= '1' else '0';
--- rest of your test bench
main_pr : PROCESS
--- test code
--- stop clock
finished <= '1';
wait;
END PROCESS;
Of course you can replace 50 ns with the constant you use, remember to add a finished signal to the test bench initialized to '0'. |
H: Why the voltage suddenly reduces when thyristors change from forward blocking to conduction mode
As per the diagram:
v-I characteristics of SCR is a graph of anode current I A on y-axis & anode to cathode Voltage plotted on x-axis v-I characteristics can be split into two parts namely Forward Characteristics & Reverse Characteristics.
Now why does the Vak suddenly drops to Vh during conduction... This is unlike a diode where the voltage remains constant even after avalanche breakdown...
Please can anyone explain this isusue to me!
AI: An SCR is not the same as a diode, the foldback indicates that there is voltage that the SCR will start conducting, without specifically applying gate current (which is normally the way you would use it). It in effect an avalanche affect.
For a nice explanation (sorry for the fragmented link on the original, google seems to have it right):
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwjS0-aLh5DeAhVpw1kKHYlLD-QQFjABegQIBBAC&url=https%3A%2F%2Fcie-wc.edu%2FSCRs9_29_11.pdf&usg=AOvVaw1fnW528a8o0eYbvpII_Cfr |
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