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stringlengths 1
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/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
// See section 7.1.2 DMA Request Assignments in MPC5634M RM
typedef enum
{
DMA_ADC_GROUP0_COMMAND_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_ADC_GROUP1_COMMAND_CHANNEL,
DMA_ADC_GROUP1_RESULT_CHANNEL,
DMA_ADC_GROUP2_COMMAND_CHANNEL,
DMA_ADC_GROUP2_RESULT_CHANNEL,
DMA_ADC_GROUP3_COMMAND_CHANNEL,
DMA_ADC_GROUP3_RESULT_CHANNEL,
DMA_ADC_GROUP4_COMMAND_CHANNEL,
DMA_ADC_GROUP4_RESULT_CHANNEL,
DMA_ADC_GROUP5_COMMAND_CHANNEL,
DMA_ADC_GROUP5_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL,
DMA_DSPI_C_RESULT_CHANNEL,
DECFIL_FILL_BUF_CHANNEL,
DECFIL_DRAIN_BUF_CHANNEL,
SCI_A_TDRE_TC_TXRDY_CHANNEL,
SCI_A_RDRF_RXRDY_CHANNEL,
DMA_EMIOS_0_CHANNEL,
DMA_EMIOS_1_CHANNEL,
DMA_EMIOS_2_CHANNEL,
DMA_EMIOS_3_CHANNEL,
DMA_EMIOS_4_CHANNEL,
DMA_EMIOS_8_CHANNEL,
DMA_EMIOS_9_CHANNEL,
DMA_TPU_0_CHANNEL,
DMA_TPU_1_CHANNEL,
DMA_TPU_2_CHANNEL,
DMA_TPU_14_CHANNEL,
DMA_TPU_15_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_ADC_GROUP0_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Dma_Cfg.h
|
C
|
unknown
| 1,961
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Eep_Cfg.h
|
C
|
unknown
| 4,149
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Eep_Lcfg.c
|
C
|
unknown
| 4,042
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5634M)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[] = {
/* NO RWW */
{
/* Bank 0, Array 0 (LOW) */
.sectCnt = 10,
.bankSize = 0x80000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x04000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x08000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x10000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x18000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
.sectAddr[5] = 0x1c000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
.sectAddr[6] = 0x20000, /* 6, B0F5, LOW */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 6,
.sectAddr[7] = 0x30000, /* 7, B0F5, LOW */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 7,
.sectAddr[8] = 0x40000, /* 6, B0F6, MID */
.addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[9] = 0x60000, /* 7, B0F7, MID */
.addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
.sectAddr[10] = 0x80000,
},
{
/* Bank 1, Array 1(HIGH) */
.sectCnt = 4,
.bankSize = 0x100000 - 0x80000,
.regBase = 0xC3FB0000UL,
.sectAddr[0] = 0x80000, /* High */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[1] = 0xA0000, /* High */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[2] = 0xC0000, /* High */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[3] = 0xE0000, /* High */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[4] = 0x100000, /* End, NOT a sector */
},
{
/* Bank 1, Array 2(HIGH) */
.sectCnt = 4,
.bankSize = 0x180000 - 0x100000,
.regBase = 0xC3FB4000UL,
.sectAddr[0] = 0x100000, /* High */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[1] = 0x120000, /* High */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[2] = 0x140000, /* High */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[3] = 0x160000, /* High */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[4] = 0x180000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Fls_Cfg.c
|
C
|
unknown
| 4,223
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5634M)
#define FLASH_BANK_CNT 3
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 10
#define FLS_TOTAL_SIZE ((16*4+32*2+64*2+128*10)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Fls_Cfg.h
|
C
|
unknown
| 3,640
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Wdg_Cfg.h
|
C
|
unknown
| 1,390
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x200,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 4000000,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 4000000,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,252
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z4D MPC55XX MPC5643L BRD_MPC5643L_SPC56L
CFG+=SPE_FPU_SCALAR_SINGLE
CFG+=MCU_ARC_CONFIG FCCU
CFG+=CREATE_SREC
CFG+=OS_SYSTICK2
CFG+=VLE
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI FLS
# Required modules
ifndef NOKERNEL
MOD_USE += MCU KERNEL
endif
# Defines
def-y += SRAM_SIZE=0x20000
ifndef NOKERNEL
def-y += L_BOOT_RESERVED_SPACE=0x20000
endif
# Default cross compiler
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
SPE_FPU_SCALAR_SINGLE=$(if $(filter $(CFG),SPE_FPU_SCALAR_SINGLE),y)
nospe=$(if $(SPE_FPU_SCALAR_SINGLE),n,y)
diab-$(vle)$(nospe)+=-tPPCE200Z3VFN:simple
diab-$(novle)$(nospe)+=-tPPCE200Z3NFS:simple
diab-$(vle)$(SPE_FPU_SCALAR_SINGLE)+=-tPPCE200Z3VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc563xm
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/build_config.mk
|
Makefile
|
unknown
| 1,284
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/config/Eep_Lcfg.c
|
C
|
unknown
| 4,071
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5643L)
#define FLASH_REGS_BASE 0xC3F88000UL
/* RWW between partitions*
*
* LOW 2*16KB + + 2*48KB + 2*64KB = 256KB
* MID 2*128KB = 256KB
* HIGH 4*128KB = 512KB
*/
const FlashType flashInfo[] = {
[0].sectCnt = 10,
[0].bankSize = 0x100000,
[0].regBase = FLASH_REGS_BASE,
/* LOW */
[0].sectAddr[0] = 0,
[0].addrSpace[0] = ADDR_SPACE(0, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[1] = 0x00004000,
[0].addrSpace[1] = ADDR_SPACE(1, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[2] = 0x00010000,
[0].addrSpace[2] = ADDR_SPACE(2, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[3] = 0x0001C000,
[0].addrSpace[3] = ADDR_SPACE(3, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[4] = 0x00020000,
[0].addrSpace[4] = ADDR_SPACE(4, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[5] = 0x00030000,
[0].addrSpace[5] = ADDR_SPACE(5, ADDR_SPACE_LOW, 2 ),
/* MID */
[0].sectAddr[6] = 0x00040000,
[0].addrSpace[6] = ADDR_SPACE(0, ADDR_SPACE_MID, 3 ),
[0].sectAddr[7] = 0x00060000,
[0].addrSpace[7] = ADDR_SPACE(1, ADDR_SPACE_MID, 3 ),
/* HIGH */
[0].sectAddr[8] = 0x00080000,
[0].addrSpace[8] = ADDR_SPACE(0, ADDR_SPACE_HIGH, 4 ),
[0].sectAddr[9] = 0x000C0000,
[0].addrSpace[9] = ADDR_SPACE(1, ADDR_SPACE_HIGH, 4 ),
[0].sectAddr[10] = 0x00100000, /* End, NOT a sector */
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/config/Fls_Cfg.c
|
C
|
unknown
| 2,957
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_ON
//#define FLS_TOTAL_SIZE
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5643L)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 10
#define FLS_TOTAL_SIZE (2*(16+48+64+128+256)*1024)
#else
#error CPU not supported
#endif
#include "Fls_ConfigTypes.h"
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/config/Fls_Cfg.h
|
C
|
unknown
| 2,850
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/config/Wdg_Cfg.h
|
C
|
unknown
| 1,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 200, // ms
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 2000, // ms
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5643l_spc56l/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,253
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z4 MPC55XX MPC5XXX MPC564XA MPC5644A BRD_MPC5644A_XPC564A TIMER_TB
CFG+=SPE_FPU_SCALAR_SINGLE
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=OS_SYSTICK2
CFG+=VLE
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG FLS SPI
# Required modules
MOD_USE += MCU KERNEL
# Defines
def-y += SRAM_SIZE=0x00030000
# Default cross compiler
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
SPE_FPU_SCALAR_SINGLE=$(if $(filter $(CFG),SPE_FPU_SCALAR_SINGLE),y)
nospe=$(if $(SPE_FPU_SCALAR_SINGLE),n,y)
diab-$(vle)$(nospe)+=-tPPCE200Z3VFN:simple
diab-$(novle)$(nospe)+=-tPPCE200Z3NFS:simple
diab-$(vle)$(SPE_FPU_SCALAR_SINGLE)+=-tPPCE200Z3VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
#GHS_TARGET?=ppc563xm
#def-y += L_BOOT_RESERVED_SPACE=0x10000
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/build_config.mk
|
Makefile
|
unknown
| 1,323
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#include "Dma.h"
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_FILL_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_DRAIN_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_TDRE_TC_TXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_RDRF_RXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
};
const Dma_ConfigType DmaConfig []=
{
{DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}
};
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Dma_Cfg.c
|
C
|
unknown
| 3,999
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
// See section 7.1.2 DMA Request Assignments in MPC5634M RM
typedef enum
{
DMA_ADC_GROUP0_COMMAND_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_ADC_GROUP1_COMMAND_CHANNEL,
DMA_ADC_GROUP1_RESULT_CHANNEL,
DMA_ADC_GROUP2_COMMAND_CHANNEL,
DMA_ADC_GROUP2_RESULT_CHANNEL,
DMA_ADC_GROUP3_COMMAND_CHANNEL,
DMA_ADC_GROUP3_RESULT_CHANNEL,
DMA_ADC_GROUP4_COMMAND_CHANNEL,
DMA_ADC_GROUP4_RESULT_CHANNEL,
DMA_ADC_GROUP5_COMMAND_CHANNEL,
DMA_ADC_GROUP5_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL,
DMA_DSPI_C_RESULT_CHANNEL,
DECFIL_FILL_BUF_CHANNEL,
DECFIL_DRAIN_BUF_CHANNEL,
SCI_A_TDRE_TC_TXRDY_CHANNEL,
SCI_A_RDRF_RXRDY_CHANNEL,
DMA_EMIOS_0_CHANNEL,
DMA_EMIOS_1_CHANNEL,
DMA_EMIOS_2_CHANNEL,
DMA_EMIOS_3_CHANNEL,
DMA_EMIOS_4_CHANNEL,
DMA_EMIOS_8_CHANNEL,
DMA_EMIOS_9_CHANNEL,
DMA_TPU_0_CHANNEL,
DMA_TPU_1_CHANNEL,
DMA_TPU_2_CHANNEL,
DMA_TPU_14_CHANNEL,
DMA_TPU_15_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_ADC_GROUP0_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Dma_Cfg.h
|
C
|
unknown
| 1,961
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Eep_Cfg.h
|
C
|
unknown
| 4,149
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Eep_Lcfg.c
|
C
|
unknown
| 4,042
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5644A)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[] = {
/* NO RWW */
/* Bank 0, Array 0 (LOW + MID) */
{
.sectCnt = 12,
.bankSize = 0x80000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x04000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x08000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x0C000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x10000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
.sectAddr[5] = 0x14000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
.sectAddr[6] = 0x18000, /* 6, B0F6, LOW */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 6,
.sectAddr[7] = 0x1C000, /* 7, B0F7, LOW */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 7,
.sectAddr[8] = 0x20000, /* 8, B0F8, LOW */
.addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 8,
.sectAddr[9] = 0x30000, /* 9, B0F9, LOW */
.addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 9,
.sectAddr[10] = 0x40000, /* 10, B0F10, MID */
.addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[11] = 0x60000, /* 11, B0F11, MID */
.addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
.sectAddr[12] = 0x80000, /* End, NOT a sector */
},
{
/* Bank 0, Array 1(HIGH) */
.sectCnt = 6,
.bankSize = 0x400000 - 0x100000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0x100000, /* High */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[1] = 0x180000, /* High */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[2] = 0x200000, /* High */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[3] = 0x280000, /* High */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[4] = 0x300000, /* High */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
.sectAddr[5] = 0x380000, /* High */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
.sectAddr[6] = 0x400000, /* End, NOT a sector */
},
{
/* Bank 1, Array 0(HIGH) */
.sectCnt = 2,
.bankSize = 0x100000-0x80000,
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x80000, /* LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0xC0000, /* MID */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[2] = 0x100000, /* End, NOT a sector */
},
{
// The high address space for the controller is a mix of controller a and b. They overlap each
// other every 16 byte. That is why this double declaration is required.
/* Bank 1, Array 1(HIGH) */
.sectCnt = 6,
.bankSize = 0, //This is intended.
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x100000, /* High */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[1] = 0x180000, /* High */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[2] = 0x200000, /* High */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[3] = 0x280000, /* High */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[4] = 0x300000, /* High */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
.sectAddr[5] = 0x380000, /* High */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
.sectAddr[6] = 0x400000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Fls_Cfg.c
|
C
|
unknown
| 5,323
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5644A)
#define FLASH_A_MCR 0xC3F88000UL
#define FLASH_A_HLR 0xC3F88008UL
#define FLASH_B_MCR 0xC3F8C000UL
#define FLASH_B_HLR 0xC3F8C008UL
#define FLASH_A_HIGH_ADDR_BANK 1
#define FLASH_B_HIGH_ADDR_BANK 3
#define FLASH_CTRL_ALIGNMENT_MASK 0x10
#define FLASH_ALIGNMENT_LENGTH 0x10
#define FLASH_BANK_CNT 4
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 12
#define FLS_TOTAL_SIZE ((16*8+64*2+128*2+256*2+512*6)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Fls_Cfg.h
|
C
|
unknown
| 3,994
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Wdg_Cfg.h
|
C
|
unknown
| 1,392
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x200,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 4000000,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 4000000,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5644a_xpc564a/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,252
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z4D MPC55XX MPC5645S BRD_MPC5645S_DEMO_V2 TIMER TIMER_TB
CFG+=VLE
CFG+=SPE_FPU_SCALAR_SINGLE
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=MCU_ARC_LP
CFG+=OS_SYSTICK2
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG FLS SPI ICU OCU
# Complex device drivers
MOD_AVAIL+=CDD_LINSLV
# Required modules
MOD_USE += MCU KERNEL
# Defines
#def-y += SRAM_SIZE=0x30000
# Default cross compiler
COMPILER?=gcc
COMPILER_FLAVOR=s32_newlib
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
SPE_FPU_SCALAR_SINGLE=$(if $(filter $(CFG),SPE_FPU_SCALAR_SINGLE),y)
nospe=$(if $(SPE_FPU_SCALAR_SINGLE),n,y)
diab-$(vle)$(nospe)+=-tPPCE200Z4DVFS:simple
diab-$(novle)$(nospe)+=-tPPCE200Z4DNMS:simple
diab-$(vle)$(SPE_FPU_SCALAR_SINGLE)+=-tPPCE200Z4DVFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
GHS_TARGET?=ppc564xs
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/build_config.mk
|
Makefile
|
unknown
| 1,292
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Dma.h"
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_RX
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
}
};
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S) || defined(CFG_MPC5645S)
DmaMuxConfig,
#endif
DmaChannelConfig,
DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Dma_Cfg.c
|
C
|
unknown
| 2,490
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
typedef enum
{
DMA_DSPI_A_COMMAND_CHANNEL = 2,
DMA_DSPI_A_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL,
DMA_DSPI_C_RESULT_CHANNEL,
/*DMA_CHANNEL8,
DMA_CHANNEL9,
DMA_CHANNEL10,
DMA_CHANNEL11,
DMA_CHANNEL12,
DMA_CHANNEL13,
DMA_CHANNEL14,
DMA_CHANNEL15,*/
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_DSPI_A_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Dma_Cfg.h
|
C
|
unknown
| 1,292
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_M9525
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Eep_Lcfg.c
|
C
|
unknown
| 4,070
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
/*lint -e940 -e785 -e835 -e9027 -e845 To increase readability */
const FlashType flashInfo[2] = {
[0].sectCnt = 18,
[0].bankSize = 0x100000,
[0].regBase = 0xc3f88000UL,
/* LOW */
[0].sectAddr[0] = 0,
[0].addrSpace[0] = ADDR_SPACE(0, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[1] = 0x00004000,
[0].addrSpace[1] = ADDR_SPACE(1, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[2] = 0x00008000,
[0].addrSpace[2] = ADDR_SPACE(2, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[3] = 0x0000c000,
[0].addrSpace[3] = ADDR_SPACE(3, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[4] = 0x00010000,
[0].addrSpace[4] = ADDR_SPACE(4, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[5] = 0x00014000,
[0].addrSpace[5] = ADDR_SPACE(5, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[6] = 0x00018000,
[0].addrSpace[6] = ADDR_SPACE(6, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[7] = 0x0001c000,
[0].addrSpace[7] = ADDR_SPACE(7, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[8] = 0x00020000,
[0].addrSpace[8] = ADDR_SPACE(8, ADDR_SPACE_LOW, 3 ),
[0].sectAddr[9] = 0x00030000,
[0].addrSpace[9] = ADDR_SPACE(9, ADDR_SPACE_LOW, 3 ),
/* MID */
[0].sectAddr[10] = 0x00040000,
[0].addrSpace[10] = ADDR_SPACE(0, ADDR_SPACE_MID, 4 ),
[0].sectAddr[11] = 0x00060000,
[0].addrSpace[11] = ADDR_SPACE(1, ADDR_SPACE_MID, 4 ),
/* HIGH */
[0].sectAddr[12] = 0x00080000,
[0].addrSpace[12] = ADDR_SPACE(0, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[13] = 0x000c0000,
[0].addrSpace[13] = ADDR_SPACE(1, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[14] = 0x00100000,
[0].addrSpace[14] = ADDR_SPACE(2, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[15] = 0x00140000,
[0].addrSpace[15] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[16] = 0x00180000,
[0].addrSpace[16] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 7 ),
[0].sectAddr[17] = 0x001c0000,
[0].addrSpace[17] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 7 ),
[0].sectAddr[18] = 0x00200000, /* End, NOT a sector */
};
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Fls_Cfg.c
|
C
|
unknown
| 3,298
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_ON
//#define FLS_TOTAL_SIZE
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 18
#define FLS_TOTAL_SIZE (2*1024*1024)
#include "Fls_ConfigTypes.h"
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Fls_Cfg.h
|
C
|
unknown
| 2,418
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Std_Types.h"
#include "Mcu.h"
#include "Mcu_Arc.h"
#include "asm_ppc.h"
/* #warning "This default file may only be used as an example!" */
/**
* @param sleepCfg
*/
void Mcu_Arc_SetModePre2( Mcu_ModeType mcuMode, const struct Mcu_Arc_SleepConfig *sleepCfg ) {
(void)mcuMode; /*lint !e920 Argument not used */
(void)sleepCfg; /*lint !e920 Argument not used */
}
/**
* @param sleepCfg
*/
void Mcu_Arc_SetModePost2( Mcu_ModeType mcuMode, const struct Mcu_Arc_SleepConfig *sleepCfg ) {
(void)mcuMode;
(void)sleepCfg; /*lint !e920 Argument not used */
}
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Mcu_Arc_Cfg.c
|
C
|
unknown
| 1,372
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MCU_ARC_CFG_H_
#define MCU_ARC_CFG_H_
#if !defined(_ASSEMBLER_)
struct Mcu_Arc_SleepPrivData {
uint32_t dummy;
};
typedef struct Mcu_Arc_SleepConfig {
uint32_t dummy;
struct Mcu_Arc_SleepPrivData *pData;
} Mcu_Arc_SleepConfigType;
typedef struct Mcu_Arc_Config {
const struct Mcu_Arc_SleepConfig *sleepConfig;
const struct TlbEntry *tblTable;
} Mcu_Arc_ConfigType;
extern const struct Mcu_Arc_Config Mcu_Arc_ConfigData;
#endif
#endif /* MCU_ARC_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Mcu_Arc_Cfg.h
|
C
|
unknown
| 1,276
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0u
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Wdg_Cfg.h
|
C
|
unknown
| 1,409
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x200,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 0x7D00,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5645s_demo_v2/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,250
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG+=PPC E200Z4D MPC55XX MPC5646B BRD_MPC5646B_XPC564XBC
CFG+=VLE
CFG+=SPE_FPU_SCALAR_SINGLE
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
#CFG+=SPE
CFG+=TIMER
CFG+=TIMER_RTC
CFG+=MCU_ARC_LP
CFG+=OS_SYSTICK2
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI OCU ICU FLS
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=cw
COMPILER_FLAVOR=s32_newlib
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
# Defines
#def-y += __BIG_ENDIAN__
def-y += SRAM_SIZE=0x30000
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
SPE_FPU_SCALAR_SINGLE=$(if $(filter $(CFG),SPE_FPU_SCALAR_SINGLE),y)
nospe=$(if $(SPE_FPU_SCALAR_SINGLE),n,y)
diab-$(vle)$(nospe)+=-tPPCE200Z4DVFS:simple
diab-$(novle)$(nospe)+=-tPPCE200Z4DNMS:simple
diab-$(vle)$(SPE_FPU_SCALAR_SINGLE)+=-tPPCE200Z4DVFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
GHS_TARGET?=ppc564xs
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/build_config.mk
|
Makefile
|
unknown
| 1,382
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Dma.h"
#if defined(CFG_MPC5646B)
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_MUXES] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_6_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_6_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_7_TX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_DSPI_7_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_0_FLAG_F0
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_0_FLAG_F1
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_0_FLAG_F9
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_0_FLAG_F18
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_0_FLAG_F25
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_0_FLAG_F26
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_1_FLAG_F0
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_1_FLAG_F1
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_1_FLAG_F9
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_1_FLAG_F18
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_1_FLAG_F25
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_EMIOS200_1_FLAG_F26
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_ADC_A
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_ADC_B
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_I2C_0_RX
},
{
.DMA_CHANNEL_ENABLE = TRUE, .DMA_CHANNEL_TRIG_ENABLE = FALSE, .DMA_CHANNEL_SOURCE = DMA_I2C_0_TX
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_0_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_0_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_1_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_1_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_2_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_2_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_3_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_3_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_4_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_4_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_5_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_5_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_6_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_6_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_7_TX */
},
{
.DMA_CHANNEL_PRIORITY = 1u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DSPI_7_RX */
},
{
.DMA_CHANNEL_PRIORITY = 15u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_0_FLAG_F0 */
},
{
.DMA_CHANNEL_PRIORITY = 14u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_0_FLAG_F1 */
},
{
.DMA_CHANNEL_PRIORITY = 13u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_0_FLAG_F9 */
},
{
.DMA_CHANNEL_PRIORITY = 12u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_0_FLAG_F18 */
},
{
.DMA_CHANNEL_PRIORITY = 11u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_0_FLAG_F25 */
},
{
.DMA_CHANNEL_PRIORITY = 10u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_0_FLAG_F26 */
},
{
.DMA_CHANNEL_PRIORITY = 9u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_1_FLAG_F0 */
},
{
.DMA_CHANNEL_PRIORITY = 8u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_1_FLAG_F1 */
},
{
.DMA_CHANNEL_PRIORITY = 7u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_1_FLAG_F9 */
},
{
.DMA_CHANNEL_PRIORITY = 6u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_1_FLAG_F18 */
},
{
.DMA_CHANNEL_PRIORITY = 5u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_1_FLAG_F25 */
},
{
.DMA_CHANNEL_PRIORITY = 4u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_EMIOS200_1_FLAG_F26 */
},
{
.DMA_CHANNEL_PRIORITY = 3u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_ADC_A */
},
{
.DMA_CHANNEL_PRIORITY = 2u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_ADC_B */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_I2C_0_RX */
},
{
.DMA_CHANNEL_PRIORITY = 0u, .DMA_CHANNEL_PREEMTION_ENABLE = TRUE /* DMA_I2C_0_TX */
}
};
#else
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC0
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_D_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_D_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_E_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_E_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_F_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_F_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
}
};
#endif
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_DMA_MUX)
DmaMuxConfig,
#endif
.dmaChannelConfigPtr = DmaChannelConfig,
.dmaChannelArbitration = DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Dma_Cfg.c
|
C
|
unknown
| 11,963
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
/* enum is used to initialize DMA channels NOT DMA MUX-es
5646B/C has 32 DMA channels
*/
typedef enum
{
DMA_CHANNEL_0, /* 0 */
DMA_CHANNEL_1, /* 1 */
DMA_CHANNEL_2, /* 2 */
DMA_CHANNEL_3, /* 3 */
DMA_CHANNEL_4, /* 4 */
DMA_CHANNEL_5, /* 5 */
DMA_CHANNEL_6, /* 6 */
DMA_CHANNEL_7, /* 7 */
DMA_CHANNEL_8, /* 8 */
DMA_CHANNEL_9, /* 9 */
DMA_CHANNEL_10, /* 10 */
DMA_CHANNEL_11, /* 11 */
DMA_CHANNEL_12, /* 12 */
DMA_CHANNEL_13, /* 13 */
DMA_CHANNEL_14, /* 14 */
DMA_CHANNEL_15, /* 15 */
DMA_CHANNEL_16, /* 16 */
DMA_CHANNEL_17, /* 17 */
DMA_CHANNEL_18, /* 18 */
DMA_CHANNEL_19, /* 19 */
DMA_CHANNEL_20, /* 20 */
DMA_CHANNEL_21, /* 21 */
DMA_CHANNEL_22, /* 22 */
DMA_CHANNEL_23, /* 23 */
DMA_CHANNEL_24, /* 24 */
DMA_CHANNEL_25, /* 25 */
DMA_CHANNEL_26, /* 26 */
DMA_CHANNEL_27, /* 27 */
DMA_CHANNEL_28, /* 28 */
DMA_CHANNEL_29, /* 29 */
DMA_CHANNEL_30, /* 30 */
DMA_CHANNEL_31, /* 31 */
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_CHANNEL_0
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Dma_Cfg.h
|
C
|
unknown
| 2,002
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Eep_Lcfg.c
|
C
|
unknown
| 4,053
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5646B)
/*lint -e940 -e785 -e835 -e9027 -e845 -e651 To increase readability */
const FlashType flashInfo[3] = {
/* NO RWW */
/* Bank 0, code flash memory */
{
.sectCnt = 16,
.bankSize = 0x180000UL,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x08000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x10000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x18000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
.sectAddr[5] = 0x20000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
.sectAddr[6] = 0x40000, /* 6, B0F6, MID */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[7] = 0x60000, /* 7, B0F7, MID */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
.sectAddr[8] = 0x80000, /* 8, B0F8, MID */
.addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[9] = 0xA0000, /* 9, B0F9, HIGH */
.addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[10] = 0xC0000, /* 10, B0FA, HIGH */
.addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[11] = 0xE0000, /* 11, B0FB, HIGH */
.addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[12] = 0x100000, /* 12, B0FC, HIGH */
.addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
.sectAddr[13] = 0x120000, /* 13, B0FD, HIGH */
.addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
.sectAddr[14] = 0x140000, /* 14, B0FE, HIGH */
.addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 6,
.sectAddr[15] = 0x160000, /* 15, B0FF, HIGH */
.addrSpace[15] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 7,
.sectAddr[16] = 0x180000, /* End, NOT a sector */
},
/* NO RWW */
/* Bank 2, code flash memory */
{
.sectCnt = 16,
.bankSize = 0x300000UL - 0x180000UL,
.regBase = 0xC3FB0000UL,
.sectAddr[0] = 0x180000, /* 0, B2F8, HIGH */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[1] = 0x1A0000, /* 1, B2F9, HIGH */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[2] = 0x1C0000, /* 2, B2FA, HIGH */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[3] = 0x1E0000, /* 3, B2FB, HIGH */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[4] = 0x200000, /* 4, B2FC, HIGH */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
.sectAddr[5] = 0x220000, /* 5, B2FD, HIGH */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
.sectAddr[6] = 0x240000, /* 6, B2FE, HIGH */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 6,
.sectAddr[7] = 0x260000, /* 7, B2FF, HIGH */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 7,
.sectAddr[8] = 0x280000, /* 8, B2F0, LOW */
.addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[9] = 0x288000, /* 9, B2F1, LOW */
.addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[10] = 0x28C000, /* 10, B2F2, LOW */
.addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[11] = 0x290000, /* 11, B2F3, LOW */
.addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[12] = 0x298000, /* 12, B2F4, LOW */
.addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
.sectAddr[13] = 0x2A0000, /* 13, B2F5, LOW */
.addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
.sectAddr[14] = 0x2C0000, /* 14, B2F6, MID */
.addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[15] = 0x2E0000, /* 15, B2F7, MID */
.addrSpace[15] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
.sectAddr[16] = 0x300000, /* End, NOT a sector */
},
{
/* Data flash memory */
.sectCnt = 4,
.bankSize = 0x810000 - 0x800000,
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x800000, /* LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x804000, /* LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x808000, /* LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x80c000, /* LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x810000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Fls_Cfg.c
|
C
|
unknown
| 5,934
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5646B)
#define FLASH_BANK_CNT 2
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 16
#define FLS_TOTAL_SIZE (3*1024*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(void); /* NO SUPPORT */
void (*FlsAcWrite)(void); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)(void);
void (*FlsJobErrorNotification)(void);
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Fls_Cfg.h
|
C
|
unknown
| 3,646
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MCU_ARC_CFG_H_
#define MCU_ARC_CFG_H_
#if !defined(_ASSEMBLER_)
struct Mcu_Arc_SleepPrivData {
uint32_t dummy;
};
typedef struct Mcu_Arc_SleepConfig {
uint32_t dummy;
struct Mcu_Arc_SleepPrivData *pData;
} Mcu_Arc_SleepConfigType;
typedef struct Mcu_Arc_Config {
const struct Mcu_Arc_SleepConfig *sleepConfig;
const struct TlbEntry *tblTable;
} Mcu_Arc_ConfigType;
extern const struct Mcu_Arc_Config Mcu_Arc_ConfigData;
#endif
#endif /* MCU_ARC_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Mcu_Arc_Cfg.h
|
C
|
unknown
| 1,276
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0u
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Wdg_Cfg.h
|
C
|
unknown
| 1,406
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 200, // ms
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 2000, // ms
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5646b_xpc564xbc/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,252
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z6 MPC55XX MPC5668 BRD_MPC5668_GKIT TIMER TIMER_TB
CFG+=SPE_FPU_SCALAR_SINGLE
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=OS_SYSTICK2
CFG+=VLE
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG FLS SPI
# Required modules
MOD_USE += MCU KERNEL
# Defines
def-y += L_BOOT_RESERVED_SPACE=0x10000
def-y += SRAM_SIZE=0x00080000
# Default cross compiler
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
SPE_FPU_SCALAR_SINGLE=$(if $(filter $(CFG),SPE_FPU_SCALAR_SINGLE),y)
nospe=$(if $(SPE_FPU_SCALAR_SINGLE),n,y)
diab-$(vle)$(nospe)+=-tPPCE200Z6VFN:simple
diab-$(novle)$(nospe)+=-tPPCE200Z6NFS:simple
diab-$(vle)$(SPE_FPU_SCALAR_SINGLE)+=-tPPCE200Z6VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
#GHS_TARGET?=ppc563xm
#def-y += L_BOOT_RESERVED_SPACE=0x10000
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/build_config.mk
|
Makefile
|
unknown
| 1,344
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#include "Dma.h"
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_FILL_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_DRAIN_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_TDRE_TC_TXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_RDRF_RXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
};
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S) || defined(CFG_MPC5645S)
.dmaMuxConfigPtr = DmaMuxConfig,
#endif
.dmaChannelConfigPtr = DmaChannelConfig,
.dmaChannelArbitration = DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Dma_Cfg.c
|
C
|
unknown
| 4,209
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
// See section 7.1.2 DMA Request Assignments in MPC5634M RM
typedef enum
{
DMA_ADC_GROUP0_COMMAND_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_ADC_GROUP1_COMMAND_CHANNEL,
DMA_ADC_GROUP1_RESULT_CHANNEL,
DMA_ADC_GROUP2_COMMAND_CHANNEL,
DMA_ADC_GROUP2_RESULT_CHANNEL,
DMA_ADC_GROUP3_COMMAND_CHANNEL,
DMA_ADC_GROUP3_RESULT_CHANNEL,
DMA_ADC_GROUP4_COMMAND_CHANNEL,
DMA_ADC_GROUP4_RESULT_CHANNEL,
DMA_ADC_GROUP5_COMMAND_CHANNEL,
DMA_ADC_GROUP5_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL,
DMA_DSPI_C_RESULT_CHANNEL,
DECFIL_FILL_BUF_CHANNEL,
DECFIL_DRAIN_BUF_CHANNEL,
SCI_A_TDRE_TC_TXRDY_CHANNEL,
SCI_A_RDRF_RXRDY_CHANNEL,
DMA_EMIOS_0_CHANNEL,
DMA_EMIOS_1_CHANNEL,
DMA_EMIOS_2_CHANNEL,
DMA_EMIOS_3_CHANNEL,
DMA_EMIOS_4_CHANNEL,
DMA_EMIOS_8_CHANNEL,
DMA_EMIOS_9_CHANNEL,
DMA_TPU_0_CHANNEL,
DMA_TPU_1_CHANNEL,
DMA_TPU_2_CHANNEL,
DMA_TPU_14_CHANNEL,
DMA_TPU_15_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_ADC_GROUP0_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Dma_Cfg.h
|
C
|
unknown
| 1,961
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Eep_Cfg.h
|
C
|
unknown
| 4,149
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Eep_Lcfg.c
|
C
|
unknown
| 4,042
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5668)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[2] = {
[0].sectCnt = 18,
[0].bankSize = 0x200000,
[0].regBase = 0xFFFF8000UL,
/* LOW */
[0].sectAddr[0] = 0,
[0].addrSpace[0] = ADDR_SPACE(0, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[1] = 0x00004000,
[0].addrSpace[1] = ADDR_SPACE(1, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[2] = 0x00008000,
[0].addrSpace[2] = ADDR_SPACE(2, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[3] = 0x0000c000,
[0].addrSpace[3] = ADDR_SPACE(3, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[4] = 0x00010000,
[0].addrSpace[4] = ADDR_SPACE(4, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[5] = 0x00014000,
[0].addrSpace[5] = ADDR_SPACE(5, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[6] = 0x00018000,
[0].addrSpace[6] = ADDR_SPACE(6, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[7] = 0x0001c000,
[0].addrSpace[7] = ADDR_SPACE(7, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[8] = 0x00020000,
[0].addrSpace[8] = ADDR_SPACE(8, ADDR_SPACE_LOW, 3 ),
[0].sectAddr[9] = 0x00030000,
[0].addrSpace[9] = ADDR_SPACE(9, ADDR_SPACE_LOW, 3 ),
/* MID */
[0].sectAddr[10] = 0x00040000,
[0].addrSpace[10] = ADDR_SPACE(0, ADDR_SPACE_MID, 4 ),
[0].sectAddr[11] = 0x00060000,
[0].addrSpace[11] = ADDR_SPACE(1, ADDR_SPACE_MID, 4 ),
/* HIGH */
[0].sectAddr[12] = 0x00080000,
[0].addrSpace[12] = ADDR_SPACE(0, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[13] = 0x000c0000,
[0].addrSpace[13] = ADDR_SPACE(1, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[14] = 0x00100000,
[0].addrSpace[14] = ADDR_SPACE(2, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[15] = 0x00140000,
[0].addrSpace[15] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[16] = 0x00180000,
[0].addrSpace[16] = ADDR_SPACE(4, ADDR_SPACE_HIGH, 7 ),
[0].sectAddr[17] = 0x001c0000,
[0].addrSpace[17] = ADDR_SPACE(5, ADDR_SPACE_HIGH, 7 ),
[0].sectAddr[18] = 0x00200000, /* End, NOT a sector */
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Fls_Cfg.c
|
C
|
unknown
| 3,719
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 18
#define FLS_TOTAL_SIZE ((16*8+64*2+128*2+256*6)*1024)
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Fls_Cfg.h
|
C
|
unknown
| 3,550
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Wdg_Cfg.h
|
C
|
unknown
| 1,392
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 5000,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 20000,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 4000000,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5668_gkit/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,249
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG+=PPC E200Z4 MPC55XX MPC57XX MPC5744P CAN_OSCILLATOR_CLOCK BRD_MPC5744P_MMB
CFG+=EFPU
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
CFG+=TIMER
CFG+=TIMER_STM
CFG+=MCU_CACHE_I
CFG+=OS_SYSTICK2
CFG+=FCCU
CFG+=MCU_ARC_CLEAR_FCCU
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG FLS SPI FR
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=gcc
COMPILER_FLAVOR=s32_newlib
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
#DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.4.8/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
efpu=$(if $(filter $(CFG),EFPU),y)
nofpu=$(if $(efpu),n,y)
diab-$(vle)$(nofpu)+=-tPPCE200Z4VFN:simple
diab-$(novle)$(nofpu)+=-tPPCE200Z4NFS:simple
#diab-$(vle)$(efpu)+=-tPPCE200Z4251N3VFF:simple
diab-$(vle)$(efpu)+=-tPPCE200Z4VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc5744p
# Defines
def-y += SRAM_SIZE=0x60000
def-y += __BIG_ENDIAN__
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/build_config.mk
|
Makefile
|
unknown
| 1,458
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/config/Eep_Lcfg.c
|
C
|
unknown
| 4,073
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5744P)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[] = {
/* NO RWW */
/* Bank 0, Array 0 (LOW) */
[0].sectCnt = 21,
[0].bankSize = 0xA00000,
// [0].bankRange = BANK_RANGE_CODE_LOW,
[0].regBase = 0xFFFE0000UL,
[0].sectAddr[0] = 0x800000, /* 0x800000, B0F0, LOW */
[0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
[0].sectAddr[1] = 0x804000, /* 1, B0F1, LOW */
[0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
[0].sectAddr[2] = 0x808000, /* 2, B0F2, LOW */
[0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
[0].sectAddr[3] = 0x810000, /* 3, B0F3, LOW */
[0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
[0].sectAddr[4] = 0x818000, /* end first chunk */
[0].sectAddr[5] = 0x0F98000, /* 5, B0F4, MID */
[0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
[0].sectAddr[6] = 0x0F9C000, /* 6, B0F5, MID */
[0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
[0].sectAddr[7] = 0x0FA0000, /* 7, B0F6, HIGH */
[0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
[0].sectAddr[8] = 0x0FB0000, /* 8, B0F7, HIGH */
[0].addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
[0].sectAddr[9] = 0x0FC0000, /* 9, B0F8, HIGH */
[0].addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
[0].sectAddr[10] = 0x0FD0000, /* 10, B0F9, HIGH */
[0].addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
[0].sectAddr[11] = 0x0FE0000, /* 11, B0F10, HIGH */
[0].addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
[0].sectAddr[12] = 0x0FF0000, /* 12, B0F11, HIGH */
[0].addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
[0].sectAddr[13] = 0x1000000, /* 13, B0F12, HIGH */
[0].addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 0,
[0].sectAddr[14] = 0x1040000, /* 14, B0F13, HIGH */
[0].addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 1,
[0].sectAddr[15] = 0x1080000, /* 15, B0F14, HIGH */
[0].addrSpace[15] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 2,
[0].sectAddr[16] = 0x10C0000, /* 16, B0F15, HIGH */
[0].addrSpace[16] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 3,
[0].sectAddr[17] = 0x1100000, /* 17, B0F16, HIGH */
[0].addrSpace[17] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 4,
[0].sectAddr[18] = 0x1140000, /* 18, B0F17, HIGH */
[0].addrSpace[18] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 5,
[0].sectAddr[19] = 0x1180000, /* 19, B0F18, HIGH */
[0].addrSpace[19] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 6,
[0].sectAddr[20] = 0x11C0000, /* 20, B0F19, HIGH */
[0].addrSpace[20] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 7,
[0].sectAddr[21] = 0x1200000, /* end of flash */
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/config/Fls_Cfg.c
|
C
|
unknown
| 4,293
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5744P)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLS_FLASH_WRITE_BUFFER_SIZE 128 /* Page buffer size for C55 flash*/
#define FLASH_MAX_SECTORS 21
#define FLS_TOTAL_SIZE ((16*4+2*32+6*64+8*256)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/config/Fls_Cfg.h
|
C
|
unknown
| 3,725
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/config/Wdg_Cfg.h
|
C
|
unknown
| 1,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x200,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 0x7D00,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5744p_mmb/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,250
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z4 MPC55XX MPC57XX MPC5746C CAN_OSCILLATOR_CLOCK BRD_MPC5746c_MPC574XG_MB
#CFG+=EFPU
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
#CFG+=TIMER
CFG+=TIMER_STM
CFG+=MCU_CACHE_I
CFG+=OS_SYSTICK2
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
MOD_AVAIL+= MCU CAN LIN PORT DIO ADC SPI EEP FLS WDG ETH PWM GPT TCPIP LWIP FR ICU
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=ghs
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
#vle=$(if $(filter $(CFG),VLE),y)
#novle=$(if $(vle),n,y)
#efpu=$(if $(filter $(CFG),EFPU),y)
#nofpu=$(if $(efpu),n,y)
# VLE
GHS_TARGET?=ppc5746mz420
# Defines
def-y += __BIG_ENDIAN__
def-y += SRAM_SIZE=0x80000
|
2301_81045437/classic-platform
|
boards/mpc5746c_mpc574xg_mb/build_config.mk
|
Makefile
|
unknown
| 1,137
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_M9525
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5746c_mpc574xg_mb/config/Eep_Lcfg.c
|
C
|
unknown
| 4,011
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
/*lint -save -e9054 OTHER Not limiting the array dimension */
#if defined(CFG_MPC5746C)
/*lint -e940 -e785 -e835 -e9027 -e845 -e651 To increase readability */
const FlashType flashInfo[] = {
/* NO RWW */
/*LOW : 16*1 + 32*4 + 64*4 = 400KB*/
/*MID : 16*8 = 128KB*/
/*HIGH : 16*2 = 32KB*/
/*LARGE : 256*10 = 2560KB*/
/* Bank 0, Array 0 */
[0].sectCnt = 32,
[0].bankSize = 0xC70000UL, /* This is used only for address range validation
so the bank size will be 0x01280000 - 0x00610000 even though available actual size is only 0x30C000 as computed above */
[0].regBase = 0xFFFE0000UL, /* C55FMC_MCR register */
/*HSM code*/ /* LOW */
[0].sectAddr[0] = 0x00610000,
[0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 7,
[0].sectAddr[1] = 0x00620000,
[0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 9,
[0].sectAddr[2] = 0x00630000, /* end first chunk */
[0].addrSpace[2] = SECTOR_EMPTY,
/*HSM Data*/ /*HIGH*/
[0].sectAddr[3] = 0x00F80000,
[0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
[0].sectAddr[4] = 0x00F84000,
[0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
[0].sectAddr[5] = 0x00F88000, /* end first chunk */
[0].addrSpace[5] = SECTOR_EMPTY,
/*Small HSM Code Block*//* LOW */
[0].sectAddr[6] = 0x00F8C000,
[0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
/*Small and Medium Flash Blocks*/
/*MID*/
[0].sectAddr[7] = 0x00F90000,
[0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
[0].sectAddr[8] = 0x00F94000,
[0].addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
[0].sectAddr[9] = 0x00F98000,
[0].addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 2,
[0].sectAddr[10] = 0x00F9C000,
[0].addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 3,
[0].sectAddr[11] = 0x00FA0000,
[0].addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 4,
[0].sectAddr[12] = 0x00FA4000,
[0].addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 5,
[0].sectAddr[13] = 0x00FA8000,
[0].addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 6,
[0].sectAddr[14] = 0x00FAC000,
[0].addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 7,
[0].sectAddr[15] = 0x00FB0000,
[0].addrSpace[15] = SECTOR_EMPTY, /* Reserved area 0x00FB0000 to 0x00FBFFFF */
/*LOW*/
[0].sectAddr[16] = 0x00FC0000,
[0].addrSpace[16] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
[0].sectAddr[17] = 0x00FC8000,
[0].addrSpace[17] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
[0].sectAddr[18] = 0x00FD0000,
[0].addrSpace[18] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
[0].sectAddr[19] = 0x00FD8000,
[0].addrSpace[19] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
[0].sectAddr[20] = 0x00FE0000,
[0].addrSpace[20] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 6,
[0].sectAddr[21] = 0x00FF0000,
[0].addrSpace[21] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 8,
/*Large Flash Blocks*/ /*LARGE*/
[0].sectAddr[22] = 0x01000000,
[0].addrSpace[22] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 0,
[0].sectAddr[23] = 0x01040000,
[0].addrSpace[23] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 1,
[0].sectAddr[24] = 0x01080000,
[0].addrSpace[24] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 2,
[0].sectAddr[25] = 0x010C0000,
[0].addrSpace[25] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 3,
[0].sectAddr[26] = 0x01100000,
[0].addrSpace[26] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 4,
[0].sectAddr[27] = 0x01140000,
[0].addrSpace[27] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 5,
[0].sectAddr[28] = 0x01180000,
[0].addrSpace[28] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 6,
[0].sectAddr[29] = 0x011C0000,
[0].addrSpace[29] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 7,
[0].sectAddr[30] = 0x01200000,
[0].addrSpace[30] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 8,
[0].sectAddr[31] = 0x01240000,
[0].addrSpace[31] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 9,
[0].sectAddr[32] = 0x01280000,
[0].addrSpace[32] =SECTOR_EMPTY,
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};/*lint -restore */
|
2301_81045437/classic-platform
|
boards/mpc5746c_mpc574xg_mb/config/Fls_Cfg.c
|
C
|
unknown
| 5,470
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE 0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5746C)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 32
#define FLS_FLASH_WRITE_BUFFER_SIZE 128 /* Page buffer size for C55 flash*/
/*LOW : 16*1 + 32*4 + 64*4 = 400KB*/
/*MID : 16*8 = 128KB*/
/*HIGH : 16*2 = 32KB*/
/*LARGE : 256*10 = 2560KB*/
#define FLS_TOTAL_SIZE 0x01280000ULL /* This is used to indicate total size including the reserved areas
the effective FLASH size is computed above 0xC70000UL */
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(void); /* NO SUPPORT */
void (*FlsAcWrite)(void); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)(void);
void (*FlsJobErrorNotification)(void);
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5746c_mpc574xg_mb/config/Fls_Cfg.h
|
C
|
unknown
| 4,347
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z4 MPC55XX MPC57XX MPC5748G CAN_OSCILLATOR_CLOCK BRD_MPC5748XG_MB_324DS
CFG+=EFPU
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
#CFG+=TIMER
CFG+=TIMER_STM
CFG+=MCU_CACHE_I
CFG+=OS_SYSTICK2
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
MOD_AVAIL+=ADC DIO DMA CAN EEP FR GPT LIN MCU PORT PWM WDG FLS SPI ETH TCPIP LWIP ICU
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=ghs
COMPILER_FLAVOR=s32_newlib
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.4.8/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
#DIAB
DIAB_VERSION = 5.9.4.8
#VLE and no EFPU
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
efpu=$(if $(filter $(CFG),EFPU),y)
nofpu=$(if $(efpu),n,y)
diab-$(vle)$(nofpu)+=-tPPCE200Z4VFN:simple
diab-$(novle)$(nofpu)+=-tPPCE200Z4NFS:simple
#diab-$(vle)$(efpu)+=-tPPCE200Z4251N3VFF:simple
diab-$(vle)$(efpu)+=-tPPCE200Z4VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc5746mz420
# Defines
def-y += __BIG_ENDIAN__
def-y += SRAM_SIZE=0xC0000
|
2301_81045437/classic-platform
|
boards/mpc5748g_mpc574xg_mb/build_config.mk
|
Makefile
|
unknown
| 1,379
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_M9525
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5748g_mpc574xg_mb/config/Eep_Lcfg.c
|
C
|
unknown
| 4,037
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @tagSettings DEFAULT_ARCHITECTURE= MPC5748G */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5748G)
/*lint -e940 -e785 -e835 -e9027 -e845 -e651 OTHER To increase readability */
const FlashType flashInfo[] = {
/*
* Resources:
* - 3.3 NVM memory map
* - 74.1.1.1 C55FMC_LOCK0 and C55FMC_SEL0 register bit mapping
* - LOW - partition 0 and 1
* - MID - partition 2 and 3
* - HIGH - partition 4 and 5
* - 256 - partition 6 to 9
*
*/
/* Bank 0, Array 0 (LOW) */
[0].sectCnt = 45,
[0].bankSize = 0x019F0000,
[0].regBase = 0xFFFE0000UL,
/* HSM Code */
[0].sectAddr[0] = 0x00610000,
[0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 7,
[0].sectAddr[1] = 0x00620000,
[0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 9,
[0].sectAddr[2] = 0x00630000, /* end first chunk */
[0].addrSpace[2] = SECTOR_EMPTY,
/* HSM Data */
[0].sectAddr[3] = 0x00F80000,
[0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
[0].sectAddr[4] = 0x00F84000,
[0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
[0].sectAddr[5] = 0x00F88000, /* end first chunk */
[0].addrSpace[5] = SECTOR_EMPTY,
/* Small HSM Code Block */
[0].sectAddr[6] = 0x00F8C000,
[0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
/* Small and Medium Flash Blocks */
/* 16KB blocks */
[0].sectAddr[7] = 0x00F90000, /* partition 2 */
[0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
[0].sectAddr[8] = 0x00F94000, /* partition 2 */
[0].addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
[0].sectAddr[9] = 0x00F98000, /* partition 2 */
[0].addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 2,
[0].sectAddr[10] = 0x00F9C000, /* partition 2 */
[0].addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 3,
[0].sectAddr[11] = 0x00FA0000, /* partition 3 */
[0].addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 4,
[0].sectAddr[12] = 0x00FA4000, /* partition 3 */
[0].addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 5,
[0].sectAddr[13] = 0x00FA8000, /* partition 3 */
[0].addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 6,
[0].sectAddr[14] = 0x00FAC000, /* partition 3 */
[0].addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 7,
[0].sectAddr[15] = 0x00FB0000, /* partition 2 */
[0].addrSpace[15] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 8,
[0].sectAddr[16] = 0x00FB8000, /* partition 3 */
[0].addrSpace[16] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 9,
/* LOW */
[0].sectAddr[17] = 0x00FC0000, /* partition 0 */
[0].addrSpace[17] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
[0].sectAddr[18] = 0x00FC8000, /* partition 0 */
[0].addrSpace[18] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
[0].sectAddr[19] = 0x00FD0000, /* partition 1 */
[0].addrSpace[19] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
[0].sectAddr[20] = 0x00FD8000, /* partition 1 */
[0].addrSpace[20] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
[0].sectAddr[21] = 0x00FE0000, /* partition 0 */
[0].addrSpace[21] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 6,
[0].sectAddr[22] = 0x00FF0000, /* partition 1 */
[0].addrSpace[22] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 8,
/* Large Flash Blocks */
[0].sectAddr[23] = 0x01000000, /* partition 6 */
[0].addrSpace[23] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 0,
[0].sectAddr[24] = 0x01040000,
[0].addrSpace[24] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 1,
[0].sectAddr[25] = 0x01080000,
[0].addrSpace[25] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 2,
[0].sectAddr[26] = 0x010C0000,
[0].addrSpace[26] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 3,
[0].sectAddr[27] = 0x01100000,
[0].addrSpace[27] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 4,
[0].sectAddr[28] = 0x01140000,
[0].addrSpace[28] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 5,
[0].sectAddr[29] = 0x01180000,
[0].addrSpace[29] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 6,
[0].sectAddr[30] = 0x011C0000,
[0].addrSpace[30] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 7,
[0].sectAddr[31] = 0x01200000, /* partition 7 */
[0].addrSpace[31] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 8,
[0].sectAddr[32] = 0x01240000,
[0].addrSpace[32] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 9,
[0].sectAddr[33] = 0x01280000,
[0].addrSpace[33] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 10,
[0].sectAddr[34] = 0x012C0000,
[0].addrSpace[34] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 11,
[0].sectAddr[35] = 0x01300000,
[0].addrSpace[35] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 12,
[0].sectAddr[36] = 0x01340000,
[0].addrSpace[36] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 13,
[0].sectAddr[37] = 0x01380000,
[0].addrSpace[37] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 14,
[0].sectAddr[38] = 0x013C0000,
[0].addrSpace[38] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 15,
[0].sectAddr[39] = 0x01400000, /* partition 8 */
[0].addrSpace[39] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 16,
[0].sectAddr[40] = 0x01440000,
[0].addrSpace[40] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 17,
[0].sectAddr[41] = 0x01480000,
[0].addrSpace[41] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 18,
[0].sectAddr[42] = 0x014C0000, /* partition 9 */
[0].addrSpace[42] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 19,
[0].sectAddr[43] = 0x01500000,
[0].addrSpace[43] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 20,
[0].sectAddr[44] = 0x01540000,
[0].addrSpace[44] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 21,
[0].sectAddr[45] = 0x01580000,
[0].addrSpace[45] = SECTOR_EMPTY,
};
#else
#error CPU NOT supported
#endif
/* @req SWS_Fls_00262 */
/* @req SWS_Fls_00263 */
/* @req SWS_Fls_00368 */
const Fls_ConfigType FlsConfigSet[] = { {
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL, .FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL, .FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16, .FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32, .FlsMaxWriteNormalMode = 32, } };
|
2301_81045437/classic-platform
|
boards/mpc5748g_mpc574xg_mb/config/Fls_Cfg.c
|
C
|
unknown
| 7,787
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @tagSettings DEFAULT_ARCHITECTURE=MPC5748G */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE 0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5748G)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLS_FLASH_WRITE_BUFFER_SIZE 128 /* Page buffer size for C55 flash*/
#define FLASH_MAX_SECTORS 45
/* THIRD PARTY EEPROM EMUL SEC CODE SEC DATA */
//#define FLS_TOTAL_SIZE (( (16*2)+(32*4)+(64*2)+(256*22) + (16*8)+(32*2) + (64*2)+ (16*1) + (16*2) )*1024)
#define FLS_TOTAL_SIZE 0x002000000
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
/* @req SWS_Fls_00355 */
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
/* @req SWS_Fls_00109 */
/* @req SWS_Fls_00110 */
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
/* !req SWS_Fls_00352 */
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5748g_mpc574xg_mb/config/Fls_Cfg.h
|
C
|
unknown
| 4,104
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z7 MPC55XX MPC57XX MPC5777C CAN_OSCILLATOR_CLOCK BRD_MPC5777C_MPC57xx_MB
CFG+=MCU_ARC_CONFIG
CFG+=MCU_CACHE_I
CFG+=EFPU
CFG+=VLE
CFG+=TIMER
CFG+=TIMER_STM
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
MOD_AVAIL+=OS ADC DIO CAN GPT MCU PWM PORT WDG FLS SPI ETH DMA
# Additional
MOD_AVAIL+= LWIP TCPIP UDPNM
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=ghs
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
efpu=$(if $(filter $(CFG),EFPU),y)
nofpu=$(if $(efpu),n,y)
diab-$(vle)$(nofpu)+=-tPPCE200Z4VFN:simple
diab-$(novle)$(nofpu)+=-tPPCE200Z4NFS:simple
#diab-$(vle)$(efpu)+=-tPPCE200Z4251N3VFF:simple
diab-$(vle)$(efpu)+=-tPPCE200Z4VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc5777mz720
# Defines
def-y += SRAM_SIZE=0x80000
def-y += L_BOOT_RESERVED_SPACE=0x0000
def-y += __BIG_ENDIAN__
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/build_config.mk
|
Makefile
|
unknown
| 1,382
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#include "Dma.h"
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_FILL_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_DRAIN_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_TDRE_TC_TXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_RDRF_RXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
};
const Dma_ConfigType DmaConfig []=
{
{DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}
};
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Dma_Cfg.c
|
C
|
unknown
| 3,999
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
typedef enum
{
DMA_ADC_GROUP0_COMMAND_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_ADC_GROUP1_COMMAND_CHANNEL,
DMA_ADC_GROUP1_RESULT_CHANNEL,
DMA_ADC_GROUP2_COMMAND_CHANNEL,
DMA_ADC_GROUP2_RESULT_CHANNEL,
DMA_ADC_GROUP3_COMMAND_CHANNEL,
DMA_ADC_GROUP3_RESULT_CHANNEL,
DMA_ADC_GROUP4_COMMAND_CHANNEL,
DMA_ADC_GROUP4_RESULT_CHANNEL,
DMA_ADC_GROUP5_COMMAND_CHANNEL,
DMA_ADC_GROUP5_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL,
DMA_DSPI_C_RESULT_CHANNEL,
DECFIL_FILL_BUF_CHANNEL,
DECFIL_DRAIN_BUF_CHANNEL,
SCI_A_TDRE_TC_TXRDY_CHANNEL,
SCI_A_RDRF_RXRDY_CHANNEL,
DMA_EMIOS_0_CHANNEL,
DMA_EMIOS_1_CHANNEL,
DMA_EMIOS_2_CHANNEL,
DMA_EMIOS_3_CHANNEL,
DMA_EMIOS_4_CHANNEL,
DMA_EMIOS_8_CHANNEL,
DMA_EMIOS_9_CHANNEL,
DMA_TPU_0_CHANNEL,
DMA_TPU_1_CHANNEL,
DMA_TPU_2_CHANNEL,
DMA_TPU_14_CHANNEL,
DMA_TPU_15_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_ADC_GROUP0_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Dma_Cfg.h
|
C
|
unknown
| 1,900
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD Spi_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 Spi_SEQ_CMD2
#define SPI_SEQ_EEP_READ Spi_SEQ_READ
#define SPI_SEQ_EEP_WRITE Spi_SEQ_WRITE
#define SPI_CH_EEP_CMD Spi_CH_CMD
#define SPI_CH_EEP_ADDR Spi_CH_ADDR
#define SPI_CH_EEP_WREN Spi_CH_WREN
#define SPI_CH_EEP_DATA Spi_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Eep_Lcfg.c
|
C
|
unknown
| 3,925
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5777C)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[] = {
/* NO RWW */
/*LOW : 64*2 = 128KB*/
/*MID : 64*2 = 128KB*/
/*HIGH : 16*2 = 32KB*/
/*LARGE : 256*32 = 8192KB*/
/* Bank 0, Array 0 (LOW) */
[0].sectCnt = 40,
[0].bankSize = 0x01000000UL,/* This is used only for address range validation
so the bank size will be 0x01000000 - 0x00000000 even though available actual size is only 0x848000 as computed above */
[0].regBase = 0xFFFE8000UL,/* C55FMC_MCR register */
/*Flash memory Low and Mid Blocks (256K)*/
/* Low*/
[0].sectAddr[0] = 0x00000000,
[0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
[0].sectAddr[1] = 0x00010000,
[0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
/*Mid*/
[0].sectAddr[2] = 0x00020000,
[0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
[0].sectAddr[3] = 0x00030000,
[0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
[0].sectAddr[4] = 0x00040000,/* end first chunk */
[0].addrSpace[4] = SECTOR_EMPTY,
/*Flash memory High Blocks (32K)*/
/*High*/
[0].sectAddr[5] = 0x00600000,
[0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
[0].sectAddr[6] = 0x00604000,
[0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
[0].sectAddr[7] = 0x00608000,/* end first chunk */
[0].addrSpace[7] = SECTOR_EMPTY,
/*Flash memory Large Blocks (8M)*/
/*Large*/
[0].sectAddr[8] = 0x00800000,
[0].addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 0,
[0].sectAddr[9] = 0x00840000,
[0].addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 1,
[0].sectAddr[10] = 0x00880000,
[0].addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 2,
[0].sectAddr[11] = 0x008C0000,
[0].addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 3,
[0].sectAddr[12] = 0x00900000,
[0].addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 4,
[0].sectAddr[13] = 0x00940000,
[0].addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 5,
[0].sectAddr[14] = 0x00980000,
[0].addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 6,
[0].sectAddr[15] = 0x009C0000,
[0].addrSpace[15] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 7,
[0].sectAddr[16] = 0x00A00000,
[0].addrSpace[16] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 8,
[0].sectAddr[17] = 0x00A40000,
[0].addrSpace[17] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 9,
[0].sectAddr[18] = 0x00A80000,
[0].addrSpace[18] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 10,
[0].sectAddr[19] = 0x00AC0000,
[0].addrSpace[19] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 11,
[0].sectAddr[20] = 0x00B00000,
[0].addrSpace[20] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 12,
[0].sectAddr[21] = 0x00B40000,
[0].addrSpace[21] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 13,
[0].sectAddr[22] = 0x00B80000,
[0].addrSpace[22] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 14,
[0].sectAddr[23] = 0x00BC0000,
[0].addrSpace[23] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 15,
[0].sectAddr[24] = 0x00C00000,
[0].addrSpace[24] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 16,
[0].sectAddr[25] = 0x00C40000,
[0].addrSpace[25] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 17,
[0].sectAddr[26] = 0x00C80000,
[0].addrSpace[26] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 18,
[0].sectAddr[27] = 0x00CC0000,
[0].addrSpace[27] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 19,
[0].sectAddr[28] = 0x00D00000,
[0].addrSpace[28] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 20,
[0].sectAddr[29] = 0x00D40000,
[0].addrSpace[29] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 21,
[0].sectAddr[30] = 0x00D80000,
[0].addrSpace[30] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 22,
[0].sectAddr[31] = 0x00DC0000,
[0].addrSpace[31] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 23,
[0].sectAddr[32] = 0x00E00000,
[0].addrSpace[32] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 24,
[0].sectAddr[33] = 0x00E40000,
[0].addrSpace[33] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 25,
[0].sectAddr[34] = 0x00E80000,
[0].addrSpace[34] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 26,
[0].sectAddr[35] = 0x00EC0000,
[0].addrSpace[35] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 27,
[0].sectAddr[36] = 0x00F00000,
[0].addrSpace[36] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 28,
[0].sectAddr[37] = 0x00F40000,
[0].addrSpace[37] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 29,
[0].sectAddr[38] = 0x00F80000,
[0].addrSpace[38] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 30,
[0].sectAddr[39] = 0x00FC0000,
[0].addrSpace[39] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 31,
[0].sectAddr[40] = 0x01000000,
[0].addrSpace[40] = SECTOR_EMPTY,
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[] = { {
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL, .FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL, .FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16, .FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32, .FlsMaxWriteNormalMode = 32,
} };
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Fls_Cfg.c
|
C
|
unknown
| 6,214
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5777C)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLS_FLASH_WRITE_BUFFER_SIZE 256 /* Page buffer size for C55 flash*/
#define FLASH_MAX_SECTORS 40
#define FLS_TOTAL_SIZE 0x01000000 /*last sector address*//* This is used to indicate total size including the reserved areas */
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Fls_Cfg.h
|
C
|
unknown
| 3,802
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Wdg_Cfg.h
|
C
|
unknown
| 1,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x280, // 5 ms
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 0xA00, // 20 ms
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5777c_mpc57xx_mb/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,264
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z4 MPC55XX MPC57XX MPC5777M CAN_OSCILLATOR_CLOCK BRD_MPC5777M_MMB
CFG+=EFPU
CFG+=MCU_ARC_CONFIG
CFG+=MCU_CACHE_I
CFG+=OS_SYSTICK2
CFG+=VLE
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
MOD_AVAIL+=OS ADC DIO DMA CAN GPT LIN MCU PORT WDG FLS SPI ETH
# Additional
MOD_AVAIL+= LWIP TCPIP SOAD DOIP UDPNM ETHSM
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=ghs
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
efpu=$(if $(filter $(CFG),EFPU),y)
nofpu=$(if $(efpu),n,y)
diab-$(vle)$(nofpu)+=-tPPCE200Z4VFN:simple
diab-$(novle)$(nofpu)+=-tPPCE200Z4NFS:simple
#diab-$(vle)$(efpu)+=-tPPCE200Z4251N3VFF:simple
diab-$(vle)$(efpu)+=-tPPCE200Z4VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc5777mz425
# Defines
def-y += SRAM_SIZE=0x60000
def-y += NON_ASR_ETH_DRIVER
def-y += USE_NO_ETHIF
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/build_config.mk
|
Makefile
|
unknown
| 1,372
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SPI_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SPI_SEQ_CMD2
#define SPI_SEQ_EEP_READ SPI_SEQ_READ
#define SPI_SEQ_EEP_WRITE SPI_SEQ_WRITE
#define SPI_CH_EEP_CMD SPI_CH_CMD
#define SPI_CH_EEP_ADDR SPI_CH_ADDR
#define SPI_CH_EEP_WREN SPI_CH_WREN
#define SPI_CH_EEP_DATA SPI_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/config/Eep_Lcfg.c
|
C
|
unknown
| 3,925
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5777M)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[] = {
/* NO RWW */
/* Bank 0, Array 0 (LOW) */
[0].sectCnt = 54,
[0].bankSize = 0x1174000,
[0].regBase = 0xFFFE0000UL,
// HSM Code—no overlay
[0].sectAddr[0] = 0x0060C000,
[0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
[0].sectAddr[1] = 0x00610000,
[0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
[0].sectAddr[2] = 0x00620000,
[0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 3,
[0].sectAddr[3] = 0x00630000, /* end first chunk */
[0].addrSpace[3] = SECTOR_EMPTY,
// HSM Data—no overlay
[0].sectAddr[4] = 0x00680000, /* 0x800000, B0F0, LOW */
[0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
[0].sectAddr[5] = 0x00684000,
[0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
[0].sectAddr[6] = 0x00688000, /* end first chunk */
[0].addrSpace[6] = SECTOR_EMPTY,
// Data Flash–no overlay
[0].sectAddr[7] = 0x800000,
[0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
[0].sectAddr[8] = 0x810000,
[0].addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
[0].sectAddr[9] = 0x820000,
[0].addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
[0].sectAddr[10] = 0x830000,
[0].addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
[0].sectAddr[11] = 0x840000,
[0].addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
[0].sectAddr[12] = 0x850000,
[0].addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
[0].sectAddr[13] = 0x860000,
[0].addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 6,
[0].sectAddr[14] = 0x870000,
[0].addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 7,
[0].sectAddr[15] = 0x880000, /* end first chunk */
[0].addrSpace[15] = SECTOR_EMPTY,
// Low & Mid & Large Flash Blocks—no overlay
[0].sectAddr[16] = 0x00FC0000,
[0].addrSpace[16] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
[0].sectAddr[17] = 0x00FC4000,
[0].addrSpace[17] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
[0].sectAddr[18] = 0x00FC8000,
[0].addrSpace[18] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
[0].sectAddr[19] = 0x00FCC000,
[0].addrSpace[19] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
[0].sectAddr[20] = 0x00FD0000,
[0].addrSpace[20] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
[0].sectAddr[21] = 0x00FD8000,
[0].addrSpace[21] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
[0].sectAddr[22] = 0x00FE0000,
[0].addrSpace[22] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
[0].sectAddr[23] = 0x0FF0000,
[0].addrSpace[23] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
[0].sectAddr[24] = 0x1000000,
[0].addrSpace[24] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 0,
[0].sectAddr[25] = 0x1040000,
[0].addrSpace[25] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 1,
[0].sectAddr[26] = 0x1080000,
[0].addrSpace[26] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 2,
[0].sectAddr[27] = 0x10C0000,
[0].addrSpace[27] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 3,
[0].sectAddr[28] = 0x1100000,
[0].addrSpace[28] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 4,
[0].sectAddr[29] = 0x1140000,
[0].addrSpace[29] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 5,
[0].sectAddr[30] = 0x1180000,
[0].addrSpace[30] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 6,
[0].sectAddr[31] = 0x11C0000,
[0].addrSpace[31] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 7,
[0].sectAddr[32] = 0x1200000,
[0].addrSpace[32] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 8,
[0].sectAddr[33] = 0x1240000,
[0].addrSpace[33] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 9,
[0].sectAddr[34] = 0x1280000,
[0].addrSpace[34] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 10,
[0].sectAddr[35] = 0x12C0000,
[0].addrSpace[35] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 11,
[0].sectAddr[36] = 0x1300000,
[0].addrSpace[36] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 12,
[0].sectAddr[37] = 0x1340000,
[0].addrSpace[37] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 13,
[0].sectAddr[38] = 0x1380000,
[0].addrSpace[38] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 14,
[0].sectAddr[39] = 0x13C0000,
[0].addrSpace[39] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 15,
[0].sectAddr[40] = 0x1400000,
[0].addrSpace[40] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 16,
[0].sectAddr[41] = 0x1440000,
[0].addrSpace[41] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 17,
[0].sectAddr[42] = 0x1480000,
[0].addrSpace[42] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 18,
[0].sectAddr[43] = 0x14C0000,
[0].addrSpace[43] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 19,
[0].sectAddr[44] = 0x1500000,
[0].addrSpace[44] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 20,
[0].sectAddr[45] = 0x1540000,
[0].addrSpace[45] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 21,
[0].sectAddr[46] = 0x1580000,
[0].addrSpace[46] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 22,
[0].sectAddr[47] = 0x15C0000,
[0].addrSpace[47] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 23,
[0].sectAddr[48] = 0x1600000,
[0].addrSpace[48] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 24,
[0].sectAddr[49] = 0x1640000,
[0].addrSpace[49] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 25,
[0].sectAddr[50] = 0x1680000,
[0].addrSpace[50] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 26,
[0].sectAddr[51] = 0x16C0000,
[0].addrSpace[51] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 27,
[0].sectAddr[52] = 0x1700000,
[0].addrSpace[52] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 28,
[0].sectAddr[53] = 0x1740000,
[0].addrSpace[53] = ADDR_SPACE_SET(ADDR_SPACE_LARGE) + 29,
[0].sectAddr[54] = 0x1780000,
[0].addrSpace[54] = SECTOR_EMPTY,
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[] = { {
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL, .FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL, .FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16, .FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32, .FlsMaxWriteNormalMode = 32,
} };
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/config/Fls_Cfg.c
|
C
|
unknown
| 7,126
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5777M)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLS_FLASH_WRITE_BUFFER_SIZE 128 /* Page buffer size for C55 flash*/
#define FLASH_MAX_SECTORS 56
#define FLS_TOTAL_SIZE 0x09780000
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/config/Fls_Cfg.h
|
C
|
unknown
| 3,706
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/config/Wdg_Cfg.h
|
C
|
unknown
| 1,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x280, // 5 ms
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 0xA00, // 20 ms
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5777m_mmb/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,264
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef _OS_H_
#define _OS_H_
#define OS_AR_RELEASE_MAJOR_VERSION 4u
#define OS_AR_RELEASE_MINOR_VERSION 0u
#define OS_AR_RELEASE_REVISION_VERSION 3u
/* @req SWS_BSW_00059 Published information */
#define OS_SW_MAJOR_VERSION 1u
#define OS_SW_MINOR_VERSION 0u
#define OS_SW_PATCH_VERSION 1u
#include "Std_Types.h"
#include "MemMap.h"
#include "Os_Cfg.h"
//#define OSTICKDURATION 1000000UL
#define E_OS_EXIT_ABORT (StatusType)30 /* ArcCore */
#define E_OS_ASSERT (StatusType)37 /* ArcCore, call to ASSERT() or CONFIG_ASSERT() */
typedef uint32 ApplicationType;
typedef uint32 CounterType;
typedef uint8 StatusType;
typedef sint16 ISRType;
typedef uint32 AreaIdType;
typedef uint32 *TickRefType;
typedef uint32 TickType;
typedef uint64 EventMaskType;
typedef uint16 TaskType;
typedef sint8 Os_IntCounterType;
StatusType GetElapsedValue( CounterType CounterID, TickRefType Value, TickRefType ElapsedValue );
extern uint16 EA_count;
static inline void SuspendOSInterrupts( void ) {
/* EA_count is incremented to get the count of number of times OS interrupts are suspended*/
EA_count++;
}
static inline void ResumeOSInterrupts( void ) {
/* EA_count is decremented to get the count of number of times OS interrupts are resumed*/
EA_count--;
}
void ShutdownOS( StatusType );
#define SYS_CALL_EnterUserMode()
#define SYS_CALL_EnterSupervisorMode()
#define SYS_CALL_ResumeAllInterrupts() ResumeAllInterrupts()
#define SYS_CALL_SuspendAllInterrupts() SuspendAllInterrupts()
#define SYS_CALL_EnableAllInterrupts() EnableAllInterrupts()
#define SYS_CALL_DisableAllInterrupts() DisableAllInterrupts()
#define SYS_CALL_ResumeOSInterrupts() ResumeOSInterrupts()
#define SYS_CALL_SuspendOSInterrupts() SuspendOSInterrupts()
#define SYS_CALL_ActivateTask ActivateTask
#define SYS_CALL_TerminateTask TerminateTask
#define SYS_CALL_ChainTask ChainTask
#define SYS_CALL_Schedule Schedule
#define SYS_CALL_GetTaskID GetTaskID
#define SYS_CALL_GetResource GetResource
#define SYS_CALL_ReleaseResource ReleaseResource
#define SYS_CALL_SetEvent SetEvent
#define SYS_CALL_ClearEvent ClearEvent
#define SYS_CALL_GetEvent GetEvent
#define SYS_CALL_WaitEvent WaitEvent
#define SYS_CALL_GetAlarmBase GetAlarmBase
#define SYS_CALL_GetAlarm GetAlarm
#define SYS_CALL_SetRelAlarm SetRelAlarm
#define SYS_CALL_SetAbsAlarm SetAbsAlarm
#define SYS_CALL_CancelAlarm CancelAlarm
#define SYS_CALL_ShutdownOS ShutdownOS
#define SYS_CALL_GetTaskState GetTaskState
#define SYS_CALL_GetISRID GetISRID
#define SYS_CALL_CheckISRMemoryAccess CheckISRMemoryAccess
#define SYS_CALL_CheckTaskMemoryAccess CheckTaskMemoryAccess
#define SYS_CALL_CheckObjectOwnership CheckObjectOwnership
#define SYS_CALL_StartScheduleTableRel StartScheduleTableRel
#define SYS_CALL_StartScheduleTableAbs StartScheduleTableAbs
#define SYS_CALL_StopScheduleTable StopScheduleTable
#define SYS_CALL_NextScheduleTable NextScheduleTable
#define SYS_CALL_GetScheduleTableStatus GetScheduleTableStatus
#define SYS_CALL_IncrementCounter IncrementCounter
#define SYS_CALL_GetCounterValue GetCounterValue
#define SYS_CALL_GetElapsedValue GetElapsedValue
#define ISR(_isr) void _isr( void )
StatusType SetEvent( TaskType TaskID, EventMaskType Mask );
#define SYS_CALL_AtomicCopy16(to, from) (to) = (from)
static inline StatusType WritePeripheral32( AreaIdType Area, uint32 *Address, uint32 WriteValue) {
*Address = WriteValue;
return E_OK;
}
#endif /* _OS_H_ */
|
2301_81045437/classic-platform
|
boards/no_os/Os.h
|
C
|
unknown
| 4,832
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This GNULinux header file probably needs to be further developed and nurtured!"
#ifndef DCM_CFG_H_
#define DCM_CFG_H_
/*
* DCM General
*/
#define DCM_VERSION_INFO_API STD_ON // Activate/Deactivate ver info API.
#define DCM_DEV_ERROR_DETECT STD_ON // Activate/Deactivate Dev Error Detection and Notification.
#define DCM_REQUEST_INDICATION_ENABLED STD_ON // Activate/Deactivate indication request mechanism.
#define DCM_RESPOND_ALL_REQUEST STD_ON // Activate/Deactivate response on SID 0x40-0x7f and 0xc0-0xff.
#define DCM_TASK_TIME TBD // Time for periodic task (in ms).
#define DCM_PAGEDBUFFER_ENABLED STD_OFF // Enable/disable page buffer mechanism (currently only disabled supported)
#endif /*DCM_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/no_os/config/Dcm_Cfg.h
|
C
|
unknown
| 1,531
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#ifndef ECUM_CFG_H_
#define ECUM_CFG_H_
#define ECUM_VERSION_INFO_API STD_OFF
#define ECUM_DEV_ERROR_DETECT STD_OFF
#include "../../no_os/config/EcuM_Generated_Types.h"
#define ECUM_MAIN_FUNCTION_PERIOD (200)
#define ECUM_NVRAM_READALL_TIMEOUT (10000)
#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)
#define ECUM_NVRAM_MIN_RUN_DURATION (10000)
typedef enum {
ECUM_USER_User_1,
ECUM_USER_ENDMARK // Must be the last in list!
} EcuM_UserList;
extern EcuM_ConfigType EcuMConfig;
#endif /*ECUM_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/no_os/config/EcuM_Cfg.h
|
C
|
unknown
| 1,353
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 3)) )
#error EcuM: Configuration file expected BSW module version to be 2.3.\*
#endif
#ifndef _ECUM_GENERATED_TYPES_H_
#define _ECUM_GENERATED_TYPES_H_
#include "PreCompiledDataHash.h"
/* @req SWS_EcuM_02992 */ /* @req SWS_EcuM_02992 */
#include "EcuM_Types.h"
#if defined(USE_MCU)
#include "Mcu.h"
#endif
#if defined(USE_PORT)
#include "Port.h"
#endif
#if defined(USE_CAN)
#include "Can.h"
#endif
#if defined(USE_DIO)
#include "Dio.h"
#endif
#if defined(USE_LIN)
#include "Lin.h"
#endif
#if defined(USE_CANIF)
#include "CanIf.h"
#endif
#if defined(USE_LINIF)
#include "LinIf.h"
#endif
#if defined(USE_PWM)
#include "Pwm.h"
#endif
#if defined (USE_OCU)
#include "Ocu.h"
#endif
#if defined (USE_ICU)
#include "Icu.h"
#endif
#if defined(USE_COM)
#include "Com.h"
#endif
#if defined(USE_PDUR)
#include "PduR.h"
#endif
#if defined(USE_DMA)
#include "Dma.h"
#endif
#if defined(USE_ADC)
#include "Adc.h"
#endif
#if defined(USE_GPT)
#include "Gpt.h"
#endif
#if defined(USE_COMM)
#include "ComM.h"
#endif
#if defined(USE_NM)
#include "Nm.h"
#endif
#if defined(USE_CANNM)
#include "CanNm.h"
#endif
#if defined(USE_CANSM)
#include "CanSM.h"
#endif
#if defined(USE_LINSM)
#include "LinSM.h"
#endif
#if defined(USE_J1939TP)
#include "J1939Tp.h"
#endif
#if defined(USE_UDPNM)
#include "UdpNm.h"
#endif
#if defined(USE_FLS)
#include "Fls.h"
#endif
#if defined(USE_EEP)
#include "Eep.h"
#endif
#if defined(USE_SPI)
#include "Spi.h"
#endif
#if defined(USE_WDG)
#include "Wdg.h"
#endif
#if defined(USE_WDGM)
#include "WdgM.h"
#endif
#if defined(USE_WDGIF)
#include "WdgIf.h"
#endif
#if defined(USE_ETH)
#include "Eth.h"
#endif
#if defined(USE_FR)
#include "Fr.h"
#endif
#if defined(USE_BSWM)
#include "BswM.h"
#endif
#if defined(USE_PDUR) || defined(USE_COM) || defined(USE_CANIF) || defined(USE_CANTP) || defined(USE_FRTP)
#include "EcuM_PBTypes.h"
#endif
#if defined(USE_DCM)
#include "Dcm.h"
#endif
#if defined(USE_DEM)
#include "Dem.h"
#endif
#if defined(USE_XCP)
#include "Xcp.h"
#endif
#if defined(USE_IPDUM)
#include "IpduM.h"
#endif
#if defined(USE_DLT)
#include "Dlt.h"
#endif
#if defined(USE_FR)
#include "Fr.h"
#endif
#if defined(USE_FRIF)
#include "FrIf.h"
#endif
#if defined(USE_FRNM)
#include "FrNm.h"
#endif
#if defined(USE_FRSM)
#include "FrSM.h"
#endif
#if defined(USE_FRTP)
#include "FrTp.h"
#endif
typedef struct EcuM_ConfigS
{
uint32 EcuMPostBuildVariant; /* @req SWS_EcuM_02794 */ /* @req SWS_EcuM_02794 */
uint64 EcuMConfigConsistencyHashLow; /* @req SWS_EcuM_02795 Hash set when compiling the whole software for the */ /* @req SWS_EcuM_02795 */
uint64 EcuMConfigConsistencyHashHigh; /* PB module. It is compared to the PB hash at startup. */
EcuM_StateType EcuMDefaultShutdownTarget;
uint8 EcuMDefaultSleepMode;
AppModeType EcuMDefaultAppMode;
uint32 EcuMRunMinimumDuration;
uint32 EcuMNvramReadAllTimeout;
uint32 EcuMNvramWriteAllTimeout;
Mcu_ModeType EcuMNormalMcuMode;
#if defined(USE_DEM)
Dem_EventIdType EcuMDemInconsistencyEventId;
Dem_EventIdType EcuMDemRamCheckFailedEventId;
Dem_EventIdType EcuMDemAllRunRequestsKilledEventId;
#endif
const EcuM_SleepModeType *EcuMSleepModeConfig;
const EcuM_WakeupSourceConfigType *EcuMWakeupSourceConfig;
#if defined(USE_ECUM_FLEXIBLE)
const EcuM_UserType *EcuMGoDownAllowedUsersConfig;
#endif
#if defined (USE_COMM)
const EcuM_ComMConfigType *EcuMComMConfig;
#endif
#if defined(USE_MCU)
const Mcu_ConfigType* McuConfigPtr;
#endif
#if defined(USE_PORT)
const Port_ConfigType* PortConfigPtr;
#endif
#if defined(USE_CAN)
const Can_ConfigType* CanConfigPtr;
#endif
#if defined(USE_DIO)
const Dio_ConfigType* DioConfigPtr;
#endif
#if defined(USE_CANSM)
const CanSM_ConfigType* CanSMConfigPtr;
#endif
#if defined(USE_LIN)
const Lin_ConfigType* LinConfigPtr;
#endif
#if defined(USE_LINIF)
const LinIf_ConfigType* LinIfConfigPtr;
#endif
#if defined(USE_LINSM)
const LinSM_ConfigType* LinSMConfigPtr;
#endif
#if defined(USE_ETH)
const Eth_ConfigType* EthConfigPtr;
#endif
#if defined(USE_NM)
const Nm_ConfigType* NmConfigPtr;
#endif
#if defined(USE_UDPNM)
const UdpNm_ConfigType* UdpNmConfigPtr;
#endif
#if defined(USE_COMM)
const ComM_ConfigType* ComMConfigPtr;
#endif
#if defined(USE_BSWM)
const BswM_ConfigType* BswMConfigPtr;
#endif
#if defined(USE_J1939TP)
const J1939Tp_ConfigType* J1939TpConfigPtr;
#endif
#if defined(USE_PWM)
const Pwm_ConfigType* PwmConfigPtr;
#endif
#if defined(USE_OCU)
const Ocu_ConfigType* OcuConfigPtr;
#endif
#if defined(USE_ICU)
const Icu_ConfigType* IcuConfigPtr;
#endif
#if defined(USE_DMA)
const Dma_ConfigType* DmaConfigPtr;
#endif
#if defined(USE_ADC)
const Adc_ConfigType* AdcConfigPtr;
#endif
#if defined(USE_GPT)
const Gpt_ConfigType* GptConfigPtr;
#endif
#if defined(USE_FLS)
const Fls_ConfigType* FlsConfigPtr;
#endif
#if defined(USE_EEP)
const Eep_ConfigType* EepConfigPtr;
#endif
#if defined(USE_SPI)
const Spi_ConfigType* SpiConfigPtr;
#endif
#if defined(USE_WDG)
const Wdg_ConfigType* WdgConfigPtr;
#endif
#if defined(USE_WDGIF)
const WdgIf_ConfigType* WdgIfConfigPtr;
#endif
#if defined(USE_WDGM)
const WdgM_ConfigType* WdgMConfigPtr;
#endif
#if defined(USE_DCM)
const Dcm_ConfigType* DcmConfigPtr;
#endif
#if defined(USE_DEM)
const Dem_ConfigType* DemConfigPtr;
#endif
#if defined(USE_XCP)
const Xcp_ConfigType* XcpConfigPtr;
#endif
#if defined(USE_IPDUM)
const IpduM_ConfigType* IpduMConfigPtr;
#endif
#if defined(USE_PDUR) || defined(USE_COM) || defined(USE_CANIF) || defined(USE_CANTP) || defined(USE_CANNM)
const PostbuildConfigType* PostBuildConfig;
#endif
#if defined(USE_DLT)
const Dlt_ConfigType* DltConfigPtr;
#endif
#if defined(USE_FR)
const Fr_ConfigType * FrConfigPtr;
#endif
#if defined(USE_FRIF)
const FrIf_ConfigType * FrIfConfigPtr;
#endif
#if defined(USE_FRNM)
const FrNm_ConfigType * FrNmConfigPtr;
#endif
#if defined(USE_FRSM)
const FrSM_ConfigType * FrSMConfigPtr;
#endif
#if defined(USE_FRTP)
const FrTp_ConfigType * FrTpConfigPtr;
#endif
} EcuM_ConfigType;
#endif /*_ECUM_GENERATED_TYPES_H_*/
|
2301_81045437/classic-platform
|
boards/no_os/config/EcuM_Generated_Types.h
|
C
|
unknown
| 7,276
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#if defined(USE_FEE)
#include "Fee.h"
#endif
const FlashType flashInfo[] =
{
{
.FlsBaseAddress= 0x00000000U,
.FlsTotalSize = 0x01000000U,
.sectCnt = 256U,
.bankSize = 0x01000000U, //128 MB
.regBase = 0xE000D000U,
.sectAddr =
{
0x00000000U,
0x00010000U,
0x00020000U,
0x00030000U,
0x00040000U,
0x00050000U,
0x00060000U,
0x00070000U,
0x00080000U,
0x00090000U,
0x000A0000U,
0x000B0000U,
0x000C0000U,
0x000D0000U,
0x000E0000U,
0x000F0000U,
0x00100000U,
0x00110000U,
0x00120000U,
0x00130000U,
0x00140000U,
0x00150000U,
0x00160000U,
0x00170000U,
0x00180000U,
0x00190000U,
0x001A0000U,
0x001B0000U,
0x001C0000U,
0x001D0000U,
0x001E0000U,
0x001F0000U,
0x00200000U,
0x00210000U,
0x00220000U,
0x00230000U,
0x00240000U,
0x00250000U,
0x00260000U,
0x00270000U,
0x00280000U,
0x00290000U,
0x002A0000U,
0x002B0000U,
0x002C0000U,
0x002D0000U,
0x002E0000U,
0x002F0000U,
0x00300000U,
0x00310000U,
0x00320000U,
0x00330000U,
0x00340000U,
0x00350000U,
0x00360000U,
0x00370000U,
0x00380000U,
0x00390000U,
0x003A0000U,
0x003B0000U,
0x003C0000U,
0x003D0000U,
0x003E0000U,
0x003F0000U,
0x00400000U,
0x00410000U,
0x00420000U,
0x00430000U,
0x00440000U,
0x00450000U,
0x00460000U,
0x00470000U,
0x00480000U,
0x00490000U,
0x004A0000U,
0x004B0000U,
0x004C0000U,
0x004D0000U,
0x004E0000U,
0x004F0000U,
0x00500000U,
0x00510000U,
0x00520000U,
0x00530000U,
0x00540000U,
0x00550000U,
0x00560000U,
0x00570000U,
0x00580000U,
0x00590000U,
0x005A0000U,
0x005B0000U,
0x005C0000U,
0x005D0000U,
0x005E0000U,
0x005F0000U,
0x00600000U,
0x00610000U,
0x00620000U,
0x00630000U,
0x00640000U,
0x00650000U,
0x00660000U,
0x00670000U,
0x00680000U,
0x00690000U,
0x006A0000U,
0x006B0000U,
0x006C0000U,
0x006D0000U,
0x006E0000U,
0x006F0000U,
0x00700000U,
0x00710000U,
0x00720000U,
0x00730000U,
0x00740000U,
0x00750000U,
0x00760000U,
0x00770000U,
0x00780000U,
0x00790000U,
0x007A0000U,
0x007B0000U,
0x007C0000U,
0x007D0000U,
0x007E0000U,
0x007F0000U,
0x00800000U,
0x00810000U,
0x00820000U,
0x00830000U,
0x00840000U,
0x00850000U,
0x00860000U,
0x00870000U,
0x00880000U,
0x00890000U,
0x008A0000U,
0x008B0000U,
0x008C0000U,
0x008D0000U,
0x008E0000U,
0x008F0000U,
0x00900000U,
0x00910000U,
0x00920000U,
0x00930000U,
0x00940000U,
0x00950000U,
0x00960000U,
0x00970000U,
0x00980000U,
0x00990000U,
0x009A0000U,
0x009B0000U,
0x009C0000U,
0x009D0000U,
0x009E0000U,
0x009F0000U,
0x00A00000U,
0x00A10000U,
0x00A20000U,
0x00A30000U,
0x00A40000U,
0x00A50000U,
0x00A60000U,
0x00A70000U,
0x00A80000U,
0x00A90000U,
0x00AA0000U,
0x00AB0000U,
0x00AC0000U,
0x00AD0000U,
0x00AE0000U,
0x00AF0000U,
0x00B00000U,
0x00B10000U,
0x00B20000U,
0x00B30000U,
0x00B40000U,
0x00B50000U,
0x00B60000U,
0x00B70000U,
0x00B80000U,
0x00B90000U,
0x00BA0000U,
0x00BB0000U,
0x00BC0000U,
0x00BD0000U,
0x00BE0000U,
0x00BF0000U,
0x00C00000U,
0x00C10000U,
0x00C20000U,
0x00C30000U,
0x00C40000U,
0x00C50000U,
0x00C60000U,
0x00C70000U,
0x00C80000U,
0x00C90000U,
0x00CA0000U,
0x00CB0000U,
0x00CC0000U,
0x00CD0000U,
0x00CE0000U,
0x00CF0000U,
0x00D00000U,
0x00D10000U,
0x00D20000U,
0x00D30000U,
0x00D40000U,
0x00D50000U,
0x00D60000U,
0x00D70000U,
0x00D80000U,
0x00D90000U,
0x00DA0000U,
0x00DB0000U,
0x00DC0000U,
0x00DD0000U,
0x00DE0000U,
0x00DF0000U,
0x00E00000U,
0x00E10000U,
0x00E20000U,
0x00E30000U,
0x00E40000U,
0x00E50000U,
0x00E60000U,
0x00E70000U,
0x00E80000U,
0x00E90000U,
0x00EA0000U,
0x00EB0000U,
0x00EC0000U,
0x00ED0000U,
0x00EE0000U,
0x00EF0000U,
0x00F00000U,
0x00F10000U,
0x00F20000U,
0x00F30000U,
0x00F40000U,
0x00F50000U,
0x00F60000U,
0x00F70000U,
0x00F80000U,
0x00F90000U,
0x00FA0000U,
0x00FB0000U,
0x00FC0000U,
0x00FD0000U,
0x00FE0000U,
0x00FF0000U,
}
}
};
const Fls_ConfigType FlsConfigSet[] =
{
{
#if (USE_FLS_INFO==STD_ON)
.FlsInfo = flashInfo ,
#endif
.FlsAcErase = 0u,
.FlsAcWrite = 0u,
.FlsMaxReadFastMode = 0x100u,
.FlsMaxReadNormalMode = 0x100u,
.FlsMaxWriteFastMode = 0x100u,
.FlsMaxWriteNormalMode = 0x100u,
#if (FEE_POLLING_MODE == STD_OFF)
.FlsJobEndNotification = Fee_JobEndNotification,
.FlsJobErrorNotification= Fee_JobErrorNotification,
#else
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification= NULL,
#endif
.FlsProtection = 0u,
}
};
|
2301_81045437/classic-platform
|
boards/no_os/config/Fls_Cfg.c
|
C
|
unknown
| 8,412
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
/** @tagSettings DEFAULT_ARCHITECTURE=ZYNQ */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Fls Driver.
*/
#if !(((FLS_SW_MAJOR_VERSION == 2) && (FLS_SW_MINOR_VERSION == 0)) )
#error Fls: Configuration file expected BSW module version to be 2.0.*
#endif
#if !(((FLS_AR_RELEASE_MAJOR_VERSION == 4) && (FLS_AR_RELEASE_MINOR_VERSION == 1)) )
#error Fls: Configuration file expected AUTOSAR version to be 4.1.*
#endif
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
/** @req SWS_Fls_00308 */
#include "MemIf_Types.h"
#if defined(USE_FEE)
/** @req SWS_Fls_00262 */
/** @req SWS_Fls_00263 */
#include "Fee_Cbk.h"
#endif
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
#define FLASH_SECTOR_SIZE 0x10000u
#define FLASH_NUM_SECTORS 0x100u
#define FLASH_MAX_SECTORS (FLASH_NUM_SECTORS - 1)
#define FLASH_NUM_PAGES 0x10000u
#define FLASH_PAGE_SIZE 0x8u
#define FLS_TOTAL_SIZE (FLASH_NUM_PAGES * FLASH_PAGE_SIZE)
typedef struct {
/** @req SWS_Fls_00109 */
/** @req SWS_Fls_00110 */
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
#if (USE_FLS_INFO==STD_ON)
/** @req SWS_Fls_00355 */
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
uint32 FlsAcErase; /* NO SUPPORT */
uint32 FlsAcWrite; /* NO SUPPORT */
// FlsCallCycle N/A in core.
uint32 FlsMaxReadFastMode; /* NO SUPPORT */
uint32 FlsMaxReadNormalMode; /* NO SUPPORT */
uint32 FlsMaxWriteFastMode; /* NO SUPPORT */
uint32 FlsMaxWriteNormalMode; /* NO SUPPORT */
uint32 FlsProtection; /* NO SUPPORT */
} Fls_ConfigSetType;
/** @req SWS_Fls_00368 */
/** @req SWS_Fls_00353 */
/** @req SWS_Fls_00354 */
typedef Fls_ConfigSetType Fls_ConfigType;
typedef struct Flash {
uint32 FlsBaseAddress;
uint32 FlsTotalSize;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_NUM_SECTORS];
} FlashType;
extern const Fls_ConfigType FlsConfigSet[1];
#endif /*FLS_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/no_os/config/Fls_Cfg.h
|
C
|
unknown
| 4,167
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
typedef enum
{
IWDG_CK_Counter_Clock_4 = 0,
IWDG_CK_Counter_Clock_8,
IWDG_CK_Counter_Clock_16,
IWDG_CK_Counter_Clock_32,
IWDG_CK_Counter_Clock_64,
IWDG_CK_Counter_Clock_128,
IWDG_CK_Counter_Clock_256,
}Wdg_IWDG_TimerBaseType;
typedef struct
{
Wdg_IWDG_TimerBaseType TimerBase;
uint16 ReloadValue;
uint8 ActivationBit;
}Wdg_IWDG_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_IWDG_SettingsType WdgSettingsFast;
Wdg_IWDG_SettingsType WdgSettingsSlow;
Wdg_IWDG_SettingsType WdgSettingsOff;
}Wdg_IWDG_ModeConfigType;
typedef struct
{
const Wdg_GeneralType *Wdg_General;
const Wdg_IWDG_ModeConfigType *Wdg_IWDGModeConfig;
}Wdg_IWDG_ConfigType;
extern const Wdg_GeneralType WdgIWDGGeneral;
extern const Wdg_IWDG_ConfigType WdgIWDGConfig;
typedef enum
{
WDG_CK_Counter_Clock_1 = 0,
WDG_CK_Counter_Clock_2,
WDG_CK_Counter_Clock_4,
WDG_CK_Counter_Clock_8,
}Wdg_WWDG_TimerBaseType;
typedef struct
{
Wdg_WWDG_TimerBaseType TimerBase;
uint8 WindowValue;
uint8 CounterPreset;
uint8 ActivationBit;
}Wdg_WWDG_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_WWDG_SettingsType WdgSettingsFast;
Wdg_WWDG_SettingsType WdgSettingsSlow;
Wdg_WWDG_SettingsType WdgSettingsOff;
}Wdg_WWDG_ModeConfigType;
typedef struct
{
const Wdg_GeneralType *Wdg_General;
const Wdg_WWDG_ModeConfigType *Wdg_WWDGModeConfig;
}Wdg_WWDG_ConfigType;
typedef struct
{
const Wdg_IWDG_ConfigType *Wdg_IWDG_Config;
const Wdg_WWDG_ConfigType *Wdg_WWDG_Config;
}Wdg_ConfigType;
extern const Wdg_GeneralType WdgWWDGGeneral;
extern const Wdg_WWDG_ConfigType WdgWWDGConfig;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/no_os/config/Wdg_Cfg.h
|
C
|
unknown
| 2,697
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_IWDG_ModeConfigType WdgIWDGModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.TimerBase = IWDG_CK_Counter_Clock_8,
.ReloadValue = 0x7FF,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.TimerBase = IWDG_CK_Counter_Clock_256,
.ReloadValue = 0xFFF,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.TimerBase = IWDG_CK_Counter_Clock_4,
.ReloadValue = 0x7F,
.ActivationBit = 0,
},
};
const Wdg_GeneralType WdgIWDGGeneral =
{
.Wdg_Index = 1,
.Wdg_TriggerLocationPtr = Wdg_IWDG_Trigger,
.Wdg_SetModeLocationPtr = Wdg_IWDG_SetMode,
};
const Wdg_IWDG_ConfigType WdgIWDGConfig =
{
.Wdg_General = &WdgIWDGGeneral,
.Wdg_IWDGModeConfig = &WdgIWDGModeConfig,
};
/* The windowed watchdog is clocked from PCLK1. Max allowed frequency
* of this is 36Mhz.
*
* Max Twwdg = T_PCLK1 * 4096 * 2^TimerBase * (CounterPreset & 0x3F) + 1)=
*
* = 58.25 ms
*
*
*
* Min Twwdg = T_PCLK1 * 4096 * 2^TimerBase * (CounterPreset & 0x3F) + 1)=
*
* = 7.28 ms
* */
/* IMPROVEMENT: Add implementation for Independent WD as well. This will make it
* possible to test a multiple WD design within the STM32. */
const Wdg_WWDG_ModeConfigType WdgWWDGModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.TimerBase = WDG_CK_Counter_Clock_4,
.WindowValue = 0x7F,
.CounterPreset = 0x7F,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.TimerBase = WDG_CK_Counter_Clock_8,
.WindowValue = 0x7F,
.CounterPreset = 0x7F,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.TimerBase = WDG_CK_Counter_Clock_8,
.WindowValue = 0x7F,
.CounterPreset = 0x7F,
.ActivationBit = 0,
},
};
const Wdg_GeneralType WdgWWDGGeneral =
{
.Wdg_Index = 0,
.Wdg_TriggerLocationPtr = Wdg_WWDG_Trigger,
.Wdg_SetModeLocationPtr = Wdg_WWDG_SetMode,
};
const Wdg_WWDG_ConfigType WdgWWDGConfig =
{
.Wdg_General = &WdgWWDGGeneral,
.Wdg_WWDGModeConfig = &WdgWWDGModeConfig,
};
const Wdg_ConfigType WdgConfig =
{
&WdgIWDGConfig,
&WdgWWDGConfig,
};
|
2301_81045437/classic-platform
|
boards/no_os/config/Wdg_Lcfg.c
|
C
|
unknown
| 3,166
|
# Note! This file should not be used directly, but included from
# subdirectories
inc-y += $(ROOTDIR)/boards/no_os/config
inc-y += $(ROOTDIR)/boards/no_os/
vpath-y += $(ROOTDIR)/boards/no_os/src
obj-y += misc_stubs.o
ifeq ($(boarddir),linux)
else
# mpc5xxx_callout_stubs.o
obj-$(CFG_PPC) += mpc5xxx_callout_stubs.o
vpath-$(CFG_PPC) += $(ROOTDIR)/mcal/arch/mpc5xxx/src/integration
obj-$(CFG_TC29X) += tcxxx_trap_asm.o
endif
|
2301_81045437/classic-platform
|
boards/no_os/makefile.mod.mk
|
Makefile
|
unknown
| 456
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Os.h"
uint16 EA_count;
/*lint -w1*/
void ShutdownOS( StatusType error ) {
}
#if defined(CFG_TC2XX)
uint32 Irq_VectorTable[1];
void Os_Isr( uint32 x) {
}
void Trap_MMU( void ) {
}
void Trap_InternalProtection( void ) {
}
void Trap_InstructionErrors( void ) {
}
void Trap_ContextManagement( void ) {
}
void Trap_SystemBusAndPeripheralErrors( void ) {
}
void Trap_AssertionTraps( void ) {
}
void Trap_SystemCall( void ) {
}
void Trap_NMI( void ) {
}
#endif
#if defined(CFG_ARM)
#define _STAY() while(1) {}
void Undefined_Instruction_Handler( void ) {
_STAY();
}
void Dummy_Irq( void ) {
_STAY();
}
void Prefetch_Exc_Handler( void ) {
_STAY();
}
void Data_Exc_Handler( void ) {
_STAY();
}
void Irq_Handler( void ) {
_STAY();
}
void Fiq_Handler( void ) {
_STAY();
}
void SupervisorCall_Handler( void ) {
_STAY();
}
#endif
|
2301_81045437/classic-platform
|
boards/no_os/src/misc_stubs.c
|
C
|
unknown
| 1,721
|
# ARCH defines
ARCH=rh850_x
ARCH_FAM=renesas
# CFG (y/n) macros
CFG=RH850 RH850F1H HW_FLOAT OS_SYSTICK2 TIMER TIMER_OSTM
CFG+=CREATE_SREC
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+= CAN MCU PORT DIO GPT FR ETH WDG ADC
# Required modules
MOD_USE += MCU KERNEL
# Defines
#def-y += SRAM_SIZE=0x00020000
# Default cross compiler
COMPILER?=ghs
#DEFAULT_CROSS_COMPILE = /c/devtools/ghs/comp_201355
#DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201355
DEFAULT_CROSS_COMPILE = /opt/v850-elf/bin/v850-elf-
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201355
GHS_TARGET?=rh850
|
2301_81045437/classic-platform
|
boards/rh850f1h/build_config.mk
|
Makefile
|
unknown
| 640
|
# ARCH defines
ARCH=rh850_x
ARCH_FAM=renesas
# CFG (y/n) macros
CFG=RH850 RH850F1L OS_SYSTICK2 TIMER TIMER_OSTM
CFG+=CREATE_SREC
# Set RF7010132 (64pin) as default device
RH850_PARTNUM?=RF7010132
# Supported RH850F1L_PARTNUM below
ifeq ($(RH850_PARTNUM),RF7010132)
def-y += L_FLASH_CODE_0_LENGTH=0x80000
endif
ifeq ($(RH850_PARTNUM),RF7010243)
def-y += L_FLASH_CODE_0_LENGTH=0xc0000
endif
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+= CAN MCU PORT DIO GPT FR ETH WDG ADC SPI EEP PWM
# Required modules
MOD_USE += MCU KERNEL
# Defines
#def-y += SRAM_SIZE=0x00020000
# Default cross compiler
COMPILER?=ghs
#DEFAULT_CROSS_COMPILE = /c/devtools/ghs/comp_201355
#DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201355
DEFAULT_CROSS_COMPILE = /opt/v850-elf/bin/v850-elf-
#DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201355
DEFAULT_GHS_COMPILE = /c/devtools/ghs/v800/comp_201355
GHS_TARGET?=rh850
|
2301_81045437/classic-platform
|
boards/rh850f1l/build_config.mk
|
Makefile
|
unknown
| 976
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/rh850f1l/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD Spi_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 Spi_SEQ_CMD2
#define SPI_SEQ_EEP_READ Spi_SEQ_READ
#define SPI_SEQ_EEP_WRITE Spi_SEQ_WRITE
#define SPI_CH_EEP_CMD Spi_CH_CMD
#define SPI_CH_EEP_ADDR Spi_CH_ADDR
#define SPI_CH_EEP_WREN Spi_CH_WREN
#define SPI_CH_EEP_DATA Spi_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/rh850f1l/config/Eep_Lcfg.c
|
C
|
unknown
| 3,925
|
# ARCH defines
ARCH=armv7_m
ARCH_FAM=arm
ARCH_MCU=s32k144
#
# CFG (y/n) macros
#
#CFG=ARM ARMV7E_M ARM_CM4 THUMB
CFG=ARM ARMV7_M ARM_CM3 THUMB
CFG+=S32K144
CFG+=S32K144EVB_0100
# Add our board
CFG+=BRD_S32K144EVB_0100
# What buildable modules does this board have,
# default or private
# MCAL (supplied by NXP)
MOD_AVAIL+=ADC CAN DIO MCU FLS FEE PORT PWM GPT WDG SPI IRQ DMA ETH FR I2C ICU IOM LIN PWM STM UART TTY_UART TCPIP LWIP
# Required modules
MOD_USE += KERNEL
#
# Extra defines
#
COMPILER?=gcc
#COMPILER?=ghs
#COMPILER?=iar
# Default cross compiler
DEFAULT_CROSS_COMPILE = /opt/arm-none-eabi/bin/arm-none-eabi-
DEFAULT_GHS_COMPILE=/c/devtools/ghs/arm/comp_201354
DEFAULT_IAR_COMPILE = /c/devtools/IAR/IAR_Systems/Embedded_Workbench_8_0
|
2301_81045437/classic-platform
|
boards/s32k144evb_0100/build_config.mk
|
Makefile
|
unknown
| 796
|
# ARCH defines
ARCH=armv7_m
ARCH_FAM=arm
ARCH_MCU=s32k148
#
# CFG (y/n) macros
#
#CFG=ARM ARMV7E_M ARM_CM4 THUMB
CFG=ARM ARMV7_M ARM_CM3 THUMB
CFG+=S32K148
# Add our board
CFG+=BRD_S32K148_EVBQ176
# What buildable modules does this board have,
# default or private
# MCAL (supplied by NXP)
MOD_AVAIL+=MCU CAN DIO PORT LIN SPI GPT ETH MCL ADC LWIP TCPIP
# Required modules
MOD_USE += KERNEL
#
# Extra defines
#
# Default cross compiler
COMPILER?=gcc
# Default cross compiler
#COMPILER_FLAVOR=s32_newlib
#DEFAULT_CROSS_COMPILE = /c/NXP/S32DS_ARM_v2018.R1/Cross_Tools/gcc-arm-none-eabi-4_9/bin/arm-none-eabi-
DEFAULT_CROSS_COMPILE = /opt/arm-none-eabi/bin/arm-none-eabi-
|
2301_81045437/classic-platform
|
boards/s32k148_evbq176/build_config.mk
|
Makefile
|
unknown
| 720
|