code
stringlengths 1
1.05M
| repo_name
stringlengths 6
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stringlengths 3
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|---|---|---|---|---|---|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#ifndef FEE_CFG_H_
#define FEE_CFG_H_
#include "MemIf_Types.h"
#include "Fee_ConfigTypes.h"
#define FEE_DEV_ERROR_DETECT STD_ON
#define FEE_VERSION_INFO_API STD_ON
#define FEE_POLLING_MODE STD_ON
#define FEE_INDEX 0
#define FEE_VIRTUAL_PAGE_SIZE 16
#define FEE_NUM_OF_BLOCKS 5
#define FEE_MAX_NUM_SETS 1
#endif /*FEE_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/generic/Fee_Cfg.h
|
C
|
unknown
| 1,193
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef FEE_MEMORY_CFG_H_
#define FEE_MEMORY_CFG_H_
#define FEE_BANK1_OFFSET 0x0000
#define FEE_BANK2_OFFSET 0x4000
#define FEE_BANK1_LENGTH 0x4000
#define FEE_BANK2_LENGTH 0x4000
#endif
|
2301_81045437/classic-platform
|
boards/generic/Fee_Memory_Cfg.h
|
C
|
unknown
| 973
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Std_Types.h"
#include "Mcu.h"
#include "Mcu_Arc.h"
#include "asm_ppc.h"
/* #warning "This default file may only be used as an example!" */
/**
* @param sleepCfg
*/
void Mcu_Arc_SetModePre2( Mcu_ModeType mcuMode, const struct Mcu_Arc_SleepConfig *sleepCfg ) {
(void)mcuMode; /*lint !e920 Argument not used */
(void)sleepCfg; /*lint !e920 Argument not used */
}
/**
* @param sleepCfg
*/
void Mcu_Arc_SetModePost2( Mcu_ModeType mcuMode, const struct Mcu_Arc_SleepConfig *sleepCfg ) {
(void)mcuMode; /*lint !e920 Argument not used */
(void)sleepCfg; /*lint !e920 Argument not used */
}
|
2301_81045437/classic-platform
|
boards/generic/Mcu_Arc_Cfg.c
|
C
|
unknown
| 1,407
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MCU_ARC_CFG_H_
#define MCU_ARC_CFG_H_
#if !defined(_ASSEMBLER_)
struct Mcu_Arc_SleepPrivData {
uint32_t dummy;
};
typedef struct Mcu_Arc_SleepConfig {
uint32_t dummy;
struct Mcu_Arc_SleepPrivData *pData;
} Mcu_Arc_SleepConfigType;
typedef struct Mcu_Arc_Config {
const struct Mcu_Arc_SleepConfig *sleepConfig;
const struct TlbEntry *tblTable;
} Mcu_Arc_ConfigType;
extern const struct Mcu_Arc_Config Mcu_Arc_ConfigData;
#endif
#endif /* MCU_ARC_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/generic/Mcu_Arc_Cfg.h
|
C
|
unknown
| 1,276
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MCU_CFG_H_
#define MCU_CFG_H_
#define MCU_DEV_ERROR_DETECT STD_OFF
#define MCU_PERFORM_RESET_API STD_OFF
#define MCU_VERSION_INFO_API STD_OFF
#define MCU_NO_PLL STD_OFF
#define MCU_INIT_CLOCK STD_OFF
#define MCU_GET_RAM_STATE STD_OFF
#define MCU_CLOCK_SRC_FAILURE_NOTIFICATION STD_OFF
/* Mcu Modes (Symbolic name) */
#define McuConf_McuModeSettingConf_RUN (Mcu_ModeType)0u
#define McuConf_McuModeSettingConf_SLEEP (Mcu_ModeType)1u
#define McuConf_McuModeSettingConf_NORMAL (Mcu_ModeType)2u
/* Mcu Clock Types (Symbolic name) */
#define McuConf_McuClockSettingConfig_EXT_REF_66MHZ (Mcu_ClockType)0u
#define McuConf_McuClockSettingConfig_EXT_REF_80MHZ (Mcu_ClockType)1u
#define McuConf_McuClockSettingConfig_XOSC_CAN (Mcu_ClockType)2u
#endif /* MCU_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/generic/Mcu_Cfg.h
|
C
|
unknown
| 1,652
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#ifndef MEMIF_CFG_H_
#define MEMIF_CFG_H_
#include "MemIf_Types.h"
#if defined(USE_FEE)
#include "Fee.h"
#endif
#if defined(USE_EA)
#include "Ea.h"
#endif
#define MEMIF_VERSION_INFO_API STD_ON // Activate/Deactivate ver info API.
#define MEMIF_DEV_ERROR_DETECT STD_ON // Activate/Deactivate Dev Error Detection and Notification.
#define MEMIF_NUMBER_OF_DEVICES 1 // Number of underlying memory abstraction modules.
#if (MEMIF_NUMBER_OF_DEVICES == 1)
#define MEMIF_DEVICE_TO_USE FLS_DRIVER_INDEX
#endif
#endif /*MEMIF_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/generic/MemIf_Cfg.h
|
C
|
unknown
| 1,407
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "NvM.h"
#warning "This default file may only be used as an example!"
const NvM_BlockDescriptorType BlockDescriptorList[] = {
};
const NvM_ConfigType NvM_Config = {
.Common = {
.MultiBlockCallback = NULL,
},
.BlockDescriptor = BlockDescriptorList,
};
|
2301_81045437/classic-platform
|
boards/generic/NvM_Cfg.c
|
C
|
unknown
| 1,072
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef NVM_CFG_H_
#define NVM_CFG_H_
#include "NvM_Types.h"
#include "NvM_ConfigTypes.h"
#define NVM_DEV_ERROR_DETECT STD_ON
#define NVM_VERSION_INFO_API STD_ON
#define NVM_SET_RAM_BLOCK_STATUS_API STD_OFF
#define NVM_API_CONFIG_CLASS NVM_API_CONFIG_CLASS_1 // Class 1-3
#define NVM_COMPILED_CONFIG_ID 0 // 0..65535
#define NVM_CRC_NUM_OF_BYTES 0 // 1..65535
#define NVM_DATASET_SELECTION_BITS 0 // 0..8
#define NVM_DRV_MODE_SWITCH STD_OFF // OFF = SLOW, ON = FAST
#define NVM_DYNAMIC_CONFIGURATION STD_OFF // OFF..ON
#define NVM_JOB_PRIORIZATION STD_OFF // OFF..ON
#define NVM_MAX_NUMBER_OF_WRITE_RETRIES 2 // 0..7
#define NVM_POLLING_MODE STD_OFF // OFF..ON
#define NVM_SIZE_IMMEDIATE_JOB_QUEUE 0 // 1..255
#define NVM_SIZE_STANDARD_JOB_QUEUE 0 // 1..255
#define NVM_NUM_OF_NVRAM_BLOCKS 0
#endif /*NVM_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/generic/NvM_Cfg.h
|
C
|
unknown
| 1,677
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* THIS IS A TEMPLATE FILE
* This file should be generated by the make system. A hash of pre compiled data (e.g.
* the header files for the modules that supports post build) shall be calculated
* produce the define below with that hash. This file is included both by the
* EcuM configuration and the Postbuild configuration. The hashes in EcuM conf. and
* post build conf. is compared in EcuM and the node will only start if they match.
*/
#define PRE_COMPILED_DATA_HASH_LOW (0x5555AAAA)
#define PRE_COMPILED_DATA_HASH_HIGH (0x5555AAAA)
|
2301_81045437/classic-platform
|
boards/generic/PreCompiledDataHash.h
|
C
|
unknown
| 1,305
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "RamTst.h"
#warning "This default file may only be used as an example!"
#define RAMTSTALGPARAMS_RAMTSTBLOCKPARAMS_INDEX 0
const RamTst_BlockParamsType RamTstAlgParams_RamTstBlockParams[] = {
{
.RamTstBlockId = 1,
.RamTstBlockIndex = RAMTSTALGPARAMS_RAMTSTBLOCKPARAMS_INDEX,
.RamTstStartAddress = (uint32)MyRamTestArea,
.RamTstEndAddress = ((uint32)MyRamTestArea+2048),
}
};
const RamTst_AlgParamsType RamTstAlgParams[] = {
{
.RamTstAlgParamsId = 19,
.RamTstAlgorithm = RAMTST_MARCH_TEST,
.RamTstNumberOfBlocks = 2,
.RamTstBlockParams = RamTstAlgParams_RamTstBlockParams,
}
};
const RamTst_ConfigParamsType RamTst_ConfigParams = {
.RamTstDefaultAlgParamsId = 1,
.RamTstNumberOfAlgParamSets = 1,
#if defined(USE_DEM)
.RAMTST_E_RAM_FAILURE = DemConf_DemEventParameter_RAMTST_E_RAM_FAILURE,
#endif
.RamTstAlgParams = RamTstAlgParams,
};
|
2301_81045437/classic-platform
|
boards/generic/RamTst_Cfg.c
|
C
|
unknown
| 1,779
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
/* @req SWS_RamTst_00080 */
#if !(((RAMTST_SW_MAJOR_VERSION == 2) && (RAMTST_SW_MINOR_VERSION == 0)) )
#error RamTst: Configuration file expected BSW module version to be 2.0.*
#endif
#if !(((RAMTST_AR_MAJOR_VERSION == 4) && (RAMTST_AR_MINOR_VERSION == 1)) )
#error RamTst: Configuration file expected AUTOSAR version to be 4.1.*
#endif
#ifndef RAMTST_CFG_H_
#define RAMTST_CFG_H_
#define RAMTST_DEV_ERROR_DETECT STD_ON
#define RAMTST_ALLOW_API STD_ON
#define RAMTST_CHANGE_NUMBER_OF_TESTED_CELLS_API STD_OFF
#define RAMTST_GET_ALG_PARAMS_API STD_OFF
#define RAMTST_GET_EXECUTION_STATUS_API STD_OFF
#define RAMTST_GET_NUMBER_OF_TESTED_CELLS_API STD_OFF
#define RAMTST_GET_TEST_ALGORITHM_API STD_OFF
#define RAMTST_GET_TEST_RESULT_API STD_OFF
#define RAMTST_GET_TEST_RESULT_PER_BLOCK_API STD_OFF
#define RAMTST_GET_VERSION_INFO_API STD_ON
#define RAMTST_RESUME_API STD_OFF
#define RAMTST_RUN_FULL_TEST_API STD_ON
#define RAMTST_RUN_PARTIAL_TEST_API STD_OFF
#define RAMTST_SELECT_ALG_PARAMS_API STD_OFF
#define RAMTST_STOP_API STD_ON
#define RAMTST_SUSPEND_API STD_OFF
#define RAMTST_ABRAHAM_TEST_SELECTED STD_OFF
#define RAMTST_CHECKERBOARD_TEST_SELECTED STD_OFF
#define RAMTST_GALPAT_TEST_SELECTED STD_OFF
#define RAMTST_MARCH_TEST_SELECTED STD_ON
#define RAMTST_TRANSP_GALPAT_TEST_SELECTED STD_OFF
#define RAMTST_WALK_PATH_TEST_SELECTED STD_OFF
extern const RamTst_ConfigParamsType RamTst_ConfigParams;
#define RAMTST_NUM_BLOCKS 1
#endif /*RAMTST_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/generic/RamTst_Cfg.h
|
C
|
unknown
| 2,846
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SCHM_CFG_H_
#define SCHM_CFG_H_
#warning "This default file may only be used as an example!"
#define SCHM_MF_MEM_PERIOD 20
/* @req SWS_BSW_00236 Configuration parameters to get Version Info */
/* @req SWS_BSW_00051 */
#define SCHM_VERSION_INFO_API STD_ON
/*
* Scheduling BSW
*/
#define SCHM_CYCLE_MAIN (5)
#define SCHM_MAINFUNCTION_CYCLE_ADC SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_WRITE SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_MODE SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_READ SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_BUSOFF SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_WAKEUP SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_ERROR SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_DCAN_WRITE SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_DCAN_MODE SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_DCAN_READ SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_DCAN_BUSOFF SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_DCAN_WAKEUP SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CAN_DCAN_ERROR SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_XCP SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CANNM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_LINIF SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_LINSM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CANSM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CANTP SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_CANTRCV SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_COMRX SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_COMTX SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_COMM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_DCM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_DEM SCHM_CYCLE_MAIN
#if defined(CFG_SAFETY_PLATFORM)
#define SCHM_MAINFUNCTION_CYCLE_ECUM_A0 SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_ECUM_QM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_SAFEIOHWAB SCHM_CYCLE_MAIN
#else
#define SCHM_MAINFUNCTION_CYCLE_ECUM SCHM_CYCLE_MAIN
#endif
#define SCHM_MAINFUNCTION_CYCLE_BSWM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_EA SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_EEP SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_J1939TP (SCHM_CYCLE_MAIN*10)
//#define SCHM_MAINFUNCTION_CYCLE_FEE SCHM_CYCLE_MAIN
//#define SCHM_MAINFUNCTION_CYCLE_FLS SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_IOHWAB SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_SAFEIOHWAB SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_NM SCHM_CYCLE_MAIN
//#define SCHM_MAINFUNCTION_CYCLE_NvM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_PDUR SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_SPI SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_WDGM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_WDGM_TRIGGER SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_WDGM_ALIVESUPERVISION SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_RTM SCHM_CYCLE_MAIN
/*
* Schedule BSW memory
*/
#define SCHM_MAINFUNCTION_CYCLE_NVM SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_FEE SCHM_CYCLE_MAIN
#define SCHM_MAINFUNCTION_CYCLE_FLS SCHM_CYCLE_MAIN
#endif /*SCHM_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/generic/SchM_cfg.h
|
C
|
unknown
| 4,126
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef ADC_CONFIGTYPES_H_
#define ADC_CONFIGTYPES_H_
#if defined(CFG_GNULINUX)
typedef uint16_t Adc_ValueGroupType;
/* Group definitions. */
typedef enum
{
ADC_CH0,
ADC_CH1,
ADC_CH2,
ADC_CH3,
ADC_CH4,
ADC_CH5,
ADC_CH6,
ADC_CH7,
ADC_CH8,
ADC_CH9,
ADC_CH10,
ADC_CH11,
ADC_CH12,
ADC_CH13,
ADC_CH14,
ADC_CH15,
ADC_NBR_OF_CHANNELS,
}Adc_ChannelType;
/* Std-type, supplier defined */
typedef enum
{
ADC_SYSTEM_CLOCK
}Adc_ClockSourceType;
/* Std-type, supplier defined */
typedef enum
{
ADC_SYSTEM_CLOCK_DISABLED,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,
}Adc_PrescaleType;
/* Non-standard type */
typedef struct
{
Adc_ClockSourceType clockSource;
uint8_t hwUnitId;
Adc_PrescaleType adcPrescale;
}Adc_HWConfigurationType;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONVERSION_TIME_2_CLOCKS,
ADC_CONVERSION_TIME_8_CLOCKS,
ADC_CONVERSION_TIME_64_CLOCKS,
ADC_CONVERSION_TIME_128_CLOCKS
}Adc_ConversionTimeType;
/* Channel definitions, std container */
typedef struct
{
Adc_ConversionTimeType adcChannelConvTime;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;
// NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;
// NOT SUPPORTED Adc_ResolutionType adcChannelResolution;
// NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;
} Adc_ChannelConfigurationType;
/* Used ?? */
typedef struct
{
uint8 notifictionEnable;
Adc_ValueGroupType * resultBufferPtr;
Adc_StatusType groupStatus;
} Adc_GroupStatus;
/* Std-type, supplier defined */
typedef enum
{
ADC_CONV_MODE_DISABLED,
ADC_CONV_MODE_ONESHOT = 1,
ADC_CONV_MODE_CONTINUOUS = 9,
} Adc_GroupConvModeType;
/** Not supported. */
typedef uint16_t Adc_StreamNumSampleType;
/* Implementation specific */
typedef struct
{
// NOT SUPPORTED Adc_GroupAccessModeType accessMode;
Adc_GroupConvModeType conversionMode;
Adc_TriggerSourceType triggerSrc;
// NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;
// NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;
void (*groupCallback)(void);
// NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;
// NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;
const Adc_ChannelType *channelList;
Adc_ValueGroupType *resultBuffer;
// NOT SUPPORTED Adc_CommandType *commandBuffer;
Adc_ChannelType numberOfChannels;
Adc_GroupStatus *status;
// NOT SUPPORTED Dma_ChannelType dmaCommandChannel;
// NOT SUPPORTED Dma_ChannelType dmaResultChannel;
// NOT SUPPORTED const struct tcd_t * groupDMACommands;
// NOT SUPPORTED const struct tcd_t * groupDMAResults;
} Adc_GroupDefType;
/* Non-standard type */
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
const Adc_ChannelConfigurationType* channelConfigPtr;
const uint16_t nbrOfChannels;
const Adc_GroupDefType* groupConfigPtr;
const uint16_t nbrOfGroups;
} Adc_ConfigType;
extern const Adc_ConfigType AdcConfig [];
#elif defined(CFG_JACINTO)
/* @req:JACINTO5 SWS_Adc_00508 */
typedef uint16_t Adc_ValueGroupType;
/* @req:JACINTO5 SWS_Adc_00507 */
typedef uint16 Adc_GroupType;
/* @req:JACINTO5 SWS_Adc_00506 */
typedef uint8_t Adc_ChannelType;
/* @req:JACINTO5 SWS_Adc_00509 */
typedef uint16_t Adc_PrescaleType;
/* !req:JACINTO5 SWS_Adc_00510 Adc_ConversionTimeType not configurable */
/* !req:JACINTO5 SWS_Adc_00511 Adc_SamplingTimeType not configurable */
/* !req:JACINTO5 SWS_Adc_00512 Adc_ResolutionType not configurable*/
/* @req:JACINTO5 SWS_Adc_00518 */
typedef uint16_t Adc_StreamNumSampleType;
/* @req:JACINTO5 SWS_Adc_00515 */
typedef enum
{
ADC_CONV_MODE_ONESHOT = 0,
ADC_CONV_MODE_CONTINUOUS
} Adc_GroupConvModeType;
typedef uint32 Adc_ArcControllerIdType;
/* Channel definitions, std container */
typedef struct
{
Adc_ChannelType Adc_Channel;
uint32 Adc_ChnDiff;
uint32 Adc_ChnSelrfm;
uint32 Adc_ChnSelrfp;
} Adc_ChannelConfigurationType;
typedef struct
{
uint8 notifictionEnable;
Adc_ValueGroupType *resultBufferPtr;
Adc_StatusType groupStatus;
Adc_StreamNumSampleType currSampleCount; /* Samples per group counter. =0 until first round of conversions complete
(all channels in group). Then =1 until second round of conversions complete and so on.*/
Adc_ValueGroupType *currResultBufPtr; /* Streaming sample current buffer pointer */
} Adc_GroupStatus;
typedef struct
{
uint8_t hwUnitId;
Adc_PrescaleType adcPrescale;
uint32 numberOfChannels;
const Adc_ChannelConfigurationType *channelList;
}Adc_HWConfigurationType;
/** Container for group setup. */
typedef struct
{
Adc_GroupAccessModeType accessMode;
Adc_GroupConvModeType conversionMode;
Adc_TriggerSourceType triggerSrc;
/* @req SWS_Adc_00085 */
void (*groupCallback)(void);
Adc_StreamBufferModeType streamBufferMode;
Adc_StreamNumSampleType streamNumSamples;
const uint32 *channelMappingList;
Adc_ChannelType numberOfChannels;
Adc_GroupStatus *status;
uint32 hwUnit;
}Adc_GroupDefType;
/** Container for module initialization parameters. */
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
const Adc_GroupDefType* groupConfigPtr;
const Adc_GroupType nbrOfGroups;
}Adc_ConfigType;
#endif
#endif /* ADC_CONFIGTYPES_H_ */
|
2301_81045437/classic-platform
|
boards/gnulinux/Adc_ConfigTypes.h
|
C
|
unknown
| 7,951
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef CPU_H
#define CPU_H
#include "Std_Types.h"
typedef uint32_t imask_t;
#define Irq_Save(flags) ((flags) = 0) // Dummy assignment to avoid compiler warnings
#define Irq_Restore(flags) (void)(flags)
#define Irq_Disable()
#define Irq_Enable()
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
#define ilog2(_x) (__builtin_ffs(_x) - 1)
#endif /* CPU_H */
|
2301_81045437/classic-platform
|
boards/gnulinux/Cpu.h
|
C
|
unknown
| 1,255
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @tagSettings DEFAULT_ARCHITECTURE=GENERIC */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2|4.3.0*/
/** @addtogroup Mcu MCU Driver
* @{ */
/** @file Mcu.h
* API and type definitions for MCU Driver.
*/
/* @req 4.1.2|4.3.0/SWS_Mcu_00215 */
#ifndef MCU_H_
#define MCU_H_
#define MCU_MODULE_ID 101
#define MCU_VENDOR_ID 60
#define MCU_SW_MAJOR_VERSION 2
#define MCU_SW_MINOR_VERSION 0
#define MCU_SW_PATCH_VERSION 0
#define MCU_AR_RELEASE_MAJOR_VERSION 4
#define MCU_AR_RELEASE_MINOR_VERSION 1
#define MCU_AR_RELEASE_PATCH_VERSION 2
/* @req 4.1.2|4.3.0/SWS_Mcu_00211 */
#include "Cpu.h"
#include "irq_types.h"
#include "Std_Types.h"
#include "Mcu_Cfg.h"
#if defined(USE_DEM)
#include "Dem.h"
#endif
/** @name Service id's */
//@{
#define MCU_INIT_SERVICE_ID 0x00
#define MCU_INITRAMSECTION_SERVICE_ID 0x01
#define MCU_INITCLOCK_SERVICE_ID 0x02
#define MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID 0x03
#define MCU_GETPLLSTATUS_SERVICE_ID 0x04
#define MCU_GETRESETREASON_SERVICE_ID 0x05
#define MCU_GETRESETRAWVALUE_SERVICE_ID 0x06
#define MCU_PERFORMRESET_SERVICE_ID 0x07
#define MCU_SETMODE_SERVICE_ID 0x08
#define MCU_GETVERSIONINFO_SERVICE_ID 0x09
#define MCU_INTCVECTORINSTALL_SERVICE_ID 0x0A // Not in spec but follows pattern
#define MCU_LOSS_OF_CLOCK_SERVICE_ID 0x0B // Not in spec but follows pattern
//@}
/* @req SWS_Mcu_000012 */
/** @name Error Codes */
//@{
#define MCU_E_PARAM_CONFIG 0x0A
#define MCU_E_PARAM_CLOCK 0x0B
#define MCU_E_PARAM_MODE 0x0C
#define MCU_E_PARAM_RAMSECTION 0x0D
#define MCU_E_PLL_NOT_LOCKED 0x0E
#define MCU_E_UNINIT 0x0F
#define MCU_E_PARAM_POINTER 0x10
//@}
/* Specific return values */
#define MCU_GETRESETRAWVALUE_NORESETREG_RV 0x00 /* Not used for PPC. Raw reset value is supported */
#define MCU_GETRESETRAWVALUE_UNINIT_RV 0xffffffffU /* Not used for PPC. Raw reset value is supported */
/* @req 4.1.2|4.3.0/SWS_Mcu_00250 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00231 */
typedef enum {
MCU_PLL_LOCKED,
MCU_PLL_UNLOCKED,
MCU_PLL_STATUS_UNDEFINED
} Mcu_PllStatusType;
/* @req 4.1.2|4.3.0/SWS_Mcu_00255 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00240 */
typedef uint8 Mcu_RamSectionType;
/* @req 4.1.2|4.3.0/SWS_Mcu_00253 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00236 */
typedef uint32 Mcu_RawResetType;
/* @req 4.1.2|4.3.0/SWS_Mcu_00251 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00233 */
typedef uint8 Mcu_ClockType;
/* @req 4.1.2|4.3.0/SWS_Mcu_00254 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00238 */
typedef uint8 Mcu_ModeType;
/* @req 4.1.2|4.3.0/SWS_Mcu_00252 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00234 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00134 */
typedef enum {
MCU_POWER_ON_RESET,
MCU_WATCHDOG_RESET,
MCU_SW_RESET,
MCU_RESET_UNDEFINED,
MCU_OSC_FAILURE_RESET,
MCU_CPU_RESET,
MCU_EXT_RESET,
MCU_VSW_RESET
} Mcu_ResetType;
typedef struct {
// This is the frequency for the specific instance of the McuClockReference-
// Point container. It shall be givn in Hz.
uint32 McuClockReferencePointFrequency;
uint8 Pll1; // PLL setting 1
uint8 Pll2; // PLL setting 2
uint8 Pll3; // PLL setting 3
uint8 Pll1_1; // PLL setting 1
uint8 Pll2_1; // PLL setting 2
uint8 Pll3_1; // PLL setting 3
uint8 Pll4; // PLL setting 4
} Mcu_ClockSettingConfigType;
typedef struct {
// This parameter shall represent the Data pre-setting to be initialized
uint32 McuRamDefaultValue;
// This parameter shall represent the MCU RAM section base address
uint32 McuRamSectionBaseAddress;
// This parameter shall represent the MCU RAM Section size
uint32 McuRamSectionSize;
} Mcu_RamSectorSettingConfigType;
#if ( MCU_GET_RAM_STATE == STD_ON )
/* @req 4.1.2|4.3.0/SWS_Mcu_00256 */
typedef enum {
MCU_RAMSTATE_INVALID,
MCU_RAMSTATE_VALID
} Mcu_RamStateType;
#endif
/* @req 4.1.2|4.3.0/SWS_Mcu_00249 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00131 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00054 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00031 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00030 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00035 */
typedef struct {
// This parameter shall represent the number of Modes available for the
// MCU. calculationFormula = Number of configured McuModeSettingConf
uint8 McuNumberOfMcuModes;
// This parameter shall represent the number of RAM sectors available for
// the MCU. calculationFormula = Number of configured McuRamSectorSet-
// tingConf
uint8 McuRamSectors;
// This parameter shall represent the number of clock setting available for
// the MCU.
uint8 McuClockSettings;
// This parameter defines the default clock settings that should be used
// It is an index into the McuClockSettingsConfig
Mcu_ClockType McuDefaultClockSettings;
// This parameter holds the DemEvent used when reporting McuClockFailure.
#ifdef USE_DEM
Dem_EventIdType McuClockFailure;
#endif
// This parameter relates to the MCU specific reset configuration. This ap-
// plies to the function Mcu_PerformReset, which performs a microcontroller
// reset using the hardware feature of the microcontroller.
//uint32 McuResetSetting;
// This container contains the configuration (parameters) for the
// Clock settings of the MCU. Please see MCU031 for more in-
// formation on the MCU clock settings.
const Mcu_ClockSettingConfigType * McuClockSettingConfig;
// This container contains the configuration (parameters) for the
// Mode setting of the MCU. Please see MCU035 for more information
// on the MCU mode settings.
//Mcu_ModeSettingConfigType *McuModeSettingConfig;
// This container contains the configuration (parameters) for the
// RAM Sector setting. Please see MCU030 for more information
// on RAM sec-tor settings.
const Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;
} Mcu_ConfigType;
extern const Mcu_ConfigType McuConfigData[];
/* @req 4.1.2|4.3.0/SWS_Mcu_00153 */
void Mcu_Init( const Mcu_ConfigType *ConfigPtr );
/* @req 4.1.2|4.3.0/SWS_Mcu_00154 */
Std_ReturnType Mcu_InitRamSection(Mcu_RamSectionType RamSection );
/* @req 4.1.2|4.3.0/SWS_Mcu_00207 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00209 */
#if ( MCU_GET_RAM_STATE == STD_ON )
Mcu_RamStateType Mcu_GetRamState( void );
#endif
/* @req 4.1.2|4.3.0/SWS_Mcu_00248*/
/* @req 4.1.2|4.3.0/SWS_Mcu_00155 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00210 */
#if ( MCU_INIT_CLOCK == STD_ON )
Std_ReturnType Mcu_InitClock( Mcu_ClockType ClockSetting );
#endif
/* @req 4.1.2|4.3.0/SWS_Mcu_00156 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00205 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00230 */
#if ( MCU_NO_PLL == STD_OFF )
Std_ReturnType Mcu_DistributePllClock( void );
#endif
/* @req 4.1.2|4.3.0/SWS_Mcu_00157 */
Mcu_PllStatusType Mcu_GetPllStatus( void );
/* @req 4.1.2|4.3.0/SWS_Mcu_00052*/
/* @req 4.1.2|4.3.0/SWS_Mcu_00158 */
Mcu_ResetType Mcu_GetResetReason( void );
/* @req 4.1.2|4.3.0/SWS_Mcu_00159 */
Mcu_RawResetType Mcu_GetResetRawValue( void );
/* @req 4.1.2|4.3.0/SWS_Mcu_00055 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00146 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00160 */
#if ( MCU_PERFORM_RESET_API == STD_ON )
void Mcu_PerformReset( void );
#endif
/* @req 4.1.2|4.3.0/SWS_Mcu_00164 */
/* @req 4.1.2|4.3.0/SWS_Mcu_00161 */
void Mcu_SetMode( Mcu_ModeType McuMode );
/* @req 4.1.2|4.3.0/SWS_Mcu_00162*/
#if ( MCU_VERSION_INFO_API == STD_ON )
void Mcu_GetVersionInfo( Std_VersionInfoType* versioninfo);
#endif
/* ArcCore extensions functions */
uint32 Mcu_Arc_GetSystemClock( void );
#if defined(CFG_MPC55XX) || defined(CFG_TMS570)
uint32 Mcu_Arc_GetPeripheralClock( Mcu_Arc_PeriperalClock_t type );
uint32 Mcu_Arc_GetClockReferencePointFrequency(void);
#endif
void Mcu_Arc_EnterLowPower( int mode );
void Mcu_Arc_LowPowerRecoverFlash( void );
void Mcu_Arc_InitZero(void);
Mcu_ResetType Mcu_Arc_GetResetReason(void);
void Mcu_Arc_DeInit(void);
void Mcu_Arc_LossOfLock(void);
void Mcu_Arc_LossOfClock(void);
#if defined(CFG_PPC)
void Mcu_Arc_GetECCError( uint8 *err );
#endif
#endif /*MCU_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/gnulinux/Mcu.h
|
C
|
unknown
| 9,293
|
# ARCH defines
ARCH=gnulinux
#ARCH_FAM=generic
ARCH_FAM=gnulinux
# CFG (y/n) macros
CFG= GNULINUX
# What buildable modules does this board have,
# default or private
#MOD_AVAIL+=XCP COM PDUR IPDUM WDGM WDGIF DET DCM DEM CANTP J1939TP CANIF RTE FEE NVM ECUM_FIXED ECUM_FLEXIBLE MCU EA KERNEL RAMLOG IOHWAB RTE E2E BSWM MEMIF DLT FRIF
MOD_AVAIL+=XCP COM PDUR IPDUM WDGM WDGIF DET DCM DEM CANTP J1939TP CANIF RTE FEE NVM ECUM_FIXED ECUM_FLEXIBLE MCU EA RAMLOG IOHWAB RTE E2E BSWM MEMIF DLT FRIF SOAD DOIP
# Linux OS
MOD_AVAIL+=LINUXOS LINUXOS_DB
# Network management
MOD_AVAIL+=COMM NM CANNM CANSM NMHB UDPNM
# Additional
MOD_AVAIL+=CRC CPL CAL
MOD_AVAIL+=LIN
MOD_AVAIL+=LINSM
MOD_AVAIL+=LINIF
MOD_AVAIL+=RAMTST
MOD_AVAIL+=CDDPDUR
MOD_AVAIL+=ETHSM
MOD_AVAIL+=FRSM
MOD_AVAIL+=FRNM
MOD_AVAIL+=FRTP
MOD_AVAIL+=ETHIF
MOD_AVAIL+=TCPIP
MOD_AVAIL+=CANTRCV
# Required modules
#MOD_USE +=
# Sqlite3 devel library needed for this.
#MOD_USE += LINUXOS_DB
SELECT_CLIB=CLIB_NATIVE
|
2301_81045437/classic-platform
|
boards/gnulinux/build_config.mk
|
Makefile
|
unknown
| 1,019
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This GNULinux header file probably needs to be further developed and nurtured!"
#ifndef DCM_CFG_H_
#define DCM_CFG_H_
/*
* DCM General
*/
#define DCM_VERSION_INFO_API STD_ON // Activate/Deactivate ver info API.
#define DCM_DEV_ERROR_DETECT STD_ON // Activate/Deactivate Dev Error Detection and Notification.
#define DCM_REQUEST_INDICATION_ENABLED STD_ON // Activate/Deactivate indication request mechanism.
#define DCM_RESPOND_ALL_REQUEST STD_ON // Activate/Deactivate response on SID 0x40-0x7f and 0xc0-0xff.
#define DCM_TASK_TIME TBD // Time for periodic task (in ms).
#define DCM_PAGEDBUFFER_ENABLED STD_OFF // Enable/disable page buffer mechanism (currently only disabled supported)
#endif /*DCM_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/gnulinux/config/Dcm_Cfg.h
|
C
|
unknown
| 1,531
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#ifndef ECUM_CFG_H_
#define ECUM_CFG_H_
#define ECUM_VERSION_INFO_API STD_OFF
#define ECUM_DEV_ERROR_DETECT STD_OFF
#include "EcuM_Generated_Types.h"
#define ECUM_MAIN_FUNCTION_PERIOD (200)
#define ECUM_NVRAM_READALL_TIMEOUT (10000)
#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)
#define ECUM_NVRAM_MIN_RUN_DURATION (10000)
typedef enum {
ECUM_USER_User_1,
ECUM_USER_ENDMARK // Must be the last in list!
} EcuM_UserList;
extern EcuM_ConfigType EcuMConfig;
#endif /*ECUM_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/gnulinux/config/EcuM_Cfg.h
|
C
|
unknown
| 1,334
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 3)) )
#error EcuM: Configuration file expected BSW module version to be 2.3.\*
#endif
#ifndef _ECUM_GENERATED_TYPES_H_
#define _ECUM_GENERATED_TYPES_H_
#include "PreCompiledDataHash.h"
/* @req SWS_EcuM_02992 */ /* @req SWS_EcuM_02992 */
#include "EcuM_Types.h"
#if defined(USE_MCU)
#include "Mcu.h"
#endif
#if defined(USE_PORT)
#include "Port.h"
#endif
#if defined(USE_CAN)
#include "Can.h"
#endif
#if defined(USE_DIO)
#include "Dio.h"
#endif
#if defined(USE_LIN)
#include "Lin.h"
#endif
#if defined(USE_CANIF)
#include "CanIf.h"
#endif
#if defined(USE_LINIF)
#include "LinIf.h"
#endif
#if defined(USE_PWM)
#include "Pwm.h"
#endif
#if defined (USE_OCU)
#include "Ocu.h"
#endif
#if defined (USE_ICU)
#include "Icu.h"
#endif
#if defined(USE_COM)
#include "Com.h"
#endif
#if defined(USE_PDUR)
#include "PduR.h"
#endif
#if defined(USE_DMA)
#include "Dma.h"
#endif
#if defined(USE_ADC)
#include "Adc.h"
#endif
#if defined(USE_GPT)
#include "Gpt.h"
#endif
#if defined(USE_COMM)
#include "ComM.h"
#endif
#if defined(USE_NM)
#include "Nm.h"
#endif
#if defined(USE_CANNM)
#include "CanNm.h"
#endif
#if defined(USE_CANSM)
#include "CanSM.h"
#endif
#if defined(USE_LINSM)
#include "LinSM.h"
#endif
#if defined(USE_J1939TP)
#include "J1939Tp.h"
#endif
#if defined(USE_UDPNM)
#include "UdpNm.h"
#endif
#if defined(USE_FLS)
#include "Fls.h"
#endif
#if defined(USE_EEP)
#include "Eep.h"
#endif
#if defined(USE_SPI)
#include "Spi.h"
#endif
#if defined(USE_WDG)
#include "Wdg.h"
#endif
#if defined(USE_WDGM)
#include "WdgM.h"
#endif
#if defined(USE_WDGIF)
#include "WdgIf.h"
#endif
#if defined(USE_ETH)
#include "Eth.h"
#endif
#if defined(USE_FR)
#include "Fr.h"
#endif
#if defined(USE_BSWM)
#include "BswM.h"
#endif
#if defined(USE_PDUR) || defined(USE_COM) || defined(USE_CANIF) || defined(USE_CANTP) || defined(USE_FRTP)
#include "EcuM_PBTypes.h"
#endif
#if defined(USE_DCM)
#include "Dcm.h"
#endif
#if defined(USE_DEM)
#include "Dem.h"
#endif
#if defined(USE_XCP)
#include "Xcp.h"
#endif
#if defined(USE_IPDUM)
#include "IpduM.h"
#endif
#if defined(USE_DLT)
#include "Dlt.h"
#endif
#if defined(USE_FR)
#include "Fr.h"
#endif
#if defined(USE_FRIF)
#include "FrIf.h"
#endif
#if defined(USE_FRNM)
#include "FrNm.h"
#endif
#if defined(USE_FRSM)
#include "FrSM.h"
#endif
#if defined(USE_FRTP)
#include "FrTp.h"
#endif
typedef struct EcuM_ConfigS
{
uint32 EcuMPostBuildVariant; /* @req SWS_EcuM_02794 */ /* @req SWS_EcuM_02794 */
uint64 EcuMConfigConsistencyHashLow; /* @req SWS_EcuM_02795 Hash set when compiling the whole software for the */ /* @req SWS_EcuM_02795 */
uint64 EcuMConfigConsistencyHashHigh; /* PB module. It is compared to the PB hash at startup. */
EcuM_StateType EcuMDefaultShutdownTarget;
uint8 EcuMDefaultSleepMode;
AppModeType EcuMDefaultAppMode;
uint32 EcuMRunMinimumDuration;
uint32 EcuMNvramReadAllTimeout;
uint32 EcuMNvramWriteAllTimeout;
Mcu_ModeType EcuMNormalMcuMode;
#if defined(USE_DEM)
Dem_EventIdType EcuMDemInconsistencyEventId;
Dem_EventIdType EcuMDemRamCheckFailedEventId;
Dem_EventIdType EcuMDemAllRunRequestsKilledEventId;
#endif
const EcuM_SleepModeType *EcuMSleepModeConfig;
const EcuM_WakeupSourceConfigType *EcuMWakeupSourceConfig;
#if defined(USE_ECUM_FLEXIBLE)
const EcuM_UserType *EcuMGoDownAllowedUsersConfig;
#endif
#if defined (USE_COMM)
const EcuM_ComMConfigType *EcuMComMConfig;
#endif
#if defined(USE_MCU)
const Mcu_ConfigType* McuConfigPtr;
#endif
#if defined(USE_PORT)
const Port_ConfigType* PortConfigPtr;
#endif
#if defined(USE_CAN)
const Can_ConfigType* CanConfigPtr;
#endif
#if defined(USE_DIO)
const Dio_ConfigType* DioConfigPtr;
#endif
#if defined(USE_CANSM)
const CanSM_ConfigType* CanSMConfigPtr;
#endif
#if defined(USE_LIN)
const Lin_ConfigType* LinConfigPtr;
#endif
#if defined(USE_LINIF)
const LinIf_ConfigType* LinIfConfigPtr;
#endif
#if defined(USE_LINSM)
const LinSM_ConfigType* LinSMConfigPtr;
#endif
#if defined(USE_ETH)
const Eth_ConfigType* EthConfigPtr;
#endif
#if defined(USE_NM)
const Nm_ConfigType* NmConfigPtr;
#endif
#if defined(USE_UDPNM)
const UdpNm_ConfigType* UdpNmConfigPtr;
#endif
#if defined(USE_COMM)
const ComM_ConfigType* ComMConfigPtr;
#endif
#if defined(USE_BSWM)
const BswM_ConfigType* BswMConfigPtr;
#endif
#if defined(USE_J1939TP)
const J1939Tp_ConfigType* J1939TpConfigPtr;
#endif
#if defined(USE_PWM)
const Pwm_ConfigType* PwmConfigPtr;
#endif
#if defined(USE_OCU)
const Ocu_ConfigType* OcuConfigPtr;
#endif
#if defined(USE_ICU)
const Icu_ConfigType* IcuConfigPtr;
#endif
#if defined(USE_DMA)
const Dma_ConfigType* DmaConfigPtr;
#endif
#if defined(USE_ADC)
const Adc_ConfigType* AdcConfigPtr;
#endif
#if defined(USE_GPT)
const Gpt_ConfigType* GptConfigPtr;
#endif
#if defined(USE_FLS)
const Fls_ConfigType* FlsConfigPtr;
#endif
#if defined(USE_EEP)
const Eep_ConfigType* EepConfigPtr;
#endif
#if defined(USE_SPI)
const Spi_ConfigType* SpiConfigPtr;
#endif
#if defined(USE_WDG)
const Wdg_ConfigType* WdgConfigPtr;
#endif
#if defined(USE_WDGIF)
const WdgIf_ConfigType* WdgIfConfigPtr;
#endif
#if defined(USE_WDGM)
const WdgM_ConfigType* WdgMConfigPtr;
#endif
#if defined(USE_DCM)
const Dcm_ConfigType* DcmConfigPtr;
#endif
#if defined(USE_DEM)
const Dem_ConfigType* DemConfigPtr;
#endif
#if defined(USE_XCP)
const Xcp_ConfigType* XcpConfigPtr;
#endif
#if defined(USE_IPDUM)
const IpduM_ConfigType* IpduMConfigPtr;
#endif
#if defined(USE_PDUR) || defined(USE_COM) || defined(USE_CANIF) || defined(USE_CANTP) || defined(USE_CANNM)
const PostbuildConfigType* PostBuildConfig;
#endif
#if defined(USE_DLT)
const Dlt_ConfigType* DltConfigPtr;
#endif
#if defined(USE_FR)
const Fr_ConfigType * FrConfigPtr;
#endif
#if defined(USE_FRIF)
const FrIf_ConfigType * FrIfConfigPtr;
#endif
#if defined(USE_FRNM)
const FrNm_ConfigType * FrNmConfigPtr;
#endif
#if defined(USE_FRSM)
const FrSM_ConfigType * FrSMConfigPtr;
#endif
#if defined(USE_FRTP)
const FrTp_ConfigType * FrTpConfigPtr;
#endif
} EcuM_ConfigType;
#endif /*_ECUM_GENERATED_TYPES_H_*/
|
2301_81045437/classic-platform
|
boards/gnulinux/config/EcuM_Generated_Types.h
|
C
|
unknown
| 7,276
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#if defined(USE_FEE)
#include "Fee.h"
#endif
const FlashType flashInfo[] =
{
{
.FlsBaseAddress= 0x00000000U,
.FlsTotalSize = 0x01000000U,
.sectCnt = 256U,
.bankSize = 0x01000000U, //128 MB
.regBase = 0xE000D000U,
.sectAddr =
{
0x00000000U,
0x00010000U,
0x00020000U,
0x00030000U,
0x00040000U,
0x00050000U,
0x00060000U,
0x00070000U,
0x00080000U,
0x00090000U,
0x000A0000U,
0x000B0000U,
0x000C0000U,
0x000D0000U,
0x000E0000U,
0x000F0000U,
0x00100000U,
0x00110000U,
0x00120000U,
0x00130000U,
0x00140000U,
0x00150000U,
0x00160000U,
0x00170000U,
0x00180000U,
0x00190000U,
0x001A0000U,
0x001B0000U,
0x001C0000U,
0x001D0000U,
0x001E0000U,
0x001F0000U,
0x00200000U,
0x00210000U,
0x00220000U,
0x00230000U,
0x00240000U,
0x00250000U,
0x00260000U,
0x00270000U,
0x00280000U,
0x00290000U,
0x002A0000U,
0x002B0000U,
0x002C0000U,
0x002D0000U,
0x002E0000U,
0x002F0000U,
0x00300000U,
0x00310000U,
0x00320000U,
0x00330000U,
0x00340000U,
0x00350000U,
0x00360000U,
0x00370000U,
0x00380000U,
0x00390000U,
0x003A0000U,
0x003B0000U,
0x003C0000U,
0x003D0000U,
0x003E0000U,
0x003F0000U,
0x00400000U,
0x00410000U,
0x00420000U,
0x00430000U,
0x00440000U,
0x00450000U,
0x00460000U,
0x00470000U,
0x00480000U,
0x00490000U,
0x004A0000U,
0x004B0000U,
0x004C0000U,
0x004D0000U,
0x004E0000U,
0x004F0000U,
0x00500000U,
0x00510000U,
0x00520000U,
0x00530000U,
0x00540000U,
0x00550000U,
0x00560000U,
0x00570000U,
0x00580000U,
0x00590000U,
0x005A0000U,
0x005B0000U,
0x005C0000U,
0x005D0000U,
0x005E0000U,
0x005F0000U,
0x00600000U,
0x00610000U,
0x00620000U,
0x00630000U,
0x00640000U,
0x00650000U,
0x00660000U,
0x00670000U,
0x00680000U,
0x00690000U,
0x006A0000U,
0x006B0000U,
0x006C0000U,
0x006D0000U,
0x006E0000U,
0x006F0000U,
0x00700000U,
0x00710000U,
0x00720000U,
0x00730000U,
0x00740000U,
0x00750000U,
0x00760000U,
0x00770000U,
0x00780000U,
0x00790000U,
0x007A0000U,
0x007B0000U,
0x007C0000U,
0x007D0000U,
0x007E0000U,
0x007F0000U,
0x00800000U,
0x00810000U,
0x00820000U,
0x00830000U,
0x00840000U,
0x00850000U,
0x00860000U,
0x00870000U,
0x00880000U,
0x00890000U,
0x008A0000U,
0x008B0000U,
0x008C0000U,
0x008D0000U,
0x008E0000U,
0x008F0000U,
0x00900000U,
0x00910000U,
0x00920000U,
0x00930000U,
0x00940000U,
0x00950000U,
0x00960000U,
0x00970000U,
0x00980000U,
0x00990000U,
0x009A0000U,
0x009B0000U,
0x009C0000U,
0x009D0000U,
0x009E0000U,
0x009F0000U,
0x00A00000U,
0x00A10000U,
0x00A20000U,
0x00A30000U,
0x00A40000U,
0x00A50000U,
0x00A60000U,
0x00A70000U,
0x00A80000U,
0x00A90000U,
0x00AA0000U,
0x00AB0000U,
0x00AC0000U,
0x00AD0000U,
0x00AE0000U,
0x00AF0000U,
0x00B00000U,
0x00B10000U,
0x00B20000U,
0x00B30000U,
0x00B40000U,
0x00B50000U,
0x00B60000U,
0x00B70000U,
0x00B80000U,
0x00B90000U,
0x00BA0000U,
0x00BB0000U,
0x00BC0000U,
0x00BD0000U,
0x00BE0000U,
0x00BF0000U,
0x00C00000U,
0x00C10000U,
0x00C20000U,
0x00C30000U,
0x00C40000U,
0x00C50000U,
0x00C60000U,
0x00C70000U,
0x00C80000U,
0x00C90000U,
0x00CA0000U,
0x00CB0000U,
0x00CC0000U,
0x00CD0000U,
0x00CE0000U,
0x00CF0000U,
0x00D00000U,
0x00D10000U,
0x00D20000U,
0x00D30000U,
0x00D40000U,
0x00D50000U,
0x00D60000U,
0x00D70000U,
0x00D80000U,
0x00D90000U,
0x00DA0000U,
0x00DB0000U,
0x00DC0000U,
0x00DD0000U,
0x00DE0000U,
0x00DF0000U,
0x00E00000U,
0x00E10000U,
0x00E20000U,
0x00E30000U,
0x00E40000U,
0x00E50000U,
0x00E60000U,
0x00E70000U,
0x00E80000U,
0x00E90000U,
0x00EA0000U,
0x00EB0000U,
0x00EC0000U,
0x00ED0000U,
0x00EE0000U,
0x00EF0000U,
0x00F00000U,
0x00F10000U,
0x00F20000U,
0x00F30000U,
0x00F40000U,
0x00F50000U,
0x00F60000U,
0x00F70000U,
0x00F80000U,
0x00F90000U,
0x00FA0000U,
0x00FB0000U,
0x00FC0000U,
0x00FD0000U,
0x00FE0000U,
0x00FF0000U,
}
}
};
const Fls_ConfigType FlsConfigSet[] =
{
{
#if (USE_FLS_INFO==STD_ON)
.FlsInfo = flashInfo ,
#endif
.FlsAcErase = 0u,
.FlsAcWrite = 0u,
.FlsMaxReadFastMode = 0x100u,
.FlsMaxReadNormalMode = 0x100u,
.FlsMaxWriteFastMode = 0x100u,
.FlsMaxWriteNormalMode = 0x100u,
#if (FEE_POLLING_MODE == STD_OFF)
.FlsJobEndNotification = Fee_JobEndNotification,
.FlsJobErrorNotification= Fee_JobErrorNotification,
#else
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification= NULL,
#endif
.FlsProtection = 0u,
}
};
|
2301_81045437/classic-platform
|
boards/gnulinux/config/Fls_Cfg.c
|
C
|
unknown
| 8,412
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
/** @tagSettings DEFAULT_ARCHITECTURE=ZYNQ */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Fls Driver.
*/
#if !(((FLS_SW_MAJOR_VERSION == 2) && (FLS_SW_MINOR_VERSION == 0)) )
#error Fls: Configuration file expected BSW module version to be 2.0.*
#endif
#if !(((FLS_AR_RELEASE_MAJOR_VERSION == 4) && (FLS_AR_RELEASE_MINOR_VERSION == 1)) )
#error Fls: Configuration file expected AUTOSAR version to be 4.1.*
#endif
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
/** @req SWS_Fls_00308 */
#include "MemIf_Types.h"
#if defined(USE_FEE)
/** @req SWS_Fls_00262 */
/** @req SWS_Fls_00263 */
#include "Fee_Cbk.h"
#endif
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
#define FLASH_SECTOR_SIZE 0x10000u
#define FLASH_NUM_SECTORS 0x100u
#define FLASH_MAX_SECTORS (FLASH_NUM_SECTORS - 1)
#define FLASH_NUM_PAGES 0x10000u
#define FLASH_PAGE_SIZE 0x8u
#define FLS_TOTAL_SIZE (FLASH_NUM_PAGES * FLASH_PAGE_SIZE)
typedef struct {
/** @req SWS_Fls_00109 */
/** @req SWS_Fls_00110 */
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
#if (USE_FLS_INFO==STD_ON)
/** @req SWS_Fls_00355 */
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
uint32 FlsAcErase; /* NO SUPPORT */
uint32 FlsAcWrite; /* NO SUPPORT */
// FlsCallCycle N/A in core.
uint32 FlsMaxReadFastMode; /* NO SUPPORT */
uint32 FlsMaxReadNormalMode; /* NO SUPPORT */
uint32 FlsMaxWriteFastMode; /* NO SUPPORT */
uint32 FlsMaxWriteNormalMode; /* NO SUPPORT */
uint32 FlsProtection; /* NO SUPPORT */
} Fls_ConfigSetType;
/** @req SWS_Fls_00368 */
/** @req SWS_Fls_00353 */
/** @req SWS_Fls_00354 */
typedef Fls_ConfigSetType Fls_ConfigType;
typedef struct Flash {
uint32 FlsBaseAddress;
uint32 FlsTotalSize;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_NUM_SECTORS];
} FlashType;
extern const Fls_ConfigType FlsConfigSet[1];
#endif /*FLS_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/gnulinux/config/Fls_Cfg.h
|
C
|
unknown
| 4,167
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
typedef enum
{
IWDG_CK_Counter_Clock_4 = 0,
IWDG_CK_Counter_Clock_8,
IWDG_CK_Counter_Clock_16,
IWDG_CK_Counter_Clock_32,
IWDG_CK_Counter_Clock_64,
IWDG_CK_Counter_Clock_128,
IWDG_CK_Counter_Clock_256,
}Wdg_IWDG_TimerBaseType;
typedef struct
{
Wdg_IWDG_TimerBaseType TimerBase;
uint16 ReloadValue;
uint8 ActivationBit;
}Wdg_IWDG_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_IWDG_SettingsType WdgSettingsFast;
Wdg_IWDG_SettingsType WdgSettingsSlow;
Wdg_IWDG_SettingsType WdgSettingsOff;
}Wdg_IWDG_ModeConfigType;
typedef struct
{
const Wdg_GeneralType *Wdg_General;
const Wdg_IWDG_ModeConfigType *Wdg_IWDGModeConfig;
}Wdg_IWDG_ConfigType;
extern const Wdg_GeneralType WdgIWDGGeneral;
extern const Wdg_IWDG_ConfigType WdgIWDGConfig;
typedef enum
{
WDG_CK_Counter_Clock_1 = 0,
WDG_CK_Counter_Clock_2,
WDG_CK_Counter_Clock_4,
WDG_CK_Counter_Clock_8,
}Wdg_WWDG_TimerBaseType;
typedef struct
{
Wdg_WWDG_TimerBaseType TimerBase;
uint8 WindowValue;
uint8 CounterPreset;
uint8 ActivationBit;
}Wdg_WWDG_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_WWDG_SettingsType WdgSettingsFast;
Wdg_WWDG_SettingsType WdgSettingsSlow;
Wdg_WWDG_SettingsType WdgSettingsOff;
}Wdg_WWDG_ModeConfigType;
typedef struct
{
const Wdg_GeneralType *Wdg_General;
const Wdg_WWDG_ModeConfigType *Wdg_WWDGModeConfig;
}Wdg_WWDG_ConfigType;
typedef struct
{
const Wdg_IWDG_ConfigType *Wdg_IWDG_Config;
const Wdg_WWDG_ConfigType *Wdg_WWDG_Config;
}Wdg_ConfigType;
extern const Wdg_GeneralType WdgWWDGGeneral;
extern const Wdg_WWDG_ConfigType WdgWWDGConfig;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/gnulinux/config/Wdg_Cfg.h
|
C
|
unknown
| 2,697
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_IWDG_ModeConfigType WdgIWDGModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.TimerBase = IWDG_CK_Counter_Clock_8,
.ReloadValue = 0x7FF,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.TimerBase = IWDG_CK_Counter_Clock_256,
.ReloadValue = 0xFFF,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.TimerBase = IWDG_CK_Counter_Clock_4,
.ReloadValue = 0x7F,
.ActivationBit = 0,
},
};
const Wdg_GeneralType WdgIWDGGeneral =
{
.Wdg_Index = 1,
.Wdg_TriggerLocationPtr = Wdg_IWDG_Trigger,
.Wdg_SetModeLocationPtr = Wdg_IWDG_SetMode,
};
const Wdg_IWDG_ConfigType WdgIWDGConfig =
{
.Wdg_General = &WdgIWDGGeneral,
.Wdg_IWDGModeConfig = &WdgIWDGModeConfig,
};
/* The windowed watchdog is clocked from PCLK1. Max allowed frequency
* of this is 36Mhz.
*
* Max Twwdg = T_PCLK1 * 4096 * 2^TimerBase * (CounterPreset & 0x3F) + 1)=
*
* = 58.25 ms
*
*
*
* Min Twwdg = T_PCLK1 * 4096 * 2^TimerBase * (CounterPreset & 0x3F) + 1)=
*
* = 7.28 ms
* */
/* IMPROVEMENT: Add implementation for Independent WD as well. This will make it
* possible to test a multiple WD design within the STM32. */
const Wdg_WWDG_ModeConfigType WdgWWDGModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.TimerBase = WDG_CK_Counter_Clock_4,
.WindowValue = 0x7F,
.CounterPreset = 0x7F,
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.TimerBase = WDG_CK_Counter_Clock_8,
.WindowValue = 0x7F,
.CounterPreset = 0x7F,
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.TimerBase = WDG_CK_Counter_Clock_8,
.WindowValue = 0x7F,
.CounterPreset = 0x7F,
.ActivationBit = 0,
},
};
const Wdg_GeneralType WdgWWDGGeneral =
{
.Wdg_Index = 0,
.Wdg_TriggerLocationPtr = Wdg_WWDG_Trigger,
.Wdg_SetModeLocationPtr = Wdg_WWDG_SetMode,
};
const Wdg_WWDG_ConfigType WdgWWDGConfig =
{
.Wdg_General = &WdgWWDGGeneral,
.Wdg_WWDGModeConfig = &WdgWWDGModeConfig,
};
const Wdg_ConfigType WdgConfig =
{
&WdgIWDGConfig,
&WdgWWDGConfig,
};
|
2301_81045437/classic-platform
|
boards/gnulinux/config/Wdg_Lcfg.c
|
C
|
unknown
| 3,166
|
# ARCH defines
ARCH=armv7_m
ARCH_FAM=arm
ARCH_MCU=jacinto
#
# CFG (y/n) macros
#
CFG=ARM ARMV7_M ARM_CM3 THUMB
CFG+=JACINTO JAC5
# Add our board
CFG+=MCU_MMU
CFG+=BRD_JACINTO
def-y += HEAPSIZE=3000
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+= CAN DIO MCU PORT FLS SPI PWM GPT
# System + Communication + Diagnostic
MOD_AVAIL+=COMM NM CANNM CANSM
# Additional
MOD_AVAIL+=TCF LWIP TCPIP SLEEP
ifndef NOKERNEL
MOD_USE += MCU KERNEL
endif
# Defines
def-y += SRAM_SIZE=0x20000
ifndef NOKERNEL
def-y += L_BOOT_RESERVED_SPACE=0x20000
endif
# Default cross compiler
DEFAULT_CROSS_COMPILE = /opt/arm-none-eabi/bin/arm-none-eabi-
|
2301_81045437/classic-platform
|
boards/jacinto5/build_config.mk
|
Makefile
|
unknown
| 716
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/jacinto5/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD Spi_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 Spi_SEQ_CMD2
#define SPI_SEQ_EEP_READ Spi_SEQ_READ
#define SPI_SEQ_EEP_WRITE Spi_SEQ_WRITE
#define SPI_CH_EEP_CMD Spi_CH_CMD
#define SPI_CH_EEP_ADDR Spi_CH_ADDR
#define SPI_CH_EEP_WREN Spi_CH_WREN
#define SPI_CH_EEP_DATA Spi_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/jacinto5/config/Eep_Lcfg.c
|
C
|
unknown
| 3,925
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include <stdlib.h>
#if defined(CFG_JAC5)
const FlashType flashInfo[] = {
[0] = {
.sectCnt = 1,
.bankSize = 0x00100000,
.sectAddr[0] = FLS_BASE_ADDRESS,
.sectAddr[1] = 0xA0000000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/jacinto5/config/Fls_Cfg.c
|
C
|
unknown
| 1,415
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x8F300000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_JAC5)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 1
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/jacinto5/config/Fls_Cfg.h
|
C
|
unknown
| 3,309
|
# ARCH defines
ARCH=armv7_m
ARCH_FAM=arm
ARCH_MCU=jacinto
#
# CFG (y/n) macros
#
CFG=ARM ARMV7_M ARM_CM3 THUMB
CFG+=JACINTO JAC5E
# Add our board
CFG+=BRD_JACINTO
CFG+=MCU_MMU
CFG+=TIMER_SCTM
def-y += HEAPSIZE=3000
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+= CAN DIO PWM MCU PORT FLS NVM MEMIF FEE FLS GPT ADC SPI
# System + Communication + Diagnostic
MOD_AVAIL+=XCP CANIF CANTP J1939TP COM DCM DEM DET ECUM_FLEXIBLE ECUM_FIXED IOHWAB KERNEL PDUR IPDUM WDGM RTE BSWM WDGIF
MOD_AVAIL+=COMM NM CANNM CANSM
# Additional
MOD_AVAIL+=RAMLOG TCF LWIP TCPIP SLEEP RTE RAMTST
# CRC
MOD_AVAIL+=CRC CPL CAL
# Required modules
ifndef NOKERNEL
MOD_USE += MCU KERNEL
endif
# Defines
def-y += SRAM_SIZE=0x20000
ifndef NOKERNEL
def-y += L_BOOT_RESERVED_SPACE=0x20000
endif
# Default cross compiler
DEFAULT_CROSS_COMPILE = /opt/arm-none-eabi/bin/arm-none-eabi-
|
2301_81045437/classic-platform
|
boards/jacinto5e/build_config.mk
|
Makefile
|
unknown
| 945
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/jacinto5e/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD Spi_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 Spi_SEQ_CMD2
#define SPI_SEQ_EEP_READ Spi_SEQ_READ
#define SPI_SEQ_EEP_WRITE Spi_SEQ_WRITE
#define SPI_CH_EEP_CMD Spi_CH_CMD
#define SPI_CH_EEP_ADDR Spi_CH_ADDR
#define SPI_CH_EEP_WREN Spi_CH_WREN
#define SPI_CH_EEP_DATA Spi_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/jacinto5e/config/Eep_Lcfg.c
|
C
|
unknown
| 3,925
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include <stdlib.h>
#if defined(CFG_JAC5E)
const FlashType flashInfo[] = {
[0] = {
.sectCnt = 1,
.bankSize = 0x00100000,
.sectAddr[0] = FLS_BASE_ADDRESS,
.sectAddr[1] = 0xA0000000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/jacinto5e/config/Fls_Cfg.c
|
C
|
unknown
| 1,416
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x8F300000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_JAC5E)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 1
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/jacinto5e/config/Fls_Cfg.h
|
C
|
unknown
| 3,310
|
# ARCH defines
ARCH=armv7_m
ARCH_FAM=arm
ARCH_MCU=jacinto
#
# CFG (y/n) macros
#
#CFG=ARM ARMV7E_M ARM_CM4 THUMB
CFG=ARM ARMV7_M ARM_CM3 THUMB
CFG+=JACINTO JAC6
# Add our board
CFG+=BRD_JACINTO
CFG+=MCU_MMU
CFG+=TIMER
CFG+=TIMER_SCTM
def-y += L3_OFFSET=0x0
def-y += HEAPSIZE=5000
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+= CAN DIO MCU PORT FLS GPT ETH PWM SPI LIN
# System + Communication + Diagnostic
MOD_AVAIL+=XCP CANIF CANTP J1939TP COM DCM DEM DET ECUM_FLEXIBLE ECUM_FIXED IOHWAB KERNEL PDUR IPDUM WDGM RTE BSWM WDGIF
MOD_AVAIL+=COMM NM CANNM CANSM ETHSM UDPNM
# Additional
MOD_AVAIL+=RAMLOG TCF LWIP TCPIP SOAD DOIP SLEEP RTE RAMTST
# CRC
MOD_AVAIL+=CRC CPL CAL
# Required modules
ifndef NOKERNEL
MOD_USE += MCU KERNEL
endif
# Defines
def-y += SRAM_SIZE=0x20000
ifndef NOKERNEL
def-y += L_BOOT_RESERVED_SPACE=0x20000
endif
# Default cross compiler
DEFAULT_CROSS_COMPILE = /opt/arm-none-eabi/bin/arm-none-eabi-
|
2301_81045437/classic-platform
|
boards/jacinto6/build_config.mk
|
Makefile
|
unknown
| 1,028
|
# ARCH defines
ARCH=armv7_m
ARCH_FAM=arm
ARCH_MCU=jacinto
#
# CFG (y/n) macros
#
#CFG=ARM ARMV7E_M ARM_CM4 THUMB
CFG=ARM ARMV7_M ARM_CM3 THUMB
CFG+=JACINTO JAC6
# Add our board
CFG+=BRD_JAC6_VAYU_EVM
CFG+=MCU_MMU
CFG+=TIMER
CFG+=TIMER_SCTM
def-y += L3_OFFSET=0x20000000
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+= CAN DIO MCU PORT FLS GPT ETH PWM SPI LIN ADC I2C
# System + Communication + Diagnostic
MOD_AVAIL+=XCP CANIF CANTP J1939TP COM DCM DEM DET ECUM_FLEXIBLE ECUM_FIXED IOHWAB KERNEL PDUR IPDUM WDGM RTE BSWM WDGIF
MOD_AVAIL+=COMM NM CANNM CANSM ETHSM UDPNM
# Additional
MOD_AVAIL+=RAMLOG TCF LWIP TCPIP SOAD DOIP SLEEP RTE RAMTST
# CRC
MOD_AVAIL+=CRC CPL CAL
# Required modules
ifndef NOKERNEL
MOD_USE += MCU KERNEL
endif
# Defines
def-y += SRAM_SIZE=0x20000
ifndef NOKERNEL
def-y += L_BOOT_RESERVED_SPACE=0x20000
endif
# Default cross compiler
DEFAULT_CROSS_COMPILE = /opt/arm-none-eabi/bin/arm-none-eabi-
|
2301_81045437/classic-platform
|
boards/jacinto6_vayu_evm/build_config.mk
|
Makefile
|
unknown
| 1,022
|
MOD_USE+= I2C
obj-y += I2c_LCfg.o
obj-y += I2c.o
|
2301_81045437/classic-platform
|
boards/jacinto6_vayu_evm/config/I2c.mk
|
Makefile
|
unknown
| 54
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @tagSettings DEFAULT_ARCHITECTURE=JACINTO6 */
/** @reqSettings DEFAULT_SPECIFICATION_REVISION=4.1.2 */
#ifndef I2C_CFG_H_
#define I2C_CFG_H_
#include "Std_Types.h"
#define I2C_IRQ_PRIORITY 5uL
#define I2C_DEV_ERROR_DETECT STD_ON /* Generate from the generator */
#define I2C_VERSION_INFO_API STD_ON /* Generate from the generator */
#define I2C_USE_GPT STD_OFF
#define I2C_JOB_GPT_CHANNEL 0u /* assign from the generator */
#define I2C_MAIN_FUNCTION_PERIOD 10u /* Generate a non zero value and avoid divide by Zero, in msec */
#define I2C_TOTAL_CHANNEL_LENGTH 950u /* Generate sum of all channel length */
#define I2C_TOTAL_CHANNEL_QUEUE_SIZE 22u /* Generate sum of all channel queue size */
typedef uint8 EcucBooleanParamDef;
typedef float EcucFloatParamDef;
typedef uint32 EcucIntegerParamDef;
typedef void (*EcucFunctionNameDef) (Std_ReturnType result, uint16 requestHandle);
/* slave addresses */
#define I2C_ADDRESS_PCF8575 0x20
#define I2C_ADDRESS_PCF8575_1 0x21
#define I2C_ADDRESS_CHIP_X1 0x28
#define I2C_ADDRESS_CHIP_X2 0x38
#define I2C_ADDRESS_CHIP_X3 0x28
#define I2C_ADDRESS_CHIP_X4 0x28
/* Number of elements in each group */
#define I2C_CHANNEL_GROUP1_COUNT 2
#define I2C_CHANNEL_GROUP2_COUNT 1
#define I2C_CHANNEL_GROUP3_COUNT 1
#define I2C_CHANNEL_GROUP4_COUNT 1
#define I2C_CHANNEL_GROUP5_COUNT 1
#define I2C_SLAVE_GROUP1_COUNT 2
#define I2C_SLAVE_GROUP2_COUNT 1
#define I2C_SLAVE_GROUP3_COUNT 1
#define I2C_SLAVE_GROUP4_COUNT 1
#define I2C_SLAVE_GROUP5_COUNT 1
/* Max length of each channel data buffer */
#define I2C_CHANNEL1_MAX_LENGTH 100
#define I2C_CHANNEL2_MAX_LENGTH 200
#define I2C_CHANNEL3_MAX_LENGTH 300
#define I2C_CHANNEL4_MAX_LENGTH 200
#define I2C_CHANNEL5_MAX_LENGTH 150
/* Queue size of each channel */
#define I2C_CHANNEL1_QUEUE_SIZE 10
#define I2C_CHANNEL2_QUEUE_SIZE 5
#define I2C_CHANNEL3_QUEUE_SIZE 2
#define I2C_CHANNEL4_QUEUE_SIZE 3
#define I2C_CHANNEL5_QUEUE_SIZE 2
typedef enum
{
I2C_ADDR_SIZE_7BIT = 0,
I2C_ADDR_SIZE_10BIT,
I2C_ADDR_SIZE_COUNT,
I2C_ADDR_SIZE_WRONG
} EcucEnumerationParamDef;
/* Width of Destination Register in Bytes */
/* @req SWS_I2c_00005 */
enum
{
I2C_SIZE_8BIT = 0, /* Register size is 8 bit */
I2C_SIZE_16BIT, /* Register size is 16 bit */
I2C_SIZE_24BIT, /* Register size is 24 bit */
I2C_SIZE_32BIT, /* Register size is 32 bit */
I2C_SIZE_NONE, /* Ignore register argument, i.e. treat it as size 0 bits. */
I2C_SIZE_COUNT,
I2C_SIZE_WRONG
};
/* name of the individual I2C controller configured */
enum
{
I2C_CONTROLLER_0 = 0, /* I2C controller 0 */
I2C_CONTROLLER_1, /* I2C controller 1 */
I2C_CONTROLLER_2, /* I2C controller 2 */
I2C_CONTROLLER_3, /* I2C controller 3 */
I2C_CONTROLLER_COUNT, /* number of I2C controllers */
I2C_CONTROLLER_WRONG /* no controller selected or wrong calculated value */
};
/* module enable / disable enumeration */
enum
{
I2C_DISABLE = 0,
I2C_ENABLE
}I2cEnumerationModulEnable;
/* Channel Names configured */
enum
{
I2C_CH_NAME1 = 0,
I2C_CH_NAME2,
I2C_CH_NAME3,
I2C_CH_NAME4,
I2C_CH_NAME5,
I2C_CH_COUNT,
I2C_CH_WRONG
};
/* slave names configured */
enum
{
I2C_SLAVE_NAME1 = 0,
I2C_SLAVE_NAME2,
I2C_SLAVE_NAME3,
I2C_SLAVE_NAME4,
I2C_SLAVE_NAME5,
I2C_SLAVE_COUNT,
I2C_SLAVE_WRONG
};
/* Handle type for identifying an I2C Channel */
/* @req SWS_I2c_00004 */
typedef uint16 I2c_ChannelHandleType;
/* Width of Destination Address in Bytes */
/* @req SWS_I2c_00005 */
typedef uint8 I2c_AddressSizeType;
/* Communication settings of an external I2C Slave */
typedef struct
{
EcucIntegerParamDef I2cSlaveAddress; /* The slave's unique I2C address */
EcucEnumerationParamDef I2cSlaveAddressSize;
} I2c_SlaveType;
/* Logical I2C channel is defined as an interaction point between an user on
the AUTOSAR stack (master) and a functional entity located on a slave.
Subsequent request on the same channel need to be serialized, but
different channel requests are queued in the I2C Driver and will be handled
be handled in the order of channel priorities. */
typedef struct
{
EcucIntegerParamDef I2cChannelId; /* Identifier of the I2cChannel. Callers need to use this Id for issuing
commands to an I2C channel. */
EcucIntegerParamDef I2cChannelMaxLength; /* Maximum number of bytes to be transferred on this channel. */
EcucIntegerParamDef I2cChannelPriority; /* The priority of the I2C channel.
The value 0 is defined as the lowest priority of an I2C channel. Accordingly
bigger numbers define higher priorities. */
EcucIntegerParamDef I2cChannelQueueSize; /* specifies the maximum number of requests that can be buffered for the channel.*/
/* @req SWS_I2c_00012 */
EcucFunctionNameDef I2cJobEndNotification; /* Callback notification for the given I2cChannel. The callback will be
executed either in case the job finished normally or if there was an error. */
/* @req SWS_I2c_00032 */
const I2c_SlaveType* I2cSlaveRef; /* Reference to the I2cSlave this I2cChannel is communicating with. */
} I2c_ChannelType;
/* Configuration of the individual i2c controller */
typedef struct
{
EcucIntegerParamDef I2cBusSpeed; /* Bus speed in kbit/s
- Standard-mode (Sm): bit rate up to 100kbit/s - Fast-mode(Fm): bit rate up
to 400kbit/s - High-speed mode (Hs): bit rate up to 3.4 MBit/s */
EcucIntegerParamDef I2cControllerTimeout; /* Timeout in seconds. If a message could not be successfully transferred
within the timeout, an error will be reported to Dem. */
const I2c_ChannelType** I2cChannel; /* A logical I2C channel is defined as an interaction point
between an user on the AUTOSAR stack (master) and a
functional entity located on a slave. Subsequent request on the
same channel need to be serialized, but different channel
requests are queued in the I2C Driver and will be handled be
handled in the order of channel priorities. */
const I2c_SlaveType** I2cSlave; /* The communication settings of an external I2C Slave. */
} I2c_ControllerType;
/* I2cConfigSet contains the global configuration parameters and sub containers of the I2c module */
typedef struct
{
const I2c_ControllerType* I2cController; /* Configuration of the individual controller */
} I2c_ConfigSetType;
/* I2cGeneral contains the general configuration parameters of the I2c module. */
typedef struct
{
EcucBooleanParamDef I2cDevErrorDetect; /* Switches the Default Error Tracer (Det)
detection and notification ON or OFF.
true: enabled (ON).
false: disabled (OFF). */
EcucFloatParamDef I2cMainFunctionPeriod; /* Specifies the period of main function I2c_MainFunction in seconds.
I2C driver does not require this information but the BSW scheduler. */
EcucBooleanParamDef I2cVersionInfoApi; /* Pre-processor switch for enabling version info API support. */
} I2c_GeneralType;
/* Configuration of the I2c (I2C Driver) module. */
typedef struct
{
const I2c_ConfigSetType* I2cConfigSet; /* This container contains the global configuration parameters
and sub containers of the I2c module. */
const I2c_GeneralType* I2cGeneral; /* Contains the general configuration parameters of the I2c module. */
} I2c_I2cType;
/* implementationSpecific */
typedef struct
{
uint8 enable; /* I2C_ENABLE: module in use; I2C_DISABLE: module not used*/
uint8 I2cChannelCount; /* number of channels */
uint8 I2cSlaveCount; /* number of slaves */
} I2c_ModuleType;
/* The type of the external data structure containing the initialization data for the I2c driver. */
/* @req SWS_I2c_00003 */
typedef struct
{
/* implementationSpecific */
const I2c_ModuleType *module;
} I2c_ConfigType;
/* publication of the I2C container */
extern const I2c_ConfigType I2c_config;
extern const I2c_ConfigSetType I2cConfigSet;
#endif /*I2C_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/jacinto6_vayu_evm/config/I2c_Cfg.h
|
C
|
unknown
| 9,946
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "I2c.h"
/* Configuration of the I2C hardware */
static const I2c_ModuleType ModuleList[I2C_CONTROLLER_COUNT] = {
{
.enable = (uint8)I2C_ENABLE,
.I2cChannelCount = I2C_CHANNEL_GROUP1_COUNT,
.I2cSlaveCount = I2C_SLAVE_GROUP1_COUNT
},
{
.enable = (uint8)I2C_ENABLE,
.I2cChannelCount = I2C_CHANNEL_GROUP2_COUNT,
.I2cSlaveCount = I2C_SLAVE_GROUP2_COUNT
},
{
.enable = (uint8)I2C_DISABLE,
.I2cChannelCount = I2C_CHANNEL_GROUP3_COUNT,
.I2cSlaveCount = I2C_SLAVE_GROUP3_COUNT
},
{
.enable = (uint8)I2C_DISABLE,
.I2cChannelCount = I2C_CHANNEL_GROUP4_COUNT,
.I2cSlaveCount = I2C_SLAVE_GROUP4_COUNT
}
};
const I2c_ConfigType I2c_config =
{
.module = ModuleList
};
/* I2cGeneral contains the general configuration parameters of the I2c module. */
static const I2c_GeneralType I2cGeneral =
{
.I2cDevErrorDetect = TRUE,
.I2cMainFunctionPeriod = 0.01f,
.I2cVersionInfoApi = TRUE
};
/* The communication settings of an external I2C Slave. */
static const I2c_SlaveType I2cSlave[I2C_SLAVE_COUNT] =
{
{ /* I2C_SLAVE_NAME1 */
.I2cSlaveAddress = I2C_ADDRESS_PCF8575,
.I2cSlaveAddressSize = I2C_ADDR_SIZE_7BIT
},
{ /* I2C_SLAVE_NAME2 */
.I2cSlaveAddress = I2C_ADDRESS_CHIP_X1,
.I2cSlaveAddressSize = I2C_ADDR_SIZE_10BIT
},
{ /* I2C_SLAVE_NAME3 */
.I2cSlaveAddress = I2C_ADDRESS_CHIP_X2,
.I2cSlaveAddressSize = I2C_ADDR_SIZE_7BIT
},
{ /* I2C_SLAVE_NAME4 */
.I2cSlaveAddress = I2C_ADDRESS_PCF8575_1,
.I2cSlaveAddressSize = I2C_ADDR_SIZE_7BIT
},
{ /* I2C_SLAVE_NAME5 */
.I2cSlaveAddress = I2C_ADDRESS_CHIP_X3,
.I2cSlaveAddressSize = I2C_ADDR_SIZE_7BIT
}
};
/* A logical I2C channel is defined as an interaction point between an user on
the AUTOSAR stack (master) and a functional entity located on a slave.
Subsequent request on the same channel need to be serialized, but
different channel requests are queued in the I2C Driver and will be handled
be handled in the order of channel priorities. */
static const I2c_ChannelType I2cChannel[I2C_CH_COUNT] =
{
{
.I2cChannelId = I2C_CH_NAME1,
.I2cChannelMaxLength = I2C_CHANNEL1_MAX_LENGTH,
.I2cChannelPriority = 5,
.I2cChannelQueueSize = I2C_CHANNEL1_QUEUE_SIZE,
.I2cJobEndNotification = NULL,
.I2cSlaveRef = &I2cSlave[I2C_SLAVE_NAME1]
},
{
.I2cChannelId = I2C_CH_NAME2,
.I2cChannelMaxLength = I2C_CHANNEL2_MAX_LENGTH,
.I2cChannelPriority = 1,
.I2cChannelQueueSize = I2C_CHANNEL2_QUEUE_SIZE,
.I2cJobEndNotification = NULL,
.I2cSlaveRef = &I2cSlave[I2C_SLAVE_NAME2]
},
{
.I2cChannelId = I2C_CH_NAME3,
.I2cChannelMaxLength = I2C_CHANNEL3_MAX_LENGTH,
.I2cChannelPriority = 4,
.I2cChannelQueueSize = I2C_CHANNEL3_QUEUE_SIZE,
.I2cJobEndNotification = NULL,
.I2cSlaveRef = &I2cSlave[I2C_SLAVE_NAME3]
},
{
.I2cChannelId = I2C_CH_NAME4,
.I2cChannelMaxLength = I2C_CHANNEL4_MAX_LENGTH,
.I2cChannelPriority = 2,
.I2cChannelQueueSize = I2C_CHANNEL4_QUEUE_SIZE,
.I2cJobEndNotification = NULL,
.I2cSlaveRef = &I2cSlave[I2C_SLAVE_NAME4]
},
{
.I2cChannelId = I2C_CH_NAME5,
.I2cChannelMaxLength = I2C_CHANNEL5_MAX_LENGTH,
.I2cChannelPriority = 0,
.I2cChannelQueueSize = I2C_CHANNEL5_QUEUE_SIZE,
.I2cJobEndNotification = NULL,
.I2cSlaveRef = &I2cSlave[I2C_SLAVE_NAME5]
}
};
/* channel groups, needed for the controller */
static const I2c_ChannelType* I2c_channelGroup1[I2C_CHANNEL_GROUP1_COUNT] =
{
&I2cChannel[I2C_CH_NAME1],
&I2cChannel[I2C_CH_NAME2]
};
static const I2c_ChannelType* I2c_channelGroup2[I2C_CHANNEL_GROUP2_COUNT] =
{
&I2cChannel[I2C_CH_NAME3]
};
static const I2c_ChannelType* I2c_channelGroup3[I2C_CHANNEL_GROUP3_COUNT] =
{
&I2cChannel[I2C_CH_NAME4]
};
static const I2c_ChannelType* I2c_channelGroup4[I2C_CHANNEL_GROUP4_COUNT] =
{
&I2cChannel[I2C_CH_NAME5]
};
/* slave groups, needed for the controller */
static const I2c_SlaveType* I2c_SlaveGroup1[I2C_SLAVE_GROUP1_COUNT] =
{
&I2cSlave[I2C_SLAVE_NAME1],
&I2cSlave[I2C_SLAVE_NAME2]
};
static const I2c_SlaveType* I2c_SlaveGroup2[I2C_SLAVE_GROUP2_COUNT] =
{
&I2cSlave[I2C_SLAVE_NAME3]
};
static const I2c_SlaveType* I2c_SlaveGroup3[I2C_SLAVE_GROUP3_COUNT] =
{
&I2cSlave[I2C_SLAVE_NAME4]
};
static const I2c_SlaveType* I2c_SlaveGroup4[I2C_SLAVE_GROUP4_COUNT] =
{
&I2cSlave[I2C_SLAVE_NAME5]
};
/* Configuration of the I2C controllers. */
static const I2c_ControllerType I2cController[I2C_CONTROLLER_COUNT] =
{
{
.I2cBusSpeed = 400u,
.I2cControllerTimeout = 10000,
.I2cChannel = I2c_channelGroup1,
.I2cSlave = I2c_SlaveGroup1
},
{
.I2cBusSpeed = 400u,
.I2cControllerTimeout = 1000,
.I2cChannel = I2c_channelGroup2,
.I2cSlave = I2c_SlaveGroup2
},
{
.I2cBusSpeed = 100u,
.I2cControllerTimeout = 100,
.I2cChannel = I2c_channelGroup3,
.I2cSlave = I2c_SlaveGroup3
},
{
.I2cBusSpeed = 100u,
.I2cControllerTimeout = 2200,
.I2cChannel = I2c_channelGroup4,
.I2cSlave = I2c_SlaveGroup4
}
};
/* This container contains the global configuration parameters and sub containers of the I2c module.*/
const I2c_ConfigSetType I2cConfigSet =
{
.I2cController = I2cController
};
/* Configuration of the I2c (I2C Driver) module. */
const I2c_I2cType I2c =
{
.I2cConfigSet = &I2cConfigSet,
.I2cGeneral = &I2cGeneral
};
|
2301_81045437/classic-platform
|
boards/jacinto6_vayu_evm/config/I2c_LCfg.c
|
C
|
unknown
| 6,720
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef OS_H_
#define OS_H_
#include "Std_Types.h"
typedef uint8 StatusType;
typedef sint16 ISRType;
typedef sint32 ApplicationType;
typedef sint32 AppModeType;
typedef uint16 TaskType;
typedef TaskType* TaskRefType;
typedef uint64_t EventMaskType;
typedef uint32 TickType;
typedef TickType *TickRefType;
static inline void DisableAllInterrupts( void ) {
}
static inline void EnableAllInterrupts( void ) {
}
static inline void SuspendAllInterrupts( void ) {
}
static inline void ResumeAllInterrupts( void ) {
}
static inline void SuspendOSInterrupts( void ) {
}
static inline void ResumeOSInterrupts( void ) {
}
#endif /*OS_H_*/
|
2301_81045437/classic-platform
|
boards/linux/Os.h
|
C
|
unknown
| 1,452
|
# ARCH defines
ARCH=linux
ARCH_FAM=generic
# CFG (y/n) macros
CFG+=BRD_LINUX
CFG+=SYSTEM_ASSERT
# What buildable modules does this board have,
# default or private
MOD_AVAIL+=XCP COM PDUR IPDUM WDGM WDGIF DET DCM DEM CANTP J1939TP CANIF RTE FEE NVM ECUM_FIXED ECUM_FLEXIBLE MCU EA KERNEL RAMLOG IOHWAB RTE E2E BSWM MEMIF DLT FRIF TCPIP LWIP
# Network management
MOD_AVAIL+=COMM NM CANNM CANSM NMHB UDPNM
# Additional
MOD_AVAIL+=CRC CPL CAL
MOD_AVAIL+=LIN
MOD_AVAIL+=LINSM
MOD_AVAIL+=LINIF
MOD_AVAIL+=RAMTST
MOD_AVAIL+=CANTRCV
MOD_AVAIL+=CDDPDUR
MOD_AVAIL+=ETHSM
MOD_AVAIL+=FRSM
MOD_AVAIL+=FRNM
MOD_AVAIL+=FRTP
MOD_AVAIL+=ETHIF
MOD_AVAIL+=ETHTSYN
MOD_AVAIL+=LDCOM
MOD_AVAIL+=STBM
# Required modules
#MOD_USE +=
# Needed by us
MOD_USE=
SELECT_CLIB=CLIB_NATIVE
|
2301_81045437/classic-platform
|
boards/linux/build_config.mk
|
Makefile
|
unknown
| 803
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/**
* @file os_trap.h
* @brief Internal trap interface for the OS used for OS_SC3 and OS_SC4.
* The intended use is to give supervisor access to the configured APIs
*
* @addtogroup os
* @details
* @{
*/
/* ----------------------------[includes]------------------------------------*/
/* ----------------------------[private macro]-------------------------------*/
/* ----------------------------[private typedef]-----------------------------*/
/* ----------------------------[private function prototypes]-----------------*/
/* ----------------------------[private variables]---------------------------*/
/* ----------------------------[private functions]---------------------------*/
/* ----------------------------[public functions]----------------------------*/
/** @} */
|
2301_81045437/classic-platform
|
boards/linux/os_trap.h
|
C
|
unknown
| 1,582
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC5516IT TIMER_TB
CFG+=MCU_ARC_CONFIG MCU_MMU MCU_ARC_LP
CFG+=CREATE_SREC
CFG+=VLE
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI
# Extra
MOD_AVAIL+=FLS_SST25XX
# Required modules
MOD_USE += MCU KERNEL
COMPILER?=gcc
COMPILER_FLAVOR=s32_newlib
# Default cross compiler
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
diab-$(vle)=-tPPCE200Z1VFN:simple
diab-$(novle)=-tPPCE200Z1NFS:simple
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc5516
# Defines
def-y += SRAM_SIZE=0x14000
def-y += L_BOOT_RESERVED_SPACE=0x10000
|
2301_81045437/classic-platform
|
boards/mpc5516it/build_config.mk
|
Makefile
|
unknown
| 979
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Dma.h"
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR0_RFDF0
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR0_CFFF0
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR1_RFDF0
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_EQADC_FISR1_CFFF0
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_A_SR_TFFF
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_A_SR_RFRD
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_B_SR_TFFF
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_B_SR_RFRD
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
}
};
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)
DmaMuxConfig,
#endif
DmaChannelConfig,
DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Dma_Cfg.c
|
C
|
unknown
| 2,949
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
typedef enum
{
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_ADC_GROUP0_COMMAND_CHANNEL,
DMA_ADC_GROUP1_RESULT_CHANNEL,
DMA_ADC_GROUP1_COMMAND_CHANNEL,
DMA_DSPI_A_COMMAND_CHANNEL,
DMA_DSPI_A_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
/*DMA_CHANNEL8,
DMA_CHANNEL9,
DMA_CHANNEL10,
DMA_CHANNEL11,
DMA_CHANNEL12,
DMA_CHANNEL13,
DMA_CHANNEL14,
DMA_CHANNEL15,*/
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_ADC_GROUP0_RESULT_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Dma_Cfg.h
|
C
|
unknown
| 1,368
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#if defined(USE_SPI)
#include "Spi.h"
#endif
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Eep_Cfg.h
|
C
|
unknown
| 4,186
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Eep_Lcfg.c
|
C
|
unknown
| 4,051
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5516)
/* RWW between partitions*
*
* LOW 8*16KB + 2*64KB = 256KB
* MID 2*128KB = 256KB
* HIGH 4*128KB = 512KB
*/
const FlashType flashInfo[] = {
[0].sectCnt = 16,
[0].bankSize = 0x100000,
[0].regBase = 0xffff8000UL,
/* LOW */
[0].sectAddr[0] = 0,
[0].addrSpace[0] = ADDR_SPACE(0, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[1] = 0x00004000,
[0].addrSpace[1] = ADDR_SPACE(1, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[2] = 0x00008000,
[0].addrSpace[2] = ADDR_SPACE(2, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[3] = 0x0000c000,
[0].addrSpace[3] = ADDR_SPACE(3, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[4] = 0x00010000,
[0].addrSpace[4] = ADDR_SPACE(4, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[5] = 0x00014000,
[0].addrSpace[5] = ADDR_SPACE(5, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[6] = 0x00018000,
[0].addrSpace[6] = ADDR_SPACE(6, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[7] = 0x0001c000,
[0].addrSpace[7] = ADDR_SPACE(7, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[8] = 0x00020000,
[0].addrSpace[8] = ADDR_SPACE(8, ADDR_SPACE_LOW, 3 ),
[0].sectAddr[9] = 0x00030000,
[0].addrSpace[9] = ADDR_SPACE(9, ADDR_SPACE_LOW, 3 ),
/* MID */
[0].sectAddr[10] = 0x00040000,
[0].addrSpace[10] = ADDR_SPACE(0, ADDR_SPACE_MID, 4 ),
[0].sectAddr[11] = 0x00060000,
[0].addrSpace[11] = ADDR_SPACE(1, ADDR_SPACE_MID, 4 ),
/* HIGH */
[0].sectAddr[12] = 0x00080000,
[0].addrSpace[12] = ADDR_SPACE(0, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[13] = 0x000a0000,
[0].addrSpace[13] = ADDR_SPACE(1, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[14] = 0x000c0000,
[0].addrSpace[14] = ADDR_SPACE(2, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[15] = 0x000e0000,
[0].addrSpace[15] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[16] = 0x00100000, /* End, NOT a sector */
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Fls_Cfg.c
|
C
|
unknown
| 3,465
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_ON
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5516)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 16
#define FLS_TOTAL_SIZE (1*1024*1024)
#else
#error CPU not supported
#endif
#include "Fls_ConfigTypes.h"
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Fls_Cfg.h
|
C
|
unknown
| 2,481
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#define FLS_INCLUDE_FILE "Fls_SST25xx.h"
#include "Fls.h"
#include <stdlib.h>
#define KB *1024
const Fls_SectorType fls_SST25xx_SectorList[] = {
{
.FlsSectorStartaddress = (Fls_AddressType)0x00000000,
.FlsPageSize = (Fls_LengthType)1,
.FlsSectorSize = (Fls_LengthType)(4 KB),
.FlsNumberOfSectors = (uint32)512,
},
};
const Fls_ConfigType FlsSST25xxConfigSet[]=
{
{
.FlsMaxReadFastMode = 64,
.FlsMaxReadNormalMode = 1,
.FlsMaxWriteFastMode = 1,
.FlsMaxWriteNormalMode = 1,
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsSectorList = &fls_SST25xx_SectorList[0],
.FlsSectorListSize = sizeof(fls_SST25xx_SectorList)/sizeof(Fls_SectorType),
}
};
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Fls_SST25xx_Cfg.c
|
C
|
unknown
| 1,551
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef FLS_SST25XX_CFG_H_
#define FLS_SST25XX_CFG_H_
// Take in the original types
#include "Fls_Cfg.h"
extern const Fls_ConfigType FlsSST25xxConfigSet[];
/*
* Fls General container
*/
// The flash driver shall load the flash access code to RAM whenever an
// erase or write job is started and unload (overwrite) it after that job has
// been finished or canceled. true: Flash access code loaded on job start /
// unloaded on job end or error. false: Flash access code not loaded to /
// unloaded from RAM at all.
#define FLS_SST25XX_AC_LOAD_ON_JOB_START STD_OFF
// The flash memory start address (see also FLS118).
// FLS169: This parameter defines the lower boundary for read / write /
// erase and compare jobs.
#define FLS_SST25XX_BASE_ADDRESS 0x00000000
// Compile switch to enable and disable the Fls_Cancel function. true: API
// supported / function provided. false: API not supported / function not pro-
// vided
#define FLS_SST25XX_CANCEL_API STD_OFF
// Compile switch to enable and disable the Fls_Compare function. true: API
// supported / function provided. false: API not supported / function not pro-
// vided
#define FLS_SST25XX_COMPARE_API STD_ON
// Pre-processor switch for enabling the development error detection and
// reporting (see FLS077).
#define FLS_SST25XX_DEV_ERROR_DETECT STD_ON
// Index of the driver, used by FEE.
#define FLS_SST25XX_DRIVER_INDEX 100
// Compile switch to enable and disable the Fls_GetJobResult function. true:
// API supported / function provided. false: API not supported / function not
// provided
#define FLS_SST25XX_GET_JOB_RESULT_API STD_OFF
// Compile switch to enable and disable the Fls_GetStatus function. true: API
// supported / function provided. false: API not supported / function not pro-
// vided
#define FLS_SST25XX_GET_STATUS_API STD_ON
// Compile switch to enable and disable the Fls_SetMode function. true: API
// supported / function provided. false: API not supported / function not pro-
// vided
#define FLS_SST25XX_SET_MODE_API STD_ON
// The total amount of flash memory in bytes (see also FLS118).
// FLS170: This parameter in conjunction with FLS_SST25XX_BASE_ADDRESS
// defines the upper boundary for read / write / erase and compare jobs
#define FLS_SST25XX_TOTAL_SIZE 0x200000 // 16Mbit->2Mb, 0x0000_0000 to 0x0020_0000
#if 0
#define FLS_SST25XX_READ_PAGE_SIZE 0x8 // Read page size of 128 bits (4 words) (8 bytes)
#endif
// Job processing triggered by hardware interrupt.
// true: Job processing triggered by interrupt (hardware controlled).
// false: Job processing not triggered by interrupt (software controlled)
// NOT supported by Freescale hardware
#define FLS_SST25XX_USE_INTERRUPTS STD_OFF
#define FLS_SST25XX_VERSION_INFO_API STD_ON
#endif /* FLS_SST25XX_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Fls_SST25xx_Cfg.h
|
C
|
unknown
| 3,650
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Std_Types.h"
#include "Mcu.h"
#include "Mcu_Arc.h"
#include "asm_ppc.h"
#include "mm.h"
#include "mpc55xx.h"
#include "io.h"
#include "isr.h"
#include "EcuM.h"
#if defined(USE_DMA)
#include "Dma.h"
#endif
#include "arc_assert.h"
#if defined(CFG_MCU_ARC_DEBUG)
#include "Ramlog.h"
#define LOG_HEX1(_str,_arg1) \
ramlog_str(_str);ramlog_hex(_arg1);ramlog_str("\n")
#define LOG_HEX2(_str,_arg1,_str2,_arg2) \
ramlog_str(_str);ramlog_hex(_arg1);ramlog_str(_str2);ramlog_hex(_arg2);ramlog_str("\n")
#define LOG_STR(_str) ramlog_str(_str)
#else
#define LOG_HEX1(_str,_arg1)
#define LOG_HEX2(_str,_arg1,_str2,_arg2)
#define LOG_STR(_str)
#endif
#if defined(CFG_VLE)
#define ADJUST_VECTOR 1
#else
#define ADJUST_VECTOR 0
#endif
struct TlbEntry TlbTable[] = {
// TLB Entry 0 = 1M Internal flash
{
0,
(0x10000000 + (0<<16)),
(0xC0000000 + MAS1_TSIZE_4M),
(CFG_FLASH_START + VLE_MAS2_VAL),
(CFG_FLASH_START + MAS3_FULL_ACCESS),
},
// TLB Entry 1 = Peripheral bridge and BAM
{
1,
(0x10000000 + (1<<16)),
(0xC0000000 + MAS1_TSIZE_1M),
(CFG_PERIPHERAL_START + VLE_MAS2_VAL + MAS2_I),
(CFG_PERIPHERAL_START + MAS3_FULL_ACCESS),
},
// TLB Entry 2 = External RAM.
{
2,
(0x10000000 + (2<<16)),
(0xC0000000 + MAS1_TSIZE_4M),
(CFG_EXT_FLASH_START + VLE_MAS2_VAL),
(CFG_EXT_FLASH_START + MAS3_FULL_ACCESS),
},
// TLB Entry 3 = Internal SRAM
{
3,
(0x10000000+(3<<16)),
(0xC0000000 + MAS1_TSIZE_256K),
(CFG_SRAM_START + VLE_MAS2_VAL + MAS2_I),
(CFG_SRAM_START + MAS3_FULL_ACCESS),
},
{
UINT32_MAX
}
};
/*
* Configuration only support:
* - Flash recovery only
* - RECPTR is used to hold stack pointer when getting back from sleep
*
*
*/
struct Mcu_Arc_SleepPrivData sleepPrivData;
const Mcu_Arc_SleepConfigType Mcu_Arc_SleepConfig = {
/* Run all */
.hlt0_run = 0x0UL,
/* Halt all but reserved bits */
.hlt0_sleep = 0x3fffffffUL,
/* Goto sleep, enable all RAM
* 0x1-8k, 0x2-16k, 0x3-32k, 0x6-64k, 0x7-80K */
.crp_pscr = PSCR_SLEEP | PSCR_SLP12EN | PCSR_RAMSEL(7),
/* Point to recovery routine. If VLE is used this must be indicated */
.z1vec = ((uint32)&Mcu_Arc_LowPowerRecoverFlash ),
/* Not using Z0 so keep in reset */
.z0vec = 2,
.sleepSysClk = 0, /* 0 - 16Mhz IRC , 1 - XOSC , 2 - PLL */
.sleepFlags = 0,
.pData = &sleepPrivData,
};
const struct Mcu_Arc_Config Mcu_Arc_ConfigData = {
.sleepConfig = &Mcu_Arc_SleepConfig,
.tblTable = TlbTable,
};
/**
* @param sleepCfg
*/
void Mcu_Arc_SetModePre2( Mcu_ModeType mcuMode, const struct Mcu_Arc_SleepConfig *sleepCfg ) {
uint32_t timeout = 0;
if( mcuMode == McuConf_McuModeSettingConf_NORMAL ) {
mcuMode = McuConf_McuModeSettingConf_RUN;
}
if( McuConf_McuModeSettingConf_RUN == mcuMode ) {
SIU.HLT.R = sleepCfg->hlt0_run;
} else if( McuConf_McuModeSettingConf_SLEEP == mcuMode ) {
#if defined(USE_DMA)
Dma_DeInit();
#endif
LOG_HEX1("CRP Sleep clock select: ", sleepCfg->sleepSysClk);
/* Set system clock to 16Mhz IRC */
SIU.SYSCLK.B.SYSCLKSEL = sleepCfg->sleepSysClk;
if( sleepCfg->sleepFlags & SLEEP_FLG_POWERDOWN_FLASH ) {
/* Set MCR[STOP] (should work if FASTREC if OFF */
SET32( 0xffff8000UL + 0, (1<<(31-25)) );
}
Irq_Disable();
/* Clear FLAGS first */
LOG_STR("CRP: Clearing wakeup flags\n");
SET32(CRP_PSCR, 0xc7ff0000UL );
SET32(CRP_RTCSC, (1<<(31-2)) ); /* Clear RTCF */
/* Write Sleep config */
WRITE32(CRP_PSCR, sleepCfg->crp_pscr);
LOG_HEX1("CRP: Z1VEC: ", sleepCfg->z1vec );
WRITE32(CRP_Z1VEC, sleepCfg->z1vec | ADJUST_VECTOR);
LOG_HEX1("CRP: Z0VEC: ", sleepCfg->z0vec );
WRITE32(CRP_Z0VEC, sleepCfg->z0vec | ADJUST_VECTOR);
ASSERT( sleepCfg->pData != NULL );
LOG_HEX1("HLT: ", sleepCfg->hlt0_sleep );
sleepCfg->pData->hlt0 = SIU.HLT.R;
sleepCfg->pData->swt_cr = MCM.SWTCR.R;
SIU.HLT.R = sleepCfg->hlt0_sleep;
while((SIU.HLTACK.R != sleepCfg->hlt0_sleep) && (timeout++<HLT_TIMEOUT)) {}
Mcu_Arc_EnterLowPower(mcuMode);
/* back from sleep */
/* Setup exceptions and INTC again */
Os_IsrInit();
/* Restore watchdog */
MCM.SWTCR.R = sleepCfg->pData->swt_cr;
#if defined(USE_ECUM_FIXED) || defined(USE_ECUM_FLEXIBLE)
EcuM_CheckWakeup( 0x3fffffffUL );
#endif
/* Clear sleep flags to allow pads to operate */
CRP.PSCR.B.SLEEPF = 0x1;
}
}
/**
* @param sleepCfg
*/
void Mcu_Arc_SetModePost2( Mcu_ModeType mcuMode, const struct Mcu_Arc_SleepConfig *sleepCfg ) {
if( mcuMode == McuConf_McuModeSettingConf_NORMAL ) {
mcuMode = McuConf_McuModeSettingConf_RUN;
}
if( McuConf_McuModeSettingConf_RUN == mcuMode ) {
} else if( McuConf_McuModeSettingConf_SLEEP == mcuMode ) {
}
}
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Mcu_Arc_Cfg.c
|
C
|
unknown
| 6,174
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef MCU_ARC_CFG_H_
#define MCU_ARC_CFG_H_
#define CFG_SRAM_START 0x40000000
#define CFG_FLASH_START 0x00000000
#define CFG_PERIPHERAL_START 0xfff00000
#define CFG_EXT_FLASH_START 0x20000000
/* Maximum time to wait before timout of HLT */
#define HLT_TIMEOUT 3000
#if !defined(_ASSEMBLER_)
#include "mm.h"
/* Set MCR[STOP] Flash block
* (this assumes that you are running from RAM (NOT SUPPORTED */
#define SLEEP_FLG_POWERDOWN_FLASH (1<<0)
struct Mcu_Arc_SleepPrivData {
uint32_t hlt0;
uint32_t swt_cr;
};
typedef struct Mcu_Arc_SleepConfig {
/* HLT bits to set when in entering RUN state */
uint32_t hlt0_run;
/* HLT bits to set when in entering SLEEP state */
uint32_t hlt0_sleep;
uint32_t crp_pscr;
uint32_t crp_recptr;
uint32_t z0vec;
uint32_t z1vec;
/* Register value of SIU.SYSCLK.B.SYSCLKSEL */
uint32_t sleepSysClk;
uint32_t sleepFlags;
struct Mcu_Arc_SleepPrivData *pData;
} Mcu_Arc_SleepConfigType;
typedef struct Mcu_Arc_Config {
const struct Mcu_Arc_SleepConfig *sleepConfig;
const struct TlbEntry *tblTable;
} Mcu_Arc_ConfigType;
extern const struct Mcu_Arc_Config Mcu_Arc_ConfigData;
#endif
#endif /* MCU_ARC_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Mcu_Arc_Cfg.h
|
C
|
unknown
| 2,054
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef SPI_CFG_H
#define SPI_CFG_H
#include "Dma.h"
#include "mpc55xx.h"
#include "Mcu.h"
/*
* General configuration
*/
// Switches the Spi_Cancel function ON or OFF.
#define SPI_CANCEL_API STD_ON
// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.
// LEVEL 0 - Only Internal buffers
// LEVEL 1 - Only external buffers
// LEVEL 2 - Both internal/external buffers
#define SPI_CHANNEL_BUFFERS_ALLOWED 1
#define SPI_DEV_ERROR_DETECT STD_ON
// Switches the Spi_GetHWUnitStatus function ON or OFF.
#define SPI_HW_STATUS_API STD_ON
// Switches the Interruptible Sequences handling functionality ON or OFF.
#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF
// LEVEL 0 - Simple sync
// LEVEL 1 - Basic async
// LEVEL 2 - Enhanced mode
#define SPI_LEVEL_DELIVERED 2
#define SPI_VERSION_INFO_API STD_ON
#if 0
#if SPI_LEVEL_DELIVERED>=1
#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON
#endif
#endif
// External devices
typedef enum {
SPI_device_1,
} Spi_ExternalDeviceTypeType;
// Channels
#define SPI_CH_WREN 0
#define SPI_CH_CMD 1
#define SPI_CH_DATA 2
#define SPI_CH_ADDR 3
// Jobs
#define SPI_JOB_CMD2 0
#define SPI_JOB_DATA 1
#define SPI_JOB_CMD 2
#define SPI_JOB_WREN 3
// Sequences
#define SPI_SEQ_CMD 0
#define SPI_SEQ_WRITE 1
#define SPI_SEQ_READ 2
#define SPI_SEQ_CMD2 3
#define SPI_MAX_JOB 4
#define SPI_MAX_CHANNEL 4
#define SPI_MAX_SEQUENCE 4
#define SPI_USE_HW_UNIT_0 STD_ON
#define SPI_USE_HW_UNIT_1 STD_OFF
#define SPI_USE_HW_UNIT_2 STD_OFF
#define SPI_USE_HW_UNIT_3 STD_OFF
#endif /*SPI_CFG_H*/
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Spi_Cfg.h
|
C
|
unknown
| 2,426
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Spi.h"
#include "Spi_Cfg.h"
#include <stdlib.h>
// SPI_0
//#define SPI_0_CS 1 /* Using PCSB1 */
#define SPI_0_CS 2 /* Using PCSB2 */
#define SPI_SEQ_END_NOTIFICATION NULL
#define SPI_JOB_END_NOTIFICAITON NULL
// Notifications
// Seq
#define SPI_SEQ_CMD_END_NOTIFICATION NULL
#define SPI_SEQ_WRITE_END_NOTIFICATION NULL
#define SPI_SEQ_READ_END_NOTIFICATION NULL
#define SPI_SEQ_CMD2_END_NOTIFICATION NULL
// Jobs
#define SPI_JOB_CMD2_END_NOTIFICATION NULL
#define SPI_JOB_DATA_END_NOTIFICATION NULL
#define SPI_JOB_CMD_END_NOTIFICATION NULL
#define SPI_JOB_WREN_END_NOTIFICATION NULL
/*************** Sequences **************/
const Spi_SequenceConfigType SpiSequenceConfigData[] =
{
{
.SpiSequenceId = SPI_SEQ_CMD,
.SpiInterruptibleSequence = false,
.SpiSeqEndNotification = SPI_SEQ_CMD_END_NOTIFICATION,
.JobAssignment = {
SPI_JOB_CMD,
(-1)
},
},
{
.SpiSequenceId = SPI_SEQ_WRITE,
.SpiInterruptibleSequence = false,
.SpiSeqEndNotification = SPI_SEQ_WRITE_END_NOTIFICATION,
.JobAssignment = {
SPI_JOB_WREN,
SPI_JOB_DATA,
(-1)
},
},
{
.SpiSequenceId = SPI_SEQ_READ,
.SpiInterruptibleSequence = false,
.SpiSeqEndNotification = SPI_SEQ_READ_END_NOTIFICATION,
.JobAssignment = {
SPI_JOB_DATA,
(-1)
},
},
{
.SpiSequenceId = SPI_SEQ_CMD2,
.SpiInterruptibleSequence = false,
.SpiSeqEndNotification = SPI_SEQ_CMD2_END_NOTIFICATION,
.JobAssignment = {
SPI_JOB_CMD2,
(-1)
},
},
};
/*************** Jobs **************/
const Spi_JobConfigType SpiJobConfigData[] =
{
{
.SpiJobId = SPI_JOB_CMD2,
.SpiHwUnit = CSIB0,
.SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS
.SpiJobEndNotification = SPI_JOB_CMD2_END_NOTIFICATION,
.ChannelAssignment = {
SPI_CH_CMD,
SPI_CH_DATA,
(-1)
},
.DeviceAssignment = SPI_device_1,
},
{
.SpiJobId = SPI_JOB_DATA,
.SpiHwUnit = CSIB0,
.SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS
.SpiJobEndNotification = SPI_JOB_DATA_END_NOTIFICATION,
.ChannelAssignment = {
SPI_CH_CMD,
SPI_CH_ADDR,
SPI_CH_DATA,
(-1)
},
.DeviceAssignment = SPI_device_1,
},
{
.SpiJobId = SPI_JOB_CMD,
.SpiHwUnit = CSIB0,
.SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS
.SpiJobEndNotification = SPI_JOB_CMD_END_NOTIFICATION,
.ChannelAssignment = {
SPI_CH_CMD,
(-1)
},
.DeviceAssignment = SPI_device_1,
},
{
.SpiJobId = SPI_JOB_WREN,
.SpiHwUnit = CSIB0,
.SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS
.SpiJobEndNotification = SPI_JOB_WREN_END_NOTIFICATION,
.ChannelAssignment = {
SPI_CH_WREN,
(-1)
},
.DeviceAssignment = SPI_device_1,
},
};
uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }
/*************** Channels **************/
const Spi_ChannelConfigType SpiChannelConfigData[] =
{
{
.SpiChannelId = SPI_CH_WREN,
.SpiChannelType = SPI_EB,
.SpiDataWidth = 8,
.SpiIbNBuffers = 0,
.SpiEbMaxLength = 1,
.SpiDefaultData = 6,
.SpiTransferStart = SPI_TRANSFER_START_MSB,
},
{
.SpiChannelId = SPI_CH_CMD,
.SpiChannelType = SPI_EB,
.SpiDataWidth = 8,
.SpiIbNBuffers = 0,
.SpiEbMaxLength = 64,
.SpiDefaultData = 0,
.SpiTransferStart = SPI_TRANSFER_START_MSB,
},
{
.SpiChannelId = SPI_CH_DATA,
.SpiChannelType = SPI_EB,
.SpiDataWidth = 8,
.SpiIbNBuffers = 0,
.SpiEbMaxLength = 64,
.SpiDefaultData = 0,
.SpiTransferStart = SPI_TRANSFER_START_MSB,
},
{
.SpiChannelId = SPI_CH_ADDR,
.SpiChannelType = SPI_EB,
.SpiDataWidth = 16,
.SpiIbNBuffers = 0,
.SpiEbMaxLength = 64,
.SpiDefaultData = 0,
.SpiTransferStart = SPI_TRANSFER_START_MSB,
},
{
.SpiChannelId = (-1),
}
};
uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }
/*************** External Devices **************/
const Spi_ExternalDeviceType SpiExternalConfigData[] =
{
{
.SpiBaudrate = 100000UL,
.SpiCsIdentifier = 2,
.SpiCsPolarity = STD_LOW,
.SpiDataShiftEdge = SPI_EDGE_LEADING,
.SpiEnableCs = 0, // NOT SUPPORTED IN TOOLS
.SpiShiftClockIdleLevel = STD_LOW,
.SpiTimeClk2Cs = 606, // ns
.SpiTimeCs2Clk = 606, // ns
},
};
uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }
const Spi_ConfigType SpiConfigData =
{
.SpiMaxChannel = SPI_MAX_CHANNEL,
.SpiMaxJob = SPI_MAX_JOB,
.SpiMaxSequence = SPI_MAX_SEQUENCE,
.SpiChannelConfig = &SpiChannelConfigData[0],
.SpiSequenceConfig = &SpiSequenceConfigData[0],
.SpiJobConfig = &SpiJobConfigData[0],
.SpiExternalDevice = &SpiExternalConfigData[0],
};
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Spi_Lcfg.c
|
C
|
unknown
| 5,632
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Wdg_Cfg.h
|
C
|
unknown
| 1,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 200, // ms
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 2000, // ms
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5516it/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,253
|
BOOT_IMAGE_ADDR=0x1c000
BOOT_BLOB_LOAD_ADDR=0x1c100
BOOT_BLOB_START_ADDR=$(BOOT_BLOB_LOAD_ADDR)
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/boot_info.mk
|
Makefile
|
unknown
| 101
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC BOOKE E200Z6 MPC55XX MPC5567 BRD_MPC5567QRTECH SPE_FPU_SCALAR_SINGLE TIMER_TB
CFG+=MCU_ARC_CONFIG MCU_CACHE # MCU_MMU MCU_LP
CFG+=CREATE_SREC
CFG+=VLE
#CFG+=BOOT
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN MCU PORT PWM WDG SPI ETH FLS
# Additional
MOD_AVAIL+=LWIP TCPIP SOAD DOIP UDPNM ETHSM
# Required modules
MOD_USE += MCU KERNEL
COMPILER?=gcc
COMPILER_FLAVOR=s32_newlib
# Default cross compiler
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
# Defines
def-y += SRAM_SIZE=0x14000
def-y += L_BOOT_RESERVED_SPACE=0x10000
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
# Software floating point, PowerPC No Small-Data ELF EABI Object Format
diab-$(vle)=-tPPCE200Z6VFS:simple
diab-$(novle)=-tPPCE200Z6NFS:simple
DIAB_TARGET?=$(diab-y)
GHS_TARGET=ppc5567
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/build_config.mk
|
Makefile
|
unknown
| 1,129
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#include "Dma.h"
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_D_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_D_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_SPI_COMBINED_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_SPI_COMBINED_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
};
const Dma_ConfigType DmaConfig []=
{
{DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}
};
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/config/Dma_Cfg.c
|
C
|
unknown
| 4,034
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
// See section 9.4.3 DMA Request Assignments in MPC5567 RM
typedef enum
{
DMA_ADC_GROUP0_COMMAND_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_ADC_GROUP1_COMMAND_CHANNEL,
DMA_ADC_GROUP1_RESULT_CHANNEL,
DMA_ADC_GROUP2_COMMAND_CHANNEL,
DMA_ADC_GROUP2_RESULT_CHANNEL,
DMA_ADC_GROUP3_COMMAND_CHANNEL,
DMA_ADC_GROUP3_RESULT_CHANNEL,
DMA_ADC_GROUP4_COMMAND_CHANNEL,
DMA_ADC_GROUP4_RESULT_CHANNEL,
DMA_ADC_GROUP5_COMMAND_CHANNEL,
DMA_ADC_GROUP5_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL,
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL,
DMA_DSPI_C_RESULT_CHANNEL,
DMA_DSPI_D_COMMAND_CHANNEL,
DMA_DSPI_D_RESULT_CHANNEL,
DMA_SPI_COMBINED_TRANSMIT_CHANNEL,
DMA_SPI_COMBINED_RECEIVE_CHANNEL,
DMA_EMIOS_0_CHANNEL,
DMA_EMIOS_1_CHANNEL,
DMA_EMIOS_2_CHANNEL,
DMA_EMIOS_3_CHANNEL,
DMA_EMIOS_4_CHANNEL,
DMA_EMIOS_8_CHANNEL,
DMA_EMIOS_9_CHANNEL,
DMA_TPU_0_CHANNEL,
DMA_TPU_1_CHANNEL,
DMA_TPU_2_CHANNEL,
DMA_TPU_14_CHANNEL,
DMA_TPU_15_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_ADC_GROUP0_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/config/Dma_Cfg.h
|
C
|
unknown
| 1,987
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5567)
/* RWW between partitions*
*
* LOW 2*16KB + 2*48KB + 2*64KB = 256KB
* MID 2*128KB = 256KB
* HIGH 12*128KB = 1.5MB
*/
const FlashType flashInfo[] = {
[0].sectCnt = 20,
[0].bankSize = 0x200000,
[0].regBase = 0xc3f88000UL,
/* LOW */
[0].sectAddr[0] = 0,
[0].addrSpace[0] = ADDR_SPACE(0, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[1] = 0x00004000,
[0].addrSpace[1] = ADDR_SPACE(1, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[2] = 0x00010000,
[0].addrSpace[2] = ADDR_SPACE(2, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[3] = 0x0001c000,
[0].addrSpace[3] = ADDR_SPACE(3, ADDR_SPACE_LOW, 1 ),
[0].sectAddr[4] = 0x00020000,
[0].addrSpace[4] = ADDR_SPACE(4, ADDR_SPACE_LOW, 2 ),
[0].sectAddr[5] = 0x00030000,
[0].addrSpace[5] = ADDR_SPACE(5, ADDR_SPACE_LOW, 2 ),
/* MID */
[0].sectAddr[6] = 0x00040000,
[0].addrSpace[6] = ADDR_SPACE(0, ADDR_SPACE_MID, 3 ),
[0].sectAddr[7] = 0x00060000,
[0].addrSpace[7] = ADDR_SPACE(1, ADDR_SPACE_MID, 3 ),
/* HIGH */
[0].sectAddr[8] = 0x00080000,
[0].addrSpace[8] = ADDR_SPACE(0, ADDR_SPACE_HIGH, 4 ),
[0].sectAddr[9] = 0x000a0000,
[0].addrSpace[9] = ADDR_SPACE(1, ADDR_SPACE_HIGH, 4 ),
[0].sectAddr[10] = 0x000c0000,
[0].addrSpace[10] = ADDR_SPACE(2, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[11] = 0x000e0000,
[0].addrSpace[11] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 5 ),
[0].sectAddr[12] = 0x00100000,
[0].addrSpace[12] = ADDR_SPACE(4, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[13] = 0x00120000,
[0].addrSpace[13] = ADDR_SPACE(5, ADDR_SPACE_HIGH, 6 ),
[0].sectAddr[14] = 0x00140000,
[0].addrSpace[14] = ADDR_SPACE(6, ADDR_SPACE_HIGH, 7 ),
[0].sectAddr[15] = 0x00160000,
[0].addrSpace[15] = ADDR_SPACE(7, ADDR_SPACE_HIGH, 7 ),
[0].sectAddr[16] = 0x00180000,
[0].addrSpace[16] = ADDR_SPACE(8, ADDR_SPACE_HIGH, 8 ),
[0].sectAddr[17] = 0x001a0000,
[0].addrSpace[17] = ADDR_SPACE(9, ADDR_SPACE_HIGH, 8 ),
[0].sectAddr[18] = 0x001c0000,
[0].addrSpace[18] = ADDR_SPACE(10, ADDR_SPACE_HIGH, 9 ),
[0].sectAddr[19] = 0x001e0000,
[0].addrSpace[19] = ADDR_SPACE(11, ADDR_SPACE_HIGH, 9 ),
[0].sectAddr[20] = 0x00200000, /* End, NOT a sector */
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/config/Fls_Cfg.c
|
C
|
unknown
| 3,669
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5567)
#define FLASH_BANK_CNT 1
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 20
#define FLS_TOTAL_SIZE (2*1024*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/config/Fls_Cfg.h
|
C
|
unknown
| 3,628
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/config/Wdg_Cfg.h
|
C
|
unknown
| 1,397
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 0x200, /* 500 ms */
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 7000uL, /* 7 seconds */
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5567qrtech/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,279
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5604B BRD_MPC5604B_XPC560B
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
CFG+=OS_SYSTICK2
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI FLS
# Required modules
MOD_USE += MCU KERNEL
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
# Defines
def-y += SRAM_SIZE=0xc000
# Software floating point, PowerPC No Small-Data ELF EABI Object Format
DIAB_TARGET?=-tPPCE200Z0VFS:simple
GHS_TARGET?=ppc560xb
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/build_config.mk
|
Makefile
|
unknown
| 870
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/config/Eep_Lcfg.c
|
C
|
unknown
| 4,049
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5604B)
/* IMPROVEMENT: This can actually be read from the flash instead */
const FlashType flashInfo[] = {
/* NO RWW */
{
/* Bank 0, Array 0 (LOW) */
.sectCnt = 8,
.bankSize = 0x80000,
// .bankRange = BANK_RANGE_CODE_LOW,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x08000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x10000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x18000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
.sectAddr[5] = 0x20000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
.sectAddr[6] = 0x40000, /* 6, B0F6, MID */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[7] = 0x60000, /* 7, B0F7, MID */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
.sectAddr[8] = 0x80000, /* End, NOT a sector */
},
{
/* Bank 1, Data */
.sectCnt = 4,
.bankSize = 0x810000 - 0x800000,
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x800000, /* LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x804000, /* LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x808000, /* LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x80c000, /* LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x810000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
// .FlsSectorList = &fls_evbSectorList[0],
// .FlsSectorListSize = sizeof(fls_evbSectorList)/sizeof(Fls_SectorType),
// .FlsBlockToPartitionMap = Fls_BlockToPartitionMap,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/config/Fls_Cfg.c
|
C
|
unknown
| 3,449
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5604B)
#define FLASH_BANK_CNT 2
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 8
#define FLS_TOTAL_SIZE ((16*4+512)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(); /* NO SUPPORT */
void (*FlsAcWrite)(); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)();
void (*FlsJobErrorNotification)();
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/config/Fls_Cfg.h
|
C
|
unknown
| 3,633
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0u
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/config/Wdg_Cfg.h
|
C
|
unknown
| 1,409
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 4u, /* ms */
.ActivationBit = 1u,
},
.WdgSettingsSlow =
{
.ReloadValue = 250, /* ms */
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00, /* not used */
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5604b_xpc560b/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,278
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5606B BRD_MPC5606B_XPC560B
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
CFG+=OS_SYSTICK2
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI OCU ICU FLS
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
# Defines
def-y += SRAM_SIZE=0x14000
# Software floating point, PowerPC No Small-Data ELF EABI Object Format
DIAB_TARGET?=-tPPCE200Z0VFS:simple
GHS_TARGET?=ppc560xb
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/build_config.mk
|
Makefile
|
unknown
| 897
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Dma.h"
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC0
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_D_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_D_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_E_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_E_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_F_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_F_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
}
};
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_DMA_MUX)
DmaMuxConfig,
#endif
.dmaChannelConfigPtr = DmaChannelConfig,
.dmaChannelArbitration = DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Dma_Cfg.c
|
C
|
unknown
| 4,102
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
typedef enum
{
DMA_DSPI_A_COMMAND_CHANNEL, /* 0 */
DMA_DSPI_A_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL, /* 1 */
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL, /* 2 */
DMA_DSPI_C_RESULT_CHANNEL,
DMA_DSPI_D_COMMAND_CHANNEL, /* 3 */
DMA_DSPI_D_RESULT_CHANNEL,
DMA_DSPI_E_COMMAND_CHANNEL, /* 4 */
DMA_DSPI_E_RESULT_CHANNEL,
DMA_DSPI_F_COMMAND_CHANNEL, /* 5 */
DMA_DSPI_F_RESULT_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_DSPI_A_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Dma_Cfg.h
|
C
|
unknown
| 1,414
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Eep_Lcfg.c
|
C
|
unknown
| 4,051
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5606B)
/*lint -e940 -e785 -e835 -e9027 -e845 -e651 To increase readability */
const FlashType flashInfo[2] = {
/* NO RWW */
/* Bank 0, Array 0 */
{
.sectCnt = 12,
.bankSize = 0x100000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) /* + 0 */,
.sectAddr[1] = 0x08000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1u,
.sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2u,
.sectAddr[3] = 0x10000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3u,
.sectAddr[4] = 0x18000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4u,
.sectAddr[5] = 0x20000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5u,
.sectAddr[6] = 0x40000, /* 6, B0F6, MID */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) /* + 0 */,
.sectAddr[7] = 0x60000, /* 7, B0F7, MID */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1u,
/* Bank 0, Array 1 */
.sectAddr[8] = 0x80000, /* 8, B0F8, HIGH */
.addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) /* + 0 */,
.sectAddr[9] = 0xa0000, /* 9, B0F9, HIGH */
.addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1u,
.sectAddr[10] = 0xc0000, /* 10, B0F10, HIGH */
.addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2u,
.sectAddr[11] = 0xe0000, /* 11, B0F11, HIGH */
.addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3u,
.sectAddr[12] = 0x100000, /* End, NOT a sector */
},
{
/* Bank 1, Data */
.sectCnt = 4u,
.bankSize = 0x810000 - 0x800000,
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x800000, /* LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) /* + 0 */,
.sectAddr[1] = 0x804000, /* LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x808000, /* LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x80c000, /* LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x810000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Fls_Cfg.c
|
C
|
unknown
| 3,588
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5606B)
#define FLASH_BANK_CNT 2
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 12
#define FLS_TOTAL_SIZE ((16*4+512+512)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(void); /* NO SUPPORT */
void (*FlsAcWrite)(void); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)(void);
void (*FlsJobErrorNotification)(void);
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Fls_Cfg.h
|
C
|
unknown
| 3,652
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0u
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Wdg_Cfg.h
|
C
|
unknown
| 1,409
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 4u, /* ms */
.ActivationBit = 1u,
},
.WdgSettingsSlow =
{
.ReloadValue = 250, /* ms */
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00, /* not used */
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5606b_xpc560b/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,278
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z0 MPC55XX MPC560X MPC5606S BRD_MPC5606S_XPC560S
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
CFG+=OS_SYSTICK2
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI FLS ICU
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
# Defines
def-y += SRAM_SIZE=0xc000
# Software floating point, PowerPC No Small-Data ELF EABI Object Format
DIAB_TARGET?=-tPPCE200Z0VFS:simple
GHS_TARGET?=ppc560xb
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/build_config.mk
|
Makefile
|
unknown
| 889
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Dma.h"
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
}
};
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_DMA_MUX)
DmaMuxConfig,
#endif
.dmaChannelConfigPtr = DmaChannelConfig,
.dmaChannelArbitration = DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Dma_Cfg.c
|
C
|
unknown
| 2,307
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
typedef enum
{
DMA_DSPI_A_COMMAND_CHANNEL, /* 0 */
DMA_DSPI_A_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL, /* 1 */
DMA_DSPI_B_RESULT_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_DSPI_A_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Dma_Cfg.h
|
C
|
unknown
| 1,122
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_M9525
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Eep_Lcfg.c
|
C
|
unknown
| 4,044
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5606S)
/*lint -e940 -e785 -e835 -e9027 -e845 -e651 To increase readability */
const FlashType flashInfo[3] = {
/* NO RWW */
/* Bank 0, Array 0 Code Flash 0*/
{
.sectCnt = 8,
.bankSize = 0x80000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) /* + 0 */,
.sectAddr[1] = 0x08000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1u,
.sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2u,
.sectAddr[3] = 0x10000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3u,
.sectAddr[4] = 0x18000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4u,
.sectAddr[5] = 0x20000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5u,
.sectAddr[6] = 0x40000, /* 6, B0F6, MID */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) /* + 0 */,
.sectAddr[7] = 0x60000, /* 7, B0F7, MID */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1u,
.sectAddr[8] = 0x80000, /* End, NOT a sector */
},
/* Bank 1, Array 1 Code Flash 1 */
{
.sectCnt = 4,
.bankSize = 0x80000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0x00080000, /* 0, B2F0, HIGH */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) /* + 0 */,
.sectAddr[1] = 0x000A0000, /* 1, B2F1, HIGH */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1u,
.sectAddr[2] = 0x000C0000, /* 2, B2F2, HIGH */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2u,
.sectAddr[3] = 0x000E0000, /* 3, B2F3, HIGH */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3u,
.sectAddr[4] = 0x00100000, /* End, NOT a sector */
},
{
/* Bank 2, Data Flash 0 */
.sectCnt = 4u,
.bankSize = 0x810000 - 0x800000,
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x800000, /* B1F0 LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) /* + 0 */,
.sectAddr[1] = 0x804000, /* B1F1 LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x808000, /* B1F2 LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x80c000, /* B1F3 LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x810000, /* End, NOT a sector */
},
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Fls_Cfg.c
|
C
|
unknown
| 3,961
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xffu /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5606S)
#define FLASH_BANK_CNT 3
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 8
#define FLS_TOTAL_SIZE ((16*4+512+512)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(void); /* NO SUPPORT */
void (*FlsAcWrite)(void); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)(void);
void (*FlsJobErrorNotification)(void);
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Fls_Cfg.h
|
C
|
unknown
| 3,646
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0u
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Wdg_Cfg.h
|
C
|
unknown
| 1,403
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 4u, /* ms */
.ActivationBit = 1u,
},
.WdgSettingsSlow =
{
.ReloadValue = 250, /* ms */
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0x7D00, /* not used */
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5606s_xpc560s/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,271
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG+=PPC E200Z0 MPC55XX MPC560X MPC560XB MPC5606B MPC5607B BRD_MPC5606B_XPC560B
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=VLE
CFG+=TIMER
CFG+=TIMER_RTC
#CFG+=MCU_ARC_LP
CFG+=OS_SYSTICK2
# What buildable modules does this board have,
# default or private
# Memory + Peripherals
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG SPI OCU ICU FLS
# Required modules
MOD_USE += MCU KERNEL
# Default cross compiler
COMPILER?=gcc
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.4.8/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
# Defines
def-y += __BIG_ENDIAN__
def-y += SRAM_SIZE=0x18000
# Software floating point, PowerPC No Small-Data ELF EABI Object Format
DIAB_TARGET?=-tPPCE200Z0VFS:simple
GHS_TARGET?=ppc560xb
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/build_config.mk
|
Makefile
|
unknown
| 1,075
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Dma.h"
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_0_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_1_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_2_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_3_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_4_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_TX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_5_RX
},
{
.DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC0
}
};
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
[DMA_START_CHANNEL] = {
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_D_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_D_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_E_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_E_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_F_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_DSPI_F_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
},
{
.DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
}
};
const Dma_ConfigType DmaConfig []=
{
{
#if defined(CFG_DMA_MUX)
DmaMuxConfig,
#endif
.dmaChannelConfigPtr = DmaChannelConfig,
.dmaChannelArbitration = DMA_FIXED_PRIORITY_ARBITRATION
}
};
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Dma_Cfg.c
|
C
|
unknown
| 4,103
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef DMA_CFG_H_
#define DMA_CFG_H_
typedef enum
{
DMA_DSPI_A_COMMAND_CHANNEL, /* 0 */
DMA_DSPI_A_RESULT_CHANNEL,
DMA_DSPI_B_COMMAND_CHANNEL, /* 1 */
DMA_DSPI_B_RESULT_CHANNEL,
DMA_DSPI_C_COMMAND_CHANNEL, /* 2 */
DMA_DSPI_C_RESULT_CHANNEL,
DMA_DSPI_D_COMMAND_CHANNEL, /* 3 */
DMA_DSPI_D_RESULT_CHANNEL,
DMA_DSPI_E_COMMAND_CHANNEL, /* 4 */
DMA_DSPI_E_RESULT_CHANNEL,
DMA_DSPI_F_COMMAND_CHANNEL, /* 5 */
DMA_DSPI_F_RESULT_CHANNEL,
DMA_ADC_GROUP0_RESULT_CHANNEL,
DMA_NUMBER_OF_CHANNELS
} Dma_ChannelType;
#define DMA_START_CHANNEL DMA_DSPI_A_COMMAND_CHANNEL
#endif /* DMA_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Dma_Cfg.h
|
C
|
unknown
| 1,414
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef EEP_CFG_H_
#define EEP_CFG_H_
#define EEP_USES_EXTERNAL_DRIVER
#include "Spi.h"
#include "Eep_ConfigTypes.h"
// M95256 or 25LC160B
#define E2_WREN 0x6 // Write Enable 0000 0110
#define E2_WRDI 0x4 // Write Disable 0000 0100
#define E2_RDSR 0x5 // Read Status Register 0000 0101
// 1 - Read data
#define E2_WRSR 0x1 // Write Status Register 0000 0001
// 1 - Write data
#define E2_READ 0x3 // Read from Memory Array 0000 0011
// 1 - Write 16-bit address
// n - 8 -bit read data
#define E2_WRITE 0x2 // WRITE Write to Memory Array 0000 0010
// 1 Write 16-bit address
// n - 8-bit reads
/* EepGeneral */
// Switches to activate or deactivate interrupt controlled job processing. true:
// Interrupt controlled job processing enabled. false: Interrupt controlled job
// processing disabled.
#define EEP_USE_INTERRUPTS STD_OFF
// Pre-processor switch to enable and disable development error detection.
// true: Development error detection enabled. false: Development error
// detection disabled.
#define EEP_DEV_ERROR_DETECT STD_ON
// Pre-processor switch to enable / disable the API to read out the modules
// version information. true: Version info API enabled. false: Version info API
// disabled.
#define EEP_VERSION_INFO_API STD_ON
// ndex of the driver, used by EA.
#define EEP_DRIVER_INDEX 1
// Switches to activate or deactivate write cycle reduction (EEPROM value is
// read and compared before being overwritten). true: Write cycle reduction
// enabled. false: Write cycle reduction disabled.
#define EEP_WRITE_CYCLE_REDUCTION STD_OFF
// Container for runtime configuration parameters of the EEPROM driver.
// Implementation Type: Eep_ConfigType.
/* EepPublishedInformation
*/
// Total size of EEPROM in bytes. Implementation Type: Eep_LengthType.
#define EEP_TOTAL_SIZE TBD
// Size of smallest erasable EEPROM data unit in bytes.
#define EEP_ERASE_UNIT_SIZE TBD
// EepMinimumLengthType {EEP_MINIMUM_LENGTH_TYPE}
// Minimum expected size of Eep_LengthType.
#define EEP_MINIMUM_LENGTH_TYPE TBD
// Minimum expected size of Eep_AddressType.
#define EEP_MINIMUM_ADDRESS_TYPE TBD
// Size of smallest writable EEPROM data unit in bytes.
#define EEP_WRITE_UNIT_SIZE TBD
// Value of an erased EEPROM cell.
#define EEP_ERASE_VALUE 0
// Number of erase cycles specified for the EEP device (usually given in the
// device data sheet).
#define EEP_SPECIFIED_ERASE_CYCLES TBD
// Size of smallest readable EEPROM data unit in bytes.
#define EEP_READ_UNIT_SIZE TBD
// Time for writing one EEPROM data unit.(float)
#define EEP_WRITE_TIME TBD
// Time for erasing one EEPROM data unit (float)
#define EEP_ERASE_TIME TBD
// Specified maximum number of write cycles under worst case conditions of
// specific EEPROM hardware (e.g. +90�C)
#define EEP_ALLOWED_WRITE_CYCLES x
extern const Eep_ConfigType EepConfigData[];
#define EEP_DEFAULT_CONFIG EepConfigData[0]
#endif /*EEP_CFG_H_*/
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Eep_Cfg.h
|
C
|
unknown
| 4,156
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/* Configured for:
* Microchip 25LC160B (32 bytes pages)
*/
#include "Eep.h"
#include "Spi.h"
#include "debug.h"
#define E2_M9525 1
#define E2_25LC160B 2
#define E2_CHIP E2_25LC160B
#if defined(USE_EA)
extern void Ea_JobErrorNotification(void);
extern void Ea_JobEndNotification(void);
#endif
static void _JobEndNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB END NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobEndNotification();
#endif
}
static void _JobErrorNotify(void){
DEBUG(DEBUG_LOW,"EEP JOB ERROR NOTIFICATION\n");
#if defined(USE_EA)
Ea_JobErrorNotification();
#endif
}
#define SPI_SEQ_EEP_CMD SpiConf_SpiSequence_SEQ_CMD
#define SPI_SEQ_EEP_CMD2 SpiConf_SpiSequence_SEQ_CMD2
#define SPI_SEQ_EEP_READ SpiConf_SpiSequence_SEQ_READ
#define SPI_SEQ_EEP_WRITE SpiConf_SpiSequence_SEQ_WRITE
#define SPI_CH_EEP_CMD SpiConf_SpiChannel_CH_CMD
#define SPI_CH_EEP_ADDR SpiConf_SpiChannel_CH_ADDR
#define SPI_CH_EEP_WREN SpiConf_SpiChannel_CH_WREN
#define SPI_CH_EEP_DATA SpiConf_SpiChannel_CH_DATA
const Eep_ExternalDriverType EepExternalDriver = {
// READ and WRITE sequences and ID's defined in Spi_Cfg.h
.EepCmdSequence = SPI_SEQ_EEP_CMD,
.EepCmd2Sequence = SPI_SEQ_EEP_CMD2,
.EepReadSequence = SPI_SEQ_EEP_READ,
.EepWriteSequence = SPI_SEQ_EEP_WRITE,
// Jobs may be left out..
// Channels used
.EepCmdChannel = SPI_CH_EEP_CMD,
.EepAddrChannel = SPI_CH_EEP_ADDR,
.EepWrenChannel = SPI_CH_EEP_WREN,
.EepDataChannel = SPI_CH_EEP_DATA,
};
const Eep_ConfigType EepConfigData[] = {
{
// call cycle of the job processing function during write/erase operations. Unit: [s]
// .EepJobCallCycle = 0.2,
// This parameter is the EEPROM device base address.
.EepBaseAddress = 0,
// This parameter is the default EEPROM device mode after initialization.
.EepDefaultMode = MEMIF_MODE_FAST,
#if (E2_CHIP == E2_25LC160B)
// This parameter is the number of bytes read within one job processing cycle in fast mode
.EepFastReadBlockSize = 32,
// This parameter is the number of bytes written within one job processing cycle in fast mode
.EepFastWriteBlockSize = 32,
#elif (E2_CHIP == E2_M9525)
.EepFastReadBlockSize = 64,
.EepFastWriteBlockSize = 64,
#endif
// This parameter is a reference to a callback function for positive job result
.Eep_JobEndNotification = _JobEndNotify,
// This parameter is a reference to a callback function for negative job result
.Eep_JobErrorNotification = _JobErrorNotify,
.EepNormalReadBlockSize = 4,
// Number of bytes written within one job processing cycle in normal mode.
.EepNormalWriteBlockSize = 1,
// This parameter is the used size of EEPROM device in bytes.
#if (E2_CHIP == E2_25LC160B)
.EepSize = 0x800, /* 16Kb for 25LC160B */
#elif (E2_CHIP == E2_M9525)
.EepSize = 0x8000, /* 256Kb for M9525 */
#endif
#if (E2_CHIP == E2_25LC160B)
.EepPageSize = 32, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#elif (E2_CHIP == E2_M9525)
.EepPageSize = 64, /* 64 for M9525, 32 for 25LC160B, 16 for 25LC160A */
#endif
.externalDriver = &EepExternalDriver,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Eep_Lcfg.c
|
C
|
unknown
| 4,053
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Fls.h"
#include "flash.h"
#include <stdlib.h>
#if defined(CFG_MPC5606B)
/*lint -e940 -e785 -e835 -e9027 -e845 -e651 To increase readability */
const FlashType flashInfo[2] = {
/* NO RWW */
/* Bank 0, code flash memory */
{
.sectCnt = 16,
.bankSize = 0x180000,
.regBase = 0xC3F88000UL,
.sectAddr[0] = 0, /* 0, B0F0, LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x08000, /* 1, B0F1, LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x10000, /* 3, B0F3, LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x18000, /* 4, B0F4, LOW */
.addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,
.sectAddr[5] = 0x20000, /* 5, B0F5, LOW */
.addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,
.sectAddr[6] = 0x40000, /* 6, B0F6, MID */
.addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,
.sectAddr[7] = 0x60000, /* 7, B0F7, MID */
.addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,
.sectAddr[8] = 0x80000, /* 8, B0F8, MID */
.addrSpace[8] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 0,
.sectAddr[9] = 0xA0000, /* 9, B0F9, HIGH */
.addrSpace[9] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 1,
.sectAddr[10] = 0xC0000, /* 10, B0F10, HIGH */
.addrSpace[10] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 2,
.sectAddr[11] = 0xE0000, /* 11, B0F11, HIGH */
.addrSpace[11] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 3,
.sectAddr[12] = 0x100000, /* 12, B0F12, HIGH */
.addrSpace[12] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 4,
.sectAddr[13] = 0x120000, /* 13, B0F13, HIGH */
.addrSpace[13] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 5,
.sectAddr[14] = 0x140000, /* 14, B0F14, HIGH */
.addrSpace[14] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 6,
.sectAddr[15] = 0x160000, /* 15, B0F15, HIGH */
.addrSpace[15] = ADDR_SPACE_SET(ADDR_SPACE_HIGH) + 7,
.sectAddr[16] = 0x180000, /* End, NOT a sector */
},
{
/* Data flash memory */
.sectCnt = 4,
.bankSize = 0x810000 - 0x800000,
.regBase = 0xC3F8C000UL,
.sectAddr[0] = 0x800000, /* LOW */
.addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,
.sectAddr[1] = 0x804000, /* LOW */
.addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,
.sectAddr[2] = 0x808000, /* LOW */
.addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,
.sectAddr[3] = 0x80c000, /* LOW */
.addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,
.sectAddr[4] = 0x810000, /* End, NOT a sector */
}
};
#else
#error CPU NOT supported
#endif
const Fls_ConfigType FlsConfigSet[]=
{
{
#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)
.FlsAcWrite = __FLS_ERASE_RAM__,
.FlsAcErase = __FLS_WRITE_RAM__,
#else
.FlsAcWrite = NULL,
.FlsAcErase = NULL,
#endif
.FlsJobEndNotification = NULL,
.FlsJobErrorNotification = NULL,
.FlsInfo = flashInfo,
.FlsMaxReadFastMode = 16,
.FlsMaxReadNormalMode = 16,
.FlsMaxWriteFastMode = 32,
.FlsMaxWriteNormalMode = 32,
}
};
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Fls_Cfg.c
|
C
|
unknown
| 3,979
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
/** @addtogroup Fls Flash Driver
* @{ */
/** @file Fls_Cfg.h
* Definitions of configuration parameters for Flash Driver.
*/
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#define USE_FLS_INFO STD_ON
/* STD container : Fls
* FlsConfigSet 1..*
* FlsGeneral 1
* FlsPublishedInformation 1
*/
#include "MemIf_Types.h"
/* FlsGeneral, 3.0 OK */
#define FLS_VARIANT_PB STD_OFF
#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */
#define FLS_BASE_ADDRESS 0x00000000
#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */
#define FLS_COMPARE_API STD_ON
#define FLS_DEV_ERROR_DETECT STD_ON
#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */
#define FLS_GET_JOB_RESULT_API STD_ON
#define FLS_GET_STATUS_API STD_ON
#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */
#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */
#define FLS_VERSION_INFO_API STD_ON
/* FlsPublishedInformation, 3.0 OK */
#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */
#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */
#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */
#define FLS_ERASE_TIME 0 /* NO SUPPORT */
#define FLS_ERASED_VALUE (uint8)0xff /* NO SUPPORT */
#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */
#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */
#define FLS_WRITE_TIME 0 /* NO SUPPORT */
/* MCU Specific */
#if defined(CFG_MPC5606B)
#define FLASH_BANK_CNT 2
#define FLASH_PAGE_SIZE 8
#define FLASH_MAX_SECTORS 16
#define FLS_TOTAL_SIZE ((16*4+512*3)*1024)
#else
#error CPU not supported
#endif
#if (USE_FLS_INFO==STD_ON)
typedef struct Flash {
uint32 size;
uint32 sectCnt;
uint32 bankSize;
uint32 regBase;
uint32 sectAddr[FLASH_MAX_SECTORS+1];
uint16 addrSpace[FLASH_MAX_SECTORS+1];
} FlashType;
#else
typedef struct {
Fls_LengthType FlsNumberOfSectors;
Fls_LengthType FlsPageSize;
Fls_LengthType FlsSectorSize;
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
#endif
struct Flash;
typedef struct {
void (*FlsAcErase)(void); /* NO SUPPORT */
void (*FlsAcWrite)(void); /* NO SUPPORT */
// FlsCallCycle N/A in core.
void (*FlsJobEndNotification)(void);
void (*FlsJobErrorNotification)(void);
uint32 FlsMaxReadFastMode;
uint32 FlsMaxReadNormalMode;
uint32 FlsMaxWriteFastMode;
uint32 FlsMaxWriteNormalMode;
uint32 FlsProtection; /* NO SUPPORT */
#if (USE_FLS_INFO==STD_ON)
const struct Flash *FlsInfo;
#else
const Fls_SectorType *FlsSectorList;
#endif
// const uint32 FlsSectorListSize; /* NO SUPPORT */
} Fls_ConfigSetType;
typedef Fls_ConfigSetType Fls_ConfigType;
extern const Fls_ConfigSetType FlsConfigSet[];
#endif /*FLS_CFG_H_*/
/** @} */
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Fls_Cfg.h
|
C
|
unknown
| 3,652
|
/* -------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#ifndef WDG_CFG_H_
#define WDG_CFG_H_
#include "Std_Types.h"
#include "WdgIf_Types.h"
#define WDG_INDEX 0u
#define WDG_VERSION_INFO_API STD_ON
#define WDG_DEV_ERROR_DETECT STD_ON
typedef struct
{
uint32 ReloadValue;
uint8 ActivationBit;
}Wdg_SettingsType;
typedef struct
{
WdgIf_ModeType Wdg_DefaultMode;
Wdg_SettingsType WdgSettingsFast;
Wdg_SettingsType WdgSettingsSlow;
Wdg_SettingsType WdgSettingsOff;
}Wdg_ModeConfigType;
typedef struct
{
const Wdg_ModeConfigType *Wdg_ModeConfig;
}Wdg_ConfigType;
extern const Wdg_ConfigType WdgConfig;
#endif /* WDG_CFG_H_ */
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Wdg_Cfg.h
|
C
|
unknown
| 1,406
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#include "Wdg.h"
const Wdg_ModeConfigType WdgModeConfig =
{
.Wdg_DefaultMode = WDGIF_OFF_MODE,
.WdgSettingsFast =
{
.ReloadValue = 200, // ms
.ActivationBit = 1,
},
.WdgSettingsSlow =
{
.ReloadValue = 2000, // ms
.ActivationBit = 1,
},
.WdgSettingsOff =
{
.ReloadValue = 0,
.ActivationBit = 0,
},
};
const Wdg_ConfigType WdgConfig =
{
.Wdg_ModeConfig = &WdgModeConfig,
};
|
2301_81045437/classic-platform
|
boards/mpc5607b_xpc560b/config/Wdg_Lcfg.c
|
C
|
unknown
| 1,252
|
# ARCH defines
ARCH=mpc5xxx
ARCH_FAM=ppc
# CFG (y/n) macros
CFG=PPC E200Z3 MPC55XX MPC563XM MPC5634M BRD_MPC5634M_TRK TIMER_TB
CFG+=SPE_FPU_SCALAR_SINGLE
CFG+=MCU_ARC_CONFIG
CFG+=CREATE_SREC
CFG+=OS_SYSTICK2
CFG+=VLE
# What buildable modules does this board have,
# default or private
# MCAL
MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG FLS SPI
# Required modules
MOD_USE += MCU KERNEL
# Defines
def-y += SRAM_SIZE=0x17800
# Default cross compiler
COMPILER?=cw
# Default cross compiler
COMPILER_FLAVOR=s32_newlib
DEFAULT_CROSS_COMPILE = /c/devtools/Freescale/S32DS_Power_v2017.R1/Cross_Tools/powerpc-eabivle-4_9/bin/powerpc-eabivle-
DEFAULT_CW_COMPILE= /c/devtools/Freescale/cw_mpc5xxx_2.10
DEFAULT_DIAB_COMPILE = /c/devtools/WindRiver/diab/5.9.3.0/WIN32
DEFAULT_GHS_COMPILE = /c/devtools/ghs/comp_201314p
vle=$(if $(filter $(CFG),VLE),y)
novle=$(if $(vle),n,y)
SPE_FPU_SCALAR_SINGLE=$(if $(filter $(CFG),SPE_FPU_SCALAR_SINGLE),y)
nospe=$(if $(SPE_FPU_SCALAR_SINGLE),n,y)
diab-$(vle)$(nospe)+=-tPPCE200Z3VFN:simple
diab-$(novle)$(nospe)+=-tPPCE200Z3NFS:simple
diab-$(vle)$(SPE_FPU_SCALAR_SINGLE)+=-tPPCE200Z3VFF:simple
diab-y+=$(diab-yy)
DIAB_TARGET?=$(diab-y)
# VLE
GHS_TARGET?=ppc563xm
def-y += L_BOOT_RESERVED_SPACE=0x10000
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/build_config.mk
|
Makefile
|
unknown
| 1,303
|
/*-------------------------------- Arctic Core ------------------------------
* Copyright (C) 2013, ArcCore AB, Sweden, www.arccore.com.
* Contact: <contact@arccore.com>
*
* You may ONLY use this file:
* 1)if you have a valid commercial ArcCore license and then in accordance with
* the terms contained in the written license agreement between you and ArcCore,
* or alternatively
* 2)if you follow the terms found in GNU General Public License version 2 as
* published by the Free Software Foundation and appearing in the file
* LICENSE.GPL included in the packaging of this file or here
* <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>
*-------------------------------- Arctic Core -----------------------------*/
#warning "This default file may only be used as an example!"
#include "Dma.h"
const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =
{
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_DSPI_C_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_FILL_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DECFIL_DRAIN_BUF_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_TDRE_TC_TXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = SCI_A_RDRF_RXRDY_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
{ .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },
};
const Dma_ConfigType DmaConfig []=
{
{DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}
};
|
2301_81045437/classic-platform
|
boards/mpc5634m_trk/config/Dma_Cfg.c
|
C
|
unknown
| 3,999
|