repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
GeminiCarrie/rust-sgx-sdk | 1,868 | sgx_trts/src/asm/thunk.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "thunk.S"
.macro DEFINE_THUNK indirect_register, thunk_name
.globl \thunk_name
.hidden \thunk_name
.type \thunk_name, @function
\thunk_name:
.cfi_startproc
jmp *%\indirect_register
.cfi_endproc
.endm
.text
.globl __x86_return_thunk
.hidden __x86_return_thunk
.type __x86_return_thunk, @function
.section .nipx,"ax",@progbits
__x86_return_thunk:
.cfi_startproc
ret
.cfi_endproc
DEFINE_THUNK rax, __x86_indirect_thunk_rax
DEFINE_THUNK rbx, __x86_indirect_thunk_rbx
DEFINE_THUNK rcx, __x86_indirect_thunk_rcx
DEFINE_THUNK rdx, __x86_indirect_thunk_rdx
DEFINE_THUNK rbp, __x86_indirect_thunk_rbp
DEFINE_THUNK rsi, __x86_indirect_thunk_rsi
DEFINE_THUNK rdi, __x86_indirect_thunk_rdi
DEFINE_THUNK r8, __x86_indirect_thunk_r8
DEFINE_THUNK r9, __x86_indirect_thunk_r9
DEFINE_THUNK r10, __x86_indirect_thunk_r10
DEFINE_THUNK r11, __x86_indirect_thunk_r11
DEFINE_THUNK r12, __x86_indirect_thunk_r12
DEFINE_THUNK r13, __x86_indirect_thunk_r13
DEFINE_THUNK r14, __x86_indirect_thunk_r14
DEFINE_THUNK r15, __x86_indirect_thunk_r15
|
GeminiCarrie/rust-sgx-sdk | 880 | sgx_trts/src/inst/hyper/td.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "td.S"
.macro READ_TD_DATA offset
mov %gs:\offset, %rax
.endm
|
GeminiCarrie/rust-sgx-sdk | 1,375 | sgx_trts/src/inst/hyper/enclu.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "enclu.S"
.equ HC_EENTER, 0x80000000
.equ HC_EEXIT, 0x80000001
.equ HC_ERESUME, 0x80000005
.equ HC_EGETKEY, 0x8000000B
.equ HC_EREPORT, 0x8000000C
.equ HC_EQUOTE, 0x8000000D
.macro ENCLU
cmp $SE_EEXIT, %rax
jne 1f
mov $HC_EEXIT, %rax
vmmcall
ud2
1:
push %rdi
push %rsi
push %rdx
push %rcx
push %rbx
push %rax
pop %rdi
pop %rsi
pop %rdx
pop %rcx
pop %r8
pop %r9
.type se3,@function
.protected se3
call se3
.endm
|
GeminiCarrie/rust-sgx-sdk | 959 | sgx_trts/src/inst/hyper/xsave_mask.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "xsave_mask.S"
.macro SET_XSAVE_MASK
xor %rax, %rax
xor %rdx, %rdx
mov $0xFFFFFFFF, %eax
mov $0xFFFFFFFF, %edx
.endm
|
GeminiCarrie/rust-sgx-sdk | 880 | sgx_trts/src/inst/hw/td.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "td.S"
.macro READ_TD_DATA offset
mov %gs:\offset, %rax
.endm
|
GeminiCarrie/rust-sgx-sdk | 1,165 | sgx_trts/src/inst/hw/everifyreport.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "everifyreport.S"
.global Leverifyreport2_inst
DECLARE_LOCAL_FUNC everifyreport2
SE_PROLOG
mov $SE_EVERIFYREPORT2, %rax /* EVERIFYREPORT2 leaf */
Leverifyreport2_inst:
ENCLU
jz .Leverifyreport2_done /* if EVERIFYREPORT2 error, ZF flag is set and error code is set to rax */
xor %rax, %rax
.Leverifyreport2_done:
SE_EPILOG
|
GeminiCarrie/rust-sgx-sdk | 873 | sgx_trts/src/inst/hw/enclu.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "enclu.S"
.macro ENCLU
.byte 0x0f, 0x01, 0xd7 /* 0xf3 */
.endm
|
GeminiCarrie/rust-sgx-sdk | 959 | sgx_trts/src/inst/hw/xsave_mask.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "xsave_mask.S"
.macro SET_XSAVE_MASK
xor %rax, %rax
xor %rdx, %rdx
mov $0xFFFFFFFF, %eax
mov $0xFFFFFFFF, %edx
.endm
|
GeminiCarrie/rust-sgx-sdk | 1,515 | sgx_trts/src/inst/sim/lowlib.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "lowlib.S"
.section .nipx,"ax",@progbits
DECLARE_LOCAL_FUNC get_bp
mov %rbp, %rax
ret
.equ reg_rax, (SE_WORDSIZE * 0)
.equ reg_rbx, (SE_WORDSIZE * 1)
.equ reg_rcx, (SE_WORDSIZE * 2)
.equ reg_rdx, (SE_WORDSIZE * 3)
.equ reg_rsi, (SE_WORDSIZE * 4)
.equ reg_rdi, (SE_WORDSIZE * 5)
.equ reg_rbp, (SE_WORDSIZE * 6)
.equ reg_rsp, (SE_WORDSIZE * 7)
.equ reg_rip, (SE_WORDSIZE * 8)
DECLARE_LOCAL_FUNC load_regs
mov %rdi, %rdx
mov reg_rax(%rdx), %rax
mov reg_rbx(%rdx), %rbx
mov reg_rcx(%rdx), %rcx
mov reg_rsi(%rdx), %rsi
mov reg_rdi(%rdx), %rdi
mov reg_rbp(%rdx), %rbp
mov reg_rsp(%rdx), %rsp
push reg_rip(%rdx)
mov reg_rdx(%rdx), %rdx
ret
|
GeminiCarrie/rust-sgx-sdk | 965 | sgx_trts/src/inst/sim/td.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "td.S"
.equ dtv, 8
.equ tls, 0
.macro READ_TD_DATA offset
mov %fs:dtv, %rax
mov tls(%rax), %rax
mov \offset(%rax), %rax
.endm
|
GeminiCarrie/rust-sgx-sdk | 1,259 | sgx_trts/src/inst/sim/enclu.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "enclu.S"
.macro ENCLU
cmp $SE_EEXIT, %rax
jne 1f
/* if leaf is EEXIT, xbp and xsp need to be passed by xdx and xcx */
mov %rbp, %rdx
mov %rsp, %rcx
1:
push %rdi
push %rsi
push %rdx
push %rcx
push %rbx
push %rax
pop %rdi
pop %rsi
pop %rdx
pop %rcx
pop %r8
pop %r9
.type se3,@function
.protected se3
call se3
.endm |
GeminiCarrie/rust-sgx-sdk | 1,312 | sgx_trts/src/inst/sim/xsave_mask.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "xsave_mask.S"
.section .nipd,"aw"
XSAVE_MASK_LOW:
.int -1
.section .nipd,"aw"
XSAVE_MASK_HIGH:
.int -1
.macro SET_XSAVE_MASK
lea_pic XSAVE_MASK_LOW, %rax
lea_pic XSAVE_MASK_HIGH, %rdx
movl (%rax), %eax
movl (%rdx), %edx
.endm
.section .text,"ax",@progbits
DECLARE_LOCAL_FUNC set_xsave_mask_low
lea_pic XSAVE_MASK_LOW, %rax
movl %edi, (%rax)
ret
DECLARE_LOCAL_FUNC set_xsave_mask_high
lea_pic XSAVE_MASK_HIGH, %rax
movl %edi, (%rax)
ret
|
GeminiCarrie/rust-sgx-sdk | 2,664 | sgx_libc/sgx_tlibc_sys/tlibc/gen/alloca.S | /* $OpenBSD: alloca.S,v 1.6 2005/08/07 11:30:38 espie Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* like alloc, but automatic free in return */
#include "sgx_cet.h"
#define _C_LABEL(x) x
#ifdef __i386__
#define _ALIGN_TEXT .align 2, 0x90
#else /* __x86_64__ */
#define _ALIGN_TEXT .align 16, 0x90
#endif
#define _ENTRY(x) .text; _ALIGN_TEXT; .globl x; .type x,@function; x:
#define ENTRY(y) _ENTRY(_C_LABEL(y));
ENTRY(alloca)
_CET_ENDBR
#ifdef __i386__
popl %edx /* pop return addr */
popl %eax /* pop amount to allocate */
movl %esp,%ecx
addl $3,%eax /* round up to next word */
andl $-4,%eax
subl %eax,%esp
movl %esp,%eax /* base of newly allocated space */
pushl 8(%ecx) /* copy possible saved registers */
pushl 4(%ecx)
pushl 0(%ecx)
pushl %eax /* dummy to pop at callsite */
_CET_NOTRACK jmp *%edx /* "return" */
#else /* __x86_64__ */
popq %rdx
movq %rsp,%rcx
addq $15,%rdi /* round up to 16 bytes */
andq $~15,%rdi
subq %rdi,%rsp
movq %rsp,%rax
_CET_NOTRACK jmp *%rdx
#endif
|
GeminiCarrie/rust-sgx-sdk | 8,355 | sgx_libc/sgx_tlibc_sys/tlibc/setjmp/_setjmp.S | /* $NetBSD: _setjmp.S,v 1.9 2014/05/23 02:34:19 uebayasi Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)_setjmp.s 5.1 (Berkeley) 4/23/90
*/
.file "_setjmp.S"
#include "sgx_cet.h"
#include "trts_inst.h"
#if defined(LIBC_SCCS)
RCSID("$NetBSD: _setjmp.S,v 1.9 2014/05/23 02:34:19 uebayasi Exp $")
#endif
#if defined(__x86_64) || defined(__x86_64__)
#define LINUX64
#elif defined(__i386) || defined(__i386__)
#define LINUX32
#else
# error unknown platform!
#endif
/*
* C library -- setjmp, longjmp
*
* longjmp(a,v)
* will generate a "return(v)" from the last call to
* setjmp(a)
* by restoring registers from the stack.
* The previous signal state is NOT restored.
*/
/*#include "../trts/linux/trts_pic.h"*/
.text
#ifdef LINUX32
#define _JB_PC 0
#define _JB_EBX 1
#define _JB_ESP 2
#define _JB_EBP 3
#define _JB_ESI 4
#define _JB_EDI 5
#define SE_WORDSIZE 4
#endif
#ifdef LINUX64
#define _JB_RBX 0
#define _JB_RBP 1
#define _JB_R12 2
#define _JB_R13 3
#define _JB_R14 4
#define _JB_R15 5
#define _JB_RSP 6
#define _JB_PC 7
#define SE_WORDSIZE 8
#endif
.macro PUSHAQ
push %rax
push %rbx
push %rcx
push %rdx
push %rsi
push %rdi
push %r8
push %r9
push %r10
push %r11
push %r12
push %r13
push %r14
push %r15
.endm
.macro POPAQ
pop %r15
pop %r14
pop %r13
pop %r12
pop %r11
pop %r10
pop %r9
pop %r8
pop %rdi
pop %rsi
pop %rdx
pop %rcx
pop %rbx
pop %rax
.endm
.global setjmp
.type setjmp @function
setjmp:
_CET_ENDBR
#ifdef LINUX32
PUSHAL
/* check the buf is within the enclave */
movl (SE_WORDSIZE + 8*SE_WORDSIZE)(%esp), %eax
pushl $SE_WORDSIZE
pushl %eax
call sgx_is_within_enclave
cmpl $0, %eax
jz .crash
addl $(2*SE_WORDSIZE), %esp
POPAL
/* store the registers */
movl SE_WORDSIZE(%esp),%eax
movl 0(%esp),%edx
movl %edx, (_JB_PC * SE_WORDSIZE)(%eax) /* rta */
movl %ebx, (_JB_EBX * SE_WORDSIZE)(%eax)
movl %esp, (_JB_ESP * SE_WORDSIZE)(%eax)
movl %ebp, (_JB_EBP * SE_WORDSIZE)(%eax)
movl %esi, (_JB_ESI * SE_WORDSIZE)(%eax)
movl %edi, (_JB_EDI * SE_WORDSIZE)(%eax)
movl %eax, %edx
/* use statck_guard as cookie*/
call get_stack_guard
xchg %eax, %edx
xorl %edx, (_JB_PC * SE_WORDSIZE)(%eax)
xorl %edx, (_JB_EBX * SE_WORDSIZE)(%eax)
xorl %edx, (_JB_ESP * SE_WORDSIZE)(%eax)
xorl %edx, (_JB_EBP * SE_WORDSIZE)(%eax)
xorl %edx, (_JB_ESI * SE_WORDSIZE)(%eax)
xorl %edx, (_JB_EDI * SE_WORDSIZE)(%eax)
#endif
#ifdef LINUX64
PUSHAQ
/* check the buf is within the enclave */
movq $SE_WORDSIZE, %rsi
call sgx_is_within_enclave
cmpl $0, %eax
jz .crash
POPAQ
/* store the registers */
movq (%rsp),%r11
movq %rbx, (_JB_RBX * SE_WORDSIZE)(%rdi)
movq %rbp, (_JB_RBP * SE_WORDSIZE)(%rdi)
movq %r12, (_JB_R12 * SE_WORDSIZE)(%rdi)
movq %r13, (_JB_R13 * SE_WORDSIZE)(%rdi)
movq %r14, (_JB_R14 * SE_WORDSIZE)(%rdi)
movq %r15, (_JB_R15 * SE_WORDSIZE)(%rdi)
movq %rsp, (_JB_RSP * SE_WORDSIZE)(%rdi)
movq %r11, (_JB_PC * SE_WORDSIZE)(%rdi)
/* use statck_guard as cookie*/
call get_stack_guard
xorq %rax, (_JB_RBX * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_RBP * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_R12 * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_R13 * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_R14 * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_R15 * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_RSP * SE_WORDSIZE)(%rdi)
xorq %rax, (_JB_PC * SE_WORDSIZE)(%rdi)
#endif
xorl %eax,%eax
ret
.crash:
ud2
.global longjmp
.type longjmp @function
longjmp:
_CET_ENDBR
#ifdef LINUX32
PUSHAL
/* check the buf is within the enclave */
movl (SE_WORDSIZE + 8*SE_WORDSIZE)(%esp), %eax
pushl $SE_WORDSIZE
pushl %eax
call sgx_is_within_enclave
cmpl $0, %eax
jz .crash
addl $(2*SE_WORDSIZE), %esp
/* restore xsp */
movl (SE_WORDSIZE + 8*SE_WORDSIZE)(%esp), %eax
movl (_JB_ESP * SE_WORDSIZE)(%eax), %ebx
call get_stack_guard
xorl %eax, %ebx
pushl %ebx
/* check restored esp is on current statck */
call is_valid_sp
cmpl $0, %eax
jz .crash
popl %ebx
POPAL
/* restore the registers */
movl SE_WORDSIZE(%esp),%edx
movl (SE_WORDSIZE*2)(%esp),%eax
pushl %eax
movl (_JB_PC * SE_WORDSIZE)(%edx),%ecx
movl (_JB_EBX * SE_WORDSIZE)(%edx),%ebx
pushl (_JB_ESP * SE_WORDSIZE)(%edx)
pushl (_JB_EBP * SE_WORDSIZE)(%edx)
movl (_JB_ESI * SE_WORDSIZE)(%edx),%esi
movl (_JB_EDI * SE_WORDSIZE)(%edx),%edi
call get_stack_guard
xorl %eax, %ecx
xorl %eax, %ebx
movl (0)(%esp), %edx
xorl %eax, %edx
movl %edx, (0)(%esp)
movl (SE_WORDSIZE)(%esp), %edx
xorl %eax, %edx
movl %edx, (SE_WORDSIZE)(%esp)
xorl %eax, %esi
xorl %eax, %edi
popl %ebp
popl %edx
movl %ecx, (0)(%edx)
popl %eax
movl %edx, %esp
#endif
#ifdef LINUX64
PUSHAQ
pushq %rdi
/* check the buf is within the enclave */
movq $SE_WORDSIZE, %rsi
call sgx_is_within_enclave
cmpl $0, %eax
jz .crash
popq %rdi
/* restore xsp*/
movq (_JB_RSP * SE_WORDSIZE)(%rdi),%rdx
call get_stack_guard
xorq %rax, %rdx
pushq %rdx
/* check restored rsp is on current statck */
popq %rdi
call is_valid_sp
cmpl $0, %eax
jz .crash
POPAQ
/* restore the registers */
movl %esi,%eax
movq (_JB_RBX * SE_WORDSIZE)(%rdi),%rbx
movq (_JB_RBP * SE_WORDSIZE)(%rdi),%rsi
movq (_JB_R12 * SE_WORDSIZE)(%rdi),%r12
movq (_JB_R13 * SE_WORDSIZE)(%rdi),%r13
movq (_JB_R14 * SE_WORDSIZE)(%rdi),%r14
movq (_JB_R15 * SE_WORDSIZE)(%rdi),%r15
movq (_JB_RSP * SE_WORDSIZE)(%rdi),%rdx
movq (_JB_PC * SE_WORDSIZE)(%rdi),%rcx
pushq %rax
call get_stack_guard
xorq %rax, %rbx
xorq %rax, %rsi
xorq %rax, %r12
xorq %rax, %r13
xorq %rax, %r14
xorq %rax, %r15
xorq %rax, %rdx
xorq %rax, %rcx
popq %rax
movq %rsi, %rbp
movq %rcx, 0(%rdx)
movq %rdx, %rsp
#endif
testl %eax,%eax
jnz 1f
incl %eax
1: ret
.weak _setjmp
_setjmp=setjmp
.weak _longjmp
_longjmp=longjmp
|
GeminiCarrie/rust-sgx-sdk | 22,551 | sgx_libc/sgx_tlibc_sys/tlibc/math/libm_logl_k80.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "libm_logl_k80.c"
.text
..TXTST0:
# -- Begin __libm_log_k80
.text
.align 16,0x90
.globl __libm_log_k80
__libm_log_k80:
# parameter 1: %rdi
# parameter 2: %rsi
..B1.1:
.cfi_startproc
..___tag_value___libm_log_k80.1:
..L2:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r12
movq %rdi, %r13
movq %r12, %rdi
movq %fs:40, %rax
xorq %rsp, %rax
movq %rax, 80(%rsp)
..___tag_value___libm_log_k80.8:
call __libm_normalizel_k80@PLT
..___tag_value___libm_log_k80.9:
..B1.2:
fldt (%r12)
fldt 16(%r12)
movl 32(%r12), %eax
cmpl $-1, %eax
je ..B1.15
..B1.3:
movl %eax, 16(%rsp)
fildl 16(%rsp)
fstpt (%rsp)
..B1.4:
addq $-32, %rsp
.cfi_def_cfa_offset 144
lea 48(%rsp), %rdi
fxch %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
..___tag_value___libm_log_k80.11:
call __libm_logl_k80@PLT
..___tag_value___libm_log_k80.12:
..B1.18:
addq $32, %rsp
.cfi_def_cfa_offset 112
..B1.5:
fldt 16(%rsp)
lea _LN2_K80(%rip), %rax
lea 16+_LN2_K80(%rip), %rdx
fmul %st(1), %st
fstpt 16(%rsp)
fldt 16(%rsp)
fldt 32(%rsp)
fmulp %st, %st(2)
movzwl 24(%rsp), %esi
andl $32767, %esi
fxch %st(1)
fstpt 32(%rsp)
fldt 32(%rsp)
fldt (%rax)
fldt (%rsp)
fmul %st, %st(1)
fxch %st(1)
fstpt 48(%rsp)
fldt 48(%rsp)
fld %st(0)
movzwl 56(%rsp), %ecx
fadd %st(4), %st
fldt (%rdx)
andl $32767, %ecx
fmulp %st, %st(3)
cmpl %esi, %ecx
fxch %st(2)
fstpt 64(%rsp)
fldt 64(%rsp)
movl $0, 32(%r13)
jg ..B1.10
..B1.6:
jne ..B1.11
..B1.7:
movl 52(%rsp), %eax
movl 20(%rsp), %edx
cmpl %edx, %eax
ja ..B1.10
..B1.8:
jne ..B1.11
..B1.9:
movl 48(%rsp), %eax
cmpl 16(%rsp), %eax
jbe ..B1.11
..B1.10:
fxch %st(1)
fsub %st(2), %st
faddp %st, %st(4)
fxch %st(2)
faddp %st, %st(3)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
jmp ..B1.12
..B1.11:
fxch %st(2)
fsubr %st, %st(4)
fxch %st(1)
faddp %st, %st(4)
fxch %st(1)
faddp %st, %st(3)
fxch %st(2)
faddp %st, %st(1)
..B1.12:
fld %st(1)
fadd %st(1), %st
fstpt (%r13)
fldt (%r13)
fsubrp %st, %st(2)
faddp %st, %st(1)
fstpt 16(%r13)
movq 80(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B1.14
..B1.13:
addq $88, %rsp
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 112
.cfi_offset 12, -16
.cfi_offset 13, -24
..B1.14:
call __stack_chk_fail@PLT
..B1.15:
lea _zeros(%rip), %rax
lea halfs(%rip), %rdx
fldl (%rax)
fstpt (%rsp)
fldt (%rdx)
fmul %st, %st(2)
fmulp %st, %st(1)
jmp ..B1.4
.align 16,0x90
.cfi_endproc
.type __libm_log_k80,@function
.size __libm_log_k80,.-__libm_log_k80
.data
# -- End __libm_log_k80
.text
# -- Begin __libm_logl_k80
.text
.align 16,0x90
.globl __libm_logl_k80
__libm_logl_k80:
# parameter 1: 8 + %rsp
# parameter 2: 24 + %rsp
# parameter 3: %rdi
..B2.1:
.cfi_startproc
..___tag_value___libm_logl_k80.23:
..L24:
fldt 8(%rsp)
movzbl 17(%rsp), %r9d
andl $128, %r9d
shrl $7, %r9d
movzwl 16(%rsp), %ecx
movl %ecx, %eax
movl %r9d, %r8d
andl $32767, %eax
shll $15, %r8d
movl 12(%rsp), %edx
orl %eax, %r8d
movl %edx, %esi
shll $16, %r8d
shrl $16, %esi
orl %esi, %r8d
fstpt -24(%rsp)
fldt -24(%rsp)
cmpl $2147450880, %r8d
fldt 24(%rsp)
jae ..B2.14
..B2.2:
lea -1073674240(%r8), %esi
cmpl $36864, %esi
ja ..B2.8
..B2.3:
addl $-1073676287, %r8d
cmpl $32769, %r8d
ja ..B2.7
..B2.4:
lea _ones(%rip), %rax
fldl (%rax)
fucomi %st(2), %st
jne ..B2.6
jp ..B2.6
..B2.5:
lea _zeros(%rip), %rax
fldl (%rax)
fucomi %st(2), %st
jp ..B2.27
je ..B2.23
..B2.27:
fstp %st(0)
..B2.6:
fld %st(2)
lea 48+_Q1(%rip), %rax
lea 16+_Q1(%rip), %rdx
lea 32+_Q1(%rip), %rcx
lea _Q1(%rip), %rsi
fsub %st(1), %st
fld %st(1)
fadd %st(1), %st
fsubrp %st, %st(4)
faddp %st, %st(3)
fld %st(1)
fadd %st(3), %st
fld %st(0)
fxch %st(1)
fsub %st, %st(4)
fxch %st(4)
fsubrp %st, %st(3)
fadd %st(2), %st
fld %st(0)
fmul %st(1), %st
fxch %st(1)
fstpt -24(%rsp)
fldt -24(%rsp)
fldt (%rax)
fmul %st(2), %st
fldt (%rdx)
faddp %st, %st(1)
fmul %st(2), %st
fmulp %st, %st(1)
fldt (%rcx)
fmul %st(2), %st
fldt (%rsi)
faddp %st, %st(1)
fmulp %st, %st(2)
faddp %st, %st(1)
fld %st(3)
fadd %st(1), %st
fstpt (%rdi)
fldt (%rdi)
fsubrp %st, %st(4)
faddp %st, %st(3)
fxch %st(2)
faddp %st, %st(1)
fstpt 16(%rdi)
ret
..B2.7:
lea 8+_ones(%rip), %rax
fld %st(1)
lea _TWO_52H(%rip), %rdx
lea 208+_Q2(%rip), %rcx
lea 176+_Q2(%rip), %rsi
lea 144+_Q2(%rip), %r8
lea 112+_Q2(%rip), %r9
lea 80+_Q2(%rip), %r10
fldl (%rax)
lea 48+_Q2(%rip), %r11
lea 16+_Q2(%rip), %rax
fadd %st, %st(1)
fld %st(1)
fxch %st(1)
fsub %st(2), %st
faddp %st, %st(4)
fxch %st(2)
faddp %st, %st(3)
fxch %st(1)
fadd %st(2), %st
fld %st(0)
fld %st(1)
fxch %st(2)
fstpt -24(%rsp)
fldt -24(%rsp)
fsubr %st, %st(3)
fxch %st(4)
faddp %st, %st(3)
fldl (%rdx)
fmul %st(4), %st
lea 192+_Q2(%rip), %rdx
fadd %st, %st(1)
fsubrp %st, %st(1)
fld %st(0)
fld %st(1)
fmul %st(2), %st
fxch %st(2)
fsubr %st, %st(3)
fxch %st(4)
faddp %st, %st(3)
fxch %st(2)
fstpt -56(%rsp)
fldt -56(%rsp)
fmul %st, %st(2)
fmul %st(4), %st
faddp %st, %st(2)
fld %st(1)
fadd %st(1), %st
fldt (%rcx)
fmul %st(1), %st
lea 160+_Q2(%rip), %rcx
fldt (%rsi)
lea 128+_Q2(%rip), %rsi
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r8)
lea 96+_Q2(%rip), %r8
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r9)
lea 64+_Q2(%rip), %r9
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r10)
lea 32+_Q2(%rip), %r10
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r11)
lea _Q2(%rip), %r11
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rax)
lea 240+_Q2(%rip), %rax
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rdx)
lea 224+_Q2(%rip), %rdx
fmul %st(2), %st
fldt (%rcx)
faddp %st, %st(1)
fmul %st(2), %st
fldt (%rsi)
faddp %st, %st(1)
fmul %st(2), %st
fldt (%r8)
faddp %st, %st(1)
fmul %st(2), %st
fldt (%r9)
faddp %st, %st(1)
fmul %st(2), %st
fldt (%r10)
faddp %st, %st(1)
fmulp %st, %st(2)
fldt (%r11)
faddp %st, %st(2)
fxch %st(5)
fmulp %st, %st(1)
faddp %st, %st(4)
fldt (%rax)
fmul %st, %st(2)
fxch %st(2)
faddp %st, %st(4)
fmulp %st, %st(1)
fld %st(1)
fldt (%rdx)
fld %st(0)
fmul %st(4), %st
faddp %st, %st(3)
fldt -56(%rsp)
fmul %st, %st(1)
fxch %st(1)
faddp %st, %st(5)
fxch %st(1)
fmul %st(4), %st
fxch %st(2)
fadd %st, %st(4)
fxch %st(1)
fmul %st, %st(4)
fxch %st(4)
faddp %st, %st(2)
fxch %st(1)
faddp %st, %st(3)
fmul %st(1), %st
fld %st(1)
fadd %st(1), %st
fsubr %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fld %st(0)
fadd %st(2), %st
fstpt (%rdi)
fldt (%rdi)
fsubrp %st, %st(1)
faddp %st, %st(1)
fstpt 16(%rdi)
lea _ones(%rip), %rdi
fldl (%rdi)
ret
..B2.8:
lea _zeros(%rip), %r8
movl $-16383, %esi
testl %eax, %eax
fldl (%r8)
movsd (%r8), %xmm0
jne ..B2.11
..B2.9:
lea _TWO_75(%rip), %rax
movl $-16458, %esi
fldl (%rax)
fmul %st, %st(3)
fxch %st(3)
fucomi %st(1), %st
fxch %st(3)
fmulp %st, %st(2)
jp ..B2.10
je ..B2.24
..B2.10:
fxch %st(2)
fstpt -24(%rsp)
fldt -24(%rsp)
movzwl -16(%rsp), %ecx
movl %ecx, %eax
movl -20(%rsp), %edx
andl $32767, %eax
fxch %st(2)
..B2.11:
fstp %st(2)
addl %eax, %esi
fucomi %st(1), %st
fxch %st(1)
fstp %st(0)
jp ..B2.12
je ..B2.13
..B2.12:
fstpt -56(%rsp)
movzwl -48(%rsp), %r8d
movl %r8d, %r9d
subl %eax, %r8d
andl $-32768, %r9d
addl $16383, %r8d
andl $32767, %r8d
orl %r8d, %r9d
movw %r9w, -48(%rsp)
fldt -56(%rsp)
..B2.13:
shrl $23, %edx
andl $-32768, %ecx
movzbl %dl, %eax
lea _TWO_32H(%rip), %rdx
orl $-49153, %ecx
lea 8+_ones(%rip), %r8
movw %cx, -16(%rsp)
lea 48+_P(%rip), %r9
fldt -24(%rsp)
lea 16+_P(%rip), %r10
fld %st(0)
lea 64+_P(%rip), %r11
fldl (%rdx)
lea 32+_P(%rip), %rdx
movq __libm_rcp_table_256@GOTPCREL(%rip), %rcx
fadd %st, %st(1)
movl %esi, -40(%rsp)
lea 80+_P(%rip), %rsi
fsubrp %st, %st(1)
fsubr %st, %st(1)
flds (%rcx,%rax,4)
fmul %st, %st(1)
fmul %st, %st(2)
fmulp %st, %st(3)
fxch %st(2)
fstpt -56(%rsp)
fldt -56(%rsp)
lea _P(%rip), %rcx
shlq $4, %rax
faddp %st, %st(1)
fldl (%r8)
fld %st(0)
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
faddp %st, %st(1)
fld %st(1)
fadd %st(1), %st
fld %st(0)
fmul %st(1), %st
fxch %st(1)
fstpt -24(%rsp)
fldt -24(%rsp)
fildl -40(%rsp)
fldt (%rsi)
fmul %st(3), %st
fldt (%r9)
movq __libm_logl_table_256@GOTPCREL(%rip), %rsi
faddp %st, %st(1)
fmul %st(3), %st
fldt (%r10)
faddp %st, %st(1)
fmul %st(3), %st
fmulp %st, %st(2)
fldt (%r11)
fmul %st(3), %st
fldt (%rdx)
faddp %st, %st(1)
fmul %st(3), %st
fldt (%rcx)
faddp %st, %st(1)
fmulp %st, %st(3)
fxch %st(2)
faddp %st, %st(1)
faddp %st, %st(2)
fldt .L_2il0floatpacket.2(%rip)
fmul %st(1), %st
fldt .L_2il0floatpacket.3(%rip)
fmulp %st, %st(2)
faddl 8(%rsi,%rax)
faddp %st, %st(2)
faddl (%rax,%rsi)
faddp %st, %st(2)
fld %st(1)
fadd %st(1), %st
fstpt (%rdi)
fldt (%rdi)
fsubrp %st, %st(2)
faddp %st, %st(1)
fstpt 16(%rdi)
lea _ones(%rip), %rdi
fldl (%rdi)
ret
..B2.14:
fstp %st(0)
testl %r9d, %r9d
jne ..B2.16
..B2.15:
lea _ones(%rip), %rax
lea _zeros(%rip), %rdx
fldl (%rax)
fmul %st, %st(1)
movsd (%rdx), %xmm1
fxch %st(1)
jmp ..B2.21
..B2.16:
cmpl $32767, %eax
je ..B2.22
..B2.17:
fstp %st(0)
testl %eax, %eax
jne ..B2.20
..B2.18:
cmpq $0, -24(%rsp)
jne ..B2.20
..B2.19:
lea _zeros(%rip), %rax
lea 8+_ones(%rip), %rdx
lea _ones(%rip), %rcx
movsd (%rax), %xmm1
fldl (%rcx)
movsd (%rdx), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, -40(%rsp)
fldl -40(%rsp)
jmp ..B2.21
..B2.20:
lea _zeros(%rip), %rax
lea _infs(%rip), %rdx
lea _ones(%rip), %rcx
movsd (%rax), %xmm1
fldl (%rcx)
movsd (%rdx), %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, -40(%rsp)
fldl -40(%rsp)
..B2.21:
movsd %xmm1, -40(%rsp)
fstpt (%rdi)
fldl -40(%rsp)
fstpt 16(%rdi)
ret
..B2.22:
movq $0x8000000000000000, %rax
cmpq -24(%rsp), %rax
jne ..B2.15
jmp ..B2.28
..B2.23:
fstp %st(1)
fstp %st(2)
fstp %st(0)
fstpt (%rdi)
fldt (%rdi)
fld %st(0)
fxch %st(1)
fstpt 16(%rdi)
ret
..B2.24:
fstp %st(2)
fstp %st(0)
lea 8+_ones(%rip), %rax
lea _ones(%rip), %rdx
fstpt 16(%rdi)
movsd (%rax), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, -40(%rsp)
fldl -40(%rsp)
fstpt (%rdi)
fldl (%rdx)
ret
..B2.28:
fstp %st(0)
jmp ..B2.20
.align 16,0x90
.cfi_endproc
.type __libm_logl_k80,@function
.size __libm_logl_k80,.-__libm_logl_k80
.data
# -- End __libm_logl_k80
.section .rodata, "a"
.align 16
.align 16
halfs:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xfe,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xfe,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type halfs,@object
.size halfs,32
.align 16
.L_2il0floatpacket.2:
.byte 0x00,0x30,0x71,0xd8,0x50,0x19,0xc2,0xb8,0xdc,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.2,@object
.size .L_2il0floatpacket.2,16
.align 16
.L_2il0floatpacket.3:
.byte 0x00,0x00,0x00,0x00,0xf8,0x17,0x72,0xb1,0xfe,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.3,@object
.size .L_2il0floatpacket.3,16
.align 4
_zeros:
.long 0
.long 0
.long 0
.long 2147483648
.type _zeros,@object
.size _zeros,16
.align 4
_ones:
.long 0
.long 1072693248
.long 0
.long 3220176896
.type _ones,@object
.size _ones,16
.align 4
_TWO_52H:
.long 0
.long 1127743488
.type _TWO_52H,@object
.size _TWO_52H,8
.align 4
_TWO_75:
.long 0
.long 1151336448
.long 0
.long 994050048
.type _TWO_75,@object
.size _TWO_75,16
.align 4
_TWO_32H:
.long 0
.long 1106771968
.type _TWO_32H,@object
.size _TWO_32H,8
.align 4
_infs:
.long 0
.long 2146435072
.long 0
.long 4293918720
.type _infs,@object
.size _infs,16
.align 2
_LN2_K80:
.word 0
.word 0
.word 6136
.word 45426
.word 16382
.word 0
.word 0
.word 0
.word 12704
.word 55409
.word 6480
.word 47298
.word 49116
.word 0
.word 0
.word 0
.type _LN2_K80,@object
.size _LN2_K80,32
.align 2
_Q1:
.word 0
.word 0
.word 0
.word 32768
.word 49150
.word 0
.word 0
.word 0
.word 5458
.word 43692
.word 43690
.word 43690
.word 16381
.word 0
.word 0
.word 0
.word 44682
.word 49156
.word 65535
.word 65535
.word 49148
.word 0
.word 0
.word 0
.word 63914
.word 24446
.word 52434
.word 52426
.word 16380
.word 0
.word 0
.word 0
.type _Q1,@object
.size _Q1,64
.align 2
_Q2:
.word 58950
.word 11767
.word 59949
.word 40744
.word 49076
.word 0
.word 0
.word 0
.word 44486
.word 43690
.word 43690
.word 43690
.word 16369
.word 0
.word 0
.word 0
.word 65514
.word 65535
.word 65535
.word 65535
.word 49148
.word 0
.word 0
.word 0
.word 49718
.word 52428
.word 52428
.word 52428
.word 16380
.word 0
.word 0
.word 0
.word 36693
.word 43691
.word 43690
.word 43690
.word 49148
.word 0
.word 0
.word 0
.word 41156
.word 18852
.word 9362
.word 37449
.word 16380
.word 0
.word 0
.word 0
.word 14101
.word 65290
.word 65535
.word 65535
.word 49147
.word 0
.word 0
.word 0
.word 21744
.word 48151
.word 14557
.word 58254
.word 16379
.word 0
.word 0
.word 0
.word 57454
.word 983
.word 52353
.word 52428
.word 49147
.word 0
.word 0
.word 0
.word 54021
.word 59409
.word 39452
.word 47662
.word 16379
.word 0
.word 0
.word 0
.word 35608
.word 4659
.word 11214
.word 43692
.word 49147
.word 0
.word 0
.word 0
.word 35524
.word 31332
.word 8749
.word 40326
.word 16379
.word 0
.word 0
.word 0
.word 54832
.word 20873
.word 17674
.word 36915
.word 49147
.word 0
.word 0
.word 0
.word 48567
.word 9481
.word 46911
.word 55870
.word 16378
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 32768
.word 49150
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 43680
.word 16381
.word 0
.word 0
.word 0
.type _Q2,@object
.size _Q2,256
.align 2
_P:
.word 65
.word 0
.word 0
.word 32768
.word 49150
.word 0
.word 0
.word 0
.word 44010
.word 43690
.word 43690
.word 43690
.word 16381
.word 0
.word 0
.word 0
.word 58670
.word 61414
.word 65535
.word 65535
.word 49148
.word 0
.word 0
.word 0
.word 24905
.word 46201
.word 52428
.word 52428
.word 16380
.word 0
.word 0
.word 0
.word 57053
.word 27587
.word 64478
.word 43690
.word 49148
.word 0
.word 0
.word 0
.word 41508
.word 48914
.word 32459
.word 37449
.word 16380
.word 0
.word 0
.word 0
.type _P,@object
.size _P,96
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
GeminiCarrie/rust-sgx-sdk | 4,736 | sgx_libc/sgx_tlibc_sys/tlibc/math/libm_normalizel_k80.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "libm_normalizel_k80.c"
.text
..TXTST0:
# -- Begin __libm_normalizel_k80
.text
.align 16,0x90
.globl __libm_normalizel_k80
__libm_normalizel_k80:
# parameter 1: %rdi
..B1.1:
.cfi_startproc
..___tag_value___libm_normalizel_k80.1:
..L2:
cmpl $0, 4(%rdi)
jne ..B1.3
..B1.2:
cmpl $0, (%rdi)
je ..B1.14
..B1.3:
movzwl 8(%rdi), %eax
movl %eax, %esi
andl $32767, %esi
cmpl $32767, %esi
je ..B1.14
..B1.4:
testl %esi, %esi
jle ..B1.16
..B1.5:
andl $-32768, %eax
addl $-16383, %esi
orl $-49153, %eax
..B1.6:
movw %ax, 8(%rdi)
cmpl $0, 20(%rdi)
jne ..B1.8
..B1.7:
cmpl $0, 16(%rdi)
je ..B1.13
..B1.8:
movzwl 24(%rdi), %edx
movl %edx, %ecx
andl $32767, %ecx
jle ..B1.15
..B1.9:
andl $-32768, %edx
addl $-16383, %ecx
orl $-49153, %edx
..B1.10:
lea -256(%rsi), %eax
cmpl %eax, %ecx
jle ..B1.12
..B1.11:
subl %esi, %ecx
andl $-32768, %edx
addl $16383, %ecx
andl $32767, %ecx
orl %ecx, %edx
movw %dx, 24(%rdi)
jmp ..B1.13
..B1.12:
lea zeros(%rip), %rax
fldt (%rax)
fstpt 16(%rdi)
..B1.13:
addl %esi, 32(%rdi)
..B1.14:
ret
..B1.15:
fldt 16(%rdi)
lea _CONSTANTS(%rip), %rax
fldt (%rax)
fmulp %st, %st(1)
fstpt 16(%rdi)
movzwl 24(%rdi), %edx
movl %edx, %ecx
andl $32767, %ecx
andl $-32768, %edx
addl $-16639, %ecx
orl $-49153, %edx
jmp ..B1.10
..B1.16:
fldt (%rdi)
lea _CONSTANTS(%rip), %rax
fldt (%rax)
fmulp %st, %st(1)
fstpt (%rdi)
movzwl 8(%rdi), %eax
movl %eax, %esi
andl $32767, %esi
andl $-32768, %eax
addl $-16639, %esi
orl $-49153, %eax
jmp ..B1.6
.align 16,0x90
.cfi_endproc
.type __libm_normalizel_k80,@function
.size __libm_normalizel_k80,.-__libm_normalizel_k80
.data
# -- End __libm_normalizel_k80
.section .rodata, "a"
.align 16
.align 16
zeros:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
.type zeros,@object
.size zeros,32
.align 2
_CONSTANTS:
.word 0
.word 0
.word 0
.word 32768
.word 16639
.word 0
.word 0
.word 0
.type _CONSTANTS,@object
.size _CONSTANTS,16
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
GeminiCarrie/rust-sgx-sdk | 3,808 | sgx_libc/sgx_tlibc_sys/tlibc/math/expf_table.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "expf_table.c"
.section .rodata, "a"
.align 8
.align 8
.globl __libm_expf_table_64
__libm_expf_table_64:
.long 0x667f3bcd,0x3fe6a09e
.long 0x3c651a2f,0x3fe6dfb2
.long 0xe8ec5f74,0x3fe71f75
.long 0x564267c9,0x3fe75feb
.long 0x73eb0187,0x3fe7a114
.long 0x36cf4e62,0x3fe7e2f3
.long 0x994cce13,0x3fe82589
.long 0x9b4492ed,0x3fe868d9
.long 0x422aa0db,0x3fe8ace5
.long 0x99157736,0x3fe8f1ae
.long 0xb0cdc5e5,0x3fe93737
.long 0x9fde4e50,0x3fe97d82
.long 0x82a3f090,0x3fe9c491
.long 0x7b5de565,0x3fea0c66
.long 0xb23e255d,0x3fea5503
.long 0x5579fdbf,0x3fea9e6b
.long 0x995ad3ad,0x3feae89f
.long 0xb84f15fb,0x3feb33a2
.long 0xf2fb5e47,0x3feb7f76
.long 0x904bc1d2,0x3febcc1e
.long 0xdd85529c,0x3fec199b
.long 0x2e57d14b,0x3fec67f1
.long 0xdcef9069,0x3fecb720
.long 0x4a07897c,0x3fed072d
.long 0xdcfba487,0x3fed5818
.long 0x03db3285,0x3feda9e6
.long 0x337b9b5f,0x3fedfc97
.long 0xe78b3ff6,0x3fee502e
.long 0xa2a490da,0x3feea4af
.long 0xee615a27,0x3feefa1b
.long 0x5b6e4540,0x3fef5076
.long 0x819e90d8,0x3fefa7c1
.long 0x00000000,0x3ff00000
.long 0x3e778061,0x3ff02c9a
.long 0xd3158574,0x3ff059b0
.long 0x18759bc8,0x3ff08745
.long 0x6cf9890f,0x3ff0b558
.long 0x32d3d1a2,0x3ff0e3ec
.long 0xd0125b51,0x3ff11301
.long 0xaea92de0,0x3ff1429a
.long 0x3c7d517b,0x3ff172b8
.long 0xeb6fcb75,0x3ff1a35b
.long 0x3168b9aa,0x3ff1d487
.long 0x88628cd6,0x3ff2063b
.long 0x6e756238,0x3ff2387a
.long 0x65e27cdd,0x3ff26b45
.long 0xf51fdee1,0x3ff29e9d
.long 0xa6e4030b,0x3ff2d285
.long 0x0a31b715,0x3ff306fe
.long 0xb26416ff,0x3ff33c08
.long 0x373aa9cb,0x3ff371a7
.long 0x34e59ff7,0x3ff3a7db
.long 0x4c123422,0x3ff3dea6
.long 0x21f72e2a,0x3ff4160a
.long 0x6061892d,0x3ff44e08
.long 0xb5c13cd0,0x3ff486a2
.long 0xd5362a27,0x3ff4bfda
.long 0x769d2ca7,0x3ff4f9b2
.long 0x569d4f82,0x3ff5342b
.long 0x36b527da,0x3ff56f47
.long 0xdd485429,0x3ff5ab07
.long 0x15ad2148,0x3ff5e76f
.long 0xb03a5585,0x3ff6247e
.long 0x82552225,0x3ff66238
.long 0x667f3bcd,0x3ff6a09e
.type __libm_expf_table_64,@object
.size __libm_expf_table_64,520
.data
.section .note.GNU-stack, ""
# End
|
GeminiCarrie/rust-sgx-sdk | 15,471 | sgx_libc/sgx_tlibc_sys/tlibc/math/exp_table.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "exp_table.c"
.section .rodata, "a"
.align 8
.align 8
.globl __libm_exp_hi_table_64
__libm_exp_hi_table_64:
.long 0x667f3c00,0x3fe6a09e
.long 0x3c651a40,0x3fe6dfb2
.long 0xe8ec5f80,0x3fe71f75
.long 0x56426800,0x3fe75feb
.long 0x73eb01c0,0x3fe7a114
.long 0x36cf4e80,0x3fe7e2f3
.long 0x994cce20,0x3fe82589
.long 0x9b449300,0x3fe868d9
.long 0x422aa0e0,0x3fe8ace5
.long 0x99157740,0x3fe8f1ae
.long 0xb0cdc600,0x3fe93737
.long 0x9fde4e60,0x3fe97d82
.long 0x82a3f0a0,0x3fe9c491
.long 0x7b5de580,0x3fea0c66
.long 0xb23e2560,0x3fea5503
.long 0x5579fdc0,0x3fea9e6b
.long 0x995ad3c0,0x3feae89f
.long 0xb84f1600,0x3feb33a2
.long 0xf2fb5e60,0x3feb7f76
.long 0x904bc1e0,0x3febcc1e
.long 0xdd8552a0,0x3fec199b
.long 0x2e57d150,0x3fec67f1
.long 0xdcef9070,0x3fecb720
.long 0x4a078980,0x3fed072d
.long 0xdcfba490,0x3fed5818
.long 0x03db3290,0x3feda9e6
.long 0x337b9b60,0x3fedfc97
.long 0xe78b3ff8,0x3fee502e
.long 0xa2a490e0,0x3feea4af
.long 0xee615a28,0x3feefa1b
.long 0x5b6e4544,0x3fef5076
.long 0x819e90da,0x3fefa7c1
.long 0x00000000,0x3ff00000
.long 0x3e778060,0x3ff02c9a
.long 0xd3158574,0x3ff059b0
.long 0x18759bc8,0x3ff08745
.long 0x6cf9890c,0x3ff0b558
.long 0x32d3d1a0,0x3ff0e3ec
.long 0xd0125b50,0x3ff11301
.long 0xaea92dd8,0x3ff1429a
.long 0x3c7d5178,0x3ff172b8
.long 0xeb6fcb70,0x3ff1a35b
.long 0x3168b9a8,0x3ff1d487
.long 0x88628cd0,0x3ff2063b
.long 0x6e756230,0x3ff2387a
.long 0x65e27cd0,0x3ff26b45
.long 0xf51fdee0,0x3ff29e9d
.long 0xa6e40300,0x3ff2d285
.long 0x0a31b710,0x3ff306fe
.long 0xb26416f0,0x3ff33c08
.long 0x373aa9c0,0x3ff371a7
.long 0x34e59ff0,0x3ff3a7db
.long 0x4c123420,0x3ff3dea6
.long 0x21f72e20,0x3ff4160a
.long 0x60618920,0x3ff44e08
.long 0xb5c13cc0,0x3ff486a2
.long 0xd5362a20,0x3ff4bfda
.long 0x769d2ca0,0x3ff4f9b2
.long 0x569d4f80,0x3ff5342b
.long 0x36b527c0,0x3ff56f47
.long 0xdd485420,0x3ff5ab07
.long 0x15ad2140,0x3ff5e76f
.long 0xb03a5580,0x3ff6247e
.long 0x82552220,0x3ff66238
.long 0x667f3bc0,0x3ff6a09e
.type __libm_exp_hi_table_64,@object
.size __libm_exp_hi_table_64,520
.align 8
.globl __libm_exp_mi_table_64
__libm_exp_mi_table_64:
.long 0x33018800,0xbfd2bec3
.long 0x8735cb80,0xbfd2409b
.long 0x2e274100,0xbfd1c114
.long 0x537b3000,0xbfd14029
.long 0x1829fc80,0xbfd0bdd7
.long 0x92616300,0xbfd03a19
.long 0x9accc780,0xbfcf69d9
.long 0x92edb400,0xbfce5c99
.long 0xf7557c80,0xbfcd4c6a
.long 0x9baa2300,0xbfcc3945
.long 0x3cc8e800,0xbfcb2321
.long 0x8086c680,0xbfca09f5
.long 0xf5703d80,0xbfc8edb9
.long 0x12886a00,0xbfc7ce66
.long 0x37076a80,0xbfc6abf1
.long 0xaa180900,0xbfc58652
.long 0x9a94b100,0xbfc45d81
.long 0x1ec3a800,0xbfc33175
.long 0x34128680,0xbfc20224
.long 0xbed0f880,0xbfc0cf85
.long 0x13d56b00,0xbfbf3321
.long 0x8d417580,0xbfbcc076
.long 0x18837c80,0xbfba46f9
.long 0xafc3b400,0xbfb7c695
.long 0x1822db80,0xbfb53f39
.long 0xe1266b80,0xbfb2b0cf
.long 0x64232500,0xbfb01b46
.long 0x874c0080,0xbfaafd11
.long 0xd5b6f200,0xbfa5b505
.long 0x19ea5d80,0xbfa05e41
.long 0x92375780,0xbf95f134
.long 0x985bc980,0xbf860f9f
.long 0x00000000,0x00000000
.long 0x3bc03000,0x3f864d1f
.long 0xc5615d00,0x3f966c34
.long 0x0eb37900,0x3fa0e8a3
.long 0x9f312180,0x3fa6ab0d
.long 0x5a7a3400,0x3fac7d86
.long 0x0125b500,0x3fb1301d
.long 0xea92dd80,0x3fb429aa
.long 0xc7d51780,0x3fb72b83
.long 0xb6fcb700,0x3fba35be
.long 0x168b9a80,0x3fbd4873
.long 0x43146680,0x3fc031dc
.long 0x73ab1180,0x3fc1c3d3
.long 0x2f13e680,0x3fc35a2b
.long 0xa8fef700,0x3fc4f4ef
.long 0x37201800,0x3fc6942d
.long 0x518db880,0x3fc837f0
.long 0x9320b780,0x3fc9e045
.long 0xb9d54e00,0x3fcb8d39
.long 0xa72cff80,0x3fcd3ed9
.long 0x6091a100,0x3fcef532
.long 0x87dcb880,0x3fd05828
.long 0x81862480,0x3fd13821
.long 0xd704f300,0x3fd21a8a
.long 0x54d8a880,0x3fd2ff6b
.long 0xda74b280,0x3fd3e6c9
.long 0x5a753e00,0x3fd4d0ad
.long 0xdad49f00,0x3fd5bd1c
.long 0x75215080,0x3fd6ac1f
.long 0x56b48500,0x3fd79dbc
.long 0xc0e95600,0x3fd891fa
.long 0x09548880,0x3fd988e2
.long 0x99fcef00,0x3fda8279
.type __libm_exp_mi_table_64,@object
.size __libm_exp_mi_table_64,520
.align 8
.globl __libm_exp_lo_table_64
__libm_exp_lo_table_64:
.long 0x682764c9,0xbcf9b7ba
.long 0x1d341e44,0xbce10ddf
.long 0x1e1a21ea,0xbcd845b9
.long 0xb2ae62dc,0xbcfba048
.long 0x77ee0499,0xbcfc9415
.long 0xfd45ea87,0xbcedefa2
.long 0xeea0a997,0xbcdaea60
.long 0xe26f53db,0xbce37f1b
.long 0xea979b4e,0xbcc29160
.long 0xb17471a2,0xbcd3a8cf
.long 0xe3c0dabf,0xbceb0baf
.long 0x6df06e17,0xbce07461
.long 0x729f1c1b,0xbcdfc707
.long 0x25747355,0xbceb4d65
.long 0xdb71a83c,0xbcbba5ed
.long 0x78840167,0xbc97829b
.long 0xcb2e88ce,0xbce2a178
.long 0xbc6109ae,0xbcc42500
.long 0x4f7e54ac,0xbce91558
.long 0xbe174986,0xbcdbb708
.long 0xa76afb72,0xbcbeeef9
.long 0x200b7c35,0xbcc2d77b
.long 0xd0b85ad9,0xbccbabf0
.long 0x743797aa,0xbcc1cbc3
.long 0xf4a29324,0xbcd1b44b
.long 0xfcb49256,0xbcd51ee7
.long 0x53c612d7,0xbca46973
.long 0xcfeac66e,0xbcad8c2e
.long 0x3179c289,0xbcc9e9c2
.long 0xbcada4a8,0xbc911c05
.long 0xda44ebcf,0xbcbcc583
.long 0x818b4d9c,0xbcad16f5
.long 0x00000000,0x00000000
.long 0x95949ef4,0x3cadcdef
.long 0xa475b465,0x3c8d73e2
.long 0x4bb284ff,0x3c6186be
.long 0xc95b8c21,0x3ccb14c5
.long 0x1727c57b,0x3cc0103a
.long 0xe35db263,0x3ca49d77
.long 0x0650ec96,0x3cdecd04
.long 0xe4628759,0x3cc6e6fb
.long 0x63da4b47,0x3cd4f2da
.long 0xc0144c88,0x3cc3c02d
.long 0xac0a5425,0x3cd8ee3b
.long 0xf5b6382c,0x3ce0cd83
.long 0xce6503a7,0x3cea4af4
.long 0x15f5a24b,0x3cb2c25d
.long 0x3aa6da0f,0x3ce68012
.long 0x56918c17,0x3cd4b7a3
.long 0x0c21b2cd,0x3cee9939
.long 0xaa05e8a9,0x3ce54e28
.long 0x24a67828,0x3cdba86f
.long 0x911f09ec,0x3cc1ada0
.long 0x4b71e7b7,0x3ce3f086
.long 0xde813be0,0x3cea0626
.long 0xa3b69063,0x3cf013c1
.long 0x5ebfb10c,0x3cdc750e
.long 0x62da6a82,0x3cdab4cf
.long 0x3c49d86a,0x3cbdf0a8
.long 0xb004764f,0x3cfa66ec
.long 0x602a323d,0x3ce2b192
.long 0xc9840733,0x3ce0dd37
.long 0xe81bf4b7,0x3cd2c7c3
.long 0x678a6e3d,0x3cd2449f
.long 0x5f626cdd,0x3ce92116
.type __libm_exp_lo_table_64,@object
.size __libm_exp_lo_table_64,520
.align 8
.globl __libm_exp_table_128
__libm_exp_table_128:
.long 0x908b2fb1,0x3def3bcc
.long 0x66600000,0x3fe6a09e
.long 0xdaed5330,0x3dd7b57d
.long 0x75000000,0x3fe6c012
.long 0xc8838b30,0x3dc468bb
.long 0x3c600000,0x3fe6dfb2
.long 0xcf87e1b5,0x3de19483
.long 0xf9400000,0x3fe6ff7d
.long 0xba46e1e6,0x3dd8bee7
.long 0xe8e00000,0x3fe71f75
.long 0xf572693a,0x3dc605ce
.long 0x48a00000,0x3fe73f9a
.long 0xfb74d51a,0x3db33e45
.long 0x56400000,0x3fe75feb
.long 0x619ae028,0x3dee5d3f
.long 0x4fc00000,0x3fe78069
.long 0xafaa2048,0x3dd6030d
.long 0x73e00000,0x3fe7a114
.long 0x7c493344,0x3de0c132
.long 0x01200000,0x3fe7c1ed
.long 0x20ba0574,0x3dde9cc4
.long 0x36c00000,0x3fe7e2f3
.long 0xb60de676,0x3dee1a11
.long 0x54200000,0x3fe80427
.long 0x159f115f,0x3dd99c25
.long 0x99400000,0x3fe82589
.long 0x7297b5cc,0x3dbe3d66
.long 0x46200000,0x3fe8471a
.long 0x03907643,0x3dc24bb2
.long 0x9b400000,0x3fe868d9
.long 0xcca6179c,0x3dd4cd32
.long 0xd9800000,0x3fe88ac7
.long 0xb74f8ab4,0x3dd541b6
.long 0x42200000,0x3fe8ace5
.long 0xef2aa1cd,0x3de5448b
.long 0x16a00000,0x3fe8cf32
.long 0x2b982746,0x3de57736
.long 0x99000000,0x3fe8f1ae
.long 0x88a61b47,0x3de1ffc5
.long 0x0b800000,0x3fe9145b
.long 0xe8a0387e,0x3ddb8bc9
.long 0xb0c00000,0x3fe93737
.long 0xd36906d3,0x3dd0a41d
.long 0xcbc00000,0x3fe95a44
.long 0x8b9e9210,0x3dee4e4f
.long 0x9fc00000,0x3fe97d82
.long 0x74621372,0x3dd40f73
.long 0x70c00000,0x3fe9a0f1
.long 0xe3e23584,0x3dbf8480
.long 0x82a00000,0x3fe9c491
.long 0xc12653c7,0x3db91918
.long 0x19e00000,0x3fe9e863
.long 0xb29ada8c,0x3dede564
.long 0x7b400000,0x3fea0c66
.long 0xb182e3ef,0x3dd45a66
.long 0xec400000,0x3fea309b
.long 0x8b424492,0x3dee255c
.long 0xb2200000,0x3fea5503
.long 0x6f2dfb2b,0x3de0b358
.long 0x13200000,0x3fea799e
.long 0x43eb243c,0x3de9fdbf
.long 0x55600000,0x3fea9e6b
.long 0xc0db966a,0x3de3f379
.long 0xbfc00000,0x3feac36b
.long 0x5e8734d1,0x3dead3ad
.long 0x99400000,0x3feae89f
.long 0x2108559c,0x3ddb6ccb
.long 0x29800000,0x3feb0e07
.long 0xed7fa1cf,0x3dde2bf5
.long 0xb8400000,0x3feb33a2
.long 0x38e20444,0x3dc564e6
.long 0x8de00000,0x3feb5972
.long 0xeaa7b082,0x3deb5e46
.long 0xf2e00000,0x3feb7f76
.long 0x40cb3c6b,0x3da06498
.long 0x30a00000,0x3feba5b0
.long 0x48f741e9,0x3dd783a4
.long 0x90400000,0x3febcc1e
.long 0x8408d702,0x3de71e08
.long 0x5bc00000,0x3febf2c2
.long 0x88832c4b,0x3dc54a70
.long 0xdd800000,0x3fec199b
.long 0x6d14df82,0x3defd07a
.long 0x5fe00000,0x3fec40ab
.long 0x4a2137fd,0x3de7d14b
.long 0x2e400000,0x3fec67f1
.long 0x46b2f122,0x3dcb9ed4
.long 0x94000000,0x3fec8f6d
.long 0x2a0797a4,0x3ddf20d2
.long 0xdce00000,0x3fecb720
.long 0xc44f8959,0x3dedc3f9
.long 0x55400000,0x3fecdf0b
.long 0x343c8bc8,0x3dce25ee
.long 0x4a000000,0x3fed072d
.long 0x15bc2473,0x3ddb13e3
.long 0x08000000,0x3fed2f87
.long 0x25da05af,0x3deba487
.long 0xdce00000,0x3fed5818
.long 0x7709f3a1,0x3dd3072f
.long 0x16c00000,0x3fed80e3
.long 0x708c01a6,0x3deb3285
.long 0x03c00000,0x3feda9e6
.long 0xb695de3c,0x3dab4604
.long 0xf3000000,0x3fedd321
.long 0xb968cac4,0x3deb9b5e
.long 0x33600000,0x3fedfc97
.long 0xa12761fa,0x3de5a128
.long 0x14e00000,0x3fee2646
.long 0x4e7a2603,0x3dd67fec
.long 0xe7800000,0x3fee502e
.long 0x2d522ca1,0x3dcd320d
.long 0xfbc00000,0x3fee7a51
.long 0x163dce86,0x3dc24366
.long 0xa2a00000,0x3feea4af
.long 0x1b60625f,0x3ddccfe1
.long 0x2d800000,0x3feecf48
.long 0x71fd21a9,0x3da5a277
.long 0xee600000,0x3feefa1b
.long 0x9d0d2df8,0x3dd7752e
.long 0x37600000,0x3fef252b
.long 0xce9f096f,0x3ddc8a80
.long 0x5b600000,0x3fef5076
.long 0x8913b4c0,0x3decbe13
.long 0xad800000,0x3fef7bfd
.long 0x2e90a7e7,0x3dee90d8
.long 0x81800000,0x3fefa7c1
.long 0x12eb7496,0x3ddee3e2
.long 0x2b800000,0x3fefd3c2
.long 0x00000000,0x00000000
.long 0x00000000,0x3ff00000
.long 0x6d84a66b,0x3dfb3335
.long 0xa9e00000,0x3ff0163d
.long 0xee6f7cad,0x3df78060
.long 0x3e600000,0x3ff02c9a
.long 0x7ae71f34,0x3decff09
.long 0xe8600000,0x3ff04315
.long 0x3ae7c549,0x3df58574
.long 0xd3000000,0x3ff059b0
.long 0xc6dc403b,0x3dfdf6dd
.long 0x29c00000,0x3ff0706b
.long 0x08c35f26,0x3df59bc8
.long 0x18600000,0x3ff08745
.long 0x14878183,0x3ddbce0d
.long 0xcac00000,0x3ff09e3e
.long 0x6298b92b,0x3df9890f
.long 0x6ce00000,0x3ff0b558
.long 0x407b705c,0x3df247f7
.long 0x2b600000,0x3ff0cc92
.long 0x020742e5,0x3df3d1a2
.long 0x32c00000,0x3ff0e3ec
.long 0xf232091e,0x3dfed31a
.long 0xafe00000,0x3ff0fb66
.long 0xa4ebbf1b,0x3df25b50
.long 0xd0000000,0x3ff11301
.long 0xf72575a6,0x3de86397
.long 0xc0600000,0x3ff12abd
.long 0x66820328,0x3de25bbf
.long 0xaea00000,0x3ff1429a
.long 0x920355cf,0x3dd63944
.long 0xc8a00000,0x3ff15a98
.long 0xdcdf7c8c,0x3dfd517a
.long 0x3c600000,0x3ff172b8
.long 0x777ee173,0x3de91bd3
.long 0x38800000,0x3ff18af9
.long 0x796d31ed,0x3def96ea
.long 0xeb600000,0x3ff1a35b
.long 0x6ac79cad,0x3dd1734e
.long 0x84000000,0x3ff1bbe0
.long 0xf00b7005,0x3de17354
.long 0x31600000,0x3ff1d487
.long 0xb8819ff6,0x3dfcd91c
.long 0x22e00000,0x3ff1ed50
.long 0xdc775815,0x3dc466b1
.long 0x88600000,0x3ff2063b
.long 0x2552fd29,0x3dfddc96
.long 0x91600000,0x3ff21f49
.long 0x66c1fadb,0x3df56238
.long 0x6e600000,0x3ff2387a
.long 0x3582ab7e,0x3df2a63f
.long 0x4fa00000,0x3ff251ce
.long 0x2bd33994,0x3dc3e6e9
.long 0x65e00000,0x3ff26b45
.long 0x96cf15cf,0x3df56380
.long 0xe1e00000,0x3ff284df
.long 0x2c25d15f,0x3dffdee1
.long 0xf5000000,0x3ff29e9d
.long 0xfddea465,0x3dfad98f
.long 0xd0c00000,0x3ff2b87f
.long 0x0024754e,0x3dd00c2d
.long 0xa6e00000,0x3ff2d285
.long 0x11ca0f46,0x3dfe2f56
.long 0xa9200000,0x3ff2ecaf
.long 0x2de8d5a4,0x3df1b715
.long 0x0a200000,0x3ff306fe
.long 0x6a739e38,0x3de9b062
.long 0xfc400000,0x3ff32170
.long 0x32721843,0x3dd05bfd
.long 0xb2600000,0x3ff33c08
.long 0xc9462347,0x3df29ff0
.long 0x5f800000,0x3ff356c5
.long 0xa7145503,0x3dfaa9ca
.long 0x37200000,0x3ff371a7
.long 0x16a72c36,0x3dd76196
.long 0x6d000000,0x3ff38cae
.long 0xa86f24a6,0x3dd67fdb
.long 0x34e00000,0x3ff3a7db
.long 0x84001f23,0x3df3a8e4
.long 0xc3000000,0x3ff3c32d
.long 0x35b41224,0x3df23422
.long 0x4c000000,0x3ff3dea6
.long 0x417ee035,0x3de90037
.long 0x04a00000,0x3ff3fa45
.long 0xf84325b9,0x3df72e29
.long 0x21e00000,0x3ff4160a
.long 0xdc704439,0x3df0a896
.long 0xd9400000,0x3ff431f5
.long 0x3136f40a,0x3db892d0
.long 0x60600000,0x3ff44e08
.long 0x72512f46,0x3dfd0057
.long 0xed000000,0x3ff46a41
.long 0x3c1a3b69,0x3db3cd01
.long 0xb5c00000,0x3ff486a2
.long 0x672d8bcf,0x3df7d3de
.long 0xf0c00000,0x3ff4a32a
.long 0x1d4397b0,0x3df62a27
.long 0xd5200000,0x3ff4bfda
.long 0x63b36ef2,0x3dfddd0d
.long 0x99e00000,0x3ff4dcb2
.long 0xad33d8b7,0x3dfd2ca6
.long 0x76800000,0x3ff4f9b2
.long 0x8225ea59,0x3deecc83
.long 0xa2c00000,0x3ff516da
.long 0xdf0a83c5,0x3dfd4f81
.long 0x56800000,0x3ff5342b
.long 0xc52ec620,0x3dfd920e
.long 0xca400000,0x3ff551a4
.long 0x66ecb004,0x3df527da
.long 0x36a00000,0x3ff56f47
.long 0x252bc2b7,0x3df7c7fd
.long 0xd4800000,0x3ff58d12
.long 0xb192602a,0x3de0a852
.long 0xdd400000,0x3ff5ab07
.long 0x01c4b1b8,0x3df946b7
.long 0x8a400000,0x3ff5c926
.long 0xdd37c984,0x3dea4290
.long 0x15a00000,0x3ff5e76f
.long 0xb076f593,0x3df6dc08
.long 0xb9600000,0x3ff605e1
.long 0xb1f0fa07,0x3dfa5584
.long 0xb0200000,0x3ff6247e
.long 0x8edf0e2a,0x3de9863f
.long 0x34c00000,0x3ff64346
.long 0x9127d9e3,0x3df52224
.long 0x82400000,0x3ff66238
.long 0x1038ae45,0x3de952e6
.long 0xd4400000,0x3ff68155
.long 0x908b2fb1,0x3dff3bcc
.long 0x66600000,0x3ff6a09e
.type __libm_exp_table_128,@object
.size __libm_exp_table_128,2064
.data
.section .note.GNU-stack, ""
# End
|
GeminiCarrie/rust-sgx-sdk | 16,776 | sgx_libc/sgx_tlibc_sys/tlibc/math/logl_table.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "logl_table.c"
.section .rodata, "a"
.align 8
.align 8
.globl __libm_logl_table_256
__libm_logl_table_256:
.long 0x55d5a000,0x3f600401
.long 0xf98e1114,0xbce76218
.long 0x14588000,0x3f781212
.long 0xf5a30364,0xbcf4abf1
.long 0xf9684000,0x3f841929
.long 0xa8bfb25e,0xbcfa20e2
.long 0x84c74000,0x3f8c3173
.long 0x18823013,0x3d0f0660
.long 0x1ac72000,0x3f91a6b9
.long 0x36a9c5bb,0x3d13861d
.long 0x5d9ac000,0x3f95ba9a
.long 0xe08d78ac,0x3cacbb84
.long 0x07434000,0x3f99d2a8
.long 0xeb1d2ef8,0xbd1a0c1f
.long 0x2597c000,0x3f9d6b27
.long 0xa1a37071,0xbd23fef6
.long 0xa19e0000,0x3fa0c58f
.long 0x58b17913,0xbd0559d1
.long 0x78cbc000,0x3fa2954c
.long 0x570c1572,0x3d1c3526
.long 0x2da98000,0x3fa4a94d
.long 0xbad48944,0xbd23a98f
.long 0xf2d4c000,0x3fa67c94
.long 0xec19afa2,0xbd029efb
.long 0xb6310000,0x3fa85188
.long 0xdf4d03fb,0xbd1f2fd5
.long 0xbe73c000,0x3faa6b8a
.long 0x5c8ed1b8,0xbd20b3b9
.long 0x06f74000,0x3fac441e
.long 0x6cf5e5d5,0xbd2561c1
.long 0x13608000,0x3fae1e67
.long 0xa4275f13,0xbd22f961
.long 0x11ab8000,0x3faffa69
.long 0x98381a8f,0x3d23008c
.long 0x9c5da000,0x3fb0ec13
.long 0xe54ebd73,0x3d180247
.long 0x643d2000,0x3fb1dbd2
.long 0x9a20edb0,0xbd1bd36c
.long 0x84fe6000,0x3fb2cc72
.long 0x34cd5d84,0xbcec742f
.long 0xa7d1e000,0x3fb3bdf5
.long 0xa5db4ed7,0x3d2cc85e
.long 0x7aa00000,0x3fb4b05d
.long 0x8ddf26e3,0x3d32e053
.long 0x7ceb8000,0x3fb580db
.long 0x26833e56,0xbd447f01
.long 0x89364000,0x3fb674f0
.long 0x4c9d3302,0x3d3a7999
.long 0x2c6b8000,0x3fb769ef
.long 0xe71892b5,0xbd44b944
.long 0x27508000,0x3fb85fd9
.long 0x19970c1c,0xbd35b818
.long 0x5d594000,0x3fb9335e
.long 0x3abd47da,0x3d23115c
.long 0x20c90000,0x3fba2b02
.long 0x9c652090,0xbd3a0b35
.long 0xac1a8000,0x3fbb0004
.long 0x037f2b35,0x3d1aaf97
.long 0x769fc000,0x3fbbf968
.long 0x8d824283,0x3d24218c
.long 0xbfee0000,0x3fbccfed
.long 0x2fe71256,0x3d33a823
.long 0x63844000,0x3fbda727
.long 0x1fa71733,0x3d1a8940
.long 0x7fe10000,0x3fbea325
.long 0x47e4627a,0x3d2ef30d
.long 0xfedc0000,0x3fbf7be9
.long 0x2b2b3bc6,0xbd00d05d
.long 0x52ff2000,0x3fc02ab3
.long 0x5d569b2b,0x3d27ce63
.long 0x579d2000,0x3fc097ce
.long 0xda652881,0x3ce33742
.long 0x82280000,0x3fc1178e
.long 0xcc74be04,0xbd4b8421
.long 0x7dbec000,0x3fc18574
.long 0x45bd9b49,0x3d3e6744
.long 0x25f26000,0x3fc1f3b9
.long 0x9b083633,0xbd15f74e
.long 0x1e6de000,0x3fc2625d
.long 0xf09e3d82,0xbcf52962
.long 0x0c868000,0x3fc2d161
.long 0xcb81b4a1,0x3d039d6c
.long 0x97412000,0x3fc340c5
.long 0xf7d9d386,0xbd37a3dc
.long 0x67580000,0x3fc3b08b
.long 0xf29320fb,0xbd3aade8
.long 0x08378000,0x3fc40dfb
.long 0xc4f7b685,0x3c9bb453
.long 0xe8ca6000,0x3fc47e74
.long 0xb7020316,0xbcf07c95
.long 0xf6466000,0x3fc4ef51
.long 0x21c8cd53,0x3d3bc83d
.long 0xe02bc000,0x3fc56092
.long 0xfe5d989a,0xbd4ae9eb
.long 0x57cd4000,0x3fc5d238
.long 0x4b74dcf5,0x3d5a6a61
.long 0x37334000,0x3fc6313a
.long 0x561bc2b2,0x3d4d7641
.long 0xdabc0000,0x3fc6a399
.long 0x399a856a,0xbd563e4d
.long 0xdd3d0000,0x3fc70337
.long 0x1d685519,0xbd4be57a
.long 0x128f8000,0x3fc77654
.long 0x520d9718,0xbd4ed8b4
.long 0x2a0b4000,0x3fc7e9d8
.long 0x605bf1b1,0xbd5ee97b
.long 0x759f8000,0x3fc84a6b
.long 0x0ab7e182,0xbd5768a0
.long 0xd5f5c000,0x3fc8ab47
.long 0xf5f4572e,0xbd4cf028
.long 0x90964000,0x3fc91fe4
.long 0x79850e19,0x3d481b4e
.long 0x4011c000,0x3fc98163
.long 0x30b7dd0f,0xbd458a91
.long 0x07088000,0x3fc9f6c4
.long 0x5a19605e,0x3d466413
.long 0x29348000,0x3fca58e7
.long 0x504551b1,0x3d3e867d
.long 0xc3168000,0x3fcabb55
.long 0x9a875994,0x3d43acd2
.long 0x491a0000,0x3fcb1e10
.long 0xed340663,0xbd402ffc
.long 0x93e38000,0x3fcb94ee
.long 0x47492dd7,0xbd48357e
.long 0xc0674000,0x3fcbf851
.long 0xd9fbd5aa,0x3d455ef8
.long 0x54bf4000,0x3fcc5c02
.long 0x5184bd39,0xbd4c5a15
.long 0xc9db4000,0x3fccc000
.long 0x5d57aff9,0xbd1d6d58
.long 0x99c84000,0x3fcd244d
.long 0x032241dc,0x3d4673ec
.long 0x3fb30000,0x3fcd88e9
.long 0x0234bf51,0xbd375f28
.long 0x37eb0000,0x3fcdedd4
.long 0x565353b4,0xbd40ff6d
.long 0xffe70000,0x3fce530e
.long 0x276041f4,0x3d401212
.long 0x1648c000,0x3fceb89a
.long 0x16fee901,0xbd2a3b21
.long 0xfadfc000,0x3fcf1e75
.long 0x64bb07ee,0xbd5210c5
.long 0x2ead8000,0x3fcf84a3
.long 0xb3098725,0xbd1e5438
.long 0x33ea0000,0x3fcfeb22
.long 0xde00938b,0x3d2f3418
.long 0xc7036000,0x3fd028f9
.long 0xe9f33100,0xbd2f1eb9
.long 0xe0d96000,0x3fd05c8b
.long 0xc77ccb58,0x3d2ad0f1
.long 0x8f8ae000,0x3fd085eb
.long 0x3f45fe7b,0x3d3e5d51
.long 0xe32d2000,0x3fd0b9c8
.long 0xedbee0d8,0xbd3bbb62
.long 0x60b78000,0x3fd0edd0
.long 0x2d8435f5,0x3d0019b5
.long 0x4cf02000,0x3fd12202
.long 0xa2415097,0xbd59c089
.long 0x927ae000,0x3fd14be2
.long 0xc85685e2,0x3d49a817
.long 0x8ef18000,0x3fd18061
.long 0x1bc9638d,0x3d45be80
.long 0xbe2fc000,0x3fd1b50b
.long 0x3263201f,0x3d38ecd7
.long 0xc7cf2000,0x3fd1df4c
.long 0x0455f7e4,0x3d30b43f
.long 0x6d0ea000,0x3fd21445
.long 0xf5d235d7,0x3d58d43e
.long 0x991ec000,0x3fd23ec5
.long 0x48a2e522,0xbd36dbe4
.long 0x9f872000,0x3fd2740d
.long 0xfa32bfeb,0xbd5504cf
.long 0xabce0000,0x3fd29ecd
.long 0x8847bb7a,0xbd37f189
.long 0x02ade000,0x3fd2d466
.long 0xbb9aa833,0xbd5311a1
.long 0xb04ea000,0x3fd2ff66
.long 0xd5f0c8e9,0x3d43a896
.long 0x4b356000,0x3fd33550
.long 0xec6206db,0xbd372206
.long 0x5ec44000,0x3fd36092
.long 0xf344bbd1,0x3d4eb929
.long 0xc3336000,0x3fd38bf1
.long 0xa0f4a8b7,0x3d5e74f4
.long 0x77332000,0x3fd3c252
.long 0x4b606bd6,0x3d5183b5
.long 0x63c16000,0x3fd3edf4
.long 0xeb4069e1,0x3d407cc1
.long 0x23d5e000,0x3fd419b4
.long 0x6ec90e0a,0x3d418e43
.long 0xe053a000,0x3fd44591
.long 0x92923d88,0xbd06e958
.long 0x75b6e000,0x3fd47c91
.long 0x8b804f1b,0x3d50ad66
.long 0x41554000,0x3fd4a8b3
.long 0xe1791b98,0xbd54f6c0
.long 0x90890000,0x3fd4d4f3
.long 0x3a9f1441,0x3d19fd79
.long 0x8da1e000,0x3fd50152
.long 0x3694fa6b,0x3d5967d6
.long 0x6347e000,0x3fd52dd0
.long 0xeb98a049,0xbd46133a
.long 0x3c7b8000,0x3fd55a6d
.long 0xd6cf85a4,0x3d45138e
.long 0x2b110000,0x3fd5925d
.long 0x4b0b521a,0x3d652c81
.long 0x6b544000,0x3fd5bf40
.long 0xeb68981c,0xbd227023
.long 0x3d5c4000,0x3fd5ec43
.long 0xf6eb1741,0xbd44a472
.long 0xcdb04000,0x3fd61965
.long 0xac078912,0xbd53e115
.long 0x4935c000,0x3fd646a8
.long 0x6d25a6ca,0xbd4abc23
.long 0xdd320000,0x3fd6740a
.long 0xb8b270ac,0xbd60b5c4
.long 0xb74a8000,0x3fd6a18d
.long 0x67b50a45,0xbd639d6d
.long 0x05868000,0x3fd6cf31
.long 0xddac7ab9,0xbd4e27a6
.long 0xe8530000,0x3fd6f180
.long 0x0a20af33,0xbd4e8c49
.long 0x71b88000,0x3fd71f5d
.long 0x712fcc92,0x3d54efa4
.long 0xefd68000,0x3fd74d5a
.long 0x30990150,0xbd52a3e5
.long 0x922bc000,0x3fd77b79
.long 0xf6201124,0x3d537dc9
.long 0x889f4000,0x3fd7a9b9
.long 0x0dd20a44,0xbd630ed1
.long 0x037ec000,0x3fd7d81b
.long 0x622fc2c1,0xbd42b381
.long 0x33828000,0x3fd8069e
.long 0xe1da7992,0xbd4b9e42
.long 0xd3ef8000,0x3fd82996
.long 0xae7d64a2,0x3d47956a
.long 0x776e0000,0x3fd85855
.long 0x0cccc887,0xbd6a02a9
.long 0x58328000,0x3fd88736
.long 0x1f7fc497,0xbd2988e2
.long 0x973ac000,0x3fd8aa75
.long 0x9e0af65a,0xbd3cc466
.long 0xdc884000,0x3fd8d992
.long 0xebb56b23,0xbd5b1b77
.long 0xea7d8000,0x3fd908d2
.long 0xf0e513c0,0x3d551185
.long 0xe79c0000,0x3fd92c59
.long 0x039fe987,0x3d4cac17
.long 0x50ee4000,0x3fd95bd7
.long 0x0649244f,0xbd12d6ab
.long 0x11a3c000,0x3fd98b78
.long 0x3a5b6609,0x3d672da9
.long 0xf33d4000,0x3fd9af47
.long 0x59d98c86,0x3cfae14a
.long 0x0c190000,0x3fd9df27
.long 0x963f4336,0x3d54a786
.long 0xed150000,0x3fda0325
.long 0xb0d5e095,0xbd22dc20
.long 0x02250000,0x3fda3344
.long 0x40314305,0xbd361cdd
.long 0x5e80c000,0x3fda5772
.long 0xd1062b1b,0x3d2c172b
.long 0x165dc000,0x3fda87d0
.long 0x7845f58e,0x3d51991f
.long 0x6c040000,0x3fdaac2e
.long 0xc856ee3b,0xbd3da90d
.long 0x6fdf8000,0x3fdadccc
.long 0x23b48979,0xbd557ef2
.long 0x3eb20000,0x3fdb015b
.long 0xa4504de4,0xbd586fcd
.long 0x3a638000,0x3fdb323a
.long 0x7a9aa342,0xbd635be0
.long 0x04464000,0x3fdb56fa
.long 0xad27be67,0xbd56f6ad
.long 0xa659c000,0x3fdb881a
.long 0x58ba5c9c,0xbd2b65ac
.long 0xef3d8000,0x3fdbad0b
.long 0xe4a81b98,0x3d68b265
.long 0x97780000,0x3fdbd212
.long 0xa247841c,0x3d5c2f63
.long 0x36f08000,0x3fdc0392
.long 0x435af523,0x3d403109
.long 0x1e4d4000,0x3fdc28cb
.long 0xdc568214,0xbd4a0635
.long 0xb8474000,0x3fdc4e19
.long 0x9ad9f32c,0xbd5c3e5b
.long 0xc7454000,0x3fdc7ff9
.long 0x47d5b6ca,0x3d54c924
.long 0x64e9c000,0x3fdca57b
.long 0xd12a2803,0x3d5b0510
.long 0x0a5d0000,0x3fdccb13
.long 0x48811a12,0xbd545041
.long 0xd18f4000,0x3fdcf0c0
.long 0xc2008d44,0xbd4b2160
.long 0x75b58000,0x3fdd2320
.long 0x12cccc3a,0x3d610091
.long 0x46df0000,0x3fdd4902
.long 0x0b2c4c2c,0xbd365228
.long 0x918d4000,0x3fdd6efa
.long 0x7676c78e,0xbd5a329d
.long 0x707ac000,0x3fdd9509
.long 0x77579caf,0x3d6297b8
.long 0xfe92c000,0x3fddbb2e
.long 0x0943c435,0x3d3550ac
.long 0x3445c000,0x3fddee2f
.long 0x3a0f9d04,0x3d625775
.long 0x1a274000,0x3fde148a
.long 0x20732293,0xbd59326b
.long 0x0a4a0000,0x3fde3afc
.long 0x573921f0,0xbd080095
.long 0x206d4000,0x3fde6185
.long 0xc9807dcf,0x3d516d95
.long 0x78824000,0x3fde8825
.long 0xaa15d3d9,0xbd25726d
.long 0x2eac8000,0x3fdeaedd
.long 0xad7934b2,0x3d590c33
.long 0x5f438000,0x3fded5ac
.long 0x1bc1c15c,0xbd541d1a
.long 0x26d14000,0x3fdefc93
.long 0x206858e7,0x3d655c54
.long 0xa2154000,0x3fdf2391
.long 0x202b7ba5,0x3d6affe2
.long 0xee030000,0x3fdf4aa7
.long 0x56f014a9,0x3d592cde
.long 0x27c30000,0x3fdf71d6
.long 0xe30f87ad,0x3d47600a
.long 0x6cb38000,0x3fdf991c
.long 0xcca0cdf3,0x3d69bcbe
.long 0xda698000,0x3fdfc07a
.long 0x2683bdae,0x3d6487fd
.long 0x8eb04000,0x3fdfe7f1
.long 0xceb37e7a,0xbd260f51
.long 0x53c50000,0x3fe007c0
.long 0xc9c065f1,0x3cf73add
.long 0x2198a000,0x3fe01b94
.long 0x5498efb5,0x3d4683ab
.long 0x400c8000,0x3fe02f74
.long 0xe23775e2,0xbd6b154b
.long 0xbe760000,0x3fe04360
.long 0x030d58c4,0x3d3d6774
.long 0xac480000,0x3fe05759
.long 0x83c1e850,0xbd2cc5f3
.long 0x1911e000,0x3fe06b5f
.long 0x2598b50b,0xbd60ae17
.long 0x0533c000,0x3fe078bf
.long 0x907b7d7f,0x3d45a048
.long 0x687e8000,0x3fe08cd9
.long 0xc00a19af,0xbd43c67f
.long 0x74cfa000,0x3fe0a100
.long 0x22f73f90,0xbd5fcd6d
.long 0x3a234000,0x3fe0b534
.long 0x4c68a7e5,0x3d41da30
.long 0xc8942000,0x3fe0c974
.long 0xa7cdcbb8,0x3d61cdc0
.long 0x305ba000,0x3fe0ddc2
.long 0x566f7df8,0xbd4de684
.long 0x4bafc000,0x3fe0eb52
.long 0x7feb3411,0x3d5230c5
.long 0x4213a000,0x3fe0ffb5
.long 0xbeeae6be,0x3d41d77b
.long 0x3da98000,0x3fe11425
.long 0x3d4743ea,0xbd33050e
.long 0x4f1da000,0x3fe128a2
.long 0x5906450d,0xbd440318
.long 0x52bf0000,0x3fe13652
.long 0xa621d4be,0x3d50c985
.long 0x58b4a000,0x3fe14ae5
.long 0x9895512f,0x3d525a20
.long 0xa19c6000,0x3fe15f85
.long 0xe4dca81e,0x3d665b5b
.long 0x38c12000,0x3fe16d4d
.long 0xaf71a89e,0xbd481628
.long 0xc20de000,0x3fe18203
.long 0x4bb7b8b9,0xbd5d995f
.long 0xbc4b2000,0x3fe196c7
.long 0x14cec2c3,0xbd18a766
.long 0x38b7a000,0x3fe1a4a7
.long 0x26042793,0x3d39e2b1
.long 0xc0c96000,0x3fe1b981
.long 0x549461ed,0x3d44f378
.long 0xe8bb0000,0x3fe1ce69
.long 0xcc3339e5,0x3d606af5
.long 0x9de06000,0x3fe1dc61
.long 0xa1767071,0x3d528836
.long 0xa2ad0000,0x3fe1f160
.long 0x6c9de298,0x3d5b4741
.long 0x77406000,0x3fe2066d
.long 0xd051f38d,0x3d637e65
.long 0xba47c000,0x3fe2147d
.long 0x0cf5c8e9,0xbd6c6c55
.long 0xbc5ec000,0x3fe229a1
.long 0xf20d6e42,0xbd44f266
.long 0x841a6000,0x3fe237c1
.long 0xa47dba85,0xbd5fa312
.long 0xe6f82000,0x3fe24cfc
.long 0xb65cb7bb,0xbd626596
.long 0x55cd6000,0x3fe25b2c
.long 0x2ff856c0,0xbd513b72
.long 0x4d5f8000,0x3fe2707f
.long 0xc37d4cdf,0xbd3df8b3
.long 0x842ca000,0x3fe285e0
.long 0x866d5f22,0x3d3c1c4d
.long 0x4708c000,0x3fe29429
.long 0x7aca88eb,0xbd5119e8
.long 0x670b0000,0x3fe2a9a2
.long 0x1c2e5d10,0xbd1e7864
.long 0x2c8d2000,0x3fe2b7fb
.long 0x00c270dd,0xbd39fb3c
.long 0x63960000,0x3fe2c65a
.long 0x03be9586,0xbd5415ea
.long 0x57b0e000,0x3fe2dbf5
.long 0x07b9dc11,0xbd17a6e5
.long 0xc3f96000,0x3fe2ea64
.long 0x8b7d46fa,0x3d6654b2
.long 0x23686000,0x3fe30018
.long 0x5363d25e,0xbd628cd2
.long 0xe9a8c000,0x3fe30e97
.long 0x06943683,0xbd546671
.long 0xebdd4000,0x3fe32463
.long 0xc46cb528,0xbd562c21
.long 0x314ae000,0x3fe332f4
.long 0x1ea74541,0xbd50d4b6
.long 0x0e746000,0x3fe348d9
.long 0x44f828b5,0x3d433f3c
.long 0xf8c44000,0x3fe35779
.long 0x22a46dd6,0xbd34934a
.long 0x961a8000,0x3fe36621
.long 0x0cdd9d24,0xbd6566ce
.long 0x9f3c2000,0x3fe37c29
.long 0x8e5820fe,0x3d666a2b
.long 0x17198000,0x3fe38ae2
.long 0x576aad35,0xbd52316f
.long 0x57a60000,0x3fe399a1
.long 0x62286d89,0x3d3f399c
.long 0xfe77c000,0x3fe3afcc
.long 0xedc1a56f,0xbd48bbbb
.long 0x50352000,0x3fe3be9d
.long 0x22f47589,0x3d63b540
.long 0x80b4a000,0x3fe3cd74
.long 0x9ebf0b71,0x3d51452e
.long 0x39190000,0x3fe3e3c4
.long 0x4c617cda,0xbd512753
.long 0xb27ec000,0x3fe3f2ac
.long 0x8d68a543,0x3d66c6ab
.long 0x2125c000,0x3fe4019c
.long 0xd9e1e717,0x3d552630
.long 0x6138a000,0x3fe41810
.long 0xa1618e8d,0xbd51bb4f
.long 0x518de000,0x3fe42711
.long 0x38d47013,0x3d65455f
.long 0x4e12c000,0x3fe43619
.long 0xaca69593,0xbd52819e
.long 0x5d68e000,0x3fe44528
.long 0xf367503a,0x3d54d27f
.long 0x464ca000,0x3fe45bcc
.long 0xa4ffdcb2,0xbd66c5eb
.long 0x21f12000,0x3fe46aed
.long 0xa0df038b,0xbd50072e
.long 0x27e8a000,0x3fe47a15
.long 0x83594fab,0x3d369a4a
.long 0x5f000000,0x3fe48944
.long 0x95dc2343,0xbd39a0cf
.long 0xbcb6a000,0x3fe4a018
.long 0xdb5ebf58,0xbd4f2ae4
.long 0x0c9d6000,0x3fe4af5a
.long 0xedc4bac0,0x3d475de0
.long 0xa5bdc000,0x3fe4bea2
.long 0xefe50211,0xbd278f64
.long 0x8f10c000,0x3fe4cdf2
.long 0x7690ed86,0xbd63b982
.long 0xcf994000,0x3fe4dd49
.long 0x24d59d34,0x3d061972
.long 0x6e64a000,0x3fe4eca8
.long 0xb1079278,0x3d4a0e67
.long 0x3cd90000,0x3fe503c4
.long 0x0f1a734d,0xbd6497fc
.long 0x6667e000,0x3fe51335
.long 0x4c9987aa,0x3d6c5739
.long 0x0738a000,0x3fe522ae
.long 0x8164c759,0x3d3ebe70
.long 0x26868000,0x3fe5322e
.long 0xba2da8ad,0xbd4ea333
.long 0xcb978000,0x3fe541b5
.long 0x62e3a6b9,0x3d680916
.long 0xfdbcc000,0x3fe55144
.long 0x2b35ba3e,0xbd34ec53
.long 0xc4518000,0x3fe560db
.long 0x776b86a6,0xbd761cb6
.long 0x26bb8000,0x3fe5707a
.long 0x5ff9981f,0x3d58ccc0
.long 0x0ed5c000,0x3fe587f6
.long 0xe6cce4c9,0xbd4c00c2
.long 0x977cc000,0x3fe597a7
.long 0xf6a33533,0xbd786770
.long 0xd6348000,0x3fe5a760
.long 0x365e53d9,0x3d7dc57c
.long 0xd2960000,0x3fe5b721
.long 0x4f6ab8cd,0xbd5de23a
.long 0x94434000,0x3fe5c6ea
.long 0xa68978ec,0xbd70837e
.long 0x22ea8000,0x3fe5d6bb
.long 0xea2eecbe,0x3d4bd7d0
.long 0x86460000,0x3fe5e693
.long 0x23677de5,0xbd763831
.long 0xc61a4000,0x3fe5f673
.long 0x7a110a0e,0xbd612e5c
.long 0xea384000,0x3fe6065b
.long 0xc49e2cb9,0x3d692622
.long 0xfa7cc000,0x3fe6164b
.long 0x27c383a0,0x3d0ad6c4
.long 0xfecfc000,0x3fe62643
.long 0x3ae25ed1,0xbd745e87
.type __libm_logl_table_256,@object
.size __libm_logl_table_256,4096
.data
.section .note.GNU-stack, ""
# End
|
GeminiCarrie/rust-sgx-sdk | 19,268 | sgx_libc/sgx_tlibc_sys/tlibc/math/cacos.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "cacos.c"
.text
..TXTST0:
# -- Begin cacosf
.text
.align 16,0x90
.globl cacosf
cacosf:
# parameter 1: %xmm0
..B1.1:
.cfi_startproc
..___tag_value_cacosf.1:
..L2:
subq $24, %rsp
.cfi_def_cfa_offset 32
cvtps2pd %xmm0, %xmm1
movaps %xmm1, %xmm0
unpckhpd %xmm1, %xmm1
..___tag_value_cacosf.4:
call cacos@PLT
..___tag_value_cacosf.5:
..B1.10:
unpcklpd %xmm1, %xmm0
..B1.2:
cvtpd2ps %xmm0, %xmm0
movsd %xmm0, 4(%rsp)
movzwl 6(%rsp), %eax
testl $32640, %eax
jne ..B1.4
..B1.3:
testl $8388607, 4(%rsp)
jne ..B1.6
..B1.4:
movzwl 10(%rsp), %eax
testl $32640, %eax
jne ..B1.7
..B1.5:
testl $8388607, 8(%rsp)
je ..B1.7
..B1.6:
movss .L_2il0floatpacket.12(%rip), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rsp)
movsd 4(%rsp), %xmm0
..B1.7:
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type cacosf,@function
.size cacosf,.-cacosf
.data
# -- End cacosf
.text
# -- Begin cacos
.text
.align 16,0x90
.globl cacos
cacos:
# parameter 1: %xmm0
..B2.1:
.cfi_startproc
..___tag_value_cacos.8:
..L9:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
xorb %r12b, %r12b
subq $152, %rsp
.cfi_def_cfa_offset 176
movsd %xmm0, 32(%rsp)
movsd %xmm1, 40(%rsp)
..B2.2:
fnstcw 138(%rsp)
..B2.3:
movzwl 38(%rsp), %edx
andl $32752, %edx
shrl $4, %edx
cmpl $2047, %edx
jge ..B2.36
..B2.4:
testl %edx, %edx
jle ..B2.57
..B2.5:
movzwl 46(%rsp), %eax
andl $32752, %eax
shrl $4, %eax
cmpl $2047, %eax
jge ..B2.36
..B2.6:
testl %eax, %eax
jle ..B2.55
..B2.7:
movzwl 138(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B2.11
..B2.8:
orl $-64768, %edx
movw %dx, 136(%rsp)
..B2.9:
fldcw 136(%rsp)
..B2.10:
movb $1, %r12b
..B2.11:
fldt .L_2il0floatpacket.14(%rip)
lea BcrossA(%rip), %rax
movsd 32(%rsp), %xmm0
fld %st(0)
fldt .L_2il0floatpacket.15(%rip)
movsd %xmm0, 120(%rsp)
fldt (%rax)
andps .L_2il0floatpacket.18(%rip), %xmm0
movsd %xmm0, (%rsp)
fldl (%rsp)
movsd 40(%rsp), %xmm1
fadd %st, %st(3)
movsd %xmm1, 128(%rsp)
andps .L_2il0floatpacket.18(%rip), %xmm1
movsd %xmm1, (%rsp)
fxch %st(3)
fstpt 104(%rsp)
fldt 104(%rsp)
fxch %st(3)
fsubr %st, %st(4)
fxch %st(4)
fstpt 88(%rsp)
fldt 88(%rsp)
fxch %st(3)
fmul %st(0), %st
fxch %st(3)
fmul %st(0), %st
fldl (%rsp)
fld %st(0)
fmul %st(1), %st
fadd %st, %st(5)
fxch %st(5)
fsqrt
fld %st(0)
fxch %st(3)
fadd %st(6), %st
fsqrt
fstpt 72(%rsp)
fldt 72(%rsp)
faddp %st, %st(3)
fxch %st(4)
fmulp %st, %st(2)
fld %st(5)
fdiv %st(2), %st
fxch %st(3)
fcomip %st(3), %st
jbe ..B2.13
..B2.12:
fstp %st(0)
addq $-16, %rsp
.cfi_def_cfa_offset 192
fxch %st(1)
fstpt (%rsp)
fxch %st(3)
fstpl 80(%rsp)
fstpt 16(%rsp)
fstpt 32(%rsp)
fstpt 48(%rsp)
call acosl@PLT
..B2.78:
fldt 48(%rsp)
fldt 32(%rsp)
fldt 16(%rsp)
fldl 80(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp ..B2.16
..B2.13:
fstp %st(2)
fldt .L_2il0floatpacket.14(%rip)
fcomip %st(5), %st
jb ..B2.15
..B2.14:
fstp %st(1)
fldt .L_2il0floatpacket.15(%rip)
addq $-32, %rsp
.cfi_def_cfa_offset 208
fld %st(2)
fld %st(2)
fadd %st(6), %st
fmulp %st, %st(2)
fldt 136(%rsp)
faddp %st, %st(1)
fdivr %st(4), %st
fldt 104(%rsp)
fldt 120(%rsp)
faddp %st, %st(1)
faddp %st, %st(1)
fmulp %st, %st(1)
fsqrt
fstpt (%rsp)
fxch %st(3)
fstpt 16(%rsp)
fldt 16(%rsp)
fstpl 96(%rsp)
fstpt 32(%rsp)
fstpt 48(%rsp)
fstpt 64(%rsp)
call atan2l@PLT
jmp ..B2.80
.cfi_def_cfa_offset 176
..B2.15:
fxch %st(2)
fstpt (%rsp)
fldt (%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 208
fld %st(2)
fadd %st(5), %st
fldt 136(%rsp)
faddp %st, %st(2)
fdiv %st, %st(1)
fldt 104(%rsp)
fldt 120(%rsp)
fsubrp %st, %st(1)
fdivrp %st, %st(1)
faddp %st, %st(1)
fldt .L_2il0floatpacket.15(%rip)
fmulp %st, %st(1)
fsqrt
fmulp %st, %st(1)
fstpt (%rsp)
fxch %st(2)
fstpt 16(%rsp)
fldt 16(%rsp)
fstpl 96(%rsp)
fstpt 48(%rsp)
fstpt 64(%rsp)
fldt 32(%rsp)
fstpt 32(%rsp)
call atan2l@PLT
..B2.80:
fldt 64(%rsp)
fldt 48(%rsp)
fldt 32(%rsp)
fldl 96(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 176
..B2.16:
lea AcrossA(%rip), %rax
fldt (%rax)
fcomip %st(4), %st
jb ..B2.21
..B2.17:
fldt 104(%rsp)
faddp %st, %st(2)
fldt .L_2il0floatpacket.14(%rip)
fcomip %st(1), %st
fstp %st(0)
jbe ..B2.19
..B2.18:
fldt 72(%rsp)
fxch %st(1)
fdivr %st(2), %st
fldt 88(%rsp)
faddp %st, %st(2)
fxch %st(1)
fdivrp %st, %st(2)
faddp %st, %st(1)
fldt .L_2il0floatpacket.15(%rip)
fmulp %st, %st(1)
jmp ..B2.20
..B2.19:
fldt 88(%rsp)
fxch %st(1)
fdivrp %st, %st(2)
fldt 72(%rsp)
fsubp %st, %st(1)
faddp %st, %st(1)
fldt .L_2il0floatpacket.15(%rip)
fmulp %st, %st(1)
..B2.20:
fldt .L_2il0floatpacket.14(%rip)
addq $-16, %rsp
.cfi_def_cfa_offset 192
faddp %st, %st(2)
fmul %st, %st(1)
fxch %st(1)
fsqrt
faddp %st, %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
call log1pl@PLT
jmp ..B2.82
.cfi_def_cfa_offset 176
..B2.21:
fstp %st(1)
fstp %st(1)
fstp %st(0)
fldt .L_2il0floatpacket.14(%rip)
fld %st(1)
fmul %st(2), %st
addq $-16, %rsp
.cfi_def_cfa_offset 192
fsubp %st, %st(1)
fsqrt
faddp %st, %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
call logl@PLT
..B2.82:
fldt 16(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
..B2.22:
lea ZEROA(%rip), %rax
movsd (%rax), %xmm1
comisd 120(%rsp), %xmm1
jbe ..B2.24
..B2.23:
fldt .L_2il0floatpacket.16(%rip)
lea PIBY2HIA(%rip), %rax
lea PIBY2LOA(%rip), %rdx
fldl (%rax)
faddl (%rdx)
fmulp %st, %st(1)
fsubp %st, %st(1)
..B2.24:
movsd 128(%rsp), %xmm0
comisd %xmm1, %xmm0
jbe ..B2.26
..B2.25:
fldt .L_2il0floatpacket.17(%rip)
fmulp %st, %st(2)
..B2.26:
fstpl 16(%rsp)
movzwl 22(%rsp), %eax
testl $32752, %eax
fstpl 24(%rsp)
jne ..B2.29
..B2.27:
testl $1048575, 20(%rsp)
jne ..B2.32
..B2.28:
cmpl $0, 16(%rsp)
jne ..B2.32
..B2.29:
movzwl 30(%rsp), %eax
testl $32752, %eax
jne ..B2.33
..B2.30:
testl $1048575, 28(%rsp)
jne ..B2.32
..B2.31:
cmpl $0, 24(%rsp)
je ..B2.33
..B2.32:
lea _LDB_MIN_NORMAL(%rip), %rax
fldt (%rax)
fmul %st(0), %st
fstpt 48(%rsp)
..B2.33:
testb %r12b, %r12b
je ..B2.35
..B2.34:
fldcw 138(%rsp)
..B2.35:
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
addq $152, %rsp
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 176
.cfi_offset 12, -16
.cfi_offset 13, -24
..B2.36:
testl %edx, %edx
jne ..B2.40
..B2.37:
testl $1048575, 36(%rsp)
jne ..B2.40
..B2.38:
cmpl $0, 32(%rsp)
jne ..B2.40
..B2.39:
movsd 40(%rsp), %xmm0
movq $0x3ff921fb54442d18, %rax
movq %rax, 16(%rsp)
call asinh@PLT
..B2.83:
xorps .L_2il0floatpacket.19(%rip), %xmm0
movsd %xmm0, 24(%rsp)
movsd 16(%rsp), %xmm0
movhpd 24(%rsp), %xmm0
jmp ..B2.54
..B2.40:
movzwl 46(%rsp), %eax
andl $32752, %eax
shrl $4, %eax
cmpl $2047, %eax
je ..B2.72
..B2.89:
cmpl $2047, %edx
..B2.41:
je ..B2.62
..B2.42:
cmpl $2047, %eax
je ..B2.59
..B2.43:
testl %eax, %eax
jne ..B2.50
..B2.44:
testl $1048575, 44(%rsp)
jne ..B2.50
..B2.45:
cmpl $0, 40(%rsp)
jne ..B2.50
..B2.46:
movsd 32(%rsp), %xmm0
cmpl $1023, %edx
jl ..B2.48
..B2.47:
movb 39(%rsp), %r12b
andb $-128, %r12b
shrb $7, %r12b
movzbl %r12b, %eax
lea ones(%rip), %r12
movsd (%r12,%rax,8), %xmm1
mulsd %xmm1, %xmm0
movsd %xmm1, (%rsp)
call acosh@PLT
..B2.85:
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
call acos@PLT
..B2.84:
movsd %xmm0, 16(%rsp)
jmp ..B2.49
..B2.48:
pxor %xmm1, %xmm1
movsd %xmm1, 8(%rsp)
call acos@PLT
..B2.86:
movsd %xmm0, 16(%rsp)
lea ones(%rip), %r12
..B2.49:
movb 47(%rsp), %al
andb $-128, %al
shrb $7, %al
movsd 8(%rsp), %xmm0
xorb $1, %al
movzbl %al, %edx
mulsd (%r12,%rdx,8), %xmm0
movsd %xmm0, 24(%rsp)
movsd 16(%rsp), %xmm0
movhpd 24(%rsp), %xmm0
jmp ..B2.54
..B2.50:
movsd 40(%rsp), %xmm0
cmpl $2047, %eax
movsd 32(%rsp), %xmm1
je ..B2.52
..B2.51:
movaps %xmm1, %xmm2
mulsd %xmm1, %xmm2
jmp ..B2.53
..B2.52:
movaps %xmm0, %xmm2
mulsd %xmm0, %xmm2
..B2.53:
movb 47(%rsp), %r13b
andb $-128, %r13b
shrb $7, %r13b
movb %r13b, %r12b
xorb $1, %r12b
movzbl %r12b, %eax
lea ones(%rip), %r12
mulsd (%r12,%rax,8), %xmm2
movsd %xmm2, 24(%rsp)
call atan2@PLT
..B2.87:
movzbl %r13b, %eax
mulsd (%r12,%rax,8), %xmm0
movsd %xmm0, 16(%rsp)
movhpd 24(%rsp), %xmm0
..B2.54:
movaps %xmm0, %xmm1
unpckhpd %xmm0, %xmm1
addq $152, %rsp
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 176
.cfi_offset 12, -16
.cfi_offset 13, -24
..B2.55:
testl $1048575, 44(%rsp)
jne ..B2.7
..B2.56:
cmpl $0, 40(%rsp)
jne ..B2.7
jmp ..B2.36
..B2.57:
testl $1048575, 36(%rsp)
jne ..B2.5
..B2.58:
cmpl $0, 32(%rsp)
jne ..B2.5
jmp ..B2.36
..B2.59:
testl $1048575, 44(%rsp)
jne ..B2.61
..B2.60:
cmpl $0, 40(%rsp)
je ..B2.50
..B2.61:
movsd 32(%rsp), %xmm1
movsd 40(%rsp), %xmm0
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
unpcklpd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.54
..B2.62:
testl $1048575, 36(%rsp)
jne ..B2.64
..B2.63:
cmpl $0, 32(%rsp)
je ..B2.66
..B2.64:
cmpl $2047, %eax
jge ..B2.66
..B2.65:
movsd 32(%rsp), %xmm0
mulsd %xmm0, %xmm0
unpcklpd %xmm0, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.54
..B2.66:
testl $1048575, 36(%rsp)
jne ..B2.68
..B2.67:
cmpl $0, 32(%rsp)
je ..B2.42
..B2.68:
cmpl $2047, %eax
jne ..B2.43
..B2.69:
testl $1048575, 44(%rsp)
jne ..B2.71
..B2.70:
cmpl $0, 40(%rsp)
je ..B2.59
..B2.71:
movsd 32(%rsp), %xmm0
movsd 40(%rsp), %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
unpcklpd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.54
..B2.72:
testl $1048575, 44(%rsp)
jne ..B2.74
..B2.73:
cmpl $0, 40(%rsp)
je ..B2.88
..B2.74:
cmpl $2047, %edx
jge ..B2.41
..B2.75:
movsd 40(%rsp), %xmm0
mulsd %xmm0, %xmm0
unpcklpd %xmm0, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.54
..B2.88:
cmpl $2047, %edx
je ..B2.62
jmp ..B2.42
.align 16,0x90
.cfi_endproc
.type cacos,@function
.size cacos,.-cacos
.data
# -- End cacos
.section .rodata, "a"
.align 16
.align 16
.L_2il0floatpacket.14:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.14,@object
.size .L_2il0floatpacket.14,16
.align 16
.L_2il0floatpacket.15:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xfe,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.15,@object
.size .L_2il0floatpacket.15,16
.align 16
.L_2il0floatpacket.16:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.16,@object
.size .L_2il0floatpacket.16,16
.align 16
.L_2il0floatpacket.17:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.17,@object
.size .L_2il0floatpacket.17,16
.align 16
.L_2il0floatpacket.18:
.long 0xffffffff,0x7fffffff,0x00000000,0x00000000
.type .L_2il0floatpacket.18,@object
.size .L_2il0floatpacket.18,16
.align 16
.L_2il0floatpacket.19:
.long 0x00000000,0x80000000,0x00000000,0x00000000
.type .L_2il0floatpacket.19,@object
.size .L_2il0floatpacket.19,16
.align 16
BcrossA:
.long 3621516424
.long 2756080513
.long 16382
.long 0
.type BcrossA,@object
.size BcrossA,16
.align 16
AcrossA:
.long 0
.long 3221225472
.long 16383
.long 0
.type AcrossA,@object
.size AcrossA,16
.align 16
ZEROA:
.long 0
.long 0
.type ZEROA,@object
.size ZEROA,8
.space 8, 0x00 # pad
.align 16
PIBY2HIA:
.long 1413754136
.long 1073291771
.type PIBY2HIA,@object
.size PIBY2HIA,8
.space 8, 0x00 # pad
.align 16
PIBY2LOA:
.long 856972295
.long 1016178214
.type PIBY2LOA,@object
.size PIBY2LOA,8
.space 8, 0x00 # pad
.align 16
_LDB_MIN_NORMAL:
.word 0
.word 0
.word 0
.word 32768
.word 1
.word 0
.word 0
.word 0
.type _LDB_MIN_NORMAL,@object
.size _LDB_MIN_NORMAL,16
.align 8
.L_2il0floatpacket.13:
.long 0x54442d18,0x3ff921fb
.type .L_2il0floatpacket.13,@object
.size .L_2il0floatpacket.13,8
.align 8
ones:
.long 0x00000000,0x3ff00000
.long 0x00000000,0xbff00000
.type ones,@object
.size ones,16
.align 4
.L_2il0floatpacket.12:
.long 0x00800000
.type .L_2il0floatpacket.12,@object
.size .L_2il0floatpacket.12,4
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
GeminiCarrie/rust-sgx-sdk | 7,241 | sgx_libc/sgx_tlibc_sys/tlibc/math/exp10f_gen.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "exp10f_gen.c"
.text
..TXTST0:
# -- Begin exp10f
.text
.align 16,0x90
.globl exp10f
exp10f:
# parameter 1: %xmm0
..B1.1:
.cfi_startproc
..___tag_value_exp10f.1:
..L2:
movd %xmm0, %edx
movss %xmm0, -8(%rsp)
movl %edx, %esi
movl %edx, %ecx
andl $2147483647, %esi
shrl $31, %ecx
cmpl $8388608, %esi
jb ..B1.17
..B1.2:
movl %ecx, %edi
lea range(%rip), %rax
cmpl (%rax,%rdi,4), %esi
ja ..B1.8
..B1.3:
movss .L_2il0floatpacket.0(%rip), %xmm1
cmpl $1065353216, %edx
jl ..B1.7
..B1.4:
movl %esi, %ecx
shrl $23, %ecx
addl $10, %ecx
shll %cl, %esi
testl %esi, %esi
jne ..B1.7
..B1.5:
addss %xmm1, %xmm0
movss %xmm0, -16(%rsp)
movl -16(%rsp), %eax
shll $10, %eax
sarl $10, %eax
cmpl $10, %eax
jg ..B1.7
..B1.6:
movslq %eax, %rax
lea exact_values(%rip), %rdx
movss (%rdx,%rax,4), %xmm0
ret
..B1.7:
pxor %xmm3, %xmm3
movq $0x3ff0000000000000, %rcx
cvtss2sd -8(%rsp), %xmm3
movaps %xmm3, %xmm0
mulsd .L_2il0floatpacket.1(%rip), %xmm0
movsd .L_2il0floatpacket.6(%rip), %xmm4
movq __libm_expf_table_64@GOTPCREL(%rip), %rsi
addsd .L_2il0floatpacket.2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -16(%rsp)
movss -16(%rsp), %xmm2
movsd .L_2il0floatpacket.4(%rip), %xmm0
subss %xmm1, %xmm2
cvtss2sd %xmm2, %xmm2
mulsd .L_2il0floatpacket.3(%rip), %xmm2
movl -16(%rsp), %edx
addsd %xmm2, %xmm3
movaps %xmm3, %xmm1
andl $4194303, %edx
mulsd %xmm3, %xmm1
movl %edx, %eax
mulsd %xmm1, %xmm0
mulsd %xmm1, %xmm4
addsd .L_2il0floatpacket.5(%rip), %xmm0
addsd .L_2il0floatpacket.7(%rip), %xmm4
mulsd %xmm1, %xmm0
mulsd %xmm3, %xmm4
shll $26, %eax
addsd %xmm4, %xmm0
sarl $26, %eax
movslq %eax, %rax
subl %eax, %edx
shrl $6, %edx
movsd 256(%rsi,%rax,8), %xmm5
mulsd %xmm5, %xmm0
shlq $52, %rdx
addsd %xmm5, %xmm0
addq %rcx, %rdx
movq %rdx, -24(%rsp)
mulsd -24(%rsp), %xmm0
cvtsd2ss %xmm0, %xmm0
ret
..B1.8:
cmpl $2139095040, %esi
jae ..B1.13
..B1.9:
testl %ecx, %ecx
je ..B1.11
..B1.10:
movss .L_2il0floatpacket.8(%rip), %xmm0
mulss %xmm0, %xmm0
ret
..B1.11:
movss .L_2il0floatpacket.9(%rip), %xmm0
mulss %xmm0, %xmm0
..B1.12:
ret
..B1.13:
jne ..B1.15
..B1.14:
lea _inf_zero(%rip), %rax
movss (%rax,%rdi,4), %xmm0
ret
..B1.15:
movss -8(%rsp), %xmm0
..B1.16:
ret
..B1.17:
movss .L_2il0floatpacket.10(%rip), %xmm0
addss -8(%rsp), %xmm0
ret
.align 16,0x90
.cfi_endproc
.type exp10f,@function
.size exp10f,.-exp10f
.data
# -- End exp10f
.section .rodata, "a"
.align 8
.align 8
.L_2il0floatpacket.1:
.long 0x0979a371,0x406a934f
.type .L_2il0floatpacket.1,@object
.size .L_2il0floatpacket.1,8
.align 8
.L_2il0floatpacket.2:
.long 0x00000000,0x41680000
.type .L_2il0floatpacket.2,@object
.size .L_2il0floatpacket.2,8
.align 8
.L_2il0floatpacket.3:
.long 0x509f79ff,0xbf734413
.type .L_2il0floatpacket.3,@object
.size .L_2il0floatpacket.3,8
.align 8
.L_2il0floatpacket.4:
.long 0xe2724acf,0x3ff2d784
.type .L_2il0floatpacket.4,@object
.size .L_2il0floatpacket.4,8
.align 8
.L_2il0floatpacket.5:
.long 0xcd26a2f3,0x40053524
.type .L_2il0floatpacket.5,@object
.size .L_2il0floatpacket.5,8
.align 8
.L_2il0floatpacket.6:
.long 0xd3f4b8ec,0x400046f7
.type .L_2il0floatpacket.6,@object
.size .L_2il0floatpacket.6,8
.align 8
.L_2il0floatpacket.7:
.long 0xbbb47127,0x40026bb1
.type .L_2il0floatpacket.7,@object
.size .L_2il0floatpacket.7,8
.align 4
.L_2il0floatpacket.0:
.long 0x4b400000
.type .L_2il0floatpacket.0,@object
.size .L_2il0floatpacket.0,4
.align 4
.L_2il0floatpacket.8:
.long 0x0d800000
.type .L_2il0floatpacket.8,@object
.size .L_2il0floatpacket.8,4
.align 4
.L_2il0floatpacket.9:
.long 0x71800000
.type .L_2il0floatpacket.9,@object
.size .L_2il0floatpacket.9,4
.align 4
.L_2il0floatpacket.10:
.long 0x3f800000
.type .L_2il0floatpacket.10,@object
.size .L_2il0floatpacket.10,4
.align 4
range:
.long 1109008539
.long 1110823542
.type range,@object
.size range,8
.align 4
exact_values:
.long 0x00000000
.long 0x41200000
.long 0x42c80000
.long 0x447a0000
.long 0x461c4000
.long 0x47c35000
.long 0x49742400
.long 0x4b189680
.long 0x4cbebc20
.long 0x4e6e6b28
.long 0x501502f9
.type exact_values,@object
.size exact_values,44
.align 4
_inf_zero:
.long 2139095040
.long 0
.type _inf_zero,@object
.size _inf_zero,8
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
.globl pow10f
.equ pow10f, exp10f
|
GeminiCarrie/rust-sgx-sdk | 11,859 | sgx_libc/sgx_tlibc_sys/tlibc/math/exp10_gen.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "exp10_gen.c"
.text
..TXTST0:
# -- Begin exp10
.text
.align 16,0x90
.globl exp10
exp10:
# parameter 1: %xmm0
..B1.1:
.cfi_startproc
..___tag_value_exp10.1:
..L2:
movsd %xmm0, -40(%rsp)
movl -36(%rsp), %esi
movl %esi, %edi
movl %esi, %edx
andl $2147483647, %edi
shrl $31, %edx
cmpl $1012924416, %edi
jb ..B1.24
..B1.2:
lea _range(%rip), %rcx
cmpl 4(%rcx,%rdx,8), %edi
jb ..B1.5
..B1.3:
jne ..B1.16
..B1.4:
movl -40(%rsp), %eax
cmpl (%rcx,%rdx,8), %eax
ja ..B1.16
..B1.5:
addl $-1072693248, %esi
cmpl $4587520, %esi
ja ..B1.8
..B1.6:
lea _TWO_52H(%rip), %rax
movsd -40(%rsp), %xmm0
movaps %xmm0, %xmm1
movsd (%rax), %xmm2
addsd (%rax), %xmm1
movsd %xmm1, -32(%rsp)
movsd -32(%rsp), %xmm1
movslq -32(%rsp), %rcx
subsd %xmm2, %xmm1
ucomisd %xmm0, %xmm1
jp ..B1.7
je ..B1.26
..B1.7:
movsd %xmm1, -24(%rsp)
jmp ..B1.9
..B1.8:
lea _TWO_52H(%rip), %rax
movsd -40(%rsp), %xmm0
movsd (%rax), %xmm2
..B1.9:
movaps %xmm0, %xmm1
lea _TWO_32H(%rip), %rcx
mulsd .L_2il0floatpacket.0(%rip), %xmm1
lea SC2_BIAS(%rip), %rdi
movsd .L_2il0floatpacket.2(%rip), %xmm3
addsd %xmm2, %xmm1
movsd %xmm1, -32(%rsp)
movsd -32(%rsp), %xmm6
movsd (%rcx), %xmm5
subsd %xmm2, %xmm6
movsd .L_2il0floatpacket.1(%rip), %xmm2
mulsd %xmm6, %xmm2
mulsd %xmm3, %xmm6
subsd %xmm2, %xmm0
movaps %xmm0, %xmm4
movl -32(%rsp), %eax
movl %eax, %r9d
movsd .L_2il0floatpacket.4(%rip), %xmm12
movl %eax, %esi
movsd .L_2il0floatpacket.8(%rip), %xmm2
subsd %xmm6, %xmm4
movsd .L_2il0floatpacket.3(%rip), %xmm8
addsd %xmm5, %xmm4
movsd %xmm4, -32(%rsp)
movsd -32(%rsp), %xmm9
movsd .L_2il0floatpacket.12(%rip), %xmm7
subsd %xmm5, %xmm9
shll $25, %r9d
subsd %xmm9, %xmm0
sarl $25, %r9d
subsd %xmm6, %xmm0
movaps %xmm0, %xmm11
subl %r9d, %esi
mulsd %xmm8, %xmm0
addsd %xmm9, %xmm11
mulsd %xmm8, %xmm9
movaps %xmm11, %xmm10
addsd %xmm9, %xmm7
mulsd %xmm11, %xmm10
mulsd %xmm10, %xmm12
mulsd %xmm10, %xmm2
addsd .L_2il0floatpacket.5(%rip), %xmm12
addsd .L_2il0floatpacket.9(%rip), %xmm2
mulsd %xmm10, %xmm12
mulsd %xmm10, %xmm2
addsd .L_2il0floatpacket.6(%rip), %xmm12
addsd .L_2il0floatpacket.10(%rip), %xmm2
mulsd %xmm10, %xmm12
mulsd %xmm10, %xmm2
addsd %xmm0, %xmm12
addsd .L_2il0floatpacket.11(%rip), %xmm2
movsd %xmm7, -24(%rsp)
movl $0, -24(%rsp)
movsd -24(%rsp), %xmm1
movsd .L_2il0floatpacket.7(%rip), %xmm0
mulsd %xmm11, %xmm2
addsd %xmm1, %xmm0
movslq %r9d, %r9
subsd %xmm0, %xmm9
shlq $4, %r9
addsd %xmm9, %xmm12
movq __libm_exp_table_128@GOTPCREL(%rip), %r10
addsd %xmm12, %xmm2
shrl $7, %esi
movsd 1032(%r10,%r9), %xmm4
movslq (%rdi,%rdx,4), %r8
movaps %xmm4, %xmm0
addq %rsi, %r8
shlq $52, %r8
movq %r8, -16(%rsp)
cmpl $-130815, %eax
movsd 1024(%r10,%r9), %xmm3
mulsd %xmm2, %xmm0
mulsd %xmm1, %xmm4
jle ..B1.11
..B1.10:
lea _SC2(%rip), %rax
addsd %xmm1, %xmm2
mulsd %xmm2, %xmm3
addsd %xmm3, %xmm0
addsd %xmm4, %xmm0
mulsd -16(%rsp), %xmm0
mulsd (%rax,%rdx,8), %xmm0
movsd %xmm0, -40(%rsp)
ret
..B1.11:
lea _SC2(%rip), %rax
addsd %xmm1, %xmm2
mulsd %xmm2, %xmm3
movaps %xmm4, %xmm1
movsd (%rax,%rdx,8), %xmm2
addsd %xmm3, %xmm0
addsd %xmm0, %xmm1
movsd %xmm1, -24(%rsp)
movl $0, -24(%rsp)
movsd -24(%rsp), %xmm3
movsd -16(%rsp), %xmm1
subsd %xmm3, %xmm4
addsd %xmm0, %xmm4
movaps %xmm3, %xmm0
addsd %xmm4, %xmm0
mulsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
movsd %xmm0, -40(%rsp)
movl -36(%rsp), %eax
cmpl $1048576, %eax
jge ..B1.15
..B1.12:
testl %eax, %eax
jle ..B1.14
..B1.13:
mulsd %xmm1, %xmm3
mulsd %xmm1, %xmm4
mulsd %xmm2, %xmm3
mulsd %xmm2, %xmm4
addsd %xmm4, %xmm3
movsd %xmm3, -40(%rsp)
..B1.14:
lea _small_value_64(%rip), %rax
movsd (%rax), %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, -32(%rsp)
movsd -40(%rsp), %xmm0
..B1.15:
ret
..B1.16:
cmpl $2146435072, %edi
jae ..B1.20
..B1.17:
testl $-2147483648, %esi
je ..B1.25
..B1.18:
lea _small_value_64(%rip), %rax
movsd (%rax), %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, -40(%rsp)
..B1.19:
ret
..B1.20:
addl $-2146435072, %edi
orl -40(%rsp), %edi
jne ..B1.22
..B1.21:
lea _inf_zero(%rip), %rax
movsd (%rax,%rdx,8), %xmm0
ret
..B1.22:
movsd -40(%rsp), %xmm0
addsd %xmm0, %xmm0
..B1.23:
ret
..B1.24:
movsd .L_2il0floatpacket.12(%rip), %xmm0
addsd -40(%rsp), %xmm0
ret
..B1.25:
lea _large_value_64(%rip), %rax
movsd (%rax), %xmm0
mulsd %xmm0, %xmm0
movsd %xmm0, -40(%rsp)
ret
..B1.26:
lea exact_values(%rip), %rax
movsd (%rax,%rcx,8), %xmm0
ret
.align 16,0x90
.cfi_endproc
.type exp10,@function
.size exp10,.-exp10
.data
# -- End exp10
.section .rodata, "a"
.align 8
.align 8
.L_2il0floatpacket.0:
.long 0x0979a371,0x407a934f
.type .L_2il0floatpacket.0,@object
.size .L_2il0floatpacket.0,8
.align 8
.L_2il0floatpacket.1:
.long 0x00000000,0x3f634413
.type .L_2il0floatpacket.1,@object
.size .L_2il0floatpacket.1,8
.align 8
.L_2il0floatpacket.2:
.long 0x7fbcc47c,0x3e0427de
.type .L_2il0floatpacket.2,@object
.size .L_2il0floatpacket.2,8
.align 8
.L_2il0floatpacket.3:
.long 0x00000000,0x40026bb1
.type .L_2il0floatpacket.3,@object
.size .L_2il0floatpacket.3,8
.align 8
.L_2il0floatpacket.4:
.long 0xd9d41e9c,0x3fca7ed8
.type .L_2il0floatpacket.4,@object
.size .L_2il0floatpacket.4,8
.align 8
.L_2il0floatpacket.5:
.long 0x09fd8b95,0x3ff2bd76
.type .L_2il0floatpacket.5,@object
.size .L_2il0floatpacket.5,8
.align 8
.L_2il0floatpacket.6:
.long 0xc73cea69,0x40053524
.type .L_2il0floatpacket.6,@object
.size .L_2il0floatpacket.6,8
.align 8
.L_2il0floatpacket.7:
.long 0x00000000,0xbff00000
.type .L_2il0floatpacket.7,@object
.size .L_2il0floatpacket.7,8
.align 8
.L_2il0floatpacket.8:
.long 0x25f8c2cc,0x3fb16e4f
.type .L_2il0floatpacket.8,@object
.size .L_2il0floatpacket.8,8
.align 8
.L_2il0floatpacket.9:
.long 0xfd1d41fe,0x3fe1429f
.type .L_2il0floatpacket.9,@object
.size .L_2il0floatpacket.9,8
.align 8
.L_2il0floatpacket.10:
.long 0x91de2ca4,0x40004705
.type .L_2il0floatpacket.10,@object
.size .L_2il0floatpacket.10,8
.align 8
.L_2il0floatpacket.11:
.long 0xa2b05ba9,0x3eb776aa
.type .L_2il0floatpacket.11,@object
.size .L_2il0floatpacket.11,8
.align 8
.L_2il0floatpacket.12:
.long 0x00000000,0x3ff00000
.type .L_2il0floatpacket.12,@object
.size .L_2il0floatpacket.12,8
.align 8
exact_values:
.long 0x00000000,0x00000000
.long 0x00000000,0x40240000
.long 0x00000000,0x40590000
.long 0x00000000,0x408f4000
.long 0x00000000,0x40c38800
.long 0x00000000,0x40f86a00
.long 0x00000000,0x412e8480
.long 0x00000000,0x416312d0
.long 0x00000000,0x4197d784
.long 0x00000000,0x41cdcd65
.long 0x20000000,0x4202a05f
.long 0xe8000000,0x42374876
.long 0xa2000000,0x426d1a94
.long 0xe5400000,0x42a2309c
.long 0x1e900000,0x42d6bcc4
.long 0x26340000,0x430c6bf5
.long 0x37e08000,0x4341c379
.long 0x85d8a000,0x43763457
.long 0x674ec800,0x43abc16d
.long 0x60913d00,0x43e158e4
.long 0x78b58c40,0x4415af1d
.long 0xd6e2ef50,0x444b1ae4
.long 0x064dd592,0x4480f0cf
.type exact_values,@object
.size exact_values,184
.align 4
_range:
.long 1352628734
.long 1081295891
.long 1189309266
.long 1081358775
.type _range,@object
.size _range,16
.align 4
_TWO_52H:
.long 0
.long 1127743488
.type _TWO_52H,@object
.size _TWO_52H,8
.align 4
_TWO_32H:
.long 0
.long 1106771968
.type _TWO_32H,@object
.size _TWO_32H,8
.align 4
SC2_BIAS:
.long 511
.long 1535
.type SC2_BIAS,@object
.size SC2_BIAS,8
.align 4
_SC2:
.long 0
.long 1609564160
.long 0
.long 535822336
.type _SC2,@object
.size _SC2,16
.align 4
_small_value_64:
.long 0
.long 24117248
.long 0
.long 2171600896
.type _small_value_64,@object
.size _small_value_64,16
.align 4
_inf_zero:
.long 0
.long 2146435072
.long 0
.long 0
.type _inf_zero,@object
.size _inf_zero,16
.align 4
_large_value_64:
.long 0
.long 2121269248
.long 0
.long 4268752896
.type _large_value_64,@object
.size _large_value_64,16
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
.globl pow10
.equ pow10, exp10
|
GeminiCarrie/rust-sgx-sdk | 19,212 | sgx_libc/sgx_tlibc_sys/tlibc/math/cacosh.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "cacosh.c"
.text
..TXTST0:
# -- Begin cacoshf
.text
.align 16,0x90
.globl cacoshf
cacoshf:
# parameter 1: %xmm0
..B1.1:
.cfi_startproc
..___tag_value_cacoshf.1:
..L2:
subq $24, %rsp
.cfi_def_cfa_offset 32
cvtps2pd %xmm0, %xmm1
movaps %xmm1, %xmm0
unpckhpd %xmm1, %xmm1
..___tag_value_cacoshf.4:
call cacosh@PLT
..___tag_value_cacoshf.5:
..B1.10:
unpcklpd %xmm1, %xmm0
..B1.2:
cvtpd2ps %xmm0, %xmm0
movsd %xmm0, 4(%rsp)
movzwl 6(%rsp), %eax
testl $32640, %eax
jne ..B1.4
..B1.3:
testl $8388607, 4(%rsp)
jne ..B1.6
..B1.4:
movzwl 10(%rsp), %eax
testl $32640, %eax
jne ..B1.7
..B1.5:
testl $8388607, 8(%rsp)
je ..B1.7
..B1.6:
movss .L_2il0floatpacket.12(%rip), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rsp)
movsd 4(%rsp), %xmm0
..B1.7:
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type cacoshf,@function
.size cacoshf,.-cacoshf
.data
# -- End cacoshf
.text
# -- Begin cacosh
.text
.align 16,0x90
.globl cacosh
cacosh:
# parameter 1: %xmm0
..B2.1:
.cfi_startproc
..___tag_value_cacosh.8:
..L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
xorb %r13b, %r13b
subq $160, %rsp
.cfi_def_cfa_offset 176
movsd %xmm0, 136(%rsp)
movsd %xmm1, 144(%rsp)
..B2.2:
fnstcw 154(%rsp)
..B2.3:
movzwl 142(%rsp), %edx
andl $32752, %edx
shrl $4, %edx
cmpl $2047, %edx
jge ..B2.36
..B2.4:
testl %edx, %edx
jle ..B2.62
..B2.5:
movzwl 150(%rsp), %eax
andl $32752, %eax
shrl $4, %eax
cmpl $2047, %eax
jge ..B2.37
..B2.6:
testl %eax, %eax
jle ..B2.60
..B2.7:
movzwl 154(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B2.11
..B2.8:
orl $-64768, %edx
movw %dx, 152(%rsp)
..B2.9:
fldcw 152(%rsp)
..B2.10:
movb $1, %r13b
..B2.11:
fldt .L_2il0floatpacket.13(%rip)
lea BcrossA(%rip), %rax
movsd 136(%rsp), %xmm0
fld %st(0)
fldt .L_2il0floatpacket.14(%rip)
movsd %xmm0, 128(%rsp)
fldt (%rax)
andps .L_2il0floatpacket.17(%rip), %xmm0
movsd %xmm0, (%rsp)
fldl (%rsp)
movsd 144(%rsp), %xmm1
fadd %st, %st(3)
movsd %xmm1, 120(%rsp)
andps .L_2il0floatpacket.17(%rip), %xmm1
movsd %xmm1, (%rsp)
fxch %st(3)
fstpt 104(%rsp)
fldt 104(%rsp)
fxch %st(3)
fsubr %st, %st(4)
fxch %st(4)
fstpt 88(%rsp)
fldt 88(%rsp)
fxch %st(3)
fmul %st(0), %st
fxch %st(3)
fmul %st(0), %st
fldl (%rsp)
fld %st(0)
fmul %st(1), %st
fadd %st, %st(5)
fxch %st(5)
fsqrt
fld %st(0)
fxch %st(3)
fadd %st(6), %st
fsqrt
fstpt 72(%rsp)
fldt 72(%rsp)
faddp %st, %st(3)
fxch %st(4)
fmulp %st, %st(2)
fld %st(5)
fdiv %st(2), %st
fxch %st(3)
fcomip %st(3), %st
jbe ..B2.13
..B2.12:
fstp %st(0)
addq $-16, %rsp
.cfi_def_cfa_offset 192
fxch %st(1)
fstpt (%rsp)
fxch %st(3)
fstpl 80(%rsp)
fstpt 16(%rsp)
fstpt 32(%rsp)
fstpt 48(%rsp)
call acosl@PLT
..B2.84:
fldt 48(%rsp)
fldt 32(%rsp)
fldt 16(%rsp)
fldl 80(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp ..B2.16
..B2.13:
fstp %st(2)
fldt .L_2il0floatpacket.13(%rip)
fcomip %st(5), %st
jb ..B2.15
..B2.14:
fstp %st(1)
fldt .L_2il0floatpacket.14(%rip)
addq $-32, %rsp
.cfi_def_cfa_offset 208
fld %st(2)
fld %st(2)
fadd %st(6), %st
fmulp %st, %st(2)
fldt 136(%rsp)
faddp %st, %st(1)
fdivr %st(4), %st
fldt 104(%rsp)
fldt 120(%rsp)
faddp %st, %st(1)
faddp %st, %st(1)
fmulp %st, %st(1)
fsqrt
fstpt (%rsp)
fxch %st(3)
fstpt 16(%rsp)
fldt 16(%rsp)
fstpl 96(%rsp)
fstpt 32(%rsp)
fstpt 48(%rsp)
fstpt 64(%rsp)
call atan2l@PLT
jmp ..B2.86
.cfi_def_cfa_offset 176
..B2.15:
fxch %st(2)
fstpt (%rsp)
fldt (%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 208
fld %st(2)
fadd %st(5), %st
fldt 136(%rsp)
faddp %st, %st(2)
fdiv %st, %st(1)
fldt 104(%rsp)
fldt 120(%rsp)
fsubrp %st, %st(1)
fdivrp %st, %st(1)
faddp %st, %st(1)
fldt .L_2il0floatpacket.14(%rip)
fmulp %st, %st(1)
fsqrt
fmulp %st, %st(1)
fstpt (%rsp)
fxch %st(2)
fstpt 16(%rsp)
fldt 16(%rsp)
fstpl 96(%rsp)
fstpt 48(%rsp)
fstpt 64(%rsp)
fldt 32(%rsp)
fstpt 32(%rsp)
call atan2l@PLT
..B2.86:
fldt 64(%rsp)
fldt 48(%rsp)
fldt 32(%rsp)
fldl 96(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 176
..B2.16:
lea AcrossA(%rip), %rax
fldt (%rax)
fcomip %st(4), %st
jb ..B2.21
..B2.17:
fldt 104(%rsp)
faddp %st, %st(2)
fldt .L_2il0floatpacket.13(%rip)
fcomip %st(1), %st
fstp %st(0)
jbe ..B2.19
..B2.18:
fldt 72(%rsp)
fxch %st(1)
fdivr %st(2), %st
fldt 88(%rsp)
faddp %st, %st(2)
fxch %st(1)
fdivrp %st, %st(2)
faddp %st, %st(1)
fldt .L_2il0floatpacket.14(%rip)
fmulp %st, %st(1)
jmp ..B2.20
..B2.19:
fldt 88(%rsp)
fxch %st(1)
fdivrp %st, %st(2)
fldt 72(%rsp)
fsubp %st, %st(1)
faddp %st, %st(1)
fldt .L_2il0floatpacket.14(%rip)
fmulp %st, %st(1)
..B2.20:
fldt .L_2il0floatpacket.13(%rip)
addq $-16, %rsp
.cfi_def_cfa_offset 192
faddp %st, %st(2)
fmul %st, %st(1)
fxch %st(1)
fsqrt
faddp %st, %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
call log1pl@PLT
jmp ..B2.88
.cfi_def_cfa_offset 176
..B2.21:
fstp %st(1)
fstp %st(1)
fstp %st(0)
fldt .L_2il0floatpacket.13(%rip)
fld %st(1)
fmul %st(2), %st
addq $-16, %rsp
.cfi_def_cfa_offset 192
fsubp %st, %st(1)
fsqrt
faddp %st, %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
call logl@PLT
..B2.88:
fldt 16(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
..B2.22:
lea ZEROA(%rip), %rax
movsd (%rax), %xmm0
comisd 128(%rsp), %xmm0
jbe ..B2.24
..B2.23:
fldt .L_2il0floatpacket.15(%rip)
lea PIBY2HIA(%rip), %rax
lea PIBY2LOA(%rip), %rdx
fldl (%rax)
faddl (%rdx)
fmulp %st, %st(1)
fsubp %st, %st(1)
..B2.24:
comisd 120(%rsp), %xmm0
jbe ..B2.26
..B2.25:
fldt .L_2il0floatpacket.16(%rip)
fmulp %st, %st(1)
..B2.26:
movb 151(%rsp), %al
lea ones(%rip), %rdx
andb $-128, %al
shrb $7, %al
fxch %st(1)
fstpl (%rsp)
movsd (%rsp), %xmm0
fstpl (%rsp)
movsd (%rsp), %xmm1
andps .L_2il0floatpacket.17(%rip), %xmm1
andps .L_2il0floatpacket.17(%rip), %xmm0
movsd %xmm0, 16(%rsp)
movzbl %al, %ecx
movzwl 22(%rsp), %esi
testl $32752, %esi
mulsd (%rdx,%rcx,8), %xmm1
movsd %xmm1, 24(%rsp)
jne ..B2.29
..B2.27:
testl $1048575, 20(%rsp)
jne ..B2.32
..B2.28:
cmpl $0, 16(%rsp)
jne ..B2.32
..B2.29:
movzwl 30(%rsp), %eax
testl $32752, %eax
jne ..B2.33
..B2.30:
testl $1048575, 28(%rsp)
jne ..B2.32
..B2.31:
cmpl $0, 24(%rsp)
je ..B2.33
..B2.32:
lea _LDB_MIN_NORMAL(%rip), %rax
fldt (%rax)
fmul %st(0), %st
fstpt 48(%rsp)
..B2.33:
testb %r13b, %r13b
je ..B2.35
..B2.34:
fldcw 154(%rsp)
..B2.35:
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
addq $160, %rsp
.cfi_def_cfa_offset 16
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 176
.cfi_offset 13, -16
..B2.36:
movzwl 150(%rsp), %eax
andl $32752, %eax
shrl $4, %eax
..B2.37:
testl %eax, %eax
jne ..B2.47
..B2.38:
testl $1048575, 148(%rsp)
jne ..B2.47
..B2.39:
cmpl $0, 144(%rsp)
jne ..B2.47
..B2.40:
cmpl $2047, %edx
jl ..B2.43
..B2.41:
testl $1048575, 140(%rsp)
jne ..B2.47
..B2.42:
cmpl $0, 136(%rsp)
jne ..B2.47
..B2.43:
cmpl $1023, %edx
jl ..B2.45
..B2.44:
movb 143(%rsp), %r13b
andb $-128, %r13b
shrb $7, %r13b
movsd 136(%rsp), %xmm0
movzbl %r13b, %eax
lea ones(%rip), %r13
movsd (%r13,%rax,8), %xmm1
mulsd %xmm1, %xmm0
movsd %xmm1, (%rsp)
call acosh@PLT
..B2.90:
movsd %xmm0, 16(%rsp)
movsd (%rsp), %xmm0
call acos@PLT
..B2.89:
lea 24(%rsp), %rcx
jmp ..B2.46
..B2.45:
movsd 136(%rsp), %xmm0
movq $0, 16(%rsp)
call acos@PLT
..B2.91:
lea ones(%rip), %r13
lea 24(%rsp), %rcx
..B2.46:
movb 151(%rsp), %al
andb $-128, %al
shrb $7, %al
movzbl %al, %edx
mulsd (%r13,%rdx,8), %xmm0
movsd %xmm0, (%rcx)
movsd 16(%rsp), %xmm0
movhpd 24(%rsp), %xmm0
jmp ..B2.59
..B2.47:
testl %edx, %edx
jne ..B2.54
..B2.48:
testl $1048575, 140(%rsp)
jne ..B2.55
..B2.49:
cmpl $0, 136(%rsp)
jne ..B2.55
..B2.50:
cmpl $2047, %eax
jl ..B2.53
..B2.51:
testl $1048575, 148(%rsp)
jne ..B2.55
..B2.52:
cmpl $0, 144(%rsp)
jne ..B2.55
..B2.53:
movb 151(%rsp), %al
lea ones(%rip), %rdx
andb $-128, %al
shrb $7, %al
movsd 144(%rsp), %xmm1
movsd %xmm1, (%rsp)
movzbl %al, %ecx
movsd (%rdx,%rcx,8), %xmm0
mulsd %xmm1, %xmm0
call asinh@PLT
..B2.93:
movsd %xmm0, 16(%rsp)
movsd 136(%rsp), %xmm1
movsd (%rsp), %xmm0
call atan2@PLT
jmp ..B2.94
..B2.54:
cmpl $2047, %edx
je ..B2.72
..B2.55:
cmpl $2047, %eax
je ..B2.68
..B2.96:
cmpl $2047, %edx
..B2.56:
je ..B2.65
..B2.57:
movsd 144(%rsp), %xmm0
movaps %xmm0, %xmm1
mulsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp)
movsd 136(%rsp), %xmm1
..B2.58:
call atan2@PLT
..B2.94:
movsd %xmm0, 24(%rsp)
movsd 16(%rsp), %xmm0
movhpd 24(%rsp), %xmm0
..B2.59:
movaps %xmm0, %xmm1
unpckhpd %xmm0, %xmm1
addq $160, %rsp
.cfi_def_cfa_offset 16
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 176
.cfi_offset 13, -16
..B2.60:
testl $1048575, 148(%rsp)
jne ..B2.7
..B2.61:
cmpl $0, 144(%rsp)
jne ..B2.7
jmp ..B2.37
..B2.62:
testl $1048575, 140(%rsp)
jne ..B2.5
..B2.63:
cmpl $0, 136(%rsp)
jne ..B2.5
jmp ..B2.36
..B2.65:
testl $1048575, 140(%rsp)
jne ..B2.57
..B2.66:
cmpl $0, 136(%rsp)
jne ..B2.57
..B2.67:
movsd 136(%rsp), %xmm1
movaps %xmm1, %xmm0
mulsd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movsd 144(%rsp), %xmm0
jmp ..B2.58
..B2.68:
testl $1048575, 148(%rsp)
jne ..B2.70
..B2.69:
cmpl $0, 144(%rsp)
je ..B2.95
..B2.70:
cmpl $2047, %edx
jge ..B2.56
..B2.71:
movsd 144(%rsp), %xmm0
mulsd %xmm0, %xmm0
unpcklpd %xmm0, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.59
..B2.72:
testl $1048575, 140(%rsp)
jne ..B2.74
..B2.73:
cmpl $0, 136(%rsp)
je ..B2.75
..B2.74:
cmpl $2047, %eax
je ..B2.79
..B2.75:
testl $1048575, 140(%rsp)
jne ..B2.77
..B2.76:
cmpl $0, 136(%rsp)
je ..B2.55
..B2.77:
cmpl $2047, %eax
jge ..B2.55
..B2.78:
movsd 136(%rsp), %xmm0
mulsd %xmm0, %xmm0
unpcklpd %xmm0, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.59
..B2.79:
testl $1048575, 148(%rsp)
jne ..B2.81
..B2.80:
cmpl $0, 144(%rsp)
je ..B2.75
..B2.81:
movsd 144(%rsp), %xmm1
movsd 136(%rsp), %xmm0
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
unpcklpd %xmm1, %xmm0
movsd %xmm0, 16(%rsp)
movhpd %xmm0, 24(%rsp)
jmp ..B2.59
..B2.95:
cmpl $2047, %edx
je ..B2.65
jmp ..B2.57
.align 16,0x90
.cfi_endproc
.type cacosh,@function
.size cacosh,.-cacosh
.data
# -- End cacosh
.section .rodata, "a"
.align 16
.align 16
.L_2il0floatpacket.13:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.13,@object
.size .L_2il0floatpacket.13,16
.align 16
.L_2il0floatpacket.14:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xfe,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.14,@object
.size .L_2il0floatpacket.14,16
.align 16
.L_2il0floatpacket.15:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.15,@object
.size .L_2il0floatpacket.15,16
.align 16
.L_2il0floatpacket.16:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.16,@object
.size .L_2il0floatpacket.16,16
.align 16
.L_2il0floatpacket.17:
.long 0xffffffff,0x7fffffff,0x00000000,0x00000000
.type .L_2il0floatpacket.17,@object
.size .L_2il0floatpacket.17,16
.align 16
BcrossA:
.long 3621516424
.long 2756080513
.long 16382
.long 0
.type BcrossA,@object
.size BcrossA,16
.align 16
AcrossA:
.long 0
.long 3221225472
.long 16383
.long 0
.type AcrossA,@object
.size AcrossA,16
.align 16
ZEROA:
.long 0
.long 0
.type ZEROA,@object
.size ZEROA,8
.space 8, 0x00 # pad
.align 16
PIBY2HIA:
.long 1413754136
.long 1073291771
.type PIBY2HIA,@object
.size PIBY2HIA,8
.space 8, 0x00 # pad
.align 16
PIBY2LOA:
.long 856972295
.long 1016178214
.type PIBY2LOA,@object
.size PIBY2LOA,8
.space 8, 0x00 # pad
.align 16
_LDB_MIN_NORMAL:
.word 0
.word 0
.word 0
.word 32768
.word 1
.word 0
.word 0
.word 0
.type _LDB_MIN_NORMAL,@object
.size _LDB_MIN_NORMAL,16
.align 8
ones:
.long 0x00000000,0x3ff00000
.long 0x00000000,0xbff00000
.type ones,@object
.size ones,16
.align 4
.L_2il0floatpacket.12:
.long 0x00800000
.type .L_2il0floatpacket.12,@object
.size .L_2il0floatpacket.12,4
.data
.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
GeminiCarrie/rust-sgx-sdk | 187,598 | sgx_libc/sgx_tlibc_sys/tlibc/math/lgammal.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "lgammal.c"
.text
..TXTST0:
# -- Begin lgammal
.text
.align 16,0x90
.globl lgammal
lgammal:
# parameter 1: 16 + %rsp
..B1.1:
.cfi_startproc
..___tag_value_lgammal.1:
..L2:
pushq %rsi
.cfi_def_cfa_offset 16
fldt 16(%rsp)
addq $-16, %rsp
.cfi_def_cfa_offset 32
lea 16(%rsp), %rdi
fstpt (%rsp)
..___tag_value_lgammal.5:
call __libm_lgammal
..___tag_value_lgammal.6:
..B1.2:
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type lgammal,@function
.size lgammal,.-lgammal
.data
# -- End lgammal
.text
# -- Begin __libm_lgammal
.text
.align 16,0x90
__libm_lgammal:
# parameter 1: 336 + %rsp
# parameter 2: %rdi
..B2.1:
.cfi_startproc
..___tag_value___libm_lgammal.9:
..L10:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r14
.cfi_def_cfa_offset 32
.cfi_offset 14, -32
pushq %r15
.cfi_def_cfa_offset 40
.cfi_offset 15, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
pushq %rbp
.cfi_def_cfa_offset 56
.cfi_offset 6, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movq %rdi, %rbp
movq %fs:40, %rax
xorl %r12d, %r12d
xorq %rsp, %rax
xorb %r14b, %r14b
movq %rax, 272(%rsp)
..B2.2:
fnstcw 194(%rsp)
..B2.3:
..___tag_value___libm_lgammal.24:
call fegetround@PLT
..___tag_value___libm_lgammal.25:
..B2.275:
movl %eax, %r13d
..B2.4:
testl %r13d, %r13d
je ..B2.6
..B2.5:
xorl %edi, %edi
movl $1, %r12d
..___tag_value___libm_lgammal.26:
call fesetround@PLT
..___tag_value___libm_lgammal.27:
..B2.6:
movzwl 194(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B2.10
..B2.7:
orl $-64768, %edx
movw %dx, 192(%rsp)
..B2.8:
fldcw 192(%rsp)
..B2.9:
movb $1, %r14b
..B2.10:
movzbl 345(%rsp), %ecx
lea ones(%rip), %rax
movl %ecx, %r15d
andl $128, %r15d
shrl $7, %r15d
movzwl 344(%rsp), %ebx
movss (%rax,%r15,4), %xmm0
andl $32767, %ebx
shll $15, %r15d
orl %ebx, %r15d
shll $16, %r15d
movzwl 342(%rsp), %edx
orl %edx, %r15d
cmpl $32767, %ebx
je ..B2.259
..B2.11:
fldt 336(%rsp)
fldt .L_2il0floatpacket.0(%rip)
fucomi %st(1), %st
jp ..B2.12
je ..B2.252
..B2.12:
lea _OFW_BOUND(%rip), %rax
fldt (%rax)
fcomip %st(2), %st
jb ..B2.244
..B2.13:
fldt .L_2il0floatpacket.1(%rip)
fucomip %st(2), %st
jp ..B2.14
je ..B2.235
..B2.14:
fldt .L_2il0floatpacket.2(%rip)
fucomip %st(2), %st
jp ..B2.15
je ..B2.235
..B2.15:
testl %r15d, %r15d
jl ..B2.227
..B2.16:
cmpl $16382, %ebx
jl ..B2.163
..B2.17:
cmpl $16463, %ebx
jge ..B2.156
..B2.18:
fldt .L_2il0floatpacket.4(%rip)
fcomip %st(2), %st
jbe ..B2.146
..B2.19:
fldt .L_2il0floatpacket.5(%rip)
fcomip %st(2), %st
jae ..B2.113
jp ..B2.113
..B2.20:
movl %r15d, %eax
andl $2147483647, %eax
cmpl $1073659904, %eax
jl ..B2.104
..B2.21:
fcomi %st(1), %st
jae ..B2.24
jp ..B2.24
..B2.22:
fldt .L_2il0floatpacket.10(%rip)
fcomip %st(2), %st
jbe ..B2.24
..B2.23:
fstp %st(0)
fldt .L_2il0floatpacket.11(%rip)
movl $1, (%rbp)
jmp ..B2.27
..B2.24:
fldt .L_2il0floatpacket.11(%rip)
fcomi %st(2), %st
jae ..B2.37
jp ..B2.37
..B2.25:
fldt .L_2il0floatpacket.12(%rip)
fcomip %st(3), %st
jbe ..B2.37
..B2.26:
fstp %st(1)
movl $1, (%rbp)
..B2.27:
lea 2800+_ldbA(%rip), %rdx
lea 480+_dbA(%rip), %rcx
fcomip %st(1), %st
jae ..B2.29
jp ..B2.29
..B2.28:
fldt .L_2il0floatpacket.2(%rip)
lea 656+_dbA(%rip), %rcx
lea 2912+_ldbA(%rip), %rdx
fsubrp %st, %st(1)
jmp ..B2.30
..B2.29:
fldt .L_2il0floatpacket.1(%rip)
fsubp %st, %st(1)
..B2.30:
fldl 88(%rcx)
lea _TWO_32H(%rip), %rax
fmul %st(1), %st
fld %st(1)
fld %st(2)
testl %r12d, %r12d
fldl (%rax)
fmul %st, %st(2)
fxch %st(1)
fadd %st(2), %st
fsubp %st, %st(2)
fld %st(3)
fsub %st(2), %st
fldt (%rdx)
fxch %st(4)
faddl 104(%rcx)
fmul %st(5), %st
fldt 48(%rdx)
fldt 16(%rdx)
fxch %st(2)
faddl 96(%rcx)
fmul %st(7), %st
faddl 80(%rcx)
fmul %st(7), %st
faddl 152(%rcx)
fmul %st(7), %st
faddl 120(%rcx)
fmul %st(7), %st
faddl 112(%rcx)
fmul %st(7), %st
faddl 136(%rcx)
fmul %st(7), %st
faddl 128(%rcx)
fmul %st(7), %st
faddl 40(%rcx)
fmul %st(7), %st
faddl 32(%rcx)
fmul %st(7), %st
faddl 56(%rcx)
fmul %st(7), %st
faddl 48(%rcx)
fmul %st(7), %st
faddl 144(%rcx)
fmul %st(7), %st
faddp %st, %st(6)
fxch %st(5)
fmul %st(6), %st
faddp %st, %st(5)
fxch %st(4)
fmul %st(5), %st
faddp %st, %st(4)
fxch %st(3)
fmul %st(4), %st
fldt 64(%rdx)
faddp %st, %st(1)
fmul %st(4), %st
fldt 32(%rdx)
faddp %st, %st(1)
fmul %st(4), %st
fldt 80(%rdx)
faddp %st, %st(1)
fmul %st(4), %st
fld %st(1)
fldt 96(%rdx)
faddp %st, %st(2)
fmul %st(1), %st
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(0)
fmul %st(4), %st
fxch %st(1)
fsubr %st, %st(2)
fxch %st(2)
fmul %st(6), %st
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(2)
fldl (%rcx)
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(3)
fmul %st(2), %st
fxch %st(1)
faddl 72(%rcx)
faddp %st, %st(3)
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fmul %st(5), %st
fld %st(3)
fmul %st(2), %st
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(1)
fldl 16(%rcx)
fld %st(0)
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fxch %st(1)
faddl 168(%rcx)
faddp %st, %st(2)
fld %st(3)
fmul %st(3), %st
fadd %st, %st(1)
fsubrp %st, %st(1)
fsubr %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
fmul %st(5), %st
fld %st(3)
fmul %st(2), %st
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(1)
fldl 64(%rcx)
fld %st(0)
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fxch %st(1)
faddl 8(%rcx)
faddp %st, %st(2)
fld %st(3)
fmul %st(3), %st
fadd %st, %st(1)
fsubrp %st, %st(1)
fsubr %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
fmul %st(5), %st
fld %st(3)
fmul %st(2), %st
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(1)
fldl 160(%rcx)
fld %st(0)
fadd %st(3), %st
fmul %st, %st(4)
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
faddl 24(%rcx)
faddp %st, %st(1)
fld %st(1)
fadd %st(3), %st
fsubp %st, %st(3)
fxch %st(2)
fmul %st, %st(4)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fmulp %st, %st(4)
fxch %st(3)
faddp %st, %st(2)
fxch %st(1)
fstpt 16(%rsp)
fldt 16(%rsp)
fxch %st(2)
fmulp %st, %st(1)
fstpt (%rsp)
fldt (%rsp)
fxch %st(1)
je ..B2.33
..B2.31:
fstp %st(1)
fstp %st(0)
movl %r13d, %edi
..___tag_value___libm_lgammal.28:
call fesetround@PLT
..___tag_value___libm_lgammal.29:
..B2.32:
fldt (%rsp)
fldt 16(%rsp)
..B2.33:
testb %r14b, %r14b
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.35
..B2.34:
fldcw 194(%rsp)
..B2.35:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.36:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.37:
fstp %st(0)
fcomi %st(1), %st
jae ..B2.46
jp ..B2.46
..B2.38:
fldt .L_2il0floatpacket.2(%rip)
fcomip %st(2), %st
jbe ..B2.46
..B2.39:
fstp %st(0)
lea 3024+_ldbA(%rip), %rax
addq $-16, %rsp
.cfi_def_cfa_offset 352
lea 3040+_ldbA(%rip), %rdi
lea 832+_dbA(%rip), %rsi
movl $1, (%rbp)
lea 16(%rsp), %rdx
fldt (%rax)
fsubrp %st, %st(1)
fstpt (%rsp)
..___tag_value___libm_lgammal.51:
call __libm_p25
..___tag_value___libm_lgammal.52:
..B2.276:
addq $16, %rsp
.cfi_def_cfa_offset 336
..B2.40:
testl %r12d, %r12d
je ..B2.42
..B2.41:
movl %r13d, %edi
..___tag_value___libm_lgammal.54:
call fesetround@PLT
..___tag_value___libm_lgammal.55:
..B2.42:
fldt (%rsp)
testb %r14b, %r14b
fldt 16(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.44
..B2.43:
fldcw 194(%rsp)
..B2.44:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.45:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.46:
fcomi %st(1), %st
jbe ..B2.95
..B2.47:
fldt .L_2il0floatpacket.14(%rip)
fcomi %st(2), %st
jae ..B2.56
jp ..B2.56
..B2.48:
fstp %st(0)
fldt .L_2il0floatpacket.15(%rip)
fcomi %st(2), %st
jbe ..B2.56
..B2.49:
fstp %st(1)
addq $-16, %rsp
.cfi_def_cfa_offset 352
lea 3424+_ldbA(%rip), %rdi
lea 1360+_dbA(%rip), %rsi
lea 16(%rsp), %rdx
movl $-1, (%rbp)
fsubrp %st, %st(1)
fstpt (%rsp)
..___tag_value___libm_lgammal.77:
call __libm_p25
..___tag_value___libm_lgammal.78:
..B2.277:
addq $16, %rsp
.cfi_def_cfa_offset 336
..B2.50:
testl %r12d, %r12d
je ..B2.52
..B2.51:
movl %r13d, %edi
..___tag_value___libm_lgammal.80:
call fesetround@PLT
..___tag_value___libm_lgammal.81:
..B2.52:
fldt (%rsp)
testb %r14b, %r14b
fldt 16(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.54
..B2.53:
fldcw 194(%rsp)
..B2.54:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.55:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.56:
fstp %st(0)
addq $-16, %rsp
.cfi_def_cfa_offset 352
fstp %st(0)
fstpt (%rsp)
fldt (%rsp)
fstpt 64(%rsp)
call nearbyintl@PLT
..B2.278:
fldt 64(%rsp)
fldt .L_2il0floatpacket.0(%rip)
addq $16, %rsp
.cfi_def_cfa_offset 336
fxch %st(2)
fucomi %st(1), %st
jp ..B2.57
je ..B2.191
..B2.57:
fldt .L_2il0floatpacket.17(%rip)
fcomip %st(2), %st
ja ..B2.69
jp ..B2.69
..B2.58:
fldt .L_2il0floatpacket.18(%rip)
fcomip %st(2), %st
jb ..B2.69
..B2.59:
fstp %st(0)
fldt .L_2il0floatpacket.19(%rip)
fcomip %st(1), %st
jae ..B2.61
jp ..B2.61
..B2.60:
movl $-1, (%rbp)
jmp ..B2.62
..B2.61:
movl $1, (%rbp)
..B2.62:
fldt .L_2il0floatpacket.1(%rip)
lea ones(%rip), %rdx
faddp %st, %st(1)
fstpt 96(%rsp)
fldt 96(%rsp)
fld %st(0)
movb 105(%rsp), %al
andb $-128, %al
shrb $7, %al
fmul %st(1), %st
fstpt 128(%rsp)
fld %st(0)
fchs
movzbl %al, %ecx
fstpt 16(%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 368
lea 240(%rsp), %rdi
fmuls (%rdx,%rcx,4)
fstpt (%rsp)
fstpt 16(%rsp)
..___tag_value___libm_lgammal.105:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.106:
..B2.279:
fstp %st(0)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.63:
fldt 96(%rsp)
lea 1560+_dbA(%rip), %rax
fldt 16(%rsp)
lea 1552+_dbA(%rip), %rdx
lea 1544+_dbA(%rip), %rcx
lea 1536+_dbA(%rip), %rbx
lea 3600+_ldbA(%rip), %rbp
lea 3584+_ldbA(%rip), %rsi
fldl (%rax)
lea 1568+_dbA(%rip), %r10
fmul %st(2), %st
lea 1576+_dbA(%rip), %r11
fldt (%rbp)
lea 1584+_dbA(%rip), %r15
fldt (%rsi)
lea 1592+_dbA(%rip), %rax
lea 3568+_ldbA(%rip), %r8
lea 3552+_ldbA(%rip), %r9
testl %r12d, %r12d
fxch %st(2)
faddl (%rdx)
fmul %st(4), %st
fldt (%r8)
fldt (%r9)
fxch %st(2)
faddl (%rcx)
fmul %st(6), %st
faddl (%rbx)
fmul %st(6), %st
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(3)
fxch %st(2)
fmul %st(4), %st
faddp %st, %st(1)
fmul %st(3), %st
faddp %st, %st(1)
fmulp %st, %st(2)
fldl (%r10)
fmul %st(1), %st
fldt 128(%rsp)
fxch %st(1)
faddl (%r11)
fmul %st(2), %st
faddl (%r15)
fmul %st(2), %st
faddl (%rax)
lea 1600+_dbA(%rip), %rax
fmul %st(2), %st
faddl (%rax)
lea 1608+_dbA(%rip), %rax
fmul %st(2), %st
faddl (%rax)
lea 1616+_dbA(%rip), %rax
fmul %st(2), %st
faddl (%rax)
lea 1624+_dbA(%rip), %rax
fmul %st(2), %st
faddl (%rax)
lea 3664+_ldbA(%rip), %rax
fmul %st(2), %st
fmul %st(2), %st
faddp %st, %st(2)
fxch %st(1)
fstpt 240(%rsp)
fldt 240(%rsp)
faddp %st, %st(2)
fldt (%rax)
lea 3648+_ldbA(%rip), %rax
fmul %st(1), %st
fldt (%rax)
lea 3632+_ldbA(%rip), %rax
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rax)
lea 3616+_ldbA(%rip), %rax
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rax)
faddp %st, %st(1)
fmulp %st, %st(1)
fsubp %st, %st(1)
fstpt (%rsp)
je ..B2.65
..B2.64:
movl %r13d, %edi
..___tag_value___libm_lgammal.108:
call fesetround@PLT
..___tag_value___libm_lgammal.109:
..B2.65:
fldt 224(%rsp)
testb %r14b, %r14b
fldt (%rsp)
fsubp %st, %st(1)
fldt 208(%rsp)
fsubrp %st, %st(1)
fstpt 176(%rsp)
je ..B2.67
..B2.66:
fldcw 194(%rsp)
..B2.67:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.68:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.69:
fnstcw (%rsp)
movzwl (%rsp), %eax
orl $3072, %eax
movl %eax, 8(%rsp)
fldcw 8(%rsp)
fistl 16(%rsp)
fldcw (%rsp)
fld %st(1)
lea 848+_ldbA(%rip), %r8
movl 16(%rsp), %edx
fsubp %st, %st(1)
negl %edx
lea -2(%rdx), %eax
andl $1, %edx
jne ..B2.72
..B2.70:
fcomi %st(2), %st
jae ..B2.73
jp ..B2.73
..B2.71:
movl $-1, (%rbp)
jmp ..B2.74
..B2.72:
jne ..B2.188
..B2.73:
movl $1, (%rbp)
..B2.74:
fldt .L_2il0floatpacket.20(%rip)
xorl %edx, %edx
fxch %st(2)
fcomi %st(2), %st
fxch %st(2)
fstp %st(0)
cmova %edx, %eax
movl $17, %ecx
xorl %ebp, %ebp
lea 1424+_ldbA(%rip), %rdx
fcomi %st(2), %st
cmova %ecx, %ebp
addl %ebp, %eax
movslq %eax, %rsi
shlq $4, %rsi
fldt (%rsi,%r8)
lea (%rax,%rax), %r8d
movslq %r8d, %r8
fsubr %st(2), %st
shlq $4, %r8
fldt (%r8,%rdx)
fcomip %st(3), %st
jae ..B2.84
jp ..B2.84
..B2.75:
fldt 16(%r8,%rdx)
fcomip %st(3), %st
jbe ..B2.84
..B2.77:
fstp %st(3)
fstp %st(1)
lea _ldbA(%rip), %rbx
lea (%rax,%rax,2), %ecx
movslq %ecx, %rcx
lea (%rax,%rax,4), %eax
shll $2, %eax
lea _dbA(%rip), %rbp
shlq $4, %rcx
addq $-16, %rsp
.cfi_def_cfa_offset 352
movslq %eax, %rax
lea 256(%rsp), %rdx
fxch %st(1)
fstpt (%rsp)
lea 4480(%rbx,%rcx), %rdi
fstpt 16(%rsp)
lea 2432(%rbp,%rax,8), %rsi
..___tag_value___libm_lgammal.131:
call __libm_p19root
..___tag_value___libm_lgammal.132:
..B2.280:
fldt 16(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 336
..B2.78:
testl %r12d, %r12d
je ..B2.80
..B2.79:
movl %r13d, %edi
fstpt (%rsp)
..___tag_value___libm_lgammal.134:
call fesetround@PLT
..___tag_value___libm_lgammal.135:
..B2.305:
fldt (%rsp)
..B2.80:
fldt 240(%rsp)
testb %r14b, %r14b
fldt 256(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.311
..B2.81:
fstpt 96(%rsp)
..B2.281:
fldcw 194(%rsp)
jmp ..B2.82
..B2.311:
fstp %st(0)
..B2.82:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.83:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.84:
fstp %st(0)
fstpt 96(%rsp)
..B2.85:
lea -16382(%rbx), %eax
cmpl $2, %eax
jne ..B2.87
..B2.86:
fldt .L_2il0floatpacket.21(%rip)
addl $-16380, %ebx
fcomip %st(1), %st
cmova %ebx, %eax
..B2.87:
fldt .L_2il0floatpacket.19(%rip)
lea (%rax,%rax,4), %edx
fmul %st, %st(1)
lea (%rdx,%rdx), %eax
fstp %st(2)
fstpt 80(%rsp)
lea _dbA(%rip), %rsi
fldt .L_2il0floatpacket.16(%rip)
lea _ldbA(%rip), %rbx
movzwl 88(%rsp), %ecx
lea _TWO_32H(%rip), %rbp
andl $-32768, %ecx
orl $-49153, %ecx
movw %cx, 88(%rsp)
fldt 80(%rsp)
shll $2, %edx
fsubp %st, %st(1)
movslq %edx, %rdx
movslq %eax, %rax
shlq $4, %rax
fstpt 80(%rsp)
fldt 80(%rsp)
fldl 1784(%rsi,%rdx,8)
fmul %st(1), %st
fldt 3824(%rbx,%rax)
fldt 3808(%rbx,%rax)
fldt 3792(%rbx,%rax)
fldt 3776(%rbx,%rax)
fldt 3760(%rbx,%rax)
fxch %st(5)
faddl 1776(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1768(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1760(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1752(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1744(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1736(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1728(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1720(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1712(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1704(%rsi,%rdx,8)
fmul %st(6), %st
faddl 1696(%rsi,%rdx,8)
fmul %st(6), %st
faddp %st, %st(4)
fxch %st(3)
fmul %st(5), %st
faddp %st, %st(2)
fxch %st(1)
fmul %st(4), %st
faddp %st, %st(1)
fmul %st(3), %st
faddp %st, %st(1)
fmul %st(2), %st
faddp %st, %st(1)
fmul %st(1), %st
fldt 3744(%rbx,%rax)
faddp %st, %st(1)
fmul %st(1), %st
fldt 3728(%rbx,%rax)
faddp %st, %st(1)
fmul %st(1), %st
fld %st(1)
fldt 3712(%rbx,%rax)
faddp %st, %st(2)
fxch %st(1)
fmul %st(2), %st
fldt 3696(%rbx,%rax)
faddp %st, %st(1)
fmul %st(2), %st
fldt 3680(%rbx,%rax)
faddp %st, %st(1)
fldl (%rbp)
fld %st(0)
fmul %st(4), %st
fadd %st, %st(3)
fsubrp %st, %st(3)
fxch %st(2)
fstpt 160(%rsp)
fldt 160(%rsp)
fld %st(2)
fmul %st(2), %st
fld %st(2)
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(0)
fmul %st(2), %st
fxch %st(1)
fsubr %st, %st(3)
fld %st(3)
fmul %st(3), %st
fxch %st(3)
fsubr %st, %st(6)
fxch %st(1)
fmul %st(6), %st
faddp %st, %st(3)
fxch %st(3)
fmul %st(5), %st
faddp %st, %st(2)
fldl 1632(%rsi,%rdx,8)
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(4)
fmul %st(2), %st
fxch %st(1)
faddl 1640(%rsi,%rdx,8)
faddp %st, %st(3)
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(0)
fmul %st(4), %st
fxch %st(1)
fsubr %st, %st(2)
fxch %st(3)
faddp %st, %st(2)
fld %st(1)
fmul %st(4), %st
fxch %st(3)
fmul %st(6), %st
faddp %st, %st(3)
fxch %st(1)
fmul %st(5), %st
faddp %st, %st(2)
fldl 1680(%rsi,%rdx,8)
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(4)
fmul %st(2), %st
fxch %st(1)
faddl 1688(%rsi,%rdx,8)
faddp %st, %st(3)
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(0)
fmul %st(4), %st
fxch %st(1)
fsubr %st, %st(2)
fxch %st(3)
faddp %st, %st(2)
fld %st(1)
fmul %st(4), %st
fxch %st(3)
fmul %st(6), %st
faddp %st, %st(3)
fxch %st(1)
fmul %st(5), %st
faddp %st, %st(2)
fldl 1664(%rsi,%rdx,8)
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(1)
fxch %st(1)
faddl 1672(%rsi,%rdx,8)
faddp %st, %st(3)
fld %st(4)
fmul %st(2), %st
fstpt 128(%rsp)
fldt 128(%rsp)
fadd %st, %st(1)
fxch %st(1)
fstpt 144(%rsp)
fldt 144(%rsp)
fsubp %st, %st(1)
fld %st(0)
fmul %st(4), %st
fxch %st(1)
fsubr %st, %st(2)
fxch %st(3)
faddp %st, %st(2)
fxch %st(1)
fmul %st, %st(3)
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(3)
fxch %st(1)
fmulp %st, %st(4)
fxch %st(3)
faddp %st, %st(1)
fldl 1648(%rsi,%rdx,8)
fld %st(0)
fadd %st(4), %st
fstpt 16(%rsp)
fldt 16(%rsp)
fsubrp %st, %st(1)
faddp %st, %st(3)
fldt .L_2il0floatpacket.0(%rip)
fxch %st(3)
faddl 1656(%rsi,%rdx,8)
faddp %st, %st(1)
fstpt (%rsp)
fldt 336(%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 368
fmulp %st, %st(3)
lea 272(%rsp), %rdi
fxch %st(2)
fstpt (%rsp)
fstpt 16(%rsp)
fstpt 64(%rsp)
..___tag_value___libm_lgammal.157:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.158:
..B2.282:
fstp %st(0)
fldt .L_2il0floatpacket.0(%rip)
fldt 64(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.88:
fldt 96(%rsp)
lea ones(%rip), %rdx
movb 105(%rsp), %al
addq $-32, %rsp
.cfi_def_cfa_offset 368
andb $-128, %al
lea 240(%rsp), %rdi
shrb $7, %al
movzbl %al, %ecx
fmuls (%rdx,%rcx,4)
fstpt (%rsp)
fldt (%rsp)
fxch %st(2)
fstpt 16(%rsp)
fxch %st(1)
fstpt 80(%rsp)
fstpt 64(%rsp)
..___tag_value___libm_lgammal.161:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.162:
..B2.283:
fstp %st(0)
fldt 64(%rsp)
fldt 80(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.89:
fld %st(0)
lea 544+_ldbA(%rip), %rcx
fmul %st(2), %st
fld %st(1)
lea 528+_ldbA(%rip), %rbx
lea 512+_ldbA(%rip), %rbp
lea 496+_ldbA(%rip), %rsi
lea 480+_ldbA(%rip), %r8
lea 464+_ldbA(%rip), %r9
lea 448+_ldbA(%rip), %r10
lea 432+_ldbA(%rip), %r11
lea 416+_ldbA(%rip), %r15
lea 304+_ldbA(%rip), %rax
lea 48+_dbA(%rip), %rdx
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(1)
fsub %st(1), %st
fxch %st(2)
fmul %st(0), %st
fldt (%rcx)
lea 400+_ldbA(%rip), %rcx
fmul %st(1), %st
fldt (%rbx)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rbp)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rsi)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r8)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r9)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r10)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r11)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r15)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 384+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 368+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 352+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 336+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fld %st(2)
fmul %st(3), %st
fldt (%rcx)
lea 320+_ldbA(%rip), %rcx
faddp %st, %st(2)
fxch %st(1)
fmul %st(2), %st
fldt (%rcx)
faddp %st, %st(1)
fmulp %st, %st(2)
fldt (%rax)
lea 64+_dbA(%rip), %rax
faddp %st, %st(2)
fld %st(0)
fldt .L_2il0floatpacket.2(%rip)
fmulp %st, %st(4)
fxch %st(3)
fmul %st(4), %st
fld %st(5)
fmul %st(3), %st
fxch %st(5)
fmul %st(0), %st
faddp %st, %st(1)
fld %st(5)
fmul %st(2), %st
fadd %st, %st(4)
fsubrp %st, %st(4)
fld %st(3)
fld %st(3)
fadd %st(6), %st
fsubp %st, %st(6)
fmul %st(5), %st
fxch %st(2)
fsub %st(4), %st
faddp %st, %st(1)
fld %st(3)
fxch %st(3)
fsub %st(5), %st
fmul %st, %st(3)
fxch %st(1)
fmul %st, %st(5)
fxch %st(5)
faddp %st, %st(3)
fmul %st(4), %st
faddp %st, %st(2)
fldl (%rax)
fld %st(0)
lea 72+_dbA(%rip), %rax
fadd %st(2), %st
fld %st(0)
fxch %st(1)
fsubr %st, %st(2)
fxch %st(3)
faddp %st, %st(2)
fld %st(6)
fmul %st(3), %st
fadd %st, %st(1)
fsubrp %st, %st(1)
fsubr %st, %st(2)
fld %st(4)
fxch %st(2)
faddl (%rax)
lea 56+_dbA(%rip), %rax
faddp %st, %st(4)
fxch %st(3)
faddp %st, %st(2)
fmul %st(1), %st
fld %st(3)
fmul %st(3), %st
fxch %st(3)
fmul %st(5), %st
faddp %st, %st(1)
fxch %st(1)
fmul %st(4), %st
faddp %st, %st(1)
fldl (%rdx)
fld %st(0)
lea ones(%rip), %rdx
fadd %st(3), %st
fmul %st, %st(6)
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fadd %st(6), %st
fsubp %st, %st(6)
fxch %st(2)
fsub %st(5), %st
fld %st(3)
fmul %st(6), %st
fstpt 64(%rsp)
fxch %st(4)
fmul %st, %st(5)
fxch %st(2)
faddl (%rax)
faddp %st, %st(1)
faddp %st, %st(3)
fxch %st(1)
fmul %st(2), %st
faddp %st, %st(3)
fmulp %st, %st(1)
faddp %st, %st(1)
fstpt 80(%rsp)
fldt 16(%rsp)
fld %st(0)
fld %st(1)
fld %st(2)
fldt (%rsp)
fadd %st, %st(1)
fxch %st(1)
fstpt 128(%rsp)
fldt 128(%rsp)
fldt 240(%rsp)
fld %st(0)
fxch %st(1)
fadd %st, %st(5)
movb 137(%rsp), %al
fxch %st(4)
fsub %st(5), %st
andb $-128, %al
fadd %st(4), %st
shrb $7, %al
fadd %st(3), %st
fxch %st(4)
fsub %st(5), %st
movzbl %al, %eax
faddp %st, %st(6)
fxch %st(1)
fmuls (%rdx,%rax,4)
fldt 256(%rsp)
fadd %st, %st(2)
fxch %st(2)
fstpt 144(%rsp)
fldt 144(%rsp)
fxch %st(2)
fadd %st, %st(6)
movb 153(%rsp), %al
fxch %st(3)
faddp %st, %st(6)
fxch %st(2)
faddp %st, %st(3)
fldt 208(%rsp)
andb $-128, %al
fld %st(0)
fldt 64(%rsp)
shrb $7, %al
fadd %st, %st(1)
fxch %st(1)
fchs
fadd %st, %st(2)
movzbl %al, %eax
fxch %st(2)
fchs
fsubp %st, %st(1)
fld %st(1)
fsub %st(6), %st
fstpt 48(%rsp)
fldt 48(%rsp)
fxch %st(3)
fmuls (%rdx,%rax,4)
fxch %st(4)
fcomip %st(4), %st
fxch %st(3)
fstp %st(0)
fxch %st(5)
fcmovnbe %st(3), %st
fstp %st(3)
fld %st(4)
fldt 224(%rsp)
fsubrp %st, %st(3)
fld %st(4)
fadd %st(4), %st
fstpt 144(%rsp)
fldt 144(%rsp)
fldt 80(%rsp)
fsubrp %st, %st(4)
fxch %st(1)
fadd %st(3), %st
fstpt 128(%rsp)
fldt 128(%rsp)
fld %st(6)
movb 137(%rsp), %al
fsub %st(3), %st
andb $-128, %al
fsub %st(6), %st
shrb $7, %al
fadd %st(4), %st
movzbl %al, %eax
fsub %st(5), %st
fxch %st(3)
faddp %st, %st(6)
fxch %st(5)
fchs
faddp %st, %st(6)
fxch %st(3)
fsubrp %st, %st(5)
fxch %st(1)
faddp %st, %st(4)
fxch %st(2)
fmuls (%rdx,%rax,4)
movb 153(%rsp), %al
andb $-128, %al
shrb $7, %al
fstpt 128(%rsp)
fldt 128(%rsp)
movzbl %al, %eax
fxch %st(1)
fmuls (%rdx,%rax,4)
fxch %st(1)
fcomip %st(1), %st
fxch %st(2)
fcmovnbe %st(1), %st
fstp %st(1)
fstpt 32(%rsp)
testl %r12d, %r12d
je ..B2.91
..B2.90:
movl %r13d, %edi
fstpt (%rsp)
..___tag_value___libm_lgammal.164:
call fesetround@PLT
..___tag_value___libm_lgammal.165:
..B2.303:
fldt (%rsp)
..B2.91:
fldt 32(%rsp)
testb %r14b, %r14b
fldt 48(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.312
..B2.92:
fstpt 144(%rsp)
..B2.284:
fldcw 194(%rsp)
jmp ..B2.93
..B2.312:
fstp %st(0)
..B2.93:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.94:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.95:
fstp %st(0)
fldt .L_2il0floatpacket.13(%rip)
lea 3168+_ldbA(%rip), %rdi
movl $1, (%rbp)
lea 1008+_dbA(%rip), %rsi
fmul %st, %st(1)
cmpl $16385, %ebx
jne ..B2.97
..B2.96:
fmul %st, %st(1)
lea 1184+_dbA(%rip), %rsi
lea 3296+_ldbA(%rip), %rdi
..B2.97:
fstp %st(0)
fldt .L_2il0floatpacket.16(%rip)
addq $-16, %rsp
.cfi_def_cfa_offset 352
fsubrp %st, %st(1)
fstpt (%rsp)
lea 16(%rsp), %rdx
..___tag_value___libm_lgammal.187:
call __libm_p25
..___tag_value___libm_lgammal.188:
..B2.285:
addq $16, %rsp
.cfi_def_cfa_offset 336
..B2.98:
testl %r12d, %r12d
je ..B2.100
..B2.99:
movl %r13d, %edi
..___tag_value___libm_lgammal.190:
call fesetround@PLT
..___tag_value___libm_lgammal.191:
..B2.100:
fldt (%rsp)
testb %r14b, %r14b
fldt 16(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.102
..B2.101:
fldcw 194(%rsp)
..B2.102:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.103:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.104:
fstp %st(0)
fldt .L_2il0floatpacket.8(%rip)
lea 2544+_ldbA(%rip), %rdi
lea 128+_dbA(%rip), %rsi
testl %r15d, %r15d
fsubr %st(1), %st
jl ..B2.200
..B2.105:
fstp %st(1)
movl $1, (%rbp)
..B2.106:
addq $-16, %rsp
.cfi_def_cfa_offset 352
lea 16(%rsp), %rdx
fstpt (%rsp)
..___tag_value___libm_lgammal.213:
call __libm_p25
..___tag_value___libm_lgammal.214:
..B2.286:
addq $16, %rsp
.cfi_def_cfa_offset 336
..B2.107:
testl %r12d, %r12d
je ..B2.109
..B2.108:
movl %r13d, %edi
..___tag_value___libm_lgammal.216:
call fesetround@PLT
..___tag_value___libm_lgammal.217:
..B2.109:
fldt (%rsp)
testb %r14b, %r14b
fldt 16(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.111
..B2.110:
fldcw 194(%rsp)
..B2.111:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.112:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.113:
addq $-16, %rsp
.cfi_def_cfa_offset 352
fstp %st(0)
fstpt (%rsp)
fldt (%rsp)
movss %xmm0, 48(%rsp)
fstpt 64(%rsp)
call nearbyintl@PLT
..B2.287:
fldt 64(%rsp)
fld %st(0)
movss 48(%rsp), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 336
fsub %st(2), %st
fldt .L_2il0floatpacket.0(%rip)
fucomi %st(1), %st
jp ..B2.114
je ..B2.209
..B2.114:
fldt .L_2il0floatpacket.9(%rip)
fcomip %st(3), %st
jae ..B2.131
jp ..B2.131
..B2.115:
fxch %st(3)
fnstcw (%rsp)
movzwl (%rsp), %eax
orl $3072, %eax
movl %eax, 8(%rsp)
fldcw 8(%rsp)
fistl 16(%rsp)
fldcw (%rsp)
lea 848+_ldbA(%rip), %rbx
movl 16(%rsp), %r8d
movl %r8d, %edx
negl %edx
lea -2(%rdx), %eax
addl $15, %edx
fxch %st(1)
fcomi %st(3), %st
cmova %edx, %eax
lea 1424+_ldbA(%rip), %rdx
movslq %eax, %rcx
shlq $4, %rcx
lea (%rax,%rax), %esi
movslq %esi, %rsi
fldt (%rcx,%rbx)
shlq $4, %rsi
fsubr %st(3), %st
fldt (%rsi,%rdx)
fcomip %st(4), %st
jae ..B2.129
jp ..B2.129
..B2.116:
fldt 16(%rsi,%rdx)
fcomip %st(4), %st
jbe ..B2.129
..B2.117:
fstp %st(2)
fstp %st(2)
negl %r8d
andl $1, %r8d
jne ..B2.120
..B2.118:
fxch %st(2)
fcomi %st(1), %st
fxch %st(2)
jbe ..B2.121
..B2.119:
fstp %st(2)
movl $-1, (%rbp)
jmp ..B2.122
..B2.120:
jne ..B2.202
..B2.121:
fstp %st(2)
movl $1, (%rbp)
..B2.122:
lea _ldbA(%rip), %rbx
lea (%rax,%rax,2), %ecx
movslq %ecx, %rcx
lea (%rax,%rax,4), %eax
shll $2, %eax
lea _dbA(%rip), %rbp
shlq $4, %rcx
addq $-16, %rsp
.cfi_def_cfa_offset 352
movslq %eax, %rax
lea 256(%rsp), %rdx
fxch %st(1)
fstpt (%rsp)
lea 4480(%rbx,%rcx), %rdi
fstpt 16(%rsp)
lea 2432(%rbp,%rax,8), %rsi
..___tag_value___libm_lgammal.241:
call __libm_p19root
..___tag_value___libm_lgammal.242:
..B2.288:
fldt 16(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 336
..B2.123:
testl %r12d, %r12d
je ..B2.125
..B2.124:
movl %r13d, %edi
fstpt (%rsp)
..___tag_value___libm_lgammal.244:
call fesetround@PLT
..___tag_value___libm_lgammal.245:
..B2.307:
fldt (%rsp)
..B2.125:
fldt 240(%rsp)
testb %r14b, %r14b
fldt 256(%rsp)
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.313
..B2.126:
fstpt 96(%rsp)
..B2.289:
fldcw 194(%rsp)
jmp ..B2.127
..B2.313:
fstp %st(0)
..B2.127:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.128:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.129:
fstp %st(0)
fstpt 96(%rsp)
fldt 96(%rsp)
fxch %st(1)
fxch %st(3)
fxch %st(1)
jmp ..B2.132
..B2.131:
fxch %st(1)
fstpt 96(%rsp)
fldt 96(%rsp)
..B2.132:
fldt .L_2il0floatpacket.13(%rip)
addq $-16, %rsp
.cfi_def_cfa_offset 352
fmulp %st, %st(4)
fstp %st(1)
fxch %st(2)
fstpt (%rsp)
fldt (%rsp)
fstpt 32(%rsp)
fxch %st(1)
fstpt 16(%rsp)
movss %xmm0, 48(%rsp)
fstpt 64(%rsp)
call nearbyintl@PLT
..B2.290:
fldt 64(%rsp)
fldt 16(%rsp)
fldt 32(%rsp)
fldt .L_2il0floatpacket.0(%rip)
movss 48(%rsp), %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 336
fxch %st(4)
fucomip %st(1), %st
fstp %st(0)
jp ..B2.133
je ..B2.206
..B2.133:
fcomip %st(2), %st
jbe ..B2.135
..B2.134:
movl $-1, (%rbp)
jmp ..B2.136
..B2.135:
movl $1, (%rbp)
..B2.136:
movss %xmm0, (%rsp)
fxch %st(1)
flds (%rsp)
fmulp %st, %st(2)
fxch %st(1)
fstpt 80(%rsp)
fldt 80(%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 368
lea 272(%rsp), %rdi
fstpt (%rsp)
fstpt 16(%rsp)
..___tag_value___libm_lgammal.269:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.270:
..B2.291:
fstp %st(0)
fldt .L_2il0floatpacket.0(%rip)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.137:
fldt 240(%rsp)
lea _TWO_32H(%rip), %rax
fldt 256(%rsp)
fstp %st(2)
lea 560+_ldbA(%rip), %rdx
fldt 80(%rsp)
fld %st(0)
fld %st(1)
fldl (%rax)
lea 80+_dbA(%rip), %rax
fstpt 16(%rsp)
fldt 16(%rsp)
fmul %st, %st(2)
fxch %st(1)
fadd %st(2), %st
fsubp %st, %st(2)
fxch %st(1)
fstpt 160(%rsp)
fldt 160(%rsp)
fld %st(2)
fsub %st(1), %st
fldt .L_2il0floatpacket.13(%rip)
fld %st(0)
fmul %st(6), %st
fxch %st(1)
fmul %st(7), %st
fstpt 48(%rsp)
fldt .L_2il0floatpacket.1(%rip)
fsubrp %st, %st(6)
fxch %st(3)
fmul %st(5), %st
fstpt 128(%rsp)
fldt 128(%rsp)
fld %st(5)
fadd %st(1), %st
fstpt 144(%rsp)
fldt 144(%rsp)
fsubp %st, %st(1)
fsubr %st, %st(5)
fxch %st(6)
faddp %st, %st(5)
fxch %st(3)
fmul %st, %st(4)
fld %st(5)
fmul %st(2), %st
fxch %st(4)
fmul %st, %st(6)
fxch %st(5)
faddp %st, %st(6)
fld %st(3)
fadd %st(3), %st
fstpt (%rsp)
fldt (%rsp)
fsubrp %st, %st(4)
fxch %st(2)
faddp %st, %st(3)
fxch %st(4)
faddp %st, %st(2)
fldt 48(%rsp)
faddp %st, %st(2)
fxch %st(1)
fstpt 32(%rsp)
fldt .L_2il0floatpacket.7(%rip)
fcomip %st(1), %st
fstp %st(0)
fldt .L_2il0floatpacket.0(%rip)
jbe ..B2.139
..B2.138:
lea 704+_ldbA(%rip), %rdx
lea 96+_dbA(%rip), %rax
..B2.139:
fldt .L_2il0floatpacket.1(%rip)
fld %st(3)
fstp %st(2)
movb 105(%rsp), %cl
lea ones(%rip), %rbx
andb $-128, %cl
fxch %st(1)
fadd %st(2), %st
shrb $7, %cl
fdivr %st(1), %st
fld %st(3)
fldt 16(%rsp)
fld %st(0)
fmul %st(3), %st
fld %st(0)
movzbl %cl, %ebp
fadd %st(4), %st
fsubp %st, %st(1)
fmul %st, %st(6)
fxch %st(4)
fsubrp %st, %st(6)
fxch %st(2)
fsub %st(3), %st
fld %st(0)
fadd %st(4), %st
fmul %st, %st(5)
fxch %st(1)
fmul %st, %st(2)
fxch %st(5)
faddp %st, %st(2)
fxch %st(1)
faddp %st, %st(5)
fmulp %st, %st(4)
fxch %st(3)
fsubrp %st, %st(2)
fld %st(0)
fadd %st(2), %st
fmul %st(0), %st
fldt 128(%rdx)
fmul %st(1), %st
fldt 112(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 96(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 80(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 64(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 48(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 32(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 16(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rdx)
lea 120+_dbA(%rip), %rdx
faddp %st, %st(1)
fmulp %st, %st(1)
fldl (%rax)
fld %st(0)
fadd %st(2), %st
fmul %st, %st(5)
fld %st(0)
fadd %st(6), %st
fsubp %st, %st(6)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(2)
fmul %st(5), %st
fstpt 240(%rsp)
fldt 240(%rsp)
fxch %st(2)
fsub %st(5), %st
fxch %st(4)
fmul %st, %st(5)
fxch %st(1)
faddl 8(%rax)
lea 112+_dbA(%rip), %rax
faddp %st, %st(4)
fxch %st(2)
fmul %st(3), %st
faddp %st, %st(4)
fxch %st(2)
fmulp %st, %st(1)
faddp %st, %st(2)
fxch %st(1)
fstpt 256(%rsp)
fldt 256(%rsp)
fldl (%rax)
fld %st(0)
fadd %st(3), %st
fstpt 64(%rsp)
fldt 64(%rsp)
fsubrp %st, %st(1)
faddp %st, %st(2)
fldt 96(%rsp)
fmuls (%rbx,%rbp,4)
fxch %st(2)
faddl (%rdx)
faddp %st, %st(1)
fstpt 48(%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 368
lea 240(%rsp), %rdi
fstpt (%rsp)
fldt (%rsp)
fldt .L_2il0floatpacket.0(%rip)
fstpt 16(%rsp)
fstpt -128(%rdi)
..___tag_value___libm_lgammal.273:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.274:
..B2.292:
fstp %st(0)
fldt 112(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.140:
fldt 16(%rsp)
lea 544+_ldbA(%rip), %rcx
fld %st(1)
lea 528+_ldbA(%rip), %rbx
lea 512+_ldbA(%rip), %rbp
lea 496+_ldbA(%rip), %rsi
fmul %st(1), %st
fld %st(2)
lea 480+_ldbA(%rip), %r8
lea 464+_ldbA(%rip), %r9
lea 448+_ldbA(%rip), %r10
lea 432+_ldbA(%rip), %r11
lea 416+_ldbA(%rip), %r15
lea 304+_ldbA(%rip), %rax
lea 48+_dbA(%rip), %rdx
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(2)
fsub %st(1), %st
fxch %st(3)
fmul %st(0), %st
fldt (%rcx)
lea 400+_ldbA(%rip), %rcx
fmul %st(1), %st
fldt (%rbx)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rbp)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rsi)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r8)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r9)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r10)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r11)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%r15)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 384+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 368+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 352+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 336+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rcx)
lea 320+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(1), %st
fld %st(3)
fldt (%rcx)
faddp %st, %st(2)
fxch %st(2)
fmulp %st, %st(1)
fld %st(2)
fmul %st(3), %st
fmul %st, %st(2)
fldt (%rax)
lea 64+_dbA(%rip), %rax
faddp %st, %st(2)
fldt .L_2il0floatpacket.2(%rip)
fmulp %st, %st(4)
fxch %st(3)
fmul %st(5), %st
fld %st(4)
fmul %st(2), %st
fxch %st(6)
fmul %st(0), %st
faddp %st, %st(1)
fld %st(3)
fadd %st(3), %st
fsubp %st, %st(3)
fld %st(2)
fld %st(2)
fadd %st(7), %st
fsubp %st, %st(7)
fmul %st(6), %st
fxch %st(3)
fsubr %st, %st(4)
fxch %st(4)
faddp %st, %st(1)
fld %st(3)
fxch %st(2)
fsub %st(6), %st
fmul %st, %st(2)
fxch %st(1)
fmul %st, %st(6)
fxch %st(6)
faddp %st, %st(2)
fmul %st(5), %st
faddp %st, %st(1)
fldl (%rax)
fld %st(0)
lea 72+_dbA(%rip), %rax
fadd %st(3), %st
fld %st(0)
fxch %st(1)
fsubr %st, %st(2)
fxch %st(4)
faddp %st, %st(2)
fld %st(5)
fmul %st(4), %st
fadd %st, %st(1)
fsubrp %st, %st(1)
fsubr %st, %st(3)
fld %st(4)
fxch %st(2)
faddl (%rax)
lea 56+_dbA(%rip), %rax
faddp %st, %st(3)
fxch %st(2)
faddp %st, %st(3)
fmul %st(2), %st
fld %st(3)
fmul %st(2), %st
fxch %st(2)
fmul %st(6), %st
faddp %st, %st(1)
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(2)
fldl (%rdx)
fld %st(0)
lea ones(%rip), %rdx
fadd %st(2), %st
fmul %st, %st(5)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(1)
fadd %st(5), %st
fsubp %st, %st(5)
fxch %st(1)
fsub %st(4), %st
fld %st(3)
fmul %st(5), %st
fxch %st(5)
fmul %st(6), %st
fxch %st(2)
faddl (%rax)
faddp %st, %st(3)
faddp %st, %st(2)
fxch %st(1)
fmul %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fmulp %st, %st(3)
faddp %st, %st(2)
fldt 64(%rsp)
fld %st(0)
fadd %st(2), %st
fstpt 160(%rsp)
fldt 160(%rsp)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fldt 48(%rsp)
faddp %st, %st(1)
faddp %st, %st(2)
fxch %st(1)
fstpt 64(%rsp)
fldt 208(%rsp)
fld %st(0)
fchs
fldt (%rsp)
fld %st(0)
fadd %st(3), %st
fstpt 176(%rsp)
fldt 176(%rsp)
fld %st(1)
movb 185(%rsp), %al
fsub %st(1), %st
andb $-128, %al
fadd %st(4), %st
shrb $7, %al
fxch %st(1)
fsubr %st, %st(4)
fxch %st(2)
fadd %st, %st(4)
fcomip %st(3), %st
fxch %st(2)
fstp %st(0)
fldt 32(%rsp)
movzbl %al, %eax
fadd %st, %st(2)
fldt 224(%rsp)
fadd %st, %st(4)
fxch %st(1)
faddp %st, %st(4)
faddp %st, %st(2)
fxch %st(2)
fcmovnbe %st(1), %st
fstp %st(1)
fld %st(1)
fadd %st(3), %st
fstpt 80(%rsp)
fldt 80(%rsp)
fld %st(2)
fsub %st(1), %st
fadd %st(4), %st
fadd %st(2), %st
flds (%rdx,%rax,4)
fmul %st(4), %st
movb 169(%rsp), %al
andb $-128, %al
shrb $7, %al
fstpt 128(%rsp)
fldt 128(%rsp)
fldt 64(%rsp)
fadd %st, %st(2)
movzbl %al, %eax
flds (%rdx,%rax,4)
fmul %st(7), %st
fxch %st(2)
fcomip %st(2), %st
fxch %st(1)
fstpt 112(%rsp)
fxch %st(2)
fsubrp %st, %st(5)
fxch %st(3)
faddp %st, %st(4)
faddp %st, %st(3)
faddp %st, %st(2)
fcmovbe %st(1), %st
fstp %st(1)
fstpt 96(%rsp)
testl %r12d, %r12d
je ..B2.142
..B2.141:
movl %r13d, %edi
..___tag_value___libm_lgammal.276:
call fesetround@PLT
..___tag_value___libm_lgammal.277:
..B2.142:
fldt 80(%rsp)
testb %r14b, %r14b
fldt 96(%rsp)
faddp %st, %st(1)
fchs
fstpt 176(%rsp)
je ..B2.144
..B2.143:
fldt 112(%rsp)
fstpt 144(%rsp)
..B2.293:
fldcw 194(%rsp)
..B2.144:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.145:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.146:
addq $-32, %rsp
.cfi_def_cfa_offset 368
movl $1, (%rbp)
lea 272(%rsp), %rdi
fxch %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
..___tag_value___libm_lgammal.299:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.300:
..B2.294:
fstp %st(0)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.147:
fldt 336(%rsp)
lea _TWO_32H(%rip), %rax
fld %st(0)
fld %st(1)
fld %st(2)
lea 560+_ldbA(%rip), %rdx
fldt 240(%rsp)
fldl (%rax)
lea 80+_dbA(%rip), %rax
fmul %st, %st(4)
fxch %st(3)
fadd %st(4), %st
fsubp %st, %st(4)
fxch %st(3)
fstpt 32(%rsp)
fldt 32(%rsp)
fsubr %st, %st(1)
fxch %st(2)
fstpt 64(%rsp)
fldt 64(%rsp)
fldt .L_2il0floatpacket.6(%rip)
fmul %st(4), %st
fldt .L_2il0floatpacket.6(%rip)
fldt 256(%rsp)
fmul %st, %st(1)
fxch %st(1)
fstpt 80(%rsp)
fldt .L_2il0floatpacket.1(%rip)
fsubrp %st, %st(6)
fxch %st(2)
fmul %st(5), %st
fstpt 16(%rsp)
fldt 16(%rsp)
fld %st(5)
fadd %st(1), %st
fstpt (%rsp)
fldt (%rsp)
fsubp %st, %st(1)
fmul %st, %st(3)
fsubr %st, %st(5)
fxch %st(2)
faddp %st, %st(5)
fxch %st(4)
fmul %st(5), %st
faddp %st, %st(2)
fmulp %st, %st(2)
fld %st(1)
fadd %st(3), %st
fstpt 48(%rsp)
fldt 48(%rsp)
fsubrp %st, %st(2)
fxch %st(2)
faddp %st, %st(1)
faddp %st, %st(1)
fldt 80(%rsp)
faddp %st, %st(1)
fldt .L_2il0floatpacket.7(%rip)
fcomip %st(2), %st
jbe ..B2.149
..B2.148:
lea 704+_ldbA(%rip), %rdx
lea 96+_dbA(%rip), %rax
..B2.149:
fldt 48(%rsp)
testl %r12d, %r12d
fstpt 48(%rsp)
fstpt 80(%rsp)
fldt 32(%rsp)
fld %st(0)
fxch %st(1)
fsubr %st, %st(2)
fxch %st(1)
fadd %st(2), %st
fldt 64(%rsp)
fld %st(0)
fldt .L_2il0floatpacket.1(%rip)
fdiv %st, %st(3)
fxch %st(1)
fmul %st(3), %st
fld %st(0)
fadd %st(4), %st
fsubp %st, %st(1)
fsubr %st, %st(3)
fld %st(3)
fadd %st(1), %st
fmul %st, %st(6)
fld %st(5)
fmul %st(5), %st
faddp %st, %st(7)
fxch %st(1)
fmul %st, %st(5)
fxch %st(2)
fsubrp %st, %st(5)
fxch %st(5)
faddp %st, %st(4)
fxch %st(3)
fmulp %st, %st(4)
fxch %st(3)
fsubrp %st, %st(1)
fld %st(1)
fadd %st(1), %st
fmul %st(0), %st
fldt 128(%rdx)
fmul %st(1), %st
fldt 112(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 96(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 80(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 64(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 48(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 32(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt 16(%rdx)
faddp %st, %st(1)
fmul %st(1), %st
fldt (%rdx)
lea 120+_dbA(%rip), %rdx
faddp %st, %st(1)
fmulp %st, %st(1)
fldl (%rax)
fld %st(0)
fadd %st(2), %st
fmul %st, %st(5)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(1)
fadd %st(5), %st
fsubp %st, %st(5)
fxch %st(1)
fsub %st(4), %st
fld %st(3)
fmul %st(5), %st
fstpt 240(%rsp)
fldt 240(%rsp)
fxch %st(3)
fmul %st, %st(5)
fxch %st(2)
faddl 8(%rax)
lea 112+_dbA(%rip), %rax
faddp %st, %st(1)
fmul %st, %st(3)
fxch %st(4)
faddp %st, %st(3)
fmulp %st, %st(3)
fxch %st(2)
faddp %st, %st(1)
fstpt 256(%rsp)
fldt 256(%rsp)
fldl (%rax)
fld %st(0)
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fldt 48(%rsp)
fxch %st(1)
faddl (%rdx)
faddp %st, %st(2)
fld %st(0)
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fldt 80(%rsp)
faddp %st, %st(1)
faddp %st, %st(1)
fstpt 48(%rsp)
je ..B2.152
..B2.150:
movl %r13d, %edi
fstpt 176(%rsp)
..___tag_value___libm_lgammal.302:
call fesetround@PLT
..___tag_value___libm_lgammal.303:
..B2.151:
fldt 176(%rsp)
..B2.152:
fldt 48(%rsp)
testb %r14b, %r14b
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.154
..B2.153:
fldt 32(%rsp)
fstpt 160(%rsp)
fldt (%rsp)
fstpt 144(%rsp)
fldt 16(%rsp)
fstpt 128(%rsp)
..B2.295:
fldcw 194(%rsp)
..B2.154:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.155:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.156:
addq $-32, %rsp
.cfi_def_cfa_offset 368
movl $1, (%rbp)
lea 272(%rsp), %rdi
fxch %st(1)
fstpt (%rsp)
fstpt 16(%rsp)
..___tag_value___libm_lgammal.325:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.326:
..B2.296:
fstp %st(0)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.157:
fldt 336(%rsp)
lea 16+_TWO5600(%rip), %rax
fldt 240(%rsp)
lea _TWO_32H(%rip), %rdx
fldt .L_2il0floatpacket.1(%rip)
testl %r12d, %r12d
fsubrp %st, %st(1)
fstpt 240(%rsp)
fldt 240(%rsp)
fldt (%rax)
fmulp %st, %st(2)
fld %st(1)
fxch %st(2)
fstpt 336(%rsp)
fldt 336(%rsp)
fldl (%rdx)
fld %st(0)
fmul %st(2), %st
fadd %st, %st(4)
fsubrp %st, %st(4)
fld %st(3)
fsubr %st(2), %st
fxch %st(1)
fmul %st(3), %st
fstpt 32(%rsp)
fldt 32(%rsp)
fld %st(3)
fadd %st(1), %st
fld %st(0)
fsubp %st, %st(2)
fld %st(1)
fmul %st(6), %st
fstpt 64(%rsp)
fxch %st(1)
fsubr %st, %st(4)
fmulp %st, %st(2)
fxch %st(4)
fstpt 48(%rsp)
fldt 256(%rsp)
faddp %st, %st(3)
fxch %st(1)
fmulp %st, %st(2)
faddp %st, %st(1)
je ..B2.159
..B2.158:
movl %r13d, %edi
fstpt (%rsp)
fstpt 16(%rsp)
..___tag_value___libm_lgammal.328:
call fesetround@PLT
..___tag_value___libm_lgammal.329:
..B2.304:
fldt 16(%rsp)
fldt (%rsp)
..B2.159:
fldt 64(%rsp)
lea _TWO5600(%rip), %rax
testb %r14b, %r14b
faddp %st, %st(1)
fldt (%rax)
fmulp %st, %st(1)
fstpt 176(%rsp)
je ..B2.314
..B2.160:
fldt 48(%rsp)
fstpt 160(%rsp)
fstpt 144(%rsp)
fldt 32(%rsp)
fstpt 128(%rsp)
..B2.297:
fldcw 194(%rsp)
jmp ..B2.161
..B2.314:
fstp %st(0)
..B2.161:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.162:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.163:
fldt .L_2il0floatpacket.3(%rip)
fcomip %st(2), %st
jbe ..B2.165
..B2.164:
movl $-1, (%rbp)
jmp ..B2.166
..B2.165:
movl $1, (%rbp)
..B2.166:
movss %xmm0, (%rsp)
flds (%rsp)
addq $-32, %rsp
.cfi_def_cfa_offset 368
fmulp %st, %st(2)
lea 272(%rsp), %rdi
fxch %st(1)
fstpt (%rsp)
fldt (%rsp)
fxch %st(1)
fstpt 16(%rsp)
fstpt 80(%rsp)
..___tag_value___libm_lgammal.351:
call __libm_logl_k80@PLT
..___tag_value___libm_lgammal.352:
..B2.298:
fstp %st(0)
fldt 80(%rsp)
addq $32, %rsp
.cfi_def_cfa_offset 336
..B2.167:
cmpl $16313, %ebx
jge ..B2.174
..B2.168:
fldt 240(%rsp)
testl %r12d, %r12d
fldt 256(%rsp)
faddp %st, %st(1)
fchs
fstpt 176(%rsp)
je ..B2.170
..B2.169:
movl %r13d, %edi
fstpt 48(%rsp)
..___tag_value___libm_lgammal.354:
call fesetround@PLT
..___tag_value___libm_lgammal.355:
..B2.310:
fldt 48(%rsp)
..B2.170:
testb %r14b, %r14b
je ..B2.315
..B2.171:
fstpt 80(%rsp)
..B2.299:
fldcw 194(%rsp)
jmp ..B2.172
..B2.315:
fstp %st(0)
..B2.172:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.173:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.174:
lea 288+_ldbA(%rip), %rax
lea 272+_ldbA(%rip), %rdx
lea 256+_ldbA(%rip), %rcx
lea 240+_ldbA(%rip), %rbx
lea 224+_ldbA(%rip), %rbp
lea 208+_ldbA(%rip), %rsi
lea 192+_ldbA(%rip), %r8
lea 176+_ldbA(%rip), %r9
fldt (%rax)
lea 160+_ldbA(%rip), %r10
fmul %st(1), %st
lea 144+_ldbA(%rip), %r11
lea 128+_ldbA(%rip), %rax
testl %r15d, %r15d
fxch %st(1)
fstpt 80(%rsp)
fldt 80(%rsp)
fldt (%rdx)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rcx)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rbx)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rbp)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rsi)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%r8)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%r9)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%r10)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%r11)
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rax)
lea 112+_ldbA(%rip), %rax
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rax)
lea 96+_ldbA(%rip), %rax
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rax)
lea 80+_ldbA(%rip), %rax
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rax)
lea 64+_ldbA(%rip), %rax
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rax)
lea 48+_ldbA(%rip), %rax
faddp %st, %st(2)
fmul %st, %st(1)
fldt (%rax)
lea 32+_ldbA(%rip), %rax
faddp %st, %st(2)
fmul %st, %st(1)
fld %st(0)
fldt (%rax)
lea 16+_ldbA(%rip), %rax
faddp %st, %st(3)
fxch %st(1)
fmul %st, %st(2)
fldt (%rax)
lea _ldbA(%rip), %rax
faddp %st, %st(3)
fmul %st, %st(2)
fld %st(0)
fldt (%rax)
lea _TWO_32H(%rip), %rax
faddp %st, %st(4)
fld %st(3)
fldl (%rax)
lea 32+_dbA(%rip), %rax
fld %st(0)
fmul %st(6), %st
fadd %st, %st(2)
fsubrp %st, %st(2)
fmul %st, %st(2)
fxch %st(2)
fadd %st, %st(4)
fsubrp %st, %st(4)
fld %st(2)
fsub %st(4), %st
fld %st(5)
fsub %st(2), %st
fmul %st(5), %st
fxch %st(1)
fmul %st, %st(6)
fxch %st(6)
faddp %st, %st(1)
fxch %st(1)
fmul %st(4), %st
fldl (%rax)
lea 40+_dbA(%rip), %rax
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(3)
fmul %st(2), %st
fxch %st(1)
faddl (%rax)
lea 16+_dbA(%rip), %rax
faddp %st, %st(3)
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(0)
fmul %st(5), %st
fld %st(2)
fmul %st(6), %st
fxch %st(3)
fmul %st(7), %st
faddp %st, %st(1)
fxch %st(1)
fmul %st(6), %st
faddp %st, %st(1)
fldl (%rax)
fld %st(0)
lea 24+_dbA(%rip), %rax
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(3)
fmul %st(3), %st
fxch %st(1)
faddl (%rax)
lea _dbA(%rip), %rax
faddp %st, %st(2)
fld %st(2)
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(0)
fmul %st(6), %st
fxch %st(1)
fsubr %st, %st(3)
fxch %st(2)
faddp %st, %st(3)
fld %st(2)
fmul %st(6), %st
fxch %st(2)
fmul %st(7), %st
faddp %st, %st(2)
fxch %st(2)
fmul %st(6), %st
faddp %st, %st(1)
fldl (%rax)
fld %st(0)
lea 8+_dbA(%rip), %rax
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fxch %st(1)
faddl (%rax)
faddp %st, %st(2)
fld %st(3)
fmul %st(3), %st
fstpt 64(%rsp)
fldt 64(%rsp)
fadd %st, %st(1)
fxch %st(1)
fstpt 48(%rsp)
fldt 48(%rsp)
fsubp %st, %st(1)
fld %st(0)
fmul %st(6), %st
fxch %st(1)
fsubr %st, %st(3)
fxch %st(2)
faddp %st, %st(3)
fld %st(2)
fmul %st(6), %st
fxch %st(2)
fmul %st(7), %st
faddp %st, %st(2)
fxch %st(2)
fmulp %st, %st(6)
faddp %st, %st(5)
fldt 240(%rsp)
jl ..B2.220
..B2.175:
fstp %st(2)
fstp %st(2)
fldt 256(%rsp)
fld %st(2)
testl %r12d, %r12d
fsub %st(2), %st
fadd %st, %st(2)
fxch %st(2)
fchs
faddp %st, %st(3)
fsubrp %st, %st(2)
fxch %st(3)
faddp %st, %st(1)
fxch %st(1)
fxch %st(2)
je ..B2.178
..B2.176:
movl %r13d, %edi
fstpt 176(%rsp)
fstpt 16(%rsp)
fstpt 32(%rsp)
..___tag_value___libm_lgammal.376:
call fesetround@PLT
..___tag_value___libm_lgammal.377:
..B2.177:
fldt 32(%rsp)
fldt 16(%rsp)
fldt 176(%rsp)
..B2.178:
testb %r14b, %r14b
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.316
..B2.179:
fldt 48(%rsp)
fstpt 144(%rsp)
fstpt 160(%rsp)
fldt 64(%rsp)
fstpt 128(%rsp)
..B2.300:
fldcw 194(%rsp)
jmp ..B2.180
..B2.316:
fstp %st(0)
..B2.180:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
..B2.181:
addq $280, %rsp
.cfi_def_cfa_offset 56
.cfi_restore 6
popq %rbp
.cfi_def_cfa_offset 48
.cfi_restore 3
popq %rbx
.cfi_def_cfa_offset 40
.cfi_restore 15
popq %r15
.cfi_def_cfa_offset 32
.cfi_restore 14
popq %r14
.cfi_def_cfa_offset 24
.cfi_restore 13
popq %r13
.cfi_def_cfa_offset 16
.cfi_restore 12
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 336
.cfi_offset 3, -48
.cfi_offset 6, -56
.cfi_offset 12, -16
.cfi_offset 13, -24
.cfi_offset 14, -32
.cfi_offset 15, -40
..B2.182:
fstp %st(0)
call __stack_chk_fail@PLT
..B2.188:
fcomi %st(2), %st
ja ..B2.71
jmp ..B2.73
..B2.191:
fstp %st(0)
fstp %st(1)
fstp %st(0)
movl $1, (%rbp)
testl %r12d, %r12d
je ..B2.193
..B2.192:
movl %r13d, %edi
..___tag_value___libm_lgammal.398:
call fesetround@PLT
..___tag_value___libm_lgammal.399:
..B2.193:
movss .L_2il0floatpacket.22(%rip), %xmm1
testb %r14b, %r14b
pxor %xmm0, %xmm0
divss %xmm0, %xmm1
movss %xmm1, (%rsp)
flds (%rsp)
fstpt 176(%rsp)
je ..B2.195
..B2.194:
fldcw 194(%rsp)
..B2.195:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.200:
fstp %st(0)
fldt .L_2il0floatpacket.8(%rip)
lea 304+_dbA(%rip), %rsi
movl $-1, (%rbp)
lea 2672+_ldbA(%rip), %rdi
faddp %st, %st(1)
jmp ..B2.106
..B2.202:
fxch %st(2)
fcomip %st(1), %st
jae ..B2.204
jp ..B2.204
..B2.203:
movl $-1, (%rbp)
jmp ..B2.122
..B2.204:
movl $1, (%rbp)
jmp ..B2.122
..B2.206:
fcomip %st(2), %st
jae ..B2.135
jp ..B2.135
jmp ..B2.134
..B2.209:
fstp %st(3)
fstp %st(2)
fstp %st(0)
movl $1, (%rbp)
testl %r12d, %r12d
je ..B2.211
..B2.210:
movl %r13d, %edi
fstpt (%rsp)
..___tag_value___libm_lgammal.400:
call fesetround@PLT
..___tag_value___libm_lgammal.401:
..B2.306:
fldt (%rsp)
..B2.211:
movss .L_2il0floatpacket.22(%rip), %xmm1
testb %r14b, %r14b
pxor %xmm0, %xmm0
divss %xmm0, %xmm1
movss %xmm1, (%rsp)
flds (%rsp)
fstpt 176(%rsp)
je ..B2.317
..B2.212:
fstpt 96(%rsp)
..B2.301:
fldcw 194(%rsp)
jmp ..B2.213
..B2.317:
fstp %st(0)
..B2.213:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.220:
lea 544+_ldbA(%rip), %rcx
lea 528+_ldbA(%rip), %rbx
fxch %st(5)
fstpt (%rsp)
fld %st(2)
lea 512+_ldbA(%rip), %rbp
lea 496+_ldbA(%rip), %rsi
lea 480+_ldbA(%rip), %r8
lea 464+_ldbA(%rip), %r9
lea 448+_ldbA(%rip), %r10
lea 432+_ldbA(%rip), %r11
lea 416+_ldbA(%rip), %r15
lea 304+_ldbA(%rip), %rax
lea 48+_dbA(%rip), %rdx
testl %r12d, %r12d
fsub %st(4), %st
fxch %st(3)
fmul %st(0), %st
fxch %st(5)
fstpt 16(%rsp)
fxch %st(3)
fstpt 32(%rsp)
fldt 32(%rsp)
fldt (%rcx)
lea 400+_ldbA(%rip), %rcx
fmul %st(5), %st
fldt (%rbx)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rbp)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rsi)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%r8)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%r9)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%r10)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%r11)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%r15)
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rcx)
lea 384+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rcx)
lea 368+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rcx)
lea 352+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rcx)
lea 336+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rcx)
lea 320+_ldbA(%rip), %rcx
faddp %st, %st(1)
fmul %st(5), %st
fldt (%rcx)
faddp %st, %st(1)
fmulp %st, %st(5)
fldt (%rax)
lea 64+_dbA(%rip), %rax
faddp %st, %st(5)
fld %st(4)
fld %st(1)
fmul %st(2), %st
fldt .L_2il0floatpacket.2(%rip)
fmulp %st, %st(3)
fxch %st(2)
fmul %st(4), %st
fld %st(3)
fmul %st(3), %st
fxch %st(5)
fmul %st(0), %st
faddp %st, %st(1)
fld %st(2)
fadd %st(5), %st
fsubp %st, %st(5)
fld %st(4)
fxch %st(3)
fsub %st(5), %st
faddp %st, %st(1)
fld %st(3)
fmul %st(7), %st
fadd %st, %st(2)
fsubrp %st, %st(2)
fxch %st(1)
fmul %st, %st(2)
fsubr %st, %st(6)
fmul %st(1), %st
fld %st(4)
fmul %st(7), %st
faddp %st, %st(1)
fxch %st(1)
fmul %st, %st(6)
fxch %st(6)
faddp %st, %st(1)
fldl (%rax)
fld %st(0)
lea 72+_dbA(%rip), %rax
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fxch %st(1)
faddl (%rax)
lea 56+_dbA(%rip), %rax
faddp %st, %st(2)
fld %st(3)
fmul %st(3), %st
fadd %st, %st(1)
fsubrp %st, %st(1)
fsubr %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fld %st(3)
fmul %st(1), %st
fxch %st(1)
fmul %st(6), %st
fld %st(4)
fmul %st(3), %st
faddp %st, %st(1)
fxch %st(2)
fmul %st(6), %st
faddp %st, %st(2)
fldl (%rdx)
fld %st(0)
fadd %st(2), %st
fmul %st, %st(4)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
faddl (%rax)
faddp %st, %st(2)
fld %st(0)
fadd %st(3), %st
fsubp %st, %st(3)
fsub %st(2), %st
faddp %st, %st(1)
fld %st(2)
fmul %st(2), %st
fxch %st(2)
fmul %st(5), %st
fxch %st(1)
fmul %st, %st(3)
fxch %st(1)
faddp %st, %st(3)
fmulp %st, %st(4)
fxch %st(3)
faddp %st, %st(1)
fld %st(1)
fldt 16(%rsp)
fadd %st, %st(1)
fxch %st(1)
fchs
fadd %st, %st(1)
fxch %st(1)
fchs
fsubp %st, %st(3)
fldt 256(%rsp)
fsubrp %st, %st(3)
fldt (%rsp)
fsubrp %st, %st(3)
fld %st(0)
fsub %st(4), %st
fsub %st, %st(1)
fxch %st(1)
fchs
fsubp %st, %st(4)
fxch %st(2)
faddp %st, %st(3)
fsubrp %st, %st(2)
fldt 32(%rsp)
fxch %st(2)
je ..B2.222
..B2.221:
movl %r13d, %edi
fstpt (%rsp)
fstpt 16(%rsp)
fstpt 32(%rsp)
..___tag_value___libm_lgammal.402:
call fesetround@PLT
..___tag_value___libm_lgammal.403:
..B2.308:
fldt 32(%rsp)
fldt 16(%rsp)
fldt (%rsp)
..B2.222:
testb %r14b, %r14b
faddp %st, %st(1)
fstpt 176(%rsp)
je ..B2.318
..B2.223:
fldt 48(%rsp)
fstpt 144(%rsp)
fstpt 160(%rsp)
fldt 64(%rsp)
fstpt 128(%rsp)
..B2.302:
fldcw 194(%rsp)
jmp ..B2.224
..B2.318:
fstp %st(0)
..B2.224:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.227:
cmpl $16446, %ebx
jle ..B2.16
..B2.228:
fstp %st(0)
fstp %st(0)
movl $1, (%rbp)
testl %r12d, %r12d
je ..B2.230
..B2.229:
movl %r13d, %edi
..___tag_value___libm_lgammal.404:
call fesetround@PLT
..___tag_value___libm_lgammal.405:
..B2.230:
movss .L_2il0floatpacket.22(%rip), %xmm1
testb %r14b, %r14b
pxor %xmm0, %xmm0
divss %xmm0, %xmm1
movss %xmm1, (%rsp)
flds (%rsp)
fstpt 176(%rsp)
je ..B2.232
..B2.231:
fldcw 194(%rsp)
..B2.232:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.235:
fstp %st(1)
movl $1, (%rbp)
..B2.236:
testl %r12d, %r12d
je ..B2.238
..B2.237:
movl %r13d, %edi
fstp %st(0)
..___tag_value___libm_lgammal.406:
call fesetround@PLT
..___tag_value___libm_lgammal.407:
..B2.309:
fldt .L_2il0floatpacket.0(%rip)
..B2.238:
fstpt 176(%rsp)
testb %r14b, %r14b
je ..B2.240
..B2.239:
fldcw 194(%rsp)
..B2.240:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.244:
fstp %st(0)
movl $1, (%rbp)
testl %r12d, %r12d
je ..B2.247
..B2.245:
fstp %st(0)
movl %r13d, %edi
..___tag_value___libm_lgammal.408:
call fesetround@PLT
..___tag_value___libm_lgammal.409:
..B2.246:
fldt 336(%rsp)
..B2.247:
fld %st(0)
testb %r14b, %r14b
fmul %st(1), %st
fmulp %st, %st(1)
fstpt 176(%rsp)
je ..B2.249
..B2.248:
fldcw 194(%rsp)
..B2.249:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.252:
fstp %st(0)
fstp %st(0)
testl %r12d, %r12d
je ..B2.254
..B2.253:
movl %r13d, %edi
movl $1, (%rbp)
..___tag_value___libm_lgammal.410:
call fesetround@PLT
..___tag_value___libm_lgammal.411:
movzbl 345(%rsp), %ecx
..B2.254:
movss .L_2il0floatpacket.22(%rip), %xmm1
andl $128, %ecx
pxor %xmm0, %xmm0
divss %xmm0, %xmm1
shrl $7, %ecx
addl %ecx, %ecx
movss %xmm1, (%rsp)
negl %ecx
flds (%rsp)
incl %ecx
fstpt 176(%rsp)
testb %r14b, %r14b
movl %ecx, (%rbp)
je ..B2.256
..B2.255:
fldcw 194(%rsp)
..B2.256:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.259:
movq $0x8000000000000000, %rax
cmpq 336(%rsp), %rax
je ..B2.270
..B2.260:
movl $0, (%rbp)
testl %r12d, %r12d
je ..B2.262
..B2.261:
movl %r13d, %edi
..___tag_value___libm_lgammal.412:
call fesetround@PLT
..___tag_value___libm_lgammal.413:
..B2.262:
fldt 336(%rsp)
fadd %st(0), %st
fstpt 176(%rsp)
..B2.263:
testl %r12d, %r12d
je ..B2.265
..B2.264:
movl %r13d, %edi
..___tag_value___libm_lgammal.414:
call fesetround@PLT
..___tag_value___libm_lgammal.415:
..B2.265:
testb %r14b, %r14b
je ..B2.267
..B2.266:
fldcw 194(%rsp)
..B2.267:
fldt 176(%rsp)
movq 272(%rsp), %rax
xorq %rsp, %rax
cmpq %fs:40, %rax
jne ..B2.182
jmp ..B2.36
..B2.270:
movl $1, (%rbp)
testl %r12d, %r12d
je ..B2.272
..B2.271:
movl %r13d, %edi
..___tag_value___libm_lgammal.416:
call fesetround@PLT
..___tag_value___libm_lgammal.417:
..B2.272:
fldt 336(%rsp)
fmul %st(0), %st
fstpt 176(%rsp)
jmp ..B2.263
.align 16,0x90
.cfi_endproc
.type __libm_lgammal,@function
.size __libm_lgammal,.-__libm_lgammal
.data
# -- End __libm_lgammal
.text
# -- Begin __libm_p25
.text
.align 16,0x90
__libm_p25:
# parameter 1: 8 + %rsp
# parameter 2: %rdi
# parameter 3: %rsi
# parameter 4: %rdx
..B3.1:
.cfi_startproc
..___tag_value___libm_p25.419:
..L420:
lea _TWO_32H(%rip), %rax
fldt 8(%rsp)
fld %st(0)
fld %st(1)
fldl 56(%rsi)
fmul %st(3), %st
fldl (%rax)
fmul %st, %st(3)
fxch %st(2)
fadd %st(3), %st
fsubp %st, %st(3)
fld %st(3)
fsub %st(3), %st
fldt 64(%rdi)
fxch %st(2)
faddl 48(%rsi)
fmul %st(5), %st
fldt (%rdi)
fldt 80(%rdi)
fxch %st(2)
faddl 152(%rsi)
fmul %st(7), %st
faddl 144(%rsi)
fmul %st(7), %st
faddl 168(%rsi)
fmul %st(7), %st
faddl 160(%rsi)
fmul %st(7), %st
faddl 104(%rsi)
fmul %st(7), %st
faddl 96(%rsi)
fmul %st(7), %st
faddl 120(%rsi)
fmul %st(7), %st
faddl 112(%rsi)
fmul %st(7), %st
faddl 136(%rsi)
fmul %st(7), %st
faddl 128(%rsi)
fmul %st(7), %st
faddl 40(%rsi)
fmul %st(7), %st
faddl 32(%rsi)
fmul %st(7), %st
faddp %st, %st(4)
fxch %st(3)
fmul %st(6), %st
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(2)
fxch %st(1)
fmul %st(4), %st
fldt 16(%rdi)
faddp %st, %st(1)
fmul %st(4), %st
fldt 32(%rdi)
fldt 96(%rdi)
faddp %st, %st(2)
fxch %st(1)
fmul %st(5), %st
faddp %st, %st(1)
fmul %st(4), %st
fldt 112(%rdi)
faddp %st, %st(1)
fmul %st(4), %st
fld %st(2)
fldt 48(%rdi)
faddp %st, %st(2)
fmul %st(1), %st
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fld %st(0)
fmul %st(5), %st
fxch %st(1)
fsubr %st, %st(2)
fxch %st(2)
fmul %st(6), %st
fxch %st(2)
fmul %st(3), %st
faddp %st, %st(2)
fldl (%rsi)
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(4)
fmul %st(2), %st
fxch %st(1)
faddl 88(%rsi)
faddp %st, %st(3)
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fmul %st(5), %st
fld %st(4)
fmul %st(2), %st
fxch %st(2)
fmul %st(3), %st
faddp %st, %st(1)
fldl 64(%rsi)
fld %st(0)
fadd %st(3), %st
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(4)
fmul %st(3), %st
fxch %st(1)
faddl 72(%rsi)
faddp %st, %st(2)
fld %st(2)
fadd %st(1), %st
fsubp %st, %st(1)
fsubr %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
fmul %st(5), %st
fld %st(4)
fmul %st(2), %st
fxch %st(2)
fmul %st(3), %st
faddp %st, %st(1)
fldl 16(%rsi)
fld %st(0)
fadd %st(3), %st
fmul %st, %st(5)
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fadd %st(5), %st
fsubp %st, %st(5)
fxch %st(4)
fmul %st, %st(5)
fsubr %st, %st(2)
fmulp %st, %st(3)
fxch %st(3)
faddl 24(%rsi)
faddp %st, %st(3)
faddp %st, %st(2)
fxch %st(1)
fmulp %st, %st(3)
faddp %st, %st(2)
fldl 80(%rsi)
fld %st(0)
fadd %st(2), %st
fstpt (%rdx)
fldt (%rdx)
fsubrp %st, %st(1)
faddp %st, %st(1)
faddl 8(%rsi)
faddp %st, %st(1)
fstpt 16(%rdx)
ret
.align 16,0x90
.cfi_endproc
.type __libm_p25,@function
.size __libm_p25,.-__libm_p25
.data
# -- End __libm_p25
.text
# -- Begin __libm_p19root
.text
.align 16,0x90
__libm_p19root:
# parameter 1: 8 + %rsp
# parameter 2: %rdi
# parameter 3: %rsi
# parameter 4: %rdx
..B4.1:
.cfi_startproc
..___tag_value___libm_p19root.422:
..L423:
lea _TWO_32H(%rip), %rax
fldt 8(%rsp)
lea ones(%rip), %r10
fld %st(0)
fld %st(1)
fldl 152(%rsi)
fmul %st(3), %st
fldl (%rax)
fmul %st, %st(3)
fxch %st(2)
fadd %st(3), %st
fsubp %st, %st(3)
fld %st(3)
fsub %st(3), %st
fldt 32(%rdi)
fxch %st(2)
faddl 144(%rsi)
fmul %st(5), %st
fldt 16(%rdi)
fldt (%rdi)
fxch %st(2)
faddl 136(%rsi)
fmul %st(7), %st
faddl 128(%rsi)
fmul %st(7), %st
faddl 120(%rsi)
fmul %st(7), %st
faddl 112(%rsi)
fmul %st(7), %st
faddl 104(%rsi)
fmul %st(7), %st
faddl 96(%rsi)
fmul %st(7), %st
faddl 88(%rsi)
fmul %st(7), %st
faddl 80(%rsi)
fmul %st(7), %st
faddl 72(%rsi)
fmul %st(7), %st
faddl 64(%rsi)
fmul %st(7), %st
faddl 56(%rsi)
fmul %st(7), %st
faddl 48(%rsi)
fmul %st(7), %st
faddp %st, %st(4)
fxch %st(3)
fmul %st(6), %st
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
faddp %st, %st(2)
fld %st(1)
fld %st(3)
fmul %st(3), %st
fadd %st, %st(1)
fsubrp %st, %st(1)
fld %st(0)
fmul %st(5), %st
fxch %st(1)
fsubr %st, %st(3)
fxch %st(3)
fmul %st(6), %st
fxch %st(2)
fmul %st, %st(3)
fxch %st(2)
faddp %st, %st(3)
fldl 32(%rsi)
fld %st(0)
fadd %st(2), %st
fsubr %st, %st(1)
fxch %st(2)
faddp %st, %st(1)
fld %st(4)
fmul %st(2), %st
fxch %st(1)
faddl 40(%rsi)
faddp %st, %st(4)
fld %st(1)
fadd %st(1), %st
fsubp %st, %st(1)
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fmul %st(5), %st
fld %st(4)
fmul %st(3), %st
fxch %st(2)
fmul %st, %st(3)
fxch %st(1)
faddp %st, %st(3)
fldl 16(%rsi)
fld %st(0)
fadd %st(3), %st
fmul %st, %st(5)
fsubr %st, %st(1)
fxch %st(3)
faddp %st, %st(1)
fld %st(2)
fadd %st(5), %st
fsubp %st, %st(5)
fxch %st(1)
fmul %st(4), %st
fxch %st(2)
fsub %st(4), %st
fxch %st(4)
fmulp %st, %st(5)
faddl 24(%rsi)
faddp %st, %st(2)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
fmulp %st, %st(3)
faddp %st, %st(2)
fld %st(1)
fadd %st(1), %st
fstpt -40(%rsp)
fldt -40(%rsp)
fldl (%rsi)
fld %st(0)
fldl 8(%rsi)
movb -31(%rsp), %cl
fadd %st, %st(1)
fxch %st(1)
fstpt -24(%rsp)
fldt -24(%rsp)
andb $-128, %cl
movb -15(%rsp), %r9b
andb $-128, %r9b
shrb $7, %r9b
shrb $7, %cl
movzbl %r9b, %r11d
movzbl %cl, %r8d
flds (%r10,%r11,4)
fmulp %st, %st(1)
fld %st(2)
fadd %st(5), %st
fstpt (%rdx)
fldt (%rdx)
flds (%r10,%r8,4)
fmulp %st, %st(5)
fxch %st(4)
fcomi %st(1), %st
fxch %st(1)
fstp %st(0)
fld %st(3)
fsubr %st(5), %st
fadd %st(3), %st
fadd %st(6), %st
fadd %st(2), %st
fxch %st(1)
fstpt -40(%rsp)
fxch %st(3)
fsubrp %st, %st(2)
fxch %st(3)
faddp %st, %st(1)
faddp %st, %st(2)
fxch %st(2)
faddp %st, %st(1)
fcmovnbe %st(1), %st
fstp %st(1)
fstpt 16(%rdx)
ret
.align 16,0x90
.cfi_endproc
.type __libm_p19root,@function
.size __libm_p19root,.-__libm_p19root
.data
# -- End __libm_p19root
.text
# -- Begin gammal
.text
.align 16,0x90
.globl gammal
gammal:
# parameter 1: 16 + %rsp
..B5.1:
.cfi_startproc
..___tag_value_gammal.425:
..L426:
pushq %rsi
.cfi_def_cfa_offset 16
fldt 16(%rsp)
addq $-16, %rsp
.cfi_def_cfa_offset 32
lea 16(%rsp), %rdi
fstpt (%rsp)
..___tag_value_gammal.429:
call __libm_lgammal
..___tag_value_gammal.430:
..B5.2:
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type gammal,@function
.size gammal,.-gammal
.data
# -- End gammal
.text
# -- Begin lgammal_r
.text
.align 16,0x90
.globl lgammal_r
lgammal_r:
# parameter 1: 8 + %rsp
# parameter 2: %rdi
..B6.1:
.cfi_startproc
..___tag_value_lgammal_r.433:
..L434:
fldt 8(%rsp)
fstpt 8(%rsp)
jmp __libm_lgammal
.align 16,0x90
.cfi_endproc
.type lgammal_r,@function
.size lgammal_r,.-lgammal_r
.data
# -- End lgammal_r
.text
# -- Begin gammal_r
.text
.align 16,0x90
.globl gammal_r
gammal_r:
# parameter 1: 8 + %rsp
# parameter 2: %rdi
..B7.1:
.cfi_startproc
..___tag_value_gammal_r.436:
..L437:
fldt 8(%rsp)
fstpt 8(%rsp)
jmp __libm_lgammal
.align 16,0x90
.cfi_endproc
.type gammal_r,@function
.size gammal_r,.-gammal_r
.data
# -- End gammal_r
.section .rodata, "a"
.align 16
.align 16
.L_2il0floatpacket.0:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.0,@object
.size .L_2il0floatpacket.0,16
.align 16
.L_2il0floatpacket.1:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.1,@object
.size .L_2il0floatpacket.1,16
.align 16
.L_2il0floatpacket.2:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.2,@object
.size .L_2il0floatpacket.2,16
.align 16
.L_2il0floatpacket.3:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.3,@object
.size .L_2il0floatpacket.3,16
.align 16
.L_2il0floatpacket.4:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x01,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.4,@object
.size .L_2il0floatpacket.4,16
.align 16
.L_2il0floatpacket.5:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x01,0xc0,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.5,@object
.size .L_2il0floatpacket.5,16
.align 16
.L_2il0floatpacket.6:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xfe,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.6,@object
.size .L_2il0floatpacket.6,16
.align 16
.L_2il0floatpacket.7:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xd0,0x02,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.7,@object
.size .L_2il0floatpacket.7,16
.align 16
.L_2il0floatpacket.8:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0xfe,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.8,@object
.size .L_2il0floatpacket.8,16
.align 16
.L_2il0floatpacket.9:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9c,0x03,0xc0,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.9,@object
.size .L_2il0floatpacket.9,16
.align 16
.L_2il0floatpacket.10:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xb0,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.10,@object
.size .L_2il0floatpacket.10,16
.align 16
.L_2il0floatpacket.11:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc8,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.11,@object
.size .L_2il0floatpacket.11,16
.align 16
.L_2il0floatpacket.12:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.12,@object
.size .L_2il0floatpacket.12,16
.align 16
.L_2il0floatpacket.13:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xfe,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.13,@object
.size .L_2il0floatpacket.13,16
.align 16
.L_2il0floatpacket.14:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xa6,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.14,@object
.size .L_2il0floatpacket.14,16
.align 16
.L_2il0floatpacket.15:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.15,@object
.size .L_2il0floatpacket.15,16
.align 16
.L_2il0floatpacket.16:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.16,@object
.size .L_2il0floatpacket.16,16
.align 16
.L_2il0floatpacket.17:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x81,0xff,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.17,@object
.size .L_2il0floatpacket.17,16
.align 16
.L_2il0floatpacket.18:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xfe,0xfe,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.18,@object
.size .L_2il0floatpacket.18,16
.align 16
.L_2il0floatpacket.19:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.19,@object
.size .L_2il0floatpacket.19,16
.align 16
.L_2il0floatpacket.20:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.20,@object
.size .L_2il0floatpacket.20,16
.align 16
.L_2il0floatpacket.21:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.21,@object
.size .L_2il0floatpacket.21,16
.align 16
_ldbA:
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ones:
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_TWO_32H:
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.word 0
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.section .note.GNU-stack, ""
// -- Begin DWARF2 SEGMENT .eh_frame
.section .eh_frame,"a",@progbits
.eh_frame_seg:
.align 1
# End
|
GeminiCarrie/rust-sgx-sdk | 16,834 | sgx_libc/sgx_tlibc_sys/tlibc/math/expl_table.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "expl_table.c"
.section .rodata, "a"
.align 8
.align 8
.globl __libm_expl_table_256
__libm_expl_table_256:
.long 0x66800000,0x3fe6a09e
.long 0xee9a09d9,0xbd98866d
.long 0xfa800000,0x3fe6b052
.long 0xcb8e15a7,0xbdd5d183
.long 0x75000000,0x3fe6c012
.long 0xdaed5330,0x3dd7b57d
.long 0xde000000,0x3fe6cfdc
.long 0x470aac92,0xbdf5c4dd
.long 0x3c400000,0x3fe6dfb2
.long 0x79107166,0x3df28d17
.long 0x98400000,0x3fe6ef92
.long 0xbd1a2d88,0x3de93ae4
.long 0xf9400000,0x3fe6ff7d
.long 0xcf87e1b5,0x3de19483
.long 0x67000000,0x3fe70f74
.long 0xf314dd96,0xbdd7a2f1
.long 0xe9000000,0x3fe71f75
.long 0x22dc8f0d,0xbde3a08c
.long 0x87000000,0x3fe72f82
.long 0x482a80b3,0xbde52f76
.long 0x48c00000,0x3fe73f9a
.long 0x42a365b2,0xbdea7e8c
.long 0x35c00000,0x3fe74fbd
.long 0x411ff586,0x3de7cbfd
.long 0x56400000,0x3fe75feb
.long 0xfb74d51a,0x3db33e45
.long 0xb1c00000,0x3fe77024
.long 0x921e23a6,0xbde491f6
.long 0x4fc00000,0x3fe78069
.long 0x619ae028,0x3dee5d3f
.long 0x38c00000,0x3fe790b9
.long 0xb2d95e75,0xbde3e309
.long 0x74000000,0x3fe7a114
.long 0x282aefdc,0xbde4fe79
.long 0x09800000,0x3fe7b17b
.long 0xdf5dac23,0xbdd2604a
.long 0x01000000,0x3fe7c1ed
.long 0x3e2499a2,0x3df86099
.long 0x63000000,0x3fe7d26a
.long 0x4224048d,0xbd8e43ee
.long 0x36c00000,0x3fe7e2f3
.long 0x20ba0574,0x3dde9cc4
.long 0x84800000,0x3fe7f387
.long 0xdf01dc61,0x3de1c490
.long 0x54400000,0x3fe80427
.long 0x9f21989b,0xbdae5ee4
.long 0xae000000,0x3fe814d2
.long 0x573791e6,0xbdf77c93
.long 0x99400000,0x3fe82589
.long 0x159f115f,0x3dd99c25
.long 0x1e800000,0x3fe8364c
.long 0xb3373464,0x3dfca0fb
.long 0x46400000,0x3fe8471a
.long 0x31ad0947,0xbdec3853
.long 0x17800000,0x3fe857f4
.long 0xf9162dc2,0x3def5b20
.long 0x9b400000,0x3fe868d9
.long 0x03907643,0x3dc24bb2
.long 0xd9400000,0x3fe879ca
.long 0xa8b4a0b5,0xbddcb793
.long 0xd9800000,0x3fe88ac7
.long 0xcca6179c,0x3dd4cd32
.long 0xa4800000,0x3fe89bd0
.long 0x2ac6abb9,0xbdce9fc2
.long 0x42400000,0x3fe8ace5
.long 0xa4583aa6,0xbde55f24
.long 0xbac00000,0x3fe8be05
.long 0x7b2d7bf1,0x3de61778
.long 0x16c00000,0x3fe8cf32
.long 0x21aabc66,0xbdd576e8
.long 0x5e400000,0x3fe8e06a
.long 0xae2294e0,0xbdfbcc93
.long 0x99000000,0x3fe8f1ae
.long 0x2b982746,0x3de57736
.long 0xd0000000,0x3fe902fe
.long 0x2b25950c,0x3df41645
.long 0x0b800000,0x3fe9145b
.long 0x88a61b47,0x3de1ffc5
.long 0x53800000,0x3fe925c3
.long 0xecbaa05a,0x3df517f0
.long 0xb0c00000,0x3fe93737
.long 0xe8a0387e,0x3ddb8bc9
.long 0x2b400000,0x3fe948b8
.long 0xc478530d,0x3def98e4
.long 0xcbc00000,0x3fe95a44
.long 0xd36906d3,0x3dd0a41d
.long 0x9a400000,0x3fe96bdd
.long 0x7c8b4d30,0x3dfb3859
.long 0x9fc00000,0x3fe97d82
.long 0x8b9e9210,0x3dee4e4f
.long 0xe4800000,0x3fe98f33
.long 0x8d509577,0xbdc77577
.long 0x70c00000,0x3fe9a0f1
.long 0x74621372,0x3dd40f73
.long 0x4d400000,0x3fe9b2bb
.long 0x889ec6c8,0x3de3fe0c
.long 0x82800000,0x3fe9c491
.long 0x0e3e2358,0x3df1f848
.long 0x19400000,0x3fe9d674
.long 0x574a0ae1,0x3dd771a9
.long 0x19c00000,0x3fe9e863
.long 0x8c12653c,0x3df19191
.long 0x8d000000,0x3fe9fa5e
.long 0x5ab18aa8,0x3dcfca77
.long 0x7b400000,0x3fea0c66
.long 0xb29ada8c,0x3dede564
.long 0xed800000,0x3fea1e7a
.long 0xe330c774,0x3ddd7176
.long 0xec400000,0x3fea309b
.long 0xb182e3ef,0x3dd45a66
.long 0x80400000,0x3fea42c9
.long 0x5587fa76,0x3dc82b5e
.long 0xb2400000,0x3fea5503
.long 0x4bdbb6e3,0xbdadaa37
.long 0x8b000000,0x3fea674a
.long 0xeaf0a9d0,0xbdd73f5b
.long 0x13400000,0x3fea799e
.long 0x21a409aa,0xbdde994f
.long 0x53c00000,0x3fea8bfe
.long 0xc1e61351,0x3da2e58a
.long 0x55400000,0x3fea9e6b
.long 0xa1f5921e,0x3dfcfedf
.long 0x21400000,0x3feab0e5
.long 0x9d8f3894,0xbdd5228b
.long 0xbfc00000,0x3feac36b
.long 0xc0db966a,0x3de3f379
.long 0x3a400000,0x3fead5ff
.long 0x0218892a,0xbdbec45d
.long 0x99800000,0x3feae89f
.long 0x50bc6597,0xbdf29629
.long 0xe6400000,0x3feafb4c
.long 0x52cbf03d,0xbded0d01
.long 0x29800000,0x3feb0e07
.long 0x2108559c,0x3ddb6ccb
.long 0x6c800000,0x3feb20ce
.long 0x53740928,0x3dea8952
.long 0xb8800000,0x3feb33a2
.long 0x84a0178c,0xbdf87502
.long 0x15c00000,0x3feb4684
.long 0x3eec7bd4,0xbdd16c9e
.long 0x8e000000,0x3feb5972
.long 0x71c77eef,0xbdeaa6c6
.long 0x2a000000,0x3feb6c6e
.long 0x6ab8656c,0xbddc75ab
.long 0xf3000000,0x3feb7f76
.long 0x55613df9,0xbdc286e4
.long 0xf2400000,0x3feb928c
.long 0x6dc85953,0xbde8b61c
.long 0x30c00000,0x3feba5b0
.long 0x7bf34c39,0xbdeef9b6
.long 0xb7c00000,0x3febb8e0
.long 0x80fa968e,0xbdf2c870
.long 0x90400000,0x3febcc1e
.long 0x48f741e9,0x3dd783a4
.long 0xc4000000,0x3febdf69
.long 0x0384c46c,0xbdd8bbf2
.long 0x5c000000,0x3febf2c2
.long 0xbdfb947f,0xbdf470fb
.long 0x61400000,0x3fec0628
.long 0x4eb4abc1,0x3dab33cc
.long 0xdd800000,0x3fec199b
.long 0x88832c4b,0x3dc54a70
.long 0xd9c00000,0x3fec2d1c
.long 0xd235d3d0,0x3dfd3295
.long 0x60000000,0x3fec40ab
.long 0x75903ef8,0xbd77c2c9
.long 0x79000000,0x3fec5447
.long 0xed0f8db7,0xbdc41376
.long 0x2e400000,0x3fec67f1
.long 0x4a2137fd,0x3de7d14b
.long 0x89c00000,0x3fec7ba8
.long 0x9e76bbbe,0xbdfb9b66
.long 0x94000000,0x3fec8f6d
.long 0x46b2f122,0x3dcb9ed4
.long 0x57400000,0x3feca340
.long 0xd01a825e,0x3de1c4da
.long 0xdd000000,0x3fecb720
.long 0xeafc342e,0xbde06f96
.long 0x2e800000,0x3feccb0f
.long 0x1d220f86,0xbde2e98b
.long 0x55400000,0x3fecdf0b
.long 0xc44f8959,0x3dedc3f9
.long 0x5b800000,0x3fecf315
.long 0x3411d371,0xbdf22a46
.long 0x4a000000,0x3fed072d
.long 0x343c8bc8,0x3dce25ee
.long 0x2b000000,0x3fed1b53
.long 0xaab1b10d,0x3dd192d0
.long 0x08000000,0x3fed2f87
.long 0x15bc2473,0x3ddb13e3
.long 0xeac00000,0x3fed43c8
.long 0x9eda9dfb,0x3dd543ac
.long 0xdd000000,0x3fed5818
.long 0x6897e945,0xbdc16de3
.long 0xe8400000,0x3fed6c76
.long 0x83fd0f49,0x3df17369
.long 0x16c00000,0x3fed80e3
.long 0x7709f3a1,0x3dd3072f
.long 0x72000000,0x3fed955d
.long 0xfd692233,0xbd93f152
.long 0x04000000,0x3feda9e6
.long 0x47b9ff2d,0xbdf266bd
.long 0xd6400000,0x3fedbe7c
.long 0xb76f1927,0xbdc5f3ad
.long 0xf3000000,0x3fedd321
.long 0xb695de3c,0x3dab4604
.long 0x64000000,0x3fede7d5
.long 0x8d6ab5c6,0x3dec0657
.long 0x33800000,0x3fedfc97
.long 0x1a5cd4f2,0xbdc19285
.long 0x6b000000,0x3fee1167
.long 0xed4ad643,0x3de97d16
.long 0x15000000,0x3fee2646
.long 0xbdb13c0c,0xbdd4bdae
.long 0x3b000000,0x3fee3b33
.long 0x982d6f38,0x3de6ee11
.long 0xe7c00000,0x3fee502e
.long 0xec61767f,0xbdfa6004
.long 0x24800000,0x3fee6539
.long 0x2c7ff0ea,0xbde8928a
.long 0xfbc00000,0x3fee7a51
.long 0x2d522ca1,0x3dcd320d
.long 0x77c00000,0x3fee8f79
.long 0x77bb5bfa,0x3ddb6e7f
.long 0xa2c00000,0x3feea4af
.long 0x7a708c5e,0xbdeb6f26
.long 0x86800000,0x3feeb9f4
.long 0x6f9a1bae,0xbdb9ac8d
.long 0x2d800000,0x3feecf48
.long 0x1b60625f,0x3ddccfe1
.long 0xa2000000,0x3feee4aa
.long 0x471a3692,0x3de88510
.long 0xee400000,0x3feefa1b
.long 0xbb8fe90d,0x3df0ad13
.long 0x1cc00000,0x3fef0f9c
.long 0x99100329,0xbdd37dac
.long 0x37800000,0x3fef252b
.long 0xb1796904,0xbde44568
.long 0x48c00000,0x3fef3ac9
.long 0xe6a5a5c1,0x3ded7273
.long 0x5b800000,0x3fef5076
.long 0x98b07b49,0xbde1babf
.long 0x79800000,0x3fef6632
.long 0xfd1bd9aa,0x3dd089f0
.long 0xadc00000,0x3fef7bfd
.long 0x3b7625a0,0xbdf1a0f6
.long 0x02400000,0x3fef91d8
.long 0x08975454,0xbdebc377
.long 0x81c00000,0x3fefa7c1
.long 0xe8b7ac0c,0xbdf0b793
.long 0x36800000,0x3fefbdba
.long 0xe6988ceb,0x3de2d513
.long 0x2b800000,0x3fefd3c2
.long 0x12eb7496,0x3ddee3e2
.long 0x6b400000,0x3fefe9d9
.long 0xeb59fc8c,0xbde5dc26
.long 0x00000000,0x3ff00000
.long 0x00000000,0x00000000
.long 0xfa600000,0x3ff00b1a
.long 0xa7b5953b,0xbdd50d04
.long 0xaa000000,0x3ff0163d
.long 0x49ed6654,0xbdd3332a
.long 0x14400000,0x3ff02168
.long 0x95f9887e,0xbdd3f5fc
.long 0x3e800000,0x3ff02c9a
.long 0x232106a7,0xbde0ff3e
.long 0x2e200000,0x3ff037d4
.long 0xea97ee11,0xbdec8867
.long 0xe8800000,0x3ff04315
.long 0x428c7066,0xbdf1807b
.long 0x73000000,0x3ff04e5f
.long 0xacf21b15,0xbde3569d
.long 0xd3200000,0x3ff059b0
.long 0x8a30756e,0xbde4f517
.long 0x0e400000,0x3ff0650a
.long 0xb96f6af3,0xbdcf03ba
.long 0x29e00000,0x3ff0706b
.long 0xc91dfe2b,0xbdc04911
.long 0x2b800000,0x3ff07bd4
.long 0xb3732eaf,0xbdeaaf93
.long 0x18800000,0x3ff08745
.long 0xee7941b4,0xbde4c86f
.long 0xf6600000,0x3ff092bd
.long 0x97f9c7ff,0x3dd81f7e
.long 0xcac00000,0x3ff09e3e
.long 0x14878183,0x3ddbce0d
.long 0x9b200000,0x3ff0a9c7
.long 0x8ba4de31,0xbda8dcda
.long 0x6d000000,0x3ff0b558
.long 0x759d1b52,0xbdd9dbc2
.long 0x45e00000,0x3ff0c0f1
.long 0x4f98906d,0x3dd1b215
.long 0x2b600000,0x3ff0cc92
.long 0x407b705c,0x3df247f7
.long 0x23400000,0x3ff0d83b
.long 0xbc14de44,0xbdda8851
.long 0x32e00000,0x3ff0e3ec
.long 0xfbf17a36,0xbde85cbb
.long 0x5fe00000,0x3ff0efa5
.long 0x9db9bc54,0xbd958ed4
.long 0xb0000000,0x3ff0fb66
.long 0xdcdf6e22,0xbdb2ce50
.long 0x28c00000,0x3ff10730
.long 0x3a8dd62d,0x3df7233e
.long 0xd0200000,0x3ff11301
.long 0xb62881ca,0xbdeb495e
.long 0xab600000,0x3ff11edb
.long 0x29153dc1,0xbdbd54a7
.long 0xc0600000,0x3ff12abd
.long 0xf72575a6,0x3de86397
.long 0x14e00000,0x3ff136a8
.long 0xf477b823,0x3df204aa
.long 0xaea00000,0x3ff1429a
.long 0x66820328,0x3de25bbf
.long 0x93600000,0x3ff14e95
.long 0x3723d073,0xbdf0ced2
.long 0xc8a00000,0x3ff15a98
.long 0x920355cf,0x3dd63944
.long 0x54600000,0x3ff166a4
.long 0x063c8ee1,0x3df1c3c2
.long 0x3c800000,0x3ff172b8
.long 0x19041b9d,0xbdc57429
.long 0x86a00000,0x3ff17ed4
.long 0xdec3803b,0xbde4887f
.long 0x38800000,0x3ff18af9
.long 0x777ee173,0x3de91bd3
.long 0x58400000,0x3ff19726
.long 0x5aa913d0,0xbde145a1
.long 0xeb600000,0x3ff1a35b
.long 0x796d31ed,0x3def96ea
.long 0xf8200000,0x3ff1af99
.long 0x4203d2da,0xbde8ebc7
.long 0x84000000,0x3ff1bbe0
.long 0x6ac79cad,0x3dd1734e
.long 0x95200000,0x3ff1c82f
.long 0x804bbc01,0x3de038d6
.long 0x31800000,0x3ff1d487
.long 0x87fa47fd,0xbdf74655
.long 0x5ec00000,0x3ff1e0e7
.long 0xb7eec044,0xbde77fb2
.long 0x23000000,0x3ff1ed50
.long 0x3bf3004f,0xbdc9371a
.long 0x84400000,0x3ff1f9c1
.long 0xbf524a09,0xbddcc6cd
.long 0x88600000,0x3ff2063b
.long 0xdc775815,0x3dc466b1
.long 0x35600000,0x3ff212be
.long 0x4d64b4b4,0x3df8a819
.long 0x91800000,0x3ff21f49
.long 0xd56816b7,0xbdc11b4e
.long 0xa2800000,0x3ff22bdd
.long 0x16582554,0xbddbb4bb
.long 0x6e800000,0x3ff2387a
.long 0x327c0a4a,0xbde53b8f
.long 0xfba00000,0x3ff2451f
.long 0xca6066de,0xbdfdebf5
.long 0x4fc00000,0x3ff251ce
.long 0x94faa904,0xbdeab381
.long 0x71200000,0x3ff25e85
.long 0x07976d4f,0xbdb318ab
.long 0x65e00000,0x3ff26b45
.long 0x2bd33994,0x3dc3e6e9
.long 0x34200000,0x3ff2780e
.long 0x3f307f41,0xbdc106b4
.long 0xe1e00000,0x3ff284df
.long 0x96cf15cf,0x3df56380
.long 0x75800000,0x3ff291ba
.long 0xda671baf,0x3df1bb6f
.long 0xf5200000,0x3ff29e9d
.long 0xed175053,0xbd808f69
.long 0x66c00000,0x3ff2ab8a
.long 0x9aa2f39c,0x3df10f12
.long 0xd0e00000,0x3ff2b87f
.long 0x08856e6b,0xbdd499c0
.long 0x39600000,0x3ff2c57e
.long 0xabfae964,0x3df71b2e
.long 0xa7000000,0x3ff2d285
.long 0xbff6e2ad,0xbdfbfcf4
.long 0x1f600000,0x3ff2df96
.long 0xd16cffbc,0x3dd05625
.long 0xa9400000,0x3ff2ecaf
.long 0xe35f0ba3,0xbdbd0a9e
.long 0x4ac00000,0x3ff2f9d2
.long 0x54f1554d,0xbdc3bca8
.long 0x0a200000,0x3ff306fe
.long 0x2de8d5a4,0x3df1b715
.long 0xee000000,0x3ff31432
.long 0xcd4cb818,0xbdf14d02
.long 0xfc400000,0x3ff32170
.long 0x6a739e38,0x3de9b062
.long 0x3ba00000,0x3ff32eb8
.long 0x1dd0be1a,0x3de1d463
.long 0xb2600000,0x3ff33c08
.long 0x32721843,0x3dd05bfd
.long 0x66e00000,0x3ff34962
.long 0xca58a6cf,0x3dcfd166
.long 0x5fa00000,0x3ff356c5
.long 0x6d73b971,0xbdeac01e
.long 0xa2e00000,0x3ff36431
.long 0x8628940e,0xbdb77c53
.long 0x37400000,0x3ff371a7
.long 0x63aeabf4,0xbdd558d5
.long 0x23200000,0x3ff37f26
.long 0x7d72a7b4,0xbdb8ab66
.long 0x6d000000,0x3ff38cae
.long 0x16a72c36,0x3dd76196
.long 0x1b800000,0x3ff39a40
.long 0xcd4d2fe4,0xbded7e22
.long 0x34e00000,0x3ff3a7db
.long 0xa86f24a6,0x3dd67fdb
.long 0xc0000000,0x3ff3b57f
.long 0xaace6476,0xbdf3930b
.long 0xc3200000,0x3ff3c32d
.long 0xf7ffc1bb,0xbde8ae36
.long 0x44e00000,0x3ff3d0e5
.long 0x3fd1a118,0x3debc2e6
.long 0x4c200000,0x3ff3dea6
.long 0x9497dbb8,0xbdeb97bb
.long 0xdf200000,0x3ff3ec70
.long 0xaf6637b9,0xbdcd7459
.long 0x04a00000,0x3ff3fa45
.long 0x417ee035,0x3de90037
.long 0xc3600000,0x3ff40822
.long 0xdeefc5b8,0x3dde8090
.long 0x22000000,0x3ff4160a
.long 0x0f79b48e,0xbde1a3ac
.long 0x27000000,0x3ff423fb
.long 0x3dce91fa,0x3de28d13
.long 0xd9600000,0x3ff431f5
.long 0x471f778d,0xbdeeaed2
.long 0x3f800000,0x3ff43ffa
.long 0xc405f4b8,0x3dd2e750
.long 0x60600000,0x3ff44e08
.long 0x3136f40a,0x3db892d0
.long 0x42a00000,0x3ff45c20
.long 0xcf37ccfa,0x3ddf48c7
.long 0xed200000,0x3ff46a41
.long 0x6d7685d3,0xbdc7fd44
.long 0x66800000,0x3ff4786d
.long 0x1ef87896,0x3de6646d
.long 0xb5c00000,0x3ff486a2
.long 0x3c1a3b69,0x3db3cd01
.long 0xe1a00000,0x3ff494e1
.long 0x4eca2579,0xbdeaa25c
.long 0xf0e00000,0x3ff4a32a
.long 0x31a4e861,0xbde05843
.long 0xea800000,0x3ff4b17d
.long 0x224b70fe,0xbdf24829
.long 0xd5400000,0x3ff4bfda
.long 0xc578d0a0,0xbde3abb1
.long 0xb8000000,0x3ff4ce41
.long 0x4178a5a4,0x3df7c114
.long 0x9a000000,0x3ff4dcb2
.long 0xe2648873,0xbdc11794
.long 0x81e00000,0x3ff4eb2d
.long 0x5257d2e6,0xbddd5005
.long 0x76a00000,0x3ff4f9b2
.long 0x96613a4b,0xbdc69aca
.long 0x7f400000,0x3ff50841
.long 0x68926d27,0x3dd4c7b8
.long 0xa2c00000,0x3ff516da
.long 0x8225ea59,0x3deecc83
.long 0xe8400000,0x3ff5257d
.long 0x9331a87e,0xbda62223
.long 0x56a00000,0x3ff5342b
.long 0x07abe1db,0xbdc583f1
.long 0xf4e00000,0x3ff542e2
.long 0x2f24da32,0x3df6ad27
.long 0xca600000,0x3ff551a4
.long 0xd689ceff,0xbdc36f89
.long 0xde000000,0x3ff56070
.long 0x43edb85a,0xbdf6ef2e
.long 0x36800000,0x3ff56f47
.long 0x33765802,0x3e0a93ed
.long 0xdbc00000,0x3ff57e27
.long 0x5e8ce6eb,0x3e016267
.long 0xd4800000,0x3ff58d12
.long 0x252bc2b7,0x3df7c7fd
.long 0x28000000,0x3ff59c08
.long 0xf1677234,0xbdaf068b
.long 0xdd400000,0x3ff5ab07
.long 0xb192602a,0x3de0a852
.long 0xfb800000,0x3ff5ba11
.long 0x4910bd68,0x3e043d01
.long 0x8a400000,0x3ff5c926
.long 0x01c4b1b8,0x3df946b7
.long 0x90800000,0x3ff5d845
.long 0x8ca5615d,0x3df98b92
.long 0x15800000,0x3ff5e76f
.long 0x374df261,0x3e0690a4
.long 0x20c00000,0x3ff5f6a3
.long 0xcc2a4438,0x3dfceb70
.long 0xb9800000,0x3ff605e1
.long 0x9f1214db,0xbde247ee
.long 0xe6c00000,0x3ff6152a
.long 0xf259f256,0x3debede8
.long 0xb0400000,0x3ff6247e
.long 0x383c17e4,0xbdd6a9ed
.long 0x1d000000,0x3ff633dd
.long 0x611c42fb,0x3df929fd
.long 0x34c00000,0x3ff64346
.long 0x8edf0e2a,0x3de9863f
.long 0xfec00000,0x3ff652b9
.long 0x5c7ab935,0xbdcb824b
.long 0x82400000,0x3ff66238
.long 0x9127d9e3,0x3df52224
.long 0xc7000000,0x3ff671c1
.long 0x85e3369e,0x3de067eb
.long 0xd4400000,0x3ff68155
.long 0x1038ae45,0x3de952e6
.long 0xb1c00000,0x3ff690f4
.long 0xe7fb4265,0xbe00b563
.long 0x66800000,0x3ff6a09e
.long 0xee9a09d9,0xbda8866d
.type __libm_expl_table_256,@object
.size __libm_expl_table_256,4112
.data
.section .note.GNU-stack, ""
# End
|
GeminiCarrie/rust-sgx-sdk | 26,344 | sgx_libc/sgx_tlibc_sys/tlibc/math/exp10l.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "exp10l.c"
.text
..TXTST0:
# -- Begin exp10l
.text
.align 16,0x90
.globl exp10l
exp10l:
# parameter 1: 96 + %rsp
..B1.1:
.cfi_startproc
..___tag_value_exp10l.1:
..L2:
subq $88, %rsp
.cfi_def_cfa_offset 96
xorb %dil, %dil
..B1.2:
fnstcw 86(%rsp)
..B1.3:
movzwl 104(%rsp), %esi
movl %esi, %eax
movzbl 105(%rsp), %ecx
andl $32767, %eax
shrl $7, %ecx
shll $15, %ecx
orl %eax, %ecx
shll $16, %ecx
movzwl 102(%rsp), %edx
orl %edx, %ecx
addl $-1073709056, %ecx
cmpl $284672, %ecx
ja ..B1.6
..B1.4:
fldt 96(%rsp)
lea _TWO_23H(%rip), %rax
fld %st(0)
fldl (%rax)
fadd %st, %st(1)
fxch %st(1)
fstps 80(%rsp)
movss 80(%rsp), %xmm0
movss %xmm0, 16(%rsp)
flds 16(%rsp)
fsubp %st, %st(1)
fucomip %st(1), %st
fstp %st(0)
jp ..B1.5
je ..B1.79
..B1.5:
movl %esi, %eax
andl $32767, %eax
..B1.6:
cmpl $16388, %eax
jge ..B1.45
..B1.7:
movzwl 86(%rsp), %edx
cmpl $16375, %eax
jge ..B1.38
..B1.8:
cmpl $16368, %eax
jge ..B1.31
..B1.9:
cmpl $16357, %eax
jge ..B1.24
..B1.10:
cmpl $16316, %eax
jge ..B1.17
..B1.11:
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.73
..B1.12:
orl $-64768, %edx
movw %dx, 84(%rsp)
..B1.13:
fldcw 84(%rsp)
..B1.14:
fldt .L_2il0floatpacket.3(%rip)
fldt 96(%rsp)
faddp %st, %st(1)
fstpt 16(%rsp)
..B1.15:
fldcw 86(%rsp)
..B1.16:
fldt 16(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.17:
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.21
..B1.18:
orl $-64768, %edx
movw %dx, 84(%rsp)
..B1.19:
fldcw 84(%rsp)
..B1.20:
movb $1, %dil
..B1.21:
fldt 96(%rsp)
lea 16+_Q2(%rip), %rax
fldt .L_2il0floatpacket.3(%rip)
lea _Q2(%rip), %rdx
testb %dil, %dil
fldt (%rax)
fmul %st(2), %st
fldt (%rdx)
faddp %st, %st(1)
fmulp %st, %st(2)
faddp %st, %st(1)
fstpt 16(%rsp)
je ..B1.23
..B1.22:
fldcw 86(%rsp)
..B1.23:
fldt 16(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.24:
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.28
..B1.25:
orl $-64768, %edx
movw %dx, 84(%rsp)
..B1.26:
fldcw 84(%rsp)
..B1.27:
movb $1, %dil
..B1.28:
fldt 96(%rsp)
lea 48+_Q1(%rip), %rax
fld %st(0)
lea 32+_Q1(%rip), %rdx
fmul %st(1), %st
lea 16+_Q1(%rip), %rcx
fldt (%rax)
lea _Q1(%rip), %rsi
fmul %st(1), %st
testb %dil, %dil
fldt (%rdx)
fmul %st(2), %st
fldt (%rcx)
faddp %st, %st(2)
fxch %st(1)
fmulp %st, %st(2)
fldt (%rsi)
faddp %st, %st(1)
fmulp %st, %st(2)
faddp %st, %st(1)
fldt .L_2il0floatpacket.3(%rip)
faddp %st, %st(1)
fstpt 16(%rsp)
je ..B1.30
..B1.29:
fldcw 86(%rsp)
..B1.30:
fldt 16(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.31:
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.35
..B1.32:
orl $-64768, %edx
movw %dx, 84(%rsp)
..B1.33:
fldcw 84(%rsp)
..B1.34:
movb $1, %dil
..B1.35:
fldt 96(%rsp)
lea 112+_Q0(%rip), %rdx
fld %st(0)
lea 96+_Q0(%rip), %rcx
fmul %st(1), %st
lea 80+_Q0(%rip), %rsi
lea 64+_Q0(%rip), %r8
lea 48+_Q0(%rip), %r9
lea 32+_Q0(%rip), %r10
lea _TWO_48H(%rip), %rax
lea 16+_Q0(%rip), %r11
fld %st(1)
fld %st(2)
testb %dil, %dil
fldt (%rdx)
lea 128+_Q0(%rip), %rdx
fmul %st(3), %st
fldl (%rax)
lea _Q0(%rip), %rax
fadd %st, %st(3)
fsubr %st(3), %st
fsubr %st, %st(2)
fldt (%rcx)
fmul %st(5), %st
fldt (%rsi)
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
fldt (%r8)
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
fldt (%r9)
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
fldt (%r10)
faddp %st, %st(3)
fxch %st(2)
fmul %st(5), %st
fldt (%r11)
faddp %st, %st(3)
fxch %st(2)
fmulp %st, %st(5)
fldt (%rax)
faddp %st, %st(2)
fxch %st(1)
fmulp %st, %st(5)
fxch %st(4)
faddp %st, %st(3)
fldt (%rdx)
fmul %st, %st(4)
fmulp %st, %st(1)
faddp %st, %st(2)
fldt .L_2il0floatpacket.3(%rip)
faddp %st, %st(3)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
fstpt 16(%rsp)
je ..B1.85
..B1.36:
fstpt 48(%rsp)
..B1.82:
fldcw 86(%rsp)
jmp ..B1.37
..B1.85:
fstp %st(0)
..B1.37:
fldt 16(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.38:
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.42
..B1.39:
orl $-64768, %edx
movw %dx, 84(%rsp)
..B1.40:
fldcw 84(%rsp)
..B1.41:
movb $1, %dil
..B1.42:
fldt 96(%rsp)
lea _TWO_63H(%rip), %rdx
fldt .L_2il0floatpacket.0(%rip)
lea _TWO_48H(%rip), %rcx
fmul %st(1), %st
lea 80+_P(%rip), %r8
fldl (%rdx)
lea 48+_P(%rip), %r10
lea 64+_P(%rip), %r9
lea 32+_P(%rip), %r11
lea 16+_P(%rip), %rdx
fadd %st, %st(1)
fxch %st(1)
fstpt 48(%rsp)
fldt 48(%rsp)
fsubp %st, %st(1)
fldt .L_2il0floatpacket.1(%rip)
fmul %st(1), %st
movl 48(%rsp), %esi
fsubrp %st, %st(2)
fld %st(1)
fldt .L_2il0floatpacket.2(%rip)
fmulp %st, %st(2)
movsbq %sil, %rax
fsub %st(1), %st
fldl (%rcx)
lea _P(%rip), %rcx
subl %eax, %esi
fadd %st, %st(1)
shrl $8, %esi
fsubr %st(1), %st
fld %st(0)
fxch %st(1)
fsubr %st, %st(4)
shll $23, %esi
fxch %st(3)
fsubrp %st, %st(4)
addl $1065353216, %esi
fadd %st(3), %st
fld %st(0)
fmul %st(1), %st
fldt (%r8)
fmul %st(1), %st
fldt (%r9)
fmul %st(2), %st
fldt (%r10)
movl %esi, 32(%rsp)
lea 96+_P(%rip), %rsi
shlq $4, %rax
faddp %st, %st(2)
fxch %st(1)
fmul %st(2), %st
testb %dil, %dil
fldt (%r11)
movq __libm_expl_table_256@GOTPCREL(%rip), %r8
faddp %st, %st(2)
fxch %st(1)
fmul %st(2), %st
fldt (%rdx)
faddp %st, %st(2)
fxch %st(2)
fmulp %st, %st(1)
fldt (%rcx)
faddp %st, %st(2)
fxch %st(2)
fmulp %st, %st(1)
faddp %st, %st(1)
fldt (%rsi)
fmul %st, %st(4)
fxch %st(4)
faddp %st, %st(1)
fxch %st(3)
fmulp %st, %st(2)
fldl 2056(%r8,%rax)
fldl 2048(%r8,%rax)
fld %st(0)
fmul %st(5), %st
fxch %st(4)
fadd %st, %st(5)
fxch %st(2)
fmul %st, %st(5)
fxch %st(5)
faddp %st, %st(4)
fxch %st(4)
faddp %st, %st(3)
fmul %st(3), %st
faddp %st, %st(3)
fxch %st(1)
faddp %st, %st(2)
fxch %st(1)
fmuls 32(%rsp)
fstpt 16(%rsp)
je ..B1.86
..B1.43:
fstpt 48(%rsp)
..B1.83:
fldcw 86(%rsp)
jmp ..B1.44
..B1.86:
fstp %st(0)
..B1.44:
fldt 16(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.45:
movb 105(%rsp), %dl
lea _ranges(%rip), %r8
andb $-128, %dl
shrb $7, %dl
movzbl %dl, %esi
movq %rsi, %rcx
shlq $4, %rcx
movzwl 8(%rcx,%r8), %edx
andl $32767, %edx
cmpl %edx, %eax
jl ..B1.50
..B1.46:
jne ..B1.62
..B1.47:
movl 100(%rsp), %edx
cmpl 4(%rcx,%r8), %edx
jb ..B1.50
..B1.48:
jne ..B1.62
..B1.49:
movl 96(%rsp), %edx
cmpl (%rcx,%r8), %edx
jae ..B1.62
..B1.50:
movzwl 86(%rsp), %edx
movl %edx, %eax
andl $768, %eax
cmpl $768, %eax
je ..B1.54
..B1.51:
orl $-64768, %edx
movw %dx, 84(%rsp)
..B1.52:
fldcw 84(%rsp)
..B1.53:
movb $1, %dil
..B1.54:
fldt .L_2il0floatpacket.3(%rip)
lea _TWO_63H(%rip), %r8
fstpt 64(%rsp)
lea _TWO_48H(%rip), %r9
fldt 96(%rsp)
lea SC2_BIAS(%rip), %r10
fldt .L_2il0floatpacket.0(%rip)
fmul %st(1), %st
fldl (%r8)
movzwl 8+.L_2il0floatpacket.3(%rip), %r8d
fadd %st, %st(1)
fxch %st(1)
fstpt 48(%rsp)
fldt 48(%rsp)
andl $-32768, %r8d
movl 48(%rsp), %edx
fsubp %st, %st(1)
fldt .L_2il0floatpacket.1(%rip)
fmul %st(1), %st
movsbq %dl, %rax
fsubr %st(2), %st
fld %st(0)
movl %eax, %r11d
fldt .L_2il0floatpacket.2(%rip)
negl %r11d
fmulp %st, %st(3)
addl %edx, %r11d
shrl $8, %r11d
addl $4196735, %edx
addl (%r10,%rsi,4), %r11d
lea 80+_P(%rip), %rsi
andl $32767, %r11d
lea 16+_P(%rip), %r10
orl %r11d, %r8d
lea _P(%rip), %r11
movw %r8w, 72(%rsp)
lea 48+_P(%rip), %r8
shlq $4, %rax
fsub %st(2), %st
fldl (%r9)
lea 32+_P(%rip), %r9
cmpl $3070, %edx
fadd %st, %st(1)
fxch %st(1)
fstpt 16(%rsp)
fldt 16(%rsp)
fsubp %st, %st(1)
fld %st(0)
fxch %st(1)
fsubr %st, %st(2)
fxch %st(3)
fsubrp %st, %st(2)
fadd %st(1), %st
fld %st(0)
fmul %st(1), %st
fldt (%rsi)
lea 64+_P(%rip), %rsi
fmul %st(1), %st
fldt (%rsi)
lea 96+_P(%rip), %rsi
fmul %st(2), %st
fldt (%r8)
movq __libm_expl_table_256@GOTPCREL(%rip), %r8
faddp %st, %st(2)
fxch %st(1)
fmul %st(2), %st
fldt (%r9)
faddp %st, %st(2)
fxch %st(1)
fmul %st(2), %st
fldt (%r10)
faddp %st, %st(2)
fxch %st(2)
fmulp %st, %st(1)
fldt (%r11)
faddp %st, %st(2)
fxch %st(2)
fmulp %st, %st(1)
faddp %st, %st(1)
fldt (%rsi)
fmul %st, %st(2)
fxch %st(2)
faddp %st, %st(1)
fxch %st(1)
fmulp %st, %st(2)
fldl 2048(%r8,%rax)
fld %st(0)
fmul %st(2), %st
fxch %st(2)
fadd %st(3), %st
fxch %st(1)
fmul %st, %st(3)
faddp %st, %st(3)
fmull 2056(%r8,%rax)
faddp %st, %st(1)
faddl 2056(%r8,%rax)
ja ..B1.57
..B1.55:
lea _exp10but(%rip), %rax
fldt (%rax)
fcomip %st(3), %st
jbe ..B1.57
..B1.56:
fstp %st(2)
fld %st(0)
lea _TWO_12H(%rip), %rax
lea _SC2(%rip), %rdx
fadd %st(2), %st
fldl (%rax)
fmul %st(1), %st
fadd %st, %st(1)
fxch %st(1)
fstpt 16(%rsp)
fldt 16(%rsp)
fsubp %st, %st(1)
fsubr %st, %st(1)
fxch %st(1)
faddp %st, %st(2)
fldt (%rcx,%rdx)
fldt 64(%rsp)
fmul %st, %st(2)
fxch %st(1)
fmul %st, %st(2)
fxch %st(1)
fmulp %st, %st(3)
fmulp %st, %st(2)
faddp %st, %st(1)
fstpt 32(%rsp)
jmp ..B1.58
..B1.57:
fstp %st(2)
fldt 64(%rsp)
fxch %st(2)
faddp %st, %st(1)
lea _SC2(%rip), %rax
fmulp %st, %st(1)
fldt (%rcx,%rax)
fmulp %st, %st(1)
fstpt 32(%rsp)
..B1.58:
fldt 32(%rsp)
lea _minnorm(%rip), %rax
fldt (%rax)
fcomip %st(1), %st
fstp %st(0)
ja ..B1.74
..B1.59:
testb %dil, %dil
je ..B1.61
..B1.60:
fldt 16(%rsp)
fstpt 48(%rsp)
..B1.84:
fldcw 86(%rsp)
..B1.61:
fldt 32(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.62:
movzwl 86(%rsp), %ecx
movl %ecx, %edx
andl $768, %edx
cmpl $768, %edx
je ..B1.66
..B1.63:
orl $-64768, %ecx
movw %cx, 84(%rsp)
..B1.64:
fldcw 84(%rsp)
..B1.65:
movzwl 104(%rsp), %eax
movb $1, %dil
andl $32767, %eax
..B1.66:
cmpl $32767, %eax
je ..B1.75
..B1.67:
testq %rsi, %rsi
je ..B1.69
..B1.68:
lea _small_value_80(%rip), %rax
fldt (%rax)
fmul %st(0), %st
fstpt 16(%rsp)
jmp ..B1.70
..B1.69:
lea _large_value_80(%rip), %rax
fldt (%rax)
fmul %st(0), %st
fstpt 16(%rsp)
..B1.70:
testb %dil, %dil
je ..B1.72
..B1.71:
fldcw 86(%rsp)
..B1.72:
fldt 16(%rsp)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_def_cfa_offset 96
..B1.73:
fldt .L_2il0floatpacket.3(%rip)
fldt 96(%rsp)
faddp %st, %st(1)
fstpt 16(%rsp)
jmp ..B1.16
..B1.74:
lea _small_value_80(%rip), %rax
fldt (%rax)
fmul %st(0), %st
fstpt (%rsp)
jmp ..B1.59
..B1.75:
cmpl $-2147483648, 100(%rsp)
jne ..B1.78
..B1.76:
cmpl $0, 96(%rsp)
jne ..B1.78
..B1.77:
lea _inf_zeros(%rip), %rax
fldl (%rax,%rsi,8)
fstpt 16(%rsp)
jmp ..B1.70
..B1.78:
fldt 96(%rsp)
fstpt 16(%rsp)
jmp ..B1.70
..B1.79:
movl 80(%rsp), %eax
lea _exact_values(%rip), %rdx
andl $4194303, %eax
shlq $4, %rax
fldt -16(%rdx,%rax)
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.align 16,0x90
.cfi_endproc
.type exp10l,@function
.size exp10l,.-exp10l
.data
# -- End exp10l
.section .rodata, "a"
.align 16
.align 16
.L_2il0floatpacket.0:
.byte 0x00,0x88,0x1b,0xcd,0x4b,0x78,0x9a,0xd4,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.0,@object
.size .L_2il0floatpacket.0,16
.align 16
.L_2il0floatpacket.1:
.byte 0x00,0x00,0x00,0x00,0x85,0x9a,0x20,0x9a,0xf5,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.1,@object
.size .L_2il0floatpacket.1,16
.align 16
.L_2il0floatpacket.2:
.byte 0x00,0xc8,0xd4,0x0e,0xee,0x0c,0x01,0x86,0xd0,0xbf,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.2,@object
.size .L_2il0floatpacket.2,16
.align 16
.L_2il0floatpacket.3:
.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xff,0x3f,0x00,0x00,0x00,0x00,0x00,0x00
.type .L_2il0floatpacket.3,@object
.size .L_2il0floatpacket.3,16
.align 4
_TWO_23H:
.long 0
.long 1097334784
.type _TWO_23H,@object
.size _TWO_23H,8
.align 4
_TWO_48H:
.long 0
.long 1123549184
.type _TWO_48H,@object
.size _TWO_48H,8
.align 4
_TWO_63H:
.long 0
.long 1139277824
.type _TWO_63H,@object
.size _TWO_63H,8
.align 4
SC2_BIAS:
.long 8191
.long 24575
.type SC2_BIAS,@object
.size SC2_BIAS,8
.align 4
_TWO_12H:
.long 0
.long 1085800448
.type _TWO_12H,@object
.size _TWO_12H,8
.align 4
_inf_zeros:
.long 0
.long 2146435072
.long 0
.long 0
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// -- Begin DWARF2 SEGMENT .eh_frame
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|
GeminiCarrie/rust-sgx-sdk | 13,604 | sgx_libc/sgx_tlibc_sys/tlibc/math/rcp_table.S | /*
* Math library
*
* Copyright (C) 2016 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
* Author Name <jingwei.zhang@intel.com>
* History:
* 03-14-2016 Initial version. numerics svn rev. 12864
*/
.file "rcp_table.c"
.section .rodata, "a"
.align 32
.align 32
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.long 0
.long 1071953920
.long 0
.long 1071949824
.long 0
.long 1071946752
.long 0
.long 1071943680
.long 0
.long 1071939584
.long 0
.long 1071936512
.long 0
.long 1071933440
.long 0
.long 1071930368
.long 0
.long 1071926272
.long 0
.long 1071923200
.long 0
.long 1071920128
.long 0
.long 1071917056
.long 0
.long 1071913984
.long 0
.long 1071909888
.long 0
.long 1071906816
.long 0
.long 1071903744
.long 0
.long 1071900672
.long 0
.long 1071897600
.long 0
.long 1071894528
.long 0
.long 1071891456
.long 0
.long 1071888384
.long 0
.long 1071885312
.long 0
.long 1071882240
.long 0
.long 1071879168
.long 0
.long 1071876096
.long 0
.long 1071873024
.long 0
.long 1071869952
.long 0
.long 1071866880
.long 0
.long 1071863808
.long 0
.long 1071860736
.long 0
.long 1071857664
.long 0
.long 1071854592
.long 0
.long 1071851520
.long 0
.long 1071849472
.long 0
.long 1071846400
.long 0
.long 1071843328
.long 0
.long 1071840256
.long 0
.long 1071837184
.long 0
.long 1071834112
.long 0
.long 1071832064
.long 0
.long 1071828992
.long 0
.long 1071825920
.long 0
.long 1071822848
.long 0
.long 1071820800
.long 0
.long 1071817728
.long 0
.long 1071814656
.long 0
.long 1071812608
.long 0
.long 1071809536
.long 0
.long 1071806464
.long 0
.long 1071804416
.long 0
.long 1071801344
.long 0
.long 1071798272
.long 0
.long 1071796224
.long 0
.long 1071793152
.long 0
.long 1071790080
.long 0
.long 1071788032
.long 0
.long 1071784960
.long 0
.long 1071782912
.long 0
.long 1071779840
.long 0
.long 1071777792
.long 0
.long 1071774720
.long 0
.long 1071771648
.long 0
.long 1071769600
.long 0
.long 1071766528
.long 0
.long 1071764480
.long 0
.long 1071762432
.long 0
.long 1071759360
.long 0
.long 1071757312
.long 0
.long 1071754240
.long 0
.long 1071752192
.long 0
.long 1071749120
.long 0
.long 1071747072
.long 0
.long 1071744000
.long 0
.long 1071741952
.long 0
.long 1071739904
.long 0
.long 1071736832
.long 0
.long 1071734784
.long 0
.long 1071732736
.long 0
.long 1071729664
.long 0
.long 1071727616
.long 0
.long 1071725568
.long 0
.long 1071722496
.long 0
.long 1071720448
.long 0
.long 1071718400
.long 0
.long 1071715328
.long 0
.long 1071713280
.long 0
.long 1071711232
.long 0
.long 1071709184
.long 0
.long 1071706112
.long 0
.long 1071704064
.long 0
.long 1071702016
.long 0
.long 1071699968
.long 0
.long 1071696896
.long 0
.long 1071694848
.long 0
.long 1071692800
.long 0
.long 1071690752
.long 0
.long 1071688704
.long 0
.long 1071686656
.long 0
.long 1071683584
.long 0
.long 1071681536
.long 0
.long 1071679488
.long 0
.long 1071677440
.long 0
.long 1071675392
.long 0
.long 1071673344
.long 0
.long 1071671296
.long 0
.long 1071669248
.long 0
.long 1071666176
.long 0
.long 1071664128
.long 0
.long 1071662080
.long 0
.long 1071660032
.long 0
.long 1071657984
.long 0
.long 1071655936
.long 0
.long 1071653888
.long 0
.long 1071651840
.long 0
.long 1071649792
.long 0
.long 1071647744
.long 0
.long 1071645696
.type __libm_double_rcp_table_256,@object
.size __libm_double_rcp_table_256,2048
.data
.section .note.GNU-stack, ""
# End
|
GeminiCarrie/rust-sgx-sdk | 817 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/bzero.S | /*
* Written by J.T. Conklin <jtc@netbsd.org>.
* Public domain.
* Adapted for NetBSD/x86_64 by Frank van der Linden <fvdl@wasabisystems.com>
*/
#include "DEFS.h"
ENTRY(_bzero)
RETGUARD_SETUP(_bzero, r11)
movq %rsi,%rdx
cld /* set fill direction forward */
xorq %rax,%rax /* set fill data to 0 */
/*
* if the string is too short, it's really not worth the overhead
* of aligning to word boundaries, etc. So we jump to a plain
* unaligned set.
*/
cmpq $16,%rdx
jb L1
movq %rdi,%rcx /* compute misalignment */
negq %rcx
andq $7,%rcx
subq %rcx,%rdx
rep /* zero until word aligned */
stosb
movq %rdx,%rcx /* zero by words */
shrq $3,%rcx
andq $7,%rdx
rep
stosq
L1: movq %rdx,%rcx /* zero remainder by bytes */
rep
stosb
RETGUARD_CHECK(_bzero, r11)
ret
END_WEAK(_bzero)
|
GeminiCarrie/rust-sgx-sdk | 2,710 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/memmove.S | /*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from locore.s.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "DEFS.h"
/*
* __memmove (dst,src,cnt)
* ws@tools.de (Wolfgang Solfrank, TooLs GmbH) +49-228-985800
*/
ENTRY(_bcopy)
xchgq %rdi,%rsi
/* fall into memmove */
NENTRY(__memmove)
RETGUARD_SETUP(__memmove, r10)
movq %rdi,%r11 /* save dest */
movq %rdx,%rcx
movq %rdi,%rax
subq %rsi,%rax
cmpq %rcx,%rax /* overlapping? */
jb 1f
cld /* copy forwards. */
shrq $3,%rcx /* copy by words */
rep
movsq
movq %rdx,%rcx
andq $7,%rcx /* any bytes left? */
rep
movsb
movq %r11,%rax
jmp 3f
1:
addq %rcx,%rdi /* copy backwards. */
addq %rcx,%rsi
std
andq $7,%rcx /* any fractional bytes? */
decq %rdi
decq %rsi
rep
movsb
movq %rdx,%rcx /* copy remainder by words */
shrq $3,%rcx
subq $7,%rsi
subq $7,%rdi
rep
movsq
movq %r11,%rax
cld
3: RETGUARD_CHECK(__memmove, r10)
ret
END_BUILTIN(__memmove)
|
GeminiCarrie/rust-sgx-sdk | 595 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/memchr.S | /*
* Written by J.T. Conklin <jtc@netbsd.org>.
* Public domain.
* Adapted for NetBSD/x86_64 by Frank van der Linden <fvdl@wasabisystems.com>
*/
#include "DEFS.h"
ENTRY(_memchr)
RETGUARD_SETUP(_memchr, r11)
movb %sil,%al /* set character to search for */
movq %rdx,%rcx /* set length of search */
testq %rcx,%rcx /* test for len == 0 */
jz L1
cld /* set search forward */
repne /* search! */
scasb
jne L1 /* scan failed, return null */
leaq -1(%rdi),%rax /* adjust result of scan */
jmp L2
L1: xorq %rax,%rax
L2: RETGUARD_CHECK(_memchr, r11)
ret
END_STRONG(_memchr)
|
GeminiCarrie/rust-sgx-sdk | 5,734 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/strlen.S | /* $OpenBSD: _strlen.S,v 1.8 2018/07/03 23:14:05 mortimer Exp $ */
/* $NetBSD: _strlen.S,v 1.6 2014/03/22 19:16:34 jakllsch Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by David Laight.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Inspired by a version written by J.T. Conklin <jtc@acorntoolworks.com>
* (Only the long comment really remains his work!)
*/
#include "DEFS.h"
/*
* There are many well known branch-free sequences which are used
* for determining whether a zero-byte is contained within a word.
* These sequences are generally much more efficent than loading
* and comparing each byte individually.
*
* The expression [1,2]:
*
* (1) ~(((x & 0x7f....7f) + 0x7f....7f) | (x | 0x7f....7f))
*
* evaluates to a non-zero value if any of the bytes in the
* original word is zero.
*
* It also has the useful property that bytes in the result word
* that correspond to non-zero bytes in the original word have
* the value 0x00, while bytes corresponding to zero bytes have
* the value 0x80. This allows calculation of the first (and
* last) occurrence of a zero byte within the word (useful for C's
* str* primitives) by counting the number of leading (or
* trailing) zeros and dividing the result by 8. On machines
* without (or with slow) clz() / ctz() instructions, testing
* each byte in the result word for zero is necessary.
*
* This typically takes 4 instructions (5 on machines without
* "not-or") not including those needed to load the constant.
*
*
* The expression:
*
* (2) ((x - 0x01....01) & 0x80....80 & ~x)
*
* evaluates to a non-zero value if any of the bytes in the
* original word is zero.
*
* On little endian machines, the first byte in the result word
* that corresponds to a zero byte in the original byte is 0x80,
* so clz() can be used as above. On big endian machines, and
* little endian machines without (or with a slow) clz() insn,
* testing each byte in the original for zero is necessary.
*
* This typically takes 3 instructions (4 on machines without
* "and with complement") not including those needed to load
* constants.
*
*
* The expression:
*
* (3) ((x - 0x01....01) & 0x80....80)
*
* always evaluates to a non-zero value if any of the bytes in
* the original word is zero or has the top bit set.
* For strings that are likely to only contain 7-bit ascii these
* false positives will be rare.
*
* To account for possible false positives, each byte of the
* original word must be checked when the expression evaluates to
* a non-zero value. However, because it is simpler than those
* presented above, code that uses it will be faster as long as
* the rate of false positives is low.
*
* This is likely, because the false positive can only occur
* if the most siginificant bit of a byte within the word is set.
* The expression will never fail for typical 7-bit ASCII strings.
*
* This typically takes 2 instructions not including those needed
* to load constants.
*
*
* [1] Henry S. Warren Jr., "Hacker's Delight", Addison-Westley 2003
*
* [2] International Business Machines, "The PowerPC Compiler Writer's
* Guide", Warthman Associates, 1996
*/
ENTRY(_strlen)
RETGUARD_SETUP(_strlen, r11)
movabsq $0x0101010101010101,%r8
test $7,%dil
movq %rdi,%rax /* Buffer, %rdi unchanged */
movabsq $0x8080808080808080,%r9
jnz 10f /* Jump if misaligned */
_ALIGN_TEXT
1:
movq (%rax),%rdx /* get bytes to check */
2:
addq $8,%rax
mov %rdx,%rcx /* save for later check */
subq %r8,%rdx /* alg (3) above first */
not %rcx /* Invert of data */
andq %r9,%rdx
je 1b /* jump if all 0x01-0x80 */
/* Do check from alg (2) above - loops for 0x81..0xff bytes */
andq %rcx,%rdx
je 1b
/* Since we are LE, use bit scan for first 0x80 byte */
sub %rdi,%rax /* length to next word */
bsf %rdx,%rdx /* 7, 15, 23 ... 63 */
shr $3,%rdx /* 0, 1, 2 ... 7 */
lea -8(%rax,%rdx),%rax
RETGUARD_CHECK(_strlen, r11)
ret
/* Misaligned, read aligned word and make low bytes non-zero */
_ALIGN_TEXT
10:
mov %al,%cl
mov $1,%rsi
and $7,%cl /* offset into word 1..7 */
and $~7,%al /* start of word with buffer */
shl $3,%cl /* bit count 8, 16 .. 56 */
movq (%rax),%rdx /* first data in high bytes */
shl %cl,%rsi
dec %rsi
or %rsi,%rdx /* low bytes now non-zero */
jmp 2b
END_STRONG(_strlen)
|
GeminiCarrie/rust-sgx-sdk | 2,174 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/memcpy_verw.S | /*
* Copyright (C) 2011-2021 Intel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "DEFS.h"
/*
* void* __memcpy_verw(void *dst, const void *src)
*
*/
ENTRY(__memcpy_verw)
RETGUARD_SETUP(__memcpy_verw, r10)
movb (%rsi), %al
sub $8, %rsp
mov %ds, (%rsp)
verw (%rsp)
movb %al, (%rdi)
mfence
lfence
add $8, %rsp
movq %rdi, %rax
RETGUARD_CHECK(__memcpy_verw, r10)
ret
END_STRONG(__memcpy_verw)
/*
* void* __memcpy_8a(void *dst, const void *src)
*
*/
ENTRY(__memcpy_8a)
RETGUARD_SETUP(__memcpy_8a, r10)
movq (%rsi), %rax
movq %rax, (%rdi)
movq %rdi, %rax
RETGUARD_CHECK(__memcpy_8a, r10)
ret
END_STRONG(__memcpy_8a)
|
GeminiCarrie/rust-sgx-sdk | 2,308 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/strrchr.S | /* $OpenBSD: _strrchr.S,v 1.9 2018/07/03 23:14:05 mortimer Exp $ */
/* $NetBSD: _strrchr.S,v 1.3 2014/03/22 19:16:34 jakllsch Exp $ */
/*
* Written by J.T. Conklin <jtc@acorntoolworks.com>
* Public domain.
*/
#include "DEFS.h"
ENTRY(_strrchr)
RETGUARD_SETUP(_strrchr, r11)
movzbq %sil,%rcx
/* zero return value */
xorq %rax,%rax
/*
* Align to word boundary.
* Consider unrolling loop?
*/
.Lalign:
testb $7,%dil
je .Lword_aligned
movb (%rdi),%dl
cmpb %cl,%dl
cmoveq %rdi,%rax
incq %rdi
testb %dl,%dl
jne .Lalign
jmp .Ldone
.Lword_aligned:
/* copy char to all bytes in word */
movb %cl,%ch
movq %rcx,%rdx
salq $16,%rcx
orq %rdx,%rcx
movq %rcx,%rdx
salq $32,%rcx
orq %rdx,%rcx
movabsq $0x0101010101010101,%r8
movabsq $0x8080808080808080,%r9
/* Check whether any byte in the word is equal to ch or 0. */
_ALIGN_TEXT
.Lloop:
movq (%rdi),%rdx
addq $8,%rdi
movq %rdx,%rsi
subq %r8,%rdx
xorq %rcx,%rsi
subq %r8,%rsi
orq %rsi,%rdx
testq %r9,%rdx
je .Lloop
/*
* In rare cases, the above loop may exit prematurely. We must
* return to the loop if none of the bytes in the word match
* ch or are equal to 0.
*/
movb -8(%rdi),%dl
cmpb %cl,%dl /* 1st byte == ch? */
jne 1f
leaq -8(%rdi),%rax
1: testb %dl,%dl /* 1st byte == 0? */
je .Ldone
movb -7(%rdi),%dl
cmpb %cl,%dl /* 2nd byte == ch? */
jne 1f
leaq -7(%rdi),%rax
1: testb %dl,%dl /* 2nd byte == 0? */
je .Ldone
movb -6(%rdi),%dl
cmpb %cl,%dl /* 3rd byte == ch? */
jne 1f
leaq -6(%rdi),%rax
1: testb %dl,%dl /* 3rd byte == 0? */
je .Ldone
movb -5(%rdi),%dl
cmpb %cl,%dl /* 4th byte == ch? */
jne 1f
leaq -5(%rdi),%rax
1: testb %dl,%dl /* 4th byte == 0? */
je .Ldone
movb -4(%rdi),%dl
cmpb %cl,%dl /* 5th byte == ch? */
jne 1f
leaq -4(%rdi),%rax
1: testb %dl,%dl /* 5th byte == 0? */
je .Ldone
movb -3(%rdi),%dl
cmpb %cl,%dl /* 6th byte == ch? */
jne 1f
leaq -3(%rdi),%rax
1: testb %dl,%dl /* 6th byte == 0? */
je .Ldone
movb -2(%rdi),%dl
cmpb %cl,%dl /* 7th byte == ch? */
jne 1f
leaq -2(%rdi),%rax
1: testb %dl,%dl /* 7th byte == 0? */
je .Ldone
movb -1(%rdi),%dl
cmpb %cl,%dl /* 8th byte == ch? */
jne 1f
leaq -1(%rdi),%rax
1: testb %dl,%dl /* 8th byte == 0? */
jne .Lloop
.Ldone:
RETGUARD_CHECK(_strrchr, r11)
ret
END_STRONG(_strrchr)
|
GeminiCarrie/rust-sgx-sdk | 1,244 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/strcmp.S | /* $OpenBSD: _strcmp.S,v 1.8 2018/07/03 23:14:05 mortimer Exp $ */
/* $NetBSD: _strcmp.S,v 1.2 2014/03/22 19:16:34 jakllsch Exp $ */
/*
* Written by J.T. Conklin <jtc@acorntoolworks.com>
* Public domain.
*/
#include "DEFS.h"
ENTRY(_strcmp)
RETGUARD_SETUP(_strcmp, r11)
/*
* Align s1 to word boundary.
* Consider unrolling loop?
*/
.Ls1align:
testb $7,%dil
je .Ls1aligned
movb (%rdi),%al
incq %rdi
movb (%rsi),%dl
incq %rsi
testb %al,%al
je .Ldone
cmpb %al,%dl
je .Ls1align
jmp .Ldone
/*
* Check whether s2 is aligned to a word boundary. If it is, we
* can compare by words. Otherwise we have to compare by bytes.
*/
.Ls1aligned:
testb $7,%sil
jne .Lbyte_loop
movabsq $0x0101010101010101,%r8
subq $8,%rdi
movabsq $0x8080808080808080,%r9
subq $8,%rsi
_ALIGN_TEXT
.Lword_loop:
movq 8(%rdi),%rax
addq $8,%rdi
movq 8(%rsi),%rdx
addq $8,%rsi
cmpq %rax,%rdx
jne .Lbyte_loop
subq %r8,%rdx
notq %rax
andq %rax,%rdx
testq %r9,%rdx
je .Lword_loop
_ALIGN_TEXT
.Lbyte_loop:
movb (%rdi),%al
incq %rdi
movb (%rsi),%dl
incq %rsi
testb %al,%al
je .Ldone
cmpb %al,%dl
je .Lbyte_loop
.Ldone:
movzbq %al,%rax
movzbq %dl,%rdx
subq %rdx,%rax
RETGUARD_CHECK(_strcmp, r11)
ret
END_STRONG(_strcmp)
|
GeminiCarrie/rust-sgx-sdk | 4,652 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/strchr.S | /* $OpenBSD: strchr.S,v 1.9 2018/07/03 23:14:05 mortimer Exp $ */
/* $NetBSD: strchr.S,v 1.7 2014/03/22 19:16:34 jakllsch Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by David Laight.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* See comments in strlen.S about checking words for byte values */
#include "DEFS.h"
//WEAK_ALIAS(index, strchr)
/*
* On entry %rdi is the buffer and the low byte of %rsi (%sil) the
* character to search for.
*
* Registers %rdx, %rcx, %r8-%r11 and %rax are also usable
*/
ENTRY(_strchr)
RETGUARD_SETUP(_strchr, r8)
RETGUARD_PUSH(r8)
movabsq $0x0101010101010101,%r8
movzbq %sil,%rdx /* value to search for (c) */
/* These imul are 'directpath' on athlons, so are fast */
imul $0x80,%r8,%r9 /* 0x8080808080808080 */
imul %r8,%rdx /* (c) copied to all bytes */
test $7,%dil
jnz 20f /* jump if misaligned */
_ALIGN_TEXT /* one byte nop */
1:
movq (%rdi),%rax /* bytes to check (x) */
2:
addq $8,%rdi
mov %rax,%r10
mov %rax,%r11 /* for 'char' check */
not %r10 /* invert of data (~x) */
xorq %rdx,%r11 /* convert 'char' test to one for NUL */
subq %r8,%rax /* x - 0x10 */
movq %r10,%rsi /* ~x */
subq %r8,%r11 /* (x ^ c) - 0x10 */
/*
* Here we could check ((x - 0x10) | ((x ^ c) - 0x10)) & 0x80
* and short-circuit the case where no top bits are set, and
* we continue the loop.
* However it needs 3 more clocks that are difficult to interleave
* in the existing dependency chain ...
*/
andq %r9,%rax /* (x - 0x10) & 0x80 */
xorq %rdx,%rsi /* c ^ ~x == ~(c ^ x) */
andq %r9,%r11 /* ((x ^ c) - 0x10) & 0x80 */
andq %r10,%rax /* (x - 0x10) & 0x80 & ~x */
jne 10f /* jump if string ends */
andq %rsi,%r11 /* ((x ^ c) - 0x10) & 0x80 & ~(x ^ c) */
je 1b /* jump if no match */
/* Found char, since LE can use bit scan */
bsf %r11,%r11 /* 7, 15, 23 ... 63 */
8: shr $3,%r11 /* 0, 1, 2 .. 7 */
lea -8(%r11,%rdi),%rax
jmp 12f
/* End of string, check whether char is before NUL */
_ALIGN_TEXT /* adds three byte nop */
10:
bsf %rax,%rax /* count to NUL */
andq %rsi,%r11 /* check for char in last 8 bytes */
je 11f
bsf %r11,%r11 /* NUL and char - see which was first */
cmp %r11,%rax
jae 8b /* return 'found' if same - searching for NUL */
11: xor %eax,%eax /* char not found */
12: RETGUARD_POP(r11)
RETGUARD_CHECK(_strchr, r11)
ret
/* Source misaligned: read aligned word and make low bytes invalid */
/* I (dsl) think a _ALIGN_TEXT here will slow things down! */
20:
xor %rcx,%rcx
sub %dil,%cl /* Convert low address values 1..7 ... */
sbb %rsi,%rsi /* carry was set, so %rsi now ~0u! */
and $7,%cl /* ... to 7..1 */
and $~7,%dil /* move address to start of word */
shl $3,%cl /* now 56, 48 ... 16, 8 */
movq (%rdi),%rax /* aligned word containing first data */
xor %rdx,%rsi /* invert of search pattern (~c) */
je 22f /* searching for 0xff */
21: shr %cl,%rsi /* ~c in low bytes */
or %rsi,%rax /* set some bits making low bytes invalid */
jmp 2b
/* We are searching for 0xff, so can't use ~pattern for invalid value */
22:
mov %r8,%r10 /* 0x01 pattern */
lea (%r8,%r8),%rsi /* 0x02 - bits gets set (above) */
not %r10 /* now 0xfe */
sar %cl,%r10 /* top bytes 0xff */
and %r10,%rax /* clear lsb from unwanted low bytes */
jmp 21b
END_STRONG(_strchr)
|
GeminiCarrie/rust-sgx-sdk | 1,024 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/memset.S | /*
* Written by J.T. Conklin <jtc@netbsd.org>.
* Public domain.
* Adapted for NetBSD/x86_64 by Frank van der Linden <fvdl@wasabisystems.com>
*/
#include "DEFS.h"
ENTRY(__memset)
RETGUARD_SETUP(__memset, r10)
movq %rsi,%rax
andq $0xff,%rax
movq %rdx,%rcx
movq %rdi,%r11
cld /* set fill direction forward */
/*
* if the string is too short, it's really not worth the overhead
* of aligning to word boundaries, etc. So we jump to a plain
* unaligned set.
*/
cmpq $0x0f,%rcx
jle L1
movb %al,%ah /* copy char to all bytes in word */
movl %eax,%edx
sall $16,%eax
orl %edx,%eax
movl %eax,%edx
salq $32,%rax
orq %rdx,%rax
movq %rdi,%rdx /* compute misalignment */
negq %rdx
andq $7,%rdx
movq %rcx,%r8
subq %rdx,%r8
movq %rdx,%rcx /* set until word aligned */
rep
stosb
movq %r8,%rcx
shrq $3,%rcx /* set by words */
rep
stosq
movq %r8,%rcx /* set remainder by bytes */
andq $7,%rcx
L1: rep
stosb
movq %r11,%rax
RETGUARD_CHECK(memset, r10)
ret
END_BUILTIN(__memset)
|
GeminiCarrie/rust-sgx-sdk | 374 | sgx_libc/sgx_tlibc_sys/tlibc/string/asm/bcmp.S | #include "DEFS.h"
ENTRY(_bcmp)
RETGUARD_SETUP(_bcmp, r11)
xorl %eax,%eax /* clear return value */
cld /* set compare direction forward */
movq %rdx,%rcx /* compare by words */
shrq $3,%rcx
repe
cmpsq
jne L1
movq %rdx,%rcx /* compare remainder by bytes */
andq $7,%rcx
repe
cmpsb
je L2
L1: incl %eax
L2: RETGUARD_CHECK(_bcmp, r11)
ret
END_WEAK(_bcmp)
|
GeminiCarrie/rust-sgx-sdk | 2,830 | sgx_unwind/libunwind/src/x86_64/setcontext.S | /* libunwind - a platform-independent unwind library
Copyright (C) 2007 Google, Inc
Contributed by Arun Sharma <arun.sharma@google.com>
Copyright (C) 2010 Konstantin Belousov <kib@freebsd.org>
This file is part of libunwind.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include "ucontext_i.h"
/* int _Ux86_64_setcontext (const ucontext_t *ucp)
Restores the machine context provided.
Unlike the libc implementation, doesn't clobber %rax
*/
.global _Ux86_64_setcontext
.type _Ux86_64_setcontext, @function
_Ux86_64_setcontext:
#if defined __linux__
/* restore fp state */
mov UC_MCONTEXT_FPREGS_PTR(%rdi),%r8
fldenv (%r8)
ldmxcsr FPREGS_OFFSET_MXCSR(%r8)
#elif defined __FreeBSD__
/* restore fp state */
cmpq $UC_MCONTEXT_FPOWNED_FPU,UC_MCONTEXT_OWNEDFP(%rdi)
jne 1f
cmpq $UC_MCONTEXT_FPFMT_XMM,UC_MCONTEXT_FPFORMAT(%rdi)
jne 1f
fxrstor UC_MCONTEXT_FPSTATE(%rdi)
1:
#else
#error Port me
#endif
/* restore the rest of the state */
mov UC_MCONTEXT_GREGS_R8(%rdi),%r8
mov UC_MCONTEXT_GREGS_R9(%rdi),%r9
mov UC_MCONTEXT_GREGS_RBX(%rdi),%rbx
mov UC_MCONTEXT_GREGS_RBP(%rdi),%rbp
mov UC_MCONTEXT_GREGS_R12(%rdi),%r12
mov UC_MCONTEXT_GREGS_R13(%rdi),%r13
mov UC_MCONTEXT_GREGS_R14(%rdi),%r14
mov UC_MCONTEXT_GREGS_R15(%rdi),%r15
mov UC_MCONTEXT_GREGS_RSI(%rdi),%rsi
mov UC_MCONTEXT_GREGS_RDX(%rdi),%rdx
mov UC_MCONTEXT_GREGS_RAX(%rdi),%rax
mov UC_MCONTEXT_GREGS_RCX(%rdi),%rcx
mov UC_MCONTEXT_GREGS_RSP(%rdi),%rsp
/* push the return address on the stack */
mov UC_MCONTEXT_GREGS_RIP(%rdi),%rcx
push %rcx
mov UC_MCONTEXT_GREGS_RCX(%rdi),%rcx
mov UC_MCONTEXT_GREGS_RDI(%rdi),%rdi
retq
.size _Ux86_64_setcontext, . - _Ux86_64_setcontext
/* We do not need executable stack. */
.section .note.GNU-stack,"",@progbits
|
GeminiCarrie/rust-sgx-sdk | 1,438 | sgx_unwind/libunwind/src/x86_64/siglongjmp.S | /* libunwind - a platform-independent unwind library
Copyright (C) 2004 Hewlett-Packard Co
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of libunwind.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
.globl _UI_siglongjmp_cont
.type _UI_siglongjmp_cont, @function
_UI_siglongjmp_cont:
retq
.size _UI_siglongjmp_cont, . - _UI_siglongjmp_cont
/* We do not need executable stack. */
.section .note.GNU-stack,"",@progbits
|
GeminiCarrie/rust-sgx-sdk | 4,427 | sgx_unwind/libunwind/src/x86_64/getcontext.S | /* libunwind - a platform-independent unwind library
Copyright (C) 2008 Google, Inc
Contributed by Paul Pluzhnikov <ppluzhnikov@google.com>
Copyright (C) 2010 Konstantin Belousov <kib@freebsd.org>
This file is part of libunwind.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include "ucontext_i.h"
/* int _Ux86_64_getcontext (ucontext_t *ucp)
Saves the machine context in UCP necessary for libunwind.
Unlike the libc implementation, we don't save the signal mask
and hence avoid the cost of a system call per unwind.
*/
.global _Ux86_64_getcontext
.type _Ux86_64_getcontext, @function
_Ux86_64_getcontext:
.cfi_startproc
/* Callee saved: RBX, RBP, R12-R15 */
movq %r12, UC_MCONTEXT_GREGS_R12(%rdi)
movq %r13, UC_MCONTEXT_GREGS_R13(%rdi)
movq %r14, UC_MCONTEXT_GREGS_R14(%rdi)
movq %r15, UC_MCONTEXT_GREGS_R15(%rdi)
movq %rbp, UC_MCONTEXT_GREGS_RBP(%rdi)
movq %rbx, UC_MCONTEXT_GREGS_RBX(%rdi)
/* Save argument registers (not strictly needed, but setcontext
restores them, so don't restore garbage). */
movq %r8, UC_MCONTEXT_GREGS_R8(%rdi)
movq %r9, UC_MCONTEXT_GREGS_R9(%rdi)
movq %rdi, UC_MCONTEXT_GREGS_RDI(%rdi)
movq %rsi, UC_MCONTEXT_GREGS_RSI(%rdi)
movq %rdx, UC_MCONTEXT_GREGS_RDX(%rdi)
movq %rax, UC_MCONTEXT_GREGS_RAX(%rdi)
movq %rcx, UC_MCONTEXT_GREGS_RCX(%rdi)
#if defined __linux__
/* Save fp state (not needed, except for setcontext not
restoring garbage). */
leaq UC_MCONTEXT_FPREGS_MEM(%rdi),%r8
movq %r8, UC_MCONTEXT_FPREGS_PTR(%rdi)
fnstenv (%r8)
stmxcsr FPREGS_OFFSET_MXCSR(%r8)
#elif defined __FreeBSD__
fxsave UC_MCONTEXT_FPSTATE(%rdi)
movq $UC_MCONTEXT_FPOWNED_FPU,UC_MCONTEXT_OWNEDFP(%rdi)
movq $UC_MCONTEXT_FPFMT_XMM,UC_MCONTEXT_FPFORMAT(%rdi)
/* Save rflags and segment registers, so that sigreturn(2)
does not complain. */
pushfq
.cfi_adjust_cfa_offset 8
popq UC_MCONTEXT_RFLAGS(%rdi)
.cfi_adjust_cfa_offset -8
movl $0, UC_MCONTEXT_FLAGS(%rdi)
movw %cs, UC_MCONTEXT_CS(%rdi)
movw %ss, UC_MCONTEXT_SS(%rdi)
#if 0
/* Setting the flags to 0 above disables restore of segment
registers from the context */
movw %ds, UC_MCONTEXT_DS(%rdi)
movw %es, UC_MCONTEXT_ES(%rdi)
movw %fs, UC_MCONTEXT_FS(%rdi)
movw %gs, UC_MCONTEXT_GS(%rdi)
#endif
movq $UC_MCONTEXT_MC_LEN_VAL, UC_MCONTEXT_MC_LEN(%rdi)
#else
#error Port me
#endif
leaq 8(%rsp), %rax /* exclude this call. */
movq %rax, UC_MCONTEXT_GREGS_RSP(%rdi)
movq 0(%rsp), %rax
movq %rax, UC_MCONTEXT_GREGS_RIP(%rdi)
xorq %rax, %rax
retq
.cfi_endproc
.size _Ux86_64_getcontext, . - _Ux86_64_getcontext
/* int _Ux86_64_getcontext_trace (ucontext_t *ucp)
Saves limited machine context in UCP necessary for libunwind.
Unlike _Ux86_64_getcontext, saves only the parts needed for
fast trace. If fast trace fails, caller will have to get the
full context.
*/
.global _Ux86_64_getcontext_trace
.hidden _Ux86_64_getcontext_trace
.type _Ux86_64_getcontext_trace, @function
_Ux86_64_getcontext_trace:
.cfi_startproc
/* Save only RBP, RBX, RSP, RIP - exclude this call. */
movq %rbp, UC_MCONTEXT_GREGS_RBP(%rdi)
movq %rbx, UC_MCONTEXT_GREGS_RBX(%rdi)
leaq 8(%rsp), %rax
movq %rax, UC_MCONTEXT_GREGS_RSP(%rdi)
movq 0(%rsp), %rax
movq %rax, UC_MCONTEXT_GREGS_RIP(%rdi)
xorq %rax, %rax
retq
.cfi_endproc
.size _Ux86_64_getcontext_trace, . - _Ux86_64_getcontext_trace
/* We do not need executable stack. */
.section .note.GNU-stack,"",@progbits
|
GeminiCarrie/rust-sgx-sdk | 1,520 | sgx_unwind/libunwind/src/x86_64/longjmp.S | /* libunwind - a platform-independent unwind library
Copyright (C) 2004-2005 Hewlett-Packard Co
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of libunwind.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
.globl _UI_longjmp_cont
.type _UI_longjmp_cont, @function
_UI_longjmp_cont:
push %rax /* push target IP as return address */
mov %rdx, %rax /* set up return-value */
retq
.size _UI_longjmp_cont, .-_UI_longjmp_cont
/* We do not need executable stack. */
.section .note.GNU-stack,"",@progbits
|
GeminiCarrie/crate-sgx-ex | 15,839 | libz-sys-sgx/src/zlib/contrib/gcc_gvmat64/gvmat64.S | /*
;uInt longest_match_x64(
; deflate_state *s,
; IPos cur_match); // current match
; gvmat64.S -- Asm portion of the optimized longest_match for 32 bits x86_64
; (AMD64 on Athlon 64, Opteron, Phenom
; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
; this file is translation from gvmat64.asm to GCC 4.x (for Linux, Mac XCode)
; Copyright (C) 1995-2010 Jean-loup Gailly, Brian Raiter and Gilles Vollant.
;
; File written by Gilles Vollant, by converting to assembly the longest_match
; from Jean-loup Gailly in deflate.c of zLib and infoZip zip.
; and by taking inspiration on asm686 with masm, optimised assembly code
; from Brian Raiter, written 1998
;
; This software is provided 'as-is', without any express or implied
; warranty. In no event will the authors be held liable for any damages
; arising from the use of this software.
;
; Permission is granted to anyone to use this software for any purpose,
; including commercial applications, and to alter it and redistribute it
; freely, subject to the following restrictions:
;
; 1. The origin of this software must not be misrepresented; you must not
; claim that you wrote the original software. If you use this software
; in a product, an acknowledgment in the product documentation would be
; appreciated but is not required.
; 2. Altered source versions must be plainly marked as such, and must not be
; misrepresented as being the original software
; 3. This notice may not be removed or altered from any source distribution.
;
; http://www.zlib.net
; http://www.winimage.com/zLibDll
; http://www.muppetlabs.com/~breadbox/software/assembly.html
;
; to compile this file for zLib, I use option:
; gcc -c -arch x86_64 gvmat64.S
;uInt longest_match(s, cur_match)
; deflate_state *s;
; IPos cur_match; // current match /
;
; with XCode for Mac, I had strange error with some jump on intel syntax
; this is why BEFORE_JMP and AFTER_JMP are used
*/
#define BEFORE_JMP .att_syntax
#define AFTER_JMP .intel_syntax noprefix
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
.intel_syntax noprefix
.globl match_init, longest_match
.text
longest_match:
#define LocalVarsSize 96
/*
; register used : rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12
; free register : r14,r15
; register can be saved : rsp
*/
#define chainlenwmask (rsp + 8 - LocalVarsSize)
#define nicematch (rsp + 16 - LocalVarsSize)
#define save_rdi (rsp + 24 - LocalVarsSize)
#define save_rsi (rsp + 32 - LocalVarsSize)
#define save_rbx (rsp + 40 - LocalVarsSize)
#define save_rbp (rsp + 48 - LocalVarsSize)
#define save_r12 (rsp + 56 - LocalVarsSize)
#define save_r13 (rsp + 64 - LocalVarsSize)
#define save_r14 (rsp + 72 - LocalVarsSize)
#define save_r15 (rsp + 80 - LocalVarsSize)
/*
; all the +4 offsets are due to the addition of pending_buf_size (in zlib
; in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, remove the +4).
; Note : these value are good with a 8 bytes boundary pack structure
*/
#define MAX_MATCH 258
#define MIN_MATCH 3
#define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1)
/*
;;; Offsets for fields in the deflate_state structure. These numbers
;;; are calculated from the definition of deflate_state, with the
;;; assumption that the compiler will dword-align the fields. (Thus,
;;; changing the definition of deflate_state could easily cause this
;;; program to crash horribly, without so much as a warning at
;;; compile time. Sigh.)
; all the +zlib1222add offsets are due to the addition of fields
; in zlib in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
; (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
; if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize %u\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask %u\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow %u\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev %u\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen %u\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch %u\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart %u\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart %u\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead %u\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen %u\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen %u\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch %u\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch %u\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
#define dsWSize 68
#define dsWMask 76
#define dsWindow 80
#define dsPrev 96
#define dsMatchLen 144
#define dsPrevMatch 148
#define dsStrStart 156
#define dsMatchStart 160
#define dsLookahead 164
#define dsPrevLen 168
#define dsMaxChainLen 172
#define dsGoodMatch 188
#define dsNiceMatch 192
#define window_size [ rcx + dsWSize]
#define WMask [ rcx + dsWMask]
#define window_ad [ rcx + dsWindow]
#define prev_ad [ rcx + dsPrev]
#define strstart [ rcx + dsStrStart]
#define match_start [ rcx + dsMatchStart]
#define Lookahead [ rcx + dsLookahead] //; 0ffffffffh on infozip
#define prev_length [ rcx + dsPrevLen]
#define max_chain_length [ rcx + dsMaxChainLen]
#define good_match [ rcx + dsGoodMatch]
#define nice_match [ rcx + dsNiceMatch]
/*
; windows:
; parameter 1 in rcx(deflate state s), param 2 in rdx (cur match)
; see http://weblogs.asp.net/oldnewthing/archive/2004/01/14/58579.aspx and
; http://msdn.microsoft.com/library/en-us/kmarch/hh/kmarch/64bitAMD_8e951dd2-ee77-4728-8702-55ce4b5dd24a.xml.asp
;
; All registers must be preserved across the call, except for
; rax, rcx, rdx, r8, r9, r10, and r11, which are scratch.
;
; gcc on macosx-linux:
; see http://www.x86-64.org/documentation/abi-0.99.pdf
; param 1 in rdi, param 2 in rsi
; rbx, rsp, rbp, r12 to r15 must be preserved
;;; Save registers that the compiler may be using, and adjust esp to
;;; make room for our stack frame.
;;; Retrieve the function arguments. r8d will hold cur_match
;;; throughout the entire function. edx will hold the pointer to the
;;; deflate_state structure during the function's setup (before
;;; entering the main loop.
; ms: parameter 1 in rcx (deflate_state* s), param 2 in edx -> r8 (cur match)
; mac: param 1 in rdi, param 2 rsi
; this clear high 32 bits of r8, which can be garbage in both r8 and rdx
*/
mov [save_rbx],rbx
mov [save_rbp],rbp
mov rcx,rdi
mov r8d,esi
mov [save_r12],r12
mov [save_r13],r13
mov [save_r14],r14
mov [save_r15],r15
//;;; uInt wmask = s->w_mask;
//;;; unsigned chain_length = s->max_chain_length;
//;;; if (s->prev_length >= s->good_match) {
//;;; chain_length >>= 2;
//;;; }
mov edi, prev_length
mov esi, good_match
mov eax, WMask
mov ebx, max_chain_length
cmp edi, esi
jl LastMatchGood
shr ebx, 2
LastMatchGood:
//;;; chainlen is decremented once beforehand so that the function can
//;;; use the sign flag instead of the zero flag for the exit test.
//;;; It is then shifted into the high word, to make room for the wmask
//;;; value, which it will always accompany.
dec ebx
shl ebx, 16
or ebx, eax
//;;; on zlib only
//;;; if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead;
mov eax, nice_match
mov [chainlenwmask], ebx
mov r10d, Lookahead
cmp r10d, eax
cmovnl r10d, eax
mov [nicematch],r10d
//;;; register Bytef *scan = s->window + s->strstart;
mov r10, window_ad
mov ebp, strstart
lea r13, [r10 + rbp]
//;;; Determine how many bytes the scan ptr is off from being
//;;; dword-aligned.
mov r9,r13
neg r13
and r13,3
//;;; IPos limit = s->strstart > (IPos)MAX_DIST(s) ?
//;;; s->strstart - (IPos)MAX_DIST(s) : NIL;
mov eax, window_size
sub eax, MIN_LOOKAHEAD
xor edi,edi
sub ebp, eax
mov r11d, prev_length
cmovng ebp,edi
//;;; int best_len = s->prev_length;
//;;; Store the sum of s->window + best_len in esi locally, and in esi.
lea rsi,[r10+r11]
//;;; register ush scan_start = *(ushf*)scan;
//;;; register ush scan_end = *(ushf*)(scan+best_len-1);
//;;; Posf *prev = s->prev;
movzx r12d,word ptr [r9]
movzx ebx, word ptr [r9 + r11 - 1]
mov rdi, prev_ad
//;;; Jump into the main loop.
mov edx, [chainlenwmask]
cmp bx,word ptr [rsi + r8 - 1]
jz LookupLoopIsZero
LookupLoop1:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
jbe LeaveNow
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry1:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop2:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry2:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop4:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry4:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
jmp LookupLoopIsZero
AFTER_JMP
/*
;;; do {
;;; match = s->window + cur_match;
;;; if (*(ushf*)(match+best_len-1) != scan_end ||
;;; *(ushf*)match != scan_start) continue;
;;; [...]
;;; } while ((cur_match = prev[cur_match & wmask]) > limit
;;; && --chain_length != 0);
;;;
;;; Here is the inner loop of the function. The function will spend the
;;; majority of its time in this loop, and majority of that time will
;;; be spent in the first ten instructions.
;;;
;;; Within this loop:
;;; ebx = scanend
;;; r8d = curmatch
;;; edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
;;; esi = windowbestlen - i.e., (window + bestlen)
;;; edi = prev
;;; ebp = limit
*/
.balign 16
LookupLoop:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
LookupLoopIsZero:
cmp r12w, word ptr [r10 + r8]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
//;;; Store the current value of chainlen.
mov [chainlenwmask], edx
/*
;;; Point edi to the string under scrutiny, and esi to the string we
;;; are hoping to match it up with. In actuality, esi and edi are
;;; both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and edx is
;;; initialized to -(MAX_MATCH_8 - scanalign).
*/
lea rsi,[r8+r10]
mov rdx, 0xfffffffffffffef8 //; -(MAX_MATCH_8)
lea rsi, [rsi + r13 + 0x0108] //;MAX_MATCH_8]
lea rdi, [r9 + r13 + 0x0108] //;MAX_MATCH_8]
prefetcht1 [rsi+rdx]
prefetcht1 [rdi+rdx]
/*
;;; Test the strings for equality, 8 bytes at a time. At the end,
;;; adjust rdx so that it is offset to the exact byte that mismatched.
;;;
;;; We already know at this point that the first three bytes of the
;;; strings match each other, and they can be safely passed over before
;;; starting the compare loop. So what this code does is skip over 0-3
;;; bytes, as much as necessary in order to dword-align the edi
;;; pointer. (rsi will still be misaligned three times out of four.)
;;;
;;; It should be confessed that this loop usually does not represent
;;; much of the total running time. Replacing it with a more
;;; straightforward "rep cmpsb" would not drastically degrade
;;; performance.
*/
LoopCmps:
mov rax, [rsi + rdx]
xor rax, [rdi + rdx]
jnz LeaveLoopCmps
mov rax, [rsi + rdx + 8]
xor rax, [rdi + rdx + 8]
jnz LeaveLoopCmps8
mov rax, [rsi + rdx + 8+8]
xor rax, [rdi + rdx + 8+8]
jnz LeaveLoopCmps16
add rdx,8+8+8
BEFORE_JMP
jnz LoopCmps
jmp LenMaximum
AFTER_JMP
LeaveLoopCmps16: add rdx,8
LeaveLoopCmps8: add rdx,8
LeaveLoopCmps:
test eax, 0x0000FFFF
jnz LenLower
test eax,0xffffffff
jnz LenLower32
add rdx,4
shr rax,32
or ax,ax
BEFORE_JMP
jnz LenLower
AFTER_JMP
LenLower32:
shr eax,16
add rdx,2
LenLower:
sub al, 1
adc rdx, 0
//;;; Calculate the length of the match. If it is longer than MAX_MATCH,
//;;; then automatically accept it as the best possible match and leave.
lea rax, [rdi + rdx]
sub rax, r9
cmp eax, MAX_MATCH
BEFORE_JMP
jge LenMaximum
AFTER_JMP
/*
;;; If the length of the match is not longer than the best match we
;;; have so far, then forget it and return to the lookup loop.
;///////////////////////////////////
*/
cmp eax, r11d
jg LongerMatch
lea rsi,[r10+r11]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
/*
;;; s->match_start = cur_match;
;;; best_len = len;
;;; if (len >= nice_match) break;
;;; scan_end = *(ushf*)(scan+best_len-1);
*/
LongerMatch:
mov r11d, eax
mov match_start, r8d
cmp eax, [nicematch]
BEFORE_JMP
jge LeaveNow
AFTER_JMP
lea rsi,[r10+rax]
movzx ebx, word ptr [r9 + rax - 1]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
//;;; Accept the current string, with the maximum possible length.
LenMaximum:
mov r11d,MAX_MATCH
mov match_start, r8d
//;;; if ((uInt)best_len <= s->lookahead) return (uInt)best_len;
//;;; return s->lookahead;
LeaveNow:
mov eax, Lookahead
cmp r11d, eax
cmovng eax, r11d
//;;; Restore the stack and return from whence we came.
// mov rsi,[save_rsi]
// mov rdi,[save_rdi]
mov rbx,[save_rbx]
mov rbp,[save_rbp]
mov r12,[save_r12]
mov r13,[save_r13]
mov r14,[save_r14]
mov r15,[save_r15]
ret 0
//; please don't remove this string !
//; Your can freely use gvmat64 in any free or commercial app
//; but it is far better don't remove the string in the binary!
// db 0dh,0ah,"asm686 with masm, optimised assembly code from Brian Raiter, written 1998, converted to amd 64 by Gilles Vollant 2005",0dh,0ah,0
match_init:
ret 0
|
GeminiCarrie/crate-sgx-ex | 12,418 | libz-sys-sgx/src/zlib/contrib/amd64/amd64-match.S | /*
* match.S -- optimized version of longest_match()
* based on the similar work by Gilles Vollant, and Brian Raiter, written 1998
*
* This is free software; you can redistribute it and/or modify it
* under the terms of the BSD License. Use by owners of Che Guevarra
* parafernalia is prohibited, where possible, and highly discouraged
* elsewhere.
*/
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
#define scanend ebx
#define scanendw bx
#define chainlenwmask edx /* high word: current chain len low word: s->wmask */
#define curmatch rsi
#define curmatchd esi
#define windowbestlen r8
#define scanalign r9
#define scanalignd r9d
#define window r10
#define bestlen r11
#define bestlend r11d
#define scanstart r12d
#define scanstartw r12w
#define scan r13
#define nicematch r14d
#define limit r15
#define limitd r15d
#define prev rcx
/*
* The 258 is a "magic number, not a parameter -- changing it
* breaks the hell loose
*/
#define MAX_MATCH (258)
#define MIN_MATCH (3)
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7)
/* stack frame offsets */
#define LocalVarsSize (112)
#define _chainlenwmask ( 8-LocalVarsSize)(%rsp)
#define _windowbestlen (16-LocalVarsSize)(%rsp)
#define save_r14 (24-LocalVarsSize)(%rsp)
#define save_rsi (32-LocalVarsSize)(%rsp)
#define save_rbx (40-LocalVarsSize)(%rsp)
#define save_r12 (56-LocalVarsSize)(%rsp)
#define save_r13 (64-LocalVarsSize)(%rsp)
#define save_r15 (80-LocalVarsSize)(%rsp)
.globl match_init, longest_match
/*
* On AMD64 the first argument of a function (in our case -- the pointer to
* deflate_state structure) is passed in %rdi, hence our offsets below are
* all off of that.
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize (%3u)(%%rdi)\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask (%3u)(%%rdi)\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow (%3u)(%%rdi)\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev (%3u)(%%rdi)\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen (%3u)(%%rdi)\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart (%3u)(%%rdi)\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart (%3u)(%%rdi)\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead (%3u)(%%rdi)\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen (%3u)(%%rdi)\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
/*
to compile for XCode 3.2 on MacOSX x86_64
- run "gcc -g -c -DXCODE_MAC_X64_STRUCTURE amd64-match.S"
*/
#ifndef CURRENT_LINX_XCODE_MAC_X64_STRUCTURE
#define dsWSize ( 68)(%rdi)
#define dsWMask ( 76)(%rdi)
#define dsWindow ( 80)(%rdi)
#define dsPrev ( 96)(%rdi)
#define dsMatchLen (144)(%rdi)
#define dsPrevMatch (148)(%rdi)
#define dsStrStart (156)(%rdi)
#define dsMatchStart (160)(%rdi)
#define dsLookahead (164)(%rdi)
#define dsPrevLen (168)(%rdi)
#define dsMaxChainLen (172)(%rdi)
#define dsGoodMatch (188)(%rdi)
#define dsNiceMatch (192)(%rdi)
#else
#ifndef STRUCT_OFFSET
# define STRUCT_OFFSET (0)
#endif
#define dsWSize ( 56 + STRUCT_OFFSET)(%rdi)
#define dsWMask ( 64 + STRUCT_OFFSET)(%rdi)
#define dsWindow ( 72 + STRUCT_OFFSET)(%rdi)
#define dsPrev ( 88 + STRUCT_OFFSET)(%rdi)
#define dsMatchLen (136 + STRUCT_OFFSET)(%rdi)
#define dsPrevMatch (140 + STRUCT_OFFSET)(%rdi)
#define dsStrStart (148 + STRUCT_OFFSET)(%rdi)
#define dsMatchStart (152 + STRUCT_OFFSET)(%rdi)
#define dsLookahead (156 + STRUCT_OFFSET)(%rdi)
#define dsPrevLen (160 + STRUCT_OFFSET)(%rdi)
#define dsMaxChainLen (164 + STRUCT_OFFSET)(%rdi)
#define dsGoodMatch (180 + STRUCT_OFFSET)(%rdi)
#define dsNiceMatch (184 + STRUCT_OFFSET)(%rdi)
#endif
.text
/* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */
longest_match:
/*
* Retrieve the function arguments. %curmatch will hold cur_match
* throughout the entire function (passed via rsi on amd64).
* rdi will hold the pointer to the deflate_state (first arg on amd64)
*/
mov %rsi, save_rsi
mov %rbx, save_rbx
mov %r12, save_r12
mov %r13, save_r13
mov %r14, save_r14
mov %r15, save_r15
/* uInt wmask = s->w_mask; */
/* unsigned chain_length = s->max_chain_length; */
/* if (s->prev_length >= s->good_match) { */
/* chain_length >>= 2; */
/* } */
movl dsPrevLen, %eax
movl dsGoodMatch, %ebx
cmpl %ebx, %eax
movl dsWMask, %eax
movl dsMaxChainLen, %chainlenwmask
jl LastMatchGood
shrl $2, %chainlenwmask
LastMatchGood:
/* chainlen is decremented once beforehand so that the function can */
/* use the sign flag instead of the zero flag for the exit test. */
/* It is then shifted into the high word, to make room for the wmask */
/* value, which it will always accompany. */
decl %chainlenwmask
shll $16, %chainlenwmask
orl %eax, %chainlenwmask
/* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */
movl dsNiceMatch, %eax
movl dsLookahead, %ebx
cmpl %eax, %ebx
jl LookaheadLess
movl %eax, %ebx
LookaheadLess: movl %ebx, %nicematch
/* register Bytef *scan = s->window + s->strstart; */
mov dsWindow, %window
movl dsStrStart, %limitd
lea (%limit, %window), %scan
/* Determine how many bytes the scan ptr is off from being */
/* dword-aligned. */
mov %scan, %scanalign
negl %scanalignd
andl $3, %scanalignd
/* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */
/* s->strstart - (IPos)MAX_DIST(s) : NIL; */
movl dsWSize, %eax
subl $MIN_LOOKAHEAD, %eax
xorl %ecx, %ecx
subl %eax, %limitd
cmovng %ecx, %limitd
/* int best_len = s->prev_length; */
movl dsPrevLen, %bestlend
/* Store the sum of s->window + best_len in %windowbestlen locally, and in memory. */
lea (%window, %bestlen), %windowbestlen
mov %windowbestlen, _windowbestlen
/* register ush scan_start = *(ushf*)scan; */
/* register ush scan_end = *(ushf*)(scan+best_len-1); */
/* Posf *prev = s->prev; */
movzwl (%scan), %scanstart
movzwl -1(%scan, %bestlen), %scanend
mov dsPrev, %prev
/* Jump into the main loop. */
movl %chainlenwmask, _chainlenwmask
jmp LoopEntry
.balign 16
/* do {
* match = s->window + cur_match;
* if (*(ushf*)(match+best_len-1) != scan_end ||
* *(ushf*)match != scan_start) continue;
* [...]
* } while ((cur_match = prev[cur_match & wmask]) > limit
* && --chain_length != 0);
*
* Here is the inner loop of the function. The function will spend the
* majority of its time in this loop, and majority of that time will
* be spent in the first ten instructions.
*/
LookupLoop:
andl %chainlenwmask, %curmatchd
movzwl (%prev, %curmatch, 2), %curmatchd
cmpl %limitd, %curmatchd
jbe LeaveNow
subl $0x00010000, %chainlenwmask
js LeaveNow
LoopEntry: cmpw -1(%windowbestlen, %curmatch), %scanendw
jne LookupLoop
cmpw %scanstartw, (%window, %curmatch)
jne LookupLoop
/* Store the current value of chainlen. */
movl %chainlenwmask, _chainlenwmask
/* %scan is the string under scrutiny, and %prev to the string we */
/* are hoping to match it up with. In actuality, %esi and %edi are */
/* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */
/* initialized to -(MAX_MATCH_8 - scanalign). */
mov $(-MAX_MATCH_8), %rdx
lea (%curmatch, %window), %windowbestlen
lea MAX_MATCH_8(%windowbestlen, %scanalign), %windowbestlen
lea MAX_MATCH_8(%scan, %scanalign), %prev
/* the prefetching below makes very little difference... */
prefetcht1 (%windowbestlen, %rdx)
prefetcht1 (%prev, %rdx)
/*
* Test the strings for equality, 8 bytes at a time. At the end,
* adjust %rdx so that it is offset to the exact byte that mismatched.
*
* It should be confessed that this loop usually does not represent
* much of the total running time. Replacing it with a more
* straightforward "rep cmpsb" would not drastically degrade
* performance -- unrolling it, for example, makes no difference.
*/
#undef USE_SSE /* works, but is 6-7% slower, than non-SSE... */
LoopCmps:
#ifdef USE_SSE
/* Preload the SSE registers */
movdqu (%windowbestlen, %rdx), %xmm1
movdqu (%prev, %rdx), %xmm2
pcmpeqb %xmm2, %xmm1
movdqu 16(%windowbestlen, %rdx), %xmm3
movdqu 16(%prev, %rdx), %xmm4
pcmpeqb %xmm4, %xmm3
movdqu 32(%windowbestlen, %rdx), %xmm5
movdqu 32(%prev, %rdx), %xmm6
pcmpeqb %xmm6, %xmm5
movdqu 48(%windowbestlen, %rdx), %xmm7
movdqu 48(%prev, %rdx), %xmm8
pcmpeqb %xmm8, %xmm7
/* Check the comparisions' results */
pmovmskb %xmm1, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
/* this is the only iteration of the loop with a possibility of having
incremented rdx by 0x108 (each loop iteration add 16*4 = 0x40
and (0x40*4)+8=0x108 */
add $8, %rdx
jz LenMaximum
add $8, %rdx
pmovmskb %xmm3, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
pmovmskb %xmm5, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
pmovmskb %xmm7, %rax
notw %ax
bsfw %ax, %ax
jnz LeaveLoopCmps
add $16, %rdx
jmp LoopCmps
LeaveLoopCmps: add %rax, %rdx
#else
mov (%windowbestlen, %rdx), %rax
xor (%prev, %rdx), %rax
jnz LeaveLoopCmps
mov 8(%windowbestlen, %rdx), %rax
xor 8(%prev, %rdx), %rax
jnz LeaveLoopCmps8
mov 16(%windowbestlen, %rdx), %rax
xor 16(%prev, %rdx), %rax
jnz LeaveLoopCmps16
add $24, %rdx
jnz LoopCmps
jmp LenMaximum
# if 0
/*
* This three-liner is tantalizingly simple, but bsf is a slow instruction,
* and the complicated alternative down below is quite a bit faster. Sad...
*/
LeaveLoopCmps: bsf %rax, %rax /* find the first non-zero bit */
shrl $3, %eax /* divide by 8 to get the byte */
add %rax, %rdx
# else
LeaveLoopCmps16:
add $8, %rdx
LeaveLoopCmps8:
add $8, %rdx
LeaveLoopCmps: testl $0xFFFFFFFF, %eax /* Check the first 4 bytes */
jnz Check16
add $4, %rdx
shr $32, %rax
Check16: testw $0xFFFF, %ax
jnz LenLower
add $2, %rdx
shrl $16, %eax
LenLower: subb $1, %al
adc $0, %rdx
# endif
#endif
/* Calculate the length of the match. If it is longer than MAX_MATCH, */
/* then automatically accept it as the best possible match and leave. */
lea (%prev, %rdx), %rax
sub %scan, %rax
cmpl $MAX_MATCH, %eax
jge LenMaximum
/* If the length of the match is not longer than the best match we */
/* have so far, then forget it and return to the lookup loop. */
cmpl %bestlend, %eax
jg LongerMatch
mov _windowbestlen, %windowbestlen
mov dsPrev, %prev
movl _chainlenwmask, %edx
jmp LookupLoop
/* s->match_start = cur_match; */
/* best_len = len; */
/* if (len >= nice_match) break; */
/* scan_end = *(ushf*)(scan+best_len-1); */
LongerMatch:
movl %eax, %bestlend
movl %curmatchd, dsMatchStart
cmpl %nicematch, %eax
jge LeaveNow
lea (%window, %bestlen), %windowbestlen
mov %windowbestlen, _windowbestlen
movzwl -1(%scan, %rax), %scanend
mov dsPrev, %prev
movl _chainlenwmask, %chainlenwmask
jmp LookupLoop
/* Accept the current string, with the maximum possible length. */
LenMaximum:
movl $MAX_MATCH, %bestlend
movl %curmatchd, dsMatchStart
/* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */
/* return s->lookahead; */
LeaveNow:
movl dsLookahead, %eax
cmpl %eax, %bestlend
cmovngl %bestlend, %eax
LookaheadRet:
/* Restore the registers and return from whence we came. */
mov save_rsi, %rsi
mov save_rbx, %rbx
mov save_r12, %r12
mov save_r13, %r13
mov save_r14, %r14
mov save_r15, %r15
ret
match_init: ret
|
GeminiCarrie/crate-sgx-ex | 10,365 | libz-sys-sgx/src/zlib/contrib/asm686/match.S | /* match.S -- x86 assembly version of the zlib longest_match() function.
* Optimized for the Intel 686 chips (PPro and later).
*
* Copyright (C) 1998, 2007 Brian Raiter <breadbox@muppetlabs.com>
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the author be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#ifndef NO_UNDERLINE
#define match_init _match_init
#define longest_match _longest_match
#endif
#define MAX_MATCH (258)
#define MIN_MATCH (3)
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7)
/* stack frame offsets */
#define chainlenwmask 0 /* high word: current chain len */
/* low word: s->wmask */
#define window 4 /* local copy of s->window */
#define windowbestlen 8 /* s->window + bestlen */
#define scanstart 16 /* first two bytes of string */
#define scanend 12 /* last two bytes of string */
#define scanalign 20 /* dword-misalignment of string */
#define nicematch 24 /* a good enough match size */
#define bestlen 28 /* size of best match so far */
#define scan 32 /* ptr to string wanting match */
#define LocalVarsSize (36)
/* saved ebx 36 */
/* saved edi 40 */
/* saved esi 44 */
/* saved ebp 48 */
/* return address 52 */
#define deflatestate 56 /* the function arguments */
#define curmatch 60
/* All the +zlib1222add offsets are due to the addition of fields
* in zlib in the deflate_state structure since the asm code was first written
* (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
* (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
* if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
#define zlib1222add (8)
#define dsWSize (36+zlib1222add)
#define dsWMask (44+zlib1222add)
#define dsWindow (48+zlib1222add)
#define dsPrev (56+zlib1222add)
#define dsMatchLen (88+zlib1222add)
#define dsPrevMatch (92+zlib1222add)
#define dsStrStart (100+zlib1222add)
#define dsMatchStart (104+zlib1222add)
#define dsLookahead (108+zlib1222add)
#define dsPrevLen (112+zlib1222add)
#define dsMaxChainLen (116+zlib1222add)
#define dsGoodMatch (132+zlib1222add)
#define dsNiceMatch (136+zlib1222add)
.file "match.S"
.globl match_init, longest_match
.text
/* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */
.cfi_sections .debug_frame
longest_match:
.cfi_startproc
/* Save registers that the compiler may be using, and adjust %esp to */
/* make room for our stack frame. */
pushl %ebp
.cfi_def_cfa_offset 8
.cfi_offset ebp, -8
pushl %edi
.cfi_def_cfa_offset 12
pushl %esi
.cfi_def_cfa_offset 16
pushl %ebx
.cfi_def_cfa_offset 20
subl $LocalVarsSize, %esp
.cfi_def_cfa_offset LocalVarsSize+20
/* Retrieve the function arguments. %ecx will hold cur_match */
/* throughout the entire function. %edx will hold the pointer to the */
/* deflate_state structure during the function's setup (before */
/* entering the main loop). */
movl deflatestate(%esp), %edx
movl curmatch(%esp), %ecx
/* uInt wmask = s->w_mask; */
/* unsigned chain_length = s->max_chain_length; */
/* if (s->prev_length >= s->good_match) { */
/* chain_length >>= 2; */
/* } */
movl dsPrevLen(%edx), %eax
movl dsGoodMatch(%edx), %ebx
cmpl %ebx, %eax
movl dsWMask(%edx), %eax
movl dsMaxChainLen(%edx), %ebx
jl LastMatchGood
shrl $2, %ebx
LastMatchGood:
/* chainlen is decremented once beforehand so that the function can */
/* use the sign flag instead of the zero flag for the exit test. */
/* It is then shifted into the high word, to make room for the wmask */
/* value, which it will always accompany. */
decl %ebx
shll $16, %ebx
orl %eax, %ebx
movl %ebx, chainlenwmask(%esp)
/* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */
movl dsNiceMatch(%edx), %eax
movl dsLookahead(%edx), %ebx
cmpl %eax, %ebx
jl LookaheadLess
movl %eax, %ebx
LookaheadLess: movl %ebx, nicematch(%esp)
/* register Bytef *scan = s->window + s->strstart; */
movl dsWindow(%edx), %esi
movl %esi, window(%esp)
movl dsStrStart(%edx), %ebp
lea (%esi,%ebp), %edi
movl %edi, scan(%esp)
/* Determine how many bytes the scan ptr is off from being */
/* dword-aligned. */
movl %edi, %eax
negl %eax
andl $3, %eax
movl %eax, scanalign(%esp)
/* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */
/* s->strstart - (IPos)MAX_DIST(s) : NIL; */
movl dsWSize(%edx), %eax
subl $MIN_LOOKAHEAD, %eax
subl %eax, %ebp
jg LimitPositive
xorl %ebp, %ebp
LimitPositive:
/* int best_len = s->prev_length; */
movl dsPrevLen(%edx), %eax
movl %eax, bestlen(%esp)
/* Store the sum of s->window + best_len in %esi locally, and in %esi. */
addl %eax, %esi
movl %esi, windowbestlen(%esp)
/* register ush scan_start = *(ushf*)scan; */
/* register ush scan_end = *(ushf*)(scan+best_len-1); */
/* Posf *prev = s->prev; */
movzwl (%edi), %ebx
movl %ebx, scanstart(%esp)
movzwl -1(%edi,%eax), %ebx
movl %ebx, scanend(%esp)
movl dsPrev(%edx), %edi
/* Jump into the main loop. */
movl chainlenwmask(%esp), %edx
jmp LoopEntry
.balign 16
/* do {
* match = s->window + cur_match;
* if (*(ushf*)(match+best_len-1) != scan_end ||
* *(ushf*)match != scan_start) continue;
* [...]
* } while ((cur_match = prev[cur_match & wmask]) > limit
* && --chain_length != 0);
*
* Here is the inner loop of the function. The function will spend the
* majority of its time in this loop, and majority of that time will
* be spent in the first ten instructions.
*
* Within this loop:
* %ebx = scanend
* %ecx = curmatch
* %edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
* %esi = windowbestlen - i.e., (window + bestlen)
* %edi = prev
* %ebp = limit
*/
LookupLoop:
andl %edx, %ecx
movzwl (%edi,%ecx,2), %ecx
cmpl %ebp, %ecx
jbe LeaveNow
subl $0x00010000, %edx
js LeaveNow
LoopEntry: movzwl -1(%esi,%ecx), %eax
cmpl %ebx, %eax
jnz LookupLoop
movl window(%esp), %eax
movzwl (%eax,%ecx), %eax
cmpl scanstart(%esp), %eax
jnz LookupLoop
/* Store the current value of chainlen. */
movl %edx, chainlenwmask(%esp)
/* Point %edi to the string under scrutiny, and %esi to the string we */
/* are hoping to match it up with. In actuality, %esi and %edi are */
/* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */
/* initialized to -(MAX_MATCH_8 - scanalign). */
movl window(%esp), %esi
movl scan(%esp), %edi
addl %ecx, %esi
movl scanalign(%esp), %eax
movl $(-MAX_MATCH_8), %edx
lea MAX_MATCH_8(%edi,%eax), %edi
lea MAX_MATCH_8(%esi,%eax), %esi
/* Test the strings for equality, 8 bytes at a time. At the end,
* adjust %edx so that it is offset to the exact byte that mismatched.
*
* We already know at this point that the first three bytes of the
* strings match each other, and they can be safely passed over before
* starting the compare loop. So what this code does is skip over 0-3
* bytes, as much as necessary in order to dword-align the %edi
* pointer. (%esi will still be misaligned three times out of four.)
*
* It should be confessed that this loop usually does not represent
* much of the total running time. Replacing it with a more
* straightforward "rep cmpsb" would not drastically degrade
* performance.
*/
LoopCmps:
movl (%esi,%edx), %eax
xorl (%edi,%edx), %eax
jnz LeaveLoopCmps
movl 4(%esi,%edx), %eax
xorl 4(%edi,%edx), %eax
jnz LeaveLoopCmps4
addl $8, %edx
jnz LoopCmps
jmp LenMaximum
LeaveLoopCmps4: addl $4, %edx
LeaveLoopCmps: testl $0x0000FFFF, %eax
jnz LenLower
addl $2, %edx
shrl $16, %eax
LenLower: subb $1, %al
adcl $0, %edx
/* Calculate the length of the match. If it is longer than MAX_MATCH, */
/* then automatically accept it as the best possible match and leave. */
lea (%edi,%edx), %eax
movl scan(%esp), %edi
subl %edi, %eax
cmpl $MAX_MATCH, %eax
jge LenMaximum
/* If the length of the match is not longer than the best match we */
/* have so far, then forget it and return to the lookup loop. */
movl deflatestate(%esp), %edx
movl bestlen(%esp), %ebx
cmpl %ebx, %eax
jg LongerMatch
movl windowbestlen(%esp), %esi
movl dsPrev(%edx), %edi
movl scanend(%esp), %ebx
movl chainlenwmask(%esp), %edx
jmp LookupLoop
/* s->match_start = cur_match; */
/* best_len = len; */
/* if (len >= nice_match) break; */
/* scan_end = *(ushf*)(scan+best_len-1); */
LongerMatch: movl nicematch(%esp), %ebx
movl %eax, bestlen(%esp)
movl %ecx, dsMatchStart(%edx)
cmpl %ebx, %eax
jge LeaveNow
movl window(%esp), %esi
addl %eax, %esi
movl %esi, windowbestlen(%esp)
movzwl -1(%edi,%eax), %ebx
movl dsPrev(%edx), %edi
movl %ebx, scanend(%esp)
movl chainlenwmask(%esp), %edx
jmp LookupLoop
/* Accept the current string, with the maximum possible length. */
LenMaximum: movl deflatestate(%esp), %edx
movl $MAX_MATCH, bestlen(%esp)
movl %ecx, dsMatchStart(%edx)
/* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */
/* return s->lookahead; */
LeaveNow:
movl deflatestate(%esp), %edx
movl bestlen(%esp), %ebx
movl dsLookahead(%edx), %eax
cmpl %eax, %ebx
jg LookaheadRet
movl %ebx, %eax
LookaheadRet:
/* Restore the stack and return from whence we came. */
addl $LocalVarsSize, %esp
.cfi_def_cfa_offset 20
popl %ebx
.cfi_def_cfa_offset 16
popl %esi
.cfi_def_cfa_offset 12
popl %edi
.cfi_def_cfa_offset 8
popl %ebp
.cfi_def_cfa_offset 4
.cfi_endproc
match_init: ret
|
GeminiCarrie/crate-sgx-ex | 42,842 | libz-sys-sgx/src/zlib/contrib/inflate86/inffast.S | /*
* inffast.S is a hand tuned assembler version of:
*
* inffast.c -- fast decoding
* Copyright (C) 1995-2003 Mark Adler
* For conditions of distribution and use, see copyright notice in zlib.h
*
* Copyright (C) 2003 Chris Anderson <christop@charm.net>
* Please use the copyright conditions above.
*
* This version (Jan-23-2003) of inflate_fast was coded and tested under
* GNU/Linux on a pentium 3, using the gcc-3.2 compiler distribution. On that
* machine, I found that gzip style archives decompressed about 20% faster than
* the gcc-3.2 -O3 -fomit-frame-pointer compiled version. Your results will
* depend on how large of a buffer is used for z_stream.next_in & next_out
* (8K-32K worked best for my 256K cpu cache) and how much overhead there is in
* stream processing I/O and crc32/addler32. In my case, this routine used
* 70% of the cpu time and crc32 used 20%.
*
* I am confident that this version will work in the general case, but I have
* not tested a wide variety of datasets or a wide variety of platforms.
*
* Jan-24-2003 -- Added -DUSE_MMX define for slightly faster inflating.
* It should be a runtime flag instead of compile time flag...
*
* Jan-26-2003 -- Added runtime check for MMX support with cpuid instruction.
* With -DUSE_MMX, only MMX code is compiled. With -DNO_MMX, only non-MMX code
* is compiled. Without either option, runtime detection is enabled. Runtime
* detection should work on all modern cpus and the recomended algorithm (flip
* ID bit on eflags and then use the cpuid instruction) is used in many
* multimedia applications. Tested under win2k with gcc-2.95 and gas-2.12
* distributed with cygwin3. Compiling with gcc-2.95 -c inffast.S -o
* inffast.obj generates a COFF object which can then be linked with MSVC++
* compiled code. Tested under FreeBSD 4.7 with gcc-2.95.
*
* Jan-28-2003 -- Tested Athlon XP... MMX mode is slower than no MMX (and
* slower than compiler generated code). Adjusted cpuid check to use the MMX
* code only for Pentiums < P4 until I have more data on the P4. Speed
* improvment is only about 15% on the Athlon when compared with code generated
* with MSVC++. Not sure yet, but I think the P4 will also be slower using the
* MMX mode because many of it's x86 ALU instructions execute in .5 cycles and
* have less latency than MMX ops. Added code to buffer the last 11 bytes of
* the input stream since the MMX code grabs bits in chunks of 32, which
* differs from the inffast.c algorithm. I don't think there would have been
* read overruns where a page boundary was crossed (a segfault), but there
* could have been overruns when next_in ends on unaligned memory (unintialized
* memory read).
*
* Mar-13-2003 -- P4 MMX is slightly slower than P4 NO_MMX. I created a C
* version of the non-MMX code so that it doesn't depend on zstrm and zstate
* structure offsets which are hard coded in this file. This was last tested
* with zlib-1.2.0 which is currently in beta testing, newer versions of this
* and inffas86.c can be found at http://www.eetbeetee.com/zlib/ and
* http://www.charm.net/~christop/zlib/
*/
/*
* if you have underscore linking problems (_inflate_fast undefined), try
* using -DGAS_COFF
*/
#if ! defined( GAS_COFF ) && ! defined( GAS_ELF )
#if defined( WIN32 ) || defined( __CYGWIN__ )
#define GAS_COFF /* windows object format */
#else
#define GAS_ELF
#endif
#endif /* ! GAS_COFF && ! GAS_ELF */
#if defined( GAS_COFF )
/* coff externals have underscores */
#define inflate_fast _inflate_fast
#define inflate_fast_use_mmx _inflate_fast_use_mmx
#endif /* GAS_COFF */
.file "inffast.S"
.globl inflate_fast
.text
.align 4,0
.L_invalid_literal_length_code_msg:
.string "invalid literal/length code"
.align 4,0
.L_invalid_distance_code_msg:
.string "invalid distance code"
.align 4,0
.L_invalid_distance_too_far_msg:
.string "invalid distance too far back"
#if ! defined( NO_MMX )
.align 4,0
.L_mask: /* mask[N] = ( 1 << N ) - 1 */
.long 0
.long 1
.long 3
.long 7
.long 15
.long 31
.long 63
.long 127
.long 255
.long 511
.long 1023
.long 2047
.long 4095
.long 8191
.long 16383
.long 32767
.long 65535
.long 131071
.long 262143
.long 524287
.long 1048575
.long 2097151
.long 4194303
.long 8388607
.long 16777215
.long 33554431
.long 67108863
.long 134217727
.long 268435455
.long 536870911
.long 1073741823
.long 2147483647
.long 4294967295
#endif /* NO_MMX */
.text
/*
* struct z_stream offsets, in zlib.h
*/
#define next_in_strm 0 /* strm->next_in */
#define avail_in_strm 4 /* strm->avail_in */
#define next_out_strm 12 /* strm->next_out */
#define avail_out_strm 16 /* strm->avail_out */
#define msg_strm 24 /* strm->msg */
#define state_strm 28 /* strm->state */
/*
* struct inflate_state offsets, in inflate.h
*/
#define mode_state 0 /* state->mode */
#define wsize_state 32 /* state->wsize */
#define write_state 40 /* state->write */
#define window_state 44 /* state->window */
#define hold_state 48 /* state->hold */
#define bits_state 52 /* state->bits */
#define lencode_state 68 /* state->lencode */
#define distcode_state 72 /* state->distcode */
#define lenbits_state 76 /* state->lenbits */
#define distbits_state 80 /* state->distbits */
/*
* inflate_fast's activation record
*/
#define local_var_size 64 /* how much local space for vars */
#define strm_sp 88 /* first arg: z_stream * (local_var_size + 24) */
#define start_sp 92 /* second arg: unsigned int (local_var_size + 28) */
/*
* offsets for local vars on stack
*/
#define out 60 /* unsigned char* */
#define window 56 /* unsigned char* */
#define wsize 52 /* unsigned int */
#define write 48 /* unsigned int */
#define in 44 /* unsigned char* */
#define beg 40 /* unsigned char* */
#define buf 28 /* char[ 12 ] */
#define len 24 /* unsigned int */
#define last 20 /* unsigned char* */
#define end 16 /* unsigned char* */
#define dcode 12 /* code* */
#define lcode 8 /* code* */
#define dmask 4 /* unsigned int */
#define lmask 0 /* unsigned int */
/*
* typedef enum inflate_mode consts, in inflate.h
*/
#define INFLATE_MODE_TYPE 11 /* state->mode flags enum-ed in inflate.h */
#define INFLATE_MODE_BAD 26
#if ! defined( USE_MMX ) && ! defined( NO_MMX )
#define RUN_TIME_MMX
#define CHECK_MMX 1
#define DO_USE_MMX 2
#define DONT_USE_MMX 3
.globl inflate_fast_use_mmx
.data
.align 4,0
inflate_fast_use_mmx: /* integer flag for run time control 1=check,2=mmx,3=no */
.long CHECK_MMX
#if defined( GAS_ELF )
/* elf info */
.type inflate_fast_use_mmx,@object
.size inflate_fast_use_mmx,4
#endif
#endif /* RUN_TIME_MMX */
#if defined( GAS_COFF )
/* coff info: scl 2 = extern, type 32 = function */
.def inflate_fast; .scl 2; .type 32; .endef
#endif
.text
.align 32,0x90
inflate_fast:
pushl %edi
pushl %esi
pushl %ebp
pushl %ebx
pushf /* save eflags (strm_sp, state_sp assumes this is 32 bits) */
subl $local_var_size, %esp
cld
#define strm_r %esi
#define state_r %edi
movl strm_sp(%esp), strm_r
movl state_strm(strm_r), state_r
/* in = strm->next_in;
* out = strm->next_out;
* last = in + strm->avail_in - 11;
* beg = out - (start - strm->avail_out);
* end = out + (strm->avail_out - 257);
*/
movl avail_in_strm(strm_r), %edx
movl next_in_strm(strm_r), %eax
addl %eax, %edx /* avail_in += next_in */
subl $11, %edx /* avail_in -= 11 */
movl %eax, in(%esp)
movl %edx, last(%esp)
movl start_sp(%esp), %ebp
movl avail_out_strm(strm_r), %ecx
movl next_out_strm(strm_r), %ebx
subl %ecx, %ebp /* start -= avail_out */
negl %ebp /* start = -start */
addl %ebx, %ebp /* start += next_out */
subl $257, %ecx /* avail_out -= 257 */
addl %ebx, %ecx /* avail_out += out */
movl %ebx, out(%esp)
movl %ebp, beg(%esp)
movl %ecx, end(%esp)
/* wsize = state->wsize;
* write = state->write;
* window = state->window;
* hold = state->hold;
* bits = state->bits;
* lcode = state->lencode;
* dcode = state->distcode;
* lmask = ( 1 << state->lenbits ) - 1;
* dmask = ( 1 << state->distbits ) - 1;
*/
movl lencode_state(state_r), %eax
movl distcode_state(state_r), %ecx
movl %eax, lcode(%esp)
movl %ecx, dcode(%esp)
movl $1, %eax
movl lenbits_state(state_r), %ecx
shll %cl, %eax
decl %eax
movl %eax, lmask(%esp)
movl $1, %eax
movl distbits_state(state_r), %ecx
shll %cl, %eax
decl %eax
movl %eax, dmask(%esp)
movl wsize_state(state_r), %eax
movl write_state(state_r), %ecx
movl window_state(state_r), %edx
movl %eax, wsize(%esp)
movl %ecx, write(%esp)
movl %edx, window(%esp)
movl hold_state(state_r), %ebp
movl bits_state(state_r), %ebx
#undef strm_r
#undef state_r
#define in_r %esi
#define from_r %esi
#define out_r %edi
movl in(%esp), in_r
movl last(%esp), %ecx
cmpl in_r, %ecx
ja .L_align_long /* if in < last */
addl $11, %ecx /* ecx = &in[ avail_in ] */
subl in_r, %ecx /* ecx = avail_in */
movl $12, %eax
subl %ecx, %eax /* eax = 12 - avail_in */
leal buf(%esp), %edi
rep movsb /* memcpy( buf, in, avail_in ) */
movl %eax, %ecx
xorl %eax, %eax
rep stosb /* memset( &buf[ avail_in ], 0, 12 - avail_in ) */
leal buf(%esp), in_r /* in = buf */
movl in_r, last(%esp) /* last = in, do just one iteration */
jmp .L_is_aligned
/* align in_r on long boundary */
.L_align_long:
testl $3, in_r
jz .L_is_aligned
xorl %eax, %eax
movb (in_r), %al
incl in_r
movl %ebx, %ecx
addl $8, %ebx
shll %cl, %eax
orl %eax, %ebp
jmp .L_align_long
.L_is_aligned:
movl out(%esp), out_r
#if defined( NO_MMX )
jmp .L_do_loop
#endif
#if defined( USE_MMX )
jmp .L_init_mmx
#endif
/*** Runtime MMX check ***/
#if defined( RUN_TIME_MMX )
.L_check_mmx:
cmpl $DO_USE_MMX, inflate_fast_use_mmx
je .L_init_mmx
ja .L_do_loop /* > 2 */
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
pushf
movl (%esp), %eax /* copy eflags to eax */
xorl $0x200000, (%esp) /* try toggling ID bit of eflags (bit 21)
* to see if cpu supports cpuid...
* ID bit method not supported by NexGen but
* bios may load a cpuid instruction and
* cpuid may be disabled on Cyrix 5-6x86 */
popf
pushf
popl %edx /* copy new eflags to edx */
xorl %eax, %edx /* test if ID bit is flipped */
jz .L_dont_use_mmx /* not flipped if zero */
xorl %eax, %eax
cpuid
cmpl $0x756e6547, %ebx /* check for GenuineIntel in ebx,ecx,edx */
jne .L_dont_use_mmx
cmpl $0x6c65746e, %ecx
jne .L_dont_use_mmx
cmpl $0x49656e69, %edx
jne .L_dont_use_mmx
movl $1, %eax
cpuid /* get cpu features */
shrl $8, %eax
andl $15, %eax
cmpl $6, %eax /* check for Pentium family, is 0xf for P4 */
jne .L_dont_use_mmx
testl $0x800000, %edx /* test if MMX feature is set (bit 23) */
jnz .L_use_mmx
jmp .L_dont_use_mmx
.L_use_mmx:
movl $DO_USE_MMX, inflate_fast_use_mmx
jmp .L_check_mmx_pop
.L_dont_use_mmx:
movl $DONT_USE_MMX, inflate_fast_use_mmx
.L_check_mmx_pop:
popl %edx
popl %ecx
popl %ebx
popl %eax
jmp .L_check_mmx
#endif
/*** Non-MMX code ***/
#if defined ( NO_MMX ) || defined( RUN_TIME_MMX )
#define hold_r %ebp
#define bits_r %bl
#define bitslong_r %ebx
.align 32,0x90
.L_while_test:
/* while (in < last && out < end)
*/
cmpl out_r, end(%esp)
jbe .L_break_loop /* if (out >= end) */
cmpl in_r, last(%esp)
jbe .L_break_loop
.L_do_loop:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out
*
* do {
* if (bits < 15) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* this = lcode[hold & lmask]
*/
cmpb $15, bits_r
ja .L_get_length_code /* if (15 < bits) */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
.L_get_length_code:
movl lmask(%esp), %edx /* edx = lmask */
movl lcode(%esp), %ecx /* ecx = lcode */
andl hold_r, %edx /* edx &= hold */
movl (%ecx,%edx,4), %eax /* eax = lcode[hold & lmask] */
.L_dolen:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out
*
* dolen:
* bits -= this.bits;
* hold >>= this.bits
*/
movb %ah, %cl /* cl = this.bits */
subb %ah, bits_r /* bits -= this.bits */
shrl %cl, hold_r /* hold >>= this.bits */
/* check if op is a literal
* if (op == 0) {
* PUP(out) = this.val;
* }
*/
testb %al, %al
jnz .L_test_for_length_base /* if (op != 0) 45.7% */
shrl $16, %eax /* output this.val char */
stosb
jmp .L_while_test
.L_test_for_length_base:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = len
*
* else if (op & 16) {
* len = this.val
* op &= 15
* if (op) {
* if (op > bits) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* len += hold & mask[op];
* bits -= op;
* hold >>= op;
* }
*/
#define len_r %edx
movl %eax, len_r /* len = this */
shrl $16, len_r /* len = this.val */
movb %al, %cl
testb $16, %al
jz .L_test_for_second_level_length /* if ((op & 16) == 0) 8% */
andb $15, %cl /* op &= 15 */
jz .L_save_len /* if (!op) */
cmpb %cl, bits_r
jae .L_add_bits_to_len /* if (op <= bits) */
movb %cl, %ch /* stash op in ch, freeing cl */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
movb %ch, %cl /* move op back to ecx */
.L_add_bits_to_len:
movl $1, %eax
shll %cl, %eax
decl %eax
subb %cl, bits_r
andl hold_r, %eax /* eax &= hold */
shrl %cl, hold_r
addl %eax, len_r /* len += hold & mask[op] */
.L_save_len:
movl len_r, len(%esp) /* save len */
#undef len_r
.L_decode_distance:
/* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = dist
*
* if (bits < 15) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* this = dcode[hold & dmask];
* dodist:
* bits -= this.bits;
* hold >>= this.bits;
* op = this.op;
*/
cmpb $15, bits_r
ja .L_get_distance_code /* if (15 < bits) */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
.L_get_distance_code:
movl dmask(%esp), %edx /* edx = dmask */
movl dcode(%esp), %ecx /* ecx = dcode */
andl hold_r, %edx /* edx &= hold */
movl (%ecx,%edx,4), %eax /* eax = dcode[hold & dmask] */
#define dist_r %edx
.L_dodist:
movl %eax, dist_r /* dist = this */
shrl $16, dist_r /* dist = this.val */
movb %ah, %cl
subb %ah, bits_r /* bits -= this.bits */
shrl %cl, hold_r /* hold >>= this.bits */
/* if (op & 16) {
* dist = this.val
* op &= 15
* if (op > bits) {
* hold |= *((unsigned short *)in)++ << bits;
* bits += 16
* }
* dist += hold & mask[op];
* bits -= op;
* hold >>= op;
*/
movb %al, %cl /* cl = this.op */
testb $16, %al /* if ((op & 16) == 0) */
jz .L_test_for_second_level_dist
andb $15, %cl /* op &= 15 */
jz .L_check_dist_one
cmpb %cl, bits_r
jae .L_add_bits_to_dist /* if (op <= bits) 97.6% */
movb %cl, %ch /* stash op in ch, freeing cl */
xorl %eax, %eax
lodsw /* al = *(ushort *)in++ */
movb bits_r, %cl /* cl = bits, needs it for shifting */
addb $16, bits_r /* bits += 16 */
shll %cl, %eax
orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */
movb %ch, %cl /* move op back to ecx */
.L_add_bits_to_dist:
movl $1, %eax
shll %cl, %eax
decl %eax /* (1 << op) - 1 */
subb %cl, bits_r
andl hold_r, %eax /* eax &= hold */
shrl %cl, hold_r
addl %eax, dist_r /* dist += hold & ((1 << op) - 1) */
jmp .L_check_window
.L_check_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes
*
* nbytes = out - beg;
* if (dist <= nbytes) {
* from = out - dist;
* do {
* PUP(out) = PUP(from);
* } while (--len > 0) {
* }
*/
movl in_r, in(%esp) /* save in so from can use it's reg */
movl out_r, %eax
subl beg(%esp), %eax /* nbytes = out - beg */
cmpl dist_r, %eax
jb .L_clip_window /* if (dist > nbytes) 4.2% */
movl len(%esp), %ecx
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
subl $3, %ecx
movb (from_r), %al
movb %al, (out_r)
movb 1(from_r), %al
movb 2(from_r), %dl
addl $3, from_r
movb %al, 1(out_r)
movb %dl, 2(out_r)
addl $3, out_r
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
jmp .L_while_test
.align 16,0x90
.L_check_dist_one:
cmpl $1, dist_r
jne .L_check_window
cmpl out_r, beg(%esp)
je .L_check_window
decl out_r
movl len(%esp), %ecx
movb (out_r), %al
subl $3, %ecx
movb %al, 1(out_r)
movb %al, 2(out_r)
movb %al, 3(out_r)
addl $4, out_r
rep stosb
jmp .L_while_test
.align 16,0x90
.L_test_for_second_level_length:
/* else if ((op & 64) == 0) {
* this = lcode[this.val + (hold & mask[op])];
* }
*/
testb $64, %al
jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */
movl $1, %eax
shll %cl, %eax
decl %eax
andl hold_r, %eax /* eax &= hold */
addl %edx, %eax /* eax += this.val */
movl lcode(%esp), %edx /* edx = lcode */
movl (%edx,%eax,4), %eax /* eax = lcode[val + (hold&mask[op])] */
jmp .L_dolen
.align 16,0x90
.L_test_for_second_level_dist:
/* else if ((op & 64) == 0) {
* this = dcode[this.val + (hold & mask[op])];
* }
*/
testb $64, %al
jnz .L_invalid_distance_code /* if ((op & 64) != 0) */
movl $1, %eax
shll %cl, %eax
decl %eax
andl hold_r, %eax /* eax &= hold */
addl %edx, %eax /* eax += this.val */
movl dcode(%esp), %edx /* edx = dcode */
movl (%edx,%eax,4), %eax /* eax = dcode[val + (hold&mask[op])] */
jmp .L_dodist
.align 16,0x90
.L_clip_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes
*
* else {
* if (dist > wsize) {
* invalid distance
* }
* from = window;
* nbytes = dist - nbytes;
* if (write == 0) {
* from += wsize - nbytes;
*/
#define nbytes_r %ecx
movl %eax, nbytes_r
movl wsize(%esp), %eax /* prepare for dist compare */
negl nbytes_r /* nbytes = -nbytes */
movl window(%esp), from_r /* from = window */
cmpl dist_r, %eax
jb .L_invalid_distance_too_far /* if (dist > wsize) */
addl dist_r, nbytes_r /* nbytes = dist - nbytes */
cmpl $0, write(%esp)
jne .L_wrap_around_window /* if (write != 0) */
subl nbytes_r, %eax
addl %eax, from_r /* from += wsize - nbytes */
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = len
*
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = out - dist;
* }
* }
*/
#define len_r %eax
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
.L_wrap_around_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = write, %eax = len
*
* else if (write < nbytes) {
* from += wsize + write - nbytes;
* nbytes -= write;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = window;
* nbytes = write;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while(--nbytes);
* from = out - dist;
* }
* }
* }
*/
#define write_r %eax
movl write(%esp), write_r
cmpl write_r, nbytes_r
jbe .L_contiguous_in_window /* if (write >= nbytes) */
addl wsize(%esp), from_r
addl write_r, from_r
subl nbytes_r, from_r /* from += wsize + write - nbytes */
subl write_r, nbytes_r /* nbytes -= write */
#undef write_r
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl window(%esp), from_r /* from = window */
movl write(%esp), nbytes_r /* nbytes = write */
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1
.L_contiguous_in_window:
/* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist
* %ecx = nbytes, %eax = write, %eax = len
*
* else {
* from += write - nbytes;
* if (nbytes < len) {
* len -= nbytes;
* do {
* PUP(out) = PUP(from);
* } while (--nbytes);
* from = out - dist;
* }
* }
*/
#define write_r %eax
addl write_r, from_r
subl nbytes_r, from_r /* from += write - nbytes */
#undef write_r
movl len(%esp), len_r
cmpl nbytes_r, len_r
jbe .L_do_copy1 /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
.L_do_copy1:
/* regs: %esi = from, %esi = in, %ebp = hold, %bl = bits, %edi = out
* %eax = len
*
* while (len > 0) {
* PUP(out) = PUP(from);
* len--;
* }
* }
* } while (in < last && out < end);
*/
#undef nbytes_r
#define in_r %esi
movl len_r, %ecx
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
jmp .L_while_test
#undef len_r
#undef dist_r
#endif /* NO_MMX || RUN_TIME_MMX */
/*** MMX code ***/
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
.align 32,0x90
.L_init_mmx:
emms
#undef bits_r
#undef bitslong_r
#define bitslong_r %ebp
#define hold_mm %mm0
movd %ebp, hold_mm
movl %ebx, bitslong_r
#define used_mm %mm1
#define dmask2_mm %mm2
#define lmask2_mm %mm3
#define lmask_mm %mm4
#define dmask_mm %mm5
#define tmp_mm %mm6
movd lmask(%esp), lmask_mm
movq lmask_mm, lmask2_mm
movd dmask(%esp), dmask_mm
movq dmask_mm, dmask2_mm
pxor used_mm, used_mm
movl lcode(%esp), %ebx /* ebx = lcode */
jmp .L_do_loop_mmx
.align 32,0x90
.L_while_test_mmx:
/* while (in < last && out < end)
*/
cmpl out_r, end(%esp)
jbe .L_break_loop /* if (out >= end) */
cmpl in_r, last(%esp)
jbe .L_break_loop
.L_do_loop_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
cmpl $32, bitslong_r
ja .L_get_length_code_mmx /* if (32 < bits) */
movd bitslong_r, tmp_mm
movd (in_r), %mm7
addl $4, in_r
psllq tmp_mm, %mm7
addl $32, bitslong_r
por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */
.L_get_length_code_mmx:
pand hold_mm, lmask_mm
movd lmask_mm, %eax
movq lmask2_mm, lmask_mm
movl (%ebx,%eax,4), %eax /* eax = lcode[hold & lmask] */
.L_dolen_mmx:
movzbl %ah, %ecx /* ecx = this.bits */
movd %ecx, used_mm
subl %ecx, bitslong_r /* bits -= this.bits */
testb %al, %al
jnz .L_test_for_length_base_mmx /* if (op != 0) 45.7% */
shrl $16, %eax /* output this.val char */
stosb
jmp .L_while_test_mmx
.L_test_for_length_base_mmx:
#define len_r %edx
movl %eax, len_r /* len = this */
shrl $16, len_r /* len = this.val */
testb $16, %al
jz .L_test_for_second_level_length_mmx /* if ((op & 16) == 0) 8% */
andl $15, %eax /* op &= 15 */
jz .L_decode_distance_mmx /* if (!op) */
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd %eax, used_mm
movd hold_mm, %ecx
subl %eax, bitslong_r
andl .L_mask(,%eax,4), %ecx
addl %ecx, len_r /* len += hold & mask[op] */
.L_decode_distance_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
cmpl $32, bitslong_r
ja .L_get_dist_code_mmx /* if (32 < bits) */
movd bitslong_r, tmp_mm
movd (in_r), %mm7
addl $4, in_r
psllq tmp_mm, %mm7
addl $32, bitslong_r
por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */
.L_get_dist_code_mmx:
movl dcode(%esp), %ebx /* ebx = dcode */
pand hold_mm, dmask_mm
movd dmask_mm, %eax
movq dmask2_mm, dmask_mm
movl (%ebx,%eax,4), %eax /* eax = dcode[hold & lmask] */
.L_dodist_mmx:
#define dist_r %ebx
movzbl %ah, %ecx /* ecx = this.bits */
movl %eax, dist_r
shrl $16, dist_r /* dist = this.val */
subl %ecx, bitslong_r /* bits -= this.bits */
movd %ecx, used_mm
testb $16, %al /* if ((op & 16) == 0) */
jz .L_test_for_second_level_dist_mmx
andl $15, %eax /* op &= 15 */
jz .L_check_dist_one_mmx
.L_add_bits_to_dist_mmx:
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd %eax, used_mm /* save bit length of current op */
movd hold_mm, %ecx /* get the next bits on input stream */
subl %eax, bitslong_r /* bits -= op bits */
andl .L_mask(,%eax,4), %ecx /* ecx = hold & mask[op] */
addl %ecx, dist_r /* dist += hold & mask[op] */
.L_check_window_mmx:
movl in_r, in(%esp) /* save in so from can use it's reg */
movl out_r, %eax
subl beg(%esp), %eax /* nbytes = out - beg */
cmpl dist_r, %eax
jb .L_clip_window_mmx /* if (dist > nbytes) 4.2% */
movl len_r, %ecx
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
subl $3, %ecx
movb (from_r), %al
movb %al, (out_r)
movb 1(from_r), %al
movb 2(from_r), %dl
addl $3, from_r
movb %al, 1(out_r)
movb %dl, 2(out_r)
addl $3, out_r
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
.align 16,0x90
.L_check_dist_one_mmx:
cmpl $1, dist_r
jne .L_check_window_mmx
cmpl out_r, beg(%esp)
je .L_check_window_mmx
decl out_r
movl len_r, %ecx
movb (out_r), %al
subl $3, %ecx
movb %al, 1(out_r)
movb %al, 2(out_r)
movb %al, 3(out_r)
addl $4, out_r
rep stosb
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
.align 16,0x90
.L_test_for_second_level_length_mmx:
testb $64, %al
jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */
andl $15, %eax
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ecx
andl .L_mask(,%eax,4), %ecx
addl len_r, %ecx
movl (%ebx,%ecx,4), %eax /* eax = lcode[hold & lmask] */
jmp .L_dolen_mmx
.align 16,0x90
.L_test_for_second_level_dist_mmx:
testb $64, %al
jnz .L_invalid_distance_code /* if ((op & 64) != 0) */
andl $15, %eax
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ecx
andl .L_mask(,%eax,4), %ecx
movl dcode(%esp), %eax /* ecx = dcode */
addl dist_r, %ecx
movl (%eax,%ecx,4), %eax /* eax = lcode[hold & lmask] */
jmp .L_dodist_mmx
.align 16,0x90
.L_clip_window_mmx:
#define nbytes_r %ecx
movl %eax, nbytes_r
movl wsize(%esp), %eax /* prepare for dist compare */
negl nbytes_r /* nbytes = -nbytes */
movl window(%esp), from_r /* from = window */
cmpl dist_r, %eax
jb .L_invalid_distance_too_far /* if (dist > wsize) */
addl dist_r, nbytes_r /* nbytes = dist - nbytes */
cmpl $0, write(%esp)
jne .L_wrap_around_window_mmx /* if (write != 0) */
subl nbytes_r, %eax
addl %eax, from_r /* from += wsize - nbytes */
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
.L_wrap_around_window_mmx:
#define write_r %eax
movl write(%esp), write_r
cmpl write_r, nbytes_r
jbe .L_contiguous_in_window_mmx /* if (write >= nbytes) */
addl wsize(%esp), from_r
addl write_r, from_r
subl nbytes_r, from_r /* from += wsize + write - nbytes */
subl write_r, nbytes_r /* nbytes -= write */
#undef write_r
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl window(%esp), from_r /* from = window */
movl write(%esp), nbytes_r /* nbytes = write */
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
jmp .L_do_copy1_mmx
.L_contiguous_in_window_mmx:
#define write_r %eax
addl write_r, from_r
subl nbytes_r, from_r /* from += write - nbytes */
#undef write_r
cmpl nbytes_r, len_r
jbe .L_do_copy1_mmx /* if (nbytes >= len) */
subl nbytes_r, len_r /* len -= nbytes */
rep movsb
movl out_r, from_r
subl dist_r, from_r /* from = out - dist */
.L_do_copy1_mmx:
#undef nbytes_r
#define in_r %esi
movl len_r, %ecx
rep movsb
movl in(%esp), in_r /* move in back to %esi, toss from */
movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */
jmp .L_while_test_mmx
#undef hold_r
#undef bitslong_r
#endif /* USE_MMX || RUN_TIME_MMX */
/*** USE_MMX, NO_MMX, and RUNTIME_MMX from here on ***/
.L_invalid_distance_code:
/* else {
* strm->msg = "invalid distance code";
* state->mode = BAD;
* }
*/
movl $.L_invalid_distance_code_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_test_for_end_of_block:
/* else if (op & 32) {
* state->mode = TYPE;
* break;
* }
*/
testb $32, %al
jz .L_invalid_literal_length_code /* if ((op & 32) == 0) */
movl $0, %ecx
movl $INFLATE_MODE_TYPE, %edx
jmp .L_update_stream_state
.L_invalid_literal_length_code:
/* else {
* strm->msg = "invalid literal/length code";
* state->mode = BAD;
* }
*/
movl $.L_invalid_literal_length_code_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_invalid_distance_too_far:
/* strm->msg = "invalid distance too far back";
* state->mode = BAD;
*/
movl in(%esp), in_r /* from_r has in's reg, put in back */
movl $.L_invalid_distance_too_far_msg, %ecx
movl $INFLATE_MODE_BAD, %edx
jmp .L_update_stream_state
.L_update_stream_state:
/* set strm->msg = %ecx, strm->state->mode = %edx */
movl strm_sp(%esp), %eax
testl %ecx, %ecx /* if (msg != NULL) */
jz .L_skip_msg
movl %ecx, msg_strm(%eax) /* strm->msg = msg */
.L_skip_msg:
movl state_strm(%eax), %eax /* state = strm->state */
movl %edx, mode_state(%eax) /* state->mode = edx (BAD | TYPE) */
jmp .L_break_loop
.align 32,0x90
.L_break_loop:
/*
* Regs:
*
* bits = %ebp when mmx, and in %ebx when non-mmx
* hold = %hold_mm when mmx, and in %ebp when non-mmx
* in = %esi
* out = %edi
*/
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
#if defined( RUN_TIME_MMX )
cmpl $DO_USE_MMX, inflate_fast_use_mmx
jne .L_update_next_in
#endif /* RUN_TIME_MMX */
movl %ebp, %ebx
.L_update_next_in:
#endif
#define strm_r %eax
#define state_r %edx
/* len = bits >> 3;
* in -= len;
* bits -= len << 3;
* hold &= (1U << bits) - 1;
* state->hold = hold;
* state->bits = bits;
* strm->next_in = in;
* strm->next_out = out;
*/
movl strm_sp(%esp), strm_r
movl %ebx, %ecx
movl state_strm(strm_r), state_r
shrl $3, %ecx
subl %ecx, in_r
shll $3, %ecx
subl %ecx, %ebx
movl out_r, next_out_strm(strm_r)
movl %ebx, bits_state(state_r)
movl %ebx, %ecx
leal buf(%esp), %ebx
cmpl %ebx, last(%esp)
jne .L_buf_not_used /* if buf != last */
subl %ebx, in_r /* in -= buf */
movl next_in_strm(strm_r), %ebx
movl %ebx, last(%esp) /* last = strm->next_in */
addl %ebx, in_r /* in += strm->next_in */
movl avail_in_strm(strm_r), %ebx
subl $11, %ebx
addl %ebx, last(%esp) /* last = &strm->next_in[ avail_in - 11 ] */
.L_buf_not_used:
movl in_r, next_in_strm(strm_r)
movl $1, %ebx
shll %cl, %ebx
decl %ebx
#if defined( USE_MMX ) || defined( RUN_TIME_MMX )
#if defined( RUN_TIME_MMX )
cmpl $DO_USE_MMX, inflate_fast_use_mmx
jne .L_update_hold
#endif /* RUN_TIME_MMX */
psrlq used_mm, hold_mm /* hold_mm >>= last bit length */
movd hold_mm, %ebp
emms
.L_update_hold:
#endif /* USE_MMX || RUN_TIME_MMX */
andl %ebx, %ebp
movl %ebp, hold_state(state_r)
#define last_r %ebx
/* strm->avail_in = in < last ? 11 + (last - in) : 11 - (in - last) */
movl last(%esp), last_r
cmpl in_r, last_r
jbe .L_last_is_smaller /* if (in >= last) */
subl in_r, last_r /* last -= in */
addl $11, last_r /* last += 11 */
movl last_r, avail_in_strm(strm_r)
jmp .L_fixup_out
.L_last_is_smaller:
subl last_r, in_r /* in -= last */
negl in_r /* in = -in */
addl $11, in_r /* in += 11 */
movl in_r, avail_in_strm(strm_r)
#undef last_r
#define end_r %ebx
.L_fixup_out:
/* strm->avail_out = out < end ? 257 + (end - out) : 257 - (out - end)*/
movl end(%esp), end_r
cmpl out_r, end_r
jbe .L_end_is_smaller /* if (out >= end) */
subl out_r, end_r /* end -= out */
addl $257, end_r /* end += 257 */
movl end_r, avail_out_strm(strm_r)
jmp .L_done
.L_end_is_smaller:
subl end_r, out_r /* out -= end */
negl out_r /* out = -out */
addl $257, out_r /* out += 257 */
movl out_r, avail_out_strm(strm_r)
#undef end_r
#undef strm_r
#undef state_r
.L_done:
addl $local_var_size, %esp
popf
popl %ebx
popl %ebp
popl %esi
popl %edi
ret
#if defined( GAS_ELF )
/* elf info */
.type inflate_fast,@function
.size inflate_fast,.-inflate_fast
#endif
|
GeminiCarrie/crate-sgx-ex | 1,472 | lexical-sgx/lexical-codegen/lexical/asm.s | / (fcn) sym.parse_u8 75
| sym.parse_u8 (unsigned int arg1);
| ; arg unsigned int arg1 @ rdi
| 0x000032f0 test rsi, rsi
| ,=< 0x000032f3 je 0x3335
| | 0x000032f5 cmp byte [rdi], 0x2b ; [0x2b:1]=0 ; '+' ; arg1
| ,==< 0x000032f8 jne 0x3304
| || 0x000032fa add rsi, 0xffffffffffffffff
| ,===< 0x000032fe je 0x3335
| ||| 0x00003300 add rdi, 1
| |`--> 0x00003304 mov rcx, rdi
| | | 0x00003307 add rcx, rsi ; '+'
| | | 0x0000330a xor eax, eax
| | | 0x0000330c mov r8b, 0xa
| | | 0x0000330f nop
| |.--> 0x00003310 mov edx, eax
| |:| 0x00003312 cmp rcx, rdi
| ,====< 0x00003315 je 0x3338
| ||:| 0x00003317 movzx esi, byte [rdi]
| ||:| 0x0000331a add esi, 0xffffffffffffffd0
| ||:| 0x0000331d cmp esi, 9
| ,=====< 0x00003320 ja 0x3332
| |||:| 0x00003322 mov eax, edx
| |||:| 0x00003324 mul r8b
| ,======< 0x00003327 jo 0x3332
| ||||:| 0x00003329 add rdi, 1
| ||||:| 0x0000332d add al, sil ; '.'
| ||||`==< 0x00003330 jae 0x3310
| ``-----> 0x00003332 xor eax, eax
| || | 0x00003334 ret
| |`-`-> 0x00003335 xor eax, eax
| | 0x00003337 ret
| `----> 0x00003338 mov al, 1
\ 0x0000333a ret
0x0000333b nop dword [rax + rax]
|
GeminiCarrie/crate-sgx-ex | 21,637 | lexical-sgx/lexical-codegen/core/asm.s | / (fcn) sym.core::num::__impl_core::str::FromStr_for_u8_::from_str::hce24b711719134f3 102
| sym.core::num::__impl_core::str::FromStr_for_u8_::from_str::hce24b711719134f3 (int arg5, unsigned int arg1, unsigned int arg2);
| ; arg int arg5 @ r8
| ; arg unsigned int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| 0x00022230 mov r8b, 1
| 0x00022233 test rsi, rsi
| ,=< 0x00022236 je 0x2224c
| | 0x00022238 cmp byte [rdi], 0x2b ; [0x2b:1]=0 ; '+' ; arg1
| | 0x0002223b mov rcx, rdi
| ,==< 0x0002223e jne 0x22256
| || 0x00022240 cmp rsi, 1 ; "ELF\x02\x01\x01" ; arg2
| ,===< 0x00022244 jne 0x22252
| ||| 0x00022246 xor edx, edx
| ||| 0x00022248 mov eax, r8d ; arg5
| ||| 0x0002224b ret
| ||`-> 0x0002224c xor edx, edx
| || 0x0002224e mov eax, r8d ; arg5
| || 0x00022251 ret
| `---> 0x00022252 lea rcx, [rdi + 1] ; "ELF\x02\x01\x01"
| `--> 0x00022256 add rdi, rsi ; '+'
| 0x00022259 xor eax, eax
| 0x0002225b mov r9b, 0xa
| 0x0002225e nop
| .-> 0x00022260 cmp rdi, rcx
| ,==< 0x00022263 je 0x22287
| |: 0x00022265 movzx esi, byte [rcx]
| |: 0x00022268 add esi, 0xffffffffffffffd0
| |: 0x0002226b mov r8b, 1
| |: 0x0002226e cmp esi, 9
| ,===< 0x00022271 ja 0x22290
| ||: 0x00022273 mul r9b
| ||: 0x00022276 mov dl, 2
| ,====< 0x00022278 jo 0x22283
| |||: 0x0002227a add rcx, 1
| |||: 0x0002227e add al, sil ; '.'
| |||`=< 0x00022281 jae 0x22260
| `----> 0x00022283 mov eax, r8d ; arg5
| || 0x00022286 ret
| |`--> 0x00022287 xor r8d, r8d
| | 0x0002228a mov edx, eax
| | 0x0002228c mov eax, r8d ; arg5
| | 0x0002228f ret
| `---> 0x00022290 mov dl, 1
| 0x00022292 mov eax, r8d ; arg5
\ 0x00022295 ret
0x00022296 nop word cs:[rax + rax]
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_u16_::from_str::h447c8ddc73e5df8e 125
| sym.core::num::__impl_core::str::FromStr_for_u16_::from_str::h447c8ddc73e5df8e (int arg6, unsigned int arg1, unsigned int arg2);
| ; arg int arg6 @ r9
| ; arg unsigned int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| 0x000222a0 mov r8d, 1
| 0x000222a6 xor r9d, r9d
| 0x000222a9 test rsi, rsi
| ,=< 0x000222ac je 0x222bc
| | 0x000222ae cmp byte [rdi], 0x2b ; [0x2b:1]=0 ; '+' ; arg1
| | 0x000222b1 mov rcx, rdi
| ,==< 0x000222b4 jne 0x222cc
| || 0x000222b6 cmp rsi, 1 ; "ELF\x02\x01\x01" ; arg2
| ,===< 0x000222ba jne 0x222c8
| ||`-> 0x000222bc xor edx, edx
| ...--.-> 0x000222be or r9d, r8d
| :::||: 0x000222c1 or r9d, edx
| :::||: 0x000222c4 mov eax, r9d ; arg6
| :::||: 0x000222c7 ret
| :::`---> 0x000222c8 lea rcx, [rdi + 1] ; "ELF\x02\x01\x01"
| ::: `--> 0x000222cc add rdi, rsi ; '+'
| ::: : 0x000222cf xor eax, eax
| ::: : 0x000222d1 mov r10w, 0xa
| ::: : 0x000222d6 nop word cs:[rax + rax]
| ::: .--> 0x000222e0 cmp rdi, rcx
| :::,===< 0x000222e3 je 0x22309
| :::|:: 0x000222e5 movzx esi, byte [rcx]
| :::|:: 0x000222e8 add esi, 0xffffffffffffffd0
| :::|:: 0x000222eb xor r9d, r9d
| :::|:: 0x000222ee cmp esi, 9
| ,=======< 0x000222f1 ja 0x22316
| |:::|:: 0x000222f3 mul r10w
| |:::|:: 0x000222f7 mov edx, 0x200 ; "Q\xe5td\x06"
| |`======< 0x000222fc jo 0x222be
| | ::|:: 0x000222fe add rcx, 1
| | ::|:: 0x00022302 add ax, si ; '-'
| | ::|`==< 0x00022305 jae 0x222e0
| | `=====< 0x00022307 jmp 0x222be
| | :`---> 0x00022309 shl eax, 0x10
| | : : 0x0002230c xor edx, edx
| | : : 0x0002230e mov r9d, eax
| | : : 0x00022311 xor r8d, r8d
| | `====< 0x00022314 jmp 0x222be
| `-------> 0x00022316 mov edx, 0x100
\ `=< 0x0002231b jmp 0x222be
0x0002231d nop dword [rax]
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_u32_::from_str::hb2d9607963b46005 121
| sym.core::num::__impl_core::str::FromStr_for_u32_::from_str::hb2d9607963b46005 (unsigned int arg1, unsigned int arg2);
| ; arg unsigned int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| 0x00022320 mov r8d, 1
| 0x00022326 test rsi, rsi
| ,=< 0x00022329 je 0x22339
| | 0x0002232b cmp byte [rdi], 0x2b ; [0x2b:1]=0 ; '+' ; arg1
| | 0x0002232e mov rcx, rdi
| ,==< 0x00022331 jne 0x2234c
| || 0x00022333 cmp rsi, 1 ; "ELF\x02\x01\x01" ; arg2
| ,===< 0x00022337 jne 0x22348
| ||`-> 0x00022339 xor r10d, r10d
| || 0x0002233c xor edx, edx
| ...--.-> 0x0002233e or r10, r8
| :::||: 0x00022341 or r10, rdx
| :::||: 0x00022344 mov rax, r10
| :::||: 0x00022347 ret
| :::`---> 0x00022348 lea rcx, [rdi + 1] ; "ELF\x02\x01\x01"
| ::: `--> 0x0002234c add rdi, rsi ; '+'
| ::: : 0x0002234f xor r10d, r10d
| ::: : 0x00022352 mov r9d, 0xa
| ::: : 0x00022358 xor eax, eax
| ::: : 0x0002235a nop word [rax + rax]
| ::: .--> 0x00022360 cmp rdi, rcx
| :::,===< 0x00022363 je 0x22384
| :::|:: 0x00022365 movzx esi, byte [rcx]
| :::|:: 0x00022368 add esi, 0xffffffffffffffd0
| :::|:: 0x0002236b cmp esi, 9
| ,=======< 0x0002236e ja 0x22392
| |:::|:: 0x00022370 mul r9d
| |:::|:: 0x00022373 mov edx, 0x200 ; "Q\xe5td\x06"
| |`======< 0x00022378 jo 0x2233e
| | ::|:: 0x0002237a add rcx, 1
| | ::|:: 0x0002237e add eax, esi
| | ::|`==< 0x00022380 jae 0x22360
| | `=====< 0x00022382 jmp 0x2233e
| | :`---> 0x00022384 shl rax, 0x20
| | : : 0x00022388 xor edx, edx
| | : : 0x0002238a mov r10, rax
| | : : 0x0002238d xor r8d, r8d
| | `====< 0x00022390 jmp 0x2233e
| `-------> 0x00022392 mov edx, 0x100
\ `=< 0x00022397 jmp 0x2233e
0x00022399 nop dword [rax]
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_usize_::from_str::hb41eb873edd26255 109
| sym.core::num::__impl_core::str::FromStr_for_usize_::from_str::hb41eb873edd26255 (int arg1, unsigned int arg2, unsigned int arg3);
| ; arg int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| ; arg unsigned int arg3 @ rdx
| 0x000223a0 mov r8, rdi ; arg1
| 0x000223a3 test rdx, rdx
| ,=< 0x000223a6 je 0x223b6
| | 0x000223a8 cmp byte [rsi], 0x2b ; [0x2b:1]=0 ; '+' ; arg2
| | 0x000223ab mov rcx, rsi
| ,==< 0x000223ae jne 0x223c1
| || 0x000223b0 cmp rdx, 1 ; "ELF\x02\x01\x01" ; arg3
| ,===< 0x000223b4 jne 0x223bd
| ||`-> 0x000223b6 mov byte [r8 + 1], 0
| ||,=< 0x000223bb jmp 0x22404
| `---> 0x000223bd lea rcx, [rsi + 1] ; "ELF\x02\x01\x01"
| `--> 0x000223c1 add rsi, rdx
| | 0x000223c4 xor eax, eax
| | 0x000223c6 mov r9d, 0xa
| | 0x000223cc nop dword [rax]
| .--> 0x000223d0 cmp rsi, rcx
| ,===< 0x000223d3 je 0x223f7
| |:| 0x000223d5 movzx edi, byte [rcx]
| |:| 0x000223d8 add edi, 0xffffffffffffffd0
| |:| 0x000223db cmp edi, 0xa
| ,====< 0x000223de jae 0x223ff
| ||:| 0x000223e0 mul r9
| ,=====< 0x000223e3 jo 0x223f0
| |||:| 0x000223e5 add rcx, 1
| |||:| 0x000223e9 mov edx, edi
| |||:| 0x000223eb add rax, rdx
| |||`==< 0x000223ee jae 0x223d0
| `-----> 0x000223f0 mov byte [r8 + 1], 2
| ||,==< 0x000223f5 jmp 0x22404
| |`---> 0x000223f7 mov qword [r8 + 8], rax
| | || 0x000223fb xor eax, eax
| |,===< 0x000223fd jmp 0x22406
| `----> 0x000223ff mov byte [r8 + 1], 1
| |``-> 0x00022404 mov al, 1
| `---> 0x00022406 mov byte [r8], al
| 0x00022409 mov rax, r8
\ 0x0002240c ret
0x0002240d nop dword [rax]
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_u128_::from_str::hb6606e086cf598b5 190
| sym.core::num::__impl_core::str::FromStr_for_u128_::from_str::hb6606e086cf598b5 (int arg1, unsigned int arg2, unsigned int arg3, int arg4);
| ; arg int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| ; arg unsigned int arg3 @ rdx
| ; arg int arg4 @ rcx
| 0x00022410 push rbp
| 0x00022411 push r15
| 0x00022413 push r14
| 0x00022415 push rbx
| 0x00022416 mov r8, rdi ; arg1
| 0x00022419 test rdx, rdx
| ,=< 0x0002241c je 0x2242c
| | 0x0002241e cmp byte [rsi], 0x2b ; [0x2b:1]=0 ; '+' ; arg2
| | 0x00022421 mov r11, rsi
| ,==< 0x00022424 jne 0x2243a
| || 0x00022426 cmp rdx, 1 ; "ELF\x02\x01\x01" ; arg3
| ,===< 0x0002242a jne 0x22436
| ||`-> 0x0002242c mov byte [r8 + 1], 0
| ||,=< 0x00022431 jmp 0x224bf
| `---> 0x00022436 lea r11, [rsi + 1] ; "ELF\x02\x01\x01"
| `--> 0x0002243a add rsi, rdx
| | 0x0002243d xor ecx, ecx
| | 0x0002243f mov r14d, 0xa
| | 0x00022445 xor edi, edi
| | 0x00022447 nop word [rax + rax]
| .--> 0x00022450 cmp rsi, r11
| ,===< 0x00022453 je 0x224ae
| |:| 0x00022455 movzx ebp, byte [r11]
| |:| 0x00022459 add ebp, 0xffffffffffffffd0
| |:| 0x0002245c cmp ebp, 0xa
| ,====< 0x0002245f jae 0x224ba
| ||:| 0x00022461 xor eax, eax
| ||:| 0x00022463 mul rcx
| ||:| 0x00022466 mov r9, rax
| ||:| 0x00022469 seto r15b
| ||:| 0x0002246d mov rax, rdi ; arg1
| ||:| 0x00022470 mul r14
| ||:| 0x00022473 mov r10, rax
| ||:| 0x00022476 seto bl
| ||:| 0x00022479 or bl, r15b
| ||:| 0x0002247c add r10, r9 ; 'k'
| ||:| 0x0002247f mov rax, rcx ; arg4
| ||:| 0x00022482 mul r14
| ||:| 0x00022485 mov rdi, rdx
| ||:| 0x00022488 add rdi, r10 ; 'l'
| ||:| 0x0002248b setb dl
| ||:| 0x0002248e or dl, bl
| ||:| 0x00022490 cmp dl, 1 ; "ELF\x02\x01\x01"
| ,=====< 0x00022493 je 0x224a7
| |||:| 0x00022495 mov rcx, rax
| |||:| 0x00022498 add r11, 1
| |||:| 0x0002249c mov eax, ebp
| |||:| 0x0002249e add rcx, rax ; '#'
| |||:| 0x000224a1 adc rdi, 0
| |||`==< 0x000224a5 jae 0x22450
| `-----> 0x000224a7 mov byte [r8 + 1], 2
| ||,==< 0x000224ac jmp 0x224bf
| |`---> 0x000224ae mov qword [r8 + 8], rcx
| | || 0x000224b2 mov qword [r8 + 0x10], rdi
| | || 0x000224b6 xor eax, eax
| |,===< 0x000224b8 jmp 0x224c1
| `----> 0x000224ba mov byte [r8 + 1], 1
| |``-> 0x000224bf mov al, 1
| `---> 0x000224c1 mov byte [r8], al
| 0x000224c4 mov rax, r8
| 0x000224c7 pop rbx
| 0x000224c8 pop r14
| 0x000224ca pop r15
| 0x000224cc pop rbp
\ 0x000224cd ret
0x000224ce nop
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_i8_::from_str::hcb78a62c9f97c037 166
| sym.core::num::__impl_core::str::FromStr_for_i8_::from_str::hcb78a62c9f97c037 (int arg1, unsigned int arg2);
| ; arg int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| 0x00021f90 mov r9w, 1
| 0x00021f95 test rsi, rsi
| ,=< 0x00021f98 je 0x21fac
| | 0x00021f9a mov al, byte [rdi] ; arg1
| | 0x00021f9c cmp al, 0x2b ; '+'
| ,==< 0x00021f9e je 0x21fb0
| || 0x00021fa0 cmp al, 0x2d ; '-'
| ,===< 0x00021fa2 jne 0x21fc5
| ||| 0x00021fa4 xor eax, eax
| ||| 0x00021fa6 cmp rsi, 1 ; "ELF\x02\x01\x01" ; arg2
| ,====< 0x00021faa jne 0x21fb8
| .---`-> 0x00021fac xor eax, eax
| :|||,=< 0x00021fae jmp 0x22029
| :||`--> 0x00021fb0 mov al, 1
| :|| | 0x00021fb2 cmp rsi, 1 ; "ELF\x02\x01\x01"
| `=====< 0x00021fb6 je 0x21fac
| `----> 0x00021fb8 test al, al
| |,==< 0x00021fba je 0x21ff0
| ||| 0x00021fbc add rsi, rdi ; '''
| ||| 0x00021fbf lea rdi, [rdi + 1] ; "ELF\x02\x01\x01" ; arg1
| ,====< 0x00021fc3 jmp 0x21fc8
| |`---> 0x00021fc5 add rsi, rdi ; '''
| `----> 0x00021fc8 xor eax, eax
| || 0x00021fca mov dl, 0xa
| || 0x00021fcc nop dword [rax]
| .---> 0x00021fd0 cmp rsi, rdi
| ,====< 0x00021fd3 je 0x22022
| |:|| 0x00021fd5 movzx ecx, byte [rdi]
| |:|| 0x00021fd8 add ecx, 0xffffffffffffffd0
| |:|| 0x00021fdb cmp ecx, 9
| ,=====< 0x00021fde ja 0x22027
| ||:|| 0x00021fe0 imul dl
| ,======< 0x00021fe2 jo 0x21fec
| |||:|| 0x00021fe4 add rdi, 1
| |||:|| 0x00021fe8 add al, cl
| |||`===< 0x00021fea jno 0x21fd0
| `------> 0x00021fec mov al, 2
| ||,===< 0x00021fee jmp 0x22029
| |||`--> 0x00021ff0 mov edx, 1
| ||| | 0x00021ff5 xor eax, eax
| ||| | 0x00021ff7 mov r8b, 0xa
| ||| | 0x00021ffa nop word [rax + rax]
| |||.--> 0x00022000 cmp rsi, rdx
| ,======< 0x00022003 je 0x22022
| ||||:| 0x00022005 movzx ecx, byte [rdi + rdx]
| ||||:| 0x00022009 add ecx, 0xffffffffffffffd0
| ||||:| 0x0002200c cmp ecx, 9
| ,=======< 0x0002200f ja 0x22027
| |||||:| 0x00022011 imul r8b
| ========< 0x00022014 jo 0x2201e
| |||||:| 0x00022016 add rdx, 1
| |||||:| 0x0002201a sub al, cl
| |||||`==< 0x0002201c jno 0x22000
| --------> 0x0002201e mov al, 3
| |||||,==< 0x00022020 jmp 0x22029
| |`-`----> 0x00022022 xor r9d, r9d
| | |,====< 0x00022025 jmp 0x22029
| `-`-----> 0x00022027 mov al, 1
| ````-> 0x00022029 movzx ecx, al
| 0x0002202c shl ecx, 8
| 0x0002202f movzx eax, r9w
| 0x00022033 or eax, ecx
\ 0x00022035 ret
0x00022036 nop word cs:[rax + rax]
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_i16_::from_str::h6a138a1ad1d474f9 221
| sym.core::num::__impl_core::str::FromStr_for_i16_::from_str::h6a138a1ad1d474f9 (int arg1, unsigned int arg2, int arg3);
| ; arg int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| ; arg int arg3 @ rdx
| 0x00022040 mov r8d, 1
| 0x00022046 xor eax, eax
| 0x00022048 test rsi, rsi
| ,=< 0x0002204b je 0x22061
| | 0x0002204d mov cl, byte [rdi] ; arg1
| | 0x0002204f cmp cl, 0x2b ; '+'
| ,==< 0x00022052 je 0x2206b
| || 0x00022054 cmp cl, 0x2d ; '-'
| ,===< 0x00022057 jne 0x22080
| ||| 0x00022059 xor ecx, ecx
| ||| 0x0002205b cmp rsi, 1 ; "ELF\x02\x01\x01" ; arg2
| ,====< 0x0002205f jne 0x22073
| .---`-> 0x00022061 xor r10d, r10d
| ..----.-> 0x00022064 or eax, r8d
| :::|||: 0x00022067 or eax, r10d
| :::|||: 0x0002206a ret
| :::||`--> 0x0002206b mov cl, 1
| :::|| : 0x0002206d cmp rsi, 1 ; "ELF\x02\x01\x01"
| ::`=====< 0x00022071 je 0x22061
| :: `----> 0x00022073 test cl, cl
| :: |,==< 0x00022075 je 0x220b9
| :: ||: 0x00022077 add rsi, rdi ; '''
| :: ||: 0x0002207a lea rdi, [rdi + 1] ; "ELF\x02\x01\x01" ; arg1
| :: ,====< 0x0002207e jmp 0x22083
| :: |`---> 0x00022080 add rsi, rdi ; '''
| :: `----> 0x00022083 xor edx, edx
| :: |: 0x00022085 nop word cs:[rax + rax]
| :: |: 0x0002208f nop
| :: .---> 0x00022090 cmp rsi, rdi
| :: ,====< 0x00022093 je 0x22102
| :: |:|: 0x00022095 movzx ecx, byte [rdi]
| :: |:|: 0x00022098 add ecx, 0xffffffffffffffd0
| :: |:|: 0x0002209b xor eax, eax
| :: |:|: 0x0002209d cmp ecx, 9
| ::,=====< 0x000220a0 ja 0x22112
| ::||:|: 0x000220a2 imul dx, dx, 0xa
| ::||:|: 0x000220a6 mov r10d, 0x200 ; "Q\xe5td\x06"
| ========< 0x000220ac jo 0x22064
| ::||:|: 0x000220ae add rdi, 1
| ::||:|: 0x000220b2 add dx, cx
| ::||`===< 0x000220b5 jno 0x22090
| ========< 0x000220b7 jmp 0x22064
| ::|| `--> 0x000220b9 mov r9d, 1
| ::|| : 0x000220bf xor edx, edx
| ::|| : 0x000220c1 nop word cs:[rax + rax]
| ::|| : 0x000220cb nop dword [rax + rax]
| ::|| .--> 0x000220d0 cmp rsi, r9
| ::||,===< 0x000220d3 je 0x22102
| ::|||:: 0x000220d5 movzx ecx, byte [rdi + r9]
| ::|||:: 0x000220da add ecx, 0xffffffffffffffd0
| ::|||:: 0x000220dd xor eax, eax
| ::|||:: 0x000220df cmp ecx, 9
| ========< 0x000220e2 ja 0x22112
| ::|||:: 0x000220e4 imul dx, dx, 0xa
| ::|||:: 0x000220e8 mov r10d, 0x300
| ========< 0x000220ee jo 0x22064
| ::|||:: 0x000220f4 add r9, 1
| ::|||:: 0x000220f8 sub dx, cx
| ::|||`==< 0x000220fb jno 0x220d0
| `=======< 0x000220fd jmp 0x22064
| :|``---> 0x00022102 shl edx, 0x10
| :| : 0x00022105 xor r10d, r10d
| :| : 0x00022108 mov eax, edx ; arg3
| :| : 0x0002210a xor r8d, r8d
| `======< 0x0002210d jmp 0x22064
| --`-----> 0x00022112 mov r10d, 0x100
\ `=< 0x00022118 jmp 0x22064
0x0002211d nop dword [rax]
/ (fcn) sym.core::num::__impl_core::str::FromStr_for_i32_::from_str::hdffbc2364705f1c5 202
| sym.core::num::__impl_core::str::FromStr_for_i32_::from_str::hdffbc2364705f1c5 (int arg1, unsigned int arg2, int arg4);
| ; arg int arg1 @ rdi
| ; arg unsigned int arg2 @ rsi
| ; arg int arg4 @ rcx
| 0x00022120 mov r8d, 1
| 0x00022126 test rsi, rsi
| ,=< 0x00022129 je 0x22152
| | 0x0002212b mov al, byte [rdi] ; arg1
| | 0x0002212d cmp al, 0x2b ; '+'
| ,==< 0x0002212f je 0x2214a
| || 0x00022131 cmp al, 0x2d ; '-'
| ,===< 0x00022133 jne 0x2215e
| ||| 0x00022135 xor eax, eax
| ||| 0x00022137 cmp rsi, 1 ; "ELF\x02\x01\x01" ; arg2
| ,====< 0x0002213b je 0x22152
| .-----> 0x0002213d test al, al
| ,======< 0x0002213f je 0x22195
| |:|||| 0x00022141 add rsi, rdi ; '''
| |:|||| 0x00022144 lea rdi, [rdi + 1] ; "ELF\x02\x01\x01" ; arg1
| ,=======< 0x00022148 jmp 0x22161
| ||:||`--> 0x0002214a mov al, 1
| ||:|| | 0x0002214c cmp rsi, 1 ; "ELF\x02\x01\x01"
| ||`=====< 0x00022150 jne 0x2213d
| || `--`-> 0x00022152 xor eax, eax
| || | 0x00022154 xor r10d, r10d
| --..-..-> 0x00022157 or rax, r8
| ||::|:: 0x0002215a or rax, r10
| ||::|:: 0x0002215d ret
| ||::`---> 0x0002215e add rsi, rdi ; '''
| `-------> 0x00022161 xor eax, eax
| |:: :: 0x00022163 xor ecx, ecx
| |:: :: 0x00022165 nop word cs:[rax + rax]
| |:: :: 0x0002216f nop
| |::.---> 0x00022170 cmp rsi, rdi
| ,=======< 0x00022173 je 0x221cd
| ||::::: 0x00022175 movzx edx, byte [rdi]
| ||::::: 0x00022178 add edx, 0xffffffffffffffd0
| ||::::: 0x0002217b cmp edx, 9
| ========< 0x0002217e ja 0x221df
| ||::::: 0x00022180 imul ecx, ecx, 0xa
| ||::::: 0x00022183 mov r10d, 0x200 ; "Q\xe5td\x06"
| ========< 0x00022189 jo 0x22157
| ||::::: 0x0002218b add rdi, 1
| ||::::: 0x0002218f add ecx, edx
| ||::`===< 0x00022191 jno 0x22170
| ========< 0x00022193 jmp 0x22157
| |`------> 0x00022195 xor eax, eax
| | :: :: 0x00022197 mov r9d, 1
| | :: :: 0x0002219d xor ecx, ecx
| | :: :: 0x0002219f nop
| | ::.---> 0x000221a0 cmp rsi, r9
| |,======< 0x000221a3 je 0x221cd
| ||::::: 0x000221a5 movzx edx, byte [rdi + r9]
| ||::::: 0x000221aa add edx, 0xffffffffffffffd0
| ||::::: 0x000221ad mov r8d, 1
| ||::::: 0x000221b3 cmp edx, 9
| ========< 0x000221b6 ja 0x221df
| ||::::: 0x000221b8 imul ecx, ecx, 0xa
| ||::::: 0x000221bb mov r10d, 0x300
| ||`=====< 0x000221c1 jo 0x22157
| || :::: 0x000221c3 add r9, 1
| || :::: 0x000221c7 sub ecx, edx
| || :`===< 0x000221c9 jno 0x221a0
| || `====< 0x000221cb jmp 0x22157
| ``------> 0x000221cd shl rcx, 0x20
| :: 0x000221d1 xor r10d, r10d
| :: 0x000221d4 mov rax, rcx ; arg4
| :: 0x000221d7 xor r8d, r8d
| `==< 0x000221da jmp 0x22157
| --------> 0x000221df mov r10d, 0x100
\ `=< 0x000221e5 jmp 0x22157
0x000221ea nop word [rax + rax]
|
G-haoyu/terminal-bench | 1,923 | tasks/reverse-engineering/tests/validate.s | .file "validate.s"
.text
.globl validate
.type validate, @function
validate:
.LFB0:
.cfi_startproc
pushq %rbx # Save callee-saved register
# Initialize hash register to 0
xorq %rbx, %rbx # Use xor to zero out rbx (our hash accumulator)
.L_LOOP_START:
# Load the next character from the input string (pointed to by rdi)
movzbq (%rdi), %rax # rax = *rdi (current character)
# Check if we've reached the end of the string (null terminator)
testb %al, %al
jz .L_LOOP_END # If char is 0, jump to the end
# --- Obfuscated Hash Calculation ---
# This algorithm is hash = (hash * 31) + char
# We implement hash * 31 as (hash * 32) - hash
movq %rbx, %rcx # rcx = old hash
shlq $5, %rbx # rbx = old hash * 32
subq %rcx, %rbx # rbx = (old hash * 32) - old hash = hash * 31
addq %rax, %rbx # rbx = (hash * 31) + current char
incq %rdi # Move to the next character
jmp .L_LOOP_START # Repeat
.L_LOOP_END:
# --- Obfuscated Comparison ---
# The real hash of "iLoVeTbENCH" is 0x1393be23a9e19b7.
# To hide this, we XOR the calculated hash with a random key
# before comparing it to a pre-XORed value.
#
# Real Hash ^ Key = Obfuscated Value
# 0x1393be23a9e19b7 ^ 0x1122334455667788 = 0x101b08a66ff86e3f
movq $0x1122334455667788, %rax
xorq %rax, %rbx # Obfuscate our calculated hash
# Compare the result to the pre-calculated obfuscated value
movq $0x101b08a66ff86e3f, %rax
cmpq %rax, %rbx
# Set return value (rax) to 1 if equal, 0 otherwise
sete %al
movzbq %al, %rax
popq %rbx # Restore register
ret
.cfi_endproc
.LFE0:
.size validate, .-validate |
ghosthunter15/termux-assembly-builder | 416 | hello.s | .section .data
msg: .asciz "Hello from AArch64 Termux!\n"
.section .text
.global _start
_start:
ldr x0, =msg // x0 = pointer to message
mov x1, #26 // x1 = length of message
mov x2, #1 // x2 = file descriptor (stdout)
mov x8, #64 // syscall number for write
svc 0
mov x0, #0 // exit code
mov x8, #93 // syscall number for exit
svc 0
|
git-ravenbin/phala-blockchain | 561 | crates/sgx-api-lite/src/enclave_api.S | .global sgx_report
.type sgx_report, @function
sgx_report:
.cfi_startproc
push rbx
push rcx
mov rbx,rdi
mov rcx,rsi
mov rax,0x0
clc
enclu
setc al
pop rcx
pop rbx
ret
.cfi_endproc
.global sgx_getkey
.type sgx_getkey, @function
sgx_getkey:
.cfi_startproc
push rbx
push rcx
mov rbx,rdi
mov rcx,rsi
mov rax,0x1
enclu
jz .Legetkey_done
xor rax, rax
.Legetkey_done:
pop rcx
pop rbx
ret
.cfi_endproc
|
gitwillsky/lite_os | 675 | kernel/src/task/switch.S | .altmacro
.macro SAVE_SN n
sd s\n, (\n+2)*8(a0)
.endm
.macro LOAD_SN n
ld s\n, (\n+2)*8(a1)
.endm
.section .text
.globl __switch
__switch:
# __switch(
# current_task_cx_ptr: *mut TaskContext,
# next_task_cx_ptr: *const TaskContext
# )
# save kernel stack of current task
sd sp, 8(a0)
# save ra & s0~s11 of current execution
sd ra, 0(a0)
.set n, 0
.rept 12
SAVE_SN %n
.set n, n + 1
.endr
# restore ra & s0~s11 of next execution
ld ra, 0(a1)
.set n, 0
.rept 12
LOAD_SN %n
.set n, n + 1
.endr
# restore kernel stack of next task
ld sp, 8(a1)
ret |
gitwillsky/lite_os | 2,515 | kernel/src/trap/trap.S | .altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __alltraps
.globl __restore
.globl __kernel_trap
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they have been saved in TrapContext
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it in TrapContext
csrr t2, sscratch
sd t2, 2*8(sp)
# load kernel_satp into t0
ld t0, 34*8(sp)
# load trap_handler into t1
ld t1, 36*8(sp)
# move to kernel_sp
ld sp, 35*8(sp)
# switch to kernel space
csrw satp, t0
sfence.vma
# jump to trap_handler
jr t1
# ----------------------------------------------------------------------
# Kernel-mode trap entry
# Save minimal caller-saved state, call into Rust to handle, then sret
# This path is used when traps/interrupts occur while executing in kernel
# mode (e.g., idle loop). It must not corrupt kernel registers/state.
# ----------------------------------------------------------------------
__kernel_trap:
# Save general purpose registers (except x0/sp/tp) like __alltraps
addi sp, sp, -(32*8)
sd x1, 1*8(sp)
# skip sp(x2)
sd x3, 3*8(sp)
# skip tp(x4)
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
call rust_trap_from_kernel
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
addi sp, sp, (32*8)
sret
__restore:
# a0: *TrapContext in user space(Constant); a1: user space token
# switch to user space
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
# now sp points to TrapContext in user space, start restoring based on it
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
# restore general purpose registers except x0/sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# back to user stack
ld sp, 2*8(sp)
sret
|
Glenda-dev/Glenda | 731 | kernel/src/boot.S | .section .text.start
.globl _start
.globl secondary_start
.equ BOOT_STACK_SIZE, 4096 // 4KB 启动栈
.equ MAX_BOOT_HARTS, 8 // 最多 8 个 hart 并发启动
.macro HART_ENTRY
csrw sie, zero
la t0, trap
csrw stvec, t0
la t1, boot_stack_top
li t2, BOOT_STACK_SIZE
li t3, MAX_BOOT_HARTS
bgeu a0, t3, 1f
mul t2, t2, a0
sub sp, t1, t2
j 2f
1:
mv sp, t1
2:
tail glenda_main
.endm
_start: // boot hart
HART_ENTRY
secondary_start: // secondary harts
HART_ENTRY
.align 2
trap:
wfi
j trap
.section .bss
.align 16
boot_stack:
.space BOOT_STACK_SIZE * MAX_BOOT_HARTS
boot_stack_top:
|
glomdom/reginald-rs | 66 | test.S | .global _start
_start:
loop:
mov $0x69420, %eax
jmp loop |
glyh/minimoonbit | 176 | riscv_rt/test/malloc.s | .global mincaml_main
mincaml_main:
li a0, 1024
call mincaml_malloc
li t0, 777
sw t0, 0(a0)
lw a0, 0(a0)
call mincaml_print_int
li a7, 93
ecall
|
glyh/minimoonbit | 173 | riscv_rt/test/float_int.s | .global mincaml_main
mincaml_main:
li a0, 1
call mincaml_float_of_int
call mincaml_int_of_float
call mincaml_print_int
li a0, 0
li a7, 93
ecall
|
glyh/minimoonbit | 115 | riscv_rt/test/print_int.s | .global mincaml_main
mincaml_main:
li a0, 666
call mincaml_print_int
li a0, 0
li a7, 93
ecall
|
gmmorgan96/rust_os_v1 | 3,883 | src/arch/x86_64/boot.s | global start
extern long_mode_start
section .text
bits 32
start:
mov esp, stack_top
call check_multiboot
call check_cpuid
call check_long_mode
call set_up_page_tables
call enable_paging
; load the 64-bit GDT
lgdt [gdt64.pointer]
jmp gdt64.code:long_mode_start
; print `OK` to screen
mov dword [0xb8000], 0x2f4b2f4f
hlt
check_multiboot:
cmp eax, 0x36d76289
jne .no_multiboot
ret
.no_multiboot:
mov al, "0"
jmp error
check_cpuid:
; Check if CPUID is supported by attempting to flip the ID bit (bit 21)
; in the FLAGS register. If we can flip it, CPUID is available.
; Copy FLAGS in to EAX via stack
pushfd
pop eax
; Copy to ECX as well for comparing later on
mov ecx, eax
; Flip the ID bit
xor eax, 1 << 21
; Copy EAX to FLAGS via the stack
push eax
popfd
; Copy FLAGS back to EAX (with the flipped bit if CPUID is supported)
pushfd
pop eax
; Restore FLAGS from the old version stored in ECX (i.e. flipping the
; ID bit back if it was ever flipped).
push ecx
popfd
; Compare EAX and ECX. If they are equal then that means the bit
; wasn't flipped, and CPUID isn't supported.
cmp eax, ecx
je .no_cpuid
ret
.no_cpuid:
mov al, "1"
jmp error
check_long_mode:
; test if extended processor info in available
mov eax, 0x80000000 ; implicit argument for cpuid
cpuid ; get highest supported argument
cmp eax, 0x80000001 ; it needs to be at least 0x80000001
jb .no_long_mode ; if it's less, the CPU is too old for long mode
; use extended info to test if long mode is available
mov eax, 0x80000001 ; argument for extended processor info
cpuid ; returns various feature bits in ecx and edx
test edx, 1 << 29 ; test if the LM-bit is set in the D-register
jz .no_long_mode ; If it's not set, there is no long mode
ret
.no_long_mode:
mov al, "2"
jmp error
set_up_page_tables:
; map first P4 entry to P3 table
mov eax, p3_table
or eax, 0b11 ; present + writable
mov [p4_table], eax
; map first P3 entry to P2 table
mov eax, p2_table
or eax, 0b11 ; present + writable
mov [p3_table], eax
; map each P2 entry to a huge 2MiB page
mov ecx, 0 ; counter variable
.map_p2_table:
; map ecx-th P2 entry to a huge page that starts at address 2MiB*ecx
mov eax, 0x200000 ; 2MiB
mul ecx ; start address of ecx-th page
or eax, 0b10000011 ; present + writable + huge
mov [p2_table + ecx * 8], eax ; map ecx-th entry
inc ecx ; increase counter
cmp ecx, 512 ; if counter == 512, the whole P2 table is mapped
jne .map_p2_table ; else map the next entry
ret
enable_paging:
; load P4 to cr3 register (cpu uses this to access the P4 table)
mov eax, p4_table
mov cr3, eax
; enable PAE-flag in cr4 (Physical Address Extension)
mov eax, cr4
or eax, 1 << 5
mov cr4, eax
; set the long mode bit in the EFER MSR (model specific register)
mov ecx, 0xC0000080
rdmsr
or eax, 1 << 8
wrmsr
; enable paging in the cr0 register
mov eax, cr0
or eax, 1 << 31
mov cr0, eax
ret
; Prints `ERR: ` and the given error code to screen and hangs.
; parameter: error code (in ascii) in al
error:
mov dword [0xb8000], 0x4f524f45
mov dword [0xb8004], 0x4f3a4f52
mov dword [0xb8008], 0x4f204f20
mov byte [0xb800a], al
hlt
section .bss
align 4096
p4_table:
resb 4096
p3_table:
resb 4096
p2_table:
resb 4096
stack_bottom:
resb 64
stack_top:
section .rodata
gdt64:
dq 0 ; zero entry
.code: equ $ - gdt64 ; new
dq (1<<43) | (1<<44) | (1<<47) | (1<<53) ; code segment
.pointer:
dw $ - gdt64 - 1
dq gdt64 |
gmmorgan96/rust_os_v1 | 442 | src/arch/x86_64/multiboot_header.s | section .multiboot_header
header_start:
dd 0xe85250d6 ; magic number (multiboot 2)
dd 0 ; architecture 0 (protected mode i386)
dd header_end - header_start ; header length
; checksum
dd 0x100000000 - (0xe85250d6 + 0 + (header_end - header_start))
; insert optional multiboot tags here
; required end tag
dw 0 ; type
dw 0 ; flags
dd 8 ; size
header_end: |
gmmorgan96/rust_os_v1 | 378 | src/arch/x86_64/long_mode_init.s | global long_mode_start
extern rust_main
section .text
bits 64
long_mode_start:
; load 0 into all data segment registers
mov ax, 0
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
; call the rust main
extern rust_main
call rust_main
; print `OKAY` to screen
mov rax, 0x2f592f412f4b2f4f
mov qword [0xb8000], rax
hlt |
gofreelee/torch_with_smask | 11,694 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm/4x8c2-xzp-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
.syntax unified
# void pytorch_q8gemm_xzp_ukernel_4x8c2__neon(
# size_t mr,
# size_t nr,
# size_t k,
# const uint8_t* restrict a,
# size_t a_stride,
# const int32_t* restrict a_sum,
# const void* restrict w,
# uint8_t* restrict c,
# size_t c_stride,
# const union pytorch_qnnp_q31_requantization_params requantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8gemm_xzp_ukernel_4x8c2__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load w
# - ip = w
LDR ip, [sp, 8]
# Load bias0123(q8), bias4567(q9)
# q8 := vacc0x0123
# q9 := vacc0x4567
VLD1.8 {d16-d19}, [ip]!
# q10 := vacc1x0123
VMOV.I32 q10, q8
# q11 := vacc1x4567
VMOV.I32 q11, q9
# q12 := vacc2x0123
VMOV.I32 q12, q8
# q13 := vacc2x4567
VMOV.I32 q13, q9
# q14 := vacc3x0123
VMOV.I32 q14, q8
# q15 := vacc3x4567
VMOV.I32 q15, q9
PUSH {r4, r5, r6, r7, r8, r9, r10, r11}
VPUSH {d8-d15}
# r3 := a0
# r4 := a1
# r5 := a2
# r6 := a3
# r7 := a_sum0
# r8 := a_sum1
# r9 := a_sum2
# r10 := a_sum3
# a_sum0 := a_sum
LDR r7, [sp, 100]
# Load a_stride
# - ip = a_stride
LDR r10, [sp, 96]
# compare mr to 2
CMP r0, 2
# a1 += a_stride
ADD r4, r3, r10
# mr < 2, a1 := a0
MOVLO r4, r3
# r8 := a_sum1
ADD r8, r7, 4
# mr < 2, a_sum1 := a_sum0
MOVLO r8, r7
# r5 := a2
ADD r5, r4, r10
# mr <= 2, a2 := a1
MOVLS r5, r4
# r9 := a_sum2
ADD r9, r8, 4
# mr <= 2, a_sum2 := a_sum1
MOVLS r9, r8
# compare mr to 4
CMP r0, 4
# r6 := a3
ADD r6, r5, r10
# mr != 4, a3 := a2
MOVNE r6, r5
# a_sum3 := a_sum2 + 1
# r10 := a_sum3
ADD r10, r9, 4
# mr != 4, a_sum3 := a_sum2
MOVNE r10, r9
# load a_sum
# q0: va_sum0
VLD1.32 {d0[], d1[]}, [r7]
# q1: va_sum1
VLD1.32 {d2[], d3[]}, [r8]
# q2: va_sum2
VLD1.32 {d4[], d5[]}, [r9]
# q3: va_sum3
VLD1.32 {d6[], d7[]}, [r10]
# accumulate a_sum into vacc
# vacc0x0123 = vaddq_s32(vacc0x0123, va_sum0)
VADD.I32 q8, q8, q0
# vacc0x4567 = vaddq_s32(vacc0x4567, va_sum0)
VADD.I32 q9, q9, q0
# vacc1x0123 = vaddq_s32(vacc1x0123, va_sum1)
VADD.I32 q10, q10, q1
# vacc1x4567 = vaddq_s32(vacc1x4567, va_sum1)
VADD.I32 q11, q11, q1
# vacc2x0123 = vaddq_s32(vacc2x0123, va_sum2)
VADD.I32 q12, q12, q2
# vacc2x4567 = vaddq_s32(vacc2x4567, va_sum2)
VADD.I32 q13, q13, q2
# vacc3x0123 = vaddq_s32(vacc3x0123, va_sum3)
VADD.I32 q14, q14, q3
# vacc3x4567 = vaddq_s32(vacc3x4567, va_sum3)
VADD.I32 q15, q15, q3
# k -= 8
SUBS r2, r2, 8
BLO 1f
.p2align 5
0:
# load a
# d0 := va0x01234567
VLD1.8 {d0}, [r3]!
# d1 := va1x01234567
VLD1.8 {d1}, [r4]!
# d2 := va1x01234567
VLD1.8 {d2}, [r5]!
# d3 := va2x01234567
VLD1.8 {d3}, [r6]!
##### k = 0, 1 #####
# load b
# q2 := vb01234567x01
VLD1.8 {d4, d5}, [ip]!
VMULL.U8 q4, d0, d4
VPADAL.U16 q8, q4
VMULL.U8 q5, d0, d5
VPADAL.U16 q9, q5
VMULL.U8 q6, d1, d4
VPADAL.U16 q10, q6
VMULL.U8 q7, d1, d5
VPADAL.U16 q11, q7
VMULL.U8 q4, d2, d4
VPADAL.U16 q12, q4
VMULL.U8 q5, d2, d5
VPADAL.U16 q13, q5
VMULL.U8 q6, d3, d4
VPADAL.U16 q14, q6
VMULL.U8 q7, d3, d5
VPADAL.U16 q15, q7
##### k = 2, 3 #####
# load b
# q2 := vb01234567x01
VLD1.8 {d4, d5}, [ip]!
# rotate a
VEXT.8 d0, d0, d0, 2
VEXT.8 d1, d1, d1, 2
VEXT.8 d2, d2, d2, 2
VEXT.8 d3, d3, d3, 2
VMULL.U8 q4, d0, d4
VPADAL.U16 q8, q4
VMULL.U8 q5, d0, d5
VPADAL.U16 q9, q5
VMULL.U8 q6, d1, d4
VPADAL.U16 q10, q6
VMULL.U8 q7, d1, d5
VPADAL.U16 q11, q7
VMULL.U8 q4, d2, d4
VPADAL.U16 q12, q4
VMULL.U8 q5, d2, d5
VPADAL.U16 q13, q5
VMULL.U8 q6, d3, d4
VPADAL.U16 q14, q6
VMULL.U8 q7, d3, d5
VPADAL.U16 q15, q7
##### k = 4, 5 #####
# load b
# q2 := vb01234567x01
VLD1.8 {d4, d5}, [ip]!
# rotate a
VEXT.8 d0, d0, d0, 2
VEXT.8 d1, d1, d1, 2
VEXT.8 d2, d2, d2, 2
VEXT.8 d3, d3, d3, 2
VMULL.U8 q4, d0, d4
VPADAL.U16 q8, q4
VMULL.U8 q5, d0, d5
VPADAL.U16 q9, q5
VMULL.U8 q6, d1, d4
VPADAL.U16 q10, q6
VMULL.U8 q7, d1, d5
VPADAL.U16 q11, q7
VMULL.U8 q4, d2, d4
VPADAL.U16 q12, q4
VMULL.U8 q5, d2, d5
VPADAL.U16 q13, q5
VMULL.U8 q6, d3, d4
VPADAL.U16 q14, q6
VMULL.U8 q7, d3, d5
VPADAL.U16 q15, q7
##### k = 6, 7 #####
# load b
# q2 := vb01234567x01
VLD1.8 {d4, d5}, [ip]!
# rotate a
VEXT.8 d0, d0, d0, 2
VEXT.8 d1, d1, d1, 2
VEXT.8 d2, d2, d2, 2
VEXT.8 d3, d3, d3, 2
VMULL.U8 q4, d0, d4
VPADAL.U16 q8, q4
VMULL.U8 q5, d0, d5
VPADAL.U16 q9, q5
VMULL.U8 q6, d1, d4
VPADAL.U16 q10, q6
VMULL.U8 q7, d1, d5
VPADAL.U16 q11, q7
VMULL.U8 q4, d2, d4
VPADAL.U16 q12, q4
VMULL.U8 q5, d2, d5
VPADAL.U16 q13, q5
VMULL.U8 q6, d3, d4
VPADAL.U16 q14, q6
VMULL.U8 q7, d3, d5
VPADAL.U16 q15, q7
# k -= 8
SUBS r2, r2, 8
# k >= 0, loop
BHS 0b
1:
# k >= 4
ADDS r2, 8
CMP r2, 4
# branch to 2f when k < 4
BLO 2f
SUB r2, r2, 4
##### k = 0, 1 #####
# d0 := va0x01010101
VLD1.16 {d0[]}, [r3]!
# d1 := va1x01010101
VLD1.16 {d1[]}, [r4]!
# d2 := va2x01010101
VLD1.16 {d2[]}, [r5]!
# d3 := va3x01010101
VLD1.16 {d3[]}, [r6]!
# q7 := vb01234567x01
VLD1.8 {d14, d15}, [ip]!
# row 0
VMULL.U8 q2, d0, d14
VPADAL.U16 q8, q2
VMULL.U8 q3, d0, d15
VPADAL.U16 q9, q3
# row 1
VMULL.U8 q4, d1, d14
VPADAL.U16 q10, q4
VMULL.U8 q5, d1, d15
VPADAL.U16 q11, q5
# row 2
VMULL.U8 q2, d2, d14
VPADAL.U16 q12, q2
VMULL.U8 q3, d2, d15
VPADAL.U16 q13, q3
# row 3
VMULL.U8 q4, d3, d14
VPADAL.U16 q14, q4
VMULL.U8 q5, d3, d15
VPADAL.U16 q15, q5
##### k = 2, 3 #####
# d0 := va0x01010101
VLD1.16 {d0[]}, [r3]!
# d1 := va1x01010101
VLD1.16 {d1[]}, [r4]!
# d2 := va2x01010101
VLD1.16 {d2[]}, [r5]!
# d3 := va3x01010101
VLD1.16 {d3[]}, [r6]!
# q7 := vb01234567x01
VLD1.8 {d14, d15}, [ip]!
# row 0
VMULL.U8 q2, d0, d14
VPADAL.U16 q8, q2
VMULL.U8 q3, d0, d15
VPADAL.U16 q9, q3
# row 1
VMULL.U8 q4, d1, d14
VPADAL.U16 q10, q4
VMULL.U8 q5, d1, d15
VPADAL.U16 q11, q5
# row 2
VMULL.U8 q2, d2, d14
VPADAL.U16 q12, q2
VMULL.U8 q3, d2, d15
VPADAL.U16 q13, q3
# row 3
VMULL.U8 q4, d3, d14
VPADAL.U16 q14, q4
VMULL.U8 q5, d3, d15
VPADAL.U16 q15, q5
2:
# k >= 2
CMP r2, 2
BLO 3f
SUB r2, r2, 2
##### k = 0, 1 #####
# d0 := va0x01010101
VLD1.16 {d0[]}, [r3]!
# d1 := va1x01010101
VLD1.16 {d1[]}, [r4]!
# d2 := va2x01010101
VLD1.16 {d2[]}, [r5]!
# d3 := va3x01010101
VLD1.16 {d3[]}, [r6]!
# q7 := vb01234567x01
VLD1.8 {d14, d15}, [ip]!
# row 0
VMULL.U8 q2, d0, d14
VPADAL.U16 q8, q2
VMULL.U8 q3, d0, d15
VPADAL.U16 q9, q3
# row 1
VMULL.U8 q4, d1, d14
VPADAL.U16 q10, q4
VMULL.U8 q5, d1, d15
VPADAL.U16 q11, q5
# row 2
VMULL.U8 q2, d2, d14
VPADAL.U16 q12, q2
VMULL.U8 q3, d2, d15
VPADAL.U16 q13, q3
# row 3
VMULL.U8 q4, d3, d14
VPADAL.U16 q14, q4
VMULL.U8 q5, d3, d15
VPADAL.U16 q15, q5
3:
# k == 1
CMP r2, 1
BLO 4f
# d0 := va0x01010101
VLD1.8 {d0[]}, [r3]
# d1 := va1x01010101
VLD1.8 {d1[]}, [r4]
# d2 := va2x01010101
VLD1.8 {d2[]}, [r5]
# d3 := va3x01010101
VLD1.8 {d3[]}, [r6]
# q7 := vb01234567x01
VLD1.8 {d14, d15}, [ip]
# row 0
VMULL.U8 q2, d0, d14
VPADAL.U16 q8, q2
VMULL.U8 q3, d0, d15
VPADAL.U16 q9, q3
# row 1
VMULL.U8 q4, d1, d14
VPADAL.U16 q10, q4
VMULL.U8 q5, d1, d15
VPADAL.U16 q11, q5
# row 2
VMULL.U8 q2, d2, d14
VPADAL.U16 q12, q2
VMULL.U8 q3, d2, d15
VPADAL.U16 q13, q3
# row 3
VMULL.U8 q4, d3, d14
VPADAL.U16 q14, q4
VMULL.U8 q5, d3, d15
VPADAL.U16 q15, q5
.p2align 4
4:
# Load params:
# - ip = params
LDR ip, [sp, 116]
# Load multiplier:
# - d12 = vmultiplier
VLD1.32 {d12[]}, [ip]!
# Load right_shift
# - q4 = d8:d9 = vright_shift
VLD1.32 {d8[], d9[]}, [ip]!
VQRDMULH.S32 q8, q8, d12[0]
VQRDMULH.S32 q9, q9, d12[0]
VQRDMULH.S32 q10, q10, d12[0]
VQRDMULH.S32 q11, q11, d12[0]
# Compute vzero_shift_mask
# - q5 = vzero_shift_mask
VCEQ.S32 q5, q4, 0
VQRDMULH.S32 q12, q12, d12[0]
VQRDMULH.S32 q13, q13, d12[0]
VQRDMULH.S32 q14, q14, d12[0]
VQRDMULH.S32 q15, q15, d12[0]
VBIC q0, q8, q5
VBIC q1, q9, q5
VBIC q2, q10, q5
VBIC q3, q11, q5
VSRA.S32 q8, q0, 31
VSRA.S32 q9, q1, 31
VSRA.S32 q10, q2, 31
VSRA.S32 q11, q3, 31
# Load zero_point
# - q7 = d14:d15 = vzero_point
VLD1.16 {d14[], d15[]}, [ip]!
VBIC q0, q12, q5
VBIC q1, q13, q5
VBIC q2, q14, q5
VBIC q3, q15, q5
VSRA.S32 q12, q0, 31
VSRA.S32 q13, q1, 31
VSRA.S32 q14, q2, 31
VSRA.S32 q15, q3, 31
# Load max:
# - q5 = d10:d11 = vmax
VLD1.8 {d10[], d11[]}, [ip]!
VRSHL.S32 q8, q8, q4
VRSHL.S32 q9, q9, q4
VRSHL.S32 q10, q10, q4
VRSHL.S32 q11, q11, q4
VRSHL.S32 q12, q12, q4
VRSHL.S32 q13, q13, q4
VRSHL.S32 q14, q14, q4
VRSHL.S32 q15, q15, q4
# Load c, c_stride:
# - r2 = c
# - r3 = c_stride
LDRD r2, r3, [sp, 108]
VQMOVN.S32 d16, q8
VQMOVN.S32 d17, q9
VQMOVN.S32 d18, q10
VQMOVN.S32 d19, q11
VQMOVN.S32 d20, q12
VQMOVN.S32 d21, q13
VQMOVN.S32 d22, q14
VQMOVN.S32 d23, q15
# Load min:
# - q4 = q8:q9 = vmin
VLD1.8 {d8[], d9[]}, [ip]!
ADD r4, r2, r3
VQADD.S16 q8, q8, q7
VQADD.S16 q9, q9, q7
CMP r0, 2
VQADD.S16 q10, q10, q7
VQADD.S16 q11, q11, q7
MOVLO r4, r2
VQMOVUN.S16 d16, q8
VQMOVUN.S16 d17, q9
ADD r5, r4, r3
VQMOVUN.S16 d18, q10
VQMOVUN.S16 d19, q11
MOVLS r5, r4
VMIN.U8 q8, q8, q5
CMP r0, 4
VMIN.U8 q9, q9, q5
ADD r3, r5, r3
VMAX.U8 q8, q8, q4
MOVNE r3, r5
CMP r1, 8
VMAX.U8 q9, q9, q4
BNE 5f
VST1.8 {d16}, [r2]
VST1.8 {d17}, [r4]
VST1.8 {d18}, [r5]
VST1.8 {d19}, [r3]
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
.p2align 3
5:
CMP r1, 4
BLO 6f
VST1.32 {d16[0]}, [r2]!
VST1.32 {d17[0]}, [r4]!
VST1.32 {d18[0]}, [r5]!
VST1.32 {d19[0]}, [r3]!
SUB r1, 4
VEXT.8 q8, q8, q8, 4
VEXT.8 q9, q9, q9, 4
6:
CMP r1, 2
BLO 7f
VST1.16 {d16[0]}, [r2]!
VST1.16 {d17[0]}, [r4]!
VST1.16 {d18[0]}, [r5]!
VST1.16 {d19[0]}, [r3]!
SUB r1, 2
VEXT.8 q8, q8, q8, 2
VEXT.8 q9, q9, q9, 2
7:
TEQ r1, 0
BEQ 8f
VST1.8 {d16[0]}, [r2]
VST1.8 {d17[0]}, [r4]
VST1.8 {d18[0]}, [r5]
VST1.8 {d19[0]}, [r3]
8:
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
END_FUNCTION pytorch_q8gemm_xzp_ukernel_4x8c2__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 26,778 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm/8x8-dq-aarch64-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
# params
# c_stride
# Args passed via stack.
# TOS
# |-----------|
# |c_stride | 0
# |out ch indx| 8
# |params | 16
# |-----------|
# void pytorch_q8gemm_dq_ukernel_8x8__aarch64_neon(
# size_t mr,
# size_t nr,
# size_t k,
# const uint8_t*restrict a,
# size_t a_stride,
# const void*restrict w,
# const float*restrict b,
# uint8_t*restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8gemm_dq_ukernel_8x8__aarch64_neon
STP d15, d14, [sp, -16]
STP d13, d12, [sp, -32]
STP d11, d10, [sp, -48]
STP d9, d8, [sp, -64]
# Skip over bias0123, bias4567
ADD x5, x5, 32
# Load c_stride & params
LDR x16, [sp]
# Load output channel index
LDR x10, [sp, 8]
# Load params
LDR x8, [sp, 16]
# Load a_zero_point
LD1R {v24.8b}, [x8]
ADD x8, x8, 8
# Load pointer to per channel zero points array
LDR x17, [x8], 8
# v8 := zero
EOR v8.16b, v8.16b, v8.16b
# v9 := zero
EOR v9.16b, v9.16b, v9.16b
# v10 := zero
EOR v10.16b, v10.16b, v10.16b
# v11 := zero
EOR v11.16b, v11.16b, v11.16b
# Load pointer to per channel multiplier
LDR x13, [x8]
# v12 := zero
EOR v12.16b, v12.16b, v12.16b
# v13 := zero
EOR v13.16b, v13.16b, v13.16b
# Add offset to the base pointer
ADD x17, x17, x10
# Mul by 4 to get byte offset for multiplier
LSL x10, x10, 2
# Add offset to the base pointer for multiplier
ADD x13, x13, x10
# Load b_zero_point
LD1 {v25.8b}, [x17]
# Load multiplier c0123
LD1 {v26.4s}, [x13], 16
# Load multiplier c4567
LD1 {v30.4s}, [x13]
# v14 := zero
EOR v14.16b, v14.16b, v14.16b
# v15 := zero
EOR v15.16b, v15.16b, v15.16b
# v16 := zero
EOR v16.16b, v16.16b, v16.16b
# v17 := zero
EOR v17.16b, v17.16b, v17.16b
# v18 := zero
EOR v18.16b, v18.16b, v18.16b
# v19 := zero
EOR v19.16b, v19.16b, v19.16b
# v20 := zero
EOR v20.16b, v20.16b, v20.16b
# v21 := zero
EOR v21.16b, v21.16b, v21.16b
# v22 := zero
EOR v22.16b, v22.16b, v22.16b
# v23 := zero
EOR v23.16b, v23.16b, v23.16b
# a1
CMP x0, 2
ADD x9, x3, x4
CSEL x9, x3, x9, LO
# a2
ADD x10, x9, x4
CSEL x10, x9, x10, LS
# a3
CMP x0, 4
ADD x11, x10, x4
CSEL x11, x10, x11, LO
# a4
ADD x12, x11, x4
CSEL x12, x11, x12, LS
# a5
CMP x0, 6
ADD x13, x12, x4
CSEL x13, x12, x13, LO
# a6
ADD x14, x13, x4
CSEL x14, x13, x14, LS
# a7
CMP x0, 8
ADD x15, x14, x4
CSEL x15, x14, x15, NE
SUBS x2, x2, 8
B.LO 1f
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 5
#endif
0:
// b0-7 (channel 0)
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
# va0 - va7 := va - va_zero_point
LD1 {v0.8b}, [x3], 8
SUB_ZERO_POINT v0.8h, v0.8b, v24.8b
LD1 {v1.8b}, [x9], 8
SUB_ZERO_POINT v1.8h, v1.8b, v24.8b
LD1 {v2.8b}, [x10], 8
SUB_ZERO_POINT v2.8h, v2.8b, v24.8b
LD1 {v3.8b}, [x11], 8
SUB_ZERO_POINT v3.8h, v3.8b, v24.8b
LD1 {v4.8b}, [x12], 8
SUB_ZERO_POINT v4.8h, v4.8b, v24.8b
LD1 {v5.8b}, [x13], 8
SUB_ZERO_POINT v5.8h, v5.8b, v24.8b
LD1 {v6.8b}, [x14], 8
SUB_ZERO_POINT v6.8h, v6.8b, v24.8b
LD1 {v7.8b}, [x15], 8
SUB_ZERO_POINT v7.8h, v7.8b, v24.8b
// b0-7 (channel 1)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[0] // vacc0x0123 += vb0123 * va0[0]
SMLAL2 v9.4s, v27.8h, v0.h[0] // vacc0x4567 += vb4567 * va0[0]
SMLAL v10.4s, v27.4h, v1.h[0] // vacc1x0123 += vb0123 * va1[0]
SMLAL2 v11.4s, v27.8h, v1.h[0] // vacc1x4567 += vb4567 * va1[0]
SMLAL v12.4s, v27.4h, v2.h[0] // vacc2x0123 += vb0123 * va2[0]
SMLAL2 v13.4s, v27.8h, v2.h[0] // vacc2x4567 += vb4567 * va2[0]
SMLAL v14.4s, v27.4h, v3.h[0] // vacc3x0123 += vb0123 * va3[0]
SMLAL2 v15.4s, v27.8h, v3.h[0] // vacc3x4567 += vb4567 * va3[0]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[0] // vacc4x0123 += vb0123 * va4[0]
SMLAL2 v17.4s, v27.8h, v4.h[0] // vacc4x4567 += vb4567 * va4[0]
SMLAL v18.4s, v27.4h, v5.h[0] // vacc5x0123 += vb0123 * va5[0]
SMLAL2 v19.4s, v27.8h, v5.h[0] // vacc5x4567 += vb4567 * va5[0]
SMLAL v20.4s, v27.4h, v6.h[0] // vacc6x0123 += vb0123 * va6[0]
SMLAL2 v21.4s, v27.8h, v6.h[0] // vacc6x4567 += vb4567 * va6[0]
SMLAL v22.4s, v27.4h, v7.h[0] // vacc7x0123 += vb0123 * va7[0]
SMLAL2 v23.4s, v27.8h, v7.h[0] // vacc7x4567 += vb4567 * va7[0]
// b0-7 (channel 2)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[1] // vacc0x0123 += vb0123 * va0[1]
SMLAL2 v9.4s, v28.8h, v0.h[1] // vacc0x4567 += vb4567 * va0[1]
SMLAL v10.4s, v28.4h, v1.h[1] // vacc1x0123 += vb0123 * va1[1]
SMLAL2 v11.4s, v28.8h, v1.h[1] // vacc1x4567 += vb4567 * va1[1]
SMLAL v12.4s, v28.4h, v2.h[1] // vacc2x0123 += vb0123 * va2[1]
SMLAL2 v13.4s, v28.8h, v2.h[1] // vacc2x4567 += vb4567 * va2[1]
SMLAL v14.4s, v28.4h, v3.h[1] // vacc3x0123 += vb0123 * va3[1]
SMLAL2 v15.4s, v28.8h, v3.h[1] // vacc3x4567 += vb4567 * va3[1]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[1] // vacc4x0123 += vb0123 * va4[1]
SMLAL2 v17.4s, v28.8h, v4.h[1] // vacc4x4567 += vb4567 * va4[1]
SMLAL v18.4s, v28.4h, v5.h[1] // vacc5x0123 += vb0123 * va5[1]
SMLAL2 v19.4s, v28.8h, v5.h[1] // vacc5x4567 += vb4567 * va5[1]
SMLAL v20.4s, v28.4h, v6.h[1] // vacc6x0123 += vb0123 * va6[1]
SMLAL2 v21.4s, v28.8h, v6.h[1] // vacc6x4567 += vb4567 * va6[1]
SMLAL v22.4s, v28.4h, v7.h[1] // vacc7x0123 += vb0123 * va7[1]
SMLAL2 v23.4s, v28.8h, v7.h[1] // vacc7x4567 += vb4567 * va7[1]
// b0-7 (channel 3)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[2] // vacc0x0123 += vb0123 * va0[2]
SMLAL2 v9.4s, v27.8h, v0.h[2] // vacc0x4567 += vb4567 * va0[2]
SMLAL v10.4s, v27.4h, v1.h[2] // vacc1x0123 += vb0123 * va1[2]
SMLAL2 v11.4s, v27.8h, v1.h[2] // vacc1x4567 += vb4567 * va1[2]
SMLAL v12.4s, v27.4h, v2.h[2] // vacc2x0123 += vb0123 * va2[2]
SMLAL2 v13.4s, v27.8h, v2.h[2] // vacc2x4567 += vb4567 * va2[2]
SMLAL v14.4s, v27.4h, v3.h[2] // vacc3x0123 += vb0123 * va3[2]
SMLAL2 v15.4s, v27.8h, v3.h[2] // vacc3x4567 += vb4567 * va3[2]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[2] // vacc4x0123 += vb0123 * va4[2]
SMLAL2 v17.4s, v27.8h, v4.h[2] // vacc4x4567 += vb4567 * va4[2]
SMLAL v18.4s, v27.4h, v5.h[2] // vacc5x0123 += vb0123 * va5[2]
SMLAL2 v19.4s, v27.8h, v5.h[2] // vacc5x4567 += vb4567 * va5[2]
SMLAL v20.4s, v27.4h, v6.h[2] // vacc6x0123 += vb0123 * va6[2]
SMLAL2 v21.4s, v27.8h, v6.h[2] // vacc6x4567 += vb4567 * va6[2]
SMLAL v22.4s, v27.4h, v7.h[2] // vacc7x0123 += vb0123 * va7[2]
SMLAL2 v23.4s, v27.8h, v7.h[2] // vacc7x4567 += vb4567 * va7[2]
// b0-7 (channel 4)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[3] // vacc0x0123 += vb0123 * va0[3]
SMLAL2 v9.4s, v28.8h, v0.h[3] // vacc0x4567 += vb4567 * va0[3]
SMLAL v10.4s, v28.4h, v1.h[3] // vacc1x0123 += vb0123 * va1[3]
SMLAL2 v11.4s, v28.8h, v1.h[3] // vacc1x4567 += vb4567 * va1[3]
SMLAL v12.4s, v28.4h, v2.h[3] // vacc2x0123 += vb0123 * va2[3]
SMLAL2 v13.4s, v28.8h, v2.h[3] // vacc2x4567 += vb4567 * va2[3]
SMLAL v14.4s, v28.4h, v3.h[3] // vacc3x0123 += vb0123 * va3[3]
SMLAL2 v15.4s, v28.8h, v3.h[3] // vacc3x4567 += vb4567 * va3[3]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[3] // vacc4x0123 += vb0123 * va4[3]
SMLAL2 v17.4s, v28.8h, v4.h[3] // vacc4x4567 += vb4567 * va4[3]
SMLAL v18.4s, v28.4h, v5.h[3] // vacc5x0123 += vb0123 * va5[3]
SMLAL2 v19.4s, v28.8h, v5.h[3] // vacc5x4567 += vb4567 * va5[3]
SMLAL v20.4s, v28.4h, v6.h[3] // vacc6x0123 += vb0123 * va6[3]
SMLAL2 v21.4s, v28.8h, v6.h[3] // vacc6x4567 += vb4567 * va6[3]
SMLAL v22.4s, v28.4h, v7.h[3] // vacc7x0123 += vb0123 * va7[3]
SMLAL2 v23.4s, v28.8h, v7.h[3] // vacc7x4567 += vb4567 * va7[3]
// b0-7 (channel 5)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[4] // vacc0x0123 += vb0123 * va0[4]
SMLAL2 v9.4s, v27.8h, v0.h[4] // vacc0x4567 += vb4567 * va0[4]
SMLAL v10.4s, v27.4h, v1.h[4] // vacc1x0123 += vb0123 * va1[4]
SMLAL2 v11.4s, v27.8h, v1.h[4] // vacc1x4567 += vb4567 * va1[4]
SMLAL v12.4s, v27.4h, v2.h[4] // vacc2x0123 += vb0123 * va2[4]
SMLAL2 v13.4s, v27.8h, v2.h[4] // vacc2x4567 += vb4567 * va2[4]
SMLAL v14.4s, v27.4h, v3.h[4] // vacc3x0123 += vb0123 * va3[4]
SMLAL2 v15.4s, v27.8h, v3.h[4] // vacc3x4567 += vb4567 * va3[4]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[4] // vacc4x0123 += vb0123 * va4[4]
SMLAL2 v17.4s, v27.8h, v4.h[4] // vacc4x4567 += vb4567 * va4[4]
SMLAL v18.4s, v27.4h, v5.h[4] // vacc5x0123 += vb0123 * va5[4]
SMLAL2 v19.4s, v27.8h, v5.h[4] // vacc5x4567 += vb4567 * va5[4]
SMLAL v20.4s, v27.4h, v6.h[4] // vacc6x0123 += vb0123 * va6[4]
SMLAL2 v21.4s, v27.8h, v6.h[4] // vacc6x4567 += vb4567 * va6[4]
SMLAL v22.4s, v27.4h, v7.h[4] // vacc7x0123 += vb0123 * va7[4]
SMLAL2 v23.4s, v27.8h, v7.h[4] // vacc7x4567 += vb4567 * va7[4]
// b0-7 (channel 6)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[5] // vacc0x0123 += vb0123 * va0[5]
SMLAL2 v9.4s, v28.8h, v0.h[5] // vacc0x4567 += vb4567 * va0[5]
SMLAL v10.4s, v28.4h, v1.h[5] // vacc1x0123 += vb0123 * va1[5]
SMLAL2 v11.4s, v28.8h, v1.h[5] // vacc1x4567 += vb4567 * va1[5]
SMLAL v12.4s, v28.4h, v2.h[5] // vacc2x0123 += vb0123 * va2[5]
SMLAL2 v13.4s, v28.8h, v2.h[5] // vacc2x4567 += vb4567 * va2[5]
SMLAL v14.4s, v28.4h, v3.h[5] // vacc3x0123 += vb0123 * va3[5]
SMLAL2 v15.4s, v28.8h, v3.h[5] // vacc3x4567 += vb4567 * va3[5]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[5] // vacc4x0123 += vb0123 * va4[5]
SMLAL2 v17.4s, v28.8h, v4.h[5] // vacc4x4567 += vb4567 * va4[5]
SMLAL v18.4s, v28.4h, v5.h[5] // vacc5x0123 += vb0123 * va5[5]
SMLAL2 v19.4s, v28.8h, v5.h[5] // vacc5x4567 += vb4567 * va5[5]
SMLAL v20.4s, v28.4h, v6.h[5] // vacc6x0123 += vb0123 * va6[5]
SMLAL2 v21.4s, v28.8h, v6.h[5] // vacc6x4567 += vb4567 * va6[5]
SMLAL v22.4s, v28.4h, v7.h[5] // vacc7x0123 += vb0123 * va7[5]
SMLAL2 v23.4s, v28.8h, v7.h[5] // vacc7x4567 += vb4567 * va7[5]
// b0-7 (channel 7)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[6] // vacc0x0123 += vb0123 * va0[6]
SMLAL2 v9.4s, v27.8h, v0.h[6] // vacc0x4567 += vb4567 * va0[6]
SMLAL v10.4s, v27.4h, v1.h[6] // vacc1x0123 += vb0123 * va1[6]
SMLAL2 v11.4s, v27.8h, v1.h[6] // vacc1x4567 += vb4567 * va1[6]
SMLAL v12.4s, v27.4h, v2.h[6] // vacc2x0123 += vb0123 * va2[6]
SMLAL2 v13.4s, v27.8h, v2.h[6] // vacc2x4567 += vb4567 * va2[6]
SMLAL v14.4s, v27.4h, v3.h[6] // vacc3x0123 += vb0123 * va3[6]
SMLAL2 v15.4s, v27.8h, v3.h[6] // vacc3x4567 += vb4567 * va3[6]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[6] // vacc4x0123 += vb0123 * va4[6]
SMLAL2 v17.4s, v27.8h, v4.h[6] // vacc4x4567 += vb4567 * va4[6]
SMLAL v18.4s, v27.4h, v5.h[6] // vacc5x0123 += vb0123 * va5[6]
SMLAL2 v19.4s, v27.8h, v5.h[6] // vacc5x4567 += vb4567 * va5[6]
SMLAL v20.4s, v27.4h, v6.h[6] // vacc6x0123 += vb0123 * va6[6]
SMLAL2 v21.4s, v27.8h, v6.h[6] // vacc6x4567 += vb4567 * va6[6]
SMLAL v22.4s, v27.4h, v7.h[6] // vacc7x0123 += vb0123 * va7[6]
SMLAL2 v23.4s, v27.8h, v7.h[6] // vacc7x4567 += vb4567 * va7[6]
SUBS x2, x2, 8
SMLAL v8.4s, v28.4h, v0.h[7] // vacc0x0123 += vb0123 * va0[7]
SMLAL2 v9.4s, v28.8h, v0.h[7] // vacc0x4567 += vb4567 * va0[7]
SMLAL v10.4s, v28.4h, v1.h[7] // vacc1x0123 += vb0123 * va1[7]
SMLAL2 v11.4s, v28.8h, v1.h[7] // vacc1x4567 += vb4567 * va1[7]
SMLAL v12.4s, v28.4h, v2.h[7] // vacc2x0123 += vb0123 * va2[7]
SMLAL2 v13.4s, v28.8h, v2.h[7] // vacc2x4567 += vb4567 * va2[7]
SMLAL v14.4s, v28.4h, v3.h[7] // vacc3x0123 += vb0123 * va3[7]
SMLAL2 v15.4s, v28.8h, v3.h[7] // vacc3x4567 += vb4567 * va3[7]
SMLAL v16.4s, v28.4h, v4.h[7] // vacc4x0123 += vb0123 * va4[7]
SMLAL2 v17.4s, v28.8h, v4.h[7] // vacc4x4567 += vb4567 * va4[7]
SMLAL v18.4s, v28.4h, v5.h[7] // vacc5x0123 += vb0123 * va5[7]
SMLAL2 v19.4s, v28.8h, v5.h[7] // vacc5x4567 += vb4567 * va5[7]
SMLAL v20.4s, v28.4h, v6.h[7] // vacc6x0123 += vb0123 * va6[7]
SMLAL2 v21.4s, v28.8h, v6.h[7] // vacc6x4567 += vb4567 * va6[7]
SMLAL v22.4s, v28.4h, v7.h[7] // vacc7x0123 += vb0123 * va7[7]
SMLAL2 v23.4s, v28.8h, v7.h[7] // vacc7x4567 += vb4567 * va7[7]
B.HS 0b
1:
CMP x2, -8
B.EQ 2f
// Adjust a0-a7
ADD x3, x3, x2
ADD x9, x9, x2
ADD x10, x10, x2
ADD x11, x11, x2
ADD x12, x12, x2
ADD x13, x13, x2
ADD x14, x14, x2
ADD x15, x15, x2
// a_shift = 8 * k - 64
LSL x2, x2, 3
FMOV d29, x2
USHL d24, d24, d29
// Load x0-a7
LD1 {v0.8b}, [x3], 8
USHL d0, d0, d29
SUB_ZERO_POINT v0.8h, v0.8b, v24.8b
LD1 {v1.8b}, [x9], 8
USHL d1, d1, d29
SUB_ZERO_POINT v1.8h, v1.8b, v24.8b
LD1 {v2.8b}, [x10], 8
USHL d2, d2, d29
SUB_ZERO_POINT v2.8h, v2.8b, v24.8b
LD1 {v3.8b}, [x11], 8
USHL d3, d3, d29
SUB_ZERO_POINT v3.8h, v3.8b, v24.8b
LD1 {v4.8b}, [x12], 8
USHL d4, d4, d29
SUB_ZERO_POINT v4.8h, v4.8b, v24.8b
LD1 {v5.8b}, [x13], 8
USHL d5, d5, d29
SUB_ZERO_POINT v5.8h, v5.8b, v24.8b
LD1 {v6.8b}, [x14], 8
USHL d6, d6, d29
SUB_ZERO_POINT v6.8h, v6.8b, v24.8b
LD1 {v7.8b}, [x15], 8
USHL d7, d7, d29
SUB_ZERO_POINT v7.8h, v7.8b, v24.8b
// Channel 0
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[0] // vacc0x0123 += vb0123 * va0[0]
SMLAL2 v9.4s, v27.8h, v0.h[0] // vacc0x4567 += vb4567 * va0[0]
SMLAL v10.4s, v27.4h, v1.h[0] // vacc1x0123 += vb0123 * va1[0]
SMLAL2 v11.4s, v27.8h, v1.h[0] // vacc1x4567 += vb4567 * va1[0]
SMLAL v12.4s, v27.4h, v2.h[0] // vacc2x0123 += vb0123 * va2[0]
SMLAL2 v13.4s, v27.8h, v2.h[0] // vacc2x4567 += vb4567 * va2[0]
SMLAL v14.4s, v27.4h, v3.h[0] // vacc3x0123 += vb0123 * va3[0]
SMLAL2 v15.4s, v27.8h, v3.h[0] // vacc3x4567 += vb4567 * va3[0]
SMLAL v16.4s, v27.4h, v4.h[0] // vacc4x0123 += vb0123 * va4[0]
SMLAL2 v17.4s, v27.8h, v4.h[0] // vacc4x4567 += vb4567 * va4[0]
SMLAL v18.4s, v27.4h, v5.h[0] // vacc5x0123 += vb0123 * va5[0]
SMLAL2 v19.4s, v27.8h, v5.h[0] // vacc5x4567 += vb4567 * va5[0]
SMLAL v20.4s, v27.4h, v6.h[0] // vacc6x0123 += vb0123 * va6[0]
SMLAL2 v21.4s, v27.8h, v6.h[0] // vacc6x4567 += vb4567 * va6[0]
SMLAL v22.4s, v27.4h, v7.h[0] // vacc7x0123 += vb0123 * va7[0]
SMLAL2 v23.4s, v27.8h, v7.h[0] // vacc7x4567 += vb4567 * va7[0]
CMP x2, -48
B.LO 2f
// Channel 1
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[1] // vacc0x0123 += vb0123 * va0[1]
SMLAL2 v9.4s, v28.8h, v0.h[1] // vacc0x4567 += vb4567 * va0[1]
SMLAL v10.4s, v28.4h, v1.h[1] // vacc1x0123 += vb0123 * va1[1]
SMLAL2 v11.4s, v28.8h, v1.h[1] // vacc1x4567 += vb4567 * va1[1]
SMLAL v12.4s, v28.4h, v2.h[1] // vacc2x0123 += vb0123 * va2[1]
SMLAL2 v13.4s, v28.8h, v2.h[1] // vacc2x4567 += vb4567 * va2[1]
SMLAL v14.4s, v28.4h, v3.h[1] // vacc3x0123 += vb0123 * va3[1]
SMLAL2 v15.4s, v28.8h, v3.h[1] // vacc3x4567 += vb4567 * va3[1]
SMLAL v16.4s, v28.4h, v4.h[1] // vacc4x0123 += vb0123 * va4[1]
SMLAL2 v17.4s, v28.8h, v4.h[1] // vacc4x4567 += vb4567 * va4[1]
SMLAL v18.4s, v28.4h, v5.h[1] // vacc5x0123 += vb0123 * va5[1]
SMLAL2 v19.4s, v28.8h, v5.h[1] // vacc5x4567 += vb4567 * va5[1]
SMLAL v20.4s, v28.4h, v6.h[1] // vacc6x0123 += vb0123 * va6[1]
SMLAL2 v21.4s, v28.8h, v6.h[1] // vacc6x4567 += vb4567 * va6[1]
SMLAL v22.4s, v28.4h, v7.h[1] // vacc7x0123 += vb0123 * va7[1]
SMLAL2 v23.4s, v28.8h, v7.h[1] // vacc7x4567 += vb4567 * va7[1]
B.LS 2f
// Channel 2
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[2] // vacc0x0123 += vb0123 * va0[2]
SMLAL2 v9.4s, v27.8h, v0.h[2] // vacc0x4567 += vb4567 * va0[2]
SMLAL v10.4s, v27.4h, v1.h[2] // vacc1x0123 += vb0123 * va1[2]
SMLAL2 v11.4s, v27.8h, v1.h[2] // vacc1x4567 += vb4567 * va1[2]
SMLAL v12.4s, v27.4h, v2.h[2] // vacc2x0123 += vb0123 * va2[2]
SMLAL2 v13.4s, v27.8h, v2.h[2] // vacc2x4567 += vb4567 * va2[2]
SMLAL v14.4s, v27.4h, v3.h[2] // vacc3x0123 += vb0123 * va3[2]
SMLAL2 v15.4s, v27.8h, v3.h[2] // vacc3x4567 += vb4567 * va3[2]
SMLAL v16.4s, v27.4h, v4.h[2] // vacc4x0123 += vb0123 * va4[2]
SMLAL2 v17.4s, v27.8h, v4.h[2] // vacc4x4567 += vb4567 * va4[2]
SMLAL v18.4s, v27.4h, v5.h[2] // vacc5x0123 += vb0123 * va5[2]
SMLAL2 v19.4s, v27.8h, v5.h[2] // vacc5x4567 += vb4567 * va5[2]
SMLAL v20.4s, v27.4h, v6.h[2] // vacc6x0123 += vb0123 * va6[2]
SMLAL2 v21.4s, v27.8h, v6.h[2] // vacc6x4567 += vb4567 * va6[2]
SMLAL v22.4s, v27.4h, v7.h[2] // vacc7x0123 += vb0123 * va7[2]
SMLAL2 v23.4s, v27.8h, v7.h[2] // vacc7x4567 += vb4567 * va7[2]
CMP x2, -32
B.LO 2f
// Channel 3
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[3] // vacc0x0123 += vb0123 * va0[3]
SMLAL2 v9.4s, v28.8h, v0.h[3] // vacc0x4567 += vb4567 * va0[3]
SMLAL v10.4s, v28.4h, v1.h[3] // vacc1x0123 += vb0123 * va1[3]
SMLAL2 v11.4s, v28.8h, v1.h[3] // vacc1x4567 += vb4567 * va1[3]
SMLAL v12.4s, v28.4h, v2.h[3] // vacc2x0123 += vb0123 * va2[3]
SMLAL2 v13.4s, v28.8h, v2.h[3] // vacc2x4567 += vb4567 * va2[3]
SMLAL v14.4s, v28.4h, v3.h[3] // vacc3x0123 += vb0123 * va3[3]
SMLAL2 v15.4s, v28.8h, v3.h[3] // vacc3x4567 += vb4567 * va3[3]
SMLAL v16.4s, v28.4h, v4.h[3] // vacc4x0123 += vb0123 * va4[3]
SMLAL2 v17.4s, v28.8h, v4.h[3] // vacc4x4567 += vb4567 * va4[3]
SMLAL v18.4s, v28.4h, v5.h[3] // vacc5x0123 += vb0123 * va5[3]
SMLAL2 v19.4s, v28.8h, v5.h[3] // vacc5x4567 += vb4567 * va5[3]
SMLAL v20.4s, v28.4h, v6.h[3] // vacc6x0123 += vb0123 * va6[3]
SMLAL2 v21.4s, v28.8h, v6.h[3] // vacc6x4567 += vb4567 * va6[3]
SMLAL v22.4s, v28.4h, v7.h[3] // vacc7x0123 += vb0123 * va7[3]
SMLAL2 v23.4s, v28.8h, v7.h[3] // vacc7x4567 += vb4567 * va7[3]
B.LS 2f
// Channel 4
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[4] // vacc0x0123 += vb0123 * va0[4]
SMLAL2 v9.4s, v27.8h, v0.h[4] // vacc0x4567 += vb4567 * va0[4]
SMLAL v10.4s, v27.4h, v1.h[4] // vacc1x0123 += vb0123 * va1[4]
SMLAL2 v11.4s, v27.8h, v1.h[4] // vacc1x4567 += vb4567 * va1[4]
SMLAL v12.4s, v27.4h, v2.h[4] // vacc2x0123 += vb0123 * va2[4]
SMLAL2 v13.4s, v27.8h, v2.h[4] // vacc2x4567 += vb4567 * va2[4]
SMLAL v14.4s, v27.4h, v3.h[4] // vacc3x0123 += vb0123 * va3[4]
SMLAL2 v15.4s, v27.8h, v3.h[4] // vacc3x4567 += vb4567 * va3[4]
SMLAL v16.4s, v27.4h, v4.h[4] // vacc4x0123 += vb0123 * va4[4]
SMLAL2 v17.4s, v27.8h, v4.h[4] // vacc4x4567 += vb4567 * va4[4]
SMLAL v18.4s, v27.4h, v5.h[4] // vacc5x0123 += vb0123 * va5[4]
SMLAL2 v19.4s, v27.8h, v5.h[4] // vacc5x4567 += vb4567 * va5[4]
SMLAL v20.4s, v27.4h, v6.h[4] // vacc6x0123 += vb0123 * va6[4]
SMLAL2 v21.4s, v27.8h, v6.h[4] // vacc6x4567 += vb4567 * va6[4]
SMLAL v22.4s, v27.4h, v7.h[4] // vacc7x0123 += vb0123 * va7[4]
SMLAL2 v23.4s, v27.8h, v7.h[4] // vacc7x4567 += vb4567 * va7[4]
CMP x2, -16
B.LO 2f
// Channel 5
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[5] // vacc0x0123 += vb0123 * va0[5]
SMLAL2 v9.4s, v28.8h, v0.h[5] // vacc0x4567 += vb4567 * va0[5]
SMLAL v10.4s, v28.4h, v1.h[5] // vacc1x0123 += vb0123 * va1[5]
SMLAL2 v11.4s, v28.8h, v1.h[5] // vacc1x4567 += vb4567 * va1[5]
SMLAL v12.4s, v28.4h, v2.h[5] // vacc2x0123 += vb0123 * va2[5]
SMLAL2 v13.4s, v28.8h, v2.h[5] // vacc2x4567 += vb4567 * va2[5]
SMLAL v14.4s, v28.4h, v3.h[5] // vacc3x0123 += vb0123 * va3[5]
SMLAL2 v15.4s, v28.8h, v3.h[5] // vacc3x4567 += vb4567 * va3[5]
SMLAL v16.4s, v28.4h, v4.h[5] // vacc4x0123 += vb0123 * va4[5]
SMLAL2 v17.4s, v28.8h, v4.h[5] // vacc4x4567 += vb4567 * va4[5]
SMLAL v18.4s, v28.4h, v5.h[5] // vacc5x0123 += vb0123 * va5[5]
SMLAL2 v19.4s, v28.8h, v5.h[5] // vacc5x4567 += vb4567 * va5[5]
SMLAL v20.4s, v28.4h, v6.h[5] // vacc6x0123 += vb0123 * va6[5]
SMLAL2 v21.4s, v28.8h, v6.h[5] // vacc6x4567 += vb4567 * va6[5]
SMLAL v22.4s, v28.4h, v7.h[5] // vacc7x0123 += vb0123 * va7[5]
SMLAL2 v23.4s, v28.8h, v7.h[5] // vacc7x4567 += vb4567 * va7[5]
B.LS 2f
// Channel 6
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[6] // vacc0x0123 += vb0123 * va0[6]
SMLAL2 v9.4s, v27.8h, v0.h[6] // vacc0x4567 += vb4567 * va0[6]
SMLAL v10.4s, v27.4h, v1.h[6] // vacc1x0123 += vb0123 * va1[6]
SMLAL2 v11.4s, v27.8h, v1.h[6] // vacc1x4567 += vb4567 * va1[6]
SMLAL v12.4s, v27.4h, v2.h[6] // vacc2x0123 += vb0123 * va2[6]
SMLAL2 v13.4s, v27.8h, v2.h[6] // vacc2x4567 += vb4567 * va2[6]
SMLAL v14.4s, v27.4h, v3.h[6] // vacc3x0123 += vb0123 * va3[6]
SMLAL2 v15.4s, v27.8h, v3.h[6] // vacc3x4567 += vb4567 * va3[6]
SMLAL v16.4s, v27.4h, v4.h[6] // vacc4x0123 += vb0123 * va4[6]
SMLAL2 v17.4s, v27.8h, v4.h[6] // vacc4x4567 += vb4567 * va4[6]
SMLAL v18.4s, v27.4h, v5.h[6] // vacc5x0123 += vb0123 * va5[6]
SMLAL2 v19.4s, v27.8h, v5.h[6] // vacc5x4567 += vb4567 * va5[6]
SMLAL v20.4s, v27.4h, v6.h[6] // vacc6x0123 += vb0123 * va6[6]
SMLAL2 v21.4s, v27.8h, v6.h[6] // vacc6x4567 += vb4567 * va6[6]
SMLAL v22.4s, v27.4h, v7.h[6] // vacc7x0123 += vb0123 * va7[6]
SMLAL2 v23.4s, v27.8h, v7.h[6] // vacc7x4567 += vb4567 * va7[6]
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 4
#endif
2:
LSL x16, x16, 2
LD1 {v24.4s}, [x6], 16
LD1 {v25.4s}, [x6]
SCVTF v8.4s, v8.4s
SCVTF v9.4s, v9.4s
SCVTF v10.4s, v10.4s
SCVTF v11.4s, v11.4s
SCVTF v12.4s, v12.4s
SCVTF v13.4s, v13.4s
SCVTF v14.4s, v14.4s
SCVTF v15.4s, v15.4s
SCVTF v16.4s, v16.4s
SCVTF v17.4s, v17.4s
SCVTF v18.4s, v18.4s
SCVTF v19.4s, v19.4s
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMUL v8.4s, v8.4s, v26.4s
FMUL v9.4s, v9.4s, v30.4s
FMUL v10.4s, v10.4s, v26.4s
FMUL v11.4s, v11.4s, v30.4s
FMUL v12.4s, v12.4s, v26.4s
FMUL v13.4s, v13.4s, v30.4s
FMUL v14.4s, v14.4s, v26.4s
FMUL v15.4s, v15.4s, v30.4s
FMUL v16.4s, v16.4s, v26.4s
FMUL v17.4s, v17.4s, v30.4s
FMUL v18.4s, v18.4s, v26.4s
FMUL v19.4s, v19.4s, v30.4s
FMUL v20.4s, v20.4s, v26.4s
FMUL v21.4s, v21.4s, v30.4s
FMUL v22.4s, v22.4s, v26.4s
FMUL v23.4s, v23.4s, v30.4s
FADD v8.4s, v8.4s, v24.4s
FADD v9.4s, v9.4s, v25.4s
FADD v10.4s, v10.4s, v24.4s
FADD v11.4s, v11.4s, v25.4s
FADD v12.4s, v12.4s, v24.4s
FADD v13.4s, v13.4s, v25.4s
FADD v14.4s, v14.4s, v24.4s
FADD v15.4s, v15.4s, v25.4s
FADD v16.4s, v16.4s, v24.4s
FADD v17.4s, v17.4s, v25.4s
FADD v18.4s, v18.4s, v24.4s
FADD v19.4s, v19.4s, v25.4s
FADD v20.4s, v20.4s, v24.4s
FADD v21.4s, v21.4s, v25.4s
FADD v22.4s, v22.4s, v24.4s
FADD v23.4s, v23.4s, v25.4s
// Compute c0-c7
ADD x9, x7, x16
CMP x0, 2
CSEL x9, x7, x9, LO
ADD x10, x9, x16
CSEL x10, x9, x10, LS
ADD x11, x10, x16
CMP x0, 4
CSEL x11, x10, x11, LO
ADD x12, x11, x16
CSEL x12, x11, x12, LS
ADD x13, x12, x16
CMP x0, 6
CSEL x13, x12, x13, LO
ADD x14, x13, x16
CSEL x14, x13, x14, LS
ADD x15, x14, x16
CMP x0, 8
CSEL x15, x14, x15, NE
CMP x1, 8
B.NE 4f
ST1 {v8.4s}, [x7], 16
ST1 {v9.4s}, [x7]
ST1 {v10.4s}, [x9], 16
ST1 {v11.4s}, [x9]
ST1 {v12.4s}, [x10], 16
ST1 {v13.4s}, [x10]
ST1 {v14.4s}, [x11], 16
ST1 {v15.4s}, [x11]
ST1 {v16.4s}, [x12], 16
ST1 {v17.4s}, [x12]
ST1 {v18.4s}, [x13], 16
ST1 {v19.4s}, [x13]
ST1 {v20.4s}, [x14], 16
ST1 {v21.4s}, [x14]
ST1 {v22.4s}, [x15], 16
ST1 {v23.4s}, [x15]
LDP d9, d8, [sp, -64]
LDP d11, d10, [sp, -48]
LDP d13, d12, [sp, -32]
LDP d15, d14, [sp, -16]
RET
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 3
#endif
4:
CMP x1, 4
B.LO 5f
ST1 {v8.4s}, [x7], 16
ST1 {v10.4s}, [x9], 16
ST1 {v12.4s}, [x10], 16
ST1 {v14.4s}, [x11], 16
ST1 {v16.4s}, [x12], 16
ST1 {v18.4s}, [x13], 16
ST1 {v20.4s}, [x14], 16
ST1 {v22.4s}, [x15], 16
SUB x1, x1, 4
MOV V8.16b, V9.16b
MOV v10.16b, v11.16b
MOV v12.16b, V13.16b
MOV V14.16b, V15.16b
MOV V16.16b, V17.16b
MOV V18.16b, V19.16b
MOV V20.16b, V21.16b
MOV V22.16b, V23.16b
5:
CMP x1, 2
B.LO 6f
ST1 {v8.2s}, [x7], 8
ST1 {v10.2s}, [x9], 8
ST1 {v12.2s}, [x10], 8
ST1 {v14.2s}, [x11], 8
ST1 {v16.2s}, [x12], 8
ST1 {v18.2s}, [x13], 8
ST1 {v20.2s}, [x14], 8
ST1 {v22.2s}, [x15], 8
SUB x1, x1, 2
EXT v8.16b, v8.16b, v8.16b, 8
EXT v10.16b, v10.16b, v10.16b, 8
EXT v12.16b, v12.16b, v12.16b, 8
EXT V14.16b, V14.16b, V14.16b, 8
EXT V16.16b, V16.16b, V16.16b, 8
EXT V18.16b, V18.16b, V18.16b, 8
EXT V20.16b, V20.16b, V20.16b, 8
EXT V22.16b, V22.16b, V22.16b, 8
6:
CMP x1, 1
B.LO 7f
ST1 {v8.s}[0], [x7]
ST1 {v10.s}[0], [x9]
ST1 {v12.s}[0], [x10]
ST1 {v14.s}[0], [x11]
ST1 {v16.s}[0], [x12]
ST1 {v18.s}[0], [x13]
ST1 {v20.s}[0], [x14]
ST1 {v22.s}[0], [x15]
7:
LDP d9, d8, [sp, -64]
LDP d11, d10, [sp, -48]
LDP d13, d12, [sp, -32]
LDP d15, d14, [sp, -16]
RET
END_FUNCTION pytorch_q8gemm_dq_ukernel_8x8__aarch64_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 17,365 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm/4x8-dq-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
# r0 mr
# r1 nr
# r2 k
# r3 a
# r6 a_stride
# d14 a_zero_point
# d15 b_zero_point
## Stack
# 4 quantization_params
# 4 c_stride
# 4 c
# 4 b
# 4 w
# 4 a_stride
# --
# 16 r4-r7
# 64 d8-d18
.syntax unified
# Args passed via stack.
# TOS
# |-----------|
# |a_stride | 0
# |w | 4
# |c | 8
# |c_stride | 12
# |out ch indx| 16
# |params | 20
# |-----------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r8 and d8-d15 on stack
# |-----------|
# |d8 - d15 | 0
# |r4 - r7 | 64
# |a_stride | 80
# |w | 84
# |b | 88
# |c | 92
# |c_stride | 96
# |out ch indx| 100
# |params | 104
# |-----------|
#
# void pytorch_q8gemm_ukernel_4x8__aarch32_neon(
# size_t mr,
# size_t nr,
# size_t k,
# const uint8_t* restrict a,
# size_t a_stride,
# const void* restrict w,
# const float* restrict b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8gemm_dq_ukernel_4x8__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load w
# - ip = w
LDR ip, [sp, 4]
ADD ip, ip, 32
PUSH {r4, r5, r6, r7}
VPUSH {d8-d15}
# Load output channel index
LDR r5, [sp, 100]
# Load quantization params
# - r7 = quantization_params
LDR r7, [sp, 104]
# Load input_zero_point
VLD1.8 {d14[]}, [r7]
ADD r7, r7, 4
# Load pointer to per channel zero points array
# Post-index: After load increment r7 by 4
LDR r4, [r7], #4
# Byte offset of output channel index for requant scale.
LSL r6, r5, 2
VEOR q8, q8, q8
VEOR q9, q9, q9
# Load pointer to per channel requant scale
LDR r7, [r7]
# Add output_channel_index to the b_zero_point pointer
ADD r4, r4, r5
# Now r7 has the base_addr + offset for multipliers
ADD r7, r7, r6
# Load a_stride
# - r6 = a_stride
LDR r6, [sp, 80]
VEOR q10, q10, q10
VEOR q11, q11, q11
VLD1.8 {d15}, [r4]
CMP r0, 2
ADD r4, r3, r6
MOVLO r4, r3
ADD r5, r4, r6
MOVLS r5, r4
CMP r0, 4
ADD r6, r5, r6
MOVNE r6, r5
VEOR q12, q12, q12
VEOR q13, q13, q13
VEOR q14, q14, q14
VEOR q15, q15, q15
SUBS r2, r2, 8
BLO 1f
.p2align 5
0:
# Load a0
# - d1 = a0
VLD1.8 {d1}, [r3]!
# Load a1
# - d3 = a1
VLD1.8 {d3}, [r4]!
# Load b0-b7 (channel 0)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# Load a2
# - d5 = a2
VLD1.8 {d5}, [r5]!
# q0 = va0 = a0
SUB_ZERO_POINT q0, d1, d14
# Load a3
# - d7 = a3
VLD1.8 {d7}, [r6]!
# q1 = va1 = a1
SUB_ZERO_POINT q1, d3, d14
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 0)
# - d9 = vb4567 (channel 0)
VSUBL.U8 q4, d9, d15
# q2 = va2 = a2
SUB_ZERO_POINT q2, d5, d14
# q3 = va3 = a3
SUB_ZERO_POINT q3, d7, d14
### Channel 0 ###
# Load b0-b7 (channel 1)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[0]
VMLAL.S16 q8, d8, d0[0]
# vacc0x4567 += vb4567 * va0[0]
VMLAL.S16 q9, d9, d0[0]
# vacc1x0123 += vb0123 * va1[0]
VMLAL.S16 q10, d8, d2[0]
# vacc1x4567 += vb4567 * va1[0]
VMLAL.S16 q11, d9, d2[0]
# vacc2x0123 += vb0123 * va2[0]
VMLAL.S16 q12, d8, d4[0]
# vacc2x4567 += vb4567 * va2[0]
VMLAL.S16 q13, d9, d4[0]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 1)
# - d11 = vb4567 (channel 1)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[0]
VMLAL.S16 q14, d8, d6[0]
# vacc3x4567 += vb4567 * va3[0]
VMLAL.S16 q15, d9, d6[0]
### Channel 1 ###
# Load b0-b7 (channel 2)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[1]
VMLAL.S16 q8, d10, d0[1]
# vacc0x4567 += vb4567 * va0[1]
VMLAL.S16 q9, d11, d0[1]
# vacc1x0123 += vb0123 * va1[1]
VMLAL.S16 q10, d10, d2[1]
# vacc1x4567 += vb4567 * va1[1]
VMLAL.S16 q11, d11, d2[1]
# vacc2x0123 += vb0123 * va2[1]
VMLAL.S16 q12, d10, d4[1]
# vacc2x4567 += vb4567 * va2[1]
VMLAL.S16 q13, d11, d4[1]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 2)
# - d9 = vb4567 (channel 2)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[1]
VMLAL.S16 q14, d10, d6[1]
# vacc3x4567 += vb4567 * va3[1]
VMLAL.S16 q15, d11, d6[1]
### Channel 2 ###
# Load b0-b7 (channel 3)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[2]
VMLAL.S16 q8, d8, d0[2]
# vacc0x4567 += vb4567 * va0[2]
VMLAL.S16 q9, d9, d0[2]
# vacc1x0123 += vb0123 * va1[2]
VMLAL.S16 q10, d8, d2[2]
# vacc1x4567 += vb4567 * va1[2]
VMLAL.S16 q11, d9, d2[2]
# vacc2x0123 += vb0123 * va2[2]
VMLAL.S16 q12, d8, d4[2]
# vacc2x4567 += vb4567 * va2[2]
VMLAL.S16 q13, d9, d4[2]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 3)
# - d11 = vb4567 (channel 3)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[2]
VMLAL.S16 q14, d8, d6[2]
# vacc3x4567 += vb4567 * va3[2]
VMLAL.S16 q15, d9, d6[2]
### Channel 3 ###
# Load b0-b7 (channel 4)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[3]
VMLAL.S16 q8, d10, d0[3]
# vacc0x4567 += vb4567 * va0[3]
VMLAL.S16 q9, d11, d0[3]
# vacc1x0123 += vb0123 * va1[3]
VMLAL.S16 q10, d10, d2[3]
# vacc1x4567 += vb4567 * va1[3]
VMLAL.S16 q11, d11, d2[3]
# vacc2x0123 += vb0123 * va2[3]
VMLAL.S16 q12, d10, d4[3]
# vacc2x4567 += vb4567 * va2[3]
VMLAL.S16 q13, d11, d4[3]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 4)
# - d11 = vb4567 (channel 4)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[3]
VMLAL.S16 q14, d10, d6[3]
# vacc3x4567 += vb4567 * va3[3]
VMLAL.S16 q15, d11, d6[3]
### Channel 4 ###
# Load b0-b7 (channel 5)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[4]
VMLAL.S16 q8, d8, d1[0]
# vacc0x4567 += vb4567 * va0[4]
VMLAL.S16 q9, d9, d1[0]
# vacc1x0123 += vb0123 * va1[4]
VMLAL.S16 q10, d8, d3[0]
# vacc1x4567 += vb4567 * va1[4]
VMLAL.S16 q11, d9, d3[0]
# vacc2x0123 += vb0123 * va2[4]
VMLAL.S16 q12, d8, d5[0]
# vacc2x4567 += vb4567 * va2[4]
VMLAL.S16 q13, d9, d5[0]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 5)
# - d9 = vb4567 (channel 5)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[4]
VMLAL.S16 q14, d8, d7[0]
# vacc3x4567 += vb4567 * va3[4]
VMLAL.S16 q15, d9, d7[0]
### Channel 5 ###
# Load b0-b7 (channel 6)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[5]
VMLAL.S16 q8, d10, d1[1]
# vacc0x4567 += vb4567 * va0[5]
VMLAL.S16 q9, d11, d1[1]
# vacc1x0123 += vb0123 * va1[5]
VMLAL.S16 q10, d10, d3[1]
# vacc1x4567 += vb4567 * va1[5]
VMLAL.S16 q11, d11, d3[1]
# vacc2x0123 += vb0123 * va2[5]
VMLAL.S16 q12, d10, d5[1]
# vacc2x4567 += vb4567 * va2[5]
VMLAL.S16 q13, d11, d5[1]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 6)
# - d9 = vb4567 (channel 6)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[5]
VMLAL.S16 q14, d10, d7[1]
# vacc3x4567 += vb4567 * va3[5]
VMLAL.S16 q15, d11, d7[1]
### Channel 6 ###
# Load b0-b7 (channel 7)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[6]
VMLAL.S16 q8, d8, d1[2]
# vacc0x4567 += vb4567 * va0[6]
VMLAL.S16 q9, d9, d1[2]
# vacc1x0123 += vb0123 * va1[6]
VMLAL.S16 q10, d8, d3[2]
# vacc1x4567 += vb4567 * va1[6]
VMLAL.S16 q11, d9, d3[2]
# vacc2x0123 += vb0123 * va2[6]
VMLAL.S16 q12, d8, d5[2]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 7)
# - d11 = vb4567 (channel 7)
VSUBL.U8 q5, d11, d15
# vacc2x4567 += vb4567 * va2[6]
VMLAL.S16 q13, d9, d5[2]
# vacc3x0123 += vb0123 * va3[6]
VMLAL.S16 q14, d8, d7[2]
# vacc3x4567 += vb4567 * va3[6]
VMLAL.S16 q15, d9, d7[2]
### Channel 8 ###
SUBS r2, r2, 8
# vacc0x0123 += vb0123 * va0[7]
VMLAL.S16 q8, d10, d1[3]
# vacc0x4567 += vb4567 * va0[7]
VMLAL.S16 q9, d11, d1[3]
# vacc1x0123 += vb0123 * va1[7]
VMLAL.S16 q10, d10, d3[3]
# vacc1x4567 += vb4567 * va1[7]
VMLAL.S16 q11, d11, d3[3]
# vacc2x0123 += vb0123 * va2[7]
VMLAL.S16 q12, d10, d5[3]
# vacc2x4567 += vb4567 * va2[7]
VMLAL.S16 q13, d11, d5[3]
# vacc3x0123 += vb0123 * va3[7]
VMLAL.S16 q14, d10, d7[3]
# vacc3x4567 += vb4567 * va3[7]
VMLAL.S16 q15, d11, d7[3]
BHS 0b
1:
CMP r2, -8
BEQ 2f
# Adjust a0, a1, a2, a3
ADD r3, r2
ADD r4, r2
ADD r5, r2
ADD r6, r2
# a_shift = 8 * k - 64
LSL r2, r2, 3
VDUP.32 d13, r2
# Load a0
# - d1 = a0
VLD1.8 {d1}, [r3]
# Load a1
# - d3 = a1
VLD1.8 {d3}, [r4]
# Load b0-b7 (channel 0)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# Load a2
# - d5 = a2
VLD1.8 {d5}, [r5]
# q0 = va0 = a0
VSHL.U64 d1, d1, d13
SUB_ZERO_POINT q0, d1, d14
# Load a3
# - d7 = a3
VLD1.8 {d7}, [r6]
# q1 = va1 = a1
VSHL.U64 d3, d3, d13
SUB_ZERO_POINT q1, d3, d14
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 0)
# - d9 = vb4567 (channel 0)
VSUBL.U8 q4, d9, d15
# q2 = va2 = a2
VSHL.U64 d5, d5, d13
SUB_ZERO_POINT q2, d5, d14
# q3 = va3 = a3
VSHL.U64 d7, d7, d13
SUB_ZERO_POINT q3, d7, d14
### Channel 0 ###
# vacc0x0123 += vb0123 * va0[0]
VMLAL.S16 q8, d8, d0[0]
# vacc0x4567 += vb4567 * va0[0]
VMLAL.S16 q9, d9, d0[0]
# vacc1x0123 += vb0123 * va1[0]
VMLAL.S16 q10, d8, d2[0]
# vacc1x4567 += vb4567 * va1[0]
VMLAL.S16 q11, d9, d2[0]
# vacc2x0123 += vb0123 * va2[0]
VMLAL.S16 q12, d8, d4[0]
# vacc2x4567 += vb4567 * va2[0]
VMLAL.S16 q13, d9, d4[0]
# vacc3x0123 += vb0123 * va3[0]
VMLAL.S16 q14, d8, d6[0]
# vacc3x4567 += vb4567 * va3[0]
VMLAL.S16 q15, d9, d6[0]
CMP r2, -48
BLO 2f
### Channel 1 ###
# Load b0-b7 (channel 1)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 1)
# - d11 = vb4567 (channel 1)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[1]
VMLAL.S16 q8, d10, d0[1]
# vacc0x4567 += vb4567 * va0[1]
VMLAL.S16 q9, d11, d0[1]
# vacc1x0123 += vb0123 * va1[1]
VMLAL.S16 q10, d10, d2[1]
# vacc1x4567 += vb4567 * va1[1]
VMLAL.S16 q11, d11, d2[1]
# vacc2x0123 += vb0123 * va2[1]
VMLAL.S16 q12, d10, d4[1]
# vacc2x4567 += vb4567 * va2[1]
VMLAL.S16 q13, d11, d4[1]
# vacc3x0123 += vb0123 * va3[1]
VMLAL.S16 q14, d10, d6[1]
# vacc3x4567 += vb4567 * va3[1]
VMLAL.S16 q15, d11, d6[1]
### Channel 2 ###
BLS 2f
# Load b0-b7 (channel 2)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 2)
# - d9 = vb4567 (channel 2)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[2]
VMLAL.S16 q8, d8, d0[2]
# vacc0x4567 += vb4567 * va0[2]
VMLAL.S16 q9, d9, d0[2]
# vacc1x0123 += vb0123 * va1[2]
VMLAL.S16 q10, d8, d2[2]
# vacc1x4567 += vb4567 * va1[2]
VMLAL.S16 q11, d9, d2[2]
# vacc2x0123 += vb0123 * va2[2]
VMLAL.S16 q12, d8, d4[2]
# vacc2x4567 += vb4567 * va2[2]
VMLAL.S16 q13, d9, d4[2]
# vacc3x0123 += vb0123 * va3[2]
VMLAL.S16 q14, d8, d6[2]
# vacc3x4567 += vb4567 * va3[2]
VMLAL.S16 q15, d9, d6[2]
### Channel 3 ###
CMP r2, -32
BLO 2f
# Load b0-b7 (channel 3)
# - d9 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 3)
# - d9 = vb4567 (channel 3)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[3]
VMLAL.S16 q8, d10, d0[3]
# vacc0x4567 += vb4567 * va0[3]
VMLAL.S16 q9, d11, d0[3]
# vacc1x0123 += vb0123 * va1[3]
VMLAL.S16 q10, d10, d2[3]
# vacc1x4567 += vb4567 * va1[3]
VMLAL.S16 q11, d11, d2[3]
# vacc2x0123 += vb0123 * va2[3]
VMLAL.S16 q12, d10, d4[3]
# vacc2x4567 += vb4567 * va2[3]
VMLAL.S16 q13, d11, d4[3]
# vacc3x0123 += vb0123 * va3[3]
VMLAL.S16 q14, d10, d6[3]
# vacc3x4567 += vb4567 * va3[3]
VMLAL.S16 q15, d11, d6[3]
### Channel 4 ###
BLS 2f
# Load b0-b7 (channel 4)
# - d11 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 4)
# - d11 = vb4567 (channel 4)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[4]
VMLAL.S16 q8, d8, d1[0]
# vacc0x4567 += vb4567 * va0[4]
VMLAL.S16 q9, d9, d1[0]
# vacc1x0123 += vb0123 * va1[4]
VMLAL.S16 q10, d8, d3[0]
# vacc1x4567 += vb4567 * va1[4]
VMLAL.S16 q11, d9, d3[0]
# vacc2x0123 += vb0123 * va2[4]
VMLAL.S16 q12, d8, d5[0]
# vacc2x4567 += vb4567 * va2[4]
VMLAL.S16 q13, d9, d5[0]
# vacc3x0123 += vb0123 * va3[4]
VMLAL.S16 q14, d8, d7[0]
# vacc3x4567 += vb4567 * va3[4]
VMLAL.S16 q15, d9, d7[0]
### Channel 5 ###
CMP r2, -16
BLO 2f
# Load b0-b7 (channel 5)
# - d13 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 5)
# - d11 = vb4567 (channel 5)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[5]
VMLAL.S16 q8, d10, d1[1]
# vacc0x4567 += vb4567 * va0[5]
VMLAL.S16 q9, d11, d1[1]
# vacc1x0123 += vb0123 * va1[5]
VMLAL.S16 q10, d10, d3[1]
# vacc1x4567 += vb4567 * va1[5]
VMLAL.S16 q11, d11, d3[1]
# vacc2x0123 += vb0123 * va2[5]
VMLAL.S16 q12, d10, d5[1]
# vacc2x4567 += vb4567 * va2[5]
VMLAL.S16 q13, d11, d5[1]
# vacc3x0123 += vb0123 * va3[5]
VMLAL.S16 q14, d10, d7[1]
# vacc3x4567 += vb4567 * va3[5]
VMLAL.S16 q15, d11, d7[1]
### Channel 6 ###
BLS 2f
# Load b0-b7 (channel 6)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 6)
# - d9 = vb4567 (channel 6)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[6]
VMLAL.S16 q8, d8, d1[2]
# vacc0x4567 += vb4567 * va0[6]
VMLAL.S16 q9, d9, d1[2]
# vacc1x0123 += vb0123 * va1[6]
VMLAL.S16 q10, d8, d3[2]
# vacc1x4567 += vb4567 * va1[6]
VMLAL.S16 q11, d9, d3[2]
# vacc2x0123 += vb0123 * va2[6]
VMLAL.S16 q12, d8, d5[2]
# vacc2x4567 += vb4567 * va2[6]
VMLAL.S16 q13, d9, d5[2]
# vacc3x0123 += vb0123 * va3[6]
VMLAL.S16 q14, d8, d7[2]
# vacc3x4567 += vb4567 * va3[6]
VMLAL.S16 q15, d9, d7[2]
.p2align 4
2:
LDR r6, [sp, 88]
# Load q6: vmultiplier_c0123
VLD1.32 {d12, d13}, [r7]!
VCVT.F32.S32 q8, q8
VCVT.F32.S32 q9, q9
VCVT.F32.S32 q10, q10
# Load q7: vmultiplier_c4567
VLD1.32 {d14, d15}, [r7]
VLD1.32 {q0, q1}, [r6]
VCVT.F32.S32 q11, q11
VCVT.F32.S32 q12, q12
VCVT.F32.S32 q13, q13
VCVT.F32.S32 q14, q14
VCVT.F32.S32 q15, q15
VMUL.F32 q8, q8, q6
VMUL.F32 q9, q9, q7
VMUL.F32 q10, q10, q6
VMUL.F32 q11, q11, q7
VMUL.F32 q12, q12, q6
VMUL.F32 q13, q13, q7
VMUL.F32 q14, q14, q6
VMUL.F32 q15, q15, q7
VADD.F32 q8, q8, q0
VADD.F32 q9, q9, q1
VADD.F32 q10, q10, q0
VADD.F32 q11, q11, q1
VADD.F32 q12, q12, q0
VADD.F32 q13, q13, q1
VADD.F32 q14, q14, q0
VADD.F32 q15, q15, q1
# Load c, c_stride:
# - r2 = c
# - r3 = c_stride
LDRD r2, r3, [sp, 92]
LSL r3, r3, 2
ADD r4, r2, r3
CMP r0, 2
MOVLO r4, r2
ADD r5, r4, r3
MOVLS r5, r4
CMP r0, 4
ADD r3, r5, r3
MOVNE r3, r5
CMP r1, 8
BNE 4f
VST1.32 {q8}, [r2]!
VST1.32 {q10}, [r4]!
VST1.32 {q12}, [r5]!
VST1.32 {q14}, [r3]!
VST1.32 {q9}, [r2]
VST1.32 {q11}, [r4]
VST1.32 {q13}, [r5]
VST1.32 {q15}, [r3]
VPOP {d8-d15}
POP {r4, r5, r6, r7}
BX lr
.p2align 3
4:
CMP r1, 4
BLO 5f
VST1.32 {q8}, [r2]!
VST1.32 {q10}, [r4]!
VST1.32 {q12}, [r5]!
VST1.32 {q14}, [r3]!
SUB r1, 4
VMOV.32 q8, q9
VMOV.32 q10, q11
VMOV.32 q12, q13
VMOV.32 q14, q15
5:
CMP r1, 2
BLO 6f
VST1.32 {d16}, [r2]!
VST1.32 {d20}, [r4]!
VST1.32 {d24}, [r5]!
VST1.32 {d28}, [r3]!
SUB r1, 2
VEXT.32 q8, q8, 2
VEXT.32 q10, q10, 2
VEXT.32 q12, q12, 2
VEXT.32 q14, q14, 2
6:
TEQ r1, 0
BEQ 7f
VST1.32 {d16[0]}, [r2]!
VST1.32 {d20[0]}, [r4]!
VST1.32 {d24[0]}, [r5]!
VST1.32 {d28[0]}, [r3]!
7:
VPOP {d8-d15}
POP {r4, r5, r6, r7}
BX lr
END_FUNCTION pytorch_q8gemm_dq_ukernel_4x8__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 18,740 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm/4x8-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
.syntax unified
# Args passed via 4 registers (16 bytes)
# r0: mr
# r1: nr
# r2: k
# r3: a
#
# Args passed via stack.
# TOS
# |-----------|
# |a_stride | 0
# |w | 4
# |c | 8
# |c_stride | 12
# |out ch indx| 16
# |params | 20
# |-----------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r9 and d8-d15 on stack
# |-----------|
# |d8 - d15 | 0
# |r4 - r9 | 64
# |a_stride | 88
# |w | 92
# |c | 96
# |c_stride | 100
# |out ch indx| 104
# |params | 108
# |-----------|
#
#
# New Struct for pytorch_qnnp_conv_quantization_params
# kernel zp : 0 offset
# input zp : 2
# requantization_scale : 4
# output zp : 8
# output max : 10
# output min : 11
# vfmin : 12
# vfmax : 16
# vfmagic : 20
# vimagic : 24
#
# void pytorch_q8gemm_ukernel_4x8__aarch32_neon(
# size_t mr,
# size_t nr,
# size_t k,
# const uint8_t*restrict a,
# size_t a_stride,
# const void*restrict w,
# uint8_t*restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8gemm_ukernel_4x8__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load w
# - ip = w
LDR ip, [sp, 4]
PUSH {r4, r5, r6, r7, r8, r9}
# Load quantization params
# - r7 = quantization_params
LDR r7, [sp, 44]
VPUSH {d8-d15}
# Load bias0123, bias4567
VLDM ip!, {d16-d19}
# Load output channel index
LDR r5, [sp, 104]
# Load pointer to per channel zero points array
# Post-index: After load increment r7 by 4
LDR r4, [r7], #4
# Load a_zero_point:
# - d14 = a_zero_point
VLD1.8 {d14[]}, [r7]
# Load a_stride
# - r6 = a_stride
LDR r9, [sp, 88]
# Byte offset of output channel index for requant scale.
LSL r6, r5, 2
# Load pointer to per channel requant scale
# Register offset, load r7+4
LDR r8, [r7, 4]
# Add output_channel_index to the b_zero_point pointer
ADD r4, r4, r5
# Load b_zero_point:
# - d15 = b_zero_point
VLD1.8 {d15}, [r4]
# add 8 bytes to get to vfmax
ADD r7, r7, 12
CMP r0, 2
ADD r4, r3, r9
# Store in r8 pointer from where to load requant scale.
ADD r8, r8, r6
MOVLO r4, r3
ADD r5, r4, r9
# q10 := vacc1x0123
VMOV.I32 q10, q8
MOVLS r5, r4
# q11 := vacc1x4567
VMOV.I32 q11, q9
ADD r6, r5, r9
# q12 := vacc2x0123
VMOV.I32 q12, q8
CMP r0, 4
# q13 := vacc2x4567
VMOV.I32 q13, q9
MOVNE r6, r5
# q14 := vacc3x0123
VMOV.I32 q14, q8
SUBS r2, r2, 8
# q15 := vacc3x4567
VMOV.I32 q15, q9
BLO 1f
.p2align 5
0:
# Load a0
# - d1 = a0
VLD1.8 {d1}, [r3]!
# Load a1
# - d3 = a1
VLD1.8 {d3}, [r4]!
# Load b0-b7 (channel 0)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# Load a2
# - d5 = a2
VLD1.8 {d5}, [r5]!
# q0 = va0 = a0
SUB_ZERO_POINT q0, d1, d14
# Load a3
# - d7 = a3
VLD1.8 {d7}, [r6]!
# q1 = va1 = a1
SUB_ZERO_POINT q1, d3, d14
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 0)
# - d9 = vb4567 (channel 0)
VSUBL.U8 q4, d9, d15
# q2 = va2 = a2
SUB_ZERO_POINT q2, d5, d14
# q3 = va3 = a3
SUB_ZERO_POINT q3, d7, d14
### Channel 0 ###
# Load b0-b7 (channel 1)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[0]
VMLAL.S16 q8, d8, d0[0]
# vacc0x4567 += vb4567 * va0[0]
VMLAL.S16 q9, d9, d0[0]
# vacc1x0123 += vb0123 * va1[0]
VMLAL.S16 q10, d8, d2[0]
# vacc1x4567 += vb4567 * va1[0]
VMLAL.S16 q11, d9, d2[0]
# vacc2x0123 += vb0123 * va2[0]
VMLAL.S16 q12, d8, d4[0]
# vacc2x4567 += vb4567 * va2[0]
VMLAL.S16 q13, d9, d4[0]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 1)
# - d11 = vb4567 (channel 1)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[0]
VMLAL.S16 q14, d8, d6[0]
# vacc3x4567 += vb4567 * va3[0]
VMLAL.S16 q15, d9, d6[0]
### Channel 1 ###
# Load b0-b7 (channel 2)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[1]
VMLAL.S16 q8, d10, d0[1]
# vacc0x4567 += vb4567 * va0[1]
VMLAL.S16 q9, d11, d0[1]
# vacc1x0123 += vb0123 * va1[1]
VMLAL.S16 q10, d10, d2[1]
# vacc1x4567 += vb4567 * va1[1]
VMLAL.S16 q11, d11, d2[1]
# vacc2x0123 += vb0123 * va2[1]
VMLAL.S16 q12, d10, d4[1]
# vacc2x4567 += vb4567 * va2[1]
VMLAL.S16 q13, d11, d4[1]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 2)
# - d9 = vb4567 (channel 2)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[1]
VMLAL.S16 q14, d10, d6[1]
# vacc3x4567 += vb4567 * va3[1]
VMLAL.S16 q15, d11, d6[1]
### Channel 2 ###
# Load b0-b7 (channel 3)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[2]
VMLAL.S16 q8, d8, d0[2]
# vacc0x4567 += vb4567 * va0[2]
VMLAL.S16 q9, d9, d0[2]
# vacc1x0123 += vb0123 * va1[2]
VMLAL.S16 q10, d8, d2[2]
# vacc1x4567 += vb4567 * va1[2]
VMLAL.S16 q11, d9, d2[2]
# vacc2x0123 += vb0123 * va2[2]
VMLAL.S16 q12, d8, d4[2]
# vacc2x4567 += vb4567 * va2[2]
VMLAL.S16 q13, d9, d4[2]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 3)
# - d11 = vb4567 (channel 3)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[2]
VMLAL.S16 q14, d8, d6[2]
# vacc3x4567 += vb4567 * va3[2]
VMLAL.S16 q15, d9, d6[2]
### Channel 3 ###
# Load b0-b7 (channel 4)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[3]
VMLAL.S16 q8, d10, d0[3]
# vacc0x4567 += vb4567 * va0[3]
VMLAL.S16 q9, d11, d0[3]
# vacc1x0123 += vb0123 * va1[3]
VMLAL.S16 q10, d10, d2[3]
# vacc1x4567 += vb4567 * va1[3]
VMLAL.S16 q11, d11, d2[3]
# vacc2x0123 += vb0123 * va2[3]
VMLAL.S16 q12, d10, d4[3]
# vacc2x4567 += vb4567 * va2[3]
VMLAL.S16 q13, d11, d4[3]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 4)
# - d11 = vb4567 (channel 4)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[3]
VMLAL.S16 q14, d10, d6[3]
# vacc3x4567 += vb4567 * va3[3]
VMLAL.S16 q15, d11, d6[3]
### Channel 4 ###
# Load b0-b7 (channel 5)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[4]
VMLAL.S16 q8, d8, d1[0]
# vacc0x4567 += vb4567 * va0[4]
VMLAL.S16 q9, d9, d1[0]
# vacc1x0123 += vb0123 * va1[4]
VMLAL.S16 q10, d8, d3[0]
# vacc1x4567 += vb4567 * va1[4]
VMLAL.S16 q11, d9, d3[0]
# vacc2x0123 += vb0123 * va2[4]
VMLAL.S16 q12, d8, d5[0]
# vacc2x4567 += vb4567 * va2[4]
VMLAL.S16 q13, d9, d5[0]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 5)
# - d9 = vb4567 (channel 5)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[4]
VMLAL.S16 q14, d8, d7[0]
# vacc3x4567 += vb4567 * va3[4]
VMLAL.S16 q15, d9, d7[0]
### Channel 5 ###
# Load b0-b7 (channel 6)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[5]
VMLAL.S16 q8, d10, d1[1]
# vacc0x4567 += vb4567 * va0[5]
VMLAL.S16 q9, d11, d1[1]
# vacc1x0123 += vb0123 * va1[5]
VMLAL.S16 q10, d10, d3[1]
# vacc1x4567 += vb4567 * va1[5]
VMLAL.S16 q11, d11, d3[1]
# vacc2x0123 += vb0123 * va2[5]
VMLAL.S16 q12, d10, d5[1]
# vacc2x4567 += vb4567 * va2[5]
VMLAL.S16 q13, d11, d5[1]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 6)
# - d9 = vb4567 (channel 6)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[5]
VMLAL.S16 q14, d10, d7[1]
# vacc3x4567 += vb4567 * va3[5]
VMLAL.S16 q15, d11, d7[1]
### Channel 6 ###
# Load b0-b7 (channel 7)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[6]
VMLAL.S16 q8, d8, d1[2]
# vacc0x4567 += vb4567 * va0[6]
VMLAL.S16 q9, d9, d1[2]
# vacc1x0123 += vb0123 * va1[6]
VMLAL.S16 q10, d8, d3[2]
# vacc1x4567 += vb4567 * va1[6]
VMLAL.S16 q11, d9, d3[2]
# vacc2x0123 += vb0123 * va2[6]
VMLAL.S16 q12, d8, d5[2]
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 7)
# - d11 = vb4567 (channel 7)
VSUBL.U8 q5, d11, d15
# vacc2x4567 += vb4567 * va2[6]
VMLAL.S16 q13, d9, d5[2]
# vacc3x0123 += vb0123 * va3[6]
VMLAL.S16 q14, d8, d7[2]
# vacc3x4567 += vb4567 * va3[6]
VMLAL.S16 q15, d9, d7[2]
### Channel 8 ###
SUBS r2, r2, 8
# vacc0x0123 += vb0123 * va0[7]
VMLAL.S16 q8, d10, d1[3]
# vacc0x4567 += vb4567 * va0[7]
VMLAL.S16 q9, d11, d1[3]
# vacc1x0123 += vb0123 * va1[7]
VMLAL.S16 q10, d10, d3[3]
# vacc1x4567 += vb4567 * va1[7]
VMLAL.S16 q11, d11, d3[3]
# vacc2x0123 += vb0123 * va2[7]
VMLAL.S16 q12, d10, d5[3]
# vacc2x4567 += vb4567 * va2[7]
VMLAL.S16 q13, d11, d5[3]
# vacc3x0123 += vb0123 * va3[7]
VMLAL.S16 q14, d10, d7[3]
# vacc3x4567 += vb4567 * va3[7]
VMLAL.S16 q15, d11, d7[3]
BHS 0b
1:
CMP r2, -8
BEQ 2f
# Adjust a0, a1, a2, a3
ADD r3, r2
ADD r4, r2
ADD r5, r2
ADD r6, r2
# a_shift = 8 * k - 64
LSL r2, r2, 3
VDUP.32 d13, r2
# Load a0
# - d1 = a0
VLD1.8 {d1}, [r3]
# Load a1
# - d3 = a1
VLD1.8 {d3}, [r4]
# Load b0-b7 (channel 0)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# Load a2
# - d5 = a2
VLD1.8 {d5}, [r5]
# q0 = va0 = a0
VSHL.U64 d1, d1, d13
SUB_ZERO_POINT q0, d1, d14
# Load a3
# - d7 = a3
VLD1.8 {d7}, [r6]
# q1 = va1 = a1
VSHL.U64 d3, d3, d13
SUB_ZERO_POINT q1, d3, d14
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 0)
# - d9 = vb4567 (channel 0)
VSUBL.U8 q4, d9, d15
# q2 = va2 = a2
VSHL.U64 d5, d5, d13
SUB_ZERO_POINT q2, d5, d14
# q3 = va3 = a3
VSHL.U64 d7, d7, d13
SUB_ZERO_POINT q3, d7, d14
### Channel 0 ###
# vacc0x0123 += vb0123 * va0[0]
VMLAL.S16 q8, d8, d0[0]
# vacc0x4567 += vb4567 * va0[0]
VMLAL.S16 q9, d9, d0[0]
# vacc1x0123 += vb0123 * va1[0]
VMLAL.S16 q10, d8, d2[0]
# vacc1x4567 += vb4567 * va1[0]
VMLAL.S16 q11, d9, d2[0]
# vacc2x0123 += vb0123 * va2[0]
VMLAL.S16 q12, d8, d4[0]
# vacc2x4567 += vb4567 * va2[0]
VMLAL.S16 q13, d9, d4[0]
# vacc3x0123 += vb0123 * va3[0]
VMLAL.S16 q14, d8, d6[0]
# vacc3x4567 += vb4567 * va3[0]
VMLAL.S16 q15, d9, d6[0]
CMP r2, -48
BLO 2f
### Channel 1 ###
# Load b0-b7 (channel 1)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 1)
# - d11 = vb4567 (channel 1)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[1]
VMLAL.S16 q8, d10, d0[1]
# vacc0x4567 += vb4567 * va0[1]
VMLAL.S16 q9, d11, d0[1]
# vacc1x0123 += vb0123 * va1[1]
VMLAL.S16 q10, d10, d2[1]
# vacc1x4567 += vb4567 * va1[1]
VMLAL.S16 q11, d11, d2[1]
# vacc2x0123 += vb0123 * va2[1]
VMLAL.S16 q12, d10, d4[1]
# vacc2x4567 += vb4567 * va2[1]
VMLAL.S16 q13, d11, d4[1]
# vacc3x0123 += vb0123 * va3[1]
VMLAL.S16 q14, d10, d6[1]
# vacc3x4567 += vb4567 * va3[1]
VMLAL.S16 q15, d11, d6[1]
### Channel 2 ###
BLS 2f
# Load b0-b7 (channel 2)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 2)
# - d9 = vb4567 (channel 2)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[2]
VMLAL.S16 q8, d8, d0[2]
# vacc0x4567 += vb4567 * va0[2]
VMLAL.S16 q9, d9, d0[2]
# vacc1x0123 += vb0123 * va1[2]
VMLAL.S16 q10, d8, d2[2]
# vacc1x4567 += vb4567 * va1[2]
VMLAL.S16 q11, d9, d2[2]
# vacc2x0123 += vb0123 * va2[2]
VMLAL.S16 q12, d8, d4[2]
# vacc2x4567 += vb4567 * va2[2]
VMLAL.S16 q13, d9, d4[2]
# vacc3x0123 += vb0123 * va3[2]
VMLAL.S16 q14, d8, d6[2]
# vacc3x4567 += vb4567 * va3[2]
VMLAL.S16 q15, d9, d6[2]
### Channel 3 ###
CMP r2, -32
BLO 2f
# Load b0-b7 (channel 3)
# - d9 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 3)
# - d9 = vb4567 (channel 3)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[3]
VMLAL.S16 q8, d10, d0[3]
# vacc0x4567 += vb4567 * va0[3]
VMLAL.S16 q9, d11, d0[3]
# vacc1x0123 += vb0123 * va1[3]
VMLAL.S16 q10, d10, d2[3]
# vacc1x4567 += vb4567 * va1[3]
VMLAL.S16 q11, d11, d2[3]
# vacc2x0123 += vb0123 * va2[3]
VMLAL.S16 q12, d10, d4[3]
# vacc2x4567 += vb4567 * va2[3]
VMLAL.S16 q13, d11, d4[3]
# vacc3x0123 += vb0123 * va3[3]
VMLAL.S16 q14, d10, d6[3]
# vacc3x4567 += vb4567 * va3[3]
VMLAL.S16 q15, d11, d6[3]
### Channel 4 ###
BLS 2f
# Load b0-b7 (channel 4)
# - d11 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 4)
# - d11 = vb4567 (channel 4)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[4]
VMLAL.S16 q8, d8, d1[0]
# vacc0x4567 += vb4567 * va0[4]
VMLAL.S16 q9, d9, d1[0]
# vacc1x0123 += vb0123 * va1[4]
VMLAL.S16 q10, d8, d3[0]
# vacc1x4567 += vb4567 * va1[4]
VMLAL.S16 q11, d9, d3[0]
# vacc2x0123 += vb0123 * va2[4]
VMLAL.S16 q12, d8, d5[0]
# vacc2x4567 += vb4567 * va2[4]
VMLAL.S16 q13, d9, d5[0]
# vacc3x0123 += vb0123 * va3[4]
VMLAL.S16 q14, d8, d7[0]
# vacc3x4567 += vb4567 * va3[4]
VMLAL.S16 q15, d9, d7[0]
### Channel 5 ###
CMP r2, -16
BLO 2f
# Load b0-b7 (channel 5)
# - d13 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q5 = b0:7 - b_zero_point
# - d10 = vb0123 (channel 5)
# - d11 = vb4567 (channel 5)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[5]
VMLAL.S16 q8, d10, d1[1]
# vacc0x4567 += vb4567 * va0[5]
VMLAL.S16 q9, d11, d1[1]
# vacc1x0123 += vb0123 * va1[5]
VMLAL.S16 q10, d10, d3[1]
# vacc1x4567 += vb4567 * va1[5]
VMLAL.S16 q11, d11, d3[1]
# vacc2x0123 += vb0123 * va2[5]
VMLAL.S16 q12, d10, d5[1]
# vacc2x4567 += vb4567 * va2[5]
VMLAL.S16 q13, d11, d5[1]
# vacc3x0123 += vb0123 * va3[5]
VMLAL.S16 q14, d10, d7[1]
# vacc3x4567 += vb4567 * va3[5]
VMLAL.S16 q15, d11, d7[1]
### Channel 6 ###
BLS 2f
# Load b0-b7 (channel 6)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]
# q4 = b0:7 - b_zero_point
# - d8 = vb0123 (channel 6)
# - d9 = vb4567 (channel 6)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[6]
VMLAL.S16 q8, d8, d1[2]
# vacc0x4567 += vb4567 * va0[6]
VMLAL.S16 q9, d9, d1[2]
# vacc1x0123 += vb0123 * va1[6]
VMLAL.S16 q10, d8, d3[2]
# vacc1x4567 += vb4567 * va1[6]
VMLAL.S16 q11, d9, d3[2]
# vacc2x0123 += vb0123 * va2[6]
VMLAL.S16 q12, d8, d5[2]
# vacc2x4567 += vb4567 * va2[6]
VMLAL.S16 q13, d9, d5[2]
# vacc3x0123 += vb0123 * va3[6]
VMLAL.S16 q14, d8, d7[2]
# vacc3x4567 += vb4567 * va3[6]
VMLAL.S16 q15, d9, d7[2]
.p2align 4
2:
# Load requantization_scale:
# - d12 = requantization_scale
VLD1.32 {d12, d13}, [r8]!
# Load vfmax:
VLD1.32 {d10[], d11[]}, [r7]!
VLD1.32 {d4, d5}, [r8]
# Load vfmin:
VLD1.32 {d8[], d9[]}, [r7]!
# Load vfmagic:
VLD1.32 {d0[], d1[]}, [r7]!
# Load vimagic:
VLD1.32 {d2[], d3[]}, [r7]!
# Moved here to hide load latency on d14
VCVT.F32.S32 q8, q8
VCVT.F32.S32 q9, q9
VCVT.F32.S32 q10, q10
VCVT.F32.S32 q11, q11
VCVT.F32.S32 q12, q12
VCVT.F32.S32 q13, q13
VCVT.F32.S32 q14, q14
VCVT.F32.S32 q15, q15
VMUL.F32 q8, q8, q6
VMUL.F32 q9, q9, q2
VMUL.F32 q10, q10, q6
VMUL.F32 q11, q11, q2
VMUL.F32 q12, q12, q6
VMUL.F32 q13, q13, q2
VMUL.F32 q14, q14, q6
VMUL.F32 q15, q15, q2
VMIN.F32 q8, q8, q5
VMIN.F32 q9, q9, q5
VMIN.F32 q10, q10, q5
VMIN.F32 q11, q11, q5
VMIN.F32 q12, q12, q5
VMIN.F32 q13, q13, q5
VMIN.F32 q14, q14, q5
VMIN.F32 q15, q15, q5
VMAX.F32 q8, q8, q4
VMAX.F32 q9, q9, q4
VMAX.F32 q10, q10, q4
VMAX.F32 q11, q11, q4
VMAX.F32 q12, q12, q4
VMAX.F32 q13, q13, q4
VMAX.F32 q14, q14, q4
VMAX.F32 q15, q15, q4
VADD.F32 q8, q8, q0
VADD.F32 q9, q9, q0
VADD.F32 q10, q10, q0
VADD.F32 q11, q11, q0
VADD.F32 q12, q12, q0
VADD.F32 q13, q13, q0
VADD.F32 q14, q14, q0
VADD.F32 q15, q15, q0
# Load c, c_stride:
# - r2 = c
# - r2 = c_stride
LDRD r2, r3, [sp, 96]
VSUB.S32 q8, q8, q1
VSUB.S32 q9, q9, q1
VSUB.S32 q10, q10, q1
VSUB.S32 q11, q11, q1
VSUB.S32 q12, q12, q1
VSUB.S32 q13, q13, q1
VSUB.S32 q14, q14, q1
VSUB.S32 q15, q15, q1
ADD r4, r2, r3
VQMOVN.S32 d16, q8
VQMOVN.S32 d17, q9
CMP r0, 2
VQMOVN.S32 d18, q10
VQMOVN.S32 d19, q11
MOVLO r4, r2
VQMOVN.S32 d20, q12
VQMOVN.S32 d21, q13
VQMOVN.S32 d22, q14
VQMOVN.S32 d23, q15
ADD r5, r4, r3
VQMOVUN.S16 d16, q8
MOVLS r5, r4
VQMOVUN.S16 d17, q9
VQMOVUN.S16 d18, q10
CMP r0, 4
ADD r3, r5, r3
MOVNE r3, r5
CMP r1, 8
VQMOVUN.S16 d19, q11
BNE 4f
VST1.8 {d16}, [r2]
VST1.8 {d17}, [r4]
VST1.8 {d18}, [r5]
VST1.8 {d19}, [r3]
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9}
BX lr
.p2align 3
4:
CMP r1, 4
BLO 5f
VST1.32 {d16[0]}, [r2]!
VST1.32 {d17[0]}, [r4]!
VST1.32 {d18[0]}, [r5]!
VST1.32 {d19[0]}, [r3]!
SUB r1, 4
VEXT.8 q8, q8, q8, 4
VEXT.8 q9, q9, q9, 4
5:
CMP r1, 2
BLO 6f
VST1.16 {d16[0]}, [r2]!
VST1.16 {d17[0]}, [r4]!
VST1.16 {d18[0]}, [r5]!
VST1.16 {d19[0]}, [r3]!
SUB r1, 2
VEXT.8 q8, q8, q8, 2
VEXT.8 q9, q9, q9, 2
6:
TEQ r1, 0
BEQ 7f
VST1.8 {d16[0]}, [r2]
VST1.8 {d17[0]}, [r4]
VST1.8 {d18[0]}, [r5]
VST1.8 {d19[0]}, [r3]
7:
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9}
BX lr
END_FUNCTION pytorch_q8gemm_ukernel_4x8__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 27,813 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm/8x8-aarch64-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
# Args passed via 8 registers (64 bytes)
# x0: mr
# x1: nr
# x2: k
# x3: a
# x4: a_stride
# x5: w
# x6: c
# x7: c_stride
#
# Args passed via stack.
# TOS
# |-----------|
# |out ch indx| 0
# |params | 8
# |-----------|
# void pytorch_q8gemm_ukernel_8x8__aarch64_neon(
# size_t mr,
# size_t nr,
# size_t k,
# const uint8_t*restrict a,
# size_t a_stride,
# const void*restrict w,
# uint8_t*restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8gemm_ukernel_8x8__aarch64_neon
# https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture
# Callee need to save 8-15 vector registers and only the lower 64 bits of each.
# Load params
LDP x16, x8, [sp]
STP d15, d14, [sp, -16]
# Load pointer to per channel zero points array
# And go to the a_zero_point with post-index
LDR x17, [x8], 8
STP d13, d12, [sp, -32]
STP d11, d10, [sp, -48]
STP d9, d8, [sp, -64]
# Load bias0123, bias4567
LD1 {v8.4s, v9.4s}, [x5], 32
# Add offset to the base pointer
ADD x17, x17, x16
# Load b_zero_point
LD1 {v25.8b}, [x17]
# Load a_zero_point
LD1R {v24.8b}, [x8]
# Load pointer to per channel requant scale
LDR x17, [x8, 8]
ADD x8, x8, 16
# v10 := vacc1x0123
MOV v10.16b, v8.16b
# v11 := vacc1x4567
MOV v11.16b, v9.16b
# v12 := vacc2x0123
MOV v12.16b, v8.16b
# v13 := vacc2x4567
MOV v13.16b, v9.16b
# v14 := vacc3x0123
MOV v14.16b, v8.16b
# v15 := vacc3x4567
MOV v15.16b, v9.16b
# v16 := vacc4x0123
MOV v16.16b, v8.16b
# v17 := vacc4x4567
MOV v17.16b, v9.16b
# v18 := vacc5x0123
MOV v18.16b, v8.16b
# v19 := vacc5x4567
MOV v19.16b, v9.16b
# v20 := vacc6x0123
MOV v20.16b, v8.16b
# v21 := vacc6x4567
MOV v21.16b, v9.16b
# v22 := vacc7x0123
MOV v22.16b, v8.16b
# v23 := vacc7x4567
MOV v23.16b, v9.16b
# Fold mul by 4 to get byte offset for requant scale.
# Add offset to the base pointer
ADD x17, x17, x16, lsl#2
// Load requantization_scale
// - v26 = requantization_scale channels 0-3
// - v27 = requantization_scale channels 4-7
LD1 {v26.4s}, [x17], 16
# a1
CMP x0, 2
ADD x9, x3, x4
CSEL x9, x3, x9, LO
# a2
ADD x10, x9, x4
CSEL x10, x9, x10, LS
# a3
CMP x0, 4
ADD x11, x10, x4
CSEL x11, x10, x11, LO
# a4
ADD x12, x11, x4
CSEL x12, x11, x12, LS
# a5
CMP x0, 6
ADD x13, x12, x4
CSEL x13, x12, x13, LO
# a6
ADD x14, x13, x4
CSEL x14, x13, x14, LS
# a7
CMP x0, 8
ADD x15, x14, x4
CSEL x15, x14, x15, NE
SUBS x2, x2, 8
B.LO 1f
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 5
#endif
0:
// b0-7 (channel 0)
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
# va0 - va7 := va - va_zero_point
LD1 {v0.8b}, [x3], 8
SUB_ZERO_POINT v0.8h, v0.8b, v24.8b
LD1 {v1.8b}, [x9], 8
SUB_ZERO_POINT v1.8h, v1.8b, v24.8b
LD1 {v2.8b}, [x10], 8
SUB_ZERO_POINT v2.8h, v2.8b, v24.8b
LD1 {v3.8b}, [x11], 8
SUB_ZERO_POINT v3.8h, v3.8b, v24.8b
LD1 {v4.8b}, [x12], 8
SUB_ZERO_POINT v4.8h, v4.8b, v24.8b
LD1 {v5.8b}, [x13], 8
SUB_ZERO_POINT v5.8h, v5.8b, v24.8b
LD1 {v6.8b}, [x14], 8
SUB_ZERO_POINT v6.8h, v6.8b, v24.8b
LD1 {v7.8b}, [x15], 8
SUB_ZERO_POINT v7.8h, v7.8b, v24.8b
// b0-7 (channel 1)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[0] // vacc0x0123 += vb0123 * va0[0]
SMLAL2 v9.4s, v27.8h, v0.h[0] // vacc0x4567 += vb4567 * va0[0]
SMLAL v10.4s, v27.4h, v1.h[0] // vacc1x0123 += vb0123 * va1[0]
SMLAL2 v11.4s, v27.8h, v1.h[0] // vacc1x4567 += vb4567 * va1[0]
SMLAL v12.4s, v27.4h, v2.h[0] // vacc2x0123 += vb0123 * va2[0]
SMLAL2 v13.4s, v27.8h, v2.h[0] // vacc2x4567 += vb4567 * va2[0]
SMLAL v14.4s, v27.4h, v3.h[0] // vacc3x0123 += vb0123 * va3[0]
SMLAL2 v15.4s, v27.8h, v3.h[0] // vacc3x4567 += vb4567 * va3[0]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[0] // vacc4x0123 += vb0123 * va4[0]
SMLAL2 v17.4s, v27.8h, v4.h[0] // vacc4x4567 += vb4567 * va4[0]
SMLAL v18.4s, v27.4h, v5.h[0] // vacc5x0123 += vb0123 * va5[0]
SMLAL2 v19.4s, v27.8h, v5.h[0] // vacc5x4567 += vb4567 * va5[0]
SMLAL v20.4s, v27.4h, v6.h[0] // vacc6x0123 += vb0123 * va6[0]
SMLAL2 v21.4s, v27.8h, v6.h[0] // vacc6x4567 += vb4567 * va6[0]
SMLAL v22.4s, v27.4h, v7.h[0] // vacc7x0123 += vb0123 * va7[0]
SMLAL2 v23.4s, v27.8h, v7.h[0] // vacc7x4567 += vb4567 * va7[0]
// b0-7 (channel 2)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[1] // vacc0x0123 += vb0123 * va0[1]
SMLAL2 v9.4s, v28.8h, v0.h[1] // vacc0x4567 += vb4567 * va0[1]
SMLAL v10.4s, v28.4h, v1.h[1] // vacc1x0123 += vb0123 * va1[1]
SMLAL2 v11.4s, v28.8h, v1.h[1] // vacc1x4567 += vb4567 * va1[1]
SMLAL v12.4s, v28.4h, v2.h[1] // vacc2x0123 += vb0123 * va2[1]
SMLAL2 v13.4s, v28.8h, v2.h[1] // vacc2x4567 += vb4567 * va2[1]
SMLAL v14.4s, v28.4h, v3.h[1] // vacc3x0123 += vb0123 * va3[1]
SMLAL2 v15.4s, v28.8h, v3.h[1] // vacc3x4567 += vb4567 * va3[1]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[1] // vacc4x0123 += vb0123 * va4[1]
SMLAL2 v17.4s, v28.8h, v4.h[1] // vacc4x4567 += vb4567 * va4[1]
SMLAL v18.4s, v28.4h, v5.h[1] // vacc5x0123 += vb0123 * va5[1]
SMLAL2 v19.4s, v28.8h, v5.h[1] // vacc5x4567 += vb4567 * va5[1]
SMLAL v20.4s, v28.4h, v6.h[1] // vacc6x0123 += vb0123 * va6[1]
SMLAL2 v21.4s, v28.8h, v6.h[1] // vacc6x4567 += vb4567 * va6[1]
SMLAL v22.4s, v28.4h, v7.h[1] // vacc7x0123 += vb0123 * va7[1]
SMLAL2 v23.4s, v28.8h, v7.h[1] // vacc7x4567 += vb4567 * va7[1]
// b0-7 (channel 3)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[2] // vacc0x0123 += vb0123 * va0[2]
SMLAL2 v9.4s, v27.8h, v0.h[2] // vacc0x4567 += vb4567 * va0[2]
SMLAL v10.4s, v27.4h, v1.h[2] // vacc1x0123 += vb0123 * va1[2]
SMLAL2 v11.4s, v27.8h, v1.h[2] // vacc1x4567 += vb4567 * va1[2]
SMLAL v12.4s, v27.4h, v2.h[2] // vacc2x0123 += vb0123 * va2[2]
SMLAL2 v13.4s, v27.8h, v2.h[2] // vacc2x4567 += vb4567 * va2[2]
SMLAL v14.4s, v27.4h, v3.h[2] // vacc3x0123 += vb0123 * va3[2]
SMLAL2 v15.4s, v27.8h, v3.h[2] // vacc3x4567 += vb4567 * va3[2]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[2] // vacc4x0123 += vb0123 * va4[2]
SMLAL2 v17.4s, v27.8h, v4.h[2] // vacc4x4567 += vb4567 * va4[2]
SMLAL v18.4s, v27.4h, v5.h[2] // vacc5x0123 += vb0123 * va5[2]
SMLAL2 v19.4s, v27.8h, v5.h[2] // vacc5x4567 += vb4567 * va5[2]
SMLAL v20.4s, v27.4h, v6.h[2] // vacc6x0123 += vb0123 * va6[2]
SMLAL2 v21.4s, v27.8h, v6.h[2] // vacc6x4567 += vb4567 * va6[2]
SMLAL v22.4s, v27.4h, v7.h[2] // vacc7x0123 += vb0123 * va7[2]
SMLAL2 v23.4s, v27.8h, v7.h[2] // vacc7x4567 += vb4567 * va7[2]
// b0-7 (channel 4)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[3] // vacc0x0123 += vb0123 * va0[3]
SMLAL2 v9.4s, v28.8h, v0.h[3] // vacc0x4567 += vb4567 * va0[3]
SMLAL v10.4s, v28.4h, v1.h[3] // vacc1x0123 += vb0123 * va1[3]
SMLAL2 v11.4s, v28.8h, v1.h[3] // vacc1x4567 += vb4567 * va1[3]
SMLAL v12.4s, v28.4h, v2.h[3] // vacc2x0123 += vb0123 * va2[3]
SMLAL2 v13.4s, v28.8h, v2.h[3] // vacc2x4567 += vb4567 * va2[3]
SMLAL v14.4s, v28.4h, v3.h[3] // vacc3x0123 += vb0123 * va3[3]
SMLAL2 v15.4s, v28.8h, v3.h[3] // vacc3x4567 += vb4567 * va3[3]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[3] // vacc4x0123 += vb0123 * va4[3]
SMLAL2 v17.4s, v28.8h, v4.h[3] // vacc4x4567 += vb4567 * va4[3]
SMLAL v18.4s, v28.4h, v5.h[3] // vacc5x0123 += vb0123 * va5[3]
SMLAL2 v19.4s, v28.8h, v5.h[3] // vacc5x4567 += vb4567 * va5[3]
SMLAL v20.4s, v28.4h, v6.h[3] // vacc6x0123 += vb0123 * va6[3]
SMLAL2 v21.4s, v28.8h, v6.h[3] // vacc6x4567 += vb4567 * va6[3]
SMLAL v22.4s, v28.4h, v7.h[3] // vacc7x0123 += vb0123 * va7[3]
SMLAL2 v23.4s, v28.8h, v7.h[3] // vacc7x4567 += vb4567 * va7[3]
// b0-7 (channel 5)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[4] // vacc0x0123 += vb0123 * va0[4]
SMLAL2 v9.4s, v27.8h, v0.h[4] // vacc0x4567 += vb4567 * va0[4]
SMLAL v10.4s, v27.4h, v1.h[4] // vacc1x0123 += vb0123 * va1[4]
SMLAL2 v11.4s, v27.8h, v1.h[4] // vacc1x4567 += vb4567 * va1[4]
SMLAL v12.4s, v27.4h, v2.h[4] // vacc2x0123 += vb0123 * va2[4]
SMLAL2 v13.4s, v27.8h, v2.h[4] // vacc2x4567 += vb4567 * va2[4]
SMLAL v14.4s, v27.4h, v3.h[4] // vacc3x0123 += vb0123 * va3[4]
SMLAL2 v15.4s, v27.8h, v3.h[4] // vacc3x4567 += vb4567 * va3[4]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[4] // vacc4x0123 += vb0123 * va4[4]
SMLAL2 v17.4s, v27.8h, v4.h[4] // vacc4x4567 += vb4567 * va4[4]
SMLAL v18.4s, v27.4h, v5.h[4] // vacc5x0123 += vb0123 * va5[4]
SMLAL2 v19.4s, v27.8h, v5.h[4] // vacc5x4567 += vb4567 * va5[4]
SMLAL v20.4s, v27.4h, v6.h[4] // vacc6x0123 += vb0123 * va6[4]
SMLAL2 v21.4s, v27.8h, v6.h[4] // vacc6x4567 += vb4567 * va6[4]
SMLAL v22.4s, v27.4h, v7.h[4] // vacc7x0123 += vb0123 * va7[4]
SMLAL2 v23.4s, v27.8h, v7.h[4] // vacc7x4567 += vb4567 * va7[4]
// b0-7 (channel 6)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[5] // vacc0x0123 += vb0123 * va0[5]
SMLAL2 v9.4s, v28.8h, v0.h[5] // vacc0x4567 += vb4567 * va0[5]
SMLAL v10.4s, v28.4h, v1.h[5] // vacc1x0123 += vb0123 * va1[5]
SMLAL2 v11.4s, v28.8h, v1.h[5] // vacc1x4567 += vb4567 * va1[5]
SMLAL v12.4s, v28.4h, v2.h[5] // vacc2x0123 += vb0123 * va2[5]
SMLAL2 v13.4s, v28.8h, v2.h[5] // vacc2x4567 += vb4567 * va2[5]
SMLAL v14.4s, v28.4h, v3.h[5] // vacc3x0123 += vb0123 * va3[5]
SMLAL2 v15.4s, v28.8h, v3.h[5] // vacc3x4567 += vb4567 * va3[5]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[5] // vacc4x0123 += vb0123 * va4[5]
SMLAL2 v17.4s, v28.8h, v4.h[5] // vacc4x4567 += vb4567 * va4[5]
SMLAL v18.4s, v28.4h, v5.h[5] // vacc5x0123 += vb0123 * va5[5]
SMLAL2 v19.4s, v28.8h, v5.h[5] // vacc5x4567 += vb4567 * va5[5]
SMLAL v20.4s, v28.4h, v6.h[5] // vacc6x0123 += vb0123 * va6[5]
SMLAL2 v21.4s, v28.8h, v6.h[5] // vacc6x4567 += vb4567 * va6[5]
SMLAL v22.4s, v28.4h, v7.h[5] // vacc7x0123 += vb0123 * va7[5]
SMLAL2 v23.4s, v28.8h, v7.h[5] // vacc7x4567 += vb4567 * va7[5]
// b0-7 (channel 7)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[6] // vacc0x0123 += vb0123 * va0[6]
SMLAL2 v9.4s, v27.8h, v0.h[6] // vacc0x4567 += vb4567 * va0[6]
SMLAL v10.4s, v27.4h, v1.h[6] // vacc1x0123 += vb0123 * va1[6]
SMLAL2 v11.4s, v27.8h, v1.h[6] // vacc1x4567 += vb4567 * va1[6]
SMLAL v12.4s, v27.4h, v2.h[6] // vacc2x0123 += vb0123 * va2[6]
SMLAL2 v13.4s, v27.8h, v2.h[6] // vacc2x4567 += vb4567 * va2[6]
SMLAL v14.4s, v27.4h, v3.h[6] // vacc3x0123 += vb0123 * va3[6]
SMLAL2 v15.4s, v27.8h, v3.h[6] // vacc3x4567 += vb4567 * va3[6]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[6] // vacc4x0123 += vb0123 * va4[6]
SMLAL2 v17.4s, v27.8h, v4.h[6] // vacc4x4567 += vb4567 * va4[6]
SMLAL v18.4s, v27.4h, v5.h[6] // vacc5x0123 += vb0123 * va5[6]
SMLAL2 v19.4s, v27.8h, v5.h[6] // vacc5x4567 += vb4567 * va5[6]
SMLAL v20.4s, v27.4h, v6.h[6] // vacc6x0123 += vb0123 * va6[6]
SMLAL2 v21.4s, v27.8h, v6.h[6] // vacc6x4567 += vb4567 * va6[6]
SMLAL v22.4s, v27.4h, v7.h[6] // vacc7x0123 += vb0123 * va7[6]
SMLAL2 v23.4s, v27.8h, v7.h[6] // vacc7x4567 += vb4567 * va7[6]
SUBS x2, x2, 8
SMLAL v8.4s, v28.4h, v0.h[7] // vacc0x0123 += vb0123 * va0[7]
SMLAL2 v9.4s, v28.8h, v0.h[7] // vacc0x4567 += vb4567 * va0[7]
SMLAL v10.4s, v28.4h, v1.h[7] // vacc1x0123 += vb0123 * va1[7]
SMLAL2 v11.4s, v28.8h, v1.h[7] // vacc1x4567 += vb4567 * va1[7]
SMLAL v12.4s, v28.4h, v2.h[7] // vacc2x0123 += vb0123 * va2[7]
SMLAL2 v13.4s, v28.8h, v2.h[7] // vacc2x4567 += vb4567 * va2[7]
SMLAL v14.4s, v28.4h, v3.h[7] // vacc3x0123 += vb0123 * va3[7]
SMLAL2 v15.4s, v28.8h, v3.h[7] // vacc3x4567 += vb4567 * va3[7]
SMLAL v16.4s, v28.4h, v4.h[7] // vacc4x0123 += vb0123 * va4[7]
SMLAL2 v17.4s, v28.8h, v4.h[7] // vacc4x4567 += vb4567 * va4[7]
SMLAL v18.4s, v28.4h, v5.h[7] // vacc5x0123 += vb0123 * va5[7]
SMLAL2 v19.4s, v28.8h, v5.h[7] // vacc5x4567 += vb4567 * va5[7]
SMLAL v20.4s, v28.4h, v6.h[7] // vacc6x0123 += vb0123 * va6[7]
SMLAL2 v21.4s, v28.8h, v6.h[7] // vacc6x4567 += vb4567 * va6[7]
SMLAL v22.4s, v28.4h, v7.h[7] // vacc7x0123 += vb0123 * va7[7]
SMLAL2 v23.4s, v28.8h, v7.h[7] // vacc7x4567 += vb4567 * va7[7]
B.HS 0b
1:
CMP x2, -8
B.EQ 2f
// Adjust a0-a7
ADD x3, x3, x2
ADD x9, x9, x2
ADD x10, x10, x2
ADD x11, x11, x2
ADD x12, x12, x2
ADD x13, x13, x2
ADD x14, x14, x2
ADD x15, x15, x2
// a_shift = 8 * k - 64
LSL x2, x2, 3
FMOV d29, x2
USHL d24, d24, d29
// Load x0-a7
LD1 {v0.8b}, [x3], 8
USHL d0, d0, d29
SUB_ZERO_POINT v0.8h, v0.8b, v24.8b
LD1 {v1.8b}, [x9], 8
USHL d1, d1, d29
SUB_ZERO_POINT v1.8h, v1.8b, v24.8b
LD1 {v2.8b}, [x10], 8
USHL d2, d2, d29
SUB_ZERO_POINT v2.8h, v2.8b, v24.8b
LD1 {v3.8b}, [x11], 8
USHL d3, d3, d29
SUB_ZERO_POINT v3.8h, v3.8b, v24.8b
LD1 {v4.8b}, [x12], 8
USHL d4, d4, d29
SUB_ZERO_POINT v4.8h, v4.8b, v24.8b
LD1 {v5.8b}, [x13], 8
USHL d5, d5, d29
SUB_ZERO_POINT v5.8h, v5.8b, v24.8b
LD1 {v6.8b}, [x14], 8
USHL d6, d6, d29
SUB_ZERO_POINT v6.8h, v6.8b, v24.8b
LD1 {v7.8b}, [x15], 8
USHL d7, d7, d29
SUB_ZERO_POINT v7.8h, v7.8b, v24.8b
// Channel 0
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[0] // vacc0x0123 += vb0123 * va0[0]
SMLAL2 v9.4s, v27.8h, v0.h[0] // vacc0x4567 += vb4567 * va0[0]
SMLAL v10.4s, v27.4h, v1.h[0] // vacc1x0123 += vb0123 * va1[0]
SMLAL2 v11.4s, v27.8h, v1.h[0] // vacc1x4567 += vb4567 * va1[0]
SMLAL v12.4s, v27.4h, v2.h[0] // vacc2x0123 += vb0123 * va2[0]
SMLAL2 v13.4s, v27.8h, v2.h[0] // vacc2x4567 += vb4567 * va2[0]
SMLAL v14.4s, v27.4h, v3.h[0] // vacc3x0123 += vb0123 * va3[0]
SMLAL2 v15.4s, v27.8h, v3.h[0] // vacc3x4567 += vb4567 * va3[0]
SMLAL v16.4s, v27.4h, v4.h[0] // vacc4x0123 += vb0123 * va4[0]
SMLAL2 v17.4s, v27.8h, v4.h[0] // vacc4x4567 += vb4567 * va4[0]
SMLAL v18.4s, v27.4h, v5.h[0] // vacc5x0123 += vb0123 * va5[0]
SMLAL2 v19.4s, v27.8h, v5.h[0] // vacc5x4567 += vb4567 * va5[0]
SMLAL v20.4s, v27.4h, v6.h[0] // vacc6x0123 += vb0123 * va6[0]
SMLAL2 v21.4s, v27.8h, v6.h[0] // vacc6x4567 += vb4567 * va6[0]
SMLAL v22.4s, v27.4h, v7.h[0] // vacc7x0123 += vb0123 * va7[0]
SMLAL2 v23.4s, v27.8h, v7.h[0] // vacc7x4567 += vb4567 * va7[0]
CMP x2, -48
B.LO 2f
// Channel 1
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[1] // vacc0x0123 += vb0123 * va0[1]
SMLAL2 v9.4s, v28.8h, v0.h[1] // vacc0x4567 += vb4567 * va0[1]
SMLAL v10.4s, v28.4h, v1.h[1] // vacc1x0123 += vb0123 * va1[1]
SMLAL2 v11.4s, v28.8h, v1.h[1] // vacc1x4567 += vb4567 * va1[1]
SMLAL v12.4s, v28.4h, v2.h[1] // vacc2x0123 += vb0123 * va2[1]
SMLAL2 v13.4s, v28.8h, v2.h[1] // vacc2x4567 += vb4567 * va2[1]
SMLAL v14.4s, v28.4h, v3.h[1] // vacc3x0123 += vb0123 * va3[1]
SMLAL2 v15.4s, v28.8h, v3.h[1] // vacc3x4567 += vb4567 * va3[1]
SMLAL v16.4s, v28.4h, v4.h[1] // vacc4x0123 += vb0123 * va4[1]
SMLAL2 v17.4s, v28.8h, v4.h[1] // vacc4x4567 += vb4567 * va4[1]
SMLAL v18.4s, v28.4h, v5.h[1] // vacc5x0123 += vb0123 * va5[1]
SMLAL2 v19.4s, v28.8h, v5.h[1] // vacc5x4567 += vb4567 * va5[1]
SMLAL v20.4s, v28.4h, v6.h[1] // vacc6x0123 += vb0123 * va6[1]
SMLAL2 v21.4s, v28.8h, v6.h[1] // vacc6x4567 += vb4567 * va6[1]
SMLAL v22.4s, v28.4h, v7.h[1] // vacc7x0123 += vb0123 * va7[1]
SMLAL2 v23.4s, v28.8h, v7.h[1] // vacc7x4567 += vb4567 * va7[1]
B.LS 2f
// Channel 2
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[2] // vacc0x0123 += vb0123 * va0[2]
SMLAL2 v9.4s, v27.8h, v0.h[2] // vacc0x4567 += vb4567 * va0[2]
SMLAL v10.4s, v27.4h, v1.h[2] // vacc1x0123 += vb0123 * va1[2]
SMLAL2 v11.4s, v27.8h, v1.h[2] // vacc1x4567 += vb4567 * va1[2]
SMLAL v12.4s, v27.4h, v2.h[2] // vacc2x0123 += vb0123 * va2[2]
SMLAL2 v13.4s, v27.8h, v2.h[2] // vacc2x4567 += vb4567 * va2[2]
SMLAL v14.4s, v27.4h, v3.h[2] // vacc3x0123 += vb0123 * va3[2]
SMLAL2 v15.4s, v27.8h, v3.h[2] // vacc3x4567 += vb4567 * va3[2]
SMLAL v16.4s, v27.4h, v4.h[2] // vacc4x0123 += vb0123 * va4[2]
SMLAL2 v17.4s, v27.8h, v4.h[2] // vacc4x4567 += vb4567 * va4[2]
SMLAL v18.4s, v27.4h, v5.h[2] // vacc5x0123 += vb0123 * va5[2]
SMLAL2 v19.4s, v27.8h, v5.h[2] // vacc5x4567 += vb4567 * va5[2]
SMLAL v20.4s, v27.4h, v6.h[2] // vacc6x0123 += vb0123 * va6[2]
SMLAL2 v21.4s, v27.8h, v6.h[2] // vacc6x4567 += vb4567 * va6[2]
SMLAL v22.4s, v27.4h, v7.h[2] // vacc7x0123 += vb0123 * va7[2]
SMLAL2 v23.4s, v27.8h, v7.h[2] // vacc7x4567 += vb4567 * va7[2]
CMP x2, -32
B.LO 2f
// Channel 3
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[3] // vacc0x0123 += vb0123 * va0[3]
SMLAL2 v9.4s, v28.8h, v0.h[3] // vacc0x4567 += vb4567 * va0[3]
SMLAL v10.4s, v28.4h, v1.h[3] // vacc1x0123 += vb0123 * va1[3]
SMLAL2 v11.4s, v28.8h, v1.h[3] // vacc1x4567 += vb4567 * va1[3]
SMLAL v12.4s, v28.4h, v2.h[3] // vacc2x0123 += vb0123 * va2[3]
SMLAL2 v13.4s, v28.8h, v2.h[3] // vacc2x4567 += vb4567 * va2[3]
SMLAL v14.4s, v28.4h, v3.h[3] // vacc3x0123 += vb0123 * va3[3]
SMLAL2 v15.4s, v28.8h, v3.h[3] // vacc3x4567 += vb4567 * va3[3]
SMLAL v16.4s, v28.4h, v4.h[3] // vacc4x0123 += vb0123 * va4[3]
SMLAL2 v17.4s, v28.8h, v4.h[3] // vacc4x4567 += vb4567 * va4[3]
SMLAL v18.4s, v28.4h, v5.h[3] // vacc5x0123 += vb0123 * va5[3]
SMLAL2 v19.4s, v28.8h, v5.h[3] // vacc5x4567 += vb4567 * va5[3]
SMLAL v20.4s, v28.4h, v6.h[3] // vacc6x0123 += vb0123 * va6[3]
SMLAL2 v21.4s, v28.8h, v6.h[3] // vacc6x4567 += vb4567 * va6[3]
SMLAL v22.4s, v28.4h, v7.h[3] // vacc7x0123 += vb0123 * va7[3]
SMLAL2 v23.4s, v28.8h, v7.h[3] // vacc7x4567 += vb4567 * va7[3]
B.LS 2f
// Channel 4
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[4] // vacc0x0123 += vb0123 * va0[4]
SMLAL2 v9.4s, v27.8h, v0.h[4] // vacc0x4567 += vb4567 * va0[4]
SMLAL v10.4s, v27.4h, v1.h[4] // vacc1x0123 += vb0123 * va1[4]
SMLAL2 v11.4s, v27.8h, v1.h[4] // vacc1x4567 += vb4567 * va1[4]
SMLAL v12.4s, v27.4h, v2.h[4] // vacc2x0123 += vb0123 * va2[4]
SMLAL2 v13.4s, v27.8h, v2.h[4] // vacc2x4567 += vb4567 * va2[4]
SMLAL v14.4s, v27.4h, v3.h[4] // vacc3x0123 += vb0123 * va3[4]
SMLAL2 v15.4s, v27.8h, v3.h[4] // vacc3x4567 += vb4567 * va3[4]
SMLAL v16.4s, v27.4h, v4.h[4] // vacc4x0123 += vb0123 * va4[4]
SMLAL2 v17.4s, v27.8h, v4.h[4] // vacc4x4567 += vb4567 * va4[4]
SMLAL v18.4s, v27.4h, v5.h[4] // vacc5x0123 += vb0123 * va5[4]
SMLAL2 v19.4s, v27.8h, v5.h[4] // vacc5x4567 += vb4567 * va5[4]
SMLAL v20.4s, v27.4h, v6.h[4] // vacc6x0123 += vb0123 * va6[4]
SMLAL2 v21.4s, v27.8h, v6.h[4] // vacc6x4567 += vb4567 * va6[4]
SMLAL v22.4s, v27.4h, v7.h[4] // vacc7x0123 += vb0123 * va7[4]
SMLAL2 v23.4s, v27.8h, v7.h[4] // vacc7x4567 += vb4567 * va7[4]
CMP x2, -16
B.LO 2f
// Channel 5
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[5] // vacc0x0123 += vb0123 * va0[5]
SMLAL2 v9.4s, v28.8h, v0.h[5] // vacc0x4567 += vb4567 * va0[5]
SMLAL v10.4s, v28.4h, v1.h[5] // vacc1x0123 += vb0123 * va1[5]
SMLAL2 v11.4s, v28.8h, v1.h[5] // vacc1x4567 += vb4567 * va1[5]
SMLAL v12.4s, v28.4h, v2.h[5] // vacc2x0123 += vb0123 * va2[5]
SMLAL2 v13.4s, v28.8h, v2.h[5] // vacc2x4567 += vb4567 * va2[5]
SMLAL v14.4s, v28.4h, v3.h[5] // vacc3x0123 += vb0123 * va3[5]
SMLAL2 v15.4s, v28.8h, v3.h[5] // vacc3x4567 += vb4567 * va3[5]
SMLAL v16.4s, v28.4h, v4.h[5] // vacc4x0123 += vb0123 * va4[5]
SMLAL2 v17.4s, v28.8h, v4.h[5] // vacc4x4567 += vb4567 * va4[5]
SMLAL v18.4s, v28.4h, v5.h[5] // vacc5x0123 += vb0123 * va5[5]
SMLAL2 v19.4s, v28.8h, v5.h[5] // vacc5x4567 += vb4567 * va5[5]
SMLAL v20.4s, v28.4h, v6.h[5] // vacc6x0123 += vb0123 * va6[5]
SMLAL2 v21.4s, v28.8h, v6.h[5] // vacc6x4567 += vb4567 * va6[5]
SMLAL v22.4s, v28.4h, v7.h[5] // vacc7x0123 += vb0123 * va7[5]
SMLAL2 v23.4s, v28.8h, v7.h[5] // vacc7x4567 += vb4567 * va7[5]
B.LS 2f
// Channel 6
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[6] // vacc0x0123 += vb0123 * va0[6]
SMLAL2 v9.4s, v27.8h, v0.h[6] // vacc0x4567 += vb4567 * va0[6]
SMLAL v10.4s, v27.4h, v1.h[6] // vacc1x0123 += vb0123 * va1[6]
SMLAL2 v11.4s, v27.8h, v1.h[6] // vacc1x4567 += vb4567 * va1[6]
SMLAL v12.4s, v27.4h, v2.h[6] // vacc2x0123 += vb0123 * va2[6]
SMLAL2 v13.4s, v27.8h, v2.h[6] // vacc2x4567 += vb4567 * va2[6]
SMLAL v14.4s, v27.4h, v3.h[6] // vacc3x0123 += vb0123 * va3[6]
SMLAL2 v15.4s, v27.8h, v3.h[6] // vacc3x4567 += vb4567 * va3[6]
SMLAL v16.4s, v27.4h, v4.h[6] // vacc4x0123 += vb0123 * va4[6]
SMLAL2 v17.4s, v27.8h, v4.h[6] // vacc4x4567 += vb4567 * va4[6]
SMLAL v18.4s, v27.4h, v5.h[6] // vacc5x0123 += vb0123 * va5[6]
SMLAL2 v19.4s, v27.8h, v5.h[6] // vacc5x4567 += vb4567 * va5[6]
SMLAL v20.4s, v27.4h, v6.h[6] // vacc6x0123 += vb0123 * va6[6]
SMLAL2 v21.4s, v27.8h, v6.h[6] // vacc6x4567 += vb4567 * va6[6]
SMLAL v22.4s, v27.4h, v7.h[6] // vacc7x0123 += vb0123 * va7[6]
SMLAL2 v23.4s, v27.8h, v7.h[6] // vacc7x4567 += vb4567 * va7[6]
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 4
#endif
2:
# Load requant scale for channels 4-7
LD1 {v27.4s}, [x17]
// Load zero_point:
// - v29 = vzero_point
LD1R {v29.8h}, [x8], 2
// Load max:
// - v30 = vmax
LD1R {v30.16b}, [x8], 1
// Load min:
// - v31 = vmin
LD1R {v31.16b}, [x8]
SCVTF v8.4s, v8.4s
SCVTF v9.4s, v9.4s
SCVTF v10.4s, v10.4s
SCVTF v11.4s, v11.4s
SCVTF v12.4s, v12.4s
SCVTF v13.4s, v13.4s
SCVTF v14.4s, v14.4s
SCVTF v15.4s, v15.4s
SCVTF v16.4s, v16.4s
SCVTF v17.4s, v17.4s
SCVTF v18.4s, v18.4s
SCVTF v19.4s, v19.4s
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMUL v8.4s, v8.4s, v26.4s
FMUL v9.4s, v9.4s, v27.4s
FMUL v10.4s, v10.4s, v26.4s
FMUL v11.4s, v11.4s, v27.4s
FMUL v12.4s, v12.4s, v26.4s
FMUL v13.4s, v13.4s, v27.4s
FMUL v14.4s, v14.4s, v26.4s
FMUL v15.4s, v15.4s, v27.4s
FMUL v16.4s, v16.4s, v26.4s
FMUL v17.4s, v17.4s, v27.4s
FMUL v18.4s, v18.4s, v26.4s
FMUL v19.4s, v19.4s, v27.4s
FMUL v20.4s, v20.4s, v26.4s
FMUL v21.4s, v21.4s, v27.4s
FMUL v22.4s, v22.4s, v26.4s
FMUL v23.4s, v23.4s, v27.4s
FCVTNS v8.4s, v8.4s
FCVTNS v9.4s, v9.4s
FCVTNS v10.4s, v10.4s
FCVTNS v11.4s, v11.4s
FCVTNS v12.4s, v12.4s
FCVTNS v13.4s, v13.4s
FCVTNS v14.4s, v14.4s
FCVTNS v15.4s, v15.4s
FCVTNS v16.4s, v16.4s
FCVTNS v17.4s, v17.4s
FCVTNS v18.4s, v18.4s
FCVTNS v19.4s, v19.4s
FCVTNS v20.4s, v20.4s
FCVTNS v21.4s, v21.4s
FCVTNS v22.4s, v22.4s
FCVTNS v23.4s, v23.4s
SQXTN v8.4h, v8.4s
SQXTN v10.4h, v10.4s
SQXTN v12.4h, v12.4s
SQXTN v14.4h, v14.4s
SQXTN v16.4h, v16.4s
SQXTN v18.4h, v18.4s
SQXTN v20.4h, v20.4s
SQXTN v22.4h, v22.4s
SQXTN2 v8.8h, v9.4s
SQXTN2 v10.8h, v11.4s
SQXTN2 v12.8h, v13.4s
SQXTN2 v14.8h, v15.4s
SQXTN2 v16.8h, v17.4s
SQXTN2 v18.8h, v19.4s
SQXTN2 v20.8h, v21.4s
SQXTN2 v22.8h, v23.4s
SQADD v8.8h, v8.8h, v29.8h
SQADD v10.8h, v10.8h, v29.8h
SQADD v12.8h, v12.8h, v29.8h
SQADD v14.8h, v14.8h, v29.8h
SQADD v16.8h, v16.8h, v29.8h
SQADD v18.8h, v18.8h, v29.8h
SQADD v20.8h, v20.8h, v29.8h
SQADD v22.8h, v22.8h, v29.8h
SQXTUN v8.8b, v8.8h
SQXTUN v12.8b, v12.8h
SQXTUN v16.8b, v16.8h
SQXTUN v20.8b, v20.8h
SQXTUN2 v8.16b, v10.8h
SQXTUN2 v12.16b, v14.8h
SQXTUN2 v16.16b, v18.8h
SQXTUN2 v20.16b, v22.8h
UMIN v8.16b, v8.16b, v30.16b
UMIN v12.16b, v12.16b, v30.16b
UMIN v16.16b, v16.16b, v30.16b
UMIN v20.16b, v20.16b, v30.16b
UMAX v8.16b, v8.16b, v31.16b
UMAX v12.16b, v12.16b, v31.16b
UMAX v16.16b, v16.16b, v31.16b
UMAX v20.16b, v20.16b, v31.16b
// Compute c0-c7
ADD x9, x6, x7
CMP x0, 2
CSEL x9, x6, x9, LO
ADD x10, x9, x7
CSEL x10, x9, x10, LS
ADD x11, x10, x7
CMP x0, 4
CSEL x11, x10, x11, LO
ADD x12, x11, x7
CSEL x12, x11, x12, LS
ADD x13, x12, x7
CMP x0, 6
CSEL x13, x12, x13, LO
ADD x14, x13, x7
CSEL x14, x13, x14, LS
ADD x15, x14, x7
CMP x0, 8
CSEL x15, x14, x15, NE
CMP x1, 8
B.NE 4f
// Store results
ST1 {v8.d}[0], [x6]
ST1 {v8.d}[1], [x9]
ST1 {v12.d}[0], [x10]
ST1 {v12.d}[1], [x11]
ST1 {v16.d}[0], [x12]
ST1 {v16.d}[1], [x13]
ST1 {v20.d}[0], [x14]
ST1 {v20.d}[1], [x15]
LDP d9, d8, [sp, -64]
LDP d11, d10, [sp, -48]
LDP d13, d12, [sp, -32]
LDP d15, d14, [sp, -16]
RET
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 3
#endif
4:
CMP x1, 4
B.LO 5f
ST1 {v8.s}[0], [x6], 4
ST1 {v8.s}[2], [x9], 4
ST1 {v12.s}[0], [x10], 4
ST1 {v12.s}[2], [x11], 4
ST1 {v16.s}[0], [x12], 4
ST1 {v16.s}[2], [x13], 4
ST1 {v20.s}[0], [x14], 4
ST1 {v20.s}[2], [x15], 4
SUB x1, x1, 4
EXT v8.16b, v8.16b, v8.16b, 4
EXT v12.16b, v12.16b, v12.16b, 4
EXT v16.16b, v16.16b, v16.16b, 4
EXT v20.16b, v20.16b, v20.16b, 4
5:
CMP x1, 2
B.LO 6f
ST1 {v8.h}[0], [x6], 2
ST1 {v8.h}[4], [x9], 2
ST1 {v12.h}[0], [x10], 2
ST1 {v12.h}[4], [x11], 2
ST1 {v16.h}[0], [x12], 2
ST1 {v16.h}[4], [x13], 2
ST1 {v20.h}[0], [x14], 2
ST1 {v20.h}[4], [x15], 2
SUB x1, x1, 2
EXT v8.16b, v8.16b, v8.16b, 2
EXT v12.16b, v12.16b, v12.16b, 2
EXT v16.16b, v16.16b, v16.16b, 2
EXT v20.16b, v20.16b, v20.16b, 2
6:
CMP x1, 1
B.LO 7f
ST1 {v8.b}[0], [x6]
ST1 {v8.b}[8], [x9]
ST1 {v12.b}[0], [x10]
ST1 {v12.b}[8], [x11]
ST1 {v16.b}[0], [x12]
ST1 {v16.b}[8], [x13]
ST1 {v20.b}[0], [x14]
ST1 {v20.b}[8], [x15]
7:
LDP d9, d8, [sp, -64]
LDP d11, d10, [sp, -48]
LDP d13, d12, [sp, -32]
LDP d15, d14, [sp, -16]
RET
END_FUNCTION pytorch_q8gemm_ukernel_8x8__aarch64_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 7,829 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8dwconv/up8x9-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
.syntax unified
# void pytorch_q8dwconv_ukernel_up8x9__aarch32_neon(
# size_t channels,
# size_t output_width,
# const uint8_t** input,
# const void* weights,
# uint8_t* output,
# size_t input_stride,
# size_t output_increment,
# const union pytorch_qnnp_conv_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8dwconv_ukernel_up8x9__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load params
# - r12 = quantization_params
LDR r12, [sp, 12]
PUSH {r4, r5, r6, r7, r8, r9, r10, r11, lr}
VPUSH {d8-d15}
STR r0, [sp, #-8]
STR r3, [sp, #-4]
# Load the address zero_point array.
# For depth wise kernels the array is of single element.
LDR r5, [r12], 4
# Load o:
# - lr = o = output
LDR lr, [sp, 100]
# Load kernel zero point:
# - d31 = vkernel_zero_point
VLD1.8 {d31[]}, [r5]
# Load input zero point:
# - d30 = vinput_zero_point
VLD1.8 {d30[]}, [r12]
# Load the address requantization_scale array.
# For depth wise kernels the array is of single element.
# pre-index r12 = r12 + 4
LDR r5, [r12, 4]!
# add 8 bytes to get to vfmax
ADD r12, r12, 8
# Load requantization_scale:
# - q14 = d28:d29 = requantization_scale
VLD1.32 {d28[], d29[]}, [r5]
# Load vfmax:
# - q13 = d26:d27 = vfmax
VLD1.32 {d26[], d27[]}, [r12]!
# Load vfmin:
# - q12 = d24:d25 = vfmin
VLD1.32 {d24[], d25[]}, [r12]!
# Load vfmagic:
# - q10 = d20:d21 = vfmagic
VLD1.32 {d20[], d21[]}, [r12]!
# Load vimagic:
# - q11 = d22:d23 = vimagic
# Since q11/d22 gets used in the remainder channels section
# This load will have to occur in that section again.
# But since r12 is overwritten below, we will have to push it
# on the stack and pop it back.
VLD1.32 {d22[], d23[]}, [r12]
VSTR d22, [sp, #-16]
VSTR d23, [sp, #-24]
.p2align 3
0:
# Load input stride
# - r3 = input_stride
LDR r3, [sp, 104]
# Load c:
# - r0 = c = channels
LDR r0, [sp, #-8]
# Load i0, i1, i2, i3, i4, i5, i6, i7, i8
# - r4 = i0
# - r5 = i1
# - r6 = i2
# - r7 = i3
# - r8 = i4
# - r9 = i5
# - r10 = i6
# - r11 = i7
# - r12 = i8
LDM r2, {r4, r5, r6, r7, r8, r9, r10, r11, r12}
# Pre-decrement c
SUBS r0, r0, 8
# Increment input by input stride
# - input = r2 := input + input_stride
ADD r2, r2, r3
# Load w:
# - r3 = w = weights
LDR r3, [sp, #-4]
BLO 2f
.p2align 4
1:
VLDM r3!, {d0-d3}
VLD1.8 {d4}, [r4]!
VLD1.8 {d6}, [r3]!
VLD1.8 {d8}, [r5]!
VLD1.8 {d10}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VLD1.8 {d12}, [r6]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r7]!
VLD1.8 {d6}, [r3]!
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VLD1.8 {d8}, [r8]!
VLD1.8 {d10}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VLD1.8 {d12}, [r9]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r10]!
VLD1.8 {d6}, [r3]!
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VLD1.8 {d8}, [r11]!
VLD1.8 {d10}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VLD1.8 {d12}, [r12]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VCVT.F32.S32 q0, q0
VCVT.F32.S32 q1, q1
VMUL.F32 q0, q0, q14
VMUL.F32 q1, q1, q14
VMIN.F32 q0, q0, q13
VMIN.F32 q1, q1, q13
VMAX.F32 q0, q0, q12
VMAX.F32 q1, q1, q12
VADD.F32 q0, q0, q10
VADD.F32 q1, q1, q10
VSUB.S32 q0, q0, q11
VSUB.S32 q1, q1, q11
VQMOVN.S32 d0, q0
VQMOVN.S32 d1, q1
VQMOVUN.S16 d0, q0
VST1.8 {d0}, [lr]!
SUBS r0, r0, 8
BHS 1b
2:
CMP r0, -8
BEQ 5f
ADD r4, r4, r0
ADD r5, r5, r0
ADD r6, r6, r0
ADD r7, r7, r0
ADD r8, r8, r0
ADD r9, r9, r0
ADD r10, r10, r0
ADD r11, r11, r0
ADD r12, r12, r0
LSL r0, r0, 3
VDUP.32 d22, r0
VLDM r3!, {d0-d3}
VLD1.8 {d4}, [r4]!
VLD1.8 {d6}, [r3]!
VLD1.8 {d8}, [r5]!
VLD1.8 {d10}, [r3]!
VSHL.U64 d4, d4, d22
VLD1.8 {d12}, [r6]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VSHL.U64 d8, d8, d22
VLD1.8 {d16}, [r7]!
VLD1.8 {d18}, [r3]!
VSHL.U64 d12, d12, d22
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r8]!
VLD1.8 {d6}, [r3]!
VSHL.U64 d16, d16, d22
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VLD1.8 {d8}, [r9]!
VLD1.8 {d10}, [r3]!
VSHL.U64 d4, d4, d22
SUB_ZERO_POINT q8, d16, d30
VSUBL.U8 q9, d18, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VLD1.8 {d12}, [r10]!
VLD1.8 {d14}, [r3]!
VSHL.U64 d8, d8, d22
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d16, d18
VMLAL.S16 q1, d17, d19
VLD1.8 {d16}, [r11]!
VLD1.8 {d18}, [r3]!
VSHL.U64 d12, d12, d22
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r12]!
VLD1.8 {d6}, [r3]!
VSHL.U64 d16, d16, d22
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VSHL.U64 d4, d4, d22
SUB_ZERO_POINT q8, d16, d30
VSUBL.U8 q9, d18, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d16, d18
VMLAL.S16 q1, d17, d19
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLDR.64 d22, [sp, #-16]
VLDR.64 d23, [sp, #-24]
VCVT.F32.S32 q0, q0
VCVT.F32.S32 q1, q1
VMUL.F32 q0, q0, q14
VMUL.F32 q1, q1, q14
VMIN.F32 q0, q0, q13
VMIN.F32 q1, q1, q13
VMAX.F32 q0, q0, q12
VMAX.F32 q1, q1, q12
VADD.F32 q0, q0, q10
VADD.F32 q1, q1, q10
VSUB.S32 q0, q0, q11
VSUB.S32 q1, q1, q11
VQMOVN.S32 d0, q0
VQMOVN.S32 d1, q1
VQMOVUN.S16 d0, q0
TST r0, 32
BEQ 3f
VST1.32 {d0[0]}, [lr]!
VEXT.8 d0, d0, 4
3:
TST r0, 16
BEQ 4f
VST1.16 {d0[0]}, [lr]!
VEXT.8 d0, d0, 2
4:
TST r0, 8
BEQ 5f
VST1.8 {d0[0]}, [lr]!
5:
# Load output increment
# - r3 = output_increment
LDR r3, [sp, 108]
# Decrement output width
SUBS r1, r1, 1
# Increment output by output_increment
ADD lr, lr, r3
# If output width is non-zero, process another pixel
BNE 0b
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11, pc}
END_FUNCTION pytorch_q8dwconv_ukernel_up8x9__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 9,433 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8dwconv/up8x9-aarch32-neon-per-channel.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
.syntax unified
# void pytorch_q8dwconv_ukernel_up8x9_per_channel__aarch32_neon(
# size_t channels,
# size_t output_width,
# const uint8_t** input,
# const void* weights,
# uint8_t* output,
# size_t input_stride,
# size_t output_increment,
# const union pytorch_qnnp_conv_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8dwconv_ukernel_up8x9_per_channel__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load params
# - r12 = quantization_params
LDR r12, [sp, 12]
PUSH {r4, r5, r6, r7, r8, r9, r10, r11, lr}
VPUSH {d8-d15}
STR r0, [sp, #-8]
STR r3, [sp, #-4]
STR r1, [sp, #-12]
STR r2, [sp, #-16]
# Load the address zero_point array.
LDR r5, [r12], 4
# Push the zero_point_array base pointer on stack
# We dont have enough registers to maintain
# base pointers. Thus we will have to do some pushes
# and pops.
# At sp #-20 we store updated/working copy pointers
# At sp #-28 we store orig pointers that can be reloaded
# for more output pixels
STR r5, [sp, #-28]
# Load o:
# - lr = o = output
LDR lr, [sp, 100]
# Load input zero point:
# - d30 = vinput_zero_point
VLD1.8 {d30[]}, [r12]
# Load the address requantization_scale array.
# For depth wise kernels the array is of single element.
# pre-index r12 = r12 + 4
LDR r5, [r12, 4]!
# Push the requantization_scales base pointer on stack
# At sp #-24 we store updated/working copy pointers
# At sp #-32 we store orig pointers that can be reloaded
# for more output pixels
STR r5, [sp, #-32]
# add 8 bytes to get to vfmax
ADD r12, r12, 8
# Load vfmax:
# - q13 = d26:d27 = vfmax
VLD1.32 {d26[], d27[]}, [r12]!
# Load vfmin:
# - q12 = d24:d25 = vfmin
VLD1.32 {d24[], d25[]}, [r12]!
# Load vfmagic:
# - q10 = d20:d21 = vfmagic
VLD1.32 {d20[], d21[]}, [r12]!
# Load vimagic:
# - q11 = d22:d23 = vimagic
# Since q11/d22 gets used in the remainder channels section
# This load will have to occur in that section again.
# But since r12 is overwritten below, we will have to push it
# on the stack and pop it back.
VLD1.32 {d22[], d23[]}, [r12]
VSTR d22, [sp, #-40]
VSTR d23, [sp, #-48]
.p2align 3
0:
# Load original zero point base pointer
LDR r4, [sp, #-28]
# Load original requant scale base pointer
LDR r5, [sp, #-32]
# Load indirection pointer from stack
LDR r2, [sp, #-16]
# Load input stride
# - r3 = input_stride
LDR r3, [sp, 104]
# Store original zero point to working copy
STR r4, [sp, #-20]
# Store original requant scale to working copy
STR r5, [sp, #-24]
# Load c:
# - r0 = c = channels
LDR r0, [sp, #-8]
# Load i0, i1, i2, i3, i4, i5, i6, i7, i8
# - r4 = i0
# - r5 = i1
# - r6 = i2
# - r7 = i3
# - r8 = i4
# - r9 = i5
# - r10 = i6
# - r11 = i7
# - r12 = i8
LDM r2, {r4, r5, r6, r7, r8, r9, r10, r11, r12}
# Pre-decrement c
SUBS r0, r0, 8
# Increment input by input stride
# - input = r2 := input + input_stride
ADD r2, r2, r3
STR r2, [sp, #-16]
# Load w:
# - r3 = w = weights
LDR r3, [sp, #-4]
BLO 2f
.p2align 4
1:
VLDM r3!, {d0-d3}
VLD1.8 {d4}, [r4]!
VLD1.8 {d6}, [r3]!
# zero point array base address
LDR r1, [sp, #-20]
# requantization scale array base address
LDR r2, [sp, #-24]
VLD1.8 {d8}, [r5]!
VLD1.8 {d10}, [r3]!
# - d31 = vkernel_zero_point
VLD1.8 {d31}, [r1]!
# - q8 = d16:d17= requantization_scale_lo
VLD1.32 {d16, d17}, [r2]!
# - q14 = d28:d29 = requantization_scale_hi
VLD1.32 {d28, d29}, [r2]!
STR r1, [sp, #-20]
STR r2, [sp, #-24]
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VLD1.8 {d12}, [r6]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r7]!
VLD1.8 {d6}, [r3]!
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VLD1.8 {d8}, [r8]!
VLD1.8 {d10}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VLD1.8 {d12}, [r9]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r10]!
VLD1.8 {d6}, [r3]!
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VLD1.8 {d8}, [r11]!
VLD1.8 {d10}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VLD1.8 {d12}, [r12]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VCVT.F32.S32 q0, q0
VCVT.F32.S32 q1, q1
VMUL.F32 q0, q0, q8
VMUL.F32 q1, q1, q14
VMIN.F32 q0, q0, q13
VMIN.F32 q1, q1, q13
VMAX.F32 q0, q0, q12
VMAX.F32 q1, q1, q12
VADD.F32 q0, q0, q10
VADD.F32 q1, q1, q10
VSUB.S32 q0, q0, q11
VSUB.S32 q1, q1, q11
VQMOVN.S32 d0, q0
VQMOVN.S32 d1, q1
VQMOVUN.S16 d0, q0
VST1.8 {d0}, [lr]!
SUBS r0, r0, 8
BHS 1b
2:
CMP r0, -8
BEQ 5f
# zero point array base address
LDR r1, [sp, #-20]
# requantization scale array base address
LDR r2, [sp, #-24]
ADD r4, r4, r0
ADD r5, r5, r0
ADD r6, r6, r0
ADD r7, r7, r0
ADD r8, r8, r0
ADD r9, r9, r0
ADD r10, r10, r0
ADD r11, r11, r0
ADD r12, r12, r0
# - d31 = vkernel_zero_point
VLD1.8 {d31}, [r1]
LSL r0, r0, 3
VDUP.32 d22, r0
VLDM r3!, {d0-d3}
VLD1.8 {d4}, [r4]!
VLD1.8 {d6}, [r3]!
VLD1.8 {d8}, [r5]!
VLD1.8 {d10}, [r3]!
VSHL.U64 d4, d4, d22
VLD1.8 {d12}, [r6]!
VLD1.8 {d14}, [r3]!
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VSHL.U64 d8, d8, d22
VLD1.8 {d16}, [r7]!
VLD1.8 {d18}, [r3]!
VSHL.U64 d12, d12, d22
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r8]!
VLD1.8 {d6}, [r3]!
VSHL.U64 d16, d16, d22
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VLD1.8 {d8}, [r9]!
VLD1.8 {d10}, [r3]!
VSHL.U64 d4, d4, d22
SUB_ZERO_POINT q8, d16, d30
VSUBL.U8 q9, d18, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
VLD1.8 {d12}, [r10]!
VLD1.8 {d14}, [r3]!
VSHL.U64 d8, d8, d22
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d16, d18
VMLAL.S16 q1, d17, d19
VLD1.8 {d16}, [r11]!
VLD1.8 {d18}, [r3]!
VSHL.U64 d12, d12, d22
SUB_ZERO_POINT q4, d8, d30
VSUBL.U8 q5, d10, d31
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLD1.8 {d4}, [r12]!
VLD1.8 {d6}, [r3]!
VSHL.U64 d16, d16, d22
SUB_ZERO_POINT q6, d12, d30
VSUBL.U8 q7, d14, d31
VMLAL.S16 q0, d8, d10
VMLAL.S16 q1, d9, d11
VSHL.U64 d4, d4, d22
SUB_ZERO_POINT q8, d16, d30
VSUBL.U8 q9, d18, d31
VMLAL.S16 q0, d12, d14
VMLAL.S16 q1, d13, d15
SUB_ZERO_POINT q2, d4, d30
VSUBL.U8 q3, d6, d31
VMLAL.S16 q0, d16, d18
VMLAL.S16 q1, d17, d19
# - q8 = d16:d17= requantization_scale_lo
VLD1.32 {d16, d17}, [r2]!
# - q14 = d28:d29 = requantization_scale_hi
VLD1.32 {d28, d29}, [r2]
VMLAL.S16 q0, d4, d6
VMLAL.S16 q1, d5, d7
VLDR.64 d22, [sp, #-40]
VLDR.64 d23, [sp, #-48]
VCVT.F32.S32 q0, q0
VCVT.F32.S32 q1, q1
VMUL.F32 q0, q0, q8
VMUL.F32 q1, q1, q14
VMIN.F32 q0, q0, q13
VMIN.F32 q1, q1, q13
VMAX.F32 q0, q0, q12
VMAX.F32 q1, q1, q12
VADD.F32 q0, q0, q10
VADD.F32 q1, q1, q10
VSUB.S32 q0, q0, q11
VSUB.S32 q1, q1, q11
VQMOVN.S32 d0, q0
VQMOVN.S32 d1, q1
VQMOVUN.S16 d0, q0
TST r0, 32
BEQ 3f
VST1.32 {d0[0]}, [lr]!
VEXT.8 d0, d0, 4
3:
TST r0, 16
BEQ 4f
VST1.16 {d0[0]}, [lr]!
VEXT.8 d0, d0, 2
4:
TST r0, 8
BEQ 5f
VST1.8 {d0[0]}, [lr]!
5:
# Load output_width from stack
LDR r1, [sp, #-12]
# Load output increment
# - r3 = output_increment
LDR r3, [sp, 108]
# Decrement output width
SUBS r1, r1, 1
# store output_width on stack
STR r1, [sp, #-12]
# Increment output by output_increment
ADD lr, lr, r3
# If output width is non-zero, process another pixel
BNE 0b
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11, pc}
END_FUNCTION pytorch_q8dwconv_ukernel_up8x9_per_channel__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 18,255 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8conv/4x8-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
.syntax unified
# Args passed via 4 registers (16 bytes)
# r0: mr
# r1: nr
# r2: kc
# r3: ks
#
# Args passed via stack.
# TOS
# |-----------|
# |a | 0
# |w | 4
# |c | 8
# |c_stride | 12
# |out ch indx| 16
# |params | 20
# |-----------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r8 and d8-d15 on stack
# |-----------|
# |d8 - d15 | 0
# |r4 - r11 | 64
# |a | 96
# |w | 100
# |c | 104
# |c_stride | 108
# |out ch indx| 112
# |params | 116
# |-----------|
#
# void pytorch_q8conv_ukernel_4x8__aarch32_neon(
# size_t mr,
# size_t nr,
# size_t kc,
# size_t ks,
# const uint8_t**restrict a,
# const void*restrict w,
# uint8_t*restrict c,
# size_t c_stride,
# const union pytorch_qnnp_conv_quantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8conv_ukernel_4x8__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load w
# - ip = w
LDR ip, [sp, 4]
PUSH {r4, r5, r6, r7, r8, r9, r10, r11}
# Load params:
# - r9 = params
LDR r9, [sp, 52]
VPUSH {d8-d15}
# Load bias0123, bias4567
VLDM ip!, {d16-d19}
# Load a
# - r8 = a
LDR r8, [sp, 96]
# Load output channel index
LDR r5, [sp, 112]
ADD r7, r9, 4
# Load pointer to per channel zero points array
LDR r4, [r9], 8
# Load pointer to per channel requant scale
# add 8 bytes to get to vfmax
LDR r11, [r9], 8
# Load a_zero_point:
# - d14 = a_zero_point
VLD1.8 {d14[]}, [r7]
# Byte offset of output channel index for requant scale.
LSL r6, r5, 2
# Add offset to the base pointer
ADD r5, r4, r5
# Store in r11 pointer from where to load requant scale.
ADD r11, r11, r6
# q10 := vacc1x0123
VMOV.I32 q10, q8
# q11 := vacc1x4567
VMOV.I32 q11, q9
# q12 := vacc2x0123
VMOV.I32 q12, q8
# q13 := vacc2x4567
VMOV.I32 q13, q9
# q14 := vacc3x0123
VMOV.I32 q14, q8
# Load b_zero_point:
# - d15 = b_zero_point
VLD1.8 {d15}, [r5]
# q15 := vacc3x4567
VMOV.I32 q15, q9
.p2align 5
0:
SUBS r10, r2, 8
# Load a0, a1, a2, a3
# - r4 = a0
# - r5 = a1
# - r6 = a2
# - r7 = a3
LDM r8!, {r4-r7}
BLO 2f
1:
# Load va0
# - d1 = va0
VLD1.8 {d1}, [r4]!
# Load va1
# - d3 = va1
VLD1.8 {d3}, [r5]!
# Load vb0-vb7 (channel 0)
# - d9 = vb0-vb7
VLD1.8 {d9}, [ip:64]!
# Load va2
# - d5 = va2
VLD1.8 {d5}, [r6]!
# q0 = va0 = a0
SUB_ZERO_POINT q0, d1, d14
# Load va3
# - d7 = va3
VLD1.8 {d7}, [r7]!
# q1 = va1 = a1
SUB_ZERO_POINT q1, d3, d14
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 0)
# - d9 = vb4567 (channel 0)
VSUBL.U8 q4, d9, d15
# q2 = va2 = a2
SUB_ZERO_POINT q2, d5, d14
# q3 = va3 = a3
SUB_ZERO_POINT q3, d7, d14
### Channel 0 ###
# Load b0-b7 (channel 1)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[0]
VMLAL.S16 q8, d8, d0[0]
# vacc0x4567 += vb4567 * va0[0]
VMLAL.S16 q9, d9, d0[0]
# vacc1x0123 += vb0123 * va1[0]
VMLAL.S16 q10, d8, d2[0]
# vacc1x4567 += vb4567 * va1[0]
VMLAL.S16 q11, d9, d2[0]
# vacc2x0123 += vb0123 * va2[0]
VMLAL.S16 q12, d8, d4[0]
# vacc2x4567 += vb4567 * va2[0]
VMLAL.S16 q13, d9, d4[0]
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 1)
# - d11 = vb4567 (channel 1)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[0]
VMLAL.S16 q14, d8, d6[0]
# vacc3x4567 += vb4567 * va3[0]
VMLAL.S16 q15, d9, d6[0]
### Channel 1 ###
# Load b0-b7 (channel 2)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[1]
VMLAL.S16 q8, d10, d0[1]
# vacc0x4567 += vb4567 * va0[1]
VMLAL.S16 q9, d11, d0[1]
# vacc1x0123 += vb0123 * va1[1]
VMLAL.S16 q10, d10, d2[1]
# vacc1x4567 += vb4567 * va1[1]
VMLAL.S16 q11, d11, d2[1]
# vacc2x0123 += vb0123 * va2[1]
VMLAL.S16 q12, d10, d4[1]
# vacc2x4567 += vb4567 * va2[1]
VMLAL.S16 q13, d11, d4[1]
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 2)
# - d9 = vb4567 (channel 2)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[1]
VMLAL.S16 q14, d10, d6[1]
# vacc3x4567 += vb4567 * va3[1]
VMLAL.S16 q15, d11, d6[1]
### Channel 2 ###
# Load b0-b7 (channel 3)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[2]
VMLAL.S16 q8, d8, d0[2]
# vacc0x4567 += vb4567 * va0[2]
VMLAL.S16 q9, d9, d0[2]
# vacc1x0123 += vb0123 * va1[2]
VMLAL.S16 q10, d8, d2[2]
# vacc1x4567 += vb4567 * va1[2]
VMLAL.S16 q11, d9, d2[2]
# vacc2x0123 += vb0123 * va2[2]
VMLAL.S16 q12, d8, d4[2]
# vacc2x4567 += vb4567 * va2[2]
VMLAL.S16 q13, d9, d4[2]
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 3)
# - d11 = vb4567 (channel 3)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[2]
VMLAL.S16 q14, d8, d6[2]
# vacc3x4567 += vb4567 * va3[2]
VMLAL.S16 q15, d9, d6[2]
### Channel 3 ###
# Load b0-b7 (channel 4)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[3]
VMLAL.S16 q8, d10, d0[3]
# vacc0x4567 += vb4567 * va0[3]
VMLAL.S16 q9, d11, d0[3]
# vacc1x0123 += vb0123 * va1[3]
VMLAL.S16 q10, d10, d2[3]
# vacc1x4567 += vb4567 * va1[3]
VMLAL.S16 q11, d11, d2[3]
# vacc2x0123 += vb0123 * va2[3]
VMLAL.S16 q12, d10, d4[3]
# vacc2x4567 += vb4567 * va2[3]
VMLAL.S16 q13, d11, d4[3]
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 4)
# - d11 = vb4567 (channel 4)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[3]
VMLAL.S16 q14, d10, d6[3]
# vacc3x4567 += vb4567 * va3[3]
VMLAL.S16 q15, d11, d6[3]
### Channel 4 ###
# Load b0-b7 (channel 5)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[4]
VMLAL.S16 q8, d8, d1[0]
# vacc0x4567 += vb4567 * va0[4]
VMLAL.S16 q9, d9, d1[0]
# vacc1x0123 += vb0123 * va1[4]
VMLAL.S16 q10, d8, d3[0]
# vacc1x4567 += vb4567 * va1[4]
VMLAL.S16 q11, d9, d3[0]
# vacc2x0123 += vb0123 * va2[4]
VMLAL.S16 q12, d8, d5[0]
# vacc2x4567 += vb4567 * va2[4]
VMLAL.S16 q13, d9, d5[0]
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 5)
# - d9 = vb4567 (channel 5)
VSUBL.U8 q5, d11, d15
# vacc3x0123 += vb0123 * va3[4]
VMLAL.S16 q14, d8, d7[0]
# vacc3x4567 += vb4567 * va3[4]
VMLAL.S16 q15, d9, d7[0]
### Channel 5 ###
# Load b0-b7 (channel 6)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# vacc0x0123 += vb0123 * va0[5]
VMLAL.S16 q8, d10, d1[1]
# vacc0x4567 += vb4567 * va0[5]
VMLAL.S16 q9, d11, d1[1]
# vacc1x0123 += vb0123 * va1[5]
VMLAL.S16 q10, d10, d3[1]
# vacc1x4567 += vb4567 * va1[5]
VMLAL.S16 q11, d11, d3[1]
# vacc2x0123 += vb0123 * va2[5]
VMLAL.S16 q12, d10, d5[1]
# vacc2x4567 += vb4567 * va2[5]
VMLAL.S16 q13, d11, d5[1]
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 6)
# - d9 = vb4567 (channel 6)
VSUBL.U8 q4, d9, d15
# vacc3x0123 += vb0123 * va3[5]
VMLAL.S16 q14, d10, d7[1]
# vacc3x4567 += vb4567 * va3[5]
VMLAL.S16 q15, d11, d7[1]
### Channel 6 ###
# Load b0-b7 (channel 7)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# vacc0x0123 += vb0123 * va0[6]
VMLAL.S16 q8, d8, d1[2]
# vacc0x4567 += vb4567 * va0[6]
VMLAL.S16 q9, d9, d1[2]
# vacc1x0123 += vb0123 * va1[6]
VMLAL.S16 q10, d8, d3[2]
# vacc1x4567 += vb4567 * va1[6]
VMLAL.S16 q11, d9, d3[2]
# vacc2x0123 += vb0123 * va2[6]
VMLAL.S16 q12, d8, d5[2]
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 7)
# - d11 = vb4567 (channel 7)
VSUBL.U8 q5, d11, d15
# vacc2x4567 += vb4567 * va2[6]
VMLAL.S16 q13, d9, d5[2]
# vacc3x0123 += vb0123 * va3[6]
VMLAL.S16 q14, d8, d7[2]
# vacc3x4567 += vb4567 * va3[6]
VMLAL.S16 q15, d9, d7[2]
### Channel 8 ###
SUBS r10, r10, 8
# vacc0x0123 += vb0123 * va0[7]
VMLAL.S16 q8, d10, d1[3]
# vacc0x4567 += vb4567 * va0[7]
VMLAL.S16 q9, d11, d1[3]
# vacc1x0123 += vb0123 * va1[7]
VMLAL.S16 q10, d10, d3[3]
# vacc1x4567 += vb4567 * va1[7]
VMLAL.S16 q11, d11, d3[3]
# vacc2x0123 += vb0123 * va2[7]
VMLAL.S16 q12, d10, d5[3]
# vacc2x4567 += vb4567 * va2[7]
VMLAL.S16 q13, d11, d5[3]
# vacc3x0123 += vb0123 * va3[7]
VMLAL.S16 q14, d10, d7[3]
# vacc3x4567 += vb4567 * va3[7]
VMLAL.S16 q15, d11, d7[3]
BHS 1b
2:
CMP r10, -8
BEQ 3f
# Adjust a0, a1, a2, a3
ADD r4, r10
ADD r5, r10
ADD r6, r10
ADD r7, r10
# a_shift = 8 * k - 64
LSL r10, r10, 3
VDUP.32 d13, r10
# Load va0
# - d1 = va0
VLD1.8 {d1}, [r4]
# Load va1
# - d3 = va1
VLD1.8 {d3}, [r5]
# Load b0-b7 (channel 0)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# Load a2
# - d5 = a2
VLD1.8 {d5}, [r6]
# q0 = va0 = a0
VSHL.U64 d1, d1, d13
SUB_ZERO_POINT q0, d1, d14
# Load a3
# - d7 = a3
VLD1.8 {d7}, [r7]
# q1 = va1 = a1
VSHL.U64 d3, d3, d13
SUB_ZERO_POINT q1, d3, d14
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 0)
# - d9 = vb4567 (channel 0)
VSUBL.U8 q4, d9, d15
# q2 = va2 = a2
VSHL.U64 d5, d5, d13
SUB_ZERO_POINT q2, d5, d14
# q3 = va3 = a3
VSHL.U64 d7, d7, d13
SUB_ZERO_POINT q3, d7, d14
### Channel 0 ###
# vacc0x0123 += vb0123 * va0[0]
VMLAL.S16 q8, d8, d0[0]
# vacc0x4567 += vb4567 * va0[0]
VMLAL.S16 q9, d9, d0[0]
# vacc1x0123 += vb0123 * va1[0]
VMLAL.S16 q10, d8, d2[0]
# vacc1x4567 += vb4567 * va1[0]
VMLAL.S16 q11, d9, d2[0]
# vacc2x0123 += vb0123 * va2[0]
VMLAL.S16 q12, d8, d4[0]
# vacc2x4567 += vb4567 * va2[0]
VMLAL.S16 q13, d9, d4[0]
# vacc3x0123 += vb0123 * va3[0]
VMLAL.S16 q14, d8, d6[0]
# vacc3x4567 += vb4567 * va3[0]
VMLAL.S16 q15, d9, d6[0]
CMP r10, -48
BLO 3f
### Channel 1 ###
# Load b0-b7 (channel 1)
# - d11 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 1)
# - d11 = vb4567 (channel 1)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[1]
VMLAL.S16 q8, d10, d0[1]
# vacc0x4567 += vb4567 * va0[1]
VMLAL.S16 q9, d11, d0[1]
# vacc1x0123 += vb0123 * va1[1]
VMLAL.S16 q10, d10, d2[1]
# vacc1x4567 += vb4567 * va1[1]
VMLAL.S16 q11, d11, d2[1]
# vacc2x0123 += vb0123 * va2[1]
VMLAL.S16 q12, d10, d4[1]
# vacc2x4567 += vb4567 * va2[1]
VMLAL.S16 q13, d11, d4[1]
# vacc3x0123 += vb0123 * va3[1]
VMLAL.S16 q14, d10, d6[1]
# vacc3x4567 += vb4567 * va3[1]
VMLAL.S16 q15, d11, d6[1]
### Channel 2 ###
BLS 3f
# Load b0-b7 (channel 2)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 2)
# - d9 = vb4567 (channel 2)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[2]
VMLAL.S16 q8, d8, d0[2]
# vacc0x4567 += vb4567 * va0[2]
VMLAL.S16 q9, d9, d0[2]
# vacc1x0123 += vb0123 * va1[2]
VMLAL.S16 q10, d8, d2[2]
# vacc1x4567 += vb4567 * va1[2]
VMLAL.S16 q11, d9, d2[2]
# vacc2x0123 += vb0123 * va2[2]
VMLAL.S16 q12, d8, d4[2]
# vacc2x4567 += vb4567 * va2[2]
VMLAL.S16 q13, d9, d4[2]
# vacc3x0123 += vb0123 * va3[2]
VMLAL.S16 q14, d8, d6[2]
# vacc3x4567 += vb4567 * va3[2]
VMLAL.S16 q15, d9, d6[2]
### Channel 3 ###
CMP r10, -32
BLO 3f
# Load b0-b7 (channel 3)
# - d9 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 3)
# - d9 = vb4567 (channel 3)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[3]
VMLAL.S16 q8, d10, d0[3]
# vacc0x4567 += vb4567 * va0[3]
VMLAL.S16 q9, d11, d0[3]
# vacc1x0123 += vb0123 * va1[3]
VMLAL.S16 q10, d10, d2[3]
# vacc1x4567 += vb4567 * va1[3]
VMLAL.S16 q11, d11, d2[3]
# vacc2x0123 += vb0123 * va2[3]
VMLAL.S16 q12, d10, d4[3]
# vacc2x4567 += vb4567 * va2[3]
VMLAL.S16 q13, d11, d4[3]
# vacc3x0123 += vb0123 * va3[3]
VMLAL.S16 q14, d10, d6[3]
# vacc3x4567 += vb4567 * va3[3]
VMLAL.S16 q15, d11, d6[3]
### Channel 4 ###
BLS 3f
# Load b0-b7 (channel 4)
# - d11 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 4)
# - d11 = vb4567 (channel 4)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[4]
VMLAL.S16 q8, d8, d1[0]
# vacc0x4567 += vb4567 * va0[4]
VMLAL.S16 q9, d9, d1[0]
# vacc1x0123 += vb0123 * va1[4]
VMLAL.S16 q10, d8, d3[0]
# vacc1x4567 += vb4567 * va1[4]
VMLAL.S16 q11, d9, d3[0]
# vacc2x0123 += vb0123 * va2[4]
VMLAL.S16 q12, d8, d5[0]
# vacc2x4567 += vb4567 * va2[4]
VMLAL.S16 q13, d9, d5[0]
# vacc3x0123 += vb0123 * va3[4]
VMLAL.S16 q14, d8, d7[0]
# vacc3x4567 += vb4567 * va3[4]
VMLAL.S16 q15, d9, d7[0]
### Channel 5 ###
CMP r10, -16
BLO 3f
# Load b0-b7 (channel 5)
# - d13 = b0-b7
VLD1.8 {d11}, [ip:64]!
# q5 = b0:7 - vb_zero_point
# - d10 = vb0123 (channel 5)
# - d11 = vb4567 (channel 5)
VSUBL.U8 q5, d11, d15
# vacc0x0123 += vb0123 * va0[5]
VMLAL.S16 q8, d10, d1[1]
# vacc0x4567 += vb4567 * va0[5]
VMLAL.S16 q9, d11, d1[1]
# vacc1x0123 += vb0123 * va1[5]
VMLAL.S16 q10, d10, d3[1]
# vacc1x4567 += vb4567 * va1[5]
VMLAL.S16 q11, d11, d3[1]
# vacc2x0123 += vb0123 * va2[5]
VMLAL.S16 q12, d10, d5[1]
# vacc2x4567 += vb4567 * va2[5]
VMLAL.S16 q13, d11, d5[1]
# vacc3x0123 += vb0123 * va3[5]
VMLAL.S16 q14, d10, d7[1]
# vacc3x4567 += vb4567 * va3[5]
VMLAL.S16 q15, d11, d7[1]
### Channel 6 ###
BLS 3f
# Load b0-b7 (channel 6)
# - d9 = b0-b7
VLD1.8 {d9}, [ip:64]!
# q4 = b0:7 - vb_zero_point
# - d8 = vb0123 (channel 6)
# - d9 = vb4567 (channel 6)
VSUBL.U8 q4, d9, d15
# vacc0x0123 += vb0123 * va0[6]
VMLAL.S16 q8, d8, d1[2]
# vacc0x4567 += vb4567 * va0[6]
VMLAL.S16 q9, d9, d1[2]
# vacc1x0123 += vb0123 * va1[6]
VMLAL.S16 q10, d8, d3[2]
# vacc1x4567 += vb4567 * va1[6]
VMLAL.S16 q11, d9, d3[2]
# vacc2x0123 += vb0123 * va2[6]
VMLAL.S16 q12, d8, d5[2]
# vacc2x4567 += vb4567 * va2[6]
VMLAL.S16 q13, d9, d5[2]
# vacc3x0123 += vb0123 * va3[6]
VMLAL.S16 q14, d8, d7[2]
# vacc3x4567 += vb4567 * va3[6]
VMLAL.S16 q15, d9, d7[2]
.p2align 4
3:
SUBS r3, r3, 1
BNE 0b
# Load requantization_scale:
# - d12 = requantization_scale
VLD1.32 {d12, d13}, [r11]!
# Load vfmax:
VLD1.32 {d10[], d11[]}, [r9]!
VLD1.32 {d4, d5}, [r11]
# Load vfmin:
VLD1.32 {d8[], d9[]}, [r9]!
# Load vfmagic:
VLD1.32 {d0[], d1[]}, [r9]!
# Load vimagic:
VLD1.32 {d2[], d3[]}, [r9]!
VCVT.F32.S32 q8, q8
VCVT.F32.S32 q9, q9
VCVT.F32.S32 q10, q10
VCVT.F32.S32 q11, q11
VCVT.F32.S32 q12, q12
VCVT.F32.S32 q13, q13
VCVT.F32.S32 q14, q14
VCVT.F32.S32 q15, q15
VMUL.F32 q8, q8, q6
VMUL.F32 q9, q9, q2
VMUL.F32 q10, q10, q6
VMUL.F32 q11, q11, q2
VMUL.F32 q12, q12, q6
VMUL.F32 q13, q13, q2
VMUL.F32 q14, q14, q6
VMUL.F32 q15, q15, q2
VMIN.F32 q8, q8, q5
VMIN.F32 q9, q9, q5
VMIN.F32 q10, q10, q5
VMIN.F32 q11, q11, q5
VMIN.F32 q12, q12, q5
VMIN.F32 q13, q13, q5
VMIN.F32 q14, q14, q5
VMIN.F32 q15, q15, q5
VMAX.F32 q8, q8, q4
VMAX.F32 q9, q9, q4
VMAX.F32 q10, q10, q4
VMAX.F32 q11, q11, q4
VMAX.F32 q12, q12, q4
VMAX.F32 q13, q13, q4
VMAX.F32 q14, q14, q4
VMAX.F32 q15, q15, q4
VADD.F32 q8, q8, q0
VADD.F32 q9, q9, q0
VADD.F32 q10, q10, q0
VADD.F32 q11, q11, q0
VADD.F32 q12, q12, q0
VADD.F32 q13, q13, q0
VADD.F32 q14, q14, q0
VADD.F32 q15, q15, q0
# Load c, c_stride:
# - r2 = c
# - r2 = c_stride
LDRD r2, r3, [sp, 104]
VSUB.S32 q8, q8, q1
VSUB.S32 q9, q9, q1
VSUB.S32 q10, q10, q1
VSUB.S32 q11, q11, q1
VSUB.S32 q12, q12, q1
VSUB.S32 q13, q13, q1
VSUB.S32 q14, q14, q1
VSUB.S32 q15, q15, q1
ADD r4, r2, r3
VQMOVN.S32 d16, q8
VQMOVN.S32 d17, q9
CMP r0, 2
VQMOVN.S32 d18, q10
VQMOVN.S32 d19, q11
MOVLO r4, r2
VQMOVN.S32 d20, q12
VQMOVN.S32 d21, q13
VQMOVN.S32 d22, q14
VQMOVN.S32 d23, q15
ADD r5, r4, r3
VQMOVUN.S16 d16, q8
MOVLS r5, r4
VQMOVUN.S16 d17, q9
VQMOVUN.S16 d18, q10
CMP r0, 4
ADD r3, r5, r3
MOVNE r3, r5
CMP r1, 8
VQMOVUN.S16 d19, q11
BNE 5f
VST1.8 {d16}, [r2]
VST1.8 {d17}, [r4]
VST1.8 {d18}, [r5]
VST1.8 {d19}, [r3]
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
.p2align 3
5:
CMP r1, 4
BLO 6f
VST1.32 {d16[0]}, [r2]!
VST1.32 {d17[0]}, [r4]!
VST1.32 {d18[0]}, [r5]!
VST1.32 {d19[0]}, [r3]!
SUB r1, 4
VEXT.8 q8, q8, q8, 4
VEXT.8 q9, q9, q9, 4
6:
CMP r1, 2
BLO 7f
VST1.16 {d16[0]}, [r2]!
VST1.16 {d17[0]}, [r4]!
VST1.16 {d18[0]}, [r5]!
VST1.16 {d19[0]}, [r3]!
SUB r1, 2
VEXT.8 q8, q8, q8, 2
VEXT.8 q9, q9, q9, 2
7:
TEQ r1, 0
BEQ 8f
VST1.8 {d16[0]}, [r2]
VST1.8 {d17[0]}, [r4]
VST1.8 {d18[0]}, [r5]
VST1.8 {d19[0]}, [r3]
8:
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
END_FUNCTION pytorch_q8conv_ukernel_4x8__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 27,616 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8conv/8x8-aarch64-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
# Args passed via 8 registers (64 bytes)
# x0: mr
# x1: nr
# x2: kc
# x3: ks
# x4: a
# x5: w
# x6: c
# x7: c_stride
#
# Args passed via stack.
# TOS
# |-----------|
# |out ch indx| 0
# |params | 8
# |-----------|
# void pytorch_q8conv_ukernel_8x8__aarch64_neon(
# size_t mr,
# size_t nr,
# size_t kc,
# size_t ks,
# const uint8_t** restrict a,
# const void* restrict w,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_q31_requantization_params quantization_params[restrict static 1])
BEGIN_FUNCTION pytorch_q8conv_ukernel_8x8__aarch64_neon
# Load params: x8
# Load output channel index: x9
# Note since this is an offset into a byte pointer
# We do not need to multiply with size of pointer type
LDP x9, x8, [sp]
STP d15, d14, [sp, -16]
STP d13, d12, [sp, -32]
STP d11, d10, [sp, -48]
STP d9, d8, [sp, -64]
# Load bias0123, bias4567
LD1 {v8.4s, v9.4s}, [x5], 32
# Load pointer to per channel zero points array
# And go to a_zero_point with post-index
LDR x10, [x8], 8
# Add offset to the base pointer
ADD x10, x10, x9
# v10 := vacc1x0123
MOV v10.16b, v8.16b
# v11 := vacc1x4567
MOV v11.16b, v9.16b
# Load b_zero_point
LD1 {v25.8b}, [x10]
# Load a_zero_point
LD1R {v24.8b}, [x8]
# Load pointer to per channel requant scale
LDR x10, [x8, 8]!
ADD x8, x8, 8
# v12 := vacc2x0123
MOV v12.16b, v8.16b
# v13 := vacc2x4567
MOV v13.16b, v9.16b
# v14 := vacc3x0123
MOV v14.16b, v8.16b
# v15 := vacc3x4567
MOV v15.16b, v9.16b
# v16 := vacc4x0123
MOV v16.16b, v8.16b
# v17 := vacc4x4567
MOV v17.16b, v9.16b
# v18 := vacc5x0123
MOV v18.16b, v8.16b
# v19 := vacc5x4567
MOV v19.16b, v9.16b
# v20 := vacc6x0123
MOV v20.16b, v8.16b
# v21 := vacc6x4567
MOV v21.16b, v9.16b
# v22 := vacc7x0123
MOV v22.16b, v8.16b
# v23 := vacc7x4567
MOV v23.16b, v9.16b
# Fold mul by 4 to get byte offset for requant scale.
# Add offset to the base pointer
ADD x10, x10, x9, lsl#2
// Load requantization_scale
// - v26 = requantization_scale channels 0-3
// - v31 = requantization_scale channels 4-7
LD1 {v26.4s}, [x10], 16
LD1 {v30.4s}, [x10]
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 4
#endif
3:
MOV x17, x2
LDR x16, [x4], 8 // a0
LDR x9, [x4], 8 // a1
LDR x10, [x4], 8 // a2
LDR x11, [x4], 8 // a3
LDR x12, [x4], 8 // a4
LDR x13, [x4], 8 // a5
LDR x14, [x4], 8 // a6
LDR x15, [x4], 8 // a7
SUBS x17, x17, 8
B.LO 1f
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 5
#endif
0:
# b0-7 (channel 0)
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
# va0 - va7 := va - va_offset
LD1 {v0.8b}, [x16], 8
SUB_ZERO_POINT v0.8h, v0.8b, v24.8b
LD1 {v1.8b}, [x9], 8
SUB_ZERO_POINT v1.8h, v1.8b, v24.8b
LD1 {v2.8b}, [x10], 8
SUB_ZERO_POINT v2.8h, v2.8b, v24.8b
LD1 {v3.8b}, [x11], 8
SUB_ZERO_POINT v3.8h, v3.8b, v24.8b
LD1 {v4.8b}, [x12], 8
SUB_ZERO_POINT v4.8h, v4.8b, v24.8b
LD1 {v5.8b}, [x13], 8
SUB_ZERO_POINT v5.8h, v5.8b, v24.8b
LD1 {v6.8b}, [x14], 8
SUB_ZERO_POINT v6.8h, v6.8b, v24.8b
LD1 {v7.8b}, [x15], 8
SUB_ZERO_POINT v7.8h, v7.8b, v24.8b
// b0-7 (channel 1)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[0] // vacc0x0123 += vb0123 * va0[0]
SMLAL2 v9.4s, v27.8h, v0.h[0] // vacc0x4567 += vb4567 * va0[0]
SMLAL v10.4s, v27.4h, v1.h[0] // vacc1x0123 += vb0123 * va1[0]
SMLAL2 v11.4s, v27.8h, v1.h[0] // vacc1x4567 += vb4567 * va1[0]
SMLAL v12.4s, v27.4h, v2.h[0] // vacc2x0123 += vb0123 * va2[0]
SMLAL2 v13.4s, v27.8h, v2.h[0] // vacc2x4567 += vb4567 * va2[0]
SMLAL v14.4s, v27.4h, v3.h[0] // vacc3x0123 += vb0123 * va3[0]
SMLAL2 v15.4s, v27.8h, v3.h[0] // vacc3x4567 += vb4567 * va3[0]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[0] // vacc4x0123 += vb0123 * va4[0]
SMLAL2 v17.4s, v27.8h, v4.h[0] // vacc4x4567 += vb4567 * va4[0]
SMLAL v18.4s, v27.4h, v5.h[0] // vacc5x0123 += vb0123 * va5[0]
SMLAL2 v19.4s, v27.8h, v5.h[0] // vacc5x4567 += vb4567 * va5[0]
SMLAL v20.4s, v27.4h, v6.h[0] // vacc6x0123 += vb0123 * va6[0]
SMLAL2 v21.4s, v27.8h, v6.h[0] // vacc6x4567 += vb4567 * va6[0]
SMLAL v22.4s, v27.4h, v7.h[0] // vacc7x0123 += vb0123 * va7[0]
SMLAL2 v23.4s, v27.8h, v7.h[0] // vacc7x4567 += vb4567 * va7[0]
// b0-7 (channel 2)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[1] // vacc0x0123 += vb0123 * va0[1]
SMLAL2 v9.4s, v28.8h, v0.h[1] // vacc0x4567 += vb4567 * va0[1]
SMLAL v10.4s, v28.4h, v1.h[1] // vacc1x0123 += vb0123 * va1[1]
SMLAL2 v11.4s, v28.8h, v1.h[1] // vacc1x4567 += vb4567 * va1[1]
SMLAL v12.4s, v28.4h, v2.h[1] // vacc2x0123 += vb0123 * va2[1]
SMLAL2 v13.4s, v28.8h, v2.h[1] // vacc2x4567 += vb4567 * va2[1]
SMLAL v14.4s, v28.4h, v3.h[1] // vacc3x0123 += vb0123 * va3[1]
SMLAL2 v15.4s, v28.8h, v3.h[1] // vacc3x4567 += vb4567 * va3[1]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[1] // vacc4x0123 += vb0123 * va4[1]
SMLAL2 v17.4s, v28.8h, v4.h[1] // vacc4x4567 += vb4567 * va4[1]
SMLAL v18.4s, v28.4h, v5.h[1] // vacc5x0123 += vb0123 * va5[1]
SMLAL2 v19.4s, v28.8h, v5.h[1] // vacc5x4567 += vb4567 * va5[1]
SMLAL v20.4s, v28.4h, v6.h[1] // vacc6x0123 += vb0123 * va6[1]
SMLAL2 v21.4s, v28.8h, v6.h[1] // vacc6x4567 += vb4567 * va6[1]
SMLAL v22.4s, v28.4h, v7.h[1] // vacc7x0123 += vb0123 * va7[1]
SMLAL2 v23.4s, v28.8h, v7.h[1] // vacc7x4567 += vb4567 * va7[1]
// b0-7 (channel 3)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[2] // vacc0x0123 += vb0123 * va0[2]
SMLAL2 v9.4s, v27.8h, v0.h[2] // vacc0x4567 += vb4567 * va0[2]
SMLAL v10.4s, v27.4h, v1.h[2] // vacc1x0123 += vb0123 * va1[2]
SMLAL2 v11.4s, v27.8h, v1.h[2] // vacc1x4567 += vb4567 * va1[2]
SMLAL v12.4s, v27.4h, v2.h[2] // vacc2x0123 += vb0123 * va2[2]
SMLAL2 v13.4s, v27.8h, v2.h[2] // vacc2x4567 += vb4567 * va2[2]
SMLAL v14.4s, v27.4h, v3.h[2] // vacc3x0123 += vb0123 * va3[2]
SMLAL2 v15.4s, v27.8h, v3.h[2] // vacc3x4567 += vb4567 * va3[2]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[2] // vacc4x0123 += vb0123 * va4[2]
SMLAL2 v17.4s, v27.8h, v4.h[2] // vacc4x4567 += vb4567 * va4[2]
SMLAL v18.4s, v27.4h, v5.h[2] // vacc5x0123 += vb0123 * va5[2]
SMLAL2 v19.4s, v27.8h, v5.h[2] // vacc5x4567 += vb4567 * va5[2]
SMLAL v20.4s, v27.4h, v6.h[2] // vacc6x0123 += vb0123 * va6[2]
SMLAL2 v21.4s, v27.8h, v6.h[2] // vacc6x4567 += vb4567 * va6[2]
SMLAL v22.4s, v27.4h, v7.h[2] // vacc7x0123 += vb0123 * va7[2]
SMLAL2 v23.4s, v27.8h, v7.h[2] // vacc7x4567 += vb4567 * va7[2]
// b0-7 (channel 4)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[3] // vacc0x0123 += vb0123 * va0[3]
SMLAL2 v9.4s, v28.8h, v0.h[3] // vacc0x4567 += vb4567 * va0[3]
SMLAL v10.4s, v28.4h, v1.h[3] // vacc1x0123 += vb0123 * va1[3]
SMLAL2 v11.4s, v28.8h, v1.h[3] // vacc1x4567 += vb4567 * va1[3]
SMLAL v12.4s, v28.4h, v2.h[3] // vacc2x0123 += vb0123 * va2[3]
SMLAL2 v13.4s, v28.8h, v2.h[3] // vacc2x4567 += vb4567 * va2[3]
SMLAL v14.4s, v28.4h, v3.h[3] // vacc3x0123 += vb0123 * va3[3]
SMLAL2 v15.4s, v28.8h, v3.h[3] // vacc3x4567 += vb4567 * va3[3]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[3] // vacc4x0123 += vb0123 * va4[3]
SMLAL2 v17.4s, v28.8h, v4.h[3] // vacc4x4567 += vb4567 * va4[3]
SMLAL v18.4s, v28.4h, v5.h[3] // vacc5x0123 += vb0123 * va5[3]
SMLAL2 v19.4s, v28.8h, v5.h[3] // vacc5x4567 += vb4567 * va5[3]
SMLAL v20.4s, v28.4h, v6.h[3] // vacc6x0123 += vb0123 * va6[3]
SMLAL2 v21.4s, v28.8h, v6.h[3] // vacc6x4567 += vb4567 * va6[3]
SMLAL v22.4s, v28.4h, v7.h[3] // vacc7x0123 += vb0123 * va7[3]
SMLAL2 v23.4s, v28.8h, v7.h[3] // vacc7x4567 += vb4567 * va7[3]
// b0-7 (channel 5)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[4] // vacc0x0123 += vb0123 * va0[4]
SMLAL2 v9.4s, v27.8h, v0.h[4] // vacc0x4567 += vb4567 * va0[4]
SMLAL v10.4s, v27.4h, v1.h[4] // vacc1x0123 += vb0123 * va1[4]
SMLAL2 v11.4s, v27.8h, v1.h[4] // vacc1x4567 += vb4567 * va1[4]
SMLAL v12.4s, v27.4h, v2.h[4] // vacc2x0123 += vb0123 * va2[4]
SMLAL2 v13.4s, v27.8h, v2.h[4] // vacc2x4567 += vb4567 * va2[4]
SMLAL v14.4s, v27.4h, v3.h[4] // vacc3x0123 += vb0123 * va3[4]
SMLAL2 v15.4s, v27.8h, v3.h[4] // vacc3x4567 += vb4567 * va3[4]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[4] // vacc4x0123 += vb0123 * va4[4]
SMLAL2 v17.4s, v27.8h, v4.h[4] // vacc4x4567 += vb4567 * va4[4]
SMLAL v18.4s, v27.4h, v5.h[4] // vacc5x0123 += vb0123 * va5[4]
SMLAL2 v19.4s, v27.8h, v5.h[4] // vacc5x4567 += vb4567 * va5[4]
SMLAL v20.4s, v27.4h, v6.h[4] // vacc6x0123 += vb0123 * va6[4]
SMLAL2 v21.4s, v27.8h, v6.h[4] // vacc6x4567 += vb4567 * va6[4]
SMLAL v22.4s, v27.4h, v7.h[4] // vacc7x0123 += vb0123 * va7[4]
SMLAL2 v23.4s, v27.8h, v7.h[4] // vacc7x4567 += vb4567 * va7[4]
// b0-7 (channel 6)
LD1 {v27.8b}, [x5], 8
SMLAL v8.4s, v28.4h, v0.h[5] // vacc0x0123 += vb0123 * va0[5]
SMLAL2 v9.4s, v28.8h, v0.h[5] // vacc0x4567 += vb4567 * va0[5]
SMLAL v10.4s, v28.4h, v1.h[5] // vacc1x0123 += vb0123 * va1[5]
SMLAL2 v11.4s, v28.8h, v1.h[5] // vacc1x4567 += vb4567 * va1[5]
SMLAL v12.4s, v28.4h, v2.h[5] // vacc2x0123 += vb0123 * va2[5]
SMLAL2 v13.4s, v28.8h, v2.h[5] // vacc2x4567 += vb4567 * va2[5]
SMLAL v14.4s, v28.4h, v3.h[5] // vacc3x0123 += vb0123 * va3[5]
SMLAL2 v15.4s, v28.8h, v3.h[5] // vacc3x4567 += vb4567 * va3[5]
USUBL v27.8h, v27.8b, v25.8b
SMLAL v16.4s, v28.4h, v4.h[5] // vacc4x0123 += vb0123 * va4[5]
SMLAL2 v17.4s, v28.8h, v4.h[5] // vacc4x4567 += vb4567 * va4[5]
SMLAL v18.4s, v28.4h, v5.h[5] // vacc5x0123 += vb0123 * va5[5]
SMLAL2 v19.4s, v28.8h, v5.h[5] // vacc5x4567 += vb4567 * va5[5]
SMLAL v20.4s, v28.4h, v6.h[5] // vacc6x0123 += vb0123 * va6[5]
SMLAL2 v21.4s, v28.8h, v6.h[5] // vacc6x4567 += vb4567 * va6[5]
SMLAL v22.4s, v28.4h, v7.h[5] // vacc7x0123 += vb0123 * va7[5]
SMLAL2 v23.4s, v28.8h, v7.h[5] // vacc7x4567 += vb4567 * va7[5]
// b0-7 (channel 7)
LD1 {v28.8b}, [x5], 8
SMLAL v8.4s, v27.4h, v0.h[6] // vacc0x0123 += vb0123 * va0[6]
SMLAL2 v9.4s, v27.8h, v0.h[6] // vacc0x4567 += vb4567 * va0[6]
SMLAL v10.4s, v27.4h, v1.h[6] // vacc1x0123 += vb0123 * va1[6]
SMLAL2 v11.4s, v27.8h, v1.h[6] // vacc1x4567 += vb4567 * va1[6]
SMLAL v12.4s, v27.4h, v2.h[6] // vacc2x0123 += vb0123 * va2[6]
SMLAL2 v13.4s, v27.8h, v2.h[6] // vacc2x4567 += vb4567 * va2[6]
SMLAL v14.4s, v27.4h, v3.h[6] // vacc3x0123 += vb0123 * va3[6]
SMLAL2 v15.4s, v27.8h, v3.h[6] // vacc3x4567 += vb4567 * va3[6]
USUBL v28.8h, v28.8b, v25.8b
SMLAL v16.4s, v27.4h, v4.h[6] // vacc4x0123 += vb0123 * va4[6]
SMLAL2 v17.4s, v27.8h, v4.h[6] // vacc4x4567 += vb4567 * va4[6]
SMLAL v18.4s, v27.4h, v5.h[6] // vacc5x0123 += vb0123 * va5[6]
SMLAL2 v19.4s, v27.8h, v5.h[6] // vacc5x4567 += vb4567 * va5[6]
SMLAL v20.4s, v27.4h, v6.h[6] // vacc6x0123 += vb0123 * va6[6]
SMLAL2 v21.4s, v27.8h, v6.h[6] // vacc6x4567 += vb4567 * va6[6]
SMLAL v22.4s, v27.4h, v7.h[6] // vacc7x0123 += vb0123 * va7[6]
SMLAL2 v23.4s, v27.8h, v7.h[6] // vacc7x4567 += vb4567 * va7[6]
SUBS x17, x17, 8
SMLAL v8.4s, v28.4h, v0.h[7] // vacc0x0123 += vb0123 * va0[7]
SMLAL2 v9.4s, v28.8h, v0.h[7] // vacc0x4567 += vb4567 * va0[7]
SMLAL v10.4s, v28.4h, v1.h[7] // vacc1x0123 += vb0123 * va1[7]
SMLAL2 v11.4s, v28.8h, v1.h[7] // vacc1x4567 += vb4567 * va1[7]
SMLAL v12.4s, v28.4h, v2.h[7] // vacc2x0123 += vb0123 * va2[7]
SMLAL2 v13.4s, v28.8h, v2.h[7] // vacc2x4567 += vb4567 * va2[7]
SMLAL v14.4s, v28.4h, v3.h[7] // vacc3x0123 += vb0123 * va3[7]
SMLAL2 v15.4s, v28.8h, v3.h[7] // vacc3x4567 += vb4567 * va3[7]
SMLAL v16.4s, v28.4h, v4.h[7] // vacc4x0123 += vb0123 * va4[7]
SMLAL2 v17.4s, v28.8h, v4.h[7] // vacc4x4567 += vb4567 * va4[7]
SMLAL v18.4s, v28.4h, v5.h[7] // vacc5x0123 += vb0123 * va5[7]
SMLAL2 v19.4s, v28.8h, v5.h[7] // vacc5x4567 += vb4567 * va5[7]
SMLAL v20.4s, v28.4h, v6.h[7] // vacc6x0123 += vb0123 * va6[7]
SMLAL2 v21.4s, v28.8h, v6.h[7] // vacc6x4567 += vb4567 * va6[7]
SMLAL v22.4s, v28.4h, v7.h[7] // vacc7x0123 += vb0123 * va7[7]
SMLAL2 v23.4s, v28.8h, v7.h[7] // vacc7x4567 += vb4567 * va7[7]
B.HS 0b
1:
CMP x17, -8
B.EQ 2f
// Adjust a0-a7
ADD x16, x16, x17
ADD x9, x9, x17
ADD x10, x10, x17
ADD x11, x11, x17
ADD x12, x12, x17
ADD x13, x13, x17
ADD x14, x14, x17
ADD x15, x15, x17
// a_shift = 8 * k - 64
LSL x17, x17, 3
FMOV d29, x17
USHL d31, d24, d29
// Load x0-a7
LD1 {v0.8b}, [x16], 8
USHL d0, d0, d29
SUB_ZERO_POINT v0.8h, v0.8b, v24.8b
LD1 {v1.8b}, [x9], 8
USHL d1, d1, d29
SUB_ZERO_POINT v1.8h, v1.8b, v24.8b
LD1 {v2.8b}, [x10], 8
USHL d2, d2, d29
SUB_ZERO_POINT v2.8h, v2.8b, v24.8b
LD1 {v3.8b}, [x11], 8
USHL d3, d3, d29
SUB_ZERO_POINT v3.8h, v3.8b, v24.8b
LD1 {v4.8b}, [x12], 8
USHL d4, d4, d29
SUB_ZERO_POINT v4.8h, v4.8b, v24.8b
LD1 {v5.8b}, [x13], 8
USHL d5, d5, d29
SUB_ZERO_POINT v5.8h, v5.8b, v24.8b
LD1 {v6.8b}, [x14], 8
USHL d6, d6, d29
SUB_ZERO_POINT v6.8h, v6.8b, v24.8b
LD1 {v7.8b}, [x15], 8
USHL d7, d7, d29
SUB_ZERO_POINT v7.8h, v7.8b, v24.8b
// Channel 0
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[0] // vacc0x0123 += vb0123 * va0[0]
SMLAL2 v9.4s, v27.8h, v0.h[0] // vacc0x4567 += vb4567 * va0[0]
SMLAL v10.4s, v27.4h, v1.h[0] // vacc1x0123 += vb0123 * va1[0]
SMLAL2 v11.4s, v27.8h, v1.h[0] // vacc1x4567 += vb4567 * va1[0]
SMLAL v12.4s, v27.4h, v2.h[0] // vacc2x0123 += vb0123 * va2[0]
SMLAL2 v13.4s, v27.8h, v2.h[0] // vacc2x4567 += vb4567 * va2[0]
SMLAL v14.4s, v27.4h, v3.h[0] // vacc3x0123 += vb0123 * va3[0]
SMLAL2 v15.4s, v27.8h, v3.h[0] // vacc3x4567 += vb4567 * va3[0]
SMLAL v16.4s, v27.4h, v4.h[0] // vacc4x0123 += vb0123 * va4[0]
SMLAL2 v17.4s, v27.8h, v4.h[0] // vacc4x4567 += vb4567 * va4[0]
SMLAL v18.4s, v27.4h, v5.h[0] // vacc5x0123 += vb0123 * va5[0]
SMLAL2 v19.4s, v27.8h, v5.h[0] // vacc5x4567 += vb4567 * va5[0]
SMLAL v20.4s, v27.4h, v6.h[0] // vacc6x0123 += vb0123 * va6[0]
SMLAL2 v21.4s, v27.8h, v6.h[0] // vacc6x4567 += vb4567 * va6[0]
SMLAL v22.4s, v27.4h, v7.h[0] // vacc7x0123 += vb0123 * va7[0]
SMLAL2 v23.4s, v27.8h, v7.h[0] // vacc7x4567 += vb4567 * va7[0]
CMP x17, -48
B.LO 2f
// Channel 1
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[1] // vacc0x0123 += vb0123 * va0[1]
SMLAL2 v9.4s, v28.8h, v0.h[1] // vacc0x4567 += vb4567 * va0[1]
SMLAL v10.4s, v28.4h, v1.h[1] // vacc1x0123 += vb0123 * va1[1]
SMLAL2 v11.4s, v28.8h, v1.h[1] // vacc1x4567 += vb4567 * va1[1]
SMLAL v12.4s, v28.4h, v2.h[1] // vacc2x0123 += vb0123 * va2[1]
SMLAL2 v13.4s, v28.8h, v2.h[1] // vacc2x4567 += vb4567 * va2[1]
SMLAL v14.4s, v28.4h, v3.h[1] // vacc3x0123 += vb0123 * va3[1]
SMLAL2 v15.4s, v28.8h, v3.h[1] // vacc3x4567 += vb4567 * va3[1]
SMLAL v16.4s, v28.4h, v4.h[1] // vacc4x0123 += vb0123 * va4[1]
SMLAL2 v17.4s, v28.8h, v4.h[1] // vacc4x4567 += vb4567 * va4[1]
SMLAL v18.4s, v28.4h, v5.h[1] // vacc5x0123 += vb0123 * va5[1]
SMLAL2 v19.4s, v28.8h, v5.h[1] // vacc5x4567 += vb4567 * va5[1]
SMLAL v20.4s, v28.4h, v6.h[1] // vacc6x0123 += vb0123 * va6[1]
SMLAL2 v21.4s, v28.8h, v6.h[1] // vacc6x4567 += vb4567 * va6[1]
SMLAL v22.4s, v28.4h, v7.h[1] // vacc7x0123 += vb0123 * va7[1]
SMLAL2 v23.4s, v28.8h, v7.h[1] // vacc7x4567 += vb4567 * va7[1]
B.LS 2f
// Channel 2
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[2] // vacc0x0123 += vb0123 * va0[2]
SMLAL2 v9.4s, v27.8h, v0.h[2] // vacc0x4567 += vb4567 * va0[2]
SMLAL v10.4s, v27.4h, v1.h[2] // vacc1x0123 += vb0123 * va1[2]
SMLAL2 v11.4s, v27.8h, v1.h[2] // vacc1x4567 += vb4567 * va1[2]
SMLAL v12.4s, v27.4h, v2.h[2] // vacc2x0123 += vb0123 * va2[2]
SMLAL2 v13.4s, v27.8h, v2.h[2] // vacc2x4567 += vb4567 * va2[2]
SMLAL v14.4s, v27.4h, v3.h[2] // vacc3x0123 += vb0123 * va3[2]
SMLAL2 v15.4s, v27.8h, v3.h[2] // vacc3x4567 += vb4567 * va3[2]
SMLAL v16.4s, v27.4h, v4.h[2] // vacc4x0123 += vb0123 * va4[2]
SMLAL2 v17.4s, v27.8h, v4.h[2] // vacc4x4567 += vb4567 * va4[2]
SMLAL v18.4s, v27.4h, v5.h[2] // vacc5x0123 += vb0123 * va5[2]
SMLAL2 v19.4s, v27.8h, v5.h[2] // vacc5x4567 += vb4567 * va5[2]
SMLAL v20.4s, v27.4h, v6.h[2] // vacc6x0123 += vb0123 * va6[2]
SMLAL2 v21.4s, v27.8h, v6.h[2] // vacc6x4567 += vb4567 * va6[2]
SMLAL v22.4s, v27.4h, v7.h[2] // vacc7x0123 += vb0123 * va7[2]
SMLAL2 v23.4s, v27.8h, v7.h[2] // vacc7x4567 += vb4567 * va7[2]
CMP x17, -32
B.LO 2f
// Channel 3
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[3] // vacc0x0123 += vb0123 * va0[3]
SMLAL2 v9.4s, v28.8h, v0.h[3] // vacc0x4567 += vb4567 * va0[3]
SMLAL v10.4s, v28.4h, v1.h[3] // vacc1x0123 += vb0123 * va1[3]
SMLAL2 v11.4s, v28.8h, v1.h[3] // vacc1x4567 += vb4567 * va1[3]
SMLAL v12.4s, v28.4h, v2.h[3] // vacc2x0123 += vb0123 * va2[3]
SMLAL2 v13.4s, v28.8h, v2.h[3] // vacc2x4567 += vb4567 * va2[3]
SMLAL v14.4s, v28.4h, v3.h[3] // vacc3x0123 += vb0123 * va3[3]
SMLAL2 v15.4s, v28.8h, v3.h[3] // vacc3x4567 += vb4567 * va3[3]
SMLAL v16.4s, v28.4h, v4.h[3] // vacc4x0123 += vb0123 * va4[3]
SMLAL2 v17.4s, v28.8h, v4.h[3] // vacc4x4567 += vb4567 * va4[3]
SMLAL v18.4s, v28.4h, v5.h[3] // vacc5x0123 += vb0123 * va5[3]
SMLAL2 v19.4s, v28.8h, v5.h[3] // vacc5x4567 += vb4567 * va5[3]
SMLAL v20.4s, v28.4h, v6.h[3] // vacc6x0123 += vb0123 * va6[3]
SMLAL2 v21.4s, v28.8h, v6.h[3] // vacc6x4567 += vb4567 * va6[3]
SMLAL v22.4s, v28.4h, v7.h[3] // vacc7x0123 += vb0123 * va7[3]
SMLAL2 v23.4s, v28.8h, v7.h[3] // vacc7x4567 += vb4567 * va7[3]
B.LS 2f
// Channel 4
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[4] // vacc0x0123 += vb0123 * va0[4]
SMLAL2 v9.4s, v27.8h, v0.h[4] // vacc0x4567 += vb4567 * va0[4]
SMLAL v10.4s, v27.4h, v1.h[4] // vacc1x0123 += vb0123 * va1[4]
SMLAL2 v11.4s, v27.8h, v1.h[4] // vacc1x4567 += vb4567 * va1[4]
SMLAL v12.4s, v27.4h, v2.h[4] // vacc2x0123 += vb0123 * va2[4]
SMLAL2 v13.4s, v27.8h, v2.h[4] // vacc2x4567 += vb4567 * va2[4]
SMLAL v14.4s, v27.4h, v3.h[4] // vacc3x0123 += vb0123 * va3[4]
SMLAL2 v15.4s, v27.8h, v3.h[4] // vacc3x4567 += vb4567 * va3[4]
SMLAL v16.4s, v27.4h, v4.h[4] // vacc4x0123 += vb0123 * va4[4]
SMLAL2 v17.4s, v27.8h, v4.h[4] // vacc4x4567 += vb4567 * va4[4]
SMLAL v18.4s, v27.4h, v5.h[4] // vacc5x0123 += vb0123 * va5[4]
SMLAL2 v19.4s, v27.8h, v5.h[4] // vacc5x4567 += vb4567 * va5[4]
SMLAL v20.4s, v27.4h, v6.h[4] // vacc6x0123 += vb0123 * va6[4]
SMLAL2 v21.4s, v27.8h, v6.h[4] // vacc6x4567 += vb4567 * va6[4]
SMLAL v22.4s, v27.4h, v7.h[4] // vacc7x0123 += vb0123 * va7[4]
SMLAL2 v23.4s, v27.8h, v7.h[4] // vacc7x4567 += vb4567 * va7[4]
CMP x17, -16
B.LO 2f
// Channel 5
LD1 {v28.8b}, [x5], 8
USUBL v28.8h, v28.8b, v25.8b
SMLAL v8.4s, v28.4h, v0.h[5] // vacc0x0123 += vb0123 * va0[5]
SMLAL2 v9.4s, v28.8h, v0.h[5] // vacc0x4567 += vb4567 * va0[5]
SMLAL v10.4s, v28.4h, v1.h[5] // vacc1x0123 += vb0123 * va1[5]
SMLAL2 v11.4s, v28.8h, v1.h[5] // vacc1x4567 += vb4567 * va1[5]
SMLAL v12.4s, v28.4h, v2.h[5] // vacc2x0123 += vb0123 * va2[5]
SMLAL2 v13.4s, v28.8h, v2.h[5] // vacc2x4567 += vb4567 * va2[5]
SMLAL v14.4s, v28.4h, v3.h[5] // vacc3x0123 += vb0123 * va3[5]
SMLAL2 v15.4s, v28.8h, v3.h[5] // vacc3x4567 += vb4567 * va3[5]
SMLAL v16.4s, v28.4h, v4.h[5] // vacc4x0123 += vb0123 * va4[5]
SMLAL2 v17.4s, v28.8h, v4.h[5] // vacc4x4567 += vb4567 * va4[5]
SMLAL v18.4s, v28.4h, v5.h[5] // vacc5x0123 += vb0123 * va5[5]
SMLAL2 v19.4s, v28.8h, v5.h[5] // vacc5x4567 += vb4567 * va5[5]
SMLAL v20.4s, v28.4h, v6.h[5] // vacc6x0123 += vb0123 * va6[5]
SMLAL2 v21.4s, v28.8h, v6.h[5] // vacc6x4567 += vb4567 * va6[5]
SMLAL v22.4s, v28.4h, v7.h[5] // vacc7x0123 += vb0123 * va7[5]
SMLAL2 v23.4s, v28.8h, v7.h[5] // vacc7x4567 += vb4567 * va7[5]
B.LS 2f
// Channel 6
LD1 {v27.8b}, [x5], 8
USUBL v27.8h, v27.8b, v25.8b
SMLAL v8.4s, v27.4h, v0.h[6] // vacc0x0123 += vb0123 * va0[6]
SMLAL2 v9.4s, v27.8h, v0.h[6] // vacc0x4567 += vb4567 * va0[6]
SMLAL v10.4s, v27.4h, v1.h[6] // vacc1x0123 += vb0123 * va1[6]
SMLAL2 v11.4s, v27.8h, v1.h[6] // vacc1x4567 += vb4567 * va1[6]
SMLAL v12.4s, v27.4h, v2.h[6] // vacc2x0123 += vb0123 * va2[6]
SMLAL2 v13.4s, v27.8h, v2.h[6] // vacc2x4567 += vb4567 * va2[6]
SMLAL v14.4s, v27.4h, v3.h[6] // vacc3x0123 += vb0123 * va3[6]
SMLAL2 v15.4s, v27.8h, v3.h[6] // vacc3x4567 += vb4567 * va3[6]
SMLAL v16.4s, v27.4h, v4.h[6] // vacc4x0123 += vb0123 * va4[6]
SMLAL2 v17.4s, v27.8h, v4.h[6] // vacc4x4567 += vb4567 * va4[6]
SMLAL v18.4s, v27.4h, v5.h[6] // vacc5x0123 += vb0123 * va5[6]
SMLAL2 v19.4s, v27.8h, v5.h[6] // vacc5x4567 += vb4567 * va5[6]
SMLAL v20.4s, v27.4h, v6.h[6] // vacc6x0123 += vb0123 * va6[6]
SMLAL2 v21.4s, v27.8h, v6.h[6] // vacc6x4567 += vb4567 * va6[6]
SMLAL v22.4s, v27.4h, v7.h[6] // vacc7x0123 += vb0123 * va7[6]
SMLAL2 v23.4s, v27.8h, v7.h[6] // vacc7x4567 += vb4567 * va7[6]
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 4
#endif
2:
SUB x3, x3, 1
CBNZ x3, 3b
// Load zero_point:
// - v29 = vzero_point
LD1R {v29.8h}, [x8], 2
SCVTF v8.4s, v8.4s
SCVTF v9.4s, v9.4s
SCVTF v10.4s, v10.4s
SCVTF v11.4s, v11.4s
SCVTF v12.4s, v12.4s
SCVTF v13.4s, v13.4s
SCVTF v14.4s, v14.4s
SCVTF v15.4s, v15.4s
SCVTF v16.4s, v16.4s
SCVTF v17.4s, v17.4s
SCVTF v18.4s, v18.4s
SCVTF v19.4s, v19.4s
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMUL v8.4s, v8.4s, v26.4s
FMUL v9.4s, v9.4s, v30.4s
FMUL v10.4s, v10.4s, v26.4s
FMUL v11.4s, v11.4s, v30.4s
FMUL v12.4s, v12.4s, v26.4s
FMUL v13.4s, v13.4s, v30.4s
FMUL v14.4s, v14.4s, v26.4s
FMUL v15.4s, v15.4s, v30.4s
FMUL v16.4s, v16.4s, v26.4s
FMUL v17.4s, v17.4s, v30.4s
FMUL v18.4s, v18.4s, v26.4s
FMUL v19.4s, v19.4s, v30.4s
FMUL v20.4s, v20.4s, v26.4s
FMUL v21.4s, v21.4s, v30.4s
FMUL v22.4s, v22.4s, v26.4s
FMUL v23.4s, v23.4s, v30.4s
// Load max:
// - v30 = vmax
LD1R {v30.16b}, [x8], 1
// Load min:
// - v31 = vmin
LD1R {v31.16b}, [x8]
FCVTNS v8.4s, v8.4s
FCVTNS v9.4s, v9.4s
FCVTNS v10.4s, v10.4s
FCVTNS v11.4s, v11.4s
FCVTNS v12.4s, v12.4s
FCVTNS v13.4s, v13.4s
FCVTNS v14.4s, v14.4s
FCVTNS v15.4s, v15.4s
FCVTNS v16.4s, v16.4s
FCVTNS v17.4s, v17.4s
FCVTNS v18.4s, v18.4s
FCVTNS v19.4s, v19.4s
FCVTNS v20.4s, v20.4s
FCVTNS v21.4s, v21.4s
FCVTNS v22.4s, v22.4s
FCVTNS v23.4s, v23.4s
SQXTN v8.4h, v8.4s
SQXTN v10.4h, v10.4s
SQXTN v12.4h, v12.4s
SQXTN v14.4h, v14.4s
SQXTN v16.4h, v16.4s
SQXTN v18.4h, v18.4s
SQXTN v20.4h, v20.4s
SQXTN v22.4h, v22.4s
SQXTN2 v8.8h, v9.4s
SQXTN2 v10.8h, v11.4s
SQXTN2 v12.8h, v13.4s
SQXTN2 v14.8h, v15.4s
SQXTN2 v16.8h, v17.4s
SQXTN2 v18.8h, v19.4s
SQXTN2 v20.8h, v21.4s
SQXTN2 v22.8h, v23.4s
SQADD v8.8h, v8.8h, v29.8h
SQADD v10.8h, v10.8h, v29.8h
SQADD v12.8h, v12.8h, v29.8h
SQADD v14.8h, v14.8h, v29.8h
SQADD v16.8h, v16.8h, v29.8h
SQADD v18.8h, v18.8h, v29.8h
SQADD v20.8h, v20.8h, v29.8h
SQADD v22.8h, v22.8h, v29.8h
SQXTUN v8.8b, v8.8h
SQXTUN v12.8b, v12.8h
SQXTUN v16.8b, v16.8h
SQXTUN v20.8b, v20.8h
SQXTUN2 v8.16b, v10.8h
SQXTUN2 v12.16b, v14.8h
SQXTUN2 v16.16b, v18.8h
SQXTUN2 v20.16b, v22.8h
UMIN v8.16b, v8.16b, v30.16b
UMIN v12.16b, v12.16b, v30.16b
UMIN v16.16b, v16.16b, v30.16b
UMIN v20.16b, v20.16b, v30.16b
UMAX v8.16b, v8.16b, v31.16b
UMAX v12.16b, v12.16b, v31.16b
UMAX v16.16b, v16.16b, v31.16b
UMAX v20.16b, v20.16b, v31.16b
// Compute c0-c7
ADD x9, x6, x7
CMP x0, 2
CSEL x9, x6, x9, LO
ADD x10, x9, x7
CSEL x10, x9, x10, LS
ADD x11, x10, x7
CMP x0, 4
CSEL x11, x10, x11, LO
ADD x12, x11, x7
CSEL x12, x11, x12, LS
ADD x13, x12, x7
CMP x0, 6
CSEL x13, x12, x13, LO
ADD x14, x13, x7
CSEL x14, x13, x14, LS
ADD x15, x14, x7
CMP x0, 8
CSEL x15, x14, x15, NE
CMP x1, 8
B.NE 4f
// Store results
ST1 {v8.d}[0], [x6]
ST1 {v8.d}[1], [x9]
ST1 {v12.d}[0], [x10]
ST1 {v12.d}[1], [x11]
ST1 {v16.d}[0], [x12]
ST1 {v16.d}[1], [x13]
ST1 {v20.d}[0], [x14]
ST1 {v20.d}[1], [x15]
LDP d9, d8, [sp, -64]
LDP d11, d10, [sp, -48]
LDP d13, d12, [sp, -32]
LDP d15, d14, [sp, -16]
RET
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
.p2align 3
#endif
4:
CMP x1, 4
B.LO 5f
ST1 {v8.s}[0], [x6], 4
ST1 {v8.s}[2], [x9], 4
ST1 {v12.s}[0], [x10], 4
ST1 {v12.s}[2], [x11], 4
ST1 {v16.s}[0], [x12], 4
ST1 {v16.s}[2], [x13], 4
ST1 {v20.s}[0], [x14], 4
ST1 {v20.s}[2], [x15], 4
SUB x1, x1, 4
EXT v8.16b, v8.16b, v8.16b, 4
EXT v12.16b, v12.16b, v12.16b, 4
EXT v16.16b, v16.16b, v16.16b, 4
EXT v20.16b, v20.16b, v20.16b, 4
5:
CMP x1, 2
B.LO 6f
ST1 {v8.h}[0], [x6], 2
ST1 {v8.h}[4], [x9], 2
ST1 {v12.h}[0], [x10], 2
ST1 {v12.h}[4], [x11], 2
ST1 {v16.h}[0], [x12], 2
ST1 {v16.h}[4], [x13], 2
ST1 {v20.h}[0], [x14], 2
ST1 {v20.h}[4], [x15], 2
SUB x1, x1, 2
EXT v8.16b, v8.16b, v8.16b, 2
EXT v12.16b, v12.16b, v12.16b, 2
EXT v16.16b, v16.16b, v16.16b, 2
EXT v20.16b, v20.16b, v20.16b, 2
6:
CMP x1, 1
B.LO 7f
ST1 {v8.b}[0], [x6]
ST1 {v8.b}[8], [x9]
ST1 {v12.b}[0], [x10]
ST1 {v12.b}[8], [x11]
ST1 {v16.b}[0], [x12]
ST1 {v16.b}[8], [x13]
ST1 {v20.b}[0], [x14]
ST1 {v20.b}[8], [x15]
7:
LDP d9, d8, [sp, -64]
LDP d11, d10, [sp, -48]
LDP d13, d12, [sp, -32]
LDP d15, d14, [sp, -16]
RET
END_FUNCTION pytorch_q8conv_ukernel_8x8__aarch64_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 12,985 | aten/src/ATen/native/quantized/cpu/qnnpack/src/hgemm/8x8-aarch32-neonfp16arith.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
.syntax unified
# void pytorch_hgemm_ukernel_8x8__aarch32_neonfp16arith(
# size_t mr,
# size_t nr,
# size_t k,
# const __fp16*restrict a,
# size_t a_stride,
# const __fp16*restrict w,
# __fp16*restrict c,
# size_t c_stride,
# const struct pytorch_qnnp_fp16_clamping_params clamping_params[restrict static 1])
BEGIN_FUNCTION pytorch_hgemm_ukernel_8x8__aarch32_neonfp16arith
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
# Load w
# - ip = w
LDR ip, [sp, 4]
PUSH {r4, r5, r6, r7, r8, r9, r10, r11}
VPUSH {d8-d15}
# Initialize vacc0x01234567
# - q8 = d16:d17 := vacc0x01234567 = bias01234567
VLD1.16 {d16-d17}, [ip:64]!
# Load a_stride
# - r10 = a_stride
LDR r10, [sp, 96]
# Initialize vacc1x01234567
# - q9 := vacc1x01234567 = vacc0x01234567
VMOV.I16 q9, q8
# Initialize vacc2x01234567
# - q10 := vacc2x01234567 = vacc0x01234567
VMOV.I16 q10, q8
# Initialize vacc3x01234567
# - q11 := vacc3x01234567 = vacc0x01234567
VMOV.I16 q11, q8
# Initialize vacc4x01234567
# - q12 := vacc4x01234567 = vacc0x01234567
VMOV.I16 q12, q8
# Initialize vacc5x01234567
# - q13 := vacc5x01234567 = vacc0x01234567
VMOV.I16 q13, q8
# Initialize vacc6x01234567
# - q14 := vacc6x01234567 = vacc0x01234567
VMOV.I16 q14, q8
# Initialize vacc7x01234567
# - q15 := vacc7x01234567 = vacc0x01234567
VMOV.I16 q15, q8
CMP r0, 2
ADD r4, r3, r10
MOVLO r4, r3
ADD r5, r4, r10
MOVLS r5, r4
CMP r0, 4
ADD r6, r5, r10
MOVLO r6, r5
ADD r7, r6, r10
MOVLS r7, r6
CMP r0, 6
ADD r8, r7, r10
MOVLO r8, r7
ADD r9, r8, r10
MOVLS r9, r8
CMP r0, 8
ADD r10, r9, r10
MOVNE r10, r9
SUBS r2, r2, 4
BLO 1f
.p2align 5
0:
# Load a0
# - d0 = a0
VLD1.16 {d0}, [r3]!
# Load a1
# - d1 = a1
VLD1.16 {d1}, [r4]!
# Load a2
# - d2 = a2
VLD1.16 {d2}, [r5]!
# Load a3
# - d3 = a3
VLD1.16 {d3}, [r6]!
# Load a4
# - d4 = a4
VLD1.16 {d4}, [r7]!
# Load a5
# - d5 = a5
VLD1.16 {d5}, [r8]!
# Load a6
# - d6 = a6
VLD1.16 {d6}, [r9]!
# Load a7
# - d7 = a7
VLD1.16 {d7}, [r10]!
### Channel 0 ###
# Load b0-b15 (channel 0)
# - q4 = d8:d9 = b0-b15
VLD1.8 {d8-d9}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[0];
.word 0xF3D80140 @ VMLA.F16 q8, q4, d0[0]
# vacc1x01234567 += vb01234567 * va1[0];
.word 0xF3D82141 @ VMLA.F16 q9, q4, d1[0]
# vacc2x01234567 += vb01234567 * va2[0];
.word 0xF3D84142 @ VMLA.F16 q10, q4, d2[0]
# vacc3x01234567 += vb01234567 * va3[0];
.word 0xF3D86143 @ VMLA.F16 q11, q4, d3[0]
# vacc4x01234567 += vb01234567 * va4[0];
.word 0xF3D88144 @ VMLA.F16 q12, q4, d4[0]
# vacc5x01234567 += vb01234567 * va5[0];
.word 0xF3D8A145 @ VMLA.F16 q13, q4, d5[0]
# vacc6x01234567 += vb01234567 * va6[0];
.word 0xF3D8C146 @ VMLA.F16 q14, q4, d6[0]
# vacc7x01234567 += vb01234567 * va7[0];
.word 0xF3D8E147 @ VMLA.F16 q15, q4, d7[0]
### Channel 1 ###
# Load b0-b15 (channel 1)
# - q5 = d10:d11 = b0-b15
VLD1.8 {d10-d11}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[1];
.word 0xF3DA0148 @ VMLA.F16 q8, q5, d0[1]
# vacc1x01234567 += vb01234567 * va1[1];
.word 0xF3DA2149 @ VMLA.F16 q9, q5, d1[1]
# vacc2x01234567 += vb01234567 * va2[1];
.word 0xF3DA414A @ VMLA.F16 q10, q5, d2[1]
# vacc3x01234567 += vb01234567 * va3[1];
.word 0xF3DA614B @ VMLA.F16 q11, q5, d3[1]
# vacc4x01234567 += vb01234567 * va4[1];
.word 0xF3DA814C @ VMLA.F16 q12, q5, d4[1]
# vacc5x01234567 += vb01234567 * va5[1];
.word 0xF3DAA14D @ VMLA.F16 q13, q5, d5[1]
# vacc6x01234567 += vb01234567 * va6[1];
.word 0xF3DAC14E @ VMLA.F16 q14, q5, d6[1]
# vacc7x01234567 += vb01234567 * va7[1];
.word 0xF3DAE14F @ VMLA.F16 q15, q5, d7[1]
### Channel 2 ###
# Load b0-b15 (channel 2)
# - q6 = d12:d13 = b0-b15
VLD1.8 {d12-d13}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[2];
.word 0xF3DC0160 @ VMLA.F16 q8, q6, d0[2]
# vacc1x01234567 += vb01234567 * va1[2];
.word 0xF3DC2161 @ VMLA.F16 q9, q6, d1[2]
# vacc2x01234567 += vb01234567 * va2[2];
.word 0xF3DC4162 @ VMLA.F16 q10, q6, d2[2]
# vacc3x01234567 += vb01234567 * va3[2];
.word 0xF3DC6163 @ VMLA.F16 q11, q6, d3[2]
# vacc4x01234567 += vb01234567 * va4[2];
.word 0xF3DC8164 @ VMLA.F16 q12, q6, d4[2]
# vacc5x01234567 += vb01234567 * va5[2];
.word 0xF3DCA165 @ VMLA.F16 q13, q6, d5[2]
# vacc6x01234567 += vb01234567 * va6[2];
.word 0xF3DCC166 @ VMLA.F16 q14, q6, d6[2]
# vacc7x01234567 += vb01234567 * va7[2];
.word 0xF3DCE167 @ VMLA.F16 q15, q6, d7[2]
### Channel 3 ###
# Load b0-b15 (channel 3)
# - q7 = d14:d15 = b0-b15
VLD1.8 {d14-d15}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[3];
.word 0xF3DE0168 @ VMLA.F16 q8, q7, d0[3]
# vacc1x01234567 += vb01234567 * va1[3];
.word 0xF3DE2169 @ VMLA.F16 q9, q7, d1[3]
# vacc2x01234567 += vb01234567 * va2[3];
.word 0xF3DE416A @ VMLA.F16 q10, q7, d2[3]
# vacc3x01234567 += vb01234567 * va3[3];
.word 0xF3DE616B @ VMLA.F16 q11, q7, d3[3]
# vacc4x01234567 += vb01234567 * va4[3];
.word 0xF3DE816C @ VMLA.F16 q12, q7, d4[3]
# vacc5x01234567 += vb01234567 * va5[3];
.word 0xF3DEA16D @ VMLA.F16 q13, q7, d5[3]
# vacc6x01234567 += vb01234567 * va6[3];
.word 0xF3DEC16E @ VMLA.F16 q14, q7, d6[3]
# vacc7x01234567 += vb01234567 * va7[3];
.word 0xF3DEE16F @ VMLA.F16 q15, q7, d7[3]
SUBS r2, r2, 4
BHS 0b
1:
CMP r2, -4
BEQ 2f
ADD r3, r3, r2, LSL #1
ADD r4, r4, r2, LSL #1
ADD r5, r5, r2, LSL #1
ADD r6, r6, r2, LSL #1
ADD r7, r7, r2, LSL #1
ADD r8, r8, r2, LSL #1
ADD r9, r9, r2, LSL #1
ADD r10, r10, r2, LSL #1
LSL r2, r2, 4
VDUP.32 d14, r2
# Load a0
# - d0 = a0
VLD1.16 {d0}, [r3]!
VSHL.U64 d0, d0, d14
# Load a1
# - d1 = a1
VLD1.16 {d1}, [r4]!
VSHL.U64 d1, d1, d14
# Load a2
# - d2 = a2
VLD1.16 {d2}, [r5]!
VSHL.U64 d2, d2, d14
# Load a3
# - d3 = a3
VLD1.16 {d3}, [r6]!
VSHL.U64 d3, d3, d14
# Load a4
# - d4 = a4
VLD1.16 {d4}, [r7]!
VSHL.U64 d4, d4, d14
# Load a5
# - d5 = a5
VLD1.16 {d5}, [r8]!
VSHL.U64 d5, d5, d14
# Load a6
# - d6 = a6
VLD1.16 {d6}, [r9]!
VSHL.U64 d6, d6, d14
# Load a7
# - d7 = a7
VLD1.16 {d7}, [r10]!
VSHL.U64 d7, d7, d14
### Channel 0 ###
# Load b0-b15 (channel 0)
# - q4 = d8:d9 = b0-b15
VLD1.8 {d8-d9}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[0];
.word 0xF3D80140 @ VMLA.F16 q8, q4, d0[0]
# vacc1x01234567 += vb01234567 * va1[0];
.word 0xF3D82141 @ VMLA.F16 q9, q4, d1[0]
# vacc2x01234567 += vb01234567 * va2[0];
.word 0xF3D84142 @ VMLA.F16 q10, q4, d2[0]
# vacc3x01234567 += vb01234567 * va3[0];
.word 0xF3D86143 @ VMLA.F16 q11, q4, d3[0]
# vacc4x01234567 += vb01234567 * va4[0];
.word 0xF3D88144 @ VMLA.F16 q12, q4, d4[0]
# vacc5x01234567 += vb01234567 * va5[0];
.word 0xF3D8A145 @ VMLA.F16 q13, q4, d5[0]
# vacc6x01234567 += vb01234567 * va6[0];
.word 0xF3D8C146 @ VMLA.F16 q14, q4, d6[0]
# vacc7x01234567 += vb01234567 * va7[0];
.word 0xF3D8E147 @ VMLA.F16 q15, q4, d7[0]
CMP r2, -32
BLO 2f
### Channel 1 ###
# Load b0-b15 (channel 1)
# - q5 = d10:d11 = b0-b15
VLD1.8 {d10-d11}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[1];
.word 0xF3DA0148 @ VMLA.F16 q8, q5, d0[1]
# vacc1x01234567 += vb01234567 * va1[1];
.word 0xF3DA2149 @ VMLA.F16 q9, q5, d1[1]
# vacc2x01234567 += vb01234567 * va2[1];
.word 0xF3DA414A @ VMLA.F16 q10, q5, d2[1]
# vacc3x01234567 += vb01234567 * va3[1];
.word 0xF3DA614B @ VMLA.F16 q11, q5, d3[1]
# vacc4x01234567 += vb01234567 * va4[1];
.word 0xF3DA814C @ VMLA.F16 q12, q5, d4[1]
# vacc5x01234567 += vb01234567 * va5[1];
.word 0xF3DAA14D @ VMLA.F16 q13, q5, d5[1]
# vacc6x01234567 += vb01234567 * va6[1];
.word 0xF3DAC14E @ VMLA.F16 q14, q5, d6[1]
# vacc7x01234567 += vb01234567 * va7[1];
.word 0xF3DAE14F @ VMLA.F16 q15, q5, d7[1]
BLS 2f
### Channel 2 ###
# Load b0-b15 (channel 2)
# - q6 = d12:d13 = b0-b15
VLD1.8 {d12-d13}, [ip:64]!
# vacc0x01234567 += vb01234567 * va0[2];
.word 0xF3DC0160 @ VMLA.F16 q8, q6, d0[2]
# vacc1x01234567 += vb01234567 * va1[2];
.word 0xF3DC2161 @ VMLA.F16 q9, q6, d1[2]
# vacc2x01234567 += vb01234567 * va2[2];
.word 0xF3DC4162 @ VMLA.F16 q10, q6, d2[2]
# vacc3x01234567 += vb01234567 * va3[2];
.word 0xF3DC6163 @ VMLA.F16 q11, q6, d3[2]
# vacc4x01234567 += vb01234567 * va4[2];
.word 0xF3DC8164 @ VMLA.F16 q12, q6, d4[2]
# vacc5x01234567 += vb01234567 * va5[2];
.word 0xF3DCA165 @ VMLA.F16 q13, q6, d5[2]
# vacc6x01234567 += vb01234567 * va6[2];
.word 0xF3DCC166 @ VMLA.F16 q14, q6, d6[2]
# vacc7x01234567 += vb01234567 * va7[2];
.word 0xF3DCE167 @ VMLA.F16 q15, q6, d7[2]
.p2align 4
2:
# Load params:
# - ip = params
LDR ip, [sp, 112]
# Load scale:
# - q0 = d0:d1 = vscale
VLD1.16 {d0[], d1[]}, [ip]!
.word 0xF3500DD0 @ VMUL.F16 q8, q8, q0
.word 0xF3522DD0 @ VMUL.F16 q9, q9, q0
.word 0xF3544DD0 @ VMUL.F16 q10, q10, q0
.word 0xF3566DD0 @ VMUL.F16 q11, q11, q0
.word 0xF3588DD0 @ VMUL.F16 q12, q12, q0
.word 0xF35AADD0 @ VMUL.F16 q13, q13, q0
.word 0xF35CCDD0 @ VMUL.F16 q14, q14, q0
.word 0xF35EEDD0 @ VMUL.F16 q15, q15, q0
# Load max:
# - q1 = d2:d3 = vmax
VLD1.16 {d2[], d3[]}, [ip]!
.word 0xF2700FC2 @ VMIN.F16 q8, q8, q1
.word 0xF2722FC2 @ VMIN.F16 q9, q9, q1
.word 0xF2744FC2 @ VMIN.F16 q10, q10, q1
.word 0xF2766FC2 @ VMIN.F16 q11, q11, q1
.word 0xF2788FC2 @ VMIN.F16 q12, q12, q1
.word 0xF27AAFC2 @ VMIN.F16 q13, q13, q1
.word 0xF27CCFC2 @ VMIN.F16 q14, q14, q1
.word 0xF27EEFC2 @ VMIN.F16 q15, q15, q1
# Load min:
# - q2 = d4:d5 = vmin
VLD1.16 {d4[], d5[]}, [ip]
.word 0xF2500FC4 @ VMAX.F16 q8, q8, q2
.word 0xF2522FC4 @ VMAX.F16 q9, q9, q2
.word 0xF2544FC4 @ VMAX.F16 q10, q10, q2
.word 0xF2566FC4 @ VMAX.F16 q11, q11, q2
.word 0xF2588FC4 @ VMAX.F16 q12, q12, q2
.word 0xF25AAFC4 @ VMAX.F16 q13, q13, q2
.word 0xF25CCFC4 @ VMAX.F16 q14, q14, q2
.word 0xF25EEFC4 @ VMAX.F16 q15, q15, q2
# Load c, c_stride:
# - r2 = c
# - r3 = c_stride
LDRD r2, r3, [sp, 104]
CMP r0, 2
ADD r4, r2, r3
MOVLO r4, r2
ADD r5, r4, r3
MOVLS r5, r4
CMP r0, 4
ADD r6, r5, r3
MOVLO r6, r5
ADD r7, r6, r3
MOVLS r7, r6
CMP r0, 6
ADD r8, r7, r3
MOVLO r8, r7
ADD r9, r8, r3
MOVLS r9, r8
CMP r0, 8
ADD r3, r9, r3
MOVNE r3, r9
CMP r1, 8
BNE 4f
VST1.16 {d16-d17}, [r2]
VST1.16 {d18-d19}, [r4]
VST1.16 {d20-d21}, [r5]
VST1.16 {d22-d23}, [r6]
VST1.16 {d24-d25}, [r7]
VST1.16 {d26-d27}, [r8]
VST1.16 {d28-d29}, [r9]
VST1.16 {d30-d31}, [r3]
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
.p2align 3
4:
CMP r1, 4
BLO 5f
VST1.16 {d16}, [r2]!
VST1.16 {d18}, [r4]!
VST1.16 {d20}, [r5]!
VST1.16 {d22}, [r6]!
VST1.16 {d24}, [r7]!
VST1.16 {d26}, [r8]!
VST1.16 {d28}, [r9]!
VST1.16 {d30}, [r3]!
SUB r1, 4
VMOV.I16 d16, d17
VMOV.I16 d18, d19
VMOV.I16 d20, d21
VMOV.I16 d22, d23
VMOV.I16 d24, d25
VMOV.I16 d26, d27
VMOV.I16 d28, d29
VMOV.I16 d30, d31
5:
CMP r1, 2
BLO 6f
VST1.32 {d16[0]}, [r2]!
VST1.32 {d18[0]}, [r4]!
VST1.32 {d20[0]}, [r5]!
VST1.32 {d22[0]}, [r6]!
VST1.32 {d24[0]}, [r7]!
VST1.32 {d26[0]}, [r8]!
VST1.32 {d28[0]}, [r9]!
VST1.32 {d30[0]}, [r3]!
SUB r1, 2
VEXT.8 d16, d16, d16, 4
VEXT.8 d18, d18, d18, 4
VEXT.8 d20, d20, d20, 4
VEXT.8 d22, d22, d22, 4
VEXT.8 d24, d24, d24, 4
VEXT.8 d26, d26, d26, 4
VEXT.8 d28, d28, d28, 4
VEXT.8 d30, d30, d30, 4
6:
TEQ r1, 0
BEQ 7f
VST1.16 {d16[0]}, [r2]
VST1.16 {d18[0]}, [r4]
VST1.16 {d20[0]}, [r5]
VST1.16 {d22[0]}, [r6]
VST1.16 {d24[0]}, [r7]
VST1.16 {d26[0]}, [r8]
VST1.16 {d28[0]}, [r9]
VST1.16 {d30[0]}, [r3]
7:
VPOP {d8-d15}
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
END_FUNCTION pytorch_hgemm_ukernel_8x8__aarch32_neonfp16arith
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 26,974 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/4x8c8x1-dq-packedA-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
#ifndef __APPLE__
#define NDEF_APPLE_SYMBOLS .arch armv7-a; .fpu neon
#else
#define NDEF_APPLE_SYMBOLS
#endif
# r0 mr
# r1 nr
# r2 packed_a
# r3 packed_w
# d14 a_zero_point
# d15 b_zero_point
## Stack
# 4 a_stride
# 4 packed_w
# 4 w_row_ptr
# 4 w_block_ids_ptr
# 4 b
# 4 c
# 4 c_stride
# 4 output channel index
# 4 quantization_params
# --
.syntax unified
# Args passed via stack.
# TOS
# |----------------|
# |packed_w | 0
# |w_row_ptr | 4
# |w_block_ids_ptr | 8
# |b | 12
# |c | 16
# |c_stride | 20
# |out ch indx | 24
# |params | 28
# |----------------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r9 and d8-d15 on stack
# |----------------|
# |d8 - d15 | 0
# |r4 - r11,lr | 64
# |w_row_ptr | 100
# |w_block_ids_ptr | 104
# |b | 108
# |c | 112
# |c_stride | 116
# |out ch indx | 120
# |params | 124
# |----------------|
#
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_4x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_row_ptr,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
#define MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_4X8_PACKEDA__AARCH32_NEON(W_INDEX_DTYPE_NUM_BITS, W_INDEX_DTYPE_NUM_BYTES_ARG, W_INDEX_DTYPE_LOG_NUM_BYTES_ARG, LOAD_INDEX_INSTRUCTION) ;\
BEGIN_FUNCTION pytorch_q8gemm_dq_sparse_8x1_ukernel_4x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch32_neon ;\
.arm ;\
NDEF_APPLE_SYMBOLS ;\
;\
PUSH {r4, r5, r6, r7, r8, r9, r10, r11, lr} ;\
VPUSH {d8-d15} ;\
;\
/* Store nr in r11 as well for late user. */ ;\
MOV r11, r1 ;\
/* Load output channel index */ ;\
LDR r5, [sp, 120] ;\
/* Load quantization params */ ;\
/* - r7 = quantization_params */ ;\
LDR r7, [sp, 124] ;\
/* Load input_zero_point */ ;\
VLD1.8 {d14[]}, [r7] ;\
ADD r7, r7, 4 ;\
/* Load pointer to per channel zero points array */ ;\
LDR r4, [r7] ;\
/* Add output_channel_index to the b_zero_point pointer */ ;\
ADD r4, r4, r5 ;\
;\
/* Load w_row_ptr + n */ ;\
LDR r5, [sp, 100] ;\
/* r7 = blocks_id_ptr */ ;\
LDR r7, [sp, 104] ;\
;\
VEOR q8, q8, q8 ;\
VEOR q9, q9, q9 ;\
VEOR q10, q10, q10 ;\
VEOR q11, q11, q11 ;\
VEOR q12, q12, q12 ;\
VEOR q13, q13, q13 ;\
VEOR q14, q14, q14 ;\
VEOR q15, q15, q15 ;\
VLD1.8 {d15}, [r4] ;\
/* ip = w_row_ptr[n], lr = w_row_ptr[n+1] */ ;\
/* r5 = r5 + W_INDEX_DTYPE_NUM_BYTES_ARG to point to next n */ ;\
LOAD_INDEX_INSTRUCTION ip, [r5], W_INDEX_DTYPE_NUM_BYTES_ARG ;\
LOAD_INDEX_INSTRUCTION lr, [r5] ;\
/* r6 = temp_packed_w = packed_w + w_row_ptr[n] * 8 */ ;\
/* * 8 because each block contains 8 values */ ;\
/* This points to the first block of nonzero value */ ;\
/* for the nth row. */ ;\
ADD r6, r3, ip, LSL #3 ;\
/* r9 = temp_w_block_ids_ptr = w_block_ids_ptr (r7) + w_row_ptr[n] */ ;\
/* LSL for when elements are >1 byte */ ;\
/* (4 bytes: LSL #2, 2 bytes: LSL #1, 1 byte: LSL #0) */ ;\
/* This points to the col block id of the first block */ ;\
/* It should contain lr - ip number of block ids */ ;\
/* Note that in this kernel sparsity pattern is 8x1. */ ;\
/* Thus each block contains only 1 k as opposed to */ ;\
/* 1x4 where each block contains 4 k. */ ;\
ADD r9, r7, ip, LSL W_INDEX_DTYPE_LOG_NUM_BYTES_ARG ;\
/* r8 = num_blocks that needs to be processed */ ;\
SUB r8, lr, ip ;\
SUBS r8, r8, 2 ;\
BLO _1_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
.p2align 5 ;\
k_loop_w##W_INDEX_DTYPE_NUM_BITS##: ;\
/* Load 2 non zero blocks of weights. Each block = 8x1. */ ;\
VLD1.8 {d0}, [r6]! ;\
VLD1.8 {d2}, [r6]! ;\
;\
/* ip = block_id_ptr[0] */ ;\
/* lr = block_id_ptr[1] */ ;\
LOAD_INDEX_INSTRUCTION ip, [r9], W_INDEX_DTYPE_NUM_BYTES_ARG ;\
LOAD_INDEX_INSTRUCTION lr, [r9], W_INDEX_DTYPE_NUM_BYTES_ARG ;\
;\
/* Add offset to r2 */ ;\
/* Shift by 4 because each packed block is a block of 4x1 */ ;\
/* which 4 bytes */ ;\
ADD r10, r2, ip, LSL #2 ;\
/* q9 = vxb */ ;\
VSUBL.U8 q0, d0, d15 ;\
VSUBL.U8 q1, d2, d15 ;\
;\
/* d4 = 4x1 transposed */ ;\
VLD1.32 {d4[]}, [r10] ;\
;\
ADD r10, r2, lr, LSL #2 ;\
;\
VSUBL.U8 q2, d4, d14 /* vxa0_t */ ;\
;\
/* d5 = next 4x1 transposed */ ;\
VLD1.32 {d6[]}, [r10] ;\
;\
VSUBL.U8 q3, d6, d14 /* vxa1_t */ ;\
;\
/* q0 = d0, d1 = 8x1 block of weight for k */ ;\
/* q1 = d2, d3 = 8x1 block of weight for k + 1 */ ;\
/* q2's d4 = 4x1 block of activation for k */ ;\
/* q3's d6 = 4x1 block of activation for k + 1 */ ;\
;\
/* Generate 4x8 block as two 4x4 blocks */ ;\
;\
VMLAL.S16 q8, d0, d4[0] ;\
VMLAL.S16 q9, d1, d4[0] ;\
VMLAL.S16 q10, d0, d4[1] ;\
VMLAL.S16 q11, d1, d4[1] ;\
VMLAL.S16 q12, d0, d4[2] ;\
VMLAL.S16 q13, d1, d4[2] ;\
VMLAL.S16 q14, d0, d4[3] ;\
VMLAL.S16 q15, d1, d4[3] ;\
;\
VMLAL.S16 q8, d2, d6[0] ;\
VMLAL.S16 q9, d3, d6[0] ;\
VMLAL.S16 q10, d2, d6[1] ;\
VMLAL.S16 q11, d3, d6[1] ;\
VMLAL.S16 q12, d2, d6[2] ;\
VMLAL.S16 q13, d3, d6[2] ;\
VMLAL.S16 q14, d2, d6[3] ;\
VMLAL.S16 q15, d3, d6[3] ;\
;\
SUBS r8, r8, 2 ;\
;\
BHS k_loop_w##W_INDEX_DTYPE_NUM_BITS ;\
_1_w##W_INDEX_DTYPE_NUM_BITS##: ;\
CMP r8, -2 ;\
BEQ _3_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
/* Load last nonzero block */ ;\
/* For this we will load 4 8 bit values as one 32 bit value */ ;\
VLD1.8 {d0}, [r6] ;\
/* q9 = vxb */ ;\
VSUBL.U8 q0, d0, d15 ;\
;\
/* ip = block_id_ptr[0] */ ;\
LOAD_INDEX_INSTRUCTION ip, [r9] ;\
;\
/* Add offset to r2 */ ;\
/* Shift by 4 because each packed block is a block of 4x1 */ ;\
/* which 4 bytes */ ;\
ADD r10, r2, ip, LSL #2 ;\
;\
VLD1.32 {d4[]}, [r10]! ;\
;\
VSUBL.U8 q2, d4, d14 /* vxa0_t */ ;\
;\
VMLAL.S16 q8, d0, d4[0] ;\
VMLAL.S16 q9, d1, d4[0] ;\
VMLAL.S16 q10, d0, d4[1] ;\
VMLAL.S16 q11, d1, d4[1] ;\
VMLAL.S16 q12, d0, d4[2] ;\
VMLAL.S16 q13, d1, d4[2] ;\
VMLAL.S16 q14, d0, d4[3] ;\
VMLAL.S16 q15, d1, d4[3] ;\
;\
;\
.p2align 4 ;\
_3_w##W_INDEX_DTYPE_NUM_BITS##: ;\
/* Load output channel index */ ;\
LDR r5, [sp, 120] ;\
/* Load quantization params */ ;\
/* - r7 = quantization_params */ ;\
LDR r7, [sp, 124] ;\
ADD r7, r7, 8 ;\
/* Load pointer to per channel requant scale */ ;\
LDR r7, [r7] ;\
/* Now r7 has the base_addr + offset for multipliers */ ;\
ADD r7, r7, r5, LSL #2 ;\
;\
LDR r6, [sp, 108] ;\
/* Load q6: vmultiplier_c0123 */ ;\
VLD1.32 {d12, d13}, [r7]! ;\
/* Load q7: vmultiplier_c4567 */ ;\
VLD1.32 {d14, d15}, [r7] ;\
VCVT.F32.S32 q8, q8 ;\
VCVT.F32.S32 q9, q9 ;\
VCVT.F32.S32 q10, q10 ;\
VLD1.32 {q0}, [r6]! ;\
VLD1.32 {q1}, [r6] ;\
;\
VCVT.F32.S32 q11, q11 ;\
VCVT.F32.S32 q12, q12 ;\
VCVT.F32.S32 q13, q13 ;\
VCVT.F32.S32 q14, q14 ;\
VCVT.F32.S32 q15, q15 ;\
;\
VMUL.F32 q8, q8, q6 ;\
VMUL.F32 q9, q9, q7 ;\
VMUL.F32 q10, q10, q6 ;\
VMUL.F32 q11, q11, q7 ;\
VMUL.F32 q12, q12, q6 ;\
VMUL.F32 q13, q13, q7 ;\
VMUL.F32 q14, q14, q6 ;\
VMUL.F32 q15, q15, q7 ;\
;\
VADD.F32 q8, q8, q0 ;\
VADD.F32 q9, q9, q1 ;\
VADD.F32 q10, q10, q0 ;\
VADD.F32 q11, q11, q1 ;\
VADD.F32 q12, q12, q0 ;\
VADD.F32 q13, q13, q1 ;\
VADD.F32 q14, q14, q0 ;\
VADD.F32 q15, q15, q1 ;\
;\
/* Load c, c_stride: */ ;\
/* - r1 = c */ ;\
/* - r9 = c_stride */ ;\
LDR r1, [sp, 112] ;\
LDR r9, [sp, 116] ;\
LSL r9, r9, 2 ;\
;\
/* r1 = c0 = c pointer */ ;\
;\
CMP r0, 2 ;\
/* r2 = c1 */ ;\
ADD r2, r1, r9 ;\
MOVLO r2, r1 ;\
;\
/* r3 = c2 */ ;\
ADD r3, r2, r9 ;\
MOVLS r3, r2 ;\
;\
CMP r0, 4 ;\
/* r4 = c3 */ ;\
ADD r4, r3, r9 ;\
MOVNE r4, r3 ;\
;\
CMP r11, 8 ;\
BNE _4_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {q8}, [r1]! ;\
VST1.32 {q10}, [r2]! ;\
VST1.32 {q12}, [r3]! ;\
VST1.32 {q14}, [r4]! ;\
VST1.32 {q9}, [r1] ;\
VST1.32 {q11}, [r2] ;\
VST1.32 {q13}, [r3] ;\
VST1.32 {q15}, [r4] ;\
;\
VPOP {d8-d15} ;\
POP {r4, r5, r6, r7, r8, r9, r10, r11, lr} ;\
BX lr ;\
;\
.p2align 3 ;\
_4_w##W_INDEX_DTYPE_NUM_BITS##: ;\
CMP r11, 4 ;\
BLO _5_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {q8}, [r1]! ;\
VST1.32 {q10}, [r2]! ;\
VST1.32 {q12}, [r3]! ;\
VST1.32 {q14}, [r4]! ;\
;\
SUB r11, 4 ;\
;\
VMOV.32 q8, q9 ;\
VMOV.32 q10, q11 ;\
VMOV.32 q12, q13 ;\
VMOV.32 q14, q15 ;\
;\
_5_w##W_INDEX_DTYPE_NUM_BITS##: ;\
CMP r11, 2 ;\
BLO _6_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {d16}, [r1]! ;\
VST1.32 {d20}, [r2]! ;\
VST1.32 {d24}, [r3]! ;\
VST1.32 {d28}, [r4]! ;\
;\
SUB r11, 2 ;\
;\
VEXT.32 q8, q8, 2 ;\
VEXT.32 q10, q10, 2 ;\
VEXT.32 q12, q12, 2 ;\
VEXT.32 q14, q14, 2 ;\
;\
_6_w##W_INDEX_DTYPE_NUM_BITS##: ;\
TEQ r11, 0 ;\
BEQ _7_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {d16[0]}, [r1] ;\
VST1.32 {d20[0]}, [r2] ;\
VST1.32 {d24[0]}, [r3] ;\
VST1.32 {d28[0]}, [r4] ;\
;\
_7_w##W_INDEX_DTYPE_NUM_BITS##: ;\
VPOP {d8-d15} ;\
POP {r4, r5, r6, r7, r8, r9, r10, r11, lr} ;\
BX lr ;\
;\
END_FUNCTION pytorch_q8gemm_dq_sparse_8x1_ukernel_4x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch32_neon
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_4x8_packedA_w32__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint32_t* w_row_ptr,
# const uint32_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_4X8_PACKEDA__AARCH32_NEON(32, #4, #2, LDR)
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_4x8_packedA_w16__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint16_t* w_row_ptr,
# const uint16_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_4X8_PACKEDA__AARCH32_NEON(16, #2, #1, LDRH)
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_4x8_packedA_w8__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint8_t* w_row_ptr,
# const uint8_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_4X8_PACKEDA__AARCH32_NEON(8, #1, #0, LDRB)
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
#undef NDEF_APPLE_SYMBOLS
#undef MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_4X8_PACKEDA__AARCH32_NEON
|
gofreelee/torch_with_smask | 34,401 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/4x8c1x4-dq-packedA-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
#ifndef __APPLE__
#define NDEF_APPLE_SYMBOLS .arch armv7-a; .fpu neon
#else
#define NDEF_APPLE_SYMBOLS
#endif
# r0 mr
# r1 nr
# r2 packed_a
# r3 packed_w
# d14 a_zero_point
# d15 b_zero_point
## Stack
# 4 a_stride
# 4 packed_w
# 4 w_row_ptr
# 4 w_block_ids_ptr
# 4 b
# 4 c
# 4 c_stride
# 4 output channel index
# 4 quantization_params
# --
.syntax unified
# Args passed via stack.
# TOS
# |----------------|
# |packed_w | 0
# |w_row_ptr | 4
# |w_block_ids_ptr | 8
# |b | 12
# |c | 16
# |c_stride | 20
# |out ch indx | 24
# |params | 28
# |----------------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r9 and d8-d15 on stack
# |----------------|
# |d8 - d15 | 0
# |r4 - r11,lr | 64
# |w_row_ptr | 100
# |w_block_ids_ptr | 104
# |b | 108
# |c | 112
# |c_stride | 116
# |out ch indx | 120
# |params | 124
# |----------------|
#
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_4x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_row_ptr,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
#define MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_4X8_PACKEDA__AARCH32_NEON(W_INDEX_DTYPE_NUM_BITS, W_INDEX_DTYPE_NUM_BYTES_ARG, W_INDEX_DTYPE_LOG_NUM_BYTES_ARG, LOAD_INDEX_INSTRUCTION) ;\
BEGIN_FUNCTION pytorch_q8gemm_dq_sparse_1x4_ukernel_4x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch32_neon ;\
.arm ;\
NDEF_APPLE_SYMBOLS ;\
;\
PUSH {r4, r5, r6, r7, r8, r9, r10, r11, lr} ;\
VPUSH {d8-d15} ;\
;\
/* Store nr in r11 as well for late user. */ ;\
MOV r11, r1 ;\
/* Load output channel index */ ;\
LDR r5, [sp, 120] ;\
/* Load quantization params */ ;\
/* - r7 = quantization_params */ ;\
LDR r7, [sp, 124] ;\
/* Load input_zero_point */ ;\
VLD1.8 {d16[]}, [r7] ;\
ADD r7, r7, 4 ;\
/* Load pointer to per channel zero points array */ ;\
LDR r4, [r7] ;\
/* Add output_channel_index to the b_zero_point pointer */ ;\
ADD r4, r4, r5 ;\
;\
/* We enter the loop if r1 is atleast 1. */ ;\
/* r1 = r1 - 1 will happen in the epilogue */ ;\
/* of the loop */ ;\
CMP r1, 1 ;\
BLO _7_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
/* Load w_row_ptr + n */ ;\
LDR r5, [sp, 100] ;\
/* r7 = blocks_id_ptr */ ;\
LDR r7, [sp, 104] ;\
;\
.p2align 5 ;\
_0_w##W_INDEX_DTYPE_NUM_BITS##: ;\
VEOR q10, q10, q10 ;\
VLD1.8 {d17[]}, [r4]! ;\
/* ip = w_row_ptr[n], lr = w_row_ptr[n+1] */ ;\
/* r5 = r5 + W_INDEX_DTYPE_NUM_BYTES_ARG to point to next n */ ;\
LOAD_INDEX_INSTRUCTION ip, [r5], W_INDEX_DTYPE_NUM_BYTES_ARG ;\
LOAD_INDEX_INSTRUCTION lr, [r5] ;\
/* r6 = temp_packed_w = packed_w + w_row_ptr[n] * 4 */ ;\
/* This points to the first block of nonzero value */ ;\
/* for the nth row. */ ;\
ADD r6, r3, ip, LSL #2 ;\
/* r9 = temp_w_block_ids_ptr = w_block_ids_ptr (r7) + w_row_ptr[n] */ ;\
/* LSL for when elements are >1 byte */ ;\
/* (4 bytes: LSL #2, 2 bytes: LSL #1, 1 byte: LSL #0) */ ;\
/* This points to the block id of the first block */ ;\
/* It should contain lr - ip number of block ids */ ;\
ADD r9, r7, ip, LSL W_INDEX_DTYPE_LOG_NUM_BYTES_ARG ;\
/* r8 = num_blocks that needs to be processed */ ;\
SUB r8, lr, ip ;\
SUBS r8, r8, 2 ;\
BLO _1_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
k_loop_w##W_INDEX_DTYPE_NUM_BITS##: ;\
/* Load 2 non zero blocks of weights. Each block = 1x4. */ ;\
VLD1.8 {d0}, [r6]! ;\
;\
/* ip = block_id_ptr[0] */ ;\
/* lr = block_id_ptr[1] */ ;\
LOAD_INDEX_INSTRUCTION ip, [r9], W_INDEX_DTYPE_NUM_BYTES_ARG ;\
LOAD_INDEX_INSTRUCTION lr, [r9], W_INDEX_DTYPE_NUM_BYTES_ARG ;\
;\
/* Add offset to r2 */ ;\
/* Shift by 4 because each packed block is a block of 4x4 */ ;\
/* which 16 bytes */ ;\
ADD r10, r2, ip, LSL #4 ;\
/* q9 = vxb */ ;\
VSUBL.U8 q0, d0, d17 ;\
;\
/* d2, d3 = 4x4 transposed */ ;\
VLD1.8 {d2}, [r10]! ;\
VLD1.8 {d3}, [r10] ;\
;\
ADD r10, r2, lr, LSL #4 ;\
;\
VSUBL.U8 q4, d2, d16 /* vxa0_t */ ;\
;\
/* d4, d5 = next 4x4 transposed */ ;\
VLD1.8 {d4}, [r10]! ;\
VLD1.8 {d5}, [r10] ;\
;\
VSUBL.U8 q5, d3, d16 /* vxa1_t */ ;\
VSUBL.U8 q6, d4, d16 /* vxa4_t */ ;\
VSUBL.U8 q7, d5, d16 /* vxa5_t */ ;\
;\
/* q4, q5 = 4x4 block (16 values each of 16 bits) */ ;\
/* q6, q7 = 4x4 block (16 values each of 16 bits) */ ;\
;\
VMLAL.S16 q10, d8, d0[0] ;\
VMLAL.S16 q10, d9, d0[1] ;\
VMLAL.S16 q10, d10, d0[2] ;\
VMLAL.S16 q10, d11, d0[3] ;\
VMLAL.S16 q10, d12, d1[0] ;\
VMLAL.S16 q10, d13, d1[1] ;\
VMLAL.S16 q10, d14, d1[2] ;\
VMLAL.S16 q10, d15, d1[3] ;\
;\
SUBS r8, r8, 2 ;\
;\
BHS k_loop_w##W_INDEX_DTYPE_NUM_BITS ;\
_1_w##W_INDEX_DTYPE_NUM_BITS##: ;\
CMP r8, -2 ;\
BEQ _2_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
/* Load last nonzero block */ ;\
/* For this we will load 4 8 bit values as one 32 bit value */ ;\
VLD1.32 {d0[]}, [r6]! ;\
/* q9 = vxb */ ;\
VSUBL.U8 q0, d0, d17 ;\
;\
/* ip = block_id_ptr[0] */ ;\
LOAD_INDEX_INSTRUCTION ip, [r9] ;\
;\
/* Add offset to r2 */ ;\
/* Shift by 4 because each packed block is a block of 4x4 */ ;\
/* which 16 bytes */ ;\
ADD r10, r2, ip, LSL #4 ;\
;\
VLD1.8 {d2}, [r10]! ;\
VLD1.8 {d3}, [r10] ;\
;\
VSUBL.U8 q4, d2, d16 /* vxa0_t */ ;\
VSUBL.U8 q5, d3, d16 /* vxa1_t */ ;\
;\
VMLAL.S16 q10, d8, d0[0] ;\
VMLAL.S16 q10, d9, d0[1] ;\
VMLAL.S16 q10, d10, d0[2] ;\
VMLAL.S16 q10, d11, d0[3] ;\
;\
.p2align 4 ;\
_2_w##W_INDEX_DTYPE_NUM_BITS##: ;\
/* Store result on stack */ ;\
;\
/* -12 because TOS - 4, TOS - 8, and TOS - 12, store mr, nr and pointer to weight zp */ ;\
/* + 128 bytes of buffer when nr = 1 */ ;\
/* This is needed because after processing all nrs we will */ ;\
/* load 128 bytes from stack. This is for q10, q11 for max nr of 4 */ ;\
/* Thus we will load accumulators back in q0, q1, q2, q3, q4, q5, q6, q7 */ ;\
/* When nr < 4, extra q values will be fetched from stack which may overlap */ ;\
/* with other parts of stack storing local variables. To avoid that we just */ ;\
/* create a buffer of 128 bytes inbetween to make sure pointer increment */ ;\
/* never produces address that is beyond the stack frame of this function. */ ;\
SUB r9, sp, 140 ;\
/* Each iteration produce 4 values each of 4 bytes */ ;\
/* Thus 4 x 4 = 16 bytes 2^4 */ ;\
/* In this implementation, first value will be stored at */ ;\
/* 1st value: sp - 12 - r1 * 16 */ ;\
/* 2nd value: sp - 12 - (r1 - 1) * 16 */ ;\
/* and so on. */ ;\
SUB r9, r9, r1, LSL #4 ;\
VST1.32 {q10}, [r9] ;\
;\
/* Check if nr >=1 */ ;\
SUBS r1, r1, 1 ;\
BHI _0_w##W_INDEX_DTYPE_NUM_BITS ;\
_3_w##W_INDEX_DTYPE_NUM_BITS##: ;\
/* First load all the accumulators from stack */ ;\
/* Load nr */ ;\
SUB r9, sp, 140 ;\
SUB r9, r9, r11, LSL #4 ;\
/* Now load q8-q15 */ ;\
/* This is 8x4 block (nrxmr) */ ;\
/* We will transpose this to 4x8 (mrxnr) */ ;\
/* q8, q12 : x00, x10, x20, x30; x04, x14, x24, x34 */ ;\
/* q9, q13 : x01, x11, x21, x31; x05, x15, x25, x35 */ ;\
/* q10, q14 : x02, x12, x22, x32; x06, x16, x26, x36 */ ;\
/* q11, q15 : x03, x13, x23, x33; x07, x17, x27, x37 */ ;\
VLD1.32 {q8}, [r9]! ;\
VLD1.32 {q9}, [r9]! ;\
VLD1.32 {q10}, [r9]! ;\
VLD1.32 {q11}, [r9]! ;\
VLD1.32 {q12}, [r9]! ;\
VLD1.32 {q13}, [r9]! ;\
VLD1.32 {q14}, [r9]! ;\
VLD1.32 {q15}, [r9] ;\
;\
/*# Now transpose q8-11 */ ;\
/* VTRN.32 q8, q9 */ ;\
/* VTRN.32 q10, q11 */ ;\
/* q8 : X00, x01, x20, x21 */ ;\
/* q9 : X10, x11, x30, x31 */ ;\
/* q10: X02, x03, x22, x23 */ ;\
/* q11: X12, x13, x32, x33 */ ;\
/* VSWP d16, d17 */ ;\
/* q8 : x20, x21, x00, x01 */ ;\
/* VEXT.32 q6, q8, q10, 2 */ ;\
/* q6 : x00, x01, x02, x03 */ ;\
/* VEXT.32 q10, q10, q8, 2 */ ;\
/* q10: x22, x23, x20, x21 */ ;\
/* VSWP d20, d21 */ ;\
/* VMOV q8, q6 */ ;\
/* q8 : X00, x01, x02, x03 */ ;\
/* q10: x20, x21, x22, x23 */ ;\
/* VSWP d18, d19 */ ;\
/* q9 : x30, x31, x10, x11 */ ;\
/* VEXT.32 q6, q9, q11, 2 */ ;\
/* q6 : x10, x11, x12, x13 */ ;\
/* VEXT.32 q11, q11, q9, 2 */ ;\
/* q11: x32, x33, x30, x31 */ ;\
/* VSWP d22, d23 */ ;\
/* VMOV q9, q6 */ ;\
/* q9 : x10, x11, x12, x13 */ ;\
/* q11: x30, x31, x32, x33 */ ;\
/* Thus we have */ ;\
/* q8 : X00, x01, x02, x03 */ ;\
/* q9 : X10, x11, x12, x13 */ ;\
/* q10: X20, x21, x22, x23 */ ;\
/* q11: X30, x31, x32, x33 */ ;\
/* Now we can do the same for q4-q7 */ ;\
/* q12: X04, X05, X06, X07 */ ;\
/* q13: X14, X15, X16, X17 */ ;\
/* q14: X24, X25, X26, X27 */ ;\
/* q15: X34, X35, X36, X37 */ ;\
;\
VTRN.32 q8, q9 ;\
VTRN.32 q10, q11 ;\
VSWP d16, d17 ;\
VEXT.32 q6, q8, q10, 2 ;\
VEXT.32 q10, q10, q8, 2 ;\
VSWP d20, d21 ;\
VMOV q8, q6 ;\
VSWP d18, d19 ;\
VEXT.32 q6, q9, q11, 2 ;\
VEXT.32 q11, q11, q9, 2 ;\
VSWP d22, d23 ;\
VMOV q9, q6 ;\
;\
VTRN.32 q12, q13 ;\
VTRN.32 q14, q15 ;\
VSWP d24, d25 ;\
VEXT.32 q6, q12, q14, 2 ;\
VEXT.32 q14, q14, q12, 2 ;\
VSWP d28, d29 ;\
VMOV q12, q6 ;\
VSWP d26, d27 ;\
VEXT.32 q6, q13, q15, 2 ;\
VEXT.32 q15, q15, q13, 2 ;\
VSWP d30, d31 ;\
VMOV q13, q6 ;\
;\
/* Load output channel index */ ;\
LDR r5, [sp, 120] ;\
/* Load quantization params */ ;\
/* - r7 = quantization_params */ ;\
LDR r7, [sp, 124] ;\
ADD r7, r7, 8 ;\
/* Load pointer to per channel requant scale */ ;\
LDR r7, [r7] ;\
/* Now r7 has the base_addr + offset for multipliers */ ;\
ADD r7, r7, r5, LSL #2 ;\
;\
LDR r6, [sp, 108] ;\
/* Load q6: vmultiplier_c0123 */ ;\
VLD1.32 {d12, d13}, [r7]! ;\
/* Load q7: vmultiplier_c4567 */ ;\
VLD1.32 {d14, d15}, [r7] ;\
VCVT.F32.S32 q8, q8 ;\
VCVT.F32.S32 q9, q9 ;\
VCVT.F32.S32 q10, q10 ;\
VLD1.32 {q0}, [r6]! ;\
VLD1.32 {q1}, [r6] ;\
;\
VCVT.F32.S32 q11, q11 ;\
VCVT.F32.S32 q12, q12 ;\
VCVT.F32.S32 q13, q13 ;\
VCVT.F32.S32 q14, q14 ;\
VCVT.F32.S32 q15, q15 ;\
;\
VMUL.F32 q8, q8, q6 ;\
VMUL.F32 q9, q9, q6 ;\
VMUL.F32 q10, q10, q6 ;\
VMUL.F32 q11, q11, q6 ;\
VMUL.F32 q12, q12, q7 ;\
VMUL.F32 q13, q13, q7 ;\
VMUL.F32 q14, q14, q7 ;\
VMUL.F32 q15, q15, q7 ;\
;\
VADD.F32 q8, q8, q0 ;\
VADD.F32 q9, q9, q0 ;\
VADD.F32 q10, q10, q0 ;\
VADD.F32 q11, q11, q0 ;\
VADD.F32 q12, q12, q1 ;\
VADD.F32 q13, q13, q1 ;\
VADD.F32 q14, q14, q1 ;\
VADD.F32 q15, q15, q1 ;\
;\
/* Load c, c_stride: */ ;\
/* - r1 = c */ ;\
/* - r9 = c_stride */ ;\
LDR r1, [sp, 112] ;\
LDR r9, [sp, 116] ;\
LSL r9, r9, 2 ;\
;\
/* r1 = c0 = c pointer */ ;\
;\
CMP r0, 2 ;\
/* r2 = c1 */ ;\
ADD r2, r1, r9 ;\
MOVLO r2, r1 ;\
;\
/* r3 = c2 */ ;\
ADD r3, r2, r9 ;\
MOVLS r3, r2 ;\
;\
CMP r0, 4 ;\
/* r4 = c3 */ ;\
ADD r4, r3, r9 ;\
MOVNE r4, r3 ;\
;\
CMP r11, 8 ;\
BNE _4_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {q8}, [r1]! ;\
VST1.32 {q9}, [r2]! ;\
VST1.32 {q10}, [r3]! ;\
VST1.32 {q11}, [r4]! ;\
VST1.32 {q12}, [r1] ;\
VST1.32 {q13}, [r2] ;\
VST1.32 {q14}, [r3] ;\
VST1.32 {q15}, [r4] ;\
;\
VPOP {d8-d15} ;\
POP {r4, r5, r6, r7, r8, r9, r10, r11, lr} ;\
BX lr ;\
;\
.p2align 3 ;\
_4_w##W_INDEX_DTYPE_NUM_BITS##: ;\
CMP r11, 4 ;\
BLO _5_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {q8}, [r1]! ;\
VST1.32 {q9}, [r2]! ;\
VST1.32 {q10}, [r3]! ;\
VST1.32 {q11}, [r4]! ;\
;\
SUB r11, 4 ;\
;\
VMOV.32 q8, q12 ;\
VMOV.32 q9, q13 ;\
VMOV.32 q10, q14 ;\
VMOV.32 q11, q15 ;\
;\
_5_w##W_INDEX_DTYPE_NUM_BITS##: ;\
CMP r11, 2 ;\
BLO _6_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {d16}, [r1]! ;\
VST1.32 {d18}, [r2]! ;\
VST1.32 {d20}, [r3]! ;\
VST1.32 {d22}, [r4]! ;\
;\
SUB r11, 2 ;\
;\
VEXT.32 q8, q8, 2 ;\
VEXT.32 q9, q9, 2 ;\
VEXT.32 q10, q10, 2 ;\
VEXT.32 q11, q11, 2 ;\
;\
_6_w##W_INDEX_DTYPE_NUM_BITS##: ;\
TEQ r11, 0 ;\
BEQ _7_w##W_INDEX_DTYPE_NUM_BITS ;\
;\
VST1.32 {d16[0]}, [r1] ;\
VST1.32 {d18[0]}, [r2] ;\
VST1.32 {d20[0]}, [r3] ;\
VST1.32 {d22[0]}, [r4] ;\
;\
_7_w##W_INDEX_DTYPE_NUM_BITS##: ;\
VPOP {d8-d15} ;\
POP {r4, r5, r6, r7, r8, r9, r10, r11, lr} ;\
BX lr ;\
;\
END_FUNCTION pytorch_q8gemm_dq_sparse_1x4_ukernel_4x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch32_neon
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_4x8_packedA_w32__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint32_t* w_row_ptr,
# const uint32_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_4X8_PACKEDA__AARCH32_NEON(32, #4, #2, LDR)
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_4x8_packedA_w16__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint16_t* w_row_ptr,
# const uint16_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_4X8_PACKEDA__AARCH32_NEON(16, #2, #1, LDRH)
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_4x8_packedA_w8__aarch32_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint8_t* w_row_ptr,
# const uint8_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_4X8_PACKEDA__AARCH32_NEON(8, #1, #0, LDRB)
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
#undef NDEF_APPLE_SYMBOLS
#undef MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_4X8_PACKEDA__AARCH32_NEON
|
gofreelee/torch_with_smask | 39,799 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/8x8c1x4-dq-packedA-aarch64-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5 .p2align 5
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4 .p2align 4
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3 .p2align 3
#else
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3
#endif
# Macro for separating instructions. For most builds, ; can be used, but for
# ARM64 + Mach, ; begins a comment, and %% is used to separate instructions
#if defined(__MACH__)
#define XX %%
#else
#define XX ;
#endif
.macro TRANSPOSE_4X4_S32 vin0, vin1, vin2, vin3, temp0, temp1, temp2, temp3
TRN1 \temp0\().4s, \vin0\().4s, \vin1\().4s
TRN2 \temp1\().4s, \vin0\().4s, \vin1\().4s
TRN1 \temp2\().4s, \vin2\().4s, \vin3\().4s
TRN2 \temp3\().4s, \vin2\().4s, \vin3\().4s
TRN1 \vin0\().2d, \temp0\().2d, \temp2\().2d
TRN1 \vin1\().2d, \temp1\().2d, \temp3\().2d
TRN2 \vin2\().2d, \temp0\().2d, \temp2\().2d
TRN2 \vin3\().2d, \temp1\().2d, \temp3\().2d
.endm
# params
# c_stride
# Args passed via stack.
# TOS
# |-----------|
# |c_stride | 0
# |out ch indx| 8
# |params | 16
# |-----------|
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_8x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_row_ptr,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
#define MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_8X8_PACKEDA__AARCH64_NEON(W_INDEX_DTYPE_NUM_BITS, W_INDEX_DTYPE_NUM_BYTES_ARG, W_INDEX_DTYPE_LOG_NUM_BYTES_ARG, LOAD_INDEX_INSTRUCTION) XX\
BEGIN_FUNCTION pytorch_q8gemm_dq_sparse_1x4_ukernel_8x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch64_neon XX\
XX\
STP d15, d14, [sp, -16] XX\
STP d13, d12, [sp, -32] XX\
STP d11, d10, [sp, -48] XX\
STP d9, d8, [sp, -64] XX\
XX\
MOV x11, x1 XX\
/* Load output channel index */ XX\
LDR x10, [sp, 8] XX\
/* Load params */ XX\
LDR x8, [sp, 16] XX\
XX\
/* Load a_zero_point */ XX\
LD1R {v24.8b}, [x8] XX\
ADD x8, x8, 8 XX\
XX\
/* Load pointer to per channel zero points array */ XX\
LDR x17, [x8], 8 XX\
XX\
/* Load pointer to per channel multiplier */ XX\
LDR x13, [x8] XX\
XX\
/* Add offset to the base pointer */ XX\
ADD x17, x17, x10 XX\
/* Mul by 4 to get byte offset for multiplier */ XX\
LSL x10, x10, 2 XX\
/* Add offset to the base pointer for multiplier */ XX\
ADD x13, x13, x10 XX\
XX\
/* Load b_zero_point */ XX\
LD1 {v25.8b}, [x17] XX\
/* Load multiplier c0123 */ XX\
LD1 {v26.4s}, [x13], 16 XX\
/* Load multiplier c4567 */ XX\
LD1 {v30.4s}, [x13] XX\
XX\
EOR x12, x12, x12 XX\
EOR x13, x13, x13 XX\
XX\
CMP x1, 1 XX\
B.LO _7_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5 XX\
_0_w##W_INDEX_DTYPE_NUM_BITS##: XX\
/* v8 := zero */ XX\
EOR v8.16b, v8.16b, v8.16b XX\
/* v9 := zero */ XX\
EOR v9.16b, v9.16b, v9.16b XX\
XX\
DUP v29.8b, v25.b[0] XX\
/* w12 = w_row_ptr[n], x13 = w_row_ptr[n+1] */ XX\
/* x4 = x4 + W_INDEX_DTYPE_NUM_BYTES_ARG to point to next n */ XX\
LOAD_INDEX_INSTRUCTION w12, [x4], W_INDEX_DTYPE_NUM_BYTES_ARG XX\
LOAD_INDEX_INSTRUCTION w13, [x4] XX\
/* x10 = temp_packed_w = packed_w + w_row_ptr[n] * 4 */ XX\
/* This points to the first block of nonzero value */ XX\
/* for the nth row. */ XX\
ADD x10, x3, x12, LSL #2 XX\
/* x9 = temp_w_block_ids_ptr = w_block_ids_ptr (x5) + w_row_ptr[n] */ XX\
/* LSL for when elements are >1 byte */ XX\
/* (4 bytes: LSL #2, 2 bytes: LSL #1, 1 byte: LSL #0) */ XX\
/* This points to the block id of the first block */ XX\
/* It should contain x13 - x12 number of block ids */ XX\
ADD x9, x5, x12, LSL W_INDEX_DTYPE_LOG_NUM_BYTES_ARG XX\
/* x8 = num_blocks that needs to be processed */ XX\
SUB x8, x13, x12 XX\
SUBS x8, x8, 2 XX\
B.LO _1_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
k_loop_w##W_INDEX_DTYPE_NUM_BITS##: XX\
/* b0-7 (channel 0) */ XX\
LD1 {v10.8b}, [x10], 8 XX\
USUBL v10.8h, v10.8b, v29.8b XX\
XX\
/* x12 = block_id_ptr[0] */ XX\
/* x13 = block_id_ptr[1] */ XX\
LOAD_INDEX_INSTRUCTION w12, [x9], W_INDEX_DTYPE_NUM_BYTES_ARG XX\
LOAD_INDEX_INSTRUCTION w13, [x9], W_INDEX_DTYPE_NUM_BYTES_ARG XX\
/* Add offset to x2 */ XX\
/* Shift by 5 because each packed block is a block of 8x4 */ XX\
/* which 32 bytes */ XX\
ADD x16, x2, x12, LSL #5 XX\
ADD x17, x2, x13, LSL #5 XX\
XX\
LD1 {v0.8b}, [x16], 8 XX\
LD1 {v1.8b}, [x16], 8 XX\
LD1 {v2.8b}, [x16], 8 XX\
LD1 {v3.8b}, [x16] XX\
LD1 {v4.8b}, [x17], 8 XX\
LD1 {v5.8b}, [x17], 8 XX\
LD1 {v6.8b}, [x17], 8 XX\
LD1 {v7.8b}, [x17] XX\
XX\
USUBL v0.8h, v0.8b, v24.8b XX\
USUBL v1.8h, v1.8b, v24.8b XX\
USUBL v2.8h, v2.8b, v24.8b XX\
USUBL v3.8h, v3.8b, v24.8b XX\
USUBL v4.8h, v4.8b, v24.8b XX\
USUBL v5.8h, v5.8b, v24.8b XX\
USUBL v6.8h, v6.8b, v24.8b XX\
USUBL v7.8h, v7.8b, v24.8b XX\
XX\
SMLAL v8.4s, v0.4h, v10.h[0] XX\
SMLAL2 v9.4s, v0.8h, v10.h[0] XX\
SMLAL v8.4s, v1.4h, v10.h[1] XX\
SMLAL2 v9.4s, v1.8h, v10.h[1] XX\
SMLAL v8.4s, v2.4h, v10.h[2] XX\
SMLAL2 v9.4s, v2.8h, v10.h[2] XX\
SMLAL v8.4s, v3.4h, v10.h[3] XX\
SMLAL2 v9.4s, v3.8h, v10.h[3] XX\
SMLAL v8.4s, v4.4h, v10.h[4] XX\
SMLAL2 v9.4s, v4.8h, v10.h[4] XX\
SMLAL v8.4s, v5.4h, v10.h[5] XX\
SMLAL2 v9.4s, v5.8h, v10.h[5] XX\
SMLAL v8.4s, v6.4h, v10.h[6] XX\
SMLAL2 v9.4s, v6.8h, v10.h[6] XX\
SUBS x8, x8, 2 XX\
SMLAL v8.4s, v7.4h, v10.h[7] XX\
SMLAL2 v9.4s, v7.8h, v10.h[7] XX\
XX\
XX\
B.HS k_loop_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
_1_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x8, -2 XX\
B.EQ _2_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
/* b0-7 (channel 0) */ XX\
LD1R {v10.4s}, [x10] XX\
USUBL v10.8h, v10.8b, v29.8b XX\
XX\
/* x12 = block_id_ptr[0] */ XX\
LOAD_INDEX_INSTRUCTION w12, [x9] XX\
/* Add offset to x2 */ XX\
/* Shift by 5 because each packed block is a block of 8x4 */ XX\
/* which 32 bytes */ XX\
ADD x16, x2, x12, LSL #5 XX\
XX\
LD1 {v0.8b}, [x16], 8 XX\
LD1 {v1.8b}, [x16], 8 XX\
LD1 {v2.8b}, [x16], 8 XX\
LD1 {v3.8b}, [x16] XX\
XX\
USUBL v0.8h, v0.8b, v24.8b XX\
USUBL v1.8h, v1.8b, v24.8b XX\
USUBL v2.8h, v2.8b, v24.8b XX\
USUBL v3.8h, v3.8b, v24.8b XX\
XX\
SMLAL v8.4s, v0.4h, v10.h[0] XX\
SMLAL2 v9.4s, v0.8h, v10.h[0] XX\
SMLAL v8.4s, v1.4h, v10.h[1] XX\
SMLAL2 v9.4s, v1.8h, v10.h[1] XX\
SMLAL v8.4s, v2.4h, v10.h[2] XX\
SMLAL2 v9.4s, v2.8h, v10.h[2] XX\
SMLAL v8.4s, v3.4h, v10.h[3] XX\
SMLAL2 v9.4s, v3.8h, v10.h[3] XX\
XX\
NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4 XX\
_2_w##W_INDEX_DTYPE_NUM_BITS##: XX\
/* Store result on stack */ XX\
XX\
/* -64 because all d8-d15 are on stack */ XX\
/* + 256 bytes of buffer when nr = 1 */ XX\
/* 256 because we are doing 8x8 block with each value being 4 bytes */ XX\
/* Thus 64 * 4 = 256 */ XX\
/* 256 + 64 = 320 */ XX\
/* This is needed because after processing all nrs we will */ XX\
/* load 256 bytes from stack. */ XX\
/* Thus we will load accumulators back in v8, v9, v10, v11, v12, v13, v14, v15 */ XX\
/* v16, v17, v18, v19, v20, v21, v22, v23 */ XX\
/* When nr < 8, say nr = 1, extra v values will be fetched from stack which may overlap */ XX\
/* with other parts of stack storing local variables. To avoid that we just */ XX\
/* create a buffer of 256 bytes inbetween to make sure pointer increment */ XX\
/* never produces address that is beyond the stack frame of this function. */ XX\
SUB x9, sp, 320 XX\
/* Each iteration produce 8 values each of 4 bytes */ XX\
/* Thus 8 x 4 = 32 bytes 2^5 */ XX\
/* In this implementation, first value will be stored at */ XX\
/* 1st value: sp - 64 - r1 * 32 */ XX\
/* 2nd value: sp - 12 - (r1 - 1) * 32 */ XX\
/* and so on. */ XX\
SUB x9, x9, x1, LSL #5 XX\
ST1 {v8.4s}, [x9], 16 XX\
ST1 {v9.4s}, [x9] XX\
XX\
/* Shift zero point vector by 8 to load */ XX\
/* zero point of the next channel */ XX\
SRI v25.2d, v25.2d, #8 XX\
/* Check if nr >=1 */ XX\
SUBS x1, x1, 1 XX\
BHI _0_w##W_INDEX_DTYPE_NUM_BITS XX\
_3_w##W_INDEX_DTYPE_NUM_BITS##: XX\
/* First load all the accumulators from stack */ XX\
/* Load nr */ XX\
SUB x9, sp, 320 XX\
SUB x9, x9, x11, LSL #5 XX\
/* Now load v8-v15 */ XX\
/* This is 8x4 block (nrxmr) */ XX\
/* We will transpose this to 4x8 (mrxnr) */ XX\
/* v8, v9 : x00, x10, x20, x30; x40, x50, x60, x70 */ XX\
/* v10, v11 : x01, x11, x21, x31; x41, x51, x61, x71 */ XX\
/* v12, v13 : x02, x12, x22, x32; x42, x52, x62, x72 */ XX\
/* v14, v15 : x03, x13, x23, x33; x43, x53, x63, x73 */ XX\
/* */ XX\
/* v16, v17 : x04, x14, x24, x34; x44, x54, x64, x74 */ XX\
/* v18, v19 : x05, x15, x25, x35; x45, x55, x65, x75 */ XX\
/* v20, v21 : x06, x16, x26, x36; x46, x56, x66, x76 */ XX\
/* v22, v23 : x07, x17, x27, x37; x47, x57, x67, x77 */ XX\
LD1 {v8.4s}, [x9], 16 XX\
LD1 {v9.4s}, [x9], 16 XX\
LD1 {v10.4s}, [x9], 16 XX\
LD1 {v11.4s}, [x9], 16 XX\
LD1 {v12.4s}, [x9], 16 XX\
LD1 {v13.4s}, [x9], 16 XX\
LD1 {v14.4s}, [x9], 16 XX\
LD1 {v15.4s}, [x9], 16 XX\
LD1 {v16.4s}, [x9], 16 XX\
LD1 {v17.4s}, [x9], 16 XX\
LD1 {v18.4s}, [x9], 16 XX\
LD1 {v19.4s}, [x9], 16 XX\
LD1 {v20.4s}, [x9], 16 XX\
LD1 {v21.4s}, [x9], 16 XX\
LD1 {v22.4s}, [x9], 16 XX\
LD1 {v23.4s}, [x9] XX\
XX\
/* We can tranpose one 4x4 block using macro */ XX\
/* TRANSPOSE_4X4_S32 v8, v10, v12, v14, v0, v1, v2, v3 */ XX\
/* After this we have */ XX\
/* v8 : x00, x01, x02, x03 */ XX\
/* v10 : x10, x11, x12, x13 */ XX\
/* v12 : x20, x21, x22, x23 */ XX\
/* v14 : x30, x31, x32, x33 */ XX\
/* Then using */ XX\
/* TRANSPOSE_4X4_S32 v16, v18, v20, v22, v4, v5, v6, v7 */ XX\
/* We get */ XX\
/* v16 : x04, x05, x06, x07 */ XX\
/* v18 : x14, x15, x16, x17 */ XX\
/* v20 : x24, x25, x26, x27 */ XX\
/* v22 : x34, x35, x36, x37 */ XX\
/* Similarly we can transpose other two 4x4 blocks and we get */ XX\
/* tranposed 8x8 */ XX\
XX\
TRANSPOSE_4X4_S32 v8, v10, v12, v14, v0, v1, v2, v3 XX\
TRANSPOSE_4X4_S32 v16, v18, v20, v22, v4, v5, v6, v7 XX\
TRANSPOSE_4X4_S32 v9, v11, v13, v15, v0, v1, v2, v3 XX\
TRANSPOSE_4X4_S32 v17, v19, v21, v23, v4, v5, v6, v7 XX\
XX\
/* row 0: v8, v16 */ XX\
/* row 1: v10, v18 */ XX\
/* row 2: v12, v20 */ XX\
/* row 3: v14, v22 */ XX\
/* row 4: v9, v17 */ XX\
/* row 5: v11, v19 */ XX\
/* row 6: v13, v21 */ XX\
/* row 7: v15, v23 */ XX\
XX\
/* Load c_stride & params */ XX\
LDR x16, [sp] XX\
LSL x16, x16, 2 XX\
LD1 {v24.4s}, [x6], 16 XX\
LD1 {v25.4s}, [x6] XX\
XX\
SCVTF v8.4s, v8.4s XX\
SCVTF v9.4s, v9.4s XX\
SCVTF v10.4s, v10.4s XX\
SCVTF v11.4s, v11.4s XX\
SCVTF v12.4s, v12.4s XX\
SCVTF v13.4s, v13.4s XX\
SCVTF v14.4s, v14.4s XX\
SCVTF v15.4s, v15.4s XX\
SCVTF v16.4s, v16.4s XX\
SCVTF v17.4s, v17.4s XX\
SCVTF v18.4s, v18.4s XX\
SCVTF v19.4s, v19.4s XX\
SCVTF v20.4s, v20.4s XX\
SCVTF v21.4s, v21.4s XX\
SCVTF v22.4s, v22.4s XX\
SCVTF v23.4s, v23.4s XX\
XX\
FMUL v8.4s, v8.4s, v26.4s XX\
FMUL v16.4s, v16.4s, v30.4s XX\
FMUL v10.4s, v10.4s, v26.4s XX\
FMUL v18.4s, v18.4s, v30.4s XX\
FMUL v12.4s, v12.4s, v26.4s XX\
FMUL v20.4s, v20.4s, v30.4s XX\
FMUL v14.4s, v14.4s, v26.4s XX\
FMUL v22.4s, v22.4s, v30.4s XX\
FMUL v9.4s, v9.4s, v26.4s XX\
FMUL v17.4s, v17.4s, v30.4s XX\
FMUL v11.4s, v11.4s, v26.4s XX\
FMUL v19.4s, v19.4s, v30.4s XX\
FMUL v13.4s, v13.4s, v26.4s XX\
FMUL v21.4s, v21.4s, v30.4s XX\
FMUL v15.4s, v15.4s, v26.4s XX\
FMUL v23.4s, v23.4s, v30.4s XX\
XX\
FADD v8.4s, v8.4s, v24.4s XX\
FADD v16.4s, v16.4s, v25.4s XX\
FADD v10.4s, v10.4s, v24.4s XX\
FADD v18.4s, v18.4s, v25.4s XX\
FADD v12.4s, v12.4s, v24.4s XX\
FADD v20.4s, v20.4s, v25.4s XX\
FADD v14.4s, v14.4s, v24.4s XX\
FADD v22.4s, v22.4s, v25.4s XX\
FADD v9.4s, v9.4s, v24.4s XX\
FADD v17.4s, v17.4s, v25.4s XX\
FADD v11.4s, v11.4s, v24.4s XX\
FADD v19.4s, v19.4s, v25.4s XX\
FADD v13.4s, v13.4s, v24.4s XX\
FADD v21.4s, v21.4s, v25.4s XX\
FADD v15.4s, v15.4s, v24.4s XX\
FADD v23.4s, v23.4s, v25.4s XX\
XX\
/* Compute c0-c7 */ XX\
XX\
ADD x9, x7, x16 XX\
CMP x0, 2 XX\
CSEL x9, x7, x9, LO XX\
XX\
ADD x10, x9, x16 XX\
CSEL x10, x9, x10, LS XX\
XX\
ADD x8, x10, x16 XX\
CMP x0, 4 XX\
CSEL x8, x10, x8, LO XX\
XX\
ADD x12, x8, x16 XX\
CSEL x12, x8, x12, LS XX\
XX\
ADD x13, x12, x16 XX\
CMP x0, 6 XX\
CSEL x13, x12, x13, LO XX\
XX\
ADD x14, x13, x16 XX\
CSEL x14, x13, x14, LS XX\
XX\
ADD x15, x14, x16 XX\
CMP x0, 8 XX\
CSEL x15, x14, x15, NE XX\
XX\
CMP x11, 8 XX\
B.NE _4_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.4s}, [x7], 16 XX\
ST1 {v16.4s}, [x7] XX\
ST1 {v10.4s}, [x9], 16 XX\
ST1 {v18.4s}, [x9] XX\
ST1 {v12.4s}, [x10], 16 XX\
ST1 {v20.4s}, [x10] XX\
ST1 {v14.4s}, [x8], 16 XX\
ST1 {v22.4s}, [x8] XX\
ST1 {v9.4s}, [x12], 16 XX\
ST1 {v17.4s}, [x12] XX\
ST1 {v11.4s}, [x13], 16 XX\
ST1 {v19.4s}, [x13] XX\
ST1 {v13.4s}, [x14], 16 XX\
ST1 {v21.4s}, [x14] XX\
ST1 {v15.4s}, [x15], 16 XX\
ST1 {v23.4s}, [x15] XX\
XX\
LDP d9, d8, [sp, -64] XX\
LDP d11, d10, [sp, -48] XX\
LDP d13, d12, [sp, -32] XX\
LDP d15, d14, [sp, -16] XX\
XX\
RET XX\
XX\
NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3 XX\
_4_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x11, 4 XX\
B.LO _5_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.4s}, [x7], 16 XX\
ST1 {v10.4s}, [x9], 16 XX\
ST1 {v12.4s}, [x10], 16 XX\
ST1 {v14.4s}, [x8], 16 XX\
ST1 {v9.4s}, [x12], 16 XX\
ST1 {v11.4s}, [x13], 16 XX\
ST1 {v13.4s}, [x14], 16 XX\
ST1 {v15.4s}, [x15], 16 XX\
XX\
SUB x11, x11, 4 XX\
XX\
MOV v8.16b, v16.16b XX\
MOV v10.16b, v18.16b XX\
MOV v12.16b, v20.16b XX\
MOV v14.16b, v22.16b XX\
MOV v9.16b, v17.16b XX\
MOV v11.16b, v19.16b XX\
MOV v13.16b, v21.16b XX\
MOV v15.16b, v23.16b XX\
XX\
_5_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x11, 2 XX\
B.LO _6_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.2s}, [x7], 8 XX\
ST1 {v10.2s}, [x9], 8 XX\
ST1 {v12.2s}, [x10], 8 XX\
ST1 {v14.2s}, [x8], 8 XX\
ST1 {v9.2s}, [x12], 8 XX\
ST1 {v11.2s}, [x13], 8 XX\
ST1 {v13.2s}, [x14], 8 XX\
ST1 {v15.2s}, [x15], 8 XX\
XX\
SUB x11, x11, 2 XX\
XX\
EXT v8.16b, v8.16b, v8.16b, 8 XX\
EXT v10.16b, v10.16b, v10.16b, 8 XX\
EXT v12.16b, v12.16b, v12.16b, 8 XX\
EXT v14.16b, v14.16b, v14.16b, 8 XX\
EXT v9.16b, v9.16b, v9.16b, 8 XX\
EXT v11.16b, v11.16b, v11.16b, 8 XX\
EXT v13.16b, v13.16b, v13.16b, 8 XX\
EXT v15.16b, v15.16b, v15.16b, 8 XX\
XX\
_6_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x11, 1 XX\
B.LO _7_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.s}[0], [x7] XX\
ST1 {v10.s}[0], [x9] XX\
ST1 {v12.s}[0], [x10] XX\
ST1 {v14.s}[0], [x8] XX\
ST1 {v9.s}[0], [x12] XX\
ST1 {v11.s}[0], [x13] XX\
ST1 {v13.s}[0], [x14] XX\
ST1 {v15.s}[0], [x15] XX\
XX\
_7_w##W_INDEX_DTYPE_NUM_BITS##: XX\
LDP d9, d8, [sp, -64] XX\
LDP d11, d10, [sp, -48] XX\
LDP d13, d12, [sp, -32] XX\
LDP d15, d14, [sp, -16] XX\
XX\
RET XX\
XX\
END_FUNCTION pytorch_q8gemm_dq_sparse_1x4_ukernel_8x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch64_neon
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_8x8_packedA_w32__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint32_t* w_row_ptr,
# const uint32_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_8X8_PACKEDA__AARCH64_NEON(32, #4, #2, LDR)
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_8x8_packedA_w16__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint16_t* w_row_ptr,
# const uint16_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_8X8_PACKEDA__AARCH64_NEON(16, #2, #1, LDRH)
# void pytorch_q8gemm_dq_sparse_1x4_ukernel_8x8_packedA_w8__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint8_t* w_row_ptr,
# const uint8_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_8X8_PACKEDA__AARCH64_NEON(8, #1, #0, LDRB)
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
#undef NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5
#undef NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4
#undef NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3
#undef MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_1X4_UKERNEL_8X8_PACKEDA__AARCH64_NEON
#undef XX
|
gofreelee/torch_with_smask | 33,514 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/8x8c8x1-dq-packedA-aarch64-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#ifndef IGNORE_CODE_ALIGN_DIRECTIVES
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5 .p2align 5
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4 .p2align 4
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3 .p2align 3
#else
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4
#define NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3
#endif
# Macro for separating instructions. For most builds, ; can be used, but for
# ARM64 + Mach, ; begins a comment, and %% is used to separate instructions
#if defined(__MACH__)
#define XX %%
#else
#define XX ;
#endif
# params
# c_stride
# Args passed via stack.
# TOS
# |-----------|
# |c_stride | 0
# |out ch indx| 8
# |params | 16
# |-----------|
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_8x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_row_ptr,
# const uint##W_INDEX_DTYPE_NUM_BITS##_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
#define MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_8X8_PACKEDA__AARCH64_NEON(W_INDEX_DTYPE_NUM_BITS, W_INDEX_DTYPE_NUM_BYTES_ARG, W_INDEX_DTYPE_LOG_NUM_BYTES_ARG, LOAD_INDEX_INSTRUCTION) XX\
BEGIN_FUNCTION pytorch_q8gemm_dq_sparse_8x1_ukernel_8x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch64_neon XX\
XX\
STP d15, d14, [sp, -16] XX\
STP d13, d12, [sp, -32] XX\
STP d11, d10, [sp, -48] XX\
STP d9, d8, [sp, -64] XX\
XX\
MOV x11, x1 XX\
/* Load output channel index */ XX\
LDR x10, [sp, 8] XX\
/* Load params */ XX\
LDR x8, [sp, 16] XX\
XX\
/* Load a_zero_point */ XX\
LD1R {v24.8b}, [x8] XX\
ADD x8, x8, 8 XX\
XX\
/* Load pointer to per channel zero points array */ XX\
LDR x17, [x8], 8 XX\
XX\
/* Load pointer to per channel multiplier */ XX\
LDR x13, [x8] XX\
XX\
/* Add offset to the base pointer */ XX\
ADD x17, x17, x10 XX\
/* Mul by 4 to get byte offset for multiplier */ XX\
LSL x10, x10, 2 XX\
/* Add offset to the base pointer for multiplier */ XX\
ADD x13, x13, x10 XX\
XX\
/* Load b_zero_point */ XX\
LD1 {v25.8b}, [x17] XX\
/* Load multiplier c0123 */ XX\
LD1 {v26.4s}, [x13], 16 XX\
/* Load multiplier c4567 */ XX\
LD1 {v30.4s}, [x13] XX\
XX\
EOR x12, x12, x12 XX\
EOR x13, x13, x13 XX\
XX\
EOR v8.16b, v8.16b, v8.16b XX\
EOR v9.16b, v9.16b, v9.16b XX\
EOR v10.16b, v10.16b, v10.16b XX\
EOR v11.16b, v11.16b, v11.16b XX\
EOR v12.16b, v12.16b, v12.16b XX\
EOR v13.16b, v13.16b, v13.16b XX\
EOR v14.16b, v14.16b, v14.16b XX\
EOR v15.16b, v15.16b, v15.16b XX\
EOR v16.16b, v16.16b, v16.16b XX\
EOR v17.16b, v17.16b, v17.16b XX\
EOR v18.16b, v18.16b, v18.16b XX\
EOR v19.16b, v19.16b, v19.16b XX\
EOR v20.16b, v20.16b, v20.16b XX\
EOR v21.16b, v21.16b, v21.16b XX\
EOR v22.16b, v22.16b, v22.16b XX\
EOR v23.16b, v23.16b, v23.16b XX\
XX\
/* w12 = w_row_ptr[n], x13 = w_row_ptr[n+1] */ XX\
/* x4 = x4 + W_INDEX_DTYPE_NUM_BYTES_ARG to point to next n */ XX\
LOAD_INDEX_INSTRUCTION w12, [x4], W_INDEX_DTYPE_NUM_BYTES_ARG XX\
LOAD_INDEX_INSTRUCTION w13, [x4] XX\
/* x10 = temp_packed_w = packed_w + w_row_ptr[n] * 8 */ XX\
/* This points to the first block of nonzero value */ XX\
/* for the nth row. */ XX\
ADD x10, x3, x12, LSL #3 XX\
/* x9 = temp_w_block_ids_ptr = w_block_ids_ptr (x5) + w_row_ptr[n] */ XX\
/* LSL for when elements are >1 byte */ XX\
/* (4 bytes: LSL #2, 2 bytes: LSL #1, 1 byte: LSL #0) */ XX\
/* This points to the block id of the first block */ XX\
/* It should contain x13 - x12 number of block ids */ XX\
ADD x9, x5, x12, LSL W_INDEX_DTYPE_LOG_NUM_BYTES_ARG XX\
/* x8 = num_blocks that needs to be processed */ XX\
SUB x8, x13, x12 XX\
SUBS x8, x8, 2 XX\
B.LO _1_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5 XX\
k_loop_w##W_INDEX_DTYPE_NUM_BITS##: XX\
/* k_loop processes two k values */ XX\
/* Load two 8x1 blocks */ XX\
LD1 {v0.8b}, [x10], 8 XX\
LD1 {v1.8b}, [x10], 8 XX\
USUBL v0.8h, v0.8b, v25.8b XX\
USUBL v1.8h, v1.8b, v25.8b XX\
XX\
/* x12 = block_id_ptr[0] */ XX\
/* x13 = block_id_ptr[1] */ XX\
LOAD_INDEX_INSTRUCTION w12, [x9], W_INDEX_DTYPE_NUM_BYTES_ARG XX\
LOAD_INDEX_INSTRUCTION w13, [x9], W_INDEX_DTYPE_NUM_BYTES_ARG XX\
/* Add offset to x2 */ XX\
/* Shift by 3 because each packed block is a block of 8x1 */ XX\
/* which 8 bytes */ XX\
ADD x16, x2, x12, LSL #3 XX\
ADD x17, x2, x13, LSL #3 XX\
XX\
/* Load two 8x1 blocks of activation */ XX\
/* First 8x1 for first channel */ XX\
/* second 8x1 for next channel */ XX\
LD1 {v2.8b}, [x16] XX\
LD1 {v3.8b}, [x17] XX\
XX\
USUBL v2.8h, v2.8b, v24.8b XX\
USUBL v3.8h, v3.8b, v24.8b XX\
XX\
/* First channel */ XX\
SMLAL v8.4s, v0.4h, v2.h[0] XX\
SMLAL2 v9.4s, v0.8h, v2.h[0] XX\
SMLAL v10.4s, v0.4h, v2.h[1] XX\
SMLAL2 v11.4s, v0.8h, v2.h[1] XX\
SMLAL v12.4s, v0.4h, v2.h[2] XX\
SMLAL2 v13.4s, v0.8h, v2.h[2] XX\
SMLAL v14.4s, v0.4h, v2.h[3] XX\
SMLAL2 v15.4s, v0.8h, v2.h[3] XX\
SMLAL v16.4s, v0.4h, v2.h[4] XX\
SMLAL2 v17.4s, v0.8h, v2.h[4] XX\
SMLAL v18.4s, v0.4h, v2.h[5] XX\
SMLAL2 v19.4s, v0.8h, v2.h[5] XX\
SMLAL v20.4s, v0.4h, v2.h[6] XX\
SMLAL2 v21.4s, v0.8h, v2.h[6] XX\
SMLAL v22.4s, v0.4h, v2.h[7] XX\
SMLAL2 v23.4s, v0.8h, v2.h[7] XX\
XX\
SUBS x8, x8, 2 XX\
/* Second channel */ XX\
SMLAL v8.4s, v1.4h, v3.h[0] XX\
SMLAL2 v9.4s, v1.8h, v3.h[0] XX\
SMLAL v10.4s, v1.4h, v3.h[1] XX\
SMLAL2 v11.4s, v1.8h, v3.h[1] XX\
SMLAL v12.4s, v1.4h, v3.h[2] XX\
SMLAL2 v13.4s, v1.8h, v3.h[2] XX\
SMLAL v14.4s, v1.4h, v3.h[3] XX\
SMLAL2 v15.4s, v1.8h, v3.h[3] XX\
SMLAL v16.4s, v1.4h, v3.h[4] XX\
SMLAL2 v17.4s, v1.8h, v3.h[4] XX\
SMLAL v18.4s, v1.4h, v3.h[5] XX\
SMLAL2 v19.4s, v1.8h, v3.h[5] XX\
SMLAL v20.4s, v1.4h, v3.h[6] XX\
SMLAL2 v21.4s, v1.8h, v3.h[6] XX\
SMLAL v22.4s, v1.4h, v3.h[7] XX\
SMLAL2 v23.4s, v1.8h, v3.h[7] XX\
XX\
B.HS k_loop_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
_1_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x8, -2 XX\
B.EQ _3_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
LD1 {v0.8b}, [x10] XX\
USUBL v0.8h, v0.8b, v25.8b XX\
XX\
/* x12 = block_id_ptr[0] */ XX\
LOAD_INDEX_INSTRUCTION w12, [x9] XX\
/* Add offset to x2 */ XX\
ADD x16, x2, x12, LSL #3 XX\
XX\
LD1 {v2.8b}, [x16] XX\
USUBL v2.8h, v2.8b, v24.8b XX\
XX\
SMLAL v8.4s, v0.4h, v2.h[0] XX\
SMLAL2 v9.4s, v0.8h, v2.h[0] XX\
SMLAL v10.4s, v0.4h, v2.h[1] XX\
SMLAL2 v11.4s, v0.8h, v2.h[1] XX\
SMLAL v12.4s, v0.4h, v2.h[2] XX\
SMLAL2 v13.4s, v0.8h, v2.h[2] XX\
SMLAL v14.4s, v0.4h, v2.h[3] XX\
SMLAL2 v15.4s, v0.8h, v2.h[3] XX\
SMLAL v16.4s, v0.4h, v2.h[4] XX\
SMLAL2 v17.4s, v0.8h, v2.h[4] XX\
SMLAL v18.4s, v0.4h, v2.h[5] XX\
SMLAL2 v19.4s, v0.8h, v2.h[5] XX\
SMLAL v20.4s, v0.4h, v2.h[6] XX\
SMLAL2 v21.4s, v0.8h, v2.h[6] XX\
SMLAL v22.4s, v0.4h, v2.h[7] XX\
SMLAL2 v23.4s, v0.8h, v2.h[7] XX\
XX\
NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4 XX\
_3_w##W_INDEX_DTYPE_NUM_BITS##: XX\
/* row 0: v8, v9 */ XX\
/* row 1: v10, v11 */ XX\
/* row 2: v12, v13 */ XX\
/* row 3: v14, v15 */ XX\
/* row 4: v16, v17 */ XX\
/* row 5: v18, v19 */ XX\
/* row 6: v20, v21 */ XX\
/* row 7: v22, v23 */ XX\
XX\
/* Load c_stride & params */ XX\
LDR x16, [sp] XX\
LSL x16, x16, 2 XX\
LD1 {v24.4s}, [x6], 16 XX\
LD1 {v25.4s}, [x6] XX\
XX\
SCVTF v8.4s, v8.4s XX\
SCVTF v9.4s, v9.4s XX\
SCVTF v10.4s, v10.4s XX\
SCVTF v11.4s, v11.4s XX\
SCVTF v12.4s, v12.4s XX\
SCVTF v13.4s, v13.4s XX\
SCVTF v14.4s, v14.4s XX\
SCVTF v15.4s, v15.4s XX\
SCVTF v16.4s, v16.4s XX\
SCVTF v17.4s, v17.4s XX\
SCVTF v18.4s, v18.4s XX\
SCVTF v19.4s, v19.4s XX\
SCVTF v20.4s, v20.4s XX\
SCVTF v21.4s, v21.4s XX\
SCVTF v22.4s, v22.4s XX\
SCVTF v23.4s, v23.4s XX\
XX\
FMUL v8.4s, v8.4s, v26.4s XX\
FMUL v9.4s, v9.4s, v30.4s XX\
FMUL v10.4s, v10.4s, v26.4s XX\
FMUL v11.4s, v11.4s, v30.4s XX\
FMUL v12.4s, v12.4s, v26.4s XX\
FMUL v13.4s, v13.4s, v30.4s XX\
FMUL v14.4s, v14.4s, v26.4s XX\
FMUL v15.4s, v15.4s, v30.4s XX\
FMUL v16.4s, v16.4s, v26.4s XX\
FMUL v17.4s, v17.4s, v30.4s XX\
FMUL v18.4s, v18.4s, v26.4s XX\
FMUL v19.4s, v19.4s, v30.4s XX\
FMUL v20.4s, v20.4s, v26.4s XX\
FMUL v21.4s, v21.4s, v30.4s XX\
FMUL v22.4s, v22.4s, v26.4s XX\
FMUL v23.4s, v23.4s, v30.4s XX\
XX\
FADD v8.4s, v8.4s, v24.4s XX\
FADD v9.4s, v9.4s, v25.4s XX\
FADD v10.4s, v10.4s, v24.4s XX\
FADD v11.4s, v11.4s, v25.4s XX\
FADD v12.4s, v12.4s, v24.4s XX\
FADD v13.4s, v13.4s, v25.4s XX\
FADD v14.4s, v14.4s, v24.4s XX\
FADD v15.4s, v15.4s, v25.4s XX\
FADD v16.4s, v16.4s, v24.4s XX\
FADD v17.4s, v17.4s, v25.4s XX\
FADD v18.4s, v18.4s, v24.4s XX\
FADD v19.4s, v19.4s, v25.4s XX\
FADD v20.4s, v20.4s, v24.4s XX\
FADD v21.4s, v21.4s, v25.4s XX\
FADD v22.4s, v22.4s, v24.4s XX\
FADD v23.4s, v23.4s, v25.4s XX\
XX\
/* Compute c0-c7 */ XX\
XX\
ADD x9, x7, x16 XX\
CMP x0, 2 XX\
CSEL x9, x7, x9, LO XX\
XX\
ADD x10, x9, x16 XX\
CSEL x10, x9, x10, LS XX\
XX\
ADD x8, x10, x16 XX\
CMP x0, 4 XX\
CSEL x8, x10, x8, LO XX\
XX\
ADD x12, x8, x16 XX\
CSEL x12, x8, x12, LS XX\
XX\
ADD x13, x12, x16 XX\
CMP x0, 6 XX\
CSEL x13, x12, x13, LO XX\
XX\
ADD x14, x13, x16 XX\
CSEL x14, x13, x14, LS XX\
XX\
ADD x15, x14, x16 XX\
CMP x0, 8 XX\
CSEL x15, x14, x15, NE XX\
XX\
CMP x11, 8 XX\
B.NE _4_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.4s}, [x7], 16 XX\
ST1 {v9.4s}, [x7] XX\
ST1 {v10.4s}, [x9], 16 XX\
ST1 {v11.4s}, [x9] XX\
ST1 {v12.4s}, [x10], 16 XX\
ST1 {v13.4s}, [x10] XX\
ST1 {v14.4s}, [x8], 16 XX\
ST1 {v15.4s}, [x8] XX\
ST1 {v16.4s}, [x12], 16 XX\
ST1 {v17.4s}, [x12] XX\
ST1 {v18.4s}, [x13], 16 XX\
ST1 {v19.4s}, [x13] XX\
ST1 {v20.4s}, [x14], 16 XX\
ST1 {v21.4s}, [x14] XX\
ST1 {v22.4s}, [x15], 16 XX\
ST1 {v23.4s}, [x15] XX\
XX\
LDP d9, d8, [sp, -64] XX\
LDP d11, d10, [sp, -48] XX\
LDP d13, d12, [sp, -32] XX\
LDP d15, d14, [sp, -16] XX\
XX\
RET XX\
XX\
NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3 XX\
_4_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x11, 4 XX\
B.LO _5_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.4s}, [x7], 16 XX\
ST1 {v10.4s}, [x9], 16 XX\
ST1 {v12.4s}, [x10], 16 XX\
ST1 {v14.4s}, [x8], 16 XX\
ST1 {v16.4s}, [x12], 16 XX\
ST1 {v18.4s}, [x13], 16 XX\
ST1 {v20.4s}, [x14], 16 XX\
ST1 {v22.4s}, [x15], 16 XX\
XX\
SUB x11, x11, 4 XX\
XX\
MOV v8.16b, v9.16b XX\
MOV v10.16b, v11.16b XX\
MOV v12.16b, v13.16b XX\
MOV v14.16b, v15.16b XX\
MOV v16.16b, v17.16b XX\
MOV v18.16b, v19.16b XX\
MOV v20.16b, v21.16b XX\
MOV v22.16b, v23.16b XX\
XX\
_5_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x11, 2 XX\
B.LO _6_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.2s}, [x7], 8 XX\
ST1 {v10.2s}, [x9], 8 XX\
ST1 {v12.2s}, [x10], 8 XX\
ST1 {v14.2s}, [x8], 8 XX\
ST1 {v16.2s}, [x12], 8 XX\
ST1 {v18.2s}, [x13], 8 XX\
ST1 {v20.2s}, [x14], 8 XX\
ST1 {v22.2s}, [x15], 8 XX\
XX\
SUB x11, x11, 2 XX\
XX\
EXT v8.16b, v8.16b, v8.16b, 8 XX\
EXT v10.16b, v10.16b, v10.16b, 8 XX\
EXT v12.16b, v12.16b, v12.16b, 8 XX\
EXT v14.16b, v14.16b, v14.16b, 8 XX\
EXT v16.16b, v16.16b, v16.16b, 8 XX\
EXT v18.16b, v18.16b, v18.16b, 8 XX\
EXT v20.16b, v20.16b, v20.16b, 8 XX\
EXT v22.16b, v22.16b, v22.16b, 8 XX\
XX\
_6_w##W_INDEX_DTYPE_NUM_BITS##: XX\
CMP x11, 1 XX\
B.LO _7_w##W_INDEX_DTYPE_NUM_BITS XX\
XX\
ST1 {v8.s}[0], [x7] XX\
ST1 {v10.s}[0], [x9] XX\
ST1 {v12.s}[0], [x10] XX\
ST1 {v14.s}[0], [x8] XX\
ST1 {v16.s}[0], [x12] XX\
ST1 {v18.s}[0], [x13] XX\
ST1 {v20.s}[0], [x14] XX\
ST1 {v22.s}[0], [x15] XX\
XX\
_7_w##W_INDEX_DTYPE_NUM_BITS##: XX\
LDP d9, d8, [sp, -64] XX\
LDP d11, d10, [sp, -48] XX\
LDP d13, d12, [sp, -32] XX\
LDP d15, d14, [sp, -16] XX\
XX\
RET XX\
XX\
END_FUNCTION pytorch_q8gemm_dq_sparse_8x1_ukernel_8x8_packedA_w##W_INDEX_DTYPE_NUM_BITS##__aarch64_neon
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_8x8_packedA_w32__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint32_t* w_row_ptr,
# const uint32_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_8X8_PACKEDA__AARCH64_NEON(32, #4, #2, LDR)
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_8x8_packedA_w16__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint16_t* w_row_ptr,
# const uint16_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_8X8_PACKEDA__AARCH64_NEON(16, #2, #1, LDRH)
# void pytorch_q8gemm_dq_sparse_8x1_ukernel_8x8_packedA_w8__aarch64_neon(
# size_t mr,
# size_t nr,
# const uint8_t* a_packed,
# const uint8_t* packed_w,
# const uint8_t* w_row_ptr,
# const uint8_t* w_block_ids_ptr,
# const float* b,
# uint8_t* restrict c,
# size_t c_stride,
# size_t output_channel_index,
# const union pytorch_qnnp_conv_dynamic_quantization_params quantization_params[restrict static 1])
MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_8X8_PACKEDA__AARCH64_NEON(8, #1, #0, LDRB)
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
#undef NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_5
#undef NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_4
#undef NDEF_IGNORE_CODE_ALIGN_DIRECTIVES_P2ALIGN_3
#undef MAKE_PYTORCH_Q8GEMM_DQ_SPARSE_8X1_UKERNEL_8X8_PACKEDA__AARCH64_NEON
#undef XX
|
gofreelee/torch_with_smask | 7,211 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/8x4-packA-aarch64-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
# Packed A format.
# 8kx4m blocks for alls blocks given 4 rows (4m) are placed in contiguous memory.
# Original A
# --------- K ----------- -- (K + 4 - 1) / 4 --
# | | | |
# | | (M + 8 - 1)/8 |
# | | Packed | |
# M | => |-------------------|
# | | Thus Packed A has (K + 4 - 1)/4 * (M + 8 -1)/8 blocks
# | |
# |---------------------|
#
# Each 8 x 4 blocks is transposed and stored.
# Each of the (K + 4 - 1)/4 blocks for a given group of 8 m blocks
# are stored adjacent in memory
# Thus, each block:
# |----8m-----|----8m-----|
# 4k | | ..... (K + 4 - 1)/4 blocks
# |-----------|-----------|
# This locality helps in loading 8kx8m blocks of activations
# Note when M is not multiple of 8, the rest can contain arbitrary
# data in packed A as we will not be writing those out.
# This wil be taken care by just copying the appropriate valid data
# void pytorch_q8gemm_sparse_packA_ukernel_8x4__aarch32_neon(
# size_t mr,
# size_t K,
# const uint8_t* a,
# size_t a_stride,
# uint8_t* packed_a,
BEGIN_FUNCTION pytorch_q8gemm_sparse_packA_ukernel_8x4__aarch64_neon
# x2 = a0 = a pointer
# x4 = packed_a pointer
CMP x0, 2
# x5 = a1
ADD x5, x2, x3
CSEL x5, x2, x5, LO
# x6 = a2
ADD x6, x5, x3
CSEL x6, x5, x6, LS
CMP x0, 4
# x7 = a3
ADD x7, x6, x3
CSEL x7, x6, x7, LO
# x8 = a4
ADD x8, x7, x3
CSEL x8, x7, x8, LS
CMP x0, 6
# x9 = a5
ADD x9, x8, x3
CSEL x9, x8, x9, LO
# x10 = a6
ADD x10, x9, x3
CSEL x10, x9, x10, LS
CMP x0, 8
# x11 = a7
ADD x11, x10, x3
CSEL x11, x10, x11, NE
# num_k_blocks = (k + (4 - 1)) / 4
ADD x1, x1, 3
LSR x1, x1, 2
SUBS x1, x1, 2
B.LO 1f
.p2align 5
k_loop:
LD1 {v0.d}[0], [x2], 8
LD1 {v0.d}[1], [x8], 8
LD1 {v1.d}[0], [x5], 8
LD1 {v1.d}[1], [x9], 8
LD1 {v2.d}[0], [x6], 8
LD1 {v2.d}[1], [x10], 8
LD1 {v3.d}[0], [x7], 8
LD1 {v3.d}[1], [x11], 8
# Now we have 8x8 block of values that we will tranpose
# A matrix
# ------------------------
# | |
# |a0-----a3a4-----a7....|
# |b0 B00 b3b4 B01 b7....|
# |c0 c3c4 c7....|
# |d0-----d3d4-----d7....|
# |e0-----e3e4-----e7....|
# |f0 B10 f3f4 B11 f7....|
# |g0 g3g4 g7....|
# |h0-----h3h4-----h7....|
# | |
# | |
# ------------------------
# {v0.2d[1], v0.2d[0]} = B00[0]+ B01[0] + B10[0] + B11[0]
# {v1.2d[1], v1.2d[0]} = B00[1]+ B01[1] + B10[1] + B11[1]
# {v2.2d[1], v2.2d[0]} = B00[2]+ B01[2] + B10[2] + B11[2]
# {v3.2d[1], v3.2d[0]} = B00[3]+ B01[3] + B10[3] + B11[3]
# v0 = e7 e6 e5 e4 e3 e2 e1 e0; a7 a6 a5 a4 a3 a2 a1 a0
# v1 = f7 f6 f5 f4 f3 f2 f1 f0; b7 b6 b5 b4 b3 b2 b1 b0
# v2 = g7 g6 g5 g4 g3 g2 g1 g0; c7 c6 c5 c4 c3 c2 c1 c0
# v3 = h7 h6 h5 h4 h3 h2 h1 h0; d7 d6 d5 d4 d3 d2 d1 d0
# Sequence:
# TRN1 v4.16b, v0.16b, v1.16b
# TRN2 v5.16b, v0.16b, v1.16b
# TRN1 v6.16b, v2.16b, v3.16b
# TRN2 v7.16b, v2.16b, v3.16b
# Now we have
# v4 = f6 e6 f4 e4 f2 e2 f0 e0; b6 a6 b4 a4 b2 a2 b0 a0
# v5 = f7 e7 f5 e5 f3 e3 f1 e1; b7 a7 b5 a5 b3 a3 b1 a1
# v6 = h6 g6 h4 g4 h2 g2 h0 g0; d6 c6 d4 c4 d2 c2 d0 c0
# v7 = h7 g7 h5 g5 h3 g3 h1 g1; d7 c7 d5 c5 d3 c3 d1 c1
# TRN1 v0.8h, v4.8h, v6.8h
# TRN2 v2.8h, v4.8h, v6.8h
# TRN1 v1.8h, v5.8h, v7.8h
# TRN2 v3.8h, v5.8h, v7.8h
# v0 = h4 g4 f4 e4 h0 g0 f0 e0; d4 c4 b4 a4 d0 c0 b0 a0
# v1 = h5 g5 f5 e5 h1 g1 f1 e1; d5 c5 b5 a5 d1 c1 b1 a1
# v2 = h6 g6 f6 e6 h2 g2 f2 e2; d6 c6 b6 a6 d2 c2 b2 a2
# v3 = h7 g7 f7 e7 h3 g3 f3 e3; d7 c7 b7 a7 d3 c3 b3 a3
# UZP1 v4.4s, v0.4s, v1.4s
# UZP2 v6.4s, v0.4s, v1.4s
# UZP1 v5.4s, v2.4s, v3.4s
# UZP2 v7.4s, v2.4s, v3.4s
# v4 = h1 g1 f1 e1 d1 c1 b1 a1; h0 g0 f0 e0 d0 c0 b0 a0
# v5 = h3 g3 f3 e3 d3 c3 b3 a3; h2 g2 f2 e2 d2 c2 b2 a2
# v6 = h5 g5 f5 e5 d5 c5 b5 a5; h4 g4 f4 e4 d4 c4 b4 a4
# v7 = h7 g7 f7 e7 d7 c7 b7 a7; h6 g6 f6 e6 d6 c6 b6 a6
# Thus 2 8x4 blocks are transposed.
TRN1 v4.16b, v0.16b, v1.16b
TRN2 v5.16b, v0.16b, v1.16b
TRN1 v6.16b, v2.16b, v3.16b
TRN2 v7.16b, v2.16b, v3.16b
TRN1 v0.8h, v4.8h, v6.8h
TRN2 v2.8h, v4.8h, v6.8h
TRN1 v1.8h, v5.8h, v7.8h
TRN2 v3.8h, v5.8h, v7.8h
UZP1 v4.4s, v0.4s, v1.4s
UZP2 v6.4s, v0.4s, v1.4s
UZP1 v5.4s, v2.4s, v3.4s
UZP2 v7.4s, v2.4s, v3.4s
ST1 {v4.16b}, [x4], 16
ST1 {v5.16b}, [x4], 16
ST1 {v6.16b}, [x4], 16
ST1 {v7.16b}, [x4], 16
SUBS x1, x1, 2
B.HS k_loop
1:
CMP x1, -2
B.EQ 2f
LD1 {v0.s}[0], [x2]
LD1 {v0.s}[1], [x8]
LD1 {v1.s}[0], [x5]
LD1 {v1.s}[1], [x9]
LD1 {v2.s}[0], [x6]
LD1 {v2.s}[1], [x10]
LD1 {v3.s}[0], [x7]
LD1 {v3.s}[1], [x11]
# Now we have 8x4 block of values that we will tranpose
# A matrix
# ----------------------------
# | |
# | a0-----a3|
# | b0 B00 b3|
# | last block c0 c3|
# | d0-----d3|
# | e0-----e3|
# | f0 B01 f3|
# | g0 g3|
# | h0-----h3|
# | |
# | |
# ---------------------------
# v0 = -; e3 e2 e1 e0 a3 a2 a1 a0
# v1 = -; f3 f2 f1 f0 b3 b2 b1 b0
# v2 = -; g3 g2 g1 g0 c3 c2 c1 c0
# v3 = -; h3 h2 h1 h0 d3 d2 d1 d0
# Sequence:
# TRN1 v4.16b, v0.16b, v1.16b
# TRN2 v5.16b, v0.16b, v1.16b
# TRN1 v6.16b, v2.16b, v3.16b
# TRN2 v7.16b, v2.16b, v3.16b
# Now we have
# v4 = -;f2 e2 f0 e0 b2 a2 b0 a0
# v5 = -;f3 e3 f1 e1 b3 a3 b1 a1
# v6 = -;h2 g2 h0 g0 d2 c2 d0 c0
# v7 = -;h3 g3 h1 g1 d3 c3 d1 c1
# TRN1 v0.8h, v4.8h, v6.8h
# TRN2 v2.8h, v4.8h, v6.8h
# TRN1 v1.8h, v5.8h, v7.8h
# TRN2 v3.8h, v5.8h, v7.8h
# v0 = -;h0 g0 f0 e0 d0 c0 b0 a0
# v1 = -;h1 g1 f1 e1 d1 c1 b1 a1
# v2 = -;h2 g2 f2 e2 d2 c2 b2 a2
# v3 = -;h3 g3 f3 e3 d3 c3 b3 a3
# Thus 1 8x4 blocks are transposed.
TRN1 v4.16b, v0.16b, v1.16b
TRN2 v5.16b, v0.16b, v1.16b
TRN1 v6.16b, v2.16b, v3.16b
TRN2 v7.16b, v2.16b, v3.16b
TRN1 v0.8h, v4.8h, v6.8h
TRN2 v2.8h, v4.8h, v6.8h
TRN1 v1.8h, v5.8h, v7.8h
TRN2 v3.8h, v5.8h, v7.8h
ST1 {v0.8b}, [x4], 8
ST1 {v1.8b}, [x4], 8
ST1 {v2.8b}, [x4], 8
ST1 {v3.8b}, [x4]
.p2align 4
2:
RET
END_FUNCTION pytorch_q8gemm_sparse_packA_ukernel_8x4__aarch64_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 7,334 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/8x4-packA-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
# r0 mr
# r1 k
# r2 a
# r3 a_stride
.syntax unified
# Args passed via stack.
# TOS
# |----------------|
# |packed_a | 0
# |----------------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r9 and d8-d15 on stack
# |----------------|
# |r4 - r11 | 0
# |packed_a | 32
# |----------------|
#
# Packed A format.
# 8kx4m blocks for alls blocks given 4 rows (4m) are placed in contiguous memory.
# Original A
# --------- K ----------- -- (K + 4 - 1) / 4 --
# | | | |
# | | (M + 8 - 1)/8 |
# | | Packed | |
# M | => |-------------------|
# | | Thus Packed A has (K + 4 - 1)/4 * (M + 8 -1)/8 blocks
# | |
# |---------------------|
#
# Each 8 x 4 blocks is transposed and stored.
# Each of the (K + 4 - 1)/4 blocks for a given group of 8 m blocks
# are stored adjacent in memory
# Thus, each block:
# |----8m-----|----8m-----|
# 4k | | ..... (K + 4 - 1)/4 blocks
# |-----------|-----------|
# This locality helps in loading 8kx8m blocks of activations
# Note when M is not multiple of 8, the rest can contain arbitrary
# data in packed A as we will not be writing those out.
# This wil be taken care by just copying the appropriate valid data
# void pytorch_q8gemm_sparse_packA_ukernel_8x4__aarch32_neon(
# size_t mr,
# size_t K,
# const uint8_t* a,
# size_t a_stride,
# uint8_t* packed_a,
BEGIN_FUNCTION pytorch_q8gemm_sparse_packA_ukernel_8x4__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
PUSH {r4, r5, r6, r7, r8, r9, r10, r11}
# r4 = a0 = a pointer
MOV r4, r2
# r2 = packed_a pointer
LDR r2, [sp, 32]
CMP r0, 2
# r5 = a1
ADD r5, r4, r3
MOVLO r5, r4
# r6 = a2
ADD r6, r5, r3
MOVLS r6, r5
CMP r0, 4
# r7 = a3
ADD r7, r6, r3
MOVLO r7, r6
# r8 = a4
ADD r8, r7, r3
MOVLS r8, r7
CMP r0, 6
# r9 = a5
ADD r9, r8, r3
MOVLO r9, r8
# r10 = a6
ADD r10, r9, r3
MOVLS r10, r9
CMP r0, 8
# r11 = a7
ADD r11, r10, r3
MOVNE r11, r10
# num_k_blocks = (k + (4 - 1)) / 4
ADD r1, r1, 3
LSR r1, r1, 2
SUBS r1, r1, 2
BLO 1f
.p2align 5
k_loop:
VLD1.8 {d0}, [r4]!
VLD1.8 {d1}, [r5]!
VLD1.8 {d2}, [r6]!
VLD1.8 {d3}, [r7]!
VLD1.8 {d4}, [r8]!
VLD1.8 {d5}, [r9]!
VLD1.8 {d6}, [r10]!
VLD1.8 {d7}, [r11]!
# Now we have 8x8 block of values that we will tranpose
# A matrix
# --------------------------------
# | |
# |a0-----a3........a4-----a7....|
# |b0 B00 b3........b4 B01 b7....|
# |c0 c3........c4 c7....|
# |d0-----d3........d4-----d7....|
# |e0-----e3........e4-----e7....|
# |f0 B10 f3........f4 B11 f7....|
# |g0 g3........g4 g7....|
# |h0-----h3........h4-----h7....|
# | |
# | |
# -------------------------------
# {va01, va23} = B00 + B01 = 2 uint8x16_t
# {va34, va56} = B10 + B11 = 2 uint8x16_t
# Sequence:
# VTRN.8 d0, d1 // low(va01), high(va01)
# VTRN.8 d2, d3 // low(va23), high(va23)
# VTRN.16 q0, q1 // va01, va23
# Now we have
# d0 = d4, c4, b4, a4 : d0, c0, b0, a0
# d1 = d5, c5, b5, a5 : d1, c1, b1, a1
# d2 = d6, c6, b6, a6 : d2, c2, b2, a2
# d3 = d7, c7, b7, a7 : d3, c3, b3, a3
# Thus 2 4x4 blocks are transposed.
# Now we will transpose 2 more sets of 4x4 blocks
# Sequence:
# VTRN.8 d4, d5 // low(va45), high(va45)
# VTRN.8 d6, d7 // low(va67), high(va67)
# VTRN.16 q2, q3 // va45, va67
# Now we have
# d4 = h4, g4, f4, e4 : h0, g0, f0, e0
# d5 = h5, g5, f5, e5 : h1, g1, f1, e1
# d6 = h6, g6, f6, e6 : h2, g2, f2, e2
# d7 = h7, g7, f7, e7 : h3, g3, f3, e3
# Now we have all 4 B00, B01, B10, B11
# transposed.
# We can now combine them to create one
# 8x8 transposed block.
# Sequence:
# VTRN.32 q0, q2
# VTRN.32 q1, q3
# d0 = h0, g0, f0, e0 : d0, c0, b0, a0
# d1 = h1, g1, f1, e1 : d1, c1, b1, a1
# d4 = h4, g4, f4, e4 : d4, c4, b4, a4
# d5 = h5, g5, f5, e5 : d5, c5, b5, a5
# d2 = h2, g2, f2, e2 : d2, c2, b2, a2
# d3 = h3, g3, f3, e3 : d3, c3, b3, a3
# d6 = h6, g6, f6, e6 : d6, c6, b6, a6
# d7 = h7, g7, f7, e7 : d7, c7, b7, a7
VTRN.8 d0, d1
VTRN.8 d2, d3
VTRN.16 q0, q1
VTRN.8 d4, d5
VTRN.8 d6, d7
VTRN.16 q2, q3
VTRN.32 q0, q2
VTRN.32 q1, q3
# Now store the tranposed values
# d0, d1, d2, d3
# then d4, d5, d6, d7 contiguously
VST1.8 {q0}, [r2]!
VST1.8 {q1}, [r2]!
VST1.8 {q2}, [r2]!
VST1.8 {q3}, [r2]!
SUBS r1, r1, 2
BHS k_loop
1:
CMP r1, -2
BEQ 2f
VLD1.32 {d0[]}, [r4]
VLD1.32 {d1[]}, [r8]
VLD1.32 {d2[]}, [r5]
VLD1.32 {d3[]}, [r9]
VLD1.32 {d4[]}, [r6]
VLD1.32 {d5[]}, [r10]
VLD1.32 {d6[]}, [r7]
VLD1.32 {d7[]}, [r11]
# Now we have 4x8 block of values that we will tranpose
# _d{0-3} are arm neon vector registers
# va04 = _d0 = a0 a1 a2 a3 e0 e1 e2 e3
# va15 = _d1 = b0 b1 b2 b3 f0 f1 f2 f3
# va26 = _d2 = c0 c1 c2 c3 g0 g1 g2 g3
# va37 = _d3 = d0 d1 d2 d3 h0 h1 h2 h3
# A matrix
# ----------------------------
# | |
# | a0-----a3|
# | b0 B00 b3|
# | last block c0 c3|
# | d0-----d3|
# | e0-----e3|
# | f0 B01 f3|
# | g0 g3|
# | h0-----h3|
# | |
# | |
# ---------------------------
# Sequence:
# VTRN.8 d0, d1 // va04, va15
# VTRN.8 d2, d3 // va26, va37
# Now we have
# d0 = f2, e2, f0, e0 : b2, a2, b0, a0
# d1 = f3, e3, f1, e1 : b3, a3, b1, a1
# d2 = h2, g2, h0, g0 : d2, c2, d0, c0
# d3 = h3, g3, h1, g1 : d3, c3, d1, c1
# Sequence:
# VTRN.16 d0, d2
# VTRN.16 d1, d3
# Now we have
# d0 = h0, g0, f0, e0 : d0, c0, b0, a0
# d1 = h1, g1, f1, e1 : d1, c1, b1, a1
# d2 = h2, g2, f2, e2 : d2, c2, b2, a2
# d3 = h3, g3, f3, e3 : d3, c3, b3, a3
VEXT.8 d0, d0, d1, #4
VEXT.8 d1, d2, d3, #4
VEXT.8 d2, d4, d5, #4
VEXT.8 d3, d6, d7, #4
VTRN.8 d0, d1
VTRN.8 d2, d3
VTRN.16 d0, d2
VTRN.16 d1, d3
# Now store the tranposed values
# d0, d1, d2, d3
# then d4, d5, d6, d7 contiguously
VST1.8 {q0}, [r2]!
VST1.8 {q1}, [r2]
.p2align 4
2:
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
END_FUNCTION pytorch_q8gemm_sparse_packA_ukernel_8x4__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 6,228 | aten/src/ATen/native/quantized/cpu/qnnpack/src/q8gemm_sparse/4x4-packA-aarch32-neon.S | /*
* Copyright (c) Facebook, Inc. and its affiliates.
* All rights reserved.
*
* This source code is licensed under the BSD-style license found in the
* LICENSE file in the root directory of this source tree.
*/
#include <qnnpack/assembly.h>
#include <requantization/runtime-assembly.h>
# r0 mr
# r1 k
# r2 a
# r3 a_stride
.syntax unified
# Args passed via stack.
# TOS
# |----------------|
# |packed_a | 0
# |----------------|
#
# After loading w pointer in ip reg.
# And after pushing r4-r9 and d8-d15 on stack
# |----------------|
# |r4 - r11 | 0
# |packed_a | 32
# |----------------|
#
# Packed A format.
# 4kx4m blocks for alls blocks given 4 rows (4m) are placed in contiguous memory.
# Original A
# --------- K ----------- -- (K + 4 - 1) / 4 --
# | | | |
# | | (M + 4 - 1)/4 |
# | | Packed | |
# M | => |-------------------|
# | | Thus Packed A has (K + 4 - 1)/4 * (M + 4 -1)/4 blocks
# | |
# |---------------------|
#
# Each 4 x 4 blocks is transposed and stored.
# Each of the (K + 4 - 1)/4 blocks for a given group of 4 m blocks
# are stored adjacent in memory
# Thus, each block:
# |----4m-----|----4m-----|
# 4k | | ..... (K + 4 - 1)/4 blocks
# |-----------|-----------|
# This locality helps in loading 8kx4m blocks of activations
# Note when M is not multiple of 4, the rest can contain arbitrary
# data in packed A as we will not be writing those out.
# This wil be taken care by just copying the appropriate valid data
# Also note that this packing is same as taking for 4x1 pattern.
# This is because all the adjacent k's are laid next to each other
# in both 4x4 as well as 4x1 blocking (mrxkr)
# So this packing kernel can be used by compute kernel that assumes
# 8x1 sparsity pattern and has register blocking of 4x8
# void pytorch_q8gemm_sparse_packA_ukernel_4x4__aarch32_neon(
# size_t mr,
# size_t K,
# const uint8_t* a,
# size_t a_stride,
# uint8_t* packed_a,
BEGIN_FUNCTION pytorch_q8gemm_sparse_packA_ukernel_4x4__aarch32_neon
.arm
#ifndef __APPLE__
.arch armv7-a
.fpu neon
#endif
PUSH {r4, r5, r6, r7, r8, r9, r10, r11}
# r4 = a0 = a pointer
MOV r4, r2
# r2 = packed_a pointer
LDR r2, [sp, 32]
CMP r0, 2
# r5 = a1
ADD r5, r4, r3
MOVLO r5, r4
# r6 = a2
ADD r6, r5, r3
MOVLS r6, r5
CMP r0, 4
# r7 = a3
ADD r7, r6, r3
MOVNE r7, r6
# num_k_blocks = (k + (4 - 1)) / 4
ADD r1, r1, 3
LSR r1, r1, 2
SUBS r1, r1, 2
BLO 1f
.p2align 5
k_loop:
VLD1.8 {d0}, [r4]!
VLD1.8 {d1}, [r5]!
VLD1.8 {d2}, [r6]!
VLD1.8 {d3}, [r7]!
# Now we have 4x8 block of values that we will tranpose
# A matrix
# --------------------------------
# | |
# |a0-----a3 a4-----a7....|
# |b0 B00 b3 b4 B01 b7....|
# |c0 c3 c4 c7....|
# |d0-----d3 d4-----d7....|
# | |
# | |
# -------------------------------
# {va01, va23} = B00 + B01 = 2 uint8x16_t
# Sequence:
# VTRN.8 d0, d1 // low(va01), high(va01)
# VTRN.8 d2, d3 // low(va23), high(va23)
# VTRN.16 q0, q1 // va01, va23
# Now we have
# d0 = d4, c4, b4, a4 : d0, c0, b0, a0
# d1 = d5, c5, b5, a5 : d1, c1, b1, a1
# d2 = d6, c6, b6, a6 : d2, c2, b2, a2
# d3 = d7, c7, b7, a7 : d3, c3, b3, a3
# Thus 2 4x4 blocks are transposed.
# Now we have all 2 B00, B01 transposed.
VTRN.8 d0, d1
VTRN.8 d2, d3
VTRN.16 q0, q1
# Now VTRN.32 d0, d1
# Now VTRN.32 d2, d3
# Thus we have
# d0 = d1, c1, b1, a1 : d0, c0, b0, a0
# d1 = d5, c5, b5, a5 : d4, c4, b4, a4
# d2 = d3, c3, b3, a3 : d2, c2, b2, a2
# d3 = d7, c7, b7, a7 : d6, c6, b6, a6
# Then we can do
# VSWP d1, d2
# d0 = d1, c1, b1, a1 : d0, c0, b0, a0
# d1 = d3, c3, b3, a3 : d2, c2, b2, a2
# d2 = d5, c5, b5, a5 : d4, c4, b4, a4
# d3 = d7, c7, b7, a7 : d6, c6, b6, a6
# Now we can store q0 contiguously followed
VTRN.32 d0, d1
VTRN.32 d2, d3
VSWP d1, d2
# Now store the tranposed values
# d0, d1, d2, d3
VST1.8 {q0}, [r2]!
VST1.8 {q1}, [r2]!
SUBS r1, r1, 2
BHS k_loop
1:
CMP r1, -2
BEQ 2f
VLD1.32 {d0[]}, [r4]
VLD1.32 {d1[]}, [r5]
VLD1.32 {d2[]}, [r6]
VLD1.32 {d3[]}, [r7]
# Now we have 4x8 block of values that we will tranpose
# _d{0-3} are arm neon vector registers
# va0 = _d0 = a0 a1 a2 a3
# va1 = _d1 = b0 b1 b2 b3
# va2 = _d2 = c0 c1 c2 c3
# va3 = _d3 = d0 d1 d2 d3
# A matrix
# ----------------------------
# | |
# | a0-----a3|
# | b0 B00 b3|
# | last block c0 c3|
# | d0-----d3|
# | |
# | |
# ---------------------------
# Sequence:
# VTRN.8 d0, d1 // va0, va1
# VTRN.8 d2, d3 // va2, va3
# Now we have
# d0 = b2, a2, b0, a0
# d1 = b3, a3, b1, a1
# d2 = d2, c2, d0, c0
# d3 = d3, c3, d1, c1
# Sequence:
# VTRN.16 d0, d2
# VTRN.16 d1, d3
# Now we have
# d0 = d0, c0, b0, a0
# d1 = d1, c1, b1, a1
# d2 = d2, c2, b2, a2
# d3 = d3, c3, b3, a3
VTRN.8 d0, d1
VTRN.8 d2, d3
VTRN.16 d0, d2
VTRN.16 d1, d3
# Since upper half of d0 just contains duplicate values
# We dont want to store those
# So let's combine upper half of d0 to the lower part of d0
# And lower half of d1 to upper half of d0
# Same for d2, d3
VEXT.8 d0, d0, d1, #4
VEXT.8 d1, d2, d3, #4
# Now store the tranposed values
# d0, d1, d2, d3
VST1.8 {q0}, [r2]
.p2align 4
2:
POP {r4, r5, r6, r7, r8, r9, r10, r11}
BX lr
END_FUNCTION pytorch_q8gemm_sparse_packA_ukernel_4x4__aarch32_neon
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
gofreelee/torch_with_smask | 162 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm/4x8c2-xzp-aarch32-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <q8gemm/4x8c2-xzp-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 167 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm/8x8-dq-aarch64-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__aarch64__)
#include <q8gemm/8x8-dq-aarch64-neon.S>
#endif /* defined(__aarch64__) */
|
gofreelee/torch_with_smask | 159 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm/4x8-dq-aarch32-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <q8gemm/4x8-dq-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 156 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm/4x8-aarch32-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <q8gemm/4x8-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 164 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm/8x8-aarch64-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__aarch64__)
#include <q8gemm/8x8-aarch64-neon.S>
#endif /* defined(__aarch64__) */
|
gofreelee/torch_with_smask | 160 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8dwconv/up8x9-aarch32-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <q8dwconv/up8x9-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 172 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8dwconv/up8x9-aarch32-neon-per-channel.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <q8dwconv/up8x9-aarch32-neon-per-channel.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 156 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8conv/4x8-aarch32-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <q8conv/4x8-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 164 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8conv/8x8-aarch64-neon.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__aarch64__)
#include <q8conv/8x8-aarch64-neon.S>
#endif /* defined(__aarch64__) */
|
gofreelee/torch_with_smask | 164 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/hgemm/8x8-aarch32-neonfp16arith.S | /* Auto-generated by generate-wrappers.py script. Do not modify */
#if defined(__arm__)
#include <hgemm/8x8-aarch32-neonfp16arith.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 110 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/4x8c8x1-dq-packedA-aarch32-neon.S | #if defined(__arm__)
#include <q8gemm_sparse/4x8c8x1-dq-packedA-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 110 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/4x8c1x4-dq-packedA-aarch32-neon.S | #if defined(__arm__)
#include <q8gemm_sparse/4x8c1x4-dq-packedA-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 114 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/8x8c1x4-dq-packedA-aarch64-neon.S | #if defined(__aarch64__)
#include <q8gemm_sparse/8x8c1x4-dq-packedA-aarch64-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 114 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/8x8c8x1-dq-packedA-aarch64-neon.S | #if defined(__aarch64__)
#include <q8gemm_sparse/8x8c8x1-dq-packedA-aarch64-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 105 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/8x4-packA-aarch64-neon.S | #if defined(__aarch64__)
#include <q8gemm_sparse/8x4-packA-aarch64-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 101 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/8x4-packA-aarch32-neon.S | #if defined(__arm__)
#include <q8gemm_sparse/8x4-packA-aarch32-neon.S>
#endif /* defined(__arm__) */
|
gofreelee/torch_with_smask | 101 | aten/src/ATen/native/quantized/cpu/qnnpack/wrappers/q8gemm_sparse/4x4-packA-aarch32-neon.S | #if defined(__arm__)
#include <q8gemm_sparse/4x4-packA-aarch32-neon.S>
#endif /* defined(__arm__) */
|
GroxyAI/groxy | 1,538 | kernel_loader/src/test_elf.S | # Copyright 2022 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
# Build instructions:
#
# For a 64-bit kernel:
# x86_64-linux-gnu-as test_elf.S -o test_elf64.o
# x86_64-linux-gnu-ld test_elf64.o -o test_elf64.bin -T test_elf.ld
#
# For a 32-bit kernel:
# i686-linux-gnu-as test_elf.S -o test_elf32.o
# i686-linux-gnu-ld test_elf32.o -o test_elf32.bin -T test_elf.ld
.intel_syntax noprefix
.section .rodata
hello_world:
.string "Hello world!\n"
.set hello_size, .-hello_world
.text
.globl _start
_start:
lea esi, [hello_world] # esi -> message string
mov ecx, hello_size # ecx = length of message
mov dx, 0x3F8 # dx = COM1 port
.print_loop:
# Wait for the transmit buffer to be empty by polling the line status.
add dx, 5 # dx = line status register
.wait_empty:
in al, dx # read line status
test al, 0x20 # check buffer empty flag
jz .wait_empty # keep waiting if flag is not set
.wait_done:
sub dx, 5 # dx = data register
# Load a byte of the message and send it to the serial port.
lodsb # load message byte from RSI to AL
out dx, al # send byte to serial port
loop .print_loop # repeat hello_size times
.done:
int3 # cause vcpu to exit
|
gsspdev/rust | 11,809 | library/std/src/sys/pal/sgx/abi/entry.S | /* This symbol is used at runtime to figure out the virtual address that the */
/* enclave is loaded at. */
.section absolute
.global IMAGE_BASE
IMAGE_BASE:
.section ".note.x86_64-fortanix-unknown-sgx", "", @note
.align 4
.long 1f - 0f /* name length (not including padding) */
.long 3f - 2f /* desc length (not including padding) */
.long 1 /* type = NT_VERSION */
0: .asciz "toolchain-version" /* name */
1: .align 4
2: .long 1 /* desc - toolchain version number, 32-bit LE */
3: .align 4
.section .rodata
/* The XSAVE area needs to be a large chunk of readable memory, but since we are */
/* going to restore everything to its initial state (XSTATE_BV=0), only certain */
/* parts need to have a defined value. In particular: */
/* */
/* * MXCSR in the legacy area. This register is always restored if RFBM[1] or */
/* RFBM[2] is set, regardless of the value of XSTATE_BV */
/* * XSAVE header */
.align 64
.Lxsave_clear:
.org .+24
.Lxsave_mxcsr:
.short 0x1fbf
/* We can store a bunch of data in the gap between MXCSR and the XSAVE header */
/* The following symbols point at read-only data that will be filled in by the */
/* post-linker. */
/* When using this macro, don't forget to adjust the linker version script! */
.macro globvar name:req size:req
.global \name
.protected \name
.align \size
.size \name , \size
\name :
.org .+\size
.endm
/* The base address (relative to enclave start) of the heap area */
globvar HEAP_BASE 8
/* The heap size in bytes */
globvar HEAP_SIZE 8
/* Value of the RELA entry in the dynamic table */
globvar RELA 8
/* Value of the RELACOUNT entry in the dynamic table */
globvar RELACOUNT 8
/* The enclave size in bytes */
globvar ENCLAVE_SIZE 8
/* The base address (relative to enclave start) of the enclave configuration area */
globvar CFGDATA_BASE 8
/* Non-zero if debugging is enabled, zero otherwise */
globvar DEBUG 1
/* The base address (relative to enclave start) of the enclave text section */
globvar TEXT_BASE 8
/* The size in bytes of enclave text section */
globvar TEXT_SIZE 8
/* The base address (relative to enclave start) of the enclave .eh_frame_hdr section */
globvar EH_FRM_HDR_OFFSET 8
/* The size in bytes of enclave .eh_frame_hdr section */
globvar EH_FRM_HDR_LEN 8
/* The base address (relative to enclave start) of the enclave .eh_frame section */
globvar EH_FRM_OFFSET 8
/* The size in bytes of enclave .eh_frame section */
globvar EH_FRM_LEN 8
.org .Lxsave_clear+512
.Lxsave_header:
.int 0, 0 /* XSTATE_BV */
.int 0, 0 /* XCOMP_BV */
.org .+48 /* reserved bits */
.data
.Laborted:
.byte 0
/* TCS local storage section */
.equ tcsls_tos, 0x00 /* initialized by loader to *offset* from image base to TOS */
.equ tcsls_flags, 0x08 /* initialized by loader */
.equ tcsls_flag_secondary, 0 /* initialized by loader; 0 = standard TCS, 1 = secondary TCS */
.equ tcsls_flag_init_once, 1 /* initialized by loader to 0 */
/* 14 unused bits */
.equ tcsls_user_fcw, 0x0a
.equ tcsls_user_mxcsr, 0x0c
.equ tcsls_last_rsp, 0x10 /* initialized by loader to 0 */
.equ tcsls_panic_last_rsp, 0x18 /* initialized by loader to 0 */
.equ tcsls_debug_panic_buf_ptr, 0x20 /* initialized by loader to 0 */
.equ tcsls_user_rsp, 0x28
.equ tcsls_user_retip, 0x30
.equ tcsls_user_rbp, 0x38
.equ tcsls_user_r12, 0x40
.equ tcsls_user_r13, 0x48
.equ tcsls_user_r14, 0x50
.equ tcsls_user_r15, 0x58
.equ tcsls_tls_ptr, 0x60
.equ tcsls_tcs_addr, 0x68
.macro load_tcsls_flag_secondary_bool reg:req comments:vararg
.ifne tcsls_flag_secondary /* to convert to a bool, must be the first bit */
.abort
.endif
mov $(1<<tcsls_flag_secondary),%e\reg
and %gs:tcsls_flags,%\reg
.endm
/* We place the ELF entry point in a separate section so it can be removed by
elf2sgxs */
.section .text_no_sgx, "ax"
.Lelf_entry_error_msg:
.ascii "Error: This file is an SGX enclave which cannot be executed as a standard Linux binary.\nSee the installation guide at https://edp.fortanix.com/docs/installation/guide/ on how to use 'cargo run' or follow the steps at https://edp.fortanix.com/docs/tasks/deployment/ for manual deployment.\n"
.Lelf_entry_error_msg_end:
.global elf_entry
.type elf_entry,function
elf_entry:
/* print error message */
movq $2,%rdi /* write to stderr (fd 2) */
lea .Lelf_entry_error_msg(%rip),%rsi
movq $.Lelf_entry_error_msg_end-.Lelf_entry_error_msg,%rdx
.Lelf_entry_call:
movq $1,%rax /* write() syscall */
syscall
test %rax,%rax
jle .Lelf_exit /* exit on error */
add %rax,%rsi
sub %rax,%rdx /* all chars written? */
jnz .Lelf_entry_call
.Lelf_exit:
movq $60,%rax /* exit() syscall */
movq $1,%rdi /* exit code 1 */
syscall
ud2 /* should not be reached */
/* end elf_entry */
/* This code needs to be called *after* the enclave stack has been setup. */
/* There are 3 places where this needs to happen, so this is put in a macro. */
.macro entry_sanitize_final
/* Sanitize rflags received from user */
/* - DF flag: x86-64 ABI requires DF to be unset at function entry/exit */
/* - AC flag: AEX on misaligned memory accesses leaks side channel info */
pushfq
andq $~0x40400, (%rsp)
popfq
/* check for abort */
bt $0,.Laborted(%rip)
jc .Lreentry_panic
.endm
.text
.global sgx_entry
.type sgx_entry,function
sgx_entry:
/* save user registers */
mov %rcx,%gs:tcsls_user_retip
mov %rsp,%gs:tcsls_user_rsp
mov %rbp,%gs:tcsls_user_rbp
mov %r12,%gs:tcsls_user_r12
mov %r13,%gs:tcsls_user_r13
mov %r14,%gs:tcsls_user_r14
mov %r15,%gs:tcsls_user_r15
mov %rbx,%gs:tcsls_tcs_addr
stmxcsr %gs:tcsls_user_mxcsr
fnstcw %gs:tcsls_user_fcw
/* check for debug buffer pointer */
testb $0xff,DEBUG(%rip)
jz .Lskip_debug_init
mov %r10,%gs:tcsls_debug_panic_buf_ptr
.Lskip_debug_init:
/* reset cpu state */
mov %rdx, %r10
mov $-1, %rax
mov $-1, %rdx
xrstor .Lxsave_clear(%rip)
lfence
mov %r10, %rdx
/* check if returning from usercall */
mov %gs:tcsls_last_rsp,%r11
test %r11,%r11
jnz .Lusercall_ret
/* setup stack */
mov %gs:tcsls_tos,%rsp /* initially, RSP is not set to the correct value */
/* here. This is fixed below under "adjust stack". */
/* check for thread init */
bts $tcsls_flag_init_once,%gs:tcsls_flags
jc .Lskip_init
/* adjust stack */
lea IMAGE_BASE(%rip),%rax
add %rax,%rsp
mov %rsp,%gs:tcsls_tos
entry_sanitize_final
/* call tcs_init */
/* store caller-saved registers in callee-saved registers */
mov %rdi,%rbx
mov %rsi,%r12
mov %rdx,%r13
mov %r8,%r14
mov %r9,%r15
load_tcsls_flag_secondary_bool di /* RDI = tcs_init() argument: secondary: bool */
call tcs_init
/* reload caller-saved registers */
mov %rbx,%rdi
mov %r12,%rsi
mov %r13,%rdx
mov %r14,%r8
mov %r15,%r9
jmp .Lafter_init
.Lskip_init:
entry_sanitize_final
.Lafter_init:
/* call into main entry point */
load_tcsls_flag_secondary_bool cx /* RCX = entry() argument: secondary: bool */
call entry /* RDI, RSI, RDX, R8, R9 passed in from userspace */
mov %rax,%rsi /* RSI = return value */
/* NOP: mov %rdx,%rdx */ /* RDX = return value */
xor %rdi,%rdi /* RDI = normal exit */
.Lexit:
/* clear general purpose register state */
/* RAX overwritten by ENCLU */
/* RBX set later */
/* RCX overwritten by ENCLU */
/* RDX contains return value */
/* RSP set later */
/* RBP set later */
/* RDI contains exit mode */
/* RSI contains return value */
xor %r8,%r8
xor %r9,%r9
xor %r10,%r10
xor %r11,%r11
/* R12 ~ R15 set by sgx_exit */
.Lsgx_exit:
/* clear extended register state */
mov %rdx, %rcx /* save RDX */
mov $-1, %rax
mov %rax, %rdx
xrstor .Lxsave_clear(%rip)
mov %rcx, %rdx /* restore RDX */
/* clear flags */
pushq $0
popfq
/* restore user registers */
mov %gs:tcsls_user_r12,%r12
mov %gs:tcsls_user_r13,%r13
mov %gs:tcsls_user_r14,%r14
mov %gs:tcsls_user_r15,%r15
mov %gs:tcsls_user_retip,%rbx
mov %gs:tcsls_user_rsp,%rsp
mov %gs:tcsls_user_rbp,%rbp
fldcw %gs:tcsls_user_fcw
ldmxcsr %gs:tcsls_user_mxcsr
/* exit enclave */
mov $0x4,%eax /* EEXIT */
enclu
/* end sgx_entry */
.Lreentry_panic:
orq $8,%rsp
jmp abort_reentry
/* This *MUST* be called with 6 parameters, otherwise register information */
/* might leak! */
.global usercall
usercall:
test %rcx,%rcx /* check `abort` function argument */
jnz .Lusercall_abort /* abort is set, jump to abort code (unlikely forward conditional) */
jmp .Lusercall_save_state /* non-aborting usercall */
.Lusercall_abort:
/* set aborted bit */
movb $1,.Laborted(%rip)
/* save registers in DEBUG mode, so that debugger can reconstruct the stack */
testb $0xff,DEBUG(%rip)
jz .Lusercall_noreturn
.Lusercall_save_state:
/* save callee-saved state */
push %r15
push %r14
push %r13
push %r12
push %rbp
push %rbx
sub $8, %rsp
fstcw 4(%rsp)
stmxcsr (%rsp)
movq %rsp,%gs:tcsls_last_rsp
.Lusercall_noreturn:
/* clear general purpose register state */
/* RAX overwritten by ENCLU */
/* RBX set by sgx_exit */
/* RCX overwritten by ENCLU */
/* RDX contains parameter */
/* RSP set by sgx_exit */
/* RBP set by sgx_exit */
/* RDI contains parameter */
/* RSI contains parameter */
/* R8 contains parameter */
/* R9 contains parameter */
xor %r10,%r10
xor %r11,%r11
/* R12 ~ R15 set by sgx_exit */
/* extended registers/flags cleared by sgx_exit */
/* exit */
jmp .Lsgx_exit
.Lusercall_ret:
movq $0,%gs:tcsls_last_rsp
/* restore callee-saved state, cf. "save" above */
mov %r11,%rsp
/* MCDT mitigation requires an lfence after ldmxcsr _before_ any of the affected */
/* vector instructions is used. We omit the lfence here as one is required before */
/* the jmp instruction anyway. */
ldmxcsr (%rsp)
fldcw 4(%rsp)
add $8, %rsp
entry_sanitize_final
pop %rbx
pop %rbp
pop %r12
pop %r13
pop %r14
pop %r15
/* return */
mov %rsi,%rax /* RAX = return value */
/* NOP: mov %rdx,%rdx */ /* RDX = return value */
pop %r11
lfence
jmp *%r11
/*
The following functions need to be defined externally:
```
// Called by entry code on re-entry after exit
extern "C" fn abort_reentry() -> !;
// Called once when a TCS is first entered
extern "C" fn tcs_init(secondary: bool);
// Standard TCS entrypoint
extern "C" fn entry(p1: u64, p2: u64, p3: u64, secondary: bool, p4: u64, p5: u64) -> (u64, u64);
```
*/
.global get_tcs_addr
get_tcs_addr:
mov %gs:tcsls_tcs_addr,%rax
pop %r11
lfence
jmp *%r11
.global get_tls_ptr
get_tls_ptr:
mov %gs:tcsls_tls_ptr,%rax
pop %r11
lfence
jmp *%r11
.global set_tls_ptr
set_tls_ptr:
mov %rdi,%gs:tcsls_tls_ptr
pop %r11
lfence
jmp *%r11
.global take_debug_panic_buf_ptr
take_debug_panic_buf_ptr:
xor %rax,%rax
xchg %gs:tcsls_debug_panic_buf_ptr,%rax
pop %r11
lfence
jmp *%r11
|
gsspdev/rust | 29 | tests/codegen/foo.s | .global foo
foo:
jmp baz
|
gsspdev/rust | 79 | tests/ui/asm/named-asm-labels.s | lab1: nop
// do more things
lab2: nop // does bar
// a: b
lab3: nop; lab4: nop
|
gsspdev/rust | 136 | tests/run-make/x86_64-fortanix-unknown-sgx-lvi/enclave/foo_asm.s | .text
.global cc_plus_one_asm
.type cc_plus_one_asm, @function
cc_plus_one_asm:
movl (%rdi), %eax
inc %eax
retq
|
gsspdev/rust | 145 | tests/run-make/x86_64-fortanix-unknown-sgx-lvi/enclave/libcmake_foo/src/foo_asm.s | .text
.global cmake_plus_one_asm
.type cmake_plus_one_asm, @function
cmake_plus_one_asm:
movl (%rdi), %eax
inc %eax
retq
|
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