repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
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FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 20,049 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs_first_task:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
mrs r2, psplim /* r2 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
msr psp, r0 /* Remember the new top of stack for the task. */
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 27,033 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r2, lr}
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r2!, {s16-s31} /* Store s16-s31. */
vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */
sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r2!, {r4-r11} /* Store r4-r11. */
ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r2!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r3, lr}
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
adds r2, r2, #12 /* r2 = r2 + 12. */
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
subs r2, r2, #12 /* r2 = r2 - 12. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
/* r0 = uint32_t *pulTCB. */
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
it ne
svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,282 | portable/RVDS/ARM7_LPC21xx/portASM.s | ;/*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
INCLUDE portmacro.inc
IMPORT vTaskSwitchContext
IMPORT xTaskIncrementTick
EXPORT vPortYieldProcessor
EXPORT vPortStartFirstTask
EXPORT vPreemptiveTick
EXPORT vPortYield
VICVECTADDR EQU 0xFFFFF030
T0IR EQU 0xE0004000
T0MATCHBIT EQU 0x00000001
ARM
AREA PORT_ASM, CODE, READONLY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Starting the first task is done by just restoring the context
; setup by pxPortInitialiseStack
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortStartFirstTask
PRESERVE8
portRESTORE_CONTEXT
vPortYield
PRESERVE8
SVC 0
bx lr
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Interrupt service routine for the SWI interrupt. The vector table is
; configured in the startup.s file.
;
; vPortYieldProcessor() is used to manually force a context switch. The
; SWI interrupt is generated by a call to taskYIELD() or portYIELD().
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortYieldProcessor
PRESERVE8
; Within an IRQ ISR the link register has an offset from the true return
; address, but an SWI ISR does not. Add the offset manually so the same
; ISR return code can be used in both cases.
ADD LR, LR, #4
; Perform the context switch.
portSAVE_CONTEXT ; Save current task context
LDR R0, =vTaskSwitchContext ; Get the address of the context switch function
MOV LR, PC ; Store the return address
BX R0 ; Call the contedxt switch function
portRESTORE_CONTEXT ; restore the context of the selected task
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Interrupt service routine for preemptive scheduler tick timer
; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h
;
; Uses timer 0 of LPC21XX Family
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPreemptiveTick
PRESERVE8
portSAVE_CONTEXT ; Save the context of the current task.
LDR R0, =xTaskIncrementTick ; Increment the tick count.
MOV LR, PC ; This may make a delayed task ready
BX R0 ; to run.
CMP R0, #0
BEQ SkipContextSwitch
LDR R0, =vTaskSwitchContext ; Find the highest priority task that
MOV LR, PC ; is ready to run.
BX R0
SkipContextSwitch
MOV R0, #T0MATCHBIT ; Clear the timer event
LDR R1, =T0IR
STR R0, [R1]
LDR R0, =VICVECTADDR ; Acknowledge the interrupt
STR R0,[R0]
portRESTORE_CONTEXT ; Restore the context of the highest
; priority task that is ready to run.
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 5,447 | portable/RVDS/ARM_CA9/portASM.s | ;/*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
INCLUDE portmacro.inc
IMPORT vApplicationIRQHandler
IMPORT vTaskSwitchContext
IMPORT ulPortYieldRequired
IMPORT ulPortInterruptNesting
IMPORT vTaskSwitchContext
IMPORT ulICCIAR
IMPORT ulICCEOIR
EXPORT FreeRTOS_SWI_Handler
EXPORT FreeRTOS_IRQ_Handler
EXPORT vPortRestoreTaskContext
ARM
AREA PORT_ASM, CODE, READONLY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; SVC handler is used to yield a task.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_SWI_Handler
PRESERVE8
; Save the context of the current task and select a new task to run.
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vPortRestoreTaskContext is used to start the scheduler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortRestoreTaskContext
; Switch to system mode
CPS #SYS_MODE
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; PL390 GIC interrupt handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_IRQ_Handler
; Return to the interrupted instruction.
SUB lr, lr, #4
; Push the return address and SPSR
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
; Change to supervisor mode to allow reentry.
CPS #SVC_MODE
; Push used registers.
PUSH {r0-r4, r12}
; Increment nesting count. r3 holds the address of ulPortInterruptNesting
; for future use. r1 holds the original ulPortInterruptNesting value for
; future use.
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
; Read value from the interrupt acknowledge register, which is stored in r0
; for future parameter and interrupt clearing use.
LDR r2, =ulICCIAR
LDR r0, [r2]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use. _RB_ Does this ever actually need to be done provided the
; start of the stack is 8-byte aligned?
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
; Call the interrupt handler. r4 is pushed to maintain alignment.
PUSH {r0-r4, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
; Write the value read from ICCIAR to ICCEOIR
LDR r4, =ulICCEOIR
STR r0, [r4]
; Restore the old nesting count
STR r1, [r3]
; A context switch is never performed if the nesting count is not 0
CMP r1, #0
BNE exit_without_switch
; Did the interrupt request a context switch? r1 holds the address of
; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
; use.
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch
; No context switch. Restore used registers, LR_irq and SPSR before
; returning.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit
; A context swtich is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
; Restore used registers, LR-irq and SPSR before saving the context
; to the task stack.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
; Call the function that selects the new task to execute.
; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
; instructions, or 8 byte aligned stack allocated data. LR does not need
; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
LDR r0, =vTaskSwitchContext
BLX r0
; Restore the context of, and branch to, the task selected to execute next.
portRESTORE_CONTEXT
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 6,013 | portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* Xtensa interrupt handling data and assembly routines.
* Also see xtensa_intr.c and xtensa_vectors.S.
*/
#include <xtensa/hal.h>
#include <xtensa/config/core.h>
#include "xtensa_context.h"
#if XCHAL_HAVE_INTERRUPTS
/*
-------------------------------------------------------------------------------
INTENABLE virtualization information.
-------------------------------------------------------------------------------
*/
.data
.global _xt_intdata
.align 8
_xt_intdata:
.global _xt_intenable
.type _xt_intenable,@object
.size _xt_intenable,4
.global _xt_vpri_mask
.type _xt_vpri_mask,@object
.size _xt_vpri_mask,4
_xt_intenable: .word 0 /* Virtual INTENABLE */
_xt_vpri_mask: .word 0xFFFFFFFF /* Virtual priority mask */
/*
-------------------------------------------------------------------------------
Table of C-callable interrupt handlers for each interrupt. Note that not all
slots can be filled, because interrupts at level > EXCM_LEVEL will not be
dispatched to a C handler by default.
-------------------------------------------------------------------------------
*/
.data
.global _xt_interrupt_table
.align 8
_xt_interrupt_table:
.set i, 0
.rept XCHAL_NUM_INTERRUPTS
.word xt_unhandled_interrupt /* handler address */
.word i /* handler arg (default: intnum) */
.set i, i+1
.endr
#endif /* XCHAL_HAVE_INTERRUPTS */
#if XCHAL_HAVE_EXCEPTIONS
/*
-------------------------------------------------------------------------------
Table of C-callable exception handlers for each exception. Note that not all
slots will be active, because some exceptions (e.g. coprocessor exceptions)
are always handled by the OS and cannot be hooked by user handlers.
-------------------------------------------------------------------------------
*/
.data
.global _xt_exception_table
.align 4
_xt_exception_table:
.rept XCHAL_EXCCAUSE_NUM
.word xt_unhandled_exception /* handler address */
.endr
#endif
/*
-------------------------------------------------------------------------------
unsigned int xt_ints_on ( unsigned int mask )
Enables a set of interrupts. Does not simply set INTENABLE directly, but
computes it as a function of the current virtual priority.
Can be called from interrupt handlers.
-------------------------------------------------------------------------------
*/
.text
.align 4
.global xt_ints_on
.type xt_ints_on,@function
xt_ints_on:
ENTRY0
#if XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xt_intdata
xsr a3, INTENABLE /* Disables all interrupts */
rsync
l32i a3, a4, 0 /* a3 = _xt_intenable */
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
or a5, a3, a2 /* a5 = _xt_intenable | mask */
s32i a5, a4, 0 /* _xt_intenable |= mask */
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
wsr a5, INTENABLE /* Reenable interrupts */
mov a2, a3 /* Previous mask */
#else
movi a2, 0 /* Return zero */
#endif
RET0
.size xt_ints_on, . - xt_ints_on
/*
-------------------------------------------------------------------------------
unsigned int xt_ints_off ( unsigned int mask )
Disables a set of interrupts. Does not simply set INTENABLE directly,
but computes it as a function of the current virtual priority.
Can be called from interrupt handlers.
-------------------------------------------------------------------------------
*/
.text
.align 4
.global xt_ints_off
.type xt_ints_off,@function
xt_ints_off:
ENTRY0
#if XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xt_intdata
xsr a3, INTENABLE /* Disables all interrupts */
rsync
l32i a3, a4, 0 /* a3 = _xt_intenable */
l32i a6, a4, 4 /* a6 = _xt_vpri_mask */
or a5, a3, a2 /* a5 = _xt_intenable | mask */
xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */
s32i a5, a4, 0 /* _xt_intenable &= ~mask */
and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */
wsr a5, INTENABLE /* Reenable interrupts */
mov a2, a3 /* Previous mask */
#else
movi a2, 0 /* return zero */
#endif
RET0
.size xt_ints_off, . - xt_ints_off
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 23,354 | portable/ThirdParty/XCC/Xtensa/xtensa_context.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* XTENSA CONTEXT SAVE AND RESTORE ROUTINES
*
* Low-level Call0 functions for handling generic context save and restore of
* registers not specifically addressed by the interrupt vectors and handlers.
* Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
* Except for the calls to RTOS functions, this code is generic to Xtensa.
*
* Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
* save regs (A12-A15), which is always the case if the handlers are coded in C.
* However A12, A13 are made available as scratch registers for interrupt dispatch
* code, so are presumed saved anyway, and are always restored even in Call0 ABI.
* Only A14, A15 are truly handled as callee-save regs.
*
* Because Xtensa is a configurable architecture, this port supports all user
* generated configurations (except restrictions stated in the release notes).
* This is accomplished by conditional compilation using macros and functions
* defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
* Only the processor state included in your configuration is saved and restored,
* including any processor state added by user configuration options or TIE.
*/
/* Warn nicely if this file gets named with a lowercase .s instead of .S: */
#define NOERROR #
NOERROR: .error "C preprocessor needed for this file: make sure its filename\
ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
#include "xtensa_rtos.h"
#ifdef XT_USE_OVLY
#include <xtensa/overlay_os_asm.h>
#endif
.text
.literal_position
/*******************************************************************************
_xt_context_save
!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
interrupt stack frame defined in xtensa_rtos.h.
Its counterpart is _xt_context_restore (which also restores A12, A13).
Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
This function preserves A12 & A13 in order to provide the caller with 2 scratch
regs that need not be saved over the call to this function. The choice of which
2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
to avoid moving data more than necessary. Caller can assign regs accordingly.
Entry Conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
Original A12, A13 have already been saved in the interrupt stack frame.
Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
point of interruption.
If windowed ABI, PS.EXCM = 1 (exceptions disabled).
Exit conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
A12, A13 as at entry (preserved).
If windowed ABI, PS.EXCM = 1 (exceptions disabled).
*******************************************************************************/
.global _xt_context_save
.type _xt_context_save,@function
.align 4
_xt_context_save:
s32i a2, sp, XT_STK_A2
s32i a3, sp, XT_STK_A3
s32i a4, sp, XT_STK_A4
s32i a5, sp, XT_STK_A5
s32i a6, sp, XT_STK_A6
s32i a7, sp, XT_STK_A7
s32i a8, sp, XT_STK_A8
s32i a9, sp, XT_STK_A9
s32i a10, sp, XT_STK_A10
s32i a11, sp, XT_STK_A11
/*
Call0 ABI callee-saved regs a12-15 do not need to be saved here.
a12-13 are the caller's responsibility so it can use them as scratch.
So only need to save a14-a15 here for Windowed ABI (not Call0).
*/
#ifndef __XTENSA_CALL0_ABI__
s32i a14, sp, XT_STK_A14
s32i a15, sp, XT_STK_A15
#endif
rsr a3, SAR
s32i a3, sp, XT_STK_SAR
#if XCHAL_HAVE_LOOPS
rsr a3, LBEG
s32i a3, sp, XT_STK_LBEG
rsr a3, LEND
s32i a3, sp, XT_STK_LEND
rsr a3, LCOUNT
s32i a3, sp, XT_STK_LCOUNT
#endif
#if XT_USE_SWPRI
/* Save virtual priority mask */
movi a3, _xt_vpri_mask
l32i a3, a3, 0
s32i a3, sp, XT_STK_VPRI
#endif
#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
mov a9, a0 /* preserve ret addr */
#endif
#ifndef __XTENSA_CALL0_ABI__
/*
To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
Need to save a9,12,13 temporarily (in frame temps) and recover originals.
Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
and underflow exceptions disabled (assured by PS.EXCM == 1).
*/
s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
s32i a13, sp, XT_STK_TMP1
s32i a9, sp, XT_STK_TMP2
/*
Save the overlay state if we are supporting overlays. Since we just saved
three registers, we can conveniently use them here. Note that as of now,
overlays only work for windowed calling ABI.
*/
#ifdef XT_USE_OVLY
l32i a9, sp, XT_STK_PC /* recover saved PC */
_xt_overlay_get_state a9, a12, a13
s32i a9, sp, XT_STK_OVLY /* save overlay state */
#endif
l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */
l32i a13, sp, XT_STK_A13
l32i a9, sp, XT_STK_A9
addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */
call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */
addi sp, sp, -XT_STK_FRMSZ
l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */
l32i a13, sp, XT_STK_TMP1
l32i a9, sp, XT_STK_TMP2
#endif
#if XCHAL_EXTRA_SA_SIZE > 0
/*
NOTE: Normally the xthal_save_extra_nw macro only affects address
registers a2-a5. It is theoretically possible for Xtensa processor
designers to write TIE that causes more address registers to be
affected, but it is generally unlikely. If that ever happens,
more registers need to be saved/restored around this macro invocation.
Here we assume a9,12,13 are preserved.
Future Xtensa tools releases might limit the regs that can be affected.
*/
addi a2, sp, XT_STK_EXTRA /* where to save it */
# if XCHAL_EXTRA_SA_ALIGN > 16
movi a3, -XCHAL_EXTRA_SA_ALIGN
and a2, a2, a3 /* align dynamically >16 bytes */
# endif
call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */
#endif
#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
mov a0, a9 /* retrieve ret addr */
#endif
ret
/*******************************************************************************
_xt_context_restore
!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
stack frame defined in xtensa_rtos.h .
Its counterpart is _xt_context_save (whose caller saved A12, A13).
Caller is responsible to restore PC, PS, A0, A1 (SP).
Entry Conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
Exit conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
Other processor state except PC, PS, A0, A1 (SP), is as at the point
of interruption.
*******************************************************************************/
.global _xt_context_restore
.type _xt_context_restore,@function
.align 4
_xt_context_restore:
#if XCHAL_EXTRA_SA_SIZE > 0
/*
NOTE: Normally the xthal_restore_extra_nw macro only affects address
registers a2-a5. It is theoretically possible for Xtensa processor
designers to write TIE that causes more address registers to be
affected, but it is generally unlikely. If that ever happens,
more registers need to be saved/restored around this macro invocation.
Here we only assume a13 is preserved.
Future Xtensa tools releases might limit the regs that can be affected.
*/
mov a13, a0 /* preserve ret addr */
addi a2, sp, XT_STK_EXTRA /* where to find it */
# if XCHAL_EXTRA_SA_ALIGN > 16
movi a3, -XCHAL_EXTRA_SA_ALIGN
and a2, a2, a3 /* align dynamically >16 bytes */
# endif
call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */
mov a0, a13 /* retrieve ret addr */
#endif
#if XCHAL_HAVE_LOOPS
l32i a2, sp, XT_STK_LBEG
l32i a3, sp, XT_STK_LEND
wsr a2, LBEG
l32i a2, sp, XT_STK_LCOUNT
wsr a3, LEND
wsr a2, LCOUNT
#endif
#ifdef XT_USE_OVLY
/*
If we are using overlays, this is a good spot to check if we need
to restore an overlay for the incoming task. Here we have a bunch
of registers to spare. Note that this step is going to use a few
bytes of storage below SP (SP-20 to SP-32) if an overlay is going
to be restored.
*/
l32i a2, sp, XT_STK_PC /* retrieve PC */
l32i a3, sp, XT_STK_PS /* retrieve PS */
l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */
l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */
_xt_overlay_check_map a2, a3, a4, a5, a6
s32i a2, sp, XT_STK_PC /* save updated PC */
s32i a3, sp, XT_STK_PS /* save updated PS */
#endif
#ifdef XT_USE_SWPRI
/* Restore virtual interrupt priority and interrupt enable */
movi a3, _xt_intdata
l32i a4, a3, 0 /* a4 = _xt_intenable */
l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */
and a4, a4, a5
wsr a4, INTENABLE /* update INTENABLE */
s32i a5, a3, 4 /* restore _xt_vpri_mask */
#endif
l32i a3, sp, XT_STK_SAR
l32i a2, sp, XT_STK_A2
wsr a3, SAR
l32i a3, sp, XT_STK_A3
l32i a4, sp, XT_STK_A4
l32i a5, sp, XT_STK_A5
l32i a6, sp, XT_STK_A6
l32i a7, sp, XT_STK_A7
l32i a8, sp, XT_STK_A8
l32i a9, sp, XT_STK_A9
l32i a10, sp, XT_STK_A10
l32i a11, sp, XT_STK_A11
/*
Call0 ABI callee-saved regs a12-15 do not need to be restored here.
However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
so need to be restored anyway, despite being callee-saved in Call0.
*/
l32i a12, sp, XT_STK_A12
l32i a13, sp, XT_STK_A13
#ifndef __XTENSA_CALL0_ABI__
l32i a14, sp, XT_STK_A14
l32i a15, sp, XT_STK_A15
#endif
ret
/*******************************************************************************
_xt_coproc_init
Initializes global co-processor management data, setting all co-processors
to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
Called during initialization of the RTOS, before any threads run.
This may be called from normal Xtensa single-threaded application code which
might use co-processors. The Xtensa run-time initialization enables all
co-processors. They must remain enabled here, else a co-processor exception
might occur outside of a thread, which the exception handler doesn't expect.
Entry Conditions:
Xtensa single-threaded run-time environment is in effect.
No thread is yet running.
Exit conditions:
None.
Obeys ABI conventions per prototype:
void _xt_coproc_init(void)
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_init
.type _xt_coproc_init,@function
.align 4
_xt_coproc_init:
ENTRY0
/* Initialize thread co-processor ownerships to 0 (unowned). */
movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
addi a3, a2, XCHAL_CP_MAX << 2 /* a3 = top+1 of owner array */
movi a4, 0 /* a4 = 0 (unowned) */
1: s32i a4, a2, 0
addi a2, a2, 4
bltu a2, a3, 1b
RET0
#endif
/*******************************************************************************
_xt_coproc_release
Releases any and all co-processors owned by a given thread. The thread is
identified by it's co-processor state save area defined in xtensa_context.h .
Must be called before a thread's co-proc save area is deleted to avoid
memory corruption when the exception handler tries to save the state.
May be called when a thread terminates or completes but does not delete
the co-proc save area, to avoid the exception handler having to save the
thread's co-proc state before another thread can use it (optimization).
Entry Conditions:
A2 = Pointer to base of co-processor state save area.
Exit conditions:
None.
Obeys ABI conventions per prototype:
void _xt_coproc_release(void * coproc_sa_base)
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_release
.type _xt_coproc_release,@function
.align 4
_xt_coproc_release:
ENTRY0 /* a2 = base of save area */
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
movi a5, 0 /* a5 = 0 (unowned) */
rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */
1: l32i a7, a3, 0 /* a7 = owner at a3 */
bne a2, a7, 2f /* if (coproc_sa_base == owner) */
s32i a5, a3, 0 /* owner = unowned */
2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */
bltu a3, a4, 1b /* repeat until end of array */
3: wsr a6, PS /* restore interrupts */
RET0
#endif
/*******************************************************************************
_xt_coproc_savecs
If there is a current thread and it has a coprocessor state save area, then
save all callee-saved state into this area. This function is called from the
solicited context switch handler. It calls a system-specific function to get
the coprocessor save area base address.
Entry conditions:
- The thread being switched out is still the current thread.
- CPENABLE state reflects which coprocessors are active.
- Registers have been saved/spilled already.
Exit conditions:
- All necessary CP callee-saved state has been saved.
- Registers a2-a7, a13-a15 have been trashed.
Must be called from assembly code only, using CALL0.
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.extern _xt_coproc_sa_offset /* external reference */
.global _xt_coproc_savecs
.type _xt_coproc_savecs,@function
.align 4
_xt_coproc_savecs:
/* At entry, CPENABLE should be showing which CPs are enabled. */
rsr a2, CPENABLE /* a2 = which CPs are enabled */
beqz a2, .Ldone /* quick exit if none */
mov a14, a0 /* save return address */
call0 XT_RTOS_CP_STATE /* get address of CP save area */
mov a0, a14 /* restore return address */
beqz a15, .Ldone /* if none then nothing to do */
s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
#if XCHAL_CP0_SA_SIZE
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP1_SA_SIZE
bbci.l a2, 1, 2f /* CP 1 not enabled */
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
add a3, a14, a15 /* a3 = save area for CP 1 */
xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP2_SA_SIZE
bbci.l a2, 2, 2f
l32i a14, a13, 8
add a3, a14, a15
xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP3_SA_SIZE
bbci.l a2, 3, 2f
l32i a14, a13, 12
add a3, a14, a15
xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP4_SA_SIZE
bbci.l a2, 4, 2f
l32i a14, a13, 16
add a3, a14, a15
xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP5_SA_SIZE
bbci.l a2, 5, 2f
l32i a14, a13, 20
add a3, a14, a15
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP6_SA_SIZE
bbci.l a2, 6, 2f
l32i a14, a13, 24
add a3, a14, a15
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP7_SA_SIZE
bbci.l a2, 7, 2f
l32i a14, a13, 28
add a3, a14, a15
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
.Ldone:
ret
#endif
/*******************************************************************************
_xt_coproc_restorecs
Restore any callee-saved coprocessor state for the incoming thread.
This function is called from coprocessor exception handling, when giving
ownership to a thread that solicited a context switch earlier. It calls a
system-specific function to get the coprocessor save area base address.
Entry conditions:
- The incoming thread is set as the current thread.
- CPENABLE is set up correctly for all required coprocessors.
- a2 = mask of coprocessors to be restored.
Exit conditions:
- All necessary CP callee-saved state has been restored.
- CPENABLE - unchanged.
- Registers a2-a7, a13-a15 have been trashed.
Must be called from assembly code only, using CALL0.
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_restorecs
.type _xt_coproc_restorecs,@function
.align 4
_xt_coproc_restorecs:
mov a14, a0 /* save return address */
call0 XT_RTOS_CP_STATE /* get address of CP save area */
mov a0, a14 /* restore return address */
beqz a15, .Ldone2 /* if none then nothing to do */
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
xor a3, a3, a2 /* clear the ones being restored */
s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
#if XCHAL_CP0_SA_SIZE
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP1_SA_SIZE
bbci.l a2, 1, 2f /* CP 1 not enabled */
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
add a3, a14, a15 /* a3 = save area for CP 1 */
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP2_SA_SIZE
bbci.l a2, 2, 2f
l32i a14, a13, 8
add a3, a14, a15
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP3_SA_SIZE
bbci.l a2, 3, 2f
l32i a14, a13, 12
add a3, a14, a15
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP4_SA_SIZE
bbci.l a2, 4, 2f
l32i a14, a13, 16
add a3, a14, a15
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP5_SA_SIZE
bbci.l a2, 5, 2f
l32i a14, a13, 20
add a3, a14, a15
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP6_SA_SIZE
bbci.l a2, 6, 2f
l32i a14, a13, 24
add a3, a14, a15
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP7_SA_SIZE
bbci.l a2, 7, 2f
l32i a14, a13, 28
add a3, a14, a15
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
.Ldone2:
ret
#endif
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 22,494 | portable/ThirdParty/XCC/Xtensa/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "xtensa_rtos.h"
#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */
#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */
.extern pxCurrentTCB
/*
*******************************************************************************
* Interrupt stack. The size of the interrupt stack is determined by the config
* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
*******************************************************************************
*/
.data
.align 16
.global port_IntStack
port_IntStack:
.space configISR_STACK_SIZE
port_IntStackTop:
.word 0
port_switch_flag:
.word 0
.text
/*
*******************************************************************************
* _frxt_setup_switch
* void _frxt_setup_switch(void);
*
* Sets an internal flag indicating that a task switch is required on return
* from interrupt handling.
*
*******************************************************************************
*/
.global _frxt_setup_switch
.type _frxt_setup_switch,@function
.align 4
_frxt_setup_switch:
ENTRY(16)
movi a2, port_switch_flag
movi a3, 1
s32i a3, a2, 0
RET(16)
/*
*******************************************************************************
* _frxt_int_enter
* void _frxt_int_enter(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
* freeRTOS. Saves the rest of the interrupt context (not already saved).
* May only be called from assembly code by the 'call0' instruction, with
* interrupts disabled.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
*******************************************************************************
*/
.globl _frxt_int_enter
.type _frxt_int_enter,@function
.align 4
_frxt_int_enter:
/* Save a12-13 in the stack frame as required by _xt_context_save. */
s32i a12, a1, XT_STK_A12
s32i a13, a1, XT_STK_A13
/* Save return address in a safe place (free a0). */
mov a12, a0
/* Save the rest of the interrupted context (preserves A12-13). */
call0 _xt_context_save
/*
Save interrupted task's SP in TCB only if not nesting.
Manage nesting directly rather than call the generic IntEnter()
(in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
*/
movi a2, port_xSchedulerRunning
movi a3, port_interruptNesting
l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */
beqz a2, 1f /* scheduler not running, no tasks */
l32i a2, a3, 0 /* a2 = port_interruptNesting */
addi a2, a2, 1 /* increment nesting count */
s32i a2, a3, 0 /* save nesting count */
bnei a2, 1, .Lnested /* !=0 before incr, so nested */
movi a2, pxCurrentTCB
l32i a2, a2, 0 /* a2 = current TCB */
beqz a2, 1f
s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
movi a1, port_IntStackTop /* a1 = top of intr stack */
.Lnested:
1:
mov a0, a12 /* restore return addr and return */
ret
/*
*******************************************************************************
* _frxt_int_exit
* void _frxt_int_exit(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
* switching, restore the (possibly) new task's context, and return to the
* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
* May only be called from assembly code by the 'call0' instruction. Does not
* return to caller.
* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
*******************************************************************************
*/
.globl _frxt_int_exit
.type _frxt_int_exit,@function
.align 4
_frxt_int_exit:
movi a2, port_xSchedulerRunning
movi a3, port_interruptNesting
rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */
l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */
beqz a2, .Lnoswitch /* scheduler not running, no tasks */
l32i a2, a3, 0 /* a2 = port_interruptNesting */
addi a2, a2, -1 /* decrement nesting count */
s32i a2, a3, 0 /* save nesting count */
bnez a2, .Lnesting /* !=0 after decr so still nested */
movi a2, pxCurrentTCB
l32i a2, a2, 0 /* a2 = current TCB */
beqz a2, 1f /* no task ? go to dispatcher */
l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */
movi a2, port_switch_flag /* address of switch flag */
l32i a3, a2, 0 /* a3 = port_switch_flag */
beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */
movi a3, 0
s32i a3, a2, 0 /* zero out the flag for next time */
1:
/*
Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
However a12-13 were already saved by _frxt_int_enter().
*/
#ifdef __XTENSA_CALL0_ABI__
s32i a14, a1, XT_STK_A14
s32i a15, a1, XT_STK_A15
#endif
#ifdef __XTENSA_CALL0_ABI__
call0 vPortYieldFromInt /* call dispatch inside the function; never returns */
#else
call4 vPortYieldFromInt /* this one returns */
call0 _frxt_dispatch /* tail-call dispatcher */
/* Never returns here. */
#endif
.Lnoswitch:
/*
If we came here then about to resume the interrupted task.
*/
.Lnesting:
/*
We come here only if there was no context switch, that is if this
is a nested interrupt, or the interrupted task was not preempted.
In either case there's no need to load the SP.
*/
/* Restore full context from interrupt stack frame */
call0 _xt_context_restore
/*
Must return via the exit dispatcher corresponding to the entrypoint from which
this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
stack frame is deallocated in the exit dispatcher.
*/
l32i a0, a1, XT_STK_EXIT
ret
/*
**********************************************************************************************************
* _frxt_timer_int
* void _frxt_timer_int(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
* Called every timer interrupt.
* Manages the tick timer and calls xPortSysTickHandler() every tick.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
*
**********************************************************************************************************
*/
.globl _frxt_timer_int
.type _frxt_timer_int,@function
.align 4
_frxt_timer_int:
/*
Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs
an interrupt is generated, and the handler has to set a new cycle count into the comparator.
To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
than one tick late, it is necessary to process multiple ticks until the new cycle count is
in the future, otherwise the next timer interrupt would not occur until after the cycle
counter had wrapped (2^32 cycles later).
do {
ticks++;
old_ccompare = read_ccompare_i();
write_ccompare_i( old_ccompare + divisor );
service one tick;
diff = read_ccount() - old_ccompare;
} while ( diff > divisor );
*/
ENTRY(16)
.L_xt_timer_int_catchup:
/* Update the timer comparator for the next tick. */
#ifdef XT_CLOCK_FREQ
movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
#else
movi a3, _xt_tick_divisor
l32i a2, a3, 0 /* a2 = comparator increment */
#endif
rsr a3, XT_CCOMPARE /* a3 = old comparator value */
add a4, a3, a2 /* a4 = new comparator value */
wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
esync
#ifdef __XTENSA_CALL0_ABI__
/* Preserve a2 and a3 across C calls. */
s32i a2, sp, 4
s32i a3, sp, 8
#endif
/* Call the FreeRTOS tick handler (see port.c). */
#ifdef __XTENSA_CALL0_ABI__
call0 xPortSysTickHandler
#else
call4 xPortSysTickHandler
#endif
#ifdef __XTENSA_CALL0_ABI__
/* Restore a2 and a3. */
l32i a2, sp, 4
l32i a3, sp, 8
#endif
/* Check if we need to process more ticks to catch up. */
esync /* ensure comparator update complete */
rsr a4, CCOUNT /* a4 = cycle count */
sub a4, a4, a3 /* diff = ccount - old comparator */
blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */
RET(16)
/*
**********************************************************************************************************
* _frxt_tick_timer_init
* void _frxt_tick_timer_init(void)
*
* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
* Callable from C (obeys ABI conventions on entry).
*
**********************************************************************************************************
*/
.globl _frxt_tick_timer_init
.type _frxt_tick_timer_init,@function
.align 4
_frxt_tick_timer_init:
ENTRY(16)
/* Set up the periodic tick timer (assume enough time to complete init). */
#ifdef XT_CLOCK_FREQ
movi a3, XT_TICK_DIVISOR
#else
movi a2, _xt_tick_divisor
l32i a3, a2, 0
#endif
rsr a2, CCOUNT /* current cycle count */
add a2, a2, a3 /* time of first timer interrupt */
wsr a2, XT_CCOMPARE /* set the comparator */
/*
Enable the timer interrupt at the device level. Don't write directly
to the INTENABLE register because it may be virtualized.
*/
#ifdef __XTENSA_CALL0_ABI__
movi a2, XT_TIMER_INTEN
call0 xt_ints_on
#else
movi a6, XT_TIMER_INTEN
call4 xt_ints_on
#endif
RET(16)
/*
**********************************************************************************************************
* DISPATCH THE HIGH READY TASK
* void _frxt_dispatch(void)
*
* Switch context to the highest priority ready task, restore its state and dispatch control to it.
*
* This is a common dispatcher that acts as a shared exit path for all the context switch functions
* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
*
* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
* If restoring a task that was preempted, restores all state including the task's CPENABLE.
*
* Entry:
* pxCurrentTCB points to the TCB of the task to suspend,
* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
*
* Exit:
* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
*
**********************************************************************************************************
*/
.globl _frxt_dispatch
.type _frxt_dispatch,@function
.align 4
_frxt_dispatch:
#ifdef __XTENSA_CALL0_ABI__
call0 vTaskSwitchContext // Get next TCB to resume
movi a2, pxCurrentTCB
#else
movi a2, pxCurrentTCB
call4 vTaskSwitchContext // Get next TCB to resume
#endif
l32i a3, a2, 0
l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */
s32i a3, a2, 0
/* Determine the type of stack frame. */
l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */
bnez a2, .L_frxt_dispatch_stk
.L_frxt_dispatch_sol:
/* Solicited stack frame. Restore minimal context and return from vPortYield(). */
l32i a3, sp, XT_SOL_PS
#ifdef __XTENSA_CALL0_ABI__
l32i a12, sp, XT_SOL_A12
l32i a13, sp, XT_SOL_A13
l32i a14, sp, XT_SOL_A14
l32i a15, sp, XT_SOL_A15
#endif
l32i a0, sp, XT_SOL_PC
#if XCHAL_CP_NUM > 0
/* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
rsync
#endif
/* As soons as PS is restored, interrupts can happen. No need to sync PS. */
wsr a3, PS
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, XT_SOL_FRMSZ
ret
#else
retw
#endif
.L_frxt_dispatch_stk:
#if XCHAL_CP_NUM > 0
/* Restore CPENABLE from task's co-processor save area. */
movi a3, pxCurrentTCB /* cp_state = */
l32i a3, a3, 0
l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */
l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */
wsr a3, CPENABLE
#endif
/* Interrupt stack frame. Restore full context and return to exit dispatcher. */
call0 _xt_context_restore
/* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
#ifdef __XTENSA_CALL0_ABI__
l32i a14, sp, XT_STK_A14
l32i a15, sp, XT_STK_A15
#endif
#if XCHAL_CP_NUM > 0
/* Ensure wsr.CPENABLE has completed. */
rsync
#endif
/*
Must return via the exit dispatcher corresponding to the entrypoint from which
this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
stack frame is deallocated in the exit dispatcher.
*/
l32i a0, sp, XT_STK_EXIT
ret
/*
**********************************************************************************************************
* PERFORM A SOLICTED CONTEXT SWITCH (from a task)
* void vPortYield(void)
*
* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
*
* At Entry:
* pxCurrentTCB points to the TCB of the task to suspend
* Callable from C (obeys ABI conventions on entry).
*
* Does not return to caller.
*
**********************************************************************************************************
*/
.globl vPortYield
.type vPortYield,@function
.align 4
vPortYield:
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, -XT_SOL_FRMSZ
#else
entry sp, XT_SOL_FRMSZ
#endif
rsr a2, PS
s32i a0, sp, XT_SOL_PC
s32i a2, sp, XT_SOL_PS
#ifdef __XTENSA_CALL0_ABI__
s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */
s32i a13, sp, XT_SOL_A13
s32i a14, sp, XT_SOL_A14
s32i a15, sp, XT_SOL_A15
#else
/* Spill register windows. Calling xthal_window_spill() causes extra */
/* spills and reloads, so we will set things up to call the _nw version */
/* instead to save cycles. */
movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */
and a2, a2, a6 /* clear WOE, INTLEVEL */
addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */
wsr a2, PS
rsync
call0 xthal_window_spill_nw
l32i a2, sp, XT_SOL_PS /* restore PS */
wsr a2, PS
#endif
rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */
#if XCHAL_CP_NUM > 0
/* Save coprocessor callee-saved state (if any). At this point CPENABLE */
/* should still reflect which CPs were in use (enabled). */
call0 _xt_coproc_savecs
#endif
movi a2, pxCurrentTCB
movi a3, 0
l32i a2, a2, 0 /* a2 = pxCurrentTCB */
s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */
s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
#if XCHAL_CP_NUM > 0
/* Clear CPENABLE, also in task's co-processor state save area. */
l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state */
movi a3, 0
wsr a3, CPENABLE
beqz a2, 1f
s16i a3, a2, XT_CPENABLE /* clear saved cpenable */
1:
#endif
/* Tail-call dispatcher. */
call0 _frxt_dispatch
/* Never reaches here. */
/*
**********************************************************************************************************
* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
* void vPortYieldFromInt(void)
*
* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
* _frxt_dispatch() to perform the actual context switch.
*
* At Entry:
* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
* pxCurrentTCB points to the TCB of the task to suspend,
* Callable from C (obeys ABI conventions on entry).
*
* At Exit:
* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
*
**********************************************************************************************************
*/
.globl vPortYieldFromInt
.type vPortYieldFromInt,@function
.align 4
vPortYieldFromInt:
ENTRY(16)
#if XCHAL_CP_NUM > 0
/* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */
movi a3, pxCurrentTCB /* cp_state = */
l32i a3, a3, 0
l32i a2, a3, CP_TOPOFSTACK_OFFS
rsr a3, CPENABLE
s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */
movi a3, 0
wsr a3, CPENABLE /* disable all co-processors */
#endif
#ifdef __XTENSA_CALL0_ABI__
/* Tail-call dispatcher. */
call0 _frxt_dispatch
/* Never reaches here. */
#else
RET(16)
#endif
/*
**********************************************************************************************************
* _frxt_task_coproc_state
* void _frxt_task_coproc_state(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
*
* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
**********************************************************************************************************
*/
#if XCHAL_CP_NUM > 0
.globl _frxt_task_coproc_state
.type _frxt_task_coproc_state,@function
.align 4
_frxt_task_coproc_state:
movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */
l32i a15, a15, 0
beqz a15, 1f
movi a15, port_interruptNesting /* && port_interruptNesting == 0 */
l32i a15, a15, 0
bnez a15, 1f
movi a15, pxCurrentTCB
l32i a15, a15, 0 /* && pxCurrentTCB != 0) { */
beqz a15, 2f
l32i a15, a15, CP_TOPOFSTACK_OFFS
ret
1: movi a15, 0
2: ret
#endif /* XCHAL_CP_NUM > 0 */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 73,679 | portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
Xtensa low level exception and interrupt vectors and handlers for an RTOS.
Interrupt handlers and user exception handlers support interaction with
the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
after user's specific interrupt handlers. These macros are defined in
xtensa_<rtos>.h to call suitable functions in a specific RTOS.
Users can install application-specific interrupt handlers for low and
medium level interrupts, by calling xt_set_interrupt_handler(). These
handlers can be written in C, and must obey C calling convention. The
handler table is indexed by the interrupt number. Each handler may be
provided with an argument.
Note that the system timer interrupt is handled specially, and is
dispatched to the RTOS-specific handler. This timer cannot be hooked
by application code.
Optional hooks are also provided to install a handler per level at
run-time, made available by compiling this source file with
'-DXT_INTEXC_HOOKS' (useful for automated testing).
!! This file is a template that usually needs to be modified to handle !!
!! application specific interrupts. Search USER_EDIT for helpful comments !!
!! on where to insert handlers and how to write them. !!
Users can also install application-specific exception handlers in the
same way, by calling xt_set_exception_handler(). One handler slot is
provided for each exception type. Note that some exceptions are handled
by the porting layer itself, and cannot be taken over by application
code in this manner. These are the alloca, syscall, and coprocessor
exceptions.
The exception handlers can be written in C, and must follow C calling
convention. Each handler is passed a pointer to an exception frame as
its single argument. The exception frame is created on the stack, and
holds the saved context of the thread that took the exception. If the
handler returns, the context will be restored and the instruction that
caused the exception will be retried. If the handler makes any changes
to the saved state in the exception frame, the changes will be applied
when restoring the context.
Because Xtensa is a configurable architecture, this port supports all user
generated configurations (except restrictions stated in the release notes).
This is accomplished by conditional compilation using macros and functions
defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
Only the relevant parts of this file will be included in your RTOS build.
For example, this file provides interrupt vector templates for all types and
all priority levels, but only the ones in your configuration are built.
NOTES on the use of 'call0' for long jumps instead of 'j':
1. This file should be assembled with the -mlongcalls option to xt-xcc.
2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
distance from the call to the destination. The linker then relaxes
it back to 'call0 dest' if it determines that dest is within range.
This allows more flexibility in locating code without the performance
overhead of the 'l32r' literal data load in cases where the destination
is in range of 'call0'. There is an additional benefit in that 'call0'
has a longer range than 'j' due to the target being word-aligned, so
the 'l32r' sequence is less likely needed.
3. The use of 'call0' with -mlongcalls requires that register a0 not be
live at the time of the call, which is always the case for a function
call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
4. This use of 'call0' is independent of the C function call ABI.
*/
#include "xtensa_rtos.h"
/* Enable stack backtrace across exception/interrupt - see below */
#define XT_DEBUG_BACKTRACE 1
/*
--------------------------------------------------------------------------------
Defines used to access _xtos_interrupt_table.
--------------------------------------------------------------------------------
*/
#define XIE_HANDLER 0
#define XIE_ARG 4
#define XIE_SIZE 8
/*
--------------------------------------------------------------------------------
Macro extract_msb - return the input with only the highest bit set.
Input : "ain" - Input value, clobbered.
Output : "aout" - Output value, has only one bit set, MSB of "ain".
The two arguments must be different AR registers.
--------------------------------------------------------------------------------
*/
.macro extract_msb aout ain
1:
addi \aout, \ain, -1 /* aout = ain - 1 */
and \ain, \ain, \aout /* ain = ain & aout */
bnez \ain, 1b /* repeat until ain == 0 */
addi \aout, \aout, 1 /* return aout + 1 */
.endm
/*
--------------------------------------------------------------------------------
Macro dispatch_c_isr - dispatch interrupts to user ISRs.
This will dispatch to user handlers (if any) that are registered in the
XTOS dispatch table (_xtos_interrupt_table). These handlers would have
been registered by calling _xtos_set_interrupt_handler(). There is one
exception - the timer interrupt used by the OS will not be dispatched
to a user handler - this must be handled by the caller of this macro.
Level triggered and software interrupts are automatically deasserted by
this code.
ASSUMPTIONS:
-- PS.INTLEVEL is set to "level" at entry
-- PS.EXCM = 0, C calling enabled
NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
NOTE: This macro will use registers a0 and a2-a6. The arguments are:
level -- interrupt level
mask -- interrupt bitmask for this level
--------------------------------------------------------------------------------
*/
.macro dispatch_c_isr level mask
/* Get mask of pending, enabled interrupts at this level into a2. */
.L_xt_user_int_&level&:
rsr a2, INTENABLE
rsr a3, INTERRUPT
movi a4, \mask
and a2, a2, a3
and a2, a2, a4
beqz a2, 9f /* nothing to do */
/* This bit of code provides a nice debug backtrace in the debugger.
It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
if you want to save the cycles.
*/
#if XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
rsr a0, EPC_1 + \level - 1 /* return address */
movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */
or a0, a0, a4 /* set top 2 bits */
addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */
#endif
#endif
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a4, _xt_intexc_hooks
l32i a4, a4, \level << 2
beqz a4, 2f
#ifdef __XTENSA_CALL0_ABI__
callx0 a4
beqz a2, 9f
#else
mov a6, a2
callx4 a4
beqz a6, 9f
mov a2, a6
#endif
2:
#endif
/* Now look up in the dispatch table and call user ISR if any. */
/* If multiple bits are set then MSB has highest priority. */
extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */
#ifdef XT_USE_SWPRI
/* Enable all interrupts at this level that are numerically higher
than the one we just selected, since they are treated as higher
priority.
*/
movi a3, \mask /* a3 = all interrupts at this level */
add a2, a4, a4 /* a2 = a4 << 1 */
addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */
and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */
movi a3, _xt_intdata
l32i a6, a3, 4 /* a6 = _xt_vpri_mask */
neg a2, a2
addi a2, a2, -1 /* a2 = mask to apply */
and a5, a6, a2 /* mask off all bits <= a4 bit */
s32i a5, a3, 4 /* update _xt_vpri_mask */
rsr a3, INTENABLE
and a3, a3, a2 /* mask off all bits <= a4 bit */
wsr a3, INTENABLE
rsil a3, \level - 1 /* lower interrupt level by 1 */
#endif
movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */
wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */
beq a3, a4, 7f /* if timer interrupt then skip table */
find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */
movi a4, _xt_interrupt_table
addx8 a3, a3, a4 /* a3 = address of interrupt table entry */
l32i a4, a3, XIE_HANDLER /* a4 = handler address */
#ifdef __XTENSA_CALL0_ABI__
mov a12, a6 /* save in callee-saved reg */
l32i a2, a3, XIE_ARG /* a2 = handler arg */
callx0 a4 /* call handler */
mov a2, a12
#else
mov a2, a6 /* save in windowed reg */
l32i a6, a3, XIE_ARG /* a6 = handler arg */
callx4 a4 /* call handler */
#endif
#ifdef XT_USE_SWPRI
j 8f
#else
j .L_xt_user_int_&level& /* check for more interrupts */
#endif
7:
.ifeq XT_TIMER_INTPRI - \level
.L_xt_user_int_timer_&level&:
/*
Interrupt handler for the RTOS tick timer if at this level.
We'll be reading the interrupt state again after this call
so no need to preserve any registers except a6 (vpri_mask).
*/
#ifdef __XTENSA_CALL0_ABI__
mov a12, a6
call0 XT_RTOS_TIMER_INT
mov a2, a12
#else
mov a2, a6
call4 XT_RTOS_TIMER_INT
#endif
.endif
#ifdef XT_USE_SWPRI
j 8f
#else
j .L_xt_user_int_&level& /* check for more interrupts */
#endif
#ifdef XT_USE_SWPRI
8:
/* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
virtual _xt_intenable which _could_ have changed during interrupt
processing. */
movi a3, _xt_intdata
l32i a4, a3, 0 /* a4 = _xt_intenable */
s32i a2, a3, 4 /* update _xt_vpri_mask */
and a4, a4, a2 /* a4 = masked intenable */
wsr a4, INTENABLE /* update INTENABLE */
#endif
9:
/* done */
.endm
/*
--------------------------------------------------------------------------------
Panic handler.
Should be reached by call0 (preferable) or jump only. If call0, a0 says where
from. If on simulator, display panic message and abort, else loop indefinitely.
--------------------------------------------------------------------------------
*/
.text
.global _xt_panic
.type _xt_panic,@function
.align 4
.literal_position
_xt_panic:
#ifdef XT_SIMULATOR
addi a4, a0, -3 /* point to call0 */
movi a3, _xt_panic_message
movi a2, SYS_log_msg
simcall
movi a2, SYS_gdb_abort
simcall
#else
rsil a2, XCHAL_EXCM_LEVEL /* disable all low & med ints */
1: j 1b /* loop infinitely */
#endif
.section .rodata, "a"
.align 4
_xt_panic_message:
.string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"
/*
--------------------------------------------------------------------------------
Hooks to dynamically install handlers for exceptions and interrupts.
Allows automated regression frameworks to install handlers per test.
Consists of an array of function pointers indexed by interrupt level,
with index 0 containing the entry for user exceptions.
Initialized with all 0s, meaning no handler is installed at each level.
See comment in xtensa_rtos.h for more details.
--------------------------------------------------------------------------------
*/
#ifdef XT_INTEXC_HOOKS
.data
.global _xt_intexc_hooks
.type _xt_intexc_hooks,@object
.align 4
_xt_intexc_hooks:
.fill XT_INTEXC_HOOK_NUM, 4, 0
#endif
/*
--------------------------------------------------------------------------------
EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
(except window exception vectors).
Each vector goes at a predetermined location according to the Xtensa
hardware configuration, which is ensured by its placement in a special
section known to the Xtensa linker support package (LSP). It performs
the minimum necessary before jumping to the handler in the .text section.
The corresponding handler goes in the normal .text section. It sets up
the appropriate stack frame, saves a few vector-specific registers and
calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
and enter the RTOS, then sets up a C environment. It then calls the
user's interrupt handler code (which may be coded in C) and finally
calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
While XT_RTOS_INT_EXIT does not return directly to the interruptee,
eventually the RTOS scheduler will want to dispatch the interrupted
task or handler. The scheduler will return to the exit point that was
saved in the interrupt stack frame at XT_STK_EXIT.
--------------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------------
Debug Exception.
--------------------------------------------------------------------------------
*/
#if XCHAL_HAVE_DEBUG
.begin literal_prefix .DebugExceptionVector
.section .DebugExceptionVector.text, "ax"
.global _DebugExceptionVector
.align 4
.literal_position
_DebugExceptionVector:
#ifdef XT_SIMULATOR
/*
In the simulator, let the debugger (if any) handle the debug exception,
or simply stop the simulation:
*/
wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL /* save a2 where sim expects it */
movi a2, SYS_gdb_enter_sktloop
simcall /* have ISS handle debug exc. */
#elif 0 /* change condition to 1 to use the HAL minimal debug handler */
wsr a3, EXCSAVE+XCHAL_DEBUGLEVEL
movi a3, xthal_debugexc_defhndlr_nw /* use default debug handler */
jx a3
#else
wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* save original a0 somewhere */
call0 _xt_panic /* does not return */
rfi XCHAL_DEBUGLEVEL /* make a0 point here not later */
#endif
.end literal_prefix
#endif
/*
--------------------------------------------------------------------------------
Double Exception.
Double exceptions are not a normal occurrence. They indicate a bug of some kind.
--------------------------------------------------------------------------------
*/
#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
.begin literal_prefix .DoubleExceptionVector
.section .DoubleExceptionVector.text, "ax"
.global _DoubleExceptionVector
.align 4
.literal_position
_DoubleExceptionVector:
#if XCHAL_HAVE_DEBUG
break 1, 4 /* unhandled double exception */
#endif
call0 _xt_panic /* does not return */
rfde /* make a0 point here not later */
.end literal_prefix
#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
/*
--------------------------------------------------------------------------------
Kernel Exception (including Level 1 Interrupt from kernel mode).
--------------------------------------------------------------------------------
*/
.begin literal_prefix .KernelExceptionVector
.section .KernelExceptionVector.text, "ax"
.global _KernelExceptionVector
.align 4
.literal_position
_KernelExceptionVector:
wsr a0, EXCSAVE_1 /* preserve a0 */
call0 _xt_kernel_exc /* kernel exception handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.align 4
_xt_kernel_exc:
#if XCHAL_HAVE_DEBUG
break 1, 0 /* unhandled kernel exception */
#endif
call0 _xt_panic /* does not return */
rfe /* make a0 point here not there */
/*
--------------------------------------------------------------------------------
User Exception (including Level 1 Interrupt from user mode).
--------------------------------------------------------------------------------
*/
.begin literal_prefix .UserExceptionVector
.section .UserExceptionVector.text, "ax"
.global _UserExceptionVector
.type _UserExceptionVector,@function
.align 4
.literal_position
_UserExceptionVector:
wsr a0, EXCSAVE_1 /* preserve a0 */
call0 _xt_user_exc /* user exception handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
/*
--------------------------------------------------------------------------------
Insert some waypoints for jumping beyond the signed 8-bit range of
conditional branch instructions, so the conditional branchces to specific
exception handlers are not taken in the mainline. Saves some cycles in the
mainline.
--------------------------------------------------------------------------------
*/
.text
#if XCHAL_HAVE_WINDOWED
.align 4
_xt_to_alloca_exc:
call0 _xt_alloca_exc /* in window vectors section */
/* never returns here - call0 is used as a jump (see note at top) */
#endif
.align 4
_xt_to_syscall_exc:
call0 _xt_syscall_exc
/* never returns here - call0 is used as a jump (see note at top) */
#if XCHAL_CP_NUM > 0
.align 4
_xt_to_coproc_exc:
call0 _xt_coproc_exc
/* never returns here - call0 is used as a jump (see note at top) */
#endif
/*
--------------------------------------------------------------------------------
User exception handler.
--------------------------------------------------------------------------------
*/
.type _xt_user_exc,@function
.align 4
_xt_user_exc:
/* If level 1 interrupt then jump to the dispatcher */
rsr a0, EXCCAUSE
beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
/* Handle any coprocessor exceptions. Rely on the fact that exception
numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
*/
#if XCHAL_CP_NUM > 0
bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
#endif
/* Handle alloca and syscall exceptions */
#if XCHAL_HAVE_WINDOWED
beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc
#endif
beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
/* Handle all other exceptions. All can have user-defined handlers. */
/* NOTE: we'll stay on the user stack for exception handling. */
/* Allocate exception frame and save minimal context. */
mov a0, sp
addi sp, sp, -XT_STK_FRMSZ
s32i a0, sp, XT_STK_A1
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
#endif
s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
call0 _xt_context_save
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
#else
movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
#endif
wsr a0, PS
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
rsr a0, EPC_1 /* return address for debug backtrace */
movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */
rsync /* wait for WSR.PS to complete */
or a0, a0, a5 /* set top 2 bits */
addx2 a0, a5, a0 /* clear top bit -- thus simulating call4 size */
#else
rsync /* wait for WSR.PS to complete */
#endif
#endif
rsr a2, EXCCAUSE /* recover exc cause */
#ifdef XT_INTEXC_HOOKS
/*
Call exception hook to pre-handle exceptions (if installed).
Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
*/
movi a4, _xt_intexc_hooks
l32i a4, a4, 0 /* user exception hook index 0 */
beqz a4, 1f
.Ln_xt_user_exc_call_hook:
#ifdef __XTENSA_CALL0_ABI__
callx0 a4
beqi a2, -1, .L_xt_user_done
#else
mov a6, a2
callx4 a4
beqi a6, -1, .L_xt_user_done
mov a2, a6
#endif
1:
#endif
rsr a2, EXCCAUSE /* recover exc cause */
movi a3, _xt_exception_table
addx4 a4, a2, a3 /* a4 = address of exception table entry */
l32i a4, a4, 0 /* a4 = handler address */
#ifdef __XTENSA_CALL0_ABI__
mov a2, sp /* a2 = pointer to exc frame */
callx0 a4 /* call handler */
#else
mov a6, sp /* a6 = pointer to exc frame */
callx4 a4 /* call handler */
#endif
.L_xt_user_done:
/* Restore context and return */
call0 _xt_context_restore
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, PS
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_1
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove exception frame */
rsync /* ensure PS and EPC written */
rfe /* PS.EXCM is cleared */
/*
--------------------------------------------------------------------------------
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
--------------------------------------------------------------------------------
*/
.global _xt_user_exit
.type _xt_user_exit,@function
.align 4
_xt_user_exit:
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, PS
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_1
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure PS and EPC written */
rfe /* PS.EXCM is cleared */
/*
--------------------------------------------------------------------------------
Syscall Exception Handler (jumped to from User Exception Handler).
Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
--------------------------------------------------------------------------------
*/
.text
.type _xt_syscall_exc,@function
.align 4
_xt_syscall_exc:
#ifdef __XTENSA_CALL0_ABI__
/*
Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
Use a minimal stack frame (16B) to save A2 & A3 for scratch.
PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
rsr a0, PS
addi a0, a0, -PS_EXCM_MASK
wsr a0, PS
*/
addi sp, sp, -16
s32i a2, sp, 8
s32i a3, sp, 12
#else /* Windowed ABI */
/*
Save necessary context and spill the register windows.
PS.EXCM is still set and must remain set until after the spill.
Reuse context save function though it saves more than necessary.
For this reason, a full interrupt stack frame is allocated.
*/
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
call0 _xt_context_save
#endif
/*
Grab the interruptee's PC and skip over the 'syscall' instruction.
If it's at the end of a zero-overhead loop and it's not on the last
iteration, decrement loop counter and skip to beginning of loop.
*/
rsr a2, EPC_1 /* a2 = PC of 'syscall' */
addi a3, a2, 3 /* ++PC */
#if XCHAL_HAVE_LOOPS
rsr a0, LEND /* if (PC == LEND */
bne a3, a0, 1f
rsr a0, LCOUNT /* && LCOUNT != 0) */
beqz a0, 1f /* { */
addi a0, a0, -1 /* --LCOUNT */
rsr a3, LBEG /* PC = LBEG */
wsr a0, LCOUNT /* } */
#endif
1: wsr a3, EPC_1 /* update PC */
/* Restore interruptee's context and return from exception. */
#ifdef __XTENSA_CALL0_ABI__
l32i a2, sp, 8
l32i a3, sp, 12
addi sp, sp, 16
#else
call0 _xt_context_restore
addi sp, sp, XT_STK_FRMSZ
#endif
movi a0, -1
movnez a2, a0, a2 /* return -1 if not syscall 0 */
rsr a0, EXCSAVE_1
rfe
/*
--------------------------------------------------------------------------------
Co-Processor Exception Handler (jumped to from User Exception Handler).
These exceptions are generated by co-processor instructions, which are only
allowed in thread code (not in interrupts or kernel code). This restriction is
deliberately imposed to reduce the burden of state-save/restore in interrupts.
--------------------------------------------------------------------------------
*/
#if XCHAL_CP_NUM > 0
.section .rodata, "a"
/* Offset to CP n save area in thread's CP save area. */
.global _xt_coproc_sa_offset
.type _xt_coproc_sa_offset,@object
.align 16 /* minimize crossing cache boundaries */
_xt_coproc_sa_offset:
.word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
.word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
/* Bitmask for CP n's CPENABLE bit. */
.type _xt_coproc_mask,@object
.align 16,,8 /* try to keep it all in one cache line */
.set i, 0
_xt_coproc_mask:
.rept XCHAL_CP_MAX
.long (i<<16) | (1<<i) // upper 16-bits = i, lower = bitmask
.set i, i+1
.endr
.data
/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */
.global _xt_coproc_owner_sa
.type _xt_coproc_owner_sa,@object
.align 16,,XCHAL_CP_MAX<<2 /* minimize crossing cache boundaries */
_xt_coproc_owner_sa:
.space XCHAL_CP_MAX << 2
.text
.align 4
.L_goto_invalid:
j .L_xt_coproc_invalid /* not in a thread (invalid) */
.align 4
.L_goto_done:
j .L_xt_coproc_done
/*
--------------------------------------------------------------------------------
Coprocessor exception handler.
At entry, only a0 has been saved (in EXCSAVE_1).
--------------------------------------------------------------------------------
*/
.type _xt_coproc_exc,@function
.align 4
_xt_coproc_exc:
/* Allocate interrupt stack frame and save minimal context. */
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
#endif
movi a0, _xt_user_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
rsr a0, EXCCAUSE
s32i a5, sp, XT_STK_A5 /* save a5 */
addi a5, a0, -EXCCAUSE_CP0_DISABLED /* a5 = CP index */
/* Save a few more of interruptee's registers (a5 was already saved). */
s32i a2, sp, XT_STK_A2
s32i a3, sp, XT_STK_A3
s32i a4, sp, XT_STK_A4
s32i a15, sp, XT_STK_A15
/* Get co-processor state save area of new owner thread. */
call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */
beqz a15, .L_goto_invalid /* not in a thread (invalid) */
/* Enable the co-processor's bit in CPENABLE. */
movi a0, _xt_coproc_mask
rsr a4, CPENABLE /* a4 = CPENABLE */
addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
movi a3, _xt_coproc_owner_sa /* (placed here for load slot) */
extui a2, a0, 0, 16 /* coprocessor bitmask portion */
or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
wsr a4, CPENABLE
/* Get old coprocessor owner thread (save area ptr) and assign new one. */
addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */
l32i a2, a3, 0 /* a2 = old owner's save area */
s32i a15, a3, 0 /* _xt_coproc_owner_sa[n] = new */
rsync /* ensure wsr.CPENABLE is complete */
/* Only need to context switch if new owner != old owner. */
beq a15, a2, .L_goto_done /* new owner == old, we're done */
/* If no old owner then nothing to save. */
beqz a2, .L_check_new
/* If old owner not actively using CP then nothing to save. */
l16ui a4, a2, XT_CPENABLE /* a4 = old owner's CPENABLE */
bnone a4, a0, .L_check_new /* old owner not using CP */
.L_save_old:
/* Save old owner's coprocessor state. */
movi a5, _xt_coproc_sa_offset
/* Mark old owner state as no longer active (CPENABLE bit n clear). */
xor a4, a4, a0 /* clear CP bit in CPENABLE */
s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */
extui a4, a0, 16, 5 /* a4 = CP index = n */
addx4 a5, a4, a5 /* a5 = &_xt_coproc_sa_offset[n] */
/* Mark old owner state as saved (CPSTORED bit n set). */
l16ui a4, a2, XT_CPSTORED /* a4 = old owner's CPSTORED */
l32i a5, a5, 0 /* a5 = XT_CP[n]_SA offset */
or a4, a4, a0 /* set CP in old owner's CPSTORED */
s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */
l32i a2, a2, XT_CP_ASA /* ptr to actual (aligned) save area */
extui a3, a0, 16, 5 /* a3 = CP index = n */
add a2, a2, a5 /* a2 = old owner's area for CP n */
/*
The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
unlikely. If that ever happens, more registers needs to be saved/restored
around this macro invocation, and the value in a15 needs to be recomputed.
*/
xchal_cpi_store_funcbody
.L_check_new:
/* Check if any state has to be restored for new owner. */
/* NOTE: a15 = new owner's save area, cannot be zero when we get here. */
l16ui a3, a15, XT_CPSTORED /* a3 = new owner's CPSTORED */
movi a4, _xt_coproc_sa_offset
bnone a3, a0, .L_check_cs /* full CP not saved, check callee-saved */
xor a3, a3, a0 /* CPSTORED bit is set, clear it */
s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */
/* Adjust new owner's save area pointers to area for CP n. */
extui a3, a0, 16, 5 /* a3 = CP index = n */
addx4 a4, a3, a4 /* a4 = &_xt_coproc_sa_offset[n] */
l32i a4, a4, 0 /* a4 = XT_CP[n]_SA */
l32i a5, a15, XT_CP_ASA /* ptr to actual (aligned) save area */
add a2, a4, a5 /* a2 = new owner's area for CP */
/*
The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
unlikely. If that ever happens, more registers needs to be saved/restored
around this macro invocation.
*/
xchal_cpi_load_funcbody
/* Restore interruptee's saved registers. */
/* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
.L_xt_coproc_done:
l32i a15, sp, XT_STK_A15
l32i a5, sp, XT_STK_A5
l32i a4, sp, XT_STK_A4
l32i a3, sp, XT_STK_A3
l32i a2, sp, XT_STK_A2
call0 _xt_user_exit /* return via exit dispatcher */
/* Never returns here - call0 is used as a jump (see note at top) */
.L_check_cs:
/* a0 = CP mask in low bits, a15 = new owner's save area */
l16ui a2, a15, XT_CP_CS_ST /* a2 = mask of CPs saved */
bnone a2, a0, .L_xt_coproc_done /* if no match then done */
and a2, a2, a0 /* a2 = which CPs to restore */
extui a2, a2, 0, 8 /* extract low 8 bits */
s32i a6, sp, XT_STK_A6 /* save extra needed regs */
s32i a7, sp, XT_STK_A7
s32i a13, sp, XT_STK_A13
s32i a14, sp, XT_STK_A14
call0 _xt_coproc_restorecs /* restore CP registers */
l32i a6, sp, XT_STK_A6 /* restore saved registers */
l32i a7, sp, XT_STK_A7
l32i a13, sp, XT_STK_A13
l32i a14, sp, XT_STK_A14
j .L_xt_coproc_done
/* Co-processor exception occurred outside a thread (not supported). */
.L_xt_coproc_invalid:
#if XCHAL_HAVE_DEBUG
break 1, 1 /* unhandled user exception */
#endif
call0 _xt_panic /* not in a thread (invalid) */
/* never returns */
#endif /* XCHAL_CP_NUM */
/*
-------------------------------------------------------------------------------
Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
-------------------------------------------------------------------------------
*/
.text
.type _xt_lowint1,@function
.align 4
_xt_lowint1:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_user_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(1) | PS_UM
#else
movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
-------------------------------------------------------------------------------
MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
Medium priority interrupts are by definition those with priority greater
than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
setting PS.EXCM and therefore can easily support a C environment for
handlers in C, and interact safely with an RTOS.
Each vector goes at a predetermined location according to the Xtensa
hardware configuration, which is ensured by its placement in a special
section known to the Xtensa linker support package (LSP). It performs
the minimum necessary before jumping to the handler in the .text section.
The corresponding handler goes in the normal .text section. It sets up
the appropriate stack frame, saves a few vector-specific registers and
calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
and enter the RTOS, then sets up a C environment. It then calls the
user's interrupt handler code (which may be coded in C) and finally
calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
While XT_RTOS_INT_EXIT does not return directly to the interruptee,
eventually the RTOS scheduler will want to dispatch the interrupted
task or handler. The scheduler will return to the exit point that was
saved in the interrupt stack frame at XT_STK_EXIT.
-------------------------------------------------------------------------------
*/
#if XCHAL_EXCM_LEVEL >= 2
.begin literal_prefix .Level2InterruptVector
.section .Level2InterruptVector.text, "ax"
.global _Level2Vector
.type _Level2Vector,@function
.align 4
.literal_position
_Level2Vector:
wsr a0, EXCSAVE_2 /* preserve a0 */
call0 _xt_medint2 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_medint2,@function
.align 4
_xt_medint2:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_2 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_2 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_2 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint2_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(2) | PS_UM
#else
movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint2_exit
.type _xt_medint2_exit,@function
.align 4
_xt_medint2_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_2
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_2
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 2
#endif /* Level 2 */
#if XCHAL_EXCM_LEVEL >= 3
.begin literal_prefix .Level3InterruptVector
.section .Level3InterruptVector.text, "ax"
.global _Level3Vector
.type _Level3Vector,@function
.align 4
.literal_position
_Level3Vector:
wsr a0, EXCSAVE_3 /* preserve a0 */
call0 _xt_medint3 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_medint3,@function
.align 4
_xt_medint3:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_3 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_3 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_3 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint3_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(3) | PS_UM
#else
movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint3_exit
.type _xt_medint3_exit,@function
.align 4
_xt_medint3_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_3
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_3
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 3
#endif /* Level 3 */
#if XCHAL_EXCM_LEVEL >= 4
.begin literal_prefix .Level4InterruptVector
.section .Level4InterruptVector.text, "ax"
.global _Level4Vector
.type _Level4Vector,@function
.align 4
.literal_position
_Level4Vector:
wsr a0, EXCSAVE_4 /* preserve a0 */
call0 _xt_medint4 /* load interrupt handler */
.end literal_prefix
.text
.type _xt_medint4,@function
.align 4
_xt_medint4:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_4 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_4 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_4 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint4_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(4) | PS_UM
#else
movi a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint4_exit
.type _xt_medint4_exit,@function
.align 4
_xt_medint4_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_4
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_4
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 4
#endif /* Level 4 */
#if XCHAL_EXCM_LEVEL >= 5
.begin literal_prefix .Level5InterruptVector
.section .Level5InterruptVector.text, "ax"
.global _Level5Vector
.type _Level5Vector,@function
.align 4
.literal_position
_Level5Vector:
wsr a0, EXCSAVE_5 /* preserve a0 */
call0 _xt_medint5 /* load interrupt handler */
.end literal_prefix
.text
.type _xt_medint5,@function
.align 4
_xt_medint5:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_5 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_5 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_5 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint5_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(5) | PS_UM
#else
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint5_exit
.type _xt_medint5_exit,@function
.align 4
_xt_medint5_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_5
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_5
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 5
#endif /* Level 5 */
#if XCHAL_EXCM_LEVEL >= 6
.begin literal_prefix .Level6InterruptVector
.section .Level6InterruptVector.text, "ax"
.global _Level6Vector
.type _Level6Vector,@function
.align 4
.literal_position
_Level6Vector:
wsr a0, EXCSAVE_6 /* preserve a0 */
call0 _xt_medint6 /* load interrupt handler */
.end literal_prefix
.text
.type _xt_medint6,@function
.align 4
_xt_medint6:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_6 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_6 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_6 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint6_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(6) | PS_UM
#else
movi a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint6_exit
.type _xt_medint6_exit,@function
.align 4
_xt_medint6_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_6
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_6
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 6
#endif /* Level 6 */
/*******************************************************************************
HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
High priority interrupts are by definition those with priorities greater
than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
interrupts cannot interact with the RTOS, that is they must save all regs
they use and not call any RTOS function.
A further restriction imposed by the Xtensa windowed architecture is that
high priority interrupts must not modify the stack area even logically
"above" the top of the interrupted stack (they need to provide their
own stack or static save area).
Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
and used for purposes requiring very short service times.
Here are templates for high priority (level 2+) interrupt vectors.
They assume only one interrupt per level to avoid the burden of identifying
which interrupts at this level are pending and enabled. This allows for
minimum latency and avoids having to save/restore a2 in addition to a0.
If more than one interrupt per high priority level is configured, this burden
is on the handler which in any case must provide a way to save and restore
registers it uses without touching the interrupted stack.
Each vector goes at a predetermined location according to the Xtensa
hardware configuration, which is ensured by its placement in a special
section known to the Xtensa linker support package (LSP). It performs
the minimum necessary before jumping to the handler in the .text section.
*******************************************************************************/
/*
Currently only shells for high priority interrupt handlers are provided
here. However a template and example can be found in the Cadence Design Systems tools
documentation: "Microprocessor Programmer's Guide".
*/
#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
.begin literal_prefix .Level2InterruptVector
.section .Level2InterruptVector.text, "ax"
.global _Level2Vector
.type _Level2Vector,@function
.align 4
_Level2Vector:
wsr a0, EXCSAVE_2 /* preserve a0 */
call0 _xt_highint2 /* load interrupt handler */
.end literal_prefix
.text
.type _xt_highint2,@function
.align 4
_xt_highint2:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, 2<<2
beqz a0, 1f
.Ln_xt_highint2_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* USER_EDIT:
ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
*/
.align 4
.L_xt_highint2_exit:
rsr a0, EXCSAVE_2 /* restore a0 */
rfi 2
#endif /* Level 2 */
#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
.begin literal_prefix .Level3InterruptVector
.section .Level3InterruptVector.text, "ax"
.global _Level3Vector
.type _Level3Vector,@function
.align 4
_Level3Vector:
wsr a0, EXCSAVE_3 /* preserve a0 */
call0 _xt_highint3 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_highint3,@function
.align 4
_xt_highint3:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, 3<<2
beqz a0, 1f
.Ln_xt_highint3_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* USER_EDIT:
ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
*/
.align 4
.L_xt_highint3_exit:
rsr a0, EXCSAVE_3 /* restore a0 */
rfi 3
#endif /* Level 3 */
#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
.begin literal_prefix .Level4InterruptVector
.section .Level4InterruptVector.text, "ax"
.global _Level4Vector
.type _Level4Vector,@function
.align 4
_Level4Vector:
wsr a0, EXCSAVE_4 /* preserve a0 */
call0 _xt_highint4 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_highint4,@function
.align 4
_xt_highint4:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, 4<<2
beqz a0, 1f
.Ln_xt_highint4_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* USER_EDIT:
ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
*/
.align 4
.L_xt_highint4_exit:
rsr a0, EXCSAVE_4 /* restore a0 */
rfi 4
#endif /* Level 4 */
#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
.begin literal_prefix .Level5InterruptVector
.section .Level5InterruptVector.text, "ax"
.global _Level5Vector
.type _Level5Vector,@function
.align 4
_Level5Vector:
wsr a0, EXCSAVE_5 /* preserve a0 */
call0 _xt_highint5 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_highint5,@function
.align 4
_xt_highint5:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, 5<<2
beqz a0, 1f
.Ln_xt_highint5_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* USER_EDIT:
ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
*/
.align 4
.L_xt_highint5_exit:
rsr a0, EXCSAVE_5 /* restore a0 */
rfi 5
#endif /* Level 5 */
#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
.begin literal_prefix .Level6InterruptVector
.section .Level6InterruptVector.text, "ax"
.global _Level6Vector
.type _Level6Vector,@function
.align 4
_Level6Vector:
wsr a0, EXCSAVE_6 /* preserve a0 */
call0 _xt_highint6 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_highint6,@function
.align 4
_xt_highint6:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, 6<<2
beqz a0, 1f
.Ln_xt_highint6_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* USER_EDIT:
ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
*/
.align 4
.L_xt_highint6_exit:
rsr a0, EXCSAVE_6 /* restore a0 */
rfi 6
#endif /* Level 6 */
#if XCHAL_HAVE_NMI
.begin literal_prefix .NMIExceptionVector
.section .NMIExceptionVector.text, "ax"
.global _NMIExceptionVector
.type _NMIExceptionVector,@function
.align 4
_NMIExceptionVector:
wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */
call0 _xt_nmi /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.text
.type _xt_nmi,@function
.align 4
_xt_nmi:
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a0, _xt_intexc_hooks
l32i a0, a0, XCHAL_NMILEVEL<<2
beqz a0, 1f
.Ln_xt_nmi_call_hook:
callx0 a0 /* must NOT disturb stack! */
1:
#endif
/* USER_EDIT:
ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
*/
.align 4
.L_xt_nmi_exit:
rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */
rfi XCHAL_NMILEVEL
#endif /* NMI */
/*******************************************************************************
WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
Here is the code for each window overflow/underflow exception vector and
(interspersed) efficient code for handling the alloca exception cause.
Window exceptions are handled entirely in the vector area and are very
tight for performance. The alloca exception is also handled entirely in
the window vector area so comes at essentially no cost in code size.
Users should never need to modify them and Cadence Design Systems recommends
they do not.
Window handlers go at predetermined vector locations according to the
Xtensa hardware configuration, which is ensured by their placement in a
special section known to the Xtensa linker support package (LSP). Since
their offsets in that section are always the same, the LSPs do not define
a section per vector.
These things are coded for XEA2 only (XEA1 is not supported).
Note on Underflow Handlers:
The underflow handler for returning from call[i+1] to call[i]
must preserve all the registers from call[i+1]'s window.
In particular, a0 and a1 must be preserved because the RETW instruction
will be reexecuted (and may even underflow if an intervening exception
has flushed call[i]'s registers).
Registers a2 and up may contain return values.
*******************************************************************************/
#if XCHAL_HAVE_WINDOWED
.section .WindowVectors.text, "ax"
/*
--------------------------------------------------------------------------------
Window Overflow Exception for Call4.
Invoked if a call[i] referenced a register (a4-a15)
that contains data from ancestor call[j];
call[j] had done a call4 to call[j+1].
On entry here:
window rotated to call[j] start point;
a0-a3 are registers to be saved;
a4-a15 must be preserved;
a5 is call[j+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x0
.global _WindowOverflow4
_WindowOverflow4:
s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
rfwo /* rotates back to call[i] position */
/*
--------------------------------------------------------------------------------
Window Underflow Exception for Call4
Invoked by RETW returning from call[i+1] to call[i]
where call[i]'s registers must be reloaded (not live in ARs);
where call[i] had done a call4 to call[i+1].
On entry here:
window rotated to call[i] start point;
a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
a4-a15 must be preserved (they are call[i+1].reg[0..11]);
a5 is call[i+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x40
.global _WindowUnderflow4
_WindowUnderflow4:
l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
rfwu
/*
--------------------------------------------------------------------------------
Handle alloca exception generated by interruptee executing 'movsp'.
This uses space between the window vectors, so is essentially "free".
All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
and PS.EXCM has been set by the exception hardware (can't be interrupted).
The fact the alloca exception was taken means the registers associated with
the base-save area have been spilled and will be restored by the underflow
handler, so those 4 registers are available for scratch.
The code is optimized to avoid unaligned branches and minimize cache misses.
--------------------------------------------------------------------------------
*/
.align 4
.global _xt_alloca_exc
_xt_alloca_exc:
rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
rsr a2, PS
extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
xor a3, a3, a4 /* bits changed from old to current windowbase */
rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */
slli a3, a3, XCHAL_PS_OWB_SHIFT
xor a2, a2, a3 /* flip changed bits in old window base */
wsr a2, PS /* update PS.OWB to new window base */
rsync
_bbci.l a4, 31, _WindowUnderflow4
rotw -1 /* original a0 goes to a8 */
_bbci.l a8, 30, _WindowUnderflow8
rotw -1
j _WindowUnderflow12
/*
--------------------------------------------------------------------------------
Window Overflow Exception for Call8
Invoked if a call[i] referenced a register (a4-a15)
that contains data from ancestor call[j];
call[j] had done a call8 to call[j+1].
On entry here:
window rotated to call[j] start point;
a0-a7 are registers to be saved;
a8-a15 must be preserved;
a9 is call[j+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x80
.global _WindowOverflow8
_WindowOverflow8:
s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */
l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
(used to find end of call[j]'s frame) */
s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */
s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */
s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */
s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */
rfwo /* rotates back to call[i] position */
/*
--------------------------------------------------------------------------------
Window Underflow Exception for Call8
Invoked by RETW returning from call[i+1] to call[i]
where call[i]'s registers must be reloaded (not live in ARs);
where call[i] had done a call8 to call[i+1].
On entry here:
window rotated to call[i] start point;
a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
a8-a15 must be preserved (they are call[i+1].reg[0..7]);
a9 is call[i+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0xC0
.global _WindowUnderflow8
_WindowUnderflow8:
l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
(used to find end of call[i]'s frame) */
l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */
l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */
l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */
rfwu
/*
--------------------------------------------------------------------------------
Window Overflow Exception for Call12
Invoked if a call[i] referenced a register (a4-a15)
that contains data from ancestor call[j];
call[j] had done a call12 to call[j+1].
On entry here:
window rotated to call[j] start point;
a0-a11 are registers to be saved;
a12-a15 must be preserved;
a13 is call[j+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x100
.global _WindowOverflow12
_WindowOverflow12:
s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */
l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
(used to find end of call[j]'s frame) */
s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */
s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */
s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */
s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */
s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */
s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */
s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */
s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */
s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */
rfwo /* rotates back to call[i] position */
/*
--------------------------------------------------------------------------------
Window Underflow Exception for Call12
Invoked by RETW returning from call[i+1] to call[i]
where call[i]'s registers must be reloaded (not live in ARs);
where call[i] had done a call12 to call[i+1].
On entry here:
window rotated to call[i] start point;
a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
a12-a15 must be preserved (they are call[i+1].reg[0..3]);
a13 is call[i+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x140
.global _WindowUnderflow12
_WindowUnderflow12:
l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a11, a1, -12 /* a11 <- call[i-1]'s sp
(used to find end of call[i]'s frame) */
l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */
l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */
l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */
l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */
l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */
l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */
l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */
l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */
l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */
rfwu
#endif /* XCHAL_HAVE_WINDOWED */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 8,299 | portable/ThirdParty/GCC/ARC_v1/arc_support.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/**
* \file
* \ingroup OS_FREERTOS
* \brief freertos support for arc processor
* like task dispatcher, interrupt handler
*/
/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
/*
* core-dependent part in assemble language (for arc)
*/
#define __ASSEMBLY__
#include "arc/arc.h"
#include "arc/arc_asm_common.h"
/*
* task dispatcher
*
*/
.text
.align 4
.global dispatch
dispatch:
/*
* the pre-conditions of this routine are task context, CPU is
* locked, dispatch is enabled.
*/
SAVE_NONSCRATCH_REGS /* save callee save registers */
mov r1, dispatch_r
PUSH r1 /* save return address */
ld r0, [pxCurrentTCB]
bl dispatcher
/* return routine when task dispatch happened in task context */
dispatch_r:
RESTORE_NONSCRATCH_REGS /* recover registers */
j [blink]
/*
* start dispatch
*/
.global start_dispatch
.align 4
start_dispatch:
/*
* this routine is called in the non-task context during the startup of the kernel
* , and all the interrupts are locked.
*
* when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
* In target_initialize, all interrupt priority mask should be cleared, cpu should be
* locked, the interrupts outside the kernel such as fiq can be
* enabled.
*/
clri
mov r0, 0
st r0, [exc_nest_count]
b dispatcher_0
/*
* dispatcher
*/
dispatcher:
ld r1, [ulCriticalNesting]
PUSH r1 /* save critical nesting */
st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
jl vTaskSwitchContext /* change the value of pxCurrentTCB */
/*
* before dispatcher is called, task context | cpu locked | dispatch enabled
* should be satisfied. In this routine, the processor will jump
* into the entry of next to run task
*
* i.e. kernel mode, IRQ disabled, dispatch enabled
*/
dispatcher_0:
ld r1, [pxCurrentTCB]
ld sp, [r1] /* recover task stack */
#if ARC_FEATURE_STACK_CHECK
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_SC
flag r0
jl vPortSetStackCheck
lr r0, [AUX_STATUS32]
bset r0, r0, AUX_STATUS_BIT_SC
flag r0
#endif
POP r0 /* get critical nesting */
st r0, [ulCriticalNesting]
POP r0 /* get return address */
j [r0]
/*
* task startup routine
*
*/
.text
.global start_r
.align 4
start_r:
seti /* unlock cpu */
mov blink, vPortEndTask /* set return address */
POP r1 /* get task function body */
POP r0 /* get task parameters */
j [r1]
/****** exceptions and interrupts handing ******/
/****** entry for exception handling ******/
.global exc_entry_cpu
.align 4
exc_entry_cpu:
EXCEPTION_PROLOGUE
mov blink, sp
mov r3, sp /* as exception handler's para(p_excinfo) */
ld r1, [exc_nest_count]
add r1, r1, 1
st r1, [exc_nest_count]
brne r1, 0, exc_handler_1
/* change to exception stack if interrupt happened in task context */
mov sp, _e_stack
exc_handler_1:
PUSH blink
/* find the exception cause */
#if ARC_FEATURE_CORE_700
lr r0, [AUX_ECR]
lsr r0, r0, 16
bmsk r0, r0, 7
#endif
mov r1, exc_int_handler_table
ld.as r2, [r1, r0]
mov r0, r3
jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */
/* interrupts are not allowed */
ret_exc:
POP sp
mov r1, exc_nest_count
ld r0, [r1]
sub r0, r0, 1
st r0, [r1]
brne r0, 0, ret_exc_1 /* nested exception case */
lr r1, [AUX_IRQ_LV12]
brne r1, 0, ret_exc_1 /* nested or pending interrupt case */
ld r0, [context_switch_reqflg]
brne r0, 0, ret_exc_2
ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
EXCEPTION_EPILOGUE
#if ARC_FEATURE_CORE_600
rtie ilink2
#else
rtie
#endif
/* there is a dispatch request */
ret_exc_2:
/* clear dispatch request */
mov r0, 0
st r0, [context_switch_reqflg]
ld r0, [pxCurrentTCB]
breq r0, 0, ret_exc_1
SAVE_CALLEE_REGS /* save callee save registers */
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */
flag r0
mov r1, ret_exc_r /* save return address */
PUSH r1
bl dispatcher /* r0->pxCurrentTCB */
ret_exc_r:
/* recover exception status */
lr r0, [AUX_STATUS32]
bset r0, r0, AUX_STATUS_BIT_AE
flag r0
RESTORE_CALLEE_REGS /* recover registers */
EXCEPTION_EPILOGUE
#if ARC_FEATURE_CORE_600
rtie ilink2
#else
rtie
#endif
/****** entry for normal interrupt exception handling ******/
.global exc_entry_int /* entry for interrupt handling */
.align 4
exc_entry_int:
INTERRUPT_PROLOGUE
mov blink, sp
/* disable interrupt */
push r0
lr r0, [AUX_STATUS32]
push r0
bclr r0, r0, AUX_STATUS_BIT_E1
bclr r0, r0, AUX_STATUS_BIT_E2
flag r0
ld r3, [exc_nest_count]
add r2, r3, 1
st r2, [exc_nest_count]
/* enable interrupt */
pop r0
flag r0
pop r0
brne r3, 0, irq_handler_1
/* change to exception stack if interrupt happened in task context */
mov sp, _e_stack
#if ARC_FEATURE_STACK_CHECK
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_SC
flag r0
#endif
irq_handler_1:
PUSH blink
/* critical area */
#if ARC_FEATURE_CORE_700
lr r0, [AUX_IRQ_CAUSE1]
#endif
mov r1, exc_int_handler_table
ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */
/* handle software triggered interrupt */
lr r3, [AUX_IRQ_HINT]
cmp r3, r0
bne.d irq_hint_handled
xor r3, r3, r3
sr r3, [AUX_IRQ_HINT]
irq_hint_handled:
jl [r2] /* jump to interrupt handler */
/* no interrupts are allowed from here */
ret_int:
clri /* disable interrupt */
POP sp
mov r1, exc_nest_count
ld r0, [r1]
sub r0, r0, 1
st r0, [r1]
/* if there are multi-bits set in IRQ_LV12, it's still in nest interrupt */
lr r1, [AUX_IRQ_LV12]
ld r0, [context_switch_reqflg]
brne r0, 0, ret_int_2
ret_int_1: /* return from non-task context */
INTERRUPT_EPILOGUE
#if ARC_FEATURE_CORE_600
/* TODO: series 600 IRQ6 and IRQ7 uses ilink2 */
rtie ilink1
#else
rtie
#endif
/* there is a dispatch request */
ret_int_2:
/* clear dispatch request */
mov r0, 0
st r0, [context_switch_reqflg]
ld r0, [pxCurrentTCB]
breq r0, 0, ret_int_1
/* r1 has old AUX_IRQ_LV12 */
PUSH r1
/* clear related bits in IRQ_ACT manually to simulate a irq return */
SAVE_CALLEE_REGS /* save callee save registers */
mov r1, ret_int_r /* save return address */
PUSH r1
bl dispatcher /* r0->pxCurrentTCB */
ret_int_r:
RESTORE_CALLEE_REGS /* recover registers */
POPAX AUX_IRQ_LV12
INTERRUPT_EPILOGUE
#if ARC_FEATURE_CORE_600
rtie ilink1
#else
rtie
#endif
/** @endcond */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 26,462 | portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S | /*
* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
*
* SPDX-License-Identifier: MIT
*
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
*/
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*******************************************************************************
XTENSA CONTEXT SAVE AND RESTORE ROUTINES
Low-level Call0 functions for handling generic context save and restore of
registers not specifically addressed by the interrupt vectors and handlers.
Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
Except for the calls to RTOS functions, this code is generic to Xtensa.
Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
save regs (A12-A15), which is always the case if the handlers are coded in C.
However A12, A13 are made available as scratch registers for interrupt dispatch
code, so are presumed saved anyway, and are always restored even in Call0 ABI.
Only A14, A15 are truly handled as callee-save regs.
Because Xtensa is a configurable architecture, this port supports all user
generated configurations (except restrictions stated in the release notes).
This is accomplished by conditional compilation using macros and functions
defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
Only the processor state included in your configuration is saved and restored,
including any processor state added by user configuration options or TIE.
*******************************************************************************/
/* Warn nicely if this file gets named with a lowercase .s instead of .S: */
#define NOERROR #
NOERROR: .error "C preprocessor needed for this file: make sure its filename\
ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
#include "xtensa_rtos.h"
#include "xtensa_context.h"
#include "esp_idf_version.h"
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#include "xt_asm_utils.h"
#endif
#ifdef XT_USE_OVLY
#include <xtensa/overlay_os_asm.h>
#endif
.text
/*******************************************************************************
_xt_context_save
!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
interrupt stack frame defined in xtensa_rtos.h.
Its counterpart is _xt_context_restore (which also restores A12, A13).
Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
This function preserves A12 & A13 in order to provide the caller with 2 scratch
regs that need not be saved over the call to this function. The choice of which
2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
to avoid moving data more than necessary. Caller can assign regs accordingly.
Entry Conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
Original A12, A13 have already been saved in the interrupt stack frame.
Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
point of interruption.
If windowed ABI, PS.EXCM = 1 (exceptions disabled).
Exit conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
A12, A13 as at entry (preserved).
If windowed ABI, PS.EXCM = 1 (exceptions disabled).
*******************************************************************************/
.global _xt_context_save
.type _xt_context_save,@function
.align 4
.literal_position
.align 4
_xt_context_save:
s32i a2, sp, XT_STK_A2
s32i a3, sp, XT_STK_A3
s32i a4, sp, XT_STK_A4
s32i a5, sp, XT_STK_A5
s32i a6, sp, XT_STK_A6
s32i a7, sp, XT_STK_A7
s32i a8, sp, XT_STK_A8
s32i a9, sp, XT_STK_A9
s32i a10, sp, XT_STK_A10
s32i a11, sp, XT_STK_A11
/*
Call0 ABI callee-saved regs a12-15 do not need to be saved here.
a12-13 are the caller's responsibility so it can use them as scratch.
So only need to save a14-a15 here for Windowed ABI (not Call0).
*/
#ifndef __XTENSA_CALL0_ABI__
s32i a14, sp, XT_STK_A14
s32i a15, sp, XT_STK_A15
#endif
rsr a3, SAR
s32i a3, sp, XT_STK_SAR
#if XCHAL_HAVE_LOOPS
rsr a3, LBEG
s32i a3, sp, XT_STK_LBEG
rsr a3, LEND
s32i a3, sp, XT_STK_LEND
rsr a3, LCOUNT
s32i a3, sp, XT_STK_LCOUNT
#endif
#ifdef XT_USE_SWPRI
/* Save virtual priority mask */
movi a3, _xt_vpri_mask
l32i a3, a3, 0
s32i a3, sp, XT_STK_VPRI
#endif
#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
mov a9, a0 /* preserve ret addr */
#endif
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
#ifndef __XTENSA_CALL0_ABI__
/*
To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
Need to save a9,12,13 temporarily (in frame temps) and recover originals.
Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
and underflow exceptions disabled (assured by PS.EXCM == 1).
*/
s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
s32i a13, sp, XT_STK_TMP1
s32i a9, sp, XT_STK_TMP2
/*
Save the overlay state if we are supporting overlays. Since we just saved
three registers, we can conveniently use them here. Note that as of now,
overlays only work for windowed calling ABI.
*/
#ifdef XT_USE_OVLY
l32i a9, sp, XT_STK_PC /* recover saved PC */
_xt_overlay_get_state a9, a12, a13
s32i a9, sp, XT_STK_OVLY /* save overlay state */
#endif
l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */
l32i a13, sp, XT_STK_A13
l32i a9, sp, XT_STK_A9
addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */
call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */
addi sp, sp, -XT_STK_FRMSZ
l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */
l32i a13, sp, XT_STK_TMP1
l32i a9, sp, XT_STK_TMP2
#endif
#endif /* (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0)) */
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
s32i a13, sp, XT_STK_TMP1
s32i a9, sp, XT_STK_TMP2
l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */
l32i a13, sp, XT_STK_A13
l32i a9, sp, XT_STK_A9
#endif
#if XCHAL_EXTRA_SA_SIZE > 0
addi a2, sp, XT_STK_EXTRA /* where to save it */
# if XCHAL_EXTRA_SA_ALIGN > 16
movi a3, -XCHAL_EXTRA_SA_ALIGN
and a2, a2, a3 /* align dynamically >16 bytes */
# endif
call0 xthal_save_extra_nw /* destroys a0,2,3 */
#endif
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifndef __XTENSA_CALL0_ABI__
#ifdef XT_USE_OVLY
l32i a9, sp, XT_STK_PC /* recover saved PC */
_xt_overlay_get_state a9, a12, a13
s32i a9, sp, XT_STK_OVLY /* save overlay state */
#endif
/* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled,
* i.e. PS.EXCM cleared and PS.WOE set.
* Since we are going to clear PS.EXCM, we also need to increase INTLEVEL
* at least to XCHAL_EXCM_LEVEL. This matches that value of effective INTLEVEL
* at entry (CINTLEVEL=max(PS.INTLEVEL, XCHAL_EXCM_LEVEL) when PS.EXCM is set.
* Since WindowOverflow exceptions will trigger inside SPILL_ALL_WINDOWS,
* need to save/restore EPC1 as well.
* Note: even though a4-a15 are saved into the exception frame, we should not
* clobber them until after SPILL_ALL_WINDOWS. This is because these registers
* may contain live windows belonging to previous frames in the call stack.
* These frames will be spilled by SPILL_ALL_WINDOWS, and if the register was
* used as a temporary by this code, the temporary value would get stored
* onto the stack, instead of the real value.
*/
rsr a2, PS /* to be restored after SPILL_ALL_WINDOWS */
movi a0, PS_INTLEVEL_MASK
and a3, a2, a0 /* get the current INTLEVEL */
bgeui a3, XCHAL_EXCM_LEVEL, 1f /* calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */
movi a3, XCHAL_EXCM_LEVEL
1:
movi a0, PS_UM | PS_WOE /* clear EXCM, enable window overflow, set new INTLEVEL */
or a3, a3, a0
wsr a3, ps
rsr a0, EPC1 /* to be restored after SPILL_ALL_WINDOWS */
addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */
SPILL_ALL_WINDOWS
addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with context save*/
wsr a2, PS /* restore to the value at entry */
rsync
wsr a0, EPC1 /* likewise */
#endif /* __XTENSA_CALL0_ABI__ */
l32i a12, sp, XT_STK_TMP0 /* restore the temp saved registers */
l32i a13, sp, XT_STK_TMP1 /* our return address is there */
l32i a9, sp, XT_STK_TMP2
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
mov a0, a9 /* retrieve ret addr */
#endif
ret
/*******************************************************************************
_xt_context_restore
!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
stack frame defined in xtensa_rtos.h .
Its counterpart is _xt_context_save (whose caller saved A12, A13).
Caller is responsible to restore PC, PS, A0, A1 (SP).
Entry Conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
Exit conditions:
A0 = Return address in caller.
A1 = Stack pointer of interrupted thread or handler ("interruptee").
Other processor state except PC, PS, A0, A1 (SP), is as at the point
of interruption.
*******************************************************************************/
.global _xt_context_restore
.type _xt_context_restore,@function
.align 4
.literal_position
.align 4
_xt_context_restore:
#if XCHAL_EXTRA_SA_SIZE > 0
/*
NOTE: Normally the xthal_restore_extra_nw macro only affects address
registers a2-a5. It is theoretically possible for Xtensa processor
designers to write TIE that causes more address registers to be
affected, but it is generally unlikely. If that ever happens,
more registers need to be saved/restored around this macro invocation.
Here we only assume a13 is preserved.
Future Xtensa tools releases might limit the regs that can be affected.
*/
mov a13, a0 /* preserve ret addr */
addi a2, sp, XT_STK_EXTRA /* where to find it */
# if XCHAL_EXTRA_SA_ALIGN > 16
movi a3, -XCHAL_EXTRA_SA_ALIGN
and a2, a2, a3 /* align dynamically >16 bytes */
# endif
call0 xthal_restore_extra_nw /* destroys a0,2,3,4,5 */
mov a0, a13 /* retrieve ret addr */
#endif
#if XCHAL_HAVE_LOOPS
l32i a2, sp, XT_STK_LBEG
l32i a3, sp, XT_STK_LEND
wsr a2, LBEG
l32i a2, sp, XT_STK_LCOUNT
wsr a3, LEND
wsr a2, LCOUNT
#endif
#ifdef XT_USE_OVLY
/*
If we are using overlays, this is a good spot to check if we need
to restore an overlay for the incoming task. Here we have a bunch
of registers to spare. Note that this step is going to use a few
bytes of storage below SP (SP-20 to SP-32) if an overlay is going
to be restored.
*/
l32i a2, sp, XT_STK_PC /* retrieve PC */
l32i a3, sp, XT_STK_PS /* retrieve PS */
l32i a4, sp, XT_STK_OVLY /* retrieve overlay state */
l32i a5, sp, XT_STK_A1 /* retrieve stack ptr */
_xt_overlay_check_map a2, a3, a4, a5, a6
s32i a2, sp, XT_STK_PC /* save updated PC */
s32i a3, sp, XT_STK_PS /* save updated PS */
#endif
#ifdef XT_USE_SWPRI
/* Restore virtual interrupt priority and interrupt enable */
movi a3, _xt_intdata
l32i a4, a3, 0 /* a4 = _xt_intenable */
l32i a5, sp, XT_STK_VPRI /* a5 = saved _xt_vpri_mask */
and a4, a4, a5
wsr a4, INTENABLE /* update INTENABLE */
s32i a5, a3, 4 /* restore _xt_vpri_mask */
#endif
l32i a3, sp, XT_STK_SAR
l32i a2, sp, XT_STK_A2
wsr a3, SAR
l32i a3, sp, XT_STK_A3
l32i a4, sp, XT_STK_A4
l32i a5, sp, XT_STK_A5
l32i a6, sp, XT_STK_A6
l32i a7, sp, XT_STK_A7
l32i a8, sp, XT_STK_A8
l32i a9, sp, XT_STK_A9
l32i a10, sp, XT_STK_A10
l32i a11, sp, XT_STK_A11
/*
Call0 ABI callee-saved regs a12-15 do not need to be restored here.
However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
so need to be restored anyway, despite being callee-saved in Call0.
*/
l32i a12, sp, XT_STK_A12
l32i a13, sp, XT_STK_A13
#ifndef __XTENSA_CALL0_ABI__
l32i a14, sp, XT_STK_A14
l32i a15, sp, XT_STK_A15
#endif
ret
/*******************************************************************************
_xt_coproc_init
Initializes global co-processor management data, setting all co-processors
to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
Called during initialization of the RTOS, before any threads run.
This may be called from normal Xtensa single-threaded application code which
might use co-processors. The Xtensa run-time initialization enables all
co-processors. They must remain enabled here, else a co-processor exception
might occur outside of a thread, which the exception handler doesn't expect.
Entry Conditions:
Xtensa single-threaded run-time environment is in effect.
No thread is yet running.
Exit conditions:
None.
Obeys ABI conventions per prototype:
void _xt_coproc_init(void)
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_init
.type _xt_coproc_init,@function
.align 4
.literal_position
.align 4
_xt_coproc_init:
ENTRY0
/* Initialize thread co-processor ownerships to 0 (unowned). */
movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */
addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */
movi a4, 0 /* a4 = 0 (unowned) */
1: s32i a4, a2, 0
addi a2, a2, 4
bltu a2, a3, 1b
RET0
#endif
/*******************************************************************************
_xt_coproc_release
Releases any and all co-processors owned by a given thread. The thread is
identified by it's co-processor state save area defined in xtensa_context.h .
Must be called before a thread's co-proc save area is deleted to avoid
memory corruption when the exception handler tries to save the state.
May be called when a thread terminates or completes but does not delete
the co-proc save area, to avoid the exception handler having to save the
thread's co-proc state before another thread can use it (optimization).
Needs to be called on the processor the thread was running on. Unpinned threads
won't have an entry here because they get pinned as soon they use a coprocessor.
Entry Conditions:
A2 = Pointer to base of co-processor state save area.
Exit conditions:
None.
Obeys ABI conventions per prototype:
void _xt_coproc_release(void * coproc_sa_base)
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_release
.type _xt_coproc_release,@function
.align 4
.literal_position
.align 4
_xt_coproc_release:
ENTRY0 /* a2 = base of save area */
getcoreid a5
movi a3, XCHAL_CP_MAX << 2
mull a5, a5, a3
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
add a3, a3, a5
addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */
movi a5, 0 /* a5 = 0 (unowned) */
rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */
1: l32i a7, a3, 0 /* a7 = owner at a3 */
bne a2, a7, 2f /* if (coproc_sa_base == owner) */
s32i a5, a3, 0 /* owner = unowned */
2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */
bltu a3, a4, 1b /* repeat until end of array */
3: wsr a6, PS /* restore interrupts */
RET0
#endif
/*******************************************************************************
_xt_coproc_savecs
If there is a current thread and it has a coprocessor state save area, then
save all callee-saved state into this area. This function is called from the
solicited context switch handler. It calls a system-specific function to get
the coprocessor save area base address.
Entry conditions:
- The thread being switched out is still the current thread.
- CPENABLE state reflects which coprocessors are active.
- Registers have been saved/spilled already.
Exit conditions:
- All necessary CP callee-saved state has been saved.
- Registers a2-a7, a13-a15 have been trashed.
Must be called from assembly code only, using CALL0.
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.extern _xt_coproc_sa_offset /* external reference */
.global _xt_coproc_savecs
.type _xt_coproc_savecs,@function
.align 4
.literal_position
.align 4
_xt_coproc_savecs:
/* At entry, CPENABLE should be showing which CPs are enabled. */
rsr a2, CPENABLE /* a2 = which CPs are enabled */
beqz a2, .Ldone /* quick exit if none */
mov a14, a0 /* save return address */
call0 XT_RTOS_CP_STATE /* get address of CP save area */
mov a0, a14 /* restore return address */
beqz a15, .Ldone /* if none then nothing to do */
s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
#if XCHAL_CP0_SA_SIZE
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP1_SA_SIZE
bbci.l a2, 1, 2f /* CP 1 not enabled */
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
add a3, a14, a15 /* a3 = save area for CP 1 */
xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP2_SA_SIZE
bbci.l a2, 2, 2f
l32i a14, a13, 8
add a3, a14, a15
xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP3_SA_SIZE
bbci.l a2, 3, 2f
l32i a14, a13, 12
add a3, a14, a15
xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP4_SA_SIZE
bbci.l a2, 4, 2f
l32i a14, a13, 16
add a3, a14, a15
xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP5_SA_SIZE
bbci.l a2, 5, 2f
l32i a14, a13, 20
add a3, a14, a15
xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP6_SA_SIZE
bbci.l a2, 6, 2f
l32i a14, a13, 24
add a3, a14, a15
xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP7_SA_SIZE
bbci.l a2, 7, 2f
l32i a14, a13, 28
add a3, a14, a15
xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
.Ldone:
ret
#endif
/*******************************************************************************
_xt_coproc_restorecs
Restore any callee-saved coprocessor state for the incoming thread.
This function is called from coprocessor exception handling, when giving
ownership to a thread that solicited a context switch earlier. It calls a
system-specific function to get the coprocessor save area base address.
Entry conditions:
- The incoming thread is set as the current thread.
- CPENABLE is set up correctly for all required coprocessors.
- a2 = mask of coprocessors to be restored.
Exit conditions:
- All necessary CP callee-saved state has been restored.
- CPENABLE - unchanged.
- Registers a2-a7, a13-a15 have been trashed.
Must be called from assembly code only, using CALL0.
*******************************************************************************/
#if XCHAL_CP_NUM > 0
.global _xt_coproc_restorecs
.type _xt_coproc_restorecs,@function
.align 4
.literal_position
.align 4
_xt_coproc_restorecs:
mov a14, a0 /* save return address */
call0 XT_RTOS_CP_STATE /* get address of CP save area */
mov a0, a14 /* restore return address */
beqz a15, .Ldone2 /* if none then nothing to do */
l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */
xor a3, a3, a2 /* clear the ones being restored */
s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
#if XCHAL_CP0_SA_SIZE
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP1_SA_SIZE
bbci.l a2, 1, 2f /* CP 1 not enabled */
l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */
add a3, a14, a15 /* a3 = save area for CP 1 */
xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP2_SA_SIZE
bbci.l a2, 2, 2f
l32i a14, a13, 8
add a3, a14, a15
xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP3_SA_SIZE
bbci.l a2, 3, 2f
l32i a14, a13, 12
add a3, a14, a15
xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP4_SA_SIZE
bbci.l a2, 4, 2f
l32i a14, a13, 16
add a3, a14, a15
xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP5_SA_SIZE
bbci.l a2, 5, 2f
l32i a14, a13, 20
add a3, a14, a15
xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP6_SA_SIZE
bbci.l a2, 6, 2f
l32i a14, a13, 24
add a3, a14, a15
xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
#if XCHAL_CP7_SA_SIZE
bbci.l a2, 7, 2f
l32i a14, a13, 28
add a3, a14, a15
xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
.Ldone2:
ret
#endif
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 14,763 | portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S | /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* LoadStoreErrorCause: Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit
* LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner
*
* xxxx xxxx = imm8 field
* yyyy = imm4 field
* ssss = s field
* tttt = t field
*
* 16 0
* -------------------
* L32I.N yyyy ssss tttt 1000
* S32I.N yyyy ssss tttt 1001
*
* 23 0
* -----------------------------
* L8UI xxxx xxxx 0000 ssss tttt 0010 <- LoadStoreError
* L16UI xxxx xxxx 0001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment
* L16SI xxxx xxxx 1001 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment
* L32I xxxx xxxx 0010 ssss tttt 0010 <- LoadStoreAlignment
*
* S8I xxxx xxxx 0100 ssss tttt 0010 <- LoadStoreError
* S16I xxxx xxxx 0101 ssss tttt 0010 <- LoadStoreError, LoadStoreAlignment
* S32I xxxx xxxx 0110 ssss tttt 0010 <- LoadStoreAlignment
*
* ******* UNSUPPORTED *******
*
* L32E 0000 1001 rrrr ssss tttt 0000
* S32E 0100 1001 rrrr ssss tttt 0000
* -----------------------------
*/
#include "xtensa_rtos.h"
#include "sdkconfig.h"
#include "soc/soc.h"
#define LOADSTORE_HANDLER_STACK_SZ 8
.section .bss, "aw"
.balign 16
LoadStoreHandlerStack:
.rept LOADSTORE_HANDLER_STACK_SZ
.word 0
.endr
/* LoadStoreErrorCause handler:
*
* Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region
* Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
*/
.global LoadStoreErrorHandler
.section .iram1, "ax"
.literal_position
.balign 4
LoadStoreErrorHandler:
.type LoadStoreErrorHandler, @function
wsr a0, depc // Save return address in depc
mov a0, sp
movi sp, LoadStoreHandlerStack
s32i a0, sp, 0x04 // Since a0 contains value of a1
s32i a2, sp, 0x08
s32i a3, sp, 0x0c
s32i a4, sp, 0x10
rsr a0, sar // Save SAR in a0 to restore later
/* Check whether the address lies in the valid range */
rsr a3, excvaddr
movi a4, _iram_text_end // End of code section of IRAM
bge a3, a4, 1f
movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region
blt a3, a4, .LS_wrong_opcode
movi a4, SOC_CACHE_APP_HIGH
bge a3, a4, .LS_wrong_opcode
j 2f
1:
movi a4, SOC_IRAM_HIGH // End of IRAM address range
bge a3, a4, .LS_wrong_opcode
2:
/* Examine the opcode which generated the exception */
/* Note: Instructions are in this order to avoid pipeline stalls. */
rsr a2, epc1
movi a4, ~3
ssa8l a2 // sar is now correct shift for aligned read
and a2, a2, a4 // a2 now 4-byte aligned address of instruction
l32i a4, a2, 0
l32i a2, a2, 4
src a2, a2, a4 // a2 now instruction that failed
bbci a2, 1, .LS_wrong_opcode
bbsi a2, 14, .LSE_store_op // Store instruction
/* l8/l16ui/l16si */
movi a4, ~3
and a4, a3, a4 // a4 now word aligned read address
ssa8l a3 // sar is now shift to extract a3's byte
l32i a4, a4, 0 // perform the actual read
srl a4, a4 // shift right correct distance
extui a3, a2, 12, 4
bnez a3, 1f // l16ui/l16si
extui a4, a4, 0, 8 // mask off bits needed for an l8
j 2f
1:
extui a4, a4, 0, 16
bbci a2, 15, 2f // l16ui
/* Sign adjustment */
slli a4, a4, 16
srai a4, a4, 16 // a4 contains the value
2:
/* a4 contains the value */
rsr a3, epc1
addi a3, a3, 3
wsr a3, epc1
wsr a0, sar
rsr a0, excsave1
extui a2, a2, 3, 5
blti a2, 10, .LSE_stack_reg
movi a3, .LS_jumptable_base
addx8 a2, a2, a3 // a2 is now the address to jump to
l32i a3, sp, 0x0c
jx a2
.LSE_stack_reg:
addx2 a2, a2, sp
s32i a4, a2, 0
/* Restore all values */
l32i a4, sp, 0x10
l32i a3, sp, 0x0c
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.LSE_store_op:
s32i a5, a1, 0x14
s32i a6, a1, 0x18
/* a2 -> instruction that caused the error */
/* a3 -> unaligned address */
extui a4, a2, 4, 4
blti a4, 7, 1f
movi a5, .LSE_store_reg
addx8 a5, a4, a5
jx a5
1:
addx4 a4, a4, sp
l32i a4, a4, 0
.LSE_store_data:
/* a4 contains the value */
rsr a6, epc1
addi a6, a6, 3
wsr a6, epc1
ssa8b a3
movi a5, -1
bbsi a2, 12, 1f // s16
extui a4, a4, 0, 8
movi a6, 0xff
j 2f
1:
extui a4, a4, 0, 16
movi a6, 0xffff
2:
sll a4, a4 // shift the value to proper offset
sll a6, a6
xor a5, a5, a6 // a5 contains the mask
movi a6, ~3
and a3, a3, a6 // a3 has the aligned address
l32i a6, a3, 0 // a6 contains the data at the aligned address
and a6, a6, a5
or a4, a6, a4
s32i a4, a3, 0
/* Restore registers */
wsr a0, sar
l32i a6, sp, 0x18
l32i a5, sp, 0x14
l32i a4, sp, 0x10
l32i a3, sp, 0x0c
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rsr a0, excsave1
rfe
.LSE_store_reg:
.org .LSE_store_reg + (7 * 8)
mov a4, a7
j .LSE_store_data
.org .LSE_store_reg + (8 * 8)
mov a4, a8
j .LSE_store_data
.org .LSE_store_reg + (9 * 8)
mov a4, a9
j .LSE_store_data
.org .LSE_store_reg + (10 * 8)
mov a4, a10
j .LSE_store_data
.org .LSE_store_reg + (11 * 8)
mov a4, a11
j .LSE_store_data
.org .LSE_store_reg + (12 * 8)
mov a4, a12
j .LSE_store_data
.org .LSE_store_reg + (13 * 8)
mov a4, a13
j .LSE_store_data
.org .LSE_store_reg + (14 * 8)
mov a4, a14
j .LSE_store_data
.org .LSE_store_reg + (15 * 8)
mov a4, a15
j .LSE_store_data
/* LoadStoreAlignmentCause handler:
*
* Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region
* Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause
*/
.global AlignmentErrorHandler
.section .iram1, "ax"
.literal_position
.balign 4
AlignmentErrorHandler:
.type AlignmentErrorHandler, @function
wsr a0, depc // Save return address in depc
mov a0, sp
movi sp, LoadStoreHandlerStack
s32i a0, sp, 0x04 // Since a0 contains value of a1
s32i a2, sp, 0x08
s32i a3, sp, 0x0c
s32i a4, sp, 0x10
rsr a0, sar // Save SAR in a0 to restore later
/* Check whether the address lies in the valid range */
rsr a3, excvaddr
movi a4, _iram_text_end // End of code section of IRAM
bge a3, a4, 1f
movi a4, SOC_CACHE_APP_LOW // Check if in APP cache region
blt a3, a4, .LS_wrong_opcode
movi a4, SOC_CACHE_APP_HIGH
bge a3, a4, .LS_wrong_opcode
j 2f
1:
movi a4, SOC_IRAM_HIGH // End of IRAM address range
bge a3, a4, .LS_wrong_opcode
2:
/* Examine the opcode which generated the exception */
/* Note: Instructions are in this order to avoid pipeline stalls. */
rsr a2, epc1
movi a4, ~3
ssa8l a2 // sar is now correct shift for aligned read
and a2, a2, a4 // a2 now 4-byte aligned address of instruction
l32i a4, a2, 0
l32i a2, a2, 4
/* a2 has the instruction that caused the error */
src a2, a2, a4
extui a4, a2, 0, 4
addi a4, a4, -9
beqz a4, .LSA_store_op
bbsi a2, 14, .LSA_store_op
ssa8l a3 // a3 contains the unaligned address
movi a4, ~3
and a4, a3, a4 // a4 has the aligned address
l32i a3, a4, 0
l32i a4, a4, 4
src a4, a4, a3
rsr a3, epc1
addi a3, a3, 2
bbsi a2, 3, 1f // l32i.n
bbci a2, 1, .LS_wrong_opcode
addi a3, a3, 1
bbsi a2, 13, 1f // l32
extui a4, a4, 0, 16
bbci a2, 15, 1f // l16ui
/* Sign adjustment */
slli a4, a4, 16
srai a4, a4, 16 // a4 contains the value
1:
wsr a3, epc1
wsr a0, sar
rsr a0, excsave1
extui a2, a2, 4, 4
blti a2, 5, .LSA_stack_reg // a3 contains the target register
movi a3, .LS_jumptable_base
slli a2, a2, 4
add a2, a2, a3 // a2 is now the address to jump to
l32i a3, sp, 0x0c
jx a2
.LSA_stack_reg:
addx4 a2, a2, sp
s32i a4, a2, 0
/* Restore all values */
l32i a4, sp, 0x10
l32i a3, sp, 0x0c
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
/* Store instruction */
.LSA_store_op:
s32i a5, sp, 0x14
s32i a6, sp, 0x18
s32i a7, sp, 0x1c
/* a2 -> instruction that caused the error */
/* a3 -> unaligned address */
extui a4, a2, 4, 4
blti a4, 8, 1f
movi a5, .LSA_store_reg
addx8 a5, a4, a5
jx a5
1:
addx4 a4, a4, sp
l32i a4, a4, 0 // a4 contains the value
.LSA_store_data:
movi a6, 0
rsr a7, epc1
addi a7, a7 ,2
bbsi a2, 3, 1f // s32i.n
bbci a2, 1, .LS_wrong_opcode
addi a7, a7, 1
bbsi a2, 13, 1f // s32i
movi a5, -1
extui a4, a4, 0, 16
slli a6, a5, 16 // 0xffff0000
1:
wsr a7, epc1
movi a5, ~3
and a5, a3, a5 // a5 has the aligned address
ssa8b a3
movi a3, -1
src a7, a6, a3
src a3, a3, a6
/* Store data on lower address */
l32i a6, a5, 0
and a6, a6, a7
sll a7, a4
or a6, a6, a7
s32i a6, a5, 0
/* Store data on higher address */
l32i a7, a5, 4
srl a6, a4
and a3, a7, a3
or a3, a3, a6
s32i a3, a5, 4
/* Restore registers */
wsr a0, sar
rsr a0, excsave1
l32i a7, sp, 0x1c
l32i a6, sp, 0x18
l32i a5, sp, 0x14
l32i a4, sp, 0x10
l32i a3, sp, 0x0c
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.LSA_store_reg:
.org .LSA_store_reg + (8 * 8)
mov a4, a8
j .LSA_store_data
.org .LSA_store_reg + (9 * 8)
mov a4, a9
j .LSA_store_data
.org .LSA_store_reg + (10 * 8)
mov a4, a10
j .LSA_store_data
.org .LSA_store_reg + (11 * 8)
mov a4, a11
j .LSA_store_data
.org .LSA_store_reg + (12 * 8)
mov a4, a12
j .LSA_store_data
.org .LSA_store_reg + (13 * 8)
mov a4, a13
j .LSA_store_data
.org .LSA_store_reg + (14 * 8)
mov a4, a14
j .LSA_store_data
.org .LSA_store_reg + (15 * 8)
mov a4, a15
j .LSA_store_data
/*
* Common routines for both the exception handlers
*/
.balign 4
.LS_jumptable:
/* The first 5 entries (80 bytes) of this table are unused (registers
a0..a4 are handled separately above). Rather than have a whole bunch
of wasted space, just pretend that the table starts 80 bytes
earlier in memory. */
.set .LS_jumptable_base, .LS_jumptable - (16 * 5)
.org .LS_jumptable_base + (16 * 5)
mov a5, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 6)
mov a6, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 7)
mov a7, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 8)
mov a8, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 9)
mov a9, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 10)
mov a10, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 11)
mov a11, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 12)
mov a12, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 13)
mov a13, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 14)
mov a14, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.org .LS_jumptable_base + (16 * 15)
mov a15, a4
l32i a4, sp, 0x10
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rfe
.LS_wrong_opcode:
/* Reaches here if the address is in invalid range or the opcode isn't supported.
* Restore registers and jump back to _xt_user_exc
*/
wsr a0, sar
l32i a4, sp, 0x10
l32i a3, sp, 0x0c
l32i a2, sp, 0x08
l32i a1, sp, 0x04
rsr a0, depc
ret // Equivalent to jx a0
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 25,340 | portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S | /*
* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
*
* SPDX-License-Identifier: MIT
*
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
*/
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "xtensa_rtos.h"
#include "sdkconfig.h"
#include "esp_idf_version.h"
#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */
#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */
.extern pxCurrentTCB
/*
*******************************************************************************
* Interrupt stack. The size of the interrupt stack is determined by the config
* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
*******************************************************************************
*/
.data
.align 16
.global port_IntStack
.global port_IntStackTop
.global port_switch_flag
port_IntStack:
.space configISR_STACK_SIZE*portNUM_PROCESSORS /* This allocates stacks for each individual CPU. */
port_IntStackTop:
.word 0
port_switch_flag:
.space portNUM_PROCESSORS*4 /* One flag for each individual CPU. */
.text
/*
*******************************************************************************
* _frxt_setup_switch
* void _frxt_setup_switch(void);
*
* Sets an internal flag indicating that a task switch is required on return
* from interrupt handling.
*
*******************************************************************************
*/
.global _frxt_setup_switch
.type _frxt_setup_switch,@function
.align 4
_frxt_setup_switch:
ENTRY(16)
getcoreid a3
movi a2, port_switch_flag
addx4 a2, a3, a2
movi a3, 1
s32i a3, a2, 0
RET(16)
/*
*******************************************************************************
* _frxt_int_enter
* void _frxt_int_enter(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
* freeRTOS. Saves the rest of the interrupt context (not already saved).
* May only be called from assembly code by the 'call0' instruction, with
* interrupts disabled.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
*******************************************************************************
*/
.globl _frxt_int_enter
.type _frxt_int_enter,@function
.align 4
_frxt_int_enter:
/* Save a12-13 in the stack frame as required by _xt_context_save. */
s32i a12, a1, XT_STK_A12
s32i a13, a1, XT_STK_A13
/* Save return address in a safe place (free a0). */
mov a12, a0
/* Save the rest of the interrupted context (preserves A12-13). */
call0 _xt_context_save
/*
Save interrupted task's SP in TCB only if not nesting.
Manage nesting directly rather than call the generic IntEnter()
(in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
*/
getcoreid a4
movi a2, port_xSchedulerRunning
addx4 a2, a4, a2
movi a3, port_interruptNesting
addx4 a3, a4, a3
l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */
beqz a2, 1f /* scheduler not running, no tasks */
l32i a2, a3, 0 /* a2 = port_interruptNesting */
addi a2, a2, 1 /* increment nesting count */
s32i a2, a3, 0 /* save nesting count */
bnei a2, 1, .Lnested /* !=0 before incr, so nested */
movi a2, pxCurrentTCB
addx4 a2, a4, a2
l32i a2, a2, 0 /* a2 = current TCB */
beqz a2, 1f
s32i a1, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
movi a1, port_IntStack+configISR_STACK_SIZE /* a1 = top of intr stack for CPU 0 */
movi a2, configISR_STACK_SIZE /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */
mull a2, a4, a2
add a1, a1, a2 /* for current proc */
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef CONFIG_FREERTOS_FPU_IN_ISR
#if XCHAL_CP_NUM > 0
rsr a3, CPENABLE /* Restore thread scope CPENABLE */
addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */
s32i a3, a1, 0 /* its trigger */
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
.Lnested:
1:
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef CONFIG_FREERTOS_FPU_IN_ISR
#if XCHAL_CP_NUM > 0
movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */
wsr a3, CPENABLE
rsync
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
mov a0, a12 /* restore return addr and return */
ret
/*
*******************************************************************************
* _frxt_int_exit
* void _frxt_int_exit(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
* switching, restore the (possibly) new task's context, and return to the
* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
* May only be called from assembly code by the 'call0' instruction. Does not
* return to caller.
* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
*******************************************************************************
*/
.globl _frxt_int_exit
.type _frxt_int_exit,@function
.align 4
_frxt_int_exit:
getcoreid a4
movi a2, port_xSchedulerRunning
addx4 a2, a4, a2
movi a3, port_interruptNesting
addx4 a3, a4, a3
rsil a0, XCHAL_EXCM_LEVEL /* lock out interrupts */
l32i a2, a2, 0 /* a2 = port_xSchedulerRunning */
beqz a2, .Lnoswitch /* scheduler not running, no tasks */
l32i a2, a3, 0 /* a2 = port_interruptNesting */
addi a2, a2, -1 /* decrement nesting count */
s32i a2, a3, 0 /* save nesting count */
bnez a2, .Lnesting /* !=0 after decr so still nested */
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef CONFIG_FREERTOS_FPU_IN_ISR
#if XCHAL_CP_NUM > 0
l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */
addi sp, sp, 4
wsr a3, CPENABLE
rsync /* ensure CPENABLE was modified */
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
movi a2, pxCurrentTCB
addx4 a2, a4, a2
l32i a2, a2, 0 /* a2 = current TCB */
beqz a2, 1f /* no task ? go to dispatcher */
l32i a1, a2, TOPOFSTACK_OFFS /* SP = pxCurrentTCB->pxTopOfStack */
movi a2, port_switch_flag /* address of switch flag */
addx4 a2, a4, a2 /* point to flag for this cpu */
l32i a3, a2, 0 /* a3 = port_switch_flag */
beqz a3, .Lnoswitch /* flag = 0 means no switch reqd */
movi a3, 0
s32i a3, a2, 0 /* zero out the flag for next time */
1:
/*
Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
However a12-13 were already saved by _frxt_int_enter().
*/
#ifdef __XTENSA_CALL0_ABI__
s32i a14, a1, XT_STK_A14
s32i a15, a1, XT_STK_A15
#endif
#ifdef __XTENSA_CALL0_ABI__
call0 vPortYieldFromInt /* call dispatch inside the function; never returns */
#else
call4 vPortYieldFromInt /* this one returns */
call0 _frxt_dispatch /* tail-call dispatcher */
/* Never returns here. */
#endif
.Lnoswitch:
/*
If we came here then about to resume the interrupted task.
*/
.Lnesting:
/*
We come here only if there was no context switch, that is if this
is a nested interrupt, or the interrupted task was not preempted.
In either case there's no need to load the SP.
*/
/* Restore full context from interrupt stack frame */
call0 _xt_context_restore
/*
Must return via the exit dispatcher corresponding to the entrypoint from which
this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
stack frame is deallocated in the exit dispatcher.
*/
l32i a0, a1, XT_STK_EXIT
ret
/*
**********************************************************************************************************
* _frxt_timer_int
* void _frxt_timer_int(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
* Called every timer interrupt.
* Manages the tick timer and calls xPortSysTickHandler() every tick.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
*
**********************************************************************************************************
*/
#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
.globl _frxt_timer_int
.type _frxt_timer_int,@function
.align 4
_frxt_timer_int:
/*
Xtensa timers work by comparing a cycle counter with a preset value. Once the match occurs
an interrupt is generated, and the handler has to set a new cycle count into the comparator.
To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
than one tick late, it is necessary to process multiple ticks until the new cycle count is
in the future, otherwise the next timer interrupt would not occur until after the cycle
counter had wrapped (2^32 cycles later).
do {
ticks++;
old_ccompare = read_ccompare_i();
write_ccompare_i( old_ccompare + divisor );
service one tick;
diff = read_ccount() - old_ccompare;
} while ( diff > divisor );
*/
ENTRY(16)
#ifdef CONFIG_PM_TRACE
movi a6, 1 /* = ESP_PM_TRACE_TICK */
getcoreid a7
call4 esp_pm_trace_enter
#endif // CONFIG_PM_TRACE
.L_xt_timer_int_catchup:
/* Update the timer comparator for the next tick. */
#ifdef XT_CLOCK_FREQ
movi a2, XT_TICK_DIVISOR /* a2 = comparator increment */
#else
movi a3, _xt_tick_divisor
l32i a2, a3, 0 /* a2 = comparator increment */
#endif
rsr a3, XT_CCOMPARE /* a3 = old comparator value */
add a4, a3, a2 /* a4 = new comparator value */
wsr a4, XT_CCOMPARE /* update comp. and clear interrupt */
esync
#ifdef __XTENSA_CALL0_ABI__
/* Preserve a2 and a3 across C calls. */
s32i a2, sp, 4
s32i a3, sp, 8
#endif
/* Call the FreeRTOS tick handler (see port_systick.c). */
#ifdef __XTENSA_CALL0_ABI__
call0 xPortSysTickHandler
#else
call4 xPortSysTickHandler
#endif
#ifdef __XTENSA_CALL0_ABI__
/* Restore a2 and a3. */
l32i a2, sp, 4
l32i a3, sp, 8
#endif
/* Check if we need to process more ticks to catch up. */
esync /* ensure comparator update complete */
rsr a4, CCOUNT /* a4 = cycle count */
sub a4, a4, a3 /* diff = ccount - old comparator */
blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */
#ifdef CONFIG_PM_TRACE
movi a6, 1 /* = ESP_PM_TRACE_TICK */
getcoreid a7
call4 esp_pm_trace_exit
#endif // CONFIG_PM_TRACE
RET(16)
#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
/*
**********************************************************************************************************
* _frxt_tick_timer_init
* void _frxt_tick_timer_init(void)
*
* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
* Callable from C (obeys ABI conventions on entry).
*
**********************************************************************************************************
*/
#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
.globl _frxt_tick_timer_init
.type _frxt_tick_timer_init,@function
.align 4
_frxt_tick_timer_init:
ENTRY(16)
/* Set up the periodic tick timer (assume enough time to complete init). */
#ifdef XT_CLOCK_FREQ
movi a3, XT_TICK_DIVISOR
#else
movi a2, _xt_tick_divisor
l32i a3, a2, 0
#endif
rsr a2, CCOUNT /* current cycle count */
add a2, a2, a3 /* time of first timer interrupt */
wsr a2, XT_CCOMPARE /* set the comparator */
/*
Enable the timer interrupt at the device level. Don't write directly
to the INTENABLE register because it may be virtualized.
*/
#ifdef __XTENSA_CALL0_ABI__
movi a2, XT_TIMER_INTEN
call0 xt_ints_on
#else
movi a6, XT_TIMER_INTEN
call4 xt_ints_on
#endif
RET(16)
#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
/*
**********************************************************************************************************
* DISPATCH THE HIGH READY TASK
* void _frxt_dispatch(void)
*
* Switch context to the highest priority ready task, restore its state and dispatch control to it.
*
* This is a common dispatcher that acts as a shared exit path for all the context switch functions
* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
*
* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
* If restoring a task that was preempted, restores all state including the task's CPENABLE.
*
* Entry:
* pxCurrentTCB points to the TCB of the task to suspend,
* Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
*
* Exit:
* If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
* If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
*
**********************************************************************************************************
*/
.globl _frxt_dispatch
.type _frxt_dispatch,@function
.align 4
_frxt_dispatch:
#ifdef __XTENSA_CALL0_ABI__
call0 vTaskSwitchContext // Get next TCB to resume
movi a2, pxCurrentTCB
getcoreid a3
addx4 a2, a3, a2
#else
call4 vTaskSwitchContext // Get next TCB to resume
movi a2, pxCurrentTCB
getcoreid a3
addx4 a2, a3, a2
#endif
l32i a3, a2, 0
l32i sp, a3, TOPOFSTACK_OFFS /* SP = next_TCB->pxTopOfStack; */
s32i a3, a2, 0
/* Determine the type of stack frame. */
l32i a2, sp, XT_STK_EXIT /* exit dispatcher or solicited flag */
bnez a2, .L_frxt_dispatch_stk
.L_frxt_dispatch_sol:
/* Solicited stack frame. Restore minimal context and return from vPortYield(). */
#if XCHAL_HAVE_THREADPTR
l32i a2, sp, XT_SOL_THREADPTR
wur.threadptr a2
#endif
l32i a3, sp, XT_SOL_PS
#ifdef __XTENSA_CALL0_ABI__
l32i a12, sp, XT_SOL_A12
l32i a13, sp, XT_SOL_A13
l32i a14, sp, XT_SOL_A14
l32i a15, sp, XT_SOL_A15
#endif
l32i a0, sp, XT_SOL_PC
#if XCHAL_CP_NUM > 0
/* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
rsync
#endif
/* As soons as PS is restored, interrupts can happen. No need to sync PS. */
wsr a3, PS
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, XT_SOL_FRMSZ
ret
#else
retw
#endif
.L_frxt_dispatch_stk:
#if XCHAL_CP_NUM > 0
/* Restore CPENABLE from task's co-processor save area. */
movi a3, pxCurrentTCB /* cp_state = */
getcoreid a2
addx4 a3, a2, a3
l32i a3, a3, 0
l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */
l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */
wsr a3, CPENABLE
#endif
/* Interrupt stack frame. Restore full context and return to exit dispatcher. */
call0 _xt_context_restore
/* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
#ifdef __XTENSA_CALL0_ABI__
l32i a14, sp, XT_STK_A14
l32i a15, sp, XT_STK_A15
#endif
#if XCHAL_CP_NUM > 0
/* Ensure wsr.CPENABLE has completed. */
rsync
#endif
/*
Must return via the exit dispatcher corresponding to the entrypoint from which
this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
stack frame is deallocated in the exit dispatcher.
*/
l32i a0, sp, XT_STK_EXIT
ret
/*
**********************************************************************************************************
* PERFORM A SOLICTED CONTEXT SWITCH (from a task)
* void vPortYield(void)
*
* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
*
* At Entry:
* pxCurrentTCB points to the TCB of the task to suspend
* Callable from C (obeys ABI conventions on entry).
*
* Does not return to caller.
*
**********************************************************************************************************
*/
.globl vPortYield
.type vPortYield,@function
.align 4
vPortYield:
#ifdef __XTENSA_CALL0_ABI__
addi sp, sp, -XT_SOL_FRMSZ
#else
entry sp, XT_SOL_FRMSZ
#endif
rsr a2, PS
s32i a0, sp, XT_SOL_PC
s32i a2, sp, XT_SOL_PS
#if XCHAL_HAVE_THREADPTR
rur.threadptr a2
s32i a2, sp, XT_SOL_THREADPTR
#endif
#ifdef __XTENSA_CALL0_ABI__
s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */
s32i a13, sp, XT_SOL_A13
s32i a14, sp, XT_SOL_A14
s32i a15, sp, XT_SOL_A15
#else
/* Spill register windows. Calling xthal_window_spill() causes extra */
/* spills and reloads, so we will set things up to call the _nw version */
/* instead to save cycles. */
movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */
and a2, a2, a6 /* clear WOE, INTLEVEL */
addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */
wsr a2, PS
rsync
call0 xthal_window_spill_nw
l32i a2, sp, XT_SOL_PS /* restore PS */
wsr a2, PS
#endif
rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */
#if XCHAL_CP_NUM > 0
/* Save coprocessor callee-saved state (if any). At this point CPENABLE */
/* should still reflect which CPs were in use (enabled). */
call0 _xt_coproc_savecs
#endif
movi a2, pxCurrentTCB
getcoreid a3
addx4 a2, a3, a2
l32i a2, a2, 0 /* a2 = pxCurrentTCB */
movi a3, 0
s32i a3, sp, XT_SOL_EXIT /* 0 to flag as solicited frame */
s32i sp, a2, TOPOFSTACK_OFFS /* pxCurrentTCB->pxTopOfStack = SP */
#if XCHAL_CP_NUM > 0
/* Clear CPENABLE, also in task's co-processor state save area. */
l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state */
movi a3, 0
wsr a3, CPENABLE
beqz a2, 1f
s16i a3, a2, XT_CPENABLE /* clear saved cpenable */
1:
#endif
/* Tail-call dispatcher. */
call0 _frxt_dispatch
/* Never reaches here. */
/*
**********************************************************************************************************
* PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
* void vPortYieldFromInt(void)
*
* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
* _frxt_dispatch() to perform the actual context switch.
*
* At Entry:
* Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
* pxCurrentTCB points to the TCB of the task to suspend,
* Callable from C (obeys ABI conventions on entry).
*
* At Exit:
* Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
* Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
*
**********************************************************************************************************
*/
.globl vPortYieldFromInt
.type vPortYieldFromInt,@function
.align 4
vPortYieldFromInt:
ENTRY(16)
#if XCHAL_CP_NUM > 0
/* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */
movi a3, pxCurrentTCB /* cp_state = */
getcoreid a2
addx4 a3, a2, a3
l32i a3, a3, 0
l32i a2, a3, CP_TOPOFSTACK_OFFS
rsr a3, CPENABLE
s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */
movi a3, 0
wsr a3, CPENABLE /* disable all co-processors */
#endif
#ifdef __XTENSA_CALL0_ABI__
/* Tail-call dispatcher. */
call0 _frxt_dispatch
/* Never reaches here. */
#else
RET(16)
#endif
/*
**********************************************************************************************************
* _frxt_task_coproc_state
* void _frxt_task_coproc_state(void)
*
* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
*
* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
*
**********************************************************************************************************
*/
#if XCHAL_CP_NUM > 0
.globl _frxt_task_coproc_state
.type _frxt_task_coproc_state,@function
.align 4
_frxt_task_coproc_state:
/* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */
getcoreid a3
movi a15, port_xSchedulerRunning /* if (port_xSchedulerRunning */
addx4 a15, a3,a15
l32i a15, a15, 0
beqz a15, 1f
movi a15, port_interruptNesting /* && port_interruptNesting == 0 */
addx4 a15, a3, a15
l32i a15, a15, 0
bnez a15, 1f
movi a15, pxCurrentTCB
addx4 a15, a3, a15
l32i a15, a15, 0 /* && pxCurrentTCB != 0) { */
beqz a15, 2f
l32i a15, a15, CP_TOPOFSTACK_OFFS
ret
1: movi a15, 0
2: ret
#endif /* XCHAL_CP_NUM > 0 */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 6,252 | portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S | /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "xtensa_rtos.h"
#include "esp_idf_version.h"
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
#include "esp_panic.h"
#else
#include "esp_private/panic_reason.h"
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
#include "sdkconfig.h"
#include "soc/soc.h"
/*
This file contains the default handlers for the high interrupt levels as well as some specialized exceptions.
The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
*/
#if XCHAL_HAVE_DEBUG
.global xt_debugexception
.weak xt_debugexception
.set xt_debugexception, _xt_debugexception
.section .iram1,"ax"
.type _xt_debugexception,@function
.align 4
_xt_debugexception:
#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#define XT_DEBUGCAUSE_DI (5)
getcoreid a0
#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM)
beqz a0, 1f
#else
bnez a0, 1f
#endif
rsr a0, DEBUGCAUSE
extui a0, a0, XT_DEBUGCAUSE_DI, 1
bnez a0, _xt_debug_di_exc
1:
#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
movi a0,PANIC_RSN_DEBUGEXCEPTION
wsr a0,EXCCAUSE
/* _xt_panic assumes a level 1 exception. As we're
crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
to level 1. */
rsr a0,(EPC + XCHAL_DEBUGLEVEL)
wsr a0,EPC_1
rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL)
wsr a0,EXCSAVE_1
call0 _xt_panic /* does not return */
rfi XCHAL_DEBUGLEVEL
#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
.align 4
_xt_debug_di_exc:
/*
The delay time can be calculated by the following formula:
T = ceil(0.25 + max(t1, t2)) us
t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2
f1: PSRAM access frequency, unit: MHz.
f2: Flash access frequency, unit: MHz.
When flash is slow/fast read, N = 1.
When flash is DOUT/DIO read, N = 2.
When flash is QOUT/QIO read, N = 4.
And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times.
*/
#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
movi a0, 54
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
movi a0, 81
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
movi a0, 81
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
movi a0, 108
# else
movi a0, 135
# endif
#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
movi a0, 81
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
movi a0, 81
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
movi a0, 135
# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
movi a0, 189
# else
movi a0, 243
# endif
#else
movi a0, 243
#endif
1: addi a0, a0, -1 /* delay_us(N) */
.rept 4
nop
.endr
bnez a0, 1b
rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL
rfi XCHAL_DEBUGLEVEL
#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#endif /* Debug exception */
#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
.global xt_highint2
.weak xt_highint2
.set xt_highint2, _xt_highint2
.section .iram1,"ax"
.type _xt_highint2,@function
.align 4
_xt_highint2:
/* Default handler does nothing; just returns */
.align 4
.L_xt_highint2_exit:
rsr a0, EXCSAVE_2 /* restore a0 */
rfi 2
#endif /* Level 2 */
#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
.global xt_highint3
.weak xt_highint3
.set xt_highint3, _xt_highint3
.section .iram1,"ax"
.type _xt_highint3,@function
.align 4
_xt_highint3:
/* Default handler does nothing; just returns */
.align 4
.L_xt_highint3_exit:
rsr a0, EXCSAVE_3 /* restore a0 */
rfi 3
#endif /* Level 3 */
#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
.global xt_highint4
.weak xt_highint4
.set xt_highint4, _xt_highint4
.section .iram1,"ax"
.type _xt_highint4,@function
.align 4
_xt_highint4:
/* Default handler does nothing; just returns */
.align 4
.L_xt_highint4_exit:
rsr a0, EXCSAVE_4 /* restore a0 */
rfi 4
#endif /* Level 4 */
#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
.global xt_highint5
.weak xt_highint5
.set xt_highint5, _xt_highint5
.section .iram1,"ax"
.type _xt_highint5,@function
.align 4
_xt_highint5:
/* Default handler does nothing; just returns */
.align 4
.L_xt_highint5_exit:
rsr a0, EXCSAVE_5 /* restore a0 */
rfi 5
#endif /* Level 5 */
#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
.global _xt_highint6
.global xt_highint6
.weak xt_highint6
.set xt_highint6, _xt_highint6
.section .iram1,"ax"
.type _xt_highint6,@function
.align 4
_xt_highint6:
/* Default handler does nothing; just returns */
.align 4
.L_xt_highint6_exit:
rsr a0, EXCSAVE_6 /* restore a0 */
rfi 6
#endif /* Level 6 */
#if XCHAL_HAVE_NMI
.global _xt_nmi
.global xt_nmi
.weak xt_nmi
.set xt_nmi, _xt_nmi
.section .iram1,"ax"
.type _xt_nmi,@function
.align 4
_xt_nmi:
/* Default handler does nothing; just returns */
.align 4
.L_xt_nmi_exit:
rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */
rfi XCHAL_NMILEVEL
#endif /* NMI */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 81,278 | portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S | /*
* SPDX-FileCopyrightText: 2015-2019 Cadence Design Systems, Inc.
*
* SPDX-License-Identifier: MIT
*
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
*/
/*
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*******************************************************************************
--------------------------------------------------------------------------------
XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
Xtensa low level exception and interrupt vectors and handlers for an RTOS.
Interrupt handlers and user exception handlers support interaction with
the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
after user's specific interrupt handlers. These macros are defined in
xtensa_<rtos>.h to call suitable functions in a specific RTOS.
Users can install application-specific interrupt handlers for low and
medium level interrupts, by calling xt_set_interrupt_handler(). These
handlers can be written in C, and must obey C calling convention. The
handler table is indexed by the interrupt number. Each handler may be
provided with an argument.
Note that the system timer interrupt is handled specially, and is
dispatched to the RTOS-specific handler. This timer cannot be hooked
by application code.
Optional hooks are also provided to install a handler per level at
run-time, made available by compiling this source file with
'-DXT_INTEXC_HOOKS' (useful for automated testing).
!! This file is a template that usually needs to be modified to handle !!
!! application specific interrupts. Search USER_EDIT for helpful comments !!
!! on where to insert handlers and how to write them. !!
Users can also install application-specific exception handlers in the
same way, by calling xt_set_exception_handler(). One handler slot is
provided for each exception type. Note that some exceptions are handled
by the porting layer itself, and cannot be taken over by application
code in this manner. These are the alloca, syscall, and coprocessor
exceptions.
The exception handlers can be written in C, and must follow C calling
convention. Each handler is passed a pointer to an exception frame as
its single argument. The exception frame is created on the stack, and
holds the saved context of the thread that took the exception. If the
handler returns, the context will be restored and the instruction that
caused the exception will be retried. If the handler makes any changes
to the saved state in the exception frame, the changes will be applied
when restoring the context.
Because Xtensa is a configurable architecture, this port supports all user
generated configurations (except restrictions stated in the release notes).
This is accomplished by conditional compilation using macros and functions
defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
Only the relevant parts of this file will be included in your RTOS build.
For example, this file provides interrupt vector templates for all types and
all priority levels, but only the ones in your configuration are built.
NOTES on the use of 'call0' for long jumps instead of 'j':
1. This file should be assembled with the -mlongcalls option to xt-xcc.
2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
distance from the call to the destination. The linker then relaxes
it back to 'call0 dest' if it determines that dest is within range.
This allows more flexibility in locating code without the performance
overhead of the 'l32r' literal data load in cases where the destination
is in range of 'call0'. There is an additional benefit in that 'call0'
has a longer range than 'j' due to the target being word-aligned, so
the 'l32r' sequence is less likely needed.
3. The use of 'call0' with -mlongcalls requires that register a0 not be
live at the time of the call, which is always the case for a function
call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
4. This use of 'call0' is independent of the C function call ABI.
*******************************************************************************/
#include "xtensa_rtos.h"
#include "esp_idf_version.h"
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
#include "esp_panic.h"
#else
#include "esp_private/panic_reason.h"
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
#include "sdkconfig.h"
#include "soc/soc.h"
/*
Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
Please change this when the tcb structure is changed
*/
#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3
.extern pxCurrentTCB
/*
--------------------------------------------------------------------------------
In order for backtracing to be able to trace from the pre-exception stack
across to the exception stack (including nested interrupts), we need to create
a pseudo base-save area to make it appear like the exception dispatcher was
triggered by a CALL4 from the pre-exception code. In reality, the exception
dispatcher uses the same window as pre-exception code, and only CALL0s are
used within the exception dispatcher.
To create the pseudo base-save area, we need to store a copy of the pre-exception's
base save area (a0 to a4) below the exception dispatcher's SP. EXCSAVE_x will
be used to store a copy of the SP that points to the interrupted code's exception
frame just in case the exception dispatcher's SP does not point to the exception
frame (which is the case when switching from task to interrupt stack).
Clearing the pseudo base-save area is uncessary as the interrupt dispatcher
will restore the current SP to that of the pre-exception SP.
--------------------------------------------------------------------------------
*/
#ifdef CONFIG_FREERTOS_INTERRUPT_BACKTRACE
#define XT_DEBUG_BACKTRACE 1
#endif
/*
--------------------------------------------------------------------------------
Defines used to access _xtos_interrupt_table.
--------------------------------------------------------------------------------
*/
#define XIE_HANDLER 0
#define XIE_ARG 4
#define XIE_SIZE 8
/*
Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
Basically does reg=reg*portNUM_PROCESSORS+current_core_id
Multiple versions here to optimize for specific portNUM_PROCESSORS values.
*/
.macro get_percpu_entry_for reg scratch
#if (portNUM_PROCESSORS == 1)
/* No need to do anything */
#elif (portNUM_PROCESSORS == 2)
/* Optimized 2-core code. */
getcoreid \scratch
addx2 \reg,\reg,\scratch
#else
/* Generalized n-core code. Untested! */
movi \scratch,portNUM_PROCESSORS
mull \scratch,\reg,\scratch
getcoreid \reg
add \reg,\scratch,\reg
#endif
.endm
/*
--------------------------------------------------------------------------------
Macro extract_msb - return the input with only the highest bit set.
Input : "ain" - Input value, clobbered.
Output : "aout" - Output value, has only one bit set, MSB of "ain".
The two arguments must be different AR registers.
--------------------------------------------------------------------------------
*/
.macro extract_msb aout ain
1:
addi \aout, \ain, -1 /* aout = ain - 1 */
and \ain, \ain, \aout /* ain = ain & aout */
bnez \ain, 1b /* repeat until ain == 0 */
addi \aout, \aout, 1 /* return aout + 1 */
.endm
/*
--------------------------------------------------------------------------------
Macro dispatch_c_isr - dispatch interrupts to user ISRs.
This will dispatch to user handlers (if any) that are registered in the
XTOS dispatch table (_xtos_interrupt_table). These handlers would have
been registered by calling _xtos_set_interrupt_handler(). There is one
exception - the timer interrupt used by the OS will not be dispatched
to a user handler - this must be handled by the caller of this macro.
Level triggered and software interrupts are automatically deasserted by
this code.
ASSUMPTIONS:
-- PS.INTLEVEL is set to "level" at entry
-- PS.EXCM = 0, C calling enabled
NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
NOTE: This macro will use registers a0 and a2-a7. The arguments are:
level -- interrupt level
mask -- interrupt bitmask for this level
--------------------------------------------------------------------------------
*/
.macro dispatch_c_isr level mask
#ifdef CONFIG_PM_TRACE
movi a6, 0 /* = ESP_PM_TRACE_IDLE */
getcoreid a7
call4 esp_pm_trace_exit
#endif // CONFIG_PM_TRACE
/* Get mask of pending, enabled interrupts at this level into a2. */
.L_xt_user_int_&level&:
rsr a2, INTENABLE
rsr a3, INTERRUPT
movi a4, \mask
and a2, a2, a3
and a2, a2, a4
beqz a2, 9f /* nothing to do */
/* This bit of code provides a nice debug backtrace in the debugger.
It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
if you want to save the cycles.
At this point, the exception frame should have been allocated and filled,
and current sp points to the interrupt stack (for non-nested interrupt)
or below the allocated exception frame (for nested interrupts). Copy the
pre-exception's base save area below the current SP.
*/
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
rsr a0, EXCSAVE_1 + \level - 1 /* Get exception frame pointer stored in EXCSAVE_x */
l32i a3, a0, XT_STK_A0 /* Copy pre-exception a0 (return address) */
s32e a3, a1, -16
l32i a3, a0, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */
s32e a3, a1, -12
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Backtracing only needs a0 and a1, no need to create full base save area.
Also need to change current frame's return address to point to pre-exception's
last run instruction.
*/
rsr a0, EPC_1 + \level - 1 /* return address */
movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */
or a0, a0, a4 /* set top 2 bits */
addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */
#endif
#endif
#ifdef CONFIG_PM_ENABLE
call4 esp_pm_impl_isr_hook
#endif
#ifdef XT_INTEXC_HOOKS
/* Call interrupt hook if present to (pre)handle interrupts. */
movi a4, _xt_intexc_hooks
l32i a4, a4, \level << 2
beqz a4, 2f
#ifdef __XTENSA_CALL0_ABI__
callx0 a4
beqz a2, 9f
#else
mov a6, a2
callx4 a4
beqz a6, 9f
mov a2, a6
#endif
2:
#endif
/* Now look up in the dispatch table and call user ISR if any. */
/* If multiple bits are set then MSB has highest priority. */
extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */
#ifdef XT_USE_SWPRI
/* Enable all interrupts at this level that are numerically higher
than the one we just selected, since they are treated as higher
priority.
*/
movi a3, \mask /* a3 = all interrupts at this level */
add a2, a4, a4 /* a2 = a4 << 1 */
addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */
and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */
movi a3, _xt_intdata
l32i a6, a3, 4 /* a6 = _xt_vpri_mask */
neg a2, a2
addi a2, a2, -1 /* a2 = mask to apply */
and a5, a6, a2 /* mask off all bits <= a4 bit */
s32i a5, a3, 4 /* update _xt_vpri_mask */
rsr a3, INTENABLE
and a3, a3, a2 /* mask off all bits <= a4 bit */
wsr a3, INTENABLE
rsil a3, \level - 1 /* lower interrupt level by 1 */
#endif
#ifdef XT_RTOS_TIMER_INT
movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */
wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */
beq a3, a4, 7f /* if timer interrupt then skip table */
#else
wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */
#endif // XT_RTOS_TIMER_INT
find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */
get_percpu_entry_for a3, a12
movi a4, _xt_interrupt_table
addx8 a3, a3, a4 /* a3 = address of interrupt table entry */
l32i a4, a3, XIE_HANDLER /* a4 = handler address */
#ifdef __XTENSA_CALL0_ABI__
mov a12, a6 /* save in callee-saved reg */
l32i a2, a3, XIE_ARG /* a2 = handler arg */
callx0 a4 /* call handler */
mov a2, a12
#else
mov a2, a6 /* save in windowed reg */
l32i a6, a3, XIE_ARG /* a6 = handler arg */
callx4 a4 /* call handler */
#endif
#ifdef XT_USE_SWPRI
j 8f
#else
j .L_xt_user_int_&level& /* check for more interrupts */
#endif
#ifdef XT_RTOS_TIMER_INT
7:
.ifeq XT_TIMER_INTPRI - \level
.L_xt_user_int_timer_&level&:
/*
Interrupt handler for the RTOS tick timer if at this level.
We'll be reading the interrupt state again after this call
so no need to preserve any registers except a6 (vpri_mask).
*/
#ifdef __XTENSA_CALL0_ABI__
mov a12, a6
call0 XT_RTOS_TIMER_INT
mov a2, a12
#else
mov a2, a6
call4 XT_RTOS_TIMER_INT
#endif
.endif
#endif // XT_RTOS_TIMER_INT
#ifdef XT_USE_SWPRI
j 8f
#else
j .L_xt_user_int_&level& /* check for more interrupts */
#endif
#ifdef XT_USE_SWPRI
8:
/* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
virtual _xt_intenable which _could_ have changed during interrupt
processing. */
movi a3, _xt_intdata
l32i a4, a3, 0 /* a4 = _xt_intenable */
s32i a2, a3, 4 /* update _xt_vpri_mask */
and a4, a4, a2 /* a4 = masked intenable */
wsr a4, INTENABLE /* update INTENABLE */
#endif
9:
/* done */
.endm
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
/*
--------------------------------------------------------------------------------
Panic handler.
Should be reached by call0 (preferable) or jump only. If call0, a0 says where
from. If on simulator, display panic message and abort, else loop indefinitely.
--------------------------------------------------------------------------------
*/
.section .iram1,"ax"
.global panicHandler
.global _xt_panic
.type _xt_panic,@function
.align 4
.literal_position
.align 4
_xt_panic:
/* Allocate exception frame and save minimal context. */
mov a0, sp
addi sp, sp, -XT_STK_FRMSZ
s32i a0, sp, XT_STK_A1
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
#endif
s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
call0 _xt_context_save
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
/* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
wsr a0, PS
//Call panic handler
mov a6,sp
call4 panicHandler
.align 4
//Call using call0. Prints the hex char in a2. Kills a3, a4, a5
panic_print_hex:
movi a3,0x60000000
movi a4,8
panic_print_hex_loop:
l32i a5, a3, 0x1c
extui a5, a5, 16, 8
bgei a5,64,panic_print_hex_loop
srli a5,a2,28
bgei a5,10,panic_print_hex_a
addi a5,a5,'0'
j panic_print_hex_ok
panic_print_hex_a:
addi a5,a5,'A'-10
panic_print_hex_ok:
s32i a5,a3,0
slli a2,a2,4
addi a4,a4,-1
bnei a4,0,panic_print_hex_loop
movi a5,' '
s32i a5,a3,0
ret
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
.section .rodata, "a"
.align 4
/*
--------------------------------------------------------------------------------
Hooks to dynamically install handlers for exceptions and interrupts.
Allows automated regression frameworks to install handlers per test.
Consists of an array of function pointers indexed by interrupt level,
with index 0 containing the entry for user exceptions.
Initialized with all 0s, meaning no handler is installed at each level.
See comment in xtensa_rtos.h for more details.
*WARNING* This array is for all CPUs, that is, installing a hook for
one CPU will install it for all others as well!
--------------------------------------------------------------------------------
*/
#ifdef XT_INTEXC_HOOKS
.data
.global _xt_intexc_hooks
.type _xt_intexc_hooks,@object
.align 4
_xt_intexc_hooks:
.fill XT_INTEXC_HOOK_NUM, 4, 0
#endif
/*
--------------------------------------------------------------------------------
EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
(except window exception vectors).
Each vector goes at a predetermined location according to the Xtensa
hardware configuration, which is ensured by its placement in a special
section known to the Xtensa linker support package (LSP). It performs
the minimum necessary before jumping to the handler in the .text section.
The corresponding handler goes in the normal .text section. It sets up
the appropriate stack frame, saves a few vector-specific registers and
calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
and enter the RTOS, then sets up a C environment. It then calls the
user's interrupt handler code (which may be coded in C) and finally
calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
While XT_RTOS_INT_EXIT does not return directly to the interruptee,
eventually the RTOS scheduler will want to dispatch the interrupted
task or handler. The scheduler will return to the exit point that was
saved in the interrupt stack frame at XT_STK_EXIT.
--------------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------------
Debug Exception.
--------------------------------------------------------------------------------
*/
#if XCHAL_HAVE_DEBUG
.begin literal_prefix .DebugExceptionVector
.section .DebugExceptionVector.text, "ax"
.global _DebugExceptionVector
.align 4
.global xt_debugexception
_DebugExceptionVector:
wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* preserve a0 */
call0 xt_debugexception /* load exception handler */
.end literal_prefix
#endif
/*
--------------------------------------------------------------------------------
Double Exception.
Double exceptions are not a normal occurrence. They indicate a bug of some kind.
--------------------------------------------------------------------------------
*/
#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
.begin literal_prefix .DoubleExceptionVector
.section .DoubleExceptionVector.text, "ax"
.global _DoubleExceptionVector
.align 4
_DoubleExceptionVector:
#if XCHAL_HAVE_DEBUG
break 1, 4 /* unhandled double exception */
#endif
movi a0,PANIC_RSN_DOUBLEEXCEPTION
wsr a0,EXCCAUSE
call0 _xt_panic /* does not return */
rfde /* make a0 point here not later */
.end literal_prefix
#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
/*
--------------------------------------------------------------------------------
Kernel Exception (including Level 1 Interrupt from kernel mode).
--------------------------------------------------------------------------------
*/
.begin literal_prefix .KernelExceptionVector
.section .KernelExceptionVector.text, "ax"
.global _KernelExceptionVector
.align 4
_KernelExceptionVector:
wsr a0, EXCSAVE_1 /* preserve a0 */
call0 _xt_kernel_exc /* kernel exception handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.section .iram1,"ax"
.align 4
_xt_kernel_exc:
#if XCHAL_HAVE_DEBUG
break 1, 0 /* unhandled kernel exception */
#endif
movi a0,PANIC_RSN_KERNELEXCEPTION
wsr a0,EXCCAUSE
call0 _xt_panic /* does not return */
rfe /* make a0 point here not there */
/*
--------------------------------------------------------------------------------
User Exception (including Level 1 Interrupt from user mode).
--------------------------------------------------------------------------------
*/
.begin literal_prefix .UserExceptionVector
.section .UserExceptionVector.text, "ax"
.global _UserExceptionVector
.type _UserExceptionVector,@function
.align 4
_UserExceptionVector:
wsr a0, EXCSAVE_1 /* preserve a0 */
call0 _xt_user_exc /* user exception handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
/*
--------------------------------------------------------------------------------
Insert some waypoints for jumping beyond the signed 8-bit range of
conditional branch instructions, so the conditional branchces to specific
exception handlers are not taken in the mainline. Saves some cycles in the
mainline.
--------------------------------------------------------------------------------
*/
#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
.global LoadStoreErrorHandler
.global AlignmentErrorHandler
#endif
.section .iram1,"ax"
#if XCHAL_HAVE_WINDOWED
.align 4
_xt_to_alloca_exc:
call0 _xt_alloca_exc /* in window vectors section */
/* never returns here - call0 is used as a jump (see note at top) */
#endif
.align 4
_xt_to_syscall_exc:
call0 _xt_syscall_exc
/* never returns here - call0 is used as a jump (see note at top) */
#if XCHAL_CP_NUM > 0
.align 4
_xt_to_coproc_exc:
call0 _xt_coproc_exc
/* never returns here - call0 is used as a jump (see note at top) */
#endif
#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
.align 4
_call_loadstore_handler:
call0 LoadStoreErrorHandler
/* This will return only if wrong opcode or address out of range*/
j .LS_exit
.align 4
_call_alignment_handler:
call0 AlignmentErrorHandler
/* This will return only if wrong opcode or address out of range*/
addi a0, a0, 1
j .LS_exit
#endif
/*
--------------------------------------------------------------------------------
User exception handler.
--------------------------------------------------------------------------------
*/
.type _xt_user_exc,@function
.align 4
_xt_user_exc:
/* If level 1 interrupt then jump to the dispatcher */
rsr a0, EXCCAUSE
beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
/* Handle any coprocessor exceptions. Rely on the fact that exception
numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
*/
#if XCHAL_CP_NUM > 0
bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
#endif
/* Handle alloca and syscall exceptions */
#if XCHAL_HAVE_WINDOWED
beqi a0, EXCCAUSE_ALLOCA, _xt_to_alloca_exc
#endif
beqi a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
beqi a0, EXCCAUSE_LOAD_STORE_ERROR, _call_loadstore_handler
addi a0, a0, -1
beqi a0, 8, _call_alignment_handler
addi a0, a0, 1
.LS_exit:
#endif
/* Handle all other exceptions. All can have user-defined handlers. */
/* NOTE: we'll stay on the user stack for exception handling. */
/* Allocate exception frame and save minimal context. */
mov a0, sp
addi sp, sp, -XT_STK_FRMSZ
s32i a0, sp, XT_STK_A1
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
#endif
s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
call0 _xt_context_save
/* Save exc cause and vaddr into exception frame */
rsr a0, EXCCAUSE
s32i a0, sp, XT_STK_EXCCAUSE
rsr a0, EXCVADDR
s32i a0, sp, XT_STK_EXCVADDR
/* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
/* Set up PS for C, reenable debug and NMI interrupts, and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 2) | PS_UM
#else
movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 2) | PS_UM | PS_WOE
#endif
wsr a0, PS
/*
Create pseudo base save area. At this point, sp is still pointing to the
allocated and filled exception stack frame.
*/
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
l32i a3, sp, XT_STK_A0 /* Copy pre-exception a0 (return address) */
s32e a3, sp, -16
l32i a3, sp, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */
s32e a3, sp, -12
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
rsr a0, EPC_1 /* return address for debug backtrace */
movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */
rsync /* wait for WSR.PS to complete */
or a0, a0, a5 /* set top 2 bits */
addx2 a0, a5, a0 /* clear top bit -- thus simulating call4 size */
#else
rsync /* wait for WSR.PS to complete */
#endif
#endif
rsr a2, EXCCAUSE /* recover exc cause */
#ifdef XT_INTEXC_HOOKS
/*
Call exception hook to pre-handle exceptions (if installed).
Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
*/
movi a4, _xt_intexc_hooks
l32i a4, a4, 0 /* user exception hook index 0 */
beqz a4, 1f
.Ln_xt_user_exc_call_hook:
#ifdef __XTENSA_CALL0_ABI__
callx0 a4
beqi a2, -1, .L_xt_user_done
#else
mov a6, a2
callx4 a4
beqi a6, -1, .L_xt_user_done
mov a2, a6
#endif
1:
#endif
rsr a2, EXCCAUSE /* recover exc cause */
movi a3, _xt_exception_table
get_percpu_entry_for a2, a4
addx4 a4, a2, a3 /* a4 = address of exception table entry */
l32i a4, a4, 0 /* a4 = handler address */
#ifdef __XTENSA_CALL0_ABI__
mov a2, sp /* a2 = pointer to exc frame */
callx0 a4 /* call handler */
#else
mov a6, sp /* a6 = pointer to exc frame */
callx4 a4 /* call handler */
#endif
.L_xt_user_done:
/* Restore context and return */
call0 _xt_context_restore
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, PS
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_1
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove exception frame */
rsync /* ensure PS and EPC written */
rfe /* PS.EXCM is cleared */
/*
--------------------------------------------------------------------------------
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
--------------------------------------------------------------------------------
*/
.global _xt_user_exit
.type _xt_user_exit,@function
.align 4
_xt_user_exit:
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, PS
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_1
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure PS and EPC written */
rfe /* PS.EXCM is cleared */
/*
--------------------------------------------------------------------------------
Syscall Exception Handler (jumped to from User Exception Handler).
Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
--------------------------------------------------------------------------------
*/
.section .iram1,"ax"
.type _xt_syscall_exc,@function
.align 4
_xt_syscall_exc:
#ifdef __XTENSA_CALL0_ABI__
/*
Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
Use a minimal stack frame (16B) to save A2 & A3 for scratch.
PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
rsr a0, PS
addi a0, a0, -PS_EXCM_MASK
wsr a0, PS
*/
addi sp, sp, -16
s32i a2, sp, 8
s32i a3, sp, 12
#else /* Windowed ABI */
/*
Save necessary context and spill the register windows.
PS.EXCM is still set and must remain set until after the spill.
Reuse context save function though it saves more than necessary.
For this reason, a full interrupt stack frame is allocated.
*/
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a12, sp, XT_STK_A12 /* _xt_context_save requires A12- */
s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */
call0 _xt_context_save
#endif
/*
Grab the interruptee's PC and skip over the 'syscall' instruction.
If it's at the end of a zero-overhead loop and it's not on the last
iteration, decrement loop counter and skip to beginning of loop.
*/
rsr a2, EPC_1 /* a2 = PC of 'syscall' */
addi a3, a2, 3 /* ++PC */
#if XCHAL_HAVE_LOOPS
rsr a0, LEND /* if (PC == LEND */
bne a3, a0, 1f
rsr a0, LCOUNT /* && LCOUNT != 0) */
beqz a0, 1f /* { */
addi a0, a0, -1 /* --LCOUNT */
rsr a3, LBEG /* PC = LBEG */
wsr a0, LCOUNT /* } */
#endif
1: wsr a3, EPC_1 /* update PC */
/* Restore interruptee's context and return from exception. */
#ifdef __XTENSA_CALL0_ABI__
l32i a2, sp, 8
l32i a3, sp, 12
addi sp, sp, 16
#else
call0 _xt_context_restore
addi sp, sp, XT_STK_FRMSZ
#endif
movi a0, -1
movnez a2, a0, a2 /* return -1 if not syscall 0 */
rsr a0, EXCSAVE_1
rfe
/*
--------------------------------------------------------------------------------
Co-Processor Exception Handler (jumped to from User Exception Handler).
These exceptions are generated by co-processor instructions, which are only
allowed in thread code (not in interrupts or kernel code). This restriction is
deliberately imposed to reduce the burden of state-save/restore in interrupts.
--------------------------------------------------------------------------------
*/
#if XCHAL_CP_NUM > 0
.section .rodata, "a"
/* Offset to CP n save area in thread's CP save area. */
.global _xt_coproc_sa_offset
.type _xt_coproc_sa_offset,@object
.align 16 /* minimize crossing cache boundaries */
_xt_coproc_sa_offset:
.word XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
.word XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
/* Bitmask for CP n's CPENABLE bit. */
.type _xt_coproc_mask,@object
.align 16,,8 /* try to keep it all in one cache line */
.set i, 0
_xt_coproc_mask:
.rept XCHAL_CP_MAX
.long (i<<16) | (1<<i) // upper 16-bits = i, lower = bitmask
.set i, i+1
.endr
.data
/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */
.global _xt_coproc_owner_sa
.type _xt_coproc_owner_sa,@object
.align 16,,XCHAL_CP_MAX<<2 /* minimize crossing cache boundaries */
_xt_coproc_owner_sa:
.space (XCHAL_CP_MAX * portNUM_PROCESSORS) << 2
.section .iram1,"ax"
.align 4
.L_goto_invalid:
j .L_xt_coproc_invalid /* not in a thread (invalid) */
.align 4
.L_goto_done:
j .L_xt_coproc_done
/*
--------------------------------------------------------------------------------
Coprocessor exception handler.
At entry, only a0 has been saved (in EXCSAVE_1).
--------------------------------------------------------------------------------
*/
.type _xt_coproc_exc,@function
.align 4
_xt_coproc_exc:
/* Allocate interrupt stack frame and save minimal context. */
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -12 /* for debug backtrace */
#endif
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
#if XCHAL_HAVE_WINDOWED
s32e a0, sp, -16 /* for debug backtrace */
#endif
movi a0, _xt_user_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
rsr a0, EXCCAUSE
s32i a5, sp, XT_STK_A5 /* save a5 */
addi a5, a0, -EXCCAUSE_CP0_DISABLED /* a5 = CP index */
/* Save a few more of interruptee's registers (a5 was already saved). */
s32i a2, sp, XT_STK_A2
s32i a3, sp, XT_STK_A3
s32i a4, sp, XT_STK_A4
s32i a15, sp, XT_STK_A15
/* Get co-processor state save area of new owner thread. */
call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
beqz a15, .L_goto_invalid /* not in a thread (invalid) */
#else
#ifndef CONFIG_FREERTOS_FPU_IN_ISR
beqz a15, .L_goto_invalid
#endif
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
/*When FPU in ISR is enabled we could deal with zeroed a15 */
/* Enable the co-processor's bit in CPENABLE. */
movi a0, _xt_coproc_mask
rsr a4, CPENABLE /* a4 = CPENABLE */
addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
/* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
here, to keep the entire thing from crashing, it's better to pin the task to whatever
core we're running on now. */
movi a2, pxCurrentTCB
getcoreid a3
addx4 a2, a3, a2
l32i a2, a2, 0 /* a2 = start of pxCurrentTCB[cpuid] */
addi a2, a2, TASKTCB_XCOREID_OFFSET /* offset to xCoreID in tcb struct */
s32i a3, a2, 0 /* store current cpuid */
/* Grab correct xt_coproc_owner_sa for this core */
movi a2, XCHAL_CP_MAX << 2
mull a2, a2, a3 /* multiply by current processor id */
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
add a3, a3, a2 /* a3 = owner area needed for this processor */
extui a2, a0, 0, 16 /* coprocessor bitmask portion */
or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
wsr a4, CPENABLE
/*
Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
everywhere): _xt_coproc_release assumes it works like this in order not to need
locking.
*/
/* Get old coprocessor owner thread (save area ptr) and assign new one. */
addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */
l32i a2, a3, 0 /* a2 = old owner's save area */
s32i a15, a3, 0 /* _xt_coproc_owner_sa[n] = new */
rsync /* ensure wsr.CPENABLE is complete */
/* Only need to context switch if new owner != old owner. */
/* If float is necessary on ISR, we need to remove this check */
/* below, because on restoring from ISR we may have new == old condition used
* to force cp restore to next thread
*/
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifndef CONFIG_FREERTOS_FPU_IN_ISR
#endif
beq a15, a2, .L_goto_done /* new owner == old, we're done */
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#endif
#endif
/* If no old owner then nothing to save. */
beqz a2, .L_check_new
/* If old owner not actively using CP then nothing to save. */
l16ui a4, a2, XT_CPENABLE /* a4 = old owner's CPENABLE */
bnone a4, a0, .L_check_new /* old owner not using CP */
.L_save_old:
/* Save old owner's coprocessor state. */
movi a5, _xt_coproc_sa_offset
/* Mark old owner state as no longer active (CPENABLE bit n clear). */
xor a4, a4, a0 /* clear CP bit in CPENABLE */
s16i a4, a2, XT_CPENABLE /* update old owner's CPENABLE */
extui a4, a0, 16, 5 /* a4 = CP index = n */
addx4 a5, a4, a5 /* a5 = &_xt_coproc_sa_offset[n] */
/* Mark old owner state as saved (CPSTORED bit n set). */
l16ui a4, a2, XT_CPSTORED /* a4 = old owner's CPSTORED */
l32i a5, a5, 0 /* a5 = XT_CP[n]_SA offset */
or a4, a4, a0 /* set CP in old owner's CPSTORED */
s16i a4, a2, XT_CPSTORED /* update old owner's CPSTORED */
l32i a2, a2, XT_CP_ASA /* ptr to actual (aligned) save area */
extui a3, a0, 16, 5 /* a3 = CP index = n */
add a2, a2, a5 /* a2 = old owner's area for CP n */
/*
The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
unlikely. If that ever happens, more registers needs to be saved/restored
around this macro invocation, and the value in a15 needs to be recomputed.
*/
xchal_cpi_store_funcbody
.L_check_new:
/* Check if any state has to be restored for new owner. */
/* NOTE: a15 = new owner's save area, cannot be zero when we get here. */
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
beqz a15, .L_xt_coproc_done
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
l16ui a3, a15, XT_CPSTORED /* a3 = new owner's CPSTORED */
movi a4, _xt_coproc_sa_offset
bnone a3, a0, .L_check_cs /* full CP not saved, check callee-saved */
xor a3, a3, a0 /* CPSTORED bit is set, clear it */
s16i a3, a15, XT_CPSTORED /* update new owner's CPSTORED */
/* Adjust new owner's save area pointers to area for CP n. */
extui a3, a0, 16, 5 /* a3 = CP index = n */
addx4 a4, a3, a4 /* a4 = &_xt_coproc_sa_offset[n] */
l32i a4, a4, 0 /* a4 = XT_CP[n]_SA */
l32i a5, a15, XT_CP_ASA /* ptr to actual (aligned) save area */
add a2, a4, a5 /* a2 = new owner's area for CP */
/*
The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
It is theoretically possible for Xtensa processor designers to write TIE
that causes more address registers to be affected, but it is generally
unlikely. If that ever happens, more registers needs to be saved/restored
around this macro invocation.
*/
xchal_cpi_load_funcbody
/* Restore interruptee's saved registers. */
/* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
.L_xt_coproc_done:
l32i a15, sp, XT_STK_A15
l32i a5, sp, XT_STK_A5
l32i a4, sp, XT_STK_A4
l32i a3, sp, XT_STK_A3
l32i a2, sp, XT_STK_A2
call0 _xt_user_exit /* return via exit dispatcher */
/* Never returns here - call0 is used as a jump (see note at top) */
.L_check_cs:
/* a0 = CP mask in low bits, a15 = new owner's save area */
l16ui a2, a15, XT_CP_CS_ST /* a2 = mask of CPs saved */
bnone a2, a0, .L_xt_coproc_done /* if no match then done */
and a2, a2, a0 /* a2 = which CPs to restore */
extui a2, a2, 0, 8 /* extract low 8 bits */
s32i a6, sp, XT_STK_A6 /* save extra needed regs */
s32i a7, sp, XT_STK_A7
s32i a13, sp, XT_STK_A13
s32i a14, sp, XT_STK_A14
call0 _xt_coproc_restorecs /* restore CP registers */
l32i a6, sp, XT_STK_A6 /* restore saved registers */
l32i a7, sp, XT_STK_A7
l32i a13, sp, XT_STK_A13
l32i a14, sp, XT_STK_A14
j .L_xt_coproc_done
/* Co-processor exception occurred outside a thread (not supported). */
.L_xt_coproc_invalid:
movi a0,PANIC_RSN_COPROCEXCEPTION
wsr a0,EXCCAUSE
call0 _xt_panic /* not in a thread (invalid) */
/* never returns */
#endif /* XCHAL_CP_NUM */
/*
-------------------------------------------------------------------------------
Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
-------------------------------------------------------------------------------
*/
.section .iram1,"ax"
.type _xt_lowint1,@function
.align 4
_xt_lowint1:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, PS /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_1 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_1 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_user_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
/* EXCSAVE_1 should now be free to use. Use it to keep a copy of the
current stack pointer that points to the exception frame (XT_STK_FRAME).*/
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
mov a0, sp
wsr a0, EXCSAVE_1
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(1) | PS_UM
#else
movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
-------------------------------------------------------------------------------
MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
Medium priority interrupts are by definition those with priority greater
than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
setting PS.EXCM and therefore can easily support a C environment for
handlers in C, and interact safely with an RTOS.
Each vector goes at a predetermined location according to the Xtensa
hardware configuration, which is ensured by its placement in a special
section known to the Xtensa linker support package (LSP). It performs
the minimum necessary before jumping to the handler in the .text section.
The corresponding handler goes in the normal .text section. It sets up
the appropriate stack frame, saves a few vector-specific registers and
calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
and enter the RTOS, then sets up a C environment. It then calls the
user's interrupt handler code (which may be coded in C) and finally
calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
While XT_RTOS_INT_EXIT does not return directly to the interruptee,
eventually the RTOS scheduler will want to dispatch the interrupted
task or handler. The scheduler will return to the exit point that was
saved in the interrupt stack frame at XT_STK_EXIT.
-------------------------------------------------------------------------------
*/
#if XCHAL_EXCM_LEVEL >= 2
.begin literal_prefix .Level2InterruptVector
.section .Level2InterruptVector.text, "ax"
.global _Level2Vector
.type _Level2Vector,@function
.align 4
_Level2Vector:
wsr a0, EXCSAVE_2 /* preserve a0 */
call0 _xt_medint2 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.section .iram1,"ax"
.type _xt_medint2,@function
.align 4
_xt_medint2:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_2 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_2 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_2 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint2_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* EXCSAVE_2 should now be free to use. Use it to keep a copy of the
current stack pointer that points to the exception frame (XT_STK_FRAME).*/
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
mov a0, sp
wsr a0, EXCSAVE_2
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(2) | PS_UM
#else
movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint2_exit
.type _xt_medint2_exit,@function
.align 4
_xt_medint2_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_2
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_2
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 2
#endif /* Level 2 */
#if XCHAL_EXCM_LEVEL >= 3
.begin literal_prefix .Level3InterruptVector
.section .Level3InterruptVector.text, "ax"
.global _Level3Vector
.type _Level3Vector,@function
.align 4
_Level3Vector:
wsr a0, EXCSAVE_3 /* preserve a0 */
call0 _xt_medint3 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
.section .iram1,"ax"
.type _xt_medint3,@function
.align 4
_xt_medint3:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_3 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_3 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_3 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint3_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* EXCSAVE_3 should now be free to use. Use it to keep a copy of the
current stack pointer that points to the exception frame (XT_STK_FRAME).*/
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
mov a0, sp
wsr a0, EXCSAVE_3
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(3) | PS_UM
#else
movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint3_exit
.type _xt_medint3_exit,@function
.align 4
_xt_medint3_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_3
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_3
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 3
#endif /* Level 3 */
#if XCHAL_EXCM_LEVEL >= 4
.begin literal_prefix .Level4InterruptVector
.section .Level4InterruptVector.text, "ax"
.global _Level4Vector
.type _Level4Vector,@function
.align 4
_Level4Vector:
wsr a0, EXCSAVE_4 /* preserve a0 */
call0 _xt_medint4 /* load interrupt handler */
.end literal_prefix
.section .iram1,"ax"
.type _xt_medint4,@function
.align 4
_xt_medint4:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_4 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_4 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_4 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint4_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* EXCSAVE_4 should now be free to use. Use it to keep a copy of the
current stack pointer that points to the exception frame (XT_STK_FRAME).*/
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
mov a0, sp
wsr a0, EXCSAVE_4
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(4) | PS_UM
#else
movi a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint4_exit
.type _xt_medint4_exit,@function
.align 4
_xt_medint4_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_4
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_4
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 4
#endif /* Level 4 */
#if XCHAL_EXCM_LEVEL >= 5
.begin literal_prefix .Level5InterruptVector
.section .Level5InterruptVector.text, "ax"
.global _Level5Vector
.type _Level5Vector,@function
.align 4
_Level5Vector:
wsr a0, EXCSAVE_5 /* preserve a0 */
call0 _xt_medint5 /* load interrupt handler */
.end literal_prefix
.section .iram1,"ax"
.type _xt_medint5,@function
.align 4
_xt_medint5:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_5 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_5 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_5 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint5_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* EXCSAVE_5 should now be free to use. Use it to keep a copy of the
current stack pointer that points to the exception frame (XT_STK_FRAME).*/
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
mov a0, sp
wsr a0, EXCSAVE_5
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(5) | PS_UM
#else
movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint5_exit
.type _xt_medint5_exit,@function
.align 4
_xt_medint5_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_5
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_5
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 5
#endif /* Level 5 */
#if XCHAL_EXCM_LEVEL >= 6
.begin literal_prefix .Level6InterruptVector
.section .Level6InterruptVector.text, "ax"
.global _Level6Vector
.type _Level6Vector,@function
.align 4
_Level6Vector:
wsr a0, EXCSAVE_6 /* preserve a0 */
call0 _xt_medint6 /* load interrupt handler */
.end literal_prefix
.section .iram1,"ax"
.type _xt_medint6,@function
.align 4
_xt_medint6:
mov a0, sp /* sp == a1 */
addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */
s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */
rsr a0, EPS_6 /* save interruptee's PS */
s32i a0, sp, XT_STK_PS
rsr a0, EPC_6 /* save interruptee's PC */
s32i a0, sp, XT_STK_PC
rsr a0, EXCSAVE_6 /* save interruptee's a0 */
s32i a0, sp, XT_STK_A0
movi a0, _xt_medint6_exit /* save exit point for dispatch */
s32i a0, sp, XT_STK_EXIT
/* EXCSAVE_6 should now be free to use. Use it to keep a copy of the
current stack pointer that points to the exception frame (XT_STK_FRAME).*/
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
#ifdef XT_DEBUG_BACKTRACE
#ifndef __XTENSA_CALL0_ABI__
mov a0, sp
wsr a0, EXCSAVE_6
#endif
#endif
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
/* Save rest of interrupt context and enter RTOS. */
call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
/* !! We are now on the RTOS system stack !! */
/* Set up PS for C, enable interrupts above this level and clear EXCM. */
#ifdef __XTENSA_CALL0_ABI__
movi a0, PS_INTLEVEL(6) | PS_UM
#else
movi a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
#endif
wsr a0, PS
rsync
/* OK to call C code at this point, dispatch user ISRs */
dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
/* Done handling interrupts, transfer control to OS */
call0 XT_RTOS_INT_EXIT /* does not return directly here */
/*
Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
on entry and used to return to a thread or interrupted interrupt handler.
*/
.global _xt_medint6_exit
.type _xt_medint6_exit,@function
.align 4
_xt_medint6_exit:
/* Restore only level-specific regs (the rest were already restored) */
l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */
wsr a0, EPS_6
l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */
wsr a0, EPC_6
l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */
l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */
rsync /* ensure EPS and EPC written */
rfi 6
#endif /* Level 6 */
/*******************************************************************************
HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
High priority interrupts are by definition those with priorities greater
than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
interrupts cannot interact with the RTOS, that is they must save all regs
they use and not call any RTOS function.
A further restriction imposed by the Xtensa windowed architecture is that
high priority interrupts must not modify the stack area even logically
"above" the top of the interrupted stack (they need to provide their
own stack or static save area).
Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
and used for purposes requiring very short service times.
Here are templates for high priority (level 2+) interrupt vectors.
They assume only one interrupt per level to avoid the burden of identifying
which interrupts at this level are pending and enabled. This allows for
minimum latency and avoids having to save/restore a2 in addition to a0.
If more than one interrupt per high priority level is configured, this burden
is on the handler which in any case must provide a way to save and restore
registers it uses without touching the interrupted stack.
Each vector goes at a predetermined location according to the Xtensa
hardware configuration, which is ensured by its placement in a special
section known to the Xtensa linker support package (LSP). It performs
the minimum necessary before jumping to the handler in the .text section.
*******************************************************************************/
/*
These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define
these in an external assembly source file. If these symbols are not defined anywhere
else, the defaults in xtensa_vector_defaults.S are used.
*/
#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
.begin literal_prefix .Level2InterruptVector
.section .Level2InterruptVector.text, "ax"
.global _Level2Vector
.type _Level2Vector,@function
.global xt_highint2
.align 4
_Level2Vector:
wsr a0, EXCSAVE_2 /* preserve a0 */
call0 xt_highint2 /* load interrupt handler */
.end literal_prefix
#endif /* Level 2 */
#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
.begin literal_prefix .Level3InterruptVector
.section .Level3InterruptVector.text, "ax"
.global _Level3Vector
.type _Level3Vector,@function
.global xt_highint3
.align 4
_Level3Vector:
wsr a0, EXCSAVE_3 /* preserve a0 */
call0 xt_highint3 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
#endif /* Level 3 */
#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
.begin literal_prefix .Level4InterruptVector
.section .Level4InterruptVector.text, "ax"
.global _Level4Vector
.type _Level4Vector,@function
.global xt_highint4
.align 4
_Level4Vector:
wsr a0, EXCSAVE_4 /* preserve a0 */
call0 xt_highint4 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
#endif /* Level 4 */
#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
.begin literal_prefix .Level5InterruptVector
.section .Level5InterruptVector.text, "ax"
.global _Level5Vector
.type _Level5Vector,@function
.global xt_highint5
.align 4
_Level5Vector:
wsr a0, EXCSAVE_5 /* preserve a0 */
call0 xt_highint5 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
#endif /* Level 5 */
#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
.begin literal_prefix .Level6InterruptVector
.section .Level6InterruptVector.text, "ax"
.global _Level6Vector
.type _Level6Vector,@function
.global xt_highint6
.align 4
_Level6Vector:
wsr a0, EXCSAVE_6 /* preserve a0 */
call0 xt_highint6 /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
#endif /* Level 6 */
#if XCHAL_HAVE_NMI
.begin literal_prefix .NMIExceptionVector
.section .NMIExceptionVector.text, "ax"
.global _NMIExceptionVector
.type _NMIExceptionVector,@function
.global xt_nmi
.align 4
_NMIExceptionVector:
wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */
call0 xt_nmi /* load interrupt handler */
/* never returns here - call0 is used as a jump (see note at top) */
.end literal_prefix
#endif /* NMI */
/*******************************************************************************
WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
Here is the code for each window overflow/underflow exception vector and
(interspersed) efficient code for handling the alloca exception cause.
Window exceptions are handled entirely in the vector area and are very
tight for performance. The alloca exception is also handled entirely in
the window vector area so comes at essentially no cost in code size.
Users should never need to modify them and Cadence Design Systems recommends
they do not.
Window handlers go at predetermined vector locations according to the
Xtensa hardware configuration, which is ensured by their placement in a
special section known to the Xtensa linker support package (LSP). Since
their offsets in that section are always the same, the LSPs do not define
a section per vector.
These things are coded for XEA2 only (XEA1 is not supported).
Note on Underflow Handlers:
The underflow handler for returning from call[i+1] to call[i]
must preserve all the registers from call[i+1]'s window.
In particular, a0 and a1 must be preserved because the RETW instruction
will be reexecuted (and may even underflow if an intervening exception
has flushed call[i]'s registers).
Registers a2 and up may contain return values.
*******************************************************************************/
#if XCHAL_HAVE_WINDOWED
.section .WindowVectors.text, "ax"
/*
--------------------------------------------------------------------------------
Window Overflow Exception for Call4.
Invoked if a call[i] referenced a register (a4-a15)
that contains data from ancestor call[j];
call[j] had done a call4 to call[j+1].
On entry here:
window rotated to call[j] start point;
a0-a3 are registers to be saved;
a4-a15 must be preserved;
a5 is call[j+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x0
.global _WindowOverflow4
_WindowOverflow4:
s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */
rfwo /* rotates back to call[i] position */
/*
--------------------------------------------------------------------------------
Window Underflow Exception for Call4
Invoked by RETW returning from call[i+1] to call[i]
where call[i]'s registers must be reloaded (not live in ARs);
where call[i] had done a call4 to call[i+1].
On entry here:
window rotated to call[i] start point;
a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
a4-a15 must be preserved (they are call[i+1].reg[0..11]);
a5 is call[i+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x40
.global _WindowUnderflow4
_WindowUnderflow4:
l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */
rfwu
/*
--------------------------------------------------------------------------------
Handle alloca exception generated by interruptee executing 'movsp'.
This uses space between the window vectors, so is essentially "free".
All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
and PS.EXCM has been set by the exception hardware (can't be interrupted).
The fact the alloca exception was taken means the registers associated with
the base-save area have been spilled and will be restored by the underflow
handler, so those 4 registers are available for scratch.
The code is optimized to avoid unaligned branches and minimize cache misses.
--------------------------------------------------------------------------------
*/
.align 4
.global _xt_alloca_exc
_xt_alloca_exc:
rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
rsr a2, PS
extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
xor a3, a3, a4 /* bits changed from old to current windowbase */
rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */
slli a3, a3, XCHAL_PS_OWB_SHIFT
xor a2, a2, a3 /* flip changed bits in old window base */
wsr a2, PS /* update PS.OWB to new window base */
rsync
_bbci.l a4, 31, _WindowUnderflow4
rotw -1 /* original a0 goes to a8 */
_bbci.l a8, 30, _WindowUnderflow8
rotw -1
j _WindowUnderflow12
/*
--------------------------------------------------------------------------------
Window Overflow Exception for Call8
Invoked if a call[i] referenced a register (a4-a15)
that contains data from ancestor call[j];
call[j] had done a call8 to call[j+1].
On entry here:
window rotated to call[j] start point;
a0-a7 are registers to be saved;
a8-a15 must be preserved;
a9 is call[j+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x80
.global _WindowOverflow8
_WindowOverflow8:
s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */
l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
(used to find end of call[j]'s frame) */
s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */
s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */
s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */
s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */
rfwo /* rotates back to call[i] position */
/*
--------------------------------------------------------------------------------
Window Underflow Exception for Call8
Invoked by RETW returning from call[i+1] to call[i]
where call[i]'s registers must be reloaded (not live in ARs);
where call[i] had done a call8 to call[i+1].
On entry here:
window rotated to call[i] start point;
a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
a8-a15 must be preserved (they are call[i+1].reg[0..7]);
a9 is call[i+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0xC0
.global _WindowUnderflow8
_WindowUnderflow8:
l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a7, a1, -12 /* a7 <- call[i-1]'s sp
(used to find end of call[i]'s frame) */
l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */
l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */
l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */
l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */
l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */
rfwu
/*
--------------------------------------------------------------------------------
Window Overflow Exception for Call12
Invoked if a call[i] referenced a register (a4-a15)
that contains data from ancestor call[j];
call[j] had done a call12 to call[j+1].
On entry here:
window rotated to call[j] start point;
a0-a11 are registers to be saved;
a12-a15 must be preserved;
a13 is call[j+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x100
.global _WindowOverflow12
_WindowOverflow12:
s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */
l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
(used to find end of call[j]'s frame) */
s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */
s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */
s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */
s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */
s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */
s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */
s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */
s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */
s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */
s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */
s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */
rfwo /* rotates back to call[i] position */
/*
--------------------------------------------------------------------------------
Window Underflow Exception for Call12
Invoked by RETW returning from call[i+1] to call[i]
where call[i]'s registers must be reloaded (not live in ARs);
where call[i] had done a call12 to call[i+1].
On entry here:
window rotated to call[i] start point;
a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
a12-a15 must be preserved (they are call[i+1].reg[0..3]);
a13 is call[i+1]'s stack pointer.
--------------------------------------------------------------------------------
*/
.org 0x140
.global _WindowUnderflow12
_WindowUnderflow12:
l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */
l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */
l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */
l32e a11, a1, -12 /* a11 <- call[i-1]'s sp
(used to find end of call[i]'s frame) */
l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */
l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */
l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */
l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */
l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */
l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */
l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */
l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */
l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */
rfwu
#endif /* XCHAL_HAVE_WINDOWED */
.section .UserEnter.text, "ax"
.global call_user_start
.type call_user_start,@function
.align 4
.literal_position
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 13,064 | portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/**
* \file
* \ingroup OS_FREERTOS
* \brief freertos support for arc processor
* like task dispatcher, interrupt handler
*/
/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
/*
* core-dependent part in assemble language (for arc)
*/
#define __ASSEMBLY__
#include "arc/arc.h"
#include "arc/arc_asm_common.h"
/*
* task dispatcher
*
*/
.text
.align 4
.global dispatch
dispatch:
/*
* the pre-conditions of this routine are task context, CPU is
* locked, dispatch is enabled.
*/
SAVE_NONSCRATCH_REGS /* save callee save registers */
mov r1, dispatch_r
PUSH r1 /* save return address */
ld r0, [pxCurrentTCB]
bl dispatcher
/* return routine when task dispatch happened in task context */
dispatch_r:
RESTORE_NONSCRATCH_REGS /* recover registers */
j [blink]
/*
* start dispatch
*/
.global start_dispatch
.align 4
start_dispatch:
/*
* this routine is called in the non-task context during the startup of the kernel
* , and all the interrupts are locked.
*
* when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
* In target_initialize, all interrupt priority mask should be cleared, cpu should be
* locked, the interrupts outside the kernel such as fiq can be
* enabled.
*/
clri
mov r0, 0
st r0, [exc_nest_count]
b dispatcher_0
/*
* dispatcher
*/
dispatcher:
ld r1, [ulCriticalNesting]
PUSH r1 /* save critical nesting */
st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
jl vTaskSwitchContext /* change the value of pxCurrentTCB */
/*
* before dispatcher is called, task context | cpu locked | dispatch enabled
* should be satisfied. In this routine, the processor will jump
* into the entry of next to run task
*
* i.e. kernel mode, IRQ disabled, dispatch enabled
*/
dispatcher_0:
ld r1, [pxCurrentTCB]
ld sp, [r1] /* recover task stack */
#if ARC_FEATURE_STACK_CHECK
#if ARC_FEATURE_SEC_PRESENT
lr r0, [AUX_SEC_STAT]
bclr r0, r0, AUX_SEC_STAT_BIT_SSC
sflag r0
#else
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_SC
kflag r0
#endif
jl vPortSetStackCheck
#if ARC_FEATURE_SEC_PRESENT
lr r0, [AUX_SEC_STAT]
bset r0, r0, AUX_SEC_STAT_BIT_SSC
sflag r0
#else
lr r0, [AUX_STATUS32]
bset r0, r0, AUX_STATUS_BIT_SC
kflag r0
#endif
#endif
POP r0 /* get critical nesting */
st r0, [ulCriticalNesting]
POP r0 /* get return address */
j [r0]
/*
* task startup routine
*
*/
.text
.global start_r
.align 4
start_r:
seti /* unlock cpu */
mov blink, vPortEndTask /* set return address */
POP r1 /* get task function body */
POP r0 /* get task parameters */
j [r1]
/****** exceptions and interrupts handing ******/
/****** entry for exception handling ******/
.global exc_entry_cpu
.align 4
exc_entry_cpu:
EXCEPTION_PROLOGUE
mov blink, sp
mov r3, sp /* as exception handler's para(p_excinfo) */
ld r0, [exc_nest_count]
add r1, r0, 1
st r1, [exc_nest_count]
brne r0, 0, exc_handler_1
/* change to exception stack if interrupt happened in task context */
mov sp, _e_stack
exc_handler_1:
PUSH blink
lr r0, [AUX_ECR]
lsr r0, r0, 16
mov r1, exc_int_handler_table
ld.as r2, [r1, r0]
mov r0, r3
jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */
/* interrupts are not allowed */
ret_exc:
POP sp
mov r1, exc_nest_count
ld r0, [r1]
sub r0, r0, 1
st r0, [r1]
brne r0, 0, ret_exc_1 /* nest exception case */
lr r1, [AUX_IRQ_ACT] /* nest interrupt case */
brne r1, 0, ret_exc_1
ld r0, [context_switch_reqflg]
brne r0, 0, ret_exc_2
ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
EXCEPTION_EPILOGUE
rtie
/* there is a dispatch request */
ret_exc_2:
/* clear dispatch request */
mov r0, 0
st r0, [context_switch_reqflg]
ld r0, [pxCurrentTCB]
breq r0, 0, ret_exc_1
SAVE_CALLEE_REGS /* save callee save registers */
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */
kflag r0
mov r1, ret_exc_r /* save return address */
PUSH r1
bl dispatcher /* r0->pxCurrentTCB */
ret_exc_r:
/* recover exception status */
lr r0, [AUX_STATUS32]
bset r0, r0, AUX_STATUS_BIT_AE
kflag r0
RESTORE_CALLEE_REGS /* recover registers */
EXCEPTION_EPILOGUE
rtie
/****** entry for normal interrupt exception handling ******/
.global exc_entry_int /* entry for interrupt handling */
.align 4
exc_entry_int:
#if ARC_FEATURE_FIRQ == 1
#if ARC_FEATURE_RGF_NUM_BANKS > 1
lr r0, [AUX_IRQ_ACT] /* check whether it is P0 interrupt */
btst r0, 0
jnz exc_entry_firq
#else
PUSH r10
lr r10, [AUX_IRQ_ACT]
btst r10, 0
POP r10
jnz exc_entry_firq
#endif
#endif
INTERRUPT_PROLOGUE
mov blink, sp
clri /* disable interrupt */
ld r3, [exc_nest_count]
add r2, r3, 1
st r2, [exc_nest_count]
seti /* enable higher priority interrupt */
brne r3, 0, irq_handler_1
/* change to exception stack if interrupt happened in task context */
mov sp, _e_stack
#if ARC_FEATURE_STACK_CHECK
#if ARC_FEATURE_SEC_PRESENT
lr r0, [AUX_SEC_STAT]
bclr r0, r0, AUX_SEC_STAT_BIT_SSC
sflag r0
#else
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_SC
kflag r0
#endif
#endif
irq_handler_1:
PUSH blink
lr r0, [AUX_IRQ_CAUSE]
mov r1, exc_int_handler_table
ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */
/* handle software triggered interrupt */
lr r3, [AUX_IRQ_HINT]
cmp r3, r0
bne.d irq_hint_handled
xor r3, r3, r3
sr r3, [AUX_IRQ_HINT]
irq_hint_handled:
jl [r2] /* jump to interrupt handler */
/* no interrupts are allowed from here */
ret_int:
clri /* disable interrupt */
POP sp
mov r1, exc_nest_count
ld r0, [r1]
sub r0, r0, 1
st r0, [r1]
/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
lr r0, [AUX_IRQ_CAUSE]
sr r0, [AUX_IRQ_SELECT]
lr r3, [AUX_IRQ_PRIORITY]
lr r1, [AUX_IRQ_ACT]
bclr r2, r1, r3
brne r2, 0, ret_int_1
ld r0, [context_switch_reqflg]
brne r0, 0, ret_int_2
ret_int_1: /* return from non-task context */
INTERRUPT_EPILOGUE
rtie
/* there is a dispatch request */
ret_int_2:
/* clear dispatch request */
mov r0, 0
st r0, [context_switch_reqflg]
ld r0, [pxCurrentTCB]
breq r0, 0, ret_int_1
/* r1 has old AUX_IRQ_ACT */
PUSH r1
/* clear related bits in IRQ_ACT manually to simulate a irq return */
sr r2, [AUX_IRQ_ACT]
SAVE_CALLEE_REGS /* save callee save registers */
mov r1, ret_int_r /* save return address */
PUSH r1
bl dispatcher /* r0->pxCurrentTCB */
ret_int_r:
RESTORE_CALLEE_REGS /* recover registers */
POPAX AUX_IRQ_ACT
INTERRUPT_EPILOGUE
rtie
#if ARC_FEATURE_FIRQ == 1
.global exc_entry_firq
.align 4
exc_entry_firq:
#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS > 1
#if ARC_FEATURE_SEC_PRESENT
lr r0, [AUX_SEC_STAT]
bclr r0, r0, AUX_SEC_STAT_BIT_SSC
sflag r0
#else
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_SC
kflag r0
#endif
#endif
SAVE_FIQ_EXC_REGS
mov blink, sp
ld r3, [exc_nest_count]
add r2, r3, 1
st r2, [exc_nest_count]
brne r3, 0, firq_handler_1
#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS == 1
#if ARC_FEATURE_SEC_PRESENT
lr r0, [AUX_SEC_STAT]
bclr r0, r0, AUX_SEC_STAT_BIT_SSC
sflag r0
#else
lr r0, [AUX_STATUS32]
bclr r0, r0, AUX_STATUS_BIT_SC
kflag r0
#endif
#endif
/* change to exception stack if interrupt happened in task context */
mov sp, _e_stack
firq_handler_1:
PUSH blink
lr r0, [AUX_IRQ_CAUSE]
mov r1, exc_int_handler_table
ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */
/* handle software triggered interrupt */
lr r3, [AUX_IRQ_HINT]
brne r3, r0, firq_hint_handled
xor r3, r3, r3
sr r3, [AUX_IRQ_HINT]
firq_hint_handled:
jl [r2] /* jump to interrupt handler */
/* no interrupts are allowed from here */
ret_firq:
clri
POP sp
mov r1, exc_nest_count
ld r0, [r1]
sub r0, r0, 1
st r0, [r1]
/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
lr r1, [AUX_IRQ_ACT]
bclr r1, r1, 0
brne r1, 0, ret_firq_1
ld r0, [context_switch_reqflg]
brne r0, 0, ret_firq_2
ret_firq_1: /* return from non-task context */
RESTORE_FIQ_EXC_REGS
rtie
/* there is a dispatch request */
ret_firq_2:
/* clear dispatch request */
mov r0, 0
st r0, [context_switch_reqflg]
ld r0, [pxCurrentTCB]
breq r0, 0, ret_firq_1
/* reconstruct the interruptted context
* When ARC_FEATURE_RGF_BANKED_REGS >= 16 (16, 32), sp is banked
* so need to restore the fast irq stack.
*/
#if ARC_FEATURE_RGF_BANKED_REGS >= 16
RESTORE_LP_REGS
#if ARC_FEATURE_CODE_DENSITY
RESTORE_CODE_DENSITY
#endif
RESTORE_R58_R59
#endif
/* when BANKED_REGS == 16, r4-r9 wiil be also saved in fast irq stack
* so pop them out
*/
#if ARC_FEATURE_RGF_BANKED_REGS == 16 && !defined(ARC_FEATURE_RF16)
POP r9
POP r8
POP r7
POP r6
POP r5
POP r4
#endif
/* for other cases, unbanked regs are already in interrupted context's stack,
* so just need to save and pop the banked regs
*/
/* save the interruptted context */
#if ARC_FEATURE_RGF_BANKED_REGS > 0
/* switch back to bank0 */
lr r0, [AUX_STATUS32]
bic r0, r0, 0x70000
kflag r0
#endif
#if ARC_FEATURE_RGF_BANKED_REGS == 4
/* r4 - r12, gp, fp, r30, blink already saved */
PUSH r0
PUSH r1
PUSH r2
PUSH r3
#elif ARC_FEATURE_RGF_BANKED_REGS == 8
/* r4 - r9, r0, r11 gp, fp, r30, blink already saved */
PUSH r0
PUSH r1
PUSH r2
PUSH r3
PUSH r12
#elif ARC_FEATURE_RGF_BANKED_REGS >= 16
/* nothing is saved, */
SAVE_R0_TO_R12
SAVE_R58_R59
PUSH gp
PUSH fp
PUSH r30 /* general purpose */
PUSH blink
#if ARC_FEATURE_CODE_DENSITY
SAVE_CODE_DENSITY
#endif
SAVE_LP_REGS
#endif
PUSH ilink
lr r0, [AUX_STATUS32_P0]
PUSH r0
lr r0, [AUX_IRQ_ACT]
PUSH r0
bclr r0, r0, 0
sr r0, [AUX_IRQ_ACT]
SAVE_CALLEE_REGS /* save callee save registers */
mov r1, ret_firq_r /* save return address */
PUSH r1
ld r0, [pxCurrentTCB]
bl dispatcher /* r0->pxCurrentTCB */
ret_firq_r:
RESTORE_CALLEE_REGS /* recover registers */
POPAX AUX_IRQ_ACT
POPAX AUX_STATUS32_P0
POP ilink
#if ARC_FEATURE_RGF_NUM_BANKS > 1
#if ARC_FEATURE_RGF_BANKED_REGS == 4
/* r4 - r12, gp, fp, r30, blink already saved */
POP r3
POP r2
POP r1
POP r0
RESTORE_FIQ_EXC_REGS
#elif ARC_FEATURE_RGF_BANKED_REGS == 8
/* r4 - r9, gp, fp, r30, blink already saved */
POP r12
POP r3
POP r2
POP r1
POP r0
RESTORE_FIQ_EXC_REGS
#elif ARC_FEATURE_RGF_BANKED_REGS >= 16
RESTORE_LP_REGS
#if ARC_FEATURE_CODE_DENSITY
RESTORE_CODE_DENSITY
#endif
POP blink
POP r30
POP fp
POP gp
RESTORE_R58_R59
RESTORE_R0_TO_R12
#endif /* ARC_FEATURE_RGF_BANKED_REGS */
#else
RESTORE_FIQ_EXC_REGS
#endif /* ARC_FEATURE_RGF_NUM_BANKS */
rtie
#endif
/** @endcond */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,556 | portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S | /*
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
//#include <csi_config.h>
/********************************************************************
* Functions: vPortStartTask
*
********************************************************************/
.global vPortStartTask
.type vPortStartTask, %function
vPortStartTask:
psrclr ie
lrw r4, pxCurrentTCB
ld.w r4, (r4) // the current task stack pointer is the first member
ld.w sp, (r4)
ldw r0, (sp, 64)
mtcr r0, epc
ldw r0, (sp, 60)
mtcr r0, epsr
ldw r15, (sp, 56)
ldm r0-r13, (sp)
addi sp, 68
rte
/********************************************************************
* Functions: vPortYield
*
********************************************************************/
.global vPortYield
.type vPortYield, %function
vPortYield:
psrclr ee
subi sp, 68
stm r0-r13, (sp)
stw r15, (sp, 56)
mfcr r0, psr
bseti r0, 8
stw r0, (sp, 60)
stw r15, (sp, 64)
lrw r2, pxCurrentTCB
ld.w r3, (r2)
st.w sp, (r3)
jbsr vTaskSwitchContext
lrw r4, pxCurrentTCB
ld.w r4, (r4)
ld.w sp, (r4)
ldw r0, (sp, 64)
mtcr r0, epc
ldw r0, (sp, 60)
mtcr r0, epsr
ldw r15, (sp, 56)
ldm r0-r13, (sp)
addi sp, 68
rte
/********************************************************************
* Functions: NOVIC_IRQ_Default_Handler
*
********************************************************************/
.global NOVIC_IRQ_Default_Handler
.type NOVIC_IRQ_Default_Handler, %function
NOVIC_IRQ_Default_Handler:
psrset ee
subi sp, 68
stm r0-r13, (sp)
stw r15, (sp, 56)
mfcr r0, epsr
stw r0, (sp, 60)
mfcr r0, epc
stw r0, (sp, 64)
lrw r7, pxCurrentTCB
ldw r7, (r7)
stw sp, (r7)
lrw sp, g_top_irqstack
lrw r1, g_irqvector
mfcr r0, psr
lsri r0, 16
sextb r0
subi r0, 32
lsli r0, 2
add r1, r0
ldw r1, (r1)
lsri r0, 2
jsr r1
lrw r7, pxCurrentTCB
ldw r7, (r7)
ldw sp, (r7)
ldw r0, (sp, 64)
mtcr r0, epc
ldw r0, (sp, 60)
mtcr r0, epsr
ldm r0-r13, (sp)
ldw r15, (sp, 56)
addi sp, 68
rte
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 7,269 | portable/ThirdParty/xClang/XCOREAI/portasm.S | // Copyright (c) 2020, XMOS Ltd, All rights reserved
#include "rtos_support_rtos_config.h"
/* The FreeRTOS interrupt code calls vTaskSwitchContext.
Therfore it must be added to the rtos_isr group with the
rest of the ISR callback functions. */
.weak _fptrgroup.rtos_isr.nstackwords.group
.add_to_set _fptrgroup.rtos_isr.nstackwords.group, vTaskSwitchContext.nstackwords, vTaskSwitchContext
.globl kexcept
.align 128 /* align the kernel section to 128 bytes */
.type kexcept,@function
.issue_mode dual
.cc_top kexcept.function, kexcept
kexcept:
ldc r11, 0x0008
shl r11, r11, 16
ldc r9, 0x0080
or r11, r11, r9
bau r11 //_TrapHandler is at 0x00080080. TODO: Is it always? Why can't I access the symbol _TrapHandler?
_yield:
{set sp, r4 /* Restore the task's SP to save the rest of its context. */
get r11, id} /* Get the logical core ID into r11. */
ldaw r0, dp[rtos_core_map]
ldw r0, r0[r11] /* Translate to the RTOS core ID into r0 */
bu _yield_continue /* Skip the ulPortYieldRequired check and jump right to */
/* the context save and switch. Also skips saving SPC */
/* since the kcall handler has already saved it. */
.align 64
kcall:
/* start saving the thread's context */
extsp RTOS_SUPPORT_INTERRUPT_STACK_GROWTH
stw r1, sp[9]
stw r11, sp[19]
/* kcall sets SPC to the instruction of the kcall rather than the next instruction */
/* so we need to adjust the SPC value that we save to the stack: */
stw spc, sp[1] /* save the saved program counter onto the stack... */
ldw r1, sp[1] /* so that we can load it into r1 (which we have already saved). */
add r1, r1, 4 /* Add 4 to the spc to make it point to the instruction after the kcall. */
{stw r1, sp[1] /* Now save it to the stack. */
/* kcall uses the same common function as interrupt callbacks. */
/* tell it to call _yield above. */
ldap r11, _yield}
mov r1, r11
/* fall into rtos_interrupt_callback_common */
.globl rtos_interrupt_callback_common
rtos_interrupt_callback_common:
/* This is the body of the RTOS _xcore_c_interrupt_callback_XXX functions. */
/* r1 = interrupt_callback_t function */
/* Save the thread's context onto the thread's stack. */
/* The stack was extended for this by the wrapper function. */
/* Begin only by saving some registers. The rest will be saved */
/* later if vTaskSwitchContext() needs to be called. */
/* DP and CP need to be saved because these are restored for the kernel ISR. */
/* LR needs to be saved because it is clobbered when calling the callback. */
/* r0-r3, and r11 need to be saved because the callback may clobber them. */
/* r4 is saved because it is used here to hold the task SP. */
stw dp, sp[5]
stw cp, sp[6]
stw lr, sp[7]
stw r0, sp[8]
/*stw r1, sp[9] already saved by the wrapper function. */
stw r2, sp[10]
stw r3, sp[11]
{stw r4, sp[12]
/*stw r11, sp[19] already saved by the wrapper function. */
ldaw r4, sp[0]} /* Get value of current stackpointer into r4. */
{kentsp 0 /* switch to the kernel stack. */
/* The value 0 is safe to use since we don't need the SP */
/* that it saves to KSP[0]. We already have it in r4. */
get r11, ed} /* Get the event data... */
ldw dp, sp[3] /* (Restore CP and DP required for the RTOS ISR */
ldw cp, sp[4] /* in case the active thread has modified them.) */
{mov r0, r11 /* ...into the first argument for the callback function, */
bla r1} /* and call the callback function. */
{set sp, r4 /* Restore the task's SP now. */
get r11, id} /* Get the logical core ID into r11. */
ldaw r0, dp[rtos_core_map]
ldw r0, r0[r11] /* Translate to the RTOS core ID into r0. */
ldaw r2, dp[ulPortYieldRequired] /* Get the yield required array into r2. */
ldw r1, r2[r0] /* Is a yield required for this core? */
{bf r1, _freertos_restore_ctx_partial /* If not, restore the context now. */
ldc r1, 0}
stw r1, r2[r0] /* Otherwise, clear the yield required flag. */
/* Save the rest of the current task's context. */
/* Save standard xs2 regs */
stw spc, sp[1]
_yield_continue:
stw ssr, sp[2]
stw sed, sp[3]
stw et, sp[4]
stw r5, sp[13]
stw r6, sp[14]
stw r7, sp[15]
stw r8, sp[16]
stw r9, sp[17]
stw r10, sp[18]
#if 1
/* Save VPU status and headroom */
vgetc r11
{stw r11, sp[20]
/* Save VPU regs */
ldaw r11, sp[21]}
{vstr r11[0]
ldaw r11, sp[29]}
{vstd r11[0]
ldaw r11, sp[37]}
vstc r11[0]
#endif
ldaw r5, dp[pxCurrentTCBs] /* Get the current TCB array into r5. */
ldw r1, r5[r0] /* Get this core's current TCB pointer into r1. */
stw r4, r1[0x0] /* Save the current task's SP to the first */
/* word (top of stack) in the current TCB. */
{kentsp 0 /* switch back to the kernel stack. */
mov r6, r0} /* copy the RTOS core ID into r6 so we don't lose it. */
ldap r11, vTaskSwitchContext
bla r11 /* Finally call vTaskSwitchContext(core_id) now that the task's */
/* entire context is saved. Note the core id in r0 is the argument. */
//krestsp 0 /* unnecessary since KSP is already set and the SP */
/* is being restored next from the current TCB. */
.globl _freertos_restore_ctx
_freertos_restore_ctx:
ldw r0, r5[r6] /* get this core's current TCB pointer into r0 */
ldw r0, r0[0x0] /* Get the top of the stack from the current TCB... */
set sp, r0 /* into the stack pointer register. */
/* Restore the current task's context */
#if 1
/* Restore VPU regs */
ldaw r11, sp[37]
{vldc r11[0]
ldaw r11, sp[29]}
{vldd r11[0]
ldaw r11, sp[21]}
vldr r11[0]
/* Restore VPU status and headroom */
ldw r11, sp[20]
vsetc r11
#endif
/* Restore standard xs2 regs */
ldw spc, sp[1]
ldw ssr, sp[2]
ldw sed, sp[3]
ldw et, sp[4]
ldw r5, sp[13]
ldw r6, sp[14]
ldw r7, sp[15]
ldw r8, sp[16]
ldw r9, sp[17]
ldw r10, sp[18]
_freertos_restore_ctx_partial:
ldw dp, sp[5]
ldw cp, sp[6]
ldw lr, sp[7]
ldw r0, sp[8]
ldw r1, sp[9]
ldw r2, sp[10]
ldw r3, sp[11]
ldw r4, sp[12]
{ldw r11, sp[19]
/* shrink the stack by the size of the context just restored */
ldaw sp, sp[RTOS_SUPPORT_INTERRUPT_STACK_GROWTH]}
kret /* exit kernel mode and return to the thread */
.cc_bottom kexcept.function
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 8,891 | portable/GCC/PPC440_Xilinx/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "FreeRTOSConfig.h"
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern xTaskIncrementTick
.extern vPortISRHandler
.global vPortStartFirstTask
.global vPortYield
.global vPortTickISR
.global vPortISRWrapper
.global vPortSaveFPURegisters
.global vPortRestoreFPURegisters
.set BChainField, 0
.set NextLRField, BChainField + 4
.set MSRField, NextLRField + 4
.set PCField, MSRField + 4
.set LRField, PCField + 4
.set CTRField, LRField + 4
.set XERField, CTRField + 4
.set CRField, XERField + 4
.set USPRG0Field, CRField + 4
.set r0Field, USPRG0Field + 4
.set r2Field, r0Field + 4
.set r3r31Field, r2Field + 4
.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
.macro portSAVE_STACK_POINTER_AND_LR
/* Get the address of the TCB. */
xor R0, R0, R0
addis R2, R0, pxCurrentTCB@ha
lwz R2, pxCurrentTCB@l( R2 )
/* Store the stack pointer into the TCB */
stw SP, 0( R2 )
/* Save the link register */
stwu R1, -24( R1 )
mflr R0
stw R31, 20( R1 )
stw R0, 28( R1 )
mr R31, r1
.endm
.macro portRESTORE_STACK_POINTER_AND_LR
/* Restore the link register */
lwz R11, 0( R1 )
lwz R0, 4( R11 )
mtlr R0
lwz R31, -4( R11 )
mr R1, R11
/* Get the address of the TCB. */
xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( R1 )
/* Get the task stack pointer from the TCB. */
lwz SP, 0( SP )
.endm
vPortStartFirstTask:
/* Get the address of the TCB. */
xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( SP )
/* Get the task stack pointer from the TCB. */
lwz SP, 0( SP )
/* Restore MSR register to SRR1. */
lwz R0, MSRField(R1)
mtsrr1 R0
/* Restore current PC location to SRR0. */
lwz R0, PCField(R1)
mtsrr0 R0
/* Save USPRG0 register */
lwz R0, USPRG0Field(R1)
mtspr 0x100,R0
/* Restore Condition register */
lwz R0, CRField(R1)
mtcr R0
/* Restore Fixed Point Exception register */
lwz R0, XERField(R1)
mtxer R0
/* Restore Counter register */
lwz R0, CTRField(R1)
mtctr R0
/* Restore Link register */
lwz R0, LRField(R1)
mtlr R0
/* Restore remaining GPR registers. */
lmw R3,r3r31Field(R1)
/* Restore r0 and r2. */
lwz R0, r0Field(R1)
lwz R2, r2Field(R1)
/* Remove frame from stack */
addi R1,R1,IFrameSize
/* Return into the first task */
rfi
vPortYield:
portSAVE_STACK_POINTER_AND_LR
bl vTaskSwitchContext
portRESTORE_STACK_POINTER_AND_LR
blr
vPortTickISR:
portSAVE_STACK_POINTER_AND_LR
bl xTaskIncrementTick
#if configUSE_PREEMPTION == 1
bl vTaskSwitchContext
#endif
/* Clear the interrupt */
lis R0, 2048
mttsr R0
portRESTORE_STACK_POINTER_AND_LR
blr
vPortISRWrapper:
portSAVE_STACK_POINTER_AND_LR
bl vPortISRHandler
portRESTORE_STACK_POINTER_AND_LR
blr
#if configUSE_FPU == 1
vPortSaveFPURegisters:
/* Enable APU and mark FPU as present. */
mfmsr r0
xor r30, r30, r30
oris r30, r30, 512
ori r30, r30, 8192
or r0, r0, r30
mtmsr r0
#ifdef USE_DP_FPU
/* Buffer address is in r3. Save each flop register into an offset from
this buffer address. */
stfd f0, 0(r3)
stfd f1, 8(r3)
stfd f2, 16(r3)
stfd f3, 24(r3)
stfd f4, 32(r3)
stfd f5, 40(r3)
stfd f6, 48(r3)
stfd f7, 56(r3)
stfd f8, 64(r3)
stfd f9, 72(r3)
stfd f10, 80(r3)
stfd f11, 88(r3)
stfd f12, 96(r3)
stfd f13, 104(r3)
stfd f14, 112(r3)
stfd f15, 120(r3)
stfd f16, 128(r3)
stfd f17, 136(r3)
stfd f18, 144(r3)
stfd f19, 152(r3)
stfd f20, 160(r3)
stfd f21, 168(r3)
stfd f22, 176(r3)
stfd f23, 184(r3)
stfd f24, 192(r3)
stfd f25, 200(r3)
stfd f26, 208(r3)
stfd f27, 216(r3)
stfd f28, 224(r3)
stfd f29, 232(r3)
stfd f30, 240(r3)
stfd f31, 248(r3)
/* Also save the FPSCR. */
mffs f31
stfs f31, 256(r3)
#else
/* Buffer address is in r3. Save each flop register into an offset from
this buffer address. */
stfs f0, 0(r3)
stfs f1, 4(r3)
stfs f2, 8(r3)
stfs f3, 12(r3)
stfs f4, 16(r3)
stfs f5, 20(r3)
stfs f6, 24(r3)
stfs f7, 28(r3)
stfs f8, 32(r3)
stfs f9, 36(r3)
stfs f10, 40(r3)
stfs f11, 44(r3)
stfs f12, 48(r3)
stfs f13, 52(r3)
stfs f14, 56(r3)
stfs f15, 60(r3)
stfs f16, 64(r3)
stfs f17, 68(r3)
stfs f18, 72(r3)
stfs f19, 76(r3)
stfs f20, 80(r3)
stfs f21, 84(r3)
stfs f22, 88(r3)
stfs f23, 92(r3)
stfs f24, 96(r3)
stfs f25, 100(r3)
stfs f26, 104(r3)
stfs f27, 108(r3)
stfs f28, 112(r3)
stfs f29, 116(r3)
stfs f30, 120(r3)
stfs f31, 124(r3)
/* Also save the FPSCR. */
mffs f31
stfs f31, 128(r3)
#endif
blr
#endif /* configUSE_FPU. */
#if configUSE_FPU == 1
vPortRestoreFPURegisters:
/* Enable APU and mark FPU as present. */
mfmsr r0
xor r30, r30, r30
oris r30, r30, 512
ori r30, r30, 8192
or r0, r0, r30
mtmsr r0
#ifdef USE_DP_FPU
/* Buffer address is in r3. Restore each flop register from an offset
into this buffer.
First the FPSCR. */
lfs f31, 256(r3)
mtfsf f31, 7
lfd f0, 0(r3)
lfd f1, 8(r3)
lfd f2, 16(r3)
lfd f3, 24(r3)
lfd f4, 32(r3)
lfd f5, 40(r3)
lfd f6, 48(r3)
lfd f7, 56(r3)
lfd f8, 64(r3)
lfd f9, 72(r3)
lfd f10, 80(r3)
lfd f11, 88(r3)
lfd f12, 96(r3)
lfd f13, 104(r3)
lfd f14, 112(r3)
lfd f15, 120(r3)
lfd f16, 128(r3)
lfd f17, 136(r3)
lfd f18, 144(r3)
lfd f19, 152(r3)
lfd f20, 160(r3)
lfd f21, 168(r3)
lfd f22, 176(r3)
lfd f23, 184(r3)
lfd f24, 192(r3)
lfd f25, 200(r3)
lfd f26, 208(r3)
lfd f27, 216(r3)
lfd f28, 224(r3)
lfd f29, 232(r3)
lfd f30, 240(r3)
lfd f31, 248(r3)
#else
/* Buffer address is in r3. Restore each flop register from an offset
into this buffer.
First the FPSCR. */
lfs f31, 128(r3)
mtfsf f31, 7
lfs f0, 0(r3)
lfs f1, 4(r3)
lfs f2, 8(r3)
lfs f3, 12(r3)
lfs f4, 16(r3)
lfs f5, 20(r3)
lfs f6, 24(r3)
lfs f7, 28(r3)
lfs f8, 32(r3)
lfs f9, 36(r3)
lfs f10, 40(r3)
lfs f11, 44(r3)
lfs f12, 48(r3)
lfs f13, 52(r3)
lfs f14, 56(r3)
lfs f15, 60(r3)
lfs f16, 64(r3)
lfs f17, 68(r3)
lfs f18, 72(r3)
lfs f19, 76(r3)
lfs f20, 80(r3)
lfs f21, 84(r3)
lfs f22, 88(r3)
lfs f23, 92(r3)
lfs f24, 96(r3)
lfs f25, 100(r3)
lfs f26, 104(r3)
lfs f27, 108(r3)
lfs f28, 112(r3)
lfs f29, 116(r3)
lfs f30, 120(r3)
lfs f31, 124(r3)
#endif
blr
#endif /* configUSE_FPU. */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 12,721 | portable/GCC/ARM_AARCH64/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.text
/* Variables and functions. */
.extern ullMaxAPIPriorityMask
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ullPortInterruptNesting
.extern ullPortTaskHasFPUContext
.extern ullCriticalNesting
.extern ullPortYieldRequired
.extern ullICCEOIR
.extern ullICCIAR
.extern _freertos_vector_table
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Save the entire context. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X20, X21, [SP, #-0x10]!
STP X22, X23, [SP, #-0x10]!
STP X24, X25, [SP, #-0x10]!
STP X26, X27, [SP, #-0x10]!
STP X28, X29, [SP, #-0x10]!
STP X30, XZR, [SP, #-0x10]!
/* Save the SPSR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
/* Save the ELR. */
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Save the critical section nesting depth. */
LDR X0, ullCriticalNestingConst
LDR X3, [X0]
/* Save the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
LDR X2, [X0]
/* Save the FPU context, if any (32 128-bit registers). */
CMP X2, #0
B.EQ 1f
STP Q0, Q1, [SP,#-0x20]!
STP Q2, Q3, [SP,#-0x20]!
STP Q4, Q5, [SP,#-0x20]!
STP Q6, Q7, [SP,#-0x20]!
STP Q8, Q9, [SP,#-0x20]!
STP Q10, Q11, [SP,#-0x20]!
STP Q12, Q13, [SP,#-0x20]!
STP Q14, Q15, [SP,#-0x20]!
STP Q16, Q17, [SP,#-0x20]!
STP Q18, Q19, [SP,#-0x20]!
STP Q20, Q21, [SP,#-0x20]!
STP Q22, Q23, [SP,#-0x20]!
STP Q24, Q25, [SP,#-0x20]!
STP Q26, Q27, [SP,#-0x20]!
STP Q28, Q29, [SP,#-0x20]!
STP Q30, Q31, [SP,#-0x20]!
1:
/* Store the critical nesting count and FPU context indicator. */
STP X2, X3, [SP, #-0x10]!
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
MOV X0, SP /* Move SP into X0 for saving. */
STR X0, [X1]
/* Switch to use the ELx stack pointer. */
MSR SPSEL, #1
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Set the SP to point to the stack of the task being restored. */
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
LDR X0, [X1]
MOV SP, X0
LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
/* Set the PMR register to be correct for the current critical nesting
depth. */
LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
MOV X1, #255 /* X1 holds the unmask value. */
LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
CMP X3, #0
LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
B.EQ 1f
LDR X6, ullMaxAPIPriorityMaskConst
LDR X1, [X6] /* X1 holds the mask value. */
1:
STR W1, [X5] /* Write the mask value to ICCPMR. */
DSB SY /* _RB_Barriers probably not required here. */
ISB SY
STR X3, [X0] /* Restore the task's critical nesting count. */
/* Restore the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
STR X2, [X0]
/* Restore the FPU context, if any. */
CMP X2, #0
B.EQ 1f
LDP Q30, Q31, [SP], #0x20
LDP Q28, Q29, [SP], #0x20
LDP Q26, Q27, [SP], #0x20
LDP Q24, Q25, [SP], #0x20
LDP Q22, Q23, [SP], #0x20
LDP Q20, Q21, [SP], #0x20
LDP Q18, Q19, [SP], #0x20
LDP Q16, Q17, [SP], #0x20
LDP Q14, Q15, [SP], #0x20
LDP Q12, Q13, [SP], #0x20
LDP Q10, Q11, [SP], #0x20
LDP Q8, Q9, [SP], #0x20
LDP Q6, Q7, [SP], #0x20
LDP Q4, Q5, [SP], #0x20
LDP Q2, Q3, [SP], #0x20
LDP Q0, Q1, [SP], #0x20
1:
LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
/* Restore the SPSR. */
MSR SPSR_EL1, X3
/* Restore the ELR. */
MSR ELR_EL1, X2
#else
/* Restore the SPSR. */
MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
/* Restore the ELR. */
MSR ELR_EL3, X2
#endif
LDP X30, XZR, [SP], #0x10
LDP X28, X29, [SP], #0x10
LDP X26, X27, [SP], #0x10
LDP X24, X25, [SP], #0x10
LDP X22, X23, [SP], #0x10
LDP X20, X21, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
MSR SPSEL, #1
ERET
.endm
/******************************************************************************
* FreeRTOS_SWI_Handler handler is used to perform a context switch.
*****************************************************************************/
.align 8
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
#if defined( GUEST )
MRS X0, ESR_EL1
#else
MRS X0, ESR_EL3
#endif
LSR X1, X0, #26
#if defined( GUEST )
CMP X1, #0x15 /* 0x15 = SVC instruction. */
#else
CMP X1, #0x17 /* 0x17 = SMC instruction. */
#endif
B.NE FreeRTOS_Abort
BL vTaskSwitchContext
portRESTORE_CONTEXT
FreeRTOS_Abort:
/* Full ESR is in X0, exception class code is in X1. */
B .
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.align 8
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
.set freertos_vector_base, _freertos_vector_table
/* Install the FreeRTOS interrupt handlers. */
LDR X1, =freertos_vector_base
#if defined( GUEST )
MSR VBAR_EL1, X1
#else
MSR VBAR_EL3, X1
#endif
DSB SY
ISB SY
/* Start the first task. */
portRESTORE_CONTEXT
/******************************************************************************
* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
*****************************************************************************/
.align 8
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Save volatile registers. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X29, X30, [SP, #-0x10]!
/* Save the SPSR and ELR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Increment the interrupt nesting counter. */
LDR X5, ullPortInterruptNestingConst
LDR X1, [X5] /* Old nesting count in X1. */
ADD X6, X1, #1
STR X6, [X5] /* Address of nesting count variable in X5. */
/* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]!
/* Read value from the interrupt acknowledge register, which is stored in W0
for future parameter and interrupt clearing use. */
LDR X2, ullICCIARConst
LDR X3, [X2]
LDR W0, [X3] /* ICCIAR in W0 as parameter. */
/* Maintain the ICCIAR value across the function call. */
STP X0, X1, [SP, #-0x10]!
/* Call the C handler. */
BL vApplicationIRQHandler
/* Disable interrupts. */
MSR DAIFSET, #2
DSB SY
ISB SY
/* Restore the ICCIAR value. */
LDP X0, X1, [SP], #0x10
/* End IRQ processing by writing ICCIAR to the EOI register. */
LDR X4, ullICCEOIRConst
LDR X4, [X4]
STR W0, [X4]
/* Restore the critical nesting count. */
LDP X1, X5, [SP], #0x10
STR X1, [X5]
/* Has interrupt nesting unwound? */
CMP X1, #0
B.NE Exit_IRQ_No_Context_Switch
/* Is a context switch required? */
LDR X0, ullPortYieldRequiredConst
LDR X1, [X0]
CMP X1, #0
B.EQ Exit_IRQ_No_Context_Switch
/* Reset ullPortYieldRequired to 0. */
MOV X2, #0
STR X2, [X0]
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
BL vTaskSwitchContext
portRESTORE_CONTEXT
Exit_IRQ_No_Context_Switch:
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
ERET
.align 8
pxCurrentTCBConst: .dword pxCurrentTCB
ullCriticalNestingConst: .dword ullCriticalNesting
ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
ullICCPMRConst: .dword ullICCPMR
ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
ullPortInterruptNestingConst: .dword ullPortInterruptNesting
ullPortYieldRequiredConst: .dword ullPortYieldRequired
ullICCIARConst: .dword ullICCIAR
ullICCEOIRConst: .dword ullICCEOIR
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 5,225 | portable/GCC/MicroBlaze/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.extern pxCurrentTCB
.extern vTaskISRHandler
.extern vTaskSwitchContext
.extern uxCriticalNesting
.extern pulISRStack
.global __FreeRTOS_interrupt_handler
.global VPortYieldASM
.global vStartFirstTask
.macro portSAVE_CONTEXT
/* Make room for the context on the stack. */
addik r1, r1, -132
/* Save r31 so it can then be used. */
swi r31, r1, 4
/* Copy the msr into r31 - this is stacked later. */
mfs r31, rmsr
/* Stack general registers. */
swi r30, r1, 12
swi r29, r1, 16
swi r28, r1, 20
swi r27, r1, 24
swi r26, r1, 28
swi r25, r1, 32
swi r24, r1, 36
swi r23, r1, 40
swi r22, r1, 44
swi r21, r1, 48
swi r20, r1, 52
swi r19, r1, 56
swi r18, r1, 60
swi r17, r1, 64
swi r16, r1, 68
swi r15, r1, 72
swi r13, r1, 80
swi r12, r1, 84
swi r11, r1, 88
swi r10, r1, 92
swi r9, r1, 96
swi r8, r1, 100
swi r7, r1, 104
swi r6, r1, 108
swi r5, r1, 112
swi r4, r1, 116
swi r3, r1, 120
swi r2, r1, 124
/* Stack the critical section nesting value. */
lwi r3, r0, uxCriticalNesting
swi r3, r1, 128
/* Save the top of stack value to the TCB. */
lwi r3, r0, pxCurrentTCB
sw r1, r0, r3
.endm
.macro portRESTORE_CONTEXT
/* Load the top of stack value from the TCB. */
lwi r3, r0, pxCurrentTCB
lw r1, r0, r3
/* Restore the general registers. */
lwi r31, r1, 4
lwi r30, r1, 12
lwi r29, r1, 16
lwi r28, r1, 20
lwi r27, r1, 24
lwi r26, r1, 28
lwi r25, r1, 32
lwi r24, r1, 36
lwi r23, r1, 40
lwi r22, r1, 44
lwi r21, r1, 48
lwi r20, r1, 52
lwi r19, r1, 56
lwi r18, r1, 60
lwi r17, r1, 64
lwi r16, r1, 68
lwi r15, r1, 72
lwi r14, r1, 76
lwi r13, r1, 80
lwi r12, r1, 84
lwi r11, r1, 88
lwi r10, r1, 92
lwi r9, r1, 96
lwi r8, r1, 100
lwi r7, r1, 104
lwi r6, r1, 108
lwi r5, r1, 112
lwi r4, r1, 116
lwi r2, r1, 124
/* Load the critical nesting value. */
lwi r3, r1, 128
swi r3, r0, uxCriticalNesting
/* Obtain the MSR value from the stack. */
lwi r3, r1, 8
/* Are interrupts enabled in the MSR? If so return using an return from
interrupt instruction to ensure interrupts are enabled only once the task
is running again. */
andi r3, r3, 2
beqid r3, 36
or r0, r0, r0
/* Reload the rmsr from the stack, clear the enable interrupt bit in the
value before saving back to rmsr register, then return enabling interrupts
as we return. */
lwi r3, r1, 8
andi r3, r3, ~2
mts rmsr, r3
lwi r3, r1, 120
addik r1, r1, 132
rtid r14, 0
or r0, r0, r0
/* Reload the rmsr from the stack, place it in the rmsr register, and
return without enabling interrupts. */
lwi r3, r1, 8
mts rmsr, r3
lwi r3, r1, 120
addik r1, r1, 132
rtsd r14, 0
or r0, r0, r0
.endm
.text
.align 2
__FreeRTOS_interrupt_handler:
portSAVE_CONTEXT
/* Entered via an interrupt so interrupts must be enabled in msr. */
ori r31, r31, 2
/* Stack msr. */
swi r31, r1, 8
/* Stack the return address. As we entered via an interrupt we do
not need to modify the return address prior to stacking. */
swi r14, r1, 76
/* Now switch to use the ISR stack. */
lwi r3, r0, pulISRStack
add r1, r3, r0
bralid r15, vTaskISRHandler
or r0, r0, r0
portRESTORE_CONTEXT
VPortYieldASM:
portSAVE_CONTEXT
/* Stack msr. */
swi r31, r1, 8
/* Modify the return address so we return to the instruction after the
exception. */
addi r14, r14, 8
swi r14, r1, 76
/* Now switch to use the ISR stack. */
lwi r3, r0, pulISRStack
add r1, r3, r0
bralid r15, vTaskSwitchContext
or r0, r0, r0
portRESTORE_CONTEXT
vStartFirstTask:
portRESTORE_CONTEXT
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 12,790 | portable/GCC/ARM_AARCH64_SRE/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.text
/* Variables and functions. */
.extern ullMaxAPIPriorityMask
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ullPortInterruptNesting
.extern ullPortTaskHasFPUContext
.extern ullCriticalNesting
.extern ullPortYieldRequired
.extern _freertos_vector_table
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Save the entire context. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X20, X21, [SP, #-0x10]!
STP X22, X23, [SP, #-0x10]!
STP X24, X25, [SP, #-0x10]!
STP X26, X27, [SP, #-0x10]!
STP X28, X29, [SP, #-0x10]!
STP X30, XZR, [SP, #-0x10]!
/* Save the SPSR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
/* Save the ELR. */
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Save the critical section nesting depth. */
LDR X0, ullCriticalNestingConst
LDR X3, [X0]
/* Save the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
LDR X2, [X0]
/* Save the FPU context, if any (32 128-bit registers). */
CMP X2, #0
B.EQ 1f
STP Q0, Q1, [SP,#-0x20]!
STP Q2, Q3, [SP,#-0x20]!
STP Q4, Q5, [SP,#-0x20]!
STP Q6, Q7, [SP,#-0x20]!
STP Q8, Q9, [SP,#-0x20]!
STP Q10, Q11, [SP,#-0x20]!
STP Q12, Q13, [SP,#-0x20]!
STP Q14, Q15, [SP,#-0x20]!
STP Q16, Q17, [SP,#-0x20]!
STP Q18, Q19, [SP,#-0x20]!
STP Q20, Q21, [SP,#-0x20]!
STP Q22, Q23, [SP,#-0x20]!
STP Q24, Q25, [SP,#-0x20]!
STP Q26, Q27, [SP,#-0x20]!
STP Q28, Q29, [SP,#-0x20]!
STP Q30, Q31, [SP,#-0x20]!
1:
/* Store the critical nesting count and FPU context indicator. */
STP X2, X3, [SP, #-0x10]!
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
MOV X0, SP /* Move SP into X0 for saving. */
STR X0, [X1]
/* Switch to use the ELx stack pointer. */
MSR SPSEL, #1
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Set the SP to point to the stack of the task being restored. */
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
LDR X0, [X1]
MOV SP, X0
LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
/* Set the PMR register to be correct for the current critical nesting
depth. */
LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
MOV X1, #255 /* X1 holds the unmask value. */
CMP X3, #0
B.EQ 1f
LDR X6, ullMaxAPIPriorityMaskConst
LDR X1, [X6] /* X1 holds the mask value. */
1:
MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */
DSB SY /* _RB_Barriers probably not required here. */
ISB SY
STR X3, [X0] /* Restore the task's critical nesting count. */
/* Restore the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
STR X2, [X0]
/* Restore the FPU context, if any. */
CMP X2, #0
B.EQ 1f
LDP Q30, Q31, [SP], #0x20
LDP Q28, Q29, [SP], #0x20
LDP Q26, Q27, [SP], #0x20
LDP Q24, Q25, [SP], #0x20
LDP Q22, Q23, [SP], #0x20
LDP Q20, Q21, [SP], #0x20
LDP Q18, Q19, [SP], #0x20
LDP Q16, Q17, [SP], #0x20
LDP Q14, Q15, [SP], #0x20
LDP Q12, Q13, [SP], #0x20
LDP Q10, Q11, [SP], #0x20
LDP Q8, Q9, [SP], #0x20
LDP Q6, Q7, [SP], #0x20
LDP Q4, Q5, [SP], #0x20
LDP Q2, Q3, [SP], #0x20
LDP Q0, Q1, [SP], #0x20
1:
LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
/* Restore the SPSR. */
MSR SPSR_EL1, X3
/* Restore the ELR. */
MSR ELR_EL1, X2
#else
/* Restore the SPSR. */
MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
/* Restore the ELR. */
MSR ELR_EL3, X2
#endif
LDP X30, XZR, [SP], #0x10
LDP X28, X29, [SP], #0x10
LDP X26, X27, [SP], #0x10
LDP X24, X25, [SP], #0x10
LDP X22, X23, [SP], #0x10
LDP X20, X21, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
MSR SPSEL, #1
ERET
.endm
/******************************************************************************
* FreeRTOS_SWI_Handler handler is used to perform a context switch.
*****************************************************************************/
.align 8
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
#if defined( GUEST )
MRS X0, ESR_EL1
#else
MRS X0, ESR_EL3
#endif
LSR X1, X0, #26
#if defined( GUEST )
CMP X1, #0x15 /* 0x15 = SVC instruction. */
#else
CMP X1, #0x17 /* 0x17 = SMC instruction. */
#endif
B.NE FreeRTOS_Abort
BL vTaskSwitchContext
portRESTORE_CONTEXT
FreeRTOS_Abort:
/* Full ESR is in X0, exception class code is in X1. */
B .
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.align 8
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
.set freertos_vector_base, _freertos_vector_table
/* Install the FreeRTOS interrupt handlers. */
LDR X1, =freertos_vector_base
#if defined( GUEST )
MSR VBAR_EL1, X1
#else
MSR VBAR_EL3, X1
#endif
DSB SY
ISB SY
/* Start the first task. */
portRESTORE_CONTEXT
/******************************************************************************
* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
* This handler is supposed to be used only for IRQs and never for FIQs. Per ARM
* GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since
* this handler is only for IRQs, We can safely assume Group 1 while accessing
* Interrupt Acknowledge and End Of Interrupt registers and therefore, use
* ICC_IAR1_EL1 and ICC_EOIR1_EL1.
*
* [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals
*****************************************************************************/
.align 8
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Save volatile registers. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X29, X30, [SP, #-0x10]!
/* Save the SPSR and ELR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Increment the interrupt nesting counter. */
LDR X5, ullPortInterruptNestingConst
LDR X1, [X5] /* Old nesting count in X1. */
ADD X6, X1, #1
STR X6, [X5] /* Address of nesting count variable in X5. */
/* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]!
/* Read interrupt ID from the interrupt acknowledge register and store it
in X0 for future parameter and interrupt clearing use. */
MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */
/* Maintain the interrupt ID value across the function call. */
STP X0, X1, [SP, #-0x10]!
/* Call the C handler. */
BL vApplicationIRQHandler
/* Disable interrupts. */
MSR DAIFSET, #2
DSB SY
ISB SY
/* Restore the interrupt ID value. */
LDP X0, X1, [SP], #0x10
/* End IRQ processing by writing interrupt ID value to the EOI register. */
MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */
/* Restore the critical nesting count. */
LDP X1, X5, [SP], #0x10
STR X1, [X5]
/* Has interrupt nesting unwound? */
CMP X1, #0
B.NE Exit_IRQ_No_Context_Switch
/* Is a context switch required? */
LDR X0, ullPortYieldRequiredConst
LDR X1, [X0]
CMP X1, #0
B.EQ Exit_IRQ_No_Context_Switch
/* Reset ullPortYieldRequired to 0. */
MOV X2, #0
STR X2, [X0]
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
BL vTaskSwitchContext
portRESTORE_CONTEXT
Exit_IRQ_No_Context_Switch:
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
ERET
.align 8
pxCurrentTCBConst: .dword pxCurrentTCB
ullCriticalNestingConst: .dword ullCriticalNesting
ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
ullPortInterruptNestingConst: .dword ullPortInterruptNesting
ullPortYieldRequiredConst: .dword ullPortYieldRequired
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 17,991 | portable/GCC/RISC-V/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
*
* + The code that is common to all RISC-V chips is implemented in
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
* portASM.S file because the same file is used no matter which RISC-V chip is
* in use.
*
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
* RISC-V chip that both includes a standard CLINT and does not add to the
* base set of RISC-V registers. There are additional
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
* that do not include a standard CLINT or do add to the base set of RISC-V
* registers.
*
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
* header file ensure the path to the correct header file is in the assembler's
* include path.
*
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
* that include a standard CLINT and do not add to the base set of RISC-V
* registers.
*
*/
#include "portContext.h"
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
definitions. */
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifdef portasmHAS_CLINT
#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#define portasmHAS_MTIME portasmHAS_CLINT
#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
#endif
#ifndef portasmHAS_MTIME
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef portasmHAS_SIFIVE_CLINT
#define portasmHAS_SIFIVE_CLINT 0
#endif
.global xPortStartFirstTask
.global pxPortInitialiseStack
.global freertos_risc_v_trap_handler
.global freertos_risc_v_exception_handler
.global freertos_risc_v_interrupt_handler
.global freertos_risc_v_mtimer_interrupt_handler
.extern vTaskSwitchContext
.extern xTaskIncrementTick
.extern pullMachineTimerCompareRegister
.extern pullNextTime
.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
.extern xTaskReturnAddress
.weak freertos_risc_v_application_exception_handler
.weak freertos_risc_v_application_interrupt_handler
/*-----------------------------------------------------------*/
.macro portUPDATE_MTIMER_COMPARE_REGISTER
load_x a0, pullMachineTimerCompareRegister /* Load address of compare register into a0. */
load_x a1, pullNextTime /* Load the address of ullNextTime into a1. */
#if( __riscv_xlen == 32 )
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
li a4, -1
lw a2, 0(a1) /* Load the low word of ullNextTime into a2. */
lw a3, 4(a1) /* Load the high word of ullNextTime into a3. */
sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwritten below. */
sw a3, 4(a0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
sw a2, 0(a0) /* Store low word of ullNextTime into compare register. */
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add a4, t0, a2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
sltu t1, a4, a2 /* See if the sum of low words overflowed (what about the zero case?). */
add t2, a3, t1 /* Add overflow to high word of ullNextTime. */
sw a4, 0(a1) /* Store new low word of ullNextTime. */
sw t2, 4(a1) /* Store new high word of ullNextTime. */
#endif /* __riscv_xlen == 32 */
#if( __riscv_xlen == 64 )
/* Update the 64-bit mtimer compare match value. */
ld t2, 0(a1) /* Load ullNextTime into t2. */
sd t2, 0(a0) /* Store ullNextTime into compare register. */
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
sd t4, 0(a1) /* Store ullNextTime. */
#endif /* __riscv_xlen == 64 */
.endm
/*-----------------------------------------------------------*/
/*
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
* for the function is as per the other ports:
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
*
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
*
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
*
* Register ABI Name Description Saver
* x0 zero Hard-wired zero -
* x1 ra Return address Caller
* x2 sp Stack pointer Callee
* x3 gp Global pointer -
* x4 tp Thread pointer -
* x5-7 t0-2 Temporaries Caller
* x8 s0/fp Saved register/Frame pointer Callee
* x9 s1 Saved register Callee
* x10-11 a0-1 Function Arguments/return values Caller
* x12-17 a2-7 Function arguments Caller
* x18-27 s2-11 Saved registers Callee
* x28-31 t3-6 Temporaries Caller
*
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
* where the global and thread pointers are currently assumed to be constant so
* are not saved:
*
* mstatus
* xCriticalNesting
* x31
* x30
* x29
* x28
* x27
* x26
* x25
* x24
* x23
* x22
* x21
* x20
* x19
* x18
* x17
* x16
* x15
* x14
* x13
* x12
* x11
* pvParameters
* x9
* x8
* x7
* x6
* x5
* portTASK_RETURN_ADDRESS
* [chip specific registers go here]
* pxCode
*/
pxPortInitialiseStack:
csrr t0, mstatus /* Obtain current mstatus value. */
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
slli t1, t1, 4
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
addi a0, a0, -portWORD_SIZE
store_x t0, 0(a0) /* mstatus onto the stack. */
addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
#ifdef __riscv_32e
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-x15. */
#else
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
#endif
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
load_x t0, xTaskReturnAddress
store_x t0, 0(a0) /* Return address onto the stack. */
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
beq t0, x0, 1f /* No more chip specific registers to save. */
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
j chip_specific_stack_frame /* Until no more chip specific registers. */
1:
addi a0, a0, -portWORD_SIZE
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
ret
/*-----------------------------------------------------------*/
xPortStartFirstTask:
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( sp ) /* Read sp from first TCB member. */
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
#ifndef __riscv_32e
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
#endif
load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
addi sp, sp, portCONTEXT_SIZE
ret
/*-----------------------------------------------------------*/
freertos_risc_v_application_exception_handler:
csrr t0, mcause /* For viewing in the debugger only. */
csrr t1, mepc /* For viewing in the debugger only */
csrr t2, mstatus /* For viewing in the debugger only */
j .
/*-----------------------------------------------------------*/
freertos_risc_v_application_interrupt_handler:
csrr t0, mcause /* For viewing in the debugger only. */
csrr t1, mepc /* For viewing in the debugger only */
csrr t2, mstatus /* For viewing in the debugger only */
j .
/*-----------------------------------------------------------*/
.section .text.freertos_risc_v_exception_handler
freertos_risc_v_exception_handler:
portcontextSAVE_EXCEPTION_CONTEXT
/* a0 now contains mcause. */
li t0, 11 /* 11 == environment call. */
bne a0, t0, other_exception /* Not an M environment call, so some other exception. */
call vTaskSwitchContext
portcontextRESTORE_CONTEXT
other_exception:
call freertos_risc_v_application_exception_handler
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
.section .text.freertos_risc_v_interrupt_handler
freertos_risc_v_interrupt_handler:
portcontextSAVE_INTERRUPT_CONTEXT
call freertos_risc_v_application_interrupt_handler
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
.section .text.freertos_risc_v_mtimer_interrupt_handler
freertos_risc_v_mtimer_interrupt_handler:
portcontextSAVE_INTERRUPT_CONTEXT
portUPDATE_MTIMER_COMPARE_REGISTER
call xTaskIncrementTick
beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
call vTaskSwitchContext
exit_without_context_switch:
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
.section .text.freertos_risc_v_trap_handler
.align 8
freertos_risc_v_trap_handler:
portcontextSAVE_CONTEXT_INTERNAL
csrr a0, mcause
csrr a1, mepc
bge a0, x0, synchronous_exception
asynchronous_interrupt:
store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
load_x sp, xISRStackTop /* Switch to ISR stack. */
j handle_interrupt
synchronous_exception:
addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
store_x a1, 0( sp ) /* Save updated exception return address. */
load_x sp, xISRStackTop /* Switch to ISR stack. */
j handle_exception
handle_interrupt:
#if( portasmHAS_MTIME != 0 )
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
addi t0, x0, 1
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
bne a0, t1, application_interrupt_handler
portUPDATE_MTIMER_COMPARE_REGISTER
call xTaskIncrementTick
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
call vTaskSwitchContext
j processed_source
#endif /* portasmHAS_MTIME */
application_interrupt_handler:
call freertos_risc_v_application_interrupt_handler
j processed_source
handle_exception:
/* a0 contains mcause. */
li t0, 11 /* 11 == environment call. */
bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */
call vTaskSwitchContext
j processed_source
application_exception_handler:
call freertos_risc_v_application_exception_handler
j processed_source /* No other exceptions handled yet. */
processed_source:
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 9,422 | portable/GCC/MicroBlazeV8/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* FreeRTOS includes. */
#include "FreeRTOSConfig.h"
/* Xilinx library includes. */
#include "microblaze_exceptions_g.h"
#include "xparameters.h"
/* The context is oversized to allow functions called from the ISR to write
back into the caller stack. */
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
#define portCONTEXT_SIZE 136
#define portMINUS_CONTEXT_SIZE -136
#else
#define portCONTEXT_SIZE 132
#define portMINUS_CONTEXT_SIZE -132
#endif
/* Offsets from the stack pointer at which saved registers are placed. */
#define portR31_OFFSET 4
#define portR30_OFFSET 8
#define portR29_OFFSET 12
#define portR28_OFFSET 16
#define portR27_OFFSET 20
#define portR26_OFFSET 24
#define portR25_OFFSET 28
#define portR24_OFFSET 32
#define portR23_OFFSET 36
#define portR22_OFFSET 40
#define portR21_OFFSET 44
#define portR20_OFFSET 48
#define portR19_OFFSET 52
#define portR18_OFFSET 56
#define portR17_OFFSET 60
#define portR16_OFFSET 64
#define portR15_OFFSET 68
#define portR14_OFFSET 72
#define portR13_OFFSET 76
#define portR12_OFFSET 80
#define portR11_OFFSET 84
#define portR10_OFFSET 88
#define portR9_OFFSET 92
#define portR8_OFFSET 96
#define portR7_OFFSET 100
#define portR6_OFFSET 104
#define portR5_OFFSET 108
#define portR4_OFFSET 112
#define portR3_OFFSET 116
#define portR2_OFFSET 120
#define portCRITICAL_NESTING_OFFSET 124
#define portMSR_OFFSET 128
#define portFSR_OFFSET 132
.extern pxCurrentTCB
.extern XIntc_DeviceInterruptHandler
.extern vTaskSwitchContext
.extern uxCriticalNesting
.extern pulISRStack
.extern ulTaskSwitchRequested
.extern vPortExceptionHandler
.extern pulStackPointerOnFunctionEntry
.global _interrupt_handler
.global VPortYieldASM
.global vPortStartFirstTask
.global vPortExceptionHandlerEntry
.macro portSAVE_CONTEXT
/* Make room for the context on the stack. */
addik r1, r1, portMINUS_CONTEXT_SIZE
/* Stack general registers. */
swi r31, r1, portR31_OFFSET
swi r30, r1, portR30_OFFSET
swi r29, r1, portR29_OFFSET
swi r28, r1, portR28_OFFSET
swi r27, r1, portR27_OFFSET
swi r26, r1, portR26_OFFSET
swi r25, r1, portR25_OFFSET
swi r24, r1, portR24_OFFSET
swi r23, r1, portR23_OFFSET
swi r22, r1, portR22_OFFSET
swi r21, r1, portR21_OFFSET
swi r20, r1, portR20_OFFSET
swi r19, r1, portR19_OFFSET
swi r18, r1, portR18_OFFSET
swi r17, r1, portR17_OFFSET
swi r16, r1, portR16_OFFSET
swi r15, r1, portR15_OFFSET
/* R14 is saved later as it needs adjustment if a yield is performed. */
swi r13, r1, portR13_OFFSET
swi r12, r1, portR12_OFFSET
swi r11, r1, portR11_OFFSET
swi r10, r1, portR10_OFFSET
swi r9, r1, portR9_OFFSET
swi r8, r1, portR8_OFFSET
swi r7, r1, portR7_OFFSET
swi r6, r1, portR6_OFFSET
swi r5, r1, portR5_OFFSET
swi r4, r1, portR4_OFFSET
swi r3, r1, portR3_OFFSET
swi r2, r1, portR2_OFFSET
/* Stack the critical section nesting value. */
lwi r18, r0, uxCriticalNesting
swi r18, r1, portCRITICAL_NESTING_OFFSET
/* Stack MSR. */
mfs r18, rmsr
swi r18, r1, portMSR_OFFSET
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* Stack FSR. */
mfs r18, rfsr
swi r18, r1, portFSR_OFFSET
#endif
/* Save the top of stack value to the TCB. */
lwi r3, r0, pxCurrentTCB
sw r1, r0, r3
.endm
.macro portRESTORE_CONTEXT
/* Load the top of stack value from the TCB. */
lwi r18, r0, pxCurrentTCB
lw r1, r0, r18
/* Restore the general registers. */
lwi r31, r1, portR31_OFFSET
lwi r30, r1, portR30_OFFSET
lwi r29, r1, portR29_OFFSET
lwi r28, r1, portR28_OFFSET
lwi r27, r1, portR27_OFFSET
lwi r26, r1, portR26_OFFSET
lwi r25, r1, portR25_OFFSET
lwi r24, r1, portR24_OFFSET
lwi r23, r1, portR23_OFFSET
lwi r22, r1, portR22_OFFSET
lwi r21, r1, portR21_OFFSET
lwi r20, r1, portR20_OFFSET
lwi r19, r1, portR19_OFFSET
lwi r17, r1, portR17_OFFSET
lwi r16, r1, portR16_OFFSET
lwi r15, r1, portR15_OFFSET
lwi r14, r1, portR14_OFFSET
lwi r13, r1, portR13_OFFSET
lwi r12, r1, portR12_OFFSET
lwi r11, r1, portR11_OFFSET
lwi r10, r1, portR10_OFFSET
lwi r9, r1, portR9_OFFSET
lwi r8, r1, portR8_OFFSET
lwi r7, r1, portR7_OFFSET
lwi r6, r1, portR6_OFFSET
lwi r5, r1, portR5_OFFSET
lwi r4, r1, portR4_OFFSET
lwi r3, r1, portR3_OFFSET
lwi r2, r1, portR2_OFFSET
/* Reload the rmsr from the stack. */
lwi r18, r1, portMSR_OFFSET
mts rmsr, r18
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* Reload the FSR from the stack. */
lwi r18, r1, portFSR_OFFSET
mts rfsr, r18
#endif
/* Load the critical nesting value. */
lwi r18, r1, portCRITICAL_NESTING_OFFSET
swi r18, r0, uxCriticalNesting
/* Test the critical nesting value. If it is non zero then the task last
exited the running state using a yield. If it is zero, then the task
last exited the running state through an interrupt. */
xori r18, r18, 0
bnei r18, exit_from_yield
/* r18 was being used as a temporary. Now restore its true value from the
stack. */
lwi r18, r1, portR18_OFFSET
/* Remove the stack frame. */
addik r1, r1, portCONTEXT_SIZE
/* Return using rtid so interrupts are re-enabled as this function is
exited. */
rtid r14, 0
or r0, r0, r0
.endm
/* This function is used to exit portRESTORE_CONTEXT() if the task being
returned to last left the Running state by calling taskYIELD() (rather than
being preempted by an interrupt). */
.text
.align 4
exit_from_yield:
/* r18 was being used as a temporary. Now restore its true value from the
stack. */
lwi r18, r1, portR18_OFFSET
/* Remove the stack frame. */
addik r1, r1, portCONTEXT_SIZE
/* Return to the task. */
rtsd r14, 0
or r0, r0, r0
.text
.align 4
_interrupt_handler:
portSAVE_CONTEXT
/* Stack the return address. */
swi r14, r1, portR14_OFFSET
/* Switch to the ISR stack. */
lwi r1, r0, pulISRStack
/* The parameter to the interrupt handler. */
ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
/* Execute any pending interrupts. */
bralid r15, XIntc_DeviceInterruptHandler
or r0, r0, r0
/* See if a new task should be selected to execute. */
lwi r18, r0, ulTaskSwitchRequested
or r18, r18, r0
/* If ulTaskSwitchRequested is already zero, then jump straight to
restoring the task that is already in the Running state. */
beqi r18, task_switch_not_requested
/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
performed. */
swi r0, r0, ulTaskSwitchRequested
/* ulTaskSwitchRequested was not 0 when tested. Select the next task to
execute. */
bralid r15, vTaskSwitchContext
or r0, r0, r0
task_switch_not_requested:
/* Restore the context of the next task scheduled to execute. */
portRESTORE_CONTEXT
.text
.align 4
VPortYieldASM:
portSAVE_CONTEXT
/* Modify the return address so a return is done to the instruction after
the call to VPortYieldASM. */
addi r14, r14, 8
swi r14, r1, portR14_OFFSET
/* Switch to use the ISR stack. */
lwi r1, r0, pulISRStack
/* Select the next task to execute. */
bralid r15, vTaskSwitchContext
or r0, r0, r0
/* Restore the context of the next task scheduled to execute. */
portRESTORE_CONTEXT
.text
.align 4
vPortStartFirstTask:
portRESTORE_CONTEXT
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
.text
.align 4
vPortExceptionHandlerEntry:
/* Take a copy of the stack pointer before vPortExecptionHandler is called,
storing its value prior to the function stack frame being created. */
swi r1, r0, pulStackPointerOnFunctionEntry
bralid r15, vPortExceptionHandler
or r0, r0, r0
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 8,891 | portable/GCC/PPC405_Xilinx/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "FreeRTOSConfig.h"
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern xTaskIncrementTick
.extern vPortISRHandler
.global vPortStartFirstTask
.global vPortYield
.global vPortTickISR
.global vPortISRWrapper
.global vPortSaveFPURegisters
.global vPortRestoreFPURegisters
.set BChainField, 0
.set NextLRField, BChainField + 4
.set MSRField, NextLRField + 4
.set PCField, MSRField + 4
.set LRField, PCField + 4
.set CTRField, LRField + 4
.set XERField, CTRField + 4
.set CRField, XERField + 4
.set USPRG0Field, CRField + 4
.set r0Field, USPRG0Field + 4
.set r2Field, r0Field + 4
.set r3r31Field, r2Field + 4
.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
.macro portSAVE_STACK_POINTER_AND_LR
/* Get the address of the TCB. */
xor R0, R0, R0
addis R2, R0, pxCurrentTCB@ha
lwz R2, pxCurrentTCB@l( R2 )
/* Store the stack pointer into the TCB */
stw SP, 0( R2 )
/* Save the link register */
stwu R1, -24( R1 )
mflr R0
stw R31, 20( R1 )
stw R0, 28( R1 )
mr R31, r1
.endm
.macro portRESTORE_STACK_POINTER_AND_LR
/* Restore the link register */
lwz R11, 0( R1 )
lwz R0, 4( R11 )
mtlr R0
lwz R31, -4( R11 )
mr R1, R11
/* Get the address of the TCB. */
xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( R1 )
/* Get the task stack pointer from the TCB. */
lwz SP, 0( SP )
.endm
vPortStartFirstTask:
/* Get the address of the TCB. */
xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( SP )
/* Get the task stack pointer from the TCB. */
lwz SP, 0( SP )
/* Restore MSR register to SRR1. */
lwz R0, MSRField(R1)
mtsrr1 R0
/* Restore current PC location to SRR0. */
lwz R0, PCField(R1)
mtsrr0 R0
/* Save USPRG0 register */
lwz R0, USPRG0Field(R1)
mtspr 0x100,R0
/* Restore Condition register */
lwz R0, CRField(R1)
mtcr R0
/* Restore Fixed Point Exception register */
lwz R0, XERField(R1)
mtxer R0
/* Restore Counter register */
lwz R0, CTRField(R1)
mtctr R0
/* Restore Link register */
lwz R0, LRField(R1)
mtlr R0
/* Restore remaining GPR registers. */
lmw R3,r3r31Field(R1)
/* Restore r0 and r2. */
lwz R0, r0Field(R1)
lwz R2, r2Field(R1)
/* Remove frame from stack */
addi R1,R1,IFrameSize
/* Return into the first task */
rfi
vPortYield:
portSAVE_STACK_POINTER_AND_LR
bl vTaskSwitchContext
portRESTORE_STACK_POINTER_AND_LR
blr
vPortTickISR:
portSAVE_STACK_POINTER_AND_LR
bl xTaskIncrementTick
#if configUSE_PREEMPTION == 1
bl vTaskSwitchContext
#endif
/* Clear the interrupt */
lis R0, 2048
mttsr R0
portRESTORE_STACK_POINTER_AND_LR
blr
vPortISRWrapper:
portSAVE_STACK_POINTER_AND_LR
bl vPortISRHandler
portRESTORE_STACK_POINTER_AND_LR
blr
#if configUSE_FPU == 1
vPortSaveFPURegisters:
/* Enable APU and mark FPU as present. */
mfmsr r0
xor r30, r30, r30
oris r30, r30, 512
ori r30, r30, 8192
or r0, r0, r30
mtmsr r0
#ifdef USE_DP_FPU
/* Buffer address is in r3. Save each flop register into an offset from
this buffer address. */
stfd f0, 0(r3)
stfd f1, 8(r3)
stfd f2, 16(r3)
stfd f3, 24(r3)
stfd f4, 32(r3)
stfd f5, 40(r3)
stfd f6, 48(r3)
stfd f7, 56(r3)
stfd f8, 64(r3)
stfd f9, 72(r3)
stfd f10, 80(r3)
stfd f11, 88(r3)
stfd f12, 96(r3)
stfd f13, 104(r3)
stfd f14, 112(r3)
stfd f15, 120(r3)
stfd f16, 128(r3)
stfd f17, 136(r3)
stfd f18, 144(r3)
stfd f19, 152(r3)
stfd f20, 160(r3)
stfd f21, 168(r3)
stfd f22, 176(r3)
stfd f23, 184(r3)
stfd f24, 192(r3)
stfd f25, 200(r3)
stfd f26, 208(r3)
stfd f27, 216(r3)
stfd f28, 224(r3)
stfd f29, 232(r3)
stfd f30, 240(r3)
stfd f31, 248(r3)
/* Also save the FPSCR. */
mffs f31
stfs f31, 256(r3)
#else
/* Buffer address is in r3. Save each flop register into an offset from
this buffer address. */
stfs f0, 0(r3)
stfs f1, 4(r3)
stfs f2, 8(r3)
stfs f3, 12(r3)
stfs f4, 16(r3)
stfs f5, 20(r3)
stfs f6, 24(r3)
stfs f7, 28(r3)
stfs f8, 32(r3)
stfs f9, 36(r3)
stfs f10, 40(r3)
stfs f11, 44(r3)
stfs f12, 48(r3)
stfs f13, 52(r3)
stfs f14, 56(r3)
stfs f15, 60(r3)
stfs f16, 64(r3)
stfs f17, 68(r3)
stfs f18, 72(r3)
stfs f19, 76(r3)
stfs f20, 80(r3)
stfs f21, 84(r3)
stfs f22, 88(r3)
stfs f23, 92(r3)
stfs f24, 96(r3)
stfs f25, 100(r3)
stfs f26, 104(r3)
stfs f27, 108(r3)
stfs f28, 112(r3)
stfs f29, 116(r3)
stfs f30, 120(r3)
stfs f31, 124(r3)
/* Also save the FPSCR. */
mffs f31
stfs f31, 128(r3)
#endif
blr
#endif /* configUSE_FPU. */
#if configUSE_FPU == 1
vPortRestoreFPURegisters:
/* Enable APU and mark FPU as present. */
mfmsr r0
xor r30, r30, r30
oris r30, r30, 512
ori r30, r30, 8192
or r0, r0, r30
mtmsr r0
#ifdef USE_DP_FPU
/* Buffer address is in r3. Restore each flop register from an offset
into this buffer.
First the FPSCR. */
lfs f31, 256(r3)
mtfsf f31, 7
lfd f0, 0(r3)
lfd f1, 8(r3)
lfd f2, 16(r3)
lfd f3, 24(r3)
lfd f4, 32(r3)
lfd f5, 40(r3)
lfd f6, 48(r3)
lfd f7, 56(r3)
lfd f8, 64(r3)
lfd f9, 72(r3)
lfd f10, 80(r3)
lfd f11, 88(r3)
lfd f12, 96(r3)
lfd f13, 104(r3)
lfd f14, 112(r3)
lfd f15, 120(r3)
lfd f16, 128(r3)
lfd f17, 136(r3)
lfd f18, 144(r3)
lfd f19, 152(r3)
lfd f20, 160(r3)
lfd f21, 168(r3)
lfd f22, 176(r3)
lfd f23, 184(r3)
lfd f24, 192(r3)
lfd f25, 200(r3)
lfd f26, 208(r3)
lfd f27, 216(r3)
lfd f28, 224(r3)
lfd f29, 232(r3)
lfd f30, 240(r3)
lfd f31, 248(r3)
#else
/* Buffer address is in r3. Restore each flop register from an offset
into this buffer.
First the FPSCR. */
lfs f31, 128(r3)
mtfsf f31, 7
lfs f0, 0(r3)
lfs f1, 4(r3)
lfs f2, 8(r3)
lfs f3, 12(r3)
lfs f4, 16(r3)
lfs f5, 20(r3)
lfs f6, 24(r3)
lfs f7, 28(r3)
lfs f8, 32(r3)
lfs f9, 36(r3)
lfs f10, 40(r3)
lfs f11, 44(r3)
lfs f12, 48(r3)
lfs f13, 52(r3)
lfs f14, 56(r3)
lfs f15, 60(r3)
lfs f16, 64(r3)
lfs f17, 68(r3)
lfs f18, 72(r3)
lfs f19, 76(r3)
lfs f20, 80(r3)
lfs f21, 84(r3)
lfs f22, 88(r3)
lfs f23, 92(r3)
lfs f24, 96(r3)
lfs f25, 100(r3)
lfs f26, 104(r3)
lfs f27, 108(r3)
lfs f28, 112(r3)
lfs f29, 116(r3)
lfs f30, 120(r3)
lfs f31, 124(r3)
#endif
blr
#endif /* configUSE_FPU. */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 10,023 | portable/GCC/ARM_CA9/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.eabi_attribute Tag_ABI_align_preserved, 1
.text
.arm
.set SYS_MODE, 0x1f
.set SVC_MODE, 0x13
.set IRQ_MODE, 0x12
/* Hardware registers. */
.extern ulICCIAR
.extern ulICCEOIR
.extern ulICCPMR
/* Variables and functions. */
.extern ulMaxAPIPriorityMask
.extern _freertos_vector_table
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ulPortInterruptNesting
.extern ulPortTaskHasFPUContext
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Save the LR and SPSR onto the system mode stack before switching to
system mode to save the remaining system mode registers. */
SRSDB sp!, #SYS_MODE
CPS #SYS_MODE
PUSH {R0-R12, R14}
/* Push the critical nesting count. */
LDR R2, ulCriticalNestingConst
LDR R1, [R2]
PUSH {R1}
/* Does the task have a floating point context that needs saving? If
ulPortTaskHasFPUContext is 0 then no. */
LDR R2, ulPortTaskHasFPUContextConst
LDR R3, [R2]
CMP R3, #0
/* Save the floating point context, if any. */
FMRXNE R1, FPSCR
PUSHNE {R1}
VPUSHNE {D0-D15}
VPUSHNE {D16-D31}
/* Save ulPortTaskHasFPUContext itself. */
PUSH {R3}
/* Save the stack pointer in the TCB. */
LDR R0, pxCurrentTCBConst
LDR R1, [R0]
STR SP, [R1]
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Set the SP to point to the stack of the task being restored. */
LDR R0, pxCurrentTCBConst
LDR R1, [R0]
LDR SP, [R1]
/* Is there a floating point context to restore? If the restored
ulPortTaskHasFPUContext is zero then no. */
LDR R0, ulPortTaskHasFPUContextConst
POP {R1}
STR R1, [R0]
CMP R1, #0
/* Restore the floating point context, if any. */
VPOPNE {D16-D31}
VPOPNE {D0-D15}
POPNE {R0}
VMSRNE FPSCR, R0
/* Restore the critical section nesting depth. */
LDR R0, ulCriticalNestingConst
POP {R1}
STR R1, [R0]
/* Ensure the priority mask is correct for the critical nesting depth. */
LDR R2, ulICCPMRConst
LDR R2, [R2]
CMP R1, #0
MOVEQ R4, #255
LDRNE R4, ulMaxAPIPriorityMaskConst
LDRNE R4, [R4]
STR R4, [R2]
/* Restore all system mode registers other than the SP (which is already
being used). */
POP {R0-R12, R14}
/* Return to the task code, loading CPSR on the way. */
RFEIA sp!
.endm
/******************************************************************************
* SVC handler is used to start the scheduler.
*****************************************************************************/
.align 4
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
/* Ensure bit 2 of the stack pointer is clear. */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
LDR R0, vTaskSwitchContextConst
BLX R0
portRESTORE_CONTEXT
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
/* Switch to system mode. */
CPS #SYS_MODE
portRESTORE_CONTEXT
.align 4
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Return to the interrupted instruction. */
SUB lr, lr, #4
/* Push the return address and SPSR. */
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
/* Change to supervisor mode to allow reentry. */
CPS #SVC_MODE
/* Push used registers. */
PUSH {r0-r4, r12}
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
for future use. r1 holds the original ulPortInterruptNesting value for
future use. */
LDR r3, ulPortInterruptNestingConst
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
/* Read value from the interrupt acknowledge register, which is stored in r0
for future parameter and interrupt clearing use. */
LDR r2, ulICCIARConst
LDR r2, [r2]
LDR r0, [r2]
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. _RB_ Does this ever actually need to be done provided the start
of the stack is 8-byte aligned? */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
/* Call the interrupt handler. r4 pushed to maintain alignment. */
PUSH {r0-r4, lr}
LDR r1, vApplicationIRQHandlerConst
BLX r1
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
DSB
ISB
/* Write the value read from ICCIAR to ICCEOIR. */
LDR r4, ulICCEOIRConst
LDR r4, [r4]
STR r0, [r4]
/* Restore the old nesting count. */
STR r1, [r3]
/* A context switch is never performed if the nesting count is not 0. */
CMP r1, #0
BNE exit_without_switch
/* Did the interrupt request a context switch? r1 holds the address of
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
use. */
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch:
/* No context switch. Restore used registers, LR_irq and SPSR before
returning. */
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
/* Restore used registers, LR-irq and SPSR before saving the context
to the task stack. */
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
/* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
LDR R0, vTaskSwitchContextConst
BLX R0
/* Restore the context of, and branch to, the task selected to execute
next. */
portRESTORE_CONTEXT
/******************************************************************************
* If the application provides an implementation of vApplicationIRQHandler(),
* then it will get called directly without saving the FPU registers on
* interrupt entry, and this weak implementation of
* vApplicationIRQHandler() will not get called.
*
* If the application provides its own implementation of
* vApplicationFPUSafeIRQHandler() then this implementation of
* vApplicationIRQHandler() will be called, save the FPU registers, and then
* call vApplicationFPUSafeIRQHandler().
*
* Therefore, if the application writer wants FPU registers to be saved on
* interrupt entry their IRQ handler must be called
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
* FPU registers to be saved on interrupt entry their IRQ handler must be
* called vApplicationIRQHandler().
*****************************************************************************/
.align 4
.weak vApplicationIRQHandler
.type vApplicationIRQHandler, %function
vApplicationIRQHandler:
PUSH {LR}
FMRX R1, FPSCR
VPUSH {D0-D15}
VPUSH {D16-D31}
PUSH {R1}
LDR r1, vApplicationFPUSafeIRQHandlerConst
BLX r1
POP {R0}
VPOP {D16-D31}
VPOP {D0-D15}
VMSR FPSCR, R0
POP {PC}
ulICCIARConst: .word ulICCIAR
ulICCEOIRConst: .word ulICCEOIR
ulICCPMRConst: .word ulICCPMR
pxCurrentTCBConst: .word pxCurrentTCB
ulCriticalNestingConst: .word ulCriticalNesting
ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
vTaskSwitchContextConst: .word vTaskSwitchContext
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
ulPortInterruptNestingConst: .word ulPortInterruptNesting
vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 7,653 | portable/GCC/ARM_CRx_No_GIC/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.text
.arm
.set SYS_MODE, 0x1f
.set SVC_MODE, 0x13
.set IRQ_MODE, 0x12
/* Variables and functions. */
.extern ulMaxAPIPriorityMask
.extern _freertos_vector_table
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ulPortInterruptNesting
.extern ulPortTaskHasFPUContext
.extern ulICCEOIR
.extern ulPortYieldRequired
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SVC_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Save the LR and SPSR onto the system mode stack before switching to
system mode to save the remaining system mode registers. */
SRSDB sp!, #SYS_MODE
CPS #SYS_MODE
PUSH {R0-R12, R14}
/* Push the critical nesting count. */
LDR R2, ulCriticalNestingConst
LDR R1, [R2]
PUSH {R1}
/* Does the task have a floating point context that needs saving? If
ulPortTaskHasFPUContext is 0 then no. */
LDR R2, ulPortTaskHasFPUContextConst
LDR R3, [R2]
CMP R3, #0
/* Save the floating point context, if any. */
FMRXNE R1, FPSCR
VPUSHNE {D0-D15}
#if configFPU_D32 == 1
VPUSHNE {D16-D31}
#endif /* configFPU_D32 */
PUSHNE {R1}
/* Save ulPortTaskHasFPUContext itself. */
PUSH {R3}
/* Save the stack pointer in the TCB. */
LDR R0, pxCurrentTCBConst
LDR R1, [R0]
STR SP, [R1]
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Set the SP to point to the stack of the task being restored. */
LDR R0, pxCurrentTCBConst
LDR R1, [R0]
LDR SP, [R1]
/* Is there a floating point context to restore? If the restored
ulPortTaskHasFPUContext is zero then no. */
LDR R0, ulPortTaskHasFPUContextConst
POP {R1}
STR R1, [R0]
CMP R1, #0
/* Restore the floating point context, if any. */
POPNE {R0}
#if configFPU_D32 == 1
VPOPNE {D16-D31}
#endif /* configFPU_D32 */
VPOPNE {D0-D15}
VMSRNE FPSCR, R0
/* Restore the critical section nesting depth. */
LDR R0, ulCriticalNestingConst
POP {R1}
STR R1, [R0]
/* Restore all system mode registers other than the SP (which is already
being used). */
POP {R0-R12, R14}
/* Return to the task code, loading CPSR on the way. */
RFEIA sp!
.endm
/******************************************************************************
* SVC handler is used to yield.
*****************************************************************************/
.align 4
.type FreeRTOS_SVC_Handler, %function
FreeRTOS_SVC_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
LDR R0, vTaskSwitchContextConst
BLX R0
portRESTORE_CONTEXT
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.align 4
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
/* Switch to system mode. */
CPS #SYS_MODE
portRESTORE_CONTEXT
.align 4
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Return to the interrupted instruction. */
SUB lr, lr, #4
/* Push the return address and SPSR. */
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
/* Change to supervisor mode to allow reentry. */
CPS #0x13
/* Push used registers. */
PUSH {r0-r3, r12}
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
for future use. r1 holds the original ulPortInterruptNesting value for
future use. */
LDR r3, ulPortInterruptNestingConst
LDR r1, [r3]
ADD r0, r1, #1
STR r0, [r3]
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. */
MOV r0, sp
AND r2, r0, #4
SUB sp, sp, r2
/* Call the interrupt handler. */
PUSH {r0-r3, lr}
LDR r1, vApplicationIRQHandlerConst
BLX r1
POP {r0-r3, lr}
ADD sp, sp, r2
CPSID i
DSB
ISB
/* Write to the EOI register. */
LDR r0, ulICCEOIRConst
LDR r2, [r0]
STR r0, [r2]
/* Restore the old nesting count. */
STR r1, [r3]
/* A context switch is never performed if the nesting count is not 0. */
CMP r1, #0
BNE exit_without_switch
/* Did the interrupt request a context switch? r1 holds the address of
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
use. */
LDR r1, ulPortYieldRequiredConst
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch:
/* No context switch. Restore used registers, LR_irq and SPSR before
returning. */
POP {r0-r3, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
/* Restore used registers, LR-irq and SPSR before saving the context
to the task stack. */
POP {r0-r3, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
/* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
LDR R0, vTaskSwitchContextConst
BLX R0
/* Restore the context of, and branch to, the task selected to execute
next. */
portRESTORE_CONTEXT
ulICCEOIRConst: .word ulICCEOIR
pxCurrentTCBConst: .word pxCurrentTCB
ulCriticalNestingConst: .word ulCriticalNesting
ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
vTaskSwitchContextConst: .word vTaskSwitchContext
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
ulPortInterruptNestingConst: .word ulPortInterruptNesting
ulPortYieldRequiredConst: .word ulPortYieldRequired
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 7,827 | portable/GCC/IA32_flat/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.file "portASM.S"
#include "FreeRTOSConfig.h"
#include "ISR_Support.h"
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vPortCentralInterruptHandler
.extern xTaskIncrementTick
.extern vPortAPICErrorHandler
.extern pucPortTaskFPUContextBuffer
.extern ulPortYieldPending
.global vPortStartFirstTask
.global vPortCentralInterruptWrapper
.global vPortAPICErrorHandlerWrapper
.global vPortTimerHandler
.global vPortYieldCall
.global vPortAPICSpuriousHandler
.text
/*-----------------------------------------------------------*/
.align 4
.func vPortYieldCall
vPortYieldCall:
/* Save general purpose registers. */
pusha
.if configSUPPORT_FPU == 1
/* If the task has a buffer allocated to save the FPU context then save
the FPU context now. */
movl pucPortTaskFPUContextBuffer, %eax
test %eax, %eax
je 1f
fnsave ( %eax )
fwait
1:
/* Save the address of the FPU context, if any. */
push pucPortTaskFPUContextBuffer
.endif /* configSUPPORT_FPU */
/* Find the TCB. */
movl pxCurrentTCB, %eax
/* Stack location is first item in the TCB. */
movl %esp, (%eax)
call vTaskSwitchContext
/* Find the location of pxCurrentTCB again - a callee saved register could
be used in place of eax to prevent this second load, but that then relies
on the compiler and other asm code. */
movl pxCurrentTCB, %eax
movl (%eax), %esp
.if configSUPPORT_FPU == 1
/* Restore address of task's FPU context buffer. */
pop pucPortTaskFPUContextBuffer
/* If the task has a buffer allocated in which its FPU context is saved,
then restore it now. */
movl pucPortTaskFPUContextBuffer, %eax
test %eax, %eax
je 1f
frstor ( %eax )
1:
.endif
popa
iret
.endfunc
/*-----------------------------------------------------------*/
.align 4
.func vPortStartFirstTask
vPortStartFirstTask:
/* Find the TCB. */
movl pxCurrentTCB, %eax
/* Stack location is first item in the TCB. */
movl (%eax), %esp
/* Restore FPU context flag. */
.if configSUPPORT_FPU == 1
pop pucPortTaskFPUContextBuffer
.endif /* configSUPPORT_FPU */
/* Restore general purpose registers. */
popa
iret
.endfunc
/*-----------------------------------------------------------*/
.align 4
.func vPortAPICErrorHandlerWrapper
vPortAPICErrorHandlerWrapper:
pusha
call vPortAPICErrorHandler
popa
/* EOI. */
movl $0x00, (0xFEE000B0)
iret
.endfunc
/*-----------------------------------------------------------*/
.align 4
.func vPortTimerHandler
vPortTimerHandler:
/* Save general purpose registers. */
pusha
/* Interrupts are not nested, so save the rest of the task context. */
.if configSUPPORT_FPU == 1
/* If the task has a buffer allocated to save the FPU context then save the
FPU context now. */
movl pucPortTaskFPUContextBuffer, %eax
test %eax, %eax
je 1f
fnsave ( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
fwait
1:
/* Save the address of the FPU context, if any. */
push pucPortTaskFPUContextBuffer
.endif /* configSUPPORT_FPU */
/* Find the TCB. */
movl pxCurrentTCB, %eax
/* Stack location is first item in the TCB. */
movl %esp, (%eax)
/* Switch stacks. */
movl ulTopOfSystemStack, %esp
movl %esp, %ebp
/* Increment nesting count. */
add $1, ulInterruptNesting
call xTaskIncrementTick
sti
/* Is a switch to another task required? */
test %eax, %eax
je _skip_context_switch
cli
call vTaskSwitchContext
_skip_context_switch:
cli
/* Decrement the variable used to determine if a switch to a system
stack is necessary. */
sub $1, ulInterruptNesting
/* Stack location is first item in the TCB. */
movl pxCurrentTCB, %eax
movl (%eax), %esp
.if configSUPPORT_FPU == 1
/* Restore address of task's FPU context buffer. */
pop pucPortTaskFPUContextBuffer
/* If the task has a buffer allocated in which its FPU context is saved,
then restore it now. */
movl pucPortTaskFPUContextBuffer, %eax
test %eax, %eax
je 1f
frstor ( %eax )
1:
.endif
popa
/* EOI. */
movl $0x00, (0xFEE000B0)
iret
.endfunc
/*-----------------------------------------------------------*/
.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1
.align 4
.func vPortCentralInterruptWrapper
vPortCentralInterruptWrapper:
portFREERTOS_INTERRUPT_ENTRY
movl $0xFEE00170, %eax /* Highest In Service Register (ISR) long word. */
movl $8, %ecx /* Loop counter. */
next_isr_long_word:
test %ecx, %ecx /* Loop counter reached 0? */
je wrapper_epilogue /* Looked at all ISR registers without finding a bit set. */
sub $1, %ecx /* Sub 1 from loop counter. */
movl (%eax), %ebx /* Load next ISR long word. */
sub $0x10, %eax /* Point to next ISR long word in case no bits are set in the current long word. */
test %ebx, %ebx /* Are there any bits set? */
je next_isr_long_word /* Look at next ISR long word if no bits were set. */
sti
bsr %ebx, %ebx /* A bit was set, which one? */
movl $32, %eax /* Destination operand for following multiplication. */
mul %ecx /* Calculate base vector for current register, 32 vectors per register. */
add %ebx, %eax /* Add bit offset into register to get final vector number. */
push %eax /* Vector number is function parameter. */
call vPortCentralInterruptHandler
pop %eax /* Remove parameter. */
wrapper_epilogue:
portFREERTOS_INTERRUPT_EXIT
.endfunc
.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
/*-----------------------------------------------------------*/
.align 4
.func vPortAPISpuriousHandler
vPortAPICSpuriousHandler:
iret
.endfunc
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 12,791 | portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.text
/* Variables and functions. */
.extern ullMaxAPIPriorityMask
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ullPortInterruptNesting
.extern ullPortTaskHasFPUContext
.extern ullCriticalNesting
.extern ullPortYieldRequired
.extern _freertos_vector_table
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Save the entire context. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X20, X21, [SP, #-0x10]!
STP X22, X23, [SP, #-0x10]!
STP X24, X25, [SP, #-0x10]!
STP X26, X27, [SP, #-0x10]!
STP X28, X29, [SP, #-0x10]!
STP X30, XZR, [SP, #-0x10]!
/* Save the SPSR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
/* Save the ELR. */
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Save the critical section nesting depth. */
LDR X0, ullCriticalNestingConst
LDR X3, [X0]
/* Save the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
LDR X2, [X0]
/* Save the FPU context, if any (32 128-bit registers). */
CMP X2, #0
B.EQ 1f
STP Q0, Q1, [SP,#-0x20]!
STP Q2, Q3, [SP,#-0x20]!
STP Q4, Q5, [SP,#-0x20]!
STP Q6, Q7, [SP,#-0x20]!
STP Q8, Q9, [SP,#-0x20]!
STP Q10, Q11, [SP,#-0x20]!
STP Q12, Q13, [SP,#-0x20]!
STP Q14, Q15, [SP,#-0x20]!
STP Q16, Q17, [SP,#-0x20]!
STP Q18, Q19, [SP,#-0x20]!
STP Q20, Q21, [SP,#-0x20]!
STP Q22, Q23, [SP,#-0x20]!
STP Q24, Q25, [SP,#-0x20]!
STP Q26, Q27, [SP,#-0x20]!
STP Q28, Q29, [SP,#-0x20]!
STP Q30, Q31, [SP,#-0x20]!
1:
/* Store the critical nesting count and FPU context indicator. */
STP X2, X3, [SP, #-0x10]!
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
MOV X0, SP /* Move SP into X0 for saving. */
STR X0, [X1]
/* Switch to use the ELx stack pointer. */
MSR SPSEL, #1
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Set the SP to point to the stack of the task being restored. */
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
LDR X0, [X1]
MOV SP, X0
LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
/* Set the PMR register to be correct for the current critical nesting
depth. */
LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
MOV X1, #255 /* X1 holds the unmask value. */
CMP X3, #0
B.EQ 1f
LDR X6, ullMaxAPIPriorityMaskConst
LDR X1, [X6] /* X1 holds the mask value. */
1:
MSR s3_0_c4_c6_0, X1 /* Write the mask value to ICCPMR. s3_0_c4_c6_0 is ICC_PMR_EL1. */
DSB SY /* _RB_Barriers probably not required here. */
ISB SY
STR X3, [X0] /* Restore the task's critical nesting count. */
/* Restore the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
STR X2, [X0]
/* Restore the FPU context, if any. */
CMP X2, #0
B.EQ 1f
LDP Q30, Q31, [SP], #0x20
LDP Q28, Q29, [SP], #0x20
LDP Q26, Q27, [SP], #0x20
LDP Q24, Q25, [SP], #0x20
LDP Q22, Q23, [SP], #0x20
LDP Q20, Q21, [SP], #0x20
LDP Q18, Q19, [SP], #0x20
LDP Q16, Q17, [SP], #0x20
LDP Q14, Q15, [SP], #0x20
LDP Q12, Q13, [SP], #0x20
LDP Q10, Q11, [SP], #0x20
LDP Q8, Q9, [SP], #0x20
LDP Q6, Q7, [SP], #0x20
LDP Q4, Q5, [SP], #0x20
LDP Q2, Q3, [SP], #0x20
LDP Q0, Q1, [SP], #0x20
1:
LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
/* Restore the SPSR. */
MSR SPSR_EL1, X3
/* Restore the ELR. */
MSR ELR_EL1, X2
#else
/* Restore the SPSR. */
MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
/* Restore the ELR. */
MSR ELR_EL3, X2
#endif
LDP X30, XZR, [SP], #0x10
LDP X28, X29, [SP], #0x10
LDP X26, X27, [SP], #0x10
LDP X24, X25, [SP], #0x10
LDP X22, X23, [SP], #0x10
LDP X20, X21, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
MSR SPSEL, #1
ERET
.endm
/******************************************************************************
* FreeRTOS_SWI_Handler handler is used to perform a context switch.
*****************************************************************************/
.align 8
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
#if defined( GUEST )
MRS X0, ESR_EL1
#else
MRS X0, ESR_EL3
#endif
LSR X1, X0, #26
#if defined( GUEST )
CMP X1, #0x15 /* 0x15 = SVC instruction. */
#else
CMP X1, #0x17 /* 0x17 = SMC instruction. */
#endif
B.NE FreeRTOS_Abort
BL vTaskSwitchContext
portRESTORE_CONTEXT
FreeRTOS_Abort:
/* Full ESR is in X0, exception class code is in X1. */
B .
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.align 8
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
.set freertos_vector_base, _freertos_vector_table
/* Install the FreeRTOS interrupt handlers. */
LDR X1, =freertos_vector_base
#if defined( GUEST )
MSR VBAR_EL1, X1
#else
MSR VBAR_EL3, X1
#endif
DSB SY
ISB SY
/* Start the first task. */
portRESTORE_CONTEXT
/******************************************************************************
* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
* This handler is supposed to be used only for IRQs and never for FIQs. Per ARM
* GIC documentation [1], Group 0 interrupts are always signaled as FIQs. Since
* this handler is only for IRQs, We can safely assume Group 1 while accessing
* Interrupt Acknowledge and End Of Interrupt registers and therefore, use
* ICC_IAR1_EL1 and ICC_EOIR1_EL1.
*
* [1] https://developer.arm.com/documentation/198123/0300/Arm-CoreLink-GIC-fundamentals
*****************************************************************************/
.align 8
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Save volatile registers. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X29, X30, [SP, #-0x10]!
/* Save the SPSR and ELR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Increment the interrupt nesting counter. */
LDR X5, ullPortInterruptNestingConst
LDR X1, [X5] /* Old nesting count in X1. */
ADD X6, X1, #1
STR X6, [X5] /* Address of nesting count variable in X5. */
/* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]!
/* Read interrupt ID from the interrupt acknowledge register and store it
in X0 for future parameter and interrupt clearing use. */
MRS X0, S3_0_C12_C12_0 /* S3_0_C12_C12_0 is ICC_IAR1_EL1. */
/* Maintain the interrupt ID value across the function call. */
STP X0, X1, [SP, #-0x10]!
/* Call the C handler. */
BL vApplicationIRQHandler
/* Disable interrupts. */
MSR DAIFSET, #2
DSB SY
ISB SY
/* Restore the interrupt ID value. */
LDP X0, X1, [SP], #0x10
/* End IRQ processing by writing interrupt ID value to the EOI register. */
MSR S3_0_C12_C12_1, X0 /* S3_0_C12_C12_1 is ICC_EOIR1_EL1. */
/* Restore the critical nesting count. */
LDP X1, X5, [SP], #0x10
STR X1, [X5]
/* Has interrupt nesting unwound? */
CMP X1, #0
B.NE Exit_IRQ_No_Context_Switch
/* Is a context switch required? */
LDR X0, ullPortYieldRequiredConst
LDR X1, [X0]
CMP X1, #0
B.EQ Exit_IRQ_No_Context_Switch
/* Reset ullPortYieldRequired to 0. */
MOV X2, #0
STR X2, [X0]
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
BL vTaskSwitchContext
portRESTORE_CONTEXT
Exit_IRQ_No_Context_Switch:
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
ERET
.align 8
pxCurrentTCBConst: .dword pxCurrentTCB
ullCriticalNestingConst: .dword ullCriticalNesting
ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
ullPortInterruptNestingConst: .dword ullPortInterruptNesting
ullPortYieldRequiredConst: .dword ullPortYieldRequired
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 10,740 | portable/GCC/AVR32_UC3/exception.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT AND BSD-3-Clause
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Exception and interrupt vectors.
*
* This file maps all events supported by an AVR32UC.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32UC devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation (Now Microchip):
* https://www.microchip.com \n
* Support and FAQ: https://www.microchip.com/support/
*
******************************************************************************/
/*
* Copyright (c) 2007, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <avr32/io.h>
#include "intc.h"
//! @{
//! \verbatim
.section .exception, "ax", @progbits
// Start of Exception Vector Table.
// EVBA must be aligned with a power of two strictly greater than the EVBA-
// relative offset of the last vector.
.balign 0x200
// Export symbol.
.global _evba
.type _evba, @function
_evba:
.org 0x000
// Unrecoverable Exception.
_handle_Unrecoverable_Exception:
rjmp $
.org 0x004
// TLB Multiple Hit: UNUSED IN AVR32UC.
_handle_TLB_Multiple_Hit:
rjmp $
.org 0x008
// Bus Error Data Fetch.
_handle_Bus_Error_Data_Fetch:
rjmp $
.org 0x00C
// Bus Error Instruction Fetch.
_handle_Bus_Error_Instruction_Fetch:
rjmp $
.org 0x010
// NMI.
_handle_NMI:
rjmp $
.org 0x014
// Instruction Address.
_handle_Instruction_Address:
rjmp $
.org 0x018
// ITLB Protection.
_handle_ITLB_Protection:
rjmp $
.org 0x01C
// Breakpoint.
_handle_Breakpoint:
rjmp $
.org 0x020
// Illegal Opcode.
_handle_Illegal_Opcode:
rjmp $
.org 0x024
// Unimplemented Instruction.
_handle_Unimplemented_Instruction:
rjmp $
.org 0x028
// Privilege Violation.
_handle_Privilege_Violation:
rjmp $
.org 0x02C
// Floating-Point: UNUSED IN AVR32UC.
_handle_Floating_Point:
rjmp $
.org 0x030
// Coprocessor Absent: UNUSED IN AVR32UC.
_handle_Coprocessor_Absent:
rjmp $
.org 0x034
// Data Address (Read).
_handle_Data_Address_Read:
rjmp $
.org 0x038
// Data Address (Write).
_handle_Data_Address_Write:
rjmp $
.org 0x03C
// DTLB Protection (Read).
_handle_DTLB_Protection_Read:
rjmp $
.org 0x040
// DTLB Protection (Write).
_handle_DTLB_Protection_Write:
rjmp $
.org 0x044
// DTLB Modified: UNUSED IN AVR32UC.
_handle_DTLB_Modified:
rjmp $
.org 0x050
// ITLB Miss: UNUSED IN AVR32UC.
_handle_ITLB_Miss:
rjmp $
.org 0x060
// DTLB Miss (Read): UNUSED IN AVR32UC.
_handle_DTLB_Miss_Read:
rjmp $
.org 0x070
// DTLB Miss (Write): UNUSED IN AVR32UC.
_handle_DTLB_Miss_Write:
rjmp $
.org 0x100
// Supervisor Call.
_handle_Supervisor_Call:
lda.w pc, SCALLYield
// Interrupt support.
// The interrupt controller must provide the offset address relative to EVBA.
// Important note:
// All interrupts call a C function named _get_interrupt_handler.
// This function will read group and interrupt line number to then return in
// R12 a pointer to a user-provided interrupt handler.
.balign 4
_int0:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int0_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int0_normal:
#endif
mov r12, 0 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int1:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int1_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int1_normal:
#endif
mov r12, 1 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int2:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int2_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int2_normal:
#endif
mov r12, 2 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
_int3:
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry.
#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
mfsr r12, AVR32_SR
bfextu r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
cp.w r12, 0b110
brlo _int3_normal
lddsp r12, sp[0 * 4]
stdsp sp[6 * 4], r12
lddsp r12, sp[1 * 4]
stdsp sp[7 * 4], r12
lddsp r12, sp[3 * 4]
sub sp, -6 * 4
rete
_int3_normal:
#endif
mov r12, 3 // Pass the int_lev parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
// Constant data area.
.balign 4
// Values to store in the interrupt priority registers for the various interrupt priority levels.
// The interrupt priority registers contain the interrupt priority level and
// the EVBA-relative interrupt vector offset.
.global ipr_val
.type ipr_val, @object
ipr_val:
.word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
(INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
(INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
(INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
//! \endverbatim
//! @}
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,448 | portable/GCC/ColdFire_V2/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
* supplied source files.
*/
.global ulPortSetIPL
.global mcf5xxx_wr_cacr
.global __cs3_isr_interrupt_80
.global vPortStartFirstTask
.text
.macro portSAVE_CONTEXT
lea.l (-60, %sp), %sp
movem.l %d0-%fp, (%sp)
move.l pxCurrentTCB, %a0
move.l %sp, (%a0)
.endm
.macro portRESTORE_CONTEXT
move.l pxCurrentTCB, %a0
move.l (%a0), %sp
movem.l (%sp), %d0-%fp
lea.l %sp@(60), %sp
rte
.endm
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
ulPortSetIPL:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
mcf5xxx_wr_cacr:
move.l 4(sp),d0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
/********************************************************************/
/* Yield interrupt. */
__cs3_isr_interrupt_80:
portSAVE_CONTEXT
jsr vPortYieldHandler
portRESTORE_CONTEXT
/********************************************************************/
vPortStartFirstTask:
portRESTORE_CONTEXT
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 9,968 | portable/GCC/ARM_CR5/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.text
.arm
.set SYS_MODE, 0x1f
.set SVC_MODE, 0x13
.set IRQ_MODE, 0x12
/* Hardware registers. */
.extern ulICCIAR
.extern ulICCEOIR
.extern ulICCPMR
/* Variables and functions. */
.extern ulMaxAPIPriorityMask
.extern _freertos_vector_table
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ulPortInterruptNesting
#if defined( __ARM_FP )
.extern ulPortTaskHasFPUContext
#endif /* __ARM_FP */
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Save the LR and SPSR onto the system mode stack before switching to
system mode to save the remaining system mode registers. */
SRSDB sp!, #SYS_MODE
CPS #SYS_MODE
PUSH {R0-R12, R14}
/* Push the critical nesting count. */
LDR R2, ulCriticalNestingConst
LDR R1, [R2]
PUSH {R1}
#if defined( __ARM_FP )
/* Does the task have a floating point context that needs saving? If
ulPortTaskHasFPUContext is 0 then no. */
LDR R2, ulPortTaskHasFPUContextConst
LDR R3, [R2]
CMP R3, #0
/* Save the floating point context, if any. */
FMRXNE R1, FPSCR
VPUSHNE {D0-D15}
PUSHNE {R1}
/* Save ulPortTaskHasFPUContext itself. */
PUSH {R3}
#endif /* __ARM_FP */
/* Save the stack pointer in the TCB. */
LDR R0, pxCurrentTCBConst
LDR R1, [R0]
STR SP, [R1]
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Set the SP to point to the stack of the task being restored. */
LDR R0, pxCurrentTCBConst
LDR R1, [R0]
LDR SP, [R1]
#if defined( __ARM_FP )
/*
* Is there a floating point context to restore? If the restored
* ulPortTaskHasFPUContext is zero then no.
*/
LDR R0, ulPortTaskHasFPUContextConst
POP {R1}
STR R1, [R0]
CMP R1, #0
/* Restore the floating point context, if any. */
POPNE {R0}
VPOPNE {D0-D15}
VMSRNE FPSCR, R0
#endif /* __ARM_FP */
/* Restore the critical section nesting depth. */
LDR R0, ulCriticalNestingConst
POP {R1}
STR R1, [R0]
/* Ensure the priority mask is correct for the critical nesting depth. */
LDR R2, ulICCPMRConst
LDR R2, [R2]
CMP R1, #0
MOVEQ R4, #255
LDRNE R4, ulMaxAPIPriorityMaskConst
LDRNE R4, [R4]
STR R4, [R2]
/* Restore all system mode registers other than the SP (which is already
being used). */
POP {R0-R12, R14}
/* Return to the task code, loading CPSR on the way. */
RFEIA sp!
.endm
/******************************************************************************
* SVC handler is used to start the scheduler.
*****************************************************************************/
.align 4
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
LDR R0, vTaskSwitchContextConst
BLX R0
portRESTORE_CONTEXT
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
/* Switch to system mode. */
CPS #SYS_MODE
portRESTORE_CONTEXT
.align 4
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Return to the interrupted instruction. */
SUB lr, lr, #4
/* Push the return address and SPSR. */
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
/* Change to supervisor mode to allow reentry. */
CPS #SVC_MODE
/* Push used registers. */
PUSH {r0-r4, r12}
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
for future use. r1 holds the original ulPortInterruptNesting value for
future use. */
LDR r3, ulPortInterruptNestingConst
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
/* Read value from the interrupt acknowledge register, which is stored in r0
for future parameter and interrupt clearing use. */
LDR r2, ulICCIARConst
LDR r2, [r2]
LDR r0, [r2]
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. _RB_ Is this ever needed provided the start of the stack is
alligned on an 8-byte boundary? */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
/* Call the interrupt handler. */
PUSH {r0-r4, lr}
LDR r1, vApplicationIRQHandlerConst
BLX r1
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
DSB
ISB
/* Write the value read from ICCIAR to ICCEOIR. */
LDR r4, ulICCEOIRConst
LDR r4, [r4]
STR r0, [r4]
/* Restore the old nesting count. */
STR r1, [r3]
/* A context switch is never performed if the nesting count is not 0. */
CMP r1, #0
BNE exit_without_switch
/* Did the interrupt request a context switch? r1 holds the address of
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
use. */
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch:
/* No context switch. Restore used registers, LR_irq and SPSR before
returning. */
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
/* Restore used registers, LR-irq and SPSR before saving the context
to the task stack. */
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
/* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
LDR R0, vTaskSwitchContextConst
BLX R0
/* Restore the context of, and branch to, the task selected to execute
next. */
portRESTORE_CONTEXT
/******************************************************************************
* If the application provides an implementation of vApplicationIRQHandler(),
* then it will get called directly without saving the FPU registers on
* interrupt entry, and this weak implementation of
* vApplicationIRQHandler() will not get called.
*
* If the application provides its own implementation of
* vApplicationFPUSafeIRQHandler() then this implementation of
* vApplicationIRQHandler() will be called, save the FPU registers, and then
* call vApplicationFPUSafeIRQHandler().
*
* Therefore, if the application writer wants FPU registers to be saved on
* interrupt entry their IRQ handler must be called
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
* FPU registers to be saved on interrupt entry their IRQ handler must be
* called vApplicationIRQHandler().
*****************************************************************************/
.align 4
.weak vApplicationIRQHandler
.type vApplicationIRQHandler, %function
vApplicationIRQHandler:
PUSH {LR}
#if defined( __ARM_FP )
FMRX R1, FPSCR
VPUSH {D0-D15}
PUSH {R1}
LDR r1, vApplicationFPUSafeIRQHandlerConst
BLX r1
POP {R0}
VPOP {D0-D15}
VMSR FPSCR, R0
#endif /* __ARM_FP */
POP {PC}
ulICCIARConst: .word ulICCIAR
ulICCEOIRConst: .word ulICCEOIR
ulICCPMRConst: .word ulICCPMR
pxCurrentTCBConst: .word pxCurrentTCB
ulCriticalNestingConst: .word ulCriticalNesting
#if defined( __ARM_FP )
ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
#endif /* __ARM_FP */
ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
vTaskSwitchContextConst: .word vTaskSwitchContext
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
ulPortInterruptNestingConst: .word ulPortInterruptNesting
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 18,203 | portable/GCC/ARM_CRx_MPU/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.arm
.syntax unified
.section privileged_functions
#define FREERTOS_ASSEMBLY
#include "portmacro_asm.h"
#include "mpu_syscall_numbers.h"
#undef FREERTOS_ASSEMBLY
/* External FreeRTOS-Kernel variables. */
.extern pxCurrentTCB
.extern uxSystemCallImplementations
.extern ulPortInterruptNesting
.extern ulPortYieldRequired
/* External Llnker script variables. */
.extern __syscalls_flash_start__
.extern __syscalls_flash_end__
/* External FreeRTOS-Kernel functions. */
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
/* ----------------------------------------------------------------------------------- */
/* Save the context of a FreeRTOS Task. */
.macro portSAVE_CONTEXT
DSB
ISB
/* Push R0 and LR to the stack for current mode. */
PUSH { R0, LR }
LDR LR, =pxCurrentTCB /* LR = &( pxCurrentTCB ). */
LDR LR, [LR] /* LR = pxCurrentTCB. */
LDR LR, [LR] /* LR = pxTopOfStack i.e. the address where to store the task context. */
LDR R0, =ulCriticalNesting /* R0 = &( ulCriticalNesting ). */
LDR R0, [R0] /* R0 = ulCriticalNesting. */
STM LR!, { R0 } /* Store ulCriticalNesting. ! increments LR after storing. */
#if ( portENABLE_FPU == 1 )
VMRS R0, FPSCR /* R0 = FPSCR. */
STM LR!, { R0 } /* Store FPSCR. */
VSTM LR!, { D0-D15 } /* Store D0-D15. */
#endif /* ( portENABLE_FPU == 1 ) */
POP { R0 } /* Restore R0 to pre-exception value. */
/* STM (user registers) - In a PL1 mode other than System mode, STM (user
* registers) instruction stores multiple User mode registers to
* consecutive memory locations using an address from a base register. The
* processor reads the base register value normally, using the current mode
* to determine the correct Banked version of the register. This instruction
* cannot writeback to the base register.
*
* The following can be derived from the above description:
* - The macro portSAVE_CONTEXT MUST be called from a PL1 mode other than
* the System mode.
* - Base register LR of the current mode will be used which contains the
* location to store the context.
* - It will store R0-R14 of User mode i.e. pre-exception SP(R13) and LR(R14)
* will be stored. */
STM LR, { R0-R14 }^
ADD LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */
POP { R0 } /* Pre-exception PC is in R0. */
MRS R1, SPSR /* R1 = Pre-exception CPSR. */
STM LR!, { R0-R1 } /* Store pre-exception PC and CPSR. */
.endm
/* ----------------------------------------------------------------------------------- */
/* Restore the context of a FreeRTOS Task. */
.macro portRESTORE_CONTEXT
/* Load the pointer to the current task's Task Control Block (TCB). */
LDR LR, =pxCurrentTCB /* LR = &( pxCurrentTCB ). */
LDR LR, [LR] /* LR = pxCurrentTCB. */
ADD R1, LR, #0x4 /* R1 now points to the xMPUSettings in TCB. */
LDR LR, [LR] /* LR = pxTopOfStack i.e. the address where to restore the task context from. */
/* When creating a loop label in a macro it has to be a numeric label.
* for( R5 = portFIRST_CONFIGURABLE_REGION ; R5 <= portNUM_CONFIGURABLE_REGIONS ; R5++ ) */
MOV R5, #portFIRST_CONFIGURABLE_REGION
123:
LDMIA R1!, { R2-R4 } /* R2 = ulRegionSize, R3 = ulRegionAttribute, R4 = ulRegionBaseAddress. */
MCR p15, #0, R5, c6, c2, #0 /* MPU Region Number Register. */
MCR p15, #0, R4, c6, c1, #0 /* MPU Region Base Address Register. */
MCR p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */
MCR p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */
ADD R5, R5, #1
CMP R5, #portNUM_CONFIGURABLE_REGIONS
BLE 123b
LDR R1, =ulCriticalNesting /* R1 = &( ulCriticalNesting ). */
LDM LR!, { R2 } /* R2 = Stored ulCriticalNesting. */
STR R2, [R1] /* Restore ulCriticalNesting. */
#if ( portENABLE_FPU == 1 )
LDM LR!, { R1 } /* R1 = Stored FPSCR. */
VMSR FPSCR, R1 /* Restore FPSCR. */
VLDM LR!, { D0-D15 } /* Restore D0-D15. */
#endif /* portENABLE_FPU*/
/* LDM (User registers) - In a PL1 mode other than System mode, LDM (User
* registers) loads multiple User mode registers from consecutive memory
* locations using an address from a base register. The registers loaded
* cannot include the PC. The processor reads the base register value
* normally, using the current mode to determine the correct Banked version
* of the register. This instruction cannot writeback to the base register.
*
* The following can be derived from the above description:
* - The macro portRESTORE_CONTEXT MUST be called from a PL1 mode other than
* the System mode.
* - Base register LR of the current mode will be used which contains the
* location to restore the context from.
* - It will restore R0-R14 of User mode i.e. SP(R13) and LR(R14) of User
* mode will be restored.
*/
LDM LR, { R0-R14 }^
ADD LR, LR, #60 /* R0-R14 - Total 155 register, each 4 byte wide. */
RFE LR /* Restore PC and CPSR from the context. */
.endm
/* ----------------------------------------------------------------------------------- */
/*
* void vPortStartFirstTask( void );
*/
.align 4
.global vPortStartFirstTask
.type vPortStartFirstTask, %function
vPortStartFirstTask:
/* This function is called from System Mode to start the FreeRTOS-Kernel.
* As described in the portRESTORE_CONTEXT macro, portRESTORE_CONTEXT cannot
* be called from the System mode. We, therefore, switch to the Supervisor
* mode before calling portRESTORE_CONTEXT. */
CPS #SVC_MODE
portRESTORE_CONTEXT
/* ----------------------------------------------------------------------------------- */
.align 4
.global FreeRTOS_SVC_Handler
.type FreeRTOS_SVC_Handler, %function
FreeRTOS_SVC_Handler:
PUSH { R11-R12 }
/* ------------------------- Caller Flash Location Check ------------------------- */
LDR R11, =__syscalls_flash_start__
LDR R12, =__syscalls_flash_end__
CMP LR, R11 /* If SVC instruction address is less than __syscalls_flash_start__, exit. */
BLT svcHandlerExit
CMP LR, R12 /* If SVC instruction address is greater than __syscalls_flash_end__, exit. */
BGT svcHandlerExit
/* ---------------------------- Get Caller SVC Number ---------------------------- */
MRS R11, SPSR /* LR = CPSR at the time of SVC. */
TST R11, #0x20 /* Check Thumb bit (5) in CPSR. */
LDRHNE R11, [LR, #-0x2] /* If Thumb, load halfword. */
BICNE R11, R11, #0xFF00 /* And extract immidiate field (i.e. SVC number). */
LDREQ R11, [LR, #-0x4] /* If ARM, load word. */
BICEQ R11, R11, #0xFF000000 /* And extract immidiate field (i.e. SVC number). */
/* --------------------------------- SVC Routing --------------------------------- */
/* If SVC Number < #NUM_SYSTEM_CALLS, go to svcSystemCallEnter. */
CMP R11, #NUM_SYSTEM_CALLS
BLT svcSystemCallEnter
/* If SVC Number == #portSVC_SYSTEM_CALL_EXIT, go to svcSystemCallExit. */
CMP R11, #portSVC_SYSTEM_CALL_EXIT
BEQ svcSystemCallExit
/* If SVC Number == #portSVC_YIELD, go to svcPortYield. */
CMP R11, #portSVC_YIELD
BEQ svcPortYield
svcHandlerExit:
POP { R11-R12 }
MOVS PC, LR /* Copies the SPSR into the CPSR, performing the mode swap. */
svcPortYield:
POP { R11-R12 }
portSAVE_CONTEXT
BL vTaskSwitchContext
portRESTORE_CONTEXT
svcSystemCallExit:
LDR R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */
LDR R11, [R11] /* R11 = pxCurrentTCB. */
ADD R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */
/* Restore the user mode SP and LR. */
LDM R11, { R13-R14 }^
AND R12, R12, #0x0 /* R12 = 0. */
STR R12, [R11] /* xSystemCallStackInfo.pulTaskStackPointer = NULL. */
STR R12, [R11, #0x4] /* xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry = NULL. */
LDMDB R11, { R12 } /* R12 = ulTaskFlags. */
TST R12, #portTASK_IS_PRIVILEGED_FLAG
/* If the task is privileged, we can exit now. */
BNE svcHandlerExit
/* Otherwise, we need to switch back to User mode. */
MRS R12, SPSR
BIC R12, R12, #0x0F
MSR SPSR_cxsf, R12
B svcHandlerExit
svcSystemCallEnter:
LDR R12, =uxSystemCallImplementations /* R12 = uxSystemCallImplementations. */
/* R12 = uxSystemCallImplementations[ R12 + ( R11 << 2 ) ].
* R12 now contains the address of the system call impl function. */
LDR R12, [R12, R11, lsl #2]
/* If R12 == NULL, exit. */
CMP R12, #0x0
BEQ svcHandlerExit
/* It is okay to clobber LR here because we do not need to return to the
* SVC enter location anymore. LR now contains the address of the system
* call impl function. */
MOV LR, R12
LDR R11, =pxCurrentTCB /* R11 = &( pxCurrentTCB ). */
LDR R11, [R11] /* R11 = pxCurrentTCB. */
ADD R11, R11, #portSYSTEM_CALL_INFO_OFFSET /* R11 now points to xSystemCallStackInfo in TCB. */
/* Store User mode SP and LR in xSystemCallStackInfo.pulTaskStackPointer and
* xSystemCallStackInfo.pulLinkRegisterAtSystemCallEntry. */
STM R11, { R13-R14 }^
ADD R11, R11, 0x8
/* Load User mode SP an LR with xSystemCallStackInfo.pulSystemCallStackPointer
* and xSystemCallStackInfo.pulSystemCallExitAddress. */
LDM R11, { R13-R14 }^
/* Change to SYS_MODE for the System Call. */
MRS R12, SPSR
ORR R12, R12, #SYS_MODE
MSR SPSR_cxsf, R12
B svcHandlerExit
/* ----------------------------------------------------------------------------------- */
/*
* void vPortDisableInterrupts( void );
*/
.align 4
.global vPortDisableInterrupts
.type vPortDisableInterrupts, %function
vPortDisableInterrupts:
CPSID I
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vPortEnableInterrupts( void );
*/
.align 4
.global vPortEnableInterrupts
.type vPortEnableInterrupts, %function
vPortEnableInterrupts:
CPSIE I
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vMPUSetRegion( uint32_t ulRegionNumber,
* uint32_t ulBaseAddress,
* uint32_t ulRegionSize,
* uint32_t ulRegionPermissions );
*
* According to the Procedure Call Standard for the ARM Architecture (AAPCS),
* paramters are passed in the following registers:
* R0 = ulRegionNumber.
* R1 = ulBaseAddress.
* R2 = ulRegionSize.
* R3 = ulRegionPermissions.
*/
.align 4
.global vMPUSetRegion
.type vMPUSetRegion, %function
vMPUSetRegion:
AND R0, R0, #0x0F /* R0 = R0 & 0x0F. Max possible region number is 15. */
MCR p15, #0, R0, c6, c2, #0 /* MPU Region Number Register. */
MCR p15, #0, R1, c6, c1, #0 /* MPU Region Base Address Register. */
MCR p15, #0, R3, c6, c1, #4 /* MPU Region Access Control Register. */
MCR p15, #0, R2, c6, c1, #2 /* MPU Region Size and Enable Register. */
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vMPUEnable( void );
*/
.align 4
.global vMPUEnable
.type vMPUEnable, %function
vMPUEnable:
PUSH { R0 }
MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
ORR R0, R0, #0x1 /* R0 = R0 | 0x1. Set the M bit in SCTLR. */
DSB
MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
ISB
POP { R0 }
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vMPUDisable( void );
*/
.align 4
.global vMPUDisable
.type vMPUDisable, %function
vMPUDisable:
PUSH { R0 }
MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
BIC R0, R0, #1 /* R0 = R0 & ~0x1. Clear the M bit in SCTLR. */
/* Wait for all pending data accesses to complete. */
DSB
MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
/* Flush the pipeline and prefetch buffer(s) in the processor to ensure that
* all following instructions are fetched from cache or memory. */
ISB
POP { R0 }
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vMPUEnableBackgroundRegion( void );
*/
.align 4
.global vMPUEnableBackgroundRegion
.type vMPUEnableBackgroundRegion, %function
vMPUEnableBackgroundRegion:
PUSH { R0 }
MRC p15, #0, R0, c1, c0, #0 /* R0 = System Control Register (SCTLR). */
ORR R0, R0, #0x20000 /* R0 = R0 | 0x20000. Set the BR bit in SCTLR. */
MCR p15, #0, R0, c1, c0, #0 /* SCTLR = R0. */
POP { R0 }
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vMPUDisableBackgroundRegion( void );
*/
.align 4
.global vMPUDisableBackgroundRegion
.type vMPUDisableBackgroundRegion, %function
vMPUDisableBackgroundRegion:
PUSH { R0 }
MRC p15, 0, R0, c1, c0, 0 /* R0 = System Control Register (SCTLR). */
BIC R0, R0, #0x20000 /* R0 = R0 & ~0x20000. Clear the BR bit in SCTLR. */
MCR p15, 0, R0, c1, c0, 0 /* SCTLR = R0. */
POP { R0 }
BX LR
/* ----------------------------------------------------------------------------------- */
.align 4
.global FreeRTOS_IRQ_Handler
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
SUB LR, LR, #4 /* Return to the interrupted instruction. */
SRSDB SP!, #IRQ_MODE /* Save return state (i.e. SPSR_irq and LR_irq) to the IRQ stack. */
/* Change to supervisor mode to allow reentry. It is necessary to ensure
* that a BL instruction within the interrupt handler code does not
* overwrite LR_irq. */
CPS #SVC_MODE
PUSH { R0-R3, R12 } /* Push AAPCS callee saved registers. */
/* Update interrupt nesting count. */
LDR R0, =ulPortInterruptNesting /* R0 = &( ulPortInterruptNesting ). */
LDR R1, [R0] /* R1 = ulPortInterruptNesting. */
ADD R2, R1, #1 /* R2 = R1 + 1. */
STR R2, [R0] /* Store the updated nesting count. */
/* Call the application provided IRQ handler. */
PUSH { R0-R3, LR }
BL vApplicationIRQHandler
POP { R0-R3, LR }
/* Disable IRQs incase vApplicationIRQHandler enabled them for re-entry. */
CPSID I
DSB
ISB
/* Restore the old interrupt nesting count. R0 holds the address of
* ulPortInterruptNesting and R1 holds original value of
* ulPortInterruptNesting. */
STR R1, [R0]
/* Context swtich is only performed when interrupt nesting count is 0. */
CMP R1, #0
BNE exit_without_switch
/* Check ulPortInterruptNesting to see if the interrupt requested a context
* switch. */
LDR R1, =ulPortYieldRequired /* R1 = &( ulPortYieldRequired ). */
LDR R0, [R1] /* R0 = ulPortYieldRequired. */
/* If ulPortYieldRequired != 0, goto switch_before_exit. */
CMP R0, #0
BNE switch_before_exit
exit_without_switch:
POP { R0-R3, R12 } /* Restore AAPCS callee saved registers. */
CPS #IRQ_MODE
RFE SP!
switch_before_exit:
/* A context swtich is to be performed. Clear ulPortYieldRequired. R1 holds
* the address of ulPortYieldRequired. */
MOV R0, #0
STR R0, [R1]
/* Restore AAPCS callee saved registers, SPSR_irq and LR_irq before saving
* the task context. */
POP { R0-R3, R12 }
CPS #IRQ_MODE
/* The contents of the IRQ stack at this point is the following:
* +----------+
* SP+4 | SPSR_irq |
* +----------+
* SP | LR_irq |
* +----------+
*/
LDMIB SP!, { LR }
MSR SPSR_cxsf, LR
LDMDB SP, { LR }
ADD SP, SP, 0x4
portSAVE_CONTEXT
/* Call the function that selects the new task to execute. */
BLX vTaskSwitchContext
/* Restore the context of, and branch to, the task selected to execute
* next. */
portRESTORE_CONTEXT
/* ----------------------------------------------------------------------------------- */
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 31,177 | portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* ----------------------------------------------------------------------------------- */
.arm
.syntax unified
.section freertos_system_calls
#define FREERTOS_ASSEMBLY
#include "FreeRTOSConfig.h"
#include "portmacro_asm.h"
#include "mpu_syscall_numbers.h"
#undef FREERTOS_ASSEMBLY
/* ----------------------- Start of Port Specific System Calls ----------------------- */
/*
* void vPortYield( void );
*/
.align 4
.global vPortYield
.type vPortYield, %function
vPortYield:
SVC #portSVC_YIELD
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* void vPortSystemCallExit( void );
*/
.align 4
.global vPortSystemCallExit
.type vPortSystemCallExit, %function
vPortSystemCallExit:
SVC #portSVC_SYSTEM_CALL_EXIT
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* BaseType_t xPortIsPrivileged( void );
*
* According to the Procedure Call Standard for the ARM Architecture (AAPCS):
* - Return value must be in R0.
*/
.align 4
.global xPortIsPrivileged
.type xPortIsPrivileged, %function
xPortIsPrivileged:
MRS R0, CPSR /* R0 = CPSR. */
AND R0, R0, #0x1F /* R0 = R0 & 0x1F. Extract mode bits.*/
CMP R0, #USER_MODE /* If R0 == #USER_MODE. */
MOVEQ R0, #0x0 /* Then, set R0 to 0 to indicate that the processer is not privileged. */
MOVNE R0, #0x01 /* Otherwise, set R0 to 1 to indicate that the processer is privileged. */
BX LR
/* ----------------------------------------------------------------------------------- */
/*
* UBaseType_t ulPortCountLeadingZeros( UBaseType_t ulBitmap );
*
* According to the Procedure Call Standard for the ARM Architecture (AAPCS):
* - Parameter ulBitmap is passed in R0.
* - Return value must be in R0.
*/
.align 4
.weak ulPortCountLeadingZeros
.type ulPortCountLeadingZeros, %function
ulPortCountLeadingZeros:
CLZ R0, R0
BX LR
/* ------------------- End of Port Specific System Calls ------------------- */
.macro INVOKE_SYSTEM_CALL systemCallNumber, systemCallImpl
PUSH {R0}
MRS R0, CPSR
AND R0, R0, #0x1F
CMP R0, #USER_MODE
POP {R0}
SVCEQ \systemCallNumber
B \systemCallImpl
.endm
/* ----------------------------------------------------------------------------------- */
.extern MPU_xTaskGetTickCountImpl
.align 4
.global MPU_xTaskGetTickCount
.type MPU_xTaskGetTickCount, function
MPU_xTaskGetTickCount:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetTickCount, MPU_xTaskGetTickCountImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_uxTaskGetNumberOfTasksImpl
.align 4
.global MPU_uxTaskGetNumberOfTasks
.type MPU_uxTaskGetNumberOfTasks, function
MPU_uxTaskGetNumberOfTasks:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetNumberOfTasks, MPU_uxTaskGetNumberOfTasksImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_vTaskSetTimeOutStateImpl
.align 4
.global MPU_vTaskSetTimeOutState
.type MPU_vTaskSetTimeOutState, function
MPU_vTaskSetTimeOutState:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetTimeOutState, MPU_vTaskSetTimeOutStateImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xTaskCheckForTimeOutImpl
.align 4
.global MPU_xTaskCheckForTimeOut
.type MPU_xTaskCheckForTimeOut, function
MPU_xTaskCheckForTimeOut:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskCheckForTimeOut, MPU_xTaskCheckForTimeOutImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xQueueGenericSendImpl
.align 4
.global MPU_xQueueGenericSend
.type MPU_xQueueGenericSend, function
MPU_xQueueGenericSend:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGenericSend, MPU_xQueueGenericSendImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_uxQueueMessagesWaitingImpl
.align 4
.global MPU_uxQueueMessagesWaiting
.type MPU_uxQueueMessagesWaiting, function
MPU_uxQueueMessagesWaiting:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxQueueMessagesWaiting, MPU_uxQueueMessagesWaitingImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_uxQueueSpacesAvailableImpl
.align 4
.global MPU_uxQueueSpacesAvailable
.type MPU_uxQueueSpacesAvailable, function
MPU_uxQueueSpacesAvailable:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxQueueSpacesAvailable, MPU_uxQueueSpacesAvailableImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xQueueReceiveImpl
.align 4
.global MPU_xQueueReceive
.type MPU_xQueueReceive, function
MPU_xQueueReceive:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueReceive, MPU_xQueueReceiveImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xQueuePeekImpl
.align 4
.global MPU_xQueuePeek
.type MPU_xQueuePeek, function
MPU_xQueuePeek:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueuePeek, MPU_xQueuePeekImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xQueueSemaphoreTakeImpl
.align 4
.global MPU_xQueueSemaphoreTake
.type MPU_xQueueSemaphoreTake, function
MPU_xQueueSemaphoreTake:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueSemaphoreTake, MPU_xQueueSemaphoreTakeImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xEventGroupWaitBitsImpl
.align 4
.global MPU_xEventGroupWaitBitsEntry
.type MPU_xEventGroupWaitBitsEntry, function
MPU_xEventGroupWaitBitsEntry:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupWaitBits, MPU_xEventGroupWaitBitsImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xEventGroupClearBitsImpl
.align 4
.global MPU_xEventGroupClearBits
.type MPU_xEventGroupClearBits, function
MPU_xEventGroupClearBits:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupClearBits, MPU_xEventGroupClearBitsImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xEventGroupSetBitsImpl
.align 4
.global MPU_xEventGroupSetBits
.type MPU_xEventGroupSetBits, function
MPU_xEventGroupSetBits:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSetBits, MPU_xEventGroupSetBitsImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xEventGroupSyncImpl
.align 4
.global MPU_xEventGroupSync
.type MPU_xEventGroupSync, function
MPU_xEventGroupSync:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xEventGroupSync, MPU_xEventGroupSyncImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferSendImpl
.align 4
.global MPU_xStreamBufferSend
.type MPU_xStreamBufferSend, function
MPU_xStreamBufferSend:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSend, MPU_xStreamBufferSendImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferReceiveImpl
.align 4
.global MPU_xStreamBufferReceive
.type MPU_xStreamBufferReceive, function
MPU_xStreamBufferReceive:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferReceive, MPU_xStreamBufferReceiveImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferIsFullImpl
.align 4
.global MPU_xStreamBufferIsFull
.type MPU_xStreamBufferIsFull, function
MPU_xStreamBufferIsFull:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsFull, MPU_xStreamBufferIsFullImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferIsEmptyImpl
.align 4
.global MPU_xStreamBufferIsEmpty
.type MPU_xStreamBufferIsEmpty, function
MPU_xStreamBufferIsEmpty:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferIsEmpty, MPU_xStreamBufferIsEmptyImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferSpacesAvailableImpl
.align 4
.global MPU_xStreamBufferSpacesAvailable
.type MPU_xStreamBufferSpacesAvailable, function
MPU_xStreamBufferSpacesAvailable:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSpacesAvailable, MPU_xStreamBufferSpacesAvailableImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferBytesAvailableImpl
.align 4
.global MPU_xStreamBufferBytesAvailable
.type MPU_xStreamBufferBytesAvailable, function
MPU_xStreamBufferBytesAvailable:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferBytesAvailable, MPU_xStreamBufferBytesAvailableImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferSetTriggerLevelImpl
.align 4
.global MPU_xStreamBufferSetTriggerLevel
.type MPU_xStreamBufferSetTriggerLevel, function
MPU_xStreamBufferSetTriggerLevel:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferSetTriggerLevel, MPU_xStreamBufferSetTriggerLevelImpl
/* ----------------------------------------------------------------------------------- */
.extern MPU_xStreamBufferNextMessageLengthBytesImpl
.align 4
.global MPU_xStreamBufferNextMessageLengthBytes
.type MPU_xStreamBufferNextMessageLengthBytes, function
MPU_xStreamBufferNextMessageLengthBytes:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes, MPU_xStreamBufferNextMessageLengthBytesImpl
/* ----------------------------------------------------------------------------------- */
#if ( ( INCLUDE_xTaskDelayUntil == 1 ) || ( INCLUDE_vTaskDelayUntil == 1 ) )
.extern MPU_xTaskDelayUntilImpl
.align 4
.global MPU_xTaskDelayUntil
.type MPU_xTaskDelayUntil, function
MPU_xTaskDelayUntil:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskDelayUntil, MPU_xTaskDelayUntilImpl
#endif /* if ( ( INCLUDE_xTaskDelayUntil == 1 ) || ( INCLUDE_vTaskDelayUntil == 1 ) ) */
/* ----------------------------------------------------------------------------------- */
#if ( INCLUDE_xTaskAbortDelay == 1 )
.extern MPU_xTaskAbortDelayImpl
.align 4
.global MPU_xTaskAbortDelay
.type MPU_xTaskAbortDelay, function
MPU_xTaskAbortDelay:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskAbortDelay, MPU_xTaskAbortDelayImpl
#endif /* if ( INCLUDE_xTaskAbortDelay == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_vTaskDelay == 1 )
.extern MPU_vTaskDelayImpl
.align 4
.global MPU_vTaskDelay
.type MPU_vTaskDelay, function
MPU_vTaskDelay:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskDelay, MPU_vTaskDelayImpl
#endif /* if ( INCLUDE_vTaskDelay == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_uxTaskPriorityGet == 1 )
.extern MPU_uxTaskPriorityGetImpl
.align 4
.global MPU_uxTaskPriorityGet
.type MPU_uxTaskPriorityGet, function
MPU_uxTaskPriorityGet:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskPriorityGet, MPU_uxTaskPriorityGetImpl
#endif /* if ( INCLUDE_uxTaskPriorityGet == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_eTaskGetState == 1 )
.extern MPU_eTaskGetStateImpl
.align 4
.global MPU_eTaskGetState
.type MPU_eTaskGetState, function
MPU_eTaskGetState:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_eTaskGetState, MPU_eTaskGetStateImpl
#endif /* if ( INCLUDE_eTaskGetState == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( configUSE_TRACE_FACILITY == 1 )
.extern MPU_vTaskGetInfoImpl
.align 4
.global MPU_vTaskGetInfo
.type MPU_vTaskGetInfo, function
MPU_vTaskGetInfo:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskGetInfo, MPU_vTaskGetInfoImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_uxTaskGetSystemStateImpl
.align 4
.global MPU_uxTaskGetSystemState
.type MPU_uxTaskGetSystemState, function
MPU_uxTaskGetSystemState:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetSystemState, MPU_uxTaskGetSystemStateImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_uxEventGroupGetNumberImpl
.align 4
.global MPU_uxEventGroupGetNumber
.type MPU_uxEventGroupGetNumber, function
MPU_uxEventGroupGetNumber:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxEventGroupGetNumber, MPU_uxEventGroupGetNumberImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_vEventGroupSetNumberImpl
.align 4
.global MPU_vEventGroupSetNumber
.type MPU_vEventGroupSetNumber, function
MPU_vEventGroupSetNumber:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vEventGroupSetNumber, MPU_vEventGroupSetNumberImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
.extern MPU_xTaskGetIdleTaskHandleImpl
.align 4
.global MPU_xTaskGetIdleTaskHandle
.type MPU_xTaskGetIdleTaskHandle, function
MPU_xTaskGetIdleTaskHandle:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetIdleTaskHandle, MPU_xTaskGetIdleTaskHandleImpl
#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_vTaskSuspend == 1 )
.extern MPU_vTaskSuspendImpl
.align 4
.global MPU_vTaskSuspend
.type MPU_vTaskSuspend, function
MPU_vTaskSuspend:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSuspend, MPU_vTaskSuspendImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_vTaskResumeImpl
.align 4
.global MPU_vTaskResume
.type MPU_vTaskResume, function
MPU_vTaskResume:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskResume, MPU_vTaskResumeImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( configGENERATE_RUN_TIME_STATS == 1 )
.extern MPU_ulTaskGetRunTimeCounterImpl
.align 4
.global MPU_ulTaskGetRunTimeCounter
.type MPU_ulTaskGetRunTimeCounter, function
MPU_ulTaskGetRunTimeCounter:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetRunTimeCounter, MPU_ulTaskGetRunTimeCounterImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_ulTaskGetRunTimePercentImpl
.align 4
.global MPU_ulTaskGetRunTimePercent
.type MPU_ulTaskGetRunTimePercent, function
MPU_ulTaskGetRunTimePercent:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetRunTimePercent, MPU_ulTaskGetRunTimePercentImpl
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
.extern MPU_ulTaskGetIdleRunTimePercentImpl
.align 4
.global MPU_ulTaskGetIdleRunTimePercent
.type MPU_ulTaskGetIdleRunTimePercent, function
MPU_ulTaskGetIdleRunTimePercent:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetIdleRunTimePercent, MPU_ulTaskGetIdleRunTimePercentImpl
/* --------------------------------------------------------------------------- */
.extern MPU_ulTaskGetIdleRunTimeCounterImpl
.align 4
.global MPU_ulTaskGetIdleRunTimeCounter
.type MPU_ulTaskGetIdleRunTimeCounter, function
MPU_ulTaskGetIdleRunTimeCounter:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter, MPU_ulTaskGetIdleRunTimeCounterImpl
/* --------------------------------------------------------------------------- */
#endif /* if ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) */
#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 )*/
/* --------------------------------------------------------------------------- */
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
.extern MPU_vTaskSetApplicationTaskTagImpl
.align 4
.global MPU_vTaskSetApplicationTaskTag
.type MPU_vTaskSetApplicationTaskTag, function
MPU_vTaskSetApplicationTaskTag:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetApplicationTaskTag, MPU_vTaskSetApplicationTaskTagImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTaskGetApplicationTaskTagImpl
.align 4
.global MPU_xTaskGetApplicationTaskTag
.type MPU_xTaskGetApplicationTaskTag, function
MPU_xTaskGetApplicationTaskTag:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetApplicationTaskTag, MPU_xTaskGetApplicationTaskTagImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
.extern MPU_vTaskSetThreadLocalStoragePointerImpl
.align 4
.global MPU_vTaskSetThreadLocalStoragePointer
.type MPU_vTaskSetThreadLocalStoragePointer, function
MPU_vTaskSetThreadLocalStoragePointer:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer, MPU_vTaskSetThreadLocalStoragePointerImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_pvTaskGetThreadLocalStoragePointerImpl
.align 4
.global MPU_pvTaskGetThreadLocalStoragePointer
.type MPU_pvTaskGetThreadLocalStoragePointer, function
MPU_pvTaskGetThreadLocalStoragePointer:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer, MPU_pvTaskGetThreadLocalStoragePointerImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
.extern MPU_uxTaskGetStackHighWaterMarkImpl
.align 4
.global MPU_uxTaskGetStackHighWaterMark
.type MPU_uxTaskGetStackHighWaterMark, function
MPU_uxTaskGetStackHighWaterMark:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetStackHighWaterMark, MPU_uxTaskGetStackHighWaterMarkImpl
#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
.extern MPU_uxTaskGetStackHighWaterMark2Impl
.align 4
.global MPU_uxTaskGetStackHighWaterMark2
.type MPU_uxTaskGetStackHighWaterMark2, function
MPU_uxTaskGetStackHighWaterMark2:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTaskGetStackHighWaterMark2, MPU_uxTaskGetStackHighWaterMark2Impl
#endif /* if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
.extern MPU_xTaskGetCurrentTaskHandleImpl
.align 4
.global MPU_xTaskGetCurrentTaskHandle
.type MPU_xTaskGetCurrentTaskHandle, function
MPU_xTaskGetCurrentTaskHandle:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetCurrentTaskHandle, MPU_xTaskGetCurrentTaskHandleImpl
#endif /* if( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
/* ------------------------------------------------------------------------------- */
#if ( INCLUDE_xTaskGetSchedulerState == 1 )
.extern MPU_xTaskGetSchedulerStateImpl
.align 4
.global MPU_xTaskGetSchedulerState
.type MPU_xTaskGetSchedulerState, function
MPU_xTaskGetSchedulerState:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGetSchedulerState, MPU_xTaskGetSchedulerStateImpl
#endif /* if ( INCLUDE_xTaskGetSchedulerState == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
.extern MPU_xQueueGetMutexHolderImpl
.align 4
.global MPU_xQueueGetMutexHolder
.type MPU_xQueueGetMutexHolder, function
MPU_xQueueGetMutexHolder:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGetMutexHolder, MPU_xQueueGetMutexHolderImpl
#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
/* ------------------------------------------------------------------------------- */
#if ( configUSE_RECURSIVE_MUTEXES == 1 )
.extern MPU_xQueueTakeMutexRecursiveImpl
.align 4
.global MPU_xQueueTakeMutexRecursive
.type MPU_xQueueTakeMutexRecursive, function
MPU_xQueueTakeMutexRecursive:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueTakeMutexRecursive, MPU_xQueueTakeMutexRecursiveImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xQueueGiveMutexRecursiveImpl
.align 4
.global MPU_xQueueGiveMutexRecursive
.type MPU_xQueueGiveMutexRecursive, function
MPU_xQueueGiveMutexRecursive:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueGiveMutexRecursive, MPU_xQueueGiveMutexRecursiveImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( configUSE_QUEUE_SETS == 1 )
.extern MPU_xQueueSelectFromSetImpl
.align 4
.global MPU_xQueueSelectFromSet
.type MPU_xQueueSelectFromSet, function
MPU_xQueueSelectFromSet:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueSelectFromSet, MPU_xQueueSelectFromSetImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xQueueAddToSetImpl
.align 4
.global MPU_xQueueAddToSet
.type MPU_xQueueAddToSet, function
MPU_xQueueAddToSet:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xQueueAddToSet, MPU_xQueueAddToSetImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( configQUEUE_REGISTRY_SIZE > 0 )
.extern MPU_vQueueAddToRegistryImpl
.align 4
.global MPU_vQueueAddToRegistry
.type MPU_vQueueAddToRegistry, function
MPU_vQueueAddToRegistry:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vQueueAddToRegistry, MPU_vQueueAddToRegistryImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_vQueueUnregisterQueueImpl
.align 4
.global MPU_vQueueUnregisterQueue
.type MPU_vQueueUnregisterQueue, function
MPU_vQueueUnregisterQueue:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vQueueUnregisterQueue, MPU_vQueueUnregisterQueueImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_pcQueueGetNameImpl
.align 4
.global MPU_pcQueueGetName
.type MPU_pcQueueGetName, function
MPU_pcQueueGetName:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_pcQueueGetName, MPU_pcQueueGetNameImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configQUEUE_REGISTRY_SIZE > 0 ) */
/* ------------------------------------------------------------------------------- */
#if ( configUSE_TIMERS == 1 )
.extern MPU_pvTimerGetTimerIDImpl
.align 4
.global MPU_pvTimerGetTimerID
.type MPU_pvTimerGetTimerID, function
MPU_pvTimerGetTimerID:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_pvTimerGetTimerID, MPU_pvTimerGetTimerIDImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_vTimerSetTimerIDImpl
.align 4
.global MPU_vTimerSetTimerID
.type MPU_vTimerSetTimerID, function
MPU_vTimerSetTimerID:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTimerSetTimerID, MPU_vTimerSetTimerIDImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTimerIsTimerActiveImpl
.align 4
.global MPU_xTimerIsTimerActive
.type MPU_xTimerIsTimerActive, function
MPU_xTimerIsTimerActive:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerIsTimerActive, MPU_xTimerIsTimerActiveImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTimerGetTimerDaemonTaskHandleImpl
.align 4
.global MPU_xTimerGetTimerDaemonTaskHandle
.type MPU_xTimerGetTimerDaemonTaskHandle, function
MPU_xTimerGetTimerDaemonTaskHandle:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle, MPU_xTimerGetTimerDaemonTaskHandleImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTimerGenericCommandFromTaskImpl
.align 4
.global MPU_xTimerGenericCommandFromTaskEntry
.type MPU_xTimerGenericCommandFromTaskEntry, function
MPU_xTimerGenericCommandFromTaskEntry:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGenericCommandFromTask, MPU_xTimerGenericCommandFromTaskImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_pcTimerGetNameImpl
.align 4
.global MPU_pcTimerGetName
.type MPU_pcTimerGetName, function
MPU_pcTimerGetName:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_pcTimerGetName, MPU_pcTimerGetNameImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_vTimerSetReloadModeImpl
.align 4
.global MPU_vTimerSetReloadMode
.type MPU_vTimerSetReloadMode, function
MPU_vTimerSetReloadMode:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_vTimerSetReloadMode, MPU_vTimerSetReloadModeImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTimerGetReloadModeImpl
.align 4
.global MPU_xTimerGetReloadMode
.type MPU_xTimerGetReloadMode, function
MPU_xTimerGetReloadMode:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetReloadMode, MPU_xTimerGetReloadModeImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_uxTimerGetReloadModeImpl
.align 4
.global MPU_uxTimerGetReloadMode
.type MPU_uxTimerGetReloadMode, function
MPU_uxTimerGetReloadMode:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_uxTimerGetReloadMode, MPU_uxTimerGetReloadModeImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTimerGetPeriodImpl
.align 4
.global MPU_xTimerGetPeriod
.type MPU_xTimerGetPeriod, function
MPU_xTimerGetPeriod:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetPeriod, MPU_xTimerGetPeriodImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTimerGetExpiryTimeImpl
.align 4
.global MPU_xTimerGetExpiryTime
.type MPU_xTimerGetExpiryTime, function
MPU_xTimerGetExpiryTime:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTimerGetExpiryTime, MPU_xTimerGetExpiryTimeImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configUSE_TIMERS == 1 ) */
/* ------------------------------------------------------------------------------- */
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
.extern MPU_xTaskGenericNotifyImpl
.align 4
.global MPU_xTaskGenericNotifyEntry
.type MPU_xTaskGenericNotifyEntry, function
MPU_xTaskGenericNotifyEntry:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotify, MPU_xTaskGenericNotifyImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTaskGenericNotifyWaitImpl
.align 4
.global MPU_xTaskGenericNotifyWaitEntry
.type MPU_xTaskGenericNotifyWaitEntry, function
MPU_xTaskGenericNotifyWaitEntry:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotifyWait, MPU_xTaskGenericNotifyWaitImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_ulTaskGenericNotifyTakeImpl
.align 4
.global MPU_ulTaskGenericNotifyTake
.type MPU_ulTaskGenericNotifyTake, function
MPU_ulTaskGenericNotifyTake:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGenericNotifyTake, MPU_ulTaskGenericNotifyTakeImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_xTaskGenericNotifyStateClearImpl
.align 4
.global MPU_xTaskGenericNotifyStateClear
.type MPU_xTaskGenericNotifyStateClear, function
MPU_xTaskGenericNotifyStateClear:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_xTaskGenericNotifyStateClear, MPU_xTaskGenericNotifyStateClearImpl
/* ------------------------------------------------------------------------------- */
.extern MPU_ulTaskGenericNotifyValueClearImpl
.align 4
.global MPU_ulTaskGenericNotifyValueClear
.type MPU_ulTaskGenericNotifyValueClear, function
MPU_ulTaskGenericNotifyValueClear:
INVOKE_SYSTEM_CALL #SYSTEM_CALL_ulTaskGenericNotifyValueClear, MPU_ulTaskGenericNotifyValueClearImpl
/* ------------------------------------------------------------------------------- */
#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
/* ------------------------------------------------------------------------------- */
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 2,686 | portable/GCC/RL78/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "FreeRTOSConfig.h"
#include "ISR_Support.h"
.global _vPortYield
.global _vPortStartFirstTask
.global _vPortTickISR
.extern _vTaskSwitchContext
.extern _xTaskIncrementTick
.text
.align 2
/* FreeRTOS yield handler. This is installed as the BRK software interrupt
handler. */
_vPortYield:
/* Save the context of the current task. */
portSAVE_CONTEXT
/* Call the scheduler to select the next task. */
call !!_vTaskSwitchContext
/* Restore the context of the next task to run. */
portRESTORE_CONTEXT
retb
/* Starts the scheduler by restoring the context of the task that will execute
first. */
.align 2
_vPortStartFirstTask:
/* Restore the context of whichever task will execute first. */
portRESTORE_CONTEXT
/* An interrupt stack frame is used so the task is started using RETI. */
reti
/* FreeRTOS tick handler. This is installed as the interval timer interrupt
handler. */
.align 2
_vPortTickISR:
/* Save the context of the currently executing task. */
portSAVE_CONTEXT
/* Call the RTOS tick function. */
call !!_xTaskIncrementTick
#if configUSE_PREEMPTION == 1
/* Select the next task to run. */
call !!_vTaskSwitchContext
#endif
/* Retore the context of whichever task will run next. */
portRESTORE_CONTEXT
reti
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 12,722 | portable/GCC/ARM_CA53_64_BIT/portASM.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.text
/* Variables and functions. */
.extern ullMaxAPIPriorityMask
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vApplicationIRQHandler
.extern ullPortInterruptNesting
.extern ullPortTaskHasFPUContext
.extern ullCriticalNesting
.extern ullPortYieldRequired
.extern ullICCEOIR
.extern ullICCIAR
.extern _freertos_vector_table
.global FreeRTOS_IRQ_Handler
.global FreeRTOS_SWI_Handler
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Save the entire context. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X20, X21, [SP, #-0x10]!
STP X22, X23, [SP, #-0x10]!
STP X24, X25, [SP, #-0x10]!
STP X26, X27, [SP, #-0x10]!
STP X28, X29, [SP, #-0x10]!
STP X30, XZR, [SP, #-0x10]!
/* Save the SPSR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
/* Save the ELR. */
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Save the critical section nesting depth. */
LDR X0, ullCriticalNestingConst
LDR X3, [X0]
/* Save the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
LDR X2, [X0]
/* Save the FPU context, if any (32 128-bit registers). */
CMP X2, #0
B.EQ 1f
STP Q0, Q1, [SP,#-0x20]!
STP Q2, Q3, [SP,#-0x20]!
STP Q4, Q5, [SP,#-0x20]!
STP Q6, Q7, [SP,#-0x20]!
STP Q8, Q9, [SP,#-0x20]!
STP Q10, Q11, [SP,#-0x20]!
STP Q12, Q13, [SP,#-0x20]!
STP Q14, Q15, [SP,#-0x20]!
STP Q16, Q17, [SP,#-0x20]!
STP Q18, Q19, [SP,#-0x20]!
STP Q20, Q21, [SP,#-0x20]!
STP Q22, Q23, [SP,#-0x20]!
STP Q24, Q25, [SP,#-0x20]!
STP Q26, Q27, [SP,#-0x20]!
STP Q28, Q29, [SP,#-0x20]!
STP Q30, Q31, [SP,#-0x20]!
1:
/* Store the critical nesting count and FPU context indicator. */
STP X2, X3, [SP, #-0x10]!
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
MOV X0, SP /* Move SP into X0 for saving. */
STR X0, [X1]
/* Switch to use the ELx stack pointer. */
MSR SPSEL, #1
.endm
; /**********************************************************************/
.macro portRESTORE_CONTEXT
/* Switch to use the EL0 stack pointer. */
MSR SPSEL, #0
/* Set the SP to point to the stack of the task being restored. */
LDR X0, pxCurrentTCBConst
LDR X1, [X0]
LDR X0, [X1]
MOV SP, X0
LDP X2, X3, [SP], #0x10 /* Critical nesting and FPU context. */
/* Set the PMR register to be correct for the current critical nesting
depth. */
LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
MOV X1, #255 /* X1 holds the unmask value. */
LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
CMP X3, #0
LDR X5, [X4] /* X5 holds the address of the ICCPMR register. */
B.EQ 1f
LDR X6, ullMaxAPIPriorityMaskConst
LDR X1, [X6] /* X1 holds the mask value. */
1:
STR W1, [X5] /* Write the mask value to ICCPMR. */
DSB SY /* _RB_Barriers probably not required here. */
ISB SY
STR X3, [X0] /* Restore the task's critical nesting count. */
/* Restore the FPU context indicator. */
LDR X0, ullPortTaskHasFPUContextConst
STR X2, [X0]
/* Restore the FPU context, if any. */
CMP X2, #0
B.EQ 1f
LDP Q30, Q31, [SP], #0x20
LDP Q28, Q29, [SP], #0x20
LDP Q26, Q27, [SP], #0x20
LDP Q24, Q25, [SP], #0x20
LDP Q22, Q23, [SP], #0x20
LDP Q20, Q21, [SP], #0x20
LDP Q18, Q19, [SP], #0x20
LDP Q16, Q17, [SP], #0x20
LDP Q14, Q15, [SP], #0x20
LDP Q12, Q13, [SP], #0x20
LDP Q10, Q11, [SP], #0x20
LDP Q8, Q9, [SP], #0x20
LDP Q6, Q7, [SP], #0x20
LDP Q4, Q5, [SP], #0x20
LDP Q2, Q3, [SP], #0x20
LDP Q0, Q1, [SP], #0x20
1:
LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
/* Restore the SPSR. */
MSR SPSR_EL1, X3
/* Restore the ELR. */
MSR ELR_EL1, X2
#else
/* Restore the SPSR. */
MSR SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
/* Restore the ELR. */
MSR ELR_EL3, X2
#endif
LDP X30, XZR, [SP], #0x10
LDP X28, X29, [SP], #0x10
LDP X26, X27, [SP], #0x10
LDP X24, X25, [SP], #0x10
LDP X22, X23, [SP], #0x10
LDP X20, X21, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Switch to use the ELx stack pointer. _RB_ Might not be required. */
MSR SPSEL, #1
ERET
.endm
/******************************************************************************
* FreeRTOS_SWI_Handler handler is used to perform a context switch.
*****************************************************************************/
.align 8
.type FreeRTOS_SWI_Handler, %function
FreeRTOS_SWI_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
#if defined( GUEST )
MRS X0, ESR_EL1
#else
MRS X0, ESR_EL3
#endif
LSR X1, X0, #26
#if defined( GUEST )
CMP X1, #0x15 /* 0x15 = SVC instruction. */
#else
CMP X1, #0x17 /* 0x17 = SMC instruction. */
#endif
B.NE FreeRTOS_Abort
BL vTaskSwitchContext
portRESTORE_CONTEXT
FreeRTOS_Abort:
/* Full ESR is in X0, exception class code is in X1. */
B .
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
.align 8
.type vPortRestoreTaskContext, %function
vPortRestoreTaskContext:
.set freertos_vector_base, _freertos_vector_table
/* Install the FreeRTOS interrupt handlers. */
LDR X1, =freertos_vector_base
#if defined( GUEST )
MSR VBAR_EL1, X1
#else
MSR VBAR_EL3, X1
#endif
DSB SY
ISB SY
/* Start the first task. */
portRESTORE_CONTEXT
/******************************************************************************
* FreeRTOS_IRQ_Handler handles IRQ entry and exit.
*****************************************************************************/
.align 8
.type FreeRTOS_IRQ_Handler, %function
FreeRTOS_IRQ_Handler:
/* Save volatile registers. */
STP X0, X1, [SP, #-0x10]!
STP X2, X3, [SP, #-0x10]!
STP X4, X5, [SP, #-0x10]!
STP X6, X7, [SP, #-0x10]!
STP X8, X9, [SP, #-0x10]!
STP X10, X11, [SP, #-0x10]!
STP X12, X13, [SP, #-0x10]!
STP X14, X15, [SP, #-0x10]!
STP X16, X17, [SP, #-0x10]!
STP X18, X19, [SP, #-0x10]!
STP X29, X30, [SP, #-0x10]!
/* Save the SPSR and ELR. */
#if defined( GUEST )
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
#else
MRS X3, SPSR_EL3
MRS X2, ELR_EL3
#endif
STP X2, X3, [SP, #-0x10]!
/* Increment the interrupt nesting counter. */
LDR X5, ullPortInterruptNestingConst
LDR X1, [X5] /* Old nesting count in X1. */
ADD X6, X1, #1
STR X6, [X5] /* Address of nesting count variable in X5. */
/* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]!
/* Read value from the interrupt acknowledge register, which is stored in W0
for future parameter and interrupt clearing use. */
LDR X2, ullICCIARConst
LDR X3, [X2]
LDR W0, [X3] /* ICCIAR in W0 as parameter. */
/* Maintain the ICCIAR value across the function call. */
STP X0, X1, [SP, #-0x10]!
/* Call the C handler. */
BL vApplicationIRQHandler
/* Disable interrupts. */
MSR DAIFSET, #2
DSB SY
ISB SY
/* Restore the ICCIAR value. */
LDP X0, X1, [SP], #0x10
/* End IRQ processing by writing ICCIAR to the EOI register. */
LDR X4, ullICCEOIRConst
LDR X4, [X4]
STR W0, [X4]
/* Restore the critical nesting count. */
LDP X1, X5, [SP], #0x10
STR X1, [X5]
/* Has interrupt nesting unwound? */
CMP X1, #0
B.NE Exit_IRQ_No_Context_Switch
/* Is a context switch required? */
LDR X0, ullPortYieldRequiredConst
LDR X1, [X0]
CMP X1, #0
B.EQ Exit_IRQ_No_Context_Switch
/* Reset ullPortYieldRequired to 0. */
MOV X2, #0
STR X2, [X0]
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
BL vTaskSwitchContext
portRESTORE_CONTEXT
Exit_IRQ_No_Context_Switch:
/* Restore volatile registers. */
LDP X4, X5, [SP], #0x10 /* SPSR and ELR. */
#if defined( GUEST )
MSR SPSR_EL1, X5
MSR ELR_EL1, X4
#else
MSR SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
MSR ELR_EL3, X4
#endif
DSB SY
ISB SY
LDP X29, X30, [SP], #0x10
LDP X18, X19, [SP], #0x10
LDP X16, X17, [SP], #0x10
LDP X14, X15, [SP], #0x10
LDP X12, X13, [SP], #0x10
LDP X10, X11, [SP], #0x10
LDP X8, X9, [SP], #0x10
LDP X6, X7, [SP], #0x10
LDP X4, X5, [SP], #0x10
LDP X2, X3, [SP], #0x10
LDP X0, X1, [SP], #0x10
ERET
.align 8
pxCurrentTCBConst: .dword pxCurrentTCB
ullCriticalNestingConst: .dword ullCriticalNesting
ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
ullICCPMRConst: .dword ullICCPMR
ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
ullPortInterruptNestingConst: .dword ullPortInterruptNesting
ullPortYieldRequiredConst: .dword ullPortYieldRequired
ullICCIARConst: .dword ullICCIAR
ullICCEOIRConst: .dword ullICCEOIR
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 11,079 | portable/GCC/MicroBlazeV9/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* FreeRTOS includes. */
#include "FreeRTOSConfig.h"
/* Xilinx library includes. */
#include "microblaze_exceptions_g.h"
#include "xparameters.h"
#include "microblaze_instructions.h"
/* The context is oversized to allow functions called from the ISR to write
back into the caller stack. */
#if defined (__arch64__)
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
#define portCONTEXT_SIZE 272
#define portMINUS_CONTEXT_SIZE -272
#else
#define portCONTEXT_SIZE 264
#define portMINUS_CONTEXT_SIZE -264
#endif
#else
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
#define portCONTEXT_SIZE 136
#define portMINUS_CONTEXT_SIZE -136
#else
#define portCONTEXT_SIZE 132
#define portMINUS_CONTEXT_SIZE -132
#endif
#endif
/* Offsets from the stack pointer at which saved registers are placed. */
#if defined (__arch64__)
#define portR31_OFFSET 8
#define portR30_OFFSET 16
#define portR29_OFFSET 24
#define portR28_OFFSET 32
#define portR27_OFFSET 40
#define portR26_OFFSET 48
#define portR25_OFFSET 56
#define portR24_OFFSET 64
#define portR23_OFFSET 72
#define portR22_OFFSET 80
#define portR21_OFFSET 88
#define portR20_OFFSET 96
#define portR19_OFFSET 104
#define portR18_OFFSET 112
#define portR17_OFFSET 120
#define portR16_OFFSET 128
#define portR15_OFFSET 136
#define portR14_OFFSET 144
#define portR13_OFFSET 152
#define portR12_OFFSET 160
#define portR11_OFFSET 168
#define portR10_OFFSET 176
#define portR9_OFFSET 184
#define portR8_OFFSET 192
#define portR7_OFFSET 200
#define portR6_OFFSET 208
#define portR5_OFFSET 216
#define portR4_OFFSET 224
#define portR3_OFFSET 232
#define portR2_OFFSET 240
#define portCRITICAL_NESTING_OFFSET 248
#define portMSR_OFFSET 256
#define portFSR_OFFSET 264
#else
#define portR31_OFFSET 4
#define portR30_OFFSET 8
#define portR29_OFFSET 12
#define portR28_OFFSET 16
#define portR27_OFFSET 20
#define portR26_OFFSET 24
#define portR25_OFFSET 28
#define portR24_OFFSET 32
#define portR23_OFFSET 36
#define portR22_OFFSET 40
#define portR21_OFFSET 44
#define portR20_OFFSET 48
#define portR19_OFFSET 52
#define portR18_OFFSET 56
#define portR17_OFFSET 60
#define portR16_OFFSET 64
#define portR15_OFFSET 68
#define portR14_OFFSET 72
#define portR13_OFFSET 76
#define portR12_OFFSET 80
#define portR11_OFFSET 84
#define portR10_OFFSET 88
#define portR9_OFFSET 92
#define portR8_OFFSET 96
#define portR7_OFFSET 100
#define portR6_OFFSET 104
#define portR5_OFFSET 108
#define portR4_OFFSET 112
#define portR3_OFFSET 116
#define portR2_OFFSET 120
#define portCRITICAL_NESTING_OFFSET 124
#define portMSR_OFFSET 128
#define portFSR_OFFSET 132
#endif
.extern pxCurrentTCB
.extern XIntc_DeviceInterruptHandler
.extern vTaskSwitchContext
.extern uxCriticalNesting
.extern pulISRStack
.extern ulTaskSwitchRequested
.extern vPortExceptionHandler
.extern pulStackPointerOnFunctionEntry
.global _interrupt_handler
.global VPortYieldASM
.global vPortStartFirstTask
.global vPortExceptionHandlerEntry
.macro portSAVE_CONTEXT
/* Make room for the context on the stack. */
ADDLIK r1, r1, portMINUS_CONTEXT_SIZE
/* Stack general registers. */
SI r31, r1, portR31_OFFSET
SI r30, r1, portR30_OFFSET
SI r29, r1, portR29_OFFSET
SI r28, r1, portR28_OFFSET
SI r27, r1, portR27_OFFSET
SI r26, r1, portR26_OFFSET
SI r25, r1, portR25_OFFSET
SI r24, r1, portR24_OFFSET
SI r23, r1, portR23_OFFSET
SI r22, r1, portR22_OFFSET
SI r21, r1, portR21_OFFSET
SI r20, r1, portR20_OFFSET
SI r19, r1, portR19_OFFSET
SI r18, r1, portR18_OFFSET
SI r17, r1, portR17_OFFSET
SI r16, r1, portR16_OFFSET
SI r15, r1, portR15_OFFSET
/* R14 is saved later as it needs adjustment if a yield is performed. */
SI r13, r1, portR13_OFFSET
SI r12, r1, portR12_OFFSET
SI r11, r1, portR11_OFFSET
SI r10, r1, portR10_OFFSET
SI r9, r1, portR9_OFFSET
SI r8, r1, portR8_OFFSET
SI r7, r1, portR7_OFFSET
SI r6, r1, portR6_OFFSET
SI r5, r1, portR5_OFFSET
SI r4, r1, portR4_OFFSET
SI r3, r1, portR3_OFFSET
SI r2, r1, portR2_OFFSET
/* Stack the critical section nesting value. */
LI r18, r0, uxCriticalNesting
SI r18, r1, portCRITICAL_NESTING_OFFSET
/* Stack MSR. */
mfs r18, rmsr
SI r18, r1, portMSR_OFFSET
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* Stack FSR. */
mfs r18, rfsr
SI r18, r1, portFSR_OFFSET
#endif
#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
/* Save the stack limits */
mfs r18, rslr
swi r18, r1, portSLR_OFFSET
mfs r18, rshr
swi r18, r1, portSHR_OFFSET
#endif
/* Save the top of stack value to the TCB. */
LI r3, r0, pxCurrentTCB
STORE r1, r0, r3
.endm
.macro portRESTORE_CONTEXT
/* Load the top of stack value from the TCB. */
LI r18, r0, pxCurrentTCB
LOAD r1, r0, r18
#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
/* Restore the stack limits -- must not load from r1 (Stack Pointer)
because if the address of load or store instruction is out of range,
it will trigger Stack Protection Violation exception. */
or r18, r0, r1
lwi r12, r18, portSLR_OFFSET
mts rslr, r12
lwi r12, r18, portSHR_OFFSET
mts rshr, r12
#endif
/* Restore the general registers. */
LI r31, r1, portR31_OFFSET
LI r30, r1, portR30_OFFSET
LI r29, r1, portR29_OFFSET
LI r28, r1, portR28_OFFSET
LI r27, r1, portR27_OFFSET
LI r26, r1, portR26_OFFSET
LI r25, r1, portR25_OFFSET
LI r24, r1, portR24_OFFSET
LI r23, r1, portR23_OFFSET
LI r22, r1, portR22_OFFSET
LI r21, r1, portR21_OFFSET
LI r20, r1, portR20_OFFSET
LI r19, r1, portR19_OFFSET
LI r17, r1, portR17_OFFSET
LI r16, r1, portR16_OFFSET
LI r15, r1, portR15_OFFSET
LI r14, r1, portR14_OFFSET
LI r13, r1, portR13_OFFSET
LI r12, r1, portR12_OFFSET
LI r11, r1, portR11_OFFSET
LI r10, r1, portR10_OFFSET
LI r9, r1, portR9_OFFSET
LI r8, r1, portR8_OFFSET
LI r7, r1, portR7_OFFSET
LI r6, r1, portR6_OFFSET
LI r5, r1, portR5_OFFSET
LI r4, r1, portR4_OFFSET
LI r3, r1, portR3_OFFSET
LI r2, r1, portR2_OFFSET
/* Reload the rmsr from the stack. */
LI r18, r1, portMSR_OFFSET
mts rmsr, r18
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* Reload the FSR from the stack. */
LI r18, r1, portFSR_OFFSET
mts rfsr, r18
#endif
/* Load the critical nesting value. */
LI r18, r1, portCRITICAL_NESTING_OFFSET
SI r18, r0, uxCriticalNesting
/* Test the critical nesting value. If it is non zero then the task last
exited the running state using a yield. If it is zero, then the task
last exited the running state through an interrupt. */
XORI r18, r18, 0
BNEI r18, exit_from_yield
/* r18 was being used as a temporary. Now restore its true value from the
stack. */
LI r18, r1, portR18_OFFSET
/* Remove the stack frame. */
ADDLIK r1, r1, portCONTEXT_SIZE
/* Return using rtid so interrupts are re-enabled as this function is
exited. */
rtid r14, 0
OR r0, r0, r0
.endm
/* This function is used to exit portRESTORE_CONTEXT() if the task being
returned to last left the Running state by calling taskYIELD() (rather than
being preempted by an interrupt). */
.text
#ifdef __arch64__
.align 8
#else
.align 4
#endif
exit_from_yield:
/* r18 was being used as a temporary. Now restore its true value from the
stack. */
LI r18, r1, portR18_OFFSET
/* Remove the stack frame. */
ADDLIK r1, r1, portCONTEXT_SIZE
/* Return to the task. */
rtsd r14, 0
OR r0, r0, r0
.text
#ifdef __arch64__
.align 8
#else
.align 4
#endif
_interrupt_handler:
portSAVE_CONTEXT
/* Stack the return address. */
SI r14, r1, portR14_OFFSET
/* Switch to the ISR stack. */
LI r1, r0, pulISRStack
#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
ori r18, r0, _stack_end
mts rslr, r18
ori r18, r0, _stack
mts rshr, r18
#endif
/* The parameter to the interrupt handler. */
ORI r5, r0, configINTERRUPT_CONTROLLER_TO_USE
/* Execute any pending interrupts. */
BRALID r15, XIntc_DeviceInterruptHandler
OR r0, r0, r0
/* See if a new task should be selected to execute. */
LI r18, r0, ulTaskSwitchRequested
OR r18, r18, r0
/* If ulTaskSwitchRequested is already zero, then jump straight to
restoring the task that is already in the Running state. */
BEQI r18, task_switch_not_requested
/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
performed. */
SI r0, r0, ulTaskSwitchRequested
/* ulTaskSwitchRequested was not 0 when tested. Select the next task to
execute. */
BRALID r15, vTaskSwitchContext
OR r0, r0, r0
task_switch_not_requested:
/* Restore the context of the next task scheduled to execute. */
portRESTORE_CONTEXT
.text
#ifdef __arch64__
.align 8
#else
.align 4
#endif
VPortYieldASM:
portSAVE_CONTEXT
/* Modify the return address so a return is done to the instruction after
the call to VPortYieldASM. */
ADDI r14, r14, 8
SI r14, r1, portR14_OFFSET
/* Switch to use the ISR stack. */
LI r1, r0, pulISRStack
#if( XPAR_MICROBLAZE_USE_STACK_PROTECTION )
ori r18, r0, _stack_end
mts rslr, r18
ori r18, r0, _stack
mts rshr, r18
#endif
/* Select the next task to execute. */
BRALID r15, vTaskSwitchContext
OR r0, r0, r0
/* Restore the context of the next task scheduled to execute. */
portRESTORE_CONTEXT
.text
#ifdef __arch64__
.align 8
#else
.align 4
#endif
vPortStartFirstTask:
portRESTORE_CONTEXT
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
.text
#ifdef __arch64__
.align 8
#else
.align 4
#endif
vPortExceptionHandlerEntry:
/* Take a copy of the stack pointer before vPortExecptionHandler is called,
storing its value prior to the function stack frame being created. */
SI r1, r0, pulStackPointerOnFunctionEntry
BRALID r15, vPortExceptionHandler
OR r0, r0, r0
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,901 | portable/GCC/NiosII/port_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
.extern vTaskSwitchContext
.set noat
# Exported to start the first task.
.globl restore_sp_from_pxCurrentTCB
# Entry point for exceptions.
.section .exceptions.entry.user, "xa"
# Save the entire context of a task.
save_context:
addi sp, sp, -116 # Create space on the stack.
stw ra, 0(sp)
# Leave a gap for muldiv 0
stw at, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r12, 52(sp)
stw r13, 56(sp)
stw r14, 60(sp)
stw r15, 64(sp)
rdctl r5, estatus # Save the eStatus
stw r5, 68(sp)
addi r15, ea, -4 # Instruction that caused exception
stw r15, 72(sp) # Save as EA
stw r16, 76(sp) # Save the remaining registers
stw r17, 80(sp)
stw r18, 84(sp)
stw r19, 88(sp)
stw r20, 92(sp)
stw r21, 96(sp)
stw r22, 100(sp)
stw r23, 104(sp)
stw gp, 108(sp)
stw fp, 112(sp)
save_sp_to_pxCurrentTCB:
movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer
ldw et, (et) # Load the value of the pxCurrentTCB pointer
stw sp, (et) # Store the stack pointer into the top of the TCB
br irq_test_user # skip the section .exceptions.entry
.section .exceptions.irqtest, "xa"
irq_test_user:
.section .exceptions.exit.user, "xa"
restore_sp_from_pxCurrentTCB:
movia et, pxCurrentTCB # Load the address of the pxCurrentTCB pointer
ldw et, (et) # Load the value of the pxCurrentTCB pointer
ldw sp, (et) # Load the stack pointer with the top value of the TCB
restore_context:
ldw ra, 0(sp) # Restore the registers.
# Leave a gap for muldiv 0.
ldw at, 8(sp)
ldw r2, 12(sp)
ldw r3, 16(sp)
ldw r4, 20(sp)
ldw r5, 24(sp)
ldw r6, 28(sp)
ldw r7, 32(sp)
ldw r8, 36(sp)
ldw r9, 40(sp)
ldw r10, 44(sp)
ldw r11, 48(sp)
ldw r12, 52(sp)
ldw r13, 56(sp)
ldw r14, 60(sp)
ldw r15, 64(sp)
ldw et, 68(sp) # Load the eStatus
wrctl estatus, et # Write the eStatus
ldw ea, 72(sp) # Load the Program Counter
ldw r16, 76(sp)
ldw r17, 80(sp)
ldw r18, 84(sp)
ldw r19, 88(sp)
ldw r20, 92(sp)
ldw r21, 96(sp)
ldw r22, 100(sp)
ldw r23, 104(sp)
ldw gp, 108(sp)
ldw fp, 112(sp)
addi sp, sp, 116 # Release stack space
eret # Return to address ea, loading eStatus into Status.
.section .exceptions.soft, "xa"
soft_exceptions:
movhi r3, 0x003b /* upper half of trap opcode */
ori r3, r3, 0x683a /* lower half of trap opcode */
beq r2, r3, call_scheduler
br exceptions_unknown_user # its something else
call_scheduler:
stw ea, 72(sp) # EA is PC+4 so will skip over instruction causing exception
movia r15, vTaskSwitchContext # Pick the next context - use long call version in place of "call"
callr r15
br restore_sp_from_pxCurrentTCB # Switch in the task context and restore.
.section .exceptions.unknown.user
exceptions_unknown_user:
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,671 | portable/CodeWarrior/ColdFire_V1/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
* supplied source files.
*/
.global ulPortSetIPL
.global _ulPortSetIPL
.global mcf5xxx_wr_cacrx
.global _mcf5xxx_wr_cacrx
.global vPortYieldISR
.global _vPortYieldISR
.global vPortStartFirstTask
.global _vPortStartFirstTask
.extern _pxCurrentTCB
.extern _vPortYieldHandler
.text
.macro portSAVE_CONTEXT
lea.l (-60, sp), sp
movem.l d0-a6, (sp)
move.l _pxCurrentTCB, a0
move.l sp, (a0)
.endm
.macro portRESTORE_CONTEXT
move.l _pxCurrentTCB, a0
move.l (a0), sp
movem.l (sp), d0-a6
lea.l (60, sp), sp
rte
.endm
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
ulPortSetIPL:
_ulPortSetIPL:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D6 /* prepare return value */
andi.l #0x0700,D6 /* mask out IPL */
lsr.l #8,D6 /* IPL */
andi.l #0x07,D0 /* least significant three bits */
lsl.l #8,D0 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D0,D7 /* place new IPL in sr */
move.w D7,SR
move.l D6, D0 /* Return value in D0. */
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
mcf5xxx_wr_cacrx:
_mcf5xxx_wr_cacrx:
move.l 4(sp),d0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
/********************************************************************/
/* Yield interrupt. */
_vPortYieldISR:
vPortYieldISR:
portSAVE_CONTEXT
jsr _vPortYieldHandler
portRESTORE_CONTEXT
/********************************************************************/
vPortStartFirstTask:
_vPortStartFirstTask:
portRESTORE_CONTEXT
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,665 | portable/CodeWarrior/ColdFire_V2/portasm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* Purpose: Lowest level routines for all ColdFire processors.
*
* Notes:
*
* ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
* supplied source files.
*/
.global ulPortSetIPL
.global _ulPortSetIPL
.global mcf5xxx_wr_cacrx
.global _mcf5xxx_wr_cacrx
.global vPortYieldISR
.global _vPortYieldISR
.global vPortStartFirstTask
.global _vPortStartFirstTask
.extern _pxCurrentTCB
.extern _vPortYieldHandler
.text
.macro portSAVE_CONTEXT
lea.l (-60, sp), sp
movem.l d0-a6, (sp)
move.l _pxCurrentTCB, a0
move.l sp, (a0)
.endm
.macro portRESTORE_CONTEXT
move.l _pxCurrentTCB, a0
move.l (a0), sp
movem.l (sp), d0-a6
lea.l (60, sp), sp
rte
.endm
/********************************************************************/
/*
* This routines changes the IPL to the value passed into the routine.
* It also returns the old IPL value back.
* Calling convention from C:
* old_ipl = asm_set_ipl(new_ipl);
* For the Diab Data C compiler, it passes return value thru D0.
* Note that only the least significant three bits of the passed
* value are used.
*/
ulPortSetIPL:
_ulPortSetIPL:
link A6,#-8
movem.l D6-D7,(SP)
move.w SR,D7 /* current sr */
move.l D7,D0 /* prepare return value */
andi.l #0x0700,D0 /* mask out IPL */
lsr.l #8,D0 /* IPL */
move.l 8(A6),D6 /* get argument */
andi.l #0x07,D6 /* least significant three bits */
lsl.l #8,D6 /* move over to make mask */
andi.l #0x0000F8FF,D7 /* zero out current IPL */
or.l D6,D7 /* place new IPL in sr */
move.w D7,SR
movem.l (SP),D6-D7
lea 8(SP),SP
unlk A6
rts
/********************************************************************/
mcf5xxx_wr_cacrx:
_mcf5xxx_wr_cacrx:
move.l 4(sp),d0
.long 0x4e7b0002 /* movec d0,cacr */
nop
rts
/********************************************************************/
/* Yield interrupt. */
_vPortYieldISR:
vPortYieldISR:
portSAVE_CONTEXT
jsr _vPortYieldHandler
portRESTORE_CONTEXT
/********************************************************************/
vPortStartFirstTask:
_vPortStartFirstTask:
portRESTORE_CONTEXT
.end
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,021 | portable/IAR/ARM_CM4F/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC vPortEnableVFP
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
isb
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r2, [r3]
/* Is the task using the FPU context? If so, push high vfp registers. */
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
/* Save the core registers. */
stmdb r0!, {r4-r11, r14}
/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
dsb
isb
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r0, r3}
/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
/* Is the task using the FPU context? If so, pop the high vfp registers
too. */
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
#if WORKAROUND_PMU_CM001 == 1
push { r14 }
pop { pc }
#endif
#endif
bx r14
/*-----------------------------------------------------------*/
vPortSVCHandler:
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
bx r14
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Clear the bit that indicates the FPU is in use in case the FPU was used
before the scheduler was started - which would otherwise result in the
unnecessary leaving of space in the SVC stack for lazy saving of FPU
registers. */
mov r0, #0
msr control, r0
/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
svc 0
/*-----------------------------------------------------------*/
vPortEnableVFP:
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,961 | portable/IAR/RX100/port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "PriorityDefinitions.h"
PUBLIC _prvStartFirstTask
PUBLIC ___interrupt_27
EXTERN _pxCurrentTCB
EXTERN _vTaskSwitchContext
RSEG CODE:CODE(4)
_prvStartFirstTask:
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
SETPSW U
/* Obtain the location of the stack associated with which ever task
pxCurrentTCB is currently pointing to. */
MOV.L #_pxCurrentTCB, R15
MOV.L [R15], R15
MOV.L [R15], R0
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15
/* R1 to R15 - R0 is not included as it is the SP. */
POPM R1-R15
/* This pops the remaining registers. */
RTE
NOP
NOP
/*-----------------------------------------------------------*/
/* The software interrupt - overwrite the default 'weak' definition. */
___interrupt_27:
/* Re-enable interrupts. */
SETPSW I
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
PUSH.L R15
/* Read the user stack pointer. */
MVFC USP, R15
/* Move the address down to the data being moved. */
SUB #12, R15
MVTC R15, USP
/* Copy the data across, R15, then PC, then PSW. */
MOV.L [ R0 ], [ R15 ]
MOV.L 4[ R0 ], 4[ R15 ]
MOV.L 8[ R0 ], 8[ R15 ]
/* Move the interrupt stack pointer to its new correct position. */
ADD #12, R0
/* All the rest of the registers are saved directly to the user stack. */
SETPSW U
/* Save the rest of the general registers (R15 has been saved already). */
PUSHM R1-R14
/* Save the accumulator. */
MVFACHI R15
PUSH.L R15
/* Middle word. */
MVFACMI R15
/* Shifted left as it is restored to the low order word. */
SHLL #16, R15
PUSH.L R15
/* Save the stack pointer to the TCB. */
MOV.L #_pxCurrentTCB, R15
MOV.L [ R15 ], R15
MOV.L R0, [ R15 ]
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
/* Select the next task to run. */
BSR.A _vTaskSwitchContext
/* Reset the interrupt mask as no more data structure access is required. */
MVTIPL #configKERNEL_INTERRUPT_PRIORITY
/* Load the stack pointer of the task that is now selected as the Running
state task from its TCB. */
MOV.L #_pxCurrentTCB,R15
MOV.L [ R15 ], R15
MOV.L [ R15 ], R0
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
POP R15
MVTACLO R15
POP R15
MVTACHI R15
POPM R1-R15
RTE
NOP
NOP
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 6,108 | portable/IAR/RXv2/port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "PriorityDefinitions.h"
PUBLIC _prvStartFirstTask
PUBLIC ___interrupt_27
EXTERN _pxCurrentTCB
EXTERN _vTaskSwitchContext
RSEG CODE:CODE(4)
_prvStartFirstTask:
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
SETPSW U
/* Obtain the location of the stack associated with which ever task
pxCurrentTCB is currently pointing to. */
MOV.L #_pxCurrentTCB, R15
MOV.L [R15], R15
MOV.L [R15], R0
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A0
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A0
POP R15
/* Accumulator guard. */
MVTACGU R15, A0
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A1
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A1
POP R15
/* Accumulator guard. */
MVTACGU R15, A1
POP R15
/* Floating point status word. */
MVTC R15, FPSW
/* R1 to R15 - R0 is not included as it is the SP. */
POPM R1-R15
/* This pops the remaining registers. */
RTE
NOP
NOP
/*-----------------------------------------------------------*/
/* The software interrupt - overwrite the default 'weak' definition. */
___interrupt_27:
/* Re-enable interrupts. */
SETPSW I
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
PUSH.L R15
/* Read the user stack pointer. */
MVFC USP, R15
/* Move the address down to the data being moved. */
SUB #12, R15
MVTC R15, USP
/* Copy the data across, R15, then PC, then PSW. */
MOV.L [ R0 ], [ R15 ]
MOV.L 4[ R0 ], 4[ R15 ]
MOV.L 8[ R0 ], 8[ R15 ]
/* Move the interrupt stack pointer to its new correct position. */
ADD #12, R0
/* All the rest of the registers are saved directly to the user stack. */
SETPSW U
/* Save the rest of the general registers (R15 has been saved already). */
PUSHM R1-R14
/* Save the FPSW and accumulator. */
MVFC FPSW, R15
PUSH.L R15
MVFACGU #0, A1, R15
PUSH.L R15
MVFACHI #0, A1, R15
PUSH.L R15
/* Low order word. */
MVFACLO #0, A1, R15
PUSH.L R15
MVFACGU #0, A0, R15
PUSH.L R15
MVFACHI #0, A0, R15
PUSH.L R15
/* Low order word. */
MVFACLO #0, A0, R15
PUSH.L R15
/* Save the stack pointer to the TCB. */
MOV.L #_pxCurrentTCB, R15
MOV.L [ R15 ], R15
MOV.L R0, [ R15 ]
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
/* Select the next task to run. */
BSR.A _vTaskSwitchContext
/* Reset the interrupt mask as no more data structure access is required. */
MVTIPL #configKERNEL_INTERRUPT_PRIORITY
/* Load the stack pointer of the task that is now selected as the Running
state task from its TCB. */
MOV.L #_pxCurrentTCB,R15
MOV.L [ R15 ], R15
MOV.L [ R15 ], R0
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A0
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A0
POP R15
/* Accumulator guard. */
MVTACGU R15, A0
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15, A1
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15, A1
POP R15
/* Accumulator guard. */
MVTACGU R15, A1
POP R15
MVTC R15, FPSW
POPM R1-R15
RTE
NOP
NOP
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 18,398 | portable/IAR/RISC-V/portASM.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
*
* + The code that is common to all RISC-V chips is implemented in
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
* portASM.S file because the same file is used no matter which RISC-V chip is
* in use.
*
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
* RISC-V chip that both includes a standard CLINT and does not add to the
* base set of RISC-V registers. There are additional
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
* that do not include a standard CLINT or do add to the base set of RISC-V
* registers.
*
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
* header file ensure the path to the correct header file is in the assembler's
* include path.
*
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
* that include a standard CLINT and do not add to the base set of RISC-V
* registers.
*
*/
#include "portContext.h"
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
definitions. */
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifdef portasmHAS_CLINT
#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#define portasmHAS_MTIME portasmHAS_CLINT
#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
#endif
#ifndef portasmHAS_MTIME
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
#endif
#ifndef portasmHAS_SIFIVE_CLINT
#define portasmHAS_SIFIVE_CLINT 0
#endif
/* CSR definitions. */
#define CSR_MSTATUS 0x300
#define CSR_MTVEC 0x305
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
PUBLIC xPortStartFirstTask
PUBLIC pxPortInitialiseStack
PUBLIC freertos_risc_v_trap_handler
PUBLIC freertos_risc_v_exception_handler
PUBLIC freertos_risc_v_interrupt_handler
PUBLIC freertos_risc_v_mtimer_interrupt_handler
EXTERN vTaskSwitchContext
EXTERN xTaskIncrementTick
EXTERN pullMachineTimerCompareRegister
EXTERN pullNextTime
EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
EXTERN xTaskReturnAddress
PUBWEAK freertos_risc_v_application_exception_handler
PUBWEAK freertos_risc_v_application_interrupt_handler
/*-----------------------------------------------------------*/
SECTION `.text`:CODE:NOROOT(2)
CODE
portUPDATE_MTIMER_COMPARE_REGISTER MACRO
load_x a0, pullMachineTimerCompareRegister /* Load address of compare register into a0. */
load_x a1, pullNextTime /* Load the address of ullNextTime into a1. */
#if( __riscv_xlen == 32 )
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
li a4, -1
lw a2, 0(a1) /* Load the low word of ullNextTime into a2. */
lw a3, 4(a1) /* Load the high word of ullNextTime into a3. */
sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwritten below. */
sw a3, 4(a0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
sw a2, 0(a0) /* Store low word of ullNextTime into compare register. */
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add a4, t0, a2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
sltu t1, a4, a2 /* See if the sum of low words overflowed (what about the zero case?). */
add t2, a3, t1 /* Add overflow to high word of ullNextTime. */
sw a4, 0(a1) /* Store new low word of ullNextTime. */
sw t2, 4(a1) /* Store new high word of ullNextTime. */
#endif /* __riscv_xlen == 32 */
#if( __riscv_xlen == 64 )
/* Update the 64-bit mtimer compare match value. */
ld t2, 0(a1) /* Load ullNextTime into t2. */
sd t2, 0(a0) /* Store ullNextTime into compare register. */
ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
sd t4, 0(a1) /* Store ullNextTime. */
#endif /* __riscv_xlen == 64 */
ENDM
/*-----------------------------------------------------------*/
/*
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
* for the function is as per the other ports:
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
*
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
*
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
*
* Register ABI Name Description Saver
* x0 zero Hard-wired zero -
* x1 ra Return address Caller
* x2 sp Stack pointer Callee
* x3 gp Global pointer -
* x4 tp Thread pointer -
* x5-7 t0-2 Temporaries Caller
* x8 s0/fp Saved register/Frame pointer Callee
* x9 s1 Saved register Callee
* x10-11 a0-1 Function Arguments/return values Caller
* x12-17 a2-7 Function arguments Caller
* x18-27 s2-11 Saved registers Callee
* x28-31 t3-6 Temporaries Caller
*
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
* where the global and thread pointers are currently assumed to be constant so
* are not saved:
*
* mstatus
* xCriticalNesting
* x31
* x30
* x29
* x28
* x27
* x26
* x25
* x24
* x23
* x22
* x21
* x20
* x19
* x18
* x17
* x16
* x15
* x14
* x13
* x12
* x11
* pvParameters
* x9
* x8
* x7
* x6
* x5
* portTASK_RETURN_ADDRESS
* [chip specific registers go here]
* pxCode
*/
pxPortInitialiseStack:
csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
slli t1, t1, 4
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
addi a0, a0, -portWORD_SIZE
store_x t0, 0(a0) /* mstatus onto the stack. */
addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
#ifdef __riscv_32e
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x10-15. */
#else
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x10-x31. */
#endif
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9 + taskReturnAddress. */
load_x t0, xTaskReturnAddress
store_x t0, 0(a0) /* Return address onto the stack. */
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
beq t0, x0, no_more_regs /* No more chip specific registers to save. */
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
j chip_specific_stack_frame /* Until no more chip specific registers. */
no_more_regs:
addi a0, a0, -portWORD_SIZE
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
ret
/*-----------------------------------------------------------*/
xPortStartFirstTask:
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
load_x sp, 0( sp ) /* Read sp from first TCB member. */
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
#ifndef __riscv_32e
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
#endif
load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
csrrw x0, CSR_MSTATUS, x5 /* Interrupts enabled from here! */
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
addi sp, sp, portCONTEXT_SIZE
ret
/*-----------------------------------------------------------*/
freertos_risc_v_application_exception_handler:
csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
csrr t1, CSR_MEPC /* For viewing in the debugger only */
csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
j $
/*-----------------------------------------------------------*/
freertos_risc_v_application_interrupt_handler:
csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
csrr t1, CSR_MEPC /* For viewing in the debugger only */
csrr t2, CSR_MSTATUS /* For viewing in the debugger only */
j $
/*-----------------------------------------------------------*/
SECTION `.text.freertos_risc_v_exception_handler`:CODE:NOROOT(2)
CODE
freertos_risc_v_exception_handler:
portcontextSAVE_EXCEPTION_CONTEXT
/* a0 now contains mcause. */
li t0, 11 /* 11 == environment call. */
bne a0, t0, other_exception /* Not an M environment call, so some other exception. */
call vTaskSwitchContext
portcontextRESTORE_CONTEXT
other_exception:
call freertos_risc_v_application_exception_handler
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
SECTION `.text.freertos_risc_v_interrupt_handler`:CODE:NOROOT(2)
CODE
freertos_risc_v_interrupt_handler:
portcontextSAVE_INTERRUPT_CONTEXT
call freertos_risc_v_application_interrupt_handler
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
SECTION `.text.freertos_risc_v_mtimer_interrupt_handler`:CODE:NOROOT(2)
CODE
freertos_risc_v_mtimer_interrupt_handler:
portcontextSAVE_INTERRUPT_CONTEXT
portUPDATE_MTIMER_COMPARE_REGISTER
call xTaskIncrementTick
beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
call vTaskSwitchContext
exit_without_context_switch:
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
SECTION `.text.freertos_risc_v_trap_handler`:CODE:NOROOT(8)
CODE
freertos_risc_v_trap_handler:
portcontextSAVE_CONTEXT_INTERNAL
csrr a0, CSR_MCAUSE
csrr a1, CSR_MEPC
bge a0, x0, synchronous_exception
asynchronous_interrupt:
store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
load_x sp, xISRStackTop /* Switch to ISR stack. */
j handle_interrupt
synchronous_exception:
addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
store_x a1, 0( sp ) /* Save updated exception return address. */
load_x sp, xISRStackTop /* Switch to ISR stack. */
j handle_exception
handle_interrupt:
#if( portasmHAS_MTIME != 0 )
test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
addi t0, x0, 1
slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
bne a0, t1, application_interrupt_handler
portUPDATE_MTIMER_COMPARE_REGISTER
call xTaskIncrementTick
beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
call vTaskSwitchContext
j processed_source
#endif /* portasmHAS_MTIME */
application_interrupt_handler:
call freertos_risc_v_application_interrupt_handler
j processed_source
handle_exception:
/* a0 contains mcause. */
li t0, 11 /* 11 == environment call. */
bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */
call vTaskSwitchContext
j processed_source
application_exception_handler:
call freertos_risc_v_application_exception_handler
j processed_source /* No other exceptions handled yet. */
processed_source:
portcontextRESTORE_CONTEXT
/*-----------------------------------------------------------*/
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 5,268 | portable/IAR/ARM_CA5_No_GIC/portASM.s | ;/*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
INCLUDE FreeRTOSConfig.h
INCLUDE portmacro.h
EXTERN vTaskSwitchContext
EXTERN ulPortYieldRequired
EXTERN ulPortInterruptNesting
EXTERN vApplicationIRQHandler
PUBLIC FreeRTOS_SWI_Handler
PUBLIC FreeRTOS_IRQ_Handler
PUBLIC vPortRestoreTaskContext
SYS_MODE EQU 0x1f
SVC_MODE EQU 0x13
IRQ_MODE EQU 0x12
SECTION .text:CODE:ROOT(2)
ARM
INCLUDE portASM.h
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; SVC handler is used to yield a task.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_SWI_Handler
PRESERVE8
; Save the context of the current task and select a new task to run.
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vPortRestoreTaskContext is used to start the scheduler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortRestoreTaskContext
PRESERVE8
; Switch to system mode
CPS #SYS_MODE
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; IRQ interrupt handler used when individual priorities cannot be masked
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_IRQ_Handler
PRESERVE8
; Return to the interrupted instruction.
SUB lr, lr, #4
; Push the return address and SPSR
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
; Change to supervisor mode to allow reentry.
CPS #SVC_MODE
; Push used registers.
PUSH {r0-r4, r12}
; Increment nesting count. r3 holds the address of ulPortInterruptNesting
; for future use. r1 holds the original ulPortInterruptNesting value for
; future use.
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use.
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
PUSH {r0-r4, lr}
; Call the port part specific handler.
LDR r0, =vApplicationIRQHandler
BLX r0
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
; Write to the EOI register.
LDR r4, =configEOI_ADDRESS
STR r0, [r4]
; Restore the old nesting count
STR r1, [r3]
; A context switch is never performed if the nesting count is not 0.
CMP r1, #0
BNE exit_without_switch
; Did the interrupt request a context switch? r1 holds the address of
; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
; use.
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch
; No context switch. Restore used registers, LR_irq and SPSR before
; returning.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit
; A context switch is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
; Restore used registers, LR-irq and SPSR before saving the context
; to the task stack.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
; Call the function that selects the new task to execute.
; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
; instructions, or 8 byte aligned stack allocated data. LR does not need
; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
LDR r0, =vTaskSwitchContext
BLX r0
; Restore the context of, and branch to, the task selected to execute next.
portRESTORE_CONTEXT
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 5,175 | portable/IAR/RX600/port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include "PriorityDefinitions.h"
PUBLIC _prvStartFirstTask
PUBLIC ___interrupt_27
EXTERN _pxCurrentTCB
EXTERN _vTaskSwitchContext
RSEG CODE:CODE(4)
_prvStartFirstTask:
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
SETPSW U
/* Obtain the location of the stack associated with which ever task
pxCurrentTCB is currently pointing to. */
MOV.L #_pxCurrentTCB, R15
MOV.L [R15], R15
MOV.L [R15], R0
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
POP R15
/* Accumulator low 32 bits. */
MVTACLO R15
POP R15
/* Accumulator high 32 bits. */
MVTACHI R15
POP R15
/* Floating point status word. */
MVTC R15, FPSW
/* R1 to R15 - R0 is not included as it is the SP. */
POPM R1-R15
/* This pops the remaining registers. */
RTE
NOP
NOP
/*-----------------------------------------------------------*/
/* The software interrupt - overwrite the default 'weak' definition. */
___interrupt_27:
/* Re-enable interrupts. */
SETPSW I
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
R15 is saved before it is clobbered. */
PUSH.L R15
/* Read the user stack pointer. */
MVFC USP, R15
/* Move the address down to the data being moved. */
SUB #12, R15
MVTC R15, USP
/* Copy the data across, R15, then PC, then PSW. */
MOV.L [ R0 ], [ R15 ]
MOV.L 4[ R0 ], 4[ R15 ]
MOV.L 8[ R0 ], 8[ R15 ]
/* Move the interrupt stack pointer to its new correct position. */
ADD #12, R0
/* All the rest of the registers are saved directly to the user stack. */
SETPSW U
/* Save the rest of the general registers (R15 has been saved already). */
PUSHM R1-R14
/* Save the FPSW and accumulator. */
MVFC FPSW, R15
PUSH.L R15
MVFACHI R15
PUSH.L R15
/* Middle word. */
MVFACMI R15
/* Shifted left as it is restored to the low order word. */
SHLL #16, R15
PUSH.L R15
/* Save the stack pointer to the TCB. */
MOV.L #_pxCurrentTCB, R15
MOV.L [ R15 ], R15
MOV.L R0, [ R15 ]
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
/* Select the next task to run. */
BSR.A _vTaskSwitchContext
/* Reset the interrupt mask as no more data structure access is required. */
MVTIPL #configKERNEL_INTERRUPT_PRIORITY
/* Load the stack pointer of the task that is now selected as the Running
state task from its TCB. */
MOV.L #_pxCurrentTCB,R15
MOV.L [ R15 ], R15
MOV.L [ R15 ], R0
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
POP R15
MVTACLO R15
POP R15
MVTACHI R15
POP R15
MVTC R15, FPSW
POPM R1-R15
RTE
NOP
NOP
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 5,557 | portable/IAR/ARM_CA9/portASM.s | ;/*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
INCLUDE FreeRTOSConfig.h
INCLUDE portmacro.h
EXTERN vApplicationIRQHandler
EXTERN vTaskSwitchContext
EXTERN ulPortYieldRequired
EXTERN ulPortInterruptNesting
PUBLIC FreeRTOS_SWI_Handler
PUBLIC FreeRTOS_IRQ_Handler
PUBLIC vPortRestoreTaskContext
SYS_MODE EQU 0x1f
SVC_MODE EQU 0x13
IRQ_MODE EQU 0x12
SECTION .text:CODE:ROOT(2)
ARM
INCLUDE portASM.h
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; SVC handler is used to yield a task.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_SWI_Handler
PRESERVE8
; Save the context of the current task and select a new task to run.
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; vPortRestoreTaskContext is used to start the scheduler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
vPortRestoreTaskContext
; Switch to system mode
CPS #SYS_MODE
portRESTORE_CONTEXT
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; PL390 GIC interrupt handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FreeRTOS_IRQ_Handler
; Return to the interrupted instruction.
SUB lr, lr, #4
; Push the return address and SPSR
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
; Change to supervisor mode to allow reentry.
CPS #SVC_MODE
; Push used registers.
PUSH {r0-r4, r12}
; Increment nesting count. r3 holds the address of ulPortInterruptNesting
; for future use. r1 holds the original ulPortInterruptNesting value for
; future use.
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
; Read value from the interrupt acknowledge register, which is stored in r0
; for future parameter and interrupt clearing use.
LDR r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS
LDR r0, [r2]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use. _RB_ Is this ever necessary if start of stack is 8-byte aligned?
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
; Call the interrupt handler. r4 is pushed to maintain alignment.
PUSH {r0-r4, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i
; Write the value read from ICCIAR to ICCEOIR
LDR r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS
STR r0, [r4]
; Restore the old nesting count
STR r1, [r3]
; A context switch is never performed if the nesting count is not 0
CMP r1, #0
BNE exit_without_switch
; Did the interrupt request a context switch? r1 holds the address of
; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
; use.
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch
; No context switch. Restore used registers, LR_irq and SPSR before
; returning.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit
; A context switch is to be performed. Clear the context switch pending
; flag.
MOV r0, #0
STR r0, [r1]
; Restore used registers, LR-irq and SPSR before saving the context
; to the task stack.
POP {r0-r4, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
; Call the function that selects the new task to execute.
; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
; instructions, or 8 byte aligned stack allocated data. LR does not need
; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
LDR r0, =vTaskSwitchContext
BLX r0
; Restore the context of, and branch to, the task selected to execute next.
portRESTORE_CONTEXT
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 7,083 | portable/IAR/ARM_CRx_No_GIC/portASM.s | ;/*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
#include "FreeRTOSConfig.h"
SECTION .text:CODE:ROOT(2)
arm
/* Variables and functions. */
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vApplicationIRQHandler
EXTERN ulPortInterruptNesting
EXTERN ulPortTaskHasFPUContext
EXTERN ulPortYieldRequired
EXTERN ulCriticalNesting
PUBLIC FreeRTOS_IRQ_Handler
PUBLIC FreeRTOS_SVC_Handler
PUBLIC vPortRestoreTaskContext
SYS_MODE EQU 0x1f
SVC_MODE EQU 0x13
IRQ_MODE EQU 0x12
portSAVE_CONTEXT MACRO
/* Save the LR and SPSR onto the system mode stack before switching to
system mode to save the remaining system mode registers. */
SRSDB sp!, #SYS_MODE
CPS #SYS_MODE
PUSH {R0-R12, R14}
/* Push the critical nesting count. */
LDR R2, =ulCriticalNesting
LDR R1, [R2]
PUSH {R1}
/* Does the task have a floating point context that needs saving? If
ulPortTaskHasFPUContext is 0 then no. */
LDR R2, =ulPortTaskHasFPUContext
LDR R3, [R2]
CMP R3, #0
/* Save the floating point context, if any. */
FMRXNE R1, FPSCR
VPUSHNE {D0-D15}
#if configFPU_D32 == 1
VPUSHNE {D16-D31}
#endif /* configFPU_D32 */
PUSHNE {R1}
/* Save ulPortTaskHasFPUContext itself. */
PUSH {R3}
/* Save the stack pointer in the TCB. */
LDR R0, =pxCurrentTCB
LDR R1, [R0]
STR SP, [R1]
ENDM
; /**********************************************************************/
portRESTORE_CONTEXT MACRO
/* Set the SP to point to the stack of the task being restored. */
LDR R0, =pxCurrentTCB
LDR R1, [R0]
LDR SP, [R1]
/* Is there a floating point context to restore? If the restored
ulPortTaskHasFPUContext is zero then no. */
LDR R0, =ulPortTaskHasFPUContext
POP {R1}
STR R1, [R0]
CMP R1, #0
/* Restore the floating point context, if any. */
POPNE {R0}
#if configFPU_D32 == 1
VPOPNE {D16-D31}
#endif /* configFPU_D32 */
VPOPNE {D0-D15}
VMSRNE FPSCR, R0
/* Restore the critical section nesting depth. */
LDR R0, =ulCriticalNesting
POP {R1}
STR R1, [R0]
/* Restore all system mode registers other than the SP (which is already
being used). */
POP {R0-R12, R14}
/* Return to the task code, loading CPSR on the way. */
RFEIA sp!
ENDM
/******************************************************************************
* SVC handler is used to yield.
*****************************************************************************/
FreeRTOS_SVC_Handler:
/* Save the context of the current task and select a new task to run. */
portSAVE_CONTEXT
LDR R0, =vTaskSwitchContext
BLX R0
portRESTORE_CONTEXT
/******************************************************************************
* vPortRestoreTaskContext is used to start the scheduler.
*****************************************************************************/
vPortRestoreTaskContext:
/* Switch to system mode. */
CPS #SYS_MODE
portRESTORE_CONTEXT
FreeRTOS_IRQ_Handler:
/* Return to the interrupted instruction. */
SUB lr, lr, #4
/* Push the return address and SPSR. */
PUSH {lr}
MRS lr, SPSR
PUSH {lr}
/* Change to supervisor mode to allow reentry. */
CPS #SVC_MODE
/* Push used registers. */
PUSH {r0-r3, r12}
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
for future use. r1 holds the original ulPortInterruptNesting value for
future use. */
LDR r3, =ulPortInterruptNesting
LDR r1, [r3]
ADD r0, r1, #1
STR r0, [r3]
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. */
MOV r0, sp
AND r2, r0, #4
SUB sp, sp, r2
/* Call the interrupt handler. */
PUSH {r0-r3, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r3, lr}
ADD sp, sp, r2
CPSID i
DSB
ISB
/* Write to the EOI register. */
LDR r2, =configEOI_ADDRESS
STR r0, [r2]
/* Restore the old nesting count. */
STR r1, [r3]
/* A context switch is never performed if the nesting count is not 0. */
CMP r1, #0
BNE exit_without_switch
/* Did the interrupt request a context switch? r1 holds the address of
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
use. */
LDR r1, =ulPortYieldRequired
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
exit_without_switch:
/* No context switch. Restore used registers, LR_irq and SPSR before
returning. */
POP {r0-r3, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
MOVS PC, LR
switch_before_exit:
/* A context swtich is to be performed. Clear the context switch pending
flag. */
MOV r0, #0
STR r0, [r1]
/* Restore used registers, LR-irq and SPSR before saving the context
to the task stack. */
POP {r0-r3, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
POP {LR}
portSAVE_CONTEXT
/* Call the function that selects the new task to execute.
vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
instructions, or 8 byte aligned stack allocated data. LR does not need
saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
LDR R0, =vTaskSwitchContext
BLX R0
/* Restore the context of, and branch to, the task selected to execute
next. */
portRESTORE_CONTEXT
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,534 | portable/IAR/ARM_CM0/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN vPortYieldFromISR
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC vSetMSP
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC ulSetInterruptMaskFromISR
PUBLIC vClearInterruptMaskFromISR
/*-----------------------------------------------------------*/
vSetMSP
msr msp, r0
bx lr
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
ldr r2, [r3]
subs r0, r0, #32 /* Make space for the remaining low registers. */
str r0, [r2] /* Save the new top of stack. */
stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
mov r4, r8 /* Store the high registers. */
mov r5, r9
mov r6, r10
mov r7, r11
stmia r0!, {r4-r7}
push {r3, r14}
cpsid i
bl vTaskSwitchContext
cpsie i
pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
ldr r1, [r2]
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
adds r0, r0, #16 /* Move to the high registers. */
ldmia r0!, {r4-r7} /* Pop the high registers. */
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
msr psp, r0 /* Remember the new top of stack for the task. */
subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */
ldmia r0!, {r4-r7} /* Pop low registers. */
bx r3
/*-----------------------------------------------------------*/
vPortSVCHandler;
/* This function is no longer used, but retained for backward
* compatibility. */
bx lr
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Don't reset the MSP stack as is done on CM3/4 devices. The vector table
* in some CM0 devices cannot be modified and thus may not hold the
* application's initial MSP value. */
ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
ldr r1, [r3]
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
movs r0, #2 /* Switch to the psp stack. */
msr CONTROL, r0
isb
pop {r0-r5} /* Pop the registers that are saved automatically. */
mov lr, r5 /* lr is now in r5. */
pop {r3} /* The return address is now in r3. */
pop {r2} /* Pop and discard the XPSR. */
cpsie i /* The first task has its context and interrupts can be enabled. */
bx r3 /* Jump to the user defined task code. */
/*-----------------------------------------------------------*/
ulSetInterruptMaskFromISR
mrs r0, PRIMASK
cpsid i
bx lr
/*-----------------------------------------------------------*/
vClearInterruptMaskFromISR
msr PRIMASK, r0
bx lr
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 12,822 | portable/IAR/ARM_CM4F_MPU/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include <FreeRTOSConfig.h>
#include <mpu_syscall_numbers.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC vPortEnableVFP
PUBLIC vPortRestoreContextOfFirstTask
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
/*-----------------------------------------------------------*/
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/* Errata 837070 workaround must be enabled on Cortex-M7 r0p0
* and r0p1 cores. */
#ifndef configENABLE_ERRATA_837070_WORKAROUND
#define configENABLE_ERRATA_837070_WORKAROUND 0
#endif
/* These must be in sync with portmacro.h. */
#define portSVC_START_SCHEDULER 100
#define portSVC_SYSTEM_CALL_EXIT 103
/*-----------------------------------------------------------*/
xPortPendSVHandler:
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
ldr r1, [r2] /* r1 = Location where the context should be saved. */
/*------------ Save Context. ----------- */
mrs r3, control
mrs r0, psp
isb
add r0, r0, #0x20 /* Move r0 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r0, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r0, r0, #0x20 /* Set r0 back to the location of hardware saved context. */
stmia r1!, {r3-r11, lr} /* Store CONTROL register, r4-r11 and LR. */
ldmia r0, {r4-r11} /* Copy hardware saved context into r4-r11. */
stmia r1!, {r0, r4-r11} /* Store original PSP (after hardware has saved context) and the hardware saved context. */
str r1, [r2] /* Save the location from where the context should be restored as the first member of TCB. */
/*---------- Select next task. --------- */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsid i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
msr basepri, r0
dsb
isb
#if ( configENABLE_ERRATA_837070_WORKAROUND == 1 )
cpsie i /* ARM Cortex-M7 r0p1 Errata 837070 workaround. */
#endif
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
/*------------ Program MPU. ------------ */
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r0] /* Read the value of MPU_CTRL. */
bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
str r3, [r0] /* Disable MPU. */
ldr r0, =0xe000ed9c /* Region Base Address register. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r0] /* Read the value of MPU_CTRL. */
orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
str r3, [r0] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
/*---------- Restore Context. ---------- */
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
ldr r1, [r2] /* r1 = Location of saved context in TCB. */
ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
msr psp, r0
stmia r0!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
msr control, r3
tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r0!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
/*-----------------------------------------------------------*/
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
vPortSVCHandler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #portSVC_SYSTEM_CALL_EXIT
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
vPortSVCHandler:
#ifndef USE_PROCESS_STACK
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
#else
mrs r0, psp
#endif
b vPortSVCHandler_C
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortStartFirstTask:
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Clear the bit that indicates the FPU is in use in case the FPU was used
before the scheduler was started - which would otherwise result in the
unnecessary leaving of space in the SVC stack for lazy saving of FPU
registers. */
mov r0, #0
msr control, r0
/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
svc #portSVC_START_SCHEDULER
/*-----------------------------------------------------------*/
vPortRestoreContextOfFirstTask:
ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0]
ldr r0, [r0]
msr msp, r0 /* Set the msp back to the start of the stack. */
/*------------ Program MPU. ------------ */
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
add r2, r2, #4 /* r2 = Second item in the TCB which is xMPUSettings. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r0] /* Read the value of MPU_CTRL. */
bic r3, #1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
str r3, [r0] /* Disable MPU. */
ldr r0, =0xe000ed9c /* Region Base Address register. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 0 - 3]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 0 - 3]. */
#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 4 - 7]. */
ldmia r2!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
stmia r0, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif
ldr r0, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r0] /* Read the value of MPU_CTRL. */
orr r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
str r3, [r0] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
/*---------- Restore Context. ---------- */
ldr r3, =pxCurrentTCB
ldr r2, [r3] /* r2 = pxCurrentTCB. */
ldr r1, [r2] /* r1 = Location of saved context in TCB. */
ldmdb r1!, {r0, r4-r11} /* r0 contains PSP after the hardware had saved context. r4-r11 contain hardware saved context. */
msr psp, r0
stmia r0, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r3-r11, lr} /* r3 contains CONTROL register. r4-r11 and LR restored. */
msr control, r3
str r1, [r2] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0
bx lr
/*-----------------------------------------------------------*/
vPortEnableVFP:
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,823 | portable/IAR/ARM_CM4F_MPU/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
* contains code not understood by the assembler - for example the 'extern' keyword.
* To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
* the code is included in C files but excluded by the preprocessor in assembly
* files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( configUSE_MPU_WRAPPERS_V1 == 0 )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,685 | portable/IAR/RL78/portasm.s | ;/*
; * FreeRTOS Kernel <DEVELOPMENT BRANCH>
; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
; *
; * SPDX-License-Identifier: MIT
; *
; * Permission is hereby granted, free of charge, to any person obtaining a copy of
; * this software and associated documentation files (the "Software"), to deal in
; * the Software without restriction, including without limitation the rights to
; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
; * the Software, and to permit persons to whom the Software is furnished to do so,
; * subject to the following conditions:
; *
; * The above copyright notice and this permission notice shall be included in all
; * copies or substantial portions of the Software.
; *
; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
; *
; * https://www.FreeRTOS.org
; * https://github.com/FreeRTOS
; *
; */
#include "portmacro.h"
EXTERN _vTaskSwitchContext
EXTERN _xTaskIncrementTick
EXTERN _interrupt_vector_table
PUBLIC _vPortYield
PUBLIC _vPortStartFirstTask
PUBLIC _vPortTickISR
#if !defined(__IASMRL78__) || (__VER__ < 310)
#error "This port requires the IAR Assembler for RL78 version 3.10 or later."
#endif
;-------------------------------------------------------------------------------
; FreeRTOS yield handler. This is installed as the BRK software interrupt
; handler.
;-------------------------------------------------------------------------------
SECTION `.text`:CODE:ROOT(1)
_vPortYield:
portSAVE_CONTEXT ; Save the context of the current task.
RCALL (_vTaskSwitchContext) ; Call the scheduler to select the next task.
portRESTORE_CONTEXT ; Restore the context of the next task to run.
RETB
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; Starts the scheduler by restoring the context of the task that will execute
; first.
;-------------------------------------------------------------------------------
SECTION `.text`:CODE:ROOT(1)
_vPortStartFirstTask:
portRESTORE_CONTEXT ; Restore the context of whichever task the ...
RETI ; An interrupt stack frame is used so the
; task is started using a RETI instruction.
;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------
; FreeRTOS Timer Tick handler.
; This is installed as the interval timer interrupt handler.
;-------------------------------------------------------------------------------
SECTION `.text`:CODE:ROOT(1)
_vPortTickISR:
portSAVE_CONTEXT ; Save the context of the current task.
RCALL (_xTaskIncrementTick) ; Call the timer tick function.
CMPW AX, #0x00
SKZ
RCALL (_vTaskSwitchContext) ; Call the scheduler to select the next task.
portRESTORE_CONTEXT ; Restore the context of the next task to run.
RETI
;-------------------------------------------------------------------------------
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,052 | portable/IAR/ARM_CM3/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
isb
ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
ldr r2, [r3]
stmdb r0!, {r4-r11} /* Save the remaining registers. */
str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
stmdb sp!, {r3, r14}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
dsb
isb
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r3, r14}
ldr r1, [r3]
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
ldmia r0!, {r4-r11} /* Pop the registers. */
msr psp, r0
isb
bx r14
/*-----------------------------------------------------------*/
vPortSVCHandler:
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
orr r14, r14, #13
bx r14
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Call SVC to start the first task, ensuring interrupts are enabled. */
cpsie i
cpsie f
dsb
isb
svc 0
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 20,049 | portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs_first_task:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
mrs r2, psplim /* r2 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
msr psp, r0 /* Remember the new top of stack for the task. */
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 22,503 | portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
#ifndef configRUN_FREERTOS_SECURE_ONLY
#define configRUN_FREERTOS_SECURE_ONLY 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
#if ( configENABLE_FPU == 1 )
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
#endif
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
beq running_privileged /* If the result of previous AND operation was 0, branch. */
movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
bx lr /* Return. */
running_privileged:
movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
orrs r0, r1 /* r0 = r0 | r1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
subs r1, #16
ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
subs r1, #16
msr psp, r2
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r3
#endif
msr control, r4
mov lr, r5
restore_general_regs_first_task:
subs r1, #32
ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r1, #48
ldmia r1!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r1, #32
ldmia r1!, {r4-r7} /* Restore r4-r7. */
subs r1, #16
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r1 /* Set this task's PSPLIM value. */
#endif
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
movs r1, #1 /* r1 = 1. */
bics r0, r1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
nop
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, PRIMASK
cpsid i
bx lr
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr PRIMASK, r0
bx lr
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
stmia r1!, {r4-r7} /* Store r4-r7. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r1!, {r4-r7} /* Store r8-r11. */
ldmia r2!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */
stmia r1!, {r4-r7} /* Store the hardware saved context. */
ldmia r2!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */
stmia r1!, {r4-r7} /* Store the hardware saved context. */
save_special_regs:
mrs r2, psp /* r2 = PSP. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
mrs r3, psplim /* r3 = PSPLIM. */
#else
movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */
#endif
mrs r4, control /* r4 = CONTROL. */
mov r5, lr /* r5 = LR. */
stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
cpsid i
bl vTaskSwitchContext
cpsie i
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
subs r1, #16
ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
subs r1, #16
msr psp, r2
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r3
#endif
msr control, r4
mov lr, r5
restore_general_regs:
subs r1, #32
ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r1, #48
ldmia r1!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r1, #32
ldmia r1!, {r4-r7} /* Restore r4-r7. */
subs r1, #16
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */
str r0, [r1] /* Save the new top of stack in TCB. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
mrs r2, psplim /* r2 = PSPLIM. */
#else
movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */
#endif
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */
cpsid i
bl vTaskSwitchContext
cpsie i
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
adds r0, r0, #24 /* Move to the high registers. */
ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
msr psp, r0 /* Remember the new top of stack for the task. */
subs r0, r0, #40 /* Move to the starting of the saved context. */
ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
#endif
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stack_on_msp
stack_on_psp:
mrs r0, psp
b route_svc
stack_on_msp:
mrs r0, msp
b route_svc
route_svc:
ldr r3, [r0, #24]
subs r3, #2
ldrb r2, [r3, #0]
cmp r2, #NUM_SYSTEM_CALLS
blt system_call_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq system_call_exit
b vPortSVCHandler_C
system_call_enter:
b vSystemCallEnter
system_call_exit:
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stacking_used_msp
mrs r0, psp
b vPortSVCHandler_C
stacking_used_msp:
mrs r0, msp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 40,430 | portable/IAR/ARM_CM23_NTZ/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0, r1}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0, r1}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0, r1}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0, r1}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0, r1}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0, r1}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0, r1}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0, r1}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0, r1}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0, r1}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0, r1}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0, r1}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0, r1}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0, r1}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0, r1}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0, r1}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0, r1}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0, r1}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0, r1}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0, r1}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0, r1}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0, r1}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0, r1}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0, r1}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0, r1}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0, r1}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0, r1}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0, r1}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0, r1}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0, r1}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0, r1}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0, r1}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0, r1}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0, r1}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0, r1}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0, r1}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0, r1}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0, r1}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0, r1}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0, r1}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0, r1}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0, r1}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0, r1}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0, r1}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0, r1}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 20,049 | portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs_first_task:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
mrs r2, psplim /* r2 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
msr psp, r0 /* Remember the new top of stack for the task. */
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM35P_NTZ/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,082 | portable/IAR/ARM_CM23/secure/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
#if ( configENABLE_FPU == 1 )
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
#endif
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
stmia r1!, {r2} /* Store CONTROL value on the stack. */
#else /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
#endif /* configENABLE_MPU */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 28,629 | portable/IAR/ARM_CM23/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
#if ( configENABLE_FPU == 1 )
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
#endif
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
beq running_privileged /* If the result of previous AND operation was 0, branch. */
movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
bx lr /* Return. */
running_privileged:
movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
orrs r0, r1 /* r0 = r0 | r1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
subs r2, #20
ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
subs r2, #20
msr psp, r3
msr control, r5
mov lr, r6
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
subs r2, #32
ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r2, #48
ldmia r2!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r2, #32
ldmia r2!, {r4-r7} /* Restore r4-r7. */
subs r2, #16
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
movs r1, #1 /* r1 = 1. */
bics r0, r1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, PRIMASK
cpsid i
bx lr
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr PRIMASK, r0
bx lr
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* Restore LR. */
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
stmia r2!, {r4-r7} /* Store r4-r7. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r2!, {r4-r7} /* Store r8-r11. */
ldmia r3!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */
stmia r2!, {r4-r7} /* Store the hardware saved context. */
ldmia r3!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */
stmia r2!, {r4-r7} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */
mrs r5, control /* r5 = CONTROL. */
mov r6, lr /* r6 = LR. */
stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
cpsid i
bl vTaskSwitchContext
cpsie i
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
subs r2, #20
ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
subs r2, #20
msr psp, r3
msr control, r5
mov lr, r6
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r4} /* LR is now in r4. */
mov lr, r4
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
subs r2, #32
ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r2, #48
ldmia r2!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r2, #32
ldmia r2!, {r4-r7} /* Restore r4-r7. */
subs r2, #16
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */
select_next_task:
cpsid i
bl vTaskSwitchContext
cpsie i
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
adds r2, r2, #16 /* Move to the high registers. */
ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
msr psp, r2 /* Remember the new top of stack for the task. */
subs r2, r2, #32 /* Go back to the low registers. */
ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stack_on_msp
stack_on_psp:
mrs r0, psp
b route_svc
stack_on_msp:
mrs r0, msp
b route_svc
route_svc:
ldr r3, [r0, #24]
subs r3, #2
ldrb r2, [r3, #0]
cmp r2, #NUM_SYSTEM_CALLS
blt system_call_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq system_call_exit
b vPortSVCHandler_C
system_call_enter:
b vSystemCallEnter
system_call_exit:
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stacking_used_msp
mrs r0, psp
b vPortSVCHandler_C
stacking_used_msp:
mrs r0, msp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
bne free_secure_context /* Branch if r1 != 0. */
bx lr /* There is no secure context (xSecureContext is NULL). */
free_secure_context:
svc 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 40,430 | portable/IAR/ARM_CM23/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0, r1}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0, r1}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0, r1}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0, r1}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0, r1}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0, r1}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0, r1}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0, r1}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0, r1}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0, r1}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0, r1}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0, r1}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0, r1}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0, r1}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0, r1}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0, r1}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0, r1}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0, r1}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0, r1}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0, r1}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0, r1}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0, r1}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0, r1}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0, r1}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0, r1}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0, r1}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0, r1}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0, r1}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0, r1}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0, r1}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0, r1}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0, r1}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0, r1}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0, r1}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0, r1}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0, r1}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0, r1}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0, r1}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0, r1}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0, r1}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0, r1}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0, r1}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0, r1}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0, r1}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0, r1}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 20,049 | portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs_first_task:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
mrs r2, psplim /* r2 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
msr psp, r0 /* Remember the new top of stack for the task. */
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,055 | portable/IAR/ARM_CM35P/secure/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
stmdb r1!, {r2} /* Store CONTROL value on the stack. */
#endif /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 27,033 | portable/IAR/ARM_CM35P/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r2, lr}
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r2!, {s16-s31} /* Store s16-s31. */
vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */
sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r2!, {r4-r11} /* Store r4-r11. */
ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r2!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r3, lr}
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
adds r2, r2, #12 /* r2 = r2 + 12. */
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
subs r2, r2, #12 /* r2 = r2 - 12. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
/* r0 = uint32_t *pulTCB. */
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
it ne
svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM35P/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 20,049 | portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs_first_task:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
msr psplim, r1 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r2, r2, #0x20 /* Move r2 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r1!, {s16-s31} /* Store s16-s31. */
vldmiaeq r2, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r1!, {s0-s16} /* Store hardware saved FP context. */
sub r2, r2, #0x20 /* Set r2 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r1!, {r4-r11} /* Store r4-r11. */
ldmia r2, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r1!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psplim /* r3 = PSPLIM. */
mrs r4, control /* r4 = CONTROL. */
stmia r1!, {r2-r4, lr} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r1!, {r2-r4, lr} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
msr psp, r2
msr psplim, r3
msr control, r4
restore_general_regs:
ldmdb r1!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r2!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r1!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r1!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r2!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r1!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r0!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
mrs r2, psplim /* r2 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmdb r0!, {r2-r11} /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
str r0, [r1] /* Save the new top of stack in TCB. */
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
ldmia r0!, {r2-r11} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst r3, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r0!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
msr psp, r0 /* Remember the new top of stack for the task. */
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,055 | portable/IAR/ARM_CM55/secure/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
stmdb r1!, {r2} /* Store CONTROL value on the stack. */
#endif /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 27,033 | portable/IAR/ARM_CM55/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r2, lr}
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r2!, {s16-s31} /* Store s16-s31. */
vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */
sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r2!, {r4-r11} /* Store r4-r11. */
ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r2!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r3, lr}
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
adds r2, r2, #12 /* r2 = r2 + 12. */
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
subs r2, r2, #12 /* r2 = r2 - 12. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
/* r0 = uint32_t *pulTCB. */
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
it ne
svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM55/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,045 | portable/IAR/ARM_CM7/r0p1/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include <FreeRTOSConfig.h>
RSEG CODE:CODE(2)
thumb
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
PUBLIC xPortPendSVHandler
PUBLIC vPortSVCHandler
PUBLIC vPortStartFirstTask
PUBLIC vPortEnableVFP
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
isb
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r2, [r3]
/* Is the task using the FPU context? If so, push high vfp registers. */
tst r14, #0x10
it eq
vstmdbeq r0!, {s16-s31}
/* Save the core registers. */
stmdb r0!, {r4-r11, r14}
/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
stmdb sp!, {r0, r3}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
cpsid i
msr basepri, r0
dsb
isb
cpsie i
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r0, r3}
/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
/* Is the task using the FPU context? If so, pop the high vfp registers
too. */
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
isb
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
#if WORKAROUND_PMU_CM001 == 1
push { r14 }
pop { pc }
#endif
#endif
bx r14
/*-----------------------------------------------------------*/
vPortSVCHandler:
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
msr psp, r0
isb
mov r0, #0
msr basepri, r0
bx r14
/*-----------------------------------------------------------*/
vPortStartFirstTask
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Clear the bit that indicates the FPU is in use in case the FPU was used
before the scheduler was started - which would otherwise result in the
unnecessary leaving of space in the SVC stack for lazy saving of FPU
registers. */
mov r0, #0
msr control, r0
/* Call SVC to start the first task. */
cpsie i
cpsie f
dsb
isb
svc 0
/*-----------------------------------------------------------*/
vPortEnableVFP:
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,055 | portable/IAR/ARM_CM85/secure/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
stmdb r1!, {r2} /* Store CONTROL value on the stack. */
#endif /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 27,033 | portable/IAR/ARM_CM85/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r2, lr}
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r2!, {s16-s31} /* Store s16-s31. */
vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */
sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r2!, {r4-r11} /* Store r4-r11. */
ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r2!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r3, lr}
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
adds r2, r2, #12 /* r2 = r2 + 12. */
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
subs r2, r2, #12 /* r2 = r2 - 12. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
/* r0 = uint32_t *pulTCB. */
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
it ne
svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM85/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,055 | portable/IAR/ARM_CM33/secure/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
stmdb r1!, {r2} /* Store CONTROL value on the stack. */
#endif /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 27,033 | portable/IAR/ARM_CM33/non_secure/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
ite ne
movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
orr r0, r0, #1 /* r0 = r0 | 1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB. */
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 set of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
msr psplim, r2 /* Set this task's PSPLIM value. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
mov r0, #0
msr basepri, r0 /* Ensure that interrupts are enabled when the first task starts. */
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
bic r0, r0, #1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
cpsie f
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, basepri /* r0 = basepri. Return original basepri value. */
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr basepri, r0 /* basepri = ulMask. */
dsb
isb
bx lr /* Return. */
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r2, lr}
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
add r3, r3, #0x20 /* Move r3 to location where s0 is saved. */
tst lr, #0x10
ittt eq
vstmiaeq r2!, {s16-s31} /* Store s16-s31. */
vldmiaeq r3, {s0-s16} /* Copy hardware saved FP context into s0-s16. */
vstmiaeq r2!, {s0-s16} /* Store hardware saved FP context. */
sub r3, r3, #0x20 /* Set r3 back to the location of hardware saved context. */
#endif /* configENABLE_FPU || configENABLE_MVE */
stmia r2!, {r4-r11} /* Store r4-r11. */
ldmia r3, {r4-r11} /* Copy the hardware saved context into r4-r11. */
stmia r2!, {r4-r11} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
mrs r4, psplim /* r4 = PSPLIM. */
mrs r5, control /* r5 = CONTROL. */
stmia r2!, {r0, r3-r5, lr} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
bic r2, #1 /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#if ( configTOTAL_MPU_REGIONS == 16 )
movs r3, #8 /* r3 = 8. */
str r3, [r1] /* Program RNR = 8. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
movs r3, #12 /* r3 = 12. */
str r3, [r1] /* Program RNR = 12. */
ldmia r0!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
stmia r2, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
#endif /* configTOTAL_MPU_REGIONS == 16 */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
orr r2, #1 /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
ldmdb r2!, {r0, r3-r5, lr} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
msr psp, r3
msr psplim, r4
msr control, r5
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r3, lr}
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
ldmdb r2!, {r4-r11} /* r4-r11 contain hardware saved context. */
stmia r3!, {r4-r11} /* Copy the hardware saved context on the task stack. */
ldmdb r2!, {r4-r11} /* r4-r11 restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10
ittt eq
vldmdbeq r2!, {s0-s16} /* s0-s16 contain hardware saved FP context. */
vstmiaeq r3!, {s0-s16} /* Copy hardware saved FP context on the task stack. */
vldmdbeq r2!, {s16-s31} /* Restore s16-s31. */
#endif /* configENABLE_FPU || configENABLE_MVE */
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vstmdbeq r2!, {s16-s31} /* Store the additional FP context registers which are not saved automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
adds r2, r2, #12 /* r2 = r2 + 12. */
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
mrs r1, psplim /* r1 = PSPLIM. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
subs r2, r2, #12 /* r2 = r2 - 12. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
select_next_task:
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
dsb
isb
bl vTaskSwitchContext
mov r0, #0 /* r0 = 0. */
msr basepri, r0 /* Enable interrupts. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
it eq
vldmiaeq r2!, {s16-s31} /* Restore the additional FP context registers which are not restored automatically. */
#endif /* configENABLE_FPU || configENABLE_MVE */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
ldr r1, [r0, #24]
ldrb r2, [r1, #-2]
cmp r2, #NUM_SYSTEM_CALLS
blt syscall_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq syscall_exit
b vPortSVCHandler_C
syscall_enter:
mov r1, lr
b vSystemCallEnter
syscall_exit:
mov r1, lr
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
tst lr, #4
ite eq
mrseq r0, msp
mrsne r0, psp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
/* r0 = uint32_t *pulTCB. */
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
it ne
svcne 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 38,470 | portable/IAR/ARM_CM33/non_secure/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0}
mrs r0, control
tst r0, #1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 7,724 | portable/MPLAB/PIC32MX/port_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include <xc.h>
#include <sys/asm.h>
#include "ISR_Support.h"
.set nomips16
.set noreorder
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vPortIncrementTick
.extern xISRStackTop
.global vPortStartFirstTask
.global vPortYieldISR
.global vPortTickInterruptHandler
/******************************************************************/
.set noreorder
.set noat
.ent vPortTickInterruptHandler
vPortTickInterruptHandler:
portSAVE_CONTEXT
jal vPortIncrementTick
nop
portRESTORE_CONTEXT
.end vPortTickInterruptHandler
/******************************************************************/
.set noreorder
.set noat
.ent vPortStartFirstTask
vPortStartFirstTask:
/* Simply restore the context of the highest priority task that has been
created so far. */
portRESTORE_CONTEXT
.end vPortStartFirstTask
/*******************************************************************/
.set noreorder
.set noat
.ent vPortYieldISR
vPortYieldISR:
/* Make room for the context. First save the current status so it can be
manipulated. */
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Prepare to re-enabled interrupt above the kernel priority. */
ins k1, zero, 10, 6
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
ins k1, zero, 1, 4
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved across
nesting interrupts. */
mfhi s7
sw s7, 12(s5)
mflo s7
sw s7, 8(s5)
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API. The
yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
raise the IPL value and never lower it. */
di
ehb
mfc0 s7, _CP0_STATUS
ins s7, zero, 10, 6
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
ehb
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
ins s6, zero, 8, 1
mtc0 s6, _CP0_CAUSE
ehb
/* Clear the interrupt in the interrupt controller. */
la s6, IFS0CLR
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7. */
mtc0 s7, _CP0_STATUS
ehb
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Restore the rest of the context. */
lw s0, 8(s5)
mtlo s0
lw s0, 12(s5)
mthi s0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
mtc0 k1, _CP0_STATUS
mtc0 k0, _CP0_EPC
ehb
eret
nop
.end vPortYieldISR
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 24,060 | portable/MPLAB/PIC32MZ/port_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#include <xc.h>
#include <sys/asm.h>
#include "FreeRTOSConfig.h"
#include "ISR_Support.h"
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vPortIncrementTick
.extern xISRStackTop
.extern ulTaskHasFPUContext
.global vPortStartFirstTask
.global vPortYieldISR
.global vPortTickInterruptHandler
.global vPortInitialiseFPSCR
/******************************************************************/
.set nomips16
.set nomicromips
.set noreorder
.set noat
/***************************************************************
* The following is needed to locate the
* vPortTickInterruptHandler function into the correct vector
***************************************************************/
#ifdef configTICK_INTERRUPT_VECTOR
#if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)
.equ __vector_dispatch_0, vPortTickInterruptHandler
.global __vector_dispatch_0
.section .vector_0, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)
.equ __vector_dispatch_4, vPortTickInterruptHandler
.global __vector_dispatch_4
.section .vector_4, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)
.equ __vector_dispatch_9, vPortTickInterruptHandler
.global __vector_dispatch_9
.section .vector_9, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)
.equ __vector_dispatch_14, vPortTickInterruptHandler
.global __vector_dispatch_14
.section .vector_14, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)
.equ __vector_dispatch_19, vPortTickInterruptHandler
.global __vector_dispatch_19
.section .vector_19, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)
.equ __vector_dispatch_24, vPortTickInterruptHandler
.global __vector_dispatch_24
.section .vector_24, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)
.equ __vector_dispatch_28, vPortTickInterruptHandler
.global __vector_dispatch_28
.section .vector_28, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)
.equ __vector_dispatch_32, vPortTickInterruptHandler
.global __vector_dispatch_32
.section .vector_32, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)
.equ __vector_dispatch_36, vPortTickInterruptHandler
.global __vector_dispatch_36
.section .vector_36, code, keep
#elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)
.equ __vector_dispatch_40, vPortTickInterruptHandler
.global __vector_dispatch_40
.section .vector_40, code, keep
#endif
#else
.equ __vector_dispatch_4, vPortTickInterruptHandler
.global __vector_dispatch_4
.section .vector_4, code, keep
#endif
.ent vPortTickInterruptHandler
vPortTickInterruptHandler:
portSAVE_CONTEXT
jal vPortIncrementTick
nop
portRESTORE_CONTEXT
.end vPortTickInterruptHandler
/******************************************************************/
.set noreorder
.set noat
.section .text, code
.ent vPortStartFirstTask
vPortStartFirstTask:
/* Simply restore the context of the highest priority task that has been
created so far. */
portRESTORE_CONTEXT
.end vPortStartFirstTask
/*******************************************************************/
.set nomips16
.set nomicromips
.set noreorder
.set noat
/***************************************************************
* The following is needed to locate the vPortYieldISR function
* into the correct vector
***************************************************************/
.equ __vector_dispatch_1, vPortYieldISR
.global __vector_dispatch_1
.section .vector_1, code
.ent vPortYieldISR
vPortYieldISR:
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/* Code sequence for FPU support, the context save requires advance
knowledge of the stack frame size and if the current task actually uses the
FPU. */
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so their original values are
captured. */
la k0, ulTaskHasFPUContext
lw k0, 0(k0)
beq k0, zero, 1f
addiu sp, sp, -portCONTEXT_SIZE /* always reserve space for the context. */
addiu sp, sp, -portFPU_CONTEXT_SIZE /* reserve additional space for the FPU context. */
1:
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
sw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
/* Prepare to re-enabled interrupts above the kernel priority. */
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved across
nesting interrupts. */
/* Save the AC0, AC1, AC2 and AC3. */
mfhi s7, $ac1
sw s7, 128(s5)
mflo s7, $ac1
sw s7, 124(s5)
mfhi s7, $ac2
sw s7, 136(s5)
mflo s7, $ac2
sw s7, 132(s5)
mfhi s7, $ac3
sw s7, 144(s5)
mflo s7, $ac3
sw s7, 140(s5)
rddsp s7
sw s7, 148(s5)
mfhi s7, $ac0
sw s7, 12(s5)
mflo s7, $ac0
sw s7, 8(s5)
/* Test if FPU context save is required. */
lw s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
beq s7, zero, 1f
nop
/* Save the FPU registers above the normal context. */
portSAVE_FPU_REGS (portCONTEXT_SIZE + 8), s5
/* Save the FPU status register */
cfc1 s7, $f31
sw s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
1:
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API. The
yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
raise the IPL value and never lower it. */
di
ehb
mfc0 s7, _CP0_STATUS
ins s7, zero, 10, 7
ins s7, zero, 18, 1
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
ehb
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
ins s6, zero, 8, 1
mtc0 s6, _CP0_CAUSE
ehb
/* Clear the interrupt in the interrupt controller. */
la s6, IFS0CLR
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7. */
mtc0 s7, _CP0_STATUS
ehb
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Test if the FPU context needs restoring. */
lw s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
beq s0, zero, 1f
nop
/* Restore the FPU status register. */
lw s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
ctc1 s0, $f31
/* Restore the FPU registers. */
portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
1:
/* Restore the rest of the context. */
lw s0, 128(s5)
mthi s0, $ac1
lw s0, 124(s5)
mtlo s0, $ac1
lw s0, 136(s5)
mthi s0, $ac2
lw s0, 132(s5)
mtlo s0, $ac2
lw s0, 144(s5)
mthi s0, $ac3
lw s0, 140(s5)
mtlo s0, $ac3
lw s0, 148(s5)
wrdsp s0
lw s0, 8(s5)
mtlo s0, $ac0
lw s0, 12(s5)
mthi s0, $ac0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the FPU context value from the stack */
lw k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
la k1, ulTaskHasFPUContext
sw k0, 0(k1)
beq k0, zero, 1f
nop
/* task has FPU context so adjust the stack frame after popping the
status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
addiu sp, sp, portFPU_CONTEXT_SIZE
beq zero, zero, 2f
nop
1:
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
2:
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
#else
/* Code sequence for no FPU support, the context save requires advance
knowledge of the stack frame size when no FPU is being used */
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so thier original values are
captured. */
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Prepare to re-enabled interrupts above the kernel priority. */
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
ins k1, zero, 18, 1 /* Clear IPL bit 7. It would be an error here if this bit were set anyway. */
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved across
nesting interrupts. */
/* Save the AC0, AC1, AC2 and AC3. */
mfhi s7, $ac1
sw s7, 128(s5)
mflo s7, $ac1
sw s7, 124(s5)
mfhi s7, $ac2
sw s7, 136(s5)
mflo s7, $ac2
sw s7, 132(s5)
mfhi s7, $ac3
sw s7, 144(s5)
mflo s7, $ac3
sw s7, 140(s5)
rddsp s7
sw s7, 148(s5)
mfhi s7, $ac0
sw s7, 12(s5)
mflo s7, $ac0
sw s7, 8(s5)
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API. The
yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
raise the IPL value and never lower it. */
di
ehb
mfc0 s7, _CP0_STATUS
ins s7, zero, 10, 7
ins s7, zero, 18, 1
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
ehb
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
ins s6, zero, 8, 1
mtc0 s6, _CP0_CAUSE
ehb
/* Clear the interrupt in the interrupt controller. */
la s6, IFS0CLR
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7. */
mtc0 s7, _CP0_STATUS
ehb
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Restore the rest of the context. */
lw s0, 128(s5)
mthi s0, $ac1
lw s0, 124(s5)
mtlo s0, $ac1
lw s0, 136(s5)
mthi s0, $ac2
lw s0, 132(s5)
mtlo s0, $ac2
lw s0, 144(s5)
mthi s0, $ac3
lw s0, 140(s5)
mtlo s0, $ac3
lw s0, 148(s5)
wrdsp s0
lw s0, 8(s5)
mtlo s0, $ac0
lw s0, 12(s5)
mthi s0, $ac0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
/* Restore the status and EPC registers and return */
mtc0 k1, _CP0_STATUS
mtc0 k0, _CP0_EPC
ehb
eret
nop
.end vPortYieldISR
/******************************************************************/
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
.macro portFPUSetAndInc reg, dest
mtc1 \reg, \dest
cvt.d.w \dest, \dest
addiu \reg, \reg, 1
.endm
.set noreorder
.set noat
.section .text, code
.ent vPortInitialiseFPSCR
vPortInitialiseFPSCR:
/* Initialize the floating point status register in CP1. The initial
value is passed in a0. */
ctc1 a0, $f31
/* Clear the FPU registers */
addiu a0, zero, 0x0000
portFPUSetAndInc a0, $f0
portFPUSetAndInc a0, $f1
portFPUSetAndInc a0, $f2
portFPUSetAndInc a0, $f3
portFPUSetAndInc a0, $f4
portFPUSetAndInc a0, $f5
portFPUSetAndInc a0, $f6
portFPUSetAndInc a0, $f7
portFPUSetAndInc a0, $f8
portFPUSetAndInc a0, $f9
portFPUSetAndInc a0, $f10
portFPUSetAndInc a0, $f11
portFPUSetAndInc a0, $f12
portFPUSetAndInc a0, $f13
portFPUSetAndInc a0, $f14
portFPUSetAndInc a0, $f15
portFPUSetAndInc a0, $f16
portFPUSetAndInc a0, $f17
portFPUSetAndInc a0, $f18
portFPUSetAndInc a0, $f19
portFPUSetAndInc a0, $f20
portFPUSetAndInc a0, $f21
portFPUSetAndInc a0, $f22
portFPUSetAndInc a0, $f23
portFPUSetAndInc a0, $f24
portFPUSetAndInc a0, $f25
portFPUSetAndInc a0, $f26
portFPUSetAndInc a0, $f27
portFPUSetAndInc a0, $f28
portFPUSetAndInc a0, $f29
portFPUSetAndInc a0, $f30
portFPUSetAndInc a0, $f31
jr ra
nop
.end vPortInitialiseFPSCR
#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
/**********************************************************************/
/* Test read back */
/* a0 = address to store registers */
.set noreorder
.set noat
.section .text, code
.ent vPortFPUReadback
.global vPortFPUReadback
vPortFPUReadback:
sdc1 $f0, 0(a0)
sdc1 $f1, 8(a0)
sdc1 $f2, 16(a0)
sdc1 $f3, 24(a0)
sdc1 $f4, 32(a0)
sdc1 $f5, 40(a0)
sdc1 $f6, 48(a0)
sdc1 $f7, 56(a0)
sdc1 $f8, 64(a0)
sdc1 $f9, 72(a0)
sdc1 $f10, 80(a0)
sdc1 $f11, 88(a0)
sdc1 $f12, 96(a0)
sdc1 $f13, 104(a0)
sdc1 $f14, 112(a0)
sdc1 $f15, 120(a0)
sdc1 $f16, 128(a0)
sdc1 $f17, 136(a0)
sdc1 $f18, 144(a0)
sdc1 $f19, 152(a0)
sdc1 $f20, 160(a0)
sdc1 $f21, 168(a0)
sdc1 $f22, 176(a0)
sdc1 $f23, 184(a0)
sdc1 $f24, 192(a0)
sdc1 $f25, 200(a0)
sdc1 $f26, 208(a0)
sdc1 $f27, 216(a0)
sdc1 $f28, 224(a0)
sdc1 $f29, 232(a0)
sdc1 $f30, 240(a0)
sdc1 $f31, 248(a0)
jr ra
nop
.end vPortFPUReadback
#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 9,067 | portable/MPLAB/PIC32MEC14xx/port_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* FreeRTOS includes. */
#include "FreeRTOSConfig.h"
#include "ISR_Support.h"
/* Microchip includes. */
#include <xc.h>
#include <sys/asm.h>
.extern pxCurrentTCB
.extern vTaskSwitchContext
.extern vPortIncrementTick
.extern xISRStackTop
PORT_CPP_JTVIC_BASE = 0xBFFFC000
PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
.global vPortStartFirstTask .text
.global vPortYieldISR .text
.global vPortTickInterruptHandler .text
/******************************************************************/
/***************************************************************
* The following is needed to locate the
* vPortTickInterruptHandler function into the correct vector
* MEC14xx - This ISR will only be used if HW timers' interrupts
* in GIRQ23 are disaggregated.
*
***************************************************************/
.set noreorder
.set noat
.set micromips
.section .text, code
.ent vPortTickInterruptHandler
#if configTIMERS_DISAGGREGATED_ISRS == 0
.globl girq23_isr
girq23_isr:
vPortTickInterruptHandler:
portSAVE_CONTEXT
jal girq23_handler
nop
portRESTORE_CONTEXT
.end vPortTickInterruptHandler
#else
.globl girq23_b4
girq23_b4:
vPortTickInterruptHandler:
portSAVE_CONTEXT
jal vPortIncrementTick
nop
portRESTORE_CONTEXT
.end vPortTickInterruptHandler
#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
/******************************************************************/
.set micromips
.set noreorder
.set noat
.section .text, code
.ent vPortStartFirstTask
vPortStartFirstTask:
/* Simply restore the context of the highest priority task that has
been created so far. */
portRESTORE_CONTEXT
.end vPortStartFirstTask
/*******************************************************************/
/***************************************************************
* The following is needed to locate the vPortYieldISR function into the correct
* vector.
***************************************************************/
.set micromips
.set noreorder
.set noat
.section .text, code
.global vPortYieldISR
#if configCPU_DISAGGREGATED_ISRS == 0
.global girq24_isr
.ent girq24_isr
girq24_isr:
la k0, PORT_CPP_JTVIC_BASE
lw k0, 0x10C(k0)
andi k1, k0, 0x2
bgtz k1, vPortYieldISR
nop
portSAVE_CONTEXT
jal girq24_b_0_2
portRESTORE_CONTEXT
.end girq24_isr
#else
.global girq24_b1
girq24_b1:
#endif
.ent vPortYieldISR
vPortYieldISR:
/* Make room for the context. First save the current status so it can be
manipulated, and the cause and EPC registers so thier original values
are captured. */
addiu sp, sp, -portCONTEXT_SIZE
mfc0 k1, _CP0_STATUS
/* Also save s6 and s5 so they can be used. Any nesting interrupts should
maintain the values of these registers across the ISR. */
sw s6, 44(sp)
sw s5, 40(sp)
sw k1, portSTATUS_STACK_LOCATION(sp)
/* Prepare to re-enable interrupts above the kernel priority. */
ins k1, zero, 10, 7 /* Clear IPL bits 0:6. */
ins k1, zero, 18, 1 /* Clear IPL bit 7 */
ori k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
ins k1, zero, 1, 4 /* Clear EXL, ERL and UM. */
/* s5 is used as the frame pointer. */
add s5, zero, sp
/* Swap to the system stack. This is not conditional on the nesting
count as this interrupt is always the lowest priority and therefore
the nesting is always 0. */
la sp, xISRStackTop
lw sp, (sp)
/* Set the nesting count. */
la k0, uxInterruptNesting
addiu s6, zero, 1
sw s6, 0(k0)
/* s6 holds the EPC value, this is saved with the rest of the context
after interrupts are enabled. */
mfc0 s6, _CP0_EPC
/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 k1, _CP0_STATUS
/* Save the context into the space just created. s6 is saved again
here as it now contains the EPC value. */
sw ra, 120(s5)
sw s8, 116(s5)
sw t9, 112(s5)
sw t8, 108(s5)
sw t7, 104(s5)
sw t6, 100(s5)
sw t5, 96(s5)
sw t4, 92(s5)
sw t3, 88(s5)
sw t2, 84(s5)
sw t1, 80(s5)
sw t0, 76(s5)
sw a3, 72(s5)
sw a2, 68(s5)
sw a1, 64(s5)
sw a0, 60(s5)
sw v1, 56(s5)
sw v0, 52(s5)
sw s7, 48(s5)
sw s6, portEPC_STACK_LOCATION(s5)
/* s5 and s6 has already been saved. */
sw s4, 36(s5)
sw s3, 32(s5)
sw s2, 28(s5)
sw s1, 24(s5)
sw s0, 20(s5)
sw $1, 16(s5)
/* s7 is used as a scratch register as this should always be saved acro ss
nesting interrupts. */
mfhi s7
sw s7, 12(s5)
mflo s7
sw s7, 8(s5)
/* Save the stack pointer to the task. */
la s7, pxCurrentTCB
lw s7, (s7)
sw s5, (s7)
/* Set the interrupt mask to the max priority that can use the API.
The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
ever raise the IPL value and never lower it. */
di
ehb
mfc0 s7, _CP0_STATUS
ins s7, zero, 10, 7
ins s7, zero, 18, 1
ori s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
/* This mtc0 re-enables interrupts, but only above
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
mtc0 s6, _CP0_STATUS
ehb
/* Clear the software interrupt in the core. */
mfc0 s6, _CP0_CAUSE
ins s6, zero, 8, 1
mtc0 s6, _CP0_CAUSE
ehb
/* Clear the interrupt in the interrupt controller.
MEC14xx GIRQ24 Source bit[1] = 1 to clear */
la s6, PORT_CCP_JTVIC_GIRQ24_SRC
addiu s4, zero, 2
sw s4, (s6)
jal vTaskSwitchContext
nop
/* Clear the interrupt mask again. The saved status value is still in s7 */
mtc0 s7, _CP0_STATUS
ehb
/* Restore the stack pointer from the TCB. */
la s0, pxCurrentTCB
lw s0, (s0)
lw s5, (s0)
/* Restore the rest of the context. */
lw s0, 8(s5)
mtlo s0
lw s0, 12(s5)
mthi s0
lw $1, 16(s5)
lw s0, 20(s5)
lw s1, 24(s5)
lw s2, 28(s5)
lw s3, 32(s5)
lw s4, 36(s5)
/* s5 is loaded later. */
lw s6, 44(s5)
lw s7, 48(s5)
lw v0, 52(s5)
lw v1, 56(s5)
lw a0, 60(s5)
lw a1, 64(s5)
lw a2, 68(s5)
lw a3, 72(s5)
lw t0, 76(s5)
lw t1, 80(s5)
lw t2, 84(s5)
lw t3, 88(s5)
lw t4, 92(s5)
lw t5, 96(s5)
lw t6, 100(s5)
lw t7, 104(s5)
lw t8, 108(s5)
lw t9, 112(s5)
lw s8, 116(s5)
lw ra, 120(s5)
/* Protect access to the k registers, and others. */
di
ehb
/* Set nesting back to zero. As the lowest priority interrupt this
interrupt cannot have nested. */
la k0, uxInterruptNesting
sw zero, 0(k0)
/* Switch back to use the real stack pointer. */
add sp, zero, s5
/* Restore the real s5 value. */
lw s5, 40(sp)
/* Pop the status and epc values. */
lw k1, portSTATUS_STACK_LOCATION(sp)
lw k0, portEPC_STACK_LOCATION(sp)
/* Remove stack frame. */
addiu sp, sp, portCONTEXT_SIZE
mtc0 k1, _CP0_STATUS
mtc0 k0, _CP0_EPC
ehb
eret
nop
.end vPortYieldISR
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,286 | portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
.global _vPortYield
.extern _vTaskSwitchContext
.extern uxCriticalNesting
_vPortYield:
PUSH SR /* Save the SR used by the task.... */
PUSH W0 /* ....then disable interrupts. */
MOV #32, W0
MOV W0, SR
PUSH W1 /* Save registers to the stack. */
PUSH.D W2
PUSH.D W4
PUSH.D W6
PUSH.D W8
PUSH.D W10
PUSH.D W12
PUSH W14
PUSH RCOUNT
PUSH TBLPAG
PUSH CORCON
#ifdef __HAS_EDS__
PUSH DSRPAG
PUSH DSWPAG
#else
PUSH PSVPAG
#endif /* __HAS_EDS__ */
MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */
PUSH W0
MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */
MOV W15, [W0]
call _vTaskSwitchContext
MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */
MOV [W0], W15
POP W0 /* Restore the critical nesting counter for the task. */
MOV W0, _uxCriticalNesting
#ifdef __HAS_EDS__
POP DSWPAG
POP DSRPAG
#else
POP PSVPAG
#endif /* __HAS_EDS__ */
POP CORCON
POP TBLPAG
POP RCOUNT /* Restore the registers from the stack. */
POP W14
POP.D W12
POP.D W10
POP.D W8
POP.D W6
POP.D W4
POP.D W2
POP.D W0
POP SR
return
.end
#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 3,429 | portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
.global _vPortYield
.extern _vTaskSwitchContext
.extern uxCriticalNesting
_vPortYield:
PUSH SR /* Save the SR used by the task.... */
PUSH W0 /* ....then disable interrupts. */
MOV #32, W0
MOV W0, SR
PUSH W1 /* Save registers to the stack. */
PUSH.D W2
PUSH.D W4
PUSH.D W6
PUSH.D W8
PUSH.D W10
PUSH.D W12
PUSH W14
PUSH RCOUNT
PUSH TBLPAG
PUSH ACCAL
PUSH ACCAH
PUSH ACCAU
PUSH ACCBL
PUSH ACCBH
PUSH ACCBU
PUSH DCOUNT
PUSH DOSTARTL
PUSH DOSTARTH
PUSH DOENDL
PUSH DOENDH
PUSH CORCON
PUSH PSVPAG
MOV _uxCriticalNesting, W0 /* Save the critical nesting counter for the task. */
PUSH W0
MOV _pxCurrentTCB, W0 /* Save the new top of stack into the TCB. */
MOV W15, [W0]
call _vTaskSwitchContext
MOV _pxCurrentTCB, W0 /* Restore the stack pointer for the task. */
MOV [W0], W15
POP W0 /* Restore the critical nesting counter for the task. */
MOV W0, _uxCriticalNesting
POP PSVPAG
POP CORCON
POP DOENDH
POP DOENDL
POP DOSTARTH
POP DOSTARTL
POP DCOUNT
POP ACCBU
POP ACCBH
POP ACCBL
POP ACCAU
POP ACCAH
POP ACCAL
POP TBLPAG
POP RCOUNT /* Restore the registers from the stack. */
POP W14
POP.D W12
POP.D W10
POP.D W8
POP.D W6
POP.D W4
POP.D W2
POP.D W0
POP SR
return
.end
#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
|
funnsam/funnssa | 289 | fib.s | .global main
main:
pushq %rbp
movq %rsp, %rbp
.L0:
movl $1, %esi
xor %edi, %edi
movl $1000, %ecx
movl %edi, %edx
movl %esi, %eax
.L1:
movl %eax, %r8d
movl %eax, %esi
add %edx, %esi
cmpl %ecx, %eax
setb %dil
jb .L3
.L2:
xor %eax, %eax
leave
ret
.L3:
movl %r8d, %edx
movl %esi, %eax
jmp .L1
|
furkantokac/artiq_ft | 24,206 | src/llvm_libunwind/src/UnwindRegistersSave.S | //===------------------------ UnwindRegistersSave.S -----------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "assembly.h"
.text
#if !defined(__USING_SJLJ_EXCEPTIONS__)
#if defined(__i386__)
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# On entry:
# + +
# +-----------------------+
# + thread_state pointer +
# +-----------------------+
# + return address +
# +-----------------------+ <-- SP
# + +
#
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
push %eax
movl 8(%esp), %eax
movl %ebx, 4(%eax)
movl %ecx, 8(%eax)
movl %edx, 12(%eax)
movl %edi, 16(%eax)
movl %esi, 20(%eax)
movl %ebp, 24(%eax)
movl %esp, %edx
addl $8, %edx
movl %edx, 28(%eax) # store what sp was at call site as esp
# skip ss
# skip eflags
movl 4(%esp), %edx
movl %edx, 40(%eax) # store return address as eip
# skip cs
# skip ds
# skip es
# skip fs
# skip gs
movl (%esp), %edx
movl %edx, (%eax) # store original eax
popl %eax
xorl %eax, %eax # return UNW_ESUCCESS
ret
#elif defined(__x86_64__)
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# On entry:
# thread_state pointer is in rdi
#
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
#if defined(_WIN64)
#define PTR %rcx
#define TMP %rdx
#else
#define PTR %rdi
#define TMP %rsi
#endif
movq %rax, (PTR)
movq %rbx, 8(PTR)
movq %rcx, 16(PTR)
movq %rdx, 24(PTR)
movq %rdi, 32(PTR)
movq %rsi, 40(PTR)
movq %rbp, 48(PTR)
movq %rsp, 56(PTR)
addq $8, 56(PTR)
movq %r8, 64(PTR)
movq %r9, 72(PTR)
movq %r10, 80(PTR)
movq %r11, 88(PTR)
movq %r12, 96(PTR)
movq %r13,104(PTR)
movq %r14,112(PTR)
movq %r15,120(PTR)
movq (%rsp),TMP
movq TMP,128(PTR) # store return address as rip
# skip rflags
# skip cs
# skip fs
# skip gs
#if defined(_WIN64)
movdqu %xmm0,176(PTR)
movdqu %xmm1,192(PTR)
movdqu %xmm2,208(PTR)
movdqu %xmm3,224(PTR)
movdqu %xmm4,240(PTR)
movdqu %xmm5,256(PTR)
movdqu %xmm6,272(PTR)
movdqu %xmm7,288(PTR)
movdqu %xmm8,304(PTR)
movdqu %xmm9,320(PTR)
movdqu %xmm10,336(PTR)
movdqu %xmm11,352(PTR)
movdqu %xmm12,368(PTR)
movdqu %xmm13,384(PTR)
movdqu %xmm14,400(PTR)
movdqu %xmm15,416(PTR)
#endif
xorl %eax, %eax # return UNW_ESUCCESS
ret
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# On entry:
# thread_state pointer is in a0 ($4)
#
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
.set push
.set noat
.set noreorder
.set nomacro
sw $1, (4 * 1)($4)
sw $2, (4 * 2)($4)
sw $3, (4 * 3)($4)
sw $4, (4 * 4)($4)
sw $5, (4 * 5)($4)
sw $6, (4 * 6)($4)
sw $7, (4 * 7)($4)
sw $8, (4 * 8)($4)
sw $9, (4 * 9)($4)
sw $10, (4 * 10)($4)
sw $11, (4 * 11)($4)
sw $12, (4 * 12)($4)
sw $13, (4 * 13)($4)
sw $14, (4 * 14)($4)
sw $15, (4 * 15)($4)
sw $16, (4 * 16)($4)
sw $17, (4 * 17)($4)
sw $18, (4 * 18)($4)
sw $19, (4 * 19)($4)
sw $20, (4 * 20)($4)
sw $21, (4 * 21)($4)
sw $22, (4 * 22)($4)
sw $23, (4 * 23)($4)
sw $24, (4 * 24)($4)
sw $25, (4 * 25)($4)
sw $26, (4 * 26)($4)
sw $27, (4 * 27)($4)
sw $28, (4 * 28)($4)
sw $29, (4 * 29)($4)
sw $30, (4 * 30)($4)
sw $31, (4 * 31)($4)
# Store return address to pc
sw $31, (4 * 32)($4)
# hi and lo
mfhi $8
sw $8, (4 * 33)($4)
mflo $8
sw $8, (4 * 34)($4)
#ifdef __mips_hard_float
#if __mips_fpr != 64
sdc1 $f0, (4 * 36 + 8 * 0)($4)
sdc1 $f2, (4 * 36 + 8 * 2)($4)
sdc1 $f4, (4 * 36 + 8 * 4)($4)
sdc1 $f6, (4 * 36 + 8 * 6)($4)
sdc1 $f8, (4 * 36 + 8 * 8)($4)
sdc1 $f10, (4 * 36 + 8 * 10)($4)
sdc1 $f12, (4 * 36 + 8 * 12)($4)
sdc1 $f14, (4 * 36 + 8 * 14)($4)
sdc1 $f16, (4 * 36 + 8 * 16)($4)
sdc1 $f18, (4 * 36 + 8 * 18)($4)
sdc1 $f20, (4 * 36 + 8 * 20)($4)
sdc1 $f22, (4 * 36 + 8 * 22)($4)
sdc1 $f24, (4 * 36 + 8 * 24)($4)
sdc1 $f26, (4 * 36 + 8 * 26)($4)
sdc1 $f28, (4 * 36 + 8 * 28)($4)
sdc1 $f30, (4 * 36 + 8 * 30)($4)
#else
sdc1 $f0, (4 * 36 + 8 * 0)($4)
sdc1 $f1, (4 * 36 + 8 * 1)($4)
sdc1 $f2, (4 * 36 + 8 * 2)($4)
sdc1 $f3, (4 * 36 + 8 * 3)($4)
sdc1 $f4, (4 * 36 + 8 * 4)($4)
sdc1 $f5, (4 * 36 + 8 * 5)($4)
sdc1 $f6, (4 * 36 + 8 * 6)($4)
sdc1 $f7, (4 * 36 + 8 * 7)($4)
sdc1 $f8, (4 * 36 + 8 * 8)($4)
sdc1 $f9, (4 * 36 + 8 * 9)($4)
sdc1 $f10, (4 * 36 + 8 * 10)($4)
sdc1 $f11, (4 * 36 + 8 * 11)($4)
sdc1 $f12, (4 * 36 + 8 * 12)($4)
sdc1 $f13, (4 * 36 + 8 * 13)($4)
sdc1 $f14, (4 * 36 + 8 * 14)($4)
sdc1 $f15, (4 * 36 + 8 * 15)($4)
sdc1 $f16, (4 * 36 + 8 * 16)($4)
sdc1 $f17, (4 * 36 + 8 * 17)($4)
sdc1 $f18, (4 * 36 + 8 * 18)($4)
sdc1 $f19, (4 * 36 + 8 * 19)($4)
sdc1 $f20, (4 * 36 + 8 * 20)($4)
sdc1 $f21, (4 * 36 + 8 * 21)($4)
sdc1 $f22, (4 * 36 + 8 * 22)($4)
sdc1 $f23, (4 * 36 + 8 * 23)($4)
sdc1 $f24, (4 * 36 + 8 * 24)($4)
sdc1 $f25, (4 * 36 + 8 * 25)($4)
sdc1 $f26, (4 * 36 + 8 * 26)($4)
sdc1 $f27, (4 * 36 + 8 * 27)($4)
sdc1 $f28, (4 * 36 + 8 * 28)($4)
sdc1 $f29, (4 * 36 + 8 * 29)($4)
sdc1 $f30, (4 * 36 + 8 * 30)($4)
sdc1 $f31, (4 * 36 + 8 * 31)($4)
#endif
#endif
jr $31
# return UNW_ESUCCESS
or $2, $0, $0
.set pop
#elif defined(__mips64)
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# On entry:
# thread_state pointer is in a0 ($4)
#
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
.set push
.set noat
.set noreorder
.set nomacro
sd $1, (8 * 1)($4)
sd $2, (8 * 2)($4)
sd $3, (8 * 3)($4)
sd $4, (8 * 4)($4)
sd $5, (8 * 5)($4)
sd $6, (8 * 6)($4)
sd $7, (8 * 7)($4)
sd $8, (8 * 8)($4)
sd $9, (8 * 9)($4)
sd $10, (8 * 10)($4)
sd $11, (8 * 11)($4)
sd $12, (8 * 12)($4)
sd $13, (8 * 13)($4)
sd $14, (8 * 14)($4)
sd $15, (8 * 15)($4)
sd $16, (8 * 16)($4)
sd $17, (8 * 17)($4)
sd $18, (8 * 18)($4)
sd $19, (8 * 19)($4)
sd $20, (8 * 20)($4)
sd $21, (8 * 21)($4)
sd $22, (8 * 22)($4)
sd $23, (8 * 23)($4)
sd $24, (8 * 24)($4)
sd $25, (8 * 25)($4)
sd $26, (8 * 26)($4)
sd $27, (8 * 27)($4)
sd $28, (8 * 28)($4)
sd $29, (8 * 29)($4)
sd $30, (8 * 30)($4)
sd $31, (8 * 31)($4)
# Store return address to pc
sd $31, (8 * 32)($4)
# hi and lo
mfhi $8
sd $8, (8 * 33)($4)
mflo $8
sd $8, (8 * 34)($4)
#ifdef __mips_hard_float
sdc1 $f0, (8 * 35)($4)
sdc1 $f1, (8 * 36)($4)
sdc1 $f2, (8 * 37)($4)
sdc1 $f3, (8 * 38)($4)
sdc1 $f4, (8 * 39)($4)
sdc1 $f5, (8 * 40)($4)
sdc1 $f6, (8 * 41)($4)
sdc1 $f7, (8 * 42)($4)
sdc1 $f8, (8 * 43)($4)
sdc1 $f9, (8 * 44)($4)
sdc1 $f10, (8 * 45)($4)
sdc1 $f11, (8 * 46)($4)
sdc1 $f12, (8 * 47)($4)
sdc1 $f13, (8 * 48)($4)
sdc1 $f14, (8 * 49)($4)
sdc1 $f15, (8 * 50)($4)
sdc1 $f16, (8 * 51)($4)
sdc1 $f17, (8 * 52)($4)
sdc1 $f18, (8 * 53)($4)
sdc1 $f19, (8 * 54)($4)
sdc1 $f20, (8 * 55)($4)
sdc1 $f21, (8 * 56)($4)
sdc1 $f22, (8 * 57)($4)
sdc1 $f23, (8 * 58)($4)
sdc1 $f24, (8 * 59)($4)
sdc1 $f25, (8 * 60)($4)
sdc1 $f26, (8 * 61)($4)
sdc1 $f27, (8 * 62)($4)
sdc1 $f28, (8 * 63)($4)
sdc1 $f29, (8 * 64)($4)
sdc1 $f30, (8 * 65)($4)
sdc1 $f31, (8 * 66)($4)
#endif
jr $31
# return UNW_ESUCCESS
or $2, $0, $0
.set pop
# elif defined(__mips__)
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# Just trap for the time being.
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
teq $0, $0
#elif defined(__powerpc64__)
//
// extern int __unw_getcontext(unw_context_t* thread_state)
//
// On entry:
// thread_state pointer is in r3
//
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
// store register (GPR)
#define PPC64_STR(n) \
std %r##n, (8 * (n + 2))(%r3)
// save GPRs
PPC64_STR(0)
mflr %r0
std %r0, PPC64_OFFS_SRR0(%r3) // store lr as ssr0
PPC64_STR(1)
PPC64_STR(2)
PPC64_STR(3)
PPC64_STR(4)
PPC64_STR(5)
PPC64_STR(6)
PPC64_STR(7)
PPC64_STR(8)
PPC64_STR(9)
PPC64_STR(10)
PPC64_STR(11)
PPC64_STR(12)
PPC64_STR(13)
PPC64_STR(14)
PPC64_STR(15)
PPC64_STR(16)
PPC64_STR(17)
PPC64_STR(18)
PPC64_STR(19)
PPC64_STR(20)
PPC64_STR(21)
PPC64_STR(22)
PPC64_STR(23)
PPC64_STR(24)
PPC64_STR(25)
PPC64_STR(26)
PPC64_STR(27)
PPC64_STR(28)
PPC64_STR(29)
PPC64_STR(30)
PPC64_STR(31)
mfcr %r0
std %r0, PPC64_OFFS_CR(%r3)
mfxer %r0
std %r0, PPC64_OFFS_XER(%r3)
mflr %r0
std %r0, PPC64_OFFS_LR(%r3)
mfctr %r0
std %r0, PPC64_OFFS_CTR(%r3)
mfvrsave %r0
std %r0, PPC64_OFFS_VRSAVE(%r3)
#ifdef PPC64_HAS_VMX
// save VS registers
// (note that this also saves floating point registers and V registers,
// because part of VS is mapped to these registers)
addi %r4, %r3, PPC64_OFFS_FP
// store VS register
#define PPC64_STVS(n) \
stxvd2x %vs##n, 0, %r4 ;\
addi %r4, %r4, 16
PPC64_STVS(0)
PPC64_STVS(1)
PPC64_STVS(2)
PPC64_STVS(3)
PPC64_STVS(4)
PPC64_STVS(5)
PPC64_STVS(6)
PPC64_STVS(7)
PPC64_STVS(8)
PPC64_STVS(9)
PPC64_STVS(10)
PPC64_STVS(11)
PPC64_STVS(12)
PPC64_STVS(13)
PPC64_STVS(14)
PPC64_STVS(15)
PPC64_STVS(16)
PPC64_STVS(17)
PPC64_STVS(18)
PPC64_STVS(19)
PPC64_STVS(20)
PPC64_STVS(21)
PPC64_STVS(22)
PPC64_STVS(23)
PPC64_STVS(24)
PPC64_STVS(25)
PPC64_STVS(26)
PPC64_STVS(27)
PPC64_STVS(28)
PPC64_STVS(29)
PPC64_STVS(30)
PPC64_STVS(31)
PPC64_STVS(32)
PPC64_STVS(33)
PPC64_STVS(34)
PPC64_STVS(35)
PPC64_STVS(36)
PPC64_STVS(37)
PPC64_STVS(38)
PPC64_STVS(39)
PPC64_STVS(40)
PPC64_STVS(41)
PPC64_STVS(42)
PPC64_STVS(43)
PPC64_STVS(44)
PPC64_STVS(45)
PPC64_STVS(46)
PPC64_STVS(47)
PPC64_STVS(48)
PPC64_STVS(49)
PPC64_STVS(50)
PPC64_STVS(51)
PPC64_STVS(52)
PPC64_STVS(53)
PPC64_STVS(54)
PPC64_STVS(55)
PPC64_STVS(56)
PPC64_STVS(57)
PPC64_STVS(58)
PPC64_STVS(59)
PPC64_STVS(60)
PPC64_STVS(61)
PPC64_STVS(62)
PPC64_STVS(63)
#else
// store FP register
#define PPC64_STF(n) \
stfd %f##n, (PPC64_OFFS_FP + n * 16)(%r3)
// save float registers
PPC64_STF(0)
PPC64_STF(1)
PPC64_STF(2)
PPC64_STF(3)
PPC64_STF(4)
PPC64_STF(5)
PPC64_STF(6)
PPC64_STF(7)
PPC64_STF(8)
PPC64_STF(9)
PPC64_STF(10)
PPC64_STF(11)
PPC64_STF(12)
PPC64_STF(13)
PPC64_STF(14)
PPC64_STF(15)
PPC64_STF(16)
PPC64_STF(17)
PPC64_STF(18)
PPC64_STF(19)
PPC64_STF(20)
PPC64_STF(21)
PPC64_STF(22)
PPC64_STF(23)
PPC64_STF(24)
PPC64_STF(25)
PPC64_STF(26)
PPC64_STF(27)
PPC64_STF(28)
PPC64_STF(29)
PPC64_STF(30)
PPC64_STF(31)
// save vector registers
// Use 16-bytes below the stack pointer as an
// aligned buffer to save each vector register.
// Note that the stack pointer is always 16-byte aligned.
subi %r4, %r1, 16
#define PPC64_STV_UNALIGNED(n) \
stvx %v##n, 0, %r4 ;\
ld %r5, 0(%r4) ;\
std %r5, (PPC64_OFFS_V + n * 16)(%r3) ;\
ld %r5, 8(%r4) ;\
std %r5, (PPC64_OFFS_V + n * 16 + 8)(%r3)
PPC64_STV_UNALIGNED(0)
PPC64_STV_UNALIGNED(1)
PPC64_STV_UNALIGNED(2)
PPC64_STV_UNALIGNED(3)
PPC64_STV_UNALIGNED(4)
PPC64_STV_UNALIGNED(5)
PPC64_STV_UNALIGNED(6)
PPC64_STV_UNALIGNED(7)
PPC64_STV_UNALIGNED(8)
PPC64_STV_UNALIGNED(9)
PPC64_STV_UNALIGNED(10)
PPC64_STV_UNALIGNED(11)
PPC64_STV_UNALIGNED(12)
PPC64_STV_UNALIGNED(13)
PPC64_STV_UNALIGNED(14)
PPC64_STV_UNALIGNED(15)
PPC64_STV_UNALIGNED(16)
PPC64_STV_UNALIGNED(17)
PPC64_STV_UNALIGNED(18)
PPC64_STV_UNALIGNED(19)
PPC64_STV_UNALIGNED(20)
PPC64_STV_UNALIGNED(21)
PPC64_STV_UNALIGNED(22)
PPC64_STV_UNALIGNED(23)
PPC64_STV_UNALIGNED(24)
PPC64_STV_UNALIGNED(25)
PPC64_STV_UNALIGNED(26)
PPC64_STV_UNALIGNED(27)
PPC64_STV_UNALIGNED(28)
PPC64_STV_UNALIGNED(29)
PPC64_STV_UNALIGNED(30)
PPC64_STV_UNALIGNED(31)
#endif
li %r3, 0 // return UNW_ESUCCESS
blr
#elif defined(__ppc__)
//
// extern int unw_getcontext(unw_context_t* thread_state)
//
// On entry:
// thread_state pointer is in r3
//
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
stw %r0, 8(%r3)
mflr %r0
stw %r0, 0(%r3) // store lr as ssr0
stw %r1, 12(%r3)
stw %r2, 16(%r3)
stw %r3, 20(%r3)
stw %r4, 24(%r3)
stw %r5, 28(%r3)
stw %r6, 32(%r3)
stw %r7, 36(%r3)
stw %r8, 40(%r3)
stw %r9, 44(%r3)
stw %r10, 48(%r3)
stw %r11, 52(%r3)
stw %r12, 56(%r3)
stw %r13, 60(%r3)
stw %r14, 64(%r3)
stw %r15, 68(%r3)
stw %r16, 72(%r3)
stw %r17, 76(%r3)
stw %r18, 80(%r3)
stw %r19, 84(%r3)
stw %r20, 88(%r3)
stw %r21, 92(%r3)
stw %r22, 96(%r3)
stw %r23,100(%r3)
stw %r24,104(%r3)
stw %r25,108(%r3)
stw %r26,112(%r3)
stw %r27,116(%r3)
stw %r28,120(%r3)
stw %r29,124(%r3)
stw %r30,128(%r3)
stw %r31,132(%r3)
// save VRSave register
mfspr %r0, 256
stw %r0, 156(%r3)
// save CR registers
mfcr %r0
stw %r0, 136(%r3)
// save CTR register
mfctr %r0
stw %r0, 148(%r3)
// save float registers
stfd %f0, 160(%r3)
stfd %f1, 168(%r3)
stfd %f2, 176(%r3)
stfd %f3, 184(%r3)
stfd %f4, 192(%r3)
stfd %f5, 200(%r3)
stfd %f6, 208(%r3)
stfd %f7, 216(%r3)
stfd %f8, 224(%r3)
stfd %f9, 232(%r3)
stfd %f10,240(%r3)
stfd %f11,248(%r3)
stfd %f12,256(%r3)
stfd %f13,264(%r3)
stfd %f14,272(%r3)
stfd %f15,280(%r3)
stfd %f16,288(%r3)
stfd %f17,296(%r3)
stfd %f18,304(%r3)
stfd %f19,312(%r3)
stfd %f20,320(%r3)
stfd %f21,328(%r3)
stfd %f22,336(%r3)
stfd %f23,344(%r3)
stfd %f24,352(%r3)
stfd %f25,360(%r3)
stfd %f26,368(%r3)
stfd %f27,376(%r3)
stfd %f28,384(%r3)
stfd %f29,392(%r3)
stfd %f30,400(%r3)
stfd %f31,408(%r3)
// save vector registers
subi %r4, %r1, 16
rlwinm %r4, %r4, 0, 0, 27 // mask low 4-bits
// r4 is now a 16-byte aligned pointer into the red zone
#define SAVE_VECTOR_UNALIGNED(_vec, _offset) \
stvx _vec, 0, %r4 SEPARATOR \
lwz %r5, 0(%r4) SEPARATOR \
stw %r5, _offset(%r3) SEPARATOR \
lwz %r5, 4(%r4) SEPARATOR \
stw %r5, _offset+4(%r3) SEPARATOR \
lwz %r5, 8(%r4) SEPARATOR \
stw %r5, _offset+8(%r3) SEPARATOR \
lwz %r5, 12(%r4) SEPARATOR \
stw %r5, _offset+12(%r3)
SAVE_VECTOR_UNALIGNED( %v0, 424+0x000)
SAVE_VECTOR_UNALIGNED( %v1, 424+0x010)
SAVE_VECTOR_UNALIGNED( %v2, 424+0x020)
SAVE_VECTOR_UNALIGNED( %v3, 424+0x030)
SAVE_VECTOR_UNALIGNED( %v4, 424+0x040)
SAVE_VECTOR_UNALIGNED( %v5, 424+0x050)
SAVE_VECTOR_UNALIGNED( %v6, 424+0x060)
SAVE_VECTOR_UNALIGNED( %v7, 424+0x070)
SAVE_VECTOR_UNALIGNED( %v8, 424+0x080)
SAVE_VECTOR_UNALIGNED( %v9, 424+0x090)
SAVE_VECTOR_UNALIGNED(%v10, 424+0x0A0)
SAVE_VECTOR_UNALIGNED(%v11, 424+0x0B0)
SAVE_VECTOR_UNALIGNED(%v12, 424+0x0C0)
SAVE_VECTOR_UNALIGNED(%v13, 424+0x0D0)
SAVE_VECTOR_UNALIGNED(%v14, 424+0x0E0)
SAVE_VECTOR_UNALIGNED(%v15, 424+0x0F0)
SAVE_VECTOR_UNALIGNED(%v16, 424+0x100)
SAVE_VECTOR_UNALIGNED(%v17, 424+0x110)
SAVE_VECTOR_UNALIGNED(%v18, 424+0x120)
SAVE_VECTOR_UNALIGNED(%v19, 424+0x130)
SAVE_VECTOR_UNALIGNED(%v20, 424+0x140)
SAVE_VECTOR_UNALIGNED(%v21, 424+0x150)
SAVE_VECTOR_UNALIGNED(%v22, 424+0x160)
SAVE_VECTOR_UNALIGNED(%v23, 424+0x170)
SAVE_VECTOR_UNALIGNED(%v24, 424+0x180)
SAVE_VECTOR_UNALIGNED(%v25, 424+0x190)
SAVE_VECTOR_UNALIGNED(%v26, 424+0x1A0)
SAVE_VECTOR_UNALIGNED(%v27, 424+0x1B0)
SAVE_VECTOR_UNALIGNED(%v28, 424+0x1C0)
SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0)
SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0)
SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0)
li %r3, 0 // return UNW_ESUCCESS
blr
#elif defined(__arm64__) || defined(__aarch64__)
//
// extern int __unw_getcontext(unw_context_t* thread_state)
//
// On entry:
// thread_state pointer is in x0
//
.p2align 2
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
stp x0, x1, [x0, #0x000]
stp x2, x3, [x0, #0x010]
stp x4, x5, [x0, #0x020]
stp x6, x7, [x0, #0x030]
stp x8, x9, [x0, #0x040]
stp x10,x11, [x0, #0x050]
stp x12,x13, [x0, #0x060]
stp x14,x15, [x0, #0x070]
stp x16,x17, [x0, #0x080]
stp x18,x19, [x0, #0x090]
stp x20,x21, [x0, #0x0A0]
stp x22,x23, [x0, #0x0B0]
stp x24,x25, [x0, #0x0C0]
stp x26,x27, [x0, #0x0D0]
stp x28,x29, [x0, #0x0E0]
str x30, [x0, #0x0F0]
mov x1,sp
str x1, [x0, #0x0F8]
str x30, [x0, #0x100] // store return address as pc
// skip cpsr
stp d0, d1, [x0, #0x110]
stp d2, d3, [x0, #0x120]
stp d4, d5, [x0, #0x130]
stp d6, d7, [x0, #0x140]
stp d8, d9, [x0, #0x150]
stp d10,d11, [x0, #0x160]
stp d12,d13, [x0, #0x170]
stp d14,d15, [x0, #0x180]
stp d16,d17, [x0, #0x190]
stp d18,d19, [x0, #0x1A0]
stp d20,d21, [x0, #0x1B0]
stp d22,d23, [x0, #0x1C0]
stp d24,d25, [x0, #0x1D0]
stp d26,d27, [x0, #0x1E0]
stp d28,d29, [x0, #0x1F0]
str d30, [x0, #0x200]
str d31, [x0, #0x208]
mov x0, #0 // return UNW_ESUCCESS
ret
#elif defined(__arm__) && !defined(__APPLE__)
#if !defined(__ARM_ARCH_ISA_ARM)
#if (__ARM_ARCH_ISA_THUMB == 2)
.syntax unified
#endif
.thumb
#endif
@
@ extern int __unw_getcontext(unw_context_t* thread_state)
@
@ On entry:
@ thread_state pointer is in r0
@
@ Per EHABI #4.7 this only saves the core integer registers.
@ EHABI #7.4.5 notes that in general all VRS registers should be restored
@ however this is very hard to do for VFP registers because it is unknown
@ to the library how many registers are implemented by the architecture.
@ Instead, VFP registers are demand saved by logic external to __unw_getcontext.
@
.p2align 2
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
stm r0!, {r0-r7}
mov r1, r8
mov r2, r9
mov r3, r10
stm r0!, {r1-r3}
mov r1, r11
mov r2, sp
mov r3, lr
str r1, [r0, #0] @ r11
@ r12 does not need storing, it it the intra-procedure-call scratch register
str r2, [r0, #8] @ sp
str r3, [r0, #12] @ lr
str r3, [r0, #16] @ store return address as pc
@ T1 does not have a non-cpsr-clobbering register-zeroing instruction.
@ It is safe to use here though because we are about to return, and cpsr is
@ not expected to be preserved.
movs r0, #0 @ return UNW_ESUCCESS
#else
@ 32bit thumb-2 restrictions for stm:
@ . the sp (r13) cannot be in the list
@ . the pc (r15) cannot be in the list in an STM instruction
stm r0, {r0-r12}
str sp, [r0, #52]
str lr, [r0, #56]
str lr, [r0, #60] @ store return address as pc
mov r0, #0 @ return UNW_ESUCCESS
#endif
JMP(lr)
@
@ static void libunwind::Registers_arm::saveVFPWithFSTMD(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.fpu vfpv3-d16
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMDEPv)
vstmia r0, {d0-d15}
JMP(lr)
@
@ static void libunwind::Registers_arm::saveVFPWithFSTMX(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.fpu vfpv3-d16
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMXEPv)
vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
JMP(lr)
@
@ static void libunwind::Registers_arm::saveVFPv3(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.fpu vfpv3
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm9saveVFPv3EPv)
@ VFP and iwMMX instructions are only available when compiling with the flags
@ that enable them. We do not want to do that in the library (because we do not
@ want the compiler to generate instructions that access those) but this is
@ only accessed if the personality routine needs these registers. Use of
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instructions using the corresponding coprocessor mnemonic.
vstmia r0, {d16-d31}
JMP(lr)
#if defined(_LIBUNWIND_ARM_WMMX)
@
@ static void libunwind::Registers_arm::saveiWMMX(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.arch armv5te
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm9saveiWMMXEPv)
stcl p1, cr0, [r0], #8 @ wstrd wR0, [r0], #8
stcl p1, cr1, [r0], #8 @ wstrd wR1, [r0], #8
stcl p1, cr2, [r0], #8 @ wstrd wR2, [r0], #8
stcl p1, cr3, [r0], #8 @ wstrd wR3, [r0], #8
stcl p1, cr4, [r0], #8 @ wstrd wR4, [r0], #8
stcl p1, cr5, [r0], #8 @ wstrd wR5, [r0], #8
stcl p1, cr6, [r0], #8 @ wstrd wR6, [r0], #8
stcl p1, cr7, [r0], #8 @ wstrd wR7, [r0], #8
stcl p1, cr8, [r0], #8 @ wstrd wR8, [r0], #8
stcl p1, cr9, [r0], #8 @ wstrd wR9, [r0], #8
stcl p1, cr10, [r0], #8 @ wstrd wR10, [r0], #8
stcl p1, cr11, [r0], #8 @ wstrd wR11, [r0], #8
stcl p1, cr12, [r0], #8 @ wstrd wR12, [r0], #8
stcl p1, cr13, [r0], #8 @ wstrd wR13, [r0], #8
stcl p1, cr14, [r0], #8 @ wstrd wR14, [r0], #8
stcl p1, cr15, [r0], #8 @ wstrd wR15, [r0], #8
JMP(lr)
@
@ static void libunwind::Registers_arm::saveiWMMXControl(unw_uint32_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.arch armv5te
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm16saveiWMMXControlEPj)
stc2 p1, cr8, [r0], #4 @ wstrw wCGR0, [r0], #4
stc2 p1, cr9, [r0], #4 @ wstrw wCGR1, [r0], #4
stc2 p1, cr10, [r0], #4 @ wstrw wCGR2, [r0], #4
stc2 p1, cr11, [r0], #4 @ wstrw wCGR3, [r0], #4
JMP(lr)
#endif
#elif defined(__or1k__)
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# On entry:
# thread_state pointer is in r3
#
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
l.sw 0(r3), r0
l.sw 4(r3), r1
l.sw 8(r3), r2
l.sw 12(r3), r3
l.sw 16(r3), r4
l.sw 20(r3), r5
l.sw 24(r3), r6
l.sw 28(r3), r7
l.sw 32(r3), r8
l.sw 36(r3), r9
l.sw 40(r3), r10
l.sw 44(r3), r11
l.sw 48(r3), r12
l.sw 52(r3), r13
l.sw 56(r3), r14
l.sw 60(r3), r15
l.sw 64(r3), r16
l.sw 68(r3), r17
l.sw 72(r3), r18
l.sw 76(r3), r19
l.sw 80(r3), r20
l.sw 84(r3), r21
l.sw 88(r3), r22
l.sw 92(r3), r23
l.sw 96(r3), r24
l.sw 100(r3), r25
l.sw 104(r3), r26
l.sw 108(r3), r27
l.sw 112(r3), r28
l.sw 116(r3), r29
l.sw 120(r3), r30
l.sw 124(r3), r31
# store ra to pc
l.sw 128(r3), r9
# zero epcr
l.sw 132(r3), r0
#elif defined(__sparc__)
#
# extern int __unw_getcontext(unw_context_t* thread_state)
#
# On entry:
# thread_state pointer is in o0
#
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
ta 3
add %o7, 8, %o7
std %g0, [%o0 + 0]
std %g2, [%o0 + 8]
std %g4, [%o0 + 16]
std %g6, [%o0 + 24]
std %o0, [%o0 + 32]
std %o2, [%o0 + 40]
std %o4, [%o0 + 48]
std %o6, [%o0 + 56]
std %l0, [%o0 + 64]
std %l2, [%o0 + 72]
std %l4, [%o0 + 80]
std %l6, [%o0 + 88]
std %i0, [%o0 + 96]
std %i2, [%o0 + 104]
std %i4, [%o0 + 112]
std %i6, [%o0 + 120]
jmp %o7
clr %o0 // return UNW_ESUCCESS
#endif
WEAK_ALIAS(__unw_getcontext, unw_getcontext)
#endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
NO_EXEC_STACK_DIRECTIVE
|
furkantokac/artiq_ft | 26,108 | src/llvm_libunwind/src/UnwindRegistersRestore.S | //===-------------------- UnwindRegistersRestore.S ------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "assembly.h"
.text
#if !defined(__USING_SJLJ_EXCEPTIONS__)
#if defined(__i386__)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_x866jumptoEv)
#
# void libunwind::Registers_x86::jumpto()
#
#if defined(_WIN32)
# On windows, the 'this' pointer is passed in ecx instead of on the stack
movl %ecx, %eax
#else
# On entry:
# + +
# +-----------------------+
# + thread_state pointer +
# +-----------------------+
# + return address +
# +-----------------------+ <-- SP
# + +
movl 4(%esp), %eax
#endif
# set up eax and ret on new stack location
movl 28(%eax), %edx # edx holds new stack pointer
subl $8,%edx
movl %edx, 28(%eax)
movl 0(%eax), %ebx
movl %ebx, 0(%edx)
movl 40(%eax), %ebx
movl %ebx, 4(%edx)
# we now have ret and eax pushed onto where new stack will be
# restore all registers
movl 4(%eax), %ebx
movl 8(%eax), %ecx
movl 12(%eax), %edx
movl 16(%eax), %edi
movl 20(%eax), %esi
movl 24(%eax), %ebp
movl 28(%eax), %esp
# skip ss
# skip eflags
pop %eax # eax was already pushed on new stack
ret # eip was already pushed on new stack
# skip cs
# skip ds
# skip es
# skip fs
# skip gs
#elif defined(__x86_64__)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind16Registers_x86_646jumptoEv)
#
# void libunwind::Registers_x86_64::jumpto()
#
#if defined(_WIN64)
# On entry, thread_state pointer is in rcx; move it into rdi
# to share restore code below. Since this routine restores and
# overwrites all registers, we can use the same registers for
# pointers and temporaries as on unix even though win64 normally
# mustn't clobber some of them.
movq %rcx, %rdi
#else
# On entry, thread_state pointer is in rdi
#endif
movq 56(%rdi), %rax # rax holds new stack pointer
subq $16, %rax
movq %rax, 56(%rdi)
movq 32(%rdi), %rbx # store new rdi on new stack
movq %rbx, 0(%rax)
movq 128(%rdi), %rbx # store new rip on new stack
movq %rbx, 8(%rax)
# restore all registers
movq 0(%rdi), %rax
movq 8(%rdi), %rbx
movq 16(%rdi), %rcx
movq 24(%rdi), %rdx
# restore rdi later
movq 40(%rdi), %rsi
movq 48(%rdi), %rbp
# restore rsp later
movq 64(%rdi), %r8
movq 72(%rdi), %r9
movq 80(%rdi), %r10
movq 88(%rdi), %r11
movq 96(%rdi), %r12
movq 104(%rdi), %r13
movq 112(%rdi), %r14
movq 120(%rdi), %r15
# skip rflags
# skip cs
# skip fs
# skip gs
#if defined(_WIN64)
movdqu 176(%rdi),%xmm0
movdqu 192(%rdi),%xmm1
movdqu 208(%rdi),%xmm2
movdqu 224(%rdi),%xmm3
movdqu 240(%rdi),%xmm4
movdqu 256(%rdi),%xmm5
movdqu 272(%rdi),%xmm6
movdqu 288(%rdi),%xmm7
movdqu 304(%rdi),%xmm8
movdqu 320(%rdi),%xmm9
movdqu 336(%rdi),%xmm10
movdqu 352(%rdi),%xmm11
movdqu 368(%rdi),%xmm12
movdqu 384(%rdi),%xmm13
movdqu 400(%rdi),%xmm14
movdqu 416(%rdi),%xmm15
#endif
movq 56(%rdi), %rsp # cut back rsp to new location
pop %rdi # rdi was saved here earlier
ret # rip was saved here
#elif defined(__powerpc64__)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_ppc646jumptoEv)
//
// void libunwind::Registers_ppc64::jumpto()
//
// On entry:
// thread_state pointer is in r3
//
// load register (GPR)
#define PPC64_LR(n) \
ld %r##n, (8 * (n + 2))(%r3)
// restore integral registers
// skip r0 for now
// skip r1 for now
PPC64_LR(2)
// skip r3 for now
// skip r4 for now
// skip r5 for now
PPC64_LR(6)
PPC64_LR(7)
PPC64_LR(8)
PPC64_LR(9)
PPC64_LR(10)
PPC64_LR(11)
PPC64_LR(12)
PPC64_LR(13)
PPC64_LR(14)
PPC64_LR(15)
PPC64_LR(16)
PPC64_LR(17)
PPC64_LR(18)
PPC64_LR(19)
PPC64_LR(20)
PPC64_LR(21)
PPC64_LR(22)
PPC64_LR(23)
PPC64_LR(24)
PPC64_LR(25)
PPC64_LR(26)
PPC64_LR(27)
PPC64_LR(28)
PPC64_LR(29)
PPC64_LR(30)
PPC64_LR(31)
#ifdef PPC64_HAS_VMX
// restore VS registers
// (note that this also restores floating point registers and V registers,
// because part of VS is mapped to these registers)
addi %r4, %r3, PPC64_OFFS_FP
// load VS register
#define PPC64_LVS(n) \
lxvd2x %vs##n, 0, %r4 ;\
addi %r4, %r4, 16
// restore the first 32 VS regs (and also all floating point regs)
PPC64_LVS(0)
PPC64_LVS(1)
PPC64_LVS(2)
PPC64_LVS(3)
PPC64_LVS(4)
PPC64_LVS(5)
PPC64_LVS(6)
PPC64_LVS(7)
PPC64_LVS(8)
PPC64_LVS(9)
PPC64_LVS(10)
PPC64_LVS(11)
PPC64_LVS(12)
PPC64_LVS(13)
PPC64_LVS(14)
PPC64_LVS(15)
PPC64_LVS(16)
PPC64_LVS(17)
PPC64_LVS(18)
PPC64_LVS(19)
PPC64_LVS(20)
PPC64_LVS(21)
PPC64_LVS(22)
PPC64_LVS(23)
PPC64_LVS(24)
PPC64_LVS(25)
PPC64_LVS(26)
PPC64_LVS(27)
PPC64_LVS(28)
PPC64_LVS(29)
PPC64_LVS(30)
PPC64_LVS(31)
// use VRSAVE to conditionally restore the remaining VS regs,
// that are where the V regs are mapped
ld %r5, PPC64_OFFS_VRSAVE(%r3) // test VRsave
cmpwi %r5, 0
beq Lnovec
// conditionally load VS
#define PPC64_CLVS_BOTTOM(n) \
beq Ldone##n ;\
addi %r4, %r3, PPC64_OFFS_FP + n * 16 ;\
lxvd2x %vs##n, 0, %r4 ;\
Ldone##n:
#define PPC64_CLVSl(n) \
andis. %r0, %r5, (1<<(47-n)) ;\
PPC64_CLVS_BOTTOM(n)
#define PPC64_CLVSh(n) \
andi. %r0, %r5, (1<<(63-n)) ;\
PPC64_CLVS_BOTTOM(n)
PPC64_CLVSl(32)
PPC64_CLVSl(33)
PPC64_CLVSl(34)
PPC64_CLVSl(35)
PPC64_CLVSl(36)
PPC64_CLVSl(37)
PPC64_CLVSl(38)
PPC64_CLVSl(39)
PPC64_CLVSl(40)
PPC64_CLVSl(41)
PPC64_CLVSl(42)
PPC64_CLVSl(43)
PPC64_CLVSl(44)
PPC64_CLVSl(45)
PPC64_CLVSl(46)
PPC64_CLVSl(47)
PPC64_CLVSh(48)
PPC64_CLVSh(49)
PPC64_CLVSh(50)
PPC64_CLVSh(51)
PPC64_CLVSh(52)
PPC64_CLVSh(53)
PPC64_CLVSh(54)
PPC64_CLVSh(55)
PPC64_CLVSh(56)
PPC64_CLVSh(57)
PPC64_CLVSh(58)
PPC64_CLVSh(59)
PPC64_CLVSh(60)
PPC64_CLVSh(61)
PPC64_CLVSh(62)
PPC64_CLVSh(63)
#else
// load FP register
#define PPC64_LF(n) \
lfd %f##n, (PPC64_OFFS_FP + n * 16)(%r3)
// restore float registers
PPC64_LF(0)
PPC64_LF(1)
PPC64_LF(2)
PPC64_LF(3)
PPC64_LF(4)
PPC64_LF(5)
PPC64_LF(6)
PPC64_LF(7)
PPC64_LF(8)
PPC64_LF(9)
PPC64_LF(10)
PPC64_LF(11)
PPC64_LF(12)
PPC64_LF(13)
PPC64_LF(14)
PPC64_LF(15)
PPC64_LF(16)
PPC64_LF(17)
PPC64_LF(18)
PPC64_LF(19)
PPC64_LF(20)
PPC64_LF(21)
PPC64_LF(22)
PPC64_LF(23)
PPC64_LF(24)
PPC64_LF(25)
PPC64_LF(26)
PPC64_LF(27)
PPC64_LF(28)
PPC64_LF(29)
PPC64_LF(30)
PPC64_LF(31)
// restore vector registers if any are in use
ld %r5, PPC64_OFFS_VRSAVE(%r3) // test VRsave
cmpwi %r5, 0
beq Lnovec
subi %r4, %r1, 16
// r4 is now a 16-byte aligned pointer into the red zone
// the _vectorScalarRegisters may not be 16-byte aligned
// so copy via red zone temp buffer
#define PPC64_CLV_UNALIGNED_BOTTOM(n) \
beq Ldone##n ;\
ld %r0, (PPC64_OFFS_V + n * 16)(%r3) ;\
std %r0, 0(%r4) ;\
ld %r0, (PPC64_OFFS_V + n * 16 + 8)(%r3) ;\
std %r0, 8(%r4) ;\
lvx %v##n, 0, %r4 ;\
Ldone ## n:
#define PPC64_CLV_UNALIGNEDl(n) \
andis. %r0, %r5, (1<<(15-n)) ;\
PPC64_CLV_UNALIGNED_BOTTOM(n)
#define PPC64_CLV_UNALIGNEDh(n) \
andi. %r0, %r5, (1<<(31-n)) ;\
PPC64_CLV_UNALIGNED_BOTTOM(n)
PPC64_CLV_UNALIGNEDl(0)
PPC64_CLV_UNALIGNEDl(1)
PPC64_CLV_UNALIGNEDl(2)
PPC64_CLV_UNALIGNEDl(3)
PPC64_CLV_UNALIGNEDl(4)
PPC64_CLV_UNALIGNEDl(5)
PPC64_CLV_UNALIGNEDl(6)
PPC64_CLV_UNALIGNEDl(7)
PPC64_CLV_UNALIGNEDl(8)
PPC64_CLV_UNALIGNEDl(9)
PPC64_CLV_UNALIGNEDl(10)
PPC64_CLV_UNALIGNEDl(11)
PPC64_CLV_UNALIGNEDl(12)
PPC64_CLV_UNALIGNEDl(13)
PPC64_CLV_UNALIGNEDl(14)
PPC64_CLV_UNALIGNEDl(15)
PPC64_CLV_UNALIGNEDh(16)
PPC64_CLV_UNALIGNEDh(17)
PPC64_CLV_UNALIGNEDh(18)
PPC64_CLV_UNALIGNEDh(19)
PPC64_CLV_UNALIGNEDh(20)
PPC64_CLV_UNALIGNEDh(21)
PPC64_CLV_UNALIGNEDh(22)
PPC64_CLV_UNALIGNEDh(23)
PPC64_CLV_UNALIGNEDh(24)
PPC64_CLV_UNALIGNEDh(25)
PPC64_CLV_UNALIGNEDh(26)
PPC64_CLV_UNALIGNEDh(27)
PPC64_CLV_UNALIGNEDh(28)
PPC64_CLV_UNALIGNEDh(29)
PPC64_CLV_UNALIGNEDh(30)
PPC64_CLV_UNALIGNEDh(31)
#endif
Lnovec:
ld %r0, PPC64_OFFS_CR(%r3)
mtcr %r0
ld %r0, PPC64_OFFS_SRR0(%r3)
mtctr %r0
PPC64_LR(0)
PPC64_LR(5)
PPC64_LR(4)
PPC64_LR(1)
PPC64_LR(3)
bctr
#elif defined(__ppc__)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
//
// void libunwind::Registers_ppc::jumpto()
//
// On entry:
// thread_state pointer is in r3
//
// restore integral registerrs
// skip r0 for now
// skip r1 for now
lwz %r2, 16(%r3)
// skip r3 for now
// skip r4 for now
// skip r5 for now
lwz %r6, 32(%r3)
lwz %r7, 36(%r3)
lwz %r8, 40(%r3)
lwz %r9, 44(%r3)
lwz %r10, 48(%r3)
lwz %r11, 52(%r3)
lwz %r12, 56(%r3)
lwz %r13, 60(%r3)
lwz %r14, 64(%r3)
lwz %r15, 68(%r3)
lwz %r16, 72(%r3)
lwz %r17, 76(%r3)
lwz %r18, 80(%r3)
lwz %r19, 84(%r3)
lwz %r20, 88(%r3)
lwz %r21, 92(%r3)
lwz %r22, 96(%r3)
lwz %r23,100(%r3)
lwz %r24,104(%r3)
lwz %r25,108(%r3)
lwz %r26,112(%r3)
lwz %r27,116(%r3)
lwz %r28,120(%r3)
lwz %r29,124(%r3)
lwz %r30,128(%r3)
lwz %r31,132(%r3)
// restore float registers
lfd %f0, 160(%r3)
lfd %f1, 168(%r3)
lfd %f2, 176(%r3)
lfd %f3, 184(%r3)
lfd %f4, 192(%r3)
lfd %f5, 200(%r3)
lfd %f6, 208(%r3)
lfd %f7, 216(%r3)
lfd %f8, 224(%r3)
lfd %f9, 232(%r3)
lfd %f10,240(%r3)
lfd %f11,248(%r3)
lfd %f12,256(%r3)
lfd %f13,264(%r3)
lfd %f14,272(%r3)
lfd %f15,280(%r3)
lfd %f16,288(%r3)
lfd %f17,296(%r3)
lfd %f18,304(%r3)
lfd %f19,312(%r3)
lfd %f20,320(%r3)
lfd %f21,328(%r3)
lfd %f22,336(%r3)
lfd %f23,344(%r3)
lfd %f24,352(%r3)
lfd %f25,360(%r3)
lfd %f26,368(%r3)
lfd %f27,376(%r3)
lfd %f28,384(%r3)
lfd %f29,392(%r3)
lfd %f30,400(%r3)
lfd %f31,408(%r3)
// restore vector registers if any are in use
lwz %r5, 156(%r3) // test VRsave
cmpwi %r5, 0
beq Lnovec
subi %r4, %r1, 16
rlwinm %r4, %r4, 0, 0, 27 // mask low 4-bits
// r4 is now a 16-byte aligned pointer into the red zone
// the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer
#define LOAD_VECTOR_UNALIGNEDl(_index) \
andis. %r0, %r5, (1<<(15-_index)) SEPARATOR \
beq Ldone ## _index SEPARATOR \
lwz %r0, 424+_index*16(%r3) SEPARATOR \
stw %r0, 0(%r4) SEPARATOR \
lwz %r0, 424+_index*16+4(%r3) SEPARATOR \
stw %r0, 4(%r4) SEPARATOR \
lwz %r0, 424+_index*16+8(%r3) SEPARATOR \
stw %r0, 8(%r4) SEPARATOR \
lwz %r0, 424+_index*16+12(%r3) SEPARATOR \
stw %r0, 12(%r4) SEPARATOR \
lvx %v ## _index, 0, %r4 SEPARATOR \
Ldone ## _index:
#define LOAD_VECTOR_UNALIGNEDh(_index) \
andi. %r0, %r5, (1<<(31-_index)) SEPARATOR \
beq Ldone ## _index SEPARATOR \
lwz %r0, 424+_index*16(%r3) SEPARATOR \
stw %r0, 0(%r4) SEPARATOR \
lwz %r0, 424+_index*16+4(%r3) SEPARATOR \
stw %r0, 4(%r4) SEPARATOR \
lwz %r0, 424+_index*16+8(%r3) SEPARATOR \
stw %r0, 8(%r4) SEPARATOR \
lwz %r0, 424+_index*16+12(%r3) SEPARATOR \
stw %r0, 12(%r4) SEPARATOR \
lvx %v ## _index, 0, %r4 SEPARATOR \
Ldone ## _index:
LOAD_VECTOR_UNALIGNEDl(0)
LOAD_VECTOR_UNALIGNEDl(1)
LOAD_VECTOR_UNALIGNEDl(2)
LOAD_VECTOR_UNALIGNEDl(3)
LOAD_VECTOR_UNALIGNEDl(4)
LOAD_VECTOR_UNALIGNEDl(5)
LOAD_VECTOR_UNALIGNEDl(6)
LOAD_VECTOR_UNALIGNEDl(7)
LOAD_VECTOR_UNALIGNEDl(8)
LOAD_VECTOR_UNALIGNEDl(9)
LOAD_VECTOR_UNALIGNEDl(10)
LOAD_VECTOR_UNALIGNEDl(11)
LOAD_VECTOR_UNALIGNEDl(12)
LOAD_VECTOR_UNALIGNEDl(13)
LOAD_VECTOR_UNALIGNEDl(14)
LOAD_VECTOR_UNALIGNEDl(15)
LOAD_VECTOR_UNALIGNEDh(16)
LOAD_VECTOR_UNALIGNEDh(17)
LOAD_VECTOR_UNALIGNEDh(18)
LOAD_VECTOR_UNALIGNEDh(19)
LOAD_VECTOR_UNALIGNEDh(20)
LOAD_VECTOR_UNALIGNEDh(21)
LOAD_VECTOR_UNALIGNEDh(22)
LOAD_VECTOR_UNALIGNEDh(23)
LOAD_VECTOR_UNALIGNEDh(24)
LOAD_VECTOR_UNALIGNEDh(25)
LOAD_VECTOR_UNALIGNEDh(26)
LOAD_VECTOR_UNALIGNEDh(27)
LOAD_VECTOR_UNALIGNEDh(28)
LOAD_VECTOR_UNALIGNEDh(29)
LOAD_VECTOR_UNALIGNEDh(30)
LOAD_VECTOR_UNALIGNEDh(31)
Lnovec:
lwz %r0, 136(%r3) // __cr
mtcr %r0
lwz %r0, 148(%r3) // __ctr
mtctr %r0
lwz %r0, 0(%r3) // __ssr0
mtctr %r0
lwz %r0, 8(%r3) // do r0 now
lwz %r5, 28(%r3) // do r5 now
lwz %r4, 24(%r3) // do r4 now
lwz %r1, 12(%r3) // do sp now
lwz %r3, 20(%r3) // do r3 last
bctr
#elif defined(__arm64__) || defined(__aarch64__)
//
// void libunwind::Registers_arm64::jumpto()
//
// On entry:
// thread_state pointer is in x0
//
.p2align 2
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_arm646jumptoEv)
// skip restore of x0,x1 for now
ldp x2, x3, [x0, #0x010]
ldp x4, x5, [x0, #0x020]
ldp x6, x7, [x0, #0x030]
ldp x8, x9, [x0, #0x040]
ldp x10,x11, [x0, #0x050]
ldp x12,x13, [x0, #0x060]
ldp x14,x15, [x0, #0x070]
// x16 and x17 were clobbered by the call into the unwinder, so no point in
// restoring them.
ldp x18,x19, [x0, #0x090]
ldp x20,x21, [x0, #0x0A0]
ldp x22,x23, [x0, #0x0B0]
ldp x24,x25, [x0, #0x0C0]
ldp x26,x27, [x0, #0x0D0]
ldp x28,x29, [x0, #0x0E0]
ldr x30, [x0, #0x100] // restore pc into lr
ldp d0, d1, [x0, #0x110]
ldp d2, d3, [x0, #0x120]
ldp d4, d5, [x0, #0x130]
ldp d6, d7, [x0, #0x140]
ldp d8, d9, [x0, #0x150]
ldp d10,d11, [x0, #0x160]
ldp d12,d13, [x0, #0x170]
ldp d14,d15, [x0, #0x180]
ldp d16,d17, [x0, #0x190]
ldp d18,d19, [x0, #0x1A0]
ldp d20,d21, [x0, #0x1B0]
ldp d22,d23, [x0, #0x1C0]
ldp d24,d25, [x0, #0x1D0]
ldp d26,d27, [x0, #0x1E0]
ldp d28,d29, [x0, #0x1F0]
ldr d30, [x0, #0x200]
ldr d31, [x0, #0x208]
// Finally, restore sp. This must be done after the the last read from the
// context struct, because it is allocated on the stack, and an exception
// could clobber the de-allocated portion of the stack after sp has been
// restored.
ldr x16, [x0, #0x0F8]
ldp x0, x1, [x0, #0x000] // restore x0,x1
mov sp,x16 // restore sp
ret x30 // jump to pc
#elif defined(__arm__) && !defined(__APPLE__)
#if !defined(__ARM_ARCH_ISA_ARM)
#if (__ARM_ARCH_ISA_THUMB == 2)
.syntax unified
#endif
.thumb
#endif
@
@ void libunwind::Registers_arm::restoreCoreAndJumpTo()
@
@ On entry:
@ thread_state pointer is in r0
@
.p2align 2
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm20restoreCoreAndJumpToEv)
#if !defined(__ARM_ARCH_ISA_ARM) && __ARM_ARCH_ISA_THUMB == 1
@ r8-r11: ldm into r1-r4, then mov to r8-r11
adds r0, #0x20
ldm r0!, {r1-r4}
subs r0, #0x30
mov r8, r1
mov r9, r2
mov r10, r3
mov r11, r4
@ r12 does not need loading, it it the intra-procedure-call scratch register
ldr r2, [r0, #0x34]
ldr r3, [r0, #0x3c]
mov sp, r2
mov lr, r3 @ restore pc into lr
ldm r0, {r0-r7}
#else
@ Use lr as base so that r0 can be restored.
mov lr, r0
@ 32bit thumb-2 restrictions for ldm:
@ . the sp (r13) cannot be in the list
@ . the pc (r15) and lr (r14) cannot both be in the list in an LDM instruction
ldm lr, {r0-r12}
ldr sp, [lr, #52]
ldr lr, [lr, #60] @ restore pc into lr
#endif
JMP(lr)
@
@ static void libunwind::Registers_arm::restoreVFPWithFLDMD(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.fpu vfpv3-d16
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMDEPv)
@ VFP and iwMMX instructions are only available when compiling with the flags
@ that enable them. We do not want to do that in the library (because we do not
@ want the compiler to generate instructions that access those) but this is
@ only accessed if the personality routine needs these registers. Use of
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instruction using the corresponding coprocessor mnemonic.
vldmia r0, {d0-d15}
JMP(lr)
@
@ static void libunwind::Registers_arm::restoreVFPWithFLDMX(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.fpu vfpv3-d16
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPv)
vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
JMP(lr)
@
@ static void libunwind::Registers_arm::restoreVFPv3(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.fpu vfpv3
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPv)
vldmia r0, {d16-d31}
JMP(lr)
#if defined(__ARM_WMMX)
@
@ static void libunwind::Registers_arm::restoreiWMMX(unw_fpreg_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.arch armv5te
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm12restoreiWMMXEPv)
ldcl p1, cr0, [r0], #8 @ wldrd wR0, [r0], #8
ldcl p1, cr1, [r0], #8 @ wldrd wR1, [r0], #8
ldcl p1, cr2, [r0], #8 @ wldrd wR2, [r0], #8
ldcl p1, cr3, [r0], #8 @ wldrd wR3, [r0], #8
ldcl p1, cr4, [r0], #8 @ wldrd wR4, [r0], #8
ldcl p1, cr5, [r0], #8 @ wldrd wR5, [r0], #8
ldcl p1, cr6, [r0], #8 @ wldrd wR6, [r0], #8
ldcl p1, cr7, [r0], #8 @ wldrd wR7, [r0], #8
ldcl p1, cr8, [r0], #8 @ wldrd wR8, [r0], #8
ldcl p1, cr9, [r0], #8 @ wldrd wR9, [r0], #8
ldcl p1, cr10, [r0], #8 @ wldrd wR10, [r0], #8
ldcl p1, cr11, [r0], #8 @ wldrd wR11, [r0], #8
ldcl p1, cr12, [r0], #8 @ wldrd wR12, [r0], #8
ldcl p1, cr13, [r0], #8 @ wldrd wR13, [r0], #8
ldcl p1, cr14, [r0], #8 @ wldrd wR14, [r0], #8
ldcl p1, cr15, [r0], #8 @ wldrd wR15, [r0], #8
JMP(lr)
@
@ static void libunwind::Registers_arm::restoreiWMMXControl(unw_uint32_t* values)
@
@ On entry:
@ values pointer is in r0
@
.p2align 2
#if defined(__ELF__)
.arch armv5te
#endif
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_arm19restoreiWMMXControlEPj)
ldc2 p1, cr8, [r0], #4 @ wldrw wCGR0, [r0], #4
ldc2 p1, cr9, [r0], #4 @ wldrw wCGR1, [r0], #4
ldc2 p1, cr10, [r0], #4 @ wldrw wCGR2, [r0], #4
ldc2 p1, cr11, [r0], #4 @ wldrw wCGR3, [r0], #4
JMP(lr)
#endif
#elif defined(__or1k__)
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
#
# void libunwind::Registers_or1k::jumpto()
#
# On entry:
# thread_state pointer is in r3
#
# restore integral registers
l.lwz r0, 0(r3)
l.lwz r1, 4(r3)
l.lwz r2, 8(r3)
# skip r3 for now
l.lwz r4, 16(r3)
l.lwz r5, 20(r3)
l.lwz r6, 24(r3)
l.lwz r7, 28(r3)
l.lwz r8, 32(r3)
# skip r9
l.lwz r10, 40(r3)
l.lwz r11, 44(r3)
l.lwz r12, 48(r3)
l.lwz r13, 52(r3)
l.lwz r14, 56(r3)
l.lwz r15, 60(r3)
l.lwz r16, 64(r3)
l.lwz r17, 68(r3)
l.lwz r18, 72(r3)
l.lwz r19, 76(r3)
l.lwz r20, 80(r3)
l.lwz r21, 84(r3)
l.lwz r22, 88(r3)
l.lwz r23, 92(r3)
l.lwz r24, 96(r3)
l.lwz r25,100(r3)
l.lwz r26,104(r3)
l.lwz r27,108(r3)
l.lwz r28,112(r3)
l.lwz r29,116(r3)
l.lwz r30,120(r3)
l.lwz r31,124(r3)
# at last, restore r3
l.lwz r3, 12(r3)
# load new pc into ra
l.lwz r9, 128(r3)
# jump to pc
l.jr r9
l.nop
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
//
// void libunwind::Registers_mips_o32::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind18Registers_mips_o326jumptoEv)
.set push
.set noat
.set noreorder
.set nomacro
#ifdef __mips_hard_float
#if __mips_fpr != 64
ldc1 $f0, (4 * 36 + 8 * 0)($4)
ldc1 $f2, (4 * 36 + 8 * 2)($4)
ldc1 $f4, (4 * 36 + 8 * 4)($4)
ldc1 $f6, (4 * 36 + 8 * 6)($4)
ldc1 $f8, (4 * 36 + 8 * 8)($4)
ldc1 $f10, (4 * 36 + 8 * 10)($4)
ldc1 $f12, (4 * 36 + 8 * 12)($4)
ldc1 $f14, (4 * 36 + 8 * 14)($4)
ldc1 $f16, (4 * 36 + 8 * 16)($4)
ldc1 $f18, (4 * 36 + 8 * 18)($4)
ldc1 $f20, (4 * 36 + 8 * 20)($4)
ldc1 $f22, (4 * 36 + 8 * 22)($4)
ldc1 $f24, (4 * 36 + 8 * 24)($4)
ldc1 $f26, (4 * 36 + 8 * 26)($4)
ldc1 $f28, (4 * 36 + 8 * 28)($4)
ldc1 $f30, (4 * 36 + 8 * 30)($4)
#else
ldc1 $f0, (4 * 36 + 8 * 0)($4)
ldc1 $f1, (4 * 36 + 8 * 1)($4)
ldc1 $f2, (4 * 36 + 8 * 2)($4)
ldc1 $f3, (4 * 36 + 8 * 3)($4)
ldc1 $f4, (4 * 36 + 8 * 4)($4)
ldc1 $f5, (4 * 36 + 8 * 5)($4)
ldc1 $f6, (4 * 36 + 8 * 6)($4)
ldc1 $f7, (4 * 36 + 8 * 7)($4)
ldc1 $f8, (4 * 36 + 8 * 8)($4)
ldc1 $f9, (4 * 36 + 8 * 9)($4)
ldc1 $f10, (4 * 36 + 8 * 10)($4)
ldc1 $f11, (4 * 36 + 8 * 11)($4)
ldc1 $f12, (4 * 36 + 8 * 12)($4)
ldc1 $f13, (4 * 36 + 8 * 13)($4)
ldc1 $f14, (4 * 36 + 8 * 14)($4)
ldc1 $f15, (4 * 36 + 8 * 15)($4)
ldc1 $f16, (4 * 36 + 8 * 16)($4)
ldc1 $f17, (4 * 36 + 8 * 17)($4)
ldc1 $f18, (4 * 36 + 8 * 18)($4)
ldc1 $f19, (4 * 36 + 8 * 19)($4)
ldc1 $f20, (4 * 36 + 8 * 20)($4)
ldc1 $f21, (4 * 36 + 8 * 21)($4)
ldc1 $f22, (4 * 36 + 8 * 22)($4)
ldc1 $f23, (4 * 36 + 8 * 23)($4)
ldc1 $f24, (4 * 36 + 8 * 24)($4)
ldc1 $f25, (4 * 36 + 8 * 25)($4)
ldc1 $f26, (4 * 36 + 8 * 26)($4)
ldc1 $f27, (4 * 36 + 8 * 27)($4)
ldc1 $f28, (4 * 36 + 8 * 28)($4)
ldc1 $f29, (4 * 36 + 8 * 29)($4)
ldc1 $f30, (4 * 36 + 8 * 30)($4)
ldc1 $f31, (4 * 36 + 8 * 31)($4)
#endif
#endif
// restore hi and lo
lw $8, (4 * 33)($4)
mthi $8
lw $8, (4 * 34)($4)
mtlo $8
// r0 is zero
lw $1, (4 * 1)($4)
lw $2, (4 * 2)($4)
lw $3, (4 * 3)($4)
// skip a0 for now
lw $5, (4 * 5)($4)
lw $6, (4 * 6)($4)
lw $7, (4 * 7)($4)
lw $8, (4 * 8)($4)
lw $9, (4 * 9)($4)
lw $10, (4 * 10)($4)
lw $11, (4 * 11)($4)
lw $12, (4 * 12)($4)
lw $13, (4 * 13)($4)
lw $14, (4 * 14)($4)
lw $15, (4 * 15)($4)
lw $16, (4 * 16)($4)
lw $17, (4 * 17)($4)
lw $18, (4 * 18)($4)
lw $19, (4 * 19)($4)
lw $20, (4 * 20)($4)
lw $21, (4 * 21)($4)
lw $22, (4 * 22)($4)
lw $23, (4 * 23)($4)
lw $24, (4 * 24)($4)
lw $25, (4 * 25)($4)
lw $26, (4 * 26)($4)
lw $27, (4 * 27)($4)
lw $28, (4 * 28)($4)
lw $29, (4 * 29)($4)
lw $30, (4 * 30)($4)
// load new pc into ra
lw $31, (4 * 32)($4)
// jump to ra, load a0 in the delay slot
jr $31
lw $4, (4 * 4)($4)
.set pop
#elif defined(__mips64)
//
// void libunwind::Registers_mips_newabi::jumpto()
//
// On entry:
// thread state pointer is in a0 ($4)
//
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind21Registers_mips_newabi6jumptoEv)
.set push
.set noat
.set noreorder
.set nomacro
#ifdef __mips_hard_float
ldc1 $f0, (8 * 35)($4)
ldc1 $f1, (8 * 36)($4)
ldc1 $f2, (8 * 37)($4)
ldc1 $f3, (8 * 38)($4)
ldc1 $f4, (8 * 39)($4)
ldc1 $f5, (8 * 40)($4)
ldc1 $f6, (8 * 41)($4)
ldc1 $f7, (8 * 42)($4)
ldc1 $f8, (8 * 43)($4)
ldc1 $f9, (8 * 44)($4)
ldc1 $f10, (8 * 45)($4)
ldc1 $f11, (8 * 46)($4)
ldc1 $f12, (8 * 47)($4)
ldc1 $f13, (8 * 48)($4)
ldc1 $f14, (8 * 49)($4)
ldc1 $f15, (8 * 50)($4)
ldc1 $f16, (8 * 51)($4)
ldc1 $f17, (8 * 52)($4)
ldc1 $f18, (8 * 53)($4)
ldc1 $f19, (8 * 54)($4)
ldc1 $f20, (8 * 55)($4)
ldc1 $f21, (8 * 56)($4)
ldc1 $f22, (8 * 57)($4)
ldc1 $f23, (8 * 58)($4)
ldc1 $f24, (8 * 59)($4)
ldc1 $f25, (8 * 60)($4)
ldc1 $f26, (8 * 61)($4)
ldc1 $f27, (8 * 62)($4)
ldc1 $f28, (8 * 63)($4)
ldc1 $f29, (8 * 64)($4)
ldc1 $f30, (8 * 65)($4)
ldc1 $f31, (8 * 66)($4)
#endif
// restore hi and lo
ld $8, (8 * 33)($4)
mthi $8
ld $8, (8 * 34)($4)
mtlo $8
// r0 is zero
ld $1, (8 * 1)($4)
ld $2, (8 * 2)($4)
ld $3, (8 * 3)($4)
// skip a0 for now
ld $5, (8 * 5)($4)
ld $6, (8 * 6)($4)
ld $7, (8 * 7)($4)
ld $8, (8 * 8)($4)
ld $9, (8 * 9)($4)
ld $10, (8 * 10)($4)
ld $11, (8 * 11)($4)
ld $12, (8 * 12)($4)
ld $13, (8 * 13)($4)
ld $14, (8 * 14)($4)
ld $15, (8 * 15)($4)
ld $16, (8 * 16)($4)
ld $17, (8 * 17)($4)
ld $18, (8 * 18)($4)
ld $19, (8 * 19)($4)
ld $20, (8 * 20)($4)
ld $21, (8 * 21)($4)
ld $22, (8 * 22)($4)
ld $23, (8 * 23)($4)
ld $24, (8 * 24)($4)
ld $25, (8 * 25)($4)
ld $26, (8 * 26)($4)
ld $27, (8 * 27)($4)
ld $28, (8 * 28)($4)
ld $29, (8 * 29)($4)
ld $30, (8 * 30)($4)
// load new pc into ra
ld $31, (8 * 32)($4)
// jump to ra, load a0 in the delay slot
jr $31
ld $4, (8 * 4)($4)
.set pop
#elif defined(__sparc__)
//
// void libunwind::Registers_sparc_o32::jumpto()
//
// On entry:
// thread_state pointer is in o0
//
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv)
ta 3
ldd [%o0 + 64], %l0
ldd [%o0 + 72], %l2
ldd [%o0 + 80], %l4
ldd [%o0 + 88], %l6
ldd [%o0 + 96], %i0
ldd [%o0 + 104], %i2
ldd [%o0 + 112], %i4
ldd [%o0 + 120], %i6
ld [%o0 + 60], %o7
jmp %o7
nop
#endif
#endif /* !defined(__USING_SJLJ_EXCEPTIONS__) */
NO_EXEC_STACK_DIRECTIVE
|
fygar256/axl | 461 | hello.s | .export _hello,_start,len
.org 0x401000
section .text
_start:
_hello:
mov edx, 0
mov eax, 1 ; sys_write (01)
mov edi, 1 ; stdout (01)
mov edx,len: ; length (13)
movq rsi, msg ; address
syscall
mov edi, 0 ; return 0
mov eax, 60 ; sys_exit
syscall
msg: .ascii "hello, world\n"
len: .equ $$ - msg
endsection
|
Gabeperson/sm213_interpreter | 2,027 | program.s | .pos 0x1000
start: #setup
ld $stacktop, r6
gpc $6, r6
j main
halt
main:
deca r5 # allocate 4 bytes
st r6, (r5) # store ra on stack
ld $-128, r0 # allocate 128 bytes on stack
add r0, r5 # cont.
deca r5 # allocate 4 bytes on stack
ld $str1, r0 # r0 = str1
st r0, (r5) # load str1 ptr to the stack
gpc $6, r6 # setup ra
j print # jump to print
inca r5 # dealloc 4 bytes (str1 ptr)
ld $0, r0 # load 0 to r0
mov r5, r1 # r1 = stackptr
ld $256, r2 # load 256 to r2
sys $0 # read data (stdin, buffer=stackptr, size=256)
mov r0, r4 # r4 = read bytes
deca r5 # allocate 4 bytes on stack
ld $str2, r0 # load str2 ptr to r0
st r0, (r5) # push str2 to stack
gpc $6, r6 # call print on str2
j print # cont.
inca r5 # dealloc str2 ptr
ld $1, r0 # r0 = 1
mov r5, r1 # r1 = stackptr
mov r4, r2 # r2 = # bytes read
sys $1 # write user input string bytes to stdout
ld $128, r0 # load 128 to r0
add r0, r5 # deallocate 128 bytes off stack
ld (r5), r6 # return
inca r5
j (r6)
print:
ld (r5), r0 # pull top value off stack (str ptr)
ld 4(r0), r1 # r1 = beginning of str buffer
ld (r0), r2 # r2 = length of str buffer
ld $1, r0 # r0 = stdout
sys $1 # print string to stdout
j (r6)
.pos 0x1800
proof:
deca r5 # allocate stack memory
ld $str3, r0 # load str3 ptr to r0
st r0, (r5) # store str3 part onto stack
gpc $6, r6 # call print
j print
halt
.pos 0x2000
str1:
.long 30
.long _str1
_str1:
.long 0x57656c63
.long 0x6f6d6521
.long 0x20506c65
.long 0x61736520
.long 0x656e7465
.long 0x72206120
.long 0x6e616d65
.long 0x3a0a0000
str2:
.long 11
.long _str2
_str2:
.long 0x476f6f64
.long 0x206c7563
.long 0x6b2c2000
str3:
.long 43
.long _str3
_str3:
.long 0x54686520
.long 0x73656372
.long 0x65742070
.long 0x68726173
.long 0x65206973
.long 0x20227371
.long 0x7565616d
.long 0x69736820
.long 0x6f737369
.long 0x66726167
.long 0x65220a00
.pos 0x4000
stack:
.long 0
.long 0
stacktop:
.long 0
|
garasubo/my-pico-rt | 384 | rt/src/asm.s | .cpu cortex-m0plus
.thumb
.section .text
.syntax unified
.global asm_execute_process
asm_execute_process:
push {r4, r5, r6, r7, lr}
mov r4, r8
mov r5, r9
mov r6, r10
mov r7, r11
push {r4, r5, r6, r7}
msr psp, r0
svc 0
mrs r0, psp
pop {r4, r5, r6, r7}
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
pop {r4, r5, r6, r7, pc}
|
garrettjoecox/2ship2harkinianLegacy | 1,742 | tools/fado/ovl_En_Hs_reloc.s | .section .ovl
# ovl_En_Hs2OverlayInfo
.word _ovl_En_Hs2SegmentTextSize
.word _ovl_En_Hs2SegmentDataSize
.word _ovl_En_Hs2SegmentRoDataSize
.word _ovl_En_Hs2SegmentBssSize
.word 28 # relocCount
# TEXT RELOCS
.word 0x45000084 # R_MIPS_HI16 0x000084 .data
.word 0x4600008C # R_MIPS_LO16 0x00008C .data
.word 0x450000B4 # R_MIPS_HI16 0x0000B4 .rodata
.word 0x460000BC # R_MIPS_LO16 0x0000BC .rodata
.word 0x450000C0 # R_MIPS_HI16 0x0000C0 func_80A6F1A4
.word 0x460000C4 # R_MIPS_LO16 0x0000C4 func_80A6F1A4
.word 0x450001DC # R_MIPS_HI16 0x0001DC func_80A6F1A4
.word 0x460001E0 # R_MIPS_LO16 0x0001E0 func_80A6F1A4
.word 0x4500022C # R_MIPS_HI16 0x00022C func_80A6F164
.word 0x46000230 # R_MIPS_LO16 0x000230 func_80A6F164
.word 0x44000238 # R_MIPS_26 0x000238 func_80A6F0B4
.word 0x450003D0 # R_MIPS_HI16 0x0003D0 .rodata
.word 0x460003D8 # R_MIPS_LO16 0x0003D8 .rodata
.word 0x45000460 # R_MIPS_HI16 0x000460 .data
.word 0x46000464 # R_MIPS_LO16 0x000464 .data
.word 0x4500049C # R_MIPS_HI16 0x00049C EnHs2_OverrideLimbDraw
.word 0x460004B4 # R_MIPS_LO16 0x0004B4 EnHs2_OverrideLimbDraw
.word 0x450004A0 # R_MIPS_HI16 0x0004A0 EnHs2_PostLimbDraw
.word 0x460004B0 # R_MIPS_LO16 0x0004B0 EnHs2_PostLimbDraw
# DATA RELOCS
.word 0x82000010 # R_MIPS_32 0x000010 EnHs2_Init
.word 0x82000014 # R_MIPS_32 0x000014 EnHs2_Destroy
.word 0x82000018 # R_MIPS_32 0x000018 EnHs2_Update
.word 0x8200001C # R_MIPS_32 0x00001C EnHs2_Draw
# RODATA RELOCS
.word 0xC2000020 # R_MIPS_32 0x000020 .text
.word 0xC2000024 # R_MIPS_32 0x000024 .text
.word 0xC2000028 # R_MIPS_32 0x000028 .text
.word 0xC200002C # R_MIPS_32 0x00002C .text
.word 0xC2000030 # R_MIPS_32 0x000030 .text
.word 0
.word 0
.word 0x00000090 # ovl_En_Hs2OverlayInfoOffset
|
garrettjoecox/2ship2harkinianLegacy | 53 | tools/asm-processor/tests/line-continuation-separate-file.s | .rdata
label: .asciiz "1\n\
2", \
"34", "56"
|
Gaurav-Shah05/rustos | 3,233 | kern/src/init/init.s | // #define EL0 0b00
// #define EL1 0b01
// #define EL2 0b10
// #define EL3 0b11
.section .text.init
.global _start
_start:
// read cpu affinity, start core 0, halt rest
mrs x1, MPIDR_EL1
and x1, x1, #3
cbz x1, setup
halt:
// core affinity != 0, halt it
wfe
b halt
setup:
// store the desired EL1 stack pointer in x1
adr x1, _start
// read the current exception level into x0 (ref: C5.2.1)
mrs x0, CurrentEL
and x0, x0, #0b1100
lsr x0, x0, #2
switch_to_el2:
// switch to EL2 if we're in EL3. otherwise switch to EL1
cmp x0, 0b11 // EL3
bne switch_to_el1
// set-up SCR_EL3 (bits 0, 4, 5, 7, 8, 10) (A53: 4.3.42)
mov x2, #0x5b1
msr SCR_EL3, x2
// set-up SPSR and PL switch! (bits 0, 3, 6, 7, 8, 9) (ref: C5.2.20)
mov x2, #0x3c9
msr SPSR_EL3, x2
adr x2, switch_to_el1
msr ELR_EL3, x2
eret
switch_to_el1:
// switch to EL1 if we're not already in EL1. otherwise continue with start
cmp x0, 0b01 // EL1
beq set_stack
// set the stack-pointer for EL1
msr SP_EL1, x1
// enable CNTP for EL1/EL0 (ref: D7.5.2, D7.5.13)
// NOTE: This doesn't actually enable the counter stream.
mrs x0, CNTHCTL_EL2
orr x0, x0, #0b11
msr CNTHCTL_EL2, x0
msr CNTVOFF_EL2, xzr
// enable AArch64 in EL1 (A53: 4.3.36)
mov x0, #(1 << 31) // Enable AArch64 for EL1
orr x0, x0, #(1 << 1) // RES1 on A-53
msr HCR_EL2, x0
mrs x0, HCR_EL2
// enable floating point and SVE (SIMD) (A53: 4.3.38, 4.3.34)
msr CPTR_EL2, xzr // don't trap accessing SVE registers
mrs x0, CPACR_EL1
orr x0, x0, #(0b11 << 20)
msr CPACR_EL1, x0
// Set SCTLR to known state (RES1: 11, 20, 22, 23, 28, 29) (A53: 4.3.30)
mov x2, #0x0800
movk x2, #0x30d0, lsl #16
msr SCTLR_EL1, x2
// set up exception handlers
// FIXME: load `_vectors` addr into appropriate register (guide: 10.4)
// change execution level to EL1 (ref: C5.2.19)
mov x2, #0x3c5
msr SPSR_EL2, x2
// FIXME: Return to EL1 at `set_stack`.
set_stack:
// set the current stack pointer
mov sp, x1
// zero_bss:
// // load the start address and number of bytes in BSS section
// ldr x1, =__bss_start
// ldr x2, =__bss_length
// zero_bss_loop:
// // zero out the BSS section, 64-bits at a time
// cbz x2, go_kmain
// str xzr, [x1], #8
// sub x2, x2, #8
// cbnz x2, zero_bss_loop
go_kmain:
// jump to kmain, which shouldn't return. halt if it does
bl kinit
b halt
context_save:
// FIXME: Save the remaining context to the stack.
.global context_restore
context_restore:
// FIXME: Restore the context from the stack.
ret
// #define HANDLER(source, kind) \
// .align 7; \
// stp lr, x0, [SP, #-16]!; \
// mov x0, ##source; \
// movk x0, ##kind, LSL #16; \
// bl context_save; \
// ldp lr, x0, [SP], #16; \
// eret
.align 11
_vectors:
// FIXME: Setup the 16 exception vectors.
|
Gaurav-Shah05/rustos | 418 | boot/src/init/init.s | .section .text.init
.global _start
_start:
// read cpu affinity, start core 0, halt rest
mrs x1, mpidr_el1
and x1, x1, #3
cbz x1, 2f
1:
// core affinity != 0, halt it
wfe
b 1b
2:
// set the stack to start before our boot code
adr x1, _start
mov sp, x1
// jump to kinit, which shouldn't return. halt if it does
bl kinit
b 1b
|
GeminiCarrie/rust-sgx-sdk | 1,851 | sgx_trts/src/asm/xsave.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "xsave.S"
.section .nipd,"aw"
XSAVE_ENABLED:
.int 0
.macro DO_XSAVEC
.byte 0x48, 0x0f, 0xc7, 0x21
.endm
.macro DO_XRSTOR
.byte 0x48, 0x0f, 0xae, 0x29
.endm
.macro DO_FXSAVE
.byte 0x48, 0x0f, 0xae, 0x01
.endm
.macro DO_FXRSTOR
.byte 0x48, 0x0f, 0xae, 0x09
.endm
.section .nipx,"ax",@progbits
DECLARE_LOCAL_FUNC restore_xregs
mov %rdi, %rcx
lea_pic XSAVE_ENABLED, %rax
movl (%rax), %eax
cmpl $0, %eax
jz 1f
SET_XSAVE_MASK
DO_XRSTOR
jmp 2f
1:
DO_FXRSTOR
2:
ret
DECLARE_LOCAL_FUNC save_xregs
mov %rdi, %rcx
lea_pic XSAVE_ENABLED, %rax
fwait
movl (%rax), %eax
cmpl $0, %eax
jz 1f
SET_XSAVE_MASK
DO_XSAVEC
jmp 2f
1:
DO_FXSAVE
2:
ret
.section .text,"ax",@progbits
DECLARE_LOCAL_FUNC get_xsave_enabled
lea_pic XSAVE_ENABLED, %rcx
xor %rax, %rax
movl (%rcx), %eax
ret
DECLARE_LOCAL_FUNC set_xsave_enabled
lea_pic XSAVE_ENABLED, %rax
movl %edi, (%rax)
ret
|
GeminiCarrie/rust-sgx-sdk | 1,954 | sgx_trts/src/asm/cet.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "cet.S"
.ifdef __CET__
.macro _CET_ENDBR
endbr64
.endm
.macro _CET_NOTRACK
notrack
.endm
.else
.macro _CET_ENDBR
.endm
.macro _CET_NOTRACK
.endm
.endif
.equ NT_GNU_PROPERTY_TYPE_0, 0x5
.equ GNU_PROPERTY_X86_FEATURE_1_AND, 0xc0000002
.equ SECTION_ALIGNMENT, 0x3
.equ GNU_PROPERTY_X86_FEATURE_1_IBT, 0x1
.equ GNU_PROPERTY_X86_FEATURE_1_SHSTK, 0x2
.equ GNU_PROPERTY_X86_FEATURE_1_CET, (GNU_PROPERTY_X86_FEATURE_1_IBT | GNU_PROPERTY_X86_FEATURE_1_SHSTK)
.pushsection ".note.gnu.property", "a"
.p2align SECTION_ALIGNMENT /* section alignment */
.long 1f - 0f /* name size (not including padding) */
.long 4f - 1f /* desc size (not including padding) */
.long NT_GNU_PROPERTY_TYPE_0 /* type NT_GNU_PROPERTY_TYPE_0*/
0: .asciz "GNU" /* name */
1: .long GNU_PROPERTY_X86_FEATURE_1_AND /* pr_type */
.long 3f - 2f /* pr_datasz */
2: .long GNU_PROPERTY_X86_FEATURE_1_CET /* cet feature bits*/
3: .p2align SECTION_ALIGNMENT
4:
.popsection |
GeminiCarrie/rust-sgx-sdk | 1,262 | sgx_trts/src/asm/metadata.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "metadata.S"
.equ METADATA_SIZE, 0x500
.section ".note.sgxmeta", "", @note
.p2align 2 /* section alignment */
.long 1f - 0f /* name size (not including padding) */
.long 2f - 1f /* desc size (not including padding) */
.long 0x01 /* type */
0: .asciz "sgx_metadata" /* name */
1: .fill METADATA_SIZE, 1, 0 /* desc - stand for metadata which is initialized with 0 */
2: .p2align 2
|
GeminiCarrie/rust-sgx-sdk | 16,317 | sgx_trts/src/asm/pic.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "pic.S"
.section absolute
.global __ImageBase
__ImageBase:
.equ SE_GUARD_PAGE_SHIFT, 16
.equ SE_GUARD_PAGE_SIZE, (1 << SE_GUARD_PAGE_SHIFT)
.equ RED_ZONE_SIZE, 128
.equ STATIC_STACK_SIZE, 2656
.equ OCMD_ERET, -1
.equ last_sp, (SE_WORDSIZE * 1)
.equ stack_base_addr, (SE_WORDSIZE * 2)
.equ stack_limit_addr, (SE_WORDSIZE * 3)
.equ first_ssa_gpr, (SE_WORDSIZE * 4)
.equ xsave_size, (SE_WORDSIZE * 7)
.equ self_addr, 0
.equ stack_guard, (SE_WORDSIZE * 5)
/* SSA GPR */
.equ ssa_sp_t, 32
.equ ssa_sp_u, 144
.equ ssa_bp_u, 152
.equ ssa_exit_info, 160
.equ EXIT_INFO_VALID, 0x80000000
/* OCALL command */
.equ OCALL_FLAG, 0x04F434944
.equ RDRAND_RETRY_TIMES, 10
.equ ENCLAVE_INIT_NOT_STARTED, 0
.equ ENCLAVE_INIT_IN_PROGRESS, 1
.equ ENCLAVE_INIT_DONE, 2
.equ ENCLAVE_CRASHED, 3
.section .nipx,"ax",@progbits
/*
* ---------------------------------------------------------------------
* Get the address of Tds
* ---------------------------------------------------------------------
*/
DECLARE_LOCAL_FUNC get_tds
READ_TD_DATA self_addr
ret
/*
* ---------------------------------------------------------------------
* Get the value of stack_guard
* ---------------------------------------------------------------------
*/
DECLARE_LOCAL_FUNC get_stack_guard
READ_TD_DATA stack_guard
ret
/*
* ---------------------------------------------------------------------
* Function: enclave_entry
* The entry point of the enclave.
*
* Registers:
* XAX - TCS.CSSA
* XBX - the address of a TCS
* XCX - the address of the instruction following the EENTER
* XDI - the reason of entering the enclave
* XSI - the pointer to the marshalling structure
*/
.global _start
DECLARE_GLOBAL_FUNC enclave_entry
/*
* ----------------------------------------------------------------------
* Dispatch code according to CSSA and the reason of EENTER
* eax > 0 - exception handler
* edi >= 0 - ecall
* edi == -1 - do_init_enclave
* edi == -2 - oret
* Registers
* No need to use any register during the dispatch
* ----------------------------------------------------------------------
*/
_start:
.cfi_startproc
/* Clear unused general registers */
xor %rdx, %rdx
add %rdx, %rdx /* OF = SF = AF = CF = 0; ZF = PF = 1 */
cld /* DF = 0 */
xor %r8, %r8
xor %r9, %r9
xor %r10, %r10
xor %r11, %r11
xor %r12, %r12
xor %r13, %r13
xor %r14, %r14
xor %r15, %r15
/* switch to trusted stack */
cmp $0, %rax
jne .Ldo_handler /* handle exception state */
/* xor %rdx, %rdx rdx is cssa, make sure it is 0 */
READ_TD_DATA last_sp
cmp $0, %rax
jne .Lswitch_stack
GET_STACK_BASE %rbx
sub $STATIC_STACK_SIZE, %rax /* give space for static stack */
.Lswitch_stack:
xchg %rsp, %rax
push %rcx
push %rbp
.cfi_def_cfa_offset 2 * SE_WORDSIZE
.cfi_offset rbp, -2 * SE_WORDSIZE
mov %rsp, %rbp
.cfi_def_cfa_register rbp
CLEAN_XFLAGS
/* Save the registers */
sub $(6*SE_WORDSIZE), %rsp
mov %rax, -1*SE_WORDSIZE(%rbp) /* rsp_u */
mov %rdx, -3*SE_WORDSIZE(%rbp) /* cssa */
mov %rbx, -4*SE_WORDSIZE(%rbp) /* TCS */
mov %rsi, -5*SE_WORDSIZE(%rbp) /* rsi */
mov %rdi, -6*SE_WORDSIZE(%rbp) /* rdi */
/* clean extended feature registers */
sub $(4*SE_WORDSIZE), %rsp
call get_synthetic_state_ptr /* lea_pic SYNTHETIC_STATE, %rdi */
mov %rax, %rdi
call restore_xregs
lfence
add $(4*SE_WORDSIZE), %rsp
/* switch to C code */
mov -6*SE_WORDSIZE(%rbp), %rdi /* index */
mov -5*SE_WORDSIZE(%rbp), %rsi /* ms */
mov -4*SE_WORDSIZE(%rbp), %rdx /* TCS */
mov -3*SE_WORDSIZE(%rbp), %rcx /* cssa */
call enter_enclave
mov %rax, %rbx
.Lexit_enclave:
/* clean extended feature registers */
call get_synthetic_state_ptr /* lea_pic SYNTHETIC_STATE, %rdi */
mov %rax, %rdi
call restore_xregs
lfence
/* set xdi and xsi */
mov $OCMD_ERET, %rdi
mov %rbx, %rsi
/* restore stack */
mov -1*SE_WORDSIZE(%rbp), %rdx /* rdx: rsp_u */
mov %rbp, %rsp
pop %rbp /* rbp_u */
pop %rbx /* ret_u */
mov %rdx, %rsp /* rsp_u */
.Lclear_and_exit_enclave:
/* Clear all GPRs, except rax, rbx, rdi and rsi */
xor %rcx, %rcx
xor %rdx, %rdx
xor %r8, %r8
xor %r9, %r9
xor %r10, %r10
xor %r11, %r11
xor %r12, %r12
xor %r13, %r13
xor %r14, %r14
xor %r15, %r15
/* Set status flags to pre-defined values */
add %rdx, %rdx /* OF = SF = AF = CF = 0; ZF = PF = 1 */
cld /* DF = 0 */
/* EEXIT */
mov $SE_EEXIT, %rax /* EEXIT leaf */
ENCLU
/* Should not come here */
ud2
.Ldo_handler:
mov %rax, %rdx /* rdx: cssa */
GET_STACK_BASE %rbx
jmp .Lswitch_stack
/* Should not come here */
ud2
.cfi_endproc
/*
* -------------------------------------------------------------------------
* SgxStatus __do_ocall(unsigned int index, void *ms);
*
* Function: __do_ocall
* The entry point of the enclave
* Parameters:
* func_addr - target function address
* ms - marshalling structure
*
* Stack: (same as do_oret)
* bottom of stack ->
* -----------------
* | ECALL/OCALL |
* previous TD.last_sp -> | frames |
* -----------------
* | ECALL frame |
* | do_ocall param 2| 3
* | do_ocall param 1| 2
* |do_ocall ret_addr| 1
* | xbp | 0 + xbp
* | .... |
* | xsave buffer |
* | .... |
* | xsave pointer | 19
* | ocall_depth | 18
* | reserved | 17
* | reserved | 16
* | reserved | 15
* | rbx | 14
* | rsi | 13
* | rdi | 12
* | rbp | 11
* | r12 | 10
* | r13 | 9
* | r14 | 8
* | r15 | 7
* | prev TD.last_sp | 6
* | ocall_index | 5
* | OCALL FLAG | 4
* | shadow | 3
* | shadow | 2
* | shadow | 1
* TD.last_sp -> | shadow | 0 + xsp
* -----------------
* -------------------------------------------------------------------------
*/
DECLARE_LOCAL_FUNC __do_ocall
/*
* 8 for GPR, 1 for TD.last_sp, 1 for ocall_index
* 1 for OCALL_FLAG, 4 for shadow space.
* Stack Pointer is 16-byte aligned under x86_64.
*/
push %rbp
mov %rsp, %rbp
/* save parameters in stack */
mov %rdi, 2*SE_WORDSIZE(%rbp)
mov %rsi, 3*SE_WORDSIZE(%rbp)
/* save and clean extended feature registers */
READ_TD_DATA xsave_size
sub %rax, %rsp /* allocate buffer to save xregs */
mov $0x3f, %rax
not %rax
and %rax, %rsp /* xsave requires 64 byte aligned */
mov %rsp, %rcx # xsave pointer
sub $(20*SE_WORDSIZE), %rsp /* 20 slots for GPRs and other info */
mov %rcx, SE_WORDSIZE*19(%rsp) /* addr for xsave */
/* save non-volatile registers, except xsp */
mov %rbx, SE_WORDSIZE*14(%rsp)
mov %rsi, SE_WORDSIZE*13(%rsp)
mov %rdi, SE_WORDSIZE*12(%rsp)
mov %rbp, SE_WORDSIZE*11(%rsp)
mov %r12, SE_WORDSIZE*10(%rsp)
mov %r13, SE_WORDSIZE* 9(%rsp)
mov %r14, SE_WORDSIZE* 8(%rsp)
mov %r15, SE_WORDSIZE* 7(%rsp)
/* save and clean extended feature registers */
mov SE_WORDSIZE*19(%rsp), %rdi /* xsave pointer */
READ_TD_DATA xsave_size
mov %rax, %rcx
shr $2, %rcx /* xsave size in dword */
xor %rax, %rax
cld
rep stos %eax, %es:(%rdi)
mov SE_WORDSIZE*19(%rsp), %rdi # xsave pointer
mov %rdi, (%rsp)
call save_xregs
call get_synthetic_state_ptr /* lea_pic SYNTHETIC_STATE, %rdi */
mov %rax, %rdi
mov %rdi, (%rsp)
call restore_xregs
lfence
/* set rdi and rsi using the input parameters */
mov SE_WORDSIZE*12(%rsp), %rdi
mov SE_WORDSIZE*13(%rsp), %rsi
/* save ocall index to the stack */
mov $OCALL_FLAG, %rax
mov %rax, SE_WORDSIZE*4(%rsp) /* save OCALL_FLAG */
mov %rdi, SE_WORDSIZE*5(%rsp) /* save ocall_index */
/*
* save the inside stack context
* push TD.last_sp
* set TD.last_sp = xsp
*/
READ_TD_DATA self_addr
mov %rax, %rbx
/* call update_ocall_lastsp */
mov %rsp, %rdi
call update_ocall_lastsp /* rax: tds.last_sp */
mov SE_WORDSIZE*12(%rsp), %rdi /* restore rdi */
mov SE_WORDSIZE*13(%rsp), %rsi /* restore rdi */
/* restore outside stack context */
mov first_ssa_gpr(%rbx), %rdx
mov ssa_bp_u(%rdx), %rbp
mov ssa_sp_u(%rdx), %rsp
/*
* set EEXIT registers
* return address can be read from the ECALL frame:
* TD.last_sp ->
* -------------
* | ret_addr |
* | xbp_u |
* | xsp_u |
* | ... |
*/
mov -1*SE_WORDSIZE(%rax), %rbx /* return address */
mov $SE_EEXIT, %rax /* EEXIT leaf */
/* Clear all GPRs, except rax, rbx, rdi, and rsi*/
xor %rcx, %rcx
xor %rdx, %rdx
xor %r8, %r8
xor %r9, %r9
xor %r10, %r10
xor %r11, %r11
xor %r12, %r12
xor %r13, %r13
xor %r14, %r14
xor %r15, %r15
/* Set status flags to pre-defined values */
add %rdx, %rdx /* OF = SF = AF = CF = 0; ZF = PF = 1 */
cld /* DF = 0 */
ENCLU
/*
* ------------------------------------------------------------------
* this function is the wrapper of do_ocall, which is used to
* stick ocall bridge and proxy frame together
* ------------------------------------------------------------------
*/
DECLARE_LOCAL_FUNC do_ocall
.cfi_startproc
push %rbp
.cfi_def_cfa_offset 2*SE_WORDSIZE
.cfi_offset rbp,-2*SE_WORDSIZE
mov %rsp, %rbp
.cfi_def_cfa_register rbp
sub $(4*SE_WORDSIZE), %rsp
call __do_ocall
leave
ret
.cfi_endproc
DECLARE_GLOBAL_FUNC asm_oret
mov %rsp, %rbx
mov %rdi, SE_WORDSIZE(%rsp)
mov %rsi, 2*SE_WORDSIZE(%rsp)
mov SE_WORDSIZE(%rbx), %rsp /* restore thread_data.last_sp */
/* restore extended feature registers */
mov 19*SE_WORDSIZE(%rsp), %rdi
call restore_xregs
/* memset_s */
xor %rax, %rax
mov 11*SE_WORDSIZE(%rsp), %rcx
sub %rdi, %rcx
sub $SE_WORDSIZE, %rcx
shr $2, %rcx
cld
rep stos %eax,%es:(%rdi)
mov 2*SE_WORDSIZE(%rbx), %rax /* ocall return value */
mov 7*SE_WORDSIZE(%rsp), %r15
mov 8*SE_WORDSIZE(%rsp), %r14
mov 9*SE_WORDSIZE(%rsp), %r13
mov 10*SE_WORDSIZE(%rsp), %r12
mov 11*SE_WORDSIZE(%rsp), %rbp
mov 12*SE_WORDSIZE(%rsp), %rdi
mov 13*SE_WORDSIZE(%rsp), %rsi
mov 14*SE_WORDSIZE(%rsp), %rbx
mov %rbp, %rsp
pop %rbp
ret
/* should not come here */
ud2
/*
* -------------------------------------------------------------------------
* do_ereport(target_info, report_data, report);
* EREPORT: rbx - the address of TARGETINFO;
* rcx - the address of REPORTDATA;
* rdx - the address where REPORT is outputted
* return value:
* zero: success
* non-zero: failure
* -------------------------------------------------------------------------
*/
/*
.global Lereport_inst
DECLARE_LOCAL_FUNC do_ereport
SE_PROLOG
mov $SE_EREPORT, %rax
clc
Lereport_inst:
ENCLU
setc %al
SE_EPILOG
*/
/*
* -------------------------------------------------------------------------
* extern "C" void abort(void) __attribute__(__noreturn__);
* -------------------------------------------------------------------------
*/
/*
DECLARE_GLOBAL_FUNC abort
lea_pic ENCLAVE_STATE, %rax
movl $ENCLAVE_CRASHED, (%rax)
ud2
*/
/*
* -------------------------------------------------------------------------
* extern "C" __attribute__((regparm(1))) void continue_execution(sgx_exception_info_t *info);
* -------------------------------------------------------------------------
*/
DECLARE_LOCAL_FUNC continue_execution
mov %rdi, %rcx
mov SE_WORDSIZE*0(%rcx), %rax
push %rax /* push rax */
mov SE_WORDSIZE*1(%rcx), %rax
push %rax /* push xcx */
mov SE_WORDSIZE*4(%rcx), %rax /* xax: xsp */
/* x86_64 requires a 128-bytes red zone. We need to allocate buffer to avoid touching the red zone. */
sub $(SE_WORDSIZE + RED_ZONE_SIZE), %rax /* allocate buffer to skip red zone and save xip */
/* restore registers except xax, xcx, xsp */
mov SE_WORDSIZE*2(%rcx), %rdx
mov SE_WORDSIZE*3(%rcx), %rbx
mov SE_WORDSIZE*5(%rcx), %rbp
mov SE_WORDSIZE*6(%rcx), %rsi
mov SE_WORDSIZE*7(%rcx), %rdi
mov SE_WORDSIZE*8(%rcx), %r8
mov SE_WORDSIZE*9(%rcx), %r9
mov SE_WORDSIZE*10(%rcx), %r10
mov SE_WORDSIZE*11(%rcx), %r11
mov SE_WORDSIZE*12(%rcx), %r12
mov SE_WORDSIZE*13(%rcx), %r13
mov SE_WORDSIZE*14(%rcx), %r14
mov SE_WORDSIZE*15(%rcx), %r15
push SE_WORDSIZE*16(%rcx)
popf /* make sure the following instructions do not affect flags */
mov SE_WORDSIZE*17(%rcx), %rcx
/* do not setup the new stack until info is not needed any more
* otherwise, info will be overwritten
*/
mov %rcx, (%rax) /* save xip to the new stack */
pop %rcx /* restore xcx */
pop %rsp /* xsp: xax */
xchg %rax, %rsp
ret $(RED_ZONE_SIZE) /* pop xip and red zone (if any) */
/*
DECLARE_GLOBAL_FUNC lfence
pop %r11
lfence
jmp *%r11
DECLARE_GLOBAL_FUNC mfence
pop %r11
mfence
jmp *%r11
*/
|
GeminiCarrie/rust-sgx-sdk | 1,970 | sgx_trts/src/asm/macro.S | /* Licensed to the Apache Software Foundation (ASF) under one
or more contributor license agreements. See the NOTICE file
distributed with this work for additional information
regarding copyright ownership. The ASF licenses this file
to you under the Apache License, Version 2.0 (the
"License"); you may not use this file except in compliance
with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing,
software distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
KIND, either express or implied. See the License for the
specific language governing permissions and limitations
under the License.. */
.file "macro.S"
.equ SE_WORDSIZE, 8
.equ SE_EREPORT, 0
.equ SE_EGETKEY, 1
.equ SE_EENTER, 2
.equ SE_EEXIT, 4
.equ SE_EACCEPT, 5
.equ SE_EMODPE, 6
.equ SE_EVERIFYREPORT2, 8
.equ SE_ECREATE, 0
.equ SE_EADD, 1
.equ SE_EINIT, 2
.equ SE_EREMOVE, 3
.macro DECLARE_GLOBAL_FUNC name
.globl \name
.type \name, @function
\name:
_CET_ENDBR
.endm
.macro DECLARE_LOCAL_FUNC name
.globl \name
.hidden \name
.type \name, @function
\name:
_CET_ENDBR
.endm
.macro SE_PROLOG
.cfi_startproc
push %rbx
push %rcx
push %rdx
movq %rdi, %rbx
movq %rsi, %rcx
.endm
/*******************************************************************/
.macro SE_EPILOG
pop %rdx
pop %rcx
pop %rbx
ret
.cfi_endproc
.endm
.macro lea_pic symbol, reg
lea \symbol(%rip), \reg
.endm
.equ FLAGS_CLEAR_BITS, 0x40000
.macro CLEAN_XFLAGS
pushfq
notq (%rsp)
orq $FLAGS_CLEAR_BITS, (%rsp)
notq (%rsp)
popfq
.endm
.macro GET_STACK_BASE tcs
mov \tcs, %rax
sub $SE_GUARD_PAGE_SIZE, %rax
.endm
|
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