repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
Engineer-Guild-Hackathon/team-18-app | 6,242 | executorch/backends/xnnpack/third-party/XNNPACK/src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neon-ld128-acc2.S | // clang-format off
// Auto-generated file. Do not edit!
// Template: src/f32-gemm/1x8-aarch64-neon-ld128-acc2.S.in
// Generator: tools/xngen
//
// Copyright 2023 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.
#include "src/xnnpack/assembly.h"
# void xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neon_ld128_acc2(
# size_t mr, (x0) - unused. mr = 1
# size_t nc, x1
# size_t kc, x2 / x0
# const float* a, x3
# size_t a_stride, (x4) - unused
# const void* w, x5
# float* c, x6
# size_t cm_stride, (x7) - unused
# size_t cn_stride, [sp] -> x14
# const xnn_f32_minmax_params* params) [sp + 8] -> (x8)
# d8-d15, x19-x30 need to be preserved if used. x18 is reserved by the OS.
# Register usage
# A0 x3 v0
# B x5 v20 v21 v22 v23
# C0 x6 v16 v17 v18 v19 v26 v27 v28 v29
# Clamp v4 v5
BEGIN_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neon_ld128_acc2
# Load cn_stride, params pointer
LDP x14, x8, [sp]
# Load min/max values
LD2R {v4.4s, v5.4s}, [x8]
0:
# Load initial bias from w into accumulators
LDP q16, q17, [x5], 32
SUBS x0, x2, 16 // k = kc - 16
MOVI v18.4s, 0 // second set of C for pipelining FMUL
MOVI v19.4s, 0
MOVI v26.4s, 0
MOVI v27.4s, 0
MOVI v28.4s, 0
MOVI v29.4s, 0
# Is there at least 4 floats (16 bytes)
B.LO 3f
# Main loop - 4 floats of A (16 bytes)
1:
LDR q22, [x5], 16
FADD v16.4s, v16.4s, v26.4s
FADD v17.4s, v17.4s, v27.4s
FADD v18.4s, v18.4s, v28.4s
FADD v19.4s, v19.4s, v29.4s
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
LDR q0, [x3], 16
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMUL v26.4s, v20.4s, v0.s[0]
FMUL v27.4s, v21.4s, v0.s[0]
FMUL v28.4s, v22.4s, v0.s[1]
FMUL v29.4s, v23.4s, v0.s[1]
LDR q22, [x5], 16
FADD v16.4s, v16.4s, v26.4s
FADD v17.4s, v17.4s, v27.4s
FADD v18.4s, v18.4s, v28.4s
FADD v19.4s, v19.4s, v29.4s
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
SUBS x0, x0, 16
FMUL v26.4s, v20.4s, v0.s[2]
FMUL v27.4s, v21.4s, v0.s[2]
FMUL v28.4s, v22.4s, v0.s[3]
FMUL v29.4s, v23.4s, v0.s[3]
B.HS 1b
FADD v16.4s, v16.4s, v26.4s
FADD v17.4s, v17.4s, v27.4s
FADD v18.4s, v18.4s, v28.4s
FADD v19.4s, v19.4s, v29.4s
# Is there a remainder?- 2 float of A (8 bytes)
TBNZ x0, 3, 4f
# Is there a remainder?- 1 float of A (4 bytes)
TBNZ x0, 2, 5f
2:
# Load Scale
LDP q24, q25, [x5], 32
FADD v16.4s, v16.4s, v18.4s
FADD v17.4s, v17.4s, v19.4s
# Scale
FMUL v16.4s, v16.4s, v24.4s
FMUL v17.4s, v17.4s, v25.4s
SUBS x1, x1, 8
# Clamp
FMAX v16.4s, v16.4s, v4.4s
FMAX v17.4s, v17.4s, v4.4s
FMIN v16.4s, v16.4s, v5.4s
FMIN v17.4s, v17.4s, v5.4s
# Store full 1 x 8
B.LO 6f
STP q16, q17, [x6]
ADD x6, x6, x14
SUB x3, x3, x2 // a0 -= kc
B.HI 0b
RET
3:
TBZ x0, 3, 5f
# Remainder- 2 float of A (4 bytes)
4:
LDR d0, [x3], 8
LDR q22, [x5], 16 // 16 QC8 weights
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMUL v26.4s, v20.4s, v0.s[0]
FMUL v27.4s, v21.4s, v0.s[0]
FMUL v28.4s, v22.4s, v0.s[1]
FMUL v29.4s, v23.4s, v0.s[1]
FADD v16.4s, v16.4s, v26.4s
FADD v17.4s, v17.4s, v27.4s
FADD v18.4s, v18.4s, v28.4s
FADD v19.4s, v19.4s, v29.4s
TBZ x0, 2, 2b
5:
# Remainder- 1 float of A (4 bytes)
LDR s0, [x3], 4
LDR d21, [x5], 8 // 8 QC8 weights
SXTL v21.8h, v21.8b
SXTL v20.4s, v21.4h
SXTL2 v21.4s, v21.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
FMUL v26.4s, v20.4s, v0.s[0]
FMUL v27.4s, v21.4s, v0.s[0]
FADD v16.4s, v16.4s, v26.4s
FADD v17.4s, v17.4s, v27.4s
B 2b
# Store odd channels
6:
TBZ x1, 2, 7f
STR q16, [x6], 16
MOV v16.16b, v17.16b
7:
TBZ x1, 1, 8f
STR d16, [x6], 8
DUP d16, v16.d[1]
8:
TBZ x1, 0, 9f
STR s16, [x6]
9:
RET
END_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neon_ld128_acc2
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
Engineer-Guild-Hackathon/team-18-app | 3,938 | executorch/backends/xnnpack/third-party/XNNPACK/src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-prfm.S | // clang-format off
// Auto-generated file. Do not edit!
// Template: src/f32-gemm/1x8-aarch64-neonfma-ld64.S.in
// Generator: tools/xngen
//
// Copyright 2020 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.
#include "src/xnnpack/assembly.h"
# void xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_prfm(
# size_t mr, (x0) - unused. mr = 1
# size_t nc, x1
# size_t kc, x2 / x0
# const float* a, x3
# size_t a_stride, (x4) - unused
# const void* w, x5
# float* c, x6
# size_t cm_stride, (x7) - unused
# size_t cn_stride, [sp] -> x14
# const xnn_f32_minmax_params* params) [sp + 8] -> (x8)
# d8-d15, x19-x30 need to be preserved if used. x18 is reserved by the OS.
# Register usage
# A0 x3 v0
# B x5 v20 v21 v22 v23
# C0 x6 v16 v17
# Clamp v4 v5
BEGIN_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_prfm
# Load cn_stride, params pointer
LDP x14, x8, [sp]
# Load min/max values
LD2R {v4.4s, v5.4s}, [x8]
0:
# Load initial bias from w into accumulators
LDP q16, q17, [x5], 32
SUBS x0, x2, 8 // k = kc - 8
# Is there at least 2 floats (8 bytes)
B.LO 3f
PRFM PLDL1KEEP, [x5]
PRFM PLDL1KEEP, [x5, 64]
PRFM PLDL1KEEP, [x5, 128]
PRFM PLDL1KEEP, [x5, 192]
# Main loop - 2 floats of A (8 bytes)
1:
LDR d0, [x3], 8
LDR q22, [x5], 16 // 16 QC8 weights
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
SUBS x0, x0, 8
FMLA v16.4s, v20.4s, v0.s[0]
PRFM PLDL1KEEP, [x5, 128]
FMLA v17.4s, v21.4s, v0.s[0]
FMLA v16.4s, v22.4s, v0.s[1]
FMLA v17.4s, v23.4s, v0.s[1]
B.HS 1b
# Is there a remainder?- 1 float of A (4 bytes)
TBNZ x0, 2, 3f
2:
# Scale
LDP q20, q21, [x5], 32
FMUL v16.4s, v16.4s, v20.4s
FMUL v17.4s, v17.4s, v21.4s
SUBS x1, x1, 8
# Clamp
FMAX v16.4s, v16.4s, v4.4s
FMAX v17.4s, v17.4s, v4.4s
FMIN v16.4s, v16.4s, v5.4s
FMIN v17.4s, v17.4s, v5.4s
# Store full 1 x 8
B.LO 4f
STP q16, q17, [x6]
ADD x6, x6, x14
SUB x3, x3, x2 // a0 -= kc
B.HI 0b
RET
3:
# Remainder- 1 float of A (4 bytes)
LDR s0, [x3], 4
LDR d21, [x5], 8 // 8 QC8 weights
SXTL v21.8h, v21.8b
SXTL v20.4s, v21.4h
SXTL2 v21.4s, v21.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v17.4s, v21.4s, v0.s[0]
B 2b
# Store odd channels
4:
TBZ x1, 2, 5f
STR q16, [x6], 16
MOV v16.16b, v17.16b
5:
TBZ x1, 1, 6f
STR d16, [x6], 8
DUP d16, v16.d[1]
6:
TBZ x1, 0, 7f
STR s16, [x6]
7:
RET
END_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_prfm
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
Engineer-Guild-Hackathon/team-18-app | 5,734 | executorch/backends/xnnpack/third-party/XNNPACK/src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc4.S | // clang-format off
// Auto-generated file. Do not edit!
// Template: src/f32-gemm/1x8-aarch64-neonfma-ld64-acc4.S.in
// Generator: tools/xngen
//
// Copyright 2020 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.
#include "src/xnnpack/assembly.h"
# void xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_acc4(
# size_t mr, (x0) - unused. mr = 1
# size_t nc, x1
# size_t kc, x2 / x0
# const float* a, x3
# size_t a_stride, (x4) - unused
# const void* w, x5
# float* c, x6
# size_t cm_stride, (x7) - unused
# size_t cn_stride, [sp] -> x14
# const xnn_f32_minmax_params* params) [sp + 8] -> (x8)
# d8-d15, x19-x30 need to be preserved if used. x18 is reserved by the OS.
# Register usage
# A0 x3 v0 v1
# B x5 v20 v21 v22 v23
# C0 x6 v16 v17 v18 v19 v26 v27 v28 v29
# Clamp v4 v5
BEGIN_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_acc4
# Load cn_stride, params pointer
LDP x14, x8, [sp]
# Load min/max values
LD2R {v4.4s, v5.4s}, [x8]
0:
# Load initial bias from w into accumulators
LDP q16, q17, [x5], 32
SUBS x0, x2, 16 // k = kc - 16
MOVI v18.4s, 0 // four sets of C for pipelining FMLA
MOVI v19.4s, 0
# Is there at least 4 floats (16 bytes)
B.LO 3f
MOVI v26.4s, 0
MOVI v27.4s, 0
MOVI v28.4s, 0
MOVI v29.4s, 0
# Main loop - 4 floats of A (16 bytes)
1:
LDR d0, [x3], 8
LDR q22, [x5], 16 // 16 QC8 weights
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v17.4s, v21.4s, v0.s[0]
FMLA v18.4s, v22.4s, v0.s[1]
FMLA v19.4s, v23.4s, v0.s[1]
LDR d1, [x3], 8
LDR q22, [x5], 16 // 16 QC8 weights
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
SUBS x0, x0, 16
FMLA v26.4s, v20.4s, v1.s[0]
FMLA v27.4s, v21.4s, v1.s[0]
FMLA v28.4s, v22.4s, v1.s[1]
FMLA v29.4s, v23.4s, v1.s[1]
B.HS 1b
FADD v16.4s, v16.4s, v26.4s
FADD v18.4s, v18.4s, v28.4s
FADD v17.4s, v17.4s, v27.4s
FADD v19.4s, v19.4s, v29.4s
# Is there a remainder?- 2 float of A (8 bytes)
TBNZ x0, 3, 4f
# Is there a remainder?- 1 float of A (4 bytes)
TBNZ x0, 2, 5f
2:
# Load Scale
LDP q24, q25, [x5], 32
FADD v16.4s, v16.4s, v18.4s
FADD v17.4s, v17.4s, v19.4s
# Scale
FMUL v16.4s, v16.4s, v24.4s
FMUL v17.4s, v17.4s, v25.4s
SUBS x1, x1, 8
# Clamp
FMAX v16.4s, v16.4s, v4.4s
FMAX v17.4s, v17.4s, v4.4s
FMIN v16.4s, v16.4s, v5.4s
FMIN v17.4s, v17.4s, v5.4s
# Store full 1 x 8
B.LO 6f
STP q16, q17, [x6]
ADD x6, x6, x14
SUB x3, x3, x2 // a0 -= kc
B.HI 0b
RET
3:
TBZ x0, 3, 5f
# Remainder- 2 float of A (4 bytes)
4:
LDR d0, [x3], 8
LDR q22, [x5], 16 // 16 QC8 weights
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v17.4s, v21.4s, v0.s[0]
FMLA v18.4s, v22.4s, v0.s[1]
FMLA v19.4s, v23.4s, v0.s[1]
TBZ x0, 2, 2b
5:
# Remainder- 1 float of A (4 bytes)
LDR s0, [x3], 4
LDR d21, [x5], 8 // 8 QC8 weights
SXTL v21.8h, v21.8b
SXTL v20.4s, v21.4h
SXTL2 v21.4s, v21.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v17.4s, v21.4s, v0.s[0]
B 2b
# Store odd channels
6:
TBZ x1, 2, 7f
STR q16, [x6], 16
MOV v16.16b, v17.16b
7:
TBZ x1, 1, 8f
STR d16, [x6], 8
DUP d16, v16.d[1]
8:
TBZ x1, 0, 9f
STR s16, [x6]
9:
RET
END_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_acc4
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
Engineer-Guild-Hackathon/team-18-app | 10,122 | executorch/backends/xnnpack/third-party/XNNPACK/src/f32-qc8w-gemm/gen/f32-qc8w-gemm-4x8-minmax-asm-aarch64-neonfma-ld128.S | // clang-format off
// Auto-generated file. Do not edit!
// Template: src/f32-gemm/4x8-aarch64-neonfma-ld128.S.in
// Generator: tools/xngen
//
// Copyright 2019 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.
#include "src/xnnpack/assembly.h"
# void xnn_f32_qc8w_gemm_minmax_ukernel_4x8__asm_aarch64_neonfma_ld128(
# size_t mr, x0
# size_t nc, x1
# size_t kc, x2 / x0
# const float* a, x3
# size_t a_stride, x4
# const void* w, x5
# float* c, x6
# size_t cm_stride, x7
# size_t cn_stride, [sp] -> x14
# const xnn_f32_minmax_params* params) [sp + 8] -> (x8)
# d8-d15, x19-x30 need to be preserved if used. x18 is reserved by the OS.
# Register usage
# A0 x3 v0
# A1 x11 v1
# A2 x12 v2
# A3 x4 v3
# B x5 v20 v24 v21 v25 v22 v26 v23 v27
# C0 x6 v16 v17
# C1 x9 v18 v19
# C2 x10 v28 v29
# C3 x7 v30 v31
# Clamp v4 v5
BEGIN_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_4x8__asm_aarch64_neonfma_ld128
# Load cn_stride, params pointer
LDP x14, x8, [sp]
# Load min/max values
LD2R {v4.4s, v5.4s}, [x8]
# Clamp A and C pointers
CMP x0, 2 // if mr < 2
ADD x11, x3, x4 // a1 = a0 + a_stride
ADD x9, x6, x7 // c1 = c0 + cm_stride
CSEL x11, x3, x11, LO // a1 = a0
CSEL x9, x6, x9, LO // c1 = c0
ADD x12, x11, x4 // a2 = a1 + a_stride
ADD x10, x9, x7 // c2 = c1 + cm_stride
// if mr <= 2
CSEL x12, x11, x12, LS // a2 = a1
CSEL x10, x9, x10, LS // c2 = c1
CMP x0, 4 // if mr < 4
ADD x4, x12, x4 // a3 = a2 + a_stride
ADD x7, x10, x7 // c3 = c2 + cm_stride
CSEL x4, x12, x4, LO // a3 = a2
CSEL x7, x10, x7, LO // c3 = c2
0:
# Load initial bias from w into accumulators
LDP q16, q17, [x5], 32
MOV v18.16b, v16.16b
MOV v19.16b, v17.16b
MOV v28.16b, v16.16b
MOV v29.16b, v17.16b
MOV v30.16b, v16.16b
MOV v31.16b, v17.16b
# Is there at least 4 floats (16 bytes)?
SUBS x0, x2, 16 // k = kc - 16
B.LO 3f
# Main loop - 4 floats of A (16 bytes)
1:
LDR q0, [x3], 16
LDP q20, q22, [x5], 32 // 32 QC8 weights
SXTL v24.8h, v20.8b
SXTL2 v25.8h, v20.16b
SXTL v20.4s, v24.4h
SXTL2 v24.4s, v24.8h
SXTL v21.4s, v25.4h
SXTL2 v25.4s, v25.8h
SCVTF v20.4s, v20.4s
SCVTF v24.4s, v24.4s
SXTL v26.8h, v22.8b
SXTL2 v27.8h, v22.16b
LDR q1, [x11], 16
LDR q2, [x12], 16
LDR q3, [x4], 16
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v18.4s, v20.4s, v1.s[0]
FMLA v28.4s, v20.4s, v2.s[0]
FMLA v30.4s, v20.4s, v3.s[0]
SCVTF v21.4s, v21.4s
SCVTF v25.4s, v25.4s
SXTL v22.4s, v26.4h
SXTL2 v26.4s, v26.8h
FMLA v17.4s, v24.4s, v0.s[0]
FMLA v19.4s, v24.4s, v1.s[0]
FMLA v29.4s, v24.4s, v2.s[0]
FMLA v31.4s, v24.4s, v3.s[0]
SCVTF v22.4s, v22.4s
SCVTF v26.4s, v26.4s
SXTL v23.4s, v27.4h
SXTL2 v27.4s, v27.8h
FMLA v16.4s, v21.4s, v0.s[1]
FMLA v18.4s, v21.4s, v1.s[1]
FMLA v28.4s, v21.4s, v2.s[1]
FMLA v30.4s, v21.4s, v3.s[1]
SCVTF v23.4s, v23.4s
SCVTF v27.4s, v27.4s
FMLA v17.4s, v25.4s, v0.s[1]
FMLA v19.4s, v25.4s, v1.s[1]
FMLA v29.4s, v25.4s, v2.s[1]
FMLA v31.4s, v25.4s, v3.s[1]
FMLA v16.4s, v22.4s, v0.s[2]
FMLA v18.4s, v22.4s, v1.s[2]
FMLA v28.4s, v22.4s, v2.s[2]
FMLA v30.4s, v22.4s, v3.s[2]
FMLA v17.4s, v26.4s, v0.s[2]
FMLA v19.4s, v26.4s, v1.s[2]
FMLA v29.4s, v26.4s, v2.s[2]
FMLA v31.4s, v26.4s, v3.s[2]
FMLA v16.4s, v23.4s, v0.s[3]
FMLA v18.4s, v23.4s, v1.s[3]
FMLA v28.4s, v23.4s, v2.s[3]
FMLA v30.4s, v23.4s, v3.s[3]
SUBS x0, x0, 16
FMLA v17.4s, v27.4s, v0.s[3]
FMLA v19.4s, v27.4s, v1.s[3]
FMLA v29.4s, v27.4s, v2.s[3]
FMLA v31.4s, v27.4s, v3.s[3]
B.HS 1b
TST x0, 15
B.NE 3f
2:
# Scale
LDP q20, q24, [x5], 32
FMUL v16.4s, v16.4s, v20.4s
FMUL v17.4s, v17.4s, v24.4s
FMUL v18.4s, v18.4s, v20.4s
FMUL v19.4s, v19.4s, v24.4s
FMUL v28.4s, v28.4s, v20.4s
FMUL v29.4s, v29.4s, v24.4s
FMUL v30.4s, v30.4s, v20.4s
FMUL v31.4s, v31.4s, v24.4s
# Clamp
FMAX v16.4s, v16.4s, v4.4s
SUBS x1, x1, 8
FMAX v17.4s, v17.4s, v4.4s
FMAX v18.4s, v18.4s, v4.4s
FMAX v19.4s, v19.4s, v4.4s
FMAX v28.4s, v28.4s, v4.4s
FMAX v29.4s, v29.4s, v4.4s
FMAX v30.4s, v30.4s, v4.4s
FMAX v31.4s, v31.4s, v4.4s
FMIN v16.4s, v16.4s, v5.4s
FMIN v17.4s, v17.4s, v5.4s
FMIN v18.4s, v18.4s, v5.4s
FMIN v19.4s, v19.4s, v5.4s
FMIN v28.4s, v28.4s, v5.4s
FMIN v29.4s, v29.4s, v5.4s
FMIN v30.4s, v30.4s, v5.4s
FMIN v31.4s, v31.4s, v5.4s
# Store full 4 x 8
B.LO 5f
ST1 {v16.16b, v17.16b}, [x6], x14
SUB x3, x3, x2 // a0 -= kc
ST1 {v18.16b, v19.16b}, [x9], x14
SUB x11, x11, x2 // a1 -= kc
ST1 {v28.16b, v29.16b}, [x10], x14
SUB x12, x12, x2 // a2 -= kc
ST1 {v30.16b, v31.16b}, [x7], x14
SUB x4, x4, x2 // a3 -= kc
B.HI 0b
RET
# Remainder- 2 floats of A (8 bytes)
3:
# Is there a remainder?- 2 floats of A (8 bytes)
TBZ x0, 3, 4f
# Remainder- 2 floats of A (8 bytes)
LDR q20, [x5], 16 // 16 QC8 weights
SXTL v24.8h, v20.8b
SXTL2 v25.8h, v20.16b
SXTL v20.4s, v24.4h
SXTL2 v24.4s, v24.8h
SXTL v21.4s, v25.4h
SXTL2 v25.4s, v25.8h
SCVTF v20.4s, v20.4s
SCVTF v24.4s, v24.4s
SCVTF v21.4s, v21.4s
SCVTF v25.4s, v25.4s
LDR d0, [x3], 8
LDR d1, [x11], 8
LDR d2, [x12], 8
LDR d3, [x4], 8
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v18.4s, v20.4s, v1.s[0]
FMLA v28.4s, v20.4s, v2.s[0]
FMLA v30.4s, v20.4s, v3.s[0]
FMLA v17.4s, v24.4s, v0.s[0]
FMLA v19.4s, v24.4s, v1.s[0]
FMLA v29.4s, v24.4s, v2.s[0]
FMLA v31.4s, v24.4s, v3.s[0]
FMLA v16.4s, v21.4s, v0.s[1]
FMLA v18.4s, v21.4s, v1.s[1]
FMLA v28.4s, v21.4s, v2.s[1]
FMLA v30.4s, v21.4s, v3.s[1]
FMLA v17.4s, v25.4s, v0.s[1]
FMLA v19.4s, v25.4s, v1.s[1]
FMLA v29.4s, v25.4s, v2.s[1]
FMLA v31.4s, v25.4s, v3.s[1]
# Is there a remainder?- 1 float of A (4 bytes)
TBZ x0, 2, 2b
# Remainder- 1 float of A (4 bytes)
4:
# Remainder- 2 floats of A (8 bytes)
LDR d20, [x5], 8 // 8 QC8 weights
SXTL v24.8h, v20.8b
SXTL v20.4s, v24.4h
SXTL2 v24.4s, v24.8h
SCVTF v20.4s, v20.4s
SCVTF v24.4s, v24.4s
LDR s0, [x3], 4
LDR s1, [x11], 4
LDR s2, [x12], 4
LDR s3, [x4], 4
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v18.4s, v20.4s, v1.s[0]
FMLA v28.4s, v20.4s, v2.s[0]
FMLA v30.4s, v20.4s, v3.s[0]
FMLA v17.4s, v24.4s, v0.s[0]
FMLA v19.4s, v24.4s, v1.s[0]
FMLA v29.4s, v24.4s, v2.s[0]
FMLA v31.4s, v24.4s, v3.s[0]
B 2b
# Store odd width
5:
TBZ x1, 2, 6f
STR q16, [x6], 16
MOV v16.16b, v17.16b
STR q18, [x9], 16
MOV v18.16b, v19.16b
STR q28, [x10], 16
MOV v28.16b, v29.16b
STR q30, [x7], 16
MOV v30.16b, v31.16b
6:
TBZ x1, 1, 7f
STR d16, [x6], 8
STR d18, [x9], 8
DUP d16, v16.d[1]
DUP d18, v18.d[1]
STR d28, [x10], 8
STR d30, [x7], 8
DUP d28, v28.d[1]
DUP d30, v30.d[1]
7:
TBZ x1, 0, 8f
STR s16, [x6]
STR s18, [x9]
STR s28, [x10]
STR s30, [x7]
8:
RET
END_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_4x8__asm_aarch64_neonfma_ld128
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
Engineer-Guild-Hackathon/team-18-app | 3,976 | executorch/backends/xnnpack/third-party/XNNPACK/src/f32-qc8w-gemm/gen/f32-qc8w-gemm-1x8-minmax-asm-aarch64-neonfma-ld64-acc2.S | // clang-format off
// Auto-generated file. Do not edit!
// Template: src/f32-gemm/1x8-aarch64-neonfma-ld64-acc2.S.in
// Generator: tools/xngen
//
// Copyright 2020 Google LLC
//
// This source code is licensed under the BSD-style license found in the
// LICENSE file in the root directory of this source tree.
#include "src/xnnpack/assembly.h"
# void xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_acc2(
# size_t mr, (x0) - unused. mr = 1
# size_t nc, x1
# size_t kc, x2 / x0
# const float* a, x3
# size_t a_stride, (x4) - unused
# const void* w, x5
# float* c, x6
# size_t cm_stride, (x7) - unused
# size_t cn_stride, [sp] -> x14
# const xnn_f32_minmax_params* params) [sp + 8] -> (x8)
# d8-d15, x19-x30 need to be preserved if used. x18 is reserved by the OS.
# Register usage
# A0 x3 v0
# B x5 v20 v21 v22 v23
# C0 x6 v16 v17 v18 v19
# Clamp v4 v5
BEGIN_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_acc2
# Load cn_stride, params pointer
LDP x14, x8, [sp]
# Load min/max values
LD2R {v4.4s, v5.4s}, [x8]
0:
# Load initial bias from w into accumulators
LDP q16, q17, [x5], 32
SUBS x0, x2, 8 // k = kc - 8
MOVI v18.4s, 0 // second set of C for pipelining FMLA
MOVI v19.4s, 0
# Is there at least 2 floats (8 bytes)
B.LO 3f
# Main loop - 2 floats of A (8 bytes)
1:
LDR d0, [x3], 8
LDR q22, [x5], 16 // 16 QC8 weights
SXTL v21.8h, v22.8b
SXTL2 v23.8h, v22.16b
SXTL v20.4s, v21.4h
SXTL v22.4s, v23.4h
SXTL2 v21.4s, v21.8h
SXTL2 v23.4s, v23.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
SCVTF v22.4s, v22.4s
SCVTF v23.4s, v23.4s
SUBS x0, x0, 8
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v17.4s, v21.4s, v0.s[0]
FMLA v18.4s, v22.4s, v0.s[1]
FMLA v19.4s, v23.4s, v0.s[1]
B.HS 1b
# Is there a remainder?- 1 float of A (4 bytes)
TBNZ x0, 2, 3f
2:
# Load Scale
LDP q24, q25, [x5], 32
FADD v16.4s, v16.4s, v18.4s
FADD v17.4s, v17.4s, v19.4s
# Scale
FMUL v16.4s, v16.4s, v24.4s
FMUL v17.4s, v17.4s, v25.4s
SUBS x1, x1, 8
# Clamp
FMAX v16.4s, v16.4s, v4.4s
FMAX v17.4s, v17.4s, v4.4s
FMIN v16.4s, v16.4s, v5.4s
FMIN v17.4s, v17.4s, v5.4s
# Store full 1 x 8
B.LO 4f
STP q16, q17, [x6]
ADD x6, x6, x14
SUB x3, x3, x2 // a0 -= kc
B.HI 0b
RET
3:
# Remainder- 1 float of A (4 bytes)
LDR s0, [x3], 4
LDR d21, [x5], 8 // 8 QC8 weights
SXTL v21.8h, v21.8b
SXTL v20.4s, v21.4h
SXTL2 v21.4s, v21.8h
SCVTF v20.4s, v20.4s
SCVTF v21.4s, v21.4s
FMLA v16.4s, v20.4s, v0.s[0]
FMLA v17.4s, v21.4s, v0.s[0]
B 2b
# Store odd channels
4:
TBZ x1, 2, 5f
STR q16, [x6], 16
MOV v16.16b, v17.16b
5:
TBZ x1, 1, 6f
STR d16, [x6], 8
DUP d16, v16.d[1]
6:
TBZ x1, 0, 7f
STR s16, [x6]
7:
RET
END_FUNCTION xnn_f32_qc8w_gemm_minmax_ukernel_1x8__asm_aarch64_neonfma_ld64_acc2
#ifdef __ELF__
.section ".note.GNU-stack","",%progbits
#endif
|
Enuwbt/cooperative_green_thread | 763 | asm/context.S | #define SET_CONTEXT set_context
#define SWITCH_CONTEXT switch_context
.global SET_CONTEXT
.global SWITCH_CONTEXT
SET_CONTEXT:
stp d8, d9, [x0]
stp d10, d11, [x0, #16]
stp d12, d13, [x0, #16 * 2]
stp d14, d15, [x0, #16 * 3]
stp d19, d20, [x0, #16 * 4]
stp x21, x22, [x0, #16 * 5]
stp x23, x24, [x0, #16 * 6]
stp x25, x26, [x0, #16 * 7]
stp x27, x28, [x0, #16 * 8]
mov x1, sp
stp x30, x1, [x0, #16 * 9]
mov x0, 0
ret
SWITCH_CONTEXT:
ldp d8, d9, [x0]
ldp d10, d11, [x0]
ldp d12, d13, [x0]
ldp d14, d15, [x0]
ldp x19, x20, [x0]
ldp x21, x22, [x0]
ldp x23, x24, [x0]
ldp x25, x26, [x0]
ldp x27, x28, [x0]
ldp x30, x2, [x0, #16 * 9]
mov sp, x2
mov x0, 1
ret
|
epiglottis-cartilage/rCore | 1,640 | os/src/trap/trap.S | .altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they have been saved in TrapContext
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it in TrapContext
csrr t2, sscratch
sd t2, 2*8(sp)
# load kernel_satp into t0
ld t0, 34*8(sp)
# load trap_handler into t1
ld t1, 36*8(sp)
# move to kernel_sp
ld sp, 35*8(sp)
# switch to kernel space
csrw satp, t0
sfence.vma
# jump to trap_handler
jr t1
__restore:
# a0: *TrapContext in user space(Constant); a1: user space token
# switch to user space
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
# now sp points to TrapContext in user space, start restoring based on it
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
# restore general purpose registers except x0/sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# back to user stack
ld sp, 2*8(sp)
sret
|
epita-rs/Rustorrent | 44 | src/testsuite/test_material/test1/asm/fibo.S | .section .text
.global fibo
fibo:
ret
|
erod4/Senior-Design | 13,812 | firmware/Core/Startup/startup_stm32g491retx.s | /**
******************************************************************************
* @file startup_stm32g491xx.s
* @author MCD Application Team
* @brief STM32G491xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FDCAN2_IT0_IRQHandler
.word FDCAN2_IT1_IRQHandler
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
|
erod4/Senior-Design | 13,812 | ADC/Core/Startup/startup_stm32g491retx.s | /**
******************************************************************************
* @file startup_stm32g491xx.s
* @author MCD Application Team
* @brief STM32G491xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word RTC_TAMP_LSECSS_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word FDCAN1_IT0_IRQHandler
.word FDCAN1_IT1_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word LPTIM1_IRQHandler
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word 0
.word 0
.word UCPD1_IRQHandler
.word COMP1_2_3_IRQHandler
.word COMP4_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word CRS_IRQHandler
.word SAI1_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FDCAN2_IT0_IRQHandler
.word FDCAN2_IT1_IRQHandler
.word 0
.word 0
.word RNG_IRQHandler
.word LPUART1_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word DMAMUX_OVR_IRQHandler
.word QUADSPI_IRQHandler
.word DMA1_Channel8_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word DMA2_Channel8_IRQHandler
.word CORDIC_IRQHandler
.word FMAC_IRQHandler
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_LSECSS_IRQHandler
.thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak UCPD1_IRQHandler
.thumb_set UCPD1_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_IRQHandler
.thumb_set COMP4_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak DMAMUX_OVR_IRQHandler
.thumb_set DMAMUX_OVR_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak DMA1_Channel8_IRQHandler
.thumb_set DMA1_Channel8_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak DMA2_Channel8_IRQHandler
.thumb_set DMA2_Channel8_IRQHandler,Default_Handler
.weak CORDIC_IRQHandler
.thumb_set CORDIC_IRQHandler,Default_Handler
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
|
eternalcomet/test | 171 | apps/nimbos/c/lib/arch/riscv/crt.S | .text
.globl _start
_start:
.option push
.option norelax
lla gp, __global_pointer$
.option pop
mv a0, sp
and sp, sp, -16
tail __start_main
|
eternalcomet/test | 511 | apps/nimbos/c/lib/arch/riscv/clone.S | // __clone(func, arg, stack)
// a0, a1, a2
// syscall(SYS_clone, stack)
// a7, a0
.global __clone
.hidden __clone
__clone:
andi a2, a2, -16
addi a2, a2, -16
sd a0, 0(a2)
sd a1, 8(a2)
// syscall(SYSCALL_CLONE, newsp)
mv a0, a2
li a7, 56
ecall
beqz a0, 1f
// parent
ret
1:
// child
ld a0, 8(sp)
ld a1, 0(sp)
jalr a1
// syscall(SYSCALL_EXIT, ret)
li a7, 60
ecall
|
eternalcomet/test | 117 | apps/nimbos/c/lib/arch/aarch64/crt.S | .text
.globl _start
_start:
mov x29, #0
mov x30, #0
mov x0, sp
and sp, x0, #-16
b __start_main
|
eternalcomet/test | 434 | apps/nimbos/c/lib/arch/aarch64/clone.S | // __clone(func, arg, stack)
// x0, x1, x2
// syscall(SYS_clone, stack)
// x8, x0
.global __clone
.hidden __clone
__clone:
and x2, x2, #-16
stp x0, x1, [x2, #-16]!
// syscall(SYSCALL_CLONE, newsp)
mov x0, x2
mov x8, #56
svc #0
cbz x0, 1f
// parent
ret
1:
// child
ldp x1, x0, [sp], #16
blr x1
// syscall(SYSCALL_EXIT, ret)
mov x8, #60
svc #0
|
eternalcomet/test | 121 | apps/nimbos/c/lib/arch/x86_64/crt.S | .text
.globl _start
_start:
xor %rbp, %rbp
mov %rsp, %rdi
andq $-16, %rsp
call __start_main
|
eternalcomet/test | 574 | apps/nimbos/c/lib/arch/x86_64/clone.S | // __clone(func, arg, stack)
// rdi, rsi, rdx
// syscall(SYS_clone, stack)
// rax, rdi
.global __clone
.hidden __clone
__clone:
// push arg (%rsi) to stack, set func (%rdi) to %r9
and $-16, %rdx
sub $8, %rdx
mov %rsi, (%rdx)
mov %rdi, %r9
// syscall(SYSCALL_CLONE, newsp)
mov %rdx, %rdi
mov $56, %rax
syscall
test %rax, %rax
jz 1f
// parent
ret
1:
// child
xor %rbp, %rbp
pop %rdi
call *%r9
// syscall(SYSCALL_EXIT, ret)
mov %rax, %rdi
mov $60, %rax
syscall
|
eternalcomet/test | 198 | apps/nimbos/c/lib/arch/loongarch64/crt.S | .section .text.entry
.globl _start
_start:
move $fp, $zero
move $a0, $sp
.weak _DYNAMIC
.hidden _DYNAMIC
la.local $a1, _DYNAMIC
bstrins.d $sp, $zero, 3, 0
b __start_main
|
eternalcomet/test | 961 | apps/nimbos/c/lib/arch/loongarch64/clone.S | #__clone(func, stack, flags, arg, ptid, tls, ctid)
# a0, a1, a2, a3, a4, a5, a6
# sys_clone(flags, stack, ptid, ctid, tls)
# a0, a1, a2, a3, a4
.global __clone
.hidden __clone
.type __clone,@function
__clone:
bstrins.d $a1, $zero, 3, 0 #stack to 16 align
# Save function pointer and argument pointer on new thread stack
addi.d $a1, $a1, -16
st.d $a0, $a1, 0 # save function pointer
st.d $a3, $a1, 8 # save argument pointer
or $a0, $a2, $zero
or $a2, $a4, $zero
or $a3, $a6, $zero
or $a4, $a5, $zero
ori $a7, $zero, 220
syscall 0 # call clone
beqz $a0, 1f # whether child process
jirl $zero, $ra, 0 # parent process return
1:
ld.d $t8, $sp, 0 # function pointer
ld.d $a0, $sp, 8 # argument pointer
jirl $ra, $t8, 0 # call the user's function
ori $a7, $zero, 93
syscall 0 # child process exit
|
eternalcomet/test | 2,095 | .arceos/modules/axhal/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
. = ALIGN(4K);
_etext = .;
}
_srodata = .;
.rodata : ALIGN(4K) {
*(.rodata .rodata.*)
*(.srodata .srodata.*)
*(.sdata2 .sdata2.*)
}
.init_array : ALIGN(0x10) {
__init_array_start = .;
*(.init_array .init_array.*)
__init_array_end = .;
}
. = ALIGN(4K);
_erodata = .;
.data : ALIGN(4K) {
_sdata = .;
*(.data.boot_page_table)
. = ALIGN(4K);
*(.data .data.*)
*(.sdata .sdata.*)
*(.got .got.*)
}
.tdata : ALIGN(0x10) {
_stdata = .;
*(.tdata .tdata.*)
_etdata = .;
}
.tbss : ALIGN(0x10) {
_stbss = .;
*(.tbss .tbss.*)
*(.tcommon)
_etbss = .;
}
. = ALIGN(4K);
_percpu_start = .;
_percpu_end = _percpu_start + SIZEOF(.percpu);
.percpu 0x0 : AT(_percpu_start) {
_percpu_load_start = .;
*(.percpu .percpu.*)
_percpu_load_end = .;
. = _percpu_load_start + ALIGN(64) * %SMP%;
}
. = _percpu_end;
. = ALIGN(4K);
_edata = .;
.bss : AT(.) ALIGN(4K) {
boot_stack = .;
*(.bss.stack)
. = ALIGN(4K);
boot_stack_top = .;
_sbss = .;
*(.bss .bss.*)
*(.sbss .sbss.*)
*(COMMON)
. = ALIGN(4K);
_ebss = .;
}
_ekernel = .;
/DISCARD/ : {
*(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
}
}
SECTIONS {
linkme_IRQ : { *(linkme_IRQ) }
linkm2_IRQ : { *(linkm2_IRQ) }
linkme_PAGE_FAULT : { *(linkme_PAGE_FAULT) }
linkm2_PAGE_FAULT : { *(linkm2_PAGE_FAULT) }
linkme_SYSCALL : { *(linkme_SYSCALL) }
linkm2_SYSCALL : { *(linkm2_SYSCALL) }
linkme_POST_TRAP : { *(linkme_POST_TRAP) }
linkm2_POST_TRAP : { *(linkm2_POST_TRAP) }
axns_resource : { *(axns_resource) }
}
INSERT AFTER .tbss;
|
eternalcomet/undefined-os-final | 171 | apps/nimbos/c/lib/arch/riscv/crt.S | .text
.globl _start
_start:
.option push
.option norelax
lla gp, __global_pointer$
.option pop
mv a0, sp
and sp, sp, -16
tail __start_main
|
eternalcomet/undefined-os-final | 511 | apps/nimbos/c/lib/arch/riscv/clone.S | // __clone(func, arg, stack)
// a0, a1, a2
// syscall(SYS_clone, stack)
// a7, a0
.global __clone
.hidden __clone
__clone:
andi a2, a2, -16
addi a2, a2, -16
sd a0, 0(a2)
sd a1, 8(a2)
// syscall(SYSCALL_CLONE, newsp)
mv a0, a2
li a7, 56
ecall
beqz a0, 1f
// parent
ret
1:
// child
ld a0, 8(sp)
ld a1, 0(sp)
jalr a1
// syscall(SYSCALL_EXIT, ret)
li a7, 60
ecall
|
eternalcomet/undefined-os-final | 117 | apps/nimbos/c/lib/arch/aarch64/crt.S | .text
.globl _start
_start:
mov x29, #0
mov x30, #0
mov x0, sp
and sp, x0, #-16
b __start_main
|
eternalcomet/undefined-os-final | 434 | apps/nimbos/c/lib/arch/aarch64/clone.S | // __clone(func, arg, stack)
// x0, x1, x2
// syscall(SYS_clone, stack)
// x8, x0
.global __clone
.hidden __clone
__clone:
and x2, x2, #-16
stp x0, x1, [x2, #-16]!
// syscall(SYSCALL_CLONE, newsp)
mov x0, x2
mov x8, #56
svc #0
cbz x0, 1f
// parent
ret
1:
// child
ldp x1, x0, [sp], #16
blr x1
// syscall(SYSCALL_EXIT, ret)
mov x8, #60
svc #0
|
eternalcomet/undefined-os-final | 121 | apps/nimbos/c/lib/arch/x86_64/crt.S | .text
.globl _start
_start:
xor %rbp, %rbp
mov %rsp, %rdi
andq $-16, %rsp
call __start_main
|
eternalcomet/undefined-os-final | 574 | apps/nimbos/c/lib/arch/x86_64/clone.S | // __clone(func, arg, stack)
// rdi, rsi, rdx
// syscall(SYS_clone, stack)
// rax, rdi
.global __clone
.hidden __clone
__clone:
// push arg (%rsi) to stack, set func (%rdi) to %r9
and $-16, %rdx
sub $8, %rdx
mov %rsi, (%rdx)
mov %rdi, %r9
// syscall(SYSCALL_CLONE, newsp)
mov %rdx, %rdi
mov $56, %rax
syscall
test %rax, %rax
jz 1f
// parent
ret
1:
// child
xor %rbp, %rbp
pop %rdi
call *%r9
// syscall(SYSCALL_EXIT, ret)
mov %rax, %rdi
mov $60, %rax
syscall
|
eternalcomet/undefined-os-final | 198 | apps/nimbos/c/lib/arch/loongarch64/crt.S | .section .text.entry
.globl _start
_start:
move $fp, $zero
move $a0, $sp
.weak _DYNAMIC
.hidden _DYNAMIC
la.local $a1, _DYNAMIC
bstrins.d $sp, $zero, 3, 0
b __start_main
|
eternalcomet/undefined-os-final | 961 | apps/nimbos/c/lib/arch/loongarch64/clone.S | #__clone(func, stack, flags, arg, ptid, tls, ctid)
# a0, a1, a2, a3, a4, a5, a6
# sys_clone(flags, stack, ptid, ctid, tls)
# a0, a1, a2, a3, a4
.global __clone
.hidden __clone
.type __clone,@function
__clone:
bstrins.d $a1, $zero, 3, 0 #stack to 16 align
# Save function pointer and argument pointer on new thread stack
addi.d $a1, $a1, -16
st.d $a0, $a1, 0 # save function pointer
st.d $a3, $a1, 8 # save argument pointer
or $a0, $a2, $zero
or $a2, $a4, $zero
or $a3, $a6, $zero
or $a4, $a5, $zero
ori $a7, $zero, 220
syscall 0 # call clone
beqz $a0, 1f # whether child process
jirl $zero, $ra, 0 # parent process return
1:
ld.d $t8, $sp, 0 # function pointer
ld.d $a0, $sp, 8 # argument pointer
jirl $ra, $t8, 0 # call the user's function
ori $a7, $zero, 93
syscall 0 # child process exit
|
eternalcomet/test | 2,358 | .arceos/modules/axhal/src/arch/riscv/trap.S | .macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
csrr t0, sepc
csrr t1, sstatus
csrrw t2, sscratch, zero // save sscratch (sp) and zero it
STR t0, sp, 31 // tf.sepc
STR t1, sp, 32 // tf.sstatus
STR t2, sp, 1 // tf.regs.sp
.if \from_user == 1
LDR t0, sp, 2 // load supervisor gp
LDR t1, sp, 3 // load supervisor tp
STR gp, sp, 2 // save user gp and tp
STR tp, sp, 3
mv gp, t0
mv tp, t1
.endif
.endm
.macro RESTORE_REGS, from_user
.if \from_user == 1
LDR t1, sp, 2 // load user gp and tp
LDR t0, sp, 3
STR gp, sp, 2 // save supervisor gp
STR tp, sp, 3 // save supervisor gp and tp
mv gp, t1
mv tp, t0
addi t0, sp, {trapframe_size} // put supervisor sp to scratch
csrw sscratch, t0
.endif
// restore sepc
LDR t0, sp, 31
csrw sepc, t0
// restore sstatus, but don't change FS
LDR t0, sp, 32 // t0 = sstatus to restore
csrr t1, sstatus // t1 = current sstatus
li t2, 0x6000 // t2 = mask for FS
and t1, t1, t2 // t1 = current FS
not t2, t2 // t2 = ~(mask for FS)
and t0, t0, t2 // t0 = sstatus to restore(cleared FS)
or t0, t0, t1 // t0 = sstatus to restore with current FS
csrw sstatus, t0 // restore sstatus
POP_GENERAL_REGS
LDR sp, sp, 1 // load sp from tf.regs.sp
.endm
.section .text
.balign 4
.global trap_vector_base
trap_vector_base:
// sscratch == 0: trap from S mode
// sscratch != 0: trap from U mode
csrrw sp, sscratch, sp // swap sscratch and sp
bnez sp, .Ltrap_entry_u
csrr sp, sscratch // put supervisor sp back
j .Ltrap_entry_s
.Ltrap_entry_s:
SAVE_REGS 0
mv a0, sp
li a1, 0
call riscv_trap_handler
RESTORE_REGS 0
sret
.Ltrap_entry_u:
SAVE_REGS 1
mv a0, sp
li a1, 1
call riscv_trap_handler
RESTORE_REGS 1
sret
|
eternalcomet/test | 2,989 | .arceos/modules/axhal/src/arch/aarch64/trap.S | .macro SAVE_REGS
sub sp, sp, {trapframe_size}
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
stp x10, x11, [sp, 10 * 8]
stp x12, x13, [sp, 12 * 8]
stp x14, x15, [sp, 14 * 8]
stp x16, x17, [sp, 16 * 8]
stp x18, x19, [sp, 18 * 8]
stp x20, x21, [sp, 20 * 8]
stp x22, x23, [sp, 22 * 8]
stp x24, x25, [sp, 24 * 8]
stp x26, x27, [sp, 26 * 8]
stp x28, x29, [sp, 28 * 8]
str x30, [sp, 30 * 8]
mrs x9, sp_el0
mrs x10, tpidr_el0
mrs x11, elr_el1
mrs x12, spsr_el1
stp x9, x10, [sp, 31 * 8]
stp x11, x12, [sp, 33 * 8]
# restore kernel tpidr_el0
mrs x1, tpidrro_el0
msr tpidr_el0, x1
# We may have interrupted userspace, or a guest, or exit-from or
# return-to either of those. So we can't trust sp_el0, and need to
# restore it.
bl {cache_current_task_ptr}
.endm
.macro RESTORE_REGS
# backup kernel tpidr_el0
mrs x1, tpidr_el0
msr tpidrro_el0, x1
ldp x11, x12, [sp, 33 * 8]
ldp x9, x10, [sp, 31 * 8]
msr sp_el0, x9
msr tpidr_el0, x10
msr elr_el1, x11
msr spsr_el1, x12
ldr x30, [sp, 30 * 8]
ldp x28, x29, [sp, 28 * 8]
ldp x26, x27, [sp, 26 * 8]
ldp x24, x25, [sp, 24 * 8]
ldp x22, x23, [sp, 22 * 8]
ldp x20, x21, [sp, 20 * 8]
ldp x18, x19, [sp, 18 * 8]
ldp x16, x17, [sp, 16 * 8]
ldp x14, x15, [sp, 14 * 8]
ldp x12, x13, [sp, 12 * 8]
ldp x10, x11, [sp, 10 * 8]
ldp x8, x9, [sp, 8 * 8]
ldp x6, x7, [sp, 6 * 8]
ldp x4, x5, [sp, 4 * 8]
ldp x2, x3, [sp, 2 * 8]
ldp x0, x1, [sp]
add sp, sp, {trapframe_size}
.endm
.macro INVALID_EXCP, kind, source
.p2align 7
SAVE_REGS
mov x0, sp
mov x1, \kind
mov x2, \source
bl invalid_exception
b .Lexception_return
.endm
.macro HANDLE_SYNC, source
.p2align 7
SAVE_REGS
mov x0, sp
mov x1, \source
bl handle_sync_exception
b .Lexception_return
.endm
.macro HANDLE_IRQ, source
.p2align 7
SAVE_REGS
mov x0, sp
mov x1, \source
bl handle_irq_exception
b .Lexception_return
.endm
.section .text
.p2align 11
.global exception_vector_base
exception_vector_base:
// current EL, with SP_EL0
INVALID_EXCP 0 0
INVALID_EXCP 1 0
INVALID_EXCP 2 0
INVALID_EXCP 3 0
// current EL, with SP_ELx
HANDLE_SYNC 1
HANDLE_IRQ 1
INVALID_EXCP 2 1
INVALID_EXCP 3 1
// lower EL, aarch64
HANDLE_SYNC 2
HANDLE_IRQ 2
INVALID_EXCP 2 2
INVALID_EXCP 3 2
// lower EL, aarch32
INVALID_EXCP 0 3
INVALID_EXCP 1 3
INVALID_EXCP 2 3
INVALID_EXCP 3 3
.Lexception_return:
RESTORE_REGS
eret
|
eternalcomet/test | 1,397 | .arceos/modules/axhal/src/arch/x86_64/syscall.S | .section .text
.code64
syscall_entry:
swapgs // switch to kernel gs
mov gs:[offset __PERCPU_USER_RSP_OFFSET], rsp // save user rsp
mov rsp, gs:[offset __PERCPU_TSS + {tss_rsp0_offset}] // switch to kernel stack
sub rsp, 8 // skip user ss
push gs:[offset __PERCPU_USER_RSP_OFFSET] // user rsp
push r11 // rflags
push {ucode64} // cs
push rcx // rip
sub rsp, 4 * 8 // skip until general registers
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rdi
push rsi
push rbp
push rbx
push rdx
push rcx
push rax
mov rdi, rsp
call x86_syscall_handler
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
add rsp, 9 * 8
mov rcx, [rsp - 5 * 8] // rip
mov r11, [rsp - 3 * 8] // rflags
mov rsp, [rsp - 2 * 8] // user rsp
swapgs
sysretq
|
eternalcomet/test | 1,627 | .arceos/modules/axhal/src/arch/x86_64/trap.S | .equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt vector
jmp .Ltrap_common
.endif
.endm
.macro DEF_TABLE_ENTRY, i
.quad .Ltrap_handler_\i
.endm
.section .text
.code64
_trap_handlers:
.set i, 0
.rept NUM_INT
DEF_HANDLER %i
.set i, i + 1
.endr
.Ltrap_common:
test byte ptr [rsp + 3 * 8], 3 # swap GS if it comes from user space
jz 1f
swapgs
1:
sub rsp, 16 # reserve space for fs_base
push r15
push r14
push r13
push r12
push r11
push r10
push r9
push r8
push rdi
push rsi
push rbp
push rbx
push rdx
push rcx
push rax
mov rdi, rsp
call x86_trap_handler
pop rax
pop rcx
pop rdx
pop rbx
pop rbp
pop rsi
pop rdi
pop r8
pop r9
pop r10
pop r11
pop r12
pop r13
pop r14
pop r15
add rsp, 16 # pop fs_base
test byte ptr [rsp + 3 * 8], 3 # swap GS back if return to user space
jz 2f
swapgs
2:
add rsp, 16 # pop vector, error_code
iretq
.section .rodata
.global trap_handler_table
trap_handler_table:
.set i, 0
.rept NUM_INT
DEF_TABLE_ENTRY %i
.set i, i + 1
.endr
|
eternalcomet/test | 1,791 | .arceos/modules/axhal/src/arch/loongarch64/trap.S | .macro SAVE_REGS, from_user
move $t0, $sp
.if \from_user == 1
csrrd $sp, KSAVE_KSP // restore kernel sp
addi.d $sp, $sp, -{trapframe_size}
STD $tp, $sp, 2
STD $r21, $sp, 21
csrrd $tp, KSAVE_TP
csrrd $r21, KSAVE_R21
.else
addi.d $sp, $sp, -{trapframe_size}
.endif
STD $t0, $sp, 3
csrrd $t0, KSAVE_TEMP
PUSH_GENERAL_REGS
csrrd $t1, LA_CSR_PRMD
csrrd $t2, LA_CSR_ERA
STD $t1, $sp, 32 // prmd
STD $t2, $sp, 33 // era
.endm
.macro RESTORE_REGS, from_user
.if \from_user == 1
csrwr $tp, KSAVE_TP
csrwr $r21, KSAVE_R21
LDD $tp, $sp, 2
LDD $r21, $sp, 21
addi.d $t1, $sp, {trapframe_size}
csrwr $t1, KSAVE_KSP // save kernel sp
.endif
LDD $t1, $sp, 33 // era
LDD $t2, $sp, 32 // prmd
csrwr $t1, LA_CSR_ERA
csrwr $t2, LA_CSR_PRMD
POP_GENERAL_REGS
LDD $sp, $sp, 3
.endm
.section .text
.balign 4096
.global exception_entry_base
exception_entry_base:
csrwr $t0, KSAVE_TEMP
csrrd $t0, LA_CSR_PRMD
andi $t0, $t0, 0x3
bnez $t0, .Lfrom_userspace
.Lfrom_kernel:
SAVE_REGS 0
move $a0, $sp
addi.d $a1, $zero, 0
bl loongarch64_trap_handler
RESTORE_REGS 0
ertn
.Lfrom_userspace:
SAVE_REGS 1
move $a0, $sp
addi.d $a1, $zero, 1
bl loongarch64_trap_handler
RESTORE_REGS 1
ertn
.section .text
.balign 4096
.global handle_tlb_refill
handle_tlb_refill:
csrwr $t0, LA_CSR_TLBRSAVE
csrrd $t0, LA_CSR_PGD
lddir $t0, $t0, 3
lddir $t0, $t0, 2
lddir $t0, $t0, 1
ldpte $t0, 0
ldpte $t0, 1
tlbfill
csrrd $t0, LA_CSR_TLBRSAVE
ertn
|
eternalcomet/test | 1,965 | .arceos/modules/axhal/src/platform/x86_pc/ap_start.S | # Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STARTUP. Thus this code must start at a 4096-byte boundary.
#
# Because this code sets DS to zero, it must sit
# at an address in the low 2^16 bytes.
.equ pa_ap_start32, ap_start32 - ap_start + {start_page_paddr}
.equ pa_ap_gdt, .Lap_tmp_gdt - ap_start + {start_page_paddr}
.equ pa_ap_gdt_desc, .Lap_tmp_gdt_desc - ap_start + {start_page_paddr}
.equ stack_ptr, {start_page_paddr} + 0xff0
.equ entry_ptr, {start_page_paddr} + 0xff8
# 0x6000
.section .text
.code16
.p2align 12
.global ap_start
ap_start:
cli
wbinvd
xor ax, ax
mov ds, ax
mov es, ax
mov ss, ax
mov fs, ax
mov gs, ax
# load the 64-bit GDT
lgdt [pa_ap_gdt_desc]
# switch to protected-mode
mov eax, cr0
or eax, (1 << 0)
mov cr0, eax
# far jump to 32-bit code. 0x8 is code32 segment selector
ljmp 0x8, offset pa_ap_start32
.code32
ap_start32:
mov esp, [stack_ptr]
mov eax, [entry_ptr]
jmp eax
.balign 8
# .type multiboot_header, STT_OBJECT
.Lap_tmp_gdt_desc:
.short .Lap_tmp_gdt_end - .Lap_tmp_gdt - 1 # limit
.long pa_ap_gdt # base
.balign 16
.Lap_tmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Lap_tmp_gdt_end:
# 0x7000
.p2align 12
.global ap_end
ap_end:
|
eternalcomet/test | 4,325 | .arceos/modules/axhal/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.balign 4
.type multiboot_header, STT_OBJECT
multiboot_header:
.int {mb_hdr_magic} # magic: 0x1BADB002
.int {mb_hdr_flags} # flags
.int -({mb_hdr_magic} + {mb_hdr_flags}) # checksum
.int multiboot_header - {offset} # header_addr
.int _skernel - {offset} # load_addr
.int _edata - {offset} # load_end
.int _ebss - {offset} # bss_end_addr
.int _start - {offset} # entry_addr
# Common code in 32-bit, prepare states to enter 64-bit.
.macro ENTRY32_COMMON
# set data segment selectors
mov ax, 0x18
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
# set PAE, PGE bit in CR4
mov eax, {cr4}
mov cr4, eax
# load the temporary page table
lea eax, [.Ltmp_pml4 - {offset}]
mov cr3, eax
# set LME, NXE bit in IA32_EFER
mov ecx, {efer_msr}
mov edx, 0
mov eax, {efer}
wrmsr
# set protected mode, write protect, paging bit in CR0
mov eax, {cr0}
mov cr0, eax
.endm
# Common code in 64-bit
.macro ENTRY64_COMMON
# clear segment selectors
xor ax, ax
mov ss, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
.endm
.code32
bsp_entry32:
lgdt [.Ltmp_gdt_desc - {offset}] # load the temporary GDT
ENTRY32_COMMON
ljmp 0x10, offset bsp_entry64 - {offset} # 0x10 is code64 segment
.code32
.global ap_entry32
ap_entry32:
ENTRY32_COMMON
ljmp 0x10, offset ap_entry64 - {offset} # 0x10 is code64 segment
.code64
bsp_entry64:
ENTRY64_COMMON
# set RSP to boot stack
movabs rsp, offset {boot_stack}
add rsp, {boot_stack_size}
# call rust_entry(magic, mbi)
movabs rax, offset {entry}
call rax
jmp .Lhlt
.code64
ap_entry64:
ENTRY64_COMMON
# set RSP to high address (already set in ap_start.S)
mov rax, {offset}
add rsp, rax
# call rust_entry_secondary(magic)
mov rdi, {mb_magic}
movabs rax, offset {entry_secondary}
call rax
jmp .Lhlt
.Lhlt:
hlt
jmp .Lhlt
.section .rodata
.balign 8
.Ltmp_gdt_desc:
.short .Ltmp_gdt_end - .Ltmp_gdt - 1 # limit
.long .Ltmp_gdt - {offset} # base
.section .data
.balign 16
.Ltmp_gdt:
.quad 0x0000000000000000 # 0x00: null
.quad 0x00cf9b000000ffff # 0x08: code segment (base=0, limit=0xfffff, type=32bit code exec/read, DPL=0, 4k)
.quad 0x00af9b000000ffff # 0x10: code segment (base=0, limit=0xfffff, type=64bit code exec/read, DPL=0, 4k)
.quad 0x00cf93000000ffff # 0x18: data segment (base=0, limit=0xfffff, type=32bit data read/write, DPL=0, 4k)
.Ltmp_gdt_end:
.balign 4096
.Ltmp_pml4:
# 0x0000_0000 ~ 0xffff_ffff
.quad .Ltmp_pdpt_low - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
.zero 8 * 255
# 0xffff_8000_0000_0000 ~ 0xffff_8000_ffff_ffff
.quad .Ltmp_pdpt_high - {offset} + 0x3 # PRESENT | WRITABLE | paddr(tmp_pdpt)
.zero 8 * 255
# FIXME: may not work on macOS using hvf as the CPU does not support 1GB page (pdpe1gb)
.Ltmp_pdpt_low:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
.Ltmp_pdpt_high:
.quad 0x0000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x0)
.quad 0x40000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x4000_0000)
.quad 0x80000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0x8000_0000)
.quad 0xc0000000 | 0x83 # PRESENT | WRITABLE | HUGE_PAGE | paddr(0xc000_0000)
.zero 8 * 508
|
eternalcomet/test | 2,544 | .arceos/tools/raspi4/chainloader/src/_arch/aarch64/cpu/boot.s | // SPDX-License-Identifier: MIT OR Apache-2.0
//
// Copyright (c) 2021-2022 Andre Richter <andre.o.richter@gmail.com>
//--------------------------------------------------------------------------------------------------
// Definitions
//--------------------------------------------------------------------------------------------------
// Load the address of a symbol into a register, PC-relative.
//
// The symbol must lie within +/- 4 GiB of the Program Counter.
//
// # Resources
//
// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html
.macro ADR_REL register, symbol
adrp \register, \symbol
add \register, \register, #:lo12:\symbol
.endm
// Load the address of a symbol into a register, absolute.
//
// # Resources
//
// - https://sourceware.org/binutils/docs-2.36/as/AArch64_002dRelocations.html
.macro ADR_ABS register, symbol
movz \register, #:abs_g2:\symbol
movk \register, #:abs_g1_nc:\symbol
movk \register, #:abs_g0_nc:\symbol
.endm
//--------------------------------------------------------------------------------------------------
// Public Code
//--------------------------------------------------------------------------------------------------
.section .text._start
//------------------------------------------------------------------------------
// fn _start()
//------------------------------------------------------------------------------
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x0, MPIDR_EL1
and x0, x0, {CONST_CORE_ID_MASK}
ldr x1, BOOT_CORE_ID // provided by bsp/__board_name__/cpu.rs
cmp x0, x1
b.ne .L_parking_loop
// If execution reaches here, it is the boot core.
// Initialize DRAM.
ADR_ABS x0, __bss_start
ADR_ABS x1, __bss_end_exclusive
.L_bss_init_loop:
cmp x0, x1
b.eq .L_relocate_binary
stp xzr, xzr, [x0], #16
b .L_bss_init_loop
// Next, relocate the binary.
.L_relocate_binary:
ADR_REL x0, __binary_nonzero_start // The address the binary got loaded to.
ADR_ABS x1, __binary_nonzero_start // The address the binary was linked to.
ADR_ABS x2, __binary_nonzero_end_exclusive
.L_copy_loop:
ldr x3, [x0], #8
str x3, [x1], #8
cmp x1, x2
b.lo .L_copy_loop
// Prepare the jump to Rust code.
// Set the stack pointer.
ADR_ABS x0, __boot_core_stack_end_exclusive
mov sp, x0
// Jump to the relocated Rust code.
ADR_ABS x1, _start_rust
br x1
// Infinitely wait for events (aka "park the core").
.L_parking_loop:
wfe
b .L_parking_loop
.size _start, . - _start
.type _start, function
.global _start
|
ethan-samplecode50/Ziren | 8,885 | crates/zkvm/entrypoint/src/memset.s | // This is musl-libc memset commit 5613a1486e6a6fc3988be6561f41b07b2647d80f:
//
// src/string/memset.c
//
// This was compiled into assembly with:
//
// clang10 -target mips -O3 -S memset.c -nostdlib -fno-builtin -funroll-loops
//
// and labels manually updated to not conflict.
//
// musl as a whole is licensed under the following standard MIT license:
//
// ----------------------------------------------------------------------
// Copyright © 2005-2020 Rich Felker, et al.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ----------------------------------------------------------------------
//
// Authors/contributors include:
//
// A. Wilcox
// Ada Worcester
// Alex Dowad
// Alex Suykov
// Alexander Monakov
// Andre McCurdy
// Andrew Kelley
// Anthony G. Basile
// Aric Belsito
// Arvid Picciani
// Bartosz Brachaczek
// Benjamin Peterson
// Bobby Bingham
// Boris Brezillon
// Brent Cook
// Chris Spiegel
// Clément Vasseur
// Daniel Micay
// Daniel Sabogal
// Daurnimator
// David Carlier
// David Edelsohn
// Denys Vlasenko
// Dmitry Ivanov
// Dmitry V. Levin
// Drew DeVault
// Emil Renner Berthing
// Fangrui Song
// Felix Fietkau
// Felix Janda
// Gianluca Anzolin
// Hauke Mehrtens
// He X
// Hiltjo Posthuma
// Isaac Dunham
// Jaydeep Patil
// Jens Gustedt
// Jeremy Huntwork
// Jo-Philipp Wich
// Joakim Sindholt
// John Spencer
// Julien Ramseier
// Justin Cormack
// Kaarle Ritvanen
// Khem Raj
// Kylie McClain
// Leah Neukirchen
// Luca Barbato
// Luka Perkov
// M Farkas-Dyck (Strake)
// Mahesh Bodapati
// Markus Wichmann
// Masanori Ogino
// Michael Clark
// Michael Forney
// Mikhail Kremnyov
// Natanael Copa
// Nicholas J. Kain
// orc
// Pascal Cuoq
// Patrick Oppenlander
// Petr Hosek
// Petr Skocik
// Pierre Carrier
// Reini Urban
// Rich Felker
// Richard Pennington
// Ryan Fairfax
// Samuel Holland
// Segev Finer
// Shiz
// sin
// Solar Designer
// Stefan Kristiansson
// Stefan O'Rear
// Szabolcs Nagy
// Timo Teräs
// Trutz Behn
// Valentin Ochs
// Will Dietz
// William Haddon
// William Pitcock
//
// Portions of this software are derived from third-party works licensed
// under terms compatible with the above MIT license:
//
// The TRE regular expression implementation (src/regex/reg* and
// src/regex/tre*) is Copyright © 2001-2008 Ville Laurikari and licensed
// under a 2-clause BSD license (license text in the source files). The
// included version has been heavily modified by Rich Felker in 2012, in
// the interests of size, simplicity, and namespace cleanliness.
//
// Much of the math library code (src/math/* and src/complex/*) is
// Copyright © 1993,2004 Sun Microsystems or
// Copyright © 2003-2011 David Schultz or
// Copyright © 2003-2009 Steven G. Kargl or
// Copyright © 2003-2009 Bruce D. Evans or
// Copyright © 2008 Stephen L. Moshier or
// Copyright © 2017-2018 Arm Limited
// and labelled as such in comments in the individual source files. All
// have been licensed under extremely permissive terms.
//
// The ARM memcpy code (src/string/arm/memcpy.S) is Copyright © 2008
// The Android Open Source Project and is licensed under a two-clause BSD
// license. It was taken from Bionic libc, used on Android.
//
// The AArch64 memcpy and memset code (src/string/aarch64/*) are
// Copyright © 1999-2019, Arm Limited.
//
// The implementation of DES for crypt (src/crypt/crypt_des.c) is
// Copyright © 1994 David Burren. It is licensed under a BSD license.
//
// The implementation of blowfish crypt (src/crypt/crypt_blowfish.c) was
// originally written by Solar Designer and placed into the public
// domain. The code also comes with a fallback permissive license for use
// in jurisdictions that may not recognize the public domain.
//
// The smoothsort implementation (src/stdlib/qsort.c) is Copyright © 2011
// Valentin Ochs and is licensed under an MIT-style license.
//
// The x86_64 port was written by Nicholas J. Kain and is licensed under
// the standard MIT terms.
//
// The mips and microblaze ports were originally written by Richard
// Pennington for use in the ellcc project. The original code was adapted
// by Rich Felker for build system and code conventions during upstream
// integration. It is licensed under the standard MIT terms.
//
// The mips64 port was contributed by Imagination Technologies and is
// licensed under the standard MIT terms.
//
// The powerpc port was also originally written by Richard Pennington,
// and later supplemented and integrated by John Spencer. It is licensed
// under the standard MIT terms.
//
// All other files which have no copyright comments are original works
// produced specifically for use as part of this library, written either
// by Rich Felker, the main author of the library, or by one or more
// contributors listed above. Details on authorship of individual files
// can be found in the git version control history of the project. The
// omission of copyright and license comments in each file is in the
// interest of source tree size.
//
// In addition, permission is hereby granted for all public header files
// (include/* and arch/* /bits/* ) and crt files intended to be linked into
// applications (crt/*, ldso/dlstart.c, and arch/* /crt_arch.h) to omit
// the copyright notice and permission notice otherwise required by the
// license, and to use these files without any requirement of
// attribution. These files include substantial contributions from:
//
// Bobby Bingham
// John Spencer
// Nicholas J. Kain
// Rich Felker
// Richard Pennington
// Stefan Kristiansson
// Szabolcs Nagy
//
// all of whom have explicitly granted such permission.
//
// This file previously contained text expressing a belief that most of
// the files covered by the above exception were sufficiently trivial not
// to be subject to copyright, resulting in confusion over whether it
// negated the permissions granted in the license. In the spirit of
// permissive licensing, and of not having licensing issues being an
// obstacle to adoption, that text has been removed.
.text
.file "memset.c"
.globl memset # -- Begin function memset
.p2align 2
.type memset,@function
.set nomicromips
.set nomips16
.ent memset
memset: # @memset
.frame $fp,8,$ra
.mask 0xc0000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
.set noat
# %bb.0:
beqz $6, $BBmemset0_9
addu $2, $6, $4
sltiu $1, $6, 3
sb $5, 0($4)
bnez $1, $BBmemset0_9
sb $5, -1($2)
# %bb.2:
sltiu $1, $6, 7
sb $5, 2($4)
sb $5, 1($4)
sb $5, -3($2)
bnez $1, $BBmemset0_9
sb $5, -2($2)
# %bb.3:
sltiu $1, $6, 9
sb $5, 3($4)
bnez $1, $BBmemset0_9
sb $5, -4($2)
# %bb.4:
negu $2, $4
andi $1, $2, 3
addu $2, $4, $1
subu $6, $6, $1
addiu $7, $zero, -4
and $6, $6, $7
andi $5, $5, 255
lui $1, 257
addi $1, $1, 257
mult $5, $1
mflo $5
sw $5, 0($2)
addu $1, $2, $6
sltiu $3, $6, 9
bnez $3, $BBmemset0_9
sw $5, -4($1)
# %bb.5:
sltiu $3, $6, 25
sw $5, 8($2)
sw $5, 4($2)
sw $5, -8($1)
bnez $3, $BBmemset0_9
sw $5, -12($1)
# %bb.6:
sw $5, 24($2)
sw $5, 20($2)
sw $5, 16($2)
sw $5, 12($2)
sw $5, -16($1)
sw $5, -20($1)
sw $5, -24($1)
andi $3, $2, 4
ori $3, $3, 24
subu $6, $6, $3
sltiu $7, $6, 32
bnez $7, $BBmemset0_9
sw $5, -28($1)
add $2, $2, $3
$BBmemset0_8: # =>This Inner Loop Header: Depth=1
sw $5, 24($2)
sw $5, 16($2)
sw $5, 8($2)
sw $5, 0($2)
sw $5, 28($2)
sw $5, 20($2)
sw $5, 12($2)
sw $5, 4($2)
addiu $6, $6, -32
sltiu $1, $6, 32
beqz $1, $BBmemset0_8
addiu $2, $2, 32
$BBmemset0_9:
jr $ra
move $2, $4
.set at
.set macro
.set reorder
.end memset
$memset_func_end0:
.size memset, ($memset_func_end0)-memset
# -- End function
.ident "clang version 10.0.0-4ubuntu1 "
.section ".note.GNU-stack","",@progbits
.addrsig
|
ethan-samplecode50/Ziren | 10,395 | crates/zkvm/entrypoint/src/memcpy.s | // This is musl-libc commit 3b0a370020c4d5b80ff32a609e5322b7760f0dc4:
//
// src/string/memcpy.c
//
// This was compiled into assembly with:
//
// clang -target mipsel -O3 -S memcpy.c -nostdlib -fno-builtin -funroll-loops
//
// and labels manually updated to not conflict.
//
// musl as a whole is licensed under the following standard MIT license:
//
// ----------------------------------------------------------------------
// Copyright © 2005-2020 Rich Felker, et al.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ----------------------------------------------------------------------
//
// Authors/contributors include:
//
// A. Wilcox
// Ada Worcester
// Alex Dowad
// Alex Suykov
// Alexander Monakov
// Andre McCurdy
// Andrew Kelley
// Anthony G. Basile
// Aric Belsito
// Arvid Picciani
// Bartosz Brachaczek
// Benjamin Peterson
// Bobby Bingham
// Boris Brezillon
// Brent Cook
// Chris Spiegel
// Clément Vasseur
// Daniel Micay
// Daniel Sabogal
// Daurnimator
// David Carlier
// David Edelsohn
// Denys Vlasenko
// Dmitry Ivanov
// Dmitry V. Levin
// Drew DeVault
// Emil Renner Berthing
// Fangrui Song
// Felix Fietkau
// Felix Janda
// Gianluca Anzolin
// Hauke Mehrtens
// He X
// Hiltjo Posthuma
// Isaac Dunham
// Jaydeep Patil
// Jens Gustedt
// Jeremy Huntwork
// Jo-Philipp Wich
// Joakim Sindholt
// John Spencer
// Julien Ramseier
// Justin Cormack
// Kaarle Ritvanen
// Khem Raj
// Kylie McClain
// Leah Neukirchen
// Luca Barbato
// Luka Perkov
// M Farkas-Dyck (Strake)
// Mahesh Bodapati
// Markus Wichmann
// Masanori Ogino
// Michael Clark
// Michael Forney
// Mikhail Kremnyov
// Natanael Copa
// Nicholas J. Kain
// orc
// Pascal Cuoq
// Patrick Oppenlander
// Petr Hosek
// Petr Skocik
// Pierre Carrier
// Reini Urban
// Rich Felker
// Richard Pennington
// Ryan Fairfax
// Samuel Holland
// Segev Finer
// Shiz
// sin
// Solar Designer
// Stefan Kristiansson
// Stefan O'Rear
// Szabolcs Nagy
// Timo Teräs
// Trutz Behn
// Valentin Ochs
// Will Dietz
// William Haddon
// William Pitcock
//
// Portions of this software are derived from third-party works licensed
// under terms compatible with the above MIT license:
//
// The TRE regular expression implementation (src/regex/reg* and
// src/regex/tre*) is Copyright © 2001-2008 Ville Laurikari and licensed
// under a 2-clause BSD license (license text in the source files). The
// included version has been heavily modified by Rich Felker in 2012, in
// the interests of size, simplicity, and namespace cleanliness.
//
// Much of the math library code (src/math/* and src/complex/*) is
// Copyright © 1993,2004 Sun Microsystems or
// Copyright © 2003-2011 David Schultz or
// Copyright © 2003-2009 Steven G. Kargl or
// Copyright © 2003-2009 Bruce D. Evans or
// Copyright © 2008 Stephen L. Moshier or
// Copyright © 2017-2018 Arm Limited
// and labelled as such in comments in the individual source files. All
// have been licensed under extremely permissive terms.
//
// The ARM memcpy code (src/string/arm/memcpy.S) is Copyright © 2008
// The Android Open Source Project and is licensed under a two-clause BSD
// license. It was taken from Bionic libc, used on Android.
//
// The AArch64 memcpy and memset code (src/string/aarch64/*) are
// Copyright © 1999-2019, Arm Limited.
//
// The implementation of DES for crypt (src/crypt/crypt_des.c) is
// Copyright © 1994 David Burren. It is licensed under a BSD license.
//
// The implementation of blowfish crypt (src/crypt/crypt_blowfish.c) was
// originally written by Solar Designer and placed into the public
// domain. The code also comes with a fallback permissive license for use
// in jurisdictions that may not recognize the public domain.
//
// The smoothsort implementation (src/stdlib/qsort.c) is Copyright © 2011
// Valentin Ochs and is licensed under an MIT-style license.
//
// The x86_64 port was written by Nicholas J. Kain and is licensed under
// the standard MIT terms.
//
// The mips and microblaze ports were originally written by Richard
// Pennington for use in the ellcc project. The original code was adapted
// by Rich Felker for build system and code conventions during upstream
// integration. It is licensed under the standard MIT terms.
//
// The mips64 port was contributed by Imagination Technologies and is
// licensed under the standard MIT terms.
//
// The powerpc port was also originally written by Richard Pennington,
// and later supplemented and integrated by John Spencer. It is licensed
// under the standard MIT terms.
//
// All other files which have no copyright comments are original works
// produced specifically for use as part of this library, written either
// by Rich Felker, the main author of the library, or by one or more
// contributors listed above. Details on authorship of individual files
// can be found in the git version control history of the project. The
// omission of copyright and license comments in each file is in the
// interest of source tree size.
//
// In addition, permission is hereby granted for all public header files
// (include/* and arch/* /bits/* ) and crt files intended to be linked into
// applications (crt/*, ldso/dlstart.c, and arch/* /crt_arch.h) to omit
// the copyright notice and permission notice otherwise required by the
// license, and to use these files without any requirement of
// attribution. These files include substantial contributions from:
//
// Bobby Bingham
// John Spencer
// Nicholas J. Kain
// Rich Felker
// Richard Pennington
// Stefan Kristiansson
// Szabolcs Nagy
//
// all of whom have explicitly granted such permission.
//
// This file previously contained text expressing a belief that most of
// the files covered by the above exception were sufficiently trivial not
// to be subject to copyright, resulting in confusion over whether it
// negated the permissions granted in the license. In the spirit of
// permissive licensing, and of not having licensing issues being an
// obstacle to adoption, that text has been removed.
.text
.file "memcpy.c"
.globl memcpy # -- Begin function memcpy
.p2align 2
.type memcpy,@function
.set nomicromips
.set nomips16
.ent memcpy
memcpy: # @memcpy
.frame $fp,8,$ra
.mask 0xc0000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
.set noat
# %bb.0: #23
andi $1, $5, 3
beqz $1, $BB0_15
nop
# %bb.1: #23
beqz $6, $BB0_6
nop
# %bb.2: #23
addiu $3, $5, 1
addiu $7, $zero, 1
move $2, $4
$BB0_3: #23 # =>This Inner Loop Header: Depth=1
lbu $1, 0($5)
move $8, $6
addiu $6, $6, -1
addiu $5, $5, 1
sb $1, 0($2)
andi $1, $3, 3
beqz $1, $BB0_7
addiu $2, $2, 1
# %bb.4: # in Loop: Header=BB0_3 Depth=1
bne $8, $7, $BB0_3
addiu $3, $3, 1
# %bb.5:
j $BB0_7
nop
$BB0_6: #23
move $2, $4
$BB0_7: #25
andi $7, $2, 3
beqz $7, $BB0_16
nop
$BB0_8: #50
sltiu $1, $6, 16
bnez $1, $BB0_32
nop
$BB0_12: #51~106
lw $3, 0($5)
swr $3, 0($2)
swl $3, 3($2)
lw $3, 4($5)
swr $3, 4($2)
swl $3, 7($2)
lw $3, 8($5)
swr $3, 8($2)
swl $3, 11($2)
lw $3, 12($5)
swr $3, 12($2)
swl $3, 15($2)
addiu $5, $5, 16
addiu $6, $6, -16
sltiu $9, $6, 16
beqz $9, $BB0_12
addiu $2, $2, 16
# %bb.14:
j $BB0_32
nop
$BB0_15: #23
move $2, $4
andi $7, $2, 3
bnez $7, $BB0_8
nop
$BB0_16: #26
sltiu $1, $6, 16
bnez $1, $BB0_23
nop
$BB0_17: #27~30 # =>This Inner Loop Header: Depth=1
lw $1, 0($5)
addiu $6, $6, -16
sw $1, 0($2)
lw $1, 4($5)
sw $1, 4($2)
lw $1, 8($5)
sw $1, 8($2)
lw $1, 12($5)
addiu $5, $5, 16
sw $1, 12($2)
sltiu $1, $6, 16
beqz $1, $BB0_17
addiu $2, $2, 16
# %bb.18: #32
sltiu $1, $6, 8
beqz $1, $BB0_24
nop
$BB0_19: #37
andi $1, $6, 4
bnez $1, $BB0_25
nop
$BB0_20: #41
andi $1, $6, 2
bnez $1, $BB0_26
nop
$BB0_21: #44
andi $1, $6, 1
beqz $1, $BB0_45
nop
# %bb.22: #47
j $BB0_44
nop
$BB0_23: #32
sltiu $1, $6, 8
bnez $1, $BB0_19
nop
$BB0_24: #33-34
lw $1, 0($5)
sw $1, 0($2)
lw $1, 4($5)
addiu $5, $5, 8
sw $1, 4($2)
andi $1, $6, 4
beqz $1, $BB0_20
addiu $2, $2, 8
$BB0_25: #38-39
lw $1, 0($5)
addiu $5, $5, 4
sw $1, 0($2)
andi $1, $6, 2
beqz $1, $BB0_21
addiu $2, $2, 4
$BB0_26: #42
lhu $1, 0($5)
addiu $5, $5, 2
sh $1, 0($2)
andi $1, $6, 1
beqz $1, $BB0_45
addiu $2, $2, 2
# %bb.27:
j $BB0_44
nop
$BB0_32:
andi $1, $6, 8
beqz $1, $BB0_40 #107
nop
$BB0_33: #108~109
lw $1, 0($5)
swr $1, 0($2)
swl $1, 3($2)
lw $1, 4($5)
swr $1, 4($2)
swl $1, 7($2)
addiu $2, $2, 8
andi $1, $6, 4
beqz $1, $BB0_41 #111
addiu $5, $5, 8
$BB0_34: #112
lw $1, 0($5)
swr $1, 0($2)
swl $1, 3($2)
addiu $2, $2, 4
andi $1, $6, 2
beqz $1, $BB0_43 #117
addiu $5, $5, 4
# %bb.35: #120
j $BB0_42
nop
$BB0_40:
andi $1, $6, 4
bnez $1, $BB0_34
nop
$BB0_41: #114
andi $1, $6, 2
beqz $1, $BB0_43
nop
$BB0_42:
lbu $1, 0($5)
sb $1, 0($2)
lbu $1, 1($5)
addiu $5, $5, 2
sb $1, 1($2)
addiu $2, $2, 2
$BB0_43: #117
andi $1, $6, 1
beqz $1, $BB0_45
nop
$BB0_44: #118
lbu $1, 0($5)
sb $1, 0($2)
$BB0_45: #120
jr $ra
move $2, $4
.set at
.set macro
.set reorder
.end memcpy
$func_end0:
.size memcpy, ($func_end0)-memcpy
# -- End function
.ident "Ubuntu clang version 18.1.3 (1ubuntu1)"
.section ".note.GNU-stack","",@progbits
.addrsig
|
ethan-samplecode50/Ziren | 786 | crates/go-runtime/zkvm_runtime/syscall_mipsle.s | //go:build mipsle
// +build mipsle
TEXT ·SyscallWrite(SB), $0-24
MOVW $2, R2 // #define SYS_write 4004
MOVW fd+0(FP), R4
MOVW write_buf+4(FP), R5
MOVW nbytes+16(FP), R6
SYSCALL
MOVW R2, ret+0(FP)
RET
TEXT ·SyscallHintLen(SB), $0-4
MOVW $0xF0, R2 // #define SYS_hint_len 0xF0
SYSCALL
MOVW R2, ret+0(FP)
RET
TEXT ·SyscallHintRead(SB), $0-16
MOVW $0xF1, R2 // #define SYS_hint_read 0xF1
MOVW ptr+0(FP), R4
MOVW len+12(FP), R5
SYSCALL
RET
TEXT ·SyscallCommit(SB), $0-8
MOVW index+0(FP), R4 // a0 = index
MOVW word+4(FP), R5 // a1 = word
MOVW $0x10, R2 // v0 = syscall 4001
SYSCALL
RET
TEXT ·SyscallExit(SB), $0-4
MOVW code+0(FP), R4 // a0 = code
MOVW $0, R2 // v0 = syscall 0
SYSCALL
RET
|
Evanev7/lang | 232 | rs/code/baby.s | .file "baby.c"
.text
.section .text.startup,"ax",@progbits
.p2align 4
.globl main
.type main, @function
main:
movl $2, %eax
ret
.size main, .-main
.ident "GCC: (GNU) 14.2.1 20241116"
.section .note.GNU-stack,"",@progbits
|
faaple/TestOS | 392 | src/link_app.S | .align 3
.section .data
.global _num_app
_num_app:
.quad 2
.quad app_0_start
.quad app_1_start
.quad app_1_end
.section .data
.global app_0_start
.global app_0_end
app_0_start:
.incbin "../user/bin/hello1.bin"
app_0_end:
.section .data
.global app_1_start
.global app_1_end
app_1_start:
.incbin "../user/bin/hello2.bin"
app_1_end: |
faaple/TestOS | 1,589 | src/trap/trap.S | .altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->kernel stack, sscratch->user stack
# allocate a TrapContext on kernel stack
addi sp, sp, -34*8
# save general-purpose registers
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they were saved on kernel stack
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it on the kernel stack
csrr t2, sscratch
sd t2, 2*8(sp)
# set input argument of trap_handler(cx: &mut TrapContext)
mv a0, sp
call trap_handler
__restore:
# case1: start running app by __restore
# case2: back to U after handling trap
mv sp, a0
# now sp->kernel stack(after allocated), sscratch->user stack
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
ld t2, 2*8(sp)
csrw sstatus, t0
csrw sepc, t1
csrw sscratch, t2
# restore general-purpuse registers except sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# release TrapContext on kernel stack
addi sp, sp, 34*8
# now sp->user stack, sscratch->kernel stack
csrrw sp, sscratch, sp
sret
|
FaintentDev/rpi-slint-baremetal | 6,263 | src/asm/boot.s | /***********************************************************************************************************************
* Raspberry Pi bootstrap code.
* This is the minimal preparation to brach into the "Rust" code line for further initialization
* and setup for the current kernel to be run at the Raspberry Pi.
*
* This is the Aarch64 version of the bootstrapping. It assumes:
* 1. There is actually only the main core entering this code
* 2. The bootcode.bin/start.elf have parked the other cores of the CPU
* 3. The current core is entering this code in EL2
* 4. The start address of the entry point is 0x8_0000 which has to be ensured by the linker script
**********************************************************************************************************************/
.global __boot // global entry point
.global __hang // helper to savely "hang" a core with nothing else to do
/***************************************************************************************************
* main entry point using specific section that is ensured to be linked against the entrypoint
* address 0x8_0000
**************************************************************************************************/
.section .text.boot
__boot:
// the very first thing to do is to setup the stack pointer.
mrs x0, mpidr_el1 // get core id to calculate core distinct stack pointers
and x0, x0, #3
ldr x1,=__stack_top_core0__
ldr x2,=__stack_top_core1__
subs x1, x1, x2 // offset = core0 - core1
mul x2, x1, x0 // core specific offset for the stack
ldr x1,=__stack_top_EL2__
sub sp, x1, x2
// once done we clear the BSS section which contains any static field defined
// in the Rust code line. This need to be properly initialized as it is expected
// to be 0 when first accessed
// as we might want to kickof other cores at a later point to also run the initial
// bootstrap we check for the current core. As all cores share the same memory the
// bss section need to and shall be cleared only once...
cbnz x0, .bss_done // only continue with bss clear on core 0
ldr x0, =__bss_start__ // linker file ensures alignment to 16Bit's for start and end
ldr x2, =__bss_end__
sub x2, x2, x0
lsr x2, x2, #4
cbz x2, .bss_done // if bss section size is 0 -> skip initialization
.bss_zero_loop:
stp xzr, xzr, [x0], #16
sub x2, x2, #1
cbnz x2, .bss_zero_loop
.bss_done:
// next step will switch from EL2 to EL1 which will be the one the kernel will be executed at
bl __switch_el2_to_el1
// next we setup the exception vector table that will act as a trampoline for
// all exceptions into the handler written in Rust code
adr x0, __ExceptionVectorTable
msr vbar_el1, x0 // set exception vector table adress in EL1
// as rust compiler optimizations quite likely result in FP/NEON instructions
// ensure they are not trapped
mrs x1, cpacr_el1
mov x0, #(3 << 20)
orr x0, x1, x0
msr cpacr_el1, x0
// now call rust code entry point.
mrs x0, mpidr_el1 // read CoreId from register
and x0, x0, #3 // mask coreId value
b __rust_entry
// usually this will never return. However to be an the save side, when ever we got back
// safely hang this core
b __hang
/***************************************************************************************************
* switch the current exception level EL2 to EL1. The EL1 return address is
* the return to the caller
**************************************************************************************************/
.global __switch_el2_to_el1
__switch_el2_to_el1:
mrs x0, currentEl // get the current exception level
cmp x0, #(1 << 2) // if already in EL1 no switch necessary
beq .SwitchReturn
msr sctlr_el1, xzr // initialize SCTRL_EL1 register before switching to EL1
// enable AArch64 when switching to EL1 (otherwise EL1 would be executed in aarch32)
mov x0, #(1 << 31) // AArch64
orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3
msr hcr_el2, x0
mrs x0, hcr_el2
mrs x2, cnthctl_el2 // enable CNTP for EL1
orr x2, x2, #3
msr cnthctl_el2, x2
msr cntvoff_el2, xzr
// set the SPSR_EL2 to a valid value before returning to EL1
// this would have been usually set when capturing an exception from EL1 to EL2
// as we would like to return we set the values as we would like to find them
// configured once we are in EL1
mov x2, #(0b0101 << 0 | 0 << 4 | 1 << 6 | 1 << 7 | 1 << 8 | 1 << 9)
//mov x2, #0x3c4 //#0b00101 // set DAIF to 0 and M[4] to 0 (exception from aarch64, M[3:0] to 0101 -> Exception from EL1h)
msr spsr_el2, x2
// before returning to EL1 also ensure that interrupts are no longer routet to EL2
mrs x0, hcr_el2
bic x0, x0, #(1 << 3 | 1 << 4 | 1 << 5) // don't route Abort, IRQ and FIQ to EL2
msr hcr_el2, x0
// we cannot directly return to the caller as the EL1 stackpointer
// is not yet setup
adr x1, .SwitchReturn
msr elr_el2, x1
eret // return from EL2 -> EL1
.SwitchReturn:
ldr x1, =__stack_top_EL1__ // get the EL1 stack base address
// use the core id to get the core specific stack pointer
mrs x0, mpidr_el1 // get CPU id
and x0, x0, #3
ldr x2,=__stack_top_core0__
ldr x3,=__stack_top_core1__
subs x2, x2, x3 // offset = core0 - core1
mul x2, x2, x0 // core specific offset for the stack
sub x0, x1, x2 // from the top base substract the core offset to get final stack top
mov sp, x0
ret
/***************************************************************************************************
* safely hang the core
* use the WFE instruction to save power while waiting for any event
* wfe is triggered by any exception/interrupt raised, but as long as there is no event
* the core sleeps....
**************************************************************************************************/
.section .text
__hang:
wfe
b __hang
|
FaintentDev/rpi-slint-baremetal | 8,458 | src/asm/exception.s | .global __ExceptionVectorTable
// specify the constants used to passed to the generic exception handler to identify
// the type and context of the exception raised
.equ EXC_CURREL_SP0_Sync, 0x1
.equ EXC_CURREL_SP0_Irq, 0x2
.equ EXC_CURREL_SP0_Fiq, 0x3
.equ EXC_CURREL_SP0_SErr, 0x4
.equ EXC_CURREL_SPX_Sync, 0x11
.equ EXC_CURREL_SPX_Irq, 0x12
.equ EXC_CURREL_SPX_Fiq, 0x13
.equ EXC_CURREL_SPX_SErr, 0x14
.equ EXC_LOWEREL64_SPX_Sync, 0x21
.equ EXC_LOWEREL64_SPX_Irq, 0x22
.equ EXC_LOWEREL64_SPX_Fiq, 0x23
.equ EXC_LOWEREL64_SPX_SErr, 0x24
.equ EXC_LOWEREL32_SPX_Sync, 0x31
.equ EXC_LOWEREL32_SPX_Irq, 0x32
.equ EXC_LOWEREL32_SPX_Fiq, 0x33
.equ EXC_LOWEREL32_SPX_SErr, 0x34
/***************************************************************************************************
* default exception handler that does nothing for the time beeing
* parameter passed: type, esr, spsr, far, elr
**************************************************************************************************/
.global __exception_handler_default
/***************************************************************************************************
* generic exception handler trampoline
* Input: X0 containing the id of the exception that has been raised
**************************************************************************************************/
__exception_trampoline:
/**********************************************************************
* save current core state before running any IRQ handler
**********************************************************************/
sub sp, sp, #176 // make place at the stack to store all register values
// register x19-x29 are callee save registers
stp x0, x1, [sp, #16 * 0]
stp x2, x3, [sp, #16 * 1]
stp x4, x5, [sp, #16 * 2]
stp x6, x7, [sp, #16 * 3]
stp x8, x9, [sp, #16 * 4]
stp x10, x11, [sp, #16 * 5]
stp x12, x13, [sp, #16 * 6]
stp x14, x15, [sp, #16 * 7]
stp x16, x17, [sp, #16 * 8]
stp x18, x30, [sp, #16 * 9]
// stack SPSR_EL1 and ELR_EL1 for an optional re-entrant interrupt handler, which would require
// to enable interrupts before the handler is called as they are deactivated on exception entrance
mrs x10, spsr_el1
mrs x11, elr_el1
stp x10, x11, [sp, #16 * 10] // reading the context of the current exception to be passed to the handler
// we assume this is taken in EL1 - therfore hardcode the respective registers
mrs x1, esr_el1
mrs x2, spsr_el1
mrs x3, far_el1
mrs x4, elr_el1
// branch to the default exception handler
// if not implemented somewhere else the default implementeation provided here will
// be called, consumes x0-x4 as parameters
bl __exception_handler_default
/**********************************************************************
* restore last core state after running any IRQ handler
**********************************************************************/
// restore SPSR_EL1 and ELR_EL1
ldp x10, x11, [sp, #16 * 10]
msr elr_el1, x11
msr spsr_el1, x10
ldp x0, x1, [sp, #16 * 0]
ldp x2, x3, [sp, #16 * 1]
ldp x4, x5, [sp, #16 * 2]
ldp x6, x7, [sp, #16 * 3]
ldp x8, x9, [sp, #16 * 4]
ldp x10, x11, [sp, #16 * 5]
ldp x12, x13, [sp, #16 * 6]
ldp x14, x15, [sp, #16 * 7]
ldp x16, x17, [sp, #16 * 8]
ldp x18, x30, [sp, #16 * 9]
add sp, sp, #176 // free the stack as it is no longer needed
ret
/**********************************************************************
* Macro to call the exception trampoline ensuring scratch registers
* are properly saved before and restored afterwards, takes the type value
* for the exception as parameter
**********************************************************************/
.macro call_trampoline type
// store the scratch registers
sub sp, sp, #16
stp x0, x30, [sp]
// call the exception trampoline
mov x0, \type
bl __exception_trampoline
// restore the scratch registers
ldp x0, x30, [sp]
add sp, sp, #16
.endm
// the exception vector table start need to be proper aligned
// the order of entries and their alignments are specified in the respective ARM
// documents. Each vector table "section" can contain max 32 instructions
// so we use this entries just to jump to the real trampoline function
.balign 0x800
__ExceptionVectorTable:
// Sync Exception raised in current EL with SP_0
.EXC_CURREL_SP0_Sync:
// call the exception trampoline
call_trampoline EXC_CURREL_SP0_Sync
eret // return from exception handler to normal processing
// Irq Exception raised in current EL with SP_0
.balign 0x80
.EXC_CURREL_SP0_Irq:
// call the exception trampoline
call_trampoline EXC_CURREL_SP0_Irq
eret // return from exception handler to normal processing
// Fiq Exception raised in current EL with SP_0
.balign 0x80
.EXC_CURREL_SP0_Fiq:
// call the exception trampoline
call_trampoline EXC_CURREL_SP0_Fiq
eret // return from exception handler to normal processing
// Sync Exception raised in current EL with SP_x
.balign 0x80
.EXC_CURREL_SP0_SErr:
// call the exception trampoline
call_trampoline EXC_CURREL_SP0_SErr
eret // return from exception handler to normal processing
/**************************************************************************************************/
// Sync Exception raised in current EL with SP_x
.balign 0x80
.EXC_CURREL_SPX_Sync:
// call the exception trampoline
call_trampoline EXC_CURREL_SPX_Sync
eret // return from exception handler to normal processing
// Irq Exception raised in current EL with SP_x
.balign 0x80
.EXC_CURREL_SPX_Irq:
// call the exception trampoline
call_trampoline EXC_CURREL_SPX_Irq
eret // return from exception handler to normal processing
// Fiq Exception raised in current EL with SP_x
.balign 0x80
.EXC_CURREL_SPX_Fiq:
// call the exception trampoline
call_trampoline EXC_CURREL_SPX_Fiq
eret // return from exception handler to normal processing
// Sync Exception raised in current EL with SP_x
.balign 0x80
.EXC_CURREL_SPX_SErr:
// call the exception trampoline
call_trampoline EXC_CURREL_SPX_SErr
eret // return from exception handler to normal processing
/**************************************************************************************************/
// Sync Exception raised in lower EL Aarch64 with SP_x
.balign 0x80
.EXC_LOWEREL64_SPX_Sync:
// call the exception trampoline
call_trampoline EXC_LOWEREL64_SPX_Sync
eret // return from exception handler to normal processing
// Irq Exception raised in current EL Aarc64 with SP_x
.balign 0x80
.EXC_LOWEREL64_SPX_Irq:
// call the exception trampoline
call_trampoline EXC_LOWEREL64_SPX_Irq
eret // return from exception handler to normal processing
// Fiq Exception raised in current EL with SP_x
.balign 0x80
.EXC_LOWEREL64_SPX_Fiq:
// call the exception trampoline
call_trampoline EXC_LOWEREL64_SPX_Fiq
eret // return from exception handler to normal processing
// Sync Exception raised in current EL with SP_x
.balign 0x80
.EXC_LOWEREL64_SPX_SErr:
// call the exception trampoline
call_trampoline EXC_LOWEREL64_SPX_SErr
eret // return from exception handler to normal processing
/**************************************************************************************************/
// Sync Exception raised in lower EL Aarch32 with SP_x
.balign 0x80
.EXC_LOWEREL32_SPX_Sync:
// call the exception trampoline
call_trampoline EXC_LOWEREL32_SPX_Sync
eret // return from exception handler to normal processing
// Irq Exception raised in current EL Aarch32 with SP_x
.balign 0x80
.EXC_LOWEREL32_SPX_Irq:
// call the exception trampoline
call_trampoline EXC_LOWEREL32_SPX_Irq
eret // return from exception handler to normal processing
// Fiq Exception raised in current EL Aarch32 with SP_x
.balign 0x80
.EXC_LOWEREL32_SPX_Fiq:
// call the exception trampoline
call_trampoline EXC_LOWEREL32_SPX_Fiq
eret // return from exception handler to normal processing
// Sync Exception raised in current EL Aarch32 with SP_x
.balign 0x80
.EXC_LOWEREL32_SPX_SErr:
// call the exception trampoline
call_trampoline EXC_LOWEREL32_SPX_SErr
eret // return from exception handler to normal processing
.balign 0x80
__ExceptionVectorTableEnd:
|
FashionablyNate/raspi4_rust_bootloader | 866 | src/boot.s |
.section .text._start
_start:
mrs x0, MPIDR_EL1 /* Read multiprocessor affinity register */
and x0, x0, {CONST_CORE_ID_MASK} /* Mask core id info */
/* If we're not on the boot core, wait indefinitely */
ldr x1, BOOT_CORE_ID
cmp x0, x1
b.ne .do_nothing
/* Grab start and end of uninitialized data section */
adrp x0, __bss_start
add x0, x0, #:lo12:__bss_start
adrp x1, __bss_end
add x1, x1, #:lo12:__bss_end
.zero_uninitialized_data:
cmp x0, x1
b.eq .set_stack_pointer
stp xzr, xzr, [x0], #16
b .zero_uninitialized_data
.set_stack_pointer:
adrp x0, __boot_core_stack_end
add x0, x0, #:lo12:__boot_core_stack_end
mov sp, x0
/* Calls our entry point rust function */
b _start_rust
.do_nothing:
wfe
b .do_nothing
/* set _start metadata for the linker */
.size _start, . - _start
.type _start, function
.global _start
|
fastest-sp1/sp1 | 8,450 | crates/zkvm/entrypoint/src/memset.s | // This is musl-libc memset commit 37e18b7bf307fa4a8c745feebfcba54a0ba74f30:
//
// src/string/memset.c
//
// This was compiled into assembly with:
//
// clang-14 -target riscv32 -march=rv32im -O3 -S memset.c -nostdlib -fno-builtin -funroll-loops
//
// and labels manually updated to not conflict.
//
// musl as a whole is licensed under the following standard MIT license:
//
// ----------------------------------------------------------------------
// Copyright © 2005-2020 Rich Felker, et al.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ----------------------------------------------------------------------
//
// Authors/contributors include:
//
// A. Wilcox
// Ada Worcester
// Alex Dowad
// Alex Suykov
// Alexander Monakov
// Andre McCurdy
// Andrew Kelley
// Anthony G. Basile
// Aric Belsito
// Arvid Picciani
// Bartosz Brachaczek
// Benjamin Peterson
// Bobby Bingham
// Boris Brezillon
// Brent Cook
// Chris Spiegel
// Clément Vasseur
// Daniel Micay
// Daniel Sabogal
// Daurnimator
// David Carlier
// David Edelsohn
// Denys Vlasenko
// Dmitry Ivanov
// Dmitry V. Levin
// Drew DeVault
// Emil Renner Berthing
// Fangrui Song
// Felix Fietkau
// Felix Janda
// Gianluca Anzolin
// Hauke Mehrtens
// He X
// Hiltjo Posthuma
// Isaac Dunham
// Jaydeep Patil
// Jens Gustedt
// Jeremy Huntwork
// Jo-Philipp Wich
// Joakim Sindholt
// John Spencer
// Julien Ramseier
// Justin Cormack
// Kaarle Ritvanen
// Khem Raj
// Kylie McClain
// Leah Neukirchen
// Luca Barbato
// Luka Perkov
// M Farkas-Dyck (Strake)
// Mahesh Bodapati
// Markus Wichmann
// Masanori Ogino
// Michael Clark
// Michael Forney
// Mikhail Kremnyov
// Natanael Copa
// Nicholas J. Kain
// orc
// Pascal Cuoq
// Patrick Oppenlander
// Petr Hosek
// Petr Skocik
// Pierre Carrier
// Reini Urban
// Rich Felker
// Richard Pennington
// Ryan Fairfax
// Samuel Holland
// Segev Finer
// Shiz
// sin
// Solar Designer
// Stefan Kristiansson
// Stefan O'Rear
// Szabolcs Nagy
// Timo Teräs
// Trutz Behn
// Valentin Ochs
// Will Dietz
// William Haddon
// William Pitcock
//
// Portions of this software are derived from third-party works licensed
// under terms compatible with the above MIT license:
//
// The TRE regular expression implementation (src/regex/reg* and
// src/regex/tre*) is Copyright © 2001-2008 Ville Laurikari and licensed
// under a 2-clause BSD license (license text in the source files). The
// included version has been heavily modified by Rich Felker in 2012, in
// the interests of size, simplicity, and namespace cleanliness.
//
// Much of the math library code (src/math/* and src/complex/*) is
// Copyright © 1993,2004 Sun Microsystems or
// Copyright © 2003-2011 David Schultz or
// Copyright © 2003-2009 Steven G. Kargl or
// Copyright © 2003-2009 Bruce D. Evans or
// Copyright © 2008 Stephen L. Moshier or
// Copyright © 2017-2018 Arm Limited
// and labelled as such in comments in the individual source files. All
// have been licensed under extremely permissive terms.
//
// The ARM memcpy code (src/string/arm/memcpy.S) is Copyright © 2008
// The Android Open Source Project and is licensed under a two-clause BSD
// license. It was taken from Bionic libc, used on Android.
//
// The AArch64 memcpy and memset code (src/string/aarch64/*) are
// Copyright © 1999-2019, Arm Limited.
//
// The implementation of DES for crypt (src/crypt/crypt_des.c) is
// Copyright © 1994 David Burren. It is licensed under a BSD license.
//
// The implementation of blowfish crypt (src/crypt/crypt_blowfish.c) was
// originally written by Solar Designer and placed into the public
// domain. The code also comes with a fallback permissive license for use
// in jurisdictions that may not recognize the public domain.
//
// The smoothsort implementation (src/stdlib/qsort.c) is Copyright © 2011
// Valentin Ochs and is licensed under an MIT-style license.
//
// The x86_64 port was written by Nicholas J. Kain and is licensed under
// the standard MIT terms.
//
// The mips and microblaze ports were originally written by Richard
// Pennington for use in the ellcc project. The original code was adapted
// by Rich Felker for build system and code conventions during upstream
// integration. It is licensed under the standard MIT terms.
//
// The mips64 port was contributed by Imagination Technologies and is
// licensed under the standard MIT terms.
//
// The powerpc port was also originally written by Richard Pennington,
// and later supplemented and integrated by John Spencer. It is licensed
// under the standard MIT terms.
//
// All other files which have no copyright comments are original works
// produced specifically for use as part of this library, written either
// by Rich Felker, the main author of the library, or by one or more
// contributors listed above. Details on authorship of individual files
// can be found in the git version control history of the project. The
// omission of copyright and license comments in each file is in the
// interest of source tree size.
//
// In addition, permission is hereby granted for all public header files
// (include/* and arch/* /bits/* ) and crt files intended to be linked into
// applications (crt/*, ldso/dlstart.c, and arch/* /crt_arch.h) to omit
// the copyright notice and permission notice otherwise required by the
// license, and to use these files without any requirement of
// attribution. These files include substantial contributions from:
//
// Bobby Bingham
// John Spencer
// Nicholas J. Kain
// Rich Felker
// Richard Pennington
// Stefan Kristiansson
// Szabolcs Nagy
//
// all of whom have explicitly granted such permission.
//
// This file previously contained text expressing a belief that most of
// the files covered by the above exception were sufficiently trivial not
// to be subject to copyright, resulting in confusion over whether it
// negated the permissions granted in the license. In the spirit of
// permissive licensing, and of not having licensing issues being an
// obstacle to adoption, that text has been removed.
.text
.attribute 4, 16
.attribute 5, "rv32im"
.file "musl_memset.c"
.globl memset
.p2align 2
.type memset,@function
memset:
beqz a2, .LBB0_9memset
sb a1, 0(a0)
add a3, a2, a0
li a4, 3
sb a1, -1(a3)
bltu a2, a4, .LBB0_9memset
sb a1, 1(a0)
sb a1, 2(a0)
sb a1, -2(a3)
li a4, 7
sb a1, -3(a3)
bltu a2, a4, .LBB0_9memset
sb a1, 3(a0)
li a5, 9
sb a1, -4(a3)
bltu a2, a5, .LBB0_9memset
neg a3, a0
andi a4, a3, 3
add a3, a0, a4
sub a2, a2, a4
andi a2, a2, -4
andi a1, a1, 255
lui a4, 4112
addi a4, a4, 257
mul a1, a1, a4
sw a1, 0(a3)
add a4, a3, a2
sw a1, -4(a4)
bltu a2, a5, .LBB0_9memset
sw a1, 4(a3)
sw a1, 8(a3)
sw a1, -12(a4)
li a5, 25
sw a1, -8(a4)
bltu a2, a5, .LBB0_9memset
sw a1, 12(a3)
sw a1, 16(a3)
sw a1, 20(a3)
sw a1, 24(a3)
sw a1, -28(a4)
sw a1, -24(a4)
sw a1, -20(a4)
andi a5, a3, 4
ori a5, a5, 24
sub a2, a2, a5
li a6, 32
sw a1, -16(a4)
bltu a2, a6, .LBB0_9memset
add a3, a3, a5
li a4, 31
.LBB0_8memset:
sw a1, 0(a3)
sw a1, 4(a3)
sw a1, 8(a3)
sw a1, 12(a3)
sw a1, 16(a3)
sw a1, 20(a3)
sw a1, 24(a3)
sw a1, 28(a3)
addi a2, a2, -32
addi a3, a3, 32
bltu a4, a2, .LBB0_8memset
.LBB0_9memset:
ret
.Lfunc_end0memset:
.size memset, .Lfunc_end0memset-memset
.ident "Ubuntu clang version 14.0.6-++20220622053131+f28c006a5895-1~exp1~20220622173215.157"
.section ".note.GNU-stack","",@progbits
.addrsig |
fastest-sp1/sp1 | 11,855 | crates/zkvm/entrypoint/src/memcpy.s | // This is musl-libc commit 37e18b7bf307fa4a8c745feebfcba54a0ba74f30:
//
// src/string/memcpy.c
//
// This was compiled into assembly with:
//
// clang-14 -target riscv32 -march=rv32im -O3 -S memcpy.c -nostdlib -fno-builtin -funroll-loops
//
// and labels manually updated to not conflict.
//
// musl as a whole is licensed under the following standard MIT license:
//
// ----------------------------------------------------------------------
// Copyright © 2005-2020 Rich Felker, et al.
//
// Permission is hereby granted, free of charge, to any person obtaining
// a copy of this software and associated documentation files (the
// "Software"), to deal in the Software without restriction, including
// without limitation the rights to use, copy, modify, merge, publish,
// distribute, sublicense, and/or sell copies of the Software, and to
// permit persons to whom the Software is furnished to do so, subject to
// the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// ----------------------------------------------------------------------
//
// Authors/contributors include:
//
// A. Wilcox
// Ada Worcester
// Alex Dowad
// Alex Suykov
// Alexander Monakov
// Andre McCurdy
// Andrew Kelley
// Anthony G. Basile
// Aric Belsito
// Arvid Picciani
// Bartosz Brachaczek
// Benjamin Peterson
// Bobby Bingham
// Boris Brezillon
// Brent Cook
// Chris Spiegel
// Clément Vasseur
// Daniel Micay
// Daniel Sabogal
// Daurnimator
// David Carlier
// David Edelsohn
// Denys Vlasenko
// Dmitry Ivanov
// Dmitry V. Levin
// Drew DeVault
// Emil Renner Berthing
// Fangrui Song
// Felix Fietkau
// Felix Janda
// Gianluca Anzolin
// Hauke Mehrtens
// He X
// Hiltjo Posthuma
// Isaac Dunham
// Jaydeep Patil
// Jens Gustedt
// Jeremy Huntwork
// Jo-Philipp Wich
// Joakim Sindholt
// John Spencer
// Julien Ramseier
// Justin Cormack
// Kaarle Ritvanen
// Khem Raj
// Kylie McClain
// Leah Neukirchen
// Luca Barbato
// Luka Perkov
// M Farkas-Dyck (Strake)
// Mahesh Bodapati
// Markus Wichmann
// Masanori Ogino
// Michael Clark
// Michael Forney
// Mikhail Kremnyov
// Natanael Copa
// Nicholas J. Kain
// orc
// Pascal Cuoq
// Patrick Oppenlander
// Petr Hosek
// Petr Skocik
// Pierre Carrier
// Reini Urban
// Rich Felker
// Richard Pennington
// Ryan Fairfax
// Samuel Holland
// Segev Finer
// Shiz
// sin
// Solar Designer
// Stefan Kristiansson
// Stefan O'Rear
// Szabolcs Nagy
// Timo Teräs
// Trutz Behn
// Valentin Ochs
// Will Dietz
// William Haddon
// William Pitcock
//
// Portions of this software are derived from third-party works licensed
// under terms compatible with the above MIT license:
//
// The TRE regular expression implementation (src/regex/reg* and
// src/regex/tre*) is Copyright © 2001-2008 Ville Laurikari and licensed
// under a 2-clause BSD license (license text in the source files). The
// included version has been heavily modified by Rich Felker in 2012, in
// the interests of size, simplicity, and namespace cleanliness.
//
// Much of the math library code (src/math/* and src/complex/*) is
// Copyright © 1993,2004 Sun Microsystems or
// Copyright © 2003-2011 David Schultz or
// Copyright © 2003-2009 Steven G. Kargl or
// Copyright © 2003-2009 Bruce D. Evans or
// Copyright © 2008 Stephen L. Moshier or
// Copyright © 2017-2018 Arm Limited
// and labelled as such in comments in the individual source files. All
// have been licensed under extremely permissive terms.
//
// The ARM memcpy code (src/string/arm/memcpy.S) is Copyright © 2008
// The Android Open Source Project and is licensed under a two-clause BSD
// license. It was taken from Bionic libc, used on Android.
//
// The AArch64 memcpy and memset code (src/string/aarch64/*) are
// Copyright © 1999-2019, Arm Limited.
//
// The implementation of DES for crypt (src/crypt/crypt_des.c) is
// Copyright © 1994 David Burren. It is licensed under a BSD license.
//
// The implementation of blowfish crypt (src/crypt/crypt_blowfish.c) was
// originally written by Solar Designer and placed into the public
// domain. The code also comes with a fallback permissive license for use
// in jurisdictions that may not recognize the public domain.
//
// The smoothsort implementation (src/stdlib/qsort.c) is Copyright © 2011
// Valentin Ochs and is licensed under an MIT-style license.
//
// The x86_64 port was written by Nicholas J. Kain and is licensed under
// the standard MIT terms.
//
// The mips and microblaze ports were originally written by Richard
// Pennington for use in the ellcc project. The original code was adapted
// by Rich Felker for build system and code conventions during upstream
// integration. It is licensed under the standard MIT terms.
//
// The mips64 port was contributed by Imagination Technologies and is
// licensed under the standard MIT terms.
//
// The powerpc port was also originally written by Richard Pennington,
// and later supplemented and integrated by John Spencer. It is licensed
// under the standard MIT terms.
//
// All other files which have no copyright comments are original works
// produced specifically for use as part of this library, written either
// by Rich Felker, the main author of the library, or by one or more
// contributors listed above. Details on authorship of individual files
// can be found in the git version control history of the project. The
// omission of copyright and license comments in each file is in the
// interest of source tree size.
//
// In addition, permission is hereby granted for all public header files
// (include/* and arch/* /bits/* ) and crt files intended to be linked into
// applications (crt/*, ldso/dlstart.c, and arch/* /crt_arch.h) to omit
// the copyright notice and permission notice otherwise required by the
// license, and to use these files without any requirement of
// attribution. These files include substantial contributions from:
//
// Bobby Bingham
// John Spencer
// Nicholas J. Kain
// Rich Felker
// Richard Pennington
// Stefan Kristiansson
// Szabolcs Nagy
//
// all of whom have explicitly granted such permission.
//
// This file previously contained text expressing a belief that most of
// the files covered by the above exception were sufficiently trivial not
// to be subject to copyright, resulting in confusion over whether it
// negated the permissions granted in the license. In the spirit of
// permissive licensing, and of not having licensing issues being an
// obstacle to adoption, that text has been removed.
.text
.attribute 4, 16
.attribute 5, "rv32im"
.file "musl_memcpy.c"
.globl memcpy
.p2align 2
.type memcpy,@function
memcpy:
andi a3, a1, 3
seqz a3, a3
seqz a4, a2
or a3, a3, a4
bnez a3, .LBBmemcpy0_11
addi a5, a1, 1
mv a6, a0
.LBBmemcpy0_2:
lb a7, 0(a1)
addi a4, a1, 1
addi a3, a6, 1
sb a7, 0(a6)
addi a2, a2, -1
andi a1, a5, 3
snez a1, a1
snez a6, a2
and a7, a1, a6
addi a5, a5, 1
mv a1, a4
mv a6, a3
bnez a7, .LBBmemcpy0_2
andi a1, a3, 3
beqz a1, .LBBmemcpy0_12
.LBBmemcpy0_4:
li a5, 32
bltu a2, a5, .LBBmemcpy0_26
li a5, 3
beq a1, a5, .LBBmemcpy0_19
li a5, 2
beq a1, a5, .LBBmemcpy0_22
li a5, 1
bne a1, a5, .LBBmemcpy0_26
lw a5, 0(a4)
sb a5, 0(a3)
srli a1, a5, 8
sb a1, 1(a3)
srli a6, a5, 16
addi a1, a3, 3
sb a6, 2(a3)
addi a2, a2, -3
addi a3, a4, 16
li a4, 16
.LBBmemcpy0_9:
lw a6, -12(a3)
srli a5, a5, 24
slli a7, a6, 8
lw t0, -8(a3)
or a5, a7, a5
sw a5, 0(a1)
srli a5, a6, 24
slli a6, t0, 8
lw a7, -4(a3)
or a5, a6, a5
sw a5, 4(a1)
srli a6, t0, 24
slli t0, a7, 8
lw a5, 0(a3)
or a6, t0, a6
sw a6, 8(a1)
srli a6, a7, 24
slli a7, a5, 8
or a6, a7, a6
sw a6, 12(a1)
addi a1, a1, 16
addi a2, a2, -16
addi a3, a3, 16
bltu a4, a2, .LBBmemcpy0_9
addi a4, a3, -13
j .LBBmemcpy0_25
.LBBmemcpy0_11:
mv a3, a0
mv a4, a1
andi a1, a3, 3
bnez a1, .LBBmemcpy0_4
.LBBmemcpy0_12:
li a1, 16
bltu a2, a1, .LBBmemcpy0_15
li a1, 15
.LBBmemcpy0_14:
lw a5, 0(a4)
lw a6, 4(a4)
lw a7, 8(a4)
lw t0, 12(a4)
sw a5, 0(a3)
sw a6, 4(a3)
sw a7, 8(a3)
sw t0, 12(a3)
addi a4, a4, 16
addi a2, a2, -16
addi a3, a3, 16
bltu a1, a2, .LBBmemcpy0_14
.LBBmemcpy0_15:
andi a1, a2, 8
beqz a1, .LBBmemcpy0_17
lw a1, 0(a4)
lw a5, 4(a4)
sw a1, 0(a3)
sw a5, 4(a3)
addi a3, a3, 8
addi a4, a4, 8
.LBBmemcpy0_17:
andi a1, a2, 4
beqz a1, .LBBmemcpy0_30
lw a1, 0(a4)
sw a1, 0(a3)
addi a3, a3, 4
addi a4, a4, 4
j .LBBmemcpy0_30
.LBBmemcpy0_19:
lw a5, 0(a4)
addi a1, a3, 1
sb a5, 0(a3)
addi a2, a2, -1
addi a3, a4, 16
li a4, 18
.LBBmemcpy0_20:
lw a6, -12(a3)
srli a5, a5, 8
slli a7, a6, 24
lw t0, -8(a3)
or a5, a7, a5
sw a5, 0(a1)
srli a5, a6, 8
slli a6, t0, 24
lw a7, -4(a3)
or a5, a6, a5
sw a5, 4(a1)
srli a6, t0, 8
slli t0, a7, 24
lw a5, 0(a3)
or a6, t0, a6
sw a6, 8(a1)
srli a6, a7, 8
slli a7, a5, 24
or a6, a7, a6
sw a6, 12(a1)
addi a1, a1, 16
addi a2, a2, -16
addi a3, a3, 16
bltu a4, a2, .LBBmemcpy0_20
addi a4, a3, -15
j .LBBmemcpy0_25
.LBBmemcpy0_22:
lw a5, 0(a4)
sb a5, 0(a3)
srli a6, a5, 8
addi a1, a3, 2
sb a6, 1(a3)
addi a2, a2, -2
addi a3, a4, 16
li a4, 17
.LBBmemcpy0_23:
lw a6, -12(a3)
srli a5, a5, 16
slli a7, a6, 16
lw t0, -8(a3)
or a5, a7, a5
sw a5, 0(a1)
srli a5, a6, 16
slli a6, t0, 16
lw a7, -4(a3)
or a5, a6, a5
sw a5, 4(a1)
srli a6, t0, 16
slli t0, a7, 16
lw a5, 0(a3)
or a6, t0, a6
sw a6, 8(a1)
srli a6, a7, 16
slli a7, a5, 16
or a6, a7, a6
sw a6, 12(a1)
addi a1, a1, 16
addi a2, a2, -16
addi a3, a3, 16
bltu a4, a2, .LBBmemcpy0_23
addi a4, a3, -14
.LBBmemcpy0_25:
mv a3, a1
.LBBmemcpy0_26:
andi a1, a2, 16
bnez a1, .LBBmemcpy0_35
andi a1, a2, 8
bnez a1, .LBBmemcpy0_36
.LBBmemcpy0_28:
andi a1, a2, 4
beqz a1, .LBBmemcpy0_30
.LBBmemcpy0_29:
lb a1, 0(a4)
lb a5, 1(a4)
lb a6, 2(a4)
sb a1, 0(a3)
sb a5, 1(a3)
lb a1, 3(a4)
sb a6, 2(a3)
addi a4, a4, 4
addi a5, a3, 4
sb a1, 3(a3)
mv a3, a5
.LBBmemcpy0_30:
andi a1, a2, 2
bnez a1, .LBBmemcpy0_33
andi a1, a2, 1
bnez a1, .LBBmemcpy0_34
.LBBmemcpy0_32:
ret
.LBBmemcpy0_33:
lb a1, 0(a4)
lb a5, 1(a4)
sb a1, 0(a3)
addi a4, a4, 2
addi a1, a3, 2
sb a5, 1(a3)
mv a3, a1
andi a1, a2, 1
beqz a1, .LBBmemcpy0_32
.LBBmemcpy0_34:
lb a1, 0(a4)
sb a1, 0(a3)
ret
.LBBmemcpy0_35:
lb a1, 0(a4)
lb a5, 1(a4)
lb a6, 2(a4)
sb a1, 0(a3)
sb a5, 1(a3)
lb a1, 3(a4)
sb a6, 2(a3)
lb a5, 4(a4)
lb a6, 5(a4)
sb a1, 3(a3)
lb a1, 6(a4)
sb a5, 4(a3)
sb a6, 5(a3)
lb a5, 7(a4)
sb a1, 6(a3)
lb a1, 8(a4)
lb a6, 9(a4)
sb a5, 7(a3)
lb a5, 10(a4)
sb a1, 8(a3)
sb a6, 9(a3)
lb a1, 11(a4)
sb a5, 10(a3)
lb a5, 12(a4)
lb a6, 13(a4)
sb a1, 11(a3)
lb a1, 14(a4)
sb a5, 12(a3)
sb a6, 13(a3)
lb a5, 15(a4)
sb a1, 14(a3)
addi a4, a4, 16
addi a1, a3, 16
sb a5, 15(a3)
mv a3, a1
andi a1, a2, 8
beqz a1, .LBBmemcpy0_28
.LBBmemcpy0_36:
lb a1, 0(a4)
lb a5, 1(a4)
lb a6, 2(a4)
sb a1, 0(a3)
sb a5, 1(a3)
lb a1, 3(a4)
sb a6, 2(a3)
lb a5, 4(a4)
lb a6, 5(a4)
sb a1, 3(a3)
lb a1, 6(a4)
sb a5, 4(a3)
sb a6, 5(a3)
lb a5, 7(a4)
sb a1, 6(a3)
addi a4, a4, 8
addi a1, a3, 8
sb a5, 7(a3)
mv a3, a1
andi a1, a2, 4
bnez a1, .LBBmemcpy0_29
j .LBBmemcpy0_30
.Lfuncmemcpy_end0:
.size memcpy, .Lfuncmemcpy_end0-memcpy
.ident "Ubuntu clang version 14.0.6-++20220622053131+f28c006a5895-1~exp1~20220622173215.157"
.section ".note.GNU-stack","",@progbits
.addrsig |
Fasamii/notes | 1,216 | ASM/notes/basics/generating-asm-from-c/loop.s | .file "loop.c"
.text
.section .rodata
.LC0:
.string "i is %i\n"
.text
.globl main
.type main, @function
main:
.LFB0:
.cfi_startproc
leal 4(%esp), %ecx
.cfi_def_cfa 1, 0
andl $-16, %esp
pushl -4(%ecx)
pushl %ebp
movl %esp, %ebp
.cfi_escape 0x10,0x5,0x2,0x75,0
pushl %ebx
pushl %ecx
.cfi_escape 0xf,0x3,0x75,0x78,0x6
.cfi_escape 0x10,0x3,0x2,0x75,0x7c
subl $16, %esp
call __x86.get_pc_thunk.bx
addl $_GLOBAL_OFFSET_TABLE_, %ebx
movl $0, -12(%ebp)
jmp .L2
.L3:
subl $8, %esp
pushl -12(%ebp)
leal .LC0@GOTOFF(%ebx), %eax
pushl %eax
call printf@PLT
addl $16, %esp
addl $1, -12(%ebp)
.L2:
cmpl $9, -12(%ebp)
jle .L3
movl $0, %eax
leal -8(%ebp), %esp
popl %ecx
.cfi_restore 1
.cfi_def_cfa 1, 0
popl %ebx
.cfi_restore 3
popl %ebp
.cfi_restore 5
leal -4(%ecx), %esp
.cfi_def_cfa 4, 4
ret
.cfi_endproc
.LFE0:
.size main, .-main
.section .text.__x86.get_pc_thunk.bx,"axG",@progbits,__x86.get_pc_thunk.bx,comdat
.globl __x86.get_pc_thunk.bx
.hidden __x86.get_pc_thunk.bx
.type __x86.get_pc_thunk.bx, @function
__x86.get_pc_thunk.bx:
.LFB1:
.cfi_startproc
movl (%esp), %ebx
ret
.cfi_endproc
.LFE1:
.ident "GCC: (GNU) 14.2.1 20250207"
.section .note.GNU-stack,"",@progbits
|
fawazadeniji123/Rust-Programming--The-Complete-Developer-s-Guide | 19,155 | exercises/activities/a8.s | .text
.file "a8.75f4988078fcc672-cgu.0"
.section .text._ZN3std10sys_common9backtrace28__rust_begin_short_backtrace17hdc5561e290b90f55E,"ax",@progbits
.p2align 4, 0x90
.type _ZN3std10sys_common9backtrace28__rust_begin_short_backtrace17hdc5561e290b90f55E,@function
_ZN3std10sys_common9backtrace28__rust_begin_short_backtrace17hdc5561e290b90f55E:
.cfi_startproc
pushq %rax
.cfi_def_cfa_offset 16
callq _ZN4core3ops8function6FnOnce9call_once17h0d82d9de4027e050E
#APP
#NO_APP
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _ZN3std10sys_common9backtrace28__rust_begin_short_backtrace17hdc5561e290b90f55E, .Lfunc_end0-_ZN3std10sys_common9backtrace28__rust_begin_short_backtrace17hdc5561e290b90f55E
.cfi_endproc
.section .text._ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE,"ax",@progbits
.hidden _ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE
.globl _ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE
.p2align 4, 0x90
.type _ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE,@function
_ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE:
.cfi_startproc
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %ecx, %eax
movq %rdx, %rcx
movq %rsi, %rdx
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rdi
leaq .L__unnamed_1(%rip), %rsi
movzbl %al, %r8d
callq *_ZN3std2rt19lang_start_internal17h103c42a9c4e95084E@GOTPCREL(%rip)
movq %rax, 8(%rsp)
movq 8(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE, .Lfunc_end1-_ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE
.cfi_endproc
.section ".text._ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E","ax",@progbits
.p2align 4, 0x90
.type _ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E,@function
_ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E:
.cfi_startproc
pushq %rax
.cfi_def_cfa_offset 16
movq (%rdi), %rdi
callq _ZN3std10sys_common9backtrace28__rust_begin_short_backtrace17hdc5561e290b90f55E
callq _ZN54_$LT$$LP$$RP$$u20$as$u20$std..process..Termination$GT$6report17h6264d63e158d705fE
movb %al, 7(%rsp)
movzbl 7(%rsp), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E, .Lfunc_end2-_ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E
.cfi_endproc
.section ".text._ZN4core3fmt3num49_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i8$GT$3fmt17h710136c20779e432E","ax",@progbits
.p2align 4, 0x90
.type _ZN4core3fmt3num49_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i8$GT$3fmt17h710136c20779e432E,@function
_ZN4core3fmt3num49_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i8$GT$3fmt17h710136c20779e432E:
.cfi_startproc
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl 52(%rsi), %eax
andl $16, %eax
cmpl $0, %eax
jne .LBB3_2
movq 8(%rsp), %rax
movl 52(%rax), %eax
andl $32, %eax
cmpl $0, %eax
je .LBB3_3
jmp .LBB3_4
.LBB3_2:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
callq *_ZN4core3fmt3num52_$LT$impl$u20$core..fmt..LowerHex$u20$for$u20$i8$GT$3fmt17hdbfbac826279eebbE@GOTPCREL(%rip)
andb $1, %al
movb %al, 23(%rsp)
jmp .LBB3_6
.LBB3_3:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
callq *_ZN4core3fmt3num3imp51_$LT$impl$u20$core..fmt..Display$u20$for$u20$i8$GT$3fmt17h1a1f1fb553a4193cE@GOTPCREL(%rip)
andb $1, %al
movb %al, 23(%rsp)
jmp .LBB3_5
.LBB3_4:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
callq *_ZN4core3fmt3num52_$LT$impl$u20$core..fmt..UpperHex$u20$for$u20$i8$GT$3fmt17hfc47048fd9db662cE@GOTPCREL(%rip)
andb $1, %al
movb %al, 23(%rsp)
.LBB3_5:
jmp .LBB3_6
.LBB3_6:
movb 23(%rsp), %al
andb $1, %al
movzbl %al, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN4core3fmt3num49_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i8$GT$3fmt17h710136c20779e432E, .Lfunc_end3-_ZN4core3fmt3num49_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i8$GT$3fmt17h710136c20779e432E
.cfi_endproc
.section ".text._ZN4core3fmt3num50_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i32$GT$3fmt17h6b678428da971659E","ax",@progbits
.p2align 4, 0x90
.type _ZN4core3fmt3num50_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i32$GT$3fmt17h6b678428da971659E,@function
_ZN4core3fmt3num50_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i32$GT$3fmt17h6b678428da971659E:
.cfi_startproc
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl 52(%rsi), %eax
andl $16, %eax
cmpl $0, %eax
jne .LBB4_2
movq 8(%rsp), %rax
movl 52(%rax), %eax
andl $32, %eax
cmpl $0, %eax
je .LBB4_3
jmp .LBB4_4
.LBB4_2:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
callq *_ZN4core3fmt3num53_$LT$impl$u20$core..fmt..LowerHex$u20$for$u20$i32$GT$3fmt17hfa7878fdd9a3147fE@GOTPCREL(%rip)
andb $1, %al
movb %al, 23(%rsp)
jmp .LBB4_6
.LBB4_3:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
callq *_ZN4core3fmt3num3imp52_$LT$impl$u20$core..fmt..Display$u20$for$u20$i32$GT$3fmt17h299accfbede7160dE@GOTPCREL(%rip)
andb $1, %al
movb %al, 23(%rsp)
jmp .LBB4_5
.LBB4_4:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
callq *_ZN4core3fmt3num53_$LT$impl$u20$core..fmt..UpperHex$u20$for$u20$i32$GT$3fmt17h67ec8c896098cb14E@GOTPCREL(%rip)
andb $1, %al
movb %al, 23(%rsp)
.LBB4_5:
jmp .LBB4_6
.LBB4_6:
movb 23(%rsp), %al
andb $1, %al
movzbl %al, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _ZN4core3fmt3num50_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i32$GT$3fmt17h6b678428da971659E, .Lfunc_end4-_ZN4core3fmt3num50_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i32$GT$3fmt17h6b678428da971659E
.cfi_endproc
.section .text._ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E,"ax",@progbits
.p2align 4, 0x90
.type _ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E,@function
_ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %r8, 8(%rsp)
movq %rcx, 16(%rsp)
movq %rdx, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdi, 40(%rsp)
movq %rdi, 48(%rsp)
cmpq %r8, %rdx
jb .LBB5_2
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
addq $1, %rcx
cmpq %rcx, %rax
ja .LBB5_4
jmp .LBB5_3
.LBB5_2:
leaq .L__unnamed_2(%rip), %rax
movq %rax, 56(%rsp)
movq $1, 64(%rsp)
movq .L__unnamed_3(%rip), %rcx
movq .L__unnamed_3+8(%rip), %rax
movq %rcx, 88(%rsp)
movq %rax, 96(%rsp)
leaq .L__unnamed_4(%rip), %rax
movq %rax, 72(%rsp)
movq $0, 80(%rsp)
leaq .L__unnamed_5(%rip), %rsi
movq _ZN4core9panicking9panic_fmt17h940d4fd01a4b4fd1E@GOTPCREL(%rip), %rax
leaq 56(%rsp), %rdi
callq *%rax
.LBB5_3:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
movq 32(%rsp), %r8
movq %r8, (%rcx)
movq %rdi, 8(%rcx)
movq .L__unnamed_3(%rip), %r8
movq .L__unnamed_3+8(%rip), %rdi
movq %r8, 32(%rcx)
movq %rdi, 40(%rcx)
movq %rsi, 16(%rcx)
movq %rdx, 24(%rcx)
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.LBB5_4:
.cfi_def_cfa_offset 112
jmp .LBB5_2
.Lfunc_end5:
.size _ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E, .Lfunc_end5-_ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E
.cfi_endproc
.section ".text._ZN4core3ops8function6FnOnce40call_once$u7b$$u7b$vtable.shim$u7d$$u7d$17h013a9584cdc8fc8bE","ax",@progbits
.p2align 4, 0x90
.type _ZN4core3ops8function6FnOnce40call_once$u7b$$u7b$vtable.shim$u7d$$u7d$17h013a9584cdc8fc8bE,@function
_ZN4core3ops8function6FnOnce40call_once$u7b$$u7b$vtable.shim$u7d$$u7d$17h013a9584cdc8fc8bE:
.cfi_startproc
pushq %rax
.cfi_def_cfa_offset 16
movq (%rdi), %rdi
callq _ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _ZN4core3ops8function6FnOnce40call_once$u7b$$u7b$vtable.shim$u7d$$u7d$17h013a9584cdc8fc8bE, .Lfunc_end6-_ZN4core3ops8function6FnOnce40call_once$u7b$$u7b$vtable.shim$u7d$$u7d$17h013a9584cdc8fc8bE
.cfi_endproc
.section .text._ZN4core3ops8function6FnOnce9call_once17h0d82d9de4027e050E,"ax",@progbits
.p2align 4, 0x90
.type _ZN4core3ops8function6FnOnce9call_once17h0d82d9de4027e050E,@function
_ZN4core3ops8function6FnOnce9call_once17h0d82d9de4027e050E:
.cfi_startproc
pushq %rax
.cfi_def_cfa_offset 16
callq *%rdi
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _ZN4core3ops8function6FnOnce9call_once17h0d82d9de4027e050E, .Lfunc_end7-_ZN4core3ops8function6FnOnce9call_once17h0d82d9de4027e050E
.cfi_endproc
.section .text._ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E,"ax",@progbits
.p2align 4, 0x90
.type _ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E,@function
_ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E:
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 155, DW.ref.rust_eh_personality
.cfi_lsda 27, .Lexception0
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, 8(%rsp)
.Ltmp0:
leaq 8(%rsp), %rdi
callq _ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E
.Ltmp1:
movl %eax, 4(%rsp)
jmp .LBB8_3
.LBB8_1:
movq 24(%rsp), %rdi
callq _Unwind_Resume@PLT
.LBB8_2:
.Ltmp2:
movq %rax, %rcx
movl %edx, %eax
movq %rcx, 24(%rsp)
movl %eax, 32(%rsp)
jmp .LBB8_1
.LBB8_3:
movl 4(%rsp), %eax
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E, .Lfunc_end8-_ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E
.cfi_endproc
.section .gcc_except_table._ZN4core3ops8function6FnOnce9call_once17hdd8f36ee4883eef0E,"a",@progbits
.p2align 2, 0x0
GCC_except_table8:
.Lexception0:
.byte 255
.byte 255
.byte 1
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0
.uleb128 .Ltmp1-.Ltmp0
.uleb128 .Ltmp2-.Lfunc_begin0
.byte 0
.uleb128 .Ltmp1-.Lfunc_begin0
.uleb128 .Lfunc_end8-.Ltmp1
.byte 0
.byte 0
.Lcst_end0:
.p2align 2, 0x0
.section ".text._ZN4core3ptr85drop_in_place$LT$std..rt..lang_start$LT$$LP$$RP$$GT$..$u7b$$u7b$closure$u7d$$u7d$$GT$17h2a02b1020a9b7772E","ax",@progbits
.p2align 4, 0x90
.type _ZN4core3ptr85drop_in_place$LT$std..rt..lang_start$LT$$LP$$RP$$GT$..$u7b$$u7b$closure$u7d$$u7d$$GT$17h2a02b1020a9b7772E,@function
_ZN4core3ptr85drop_in_place$LT$std..rt..lang_start$LT$$LP$$RP$$GT$..$u7b$$u7b$closure$u7d$$u7d$$GT$17h2a02b1020a9b7772E:
.cfi_startproc
retq
.Lfunc_end9:
.size _ZN4core3ptr85drop_in_place$LT$std..rt..lang_start$LT$$LP$$RP$$GT$..$u7b$$u7b$closure$u7d$$u7d$$GT$17h2a02b1020a9b7772E, .Lfunc_end9-_ZN4core3ptr85drop_in_place$LT$std..rt..lang_start$LT$$LP$$RP$$GT$..$u7b$$u7b$closure$u7d$$u7d$$GT$17h2a02b1020a9b7772E
.cfi_endproc
.section ".text._ZN54_$LT$$LP$$RP$$u20$as$u20$std..process..Termination$GT$6report17h6264d63e158d705fE","ax",@progbits
.p2align 4, 0x90
.type _ZN54_$LT$$LP$$RP$$u20$as$u20$std..process..Termination$GT$6report17h6264d63e158d705fE,@function
_ZN54_$LT$$LP$$RP$$u20$as$u20$std..process..Termination$GT$6report17h6264d63e158d705fE:
.cfi_startproc
xorl %eax, %eax
retq
.Lfunc_end10:
.size _ZN54_$LT$$LP$$RP$$u20$as$u20$std..process..Termination$GT$6report17h6264d63e158d705fE, .Lfunc_end10-_ZN54_$LT$$LP$$RP$$u20$as$u20$std..process..Termination$GT$6report17h6264d63e158d705fE
.cfi_endproc
.section .text._ZN2a816print_drink_info17h3b89554d6f624319E,"ax",@progbits
.p2align 4, 0x90
.type _ZN2a816print_drink_info17h3b89554d6f624319E,@function
_ZN2a816print_drink_info17h3b89554d6f624319E:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movb %sil, %cl
movb %dil, %al
movb %al, 6(%rsp)
leaq 7(%rsp), %rax
movb %cl, 7(%rsp)
leaq 6(%rsp), %rcx
movq %rcx, 88(%rsp)
leaq _ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E(%rip), %rcx
movq %rcx, 96(%rsp)
movq 88(%rsp), %rsi
movq 96(%rsp), %rdx
movq %rax, 104(%rsp)
leaq _ZN4core3fmt3num49_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i8$GT$3fmt17h710136c20779e432E(%rip), %rax
movq %rax, 112(%rsp)
movq 104(%rsp), %rcx
movq 112(%rsp), %rax
movq %rsi, 56(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq .L__unnamed_6(%rip), %rsi
movl $3, %edx
leaq 56(%rsp), %rcx
movl $2, %r8d
callq _ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E
leaq 8(%rsp), %rdi
callq *_ZN3std2io5stdio6_print17h5c2f653c9c3347e5E@GOTPCREL(%rip)
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _ZN2a816print_drink_info17h3b89554d6f624319E, .Lfunc_end11-_ZN2a816print_drink_info17h3b89554d6f624319E
.cfi_endproc
.section .text._ZN2a84main17h23503ad0f97faaa8E,"ax",@progbits
.p2align 4, 0x90
.type _ZN2a84main17h23503ad0f97faaa8E,@function
_ZN2a84main17h23503ad0f97faaa8E:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movb $1, 7(%rsp)
movb 7(%rsp), %al
movb %al, 5(%rsp)
movb $1, 6(%rsp)
movl $1, 8(%rsp)
leaq 12(%rsp), %rax
movl $2, 12(%rsp)
movl $3, 16(%rsp)
movl $4, 20(%rsp)
movl $9, 8(%rsp)
movq %rax, 88(%rsp)
leaq _ZN4core3fmt3num50_$LT$impl$u20$core..fmt..Debug$u20$for$u20$i32$GT$3fmt17h6b678428da971659E(%rip), %rax
movq %rax, 96(%rsp)
movq 88(%rsp), %rcx
movq 96(%rsp), %rax
movq %rcx, 72(%rsp)
movq %rax, 80(%rsp)
leaq 24(%rsp), %rdi
leaq .L__unnamed_7(%rip), %rsi
movl $2, %edx
leaq 72(%rsp), %rcx
movl $1, %r8d
callq _ZN4core3fmt9Arguments6new_v117hb68d7b39eb7841b3E
leaq 24(%rsp), %rdi
callq *_ZN3std2io5stdio6_print17h5c2f653c9c3347e5E@GOTPCREL(%rip)
movb 5(%rsp), %al
movzbl %al, %edi
movzbl 6(%rsp), %esi
callq _ZN2a816print_drink_info17h3b89554d6f624319E
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size _ZN2a84main17h23503ad0f97faaa8E, .Lfunc_end12-_ZN2a84main17h23503ad0f97faaa8E
.cfi_endproc
.section ".text._ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E","ax",@progbits
.p2align 4, 0x90
.type _ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E,@function
_ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E:
.cfi_startproc
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rsi, 8(%rsp)
movzbl (%rdi), %eax
movq %rax, 16(%rsp)
movq 16(%rsp), %rax
leaq .LJTI13_0(%rip), %rcx
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
.cfi_def_cfa_offset 8
ud2
.LBB13_2:
.cfi_def_cfa_offset 48
leaq .L__unnamed_8(%rip), %rax
movq %rax, 24(%rsp)
movq $7, 32(%rsp)
jmp .LBB13_6
.LBB13_3:
leaq .L__unnamed_9(%rip), %rax
movq %rax, 24(%rsp)
movq $4, 32(%rsp)
jmp .LBB13_6
.LBB13_4:
leaq .L__unnamed_10(%rip), %rax
movq %rax, 24(%rsp)
movq $9, 32(%rsp)
jmp .LBB13_6
.LBB13_5:
leaq .L__unnamed_11(%rip), %rax
movq %rax, 24(%rsp)
movq $6, 32(%rsp)
.LBB13_6:
movq 8(%rsp), %rdi
movq 24(%rsp), %rsi
movq 32(%rsp), %rdx
callq *_ZN4core3fmt9Formatter9write_str17h6c3af88f9efb7dc3E@GOTPCREL(%rip)
andb $1, %al
movzbl %al, %eax
addq $40, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end13:
.size _ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E, .Lfunc_end13-_ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E
.cfi_endproc
.section ".rodata._ZN48_$LT$a8..Flavour$u20$as$u20$core..fmt..Debug$GT$3fmt17he86c2dec98ae1167E","a",@progbits
.p2align 2, 0x0
.LJTI13_0:
.long .LBB13_2-.LJTI13_0
.long .LBB13_3-.LJTI13_0
.long .LBB13_4-.LJTI13_0
.long .LBB13_5-.LJTI13_0
.section .text.main,"ax",@progbits
.globl main
.p2align 4, 0x90
.type main,@function
main:
.cfi_startproc
pushq %rax
.cfi_def_cfa_offset 16
movq %rsi, %rdx
movslq %edi, %rsi
leaq _ZN2a84main17h23503ad0f97faaa8E(%rip), %rdi
xorl %ecx, %ecx
callq _ZN3std2rt10lang_start17h1d85cc9c5f0f8f5dE
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end14:
.size main, .Lfunc_end14-main
.cfi_endproc
.type .L__unnamed_1,@object
.section .data.rel.ro..L__unnamed_1,"aw",@progbits
.p2align 3, 0x0
.L__unnamed_1:
.quad _ZN4core3ptr85drop_in_place$LT$std..rt..lang_start$LT$$LP$$RP$$GT$..$u7b$$u7b$closure$u7d$$u7d$$GT$17h2a02b1020a9b7772E
.asciz "\b\000\000\000\000\000\000\000\b\000\000\000\000\000\000"
.quad _ZN4core3ops8function6FnOnce40call_once$u7b$$u7b$vtable.shim$u7d$$u7d$17h013a9584cdc8fc8bE
.quad _ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E
.quad _ZN3std2rt10lang_start28_$u7b$$u7b$closure$u7d$$u7d$17ha09050c358b08b10E
.size .L__unnamed_1, 48
.type .L__unnamed_3,@object
.section .rodata.cst16,"aM",@progbits,16
.p2align 3, 0x0
.L__unnamed_3:
.zero 8
.zero 8
.size .L__unnamed_3, 16
.type .L__unnamed_12,@object
.section .rodata..L__unnamed_12,"a",@progbits
.L__unnamed_12:
.ascii "invalid args"
.size .L__unnamed_12, 12
.type .L__unnamed_2,@object
.section .data.rel.ro..L__unnamed_2,"aw",@progbits
.p2align 3, 0x0
.L__unnamed_2:
.quad .L__unnamed_12
.asciz "\f\000\000\000\000\000\000"
.size .L__unnamed_2, 16
.type .L__unnamed_4,@object
.section .rodata..L__unnamed_4,"a",@progbits
.p2align 3, 0x0
.L__unnamed_4:
.size .L__unnamed_4, 0
.type .L__unnamed_13,@object
.section .rodata..L__unnamed_13,"a",@progbits
.L__unnamed_13:
.ascii "/rustc/9b00956e56009bab2aa15d7bff10916599e3d6d6/library/core/src/fmt/mod.rs"
.size .L__unnamed_13, 75
.type .L__unnamed_5,@object
.section .data.rel.ro..L__unnamed_5,"aw",@progbits
.p2align 3, 0x0
.L__unnamed_5:
.quad .L__unnamed_13
.asciz "K\000\000\000\000\000\000\000U\001\000\000\r\000\000"
.size .L__unnamed_5, 24
.type .L__unnamed_14,@object
.section .rodata..L__unnamed_14,"a",@progbits
.L__unnamed_14:
.ascii "This drink has "
.size .L__unnamed_14, 15
.type .L__unnamed_15,@object
.section .rodata..L__unnamed_15,"a",@progbits
.L__unnamed_15:
.ascii " flavour and it's "
.size .L__unnamed_15, 18
.type .L__unnamed_16,@object
.section .rodata..L__unnamed_16,"a",@progbits
.L__unnamed_16:
.ascii "L\n"
.size .L__unnamed_16, 2
.type .L__unnamed_6,@object
.section .data.rel.ro..L__unnamed_6,"aw",@progbits
.p2align 3, 0x0
.L__unnamed_6:
.quad .L__unnamed_14
.asciz "\017\000\000\000\000\000\000"
.quad .L__unnamed_15
.asciz "\022\000\000\000\000\000\000"
.quad .L__unnamed_16
.asciz "\002\000\000\000\000\000\000"
.size .L__unnamed_6, 48
.type .L__unnamed_17,@object
.section .rodata..L__unnamed_17,"a",@progbits
.L__unnamed_17:
.byte 10
.size .L__unnamed_17, 1
.type .L__unnamed_7,@object
.section .data.rel.ro..L__unnamed_7,"aw",@progbits
.p2align 3, 0x0
.L__unnamed_7:
.quad .L__unnamed_4
.zero 8
.quad .L__unnamed_17
.asciz "\001\000\000\000\000\000\000"
.size .L__unnamed_7, 32
.type .L__unnamed_8,@object
.section .rodata..L__unnamed_8,"a",@progbits
.L__unnamed_8:
.ascii "Vanilla"
.size .L__unnamed_8, 7
.type .L__unnamed_9,@object
.section .rodata.cst4,"aM",@progbits,4
.L__unnamed_9:
.ascii "Lime"
.size .L__unnamed_9, 4
.type .L__unnamed_10,@object
.section .rodata..L__unnamed_10,"a",@progbits
.L__unnamed_10:
.ascii "Chocolate"
.size .L__unnamed_10, 9
.type .L__unnamed_11,@object
.section .rodata..L__unnamed_11,"a",@progbits
.L__unnamed_11:
.ascii "Orange"
.size .L__unnamed_11, 6
.hidden DW.ref.rust_eh_personality
.weak DW.ref.rust_eh_personality
.section .data.DW.ref.rust_eh_personality,"awG",@progbits,DW.ref.rust_eh_personality,comdat
.p2align 3, 0x0
.type DW.ref.rust_eh_personality,@object
.size DW.ref.rust_eh_personality, 8
DW.ref.rust_eh_personality:
.quad rust_eh_personality
.ident "rustc version 1.78.0 (9b00956e5 2024-04-29)"
.section ".note.GNU-stack","",@progbits
|
fberlakovich/cmq-ae | 776 | Python/asm_trampoline.S | .text
.globl _Py_trampoline_func_start
# The following assembly is equivalent to:
# PyObject *
# trampoline(PyThreadState *ts, _PyInterpreterFrame *f,
# int throwflag, py_evaluator evaluator)
# {
# return evaluator(ts, f, throwflag);
# }
_Py_trampoline_func_start:
#ifdef __x86_64__
sub $8, %rsp
call *%rcx
add $8, %rsp
ret
#endif // __x86_64__
#if defined(__aarch64__) && defined(__AARCH64EL__) && !defined(__ILP32__)
// ARM64 little endian, 64bit ABI
// generate with aarch64-linux-gnu-gcc 12.1
stp x29, x30, [sp, -16]!
mov x29, sp
blr x3
ldp x29, x30, [sp], 16
ret
#endif
.globl _Py_trampoline_func_end
_Py_trampoline_func_end:
.section .note.GNU-stack,"",@progbits
|
fedi-nabli/ARM-bare-metal-booting-for-QEMU | 597 | startup.S | .section ".text.boot"
.global _start
_start:
// Check processor ID is 0 (primary core)
mrs x0, mpidr_el1
and x0, x0, #0xFF
cbz x0, setup_stack
// If we're not on CPU0, wait forever
b wait_forever
setup_stack:
// Setup up stack before C code
ldr x0, =_start
mov sp, x0
// Clearn BSS section
ldr x0, =__bss_start
ldr x1, =__bss_end
cmp x0, x1
b.eq call_main
clear_bss_loop:
str xzr, [x0], #8
cmp x0, x1
b.lo clear_bss_loop
call_main:
// Call the C kernel main
bl kernel_main
wait_forever:
// If return or not on CPU0, wait forever
wfe
b wait_forever |
fedi-nabli/ARM-bare-metal-booting-for-QEMU | 386 | asm_funcs.S | .global asm_test_func
.section ".text"
// Simple function that multiplies two numbers
// x0, first parameter
// x1, second parameter
// result in x0
asm_test_func:
// Save the frame pointer and link register
stp x29, x30, [sp, #-16]!
mov x29, sp
// Multiply the two parameters
mul x0, x0, x1
// Restore the frame pointer and link register
ldp x29, x30, [sp], #16
ret |
FeeYo7/ross | 418 | kern/src/init/init.s | .section .text.init
.global _start
_start:
// read cpu affinity, start core 0, halt rest
mrs x1, mpidr_el1
and x1, x1, #3
cbz x1, 2f
1:
// core affinity != 0, halt it
wfe
b 1b
2:
// set the stack to start before our boot code
adr x1, _start
mov sp, x1
// jump to kinit, which shouldn't return. halt if it does
bl kinit
b 1b
|
FeeYo7/ross | 418 | boot/src/init/init.s | .section .text.init
.global _start
_start:
// read cpu affinity, start core 0, halt rest
mrs x1, mpidr_el1
and x1, x1, #3
cbz x1, 2f
1:
// core affinity != 0, halt it
wfe
b 1b
2:
// set the stack to start before our boot code
adr x1, _start
mov sp, x1
// jump to kinit, which shouldn't return. halt if it does
bl kinit
b 1b
|
fff1214/SoC-Final | 6,209 | Final/sdram/firmware/start_pico.S | /*
* Copyright 2018, Serge Bazanski <serge@bazanski.pl>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted.
*/
#include "../extraops.S"
/*
* Interrupt vector.
*/
.global _start
_start:
.org 0x00000000 # Reset
j _crt0
.org 0x00000010 # IRQ
_irq_vector:
addi sp, sp, -16
sw t0, 4(sp)
sw ra, 8(sp)
/* By convention, q2 holds true IRQ vector, but remains caller-save.
We rely on the assumption that compiler-generated code will never touch
the QREGs. q3 is truly scratch/caller-save. */
picorv32_getq_insn(t0, q2)
sw t0, 12(sp)
jalr t0 // Call the true IRQ vector.
lw t0, 12(sp)
picorv32_setq_insn(q2, t0) // Restore the true IRQ vector.
lw ra, 8(sp)
lw t0, 4(sp)
addi sp, sp, 16
picorv32_retirq_insn() // return from interrupt
/*
* IRQ handler, branched to from the vector.
*/
_irq:
/* save x1/x2 to q1/q2 */
picorv32_setq_insn(q2, x1)
picorv32_setq_insn(q3, x2)
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* use x2 as scratch space for saving registers */
/* q0 (== x1), q2(== x2), q3 */
picorv32_getq_insn(x2, q0)
sw x2, 0*4(x1)
picorv32_getq_insn(x2, q2)
sw x2, 1*4(x1)
picorv32_getq_insn(x2, q3)
sw x2, 2*4(x1)
/* save x3 - x31 */
sw x3, 3*4(x1)
sw x4, 4*4(x1)
sw x5, 5*4(x1)
sw x6, 6*4(x1)
sw x7, 7*4(x1)
sw x8, 8*4(x1)
sw x9, 9*4(x1)
sw x10, 10*4(x1)
sw x11, 11*4(x1)
sw x12, 12*4(x1)
sw x13, 13*4(x1)
sw x14, 14*4(x1)
sw x15, 15*4(x1)
sw x16, 16*4(x1)
sw x17, 17*4(x1)
sw x18, 18*4(x1)
sw x19, 19*4(x1)
sw x20, 20*4(x1)
sw x21, 21*4(x1)
sw x22, 22*4(x1)
sw x23, 23*4(x1)
sw x24, 24*4(x1)
sw x25, 25*4(x1)
sw x26, 26*4(x1)
sw x27, 27*4(x1)
sw x28, 28*4(x1)
sw x29, 29*4(x1)
sw x30, 30*4(x1)
sw x31, 31*4(x1)
/* update _irq_pending to the currently pending interrupts */
picorv32_getq_insn(t0, q1)
la t1, (_irq_pending)
sw t0, 0(t1)
/* prepare C handler stack */
lui sp, %hi(_irq_stack)
addi sp, sp, %lo(_irq_stack)
/* call C handler */
jal ra, isr
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* restore q0 - q2 */
lw x2, 0*4(x1)
picorv32_setq_insn(q0, x2)
lw x2, 1*4(x1)
picorv32_setq_insn(q1, x2)
lw x2, 2*4(x1)
picorv32_setq_insn(q2, x2)
/* restore x3 - x31 */
lw x3, 3*4(x1)
lw x4, 4*4(x1)
lw x5, 5*4(x1)
lw x6, 6*4(x1)
lw x7, 7*4(x1)
lw x8, 8*4(x1)
lw x9, 9*4(x1)
lw x10, 10*4(x1)
lw x11, 11*4(x1)
lw x12, 12*4(x1)
lw x13, 13*4(x1)
lw x14, 14*4(x1)
lw x15, 15*4(x1)
lw x16, 16*4(x1)
lw x17, 17*4(x1)
lw x18, 18*4(x1)
lw x19, 19*4(x1)
lw x20, 20*4(x1)
lw x21, 21*4(x1)
lw x22, 22*4(x1)
lw x23, 23*4(x1)
lw x24, 24*4(x1)
lw x25, 25*4(x1)
lw x26, 26*4(x1)
lw x27, 27*4(x1)
lw x28, 28*4(x1)
lw x29, 29*4(x1)
lw x30, 30*4(x1)
lw x31, 31*4(x1)
/* restore x1 - x2 from q registers */
picorv32_getq_insn(x1, q1)
picorv32_getq_insn(x2, q2)
ret
/*
* Reset handler, branched to from the vector.
*/
_crt0:
/* zero-initialize all registers */
addi x1, zero, 0
addi x2, zero, 0
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
/* mask all interrupts */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* reflect that in _irq_mask */
la t1, _irq_mask
sw t0, 0(t1)
/* Load DATA */
la t0, _fdata_rom
la t1, _fdata
la t2, _edata
3:
lw t3, 0(t0)
sw t3, 0(t1)
/* _edata is aligned to 16 bytes. Use word-xfers. */
addi t0, t0, 4
addi t1, t1, 4
bltu t1, t2, 3b
/* Clear BSS */
#la t0, _fbss
#la t1, _ebss
2:
#sw zero, 0(t0)
#addi t0, t0, 4
#bltu t0, t1, 2b
/* set main stack */
la sp, _fstack
/* Set up address to IRQ handler since vector is hardcoded.
By convention, q2 keeps the pointer to the true IRQ handler,
to emulate relocatable interrupts. */
la t0, _irq
picorv32_setq_insn(q2, t0)
/* jump to main */
jal ra, main
1:
/* loop forever */
j 1b
/*
* Enable interrupts by copying the software mask to the hardware mask
*/
.global _irq_enable
_irq_enable:
/* Set _irq_enabled to true */
la t0, _irq_enabled
addi t1, zero, 1
sw t1, 0(t0)
/* Set the HW IRQ mask to _irq_mask */
la t0, _irq_mask
lw t0, 0(t0)
picorv32_maskirq_insn(zero, t0)
ret
/*
* Disable interrupts by masking all interrupts (the mask should already be
* up to date)
*/
.global _irq_disable
_irq_disable:
/* Mask all IRQs */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* Set _irq_enabled to false */
la t0, _irq_enabled
sw zero, (t0)
ret
/*
* Set interrrupt mask.
* This updates the software mask (for readback and interrupt inable/disable)
* and the hardware mask.
* 1 means interrupt is masked (disabled).
*/
.global _irq_setmask
_irq_setmask:
/* Update _irq_mask */
la t0, _irq_mask
sw a0, (t0)
/* Are interrupts enabled? */
la t0, _irq_enabled
lw t0, 0(t0)
beq t0, zero, 1f
/* If so, update the HW IRQ mask */
picorv32_maskirq_insn(zero, a0)
1:
ret
.section .bss
irq_regs:
/* saved interrupt registers, x0 - x31 */
.fill 32,4
/* interrupt stack */
.fill 256,4
_irq_stack:
/*
* Bitfield of pending interrupts, updated on ISR entry.
*/
.global _irq_pending
_irq_pending:
.word 0
/*
* Software copy of enabled interrupts. Do not write directly, use
* _irq_set_mask instead.
*/
.global _irq_mask
_irq_mask:
.word 0
/*
* Software state of global interrupts being enabled or disabled. Do not write
* directly, use _irq_disable / _irq_enable instead.
*/
.global _irq_enabled
_irq_enabled:
.word 0
|
fff1214/SoC-Final | 2,655 | Final/sdram/firmware/extraops.S | // This is free and unencumbered software released into the public domain.
//
// Anyone is free to copy, modify, publish, use, compile, sell, or
// distribute this software, either in source code form or as a compiled
// binary, for any purpose, commercial or non-commercial, and by any
// means.
#define regnum_q0 0
#define regnum_q1 1
#define regnum_q2 2
#define regnum_q3 3
#define regnum_x0 0
#define regnum_x1 1
#define regnum_x2 2
#define regnum_x3 3
#define regnum_x4 4
#define regnum_x5 5
#define regnum_x6 6
#define regnum_x7 7
#define regnum_x8 8
#define regnum_x9 9
#define regnum_x10 10
#define regnum_x11 11
#define regnum_x12 12
#define regnum_x13 13
#define regnum_x14 14
#define regnum_x15 15
#define regnum_x16 16
#define regnum_x17 17
#define regnum_x18 18
#define regnum_x19 19
#define regnum_x20 20
#define regnum_x21 21
#define regnum_x22 22
#define regnum_x23 23
#define regnum_x24 24
#define regnum_x25 25
#define regnum_x26 26
#define regnum_x27 27
#define regnum_x28 28
#define regnum_x29 29
#define regnum_x30 30
#define regnum_x31 31
#define regnum_zero 0
#define regnum_ra 1
#define regnum_sp 2
#define regnum_gp 3
#define regnum_tp 4
#define regnum_t0 5
#define regnum_t1 6
#define regnum_t2 7
#define regnum_s0 8
#define regnum_s1 9
#define regnum_a0 10
#define regnum_a1 11
#define regnum_a2 12
#define regnum_a3 13
#define regnum_a4 14
#define regnum_a5 15
#define regnum_a6 16
#define regnum_a7 17
#define regnum_s2 18
#define regnum_s3 19
#define regnum_s4 20
#define regnum_s5 21
#define regnum_s6 22
#define regnum_s7 23
#define regnum_s8 24
#define regnum_s9 25
#define regnum_s10 26
#define regnum_s11 27
#define regnum_t3 28
#define regnum_t4 29
#define regnum_t5 30
#define regnum_t6 31
// x8 is s0 and also fp
#define regnum_fp 8
#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
#define picorv32_getq_insn(_rd, _qs) \
r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
#define picorv32_setq_insn(_qd, _rs) \
r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
#define picorv32_retirq_insn() \
r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
#define picorv32_maskirq_insn(_rd, _rs) \
r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
#define picorv32_waitirq_insn(_rd) \
r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
#define picorv32_timer_insn(_rd, _rs) \
r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
|
fff1214/SoC-Final | 1,662 | Final/sdram/firmware/crt0_vex.S | .global main
.global isr
.global _start
_start:
j crt_init
nop
nop
nop
nop
nop
nop
nop
.global trap_entry
trap_entry:
sw x1, - 1*4(sp)
sw x5, - 2*4(sp)
sw x6, - 3*4(sp)
sw x7, - 4*4(sp)
sw x10, - 5*4(sp)
sw x11, - 6*4(sp)
sw x12, - 7*4(sp)
sw x13, - 8*4(sp)
sw x14, - 9*4(sp)
sw x15, -10*4(sp)
sw x16, -11*4(sp)
sw x17, -12*4(sp)
sw x28, -13*4(sp)
sw x29, -14*4(sp)
sw x30, -15*4(sp)
sw x31, -16*4(sp)
addi sp,sp,-16*4
call isr
lw x1 , 15*4(sp)
lw x5, 14*4(sp)
lw x6, 13*4(sp)
lw x7, 12*4(sp)
lw x10, 11*4(sp)
lw x11, 10*4(sp)
lw x12, 9*4(sp)
lw x13, 8*4(sp)
lw x14, 7*4(sp)
lw x15, 6*4(sp)
lw x16, 5*4(sp)
lw x17, 4*4(sp)
lw x28, 3*4(sp)
lw x29, 2*4(sp)
lw x30, 1*4(sp)
lw x31, 0*4(sp)
addi sp,sp,16*4
mret
.text
crt_init:
la sp, _fstack
la a0, trap_entry
csrw mtvec, a0
sram_init:
la a0, _fsram
la a1, _esram
la a2, _esram_rom
sram_loop:
beq a0,a1,sram_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j sram_loop
sram_done:
data_init:
la a0, _fdata
la a1, _edata
la a2, _fdata_rom
data_loop:
beq a0,a1,data_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j data_loop
data_done:
bss_init:
la a0, _fbss
la a1, _ebss
bss_loop:
beq a0,a1,bss_done
sw zero,0(a0)
add a0,a0,4
#ifndef SIM
j bss_loop
#endif
bss_done:
li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
csrw mie,a0
#ifdef USER_PROJ_IRQ0_EN
csrrs a0, mstatus, 0x8 //0x8 set mstatus.MIE
#endif
call main
infinit_loop:
j infinit_loop
|
fff1214/SoC-Final | 1,803 | Final/sdram/firmware/crt0_ibex.S | # Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#include "simple_system_regs.h"
.section .text
default_exc_handler:
jal x0, simple_exc_handler
timer_handler:
jal x0, simple_timer_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initilization */
# la x2, _stack_start
la x2, 0x01000800
_start:
.global _start
/* clear BSS */
la x26, _bss_start
la x27, _bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
main_entry:
/* jump to main program entry point (argc = argv = 0) */
addi x10, x0, 0
addi x11, x0, 0
jal x1, main
/* Halt simulation */
#li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL
#li x6, 1
#sw x6, 0(x5)
/* If execution ends up here just put the core to sleep */
sleep_loop:
wfi
j sleep_loop
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// All unimplemented interrupts/exceptions go to the default_exc_handler.
.org 0x00
.rept 7
jal x0, default_exc_handler
.endr
jal x0, timer_handler
.rept 23
jal x0, default_exc_handler
.endr
// reset vector
.org 0x80
jal x0, reset_handler
|
fff1214/SoC-Final | 3,215 | Final/sdram/firmware/start_caravel_vexriscv.s | # SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
.section .text
start:
# zero-initialize register file
addi x1, zero, 0
# x2 (sp) is initialized by reset
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
# zero initialize scratchpad memory
# setmemloop:
# sw zero, 0(x1)
# addi x1, x1, 4
# blt x1, sp, setmemloop
# copy data section
la a0, _sidata
la a1, _sdata
la a2, _edata
bge a1, a2, end_init_data
loop_init_data:
lw a3, 0(a0)
sw a3, 0(a1)
addi a0, a0, 4
addi a1, a1, 4
blt a1, a2, loop_init_data
end_init_data:
# zero-init bss section
la a0, _sbss
la a1, _ebss
bge a0, a1, end_init_bss
loop_init_bss:
sw zero, 0(a0)
addi a0, a0, 4
blt a0, a1, loop_init_bss
end_init_bss:
la sp, _fstack
# call main
call main
loop:
j loop
.global flashio_worker_begin
.global flashio_worker_end
.balign 4
flashio_worker_begin:
# a0 ... data pointer
# a1 ... data length
# a2 ... optional WREN cmd (0 = disable)
# address of SPI ctrl reg
li t0, 0x28000000
# Set CS high, IO0 is output
li t1, 0x120
sh t1, 0(t0)
# Enable Manual SPI Ctrl
sb zero, 3(t0)
# Send optional WREN cmd
beqz a2, flashio_worker_L1
li t5, 8
andi t2, a2, 0xff
flashio_worker_L4:
srli t4, t2, 7
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
slli t2, t2, 1
andi t2, t2, 0xff
addi t5, t5, -1
bnez t5, flashio_worker_L4
sb t1, 0(t0)
# SPI transfer
flashio_worker_L1:
# If byte count is zero, we're done
beqz a1, flashio_worker_L3
# Set t5 to count down 32 bits
li t5, 32
# Load t2 from address a0 (4 bytes)
lw t2, 0(a0)
flashio_worker_LY:
# Set t6 to count down 8 bits
li t6, 8
flashio_worker_L2:
# Clock out the bit (msb first) on IO0 and read bit in from IO1
srli t4, t2, 31
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
lbu t4, 0(t0)
andi t4, t4, 2
srli t4, t4, 1
slli t2, t2, 1
or t2, t2, t4
# Decrement 32 bit count
addi t5, t5, -1
bnez t5, flashio_worker_LX
sw t2, 0(a0)
addi a0, a0, 4
lw t2, 0(a0)
flashio_worker_LX:
addi t6, t6, -1
bnez t6, flashio_worker_L2
addi a1, a1, -1
bnez a1, flashio_worker_LY
beqz t5, flashio_worker_L3
sw t2, 0(a0)
flashio_worker_L3:
# Back to MEMIO mode
li t1, 0x80
sb t1, 3(t0)
ret
.balign 4
flashio_worker_end:
|
fff1214/SoC-Final | 3,199 | Final/sdram/firmware/start_caravel_ibex.s | # SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
.section .text
start:
# zero-initialize register file
addi x1, zero, 0
# x2 (sp) is initialized by reset
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
# zero initialize scratchpad memory
# setmemloop:
# sw zero, 0(x1)
# addi x1, x1, 4
# blt x1, sp, setmemloop
# copy data section
la a0, _sidata
la a1, _sdata
la a2, _edata
bge a1, a2, end_init_data
loop_init_data:
lw a3, 0(a0)
sw a3, 0(a1)
addi a0, a0, 4
addi a1, a1, 4
blt a1, a2, loop_init_data
end_init_data:
# zero-init bss section
la a0, _sbss
la a1, _ebss
bge a0, a1, end_init_bss
loop_init_bss:
sw zero, 0(a0)
addi a0, a0, 4
blt a0, a1, loop_init_bss
end_init_bss:
# call main
call main
loop:
j loop
.global flashio_worker_begin
.global flashio_worker_end
.balign 4
flashio_worker_begin:
# a0 ... data pointer
# a1 ... data length
# a2 ... optional WREN cmd (0 = disable)
# address of SPI ctrl reg
li t0, 0x28000000
# Set CS high, IO0 is output
li t1, 0x120
sh t1, 0(t0)
# Enable Manual SPI Ctrl
sb zero, 3(t0)
# Send optional WREN cmd
beqz a2, flashio_worker_L1
li t5, 8
andi t2, a2, 0xff
flashio_worker_L4:
srli t4, t2, 7
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
slli t2, t2, 1
andi t2, t2, 0xff
addi t5, t5, -1
bnez t5, flashio_worker_L4
sb t1, 0(t0)
# SPI transfer
flashio_worker_L1:
# If byte count is zero, we're done
beqz a1, flashio_worker_L3
# Set t5 to count down 32 bits
li t5, 32
# Load t2 from address a0 (4 bytes)
lw t2, 0(a0)
flashio_worker_LY:
# Set t6 to count down 8 bits
li t6, 8
flashio_worker_L2:
# Clock out the bit (msb first) on IO0 and read bit in from IO1
srli t4, t2, 31
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
lbu t4, 0(t0)
andi t4, t4, 2
srli t4, t4, 1
slli t2, t2, 1
or t2, t2, t4
# Decrement 32 bit count
addi t5, t5, -1
bnez t5, flashio_worker_LX
sw t2, 0(a0)
addi a0, a0, 4
lw t2, 0(a0)
flashio_worker_LX:
addi t6, t6, -1
bnez t6, flashio_worker_L2
addi a1, a1, -1
bnez a1, flashio_worker_LY
beqz t5, flashio_worker_L3
sw t2, 0(a0)
flashio_worker_L3:
# Back to MEMIO mode
li t1, 0x80
sb t1, 3(t0)
ret
.balign 4
flashio_worker_end:
|
fff1214/SoC-Final | 6,209 | Final/sdram/firmware/start.S | /*
* Copyright 2018, Serge Bazanski <serge@bazanski.pl>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted.
*/
#include "../extraops.S"
/*
* Interrupt vector.
*/
.global _start
_start:
.org 0x00000000 # Reset
j _crt0
.org 0x00000010 # IRQ
_irq_vector:
addi sp, sp, -16
sw t0, 4(sp)
sw ra, 8(sp)
/* By convention, q2 holds true IRQ vector, but remains caller-save.
We rely on the assumption that compiler-generated code will never touch
the QREGs. q3 is truly scratch/caller-save. */
picorv32_getq_insn(t0, q2)
sw t0, 12(sp)
jalr t0 // Call the true IRQ vector.
lw t0, 12(sp)
picorv32_setq_insn(q2, t0) // Restore the true IRQ vector.
lw ra, 8(sp)
lw t0, 4(sp)
addi sp, sp, 16
picorv32_retirq_insn() // return from interrupt
/*
* IRQ handler, branched to from the vector.
*/
_irq:
/* save x1/x2 to q1/q2 */
picorv32_setq_insn(q2, x1)
picorv32_setq_insn(q3, x2)
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* use x2 as scratch space for saving registers */
/* q0 (== x1), q2(== x2), q3 */
picorv32_getq_insn(x2, q0)
sw x2, 0*4(x1)
picorv32_getq_insn(x2, q2)
sw x2, 1*4(x1)
picorv32_getq_insn(x2, q3)
sw x2, 2*4(x1)
/* save x3 - x31 */
sw x3, 3*4(x1)
sw x4, 4*4(x1)
sw x5, 5*4(x1)
sw x6, 6*4(x1)
sw x7, 7*4(x1)
sw x8, 8*4(x1)
sw x9, 9*4(x1)
sw x10, 10*4(x1)
sw x11, 11*4(x1)
sw x12, 12*4(x1)
sw x13, 13*4(x1)
sw x14, 14*4(x1)
sw x15, 15*4(x1)
sw x16, 16*4(x1)
sw x17, 17*4(x1)
sw x18, 18*4(x1)
sw x19, 19*4(x1)
sw x20, 20*4(x1)
sw x21, 21*4(x1)
sw x22, 22*4(x1)
sw x23, 23*4(x1)
sw x24, 24*4(x1)
sw x25, 25*4(x1)
sw x26, 26*4(x1)
sw x27, 27*4(x1)
sw x28, 28*4(x1)
sw x29, 29*4(x1)
sw x30, 30*4(x1)
sw x31, 31*4(x1)
/* update _irq_pending to the currently pending interrupts */
picorv32_getq_insn(t0, q1)
la t1, (_irq_pending)
sw t0, 0(t1)
/* prepare C handler stack */
lui sp, %hi(_irq_stack)
addi sp, sp, %lo(_irq_stack)
/* call C handler */
jal ra, isr
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* restore q0 - q2 */
lw x2, 0*4(x1)
picorv32_setq_insn(q0, x2)
lw x2, 1*4(x1)
picorv32_setq_insn(q1, x2)
lw x2, 2*4(x1)
picorv32_setq_insn(q2, x2)
/* restore x3 - x31 */
lw x3, 3*4(x1)
lw x4, 4*4(x1)
lw x5, 5*4(x1)
lw x6, 6*4(x1)
lw x7, 7*4(x1)
lw x8, 8*4(x1)
lw x9, 9*4(x1)
lw x10, 10*4(x1)
lw x11, 11*4(x1)
lw x12, 12*4(x1)
lw x13, 13*4(x1)
lw x14, 14*4(x1)
lw x15, 15*4(x1)
lw x16, 16*4(x1)
lw x17, 17*4(x1)
lw x18, 18*4(x1)
lw x19, 19*4(x1)
lw x20, 20*4(x1)
lw x21, 21*4(x1)
lw x22, 22*4(x1)
lw x23, 23*4(x1)
lw x24, 24*4(x1)
lw x25, 25*4(x1)
lw x26, 26*4(x1)
lw x27, 27*4(x1)
lw x28, 28*4(x1)
lw x29, 29*4(x1)
lw x30, 30*4(x1)
lw x31, 31*4(x1)
/* restore x1 - x2 from q registers */
picorv32_getq_insn(x1, q1)
picorv32_getq_insn(x2, q2)
ret
/*
* Reset handler, branched to from the vector.
*/
_crt0:
/* zero-initialize all registers */
addi x1, zero, 0
addi x2, zero, 0
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
/* mask all interrupts */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* reflect that in _irq_mask */
la t1, _irq_mask
sw t0, 0(t1)
/* Load DATA */
la t0, _fdata_rom
la t1, _fdata
la t2, _edata
3:
lw t3, 0(t0)
sw t3, 0(t1)
/* _edata is aligned to 16 bytes. Use word-xfers. */
addi t0, t0, 4
addi t1, t1, 4
bltu t1, t2, 3b
/* Clear BSS */
#la t0, _fbss
#la t1, _ebss
2:
#sw zero, 0(t0)
#addi t0, t0, 4
#bltu t0, t1, 2b
/* set main stack */
la sp, _fstack
/* Set up address to IRQ handler since vector is hardcoded.
By convention, q2 keeps the pointer to the true IRQ handler,
to emulate relocatable interrupts. */
la t0, _irq
picorv32_setq_insn(q2, t0)
/* jump to main */
jal ra, main
1:
/* loop forever */
j 1b
/*
* Enable interrupts by copying the software mask to the hardware mask
*/
.global _irq_enable
_irq_enable:
/* Set _irq_enabled to true */
la t0, _irq_enabled
addi t1, zero, 1
sw t1, 0(t0)
/* Set the HW IRQ mask to _irq_mask */
la t0, _irq_mask
lw t0, 0(t0)
picorv32_maskirq_insn(zero, t0)
ret
/*
* Disable interrupts by masking all interrupts (the mask should already be
* up to date)
*/
.global _irq_disable
_irq_disable:
/* Mask all IRQs */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* Set _irq_enabled to false */
la t0, _irq_enabled
sw zero, (t0)
ret
/*
* Set interrrupt mask.
* This updates the software mask (for readback and interrupt inable/disable)
* and the hardware mask.
* 1 means interrupt is masked (disabled).
*/
.global _irq_setmask
_irq_setmask:
/* Update _irq_mask */
la t0, _irq_mask
sw a0, (t0)
/* Are interrupts enabled? */
la t0, _irq_enabled
lw t0, 0(t0)
beq t0, zero, 1f
/* If so, update the HW IRQ mask */
picorv32_maskirq_insn(zero, a0)
1:
ret
.section .bss
irq_regs:
/* saved interrupt registers, x0 - x31 */
.fill 32,4
/* interrupt stack */
.fill 256,4
_irq_stack:
/*
* Bitfield of pending interrupts, updated on ISR entry.
*/
.global _irq_pending
_irq_pending:
.word 0
/*
* Software copy of enabled interrupts. Do not write directly, use
* _irq_set_mask instead.
*/
.global _irq_mask
_irq_mask:
.word 0
/*
* Software state of global interrupts being enabled or disabled. Do not write
* directly, use _irq_disable / _irq_enable instead.
*/
.global _irq_enabled
_irq_enabled:
.word 0
|
fff1214/SoC-Final | 4,495 | Final/sdram/testbench/counter_la_qs/counter_la_qs.elf-isr.s | .file "isr.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs" "../../firmware/isr.c"
.align 2
.globl isr
.type isr, @function
isr:
.LFB321:
.file 1 "../../firmware/isr.c"
.loc 1 24 1
.cfi_startproc
.loc 1 28 5
.LVL0:
.LBB4:
.LBB5:
.file 2 "../../firmware/irq_vex.h"
.loc 2 31 2
li a5,0
#APP
# 31 "../../firmware/irq_vex.h" 1
csrw 3008, a5
# 0 "" 2
.LVL1:
#NO_APP
.LBE5:
.LBE4:
.loc 1 43 5
.loc 1 45 1 is_stmt 0
ret
.cfi_endproc
.LFE321:
.size isr, .-isr
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0xb0
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x2
.4byte .LASF11
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0x3
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0x4
.string "isr"
.byte 0x1
.byte 0x17
.byte 0x6
.4byte .LFB321
.4byte .LFE321-.LFB321
.byte 0x1
.byte 0x9c
.4byte 0x9d
.byte 0x5
.4byte 0x9d
.4byte .LBB4
.4byte .LBE4-.LBB4
.byte 0x1
.byte 0x1c
.byte 0x5
.byte 0x6
.4byte 0xa6
.4byte .LLST0
.byte 0
.byte 0
.byte 0x7
.4byte .LASF12
.byte 0x2
.byte 0x1d
.byte 0x14
.byte 0x3
.byte 0x8
.4byte .LASF13
.byte 0x2
.byte 0x1d
.byte 0x2d
.4byte 0x65
.byte 0
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x3
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0x4
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x5
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x58
.byte 0xb
.byte 0x59
.byte 0xb
.byte 0x57
.byte 0xb
.byte 0
.byte 0
.byte 0x6
.byte 0x5
.byte 0
.byte 0x31
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x7
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0
.byte 0
.byte 0x8
.byte 0x5
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",@progbits
.4byte .Ldebug_loc3-.Ldebug_loc2
.Ldebug_loc2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.Ldebug_loc0:
.LLST0:
.byte 0x7
.4byte .LVL0
.4byte .LVL1
.byte 0x2
.byte 0x30
.byte 0x9f
.byte 0
.Ldebug_loc3:
.section .debug_aranges,"",@progbits
.4byte 0x1c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte 0
.4byte 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF5:
.string "long long int"
.LASF10:
.string "unsigned int"
.LASF11:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -Os -ffreestanding"
.LASF8:
.string "long unsigned int"
.LASF9:
.string "long long unsigned int"
.LASF12:
.string "irq_setmask"
.LASF13:
.string "mask"
.LASF6:
.string "unsigned char"
.LASF4:
.string "long int"
.LASF7:
.string "short unsigned int"
.LASF2:
.string "signed char"
.LASF3:
.string "short int"
.section .debug_line_str,"MS",@progbits,1
.LASF0:
.string "../../firmware/isr.c"
.LASF1:
.string "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 13,503 | Final/sdram/testbench/counter_la_qs/counter_la_qs.elf-counter_la_qs.s | .file "counter_la_qs.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs" "counter_la_qs.c"
.align 2
.globl putchar
.type putchar, @function
putchar:
.LFB316:
.file 1 "../../firmware/stub.c"
.loc 1 19 1
.cfi_startproc
.LVL0:
.loc 1 20 2
.loc 1 19 1 is_stmt 0
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,8(sp)
sw ra,12(sp)
.cfi_offset 8, -8
.cfi_offset 1, -4
.loc 1 20 5
li a5,10
.loc 1 19 1
mv s0,a0
.loc 1 20 5
bne a0,a5,.L2
.loc 1 21 3 is_stmt 1
li a0,13
.LVL1:
call putchar
.LVL2:
.L2:
.loc 1 22 13 is_stmt 0 discriminator 1
li a5,-268410880
.loc 1 22 60 discriminator 1
li a4,1
.L3:
.loc 1 22 60 is_stmt 1 discriminator 1
.loc 1 22 13 is_stmt 0 discriminator 1
lw a3,-2044(a5)
.loc 1 22 60 discriminator 1
beq a3,a4,.L3
.loc 1 23 2 is_stmt 1
.loc 1 24 1 is_stmt 0
lw ra,12(sp)
.cfi_restore 1
.loc 1 23 50
sw s0,-2048(a5)
.loc 1 24 1
lw s0,8(sp)
.cfi_restore 8
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE316:
.size putchar, .-putchar
.align 2
.globl print
.type print, @function
print:
.LFB317:
.loc 1 27 1 is_stmt 1
.cfi_startproc
.LVL3:
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,8(sp)
sw ra,12(sp)
.cfi_offset 8, -8
.cfi_offset 1, -4
mv s0,a0
.loc 1 28 2
.LVL4:
.L7:
.loc 1 28 9
lbu a0,0(s0)
bne a0,zero,.L8
.loc 1 30 1 is_stmt 0
lw ra,12(sp)
.cfi_remember_state
.cfi_restore 1
lw s0,8(sp)
.cfi_restore 8
.LVL5:
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.LVL6:
.L8:
.cfi_restore_state
.loc 1 29 3 is_stmt 1
.loc 1 29 14 is_stmt 0
addi s0,s0,1
.LVL7:
.loc 1 29 3
call putchar
.LVL8:
j .L7
.cfi_endproc
.LFE317:
.size print, .-print
.section .text.startup,"ax",@progbits
.align 2
.globl main
.type main, @function
main:
.LFB318:
.file 2 "counter_la_qs.c"
.loc 2 35 1 is_stmt 1
.cfi_startproc
.loc 2 36 2
.loc 2 63 9
.loc 2 35 1 is_stmt 0
addi sp,sp,-16
.cfi_def_cfa_offset 16
.loc 2 63 43
li a4,8192
li a5,637534208
.loc 2 35 1
sw s0,8(sp)
sw ra,12(sp)
.cfi_offset 8, -8
.cfi_offset 1, -4
.loc 2 63 43
addi a3,a4,-2039
sw a3,160(a5)
.loc 2 64 9 is_stmt 1
.loc 2 64 43 is_stmt 0
sw a3,156(a5)
.loc 2 65 9 is_stmt 1
.loc 2 65 43 is_stmt 0
sw a3,152(a5)
.loc 2 66 9 is_stmt 1
.loc 2 66 43 is_stmt 0
sw a3,148(a5)
.loc 2 67 9 is_stmt 1
.loc 2 67 43 is_stmt 0
sw a3,144(a5)
.loc 2 68 9 is_stmt 1
.loc 2 68 43 is_stmt 0
sw a3,140(a5)
.loc 2 69 9 is_stmt 1
.loc 2 69 43 is_stmt 0
sw a3,136(a5)
.loc 2 70 9 is_stmt 1
.loc 2 70 43 is_stmt 0
sw a3,132(a5)
.loc 2 71 9 is_stmt 1
.loc 2 71 43 is_stmt 0
sw a3,128(a5)
.loc 2 72 9 is_stmt 1
.loc 2 72 43 is_stmt 0
sw a3,124(a5)
.loc 2 73 9 is_stmt 1
.loc 2 73 43 is_stmt 0
sw a3,120(a5)
.loc 2 74 9 is_stmt 1
.loc 2 74 43 is_stmt 0
sw a3,116(a5)
.loc 2 75 9 is_stmt 1
.loc 2 75 43 is_stmt 0
sw a3,112(a5)
.loc 2 76 9 is_stmt 1
.loc 2 76 43 is_stmt 0
sw a3,108(a5)
.loc 2 77 9 is_stmt 1
.loc 2 77 43 is_stmt 0
sw a3,104(a5)
.loc 2 78 9 is_stmt 1
.loc 2 78 43 is_stmt 0
sw a3,100(a5)
.loc 2 80 9 is_stmt 1
.loc 2 80 43 is_stmt 0
addi a4,a4,-2040
sw a4,96(a5)
.loc 2 81 9 is_stmt 1
.loc 2 81 43 is_stmt 0
sw a4,92(a5)
.loc 2 82 9 is_stmt 1
.loc 2 82 43 is_stmt 0
sw a4,88(a5)
.loc 2 83 9 is_stmt 1
.loc 2 83 43 is_stmt 0
sw a4,84(a5)
.loc 2 84 9 is_stmt 1
.loc 2 84 43 is_stmt 0
sw a4,80(a5)
.loc 2 85 9 is_stmt 1
.loc 2 85 43 is_stmt 0
sw a4,76(a5)
.loc 2 86 9 is_stmt 1
.loc 2 86 43 is_stmt 0
sw a4,72(a5)
.loc 2 87 9 is_stmt 1
.loc 2 87 43 is_stmt 0
sw a4,68(a5)
.loc 2 88 9 is_stmt 1
.loc 2 88 43 is_stmt 0
sw a4,64(a5)
.loc 2 89 9 is_stmt 1
.loc 2 89 43 is_stmt 0
sw a4,56(a5)
.loc 2 90 9 is_stmt 1
.loc 2 90 43 is_stmt 0
sw a4,52(a5)
.loc 2 91 9 is_stmt 1
.loc 2 91 43 is_stmt 0
sw a4,48(a5)
.loc 2 92 9 is_stmt 1
.loc 2 92 43 is_stmt 0
sw a4,44(a5)
.loc 2 93 9 is_stmt 1
.loc 2 93 43 is_stmt 0
sw a4,40(a5)
.loc 2 94 9 is_stmt 1
.loc 2 94 43 is_stmt 0
sw a4,36(a5)
.loc 2 96 9 is_stmt 1
.loc 2 96 43 is_stmt 0
sw a3,60(a5)
.loc 2 100 2 is_stmt 1
.loc 2 100 50 is_stmt 0
li a4,1
li a3,-268410880
sw a4,0(a3)
.loc 2 103 2 is_stmt 1
.loc 2 103 36 is_stmt 0
sw a4,0(a5)
.loc 2 104 2 is_stmt 1
.loc 2 104 10 is_stmt 0
li s0,637534208
.loc 2 104 43
li a5,1
.L11:
.loc 2 104 43 is_stmt 1 discriminator 1
.loc 2 104 10 is_stmt 0 discriminator 1
lw a4,0(s0)
.loc 2 104 43 discriminator 1
beq a4,a5,.L11
.loc 2 108 2 is_stmt 1
.loc 2 108 114 is_stmt 0
li a5,-268423168
sw zero,12(a5)
.loc 2 108 57
sw zero,28(a5)
.loc 2 109 2 is_stmt 1
.loc 2 109 112 is_stmt 0
li a4,-1
sw a4,8(a5)
.loc 2 109 56
sw a4,24(a5)
.loc 2 110 2 is_stmt 1
.loc 2 110 112 is_stmt 0
sw zero,4(a5)
.loc 2 110 56
sw zero,20(a5)
.loc 2 111 2 is_stmt 1
.loc 2 111 100 is_stmt 0
sw zero,0(a5)
.loc 2 111 50
sw zero,16(a5)
.loc 2 114 2 is_stmt 1
.loc 2 114 36 is_stmt 0
li a4,-1421869056
sw a4,12(s0)
.loc 2 117 2 is_stmt 1
.loc 2 117 56 is_stmt 0
sw zero,56(a5)
.loc 2 120 2 is_stmt 1
.loc 2 120 112 is_stmt 0
sw zero,8(a5)
.loc 2 120 56
sw zero,24(a5)
.loc 2 130 2 is_stmt 1
.loc 2 130 13 is_stmt 0
call qsort
.LVL9:
.loc 2 131 2 is_stmt 1
.loc 2 131 43 is_stmt 0
lw a5,0(a0)
.loc 2 132 47
lw a4,4(a0)
.loc 2 146 1
lw ra,12(sp)
.cfi_restore 1
.loc 2 131 43
slli a5,a5,16
.loc 2 131 36
sw a5,12(s0)
.loc 2 132 2 is_stmt 1
.loc 2 132 47 is_stmt 0
slli a4,a4,16
.loc 2 132 36
sw a4,12(s0)
.loc 2 133 2 is_stmt 1
.loc 2 133 47 is_stmt 0
lw a4,8(a0)
slli a4,a4,16
.loc 2 133 36
sw a4,12(s0)
.loc 2 134 2 is_stmt 1
.loc 2 134 47 is_stmt 0
lw a4,12(a0)
slli a4,a4,16
.loc 2 134 36
sw a4,12(s0)
.loc 2 135 2 is_stmt 1
.loc 2 135 47 is_stmt 0
lw a4,16(a0)
slli a4,a4,16
.loc 2 135 36
sw a4,12(s0)
.loc 2 136 2 is_stmt 1
.loc 2 136 47 is_stmt 0
lw a4,20(a0)
slli a4,a4,16
.loc 2 136 36
sw a4,12(s0)
.loc 2 137 2 is_stmt 1
.loc 2 137 47 is_stmt 0
lw a4,24(a0)
slli a4,a4,16
.loc 2 137 36
sw a4,12(s0)
.loc 2 138 2 is_stmt 1
.loc 2 138 47 is_stmt 0
lw a4,28(a0)
slli a4,a4,16
.loc 2 138 36
sw a4,12(s0)
.loc 2 139 2 is_stmt 1
.loc 2 139 47 is_stmt 0
lw a4,32(a0)
slli a4,a4,16
.loc 2 139 36
sw a4,12(s0)
.loc 2 140 2 is_stmt 1
.loc 2 140 47 is_stmt 0
lw a4,36(a0)
slli a4,a4,16
.loc 2 140 36
sw a4,12(s0)
.loc 2 144 2 is_stmt 1
.loc 2 144 36 is_stmt 0
li a4,-1420754944
sw a4,12(s0)
.loc 2 145 2 is_stmt 1
.loc 2 145 36 is_stmt 0
sw a5,12(s0)
.loc 2 146 1
lw s0,8(sp)
.cfi_restore 8
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE318:
.size main, .-main
.text
.Letext0:
.file 3 "/opt/riscv/lib/gcc/riscv32-unknown-elf/12.1.0/include/stdint-gcc.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0x131
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x5
.4byte .LASF14
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .LLRL2
.4byte 0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0x6
.4byte .LASF15
.byte 0x3
.byte 0x34
.byte 0x1b
.4byte 0x5c
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0x7
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0x8
.4byte .LASF16
.byte 0x2
.byte 0x16
.byte 0xd
.4byte 0x8a
.4byte 0x8a
.byte 0x9
.byte 0
.byte 0x2
.4byte 0x6a
.byte 0xa
.4byte .LASF12
.byte 0x2
.byte 0x22
.byte 0x6
.4byte .LFB318
.4byte .LFE318-.LFB318
.byte 0x1
.byte 0x9c
.4byte 0xc7
.byte 0xb
.string "j"
.byte 0x2
.byte 0x24
.byte 0x6
.4byte 0x6a
.byte 0xc
.string "tmp"
.byte 0x2
.byte 0x82
.byte 0x7
.4byte 0x8a
.byte 0x1
.byte 0x5a
.byte 0x3
.4byte .LVL9
.4byte 0x78
.byte 0
.byte 0xd
.4byte .LASF17
.byte 0x1
.byte 0x1a
.byte 0x6
.4byte .LFB317
.4byte .LFE317-.LFB317
.byte 0x1
.byte 0x9c
.4byte 0xf4
.byte 0x4
.string "p"
.byte 0x1a
.byte 0x18
.4byte 0xf4
.4byte .LLST1
.byte 0x3
.4byte .LVL8
.4byte 0x105
.byte 0
.byte 0x2
.4byte 0x100
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF11
.byte 0xe
.4byte 0xf9
.byte 0xf
.4byte .LASF13
.byte 0x1
.byte 0x12
.byte 0x6
.4byte .LFB316
.4byte .LFE316-.LFB316
.byte 0x1
.byte 0x9c
.byte 0x4
.string "c"
.byte 0x12
.byte 0x13
.4byte 0xf9
.4byte .LLST0
.byte 0x10
.4byte .LVL2
.4byte 0x105
.byte 0x11
.byte 0x1
.byte 0x5a
.byte 0x1
.byte 0x3d
.byte 0
.byte 0
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0xf
.byte 0
.byte 0xb
.byte 0x21
.byte 0x4
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x3
.byte 0x48
.byte 0
.byte 0x7d
.byte 0x1
.byte 0x7f
.byte 0x13
.byte 0
.byte 0
.byte 0x4
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x5
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x55
.byte 0x17
.byte 0x11
.byte 0x1
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x6
.byte 0x16
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x7
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0x8
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x3c
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x9
.byte 0x18
.byte 0
.byte 0
.byte 0
.byte 0xa
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xb
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xc
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0xd
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xe
.byte 0x26
.byte 0
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xf
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0
.byte 0
.byte 0x10
.byte 0x48
.byte 0x1
.byte 0x7d
.byte 0x1
.byte 0x7f
.byte 0x13
.byte 0
.byte 0
.byte 0x11
.byte 0x49
.byte 0
.byte 0x2
.byte 0x18
.byte 0x7e
.byte 0x18
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",@progbits
.4byte .Ldebug_loc3-.Ldebug_loc2
.Ldebug_loc2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.Ldebug_loc0:
.LLST1:
.byte 0x7
.4byte .LVL3
.4byte .LVL4
.byte 0x1
.byte 0x5a
.byte 0x7
.4byte .LVL4
.4byte .LVL5
.byte 0x1
.byte 0x58
.byte 0x7
.4byte .LVL6
.4byte .LFE317
.byte 0x1
.byte 0x58
.byte 0
.LLST0:
.byte 0x7
.4byte .LVL0
.4byte .LVL1
.byte 0x1
.byte 0x5a
.byte 0x7
.4byte .LVL1
.4byte .LFE316
.byte 0x4
.byte 0xa3
.byte 0x1
.byte 0x5a
.byte 0x9f
.byte 0
.Ldebug_loc3:
.section .debug_aranges,"",@progbits
.4byte 0x24
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte .LFB318
.4byte .LFE318-.LFB318
.4byte 0
.4byte 0
.section .debug_rnglists,"",@progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2
.Ldebug_ranges2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.LLRL2:
.byte 0x6
.4byte .Ltext0
.4byte .Letext0
.byte 0x6
.4byte .LFB318
.4byte .LFE318
.byte 0
.Ldebug_ranges3:
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF16:
.string "qsort"
.LASF6:
.string "unsigned char"
.LASF8:
.string "long unsigned int"
.LASF7:
.string "short unsigned int"
.LASF13:
.string "putchar"
.LASF12:
.string "main"
.LASF10:
.string "unsigned int"
.LASF14:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -Os -ffreestanding"
.LASF9:
.string "long long unsigned int"
.LASF5:
.string "long long int"
.LASF11:
.string "char"
.LASF17:
.string "print"
.LASF3:
.string "short int"
.LASF15:
.string "uint32_t"
.LASF4:
.string "long int"
.LASF2:
.string "signed char"
.section .debug_line_str,"MS",@progbits,1
.LASF0:
.string "counter_la_qs.c"
.LASF1:
.string "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 1,604 | Final/sdram/testbench/counter_la_qs/counter_la_qs.elf-crt0_vex.s | # 0 "../../firmware/crt0_vex.S"
# 1 "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs//"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "../../firmware/crt0_vex.S"
.global main
.global isr
.global _start
_start:
j crt_init
nop
nop
nop
nop
nop
nop
nop
.global trap_entry
trap_entry:
sw x1, - 1*4(sp)
sw x5, - 2*4(sp)
sw x6, - 3*4(sp)
sw x7, - 4*4(sp)
sw x10, - 5*4(sp)
sw x11, - 6*4(sp)
sw x12, - 7*4(sp)
sw x13, - 8*4(sp)
sw x14, - 9*4(sp)
sw x15, -10*4(sp)
sw x16, -11*4(sp)
sw x17, -12*4(sp)
sw x28, -13*4(sp)
sw x29, -14*4(sp)
sw x30, -15*4(sp)
sw x31, -16*4(sp)
addi sp,sp,-16*4
call isr
lw x1 , 15*4(sp)
lw x5, 14*4(sp)
lw x6, 13*4(sp)
lw x7, 12*4(sp)
lw x10, 11*4(sp)
lw x11, 10*4(sp)
lw x12, 9*4(sp)
lw x13, 8*4(sp)
lw x14, 7*4(sp)
lw x15, 6*4(sp)
lw x16, 5*4(sp)
lw x17, 4*4(sp)
lw x28, 3*4(sp)
lw x29, 2*4(sp)
lw x30, 1*4(sp)
lw x31, 0*4(sp)
addi sp,sp,16*4
mret
.text
crt_init:
la sp, _fstack
la a0, trap_entry
csrw mtvec, a0
sram_init:
la a0, _fsram
la a1, _esram
la a2, _esram_rom
sram_loop:
beq a0,a1,sram_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j sram_loop
sram_done:
data_init:
la a0, _fdata
la a1, _edata
la a2, _fdata_rom
data_loop:
beq a0,a1,data_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j data_loop
data_done:
bss_init:
la a0, _fbss
la a1, _ebss
bss_loop:
beq a0,a1,bss_done
sw zero,0(a0)
add a0,a0,4
j bss_loop
bss_done:
li a0, 0x880
csrw mie,a0
call main
infinit_loop:
j infinit_loop
|
fff1214/SoC-Final | 11,637 | Final/sdram/testbench/counter_la_qs/counter_la_qs.elf-qsort.s | .file "qsort.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs" "qsort.c"
.section .mprjram,"ax",@progbits
.align 2
.globl partition
.type partition, @function
partition:
.LFB0:
.file 1 "qsort.c"
.loc 1 3 75
.cfi_startproc
.LVL0:
.loc 1 4 2
.loc 1 4 6 is_stmt 0
lui a5,%hi(.LANCHOR0)
addi a3,a5,%lo(.LANCHOR0)
slli a7,a1,2
add a2,a3,a7
lw t4,0(a2)
.LVL1:
.loc 1 5 2 is_stmt 1
slli a2,a0,2
.loc 1 3 75 is_stmt 0
mv a4,a0
.loc 1 5 6
addi t1,a0,-1
.LVL2:
.loc 1 6 2 is_stmt 1
.loc 1 7 2
add a3,a3,a2
addi a5,a5,%lo(.LANCHOR0)
.LVL3:
.L2:
.loc 1 7 15 discriminator 1
.loc 1 9 6 is_stmt 0 discriminator 1
addi a0,t1,1
.loc 1 10 9 discriminator 1
slli a2,a0,2
add a2,a5,a2
lw a6,0(a2)
.loc 1 7 15 discriminator 1
blt a4,a1,.L4
.loc 1 15 2 is_stmt 1
.loc 1 15 6 is_stmt 0
add a5,a5,a7
lw a4,0(a5)
.LVL4:
.loc 1 15 4
bge a4,a6,.L1
.loc 1 16 3 is_stmt 1
.LVL5:
.loc 1 17 3
.loc 1 17 10 is_stmt 0
sw a4,0(a2)
.LVL6:
.loc 1 18 3 is_stmt 1
.loc 1 18 9 is_stmt 0
sw a6,0(a5)
.loc 1 20 2 is_stmt 1
.LVL7:
.L1:
.loc 1 21 1 is_stmt 0
ret
.LVL8:
.L4:
.loc 1 8 3 is_stmt 1
.loc 1 8 7 is_stmt 0
lw t3,0(a3)
.loc 1 8 5
bge t3,t4,.L3
.loc 1 9 4 is_stmt 1
.LVL9:
.loc 1 10 4
.loc 1 11 4
.loc 1 11 9 is_stmt 0
sw t3,0(a2)
.LVL10:
.loc 1 12 4 is_stmt 1
.loc 1 12 9 is_stmt 0
sw a6,0(a3)
.LVL11:
.loc 1 9 6
mv t1,a0
.LVL12:
.L3:
.loc 1 7 20 is_stmt 1 discriminator 2
addi a4,a4,1
.LVL13:
addi a3,a3,4
j .L2
.cfi_endproc
.LFE0:
.size partition, .-partition
.align 2
.globl sort
.type sort, @function
sort:
.LFB1:
.loc 1 23 72
.cfi_startproc
.LVL14:
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,8(sp)
sw s2,0(sp)
sw ra,12(sp)
sw s1,4(sp)
.cfi_offset 8, -8
.cfi_offset 18, -16
.cfi_offset 1, -4
.cfi_offset 9, -12
mv s0,a0
mv s2,a1
.LVL15:
.L8:
.loc 1 24 2
.loc 1 24 4 is_stmt 0
bge s0,s2,.L6
.LBB2:
.loc 1 25 3 is_stmt 1
.loc 1 25 11 is_stmt 0
mv a1,s2
mv a0,s0
call partition
.LVL16:
mv s1,a0
.LVL17:
.loc 1 26 3 is_stmt 1
addi a1,a0,-1
mv a0,s0
call sort
.LVL18:
.loc 1 27 3
addi s0,s1,1
j .L8
.LVL19:
.L6:
.LBE2:
.loc 1 29 1 is_stmt 0
lw ra,12(sp)
.cfi_restore 1
lw s0,8(sp)
.cfi_restore 8
lw s1,4(sp)
.cfi_restore 9
lw s2,0(sp)
.cfi_restore 18
.LVL20:
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE1:
.size sort, .-sort
.align 2
.globl qsort
.type qsort, @function
qsort:
.LFB2:
.loc 1 31 58 is_stmt 1
.cfi_startproc
.loc 1 32 2
.loc 1 31 58 is_stmt 0
addi sp,sp,-16
.cfi_def_cfa_offset 16
.loc 1 32 2
li a0,0
li a1,9
.loc 1 31 58
sw ra,12(sp)
.cfi_offset 1, -4
.loc 1 32 2
call sort
.LVL21:
.loc 1 33 2 is_stmt 1
.loc 1 34 1 is_stmt 0
lw ra,12(sp)
.cfi_restore 1
.loc 1 33 9
lui a0,%hi(.LANCHOR0)
.loc 1 34 1
addi a0,a0,%lo(.LANCHOR0)
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE2:
.size qsort, .-qsort
.globl A
.data
.align 2
.set .LANCHOR0,. + 0
.type A, @object
.size A, 40
A:
.word 893
.word 40
.word 3233
.word 4267
.word 2669
.word 2541
.word 9073
.word 6023
.word 5681
.word 4622
.text
.Letext0:
.file 2 "qsort.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0x16c
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x5
.4byte .LASF8
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .LLRL7
.4byte 0
.4byte .Ldebug_line0
.byte 0x6
.4byte 0x3d
.4byte 0x36
.byte 0x7
.4byte 0x36
.byte 0x9
.byte 0
.byte 0x8
.byte 0x4
.byte 0x7
.4byte .LASF2
.byte 0x9
.byte 0x4
.byte 0x5
.string "int"
.byte 0xa
.string "A"
.byte 0x2
.byte 0x5
.byte 0x5
.4byte 0x26
.byte 0x5
.byte 0x3
.4byte A
.byte 0xb
.4byte .LASF3
.byte 0x1
.byte 0x1f
.byte 0x33
.4byte 0x83
.4byte .LFB2
.4byte .LFE2-.LFB2
.byte 0x1
.byte 0x9c
.4byte 0x83
.byte 0x4
.4byte .LVL21
.4byte 0x89
.byte 0x1
.byte 0x1
.byte 0x5a
.byte 0x1
.byte 0x30
.byte 0x1
.byte 0x1
.byte 0x5b
.byte 0x1
.byte 0x39
.byte 0
.byte 0
.byte 0xc
.byte 0x4
.4byte 0x3d
.byte 0xd
.4byte .LASF4
.byte 0x1
.byte 0x17
.byte 0x33
.4byte .LFB1
.4byte .LFE1-.LFB1
.byte 0x1
.byte 0x9c
.4byte 0x104
.byte 0x2
.string "low"
.byte 0x17
.byte 0x3c
.4byte 0x3d
.4byte .LLST4
.byte 0x2
.string "hi"
.byte 0x17
.byte 0x45
.4byte 0x3d
.4byte .LLST5
.byte 0xe
.4byte .LBB2
.4byte .LBE2-.LBB2
.byte 0x3
.string "p"
.byte 0x19
.byte 0x7
.4byte 0x3d
.4byte .LLST6
.byte 0xf
.4byte .LVL16
.4byte 0x104
.4byte 0xec
.byte 0x1
.byte 0x1
.byte 0x5a
.byte 0x2
.byte 0x78
.byte 0
.byte 0x1
.byte 0x1
.byte 0x5b
.byte 0x2
.byte 0x82
.byte 0
.byte 0
.byte 0x4
.4byte .LVL18
.4byte 0x89
.byte 0x1
.byte 0x1
.byte 0x5a
.byte 0x2
.byte 0x78
.byte 0
.byte 0x1
.byte 0x1
.byte 0x5b
.byte 0x2
.byte 0x79
.byte 0x7f
.byte 0
.byte 0
.byte 0
.byte 0x10
.4byte .LASF5
.byte 0x1
.byte 0x3
.byte 0x32
.4byte 0x3d
.4byte .LFB0
.4byte .LFE0-.LFB0
.byte 0x1
.byte 0x9c
.byte 0x2
.string "low"
.byte 0x3
.byte 0x40
.4byte 0x3d
.4byte .LLST0
.byte 0x11
.string "hi"
.byte 0x1
.byte 0x3
.byte 0x48
.4byte 0x3d
.byte 0x1
.byte 0x5b
.byte 0x12
.4byte .LASF6
.byte 0x1
.byte 0x4
.byte 0x6
.4byte 0x3d
.byte 0x1
.byte 0x6d
.byte 0x3
.string "i"
.byte 0x5
.byte 0x6
.4byte 0x3d
.4byte .LLST1
.byte 0x3
.string "j"
.byte 0x5
.byte 0x10
.4byte 0x3d
.4byte .LLST2
.byte 0x13
.4byte .LASF7
.byte 0x1
.byte 0x6
.byte 0x6
.4byte 0x3d
.4byte .LLST3
.byte 0
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x49
.byte 0
.byte 0x2
.byte 0x18
.byte 0x7e
.byte 0x18
.byte 0
.byte 0
.byte 0x2
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x3
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x4
.byte 0x48
.byte 0x1
.byte 0x7d
.byte 0x1
.byte 0x7f
.byte 0x13
.byte 0
.byte 0
.byte 0x5
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x55
.byte 0x17
.byte 0x11
.byte 0x1
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x6
.byte 0x1
.byte 0x1
.byte 0x49
.byte 0x13
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x7
.byte 0x21
.byte 0
.byte 0x49
.byte 0x13
.byte 0x2f
.byte 0xb
.byte 0
.byte 0
.byte 0x8
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x9
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0xa
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x3f
.byte 0x19
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0xb
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xc
.byte 0xf
.byte 0
.byte 0xb
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xd
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xe
.byte 0xb
.byte 0x1
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0
.byte 0
.byte 0xf
.byte 0x48
.byte 0x1
.byte 0x7d
.byte 0x1
.byte 0x7f
.byte 0x13
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x10
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x49
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0
.byte 0
.byte 0x11
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x12
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x13
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",@progbits
.4byte .Ldebug_loc3-.Ldebug_loc2
.Ldebug_loc2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.Ldebug_loc0:
.LLST4:
.byte 0x7
.4byte .LVL14
.4byte .LVL15
.byte 0x1
.byte 0x5a
.byte 0x7
.4byte .LVL15
.4byte .LFE1
.byte 0x4
.byte 0xa3
.byte 0x1
.byte 0x5a
.byte 0x9f
.byte 0
.LLST5:
.byte 0x7
.4byte .LVL14
.4byte .LVL15
.byte 0x1
.byte 0x5b
.byte 0x7
.4byte .LVL15
.4byte .LVL20
.byte 0x1
.byte 0x62
.byte 0x7
.4byte .LVL20
.4byte .LFE1
.byte 0x4
.byte 0xa3
.byte 0x1
.byte 0x5b
.byte 0x9f
.byte 0
.LLST6:
.byte 0x7
.4byte .LVL17
.4byte .LVL19
.byte 0x1
.byte 0x59
.byte 0
.LLST0:
.byte 0x7
.4byte .LVL0
.4byte .LVL3
.byte 0x1
.byte 0x5a
.byte 0x7
.4byte .LVL3
.4byte .LFE0
.byte 0x4
.byte 0xa3
.byte 0x1
.byte 0x5a
.byte 0x9f
.byte 0
.LLST1:
.byte 0x7
.4byte .LVL2
.4byte .LVL9
.byte 0x1
.byte 0x56
.byte 0x7
.4byte .LVL9
.4byte .LVL11
.byte 0x3
.byte 0x76
.byte 0x1
.byte 0x9f
.byte 0x7
.4byte .LVL11
.4byte .LVL12
.byte 0x3
.byte 0x7a
.byte 0x1
.byte 0x9f
.byte 0x7
.4byte .LVL12
.4byte .LFE0
.byte 0x1
.byte 0x56
.byte 0
.LLST2:
.byte 0x7
.4byte .LVL2
.4byte .LVL3
.byte 0x1
.byte 0x5a
.byte 0x7
.4byte .LVL3
.4byte .LVL4
.byte 0x1
.byte 0x5e
.byte 0x7
.4byte .LVL8
.4byte .LFE0
.byte 0x1
.byte 0x5e
.byte 0
.LLST3:
.byte 0x7
.4byte .LVL5
.4byte .LVL6
.byte 0xa
.byte 0x76
.byte 0x1
.byte 0x32
.byte 0x24
.byte 0x3
.4byte A
.byte 0x22
.byte 0x7
.4byte .LVL9
.4byte .LVL10
.byte 0xa
.byte 0x76
.byte 0x1
.byte 0x32
.byte 0x24
.byte 0x3
.4byte A
.byte 0x22
.byte 0
.Ldebug_loc3:
.section .debug_aranges,"",@progbits
.4byte 0x2c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .LFB0
.4byte .LFE0-.LFB0
.4byte .LFB1
.4byte .LFE1-.LFB1
.4byte .LFB2
.4byte .LFE2-.LFB2
.4byte 0
.4byte 0
.section .debug_rnglists,"",@progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2
.Ldebug_ranges2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.LLRL7:
.byte 0x6
.4byte .LFB0
.4byte .LFE0
.byte 0x6
.4byte .LFB1
.4byte .LFE1
.byte 0x6
.4byte .LFB2
.4byte .LFE2
.byte 0
.Ldebug_ranges3:
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF2:
.string "unsigned int"
.LASF8:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -Os -ffreestanding"
.LASF6:
.string "pivot"
.LASF3:
.string "qsort"
.LASF7:
.string "temp"
.LASF5:
.string "partition"
.LASF4:
.string "sort"
.section .debug_line_str,"MS",@progbits,1
.LASF0:
.string "qsort.c"
.LASF1:
.string "/home/ubuntu/Desktop/Final_test-main/testbench/counter_la_qs"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 5,979 | Final/sdram/testbench/counter_la_mm/counter_la_mm.elf-isr.s | .file "isr.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm" "../../firmware/isr.c"
.align 2
.type flush_cpu_icache, @function
flush_cpu_icache:
.LFB21:
.file 1 "../../firmware/system.h"
.loc 1 15 1
.cfi_startproc
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,12(sp)
.cfi_offset 8, -4
addi s0,sp,16
.cfi_def_cfa 8, 0
.loc 1 26 1
nop
lw s0,12(sp)
.cfi_restore 8
.cfi_def_cfa 2, 16
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE21:
.size flush_cpu_icache, .-flush_cpu_icache
.align 2
.type flush_cpu_dcache, @function
flush_cpu_dcache:
.LFB22:
.loc 1 29 1
.cfi_startproc
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,12(sp)
.cfi_offset 8, -4
addi s0,sp,16
.cfi_def_cfa 8, 0
.loc 1 33 1
nop
lw s0,12(sp)
.cfi_restore 8
.cfi_def_cfa 2, 16
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE22:
.size flush_cpu_dcache, .-flush_cpu_dcache
.align 2
.type irq_setmask, @function
irq_setmask:
.LFB319:
.file 2 "../../firmware/irq_vex.h"
.loc 2 30 1
.cfi_startproc
addi sp,sp,-32
.cfi_def_cfa_offset 32
sw s0,28(sp)
.cfi_offset 8, -4
addi s0,sp,32
.cfi_def_cfa 8, 0
sw a0,-20(s0)
.loc 2 31 2
lw a5,-20(s0)
#APP
# 31 "../../firmware/irq_vex.h" 1
csrw 3008, a5
# 0 "" 2
.loc 2 32 1
#NO_APP
nop
lw s0,28(sp)
.cfi_restore 8
.cfi_def_cfa 2, 32
addi sp,sp,32
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE319:
.size irq_setmask, .-irq_setmask
.align 2
.globl isr
.type isr, @function
isr:
.LFB321:
.file 3 "../../firmware/isr.c"
.loc 3 24 1
.cfi_startproc
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw ra,12(sp)
sw s0,8(sp)
.cfi_offset 1, -4
.cfi_offset 8, -8
addi s0,sp,16
.cfi_def_cfa 8, 0
.loc 3 28 5
li a0,0
call irq_setmask
.loc 3 43 5
nop
.loc 3 45 1
lw ra,12(sp)
.cfi_restore 1
lw s0,8(sp)
.cfi_restore 8
.cfi_def_cfa 2, 16
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE321:
.size isr, .-isr
.Letext0:
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0xc1
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x3
.4byte .LASF13
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0x4
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0x5
.string "isr"
.byte 0x3
.byte 0x17
.byte 0x6
.4byte .LFB321
.4byte .LFE321-.LFB321
.byte 0x1
.byte 0x9c
.byte 0x6
.4byte .LASF14
.byte 0x2
.byte 0x1d
.byte 0x14
.4byte .LFB319
.4byte .LFE319-.LFB319
.byte 0x1
.byte 0x9c
.4byte 0xa4
.byte 0x7
.4byte .LASF15
.byte 0x2
.byte 0x1d
.byte 0x2d
.4byte 0x65
.byte 0x2
.byte 0x91
.byte 0x6c
.byte 0
.byte 0x2
.4byte .LASF11
.byte 0x1c
.4byte .LFB22
.4byte .LFE22-.LFB22
.byte 0x1
.byte 0x9c
.byte 0x2
.4byte .LASF12
.byte 0xe
.4byte .LFB21
.4byte .LFE21-.LFB21
.byte 0x1
.byte 0x9c
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0x2e
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x25
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0
.byte 0
.byte 0x3
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x4
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0x5
.byte 0x2e
.byte 0
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7c
.byte 0x19
.byte 0
.byte 0
.byte 0x6
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x7
.byte 0x5
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"",@progbits
.4byte 0x1c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte 0
.4byte 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF11:
.string "flush_cpu_dcache"
.LASF6:
.string "unsigned char"
.LASF8:
.string "long unsigned int"
.LASF7:
.string "short unsigned int"
.LASF13:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -ffreestanding"
.LASF14:
.string "irq_setmask"
.LASF10:
.string "unsigned int"
.LASF9:
.string "long long unsigned int"
.LASF12:
.string "flush_cpu_icache"
.LASF5:
.string "long long int"
.LASF15:
.string "mask"
.LASF3:
.string "short int"
.LASF4:
.string "long int"
.LASF2:
.string "signed char"
.section .debug_line_str,"MS",@progbits,1
.LASF0:
.string "../../firmware/isr.c"
.LASF1:
.string "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 14,339 | Final/sdram/testbench/counter_la_mm/counter_la_mm.elf-counter_la_mm.s | .file "counter_la_mm.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm" "counter_la_mm.c"
.align 2
.type flush_cpu_icache, @function
flush_cpu_icache:
.LFB21:
.file 1 "../../firmware/system.h"
.loc 1 15 1
.cfi_startproc
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,12(sp)
.cfi_offset 8, -4
addi s0,sp,16
.cfi_def_cfa 8, 0
.loc 1 26 1
nop
lw s0,12(sp)
.cfi_restore 8
.cfi_def_cfa 2, 16
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE21:
.size flush_cpu_icache, .-flush_cpu_icache
.align 2
.type flush_cpu_dcache, @function
flush_cpu_dcache:
.LFB22:
.loc 1 29 1
.cfi_startproc
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw s0,12(sp)
.cfi_offset 8, -4
addi s0,sp,16
.cfi_def_cfa 8, 0
.loc 1 33 1
nop
lw s0,12(sp)
.cfi_restore 8
.cfi_def_cfa 2, 16
addi sp,sp,16
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE22:
.size flush_cpu_dcache, .-flush_cpu_dcache
.align 2
.globl putchar
.type putchar, @function
putchar:
.LFB316:
.file 2 "../../firmware/stub.c"
.loc 2 19 1
.cfi_startproc
addi sp,sp,-32
.cfi_def_cfa_offset 32
sw ra,28(sp)
sw s0,24(sp)
.cfi_offset 1, -4
.cfi_offset 8, -8
addi s0,sp,32
.cfi_def_cfa 8, 0
mv a5,a0
sb a5,-17(s0)
.loc 2 20 5
lbu a4,-17(s0)
li a5,10
bne a4,a5,.L6
.loc 2 21 3
li a0,13
call putchar
.L6:
.loc 2 22 11
nop
.L5:
.loc 2 22 13 discriminator 1
li a5,-268410880
addi a5,a5,-2044
lw a4,0(a5)
.loc 2 22 60 discriminator 1
li a5,1
beq a4,a5,.L5
.loc 2 23 3
li a5,-268410880
addi a5,a5,-2048
.loc 2 23 50
lbu a4,-17(s0)
sw a4,0(a5)
.loc 2 24 1
nop
lw ra,28(sp)
.cfi_restore 1
lw s0,24(sp)
.cfi_restore 8
.cfi_def_cfa 2, 32
addi sp,sp,32
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE316:
.size putchar, .-putchar
.align 2
.globl print
.type print, @function
print:
.LFB317:
.loc 2 27 1
.cfi_startproc
addi sp,sp,-32
.cfi_def_cfa_offset 32
sw ra,28(sp)
sw s0,24(sp)
.cfi_offset 1, -4
.cfi_offset 8, -8
addi s0,sp,32
.cfi_def_cfa 8, 0
sw a0,-20(s0)
.loc 2 28 8
j .L8
.L9:
.loc 2 29 14
lw a5,-20(s0)
addi a4,a5,1
sw a4,-20(s0)
.loc 2 29 3
lbu a5,0(a5)
mv a0,a5
call putchar
.L8:
.loc 2 28 9
lw a5,-20(s0)
lbu a5,0(a5)
bne a5,zero,.L9
.loc 2 30 1
nop
nop
lw ra,28(sp)
.cfi_restore 1
lw s0,24(sp)
.cfi_restore 8
.cfi_def_cfa 2, 32
addi sp,sp,32
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE317:
.size print, .-print
.align 2
.globl main
.type main, @function
main:
.LFB318:
.file 3 "counter_la_mm.c"
.loc 3 35 1
.cfi_startproc
addi sp,sp,-32
.cfi_def_cfa_offset 32
sw ra,28(sp)
sw s0,24(sp)
.cfi_offset 1, -4
.cfi_offset 8, -8
addi s0,sp,32
.cfi_def_cfa 8, 0
.loc 3 63 10
li a5,637534208
addi a5,a5,160
.loc 3 63 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 64 10
li a5,637534208
addi a5,a5,156
.loc 3 64 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 65 10
li a5,637534208
addi a5,a5,152
.loc 3 65 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 66 10
li a5,637534208
addi a5,a5,148
.loc 3 66 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 67 10
li a5,637534208
addi a5,a5,144
.loc 3 67 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 68 10
li a5,637534208
addi a5,a5,140
.loc 3 68 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 69 10
li a5,637534208
addi a5,a5,136
.loc 3 69 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 70 10
li a5,637534208
addi a5,a5,132
.loc 3 70 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 71 10
li a5,637534208
addi a5,a5,128
.loc 3 71 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 72 10
li a5,637534208
addi a5,a5,124
.loc 3 72 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 73 10
li a5,637534208
addi a5,a5,120
.loc 3 73 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 74 10
li a5,637534208
addi a5,a5,116
.loc 3 74 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 75 10
li a5,637534208
addi a5,a5,112
.loc 3 75 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 76 10
li a5,637534208
addi a5,a5,108
.loc 3 76 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 77 10
li a5,637534208
addi a5,a5,104
.loc 3 77 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 78 10
li a5,637534208
addi a5,a5,100
.loc 3 78 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 80 10
li a5,637534208
addi a5,a5,96
.loc 3 80 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 81 10
li a5,637534208
addi a5,a5,92
.loc 3 81 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 82 10
li a5,637534208
addi a5,a5,88
.loc 3 82 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 83 10
li a5,637534208
addi a5,a5,84
.loc 3 83 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 84 10
li a5,637534208
addi a5,a5,80
.loc 3 84 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 85 10
li a5,637534208
addi a5,a5,76
.loc 3 85 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 86 10
li a5,637534208
addi a5,a5,72
.loc 3 86 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 87 10
li a5,637534208
addi a5,a5,68
.loc 3 87 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 88 10
li a5,637534208
addi a5,a5,64
.loc 3 88 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 89 10
li a5,637534208
addi a5,a5,56
.loc 3 89 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 90 10
li a5,637534208
addi a5,a5,52
.loc 3 90 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 91 10
li a5,637534208
addi a5,a5,48
.loc 3 91 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 92 10
li a5,637534208
addi a5,a5,44
.loc 3 92 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 93 10
li a5,637534208
addi a5,a5,40
.loc 3 93 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 94 10
li a5,637534208
addi a5,a5,36
.loc 3 94 43
li a4,8192
addi a4,a4,-2040
sw a4,0(a5)
.loc 3 96 10
li a5,637534208
addi a5,a5,60
.loc 3 96 43
li a4,8192
addi a4,a4,-2039
sw a4,0(a5)
.loc 3 100 3
li a5,-268410880
.loc 3 100 50
li a4,1
sw a4,0(a5)
.loc 3 103 3
li a5,637534208
.loc 3 103 36
li a4,1
sw a4,0(a5)
.loc 3 104 8
nop
.L11:
.loc 3 104 10 discriminator 1
li a5,637534208
lw a4,0(a5)
.loc 3 104 43 discriminator 1
li a5,1
beq a4,a5,.L11
.loc 3 108 60
li a5,-268423168
addi a4,a5,12
.loc 3 108 114
li a5,0
sw a5,0(a4)
.loc 3 108 3
li a4,-268423168
addi a4,a4,28
.loc 3 108 57
sw a5,0(a4)
.loc 3 109 59
li a5,-268423168
addi a4,a5,8
.loc 3 109 112
li a5,-1
sw a5,0(a4)
.loc 3 109 3
li a4,-268423168
addi a4,a4,24
.loc 3 109 56
sw a5,0(a4)
.loc 3 110 59
li a5,-268423168
addi a4,a5,4
.loc 3 110 112
li a5,0
sw a5,0(a4)
.loc 3 110 3
li a4,-268423168
addi a4,a4,20
.loc 3 110 56
sw a5,0(a4)
.loc 3 111 53
li a4,-268423168
.loc 3 111 100
li a5,0
sw a5,0(a4)
.loc 3 111 3
li a4,-268423168
addi a4,a4,16
.loc 3 111 50
sw a5,0(a4)
.loc 3 114 3
li a5,637534208
addi a5,a5,12
.loc 3 114 36
li a4,-1421869056
sw a4,0(a5)
.loc 3 117 3
li a5,-268423168
addi a5,a5,56
.loc 3 117 56
sw zero,0(a5)
.loc 3 120 59
li a5,-268423168
addi a4,a5,8
.loc 3 120 112
li a5,0
sw a5,0(a4)
.loc 3 120 3
li a4,-268423168
addi a4,a4,24
.loc 3 120 56
sw a5,0(a4)
.loc 3 130 13
call matmul
sw a0,-20(s0)
.loc 3 131 38
lw a5,-20(s0)
lw a5,0(a5)
.loc 3 131 43
slli a4,a5,16
.loc 3 131 3
li a5,637534208
addi a5,a5,12
.loc 3 131 36
sw a4,0(a5)
.loc 3 132 43
lw a5,-20(s0)
addi a5,a5,4
.loc 3 132 38
lw a5,0(a5)
.loc 3 132 47
slli a4,a5,16
.loc 3 132 3
li a5,637534208
addi a5,a5,12
.loc 3 132 36
sw a4,0(a5)
.loc 3 133 43
lw a5,-20(s0)
addi a5,a5,8
.loc 3 133 38
lw a5,0(a5)
.loc 3 133 47
slli a4,a5,16
.loc 3 133 3
li a5,637534208
addi a5,a5,12
.loc 3 133 36
sw a4,0(a5)
.loc 3 134 43
lw a5,-20(s0)
addi a5,a5,12
.loc 3 134 38
lw a5,0(a5)
.loc 3 134 47
slli a4,a5,16
.loc 3 134 3
li a5,637534208
addi a5,a5,12
.loc 3 134 36
sw a4,0(a5)
.loc 3 138 43
lw a5,-20(s0)
addi a5,a5,36
.loc 3 138 38
lw a5,0(a5)
.loc 3 138 47
slli a4,a5,16
.loc 3 138 3
li a5,637534208
addi a5,a5,12
.loc 3 138 36
sw a4,0(a5)
.loc 3 139 3
li a5,637534208
addi a5,a5,12
.loc 3 139 36
li a4,-1420754944
sw a4,0(a5)
.loc 3 140 1
nop
lw ra,28(sp)
.cfi_restore 1
lw s0,24(sp)
.cfi_restore 8
.cfi_def_cfa 2, 32
addi sp,sp,32
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE318:
.size main, .-main
.Letext0:
.file 4 "/opt/riscv/lib/gcc/riscv32-unknown-elf/12.1.0/include/stdint-gcc.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0x12f
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x6
.4byte .LASF16
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0x7
.4byte .LASF17
.byte 0x4
.byte 0x34
.byte 0x1b
.4byte 0x5c
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0x8
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0x9
.4byte .LASF18
.byte 0x3
.byte 0x16
.byte 0xd
.4byte 0x8a
.4byte 0x8a
.byte 0xa
.byte 0
.byte 0x2
.4byte 0x6a
.byte 0xb
.4byte .LASF19
.byte 0x3
.byte 0x22
.byte 0x6
.4byte .LFB318
.4byte .LFE318-.LFB318
.byte 0x1
.byte 0x9c
.4byte 0xbf
.byte 0xc
.string "j"
.byte 0x3
.byte 0x24
.byte 0x6
.4byte 0x6a
.byte 0xd
.string "tmp"
.byte 0x3
.byte 0x82
.byte 0x7
.4byte 0x8a
.byte 0x2
.byte 0x91
.byte 0x6c
.byte 0
.byte 0x3
.4byte .LASF12
.byte 0x1a
.4byte .LFB317
.4byte .LFE317-.LFB317
.byte 0x1
.byte 0x9c
.4byte 0xe0
.byte 0x4
.string "p"
.byte 0x1a
.byte 0x18
.4byte 0xe0
.byte 0x2
.byte 0x91
.byte 0x6c
.byte 0
.byte 0x2
.4byte 0xec
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF11
.byte 0xe
.4byte 0xe5
.byte 0x3
.4byte .LASF13
.byte 0x12
.4byte .LFB316
.4byte .LFE316-.LFB316
.byte 0x1
.byte 0x9c
.4byte 0x112
.byte 0x4
.string "c"
.byte 0x12
.byte 0x13
.4byte 0xe5
.byte 0x2
.byte 0x91
.byte 0x6f
.byte 0
.byte 0x5
.4byte .LASF14
.byte 0x1c
.4byte .LFB22
.4byte .LFE22-.LFB22
.byte 0x1
.byte 0x9c
.byte 0x5
.4byte .LASF15
.byte 0xe
.4byte .LFB21
.4byte .LFE21-.LFB21
.byte 0x1
.byte 0x9c
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0xf
.byte 0
.byte 0xb
.byte 0x21
.byte 0x4
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x3
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x2
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x6
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7c
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x4
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x2
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x5
.byte 0x2e
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x25
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0
.byte 0
.byte 0x6
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x7
.byte 0x16
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x8
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0x9
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x3c
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xa
.byte 0x18
.byte 0
.byte 0
.byte 0
.byte 0xb
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7c
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xc
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xd
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0xe
.byte 0x26
.byte 0
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"",@progbits
.4byte 0x1c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte 0
.4byte 0
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF14:
.string "flush_cpu_dcache"
.LASF18:
.string "matmul"
.LASF6:
.string "unsigned char"
.LASF8:
.string "long unsigned int"
.LASF7:
.string "short unsigned int"
.LASF13:
.string "putchar"
.LASF16:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -ffreestanding"
.LASF19:
.string "main"
.LASF10:
.string "unsigned int"
.LASF9:
.string "long long unsigned int"
.LASF15:
.string "flush_cpu_icache"
.LASF5:
.string "long long int"
.LASF11:
.string "char"
.LASF12:
.string "print"
.LASF3:
.string "short int"
.LASF17:
.string "uint32_t"
.LASF4:
.string "long int"
.LASF2:
.string "signed char"
.section .debug_line_str,"MS",@progbits,1
.LASF0:
.string "counter_la_mm.c"
.LASF1:
.string "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 1,606 | Final/sdram/testbench/counter_la_mm/counter_la_mm.elf-crt0_vex.s | # 0 "../../firmware/crt0_vex.S"
# 1 "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm//"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "../../firmware/crt0_vex.S"
.global main
.global isr
.global _start
_start:
j crt_init
nop
nop
nop
nop
nop
nop
nop
.global trap_entry
trap_entry:
sw x1, - 1*4(sp)
sw x5, - 2*4(sp)
sw x6, - 3*4(sp)
sw x7, - 4*4(sp)
sw x10, - 5*4(sp)
sw x11, - 6*4(sp)
sw x12, - 7*4(sp)
sw x13, - 8*4(sp)
sw x14, - 9*4(sp)
sw x15, -10*4(sp)
sw x16, -11*4(sp)
sw x17, -12*4(sp)
sw x28, -13*4(sp)
sw x29, -14*4(sp)
sw x30, -15*4(sp)
sw x31, -16*4(sp)
addi sp,sp,-16*4
call isr
lw x1 , 15*4(sp)
lw x5, 14*4(sp)
lw x6, 13*4(sp)
lw x7, 12*4(sp)
lw x10, 11*4(sp)
lw x11, 10*4(sp)
lw x12, 9*4(sp)
lw x13, 8*4(sp)
lw x14, 7*4(sp)
lw x15, 6*4(sp)
lw x16, 5*4(sp)
lw x17, 4*4(sp)
lw x28, 3*4(sp)
lw x29, 2*4(sp)
lw x30, 1*4(sp)
lw x31, 0*4(sp)
addi sp,sp,16*4
mret
.text
crt_init:
la sp, _fstack
la a0, trap_entry
csrw mtvec, a0
sram_init:
la a0, _fsram
la a1, _esram
la a2, _esram_rom
sram_loop:
beq a0,a1,sram_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j sram_loop
sram_done:
data_init:
la a0, _fdata
la a1, _edata
la a2, _fdata_rom
data_loop:
beq a0,a1,data_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j data_loop
data_done:
bss_init:
la a0, _fbss
la a1, _ebss
bss_loop:
beq a0,a1,bss_done
sw zero,0(a0)
add a0,a0,4
j bss_loop
bss_done:
li a0, 0x880
csrw mie,a0
call main
infinit_loop:
j infinit_loop
|
fff1214/SoC-Final | 7,308 | Final/sdram/testbench/counter_la_mm/counter_la_mm.elf-matmul.s | .file "matmul.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm" "matmul.c"
.globl A
.data
.align 2
.type A, @object
.size A, 64
A:
.word 0
.word 1
.word 2
.word 3
.word 0
.word 1
.word 2
.word 3
.word 0
.word 1
.word 2
.word 3
.word 0
.word 1
.word 2
.word 3
.globl B
.align 2
.type B, @object
.size B, 64
B:
.word 1
.word 2
.word 3
.word 4
.word 5
.word 6
.word 7
.word 8
.word 9
.word 10
.word 11
.word 12
.word 13
.word 14
.word 15
.word 16
.globl result
.bss
.align 2
.type result, @object
.size result, 64
result:
.zero 64
.globl __mulsi3
.section .mprjram,"ax",@progbits
.align 2
.globl matmul
.type matmul, @function
matmul:
.LFB0:
.file 1 "matmul.c"
.loc 1 4 1
.cfi_startproc
addi sp,sp,-48
.cfi_def_cfa_offset 48
sw ra,44(sp)
sw s0,40(sp)
.cfi_offset 1, -4
.cfi_offset 8, -8
addi s0,sp,48
.cfi_def_cfa 8, 0
.loc 1 5 6
sw zero,-20(s0)
.loc 1 10 15
sw zero,-36(s0)
.loc 1 11 8
sw zero,-20(s0)
.loc 1 11 2
j .L2
.L7:
.loc 1 12 9
sw zero,-24(s0)
.loc 1 12 3
j .L3
.L6:
.loc 1 13 8
sw zero,-32(s0)
.loc 1 14 10
sw zero,-28(s0)
.loc 1 14 4
j .L4
.L5:
.loc 1 15 16 discriminator 3
lw a5,-20(s0)
slli a4,a5,2
.loc 1 15 20 discriminator 3
lw a5,-28(s0)
add a5,a4,a5
.loc 1 15 13 discriminator 3
lui a4,%hi(A)
addi a4,a4,%lo(A)
slli a5,a5,2
add a5,a4,a5
lw a3,0(a5)
.loc 1 15 31 discriminator 3
lw a5,-28(s0)
slli a4,a5,2
.loc 1 15 35 discriminator 3
lw a5,-24(s0)
add a5,a4,a5
.loc 1 15 28 discriminator 3
lui a4,%hi(B)
addi a4,a4,%lo(B)
slli a5,a5,2
add a5,a4,a5
lw a5,0(a5)
.loc 1 15 25 discriminator 3
mv a1,a5
mv a0,a3
call __mulsi3
mv a5,a0
mv a4,a5
.loc 1 15 9 discriminator 3
lw a5,-32(s0)
add a5,a5,a4
sw a5,-32(s0)
.loc 1 14 19 discriminator 3
lw a5,-28(s0)
addi a5,a5,1
sw a5,-28(s0)
.L4:
.loc 1 14 15 discriminator 1
lw a4,-28(s0)
li a5,3
ble a4,a5,.L5
.loc 1 16 13 discriminator 2
lw a5,-20(s0)
slli a4,a5,2
.loc 1 16 17 discriminator 2
lw a5,-24(s0)
add a5,a4,a5
.loc 1 16 22 discriminator 2
lui a4,%hi(result)
addi a4,a4,%lo(result)
slli a5,a5,2
add a5,a4,a5
lw a4,-32(s0)
sw a4,0(a5)
.loc 1 12 19 discriminator 2
lw a5,-24(s0)
addi a5,a5,1
sw a5,-24(s0)
.L3:
.loc 1 12 14 discriminator 1
lw a4,-24(s0)
li a5,3
ble a4,a5,.L6
.loc 1 11 18 discriminator 2
lw a5,-20(s0)
addi a5,a5,1
sw a5,-20(s0)
.L2:
.loc 1 11 13 discriminator 1
lw a4,-20(s0)
li a5,3
ble a4,a5,.L7
.loc 1 19 9
lui a5,%hi(result)
addi a5,a5,%lo(result)
.loc 1 20 1
mv a0,a5
lw ra,44(sp)
.cfi_restore 1
lw s0,40(sp)
.cfi_restore 8
.cfi_def_cfa 2, 48
addi sp,sp,48
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
.LFE0:
.size matmul, .-matmul
.text
.Letext0:
.file 2 "matmul.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0xd8
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x3
.4byte .LASF5
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .LLRL0
.4byte 0
.4byte .Ldebug_line0
.byte 0x4
.4byte 0x3d
.4byte 0x36
.byte 0x5
.4byte 0x36
.byte 0xf
.byte 0
.byte 0x6
.byte 0x4
.byte 0x7
.4byte .LASF2
.byte 0x7
.byte 0x4
.byte 0x5
.string "int"
.byte 0x2
.string "A"
.byte 0x5
.4byte 0x26
.byte 0x5
.byte 0x3
.4byte A
.byte 0x2
.string "B"
.byte 0xa
.4byte 0x26
.byte 0x5
.byte 0x3
.4byte B
.byte 0x8
.4byte .LASF3
.byte 0x2
.byte 0xf
.byte 0x6
.4byte 0x26
.byte 0x5
.byte 0x3
.4byte result
.byte 0x9
.4byte .LASF6
.byte 0x1
.byte 0x3
.byte 0x33
.4byte 0xd5
.4byte .LFB0
.4byte .LFE0-.LFB0
.byte 0x1
.byte 0x9c
.4byte 0xd5
.byte 0x1
.string "i"
.byte 0x5
.4byte 0x3d
.byte 0x2
.byte 0x91
.byte 0x6c
.byte 0x1
.string "j"
.byte 0x6
.4byte 0x3d
.byte 0x2
.byte 0x91
.byte 0x68
.byte 0x1
.string "k"
.byte 0x7
.4byte 0x3d
.byte 0x2
.byte 0x91
.byte 0x64
.byte 0x1
.string "sum"
.byte 0x8
.4byte 0x3d
.byte 0x2
.byte 0x91
.byte 0x60
.byte 0xa
.string "kk"
.byte 0x1
.byte 0x9
.byte 0x6
.4byte 0x3d
.byte 0xb
.4byte .LASF4
.byte 0x1
.byte 0xa
.byte 0xf
.4byte 0x36
.byte 0x2
.byte 0x91
.byte 0x5c
.byte 0
.byte 0xc
.byte 0x4
.4byte 0x3d
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x6
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x2
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x2
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x6
.byte 0x49
.byte 0x13
.byte 0x3f
.byte 0x19
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x3
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x55
.byte 0x17
.byte 0x11
.byte 0x1
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x4
.byte 0x1
.byte 0x1
.byte 0x49
.byte 0x13
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x5
.byte 0x21
.byte 0
.byte 0x49
.byte 0x13
.byte 0x2f
.byte 0xb
.byte 0
.byte 0
.byte 0x6
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x7
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0x8
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x3f
.byte 0x19
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x9
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7c
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xa
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xb
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0xc
.byte 0xf
.byte 0
.byte 0xb
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0
.section .debug_aranges,"",@progbits
.4byte 0x1c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .LFB0
.4byte .LFE0-.LFB0
.4byte 0
.4byte 0
.section .debug_rnglists,"",@progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2
.Ldebug_ranges2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.LLRL0:
.byte 0x6
.4byte .LFB0
.4byte .LFE0
.byte 0
.Ldebug_ranges3:
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF2:
.string "unsigned int"
.LASF3:
.string "result"
.LASF4:
.string "count"
.LASF6:
.string "matmul"
.LASF5:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -ffreestanding"
.section .debug_line_str,"MS",@progbits,1
.LASF1:
.string "/home/ubuntu/Desktop/lab-wlos_baseline/testbench/counter_la_mm"
.LASF0:
.string "matmul.c"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 6,209 | Final/Final_UART_FIFO/firmware/start_pico.S | /*
* Copyright 2018, Serge Bazanski <serge@bazanski.pl>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted.
*/
#include "../extraops.S"
/*
* Interrupt vector.
*/
.global _start
_start:
.org 0x00000000 # Reset
j _crt0
.org 0x00000010 # IRQ
_irq_vector:
addi sp, sp, -16
sw t0, 4(sp)
sw ra, 8(sp)
/* By convention, q2 holds true IRQ vector, but remains caller-save.
We rely on the assumption that compiler-generated code will never touch
the QREGs. q3 is truly scratch/caller-save. */
picorv32_getq_insn(t0, q2)
sw t0, 12(sp)
jalr t0 // Call the true IRQ vector.
lw t0, 12(sp)
picorv32_setq_insn(q2, t0) // Restore the true IRQ vector.
lw ra, 8(sp)
lw t0, 4(sp)
addi sp, sp, 16
picorv32_retirq_insn() // return from interrupt
/*
* IRQ handler, branched to from the vector.
*/
_irq:
/* save x1/x2 to q1/q2 */
picorv32_setq_insn(q2, x1)
picorv32_setq_insn(q3, x2)
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* use x2 as scratch space for saving registers */
/* q0 (== x1), q2(== x2), q3 */
picorv32_getq_insn(x2, q0)
sw x2, 0*4(x1)
picorv32_getq_insn(x2, q2)
sw x2, 1*4(x1)
picorv32_getq_insn(x2, q3)
sw x2, 2*4(x1)
/* save x3 - x31 */
sw x3, 3*4(x1)
sw x4, 4*4(x1)
sw x5, 5*4(x1)
sw x6, 6*4(x1)
sw x7, 7*4(x1)
sw x8, 8*4(x1)
sw x9, 9*4(x1)
sw x10, 10*4(x1)
sw x11, 11*4(x1)
sw x12, 12*4(x1)
sw x13, 13*4(x1)
sw x14, 14*4(x1)
sw x15, 15*4(x1)
sw x16, 16*4(x1)
sw x17, 17*4(x1)
sw x18, 18*4(x1)
sw x19, 19*4(x1)
sw x20, 20*4(x1)
sw x21, 21*4(x1)
sw x22, 22*4(x1)
sw x23, 23*4(x1)
sw x24, 24*4(x1)
sw x25, 25*4(x1)
sw x26, 26*4(x1)
sw x27, 27*4(x1)
sw x28, 28*4(x1)
sw x29, 29*4(x1)
sw x30, 30*4(x1)
sw x31, 31*4(x1)
/* update _irq_pending to the currently pending interrupts */
picorv32_getq_insn(t0, q1)
la t1, (_irq_pending)
sw t0, 0(t1)
/* prepare C handler stack */
lui sp, %hi(_irq_stack)
addi sp, sp, %lo(_irq_stack)
/* call C handler */
jal ra, isr
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* restore q0 - q2 */
lw x2, 0*4(x1)
picorv32_setq_insn(q0, x2)
lw x2, 1*4(x1)
picorv32_setq_insn(q1, x2)
lw x2, 2*4(x1)
picorv32_setq_insn(q2, x2)
/* restore x3 - x31 */
lw x3, 3*4(x1)
lw x4, 4*4(x1)
lw x5, 5*4(x1)
lw x6, 6*4(x1)
lw x7, 7*4(x1)
lw x8, 8*4(x1)
lw x9, 9*4(x1)
lw x10, 10*4(x1)
lw x11, 11*4(x1)
lw x12, 12*4(x1)
lw x13, 13*4(x1)
lw x14, 14*4(x1)
lw x15, 15*4(x1)
lw x16, 16*4(x1)
lw x17, 17*4(x1)
lw x18, 18*4(x1)
lw x19, 19*4(x1)
lw x20, 20*4(x1)
lw x21, 21*4(x1)
lw x22, 22*4(x1)
lw x23, 23*4(x1)
lw x24, 24*4(x1)
lw x25, 25*4(x1)
lw x26, 26*4(x1)
lw x27, 27*4(x1)
lw x28, 28*4(x1)
lw x29, 29*4(x1)
lw x30, 30*4(x1)
lw x31, 31*4(x1)
/* restore x1 - x2 from q registers */
picorv32_getq_insn(x1, q1)
picorv32_getq_insn(x2, q2)
ret
/*
* Reset handler, branched to from the vector.
*/
_crt0:
/* zero-initialize all registers */
addi x1, zero, 0
addi x2, zero, 0
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
/* mask all interrupts */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* reflect that in _irq_mask */
la t1, _irq_mask
sw t0, 0(t1)
/* Load DATA */
la t0, _fdata_rom
la t1, _fdata
la t2, _edata
3:
lw t3, 0(t0)
sw t3, 0(t1)
/* _edata is aligned to 16 bytes. Use word-xfers. */
addi t0, t0, 4
addi t1, t1, 4
bltu t1, t2, 3b
/* Clear BSS */
#la t0, _fbss
#la t1, _ebss
2:
#sw zero, 0(t0)
#addi t0, t0, 4
#bltu t0, t1, 2b
/* set main stack */
la sp, _fstack
/* Set up address to IRQ handler since vector is hardcoded.
By convention, q2 keeps the pointer to the true IRQ handler,
to emulate relocatable interrupts. */
la t0, _irq
picorv32_setq_insn(q2, t0)
/* jump to main */
jal ra, main
1:
/* loop forever */
j 1b
/*
* Enable interrupts by copying the software mask to the hardware mask
*/
.global _irq_enable
_irq_enable:
/* Set _irq_enabled to true */
la t0, _irq_enabled
addi t1, zero, 1
sw t1, 0(t0)
/* Set the HW IRQ mask to _irq_mask */
la t0, _irq_mask
lw t0, 0(t0)
picorv32_maskirq_insn(zero, t0)
ret
/*
* Disable interrupts by masking all interrupts (the mask should already be
* up to date)
*/
.global _irq_disable
_irq_disable:
/* Mask all IRQs */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* Set _irq_enabled to false */
la t0, _irq_enabled
sw zero, (t0)
ret
/*
* Set interrrupt mask.
* This updates the software mask (for readback and interrupt inable/disable)
* and the hardware mask.
* 1 means interrupt is masked (disabled).
*/
.global _irq_setmask
_irq_setmask:
/* Update _irq_mask */
la t0, _irq_mask
sw a0, (t0)
/* Are interrupts enabled? */
la t0, _irq_enabled
lw t0, 0(t0)
beq t0, zero, 1f
/* If so, update the HW IRQ mask */
picorv32_maskirq_insn(zero, a0)
1:
ret
.section .bss
irq_regs:
/* saved interrupt registers, x0 - x31 */
.fill 32,4
/* interrupt stack */
.fill 256,4
_irq_stack:
/*
* Bitfield of pending interrupts, updated on ISR entry.
*/
.global _irq_pending
_irq_pending:
.word 0
/*
* Software copy of enabled interrupts. Do not write directly, use
* _irq_set_mask instead.
*/
.global _irq_mask
_irq_mask:
.word 0
/*
* Software state of global interrupts being enabled or disabled. Do not write
* directly, use _irq_disable / _irq_enable instead.
*/
.global _irq_enabled
_irq_enabled:
.word 0
|
fff1214/SoC-Final | 2,655 | Final/Final_UART_FIFO/firmware/extraops.S | // This is free and unencumbered software released into the public domain.
//
// Anyone is free to copy, modify, publish, use, compile, sell, or
// distribute this software, either in source code form or as a compiled
// binary, for any purpose, commercial or non-commercial, and by any
// means.
#define regnum_q0 0
#define regnum_q1 1
#define regnum_q2 2
#define regnum_q3 3
#define regnum_x0 0
#define regnum_x1 1
#define regnum_x2 2
#define regnum_x3 3
#define regnum_x4 4
#define regnum_x5 5
#define regnum_x6 6
#define regnum_x7 7
#define regnum_x8 8
#define regnum_x9 9
#define regnum_x10 10
#define regnum_x11 11
#define regnum_x12 12
#define regnum_x13 13
#define regnum_x14 14
#define regnum_x15 15
#define regnum_x16 16
#define regnum_x17 17
#define regnum_x18 18
#define regnum_x19 19
#define regnum_x20 20
#define regnum_x21 21
#define regnum_x22 22
#define regnum_x23 23
#define regnum_x24 24
#define regnum_x25 25
#define regnum_x26 26
#define regnum_x27 27
#define regnum_x28 28
#define regnum_x29 29
#define regnum_x30 30
#define regnum_x31 31
#define regnum_zero 0
#define regnum_ra 1
#define regnum_sp 2
#define regnum_gp 3
#define regnum_tp 4
#define regnum_t0 5
#define regnum_t1 6
#define regnum_t2 7
#define regnum_s0 8
#define regnum_s1 9
#define regnum_a0 10
#define regnum_a1 11
#define regnum_a2 12
#define regnum_a3 13
#define regnum_a4 14
#define regnum_a5 15
#define regnum_a6 16
#define regnum_a7 17
#define regnum_s2 18
#define regnum_s3 19
#define regnum_s4 20
#define regnum_s5 21
#define regnum_s6 22
#define regnum_s7 23
#define regnum_s8 24
#define regnum_s9 25
#define regnum_s10 26
#define regnum_s11 27
#define regnum_t3 28
#define regnum_t4 29
#define regnum_t5 30
#define regnum_t6 31
// x8 is s0 and also fp
#define regnum_fp 8
#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
#define picorv32_getq_insn(_rd, _qs) \
r_type_insn(0b0000000, 0, regnum_ ## _qs, 0b100, regnum_ ## _rd, 0b0001011)
#define picorv32_setq_insn(_qd, _rs) \
r_type_insn(0b0000001, 0, regnum_ ## _rs, 0b010, regnum_ ## _qd, 0b0001011)
#define picorv32_retirq_insn() \
r_type_insn(0b0000010, 0, 0, 0b000, 0, 0b0001011)
#define picorv32_maskirq_insn(_rd, _rs) \
r_type_insn(0b0000011, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
#define picorv32_waitirq_insn(_rd) \
r_type_insn(0b0000100, 0, 0, 0b100, regnum_ ## _rd, 0b0001011)
#define picorv32_timer_insn(_rd, _rs) \
r_type_insn(0b0000101, 0, regnum_ ## _rs, 0b110, regnum_ ## _rd, 0b0001011)
|
fff1214/SoC-Final | 1,662 | Final/Final_UART_FIFO/firmware/crt0_vex.S | .global main
.global isr
.global _start
_start:
j crt_init
nop
nop
nop
nop
nop
nop
nop
.global trap_entry
trap_entry:
sw x1, - 1*4(sp)
sw x5, - 2*4(sp)
sw x6, - 3*4(sp)
sw x7, - 4*4(sp)
sw x10, - 5*4(sp)
sw x11, - 6*4(sp)
sw x12, - 7*4(sp)
sw x13, - 8*4(sp)
sw x14, - 9*4(sp)
sw x15, -10*4(sp)
sw x16, -11*4(sp)
sw x17, -12*4(sp)
sw x28, -13*4(sp)
sw x29, -14*4(sp)
sw x30, -15*4(sp)
sw x31, -16*4(sp)
addi sp,sp,-16*4
call isr
lw x1 , 15*4(sp)
lw x5, 14*4(sp)
lw x6, 13*4(sp)
lw x7, 12*4(sp)
lw x10, 11*4(sp)
lw x11, 10*4(sp)
lw x12, 9*4(sp)
lw x13, 8*4(sp)
lw x14, 7*4(sp)
lw x15, 6*4(sp)
lw x16, 5*4(sp)
lw x17, 4*4(sp)
lw x28, 3*4(sp)
lw x29, 2*4(sp)
lw x30, 1*4(sp)
lw x31, 0*4(sp)
addi sp,sp,16*4
mret
.text
crt_init:
la sp, _fstack
la a0, trap_entry
csrw mtvec, a0
sram_init:
la a0, _fsram
la a1, _esram
la a2, _esram_rom
sram_loop:
beq a0,a1,sram_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j sram_loop
sram_done:
data_init:
la a0, _fdata
la a1, _edata
la a2, _fdata_rom
data_loop:
beq a0,a1,data_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j data_loop
data_done:
bss_init:
la a0, _fbss
la a1, _ebss
bss_loop:
beq a0,a1,bss_done
sw zero,0(a0)
add a0,a0,4
#ifndef SIM
j bss_loop
#endif
bss_done:
li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
csrw mie,a0
#ifdef USER_PROJ_IRQ0_EN
csrrs a0, mstatus, 0x8 //0x8 set mstatus.MIE
#endif
call main
infinit_loop:
j infinit_loop
|
fff1214/SoC-Final | 1,803 | Final/Final_UART_FIFO/firmware/crt0_ibex.S | # Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#include "simple_system_regs.h"
.section .text
default_exc_handler:
jal x0, simple_exc_handler
timer_handler:
jal x0, simple_timer_handler
reset_handler:
/* set all registers to zero */
mv x1, x0
mv x2, x1
mv x3, x1
mv x4, x1
mv x5, x1
mv x6, x1
mv x7, x1
mv x8, x1
mv x9, x1
mv x10, x1
mv x11, x1
mv x12, x1
mv x13, x1
mv x14, x1
mv x15, x1
mv x16, x1
mv x17, x1
mv x18, x1
mv x19, x1
mv x20, x1
mv x21, x1
mv x22, x1
mv x23, x1
mv x24, x1
mv x25, x1
mv x26, x1
mv x27, x1
mv x28, x1
mv x29, x1
mv x30, x1
mv x31, x1
/* stack initilization */
# la x2, _stack_start
la x2, 0x01000800
_start:
.global _start
/* clear BSS */
la x26, _bss_start
la x27, _bss_end
bge x26, x27, zero_loop_end
zero_loop:
sw x0, 0(x26)
addi x26, x26, 4
ble x26, x27, zero_loop
zero_loop_end:
main_entry:
/* jump to main program entry point (argc = argv = 0) */
addi x10, x0, 0
addi x11, x0, 0
jal x1, main
/* Halt simulation */
#li x5, SIM_CTRL_BASE + SIM_CTRL_CTRL
#li x6, 1
#sw x6, 0(x5)
/* If execution ends up here just put the core to sleep */
sleep_loop:
wfi
j sleep_loop
/* =================================================== [ exceptions ] === */
/* This section has to be down here, since we have to disable rvc for it */
.section .vectors, "ax"
.option norvc;
// All unimplemented interrupts/exceptions go to the default_exc_handler.
.org 0x00
.rept 7
jal x0, default_exc_handler
.endr
jal x0, timer_handler
.rept 23
jal x0, default_exc_handler
.endr
// reset vector
.org 0x80
jal x0, reset_handler
|
fff1214/SoC-Final | 3,215 | Final/Final_UART_FIFO/firmware/start_caravel_vexriscv.s | # SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
.section .text
start:
# zero-initialize register file
addi x1, zero, 0
# x2 (sp) is initialized by reset
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
# zero initialize scratchpad memory
# setmemloop:
# sw zero, 0(x1)
# addi x1, x1, 4
# blt x1, sp, setmemloop
# copy data section
la a0, _sidata
la a1, _sdata
la a2, _edata
bge a1, a2, end_init_data
loop_init_data:
lw a3, 0(a0)
sw a3, 0(a1)
addi a0, a0, 4
addi a1, a1, 4
blt a1, a2, loop_init_data
end_init_data:
# zero-init bss section
la a0, _sbss
la a1, _ebss
bge a0, a1, end_init_bss
loop_init_bss:
sw zero, 0(a0)
addi a0, a0, 4
blt a0, a1, loop_init_bss
end_init_bss:
la sp, _fstack
# call main
call main
loop:
j loop
.global flashio_worker_begin
.global flashio_worker_end
.balign 4
flashio_worker_begin:
# a0 ... data pointer
# a1 ... data length
# a2 ... optional WREN cmd (0 = disable)
# address of SPI ctrl reg
li t0, 0x28000000
# Set CS high, IO0 is output
li t1, 0x120
sh t1, 0(t0)
# Enable Manual SPI Ctrl
sb zero, 3(t0)
# Send optional WREN cmd
beqz a2, flashio_worker_L1
li t5, 8
andi t2, a2, 0xff
flashio_worker_L4:
srli t4, t2, 7
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
slli t2, t2, 1
andi t2, t2, 0xff
addi t5, t5, -1
bnez t5, flashio_worker_L4
sb t1, 0(t0)
# SPI transfer
flashio_worker_L1:
# If byte count is zero, we're done
beqz a1, flashio_worker_L3
# Set t5 to count down 32 bits
li t5, 32
# Load t2 from address a0 (4 bytes)
lw t2, 0(a0)
flashio_worker_LY:
# Set t6 to count down 8 bits
li t6, 8
flashio_worker_L2:
# Clock out the bit (msb first) on IO0 and read bit in from IO1
srli t4, t2, 31
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
lbu t4, 0(t0)
andi t4, t4, 2
srli t4, t4, 1
slli t2, t2, 1
or t2, t2, t4
# Decrement 32 bit count
addi t5, t5, -1
bnez t5, flashio_worker_LX
sw t2, 0(a0)
addi a0, a0, 4
lw t2, 0(a0)
flashio_worker_LX:
addi t6, t6, -1
bnez t6, flashio_worker_L2
addi a1, a1, -1
bnez a1, flashio_worker_LY
beqz t5, flashio_worker_L3
sw t2, 0(a0)
flashio_worker_L3:
# Back to MEMIO mode
li t1, 0x80
sb t1, 3(t0)
ret
.balign 4
flashio_worker_end:
|
fff1214/SoC-Final | 3,199 | Final/Final_UART_FIFO/firmware/start_caravel_ibex.s | # SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
.section .text
start:
# zero-initialize register file
addi x1, zero, 0
# x2 (sp) is initialized by reset
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
# zero initialize scratchpad memory
# setmemloop:
# sw zero, 0(x1)
# addi x1, x1, 4
# blt x1, sp, setmemloop
# copy data section
la a0, _sidata
la a1, _sdata
la a2, _edata
bge a1, a2, end_init_data
loop_init_data:
lw a3, 0(a0)
sw a3, 0(a1)
addi a0, a0, 4
addi a1, a1, 4
blt a1, a2, loop_init_data
end_init_data:
# zero-init bss section
la a0, _sbss
la a1, _ebss
bge a0, a1, end_init_bss
loop_init_bss:
sw zero, 0(a0)
addi a0, a0, 4
blt a0, a1, loop_init_bss
end_init_bss:
# call main
call main
loop:
j loop
.global flashio_worker_begin
.global flashio_worker_end
.balign 4
flashio_worker_begin:
# a0 ... data pointer
# a1 ... data length
# a2 ... optional WREN cmd (0 = disable)
# address of SPI ctrl reg
li t0, 0x28000000
# Set CS high, IO0 is output
li t1, 0x120
sh t1, 0(t0)
# Enable Manual SPI Ctrl
sb zero, 3(t0)
# Send optional WREN cmd
beqz a2, flashio_worker_L1
li t5, 8
andi t2, a2, 0xff
flashio_worker_L4:
srli t4, t2, 7
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
slli t2, t2, 1
andi t2, t2, 0xff
addi t5, t5, -1
bnez t5, flashio_worker_L4
sb t1, 0(t0)
# SPI transfer
flashio_worker_L1:
# If byte count is zero, we're done
beqz a1, flashio_worker_L3
# Set t5 to count down 32 bits
li t5, 32
# Load t2 from address a0 (4 bytes)
lw t2, 0(a0)
flashio_worker_LY:
# Set t6 to count down 8 bits
li t6, 8
flashio_worker_L2:
# Clock out the bit (msb first) on IO0 and read bit in from IO1
srli t4, t2, 31
sb t4, 0(t0)
ori t4, t4, 0x10
sb t4, 0(t0)
lbu t4, 0(t0)
andi t4, t4, 2
srli t4, t4, 1
slli t2, t2, 1
or t2, t2, t4
# Decrement 32 bit count
addi t5, t5, -1
bnez t5, flashio_worker_LX
sw t2, 0(a0)
addi a0, a0, 4
lw t2, 0(a0)
flashio_worker_LX:
addi t6, t6, -1
bnez t6, flashio_worker_L2
addi a1, a1, -1
bnez a1, flashio_worker_LY
beqz t5, flashio_worker_L3
sw t2, 0(a0)
flashio_worker_L3:
# Back to MEMIO mode
li t1, 0x80
sb t1, 3(t0)
ret
.balign 4
flashio_worker_end:
|
fff1214/SoC-Final | 6,209 | Final/Final_UART_FIFO/firmware/start.S | /*
* Copyright 2018, Serge Bazanski <serge@bazanski.pl>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted.
*/
#include "../extraops.S"
/*
* Interrupt vector.
*/
.global _start
_start:
.org 0x00000000 # Reset
j _crt0
.org 0x00000010 # IRQ
_irq_vector:
addi sp, sp, -16
sw t0, 4(sp)
sw ra, 8(sp)
/* By convention, q2 holds true IRQ vector, but remains caller-save.
We rely on the assumption that compiler-generated code will never touch
the QREGs. q3 is truly scratch/caller-save. */
picorv32_getq_insn(t0, q2)
sw t0, 12(sp)
jalr t0 // Call the true IRQ vector.
lw t0, 12(sp)
picorv32_setq_insn(q2, t0) // Restore the true IRQ vector.
lw ra, 8(sp)
lw t0, 4(sp)
addi sp, sp, 16
picorv32_retirq_insn() // return from interrupt
/*
* IRQ handler, branched to from the vector.
*/
_irq:
/* save x1/x2 to q1/q2 */
picorv32_setq_insn(q2, x1)
picorv32_setq_insn(q3, x2)
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* use x2 as scratch space for saving registers */
/* q0 (== x1), q2(== x2), q3 */
picorv32_getq_insn(x2, q0)
sw x2, 0*4(x1)
picorv32_getq_insn(x2, q2)
sw x2, 1*4(x1)
picorv32_getq_insn(x2, q3)
sw x2, 2*4(x1)
/* save x3 - x31 */
sw x3, 3*4(x1)
sw x4, 4*4(x1)
sw x5, 5*4(x1)
sw x6, 6*4(x1)
sw x7, 7*4(x1)
sw x8, 8*4(x1)
sw x9, 9*4(x1)
sw x10, 10*4(x1)
sw x11, 11*4(x1)
sw x12, 12*4(x1)
sw x13, 13*4(x1)
sw x14, 14*4(x1)
sw x15, 15*4(x1)
sw x16, 16*4(x1)
sw x17, 17*4(x1)
sw x18, 18*4(x1)
sw x19, 19*4(x1)
sw x20, 20*4(x1)
sw x21, 21*4(x1)
sw x22, 22*4(x1)
sw x23, 23*4(x1)
sw x24, 24*4(x1)
sw x25, 25*4(x1)
sw x26, 26*4(x1)
sw x27, 27*4(x1)
sw x28, 28*4(x1)
sw x29, 29*4(x1)
sw x30, 30*4(x1)
sw x31, 31*4(x1)
/* update _irq_pending to the currently pending interrupts */
picorv32_getq_insn(t0, q1)
la t1, (_irq_pending)
sw t0, 0(t1)
/* prepare C handler stack */
lui sp, %hi(_irq_stack)
addi sp, sp, %lo(_irq_stack)
/* call C handler */
jal ra, isr
/* use x1 to index into irq_regs */
lui x1, %hi(irq_regs)
addi x1, x1, %lo(irq_regs)
/* restore q0 - q2 */
lw x2, 0*4(x1)
picorv32_setq_insn(q0, x2)
lw x2, 1*4(x1)
picorv32_setq_insn(q1, x2)
lw x2, 2*4(x1)
picorv32_setq_insn(q2, x2)
/* restore x3 - x31 */
lw x3, 3*4(x1)
lw x4, 4*4(x1)
lw x5, 5*4(x1)
lw x6, 6*4(x1)
lw x7, 7*4(x1)
lw x8, 8*4(x1)
lw x9, 9*4(x1)
lw x10, 10*4(x1)
lw x11, 11*4(x1)
lw x12, 12*4(x1)
lw x13, 13*4(x1)
lw x14, 14*4(x1)
lw x15, 15*4(x1)
lw x16, 16*4(x1)
lw x17, 17*4(x1)
lw x18, 18*4(x1)
lw x19, 19*4(x1)
lw x20, 20*4(x1)
lw x21, 21*4(x1)
lw x22, 22*4(x1)
lw x23, 23*4(x1)
lw x24, 24*4(x1)
lw x25, 25*4(x1)
lw x26, 26*4(x1)
lw x27, 27*4(x1)
lw x28, 28*4(x1)
lw x29, 29*4(x1)
lw x30, 30*4(x1)
lw x31, 31*4(x1)
/* restore x1 - x2 from q registers */
picorv32_getq_insn(x1, q1)
picorv32_getq_insn(x2, q2)
ret
/*
* Reset handler, branched to from the vector.
*/
_crt0:
/* zero-initialize all registers */
addi x1, zero, 0
addi x2, zero, 0
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
/* mask all interrupts */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* reflect that in _irq_mask */
la t1, _irq_mask
sw t0, 0(t1)
/* Load DATA */
la t0, _fdata_rom
la t1, _fdata
la t2, _edata
3:
lw t3, 0(t0)
sw t3, 0(t1)
/* _edata is aligned to 16 bytes. Use word-xfers. */
addi t0, t0, 4
addi t1, t1, 4
bltu t1, t2, 3b
/* Clear BSS */
#la t0, _fbss
#la t1, _ebss
2:
#sw zero, 0(t0)
#addi t0, t0, 4
#bltu t0, t1, 2b
/* set main stack */
la sp, _fstack
/* Set up address to IRQ handler since vector is hardcoded.
By convention, q2 keeps the pointer to the true IRQ handler,
to emulate relocatable interrupts. */
la t0, _irq
picorv32_setq_insn(q2, t0)
/* jump to main */
jal ra, main
1:
/* loop forever */
j 1b
/*
* Enable interrupts by copying the software mask to the hardware mask
*/
.global _irq_enable
_irq_enable:
/* Set _irq_enabled to true */
la t0, _irq_enabled
addi t1, zero, 1
sw t1, 0(t0)
/* Set the HW IRQ mask to _irq_mask */
la t0, _irq_mask
lw t0, 0(t0)
picorv32_maskirq_insn(zero, t0)
ret
/*
* Disable interrupts by masking all interrupts (the mask should already be
* up to date)
*/
.global _irq_disable
_irq_disable:
/* Mask all IRQs */
li t0, 0xffffffff
picorv32_maskirq_insn(zero, t0)
/* Set _irq_enabled to false */
la t0, _irq_enabled
sw zero, (t0)
ret
/*
* Set interrrupt mask.
* This updates the software mask (for readback and interrupt inable/disable)
* and the hardware mask.
* 1 means interrupt is masked (disabled).
*/
.global _irq_setmask
_irq_setmask:
/* Update _irq_mask */
la t0, _irq_mask
sw a0, (t0)
/* Are interrupts enabled? */
la t0, _irq_enabled
lw t0, 0(t0)
beq t0, zero, 1f
/* If so, update the HW IRQ mask */
picorv32_maskirq_insn(zero, a0)
1:
ret
.section .bss
irq_regs:
/* saved interrupt registers, x0 - x31 */
.fill 32,4
/* interrupt stack */
.fill 256,4
_irq_stack:
/*
* Bitfield of pending interrupts, updated on ISR entry.
*/
.global _irq_pending
_irq_pending:
.word 0
/*
* Software copy of enabled interrupts. Do not write directly, use
* _irq_set_mask instead.
*/
.global _irq_mask
_irq_mask:
.word 0
/*
* Software state of global interrupts being enabled or disabled. Do not write
* directly, use _irq_disable / _irq_enable instead.
*/
.global _irq_enabled
_irq_enabled:
.word 0
|
fff1214/SoC-Final | 12,305 | Final/Final_UART_FIFO/testbench/uart/uart.elf-counter_la_uart.s | .file "counter_la_uart.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/Final_test-main/testbench/uart" "counter_la_uart.c"
.section .text.startup,"ax",@progbits
.align 2
.globl main
.type main, @function
main:
.LFB321:
.file 1 "counter_la_uart.c"
.loc 1 44 1
.cfi_startproc
.loc 1 46 5
.loc 1 74 5
.loc 1 74 53 is_stmt 0
li a2,1
.loc 1 76 39
li a3,8192
.loc 1 74 53
li a4,-268419072
.loc 1 76 39
li a5,637534208
.loc 1 74 53
sw a2,-2048(a4)
.loc 1 76 5 is_stmt 1
.loc 1 76 39 is_stmt 0
addi a4,a3,-2039
sw a4,160(a5)
.loc 1 77 5 is_stmt 1
.loc 1 77 39 is_stmt 0
sw a4,156(a5)
.loc 1 78 5 is_stmt 1
.loc 1 78 39 is_stmt 0
sw a4,152(a5)
.loc 1 79 5 is_stmt 1
.loc 1 79 39 is_stmt 0
sw a4,148(a5)
.loc 1 80 5 is_stmt 1
.loc 1 80 39 is_stmt 0
sw a4,144(a5)
.loc 1 81 5 is_stmt 1
.loc 1 81 39 is_stmt 0
sw a4,140(a5)
.loc 1 82 5 is_stmt 1
.loc 1 82 39 is_stmt 0
sw a4,136(a5)
.loc 1 83 5 is_stmt 1
.loc 1 83 39 is_stmt 0
sw a4,132(a5)
.loc 1 84 5 is_stmt 1
.loc 1 84 39 is_stmt 0
sw a4,128(a5)
.loc 1 85 5 is_stmt 1
.loc 1 85 39 is_stmt 0
sw a4,124(a5)
.loc 1 86 5 is_stmt 1
.loc 1 86 39 is_stmt 0
sw a4,120(a5)
.loc 1 87 5 is_stmt 1
.loc 1 87 39 is_stmt 0
sw a4,116(a5)
.loc 1 88 5 is_stmt 1
.loc 1 88 39 is_stmt 0
sw a4,112(a5)
.loc 1 89 5 is_stmt 1
.loc 1 89 39 is_stmt 0
sw a4,108(a5)
.loc 1 90 5 is_stmt 1
.loc 1 90 39 is_stmt 0
sw a4,104(a5)
.loc 1 91 5 is_stmt 1
.loc 1 91 39 is_stmt 0
sw a4,100(a5)
.loc 1 93 5 is_stmt 1
.loc 1 93 39 is_stmt 0
sw a4,96(a5)
.loc 1 94 5 is_stmt 1
.loc 1 94 39 is_stmt 0
sw a4,92(a5)
.loc 1 95 5 is_stmt 1
.loc 1 95 39 is_stmt 0
sw a4,88(a5)
.loc 1 96 5 is_stmt 1
.loc 1 96 39 is_stmt 0
sw a4,84(a5)
.loc 1 97 5 is_stmt 1
.loc 1 97 39 is_stmt 0
sw a4,80(a5)
.loc 1 98 5 is_stmt 1
.loc 1 98 39 is_stmt 0
sw a4,76(a5)
.loc 1 99 5 is_stmt 1
.loc 1 99 39 is_stmt 0
sw a4,72(a5)
.loc 1 100 5 is_stmt 1
.loc 1 100 39 is_stmt 0
sw a4,68(a5)
.loc 1 101 5 is_stmt 1
.loc 1 101 39 is_stmt 0
sw a4,64(a5)
.loc 1 102 5 is_stmt 1
.loc 1 102 39 is_stmt 0
sw a4,52(a5)
.loc 1 103 5 is_stmt 1
.loc 1 103 39 is_stmt 0
sw a4,48(a5)
.loc 1 104 5 is_stmt 1
.loc 1 104 39 is_stmt 0
sw a4,44(a5)
.loc 1 105 5 is_stmt 1
.loc 1 105 39 is_stmt 0
sw a4,40(a5)
.loc 1 106 5 is_stmt 1
.loc 1 106 39 is_stmt 0
sw a4,36(a5)
.loc 1 108 5 is_stmt 1
.loc 1 108 39 is_stmt 0
addi a3,a3,-2040
sw a3,60(a5)
.loc 1 109 5 is_stmt 1
.loc 1 109 39 is_stmt 0
li a4,1026
sw a4,56(a5)
.loc 1 113 2 is_stmt 1
.loc 1 114 43 is_stmt 0
li a3,1
.loc 1 114 10
li a4,637534208
.loc 1 113 36
sw a2,0(a5)
.loc 1 114 2 is_stmt 1
.L2:
.loc 1 114 43 discriminator 1
.loc 1 114 10 is_stmt 0 discriminator 1
lw a5,0(a4)
.loc 1 114 43 discriminator 1
beq a5,a3,.L2
.loc 1 118 2 is_stmt 1
.loc 1 118 114 is_stmt 0
li a5,-268423168
sw zero,12(a5)
.loc 1 118 57
sw zero,28(a5)
.loc 1 119 2 is_stmt 1
.loc 1 119 112 is_stmt 0
li a2,-1
sw a2,8(a5)
.loc 1 119 56
sw a2,24(a5)
.loc 1 120 2 is_stmt 1
.loc 1 120 112 is_stmt 0
sw zero,4(a5)
.loc 1 120 56
sw zero,20(a5)
.loc 1 121 2 is_stmt 1
.loc 1 121 100 is_stmt 0
sw zero,0(a5)
.loc 1 121 50
sw zero,16(a5)
.loc 1 124 2 is_stmt 1
.loc 1 124 36 is_stmt 0
li a2,-1421869056
sw a2,12(a4)
.loc 1 127 2 is_stmt 1
.loc 1 127 56 is_stmt 0
sw zero,56(a5)
.loc 1 130 2 is_stmt 1
.loc 1 130 112 is_stmt 0
sw zero,8(a5)
.loc 1 130 56
sw zero,24(a5)
.loc 1 152 2 is_stmt 1
.loc 1 152 36 is_stmt 0
li a5,-1420754944
sw a5,12(a4)
.loc 1 156 2 is_stmt 1
.LBB12:
.LBB13:
.file 2 "../../firmware/irq_vex.h"
.loc 2 24 2
.loc 2 25 2
#APP
# 25 "../../firmware/irq_vex.h" 1
csrr a5, 3008
# 0 "" 2
.LVL0:
.loc 2 26 2
#NO_APP
.LBE13:
.LBE12:
.loc 1 157 2
.loc 1 158 2
.LBB14:
.LBB15:
.loc 2 31 2
ori a5,a5,4
.LVL1:
#APP
# 31 "../../firmware/irq_vex.h" 1
csrw 3008, a5
# 0 "" 2
.LVL2:
#NO_APP
.LBE15:
.LBE14:
.loc 1 160 2
.LBB16:
.file 3 "../../firmware/csr.h"
.loc 3 806 2
.LBB17:
.LBB18:
.file 4 "../../firmware/hw/common.h"
.loc 4 34 2
.loc 4 34 32 is_stmt 0
li a5,-268406784
.LVL3:
sw a3,-2028(a5)
.LVL4:
.LBE18:
.LBE17:
.LBE16:
.loc 1 162 1
ret
.cfi_endproc
.LFE321:
.size main, .-main
.text
.Letext0:
.file 5 "/opt/riscv/lib/gcc/riscv32-unknown-elf/12.1.0/include/stdint-gcc.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0x17c
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x5
.4byte .LASF14
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .LLRL5
.4byte 0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0x6
.4byte .LASF15
.byte 0x5
.byte 0x34
.byte 0x1b
.4byte 0x5c
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0x7
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0x8
.4byte .LASF16
.byte 0x1
.byte 0x2b
.byte 0x6
.4byte .LFB321
.4byte .LFE321-.LFB321
.byte 0x1
.byte 0x9c
.4byte 0x113
.byte 0x9
.4byte .LASF13
.byte 0x1
.byte 0x2e
.byte 0x9
.4byte 0x6a
.4byte .LLST0
.byte 0x3
.4byte 0x12d
.4byte .LBB12
.4byte .LBE12-.LBB12
.byte 0x9c
.byte 0x9
.4byte 0xb7
.byte 0xa
.4byte 0x13e
.byte 0
.byte 0x3
.4byte 0x113
.4byte .LBB14
.4byte .LBE14-.LBB14
.byte 0x9e
.byte 0x2
.4byte 0xd4
.byte 0x2
.4byte 0x120
.4byte .LLST1
.byte 0
.byte 0xb
.4byte 0x14b
.4byte .LBB16
.4byte .LBE16-.LBB16
.byte 0x1
.byte 0xa0
.byte 0x2
.byte 0x2
.4byte 0x159
.4byte .LLST2
.byte 0xc
.4byte 0x165
.4byte .LBB17
.4byte .LBE17-.LBB17
.byte 0x3
.2byte 0x326
.byte 0x2
.byte 0x2
.4byte 0x176
.4byte .LLST3
.byte 0x2
.4byte 0x16e
.4byte .LLST2
.byte 0
.byte 0
.byte 0
.byte 0xd
.4byte .LASF11
.byte 0x2
.byte 0x1d
.byte 0x14
.byte 0x3
.4byte 0x12d
.byte 0xe
.4byte .LASF13
.byte 0x2
.byte 0x1d
.byte 0x2d
.4byte 0x71
.byte 0
.byte 0xf
.4byte .LASF17
.byte 0x2
.byte 0x16
.byte 0x1c
.4byte 0x71
.byte 0x3
.4byte 0x14b
.byte 0x10
.4byte .LASF13
.byte 0x2
.byte 0x18
.byte 0xf
.4byte 0x71
.byte 0
.byte 0x11
.4byte .LASF12
.byte 0x3
.2byte 0x325
.byte 0x14
.byte 0x3
.4byte 0x165
.byte 0x12
.string "v"
.byte 0x3
.2byte 0x325
.byte 0x38
.4byte 0x50
.byte 0
.byte 0x13
.4byte .LASF18
.byte 0x4
.byte 0x20
.byte 0x14
.byte 0x3
.byte 0x4
.string "v"
.byte 0x33
.4byte 0x5c
.byte 0x4
.string "a"
.byte 0x44
.4byte 0x5c
.byte 0
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0x5
.byte 0
.byte 0x31
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x3
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x58
.byte 0x21
.byte 0x1
.byte 0x59
.byte 0xb
.byte 0x57
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x4
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x4
.byte 0x3b
.byte 0x21
.byte 0x20
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x5
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x55
.byte 0x17
.byte 0x11
.byte 0x1
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0x6
.byte 0x16
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x7
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0x8
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x9
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0xa
.byte 0x34
.byte 0
.byte 0x31
.byte 0x13
.byte 0
.byte 0
.byte 0xb
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x58
.byte 0xb
.byte 0x59
.byte 0xb
.byte 0x57
.byte 0xb
.byte 0
.byte 0
.byte 0xc
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x58
.byte 0xb
.byte 0x59
.byte 0x5
.byte 0x57
.byte 0xb
.byte 0
.byte 0
.byte 0xd
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xe
.byte 0x5
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xf
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x49
.byte 0x13
.byte 0x20
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x10
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x11
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0x5
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x12
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0x5
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x13
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",@progbits
.4byte .Ldebug_loc3-.Ldebug_loc2
.Ldebug_loc2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.Ldebug_loc0:
.LLST0:
.byte 0x7
.4byte .LVL0
.4byte .LVL1
.byte 0x5
.byte 0x7f
.byte 0
.byte 0x34
.byte 0x21
.byte 0x9f
.byte 0x7
.4byte .LVL1
.4byte .LVL3
.byte 0x1
.byte 0x5f
.byte 0
.LLST1:
.byte 0x7
.4byte .LVL0
.4byte .LVL1
.byte 0x5
.byte 0x7f
.byte 0
.byte 0x34
.byte 0x21
.byte 0x9f
.byte 0x7
.4byte .LVL1
.4byte .LVL2
.byte 0x1
.byte 0x5f
.byte 0
.LLST2:
.byte 0x7
.4byte .LVL2
.4byte .LVL4
.byte 0x2
.byte 0x31
.byte 0x9f
.byte 0
.LLST3:
.byte 0x7
.4byte .LVL2
.4byte .LVL4
.byte 0x6
.byte 0x9e
.byte 0x4
.4byte 0xf0006814
.byte 0
.Ldebug_loc3:
.section .debug_aranges,"",@progbits
.4byte 0x1c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .LFB321
.4byte .LFE321-.LFB321
.4byte 0
.4byte 0
.section .debug_rnglists,"",@progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2
.Ldebug_ranges2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.LLRL5:
.byte 0x6
.4byte .LFB321
.4byte .LFE321
.byte 0
.Ldebug_ranges3:
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF18:
.string "csr_write_simple"
.LASF6:
.string "unsigned char"
.LASF8:
.string "long unsigned int"
.LASF7:
.string "short unsigned int"
.LASF16:
.string "main"
.LASF17:
.string "irq_getmask"
.LASF11:
.string "irq_setmask"
.LASF10:
.string "unsigned int"
.LASF14:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -O3 -ffreestanding"
.LASF12:
.string "user_irq_0_ev_enable_write"
.LASF9:
.string "long long unsigned int"
.LASF5:
.string "long long int"
.LASF13:
.string "mask"
.LASF3:
.string "short int"
.LASF15:
.string "uint32_t"
.LASF4:
.string "long int"
.LASF2:
.string "signed char"
.section .debug_line_str,"MS",@progbits,1
.LASF1:
.string "/home/ubuntu/Desktop/Final_test-main/testbench/uart"
.LASF0:
.string "counter_la_uart.c"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 13,488 | Final/Final_UART_FIFO/testbench/uart/uart.elf-uart.s | .file "uart.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/Final_test-main/testbench/uart" "uart.c"
.section .mprj,"ax",@progbits
.align 2
.globl uart_write
.type uart_write, @function
uart_write:
.LFB321:
.file 1 "uart.c"
.loc 1 7 1
.cfi_startproc
.LVL0:
.loc 1 8 5
.loc 1 8 14 is_stmt 0
li a4,805306368
.L2:
.loc 1 8 11 is_stmt 1 discriminator 1
.loc 1 8 14 is_stmt 0 discriminator 1
lw a5,8(a4)
.loc 1 8 11 discriminator 1
andi a5,a5,8
bne a5,zero,.L2
.loc 1 9 5 is_stmt 1
.loc 1 9 39 is_stmt 0
sw a0,4(a4)
.loc 1 10 1
ret
.cfi_endproc
.LFE321:
.size uart_write, .-uart_write
.align 2
.globl uart_write_char
.type uart_write_char, @function
uart_write_char:
.LFB322:
.loc 1 13 1 is_stmt 1
.cfi_startproc
.LVL1:
.loc 1 14 2
.loc 1 14 5 is_stmt 0
li a5,10
beq a0,a5,.L11
.L6:
.loc 1 18 14 discriminator 1
li a4,805306368
.L8:
.loc 1 18 11 is_stmt 1 discriminator 1
.loc 1 18 14 is_stmt 0 discriminator 1
lw a5,8(a4)
.loc 1 18 11 discriminator 1
andi a5,a5,8
bne a5,zero,.L8
.loc 1 19 5 is_stmt 1
.loc 1 19 39 is_stmt 0
sw a0,4(a4)
.loc 1 20 1
ret
.L11:
.LBB6:
.LBB7:
.loc 1 18 14
li a4,805306368
.L7:
.loc 1 18 11 is_stmt 1
.loc 1 18 14 is_stmt 0
lw a5,8(a4)
.loc 1 18 11
andi a5,a5,8
bne a5,zero,.L7
.loc 1 19 5 is_stmt 1
.loc 1 19 39 is_stmt 0
li a5,13
sw a5,4(a4)
.loc 1 20 1
j .L6
.LBE7:
.LBE6:
.cfi_endproc
.LFE322:
.size uart_write_char, .-uart_write_char
.align 2
.globl uart_write_string
.type uart_write_string, @function
uart_write_string:
.LFB323:
.loc 1 23 1 is_stmt 1
.cfi_startproc
.LVL2:
.loc 1 24 5
.loc 1 24 12
lbu a3,0(a0)
beq a3,zero,.L12
.LBB12:
.LBB13:
.loc 1 14 5 is_stmt 0
li a2,10
.LBB14:
.LBB15:
.loc 1 18 14
li a4,805306368
.loc 1 19 39
li a1,13
.L17:
.LBE15:
.LBE14:
.LBE13:
.LBE12:
.loc 1 25 9 is_stmt 1
.loc 1 25 28 is_stmt 0
addi a0,a0,1
.LVL3:
.LBB20:
.LBB18:
.loc 1 14 2 is_stmt 1
.loc 1 14 5 is_stmt 0
beq a3,a2,.L15
.L16:
.loc 1 18 11 is_stmt 1
.loc 1 18 14 is_stmt 0
lw a5,8(a4)
.loc 1 18 11
andi a5,a5,8
bne a5,zero,.L16
.loc 1 19 5 is_stmt 1
.loc 1 19 39 is_stmt 0
sw a3,4(a4)
.LVL4:
.LBE18:
.LBE20:
.loc 1 24 12 is_stmt 1
lbu a3,0(a0)
bne a3,zero,.L17
.L12:
.loc 1 26 1 is_stmt 0
ret
.LVL5:
.L15:
.LBB21:
.LBB19:
.LBB17:
.LBB16:
.loc 1 18 11 is_stmt 1
.loc 1 18 14 is_stmt 0
lw a5,8(a4)
.loc 1 18 11
andi a5,a5,8
bne a5,zero,.L15
.loc 1 19 5 is_stmt 1
.loc 1 19 39 is_stmt 0
sw a1,4(a4)
.loc 1 20 1
j .L16
.LBE16:
.LBE17:
.LBE19:
.LBE21:
.cfi_endproc
.LFE323:
.size uart_write_string, .-uart_write_string
.align 2
.globl uart_read_char
.type uart_read_char, @function
uart_read_char:
.LFB324:
.loc 1 30 1 is_stmt 1
.cfi_startproc
.loc 1 31 2
.loc 1 32 5
.loc 1 32 12 is_stmt 0
li a4,805306368
lw a5,8(a4)
.loc 1 30 1
li a0,0
.loc 1 32 44
srli a5,a5,5
.loc 1 32 7
bne a5,zero,.L25
.loc 1 32 67 discriminator 1
lw a5,8(a4)
.loc 1 32 99 discriminator 1
srli a5,a5,4
.loc 1 32 60 discriminator 1
bne a5,zero,.L25
.LVL6:
.LBB22:
.loc 1 33 26 is_stmt 1 discriminator 1
.loc 1 34 13 discriminator 1
#APP
# 34 "uart.c" 1
nop
# 0 "" 2
.loc 1 33 32 discriminator 1
.LVL7:
.loc 1 33 26 discriminator 1
#NO_APP
.LBE22:
.loc 1 36 9 discriminator 1
.loc 1 36 16 is_stmt 0 discriminator 1
lw a0,0(a4)
.loc 1 36 13 discriminator 1
andi a0,a0,0xff
.LVL8:
.L25:
.loc 1 39 5 is_stmt 1
.loc 1 40 1 is_stmt 0
ret
.cfi_endproc
.LFE324:
.size uart_read_char, .-uart_read_char
.align 2
.globl uart_read
.type uart_read, @function
uart_read:
.LFB325:
.loc 1 43 1 is_stmt 1
.cfi_startproc
.loc 1 44 5
.loc 1 45 5
.loc 1 45 12 is_stmt 0
li a4,805306368
lw a5,8(a4)
.loc 1 45 44
srli a5,a5,5
.loc 1 45 7
bne a5,zero,.L27
.loc 1 45 67 discriminator 1
lw a5,8(a4)
.loc 1 45 99 discriminator 1
srli a5,a5,4
.loc 1 45 60 discriminator 1
bne a5,zero,.L27
.LVL9:
.LBB23:
.loc 1 46 26 is_stmt 1 discriminator 1
.loc 1 47 13 discriminator 1
#APP
# 47 "uart.c" 1
nop
# 0 "" 2
.loc 1 46 32 discriminator 1
.LVL10:
.loc 1 46 26 discriminator 1
#NO_APP
.LBE23:
.loc 1 49 9 discriminator 1
.loc 1 49 16 is_stmt 0 discriminator 1
lw a0,0(a4)
.LVL11:
.L27:
.loc 1 52 5 is_stmt 1
.loc 1 53 1 is_stmt 0
ret
.cfi_endproc
.LFE325:
.size uart_read, .-uart_read
.text
.Letext0:
.file 2 "/opt/riscv/lib/gcc/riscv32-unknown-elf/12.1.0/include/stdint-gcc.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0x1b8
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0x9
.4byte .LASF16
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .LLRL6
.4byte 0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0xa
.4byte .LASF17
.byte 0x2
.byte 0x34
.byte 0x1b
.4byte 0x5c
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0xb
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0x2
.4byte .LASF11
.byte 0x2a
.byte 0x2f
.4byte 0x6a
.4byte .LFB325
.4byte .LFE325-.LFB325
.byte 0x1
.byte 0x9c
.4byte 0xb5
.byte 0x3
.string "num"
.byte 0x2c
.byte 0x9
.4byte 0x6a
.byte 0x1
.byte 0x5a
.byte 0x4
.4byte .LBB23
.4byte .LBE23-.LBB23
.byte 0x5
.string "i"
.byte 0x2e
.4byte 0x6a
.4byte .LLST5
.byte 0
.byte 0
.byte 0x2
.4byte .LASF12
.byte 0x1d
.byte 0x30
.4byte 0xf2
.4byte .LFB324
.4byte .LFE324-.LFB324
.byte 0x1
.byte 0x9c
.4byte 0xf2
.byte 0x3
.string "num"
.byte 0x1f
.byte 0x7
.4byte 0xf2
.byte 0x1
.byte 0x5a
.byte 0x4
.4byte .LBB22
.4byte .LBE22-.LBB22
.byte 0x5
.string "i"
.byte 0x21
.4byte 0x6a
.4byte .LLST4
.byte 0
.byte 0
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF13
.byte 0xc
.4byte 0xf2
.byte 0x6
.4byte .LASF14
.byte 0x16
.4byte .LFB323
.4byte .LFE323-.LFB323
.byte 0x1
.byte 0x9c
.4byte 0x14f
.byte 0xd
.string "s"
.byte 0x1
.byte 0x16
.byte 0x4e
.4byte 0x14f
.4byte .LLST0
.byte 0x7
.4byte 0x155
.4byte .LBB12
.4byte .LLRL1
.byte 0x19
.byte 0x9
.byte 0xe
.4byte 0x162
.4byte .LLST2
.byte 0x7
.4byte 0x155
.4byte .LBB14
.4byte .LLRL3
.byte 0xf
.byte 0x3
.byte 0x8
.4byte 0x162
.byte 0
.byte 0
.byte 0
.byte 0xf
.byte 0x4
.4byte 0xf9
.byte 0x10
.4byte .LASF18
.byte 0x1
.byte 0xc
.byte 0x30
.byte 0x1
.4byte 0x16d
.byte 0x11
.string "c"
.byte 0x1
.byte 0xc
.byte 0x45
.4byte 0xf2
.byte 0
.byte 0x6
.4byte .LASF15
.byte 0x6
.4byte .LFB321
.4byte .LFE321-.LFB321
.byte 0x1
.byte 0x9c
.4byte 0x18e
.byte 0x12
.string "n"
.byte 0x1
.byte 0x6
.byte 0x3f
.4byte 0x6a
.byte 0x1
.byte 0x5a
.byte 0
.byte 0x13
.4byte 0x155
.4byte .LFB322
.4byte .LFE322-.LFB322
.byte 0x1
.byte 0x9c
.byte 0x14
.4byte 0x162
.byte 0x1
.byte 0x5a
.byte 0x15
.4byte 0x155
.4byte .LBB6
.4byte .LBE6-.LBB6
.byte 0x1
.byte 0xf
.byte 0x3
.byte 0x8
.4byte 0x162
.byte 0
.byte 0
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x3
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x4
.byte 0xb
.byte 0x1
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0
.byte 0
.byte 0x5
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x11
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x6
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x30
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x7
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x52
.byte 0x1
.byte 0x55
.byte 0x17
.byte 0x58
.byte 0x21
.byte 0x1
.byte 0x59
.byte 0xb
.byte 0x57
.byte 0xb
.byte 0
.byte 0
.byte 0x8
.byte 0x5
.byte 0
.byte 0x31
.byte 0x13
.byte 0
.byte 0
.byte 0x9
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x55
.byte 0x17
.byte 0x11
.byte 0x1
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0xa
.byte 0x16
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xb
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0xc
.byte 0x26
.byte 0
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xd
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0xe
.byte 0x5
.byte 0
.byte 0x31
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0xf
.byte 0xf
.byte 0
.byte 0xb
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x10
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x11
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x12
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x13
.byte 0x2e
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0
.byte 0
.byte 0x14
.byte 0x5
.byte 0
.byte 0x31
.byte 0x13
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0x15
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x58
.byte 0xb
.byte 0x59
.byte 0xb
.byte 0x57
.byte 0xb
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",@progbits
.4byte .Ldebug_loc3-.Ldebug_loc2
.Ldebug_loc2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.Ldebug_loc0:
.LLST5:
.byte 0x7
.4byte .LVL9
.4byte .LVL10
.byte 0x2
.byte 0x30
.byte 0x9f
.byte 0x7
.4byte .LVL10
.4byte .LVL11
.byte 0x2
.byte 0x31
.byte 0x9f
.byte 0
.LLST4:
.byte 0x7
.4byte .LVL6
.4byte .LVL7
.byte 0x2
.byte 0x30
.byte 0x9f
.byte 0x7
.4byte .LVL7
.4byte .LVL8
.byte 0x2
.byte 0x31
.byte 0x9f
.byte 0
.LLST0:
.byte 0x7
.4byte .LVL2
.4byte .LVL3
.byte 0x1
.byte 0x5a
.byte 0x7
.4byte .LVL3
.4byte .LFE323
.byte 0x1
.byte 0x5a
.byte 0
.LLST2:
.byte 0x7
.4byte .LVL3
.4byte .LVL4
.byte 0x1
.byte 0x5d
.byte 0x7
.4byte .LVL5
.4byte .LFE323
.byte 0x1
.byte 0x5d
.byte 0
.Ldebug_loc3:
.section .debug_aranges,"",@progbits
.4byte 0x3c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .LFB321
.4byte .LFE321-.LFB321
.4byte .LFB322
.4byte .LFE322-.LFB322
.4byte .LFB323
.4byte .LFE323-.LFB323
.4byte .LFB324
.4byte .LFE324-.LFB324
.4byte .LFB325
.4byte .LFE325-.LFB325
.4byte 0
.4byte 0
.section .debug_rnglists,"",@progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2
.Ldebug_ranges2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.LLRL1:
.byte 0x6
.4byte .LBB12
.4byte .LBE12
.byte 0x6
.4byte .LBB20
.4byte .LBE20
.byte 0x6
.4byte .LBB21
.4byte .LBE21
.byte 0
.LLRL3:
.byte 0x6
.4byte .LBB14
.4byte .LBE14
.byte 0x6
.4byte .LBB17
.4byte .LBE17
.byte 0
.LLRL6:
.byte 0x6
.4byte .LFB321
.4byte .LFE321
.byte 0x6
.4byte .LFB322
.4byte .LFE322
.byte 0x6
.4byte .LFB323
.4byte .LFE323
.byte 0x6
.4byte .LFB324
.4byte .LFE324
.byte 0x6
.4byte .LFB325
.4byte .LFE325
.byte 0
.Ldebug_ranges3:
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF15:
.string "uart_write"
.LASF11:
.string "uart_read"
.LASF6:
.string "unsigned char"
.LASF14:
.string "uart_write_string"
.LASF8:
.string "long unsigned int"
.LASF7:
.string "short unsigned int"
.LASF10:
.string "unsigned int"
.LASF12:
.string "uart_read_char"
.LASF16:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -O3 -ffreestanding"
.LASF9:
.string "long long unsigned int"
.LASF18:
.string "uart_write_char"
.LASF5:
.string "long long int"
.LASF13:
.string "char"
.LASF3:
.string "short int"
.LASF17:
.string "uint32_t"
.LASF4:
.string "long int"
.LASF2:
.string "signed char"
.section .debug_line_str,"MS",@progbits,1
.LASF1:
.string "/home/ubuntu/Desktop/Final_test-main/testbench/uart"
.LASF0:
.string "uart.c"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 10,685 | Final/Final_UART_FIFO/testbench/uart/uart.elf-isr.s | .file "isr.c"
.option nopic
.attribute arch, "rv32i2p0"
.attribute unaligned_access, 0
.attribute stack_align, 16
.text
.Ltext0:
.cfi_sections .debug_frame
.file 0 "/home/ubuntu/Desktop/Final_test-main/testbench/uart" "../../firmware/isr.c"
.align 2
.globl isr
.type isr, @function
isr:
.LFB321:
.file 1 "../../firmware/isr.c"
.loc 1 24 1
.cfi_startproc
.loc 1 32 5
.LBB12:
.LBB13:
.file 2 "../../firmware/irq_vex.h"
.loc 2 36 2
.loc 2 37 2
#APP
# 37 "../../firmware/irq_vex.h" 1
csrr a4, 4032
# 0 "" 2
.LVL0:
.loc 2 38 2
#NO_APP
.LBE13:
.LBE12:
.LBB14:
.LBB15:
.loc 2 24 2
.loc 2 25 2
#APP
# 25 "../../firmware/irq_vex.h" 1
csrr a5, 3008
# 0 "" 2
.LVL1:
.loc 2 26 2
#NO_APP
.LBE15:
.LBE14:
.loc 1 33 5
.loc 1 35 5
.loc 1 32 14 is_stmt 0
and a5,a5,a4
.LVL2:
.loc 1 35 15
andi a5,a5,4
.LVL3:
.loc 1 35 8
bne a5,zero,.L7
ret
.L7:
.loc 1 36 9 is_stmt 1
.LVL4:
.LBB16:
.file 3 "../../firmware/csr.h"
.loc 3 779 2
.LBB17:
.LBB18:
.file 4 "../../firmware/hw/common.h"
.loc 4 34 2
.LBE18:
.LBE17:
.LBE16:
.loc 1 24 1 is_stmt 0
addi sp,sp,-16
.cfi_def_cfa_offset 16
sw ra,12(sp)
.cfi_offset 1, -4
.LBB21:
.LBB20:
.LBB19:
.loc 4 34 32
li a5,-268406784
li a4,1
sw a4,-2032(a5)
.LVL5:
.LBE19:
.LBE20:
.LBE21:
.loc 1 37 9 is_stmt 1
.loc 1 37 15 is_stmt 0
call uart_read
.LVL6:
.loc 1 38 9 is_stmt 1
.loc 1 45 1 is_stmt 0
lw ra,12(sp)
.cfi_restore 1
addi sp,sp,16
.cfi_def_cfa_offset 0
.loc 1 38 9
tail uart_write
.LVL7:
.cfi_endproc
.LFE321:
.size isr, .-isr
.globl counter
.section .sdata,"aw"
.align 2
.type counter, @object
.size counter, 4
counter:
.word -65536
.text
.Letext0:
.file 5 "/opt/riscv/lib/gcc/riscv32-unknown-elf/12.1.0/include/stdint-gcc.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
.4byte 0x1c8
.2byte 0x5
.byte 0x1
.byte 0x4
.4byte .Ldebug_abbrev0
.byte 0xa
.4byte .LASF18
.byte 0x1d
.4byte .LASF0
.4byte .LASF1
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte .Ldebug_line0
.byte 0x1
.byte 0x1
.byte 0x6
.4byte .LASF2
.byte 0x1
.byte 0x2
.byte 0x5
.4byte .LASF3
.byte 0x1
.byte 0x4
.byte 0x5
.4byte .LASF4
.byte 0x1
.byte 0x8
.byte 0x5
.4byte .LASF5
.byte 0x1
.byte 0x1
.byte 0x8
.4byte .LASF6
.byte 0x1
.byte 0x2
.byte 0x7
.4byte .LASF7
.byte 0xb
.4byte .LASF19
.byte 0x5
.byte 0x34
.byte 0x1b
.4byte 0x5c
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF8
.byte 0x1
.byte 0x8
.byte 0x7
.4byte .LASF9
.byte 0xc
.byte 0x4
.byte 0x5
.string "int"
.byte 0x1
.byte 0x4
.byte 0x7
.4byte .LASF10
.byte 0xd
.4byte .LASF20
.byte 0x1
.byte 0x14
.byte 0xa
.4byte 0x50
.byte 0x5
.byte 0x3
.4byte counter
.byte 0x3
.4byte .LASF11
.byte 0xd
.4byte 0x6a
.4byte 0x9a
.byte 0x4
.byte 0
.byte 0x3
.4byte .LASF12
.byte 0xa
.4byte 0x6a
.4byte 0xaa
.byte 0x4
.byte 0
.byte 0xe
.string "isr"
.byte 0x1
.byte 0x17
.byte 0x6
.4byte .LFB321
.4byte .LFE321-.LFB321
.byte 0x1
.byte 0x9c
.4byte 0x165
.byte 0xf
.4byte .LASF13
.byte 0x1
.byte 0x20
.byte 0xe
.4byte 0x50
.4byte .LLST0
.byte 0x10
.string "buf"
.byte 0x1
.byte 0x21
.byte 0x9
.4byte 0x6a
.4byte .LLST1
.byte 0x5
.4byte 0x165
.4byte .LBB12
.4byte .LBE12-.LBB12
.byte 0x15
.4byte 0xf8
.byte 0x6
.4byte 0x173
.byte 0
.byte 0x5
.4byte 0x17e
.4byte .LBB14
.4byte .LBE14-.LBB14
.byte 0x25
.4byte 0x110
.byte 0x6
.4byte 0x18c
.byte 0
.byte 0x11
.4byte 0x197
.4byte .LBB16
.4byte .LLRL2
.byte 0x1
.byte 0x24
.byte 0x9
.4byte 0x152
.byte 0x2
.4byte 0x1a5
.4byte .LLST3
.byte 0x12
.4byte 0x1b1
.4byte .LBB17
.4byte .LLRL2
.byte 0x3
.2byte 0x30b
.byte 0x2
.byte 0x2
.4byte 0x1c2
.4byte .LLST4
.byte 0x2
.4byte 0x1ba
.4byte .LLST3
.byte 0
.byte 0
.byte 0x13
.4byte .LVL6
.4byte 0x9a
.byte 0x14
.4byte .LVL7
.4byte 0x8a
.byte 0
.byte 0x7
.4byte .LASF14
.byte 0x22
.4byte 0x71
.4byte 0x17e
.byte 0x8
.4byte .LASF16
.byte 0x24
.4byte 0x71
.byte 0
.byte 0x7
.4byte .LASF15
.byte 0x16
.4byte 0x71
.4byte 0x197
.byte 0x8
.4byte .LASF17
.byte 0x18
.4byte 0x71
.byte 0
.byte 0x15
.4byte .LASF21
.byte 0x3
.2byte 0x30a
.byte 0x14
.byte 0x3
.4byte 0x1b1
.byte 0x16
.string "v"
.byte 0x3
.2byte 0x30a
.byte 0x39
.4byte 0x50
.byte 0
.byte 0x17
.4byte .LASF22
.byte 0x4
.byte 0x20
.byte 0x14
.byte 0x3
.byte 0x9
.string "v"
.byte 0x33
.4byte 0x5c
.byte 0x9
.string "a"
.byte 0x44
.4byte 0x5c
.byte 0
.byte 0
.section .debug_abbrev,"",@progbits
.Ldebug_abbrev0:
.byte 0x1
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0xe
.byte 0
.byte 0
.byte 0x2
.byte 0x5
.byte 0
.byte 0x31
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x3
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x1
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0xc
.byte 0x49
.byte 0x13
.byte 0x3c
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x4
.byte 0x18
.byte 0
.byte 0
.byte 0
.byte 0x5
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x58
.byte 0x21
.byte 0x1
.byte 0x59
.byte 0x21
.byte 0x20
.byte 0x57
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x6
.byte 0x34
.byte 0
.byte 0x31
.byte 0x13
.byte 0
.byte 0
.byte 0x7
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x2
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0x1c
.byte 0x27
.byte 0x19
.byte 0x49
.byte 0x13
.byte 0x20
.byte 0x21
.byte 0x3
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x8
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0x21
.byte 0x2
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0x21
.byte 0xf
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x9
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0x21
.byte 0x4
.byte 0x3b
.byte 0x21
.byte 0x20
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xa
.byte 0x11
.byte 0x1
.byte 0x25
.byte 0xe
.byte 0x13
.byte 0xb
.byte 0x3
.byte 0x1f
.byte 0x1b
.byte 0x1f
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x10
.byte 0x17
.byte 0
.byte 0
.byte 0xb
.byte 0x16
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0xc
.byte 0x24
.byte 0
.byte 0xb
.byte 0xb
.byte 0x3e
.byte 0xb
.byte 0x3
.byte 0x8
.byte 0
.byte 0
.byte 0xd
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x3f
.byte 0x19
.byte 0x2
.byte 0x18
.byte 0
.byte 0
.byte 0xe
.byte 0x2e
.byte 0x1
.byte 0x3f
.byte 0x19
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x11
.byte 0x1
.byte 0x12
.byte 0x6
.byte 0x40
.byte 0x18
.byte 0x7a
.byte 0x19
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0xf
.byte 0x34
.byte 0
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x10
.byte 0x34
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0x2
.byte 0x17
.byte 0
.byte 0
.byte 0x11
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x52
.byte 0x1
.byte 0x55
.byte 0x17
.byte 0x58
.byte 0xb
.byte 0x59
.byte 0xb
.byte 0x57
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x12
.byte 0x1d
.byte 0x1
.byte 0x31
.byte 0x13
.byte 0x52
.byte 0x1
.byte 0x55
.byte 0x17
.byte 0x58
.byte 0xb
.byte 0x59
.byte 0x5
.byte 0x57
.byte 0xb
.byte 0
.byte 0
.byte 0x13
.byte 0x48
.byte 0
.byte 0x7d
.byte 0x1
.byte 0x7f
.byte 0x13
.byte 0
.byte 0
.byte 0x14
.byte 0x48
.byte 0
.byte 0x7d
.byte 0x1
.byte 0x82,0x1
.byte 0x19
.byte 0x7f
.byte 0x13
.byte 0
.byte 0
.byte 0x15
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0x5
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0x1
.byte 0x13
.byte 0
.byte 0
.byte 0x16
.byte 0x5
.byte 0
.byte 0x3
.byte 0x8
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0x5
.byte 0x39
.byte 0xb
.byte 0x49
.byte 0x13
.byte 0
.byte 0
.byte 0x17
.byte 0x2e
.byte 0x1
.byte 0x3
.byte 0xe
.byte 0x3a
.byte 0xb
.byte 0x3b
.byte 0xb
.byte 0x39
.byte 0xb
.byte 0x27
.byte 0x19
.byte 0x20
.byte 0xb
.byte 0
.byte 0
.byte 0
.section .debug_loclists,"",@progbits
.4byte .Ldebug_loc3-.Ldebug_loc2
.Ldebug_loc2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.Ldebug_loc0:
.LLST0:
.byte 0x7
.4byte .LVL1
.4byte .LVL2
.byte 0x6
.byte 0x7f
.byte 0
.byte 0x7e
.byte 0
.byte 0x1a
.byte 0x9f
.byte 0x7
.4byte .LVL2
.4byte .LVL3
.byte 0x1
.byte 0x5f
.byte 0
.LLST1:
.byte 0x7
.4byte .LVL6
.4byte .LVL7-1
.byte 0x1
.byte 0x5a
.byte 0
.LLST3:
.byte 0x7
.4byte .LVL4
.4byte .LVL5
.byte 0x2
.byte 0x31
.byte 0x9f
.byte 0
.LLST4:
.byte 0x7
.4byte .LVL4
.4byte .LVL5
.byte 0x6
.byte 0x9e
.byte 0x4
.4byte 0xf0006810
.byte 0
.Ldebug_loc3:
.section .debug_aranges,"",@progbits
.4byte 0x1c
.2byte 0x2
.4byte .Ldebug_info0
.byte 0x4
.byte 0
.2byte 0
.2byte 0
.4byte .Ltext0
.4byte .Letext0-.Ltext0
.4byte 0
.4byte 0
.section .debug_rnglists,"",@progbits
.Ldebug_ranges0:
.4byte .Ldebug_ranges3-.Ldebug_ranges2
.Ldebug_ranges2:
.2byte 0x5
.byte 0x4
.byte 0
.4byte 0
.LLRL2:
.byte 0x6
.4byte .LBB16
.4byte .LBE16
.byte 0x6
.4byte .LBB21
.4byte .LBE21
.byte 0
.Ldebug_ranges3:
.section .debug_line,"",@progbits
.Ldebug_line0:
.section .debug_str,"MS",@progbits,1
.LASF21:
.string "user_irq_0_ev_pending_write"
.LASF11:
.string "uart_write"
.LASF22:
.string "csr_write_simple"
.LASF12:
.string "uart_read"
.LASF20:
.string "counter"
.LASF6:
.string "unsigned char"
.LASF8:
.string "long unsigned int"
.LASF7:
.string "short unsigned int"
.LASF15:
.string "irq_getmask"
.LASF10:
.string "unsigned int"
.LASF18:
.string "GNU C17 12.1.0 -mabi=ilp32 -mtune=rocket -misa-spec=2.2 -march=rv32i -g -O3 -ffreestanding"
.LASF9:
.string "long long unsigned int"
.LASF5:
.string "long long int"
.LASF17:
.string "mask"
.LASF13:
.string "irqs"
.LASF3:
.string "short int"
.LASF19:
.string "uint32_t"
.LASF4:
.string "long int"
.LASF16:
.string "pending"
.LASF2:
.string "signed char"
.LASF14:
.string "irq_pending"
.section .debug_line_str,"MS",@progbits,1
.LASF0:
.string "../../firmware/isr.c"
.LASF1:
.string "/home/ubuntu/Desktop/Final_test-main/testbench/uart"
.ident "GCC: (g1ea978e3066) 12.1.0"
|
fff1214/SoC-Final | 1,619 | Final/Final_UART_FIFO/testbench/uart/uart.elf-crt0_vex.s | # 0 "../../firmware/crt0_vex.S"
# 1 "/home/ubuntu/Desktop/Final_test-main/testbench/uart//"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "../../firmware/crt0_vex.S"
.global main
.global isr
.global _start
_start:
j crt_init
nop
nop
nop
nop
nop
nop
nop
.global trap_entry
trap_entry:
sw x1, - 1*4(sp)
sw x5, - 2*4(sp)
sw x6, - 3*4(sp)
sw x7, - 4*4(sp)
sw x10, - 5*4(sp)
sw x11, - 6*4(sp)
sw x12, - 7*4(sp)
sw x13, - 8*4(sp)
sw x14, - 9*4(sp)
sw x15, -10*4(sp)
sw x16, -11*4(sp)
sw x17, -12*4(sp)
sw x28, -13*4(sp)
sw x29, -14*4(sp)
sw x30, -15*4(sp)
sw x31, -16*4(sp)
addi sp,sp,-16*4
call isr
lw x1 , 15*4(sp)
lw x5, 14*4(sp)
lw x6, 13*4(sp)
lw x7, 12*4(sp)
lw x10, 11*4(sp)
lw x11, 10*4(sp)
lw x12, 9*4(sp)
lw x13, 8*4(sp)
lw x14, 7*4(sp)
lw x15, 6*4(sp)
lw x16, 5*4(sp)
lw x17, 4*4(sp)
lw x28, 3*4(sp)
lw x29, 2*4(sp)
lw x30, 1*4(sp)
lw x31, 0*4(sp)
addi sp,sp,16*4
mret
.text
crt_init:
la sp, _fstack
la a0, trap_entry
csrw mtvec, a0
sram_init:
la a0, _fsram
la a1, _esram
la a2, _esram_rom
sram_loop:
beq a0,a1,sram_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j sram_loop
sram_done:
data_init:
la a0, _fdata
la a1, _edata
la a2, _fdata_rom
data_loop:
beq a0,a1,data_done
lw a3,0(a2)
sw a3,0(a0)
add a0,a0,4
add a2,a2,4
j data_loop
data_done:
bss_init:
la a0, _fbss
la a1, _ebss
bss_loop:
beq a0,a1,bss_done
sw zero,0(a0)
add a0,a0,4
j bss_loop
bss_done:
li a0, 0x880
csrw mie,a0
csrrs a0, mstatus, 0x8
call main
infinit_loop:
j infinit_loop
|
fhuko1357/spectre | 8,619 | src/asm/keccakf1600_x86-64-elf.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.type __KeccakF1600,@function
.align 32
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.align 32
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz .Loop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.size __KeccakF1600,.-__KeccakF1600
.globl KeccakF1600
.type KeccakF1600,@function
.align 32
KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
leaq 248(%rsp),%r11
.cfi_def_cfa %r11,8
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.size KeccakF1600,.-KeccakF1600
.globl SHA3_absorb
.type SHA3_absorb,@function
.align 32
SHA3_absorb:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $232,%rsp
.cfi_adjust_cfa_offset 232
movq %rsi,%r9
leaq 100(%rsp),%rsi
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
movq %rcx,216-100(%rsi)
.Loop_absorb:
cmpq %rcx,%rdx
jc .Ldone_absorb
shrq $3,%rcx
leaq -100(%rdi),%r8
.Lblock_absorb:
movq (%r9),%rax
leaq 8(%r9),%r9
xorq (%r8),%rax
leaq 8(%r8),%r8
subq $8,%rdx
movq %rax,-8(%r8)
subq $1,%rcx
jnz .Lblock_absorb
movq %r9,200-100(%rsi)
movq %rdx,208-100(%rsi)
call __KeccakF1600
movq 200-100(%rsi),%r9
movq 208-100(%rsi),%rdx
movq 216-100(%rsi),%rcx
jmp .Loop_absorb
.align 32
.Ldone_absorb:
movq %rdx,%rax
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq 280(%rsp),%r11
.cfi_def_cfa %r11,8
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.size SHA3_absorb,.-SHA3_absorb
.globl SHA3_squeeze
.type SHA3_squeeze,@function
.align 32
SHA3_squeeze:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-16
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-24
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-32
subq $32,%rsp
.cfi_adjust_cfa_offset 32
shrq $3,%rcx
movq %rdi,%r8
movq %rsi,%r12
movq %rdx,%r13
movq %rcx,%r14
jmp .Loop_squeeze
.align 32
.Loop_squeeze:
cmpq $8,%r13
jb .Ltail_squeeze
movq (%r8),%rax
leaq 8(%r8),%r8
movq %rax,(%r12)
leaq 8(%r12),%r12
subq $8,%r13
jz .Ldone_squeeze
subq $1,%rcx
jnz .Loop_squeeze
movq %rdi,%rcx
call KeccakF1600
movq %rdi,%r8
movq %r14,%rcx
jmp .Loop_squeeze
.Ltail_squeeze:
movq %r8,%rsi
movq %r12,%rdi
movq %r13,%rcx
.byte 0xf3,0xa4
.Ldone_squeeze:
movq 32(%rsp),%r14
movq 40(%rsp),%r13
movq 48(%rsp),%r12
addq $56,%rsp
.cfi_adjust_cfa_offset -56
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.byte 0xf3,0xc3
.cfi_endproc
.size SHA3_squeeze,.-SHA3_squeeze
.align 256
.quad 0,0,0,0,0,0,0,0
.type iotas,@object
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.size iotas,.-iotas
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.section .note.gnu.property,"a",@note
.long 4,2f-1f,5
.byte 0x47,0x4E,0x55,0
1: .long 0xc0000002,4,3
.align 8
2:
|
fhuko1357/spectre | 10,572 | src/asm/keccakf1600_x86-64-win64.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.def __KeccakF1600; .scl 3; .type 32; .endef
.p2align 5
__KeccakF1600:
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.p2align 5
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz .Loop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.globl KeccakF1600
.def KeccakF1600; .scl 2; .type 32; .endef
.p2align 5
KeccakF1600:
.byte 0xf3,0x0f,0x1e,0xfa
movq %rdi,8(%rsp)
movq %rsi,16(%rsp)
movq %rsp,%r11
.LSEH_begin_KeccakF1600:
movq %rcx,%rdi
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
leaq 100(%rdi),%rdi
subq $200,%rsp
.LSEH_body_KeccakF1600:
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
leaq 248(%rsp),%r11
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.LSEH_epilogue_KeccakF1600:
mov 8(%r11),%rdi
mov 16(%r11),%rsi
.byte 0xf3,0xc3
.LSEH_end_KeccakF1600:
.globl SHA3_absorb
.def SHA3_absorb; .scl 2; .type 32; .endef
.p2align 5
SHA3_absorb:
.byte 0xf3,0x0f,0x1e,0xfa
movq %rdi,8(%rsp)
movq %rsi,16(%rsp)
movq %rsp,%r11
.LSEH_begin_SHA3_absorb:
movq %rcx,%rdi
movq %rdx,%rsi
movq %r8,%rdx
movq %r9,%rcx
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
leaq 100(%rdi),%rdi
subq $232,%rsp
.LSEH_body_SHA3_absorb:
movq %rsi,%r9
leaq 100(%rsp),%rsi
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
movq %rcx,216-100(%rsi)
.Loop_absorb:
cmpq %rcx,%rdx
jc .Ldone_absorb
shrq $3,%rcx
leaq -100(%rdi),%r8
.Lblock_absorb:
movq (%r9),%rax
leaq 8(%r9),%r9
xorq (%r8),%rax
leaq 8(%r8),%r8
subq $8,%rdx
movq %rax,-8(%r8)
subq $1,%rcx
jnz .Lblock_absorb
movq %r9,200-100(%rsi)
movq %rdx,208-100(%rsi)
call __KeccakF1600
movq 200-100(%rsi),%r9
movq 208-100(%rsi),%rdx
movq 216-100(%rsi),%rcx
jmp .Loop_absorb
.p2align 5
.Ldone_absorb:
movq %rdx,%rax
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq 280(%rsp),%r11
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.LSEH_epilogue_SHA3_absorb:
mov 8(%r11),%rdi
mov 16(%r11),%rsi
.byte 0xf3,0xc3
.LSEH_end_SHA3_absorb:
.globl SHA3_squeeze
.def SHA3_squeeze; .scl 2; .type 32; .endef
.p2align 5
SHA3_squeeze:
.byte 0xf3,0x0f,0x1e,0xfa
movq %rdi,8(%rsp)
movq %rsi,16(%rsp)
movq %rsp,%r11
.LSEH_begin_SHA3_squeeze:
movq %rcx,%rdi
movq %rdx,%rsi
movq %r8,%rdx
movq %r9,%rcx
pushq %r12
pushq %r13
pushq %r14
subq $32,%rsp
.LSEH_body_SHA3_squeeze:
shrq $3,%rcx
movq %rdi,%r8
movq %rsi,%r12
movq %rdx,%r13
movq %rcx,%r14
jmp .Loop_squeeze
.p2align 5
.Loop_squeeze:
cmpq $8,%r13
jb .Ltail_squeeze
movq (%r8),%rax
leaq 8(%r8),%r8
movq %rax,(%r12)
leaq 8(%r12),%r12
subq $8,%r13
jz .Ldone_squeeze
subq $1,%rcx
jnz .Loop_squeeze
movq %rdi,%rcx
call KeccakF1600
movq %rdi,%r8
movq %r14,%rcx
jmp .Loop_squeeze
.Ltail_squeeze:
movq %r8,%rsi
movq %r12,%rdi
movq %r13,%rcx
.byte 0xf3,0xa4
.Ldone_squeeze:
movq 32(%rsp),%r14
movq 40(%rsp),%r13
movq 48(%rsp),%r12
addq $56,%rsp
.LSEH_epilogue_SHA3_squeeze:
mov 8(%rsp),%rdi
mov 16(%rsp),%rsi
.byte 0xf3,0xc3
.LSEH_end_SHA3_squeeze:
.p2align 8
.quad 0,0,0,0,0,0,0,0
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.section .pdata
.p2align 2
.rva .LSEH_begin_KeccakF1600
.rva .LSEH_body_KeccakF1600
.rva .LSEH_info_KeccakF1600_prologue
.rva .LSEH_body_KeccakF1600
.rva .LSEH_epilogue_KeccakF1600
.rva .LSEH_info_KeccakF1600_body
.rva .LSEH_epilogue_KeccakF1600
.rva .LSEH_end_KeccakF1600
.rva .LSEH_info_KeccakF1600_epilogue
.rva .LSEH_begin_SHA3_absorb
.rva .LSEH_body_SHA3_absorb
.rva .LSEH_info_SHA3_absorb_prologue
.rva .LSEH_body_SHA3_absorb
.rva .LSEH_epilogue_SHA3_absorb
.rva .LSEH_info_SHA3_absorb_body
.rva .LSEH_epilogue_SHA3_absorb
.rva .LSEH_end_SHA3_absorb
.rva .LSEH_info_SHA3_absorb_epilogue
.rva .LSEH_begin_SHA3_squeeze
.rva .LSEH_body_SHA3_squeeze
.rva .LSEH_info_SHA3_squeeze_prologue
.rva .LSEH_body_SHA3_squeeze
.rva .LSEH_epilogue_SHA3_squeeze
.rva .LSEH_info_SHA3_squeeze_body
.rva .LSEH_epilogue_SHA3_squeeze
.rva .LSEH_end_SHA3_squeeze
.rva .LSEH_info_SHA3_squeeze_epilogue
.section .xdata
.p2align 3
.LSEH_info_KeccakF1600_prologue:
.byte 1,0,5,0x0b
.byte 0,0x74,1,0
.byte 0,0x64,2,0
.byte 0,0xb3
.byte 0,0
.long 0,0
.LSEH_info_KeccakF1600_body:
.byte 1,0,18,0
.byte 0x00,0xf4,0x19,0x00
.byte 0x00,0xe4,0x1a,0x00
.byte 0x00,0xd4,0x1b,0x00
.byte 0x00,0xc4,0x1c,0x00
.byte 0x00,0x54,0x1d,0x00
.byte 0x00,0x34,0x1e,0x00
.byte 0x00,0x74,0x20,0x00
.byte 0x00,0x64,0x21,0x00
.byte 0x00,0x01,0x1f,0x00
.byte 0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_KeccakF1600_epilogue:
.byte 1,0,5,11
.byte 0x00,0x74,0x01,0x00
.byte 0x00,0x64,0x02,0x00
.byte 0x00,0xb3
.byte 0x00,0x00,0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_SHA3_absorb_prologue:
.byte 1,0,5,0x0b
.byte 0,0x74,1,0
.byte 0,0x64,2,0
.byte 0,0xb3
.byte 0,0
.long 0,0
.LSEH_info_SHA3_absorb_body:
.byte 1,0,18,0
.byte 0x00,0xf4,0x1d,0x00
.byte 0x00,0xe4,0x1e,0x00
.byte 0x00,0xd4,0x1f,0x00
.byte 0x00,0xc4,0x20,0x00
.byte 0x00,0x54,0x21,0x00
.byte 0x00,0x34,0x22,0x00
.byte 0x00,0x74,0x24,0x00
.byte 0x00,0x64,0x25,0x00
.byte 0x00,0x01,0x23,0x00
.byte 0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_SHA3_absorb_epilogue:
.byte 1,0,5,11
.byte 0x00,0x74,0x01,0x00
.byte 0x00,0x64,0x02,0x00
.byte 0x00,0xb3
.byte 0x00,0x00,0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_SHA3_squeeze_prologue:
.byte 1,0,5,0x0b
.byte 0,0x74,1,0
.byte 0,0x64,2,0
.byte 0,0xb3
.byte 0,0
.long 0,0
.LSEH_info_SHA3_squeeze_body:
.byte 1,0,11,0
.byte 0x00,0xe4,0x04,0x00
.byte 0x00,0xd4,0x05,0x00
.byte 0x00,0xc4,0x06,0x00
.byte 0x00,0x74,0x08,0x00
.byte 0x00,0x64,0x09,0x00
.byte 0x00,0x62
.byte 0x00,0x00,0x00,0x00,0x00,0x00
.LSEH_info_SHA3_squeeze_epilogue:
.byte 1,0,4,0
.byte 0x00,0x74,0x01,0x00
.byte 0x00,0x64,0x02,0x00
.byte 0x00,0x00,0x00,0x00
|
fhuko1357/spectre | 8,238 | src/asm/keccakf1600_x86-64-osx.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.p2align 5
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp L$oop
.p2align 5
L$oop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz L$oop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.cfi_endproc
.globl _KeccakF1600
.p2align 5
_KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $200,%rsp
.cfi_adjust_cfa_offset 200
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
leaq 248(%rsp),%r11
.cfi_def_cfa %r11,8
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.globl _SHA3_absorb
.p2align 5
_SHA3_absorb:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-40
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-48
pushq %r15
.cfi_adjust_cfa_offset 8
.cfi_offset %r15,-56
leaq 100(%rdi),%rdi
subq $232,%rsp
.cfi_adjust_cfa_offset 232
movq %rsi,%r9
leaq 100(%rsp),%rsi
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
movq %rcx,216-100(%rsi)
L$oop_absorb:
cmpq %rcx,%rdx
jc L$done_absorb
shrq $3,%rcx
leaq -100(%rdi),%r8
L$block_absorb:
movq (%r9),%rax
leaq 8(%r9),%r9
xorq (%r8),%rax
leaq 8(%r8),%r8
subq $8,%rdx
movq %rax,-8(%r8)
subq $1,%rcx
jnz L$block_absorb
movq %r9,200-100(%rsi)
movq %rdx,208-100(%rsi)
call __KeccakF1600
movq 200-100(%rsi),%r9
movq 208-100(%rsi),%rdx
movq 216-100(%rsi),%rcx
jmp L$oop_absorb
.p2align 5
L$done_absorb:
movq %rdx,%rax
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq 280(%rsp),%r11
.cfi_def_cfa %r11,8
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.cfi_restore %rbx
.byte 0xf3,0xc3
.cfi_endproc
.globl _SHA3_squeeze
.p2align 5
_SHA3_squeeze:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-16
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-24
pushq %r14
.cfi_adjust_cfa_offset 8
.cfi_offset %r14,-32
subq $32,%rsp
.cfi_adjust_cfa_offset 32
shrq $3,%rcx
movq %rdi,%r8
movq %rsi,%r12
movq %rdx,%r13
movq %rcx,%r14
jmp L$oop_squeeze
.p2align 5
L$oop_squeeze:
cmpq $8,%r13
jb L$tail_squeeze
movq (%r8),%rax
leaq 8(%r8),%r8
movq %rax,(%r12)
leaq 8(%r12),%r12
subq $8,%r13
jz L$done_squeeze
subq $1,%rcx
jnz L$oop_squeeze
movq %rdi,%rcx
call _KeccakF1600
movq %rdi,%r8
movq %r14,%rcx
jmp L$oop_squeeze
L$tail_squeeze:
movq %r8,%rsi
movq %r12,%rdi
movq %r13,%rcx
.byte 0xf3,0xa4
L$done_squeeze:
movq 32(%rsp),%r14
movq 40(%rsp),%r13
movq 48(%rsp),%r12
addq $56,%rsp
.cfi_adjust_cfa_offset -56
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.byte 0xf3,0xc3
.cfi_endproc
.p2align 8
.quad 0,0,0,0,0,0,0,0
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
|
fhuko1357/spectre | 10,572 | src/asm/keccakf1600_x86-64-mingw64.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.def __KeccakF1600; .scl 3; .type 32; .endef
.p2align 5
__KeccakF1600:
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.p2align 5
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76(%rdi),%rdx
xorq %r8,%rax
xorq -92(%rdi),%rbx
xorq -44(%rdi),%rcx
xorq -60(%rdi),%rax
movq %rbp,%r12
xorq -68(%rdi),%rbp
xorq %r10,%rcx
xorq -20(%rdi),%rax
xorq -36(%rdi),%rdx
xorq %r9,%rbx
xorq -28(%rdi),%rbp
xorq 36(%rdi),%rcx
xorq 20(%rdi),%rax
xorq 4(%rdi),%rdx
xorq -12(%rdi),%rbx
xorq 12(%rdi),%rbp
movq %rcx,%r13
rolq $1,%rcx
xorq %rax,%rcx
xorq %r11,%rdx
rolq $1,%rax
xorq %rdx,%rax
xorq 28(%rdi),%rbx
rolq $1,%rdx
xorq %rbx,%rdx
xorq 52(%rdi),%rbp
rolq $1,%rbx
xorq %rbp,%rbx
rolq $1,%rbp
xorq %r13,%rbp
xorq %rcx,%r9
xorq %rdx,%r10
rolq $44,%r9
xorq %rbp,%r11
xorq %rax,%r12
rolq $43,%r10
xorq %rbx,%r8
movq %r9,%r13
rolq $21,%r11
orq %r10,%r9
xorq %r8,%r9
rolq $14,%r12
xorq (%r15),%r9
leaq 8(%r15),%r15
movq %r12,%r14
andq %r11,%r12
movq %r9,-100(%rsi)
xorq %r10,%r12
notq %r10
movq %r12,-84(%rsi)
orq %r11,%r10
movq 76(%rdi),%r12
xorq %r13,%r10
movq %r10,-92(%rsi)
andq %r8,%r13
movq -28(%rdi),%r9
xorq %r14,%r13
movq -20(%rdi),%r10
movq %r13,-68(%rsi)
orq %r8,%r14
movq -76(%rdi),%r8
xorq %r11,%r14
movq 28(%rdi),%r11
movq %r14,-76(%rsi)
xorq %rbp,%r8
xorq %rdx,%r12
rolq $28,%r8
xorq %rcx,%r11
xorq %rax,%r9
rolq $61,%r12
rolq $45,%r11
xorq %rbx,%r10
rolq $20,%r9
movq %r8,%r13
orq %r12,%r8
rolq $3,%r10
xorq %r11,%r8
movq %r8,-36(%rsi)
movq %r9,%r14
andq %r13,%r9
movq -92(%rdi),%r8
xorq %r12,%r9
notq %r12
movq %r9,-28(%rsi)
orq %r11,%r12
movq -44(%rdi),%r9
xorq %r10,%r12
movq %r12,-44(%rsi)
andq %r10,%r11
movq 60(%rdi),%r12
xorq %r14,%r11
movq %r11,-52(%rsi)
orq %r10,%r14
movq 4(%rdi),%r10
xorq %r13,%r14
movq 52(%rdi),%r11
movq %r14,-60(%rsi)
xorq %rbp,%r10
xorq %rax,%r11
rolq $25,%r10
xorq %rdx,%r9
rolq $8,%r11
xorq %rbx,%r12
rolq $6,%r9
xorq %rcx,%r8
rolq $18,%r12
movq %r10,%r13
andq %r11,%r10
rolq $1,%r8
notq %r11
xorq %r9,%r10
movq %r10,-12(%rsi)
movq %r12,%r14
andq %r11,%r12
movq -12(%rdi),%r10
xorq %r13,%r12
movq %r12,-4(%rsi)
orq %r9,%r13
movq 84(%rdi),%r12
xorq %r8,%r13
movq %r13,-20(%rsi)
andq %r8,%r9
xorq %r14,%r9
movq %r9,12(%rsi)
orq %r8,%r14
movq -60(%rdi),%r9
xorq %r11,%r14
movq 36(%rdi),%r11
movq %r14,4(%rsi)
movq -68(%rdi),%r8
xorq %rcx,%r10
xorq %rdx,%r11
rolq $10,%r10
xorq %rbx,%r9
rolq $15,%r11
xorq %rbp,%r12
rolq $36,%r9
xorq %rax,%r8
rolq $56,%r12
movq %r10,%r13
orq %r11,%r10
rolq $27,%r8
notq %r11
xorq %r9,%r10
movq %r10,28(%rsi)
movq %r12,%r14
orq %r11,%r12
xorq %r13,%r12
movq %r12,36(%rsi)
andq %r9,%r13
xorq %r8,%r13
movq %r13,20(%rsi)
orq %r8,%r9
xorq %r14,%r9
movq %r9,52(%rsi)
andq %r14,%r8
xorq %r11,%r8
movq %r8,44(%rsi)
xorq -84(%rdi),%rdx
xorq -36(%rdi),%rbp
rolq $62,%rdx
xorq 68(%rdi),%rcx
rolq $55,%rbp
xorq 12(%rdi),%rax
rolq $2,%rcx
xorq 20(%rdi),%rbx
xchgq %rsi,%rdi
rolq $39,%rax
rolq $41,%rbx
movq %rdx,%r13
andq %rbp,%rdx
notq %rbp
xorq %rcx,%rdx
movq %rdx,92(%rdi)
movq %rax,%r14
andq %rbp,%rax
xorq %r13,%rax
movq %rax,60(%rdi)
orq %rcx,%r13
xorq %rbx,%r13
movq %r13,84(%rdi)
andq %rbx,%rcx
xorq %r14,%rcx
movq %rcx,76(%rdi)
orq %r14,%rbx
xorq %rbp,%rbx
movq %rbx,68(%rdi)
movq %rdx,%rbp
movq %r13,%rdx
testq $255,%r15
jnz .Loop
leaq -192(%r15),%r15
.byte 0xf3,0xc3
.globl KeccakF1600
.def KeccakF1600; .scl 2; .type 32; .endef
.p2align 5
KeccakF1600:
.byte 0xf3,0x0f,0x1e,0xfa
movq %rdi,8(%rsp)
movq %rsi,16(%rsp)
movq %rsp,%r11
.LSEH_begin_KeccakF1600:
movq %rcx,%rdi
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
leaq 100(%rdi),%rdi
subq $200,%rsp
.LSEH_body_KeccakF1600:
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
leaq 100(%rsp),%rsi
call __KeccakF1600
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq -100(%rdi),%rdi
leaq 248(%rsp),%r11
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.LSEH_epilogue_KeccakF1600:
mov 8(%r11),%rdi
mov 16(%r11),%rsi
.byte 0xf3,0xc3
.LSEH_end_KeccakF1600:
.globl SHA3_absorb
.def SHA3_absorb; .scl 2; .type 32; .endef
.p2align 5
SHA3_absorb:
.byte 0xf3,0x0f,0x1e,0xfa
movq %rdi,8(%rsp)
movq %rsi,16(%rsp)
movq %rsp,%r11
.LSEH_begin_SHA3_absorb:
movq %rcx,%rdi
movq %rdx,%rsi
movq %r8,%rdx
movq %r9,%rcx
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
leaq 100(%rdi),%rdi
subq $232,%rsp
.LSEH_body_SHA3_absorb:
movq %rsi,%r9
leaq 100(%rsp),%rsi
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq iotas(%rip),%r15
movq %rcx,216-100(%rsi)
.Loop_absorb:
cmpq %rcx,%rdx
jc .Ldone_absorb
shrq $3,%rcx
leaq -100(%rdi),%r8
.Lblock_absorb:
movq (%r9),%rax
leaq 8(%r9),%r9
xorq (%r8),%rax
leaq 8(%r8),%r8
subq $8,%rdx
movq %rax,-8(%r8)
subq $1,%rcx
jnz .Lblock_absorb
movq %r9,200-100(%rsi)
movq %rdx,208-100(%rsi)
call __KeccakF1600
movq 200-100(%rsi),%r9
movq 208-100(%rsi),%rdx
movq 216-100(%rsi),%rcx
jmp .Loop_absorb
.p2align 5
.Ldone_absorb:
movq %rdx,%rax
notq -92(%rdi)
notq -84(%rdi)
notq -36(%rdi)
notq -4(%rdi)
notq 36(%rdi)
notq 60(%rdi)
leaq 280(%rsp),%r11
movq -48(%r11),%r15
movq -40(%r11),%r14
movq -32(%r11),%r13
movq -24(%r11),%r12
movq -16(%r11),%rbp
movq -8(%r11),%rbx
leaq (%r11),%rsp
.LSEH_epilogue_SHA3_absorb:
mov 8(%r11),%rdi
mov 16(%r11),%rsi
.byte 0xf3,0xc3
.LSEH_end_SHA3_absorb:
.globl SHA3_squeeze
.def SHA3_squeeze; .scl 2; .type 32; .endef
.p2align 5
SHA3_squeeze:
.byte 0xf3,0x0f,0x1e,0xfa
movq %rdi,8(%rsp)
movq %rsi,16(%rsp)
movq %rsp,%r11
.LSEH_begin_SHA3_squeeze:
movq %rcx,%rdi
movq %rdx,%rsi
movq %r8,%rdx
movq %r9,%rcx
pushq %r12
pushq %r13
pushq %r14
subq $32,%rsp
.LSEH_body_SHA3_squeeze:
shrq $3,%rcx
movq %rdi,%r8
movq %rsi,%r12
movq %rdx,%r13
movq %rcx,%r14
jmp .Loop_squeeze
.p2align 5
.Loop_squeeze:
cmpq $8,%r13
jb .Ltail_squeeze
movq (%r8),%rax
leaq 8(%r8),%r8
movq %rax,(%r12)
leaq 8(%r12),%r12
subq $8,%r13
jz .Ldone_squeeze
subq $1,%rcx
jnz .Loop_squeeze
movq %rdi,%rcx
call KeccakF1600
movq %rdi,%r8
movq %r14,%rcx
jmp .Loop_squeeze
.Ltail_squeeze:
movq %r8,%rsi
movq %r12,%rdi
movq %r13,%rcx
.byte 0xf3,0xa4
.Ldone_squeeze:
movq 32(%rsp),%r14
movq 40(%rsp),%r13
movq 48(%rsp),%r12
addq $56,%rsp
.LSEH_epilogue_SHA3_squeeze:
mov 8(%rsp),%rdi
mov 16(%rsp),%rsi
.byte 0xf3,0xc3
.LSEH_end_SHA3_squeeze:
.p2align 8
.quad 0,0,0,0,0,0,0,0
iotas:
.quad 0x0000000000000001
.quad 0x0000000000008082
.quad 0x800000000000808a
.quad 0x8000000080008000
.quad 0x000000000000808b
.quad 0x0000000080000001
.quad 0x8000000080008081
.quad 0x8000000000008009
.quad 0x000000000000008a
.quad 0x0000000000000088
.quad 0x0000000080008009
.quad 0x000000008000000a
.quad 0x000000008000808b
.quad 0x800000000000008b
.quad 0x8000000000008089
.quad 0x8000000000008003
.quad 0x8000000000008002
.quad 0x8000000000000080
.quad 0x000000000000800a
.quad 0x800000008000000a
.quad 0x8000000080008081
.quad 0x8000000000008080
.quad 0x0000000080000001
.quad 0x8000000080008008
.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.section .pdata
.p2align 2
.rva .LSEH_begin_KeccakF1600
.rva .LSEH_body_KeccakF1600
.rva .LSEH_info_KeccakF1600_prologue
.rva .LSEH_body_KeccakF1600
.rva .LSEH_epilogue_KeccakF1600
.rva .LSEH_info_KeccakF1600_body
.rva .LSEH_epilogue_KeccakF1600
.rva .LSEH_end_KeccakF1600
.rva .LSEH_info_KeccakF1600_epilogue
.rva .LSEH_begin_SHA3_absorb
.rva .LSEH_body_SHA3_absorb
.rva .LSEH_info_SHA3_absorb_prologue
.rva .LSEH_body_SHA3_absorb
.rva .LSEH_epilogue_SHA3_absorb
.rva .LSEH_info_SHA3_absorb_body
.rva .LSEH_epilogue_SHA3_absorb
.rva .LSEH_end_SHA3_absorb
.rva .LSEH_info_SHA3_absorb_epilogue
.rva .LSEH_begin_SHA3_squeeze
.rva .LSEH_body_SHA3_squeeze
.rva .LSEH_info_SHA3_squeeze_prologue
.rva .LSEH_body_SHA3_squeeze
.rva .LSEH_epilogue_SHA3_squeeze
.rva .LSEH_info_SHA3_squeeze_body
.rva .LSEH_epilogue_SHA3_squeeze
.rva .LSEH_end_SHA3_squeeze
.rva .LSEH_info_SHA3_squeeze_epilogue
.section .xdata
.p2align 3
.LSEH_info_KeccakF1600_prologue:
.byte 1,0,5,0x0b
.byte 0,0x74,1,0
.byte 0,0x64,2,0
.byte 0,0xb3
.byte 0,0
.long 0,0
.LSEH_info_KeccakF1600_body:
.byte 1,0,18,0
.byte 0x00,0xf4,0x19,0x00
.byte 0x00,0xe4,0x1a,0x00
.byte 0x00,0xd4,0x1b,0x00
.byte 0x00,0xc4,0x1c,0x00
.byte 0x00,0x54,0x1d,0x00
.byte 0x00,0x34,0x1e,0x00
.byte 0x00,0x74,0x20,0x00
.byte 0x00,0x64,0x21,0x00
.byte 0x00,0x01,0x1f,0x00
.byte 0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_KeccakF1600_epilogue:
.byte 1,0,5,11
.byte 0x00,0x74,0x01,0x00
.byte 0x00,0x64,0x02,0x00
.byte 0x00,0xb3
.byte 0x00,0x00,0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_SHA3_absorb_prologue:
.byte 1,0,5,0x0b
.byte 0,0x74,1,0
.byte 0,0x64,2,0
.byte 0,0xb3
.byte 0,0
.long 0,0
.LSEH_info_SHA3_absorb_body:
.byte 1,0,18,0
.byte 0x00,0xf4,0x1d,0x00
.byte 0x00,0xe4,0x1e,0x00
.byte 0x00,0xd4,0x1f,0x00
.byte 0x00,0xc4,0x20,0x00
.byte 0x00,0x54,0x21,0x00
.byte 0x00,0x34,0x22,0x00
.byte 0x00,0x74,0x24,0x00
.byte 0x00,0x64,0x25,0x00
.byte 0x00,0x01,0x23,0x00
.byte 0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_SHA3_absorb_epilogue:
.byte 1,0,5,11
.byte 0x00,0x74,0x01,0x00
.byte 0x00,0x64,0x02,0x00
.byte 0x00,0xb3
.byte 0x00,0x00,0x00,0x00,0x00,0x00
.byte 0x00,0x00,0x00,0x00
.LSEH_info_SHA3_squeeze_prologue:
.byte 1,0,5,0x0b
.byte 0,0x74,1,0
.byte 0,0x64,2,0
.byte 0,0xb3
.byte 0,0
.long 0,0
.LSEH_info_SHA3_squeeze_body:
.byte 1,0,11,0
.byte 0x00,0xe4,0x04,0x00
.byte 0x00,0xd4,0x05,0x00
.byte 0x00,0xc4,0x06,0x00
.byte 0x00,0x74,0x08,0x00
.byte 0x00,0x64,0x09,0x00
.byte 0x00,0x62
.byte 0x00,0x00,0x00,0x00,0x00,0x00
.LSEH_info_SHA3_squeeze_epilogue:
.byte 1,0,4,0
.byte 0x00,0x74,0x01,0x00
.byte 0x00,0x64,0x02,0x00
.byte 0x00,0x00,0x00,0x00
|
Fircube/ACore-2024 | 1,426 | os/src/link_app.s |
.align 3
.section .data
.global _num_app
_num_app:
.quad 6
.quad app_0_start
.quad app_1_start
.quad app_2_start
.quad app_3_start
.quad app_4_start
.quad app_5_start
.quad app_5_end
.global _app_names
_app_names:
.string "exec"
.string "fork"
.string "get"
.string "hello_world"
.string "initproc"
.string "shell"
.section .data
.global app_0_start
.global app_0_end
.align 3
app_0_start:
.incbin "../usr/target/riscv64gc-unknown-none-elf/release/exec"
app_0_end:
.section .data
.global app_1_start
.global app_1_end
.align 3
app_1_start:
.incbin "../usr/target/riscv64gc-unknown-none-elf/release/fork"
app_1_end:
.section .data
.global app_2_start
.global app_2_end
.align 3
app_2_start:
.incbin "../usr/target/riscv64gc-unknown-none-elf/release/get"
app_2_end:
.section .data
.global app_3_start
.global app_3_end
.align 3
app_3_start:
.incbin "../usr/target/riscv64gc-unknown-none-elf/release/hello_world"
app_3_end:
.section .data
.global app_4_start
.global app_4_end
.align 3
app_4_start:
.incbin "../usr/target/riscv64gc-unknown-none-elf/release/initproc"
app_4_end:
.section .data
.global app_5_start
.global app_5_end
.align 3
app_5_start:
.incbin "../usr/target/riscv64gc-unknown-none-elf/release/shell"
app_5_end:
|
Fircube/ACore-2024 | 561 | os/src/time/interrupt.s | .section .text.trap
.globl _timer_int_handle
.align 2
_timer_int_handle:
csrrw sp, mscratch, sp
sd t0, 0(sp)
sd t1, 1*8(sp)
sd t2, 2*8(sp)
# setup next timer trigger
ld t0, 3*8(sp) # address of mtimercmp
ld t1, 4*8(sp) # timer interval
ld t2, 0(t0) # current time
add t2, t2, t1 # new time
sd t2, 0(t0) # set new time
# setup timer interrupt for supervisor
li t0, 2
csrw sip, t0
# restore registers
ld t0, 0(sp)
ld t1, 1*8(sp)
ld t2, 2*8(sp)
csrrw sp, mscratch, sp
mret |
Fircube/ACore-2024 | 690 | os/src/task/switch.s | .altmacro
.macro SAVE_SN n
sd s\n, (\n+2)*8(a0)
.endm
.macro LOAD_SN n
ld s\n, (\n+2)*8(a1)
.endm
.section .text
.globl __switch
__switch:
# __switch(
# current_task_cx_ptr: *mut TaskContext, // a0
# next_task_cx_ptr: *const TaskContext // a1
# )
# save kernel stack of current task
sd sp, 8(a0)
# save ra & s0~s11 of current execution
sd ra, 0(a0)
.set n, 0
.rept 12
SAVE_SN %n
.set n, n + 1
.endr
# restore ra & s0~s11 of next execution
ld ra, 0(a1)
.set n, 0
.rept 12
LOAD_SN %n
.set n, n + 1
.endr
# restore kernel stack of next task
ld sp, 8(a1)
ret
|
Fircube/ACore-2024 | 1,685 | os/src/trap/trap.S | .altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __usertrap
.globl __userret
.align 2
__usertrap:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose registers x1(ra) x3(gp)
sd x1, 1*8(sp)
# skip sp(x2), we will save it later
sd x3, 3*8(sp)
# skip tp(x4), application does not use it
# save x5~x31
.set n, 5
.rept 27
SAVE_GP %n
.set n, n+1
.endr
# we can use t0/t1/t2 freely, because they have been saved in TrapContext
csrr t0, sstatus
csrr t1, sepc
sd t0, 32*8(sp)
sd t1, 33*8(sp)
# read user stack from sscratch and save it in TrapContext
csrr t2, sscratch
sd t2, 2*8(sp)
# load kernel_satp into t0
ld t0, 34*8(sp)
# load trap_handler into t1
ld t1, 36*8(sp)
# move to kernel_sp
ld sp, 35*8(sp)
# switch to kernel space
sfence.vma
csrw satp, t0
sfence.vma
# jump to trap_handler
jr t1
__userret:
# a0: *TrapContext in user space(Constant); a1: user space token
# switch to user space
sfence.vma
csrw satp, a1
sfence.vma
csrw sscratch, a0
mv sp, a0
# now sp points to TrapContext in user space, start restoring based on it
# restore sstatus/sepc
ld t0, 32*8(sp)
ld t1, 33*8(sp)
csrw sstatus, t0
csrw sepc, t1
# restore general purpose registers except x0/sp/tp
ld x1, 1*8(sp)
ld x3, 3*8(sp)
.set n, 5
.rept 27
LOAD_GP %n
.set n, n+1
.endr
# back to user stack
ld sp, 2*8(sp)
sret |
flattte/crypto-usage | 323 | res/entry.s | .option norvc
.section .init
.global _start
_start:
.option push
.option norelax
la gp, global_pointer
.option pop
/* Setup stack */
la sp, stack_top
/* Clear the BSS section */
la t5, bss_start
la t6, bss_end
bss_clear:
sd zero, (t5)
addi t5, t5, 8
bgeu t5, t6, bss_clear
start:
tail main
|
FloppyO1/Floppy-Ant-Controller | 9,173 | SOFTWARE/FAC firmware/Core/Startup/startup_stm32f070cbtx.s | /**
******************************************************************************
* @file startup_stm32f070xb.s
* @author MCD Application Team
* @brief STM32F070xb/STM32F070x8 devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word 0 /* Reserved */
.word RTC_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* Reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word 0 /* Reserved */
.word TIM3_IRQHandler /* TIM3 */
.word TIM6_IRQHandler /* TIM6 */
.word TIM7_IRQHandler /* TIM7 */
.word TIM14_IRQHandler /* TIM14 */
.word TIM15_IRQHandler /* TIM15 */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word I2C2_IRQHandler /* I2C2 */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_4_IRQHandler /* USART3 and USART4 */
.word 0 /* Reserved */
.word USB_IRQHandler /* USB */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_4_IRQHandler
.thumb_set USART3_4_IRQHandler,Default_Handler
.weak USB_IRQHandler
.thumb_set USB_IRQHandler,Default_Handler
|
flux-rs/flux-verify-std | 11,809 | library/std/src/sys/pal/sgx/abi/entry.S | /* This symbol is used at runtime to figure out the virtual address that the */
/* enclave is loaded at. */
.section absolute
.global IMAGE_BASE
IMAGE_BASE:
.section ".note.x86_64-fortanix-unknown-sgx", "", @note
.align 4
.long 1f - 0f /* name length (not including padding) */
.long 3f - 2f /* desc length (not including padding) */
.long 1 /* type = NT_VERSION */
0: .asciz "toolchain-version" /* name */
1: .align 4
2: .long 1 /* desc - toolchain version number, 32-bit LE */
3: .align 4
.section .rodata
/* The XSAVE area needs to be a large chunk of readable memory, but since we are */
/* going to restore everything to its initial state (XSTATE_BV=0), only certain */
/* parts need to have a defined value. In particular: */
/* */
/* * MXCSR in the legacy area. This register is always restored if RFBM[1] or */
/* RFBM[2] is set, regardless of the value of XSTATE_BV */
/* * XSAVE header */
.align 64
.Lxsave_clear:
.org .+24
.Lxsave_mxcsr:
.short 0x1fbf
/* We can store a bunch of data in the gap between MXCSR and the XSAVE header */
/* The following symbols point at read-only data that will be filled in by the */
/* post-linker. */
/* When using this macro, don't forget to adjust the linker version script! */
.macro globvar name:req size:req
.global \name
.protected \name
.align \size
.size \name , \size
\name :
.org .+\size
.endm
/* The base address (relative to enclave start) of the heap area */
globvar HEAP_BASE 8
/* The heap size in bytes */
globvar HEAP_SIZE 8
/* Value of the RELA entry in the dynamic table */
globvar RELA 8
/* Value of the RELACOUNT entry in the dynamic table */
globvar RELACOUNT 8
/* The enclave size in bytes */
globvar ENCLAVE_SIZE 8
/* The base address (relative to enclave start) of the enclave configuration area */
globvar CFGDATA_BASE 8
/* Non-zero if debugging is enabled, zero otherwise */
globvar DEBUG 1
/* The base address (relative to enclave start) of the enclave text section */
globvar TEXT_BASE 8
/* The size in bytes of enclave text section */
globvar TEXT_SIZE 8
/* The base address (relative to enclave start) of the enclave .eh_frame_hdr section */
globvar EH_FRM_HDR_OFFSET 8
/* The size in bytes of enclave .eh_frame_hdr section */
globvar EH_FRM_HDR_LEN 8
/* The base address (relative to enclave start) of the enclave .eh_frame section */
globvar EH_FRM_OFFSET 8
/* The size in bytes of enclave .eh_frame section */
globvar EH_FRM_LEN 8
.org .Lxsave_clear+512
.Lxsave_header:
.int 0, 0 /* XSTATE_BV */
.int 0, 0 /* XCOMP_BV */
.org .+48 /* reserved bits */
.data
.Laborted:
.byte 0
/* TCS local storage section */
.equ tcsls_tos, 0x00 /* initialized by loader to *offset* from image base to TOS */
.equ tcsls_flags, 0x08 /* initialized by loader */
.equ tcsls_flag_secondary, 0 /* initialized by loader; 0 = standard TCS, 1 = secondary TCS */
.equ tcsls_flag_init_once, 1 /* initialized by loader to 0 */
/* 14 unused bits */
.equ tcsls_user_fcw, 0x0a
.equ tcsls_user_mxcsr, 0x0c
.equ tcsls_last_rsp, 0x10 /* initialized by loader to 0 */
.equ tcsls_panic_last_rsp, 0x18 /* initialized by loader to 0 */
.equ tcsls_debug_panic_buf_ptr, 0x20 /* initialized by loader to 0 */
.equ tcsls_user_rsp, 0x28
.equ tcsls_user_retip, 0x30
.equ tcsls_user_rbp, 0x38
.equ tcsls_user_r12, 0x40
.equ tcsls_user_r13, 0x48
.equ tcsls_user_r14, 0x50
.equ tcsls_user_r15, 0x58
.equ tcsls_tls_ptr, 0x60
.equ tcsls_tcs_addr, 0x68
.macro load_tcsls_flag_secondary_bool reg:req comments:vararg
.ifne tcsls_flag_secondary /* to convert to a bool, must be the first bit */
.abort
.endif
mov $(1<<tcsls_flag_secondary),%e\reg
and %gs:tcsls_flags,%\reg
.endm
/* We place the ELF entry point in a separate section so it can be removed by
elf2sgxs */
.section .text_no_sgx, "ax"
.Lelf_entry_error_msg:
.ascii "Error: This file is an SGX enclave which cannot be executed as a standard Linux binary.\nSee the installation guide at https://edp.fortanix.com/docs/installation/guide/ on how to use 'cargo run' or follow the steps at https://edp.fortanix.com/docs/tasks/deployment/ for manual deployment.\n"
.Lelf_entry_error_msg_end:
.global elf_entry
.type elf_entry,function
elf_entry:
/* print error message */
movq $2,%rdi /* write to stderr (fd 2) */
lea .Lelf_entry_error_msg(%rip),%rsi
movq $.Lelf_entry_error_msg_end-.Lelf_entry_error_msg,%rdx
.Lelf_entry_call:
movq $1,%rax /* write() syscall */
syscall
test %rax,%rax
jle .Lelf_exit /* exit on error */
add %rax,%rsi
sub %rax,%rdx /* all chars written? */
jnz .Lelf_entry_call
.Lelf_exit:
movq $60,%rax /* exit() syscall */
movq $1,%rdi /* exit code 1 */
syscall
ud2 /* should not be reached */
/* end elf_entry */
/* This code needs to be called *after* the enclave stack has been setup. */
/* There are 3 places where this needs to happen, so this is put in a macro. */
.macro entry_sanitize_final
/* Sanitize rflags received from user */
/* - DF flag: x86-64 ABI requires DF to be unset at function entry/exit */
/* - AC flag: AEX on misaligned memory accesses leaks side channel info */
pushfq
andq $~0x40400, (%rsp)
popfq
/* check for abort */
bt $0,.Laborted(%rip)
jc .Lreentry_panic
.endm
.text
.global sgx_entry
.type sgx_entry,function
sgx_entry:
/* save user registers */
mov %rcx,%gs:tcsls_user_retip
mov %rsp,%gs:tcsls_user_rsp
mov %rbp,%gs:tcsls_user_rbp
mov %r12,%gs:tcsls_user_r12
mov %r13,%gs:tcsls_user_r13
mov %r14,%gs:tcsls_user_r14
mov %r15,%gs:tcsls_user_r15
mov %rbx,%gs:tcsls_tcs_addr
stmxcsr %gs:tcsls_user_mxcsr
fnstcw %gs:tcsls_user_fcw
/* check for debug buffer pointer */
testb $0xff,DEBUG(%rip)
jz .Lskip_debug_init
mov %r10,%gs:tcsls_debug_panic_buf_ptr
.Lskip_debug_init:
/* reset cpu state */
mov %rdx, %r10
mov $-1, %rax
mov $-1, %rdx
xrstor .Lxsave_clear(%rip)
lfence
mov %r10, %rdx
/* check if returning from usercall */
mov %gs:tcsls_last_rsp,%r11
test %r11,%r11
jnz .Lusercall_ret
/* setup stack */
mov %gs:tcsls_tos,%rsp /* initially, RSP is not set to the correct value */
/* here. This is fixed below under "adjust stack". */
/* check for thread init */
bts $tcsls_flag_init_once,%gs:tcsls_flags
jc .Lskip_init
/* adjust stack */
lea IMAGE_BASE(%rip),%rax
add %rax,%rsp
mov %rsp,%gs:tcsls_tos
entry_sanitize_final
/* call tcs_init */
/* store caller-saved registers in callee-saved registers */
mov %rdi,%rbx
mov %rsi,%r12
mov %rdx,%r13
mov %r8,%r14
mov %r9,%r15
load_tcsls_flag_secondary_bool di /* RDI = tcs_init() argument: secondary: bool */
call tcs_init
/* reload caller-saved registers */
mov %rbx,%rdi
mov %r12,%rsi
mov %r13,%rdx
mov %r14,%r8
mov %r15,%r9
jmp .Lafter_init
.Lskip_init:
entry_sanitize_final
.Lafter_init:
/* call into main entry point */
load_tcsls_flag_secondary_bool cx /* RCX = entry() argument: secondary: bool */
call entry /* RDI, RSI, RDX, R8, R9 passed in from userspace */
mov %rax,%rsi /* RSI = return value */
/* NOP: mov %rdx,%rdx */ /* RDX = return value */
xor %rdi,%rdi /* RDI = normal exit */
.Lexit:
/* clear general purpose register state */
/* RAX overwritten by ENCLU */
/* RBX set later */
/* RCX overwritten by ENCLU */
/* RDX contains return value */
/* RSP set later */
/* RBP set later */
/* RDI contains exit mode */
/* RSI contains return value */
xor %r8,%r8
xor %r9,%r9
xor %r10,%r10
xor %r11,%r11
/* R12 ~ R15 set by sgx_exit */
.Lsgx_exit:
/* clear extended register state */
mov %rdx, %rcx /* save RDX */
mov $-1, %rax
mov %rax, %rdx
xrstor .Lxsave_clear(%rip)
mov %rcx, %rdx /* restore RDX */
/* clear flags */
pushq $0
popfq
/* restore user registers */
mov %gs:tcsls_user_r12,%r12
mov %gs:tcsls_user_r13,%r13
mov %gs:tcsls_user_r14,%r14
mov %gs:tcsls_user_r15,%r15
mov %gs:tcsls_user_retip,%rbx
mov %gs:tcsls_user_rsp,%rsp
mov %gs:tcsls_user_rbp,%rbp
fldcw %gs:tcsls_user_fcw
ldmxcsr %gs:tcsls_user_mxcsr
/* exit enclave */
mov $0x4,%eax /* EEXIT */
enclu
/* end sgx_entry */
.Lreentry_panic:
orq $8,%rsp
jmp abort_reentry
/* This *MUST* be called with 6 parameters, otherwise register information */
/* might leak! */
.global usercall
usercall:
test %rcx,%rcx /* check `abort` function argument */
jnz .Lusercall_abort /* abort is set, jump to abort code (unlikely forward conditional) */
jmp .Lusercall_save_state /* non-aborting usercall */
.Lusercall_abort:
/* set aborted bit */
movb $1,.Laborted(%rip)
/* save registers in DEBUG mode, so that debugger can reconstruct the stack */
testb $0xff,DEBUG(%rip)
jz .Lusercall_noreturn
.Lusercall_save_state:
/* save callee-saved state */
push %r15
push %r14
push %r13
push %r12
push %rbp
push %rbx
sub $8, %rsp
fstcw 4(%rsp)
stmxcsr (%rsp)
movq %rsp,%gs:tcsls_last_rsp
.Lusercall_noreturn:
/* clear general purpose register state */
/* RAX overwritten by ENCLU */
/* RBX set by sgx_exit */
/* RCX overwritten by ENCLU */
/* RDX contains parameter */
/* RSP set by sgx_exit */
/* RBP set by sgx_exit */
/* RDI contains parameter */
/* RSI contains parameter */
/* R8 contains parameter */
/* R9 contains parameter */
xor %r10,%r10
xor %r11,%r11
/* R12 ~ R15 set by sgx_exit */
/* extended registers/flags cleared by sgx_exit */
/* exit */
jmp .Lsgx_exit
.Lusercall_ret:
movq $0,%gs:tcsls_last_rsp
/* restore callee-saved state, cf. "save" above */
mov %r11,%rsp
/* MCDT mitigation requires an lfence after ldmxcsr _before_ any of the affected */
/* vector instructions is used. We omit the lfence here as one is required before */
/* the jmp instruction anyway. */
ldmxcsr (%rsp)
fldcw 4(%rsp)
add $8, %rsp
entry_sanitize_final
pop %rbx
pop %rbp
pop %r12
pop %r13
pop %r14
pop %r15
/* return */
mov %rsi,%rax /* RAX = return value */
/* NOP: mov %rdx,%rdx */ /* RDX = return value */
pop %r11
lfence
jmp *%r11
/*
The following functions need to be defined externally:
```
// Called by entry code on re-entry after exit
extern "C" fn abort_reentry() -> !;
// Called once when a TCS is first entered
extern "C" fn tcs_init(secondary: bool);
// Standard TCS entrypoint
extern "C" fn entry(p1: u64, p2: u64, p3: u64, secondary: bool, p4: u64, p5: u64) -> (u64, u64);
```
*/
.global get_tcs_addr
get_tcs_addr:
mov %gs:tcsls_tcs_addr,%rax
pop %r11
lfence
jmp *%r11
.global get_tls_ptr
get_tls_ptr:
mov %gs:tcsls_tls_ptr,%rax
pop %r11
lfence
jmp *%r11
.global set_tls_ptr
set_tls_ptr:
mov %rdi,%gs:tcsls_tls_ptr
pop %r11
lfence
jmp *%r11
.global take_debug_panic_buf_ptr
take_debug_panic_buf_ptr:
xor %rax,%rax
xchg %gs:tcsls_debug_panic_buf_ptr,%rax
pop %r11
lfence
jmp *%r11
|
foss-for-synopsys-dwc-arc-processors/compiler-abi-extractor | 336 | src/arch/riscv2.s | # Copyright 2025-present, Synopsys, Inc.
# All rights reserved.
#
# This source code is licensed under the GPL-3.0 license found in
# the LICENSE file in the root directory of this source tree.
.data
.text
.globl foo
foo:
addi sp, sp, -8
sw ra, 0(sp)
call bar
call callee
lw ra, 0(sp)
addi sp, sp, 8
ret
|
foss-for-synopsys-dwc-arc-processors/compiler-abi-extractor | 4,651 | src/arch/riscv.S | # Copyright 2025-present, Synopsys, Inc.
# All rights reserved.
#
# This source code is licensed under the GPL-3.0 license found in
# the LICENSE file in the root directory of this source tree.
#if __riscv_xlen == 64
#define T6_STACK_OFFSET -8
#define S2_STACK_OFFSET -16
#else
#define T6_STACK_OFFSET -4
#define S2_STACK_OFFSET -8
#endif
.data
.globl regs_bank0
.globl regs_bank1
regs_bank0:
.rept 32
.dword 0
.endr
.size regs_bank0, .-regs_bank0
regs_bank1:
.rept 32
.dword 0
.endr
.size regs_bank1, .-regs_bank1
.text
.align 1
.globl callee
.globl get_stack_pointer
.globl set_registers
.type callee, @function
callee:
#if __riscv_xlen == 64
# Save t6 to the stack
sd t6, T6_STACK_OFFSET(sp)
# Initialize t6 to point to the start of the regs_bank0 array
la t6, regs_bank0
sd x0, 0(t6)
sd x1, 8(t6)
sd x2, 16(t6)
sd x3, 24(t6)
sd x4, 32(t6)
sd x5, 40(t6)
sd x6, 48(t6)
sd x7, 56(t6)
sd x8, 64(t6)
sd x9, 72(t6)
sd x10, 80(t6)
sd x11, 88(t6)
sd x12, 96(t6)
sd x13, 104(t6)
sd x14, 112(t6)
sd x15, 120(t6)
sd x16, 128(t6)
sd x17, 136(t6)
sd x18, 144(t6)
sd x19, 152(t6)
sd x20, 160(t6)
sd x21, 168(t6)
sd x22, 176(t6)
sd x23, 184(t6)
sd x24, 192(t6)
sd x25, 200(t6)
sd x26, 208(t6)
sd x27, 216(t6)
sd x28, 224(t6)
sd x29, 232(t6)
sd x30, 240(t6)
#else
# Save t6 to the stack
sw t6, T6_STACK_OFFSET(sp)
# Initialize t6 to point to the start of the regs_bank0 array
la t6, regs_bank0
sw x0, 0(t6)
sw x1, 4(t6)
sw x2, 8(t6)
sw x3, 12(t6)
sw x4, 16(t6)
sw x5, 20(t6)
sw x6, 24(t6)
sw x7, 28(t6)
sw x8, 32(t6)
sw x9, 36(t6)
sw x10, 40(t6)
sw x11, 44(t6)
sw x12, 48(t6)
sw x13, 52(t6)
sw x14, 56(t6)
sw x15, 60(t6)
sw x16, 64(t6)
sw x17, 68(t6)
sw x18, 72(t6)
sw x19, 76(t6)
sw x20, 80(t6)
sw x21, 84(t6)
sw x22, 88(t6)
sw x23, 92(t6)
sw x24, 96(t6)
sw x25, 100(t6)
sw x26, 104(t6)
sw x27, 108(t6)
sw x28, 112(t6)
sw x29, 116(t6)
sw x30, 120(t6)
#endif
# Initialize t6 to point to the start of the regs_bank1 array
#ifndef __riscv_float_abi_soft
la t6, regs_bank1
fsd f0, 0(t6)
fsd f1, 8(t6)
fsd f2, 16(t6)
fsd f3, 24(t6)
fsd f4, 32(t6)
fsd f5, 40(t6)
fsd f6, 48(t6)
fsd f7, 56(t6)
fsd f8, 64(t6)
fsd f9, 72(t6)
fsd f10, 80(t6)
fsd f11, 88(t6)
fsd f12, 96(t6)
fsd f13, 104(t6)
fsd f14, 112(t6)
fsd f15, 120(t6)
fsd f16, 128(t6)
fsd f17, 136(t6)
fsd f18, 144(t6)
fsd f19, 152(t6)
fsd f20, 160(t6)
fsd f21, 168(t6)
fsd f22, 176(t6)
fsd f23, 184(t6)
fsd f24, 192(t6)
fsd f25, 200(t6)
fsd f26, 208(t6)
fsd f27, 216(t6)
fsd f28, 224(t6)
fsd f29, 232(t6)
fsd f30, 240(t6)
fsd f31, 248(t6)
#endif
la t6, regs_bank0
#if __riscv_xlen == 64
# handle t6/x31
ld x30, T6_STACK_OFFSET(sp)
sd x30, 248(t6)
ld x30, 240(t6)
# Note: t6 register itself (x31) is not stored to regs_bank0 array
# save the callee-saved register
sd s2, S2_STACK_OFFSET(sp)
# save the return address to a callee-saved register
ld s2, 8(t6)
# call to dump_information
mv x10, sp
call dump_information
# restore the return address
addi ra, s2, 0
# restore the calee-saved register
ld s2, S2_STACK_OFFSET(sp)
#else
# handle t6/x31
lw x30, T6_STACK_OFFSET(sp)
sw x30, 124(t6)
lw x30, 120(t6)
# Note: t6 register itself (x31) is not stored to regs_bank0 array
# save the callee-saved register
sw s2, S2_STACK_OFFSET(sp)
# save the return address to a callee-saved register
lw s2, 4(t6)
# call to dump_information
mv x10, sp
call dump_information
# restore the return address
addi ra, s2, 0
# restore the calee-saved register
lw s2, S2_STACK_OFFSET(sp)
#endif
ret
.size callee, .-callee
get_stack_pointer:
mv a0, sp
ret
set_registers:
addi x5, a0, 0
addi x6, a0, 0
addi x7, a0, 0
addi x8, a0, 0
addi x9, a0, 0
addi x10, a0, 0
addi x11, a0, 0
addi x12, a0, 0
addi x13, a0, 0
addi x14, a0, 0
addi x15, a0, 0
addi x16, a0, 0
addi x17, a0, 0
addi x18, a0, 0
addi x19, a0, 0
addi x20, a0, 0
addi x21, a0, 0
addi x22, a0, 0
addi x23, a0, 0
addi x24, a0, 0
addi x25, a0, 0
addi x26, a0, 0
addi x27, a0, 0
addi x28, a0, 0
addi x29, a0, 0
addi x30, a0, 0
addi x31, a0, 0
ret
|
Foundation-Devices/pqcrypto | 5,583 | pqcrypto-internals/cfiles/keccak2x/feat.S |
/*
MIT License
Copyright (c) 2020 Bas Westerbaan
Copyright (c) 2023: Hanno Becker, Vincent Hwang, Matthias J. Kannwischer, Bo-Yin Yang, and Shang-Yi Yang
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
#if (__APPLE__ && __ARM_FEATURE_CRYPTO) || (__ARM_FEATURE_SHA3)
.macro round
// Execute theta, but without xoring into the state yet.
// Compute parities p[i] = a[i] ^ a[5+i] ^ ... ^ a[20+i].
eor3 v25.16b, v0.16b, v5.16b, v10.16b
eor3 v26.16b, v1.16b, v6.16b, v11.16b
eor3 v27.16b, v2.16b, v7.16b, v12.16b
eor3 v28.16b, v3.16b, v8.16b, v13.16b
eor3 v29.16b, v4.16b, v9.16b, v14.16b
eor3 v25.16b, v25.16b, v15.16b, v20.16b
eor3 v26.16b, v26.16b, v16.16b, v21.16b
eor3 v27.16b, v27.16b, v17.16b, v22.16b
eor3 v28.16b, v28.16b, v18.16b, v23.16b
eor3 v29.16b, v29.16b, v19.16b, v24.16b
rax1 v30.2d, v29.2d, v26.2d // d[0] = rotl(p[1], 1) ^ p[4]
rax1 v29.2d, v27.2d, v29.2d // d[3] = rotl(p[4], 1) ^ p[2]
rax1 v27.2d, v25.2d, v27.2d // d[1] = rotl(p[2], 1) ^ p[0]
rax1 v25.2d, v28.2d, v25.2d // d[4] = rotl(p[0], 1) ^ p[3]
rax1 v28.2d, v26.2d, v28.2d // d[2] = rotl(p[3], 1) ^ p[1]
// Xor parities from step theta into the state at the same time
// as executing rho and pi.
eor v0.16b, v0.16b, v30.16b
mov v31.16b, v1.16b
xar v1.2d, v6.2d, v27.2d, 20
xar v6.2d, v9.2d, v25.2d, 44
xar v9.2d, v22.2d, v28.2d, 3
xar v22.2d, v14.2d, v25.2d, 25
xar v14.2d, v20.2d, v30.2d, 46
xar v20.2d, v2.2d, v28.2d, 2
xar v2.2d, v12.2d, v28.2d, 21
xar v12.2d, v13.2d, v29.2d, 39
xar v13.2d, v19.2d, v25.2d, 56
xar v19.2d, v23.2d, v29.2d, 8
xar v23.2d, v15.2d, v30.2d, 23
xar v15.2d, v4.2d, v25.2d, 37
xar v4.2d, v24.2d, v25.2d, 50
xar v24.2d, v21.2d, v27.2d, 62
xar v21.2d, v8.2d, v29.2d, 9
xar v8.2d, v16.2d, v27.2d, 19
xar v16.2d, v5.2d, v30.2d, 28
xar v5.2d, v3.2d, v29.2d, 36
xar v3.2d, v18.2d, v29.2d, 43
xar v18.2d, v17.2d, v28.2d, 49
xar v17.2d, v11.2d, v27.2d, 54
xar v11.2d, v7.2d, v28.2d, 58
xar v7.2d, v10.2d, v30.2d, 61
xar v10.2d, v31.2d, v27.2d, 63
// Chi
bcax v25.16b, v0.16b, v2.16b, v1.16b
bcax v26.16b, v1.16b, v3.16b, v2.16b
bcax v2.16b, v2.16b, v4.16b, v3.16b
bcax v3.16b, v3.16b, v0.16b, v4.16b
bcax v4.16b, v4.16b, v1.16b, v0.16b
mov v0.16b, v25.16b
mov v1.16b, v26.16b
bcax v25.16b, v5.16b, v7.16b, v6.16b
bcax v26.16b, v6.16b, v8.16b, v7.16b
bcax v7.16b, v7.16b, v9.16b, v8.16b
bcax v8.16b, v8.16b, v5.16b, v9.16b
bcax v9.16b, v9.16b, v6.16b, v5.16b
mov v5.16b, v25.16b
mov v6.16b, v26.16b
bcax v25.16b, v10.16b, v12.16b, v11.16b
bcax v26.16b, v11.16b, v13.16b, v12.16b
bcax v12.16b, v12.16b, v14.16b, v13.16b
bcax v13.16b, v13.16b, v10.16b, v14.16b
bcax v14.16b, v14.16b, v11.16b, v10.16b
mov v10.16b, v25.16b
mov v11.16b, v26.16b
bcax v25.16b, v15.16b, v17.16b, v16.16b
bcax v26.16b, v16.16b, v18.16b, v17.16b
bcax v17.16b, v17.16b, v19.16b, v18.16b
bcax v18.16b, v18.16b, v15.16b, v19.16b
bcax v19.16b, v19.16b, v16.16b, v15.16b
mov v15.16b, v25.16b
mov v16.16b, v26.16b
bcax v25.16b, v20.16b, v22.16b, v21.16b
bcax v26.16b, v21.16b, v23.16b, v22.16b
bcax v22.16b, v22.16b, v24.16b, v23.16b
bcax v23.16b, v23.16b, v20.16b, v24.16b
bcax v24.16b, v24.16b, v21.16b, v20.16b
mov v20.16b, v25.16b
mov v21.16b, v26.16b
// iota
ld1r {v25.2d}, [x1], #8
eor v0.16b, v0.16b, v25.16b
.endm
.align 4
.global f1600x2
.global _f1600x2
f1600x2:
_f1600x2:
stp d8, d9, [sp,#-16]!
stp d10, d11, [sp,#-16]!
stp d12, d13, [sp,#-16]!
stp d14, d15, [sp,#-16]!
mov x2, x0
mov x3, #24
ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64
ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64
ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64
ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64
ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64
ld1 {v24.2d}, [x0]
loop:
round
subs x3, x3, #1
cbnz x3, loop
mov x0, x2
st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64
st1 {v4.2d, v5.2d, v6.2d, v7.2d}, [x0], #64
st1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x0], #64
st1 {v12.2d, v13.2d, v14.2d, v15.2d}, [x0], #64
st1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0], #64
st1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x0], #64
st1 {v24.2d}, [x0]
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
ret lr
#endif
|
fpdotmonkey/hot-reload | 62 | tls-dtor-fallback.s | .global __cxa_thread_atexit_impl
__cxa_thread_atexit_impl = 0
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,082 | portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
#if ( configENABLE_FPU == 1 )
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
#endif
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
stmia r1!, {r2} /* Store CONTROL value on the stack. */
#else /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
#endif /* configENABLE_MPU */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 4,055 | portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION .text:CODE:NOROOT(2)
THUMB
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
PUBLIC SecureContext_LoadContextAsm
PUBLIC SecureContext_SaveContextAsm
/*-----------------------------------------------------------*/
SecureContext_LoadContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
ldmia r0!, {r1, r2} /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
#if ( configENABLE_MPU == 1 )
ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
msr control, r3 /* CONTROL = r3. */
#endif /* configENABLE_MPU */
msr psplim, r2 /* PSPLIM = r2. */
msr psp, r1 /* PSP = r1. */
load_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
SecureContext_SaveContextAsm:
/* pxSecureContext value is in r0. */
mrs r1, ipsr /* r1 = IPSR. */
cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
mrs r1, psp /* r1 = PSP. */
#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
vstmdb r1!, {s0} /* Trigger the deferred stacking of FPU registers. */
vldmia r1!, {s0} /* Nullify the effect of the previous statement. */
#endif /* configENABLE_FPU || configENABLE_MVE */
#if ( configENABLE_MPU == 1 )
mrs r2, control /* r2 = CONTROL. */
stmdb r1!, {r2} /* Store CONTROL value on the stack. */
#endif /* configENABLE_MPU */
str r1, [r0] /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
movs r1, #0 /* r1 = securecontextNO_STACK. */
msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
save_ctx_therad_mode:
bx lr
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 22,503 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
#ifndef configRUN_FREERTOS_SECURE_ONLY
#define configRUN_FREERTOS_SECURE_ONLY 0
#endif
EXTERN pxCurrentTCB
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
#if ( configENABLE_FPU == 1 )
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
#endif
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
beq running_privileged /* If the result of previous AND operation was 0, branch. */
movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
bx lr /* Return. */
running_privileged:
movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
orrs r0, r1 /* r0 = r0 | r1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs_first_task:
subs r1, #16
ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
subs r1, #16
msr psp, r2
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r3
#endif
msr control, r4
mov lr, r5
restore_general_regs_first_task:
subs r1, #32
ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r1, #48
ldmia r1!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r1, #32
ldmia r1!, {r4-r7} /* Restore r4-r7. */
subs r1, #16
restore_context_done_first_task:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r1 /* Set this task's PSPLIM value. */
#endif
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
bx r2 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
movs r1, #1 /* r1 = 1. */
bics r0, r1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
nop
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, PRIMASK
cpsid i
bx lr
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr PRIMASK, r0
bx lr
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB. */
ldr r1, [r0] /* r1 = Location in TCB where the context should be saved. */
mrs r2, psp /* r2 = PSP. */
save_general_regs:
stmia r1!, {r4-r7} /* Store r4-r7. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r1!, {r4-r7} /* Store r8-r11. */
ldmia r2!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */
stmia r1!, {r4-r7} /* Store the hardware saved context. */
ldmia r2!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */
stmia r1!, {r4-r7} /* Store the hardware saved context. */
save_special_regs:
mrs r2, psp /* r2 = PSP. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
mrs r3, psplim /* r3 = PSPLIM. */
#else
movs r3, #0 /* r3 = 0. 0 is stored in the PSPLIM slot. */
#endif
mrs r4, control /* r4 = CONTROL. */
mov r5, lr /* r5 = LR. */
stmia r1!, {r2-r5} /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r1, [r0] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
cpsid i
bl vTaskSwitchContext
cpsie i
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r2] /* r0 = pxCurrentTCB.*/
ldr r1, [r0] /* r1 = Location of saved context in TCB. */
restore_special_regs:
subs r1, #16
ldmia r1!, {r2-r5} /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
subs r1, #16
msr psp, r2
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r3
#endif
msr control, r4
mov lr, r5
restore_general_regs:
subs r1, #32
ldmia r1!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r1!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r2!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r1, #48
ldmia r1!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r1, #32
ldmia r1!, {r4-r7} /* Restore r4-r7. */
subs r1, #16
restore_context_done:
str r1, [r0] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
mrs r0, psp /* Read PSP in r0. */
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */
str r0, [r1] /* Save the new top of stack in TCB. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
mrs r2, psplim /* r2 = PSPLIM. */
#else
movs r2, #0 /* r0 = 0. 0 is stored in the PSPLIM slot. */
#endif
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */
cpsid i
bl vTaskSwitchContext
cpsie i
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r2] /* Read pxCurrentTCB. */
ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
adds r0, r0, #24 /* Move to the high registers. */
ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
msr psp, r0 /* Remember the new top of stack for the task. */
subs r0, r0, #40 /* Move to the starting of the saved context. */
ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
#endif
bx r3
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stack_on_msp
stack_on_psp:
mrs r0, psp
b route_svc
stack_on_msp:
mrs r0, msp
b route_svc
route_svc:
ldr r3, [r0, #24]
subs r3, #2
ldrb r2, [r3, #0]
cmp r2, #NUM_SYSTEM_CALLS
blt system_call_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq system_call_exit
b vPortSVCHandler_C
system_call_enter:
b vSystemCallEnter
system_call_exit:
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stacking_used_msp
mrs r0, psp
b vPortSVCHandler_C
stacking_used_msp:
mrs r0, msp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 40,430 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0, r1}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0, r1}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0, r1}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0, r1}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0, r1}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0, r1}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0, r1}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0, r1}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0, r1}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0, r1}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0, r1}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0, r1}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0, r1}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0, r1}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0, r1}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0, r1}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0, r1}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0, r1}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0, r1}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0, r1}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0, r1}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0, r1}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0, r1}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0, r1}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0, r1}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0, r1}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0, r1}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0, r1}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0, r1}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0, r1}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0, r1}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0, r1}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0, r1}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0, r1}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0, r1}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0, r1}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0, r1}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0, r1}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0, r1}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0, r1}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0, r1}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0, r1}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0, r1}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0, r1}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0, r1}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 28,629 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
/* Including FreeRTOSConfig.h here will cause build errors if the header file
contains code not understood by the assembler - for example the 'extern' keyword.
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
the code is included in C files but excluded by the preprocessor in assembly
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
#include "FreeRTOSConfig.h"
/* System call numbers includes. */
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
EXTERN pxCurrentTCB
EXTERN xSecureContext
EXTERN vTaskSwitchContext
EXTERN vPortSVCHandler_C
EXTERN SecureContext_SaveContext
EXTERN SecureContext_LoadContext
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
EXTERN vSystemCallEnter
EXTERN vSystemCallExit
#endif
PUBLIC xIsPrivileged
PUBLIC vResetPrivilege
PUBLIC vPortAllocateSecureContext
PUBLIC vRestoreContextOfFirstTask
PUBLIC vRaisePrivilege
PUBLIC vStartFirstTask
PUBLIC ulSetInterruptMask
PUBLIC vClearInterruptMask
PUBLIC PendSV_Handler
PUBLIC SVC_Handler
PUBLIC vPortFreeSecureContext
#if ( configENABLE_FPU == 1 )
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
#endif
/*-----------------------------------------------------------*/
/*---------------- Unprivileged Functions -------------------*/
/*-----------------------------------------------------------*/
SECTION .text:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
xIsPrivileged:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
beq running_privileged /* If the result of previous AND operation was 0, branch. */
movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
bx lr /* Return. */
running_privileged:
movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
vResetPrivilege:
mrs r0, control /* r0 = CONTROL. */
movs r1, #1 /* r1 = 1. */
orrs r0, r1 /* r0 = r0 | r1. */
msr control, r0 /* CONTROL = r0. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vPortAllocateSecureContext:
svc 100 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
/*----------------- Privileged Functions --------------------*/
/*-----------------------------------------------------------*/
SECTION privileged_functions:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
vRestoreContextOfFirstTask:
program_mpu_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context_first_task:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs_first_task:
subs r2, #20
ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
subs r2, #20
msr psp, r3
msr control, r5
mov lr, r6
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
restore_general_regs_first_task:
subs r2, #32
ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r2, #48
ldmia r2!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r2, #32
ldmia r2!, {r4-r7} /* Restore r4-r7. */
subs r2, #16
restore_context_done_first_task:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
vRestoreContextOfFirstTask:
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r3, [r2] /* Read pxCurrentTCB. */
ldr r0, [r3] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
ldm r0!, {r1-r3} /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
ldr r4, =xSecureContext
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
movs r1, #2 /* r1 = 2. */
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
adds r0, #32 /* Discard everything up to r0. */
msr psp, r0 /* This is now the new top of stack to use in the task. */
isb
bx r3 /* Finally, branch to EXC_RETURN. */
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
vRaisePrivilege:
mrs r0, control /* Read the CONTROL register. */
movs r1, #1 /* r1 = 1. */
bics r0, r1 /* Clear the bit 0. */
msr control, r0 /* Write back the new CONTROL value. */
bx lr /* Return to the caller. */
/*-----------------------------------------------------------*/
vStartFirstTask:
ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
ldr r0, [r0] /* The first entry in vector table is stack pointer. */
msr msp, r0 /* Set the MSP back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
dsb
isb
svc 102 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
/*-----------------------------------------------------------*/
ulSetInterruptMask:
mrs r0, PRIMASK
cpsid i
bx lr
/*-----------------------------------------------------------*/
vClearInterruptMask:
msr PRIMASK, r0
bx lr
/*-----------------------------------------------------------*/
#if ( configENABLE_MPU == 1 )
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
ldr r2, [r1] /* r2 = Location in TCB where the context should be saved. */
cbz r0, save_ns_context /* No secure context to save. */
save_s_context:
push {r0-r2, lr}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* Restore LR. */
save_ns_context:
mov r3, lr /* r3 = LR (EXC_RETURN). */
lsls r3, r3, #25 /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi save_special_regs /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
save_general_regs:
mrs r3, psp
stmia r2!, {r4-r7} /* Store r4-r7. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r2!, {r4-r7} /* Store r8-r11. */
ldmia r3!, {r4-r7} /* Copy half of the hardware saved context into r4-r7. */
stmia r2!, {r4-r7} /* Store the hardware saved context. */
ldmia r3!, {r4-r7} /* Copy rest half of the hardware saved context into r4-r7. */
stmia r2!, {r4-r7} /* Store the hardware saved context. */
save_special_regs:
mrs r3, psp /* r3 = PSP. */
movs r4, #0 /* r4 = 0. 0 is stored in the PSPLIM slot. */
mrs r5, control /* r5 = CONTROL. */
mov r6, lr /* r6 = LR. */
stmia r2!, {r0, r3-r6} /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
str r2, [r1] /* Save the location from where the context should be restored as the first member of TCB. */
select_next_task:
cpsid i
bl vTaskSwitchContext
cpsie i
program_mpu:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r0, [r3] /* r0 = pxCurrentTCB.*/
dmb /* Complete outstanding transfers before disabling MPU. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
bics r2, r3 /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
str r2, [r1] /* Disable MPU. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
ldr r1, [r0] /* r1 = *r0 i.e. r1 = MAIR0. */
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
str r1, [r2] /* Program MAIR0. */
adds r0, #4 /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
ldr r1, =0xe000ed98 /* r1 = 0xe000ed98 [Location of RNR]. */
movs r3, #4 /* r3 = 4. */
str r3, [r1] /* Program RNR = 4. */
ldmia r0!, {r4-r5} /* Read first set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write first set of RBAR/RLAR registers. */
movs r3, #5 /* r3 = 5. */
str r3, [r1] /* Program RNR = 5. */
ldmia r0!, {r4-r5} /* Read second set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write second set of RBAR/RLAR registers. */
movs r3, #6 /* r3 = 6. */
str r3, [r1] /* Program RNR = 6. */
ldmia r0!, {r4-r5} /* Read third set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write third set of RBAR/RLAR registers. */
movs r3, #7 /* r3 = 6. */
str r3, [r1] /* Program RNR = 7. */
ldmia r0!, {r4-r5} /* Read fourth set of RBAR/RLAR registers from TCB. */
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
stmia r2!, {r4-r5} /* Write fourth set of RBAR/RLAR registers. */
ldr r1, =0xe000ed94 /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
ldr r2, [r1] /* Read the value of MPU_CTRL. */
movs r3, #1 /* r3 = 1. */
orrs r2, r3 /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
str r2, [r1] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
restore_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* r1 = pxCurrentTCB.*/
ldr r2, [r1] /* r2 = Location of saved context in TCB. */
restore_special_regs:
subs r2, #20
ldmia r2!, {r0, r3-r6} /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
subs r2, #20
msr psp, r3
msr control, r5
mov lr, r6
ldr r4, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r4] /* Restore xSecureContext. */
cbz r0, restore_ns_context /* No secure context to restore. */
restore_s_context:
push {r1-r3, lr}
bl SecureContext_LoadContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r1-r4} /* LR is now in r4. */
mov lr, r4
restore_ns_context:
mov r0, lr /* r0 = LR (EXC_RETURN). */
lsls r0, r0, #25 /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bmi restore_context_done /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
restore_general_regs:
subs r2, #32
ldmia r2!, {r4-r7} /* r4-r7 contain half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy half of the the hardware saved context on the task stack. */
ldmia r2!, {r4-r7} /* r4-r7 contain rest half of the hardware saved context. */
stmia r3!, {r4-r7} /* Copy rest half of the the hardware saved context on the task stack. */
subs r2, #48
ldmia r2!, {r4-r7} /* Restore r8-r11. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
subs r2, #32
ldmia r2!, {r4-r7} /* Restore r4-r7. */
subs r2, #16
restore_context_done:
str r2, [r1] /* Save the location where the context should be saved next as the first member of TCB. */
bx lr
#else /* configENABLE_MPU */
PendSV_Handler:
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
mrs r2, psp /* Read PSP in r2. */
cbz r0, save_ns_context /* No secure context to save. */
push {r0-r2, r14}
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r0-r3} /* LR is now in r3. */
mov lr, r3 /* LR = r3. */
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
b select_next_task
save_ns_context:
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
str r2, [r1] /* Save the new top of stack in TCB. */
movs r1, #0 /* r1 = 0. 0 is stored in the PSPLIM slot. */
mov r3, lr /* r3 = LR/EXC_RETURN. */
stmia r2!, {r0, r1, r3-r7} /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
mov r4, r8 /* r4 = r8. */
mov r5, r9 /* r5 = r9. */
mov r6, r10 /* r6 = r10. */
mov r7, r11 /* r7 = r11. */
stmia r2!, {r4-r7} /* Store the high registers that are not saved automatically. */
select_next_task:
cpsid i
bl vTaskSwitchContext
cpsie i
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
mov lr, r4 /* LR = r4. */
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
str r0, [r3] /* Restore the task's xSecureContext. */
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
ldr r1, [r3] /* Read pxCurrentTCB. */
push {r2, r4}
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
pop {r2, r4}
mov lr, r4 /* LR = r4. */
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
msr psp, r2 /* Remember the new top of stack for the task. */
bx lr
restore_ns_context:
adds r2, r2, #16 /* Move to the high registers. */
ldmia r2!, {r4-r7} /* Restore the high registers that are not automatically restored. */
mov r8, r4 /* r8 = r4. */
mov r9, r5 /* r9 = r5. */
mov r10, r6 /* r10 = r6. */
mov r11, r7 /* r11 = r7. */
msr psp, r2 /* Remember the new top of stack for the task. */
subs r2, r2, #32 /* Go back to the low registers. */
ldmia r2!, {r4-r7} /* Restore the low registers that are not automatically restored. */
bx lr
#endif /* configENABLE_MPU */
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stack_on_msp
stack_on_psp:
mrs r0, psp
b route_svc
stack_on_msp:
mrs r0, msp
b route_svc
route_svc:
ldr r3, [r0, #24]
subs r3, #2
ldrb r2, [r3, #0]
cmp r2, #NUM_SYSTEM_CALLS
blt system_call_enter
cmp r2, #104 /* portSVC_SYSTEM_CALL_EXIT. */
beq system_call_exit
b vPortSVCHandler_C
system_call_enter:
b vSystemCallEnter
system_call_exit:
b vSystemCallExit
#else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
SVC_Handler:
movs r0, #4
mov r1, lr
tst r0, r1
beq stacking_used_msp
mrs r0, psp
b vPortSVCHandler_C
stacking_used_msp:
mrs r0, msp
b vPortSVCHandler_C
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
/*-----------------------------------------------------------*/
vPortFreeSecureContext:
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
bne free_secure_context /* Branch if r1 != 0. */
bx lr /* There is no secure context (xSecureContext is NULL). */
free_secure_context:
svc 101 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
bx lr /* Return. */
/*-----------------------------------------------------------*/
END
|
FreeRTOSCIRunnerIntegrationTest/lab-freertos-kernel | 40,430 | portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/mpu_wrappers_v2_asm.S | /*
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* https://www.FreeRTOS.org
* https://github.com/FreeRTOS
*
*/
SECTION freertos_system_calls:CODE:NOROOT(2)
THUMB
/*-----------------------------------------------------------*/
#include "FreeRTOSConfig.h"
#include "mpu_syscall_numbers.h"
#ifndef configUSE_MPU_WRAPPERS_V1
#define configUSE_MPU_WRAPPERS_V1 0
#endif
/*-----------------------------------------------------------*/
#if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
PUBLIC MPU_xTaskDelayUntil
MPU_xTaskDelayUntil:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskDelayUntil_Unpriv
MPU_xTaskDelayUntil_Priv:
pop {r0, r1}
b MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntil_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskDelayUntil
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskAbortDelay
MPU_xTaskAbortDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskAbortDelay_Unpriv
MPU_xTaskAbortDelay_Priv:
pop {r0, r1}
b MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskAbortDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskDelay
MPU_vTaskDelay:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskDelay_Unpriv
MPU_vTaskDelay_Priv:
pop {r0, r1}
b MPU_vTaskDelayImpl
MPU_vTaskDelay_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskDelay
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskPriorityGet
MPU_uxTaskPriorityGet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskPriorityGet_Unpriv
MPU_uxTaskPriorityGet_Priv:
pop {r0, r1}
b MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskPriorityGet
/*-----------------------------------------------------------*/
PUBLIC MPU_eTaskGetState
MPU_eTaskGetState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_eTaskGetState_Unpriv
MPU_eTaskGetState_Priv:
pop {r0, r1}
b MPU_eTaskGetStateImpl
MPU_eTaskGetState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_eTaskGetState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskGetInfo
MPU_vTaskGetInfo:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskGetInfo_Unpriv
MPU_vTaskGetInfo_Priv:
pop {r0, r1}
b MPU_vTaskGetInfoImpl
MPU_vTaskGetInfo_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskGetInfo
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetIdleTaskHandle
MPU_xTaskGetIdleTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetIdleTaskHandle_Unpriv
MPU_xTaskGetIdleTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetIdleTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSuspend
MPU_vTaskSuspend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSuspend_Unpriv
MPU_vTaskSuspend_Priv:
pop {r0, r1}
b MPU_vTaskSuspendImpl
MPU_vTaskSuspend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSuspend
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskResume
MPU_vTaskResume:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskResume_Unpriv
MPU_vTaskResume_Priv:
pop {r0, r1}
b MPU_vTaskResumeImpl
MPU_vTaskResume_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskResume
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetTickCount
MPU_xTaskGetTickCount:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetTickCount_Unpriv
MPU_xTaskGetTickCount_Priv:
pop {r0, r1}
b MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCount_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetTickCount
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetNumberOfTasks
MPU_uxTaskGetNumberOfTasks:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetNumberOfTasks_Unpriv
MPU_uxTaskGetNumberOfTasks_Priv:
pop {r0, r1}
b MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasks_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetNumberOfTasks
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimeCounter
MPU_ulTaskGetRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimeCounter_Unpriv
MPU_ulTaskGetRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetRunTimePercent
MPU_ulTaskGetRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetRunTimePercent_Unpriv
MPU_ulTaskGetRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimePercent
MPU_ulTaskGetIdleRunTimePercent:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimePercent_Unpriv
MPU_ulTaskGetIdleRunTimePercent_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercent_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimePercent
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGetIdleRunTimeCounter
MPU_ulTaskGetIdleRunTimeCounter:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGetIdleRunTimeCounter_Unpriv
MPU_ulTaskGetIdleRunTimeCounter_Priv:
pop {r0, r1}
b MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounter_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGetIdleRunTimeCounter
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetApplicationTaskTag
MPU_vTaskSetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetApplicationTaskTag_Unpriv
MPU_vTaskSetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetApplicationTaskTag
MPU_xTaskGetApplicationTaskTag:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetApplicationTaskTag_Unpriv
MPU_xTaskGetApplicationTaskTag_Priv:
pop {r0, r1}
b MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTag_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetApplicationTaskTag
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetThreadLocalStoragePointer
MPU_vTaskSetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetThreadLocalStoragePointer_Unpriv
MPU_vTaskSetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTaskGetThreadLocalStoragePointer
MPU_pvTaskGetThreadLocalStoragePointer:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTaskGetThreadLocalStoragePointer_Unpriv
MPU_pvTaskGetThreadLocalStoragePointer_Priv:
pop {r0, r1}
b MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointer_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetSystemState
MPU_uxTaskGetSystemState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetSystemState_Unpriv
MPU_uxTaskGetSystemState_Priv:
pop {r0, r1}
b MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetSystemState
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark
MPU_uxTaskGetStackHighWaterMark:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark_Unpriv
MPU_uxTaskGetStackHighWaterMark_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMark_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTaskGetStackHighWaterMark2
MPU_uxTaskGetStackHighWaterMark2:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTaskGetStackHighWaterMark2_Unpriv
MPU_uxTaskGetStackHighWaterMark2_Priv:
pop {r0, r1}
b MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTaskGetStackHighWaterMark2
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetCurrentTaskHandle
MPU_xTaskGetCurrentTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetCurrentTaskHandle_Unpriv
MPU_xTaskGetCurrentTaskHandle_Priv:
pop {r0, r1}
b MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetCurrentTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGetSchedulerState
MPU_xTaskGetSchedulerState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGetSchedulerState_Unpriv
MPU_xTaskGetSchedulerState_Priv:
pop {r0, r1}
b MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGetSchedulerState
/*-----------------------------------------------------------*/
PUBLIC MPU_vTaskSetTimeOutState
MPU_vTaskSetTimeOutState:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTaskSetTimeOutState_Unpriv
MPU_vTaskSetTimeOutState_Priv:
pop {r0, r1}
b MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutState_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTaskSetTimeOutState
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskCheckForTimeOut
MPU_xTaskCheckForTimeOut:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskCheckForTimeOut_Unpriv
MPU_xTaskCheckForTimeOut_Priv:
pop {r0, r1}
b MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOut_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskCheckForTimeOut
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyEntry
MPU_xTaskGenericNotifyEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotify_Unpriv
MPU_xTaskGenericNotify_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotify_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotify
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyWaitEntry
MPU_xTaskGenericNotifyWaitEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyWait_Unpriv
MPU_xTaskGenericNotifyWait_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWait_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyWait
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyTake
MPU_ulTaskGenericNotifyTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyTake_Unpriv
MPU_ulTaskGenericNotifyTake_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xTaskGenericNotifyStateClear
MPU_xTaskGenericNotifyStateClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTaskGenericNotifyStateClear_Unpriv
MPU_xTaskGenericNotifyStateClear_Priv:
pop {r0, r1}
b MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTaskGenericNotifyStateClear
/*-----------------------------------------------------------*/
PUBLIC MPU_ulTaskGenericNotifyValueClear
MPU_ulTaskGenericNotifyValueClear:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_ulTaskGenericNotifyValueClear_Unpriv
MPU_ulTaskGenericNotifyValueClear_Priv:
pop {r0, r1}
b MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClear_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_ulTaskGenericNotifyValueClear
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGenericSend
MPU_xQueueGenericSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGenericSend_Unpriv
MPU_xQueueGenericSend_Priv:
pop {r0, r1}
b MPU_xQueueGenericSendImpl
MPU_xQueueGenericSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGenericSend
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueMessagesWaiting
MPU_uxQueueMessagesWaiting:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueMessagesWaiting_Unpriv
MPU_uxQueueMessagesWaiting_Priv:
pop {r0, r1}
b MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaiting_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueMessagesWaiting
/*-----------------------------------------------------------*/
PUBLIC MPU_uxQueueSpacesAvailable
MPU_uxQueueSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxQueueSpacesAvailable_Unpriv
MPU_uxQueueSpacesAvailable_Priv:
pop {r0, r1}
b MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxQueueSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueReceive
MPU_xQueueReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueReceive_Unpriv
MPU_xQueueReceive_Priv:
pop {r0, r1}
b MPU_xQueueReceiveImpl
MPU_xQueueReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueuePeek
MPU_xQueuePeek:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueuePeek_Unpriv
MPU_xQueuePeek_Priv:
pop {r0, r1}
b MPU_xQueuePeekImpl
MPU_xQueuePeek_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueuePeek
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSemaphoreTake
MPU_xQueueSemaphoreTake:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSemaphoreTake_Unpriv
MPU_xQueueSemaphoreTake_Priv:
pop {r0, r1}
b MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTake_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSemaphoreTake
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGetMutexHolder
MPU_xQueueGetMutexHolder:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGetMutexHolder_Unpriv
MPU_xQueueGetMutexHolder_Priv:
pop {r0, r1}
b MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolder_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGetMutexHolder
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueTakeMutexRecursive
MPU_xQueueTakeMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueTakeMutexRecursive_Unpriv
MPU_xQueueTakeMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueTakeMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueGiveMutexRecursive
MPU_xQueueGiveMutexRecursive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueGiveMutexRecursive_Unpriv
MPU_xQueueGiveMutexRecursive_Priv:
pop {r0, r1}
b MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueGiveMutexRecursive
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueSelectFromSet
MPU_xQueueSelectFromSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueSelectFromSet_Unpriv
MPU_xQueueSelectFromSet_Priv:
pop {r0, r1}
b MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueSelectFromSet
/*-----------------------------------------------------------*/
PUBLIC MPU_xQueueAddToSet
MPU_xQueueAddToSet:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xQueueAddToSet_Unpriv
MPU_xQueueAddToSet_Priv:
pop {r0, r1}
b MPU_xQueueAddToSetImpl
MPU_xQueueAddToSet_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xQueueAddToSet
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueAddToRegistry
MPU_vQueueAddToRegistry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueAddToRegistry_Unpriv
MPU_vQueueAddToRegistry_Priv:
pop {r0, r1}
b MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistry_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueAddToRegistry
/*-----------------------------------------------------------*/
PUBLIC MPU_vQueueUnregisterQueue
MPU_vQueueUnregisterQueue:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vQueueUnregisterQueue_Unpriv
MPU_vQueueUnregisterQueue_Priv:
pop {r0, r1}
b MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueue_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vQueueUnregisterQueue
/*-----------------------------------------------------------*/
PUBLIC MPU_pcQueueGetName
MPU_pcQueueGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcQueueGetName_Unpriv
MPU_pcQueueGetName_Priv:
pop {r0, r1}
b MPU_pcQueueGetNameImpl
MPU_pcQueueGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcQueueGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_pvTimerGetTimerID
MPU_pvTimerGetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pvTimerGetTimerID_Unpriv
MPU_pvTimerGetTimerID_Priv:
pop {r0, r1}
b MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pvTimerGetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetTimerID
MPU_vTimerSetTimerID:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetTimerID_Unpriv
MPU_vTimerSetTimerID_Priv:
pop {r0, r1}
b MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerID_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetTimerID
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerIsTimerActive
MPU_xTimerIsTimerActive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerIsTimerActive_Unpriv
MPU_xTimerIsTimerActive_Priv:
pop {r0, r1}
b MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerIsTimerActive
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetTimerDaemonTaskHandle
MPU_xTimerGetTimerDaemonTaskHandle:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetTimerDaemonTaskHandle_Unpriv
MPU_xTimerGetTimerDaemonTaskHandle_Priv:
pop {r0, r1}
b MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandle_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGenericCommandFromTaskEntry
MPU_xTimerGenericCommandFromTaskEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGenericCommandFromTask_Unpriv
MPU_xTimerGenericCommandFromTask_Priv:
pop {r0, r1}
b MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTask_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGenericCommandFromTask
/*-----------------------------------------------------------*/
PUBLIC MPU_pcTimerGetName
MPU_pcTimerGetName:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_pcTimerGetName_Unpriv
MPU_pcTimerGetName_Priv:
pop {r0, r1}
b MPU_pcTimerGetNameImpl
MPU_pcTimerGetName_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_pcTimerGetName
/*-----------------------------------------------------------*/
PUBLIC MPU_vTimerSetReloadMode
MPU_vTimerSetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vTimerSetReloadMode_Unpriv
MPU_vTimerSetReloadMode_Priv:
pop {r0, r1}
b MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vTimerSetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetReloadMode
MPU_xTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetReloadMode_Unpriv
MPU_xTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_uxTimerGetReloadMode
MPU_uxTimerGetReloadMode:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxTimerGetReloadMode_Unpriv
MPU_uxTimerGetReloadMode_Priv:
pop {r0, r1}
b MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadMode_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxTimerGetReloadMode
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetPeriod
MPU_xTimerGetPeriod:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetPeriod_Unpriv
MPU_xTimerGetPeriod_Priv:
pop {r0, r1}
b MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriod_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetPeriod
/*-----------------------------------------------------------*/
PUBLIC MPU_xTimerGetExpiryTime
MPU_xTimerGetExpiryTime:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xTimerGetExpiryTime_Unpriv
MPU_xTimerGetExpiryTime_Priv:
pop {r0, r1}
b MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTime_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xTimerGetExpiryTime
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupWaitBitsEntry
MPU_xEventGroupWaitBitsEntry:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupWaitBits_Unpriv
MPU_xEventGroupWaitBits_Priv:
pop {r0, r1}
b MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupWaitBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupClearBits
MPU_xEventGroupClearBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupClearBits_Unpriv
MPU_xEventGroupClearBits_Priv:
pop {r0, r1}
b MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupClearBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSetBits
MPU_xEventGroupSetBits:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSetBits_Unpriv
MPU_xEventGroupSetBits_Priv:
pop {r0, r1}
b MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBits_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSetBits
/*-----------------------------------------------------------*/
PUBLIC MPU_xEventGroupSync
MPU_xEventGroupSync:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xEventGroupSync_Unpriv
MPU_xEventGroupSync_Priv:
pop {r0, r1}
b MPU_xEventGroupSyncImpl
MPU_xEventGroupSync_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xEventGroupSync
/*-----------------------------------------------------------*/
PUBLIC MPU_uxEventGroupGetNumber
MPU_uxEventGroupGetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_uxEventGroupGetNumber_Unpriv
MPU_uxEventGroupGetNumber_Priv:
pop {r0, r1}
b MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_uxEventGroupGetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_vEventGroupSetNumber
MPU_vEventGroupSetNumber:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_vEventGroupSetNumber_Unpriv
MPU_vEventGroupSetNumber_Priv:
pop {r0, r1}
b MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumber_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_vEventGroupSetNumber
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSend
MPU_xStreamBufferSend:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSend_Unpriv
MPU_xStreamBufferSend_Priv:
pop {r0, r1}
b MPU_xStreamBufferSendImpl
MPU_xStreamBufferSend_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSend
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferReceive
MPU_xStreamBufferReceive:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferReceive_Unpriv
MPU_xStreamBufferReceive_Priv:
pop {r0, r1}
b MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceive_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferReceive
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsFull
MPU_xStreamBufferIsFull:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsFull_Unpriv
MPU_xStreamBufferIsFull_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFull_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsFull
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferIsEmpty
MPU_xStreamBufferIsEmpty:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferIsEmpty_Unpriv
MPU_xStreamBufferIsEmpty_Priv:
pop {r0, r1}
b MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmpty_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferIsEmpty
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSpacesAvailable
MPU_xStreamBufferSpacesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSpacesAvailable_Unpriv
MPU_xStreamBufferSpacesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSpacesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferBytesAvailable
MPU_xStreamBufferBytesAvailable:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferBytesAvailable_Unpriv
MPU_xStreamBufferBytesAvailable_Priv:
pop {r0, r1}
b MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailable_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferBytesAvailable
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferSetTriggerLevel
MPU_xStreamBufferSetTriggerLevel:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferSetTriggerLevel_Unpriv
MPU_xStreamBufferSetTriggerLevel_Priv:
pop {r0, r1}
b MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevel_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferSetTriggerLevel
/*-----------------------------------------------------------*/
PUBLIC MPU_xStreamBufferNextMessageLengthBytes
MPU_xStreamBufferNextMessageLengthBytes:
push {r0, r1}
mrs r0, control
movs r1, #1
tst r0, r1
bne MPU_xStreamBufferNextMessageLengthBytes_Unpriv
MPU_xStreamBufferNextMessageLengthBytes_Priv:
pop {r0, r1}
b MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytes_Unpriv:
pop {r0, r1}
svc #SYSTEM_CALL_xStreamBufferNextMessageLengthBytes
/*-----------------------------------------------------------*/
/* Default weak implementations in case one is not available from
* mpu_wrappers because of config options. */
PUBWEAK MPU_xTaskDelayUntilImpl
MPU_xTaskDelayUntilImpl:
b MPU_xTaskDelayUntilImpl
PUBWEAK MPU_xTaskAbortDelayImpl
MPU_xTaskAbortDelayImpl:
b MPU_xTaskAbortDelayImpl
PUBWEAK MPU_vTaskDelayImpl
MPU_vTaskDelayImpl:
b MPU_vTaskDelayImpl
PUBWEAK MPU_uxTaskPriorityGetImpl
MPU_uxTaskPriorityGetImpl:
b MPU_uxTaskPriorityGetImpl
PUBWEAK MPU_eTaskGetStateImpl
MPU_eTaskGetStateImpl:
b MPU_eTaskGetStateImpl
PUBWEAK MPU_vTaskGetInfoImpl
MPU_vTaskGetInfoImpl:
b MPU_vTaskGetInfoImpl
PUBWEAK MPU_xTaskGetIdleTaskHandleImpl
MPU_xTaskGetIdleTaskHandleImpl:
b MPU_xTaskGetIdleTaskHandleImpl
PUBWEAK MPU_vTaskSuspendImpl
MPU_vTaskSuspendImpl:
b MPU_vTaskSuspendImpl
PUBWEAK MPU_vTaskResumeImpl
MPU_vTaskResumeImpl:
b MPU_vTaskResumeImpl
PUBWEAK MPU_xTaskGetTickCountImpl
MPU_xTaskGetTickCountImpl:
b MPU_xTaskGetTickCountImpl
PUBWEAK MPU_uxTaskGetNumberOfTasksImpl
MPU_uxTaskGetNumberOfTasksImpl:
b MPU_uxTaskGetNumberOfTasksImpl
PUBWEAK MPU_ulTaskGetRunTimeCounterImpl
MPU_ulTaskGetRunTimeCounterImpl:
b MPU_ulTaskGetRunTimeCounterImpl
PUBWEAK MPU_ulTaskGetRunTimePercentImpl
MPU_ulTaskGetRunTimePercentImpl:
b MPU_ulTaskGetRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimePercentImpl
MPU_ulTaskGetIdleRunTimePercentImpl:
b MPU_ulTaskGetIdleRunTimePercentImpl
PUBWEAK MPU_ulTaskGetIdleRunTimeCounterImpl
MPU_ulTaskGetIdleRunTimeCounterImpl:
b MPU_ulTaskGetIdleRunTimeCounterImpl
PUBWEAK MPU_vTaskSetApplicationTaskTagImpl
MPU_vTaskSetApplicationTaskTagImpl:
b MPU_vTaskSetApplicationTaskTagImpl
PUBWEAK MPU_xTaskGetApplicationTaskTagImpl
MPU_xTaskGetApplicationTaskTagImpl:
b MPU_xTaskGetApplicationTaskTagImpl
PUBWEAK MPU_vTaskSetThreadLocalStoragePointerImpl
MPU_vTaskSetThreadLocalStoragePointerImpl:
b MPU_vTaskSetThreadLocalStoragePointerImpl
PUBWEAK MPU_pvTaskGetThreadLocalStoragePointerImpl
MPU_pvTaskGetThreadLocalStoragePointerImpl:
b MPU_pvTaskGetThreadLocalStoragePointerImpl
PUBWEAK MPU_uxTaskGetSystemStateImpl
MPU_uxTaskGetSystemStateImpl:
b MPU_uxTaskGetSystemStateImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMarkImpl
MPU_uxTaskGetStackHighWaterMarkImpl:
b MPU_uxTaskGetStackHighWaterMarkImpl
PUBWEAK MPU_uxTaskGetStackHighWaterMark2Impl
MPU_uxTaskGetStackHighWaterMark2Impl:
b MPU_uxTaskGetStackHighWaterMark2Impl
PUBWEAK MPU_xTaskGetCurrentTaskHandleImpl
MPU_xTaskGetCurrentTaskHandleImpl:
b MPU_xTaskGetCurrentTaskHandleImpl
PUBWEAK MPU_xTaskGetSchedulerStateImpl
MPU_xTaskGetSchedulerStateImpl:
b MPU_xTaskGetSchedulerStateImpl
PUBWEAK MPU_vTaskSetTimeOutStateImpl
MPU_vTaskSetTimeOutStateImpl:
b MPU_vTaskSetTimeOutStateImpl
PUBWEAK MPU_xTaskCheckForTimeOutImpl
MPU_xTaskCheckForTimeOutImpl:
b MPU_xTaskCheckForTimeOutImpl
PUBWEAK MPU_xTaskGenericNotifyImpl
MPU_xTaskGenericNotifyImpl:
b MPU_xTaskGenericNotifyImpl
PUBWEAK MPU_xTaskGenericNotifyWaitImpl
MPU_xTaskGenericNotifyWaitImpl:
b MPU_xTaskGenericNotifyWaitImpl
PUBWEAK MPU_ulTaskGenericNotifyTakeImpl
MPU_ulTaskGenericNotifyTakeImpl:
b MPU_ulTaskGenericNotifyTakeImpl
PUBWEAK MPU_xTaskGenericNotifyStateClearImpl
MPU_xTaskGenericNotifyStateClearImpl:
b MPU_xTaskGenericNotifyStateClearImpl
PUBWEAK MPU_ulTaskGenericNotifyValueClearImpl
MPU_ulTaskGenericNotifyValueClearImpl:
b MPU_ulTaskGenericNotifyValueClearImpl
PUBWEAK MPU_xQueueGenericSendImpl
MPU_xQueueGenericSendImpl:
b MPU_xQueueGenericSendImpl
PUBWEAK MPU_uxQueueMessagesWaitingImpl
MPU_uxQueueMessagesWaitingImpl:
b MPU_uxQueueMessagesWaitingImpl
PUBWEAK MPU_uxQueueSpacesAvailableImpl
MPU_uxQueueSpacesAvailableImpl:
b MPU_uxQueueSpacesAvailableImpl
PUBWEAK MPU_xQueueReceiveImpl
MPU_xQueueReceiveImpl:
b MPU_xQueueReceiveImpl
PUBWEAK MPU_xQueuePeekImpl
MPU_xQueuePeekImpl:
b MPU_xQueuePeekImpl
PUBWEAK MPU_xQueueSemaphoreTakeImpl
MPU_xQueueSemaphoreTakeImpl:
b MPU_xQueueSemaphoreTakeImpl
PUBWEAK MPU_xQueueGetMutexHolderImpl
MPU_xQueueGetMutexHolderImpl:
b MPU_xQueueGetMutexHolderImpl
PUBWEAK MPU_xQueueTakeMutexRecursiveImpl
MPU_xQueueTakeMutexRecursiveImpl:
b MPU_xQueueTakeMutexRecursiveImpl
PUBWEAK MPU_xQueueGiveMutexRecursiveImpl
MPU_xQueueGiveMutexRecursiveImpl:
b MPU_xQueueGiveMutexRecursiveImpl
PUBWEAK MPU_xQueueSelectFromSetImpl
MPU_xQueueSelectFromSetImpl:
b MPU_xQueueSelectFromSetImpl
PUBWEAK MPU_xQueueAddToSetImpl
MPU_xQueueAddToSetImpl:
b MPU_xQueueAddToSetImpl
PUBWEAK MPU_vQueueAddToRegistryImpl
MPU_vQueueAddToRegistryImpl:
b MPU_vQueueAddToRegistryImpl
PUBWEAK MPU_vQueueUnregisterQueueImpl
MPU_vQueueUnregisterQueueImpl:
b MPU_vQueueUnregisterQueueImpl
PUBWEAK MPU_pcQueueGetNameImpl
MPU_pcQueueGetNameImpl:
b MPU_pcQueueGetNameImpl
PUBWEAK MPU_pvTimerGetTimerIDImpl
MPU_pvTimerGetTimerIDImpl:
b MPU_pvTimerGetTimerIDImpl
PUBWEAK MPU_vTimerSetTimerIDImpl
MPU_vTimerSetTimerIDImpl:
b MPU_vTimerSetTimerIDImpl
PUBWEAK MPU_xTimerIsTimerActiveImpl
MPU_xTimerIsTimerActiveImpl:
b MPU_xTimerIsTimerActiveImpl
PUBWEAK MPU_xTimerGetTimerDaemonTaskHandleImpl
MPU_xTimerGetTimerDaemonTaskHandleImpl:
b MPU_xTimerGetTimerDaemonTaskHandleImpl
PUBWEAK MPU_xTimerGenericCommandFromTaskImpl
MPU_xTimerGenericCommandFromTaskImpl:
b MPU_xTimerGenericCommandFromTaskImpl
PUBWEAK MPU_pcTimerGetNameImpl
MPU_pcTimerGetNameImpl:
b MPU_pcTimerGetNameImpl
PUBWEAK MPU_vTimerSetReloadModeImpl
MPU_vTimerSetReloadModeImpl:
b MPU_vTimerSetReloadModeImpl
PUBWEAK MPU_xTimerGetReloadModeImpl
MPU_xTimerGetReloadModeImpl:
b MPU_xTimerGetReloadModeImpl
PUBWEAK MPU_uxTimerGetReloadModeImpl
MPU_uxTimerGetReloadModeImpl:
b MPU_uxTimerGetReloadModeImpl
PUBWEAK MPU_xTimerGetPeriodImpl
MPU_xTimerGetPeriodImpl:
b MPU_xTimerGetPeriodImpl
PUBWEAK MPU_xTimerGetExpiryTimeImpl
MPU_xTimerGetExpiryTimeImpl:
b MPU_xTimerGetExpiryTimeImpl
PUBWEAK MPU_xEventGroupWaitBitsImpl
MPU_xEventGroupWaitBitsImpl:
b MPU_xEventGroupWaitBitsImpl
PUBWEAK MPU_xEventGroupClearBitsImpl
MPU_xEventGroupClearBitsImpl:
b MPU_xEventGroupClearBitsImpl
PUBWEAK MPU_xEventGroupSetBitsImpl
MPU_xEventGroupSetBitsImpl:
b MPU_xEventGroupSetBitsImpl
PUBWEAK MPU_xEventGroupSyncImpl
MPU_xEventGroupSyncImpl:
b MPU_xEventGroupSyncImpl
PUBWEAK MPU_uxEventGroupGetNumberImpl
MPU_uxEventGroupGetNumberImpl:
b MPU_uxEventGroupGetNumberImpl
PUBWEAK MPU_vEventGroupSetNumberImpl
MPU_vEventGroupSetNumberImpl:
b MPU_vEventGroupSetNumberImpl
PUBWEAK MPU_xStreamBufferSendImpl
MPU_xStreamBufferSendImpl:
b MPU_xStreamBufferSendImpl
PUBWEAK MPU_xStreamBufferReceiveImpl
MPU_xStreamBufferReceiveImpl:
b MPU_xStreamBufferReceiveImpl
PUBWEAK MPU_xStreamBufferIsFullImpl
MPU_xStreamBufferIsFullImpl:
b MPU_xStreamBufferIsFullImpl
PUBWEAK MPU_xStreamBufferIsEmptyImpl
MPU_xStreamBufferIsEmptyImpl:
b MPU_xStreamBufferIsEmptyImpl
PUBWEAK MPU_xStreamBufferSpacesAvailableImpl
MPU_xStreamBufferSpacesAvailableImpl:
b MPU_xStreamBufferSpacesAvailableImpl
PUBWEAK MPU_xStreamBufferBytesAvailableImpl
MPU_xStreamBufferBytesAvailableImpl:
b MPU_xStreamBufferBytesAvailableImpl
PUBWEAK MPU_xStreamBufferSetTriggerLevelImpl
MPU_xStreamBufferSetTriggerLevelImpl:
b MPU_xStreamBufferSetTriggerLevelImpl
PUBWEAK MPU_xStreamBufferNextMessageLengthBytesImpl
MPU_xStreamBufferNextMessageLengthBytesImpl:
b MPU_xStreamBufferNextMessageLengthBytesImpl
/*-----------------------------------------------------------*/
#endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
END
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