repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
xem/nes | 1,491 | nes-test-roms/instr_misc/source/common/build_rom.s | ; Builds program as iNES ROM
; Default is 16K PRG and 8K CHR ROM, NROM (0)
.if 0 ; Options to set before .include "shell.inc":
CHR_RAM=1 ; Use CHR-RAM instead of CHR-ROM
CART_WRAM=1 ; Use mapper that supports 8K WRAM in cart
CUSTOM_MAPPER=n ; Specify mapper number
.endif
.ifndef CUSTOM_MAPPER
.ifdef CART_WRAM
CUSTOM_MAPPER = 2 ; UNROM
.else
CUSTOM_MAPPER = 0 ; NROM
.endif
.endif
;;;; iNES header
.ifndef CUSTOM_HEADER
.segment "HEADER"
.byte $4E,$45,$53,26 ; "NES" EOF
.ifdef CHR_RAM
.byte 2,0 ; 32K PRG, CHR RAM
.else
.byte 2,1 ; 32K PRG, 8K CHR
.endif
.byte CUSTOM_MAPPER*$10+$01 ; vertical mirroring
.endif
.ifndef CUSTOM_VECTORS
.segment "VECTORS"
.word -1,-1,-1, nmi, reset, irq
.endif
;;;; CHR-RAM/ROM
.ifdef CHR_RAM
.define CHARS "CHARS_PRG"
.segment CHARS
ascii_chr:
.segment "CHARS_PRG_ASCII"
.align $200
.incbin "ascii.chr"
ascii_chr_end:
.else
.define CHARS "CHARS"
.segment "CHARS_ASCII"
.align $200
.incbin "ascii.chr"
.res $1800
.endif
.segment CHARS
.res $10,0
;;;; Shell
.ifndef NEED_CONSOLE
NEED_CONSOLE=1
.endif
; Move code to $C000
.segment "DMC"
.res $4000
.include "shell.s"
std_reset:
lda #0
sta PPUCTRL
sta PPUMASK
jmp run_shell
init_runtime:
.ifdef CHR_RAM
load_ascii_chr
.endif
rts
post_exit:
jsr set_final_result
jmp forever
; This helps devcart recover after running test.
; It is never executed by test ROM.
.segment "LOADER"
.incbin "devcart.bin"
.code
.align 256
|
xem/nes | 5,523 | nes-test-roms/instr_misc/source/common/console.s | ; Scrolling text console with line wrapping, 30x29 characters.
; Buffers lines for speed. Will work even if PPU doesn't
; support scrolling (until text reaches bottom). Keeps border
; along bottom in case TV cuts it off.
;
; Defers most initialization until first newline, at which
; point it clears nametable and makes palette non-black.
;
; ** ASCII font must already be in CHR, and mirroring
; must be vertical or single-screen.
.ifndef CONSOLE_COLOR
CONSOLE_COLOR = $30 ; white
.endif
console_screen_width = 32 ; if lower than 32, left-justifies
; Number of characters of margin on left and right, to avoid
; text getting cut off by common TVs. OK if either/both are 0.
console_left_margin = 1
console_right_margin = 1
console_width = console_screen_width - console_left_margin - console_right_margin
zp_byte console_pos ; 0 to console_width
zp_byte console_scroll
zp_byte console_temp
bss_res console_buf,console_width
; Initializes console
console_init:
; Flag that console hasn't been initialized
setb console_scroll,-1
setb console_pos,0
rts
; Hides console by disabling PPU rendering and blacking out
; first four entries of palette.
; Preserved: A, X, Y
console_hide:
pha
jsr console_wait_vbl_
setb PPUMASK,0
lda #$0F
jsr console_load_palette_
pla
rts
; Shows console display
; Preserved: X, Y
console_show:
pha
lda #CONSOLE_COLOR
jsr console_show_custom_color_
pla
rts
; Prints char A to console. Will not appear until
; a newline or flush occurs.
; Preserved: A, X, Y
console_print:
cmp #10
beq console_newline
sty console_temp
ldy console_pos
cpy #console_width
beq console_full_
sta console_buf,y
iny
sty console_pos
ldy console_temp
rts
; Displays current line and starts new one
; Preserved: A, X, Y
console_newline:
pha
jsr console_wait_vbl_
jsr console_flush_
jsr console_scroll_up_
setb console_pos,0
pla
rts
; Displays current line's contents without scrolling.
; Preserved: A, X, Y
console_flush:
pha
jsr console_wait_vbl_
jsr console_flush_
jsr console_apply_scroll_
pla
rts
;**** Internal routines ****
console_full_:
ldy console_temp
; Line is full
; If space, treat as newline
cmp #' '
beq console_newline
; Wrap current line at appropriate point
pha
tya
pha
jsr console_wrap_
pla
tay
pla
jmp console_print
; Inserts newline into buffer at appropriate position, leaving
; next line ready in buffer
; Preserved: X, console_temp
console_wrap_:
; Find beginning of last word
ldy #console_width
lda #' '
: dey
bmi console_newline
cmp console_buf,y
bne :-
; y = 0 to console_width-1
; Flush through current word and put remaining
; in buffer for next line
jsr console_wait_vbl_
; Time to last PPU write: 207 + 32*(26 + 10)
lda console_scroll
jsr console_set_ppuaddr_
stx console_pos ; save X
ldx #0
; Print everything before last word
: lda console_buf,x
sta PPUDATA
inx
dey
bpl :-
; x = 1 to console_width
; Move last word to beginning of buffer, and
; print spaces for rest of line
ldy #0
beq :++
: lda #' '
sta PPUDATA
lda console_buf,x
inx
sta console_buf,y
iny
: cpx #console_width
bne :--
ldx console_pos ; restore X
; Append new text after that
sty console_pos
; FALL THROUGH
; Scrolls up 8 pixels and clears one line BELOW new line
; Preserved: X, console_temp
console_scroll_up_:
; Scroll up 8 pixels
lda console_scroll
jsr console_add_8_to_scroll_
sta console_scroll
; Clear line AFTER that on screen
jsr console_add_8_to_scroll_
jsr console_set_ppuaddr_
ldy #console_width
lda #' '
: sta PPUDATA
dey
bne :-
; FALL THROUGH
; Applies current scrolling position to PPU
; Preserved: X, Y, console_temp
console_apply_scroll_:
lda #0
sta PPUADDR
sta PPUADDR
sta PPUSCROLL
lda console_scroll
jsr console_add_8_to_scroll_
jsr console_add_8_to_scroll_
sta PPUSCROLL
rts
; Sets PPU address for row
; In: A = scroll position
; Preserved: X, Y
console_set_ppuaddr_:
sta console_temp
lda #$08
asl console_temp
rol a
asl console_temp
rol a
sta PPUADDR
lda console_temp
ora #console_left_margin
sta PPUADDR
rts
; A = (A + 8) % 240
; Preserved: X, Y
console_add_8_to_scroll_:
cmp #240-8
bcc :+
adc #16-1;+1 for set carry
: adc #8
rts
console_show_custom_color_:
pha
jsr console_wait_vbl_
setb PPUMASK,PPUMASK_BG0
pla
jsr console_load_palette_
jmp console_apply_scroll_
console_load_palette_:
pha
setb PPUADDR,$3F
setb PPUADDR,$00
setb PPUDATA,$0F ; black
pla
sta PPUDATA
sta PPUDATA
sta PPUDATA
rts
; Initializes PPU if necessary, then waits for VBL
; Preserved: A, X, Y, console_temp
console_wait_vbl_:
lda console_scroll
cmp #-1
bne @already_initialized
; Deferred initialization of PPU until first use of console
; In case PPU doesn't support scrolling, start a
; couple of lines down
setb console_scroll,16
jsr console_hide
tya
pha
; Fill nametable with spaces
setb PPUADDR,$20
setb PPUADDR,$00
ldy #240
lda #' '
: sta PPUDATA
sta PPUDATA
sta PPUDATA
sta PPUDATA
dey
bne :-
; Clear attributes
lda #0
ldy #$40
: sta PPUDATA
dey
bne :-
pla
tay
jsr console_show
@already_initialized:
jmp wait_vbl_optional
; Flushes current line
; Preserved: X, Y
console_flush_:
lda console_scroll
jsr console_set_ppuaddr_
sty console_temp
; Copy line
ldy #0
beq :++
: lda console_buf,y
sta PPUDATA
iny
: cpy console_pos
bne :--
ldy console_temp
rts
|
xem/nes | 1,096 | nes-test-roms/instr_misc/source/common/text_out.s | ; Text output as expanding zero-terminated string at text_out_base
; The final exit result byte is written here
final_result = $6000
; Text output is written here as an expanding
; zero-terminated string
text_out_base = $6004
bss_res text_out_temp
zp_res text_out_addr,2
init_text_out:
ldx #0
; Put valid data first
setb text_out_base,0
lda #$80
jsr set_final_result
; Now fill in signature that tells emulator there's
; useful data there
setb text_out_base-3,$DE
setb text_out_base-2,$B0
setb text_out_base-1,$61
ldx #>text_out_base
stx text_out_addr+1
setb text_out_addr,<text_out_base
rts
; Sets final result byte in memory
set_final_result:
sta final_result
rts
; Writes character to text output
; In: A=Character to write
; Preserved: A, X, Y
write_text_out:
sty text_out_temp
; Write new terminator FIRST, then new char before it,
; in case emulator looks at string in middle of this routine.
ldy #1
pha
lda #0
sta (text_out_addr),y
dey
pla
sta (text_out_addr),y
inc text_out_addr
bne :+
inc text_out_addr+1
:
ldy text_out_temp
rts
|
xem/nes | 2,024 | nes-test-roms/instr_misc/source/common/ppu.s | ; PPU utilities
bss_res ppu_not_present
; Sets PPUADDR to w
; Preserved: X, Y
.macro set_ppuaddr w
bit PPUSTATUS
setb PPUADDR,>w
setb PPUADDR,<w
.endmacro
; Delays by no more than n scanlines
.macro delay_scanlines n
.if CLOCK_RATE <> 1789773
.error "Currently only supports NTSC"
.endif
delay ((n)*341)/3
.endmacro
; Waits for VBL then disables PPU rendering.
; Preserved: A, X, Y
disable_rendering:
pha
jsr wait_vbl_optional
setb PPUMASK,0
pla
rts
; Fills first nametable with $00
; Preserved: Y
clear_nametable:
ldx #$20
bne clear_nametable_
clear_nametable2:
ldx #$24
clear_nametable_:
lda #0
jsr fill_screen_
; Clear pattern table
ldx #64
: sta PPUDATA
dex
bne :-
rts
; Fills screen with tile A
; Preserved: A, Y
fill_screen:
ldx #$20
bne fill_screen_
; Same as fill_screen, but fills other nametable
fill_screen2:
ldx #$24
fill_screen_:
stx PPUADDR
ldx #$00
stx PPUADDR
ldx #240
: sta PPUDATA
sta PPUDATA
sta PPUDATA
sta PPUDATA
dex
bne :-
rts
; Fills palette with $0F
; Preserved: Y
clear_palette:
set_ppuaddr $3F00
ldx #$20
lda #$0F
: sta PPUDATA
dex
bne :-
; Fills OAM with $FF
; Preserved: Y
clear_oam:
lda #$FF
; Fills OAM with A
; Preserved: A, Y
fill_oam:
ldx #0
stx SPRADDR
: sta SPRDATA
dex
bne :-
rts
; Initializes wait_vbl_optional. Must be called before
; using it.
.align 32
init_wait_vbl:
; Wait for VBL flag to be set, or ~60000
; clocks (2 frames) to pass
ldy #24
ldx #1
bit PPUSTATUS
: bit PPUSTATUS
bmi @set
dex
bne :-
dey
bpl :-
@set:
; Be sure flag didn't stay set (in case
; PPUSTATUS always has high bit set)
tya
ora PPUSTATUS
sta ppu_not_present
rts
; Same as wait_vbl, but returns immediately if PPU
; isn't working or doesn't support VBL flag
; Preserved: A, X, Y
.align 16
wait_vbl_optional:
bit ppu_not_present
bmi :++
; FALL THROUGH
; Clears VBL flag then waits for it to be set.
; Preserved: A, X, Y
wait_vbl:
bit PPUSTATUS
: bit PPUSTATUS
bpl :-
: rts
|
xem/nes | 4,658 | nes-test-roms/instr_misc/source/common/shell.s | ; Common routines and runtime
; Detect inclusion loops (otherwise ca65 goes crazy)
.ifdef SHELL_INCLUDED
.error "shell.s included twice"
.end
.endif
SHELL_INCLUDED = 1
;**** Special globals ****
; Temporary variables that ANY routine might modify, so
; only use them between routine calls.
temp = <$A
temp2 = <$B
temp3 = <$C
addr = <$E
ptr = addr
.segment "NVRAM"
; Beginning of variables not cleared at startup
nvram_begin:
;**** Code segment setup ****
.segment "RODATA"
; Any user code which runs off end might end up here,
; so catch that mistake.
nop ; in case there was three-byte opcode before this
nop
jmp internal_error
; Move code to $E200 ($200 bytes for text output)
.segment "DMC"
.res $2200
; Devcart corrupts byte at $E000 when powering off
.segment "CODE"
nop
;**** Common routines ****
.include "macros.inc"
.include "neshw.inc"
.include "print.s"
.include "delay.s"
.include "crc.s"
.include "testing.s"
.ifdef NEED_CONSOLE
.include "console.s"
.else
; Stubs so code doesn't have to care whether
; console exists
console_init:
console_show:
console_hide:
console_print:
console_flush:
rts
.endif
.ifndef CUSTOM_PRINT
.include "text_out.s"
print_char_:
jsr write_text_out
jmp console_print
stop_capture:
rts
.endif
;**** Shell core ****
.ifndef CUSTOM_RESET
reset:
sei
jmp std_reset
.endif
; Sets up hardware then runs main
run_shell:
sei
cld ; unnecessary on NES, but might help on clone
ldx #$FF
txs
jsr init_shell
set_test $FF
jmp run_main
; Initializes shell
init_shell:
jsr clear_ram
jsr init_wait_vbl ; waits for VBL once here,
jsr wait_vbl_optional ; so only need to wait once more
jsr init_text_out
jsr init_testing
jsr init_runtime
jsr console_init
rts
; Runs main in consistent PPU/APU environment, then exits
; with code 0
run_main:
jsr pre_main
jsr main
lda #0
jmp exit
; Sets up environment for main to run in
pre_main:
.ifndef BUILD_NSF
jsr disable_rendering
setb PPUCTRL,0
jsr clear_palette
jsr clear_nametable
jsr clear_nametable2
jsr clear_oam
.endif
lda #$34
pha
lda #0
tax
tay
jsr wait_vbl_optional
plp
sta SNDMODE
rts
.ifndef CUSTOM_EXIT
exit:
.endif
; Reports result and ends program
std_exit:
sei
cld
ldx #$FF
txs
pha
setb SNDCHN,0
.ifndef BUILD_NSF
setb PPUCTRL,0
.endif
pla
pha
jsr report_result
;jsr clear_nvram ; TODO: was this needed for anything?
pla
jmp post_exit
; Reports final result code in A
report_result:
jsr :+
jmp play_byte
: jsr print_newline
jsr console_show
; 0: ""
cmp #1
bge :+
rts
:
; 1: "Failed"
bne :+
print_str {"Failed",newline}
rts
; n: "Failed #n"
: print_str "Failed #"
jsr print_dec
jsr print_newline
rts
;**** Other routines ****
; Reports internal error and exits program
internal_error:
print_str newline,"Internal error"
lda #255
jmp exit
.import __NVRAM_LOAD__, __NVRAM_SIZE__
; Clears $0-($100+S) and nv_ram_end-$7FF
clear_ram:
lda #0
; Main pages
tax
: sta 0,x
sta $300,x
sta $400,x
sta $500,x
sta $600,x
sta $700,x
inx
bne :-
; Stack except that above stack pointer
tsx
inx
: dex
sta $100,x
bne :-
; BSS except nvram
ldx #<__NVRAM_SIZE__
: sta __NVRAM_LOAD__,x
inx
bne :-
rts
; Clears nvram
clear_nvram:
ldx #<__NVRAM_SIZE__
beq @empty
lda #0
: dex
sta __NVRAM_LOAD__,x
bne :-
@empty:
rts
; Prints filename and newline, if available, otherwise nothing.
; Preserved: A, X, Y
print_filename:
.ifdef FILENAME_KNOWN
pha
jsr print_newline
setw addr,filename
jsr print_str_addr
jsr print_newline
pla
.endif
rts
.pushseg
.segment "RODATA"
; Filename terminated with zero byte.
filename:
.ifdef FILENAME_KNOWN
.incbin "ram:nes_temp"
.endif
.byte 0
.popseg
;**** ROM-specific ****
.ifndef BUILD_NSF
.include "ppu.s"
avoid_silent_nsf:
play_byte:
rts
; Loads ASCII font into CHR RAM
.macro load_ascii_chr
bit PPUSTATUS
setb PPUADDR,$00
setb PPUADDR,$00
setb addr,<ascii_chr
ldx #>ascii_chr
ldy #0
@page:
stx addr+1
: lda (addr),y
sta PPUDATA
iny
bne :-
inx
cpx #>ascii_chr_end
bne @page
.endmacro
; Disables interrupts and loops forever
.ifndef CUSTOM_FOREVER
forever:
sei
lda #0
sta PPUCTRL
: beq :-
.res $10,$EA ; room for code to run loader
.endif
; Default NMI
.ifndef CUSTOM_NMI
zp_byte nmi_count
nmi:
inc nmi_count
rti
; Waits for NMI. Must be using NMI handler that increments
; nmi_count, with NMI enabled.
; Preserved: X, Y
wait_nmi:
lda nmi_count
: cmp nmi_count
beq :-
rts
.endif
; Default IRQ
.ifndef CUSTOM_IRQ
irq:
bit SNDCHN ; clear APU IRQ flag
rti
.endif
.endif
|
xem/nes | 3,437 | nes-test-roms/instr_misc/source/common/delay.s | ; Delays in CPU clocks, milliseconds, etc. All routines are re-entrant
; (no global data). No routines touch X or Y during execution.
; Code generated by macros is relocatable; it contains no JMPs to itself.
zp_byte delay_temp_ ; only written to
; Delays n clocks, from 2 to 16777215
; Preserved: A, X, Y, flags
.macro delay n
.if (n) < 0 .or (n) = 1 .or (n) > 16777215
.error "Delay out of range"
.endif
delay_ (n)
.endmacro
; Delays n milliseconds (1/1000 second)
; n can range from 0 to 1100.
; Preserved: A, X, Y, flags
.macro delay_msec n
.if (n) < 0 .or (n) > 1100
.error "time out of range"
.endif
delay ((n)*CLOCK_RATE+500)/1000
.endmacro
; Delays n microseconds (1/1000000 second).
; n can range from 0 to 100000.
; Preserved: A, X, Y, flags
.macro delay_usec n
.if (n) < 0 .or (n) > 100000
.error "time out of range"
.endif
delay ((n)*((CLOCK_RATE+50)/100)+5000)/10000
.endmacro
.align 64
; Delays A clocks + overhead
; Preserved: X, Y
; Time: A+25 clocks (including JSR)
: sbc #7 ; carry set by CMP
delay_a_25_clocks:
cmp #7
bcs :- ; do multiples of 7
lsr a ; bit 0
bcs :+
: ; A=clocks/2, either 0,1,2,3
beq @zero ; 0: 5
lsr a
beq :+ ; 1: 7
bcc :+ ; 2: 9
@zero: bne :+ ; 3: 11
: rts ; (thanks to dclxvi for the algorithm)
; Delays A*256 clocks + overhead
; Preserved: X, Y
; Time: A*256+16 clocks (including JSR)
delay_256a_16_clocks:
cmp #0
bne :+
rts
delay_256a_11_clocks_:
: pha
lda #256-19-22
jsr delay_a_25_clocks
pla
clc
adc #-1
bne :-
rts
; Delays A*65536 clocks + overhead
; Preserved: X, Y
; Time: A*65536+16 clocks (including JSR)
delay_65536a_16_clocks:
cmp #0
bne :+
rts
delay_65536a_11_clocks_:
: pha
lda #256-19-22-13
jsr delay_a_25_clocks
lda #255
jsr delay_256a_11_clocks_
pla
clc
adc #-1
bne :-
rts
max_short_delay = 41
; delay_short_ macro jumps into these
.res (max_short_delay-12)/2,$EA ; NOP
delay_unrolled_:
rts
.macro delay_short_ n
.if n < 0 .or n = 1 .or n > max_short_delay
.error "Internal delay error"
.endif
.if n = 0
; nothing
.elseif n = 2
nop
.elseif n = 3
sta <delay_temp_
.elseif n = 4
nop
nop
.elseif n = 5
sta <delay_temp_
nop
.elseif n = 6
nop
nop
nop
.elseif n = 7
php
plp
.elseif n = 8
nop
nop
nop
nop
.elseif n = 9
php
plp
nop
.elseif n = 10
sta <delay_temp_
php
plp
.elseif n = 11
php
plp
nop
nop
.elseif n = 13
php
plp
nop
nop
nop
.elseif n & 1
sta <delay_temp_
jsr delay_unrolled_-((n-15)/2)
.else
jsr delay_unrolled_-((n-12)/2)
.endif
.endmacro
.macro delay_nosave_ n
; 65536+17 = maximum delay using delay_256a_11_clocks_
; 255+27 = maximum delay using delay_a_25_clocks
; 27 = minimum delay using delay_a_25_clocks
.if n > 65536+17
lda #^(n - 15)
jsr delay_65536a_11_clocks_
; +2 ensures remaining clocks is never 1
delay_nosave_ (((n - 15) & $FFFF) + 2)
.elseif n > 255+27
lda #>(n - 15)
jsr delay_256a_11_clocks_
; +2 ensures remaining clocks is never 1
delay_nosave_ (<(n - 15) + 2)
.elseif n >= 27
lda #<(n - 27)
jsr delay_a_25_clocks
.else
delay_short_ n
.endif
.endmacro
.macro delay_ n
.if n > max_short_delay
php
pha
delay_nosave_ (n - 14)
pla
plp
.else
delay_short_ n
.endif
.endmacro
|
xem/nes | 1,632 | nes-test-roms/instr_misc/source/common/crc.s | ; CRC-32 checksum calculation
zp_res checksum,4
zp_byte checksum_temp
zp_byte checksum_off_
; Turns CRC updating on/off. Allows nesting.
; Preserved: A, X, Y
crc_off:
dec checksum_off_
rts
crc_on: inc checksum_off_
beq :+
jpl internal_error ; catch unbalanced crc calls
: rts
; Initializes checksum module. Might initialize tables
; in the future.
init_crc:
jmp reset_crc
; Clears checksum and turns it on
; Preserved: X, Y
reset_crc:
lda #0
sta checksum_off_
lda #$FF
sta checksum
sta checksum + 1
sta checksum + 2
sta checksum + 3
rts
; Updates checksum with byte in A (unless disabled via crc_off)
; Preserved: A, X, Y
; Time: 357 clocks average
update_crc:
bit checksum_off_
bmi update_crc_off
update_crc_:
pha
stx checksum_temp
eor checksum
ldx #8
@bit: lsr checksum+3
ror checksum+2
ror checksum+1
ror a
bcc :+
sta checksum
lda checksum+3
eor #$ED
sta checksum+3
lda checksum+2
eor #$B8
sta checksum+2
lda checksum+1
eor #$83
sta checksum+1
lda checksum
eor #$20
: dex
bne @bit
sta checksum
ldx checksum_temp
pla
update_crc_off:
rts
; Prints checksum as 8-character hex value
print_crc:
jsr crc_off
; Print complement
ldx #3
: lda checksum,x
eor #$FF
jsr print_hex
dex
bpl :-
jmp crc_on
; EQ if checksum matches CRC
; Out: A=0 and EQ if match, A>0 and NE if different
; Preserved: X, Y
.macro is_crc crc
jsr_with_addr is_crc_,{.dword crc}
.endmacro
is_crc_:
tya
pha
; Compare with complemented checksum
ldy #3
: lda (ptr),y
sec
adc checksum,y
bne @wrong
dey
bpl :-
pla
tay
lda #0
rts
@wrong:
pla
tay
lda #1
rts
|
xen2/SharpLang | 3,638 | src/SharpLang.Runtime/coreclr/pal/tests/palsuite/composite/synchronization/nativecs_interlocked/hpitinterlock.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
/*++
Module Name:
interlock.s
Abstract:
Implementation of Interlocked functions (32 and 64 bits) for the HPUX/Itanium
platform. These functions are processor dependent.
See the i386 implementations for more information.
--*/
.file "interlock.s"
.section .text, "ax", "progbits"
.align 16
.global InterlockedExchangeAdd#
.proc InterlockedExchangeAdd#
InterlockedExchangeAdd:
.body
ld4.nt1 r8 = [r32]
;;
Iea10:
mov ar.ccv = r8
add r15 = r33, r8
mov r14 = r8
;;
cmpxchg4.acq r8 = [r32], r15, ar.ccv
;;
cmp.ne p6,p7 = r8, r14 // check if the target changes?
(p6)br.cond.spnt.few Iea10 // if yes, go back to do it again
(p7)br.ret.sptk.clr b0
;;
.endp InterlockedExchangeAdd#
.align 16
.global InterlockedIncrement#
.proc InterlockedIncrement#
InterlockedIncrement:
.body
fetchadd4.acq r8 = [r32], 1
;;
adds r8 = 1, r8
br.ret.sptk b0
;;
.endp InterlockedIncrement#
.align 16
.global InterlockedIncrement64#
.proc InterlockedIncrement64#
InterlockedIncrement64:
.body
fetchadd8.acq r8 = [r32], 1
;;
adds r8 = 1, r8
br.ret.sptk b0
;;
.endp InterlockedIncrement64#
.align 16
.global InterlockedDecrement#
.proc InterlockedDecrement#
InterlockedDecrement:
.body
fetchadd4.acq r8 = [r32], -1
;;
adds r8 = -1, r8
br.ret.sptk b0
;;
.endp InterlockedDecrement#
.align 16
.global InterlockedDecrement64#
.proc InterlockedDecrement64#
InterlockedDecrement64:
.body
fetchadd8.acq r8 = [r32], -1
;;
adds r8 = -1, r8
br.ret.sptk b0
;;
.endp InterlockedDecrement64#
.align 16
.global InterlockedExchange#
.proc InterlockedExchange#
InterlockedExchange:
.body
mf
zxt4 r33 = r33 // sanitize the upper 32 bits
;;
xchg4 r8 = [r32], r33
br.ret.sptk b0
;;
.endp InterlockedExchange#
.align 16
.global InterlockedExchange64#
.proc InterlockedExchange64#
InterlockedExchange64:
.body
mf
xchg8 r8 = [r32], r33
br.ret.sptk b0
;;
.endp InterlockedExchange64#
.align 16
.global InterlockedCompareExchange#
.proc InterlockedCompareExchange#
InterlockedCompareExchange:
.body
mf
zxt4 r33 = r33 // sanitize the upper 32 bits
zxt4 r34 = r34 // sanitize the upper 32 bits
;;
mov ar.ccv = r34
;;
cmpxchg4.acq r8 = [r32], r33, ar.ccv
br.ret.sptk.clr b0
;;
.endp InterlockedCompareExchange#
.align 16
.global InterlockedCompareExchange64#
.proc InterlockedCompareExchange64#
InterlockedCompareExchange64:
.body
mf
mov ar.ccv = r34
;;
cmpxchg8.acq r8 = [r32], r33, ar.ccv
br.ret.sptk.clr b0
;;
.endp InterlockedCompareExchange64#
/*++
DBG_DebugBreak is extracted from DbgBreakPoint function
in debugstb.s from win64.
--*/
BREAKPOINT_STOP = 0x80016
.align 16
.global DBG_DebugBreak#
.proc DBG_DebugBreak#
DBG_DebugBreak:
.body
flushrs
;;
break.i BREAKPOINT_STOP
br.ret.sptk.clr b0
;;
.endp DBG_DebugBreak#
.align 16
.global MemoryBarrier#
.proc MemoryBarrier#
MemoryBarrier:
.body
mf
br.ret.sptk.clr b0
;;
.endp MemoryBarrier#
|
xen2/SharpLang | 1,492 | src/SharpLang.Runtime/coreclr/pal/tests/palsuite/composite/synchronization/nativecs_interlocked/sparcinterloc.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
/*++
Module Name:
interlock.s
Abstract:
Implementation of Interlocked functions for the SPARC
platform. These functions are processor dependent.
See the i386 implementations for more information.
--*/
// A handy macro for declaring a public function
// The first argument is the function name.
#define ASMFUNC(n,typename); \
.align 4 ; \
.global n ; \
.type n,typename ; \
n: ;
.text
ASMFUNC(InterlockedIncrement,#function)
ld [%o0], %o1
loopI:
mov %o1, %o2
add %o1, 1, %o1
cas [%o0], %o2, %o1
cmp %o2, %o1
bne loopI
nop
retl
add %o1, 1, %o0
ASMFUNC(InterlockedDecrement,#function)
ld [%o0], %o1
loopD:
mov %o1, %o2
sub %o1, 1, %o1
cas [%o0], %o2, %o1
cmp %o2, %o1
bne loopD
nop
retl
sub %o1, 1, %o0
ASMFUNC(InterlockedExchange,#function)
swap [%o0], %o1
retl
mov %o1, %o0
ASMFUNC(InterlockedCompareExchange,#function)
cas [%o0], %o2, %o1
retl
mov %o1, %o0
ASMFUNC(MemoryBarrier,#function)
// ROTORTODO: SPARC
retl
nop
ASMFUNC(YieldProcessor,#function)
retl
nop
|
xen2/SharpLang | 3,738 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/dispatchexceptionwrapper.S | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
// ==++==
//
// ==--==
//
// Implementation of the PAL_DispatchExceptionWrapper that is
// interposed between a function that caused a hardware fault
// and PAL_DispatchException that throws an SEH exception for
// the fault, to make the stack unwindable.
//
// On Mac OS X 10.6, the unwinder fails to operate correctly
// on our original int3; int3 body. The workaround is to
// increase the size of the function to include a call statement,
// even though it will never be executed.
#if defined(__x86_64__)
#define PAL_DISPATCHEXCEPTION __Z21PAL_DispatchExceptionmmmmmmP8_CONTEXTP17_EXCEPTION_RECORD
#else //!defined(_AMD64_)
#define PAL_DISPATCHEXCEPTION __Z21PAL_DispatchExceptionP8_CONTEXTP17_EXCEPTION_RECORD
#endif // defined(_AMD64_)
.text
.globl __Z21PAL_DispatchExceptionP8_CONTEXTP17_EXCEPTION_RECORD
.globl _PAL_DispatchExceptionWrapper
_PAL_DispatchExceptionWrapper:
LBegin:
int3
call PAL_DISPATCHEXCEPTION
int3
LEnd:
//
// PAL_DispatchExceptionWrapper will never be called; it only serves
// to be referenced from a stack frame on the faulting thread. Its
// unwinding behavior is equivalent to any standard function having
// an ebp frame. The FDE below is analogous to the one generated
// by "g++ -S" for the following source file.
//
// --- snip ---
// struct CONTEXT
// {
// char reserved[716];
// };
//
// struct EXCEPTION_RECORD
// {
// char reserved[80];
// };
//
// void PAL_DispatchException(CONTEXT *pContext, EXCEPTION_RECORD *pExceptionRecord);
//
// extern "C" void PAL_DispatchExceptionWrapper()
// {
// CONTEXT Context;
// EXCEPTION_RECORD ExceptionRecord;
// PAL_DispatchException(&Context, &ExceptionRecord);
// }
// --- snip ---
//
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
CIE_DispatchExceptionPersonality:
.long LECIE1-LSCIE1
LSCIE1:
.long 0x0
.byte 0x1
.ascii "zLR\0"
.byte 0x1
#ifdef BIT64
.byte 0x78 // data_align: -8
.byte 16 // return address register: rip
#else // BIT64
.byte 0x7c // data_align: -4
.byte 0x8 // return address register: eip
#endif // BIT64 else
.byte 0x2
.byte 0x10
.byte 0x10
.byte 0xc // DW_CFA_def_cfa
#ifdef BIT64
.byte 0x7 // operand1 = rsp
.byte 0x8 // operand2 = offset 8
.byte 0x80 | 16 // DW_CFA_offset of return address register
#else // BIT64
.byte 0x5 // operand1 = esp
.byte 0x4 // operand2 = offset 4
.byte 0x80 | 8 // DW_CFA_offset of return address register
#endif // BIT64 else
.byte 0x1 // operand1 = 1 word
.align 2
LECIE1:
.globl _PAL_DispatchExceptionWrapper.eh
_PAL_DispatchExceptionWrapper.eh:
LSFDE1:
.set LLFDE1,LEFDE1-LASFDE1
.set LLength,LEnd-LBegin
.long LLFDE1
LASFDE1:
.long LASFDE1-CIE_DispatchExceptionPersonality
#ifdef BIT64
.quad LBegin-.
.quad LLength
.byte 0x8
.quad 0x0
#else // BIT64
.long LBegin-.
.long LLength
.byte 0x4
.long 0x0
#endif // BIT64 else
.byte 0xe // DW_CFA_def_cfa_offset
#ifdef BIT64
.byte 0x10
.byte 0x80 | 6 // DW_CFA_offset rbp
#else // BIT64
.byte 0x8
.byte 0x80 | 4 // DW_CFA_offset ebp
#endif // BIT64 else
.byte 0x2
.byte 0xd // DW_CFA_def_cfa_register
#ifdef BIT64
.byte 6 // operand1 = rbp
#else // BIT64
.byte 4 // operand1 = ebp
#endif // BIT64
.align 2
LEFDE1:
|
xen2/SharpLang | 5,999 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/tryexcept.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
// ==++==
//
// ==--==
//
// Implementation of the PAL_TryExcept primitive for MSVC-style
// exception handling.
//
#define ALIGN_UP(x) ((x + 15) & ~15)
#ifdef BIT64
// GCC follows the AMD64 ABI calling convention which is considerably different from the Microsoft AMD64 calling convention.
//
// With MSVC, the first four arguments are passed in RCX, RDX, R8, R9 and the remaining on the stack.
// With GCC, the first six arguments are passed in RDI, RSI, RDX, RCX, R8, R9 and the remaining on the stack.
// => Size of the total number of arguments PAL_TryExcept takes (32 bytes) +
// => 1 stack slot (8 bytes) to preserve "actions" flags when PAL_SEHPersonalityRoutine is invoked during unwind copies
// data to the stack location before fixing the context to invoke PAL_CallRunHandler +
// => 1 stack slot (8 bytes) to ensure stack is 16bytes aligned.
//
// Hence, the 48 bytes frame size.
#define SIZEOF_ARG_REGISTERS 48
#define FRAME_SIZE ALIGN_UP(SIZEOF_ARG_REGISTERS)
.text
.globl _PAL_TryExcept
_PAL_TryExcept:
LFB7:
push %rbp
LCFI0:
mov %rsp, %rbp
LCFI1:
sub $FRAME_SIZE, %rsp
mov %rdi, (%rsp) // Move the Body address to the stack
mov %rsi, 8(%rsp) // Move the Filter address to the stack
mov %rdx, 16(%rsp) // Move pvParam (i.e. HandlerData) to the stack
mov %rcx, 24(%rsp) // Move pfExecuteHandler value to the stack
mov %rdi, %r9 // Move the body address to r9
mov %rdx, %rdi // Move the HandlerData argument to RDI - this will serve as the first (and only) argument passed to the __try block body below
LEHB0:
call *%r9 // ..and invoke the body of the __try block
LEHE0:
xor %rax, %rax // NULL, meaning "do not run handler"
jmp Lepilog
.globl _PAL_CallRunHandler
_PAL_CallRunHandler:
// Note: First two args (actions and exceptionObject) have already been
// setup by PAL_SEHPersonalityRoutine's cleanup phase handling. They are at
// RSP+32 and RSP+48 respectively.
//
// Prepare the arguments to be passed to PAL_RunHandler.
mov 32(%rsp), %rdi // actions
mov 40(%rsp), %rsi // exceptionObject
mov 8(%rsp), %rdx // filter
mov 16(%rsp), %rcx // param
mov 24(%rsp), %r8 // pfExecuteHandler
call _PAL_RunHandler
Lepilog:
leave
ret
LFE7:
#else // BIT64
#define SIZEOF_ARG_REGISTERS 20
#define FRAME_SIZE ALIGN_UP(8 + SIZEOF_ARG_REGISTERS) - 8
.text
.globl _PAL_TryExcept
_PAL_TryExcept:
LFB7:
pushl %ebp
LCFI0:
movl %esp, %ebp
LCFI1:
subl $FRAME_SIZE, %esp
movl 16(%ebp), %eax // param
movl %eax, (%esp)
LEHB0:
call *8(%ebp) // body
LEHE0:
xor %eax, %eax // NULL, meaning "do not run handler"
jmp Lepilog
.globl _PAL_CallRunHandler
_PAL_CallRunHandler:
// note: first two args already set when we get here
mov 12(%ebp), %eax // filter
mov %eax, 8(%esp)
mov 16(%ebp), %eax // param
mov %eax, 12(%esp)
mov 20(%ebp), %eax // pfExecuteHandler
mov %eax, 16(%esp)
call L_PAL_RunHandler$stub
Lepilog:
leave
ret
LFE7:
#endif // BIT64 else
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
CIE_SEHPersonality:
.long LECIE1-LSCIE1
LSCIE1:
.long 0x0
.byte 0x1
#ifdef BIT64
.ascii "zPLR\0"
.byte 0x1
.byte 0x78 // data_align: -8
.byte 16 // return address register: rip
.byte 0x7
.byte 0x9b
.long _PAL_SEHPersonalityRoutine+4@GOTPCREL
.byte 0x10
.byte 0x10
.byte 0xc // DW_CFA_def_cfa
.byte 0x7 // operand1 = rsp
.byte 0x8 // operand2 = offset 8
.byte 0x80 | 16 // DW_CFA_offset of return address register
.byte 0x1 // operand1 = 1 word
.align 2
#else // BIT64
.ascii "zPLR\0"
.byte 0x1
.byte 0x7c // data_align: -4
.byte 0x8 // return address register: eip
.byte 0x7
.byte 0x9b
.long L_PAL_SEHPersonalityRoutine$non_lazy_ptr-.
.byte 0x10
.byte 0x10
.byte 0xc // DW_CFA_def_cfa
.byte 0x5 // operand1 = esp
.byte 0x4 // operand2 = offset 4
.byte 0x80 | 8 // DW_CFA_offset of return address register
.byte 0x1 // operand1 = 1 word
.align 2
#endif // BIT64 else
LECIE1:
.globl _PAL_TryExcept.eh
_PAL_TryExcept.eh:
LSFDE1:
.set LLFDE1,LEFDE1-LASFDE1
.set LFL7,LFE7-LFB7
.long LLFDE1
LASFDE1:
.long LASFDE1-CIE_SEHPersonality
#ifdef BIT64
.quad LFB7-.
.quad LFL7
.byte 0x8
.quad 0x0
.byte 0x4 // DW_CFA_advance_loc4
#else // BIT64
.long LFB7-.
.long LFL7
.byte 0x4
.long 0x0
.byte 0x4 // DW_CFA_advance_loc4
#endif // BIT64 else
.long LCFI0-LFB7
.byte 0xe // DW_CFA_def_cfa_offset
#ifdef BIT64
.byte 0x10
.byte 0x80 | 6 // DW_CFA_offset rbp
#else // BIT64
.byte 0x8
.byte 0x80 | 4 // DW_CFA_offset ebp
#endif // BIT64 else
.byte 0x2
.byte 0x4 // DW_CFA_advance_loc4
.long LCFI1-LCFI0
.byte 0xd // DW_CFA_def_cfa_register
#ifdef BIT64
.byte 6 // operand1 = rbp
.align 2
#else // BIT64
.byte 4 // operand1 = ebp
.align 2
#endif // BIT64
LEFDE1:
#ifndef BIT64
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_PAL_RunHandler$stub:
.indirect_symbol _PAL_RunHandler
hlt ; hlt ; hlt ; hlt ; hlt
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_PAL_SEHPersonalityRoutine$non_lazy_ptr:
.indirect_symbol _PAL_SEHPersonalityRoutine
.long 0
#endif // !BIT64
|
xen2/SharpLang | 6,654 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/context2.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
//
// Implementation of _CONTEXT_CaptureContext for the Intel x86 platform.
// This function is processor dependent. It is used by exception handling,
// and is always apply to the current thread.
//
#ifdef BIT64
#define CONTEXT_CONTROL 1 // SegSs, Rsp, SegCs, Rip, and EFlags
#define CONTEXT_INTEGER 2 // Rax, Rcx, Rdx, Rbx, Rbp, Rsi, Rdi, R8-R15
#define CONTEXT_SEGMENTS 4 // SegDs, SegEs, SegFs, SegGs
#define CONTEXT_FLOATING_POINT 8
#define CONTEXT_DEBUG_REGISTERS 16 // Dr0-Dr3 and Dr6-Dr7
#define CONTEXT_ContextFlags 6*8
#define CONTEXT_SegCs CONTEXT_ContextFlags+8
#define CONTEXT_SegDs CONTEXT_SegCs+2
#define CONTEXT_SegEs CONTEXT_SegDs+2
#define CONTEXT_SegFs CONTEXT_SegEs+2
#define CONTEXT_SegGs CONTEXT_SegFs+2
#define CONTEXT_SegSs CONTEXT_SegGs+2
#define CONTEXT_EFlags CONTEXT_SegSs+2
#define CONTEXT_Dr0 CONTEXT_EFlags+4
#define CONTEXT_Dr1 CONTEXT_Dr0+8
#define CONTEXT_Dr2 CONTEXT_Dr1+8
#define CONTEXT_Dr3 CONTEXT_Dr2+8
#define CONTEXT_Dr6 CONTEXT_Dr3+8
#define CONTEXT_Dr7 CONTEXT_Dr6+8
#define CONTEXT_Rax CONTEXT_Dr7+8
#define CONTEXT_Rcx CONTEXT_Rax+8
#define CONTEXT_Rdx CONTEXT_Rcx+8
#define CONTEXT_Rbx CONTEXT_Rdx+8
#define CONTEXT_Rsp CONTEXT_Rbx+8
#define CONTEXT_Rbp CONTEXT_Rsp+8
#define CONTEXT_Rsi CONTEXT_Rbp+8
#define CONTEXT_Rdi CONTEXT_Rsi+8
#define CONTEXT_R8 CONTEXT_Rdi+8
#define CONTEXT_R9 CONTEXT_R8+8
#define CONTEXT_R10 CONTEXT_R9+8
#define CONTEXT_R11 CONTEXT_R10+8
#define CONTEXT_R12 CONTEXT_R11+8
#define CONTEXT_R13 CONTEXT_R12+8
#define CONTEXT_R14 CONTEXT_R13+8
#define CONTEXT_R15 CONTEXT_R14+8
#define CONTEXT_Rip CONTEXT_R15+8
#define CONTEXT_FltSave CONTEXT_Rip+8
#define FLOATING_SAVE_AREA_SIZE 4*8+24*16+96
#define CONTEXT_Xmm0 CONTEXT_FltSave+10*16
#define CONTEXT_Xmm1 CONTEXT_Xmm0+16
#define CONTEXT_Xmm2 CONTEXT_Xmm1+16
#define CONTEXT_Xmm3 CONTEXT_Xmm2+16
#define CONTEXT_Xmm4 CONTEXT_Xmm3+16
#define CONTEXT_Xmm5 CONTEXT_Xmm4+16
#define CONTEXT_Xmm6 CONTEXT_Xmm5+16
#define CONTEXT_Xmm7 CONTEXT_Xmm6+16
#define CONTEXT_Xmm8 CONTEXT_Xmm7+16
#define CONTEXT_Xmm9 CONTEXT_Xmm8+16
#define CONTEXT_Xmm10 CONTEXT_Xmm9+16
#define CONTEXT_Xmm11 CONTEXT_Xmm10+16
#define CONTEXT_Xmm12 CONTEXT_Xmm11+16
#define CONTEXT_Xmm13 CONTEXT_Xmm12+16
#define CONTEXT_Xmm14 CONTEXT_Xmm13+16
#define CONTEXT_Xmm15 CONTEXT_Xmm14+16
#define CONTEXT_VectorRegister CONTEXT_Xmm15+16
#define CONTEXT_VectorControl CONTEXT_VectorRegister+16*26
#define CONTEXT_DebugControl CONTEXT_VectorControl+8
#define CONTEXT_LastBranchToRip CONTEXT_DebugControl+8
#define CONTEXT_LastBranchFromRip CONTEXT_LastBranchToRip+8
#define CONTEXT_LastExceptionToRip CONTEXT_LastBranchFromRip+8
#define CONTEXT_LastExceptionFromRip CONTEXT_LastExceptionToRip+8
// Incoming:
// RDI: Context*
//
.globl _CONTEXT_CaptureContext
_CONTEXT_CaptureContext:
testb $CONTEXT_INTEGER, CONTEXT_ContextFlags(%rdi)
je 0f
mov %rdi, CONTEXT_Rdi(%rdi)
mov %rsi, CONTEXT_Rsi(%rdi)
mov %rbx, CONTEXT_Rbx(%rdi)
mov %rdx, CONTEXT_Rdx(%rdi)
mov %rcx, CONTEXT_Rcx(%rdi)
mov %rax, CONTEXT_Rax(%rdi)
mov %rbp, CONTEXT_Rbp(%rdi)
mov %r8, CONTEXT_R8(%rdi)
mov %r9, CONTEXT_R9(%rdi)
mov %r10, CONTEXT_R10(%rdi)
mov %r11, CONTEXT_R11(%rdi)
mov %r12, CONTEXT_R12(%rdi)
mov %r13, CONTEXT_R13(%rdi)
mov %r14, CONTEXT_R14(%rdi)
mov %r15, CONTEXT_R15(%rdi)
jmp 1f
0:
nop
1:
testb $CONTEXT_CONTROL, CONTEXT_ContextFlags(%rdi)
je 2f
// Return address is @ RSP
mov (%rsp), %rdx
mov %rdx, CONTEXT_Rip(%rdi)
mov %cs, CONTEXT_SegCs(%rdi)
pushfq
pop %rdx
mov %edx, CONTEXT_EFlags(%rdi)
lea 8(%rsp), %rdx
mov %rdx, CONTEXT_Rsp(%rdi)
mov %ss, CONTEXT_SegSs(%rdi)
2:
// Need to double check this is producing the right result
// also that FFSXR (fast save/restore) is not turned on
// otherwise it omits the xmm registers.
testb $CONTEXT_FLOATING_POINT, CONTEXT_ContextFlags(%rdi)
je 3f
fxsave CONTEXT_FltSave(%rdi)
3:
testb $CONTEXT_DEBUG_REGISTERS, CONTEXT_ContextFlags(%rdi)
je 4f
mov %dr0, %rdx
mov %rdx, CONTEXT_Dr0(%rdi)
mov %dr1, %rdx
mov %rdx, CONTEXT_Dr1(%rdi)
mov %dr2, %rdx
mov %rdx, CONTEXT_Dr2(%rdi)
mov %dr3, %rdx
mov %rdx, CONTEXT_Dr3(%rdi)
mov %dr6, %rdx
mov %rdx, CONTEXT_Dr6(%rdi)
mov %dr7, %rdx
mov %rdx, CONTEXT_Dr7(%rdi)
4:
ret
#else
#define CONTEXT_ContextFlags 0
#define CONTEXT_FLOATING_POINT 8
#define CONTEXT_FloatSave 7*4
#define FLOATING_SAVE_AREA_SIZE 8*4+80
#define CONTEXT_Edi CONTEXT_FloatSave + FLOATING_SAVE_AREA_SIZE + 4*4
#define CONTEXT_Esi CONTEXT_Edi+4
#define CONTEXT_Ebx CONTEXT_Esi+4
#define CONTEXT_Edx CONTEXT_Ebx+4
#define CONTEXT_Ecx CONTEXT_Edx+4
#define CONTEXT_Eax CONTEXT_Ecx+4
#define CONTEXT_Ebp CONTEXT_Eax+4
#define CONTEXT_Eip CONTEXT_Ebp+4
#define CONTEXT_SegCs CONTEXT_Eip+4
#define CONTEXT_EFlags CONTEXT_SegCs+4
#define CONTEXT_Esp CONTEXT_EFlags+4
#define CONTEXT_SegSs CONTEXT_Esp+4
#define CONTEXT_EXTENDED_REGISTERS 32
#define CONTEXT_ExtendedRegisters CONTEXT_SegSs+4
#define CONTEXT_Xmm0 CONTEXT_ExtendedRegisters+160
#define CONTEXT_Xmm1 CONTEXT_Xmm0+16
#define CONTEXT_Xmm2 CONTEXT_Xmm1+16
#define CONTEXT_Xmm3 CONTEXT_Xmm2+16
#define CONTEXT_Xmm4 CONTEXT_Xmm3+16
#define CONTEXT_Xmm5 CONTEXT_Xmm4+16
#define CONTEXT_Xmm6 CONTEXT_Xmm5+16
#define CONTEXT_Xmm7 CONTEXT_Xmm6+16
.globl _CONTEXT_CaptureContext
_CONTEXT_CaptureContext:
push %eax
mov 8(%esp), %eax
mov %edi, CONTEXT_Edi(%eax)
mov %esi, CONTEXT_Esi(%eax)
mov %ebx, CONTEXT_Ebx(%eax)
mov %edx, CONTEXT_Edx(%eax)
mov %ecx, CONTEXT_Ecx(%eax)
pop %ecx
mov %ecx, CONTEXT_Eax(%eax)
mov %ebp, CONTEXT_Ebp(%eax)
mov (%esp), %edx
mov %edx, CONTEXT_Eip(%eax)
push %cs
pop %edx
mov %edx, CONTEXT_SegCs(%eax)
pushf
pop %edx
mov %edx, CONTEXT_EFlags(%eax)
lea 4(%esp), %edx
mov %edx, CONTEXT_Esp(%eax)
push %ss
pop %edx
mov %edx, CONTEXT_SegSs(%eax)
testb $CONTEXT_FLOATING_POINT, CONTEXT_ContextFlags(%eax)
je 0f
fnsave CONTEXT_FloatSave(%eax)
frstor CONTEXT_FloatSave(%eax)
0:
testb $CONTEXT_EXTENDED_REGISTERS, CONTEXT_ContextFlags(%eax)
je 2f
movdqu %xmm0, CONTEXT_Xmm0(%eax)
movdqu %xmm1, CONTEXT_Xmm1(%eax)
movdqu %xmm2, CONTEXT_Xmm2(%eax)
movdqu %xmm3, CONTEXT_Xmm3(%eax)
movdqu %xmm4, CONTEXT_Xmm4(%eax)
movdqu %xmm5, CONTEXT_Xmm5(%eax)
movdqu %xmm6, CONTEXT_Xmm6(%eax)
movdqu %xmm7, CONTEXT_Xmm7(%eax)
2:
ret
#endif
|
xen2/SharpLang | 3,990 | src/SharpLang.Runtime/coreclr/pal/src/arch/i386/runfilter.s | //
// Copyright (c) Microsoft. All rights reserved.
// Licensed under the MIT license. See LICENSE file in the project root for full license information.
//
//
// Implementation of the PAL_RunFilter primitive that allows
// to run a filter guarded by a personality routine that can
// deal with nested exceptions.
//
#define ALIGN_UP(x) ((x + 15) & ~15)
#ifdef BIT64
#define SIZEOF_ARG_REGISTERS 32
#define FRAME_SIZE ALIGN_UP(SIZEOF_ARG_REGISTERS)
.text
.globl _PAL_RunFilter
_PAL_RunFilter:
LFB7:
push %rbp
LCFI0:
mov %rsp, %rbp
LCFI1:
sub $FRAME_SIZE, %rsp
mov %rdi, (%rsp) // ExceptionPointers
mov %rsi, 8(%rsp) // DispatcherContext
mov %rdx, 16(%rsp) // pvParam
mov %rcx, 24(%rsp) // pfnFilter
// Filters need to be passed ExceptionPointers and pvParam arguments, in that order.
// ExceptionPointers is already in the right register (RDI), so setup pvParam to be
// in RSI
mov %rdx, %rsi
LEHB0:
call *%rcx // Invoke the filter
LEHE0:
leave
ret
LFE7:
#else // BIT64
#define SIZEOF_ARG_REGISTERS 12
#define FRAME_SIZE ALIGN_UP(8 + SIZEOF_ARG_REGISTERS) - 8
.text
.globl _PAL_RunFilter
_PAL_RunFilter:
LFB7:
pushl %ebp
LCFI0:
movl %esp, %ebp
LCFI1:
subl $FRAME_SIZE, %esp
movl 8(%ebp), %eax // exception pointers
movl %eax, (%esp)
movl 12(%ebp), %eax // dispatcher context
movl %eax, 4(%esp)
movl 16(%ebp), %eax // param
movl %eax, 8(%esp)
LEHB0:
call *20(%ebp) // filter
LEHE0:
leave
ret
LFE7:
#endif // BIT64 else
.section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support
CIE_SEHFilterPersonality:
.long LECIE1-LSCIE1
LSCIE1:
.long 0x0
.byte 0x1
.ascii "zPLR\0"
.byte 0x1
#ifdef BIT64
.byte 0x78 // data_align: -8
.byte 16 // return address register: rip
#else // BIT64
.byte 0x7c // data_align: -4
.byte 0x8 // return address register: eip
#endif // BIT64 else
.byte 0x7
.byte 0x9b
#ifdef BIT64
.long _PAL_SEHFilterPersonalityRoutine+4@GOTPCREL
#else // BIT64
.long L_PAL_SEHFilterPersonalityRoutine$non_lazy_ptr-.
#endif // BIT64 else
.byte 0x10
.byte 0x10
.byte 0xc // DW_CFA_def_cfa
#ifdef BIT64
.byte 0x7 // operand1 = rsp
.byte 0x8 // operand2 = offset 8
.byte 0x80 | 16 // DW_CFA_offset of return address register
#else // BIT64
.byte 0x5 // operand1 = esp
.byte 0x4 // operand2 = offset 4
.byte 0x80 | 8 // DW_CFA_offset of return address register
#endif // BIT64 else
.byte 0x1 // operand1 = 1 word
.align 2
LECIE1:
.globl _PAL_RunFilter.eh
_PAL_RunFilter.eh:
LSFDE1:
.set LLFDE1,LEFDE1-LASFDE1
.set LFL7,LFE7-LFB7
.long LLFDE1
LASFDE1:
.long LASFDE1-CIE_SEHFilterPersonality
#ifdef BIT64
.quad LFB7-.
.quad LFL7
.byte 0x8
.quad 0x0
#else // BIT64
.long LFB7-.
.long LFL7
.byte 0x4
.long 0x0
#endif // BIT64 else
.byte 0x4 // DW_CFA_advance_loc4
.long LCFI0-LFB7
.byte 0xe // DW_CFA_def_cfa_offset
#ifdef BIT64
.byte 0x10
.byte 0x80 | 6 // DW_CFA_offset rbp
#else // BIT64
.byte 0x8
.byte 0x80 | 4 // DW_CFA_offset ebp
#endif // BIT64 else
.byte 0x2
.byte 0x4 // DW_CFA_advance_loc4
.long LCFI1-LCFI0
.byte 0xd // DW_CFA_def_cfa_register
#ifdef BIT64
.byte 6 // operand1 = rbp
#else // BIT64
.byte 4 // operand1 = ebp
#endif // BIT64
.align 2
LEFDE1:
#ifndef BIT64
.section __IMPORT,__pointers,non_lazy_symbol_pointers
L_PAL_SEHFilterPersonalityRoutine$non_lazy_ptr:
.indirect_symbol _PAL_SEHFilterPersonalityRoutine
.long 0
#endif // BIT64
|
xenia-project/xenia | 5,140 | src/xenia/cpu/ppc/testing/instr_rldicr.s | .macro make_full_test_constant dest, a, b, c, d
lis \dest, \a
ori \dest, \dest, \b
sldi \dest, \dest, 32
lis r3, \c
ori r3, r3, \d
clrldi r3, r3, 32
or \dest, \dest, r3
.endm
test_rldicr_1:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x0000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_1_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x0000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_2:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 24, 8
blr
#_ REGISTER_OUT r3 0x6780000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_2_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 24, 8
blr
#_ REGISTER_OUT r3 0x6780000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_3:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 24, 63
blr
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_3_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 24, 63
blr
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_4:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 0, 0
blr
#_ REGISTER_OUT r3 0x0000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_4_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 0, 0
blr
#_ REGISTER_OUT r3 0x0000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_5:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 0, 63
blr
#_ REGISTER_OUT r3 0x0123456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_5_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 0, 63
blr
#_ REGISTER_OUT r3 0x0123456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_6:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 0, 8
blr
#_ REGISTER_OUT r3 0x0100000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_6_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 0, 8
blr
#_ REGISTER_OUT r3 0x0100000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_7:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 63, 0
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_7_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 63, 0
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_8:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 63, 63
blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_8_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 63, 63
blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_9:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicr r3, r4, 31, 0
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicr_9_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicr r3, r4, 31, 0
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_sldi_1:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
sldi r3, r3, 0
sldi r4, r4, 0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_sldi_1_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
sldi r3, r3, 0
sldi r4, r4, 0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_sldi_2:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
sldi r3, r3, 1
sldi r4, r4, 1
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0x02468acf13579bde
test_sldi_2_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
sldi r3, r3, 1
sldi r4, r4, 1
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0x02468acf13579bde
test_sldi_3:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
sldi r3, r3, 32
sldi r4, r4, 32
blr
#_ REGISTER_OUT r3 0xffffffff00000000
#_ REGISTER_OUT r4 0x89abcdef00000000
test_sldi_3_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
sldi r3, r3, 32
sldi r4, r4, 32
blr
#_ REGISTER_OUT r3 0xffffffff00000000
#_ REGISTER_OUT r4 0x89abcdef00000000
test_sldi_4:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
sldi r3, r3, 63
sldi r4, r4, 63
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0x8000000000000000
test_sldi_4_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
sldi r3, r3, 63
sldi r4, r4, 63
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0x8000000000000000
|
xenia-project/xenia | 9,885 | src/xenia/cpu/ppc/testing/instr_vpkd3d128.s | # vpkd3d128 dest, src, type, mask, shift
# type:
# 0 = PACK_TYPE_D3DCOLOR
# 1 = PACK_TYPE_SHORT_2
# 2 = PACK_TYPE_2_10_10_10
# 3 = PACK_TYPE_FLOAT16_2
# 4 = PACK_TYPE_SHORT_4
# 5 = PACK_TYPE_FLOAT16_4
# mask:
# must not be zero
# 1 = 00000000 00000000 00000000 FFFFFFFF
# 2 = 00000000 00000000 FFFFFFFF FFFFFFFF
# 3 = same as 2? except mask3/shift3
# shift:
# 0 = no shift
# 1 = shift left by one word
# 2 ...
# 3 ...
# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF
# vpkd3d128 is broken in binutils, so these are hand coded
test_vpkd3d128_d3dcolor_invalid_0:
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
test_vpkd3d128_d3dcolor_invalid_1:
#_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000]
test_vpkd3d128_d3dcolor_invalid_2:
#_ REGISTER_IN v3 [40800000, 40000000, C2F60000, FFFFFFFF]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, FFFFFFFF]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00FF0000]
test_vpkd3d128_d3dcolor_1_0:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 0
.long 0x18811E10
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vpkd3d128_d3dcolor_1_1:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 1
.long 0x18811E50
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_1_2:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 2
.long 0x18811E90
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_1_3:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 1, 3
.long 0x18811ED0
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_0:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 0
.long 0x18821E10
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
test_vpkd3d128_d3dcolor_2_1:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 1
.long 0x18821E50
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_2:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 2
.long 0x18821E90
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_3:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 2, 3
.long 0x18821ED0
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_0:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 0
.long 0x18831E10
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
test_vpkd3d128_d3dcolor_3_1:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 1
.long 0x18831E50
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_2:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 2
.long 0x18831E90
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_3:
#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 0, 3, 3
.long 0x18831ED0
blr
#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
test_vpkd3d128_short2_invalid_0:
#_ REGISTER_IN v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 1, 1, 0
.long 0x18851E10
blr
#_ REGISTER_OUT v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
test_vpkd3d128_short2_invalid_1:
#_ REGISTER_IN v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 1, 1, 0
.long 0x18851E10
blr
#_ REGISTER_OUT v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
test_vpkd3d128_short2_0:
#_ REGISTER_IN v3 [40407FFF, 403F8001, 00000000, 00000000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 1, 1, 0
.long 0x18851E10
blr
#_ REGISTER_OUT v3 [40407FFF, 403F8001, 00000000, 00000000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
test_vpkd3d128_short2_1:
#_ REGISTER_IN v3 [40404000, 403FC000, 40400003, 403F8001]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 1, 1, 0
.long 0x18851E10
blr
#_ REGISTER_OUT v3 [40404000, 403FC000, 40400003, 403F8001]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
test_vpkd3d128_short2_2:
#_ REGISTER_IN v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 1, 1, 0
.long 0x18851E10
blr
#_ REGISTER_OUT v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]
test_vpkd3d128_short4_0:
# v3 = [1.5, -1.5, 1.5, -1.5]
#_ REGISTER_IN v3 [403F8001, 403FFFF8, 4040007F, 40400000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 4, 2, 0
.long 0x18921E10
blr
#_ REGISTER_OUT v3 [403F8001, 403FFFF8, 4040007F, 40400000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 8001FFF8, 007F0000]
test_vpkd3d128_uint_2101010_0:
#_ REGISTER_IN v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 2, 1, 0
.long 0x18891E10
blr
#_ REGISTER_OUT v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, E0180601]
test_vpkd3d128_uint_2101010_1:
#_ REGISTER_IN v3 [42C80000, C2C80000, 40400000, 3F800000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 2, 1, 0
.long 0x18891E10
blr
#_ REGISTER_OUT v3 [42C80000, C2C80000, 40400000, 3F800000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000805FF]
test_vpkd3d128_uint_2101010_2:
#_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, 00000000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 2, 1, 0
.long 0x18891E10
blr
#_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, 00000000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 20180601]
test_vpkd3d128_float16_2_invalid_0:
#_ REGISTER_IN v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 3, 1, 0
.long 0x188D1E10
blr
#_ REGISTER_OUT v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3E00BE00]
test_vpkd3d128_float16_2_0:
#_ REGISTER_IN v3 [3F000000, BF000000, 00000000, 00000000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 3, 1, 0
.long 0x188D1E10
blr
#_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]
test_vpkd3d128_float16_4_invalid_0:
#_ REGISTER_IN v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 5, 2, 0
.long 0x18961E10
blr
#_ REGISTER_OUT v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3E00BE00, 3E00BE00]
test_vpkd3d128_float16_4_0:
#_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, BF800000]
#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
# vpkd3d128 v4, v3, 5, 2, 0
.long 0x18961E10
blr
#_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, BF800000]
#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3800B800, 3C00BC00]
|
xenia-project/xenia | 2,620 | src/xenia/cpu/ppc/testing/instr_mulhwu.s | test_mulhwu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_1_constant:
li r4, 1
li r5, 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_2_constant:
li r4, -1
clrldi r4, r4, 32
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3_constant:
li r4, -1
clrldi r4, r4, 31
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
sldi r5, r5, 63
or r4, r4, r5
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5_constant:
li r4, -1
li r5, 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhwu_6_constant:
li r4, -1
li r5, -1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhwu_7:
#_ REGISTER_IN r0 0x1
#_ REGISTER_IN r3 0xFFFFFFFF
mulhwu. r0, r3, r0
blr
#_ REGISTER_OUT r0 0
#_ REGISTER_OUT r3 0xFFFFFFFF
#_ REGISTER_OUT cr 0x0000000020000000
test_mulhwu_8:
#_ REGISTER_IN r0 0x1
#_ REGISTER_IN r3 0x1FFFFFFFF
mulhwu. r0, r3, r0
blr
#_ REGISTER_OUT r0 0
#_ REGISTER_OUT r3 0x1FFFFFFFF
#_ REGISTER_OUT cr 0x0000000020000000
|
xenia-project/xenia | 11,815 | src/xenia/cpu/ppc/testing/instr_adde.s | test_adde_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_1_constant:
li r4, 1
li r5, 2
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 4
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_2_constant:
li r4, 1
li r5, 2
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 4
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_adde_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_adde_3_constant:
li r4, -1
li r5, 0
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_adde_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 1
test_adde_4_constant:
li r4, -1
li r5, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 1
test_adde_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_adde_5_constant:
li r4, -1
li r5, 1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_adde_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_adde_6_constant:
li r4, -1
li r5, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_adde_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_adde_7_constant:
li r4, -1
li r5, 123
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_adde_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007B
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_adde_8_constant:
li r4, -1
li r5, 123
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007B
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_adde_9:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_adde_9_constant:
li r5, -1
srdi r4, r5, 1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_adde_10:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_adde_10_constant:
li r5, -1
srdi r4, r5, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_adde_cr_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x20000000
test_adde_cr_1_constant:
li r4, 1
li r5, 2
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x20000000
test_adde_cr_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 4
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x20000000
test_adde_cr_2_constant:
li r4, 1
li r5, 2
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 4
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x20000000
test_adde_cr_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r11 0x80000000
#_ REGISTER_OUT r12 0x20000000
test_adde_cr_3_constant:
li r4, -1
li r5, 0
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r11 0x80000000
#_ REGISTER_OUT r12 0x20000000
test_adde_cr_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x20000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_4_constant:
li r4, -1
li r5, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x20000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x20000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_5_constant:
li r4, -1
li r5, 1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x20000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_6_constant:
li r4, -1
li r5, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_7_constant:
li r4, -1
li r5, 123
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x000000000000007B
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_8_constant:
li r4, -1
li r5, 123
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x000000000000007B
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x40000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_9:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x80000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_9_constant:
li r5, -1
srdi r4, r5, 1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x80000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_10:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x80000000
#_ REGISTER_OUT r12 0x40000000
test_adde_cr_10_constant:
li r5, -1
srdi r4, r5, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
adde. r3, r4, r5
mfcr r11
adde. r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r11 0x80000000
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 5,237 | src/xenia/cpu/ppc/testing/instr_twi.s | test_twlti_1:
#_ REGISTER_IN r3 24
twlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlti_1_constant:
li r3, 24
twlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlti_2:
#_ REGISTER_IN r3 24
twlti r3, 0
blr
#_ REGISTER_OUT r3 24
test_twlti_2_constant:
li r3, 24
twlti r3, 0
blr
#_ REGISTER_OUT r3 24
test_twlei_1:
#_ REGISTER_IN r3 24
twlei r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlei_1_constant:
li r3, 24
twlei r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlei_2:
#_ REGISTER_IN r3 24
twlei r3, 0
blr
#_ REGISTER_OUT r3 24
test_twlei_2_constant:
li r3, 24
twlei r3, 0
blr
#_ REGISTER_OUT r3 24
test_tweqi_1:
#_ REGISTER_IN r3 0
tweqi r3, 24
blr
#_ REGISTER_OUT r3 0
test_tweqi_1_constant:
li r3, 0
tweqi r3, 24
blr
#_ REGISTER_OUT r3 0
test_tweqi_2:
#_ REGISTER_IN r3 24
tweqi r3, 0
blr
#_ REGISTER_OUT r3 24
test_tweqi_2_constant:
li r3, 24
tweqi r3, 0
blr
#_ REGISTER_OUT r3 24
test_twgei_1:
#_ REGISTER_IN r3 24
twgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_twgei_1_constant:
li r3, 24
twgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_twgei_2:
#_ REGISTER_IN r3 0
twgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_twgei_2_constant:
li r3, 0
twgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_twgei_3:
#_ REGISTER_IN r3 -1
twgei r3, 0
blr
#_ REGISTER_OUT r3 -1
test_twgei_3_constant:
li r3, -1
twgei r3, 0
blr
#_ REGISTER_OUT r3 -1
test_twgti_1:
#_ REGISTER_IN r3 24
twgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_twgti_1_constant:
li r3, 24
twgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_twgti_2:
#_ REGISTER_IN r3 0
twgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_twgti_2_constant:
li r3, 0
twgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_twgti_3:
#_ REGISTER_IN r3 -1
twgti r3, 0
blr
#_ REGISTER_OUT r3 -1
test_twgti_3_constant:
li r3, -1
twgti r3, 0
blr
#_ REGISTER_OUT r3 -1
test_twnli_1:
#_ REGISTER_IN r3 24
twnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_twnli_1_constant:
li r3, 24
twnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_twnli_2:
#_ REGISTER_IN r3 0
twnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_twnli_2_constant:
li r3, 0
twnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_twnli_3:
#_ REGISTER_IN r3 -1
twnli r3, 0
blr
#_ REGISTER_OUT r3 -1
test_twnli_3_constant:
li r3, -1
twnli r3, 0
blr
#_ REGISTER_OUT r3 -1
test_twnei_1:
#_ REGISTER_IN r3 24
twnei r3, 24
blr
#_ REGISTER_OUT r3 24
test_twnei_1_constant:
li r3, 24
twnei r3, 24
blr
#_ REGISTER_OUT r3 24
test_twnei_2:
#_ REGISTER_IN r3 0
twnei r3, 0
blr
#_ REGISTER_OUT r3 0
test_twnei_2_constant:
li r3, 0
twnei r3, 0
blr
#_ REGISTER_OUT r3 0
test_twngi_1:
#_ REGISTER_IN r3 24
twngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_twngi_1_constant:
li r3, 24
twngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_twngi_2:
#_ REGISTER_IN r3 24
twngi r3, 0
blr
#_ REGISTER_OUT r3 24
test_twngi_2_constant:
li r3, 24
twngi r3, 0
blr
#_ REGISTER_OUT r3 24
test_twngi_3:
#_ REGISTER_IN r3 0
twngi r3, -1
blr
#_ REGISTER_OUT r3 0
test_twngi_3_constant:
li r3, 0
twngi r3, -1
blr
#_ REGISTER_OUT r3 0
test_twllti_1:
#_ REGISTER_IN r3 24
twllti r3, 16
blr
#_ REGISTER_OUT r3 24
test_twllti_1_constant:
li r3, 24
twllti r3, 16
blr
#_ REGISTER_OUT r3 24
test_twllti_2:
#_ REGISTER_IN r3 24
twllti r3, 0
blr
#_ REGISTER_OUT r3 24
test_twllti_2_constant:
li r3, 24
twllti r3, 0
blr
#_ REGISTER_OUT r3 24
test_twllei_1:
#_ REGISTER_IN r3 24
twllei r3, 16
blr
#_ REGISTER_OUT r3 24
test_twllei_1_constant:
li r3, 24
twllei r3, 16
blr
#_ REGISTER_OUT r3 24
test_twllei_2:
#_ REGISTER_IN r3 24
twllei r3, 0
blr
#_ REGISTER_OUT r3 24
test_twllei_2_constant:
li r3, 24
twllei r3, 0
blr
#_ REGISTER_OUT r3 24
test_twlgei_1:
#_ REGISTER_IN r3 24
twlgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_twlgei_1_constant:
li r3, 24
twlgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_twlgei_2:
#_ REGISTER_IN r3 0
twlgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_twlgei_2_constant:
li r3, 0
twlgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_twlgti_1:
#_ REGISTER_IN r3 24
twlgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_twlgti_1_constant:
li r3, 24
twlgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_twlgti_2:
#_ REGISTER_IN r3 0
twlgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_twlgti_2_constant:
li r3, 0
twlgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_twlnli_1:
#_ REGISTER_IN r3 24
twlnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_twlnli_1_constant:
li r3, 24
twlnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_twlnli_2:
#_ REGISTER_IN r3 0
twlnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_twlnli_2_constant:
li r3, 0
twlnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_twlngi_1:
#_ REGISTER_IN r3 24
twlngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlngi_1_constant:
li r3, 24
twlngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_twlngi_2:
#_ REGISTER_IN r3 24
twlngi r3, 0
blr
#_ REGISTER_OUT r3 24
test_twlngi_2_constant:
li r3, 24
twlngi r3, 0
blr
#_ REGISTER_OUT r3 24
|
xenia-project/xenia | 1,322 | src/xenia/cpu/ppc/testing/instr_vpkuwum128.s | test_vpkuwum128_1:
# {0, 1, 2, 3}
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
# {4, 5, 6, 7}
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
# {0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
test_vpkuwum128_2:
# {-4, -3, -2, -1}
#_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
# {0, 1, 2, 3}
#_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
# {-4, -3, -2, -1, 0, 1, 2, 3}
#_ REGISTER_OUT v5 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vpkuwum128_3:
# {0, 4294967295, 4294967295, 4294967295}
#_ REGISTER_IN v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# {4294967295, 0, 0, 0}
#_ REGISTER_IN v4 [FFFFFFFF, 00000000, 00000000, 00000000]
vpkuwum128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [FFFFFFFF, 00000000, 00000000, 00000000]
# {0, 65535, 65535, 65535, 65535, 0, 0, 0}
#_ REGISTER_OUT v5 [0000FFFF, FFFFFFFF, FFFF0000, 00000000]
|
xenia-project/xenia | 1,176 | src/xenia/cpu/ppc/testing/instr_vpkswss128.s | test_vpkswss128_1:
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
vpkswss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
#_ REGISTER_OUT v5 [00010002, 00030004, 00050006, 00070008]
test_vpkswss128_2:
#_ REGISTER_IN v3 [7FFFFFFF, 80000000, 00000000, 00000004]
#_ REGISTER_IN v4 [7FFFFFFF, 80000000, 00000000, 00000008]
vpkswss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [7FFFFFFF, 80000000, 00000000, 00000004]
#_ REGISTER_OUT v4 [7FFFFFFF, 80000000, 00000000, 00000008]
#_ REGISTER_OUT v5 [7FFF8000, 00000004, 7FFF8000, 00000008]
test_vpkswss128_3:
# {-1, -32768, 0, 32767}
#_ REGISTER_IN v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
# {-2, -32769, 1, 32768}
#_ REGISTER_IN v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
vpkswss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
#_ REGISTER_OUT v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
# {-1, -32768, 0, 32767, -2, -32768, 1, 32767}
#_ REGISTER_OUT v5 [FFFF8000, 00007FFF, FFFE8000, 00017FFF]
|
xenia-project/xenia | 2,294 | src/xenia/cpu/ppc/testing/instr_subfe.s | test_subfe_1:
#_ REGISTER_IN r10 0x00000000000103BF
#_ REGISTER_IN r11 0x00000000000103C0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 0x0
#_ REGISTER_OUT r4 1
test_subfe_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
lis r11, 1
ori r11, r11, 0x03C0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 0x0
#_ REGISTER_OUT r4 1
test_subfe_2:
#_ REGISTER_IN r10 0
#_ REGISTER_IN r11 0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0
test_subfe_2_constant:
li r10, 0
li r11, 0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0
test_subfe_3:
#_ REGISTER_IN r10 1
#_ REGISTER_IN r11 0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
test_subfe_3_constant:
li r10, 1
li r11, 0
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
test_subfe_4:
#_ REGISTER_IN r10 0
#_ REGISTER_IN r11 1
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 1
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfe_4_constant:
li r10, 0
li r11, 1
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 1
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfe_5:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
test_subfe_5_constant:
li r10, -1
li r11, -1
subfe r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
|
xenia-project/xenia | 6,691 | src/xenia/cpu/ppc/testing/instr_addme.s | test_addme_1:
#_ REGISTER_IN r4 1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
test_addme_1_constant:
li r4, 1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
test_addme_2:
#_ REGISTER_IN r4 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
test_addme_2_constant:
li r4, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
test_addme_3:
#_ REGISTER_IN r4 12
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 11
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
test_addme_3_constant:
li r4, 12
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 11
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
test_addme_4:
#_ REGISTER_IN r4 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
test_addme_4_constant:
li r4, 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
test_addme_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addme_5_constant:
li r4, -1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addme_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addme_6_constant:
li r4, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addme_7:
#_ REGISTER_IN r4 0
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addme_7_constant:
li r4, 0
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addme_8:
#_ REGISTER_IN r4 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
test_addme_8_constant:
li r4, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
test_addme_cr_1:
#_ REGISTER_IN r4 1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addme_cr_1_constant:
li r4, 1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addme_cr_2:
#_ REGISTER_IN r4 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_2_constant:
li r4, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_3:
#_ REGISTER_IN r4 12
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 11
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_3_constant:
li r4, 12
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 11
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_4:
#_ REGISTER_IN r4 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_4_constant:
li r4, 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addme_cr_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_5_constant:
li r4, -1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_6_constant:
li r4, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_7:
#_ REGISTER_IN r4 0
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_7_constant:
li r4, 0
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addme_cr_8:
#_ REGISTER_IN r4 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addme_cr_8_constant:
li r4, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addme. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
|
xenia-project/xenia | 1,304 | src/xenia/cpu/ppc/testing/instr_vpkuwum.s | test_vpkuwum_1:
# {0, 1, 2, 3}
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
# {4, 5, 6, 7}
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vpkuwum v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
# {0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
test_vpkuwum_2:
# {-4, -3, -2, -1}
#_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
# {0, 1, 2, 3}
#_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
vpkuwum v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
# {-4, -3, -2, -1, 0, 1, 2, 3}
#_ REGISTER_OUT v5 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vpkuwum_3:
# {0, 4294967295, 4294967295, 4294967295}
#_ REGISTER_IN v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# {4294967295, 0, 0, 0}
#_ REGISTER_IN v4 [FFFFFFFF, 00000000, 00000000, 00000000]
vpkuwum v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [FFFFFFFF, 00000000, 00000000, 00000000]
# {0, 65535, 65535, 65535, 65535, 0, 0, 0}
#_ REGISTER_OUT v5 [0000FFFF, FFFFFFFF, FFFF0000, 00000000]
|
xenia-project/xenia | 1,136 | src/xenia/cpu/ppc/testing/instr_lvr.s | test_lvr_1:
#_ MEMORY_IN 100010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
#_ REGISTER_IN r4 0x100010B7
#_ REGISTER_IN r5 0x10
lvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x100010B7
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]
test_lvr_1_constant:
#_ MEMORY_IN 100010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
lis r4, 0x1000
ori r4, r4, 0x10B7
li r5, 0x10
lvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x100010B7
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]
test_lvr_2:
#_ REGISTER_IN r4 0x20000000
#_ REGISTER_IN r5 0x10
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
lvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x20000000
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_lvr_2_constant:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
lis r4, 0x2000
li r5, 0x10
lvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x20000000
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
xenia-project/xenia | 3,164 | src/xenia/cpu/ppc/testing/instr_divd.s | test_divd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
test_divd_1_constant:
li r4, 1
li r5, 2
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
# TODO(benvanik): x64 ignore divide by zero (=0)
#test_divd_2:
# #_ REGISTER_IN r4 1
# #_ REGISTER_IN r5 0
# divd r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 0
# TODO(benvanik): x64 ignore divide by zero (=0)
#test_divd_2_constant:
# li r4, 1
# li r5, 0
# divd r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 0
test_divd_3:
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 1
test_divd_3_constant:
li r4, 2
li r5, 1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 1
test_divd_4:
#_ REGISTER_IN r4 35
#_ REGISTER_IN r5 7
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 35
#_ REGISTER_OUT r5 7
test_divd_4_constant:
li r4, 35
li r5, 7
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 35
#_ REGISTER_OUT r5 7
test_divd_5:
#_ REGISTER_IN r4 0
#_ REGISTER_IN r5 1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_divd_5_constant:
li r4, 0
li r5, 1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_divd_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_divd_6_constant:
li r4, -1
li r5, 1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_divd_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divd_7_constant:
li r4, -1
li r5, -1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divd_8:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divd_8_constant:
li r4, 1
li r5, -1
divd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
# TODO(benvanik): integer overflow (=0)
#test_divd_9:
# #_ REGISTER_IN r4 0x8000000000000000
# #_ REGISTER_IN r5 -1
# divd r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 0x8000000000000000
# #_ REGISTER_OUT r5 -1
# TODO(benvanik): integer overflow (=0)
#test_divd_9_constant:
# li r4, 1
# sldi r4, r4, 63
# li r5, -1
# divd r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 0x8000000000000000
# #_ REGISTER_OUT r5 -1
|
xenia-project/xenia | 4,465 | src/xenia/cpu/ppc/testing/instr_andc.s | test_andc_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_1_constant:
li r5, -1
li r25, -1
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_andc_2_constant:
li r5, -1
li r25, 0
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_andc_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_3_constant:
li r5, 0
li r25, -1
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_andc_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
test_andc_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
andc r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
test_andc_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
andc r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
test_andc_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
andc r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
test_andc_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_1_constant:
li r5, -1
li r25, -1
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_2_constant:
li r5, -1
li r25, 0
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_3_constant:
li r5, 0
li r25, -1
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andc_cr_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
andc. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFF0000
#_ REGISTER_OUT r12 0x80000000
test_andc_cr_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
andc. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
#_ REGISTER_OUT r12 0x40000000
test_andc_cr_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
andc. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x10000000
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 2,503 | src/xenia/cpu/ppc/testing/instr_extsh.s | test_extsh_1:
#_ REGISTER_IN r4 0x0F
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsh_1_constant:
li r4, 0x0F
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsh_2:
#_ REGISTER_IN r4 0x7FFF
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x7FFF
#_ REGISTER_OUT r4 0x7FFF
test_extsh_2_constant:
li r4, 0x7FFF
extsh r3, r4
blr
#_ REGISTER_OUT r3 0x7FFF
#_ REGISTER_OUT r4 0x7FFF
test_extsh_3:
#_ REGISTER_IN r4 0x8000
extsh r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0x8000
test_extsh_3_constant:
li r4, 0x80
sldi r4, r4, 8
extsh r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0x8000
test_extsh_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFF08000
extsh r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
test_extsh_4_constant:
li r4, 0xF7F
not r4, r4
sldi r4, r4, 8
extsh r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
test_extsh_cr_1:
#_ REGISTER_IN r4 0x0F
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
#_ REGISTER_OUT r12 0x40000000
test_extsh_cr_1_constant:
li r4, 0x0F
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
#_ REGISTER_OUT r12 0x40000000
test_extsh_cr_2:
#_ REGISTER_IN r4 0x7FFF
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFF
#_ REGISTER_OUT r4 0x7FFF
#_ REGISTER_OUT r12 0x40000000
test_extsh_cr_2_constant:
li r4, 0x7FFF
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFF
#_ REGISTER_OUT r4 0x7FFF
#_ REGISTER_OUT r12 0x40000000
test_extsh_cr_3:
#_ REGISTER_IN r4 0x8000
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0x8000
#_ REGISTER_OUT r12 0x80000000
test_extsh_cr_3_constant:
li r4, 0x80
sldi r4, r4, 8
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0x8000
#_ REGISTER_OUT r12 0x80000000
test_extsh_cr_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFF08000
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
#_ REGISTER_OUT r12 0x80000000
test_extsh_cr_4_constant:
li r4, 0xF7F
not r4, r4
sldi r4, r4, 8
extsh. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
#_ REGISTER_OUT r4 0xFFFFFFFFFFF08000
#_ REGISTER_OUT r12 0x80000000
|
xenia-project/xenia | 1,832 | src/xenia/cpu/ppc/testing/instr_mulhd.s | test_mulhd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_1_constant:
li r4, 1
li r5, 0
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhd_2_constant:
li r4, -1
li r5, 1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhd_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhd_3_constant:
li r4, -1
li r5, 2
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhd_4:
#_ REGISTER_IN r4 0x8000000000000000
#_ REGISTER_IN r5 1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhd_4_constant:
li r5, 1
sldi r4, r5, 63
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhd_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhd_5_constant:
li r4, -1
li r5, -1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
xenia-project/xenia | 1,784 | src/xenia/cpu/ppc/testing/instr_mulhdu.s | test_mulhdu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_1_constant:
li r4, 1
li r5, 0
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhdu_2_constant:
li r4, -1
li r5, 1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhdu_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhdu_3_constant:
li r4, -1
li r5, 2
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhdu_4:
#_ REGISTER_IN r4 0x8000000000000000
#_ REGISTER_IN r5 1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhdu_4_constant:
li r5, 1
sldi r4, r5, 63
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhdu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhdu_5_constant:
li r4, -1
li r5, -1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
xenia-project/xenia | 1,127 | src/xenia/cpu/ppc/testing/instr_vsl.s | test_vsl_1:
#_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsl v3, v3, v4
blr
#_ REGISTER_OUT v3 [EFEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFE0]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsl_2:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsl v3, v3, v4
blr
#_ REGISTER_OUT v3 [01122334, 45566778, 899AABBC, CDDEEFF0]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsl_3:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
vsl v3, v3, v4
blr
#_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
test_vsl_4:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v3, v4
blr
#_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
xenia-project/xenia | 2,415 | src/xenia/cpu/ppc/testing/instr_vperm.s | test_vperm_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vperm v6, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v6 [00000000, 00000000, 00000000, 00000000]
test_vperm_2:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [01010101, 01010101, 01010101, 01010101]
vperm v6, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
#_ REGISTER_OUT v6 [01010101, 01010101, 01010101, 01010101]
test_vperm_3:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [11111111, 11111111, 11111111, 11111111]
vperm v6, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [11111111, 11111111, 11111111, 11111111]
#_ REGISTER_OUT v6 [11111111, 11111111, 11111111, 11111111]
test_vperm_4:
# try with > 32b values (should mod)
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [21212121, 21212121, 21212121, 21212121]
vperm v6, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [21212121, 21212121, 21212121, 21212121]
#_ REGISTER_OUT v6 [01010101, 01010101, 01010101, 01010101]
test_vperm_5:
#_ REGISTER_IN v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v6 [01020003, 14150001, 1F1C1D1E, 00141518]
vperm v3, v4, v5, v6
blr
#_ REGISTER_OUT v3 [01020003, 14150001, 1F1C1D1E, 00141518]
#_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v6 [01020003, 14150001, 1F1C1D1E, 00141518]
|
xenia-project/xenia | 2,462 | src/xenia/cpu/ppc/testing/instr_sld.s | test_sld_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_sld_1_constant:
li r4, 1
li r5, 0
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_sld_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_sld_2_constant:
li r4, -1
li r5, 0
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_sld_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_sld_3_constant:
li r4, -1
li r5, 1
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_sld_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 62
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xc000000000000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
test_sld_4_constant:
li r4, -1
li r5, 62
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xc000000000000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
test_sld_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_sld_5_constant:
li r4, -1
li r5, 63
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0x8000000000000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_sld_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_sld_6_constant:
li r4, -1
li r5, 64
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_sld_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
test_sld_7_constant:
li r4, -1
li r5, 100
sld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
|
xenia-project/xenia | 3,563 | src/xenia/cpu/ppc/testing/instr_subfze.s | test_subfze_one_ca_1:
#_ REGISTER_IN r10 0x00000000000103BF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc41
#_ REGISTER_OUT r4 0
test_subfze_one_ca_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc41
#_ REGISTER_OUT r4 0
test_subfze_one_ca_2:
#_ REGISTER_IN r10 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfze_one_ca_2_constant:
li r10, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfze_one_ca_3:
#_ REGISTER_IN r10 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_subfze_one_ca_3_constant:
li r10, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_subfze_one_ca_4:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0x1
#_ REGISTER_OUT r4 0
test_subfze_one_ca_4_constant:
li r10, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0x1
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_1:
#_ REGISTER_IN r10 0x00000000000103BF
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc40
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc40
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_2:
#_ REGISTER_IN r10 0
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_2_constant:
li r10, 0
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_3:
#_ REGISTER_IN r10 1
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_3_constant:
li r10, 1
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_4:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
test_subfze_zero_ca_4_constant:
li r10, -1
xor r3, r3, r3
addic r3, r3, 1
subfze r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
|
xenia-project/xenia | 1,570 | src/xenia/cpu/ppc/testing/instr_vpkuhum128.s | #vpkuhum128 isn't implemented yet
#test_vpkuhum128_1:
# # {0, 1, 2, 3, 4, 5, 6, 7}
# #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
# # {8, 9, 10, 11, 12, 13, 14, 15}
# #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
# vpkuhum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
# #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
# # {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
# #_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
# blr
#test_vpkuhum128_2:
# # {-8, -7, -6, -5, -4, -3, -2, -1}
# #_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
# # {0, 1, 2, 3, 4, 5, 6, 7}
# #_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007]
# vpkuhum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
# #_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007]
# # {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}
# #_ REGISTER_OUT v5 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
# blr
#test_vpkuhum128_3:
# # {0, 65535, 65535, 0, 0, 0, 65535, 0}
# #_ REGISTER_IN v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
# # {65535, 0, 0, 65535, 65535, 65535, 0, 65535}
# #_ REGISTER_IN v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
# vpkuhum128 v5, v3, v4
# blr
# #_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
# #_ REGISTER_OUT v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
# # {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255}
# #_ REGISTER_OUT v5 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
# blr
|
xenia-project/xenia | 3,132 | src/xenia/cpu/ppc/testing/instr_srad.s | test_srad_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_1_constant:
li r4, 1
li r5, 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_2_constant:
li r4, -1
li r5, 0
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_srad_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_srad_3_constant:
li r4, -1
li r5, 1
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_srad_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 62
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
#_ REGISTER_OUT r6 1
test_srad_4_constant:
li r4, -1
li r5, 62
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
#_ REGISTER_OUT r6 1
test_srad_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_srad_5_constant:
li r4, -1
li r5, 63
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_srad_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 1
test_srad_6_constant:
li r4, -1
li r5, 64
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 1
test_srad_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
test_srad_7_constant:
li r4, -1
li r5, 100
srad r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
|
xenia-project/xenia | 1,232 | src/xenia/cpu/ppc/testing/instr_cntlzw.s | test_cntlzw_1:
#_ REGISTER_IN r5 0
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 32
test_cntlzw_1_constant:
li r5, 0
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 32
test_cntlzw_2:
#_ REGISTER_IN r5 1
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 31
test_cntlzw_2_constant:
li r5, 1
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 31
test_cntlzw_3:
#_ REGISTER_IN r5 0xFFFFFFFF
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0xFFFFFFFF
#_ REGISTER_OUT r6 0
test_cntlzw_3_constant:
li r5, -1
srwi r5, r5, 0
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0xFFFFFFFF
#_ REGISTER_OUT r6 0
test_cntlzw_4:
#_ REGISTER_IN r5 0x7FFFFFFF
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0x7FFFFFFF
#_ REGISTER_OUT r6 1
test_cntlzw_4_constant:
li r5, -1
srwi r5, r5, 1
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0x7FFFFFFF
#_ REGISTER_OUT r6 1
test_cntlzw_5:
#_ REGISTER_IN r5 0xFFFFFFFF00000001
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0xFFFFFFFF00000001
#_ REGISTER_OUT r6 31
test_cntlzw_5_constant:
li r5, -1
sldi r5, r5, 32
addi r5, r5, 1
cntlzw r6, r5
blr
#_ REGISTER_OUT r5 0xFFFFFFFF00000001
#_ REGISTER_OUT r6 31
|
xenia-project/xenia | 2,779 | src/xenia/cpu/ppc/testing/instr_vrlimi128.s | test_vrlimi128_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
test_vrlimi128_2:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0xF, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vrlimi128_3:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
# assember is busted here:
# vrlimi128 v4, v3, 0xF, 1
.long 0x188f1f50
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [04050607, 08090A0B, 0C0D0E0F, 00010203]
test_vrlimi128_4:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0xF, 2
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [08090A0B, 0C0D0E0F, 00010203, 04050607]
test_vrlimi128_5:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
# assember is busted here:
# vrlimi128 v4, v3, 0xF, 3
.long 0x188f1fd0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [0C0D0E0F, 00010203, 04050607, 08090A0B]
test_vrlimi128_6:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0x8, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [00010203, CCCCCCCC, CCCCCCCC, CCCCCCCC]
test_vrlimi128_7:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0x4, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [CCCCCCCC, 04050607, CCCCCCCC, CCCCCCCC]
test_vrlimi128_8:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0x2, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, 08090A0B, CCCCCCCC]
test_vrlimi128_9:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, CCCCCCCC]
vrlimi128 v4, v3, 0x1, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [CCCCCCCC, CCCCCCCC, CCCCCCCC, 0C0D0E0F]
|
xenia-project/xenia | 2,633 | src/xenia/cpu/ppc/testing/instr_mulld.s | test_mulld_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_1_constant:
li r4, 1
li r5, 0
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mulld_2_constant:
li r4, 1
li r5, 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mulld_3:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_3_constant:
li r4, 1
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_4:
#_ REGISTER_IN r4 123
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mulld_4_constant:
li r4, 123
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mulld_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulld_5_constant:
li r4, -1
li r5, 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulld_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulld_6_constant:
li r4, -1
li r5, 2
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulld_7:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_7_constant:
li r4, 1
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mulld_8_constant:
li r4, -1
li r5, -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
|
xenia-project/xenia | 2,006 | src/xenia/cpu/ppc/testing/instr_cmpli.s | test_cmpldi_1:
#_ REGISTER_IN r3 0x0000000100000000
cmpldi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_cmpldi_1_constant:
li r3, 1
sldi r3, r3, 32
cmpldi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_cmpldi_2:
#_ REGISTER_IN r3 1
cmpldi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x80000000
test_cmpldi_2_constant:
li r3, 1
cmpldi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x80000000
test_cmplwi_1:
#_ REGISTER_IN r3 0x0000000100000000
cmplwi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x80000000
test_cmplwi_1_constant:
li r3, 1
sldi r3, r3, 32
cmplwi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x80000000
test_cmplwi_2:
#_ REGISTER_IN r3 2
cmplwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x40000000
test_cmplwi_2_constant:
li r3, 2
cmplwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x40000000
test_cmplwi_5:
#_ REGISTER_IN r3 0x0000000100000002
cmplwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000002
#_ REGISTER_OUT r12 0x40000000
test_cmplwi_5_constant:
li r3, 1
sldi r3, r3, 32
sldi r4, r3, 1
addi r3, r3, 2
cmplwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000002
#_ REGISTER_OUT r12 0x40000000
test_cmpli_1:
#_ REGISTER_IN r3 1
cmpli 5, 0, r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x00000800
test_cmpli_1_constant:
li r3, 1
cmpli 5, 0, r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x00000800
test_cmpli_2:
#_ REGISTER_IN r3 2
cmpli 3, 0, r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x00040000
test_cmpli_2_constant:
li r3, 2
cmpli 3, 0, r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x00040000
|
xenia-project/xenia | 1,158 | src/xenia/cpu/ppc/testing/instr_vpkswss.s | test_vpkswss_1:
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_IN v4 [00000005, 00000006, 00000007, 00000008]
vpkswss v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
#_ REGISTER_OUT v4 [00000005, 00000006, 00000007, 00000008]
#_ REGISTER_OUT v5 [00010002, 00030004, 00050006, 00070008]
test_vpkswss_2:
#_ REGISTER_IN v3 [7FFFFFFF, 80000000, 00000000, 00000004]
#_ REGISTER_IN v4 [7FFFFFFF, 80000000, 00000000, 00000008]
vpkswss v5, v3, v4
blr
#_ REGISTER_OUT v3 [7FFFFFFF, 80000000, 00000000, 00000004]
#_ REGISTER_OUT v4 [7FFFFFFF, 80000000, 00000000, 00000008]
#_ REGISTER_OUT v5 [7FFF8000, 00000004, 7FFF8000, 00000008]
test_vpkswss_3:
# {-1, -32768, 0, 32767}
#_ REGISTER_IN v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
# {-2, -32769, 1, 32768}
#_ REGISTER_IN v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
vpkswss v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFF8000, 00000000, 00007FFF]
#_ REGISTER_OUT v4 [FFFFFFFE, FFFF7FFF, 00000001, 00008000]
# {-1, -32768, 0, 32767, -2, -32768, 1, 32767}
#_ REGISTER_OUT v5 [FFFF8000, 00007FFF, FFFE8000, 00017FFF]
|
xenia-project/xenia | 1,874 | src/xenia/cpu/ppc/testing/instr_andis.s | test_andis_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andis. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xCAFE0000
#_ REGISTER_OUT r12 0x80000000
test_andis_cr_1_constant:
li r5, -1
andis. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xCAFE0000
#_ REGISTER_OUT r12 0x80000000
test_andis_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andis. r11, r5, 0
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andis_cr_2_constant:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andis. r11, r5, 0
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andis_cr_3:
#_ REGISTER_IN r5 0
andis. r11, r5, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andis_cr_3_constant:
li r5, 0
andis. r11, r5, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andis_cr_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andis. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xCAFE0000
#_ REGISTER_OUT r12 0x80000000
test_andis_cr_4_constant:
li r5, -1
andis. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xCAFE0000
#_ REGISTER_OUT r12 0x80000000
test_andis_cr_5:
#_ REGISTER_IN r0 0x100000FF
andis. r11, r0, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r11 0x10000000
#_ REGISTER_OUT r12 0x40000000
test_andis_cr_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
andis. r11, r0, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r11 0x10000000
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 7,743 | src/xenia/cpu/ppc/testing/instr_tw.s | test_twlt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlt_1_constant:
li r3, 24
li r4, 16
twlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlt_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twlt_2_constant:
li r3, 24
li r4, 0
twlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twle_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twle_1_constant:
li r3, 24
li r4, 16
twle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twle_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twle_2_constant:
li r3, 24
li r4, 0
twle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tweq_1:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 24
tweq r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 24
test_tweq_1_constant:
li r3, 0
li r4, 24
tweq r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 24
test_tweq_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tweq r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tweq_2_constant:
li r3, 24
li r4, 0
tweq r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twge_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
twge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twge_1_constant:
li r3, 24
li r4, 48
twge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twge_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
twge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twge_2_constant:
li r3, 0
li r4, 48
twge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twge_3:
#_ REGISTER_IN r3 -1
#_ REGISTER_IN r4 0
twge r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_twge_3_constant:
li r3, -1
li r4, 0
twge r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_twgt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
twgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twgt_1_constant:
li r3, 24
li r4, 48
twgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twgt_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
twgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twgt_2_constant:
li r3, 0
li r4, 48
twgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twgt_3:
#_ REGISTER_IN r3 -1
#_ REGISTER_IN r4 0
twgt r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_twgt_3_constant:
li r3, -1
li r4, 0
twgt r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_twnl_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
twnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twnl_1_constant:
li r3, 24
li r4, 48
twnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twnl_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
twnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twnl_2_constant:
li r3, 0
li r4, 48
twnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twnl_3:
#_ REGISTER_IN r3 -1
#_ REGISTER_IN r4 0
twnl r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_twnl_3_constant:
li r3, -1
li r4, 0
twnl r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_twne_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 24
twne r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 24
test_twne_1_constant:
li r3, 24
li r4, 24
twne r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 24
test_twne_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 0
twne r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
test_twne_2_constant:
li r3, 0
li r4, 0
twne r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
test_twng_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twng_1_constant:
li r3, 24
li r4, 16
twng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twng_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twng_2_constant:
li r3, 24
li r4, 0
twng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twng_3:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 -1
twng r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 -1
test_twng_3_constant:
li r3, 0
li r4, -1
twng r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 -1
test_twllt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twllt_1_constant:
li r3, 24
li r4, 16
twllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twllt_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twllt_2_constant:
li r3, 24
li r4, 0
twllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twlle_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlle_1_constant:
li r3, 24
li r4, 16
twlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlle_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twlle_2_constant:
li r3, 24
li r4, 0
twlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twlge_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
twlge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twlge_1_constant:
li r3, 24
li r4, 48
twlge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twlge_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
twlge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twlge_2_constant:
li r3, 0
li r4, 48
twlge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twlgt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
twlgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twlgt_1_constant:
li r3, 24
li r4, 48
twlgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twlgt_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
twlgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twlgt_2_constant:
li r3, 0
li r4, 48
twlgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twlnl_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
twlnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twlnl_1_constant:
li r3, 24
li r4, 48
twlnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_twlnl_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
twlnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twlnl_2_constant:
li r3, 0
li r4, 48
twlnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_twlng_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
twlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlng_1_constant:
li r3, 24
li r4, 16
twlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_twlng_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
twlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_twlng_2_constant:
li r3, 24
li r4, 0
twlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
|
xenia-project/xenia | 2,276 | src/xenia/cpu/ppc/testing/instr_mulhw.s | test_mulhw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_1_constant:
li r4, 1
li r5, 0
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_2_constant:
li r4, -1
clrldi r4, r4, 32
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_3_constant:
li r4, -1
clrldi r4, r4, 31
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_4_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
sldi r5, r5, 63
or r4, r4, r5
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_5_constant:
li r4, -1
li r5, 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_mulhw_6_constant:
li r4, -1
li r5, -1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
xenia-project/xenia | 4,388 | src/xenia/cpu/ppc/testing/instr_rlwnm.s | test_rlwnm_1:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 24
rlwnm r3, r4, r5, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 24
test_rlwnm_1_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 24
rlwnm r3, r4, r5, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 24
test_rlwnm_2:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 4
rlwnm r3, r4, r5, 0, 27
blr
#_ REGISTER_OUT r3 0x23456780
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 4
test_rlwnm_2_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 4
rlwnm r3, r4, r5, 0, 27
blr
#_ REGISTER_OUT r3 0x23456780
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 4
test_rlwnm_3:
#_ REGISTER_IN r4 0x90003000
#_ REGISTER_IN r5 2
rlwnm r3, r4, r5, 0, 0x1D
blr
#_ REGISTER_OUT r3 0x4000C000
#_ REGISTER_OUT r4 0x90003000
#_ REGISTER_OUT r5 2
test_rlwnm_3_constant:
lis r4, 0x9000
ori r4, r4, 0x3000
clrldi r4, r4, 32
li r5, 2
rlwnm r3, r4, r5, 0, 0x1D
blr
#_ REGISTER_OUT r3 0x4000C000
#_ REGISTER_OUT r4 0x90003000
#_ REGISTER_OUT r5 2
test_rlwnm_4:
#_ REGISTER_IN r4 0xB0043000
#_ REGISTER_IN r5 2
rlwnm. r3, r4, r5, 0, 0x1D
blr
#_ REGISTER_OUT r3 0xC010C000
#_ REGISTER_OUT r4 0xB0043000
#_ REGISTER_OUT r5 2
# CRF = 0x8
test_rlwnm_4_constant:
lis r4, 0xB004
ori r4, r4, 0x3000
clrldi r4, r4, 32
li r5, 2
rlwnm. r3, r4, r5, 0, 0x1D
blr
#_ REGISTER_OUT r3 0xC010C000
#_ REGISTER_OUT r4 0xB0043000
#_ REGISTER_OUT r5 2
# CRF = 0x8
test_rlwnm_5:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 0
rlwnm r3, r4, r5, 5, 0x1D
blr
#_ REGISTER_OUT r3 0x02345678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_5_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 0
rlwnm r3, r4, r5, 5, 0x1D
blr
#_ REGISTER_OUT r3 0x02345678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_6:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 0
rlwnm r3, r4, r5, 0, 31
blr
#_ REGISTER_OUT r3 0x12345678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_6_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 0
rlwnm r3, r4, r5, 0, 31
blr
#_ REGISTER_OUT r3 0x12345678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_7:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 0
rlwnm r3, r4, r5, 0, 16
blr
#_ REGISTER_OUT r3 0x12340000
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_7_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 0
rlwnm r3, r4, r5, 0, 16
blr
#_ REGISTER_OUT r3 0x12340000
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_8:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 0
rlwnm r3, r4, r5, 16, 31
blr
#_ REGISTER_OUT r3 0x00005678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_8_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 0
rlwnm r3, r4, r5, 16, 31
blr
#_ REGISTER_OUT r3 0x00005678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 0
test_rlwnm_9:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 16
rlwnm r3, r4, r5, 16, 31
blr
#_ REGISTER_OUT r3 0x00001234
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 16
test_rlwnm_9_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 16
rlwnm r3, r4, r5, 16, 31
blr
#_ REGISTER_OUT r3 0x00001234
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 16
test_rlwnm_10:
#_ REGISTER_IN r4 0x12345678
#_ REGISTER_IN r5 32
rlwnm r3, r4, r5, 0, 31
blr
#_ REGISTER_OUT r3 0x12345678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 32
test_rlwnm_10_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
li r5, 32
rlwnm r3, r4, r5, 0, 31
blr
#_ REGISTER_OUT r3 0x12345678
#_ REGISTER_OUT r4 0x12345678
#_ REGISTER_OUT r5 32
test_rlwnm_11:
#_ REGISTER_IN r0 0x1
rlwnm r0, r0, r0, 1, 0
blr
#_ REGISTER_OUT r0 0x0000000200000002
test_rlwnm_12:
#_ REGISTER_IN r3 0xFFFFFFFF
rlwnm r0, r3, r3, 30, 1
blr
#_ REGISTER_OUT r0 0xFFFFFFFFC0000003
#_ REGISTER_OUT r3 0xFFFFFFFF
test_rlwnm_13:
#_ REGISTER_IN r7 0x01234567
#_ REGISTER_IN r8 0x0123456789ABCDEFull
rlwnm r6, r8, r7, 31, 30
blr
#_ REGISTER_OUT r6 0xD5E6F7C4D5E6F7C4
#_ REGISTER_OUT r7 0x01234567
#_ REGISTER_OUT r8 0x0123456789ABCDEFull
|
xenia-project/xenia | 3,869 | src/xenia/cpu/ppc/testing/instr_slw.s | test_slw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_slw_1_constant:
li r4, 1
li r5, 0
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_slw_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_slw_2_constant:
li r4, -1
li r5, 0
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_slw_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_slw_3_constant:
li r4, -1
li r5, 1
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_slw_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_slw_4_constant:
li r4, -1
li r5, 63
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_slw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_slw_5_constant:
li r4, -1
li r5, 64
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_slw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
test_slw_6_constant:
li r4, -1
li r5, 100
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
test_slw_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 30
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000c0000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
test_slw_7_constant:
li r4, -1
li r5, 30
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000c0000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
test_slw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 31
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000080000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
test_slw_8_constant:
li r4, -1
li r5, 31
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000080000000
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
test_slw_9:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 32
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
test_slw_9_constant:
li r4, -1
li r5, 32
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
test_slw_10:
#_ REGISTER_IN r4 99
#_ REGISTER_IN r5 1
cntlzw r5, r5
subi r5, r5, 28
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 792
#_ REGISTER_OUT r4 99
#_ REGISTER_OUT r5 3
test_slw_10_constant:
#_ REGISTER_IN r4 99
li r5, 1
cntlzw r5, r5
subi r5, r5, 28
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 792
#_ REGISTER_OUT r4 99
#_ REGISTER_OUT r5 3
test_slw_11:
#_ REGISTER_IN r4 99
#_ REGISTER_IN r5 3
li r5, 3
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 792
#_ REGISTER_OUT r4 99
#_ REGISTER_OUT r5 3
test_slw_11_constant:
#_ REGISTER_IN r4 99
li r5, 3
slw r3, r4, r5
blr
#_ REGISTER_OUT r3 792
#_ REGISTER_OUT r4 99
#_ REGISTER_OUT r5 3
|
xenia-project/xenia | 5,645 | src/xenia/cpu/ppc/testing/instr_rlwinm.s | test_rlwinm_1:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 24, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_1_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 24, 8, 15
blr
#_ REGISTER_OUT r3 0x00120000
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_2:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 4, 0, 27
blr
#_ REGISTER_OUT r3 0x23456780
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_2_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 4, 0, 27
blr
#_ REGISTER_OUT r3 0x23456780
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_3:
#_ REGISTER_IN r4 0x90003000
rlwinm r3, r4, 2, 0, 0x1D
blr
#_ REGISTER_OUT r3 0x4000C000
#_ REGISTER_OUT r4 0x90003000
test_rlwinm_3_constant:
lis r4, 0x9000
ori r4, r4, 0x3000
clrldi r4, r4, 32
rlwinm r3, r4, 2, 0, 0x1D
blr
#_ REGISTER_OUT r3 0x4000C000
#_ REGISTER_OUT r4 0x90003000
test_rlwinm_4:
#_ REGISTER_IN r4 0xB0043000
rlwinm. r3, r4, 2, 0, 0x1D
blr
#_ REGISTER_OUT r3 0xC010C000
#_ REGISTER_OUT r4 0xB0043000
# CRF = 0x8
test_rlwinm_4_constant:
lis r4, 0xB004
ori r4, r4, 0x3000
clrldi r4, r4, 32
rlwinm. r3, r4, 2, 0, 0x1D
blr
#_ REGISTER_OUT r3 0xC010C000
#_ REGISTER_OUT r4 0xB0043000
# CRF = 0x8
test_rlwinm_5:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 0, 5, 0x1D
blr
#_ REGISTER_OUT r3 0x02345678
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_5_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 0, 5, 0x1D
blr
#_ REGISTER_OUT r3 0x02345678
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_6:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 0, 0, 31
blr
#_ REGISTER_OUT r3 0x12345678
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_6_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 0, 0, 31
blr
#_ REGISTER_OUT r3 0x12345678
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_7:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 0, 0, 16
blr
#_ REGISTER_OUT r3 0x12340000
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_7_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 0, 0, 16
blr
#_ REGISTER_OUT r3 0x12340000
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_8:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 0, 16, 31
blr
#_ REGISTER_OUT r3 0x00005678
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_8_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 0, 16, 31
blr
#_ REGISTER_OUT r3 0x00005678
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_9:
#_ REGISTER_IN r4 0x12345678
rlwinm r3, r4, 16, 16, 31
blr
#_ REGISTER_OUT r3 0x00001234
#_ REGISTER_OUT r4 0x12345678
test_rlwinm_9_constant:
lis r4, 0x1234
ori r4, r4, 0x5678
rlwinm r3, r4, 16, 16, 31
blr
#_ REGISTER_OUT r3 0x00001234
#_ REGISTER_OUT r4 0x12345678
# Extract and right justify immediate
# extrwi RA, RS, n, b
# rlwinm RA, RS, b+n, 32-n, 31
test_extrwi_1:
# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
#_ REGISTER_IN r5 0x30
rlwinm r7, r5, 29, 28, 31
#extrwi r7, r5, 4, 25
blr
#_ REGISTER_OUT r5 0x30
#_ REGISTER_OUT r7 0x06
test_extrwi_1_constant:
# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
li r5, 0x30
rlwinm r7, r5, 29, 28, 31
#extrwi r7, r5, 4, 25
blr
#_ REGISTER_OUT r5 0x30
#_ REGISTER_OUT r7 0x06
test_extrwi_2:
#_ REGISTER_IN r5 0xFFFFFFFF01234567
rlwinm r7, r5, 26, 16, 31
#extrwi r7, r5, 16, 10
blr
#_ REGISTER_OUT r5 0xFFFFFFFF01234567
#_ REGISTER_OUT r7 0x0000000000008D15
test_extrwi_2_constant:
li r5, -1
sldi r5, r5, 32
oris r5, r5, 0x0123
ori r5, r5, 0x4567
rlwinm r7, r5, 26, 16, 31
#extrwi r7, r5, 16, 10
blr
#_ REGISTER_OUT r5 0xFFFFFFFF01234567
#_ REGISTER_OUT r7 0x0000000000008D15
test_extrwi_cr_1:
#_ REGISTER_IN r5 0x30
rlwinm. r7, r5, 29, 28, 31
#extrwi. r7, r5, 4, 25
mfcr r12
blr
#_ REGISTER_OUT r5 0x30
#_ REGISTER_OUT r7 0x06
#_ REGISTER_OUT r12 0x40000000
test_extrwi_cr_1_constant:
li r5, 0x30
rlwinm. r7, r5, 29, 28, 31
#extrwi. r7, r5, 4, 25
mfcr r12
blr
#_ REGISTER_OUT r5 0x30
#_ REGISTER_OUT r7 0x06
#_ REGISTER_OUT r12 0x40000000
test_extrwi_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFF01234567
rlwinm. r7, r5, 26, 16, 31
#extrwi. r7, r5, 16, 10
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFF01234567
#_ REGISTER_OUT r7 0x0000000000008D15
#_ REGISTER_OUT r12 0x40000000
test_extrwi_cr_2_constant:
li r5, -1
sldi r5, r5, 32
oris r5, r5, 0x0123
ori r5, r5, 0x4567
rlwinm. r7, r5, 26, 16, 31
#extrwi. r7, r5, 16, 10
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFF01234567
#_ REGISTER_OUT r7 0x0000000000008D15
#_ REGISTER_OUT r12 0x40000000
test_extrwi_cr_3:
#_ REGISTER_IN r5 0xFFFFFFFF00000000
rlwinm. r7, r5, 26, 16, 31
#extrwi. r7, r5, 16, 10
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
#_ REGISTER_OUT r7 0x0000000000000000
#_ REGISTER_OUT r12 0x20000000
test_extrwi_cr_3_constant:
li r5, -1
sldi r5, r5, 32
rlwinm. r7, r5, 26, 16, 31
#extrwi. r7, r5, 16, 10
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
#_ REGISTER_OUT r7 0x0000000000000000
#_ REGISTER_OUT r12 0x20000000
test_rlwinm_10:
#_ REGISTER_IN r7 0x01234567
rlwinm r6, r7, 31, 31, 1
blr
#_ REGISTER_OUT r6 0x8091A2B380000001
#_ REGISTER_OUT r7 0x01234567
test_rlwinm_11:
#_ REGISTER_IN r8 0x0123456789ABCDEF
rlwinm r6, r8, 8, 2, 0
blr
#_ REGISTER_OUT r6 0xABCDEF89ABCDEF89
#_ REGISTER_OUT r8 0x0123456789ABCDEF
test_rlwinm_12:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
rlwinm r7, r4, 31, 30, 1
blr
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r7 0xFFFFFFFFC0000003
|
xenia-project/xenia | 2,681 | src/xenia/cpu/ppc/testing/instr_vctuxs.s | # 0 * 2^31
test_vctuxs_1:
#_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000]
vctuxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# -0 ^ 2^31
test_vctuxs_2:
#_ REGISTER_IN v0 [80000000, 80000000, 80000000, 80000000]
vctuxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [80000000, 80000000, 80000000, 80000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# smallest positive subnormal * 2^31
test_vctuxs_3:
#_ REGISTER_IN v0 [00000001, 00000001, 00000001, 00000001]
vctuxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# largest subnormal * 2^31
test_vctuxs_4:
#_ REGISTER_IN v0 [007FFFFF, 007FFFFF, 007FFFFF, 007FFFFF]
vctuxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [007FFFFF, 007FFFFF, 007FFFFF, 007FFFFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# +1 * 2^0
test_vctuxs_5:
#_ REGISTER_IN v0 [3F800000, 3F800000, 3F800000, 3F800000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [3F800000, 3F800000, 3F800000, 3F800000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
# -1 * 2^0
test_vctuxs_6:
#_ REGISTER_IN v0 [BF800000, BF800000, BF800000, BF800000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [BF800000, BF800000, BF800000, BF800000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# 2^31 * 2^0
test_vctuxs_7:
#_ REGISTER_IN v0 [4F000000, 4F000000, 4F000000, 4F000000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [4F000000, 4F000000, 4F000000, 4F000000]
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
# 2^31 * 1.5 * 2^0
test_vctuxs_8:
#_ REGISTER_IN v0 [4F400000, 4F400000, 4F400000, 4F400000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [4F400000, 4F400000, 4F400000, 4F400000]
#_ REGISTER_OUT v3 [C0000000, C0000000, C0000000, C0000000]
# 2^32 * 2^0
test_vctuxs_9:
#_ REGISTER_IN v0 [4F800000, 4F800000, 4F800000, 4F800000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [4F800000, 4F800000, 4F800000, 4F800000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# +infinity * 2^0
test_vctuxs_10:
#_ REGISTER_IN v0 [7F800000, 7F800000, 7F800000, 7F800000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [7F800000, 7F800000, 7F800000, 7F800000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# -infinity * 2^0
test_vctuxs_11:
#_ REGISTER_IN v0 [FF800000, FF800000, FF800000, FF800000]
vctuxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [FF800000, FF800000, FF800000, FF800000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
xenia-project/xenia | 1,399 | src/xenia/cpu/ppc/testing/instr_vmrghw.s | test_vmrghw_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
vmrghw v5, v3, v4
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [00010203, 10111213, 04050607, 14151617]
test_vmrghw_2:
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vmrghw v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
#_ REGISTER_OUT v5 [00000000, 00000004, 00000001, 00000005]
test_vmrghw_3:
#_ REGISTER_IN v3 [C0800000, C0400000, C0000000, BF800000]
#_ REGISTER_IN v4 [00000000, 3F800000, 40000000, 40400000]
vmrghw v5, v3, v4
blr
#_ REGISTER_OUT v3 [C0800000, C0400000, C0000000, BF800000]
#_ REGISTER_OUT v4 [00000000, 3F800000, 40000000, 40400000]
#_ REGISTER_OUT v5 [C0800000, 00000000, C0400000, 3F800000]
test_vmrghw_4:
#_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
vmrghw v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v5 [FFFFFFFC, 00000000, FFFFFFFD, 00000001]
|
xenia-project/xenia | 2,190 | src/xenia/cpu/ppc/testing/instr_subfc.s | test_subfc_1:
#_ REGISTER_IN r10 0x00000000000103BF
#_ REGISTER_IN r11 0x00000000000103C0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfc_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
lis r11, 1
ori r11, r11, 0x03C0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfc_2:
#_ REGISTER_IN r10 0
#_ REGISTER_IN r11 0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfc_2_constant:
li r10, 0
li r11, 0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfc_3:
#_ REGISTER_IN r10 1
#_ REGISTER_IN r11 0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_subfc_3_constant:
li r10, 1
li r11, 0
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_subfc_4:
#_ REGISTER_IN r10 0
#_ REGISTER_IN r11 1
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 1
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfc_4_constant:
li r10, 0
li r11, 1
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 1
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfc_5:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfc_5_constant:
li r10, -1
li r11, -1
subfc r3, r10, r11
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
|
xenia-project/xenia | 2,054 | src/xenia/cpu/ppc/testing/instr_vsel.s | test_vsel_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsel_2:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
test_vsel_3:
#_ REGISTER_IN v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [10101010, 10101010, 10101010, 10101010]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [1C111213, 14151617, 18191A1B, 1C1D1E1F]
test_vsel_4:
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v5 [01234567, 89ABCDEF, FEDCBA98, 76543210]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v5 [01234567, 89ABCDEF, FEDCBA98, 76543210]
test_vsel_5:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v5 [01234567, 89ABCDEF, FEDCBA98, 76543210]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v5 [FEDCBA98, 76543210, 01234567, 89ABCDEF]
|
xenia-project/xenia | 1,703 | src/xenia/cpu/ppc/testing/instr_vslh.s | test_vslh_1:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
test_vslh_2:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
test_vslh_3:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [000F000F, 000F000F, 000F000F, 000F000F]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
#_ REGISTER_OUT v4 [000F000F, 000F000F, 000F000F, 000F000F]
test_vslh_4:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00100010, 00100010, 00100010, 00100010]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00100010, 00100010, 00100010, 00100010]
test_vslh_5:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00090009, 00090009, 00090009, 00090009]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [FE00FE00, FE00FE00, FE00FE00, FE00FE00]
#_ REGISTER_OUT v4 [00090009, 00090009, 00090009, 00090009]
test_vslh_6:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00110011, 00110011, 00110011, 00110011]
vslh v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]
#_ REGISTER_OUT v4 [00110011, 00110011, 00110011, 00110011]
|
xenia-project/xenia | 4,311 | src/xenia/cpu/ppc/testing/instr_divw.s | test_divw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
test_divw_1_constant:
li r4, 1
li r5, 2
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
# TODO(benvanik): x64 ignore divide by zero (=0)
#test_divw_2:
# #_ REGISTER_IN r4 1
# #_ REGISTER_IN r5 0
# divw r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 0
# TODO(benvanik): x64 ignore divide by zero (=0)
#test_divw_2_constant:
# li r4, 1
# li r5, 0
# divw r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 0
test_divw_3:
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 1
test_divw_3_constant:
li r4, 2
li r5, 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 1
test_divw_4:
#_ REGISTER_IN r4 35
#_ REGISTER_IN r5 7
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 35
#_ REGISTER_OUT r5 7
test_divw_4_constant:
li r4, 35
li r5, 7
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 35
#_ REGISTER_OUT r5 7
test_divw_5:
#_ REGISTER_IN r4 0
#_ REGISTER_IN r5 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_divw_5_constant:
li r4, 0
li r5, 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_divw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_divw_6_constant:
li r4, -1
li r5, 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_divw_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divw_7_constant:
li r4, -1
li r5, -1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divw_8:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divw_8_constant:
li r4, 1
li r5, -1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divw_9:
#_ REGISTER_IN r4 0x000000007FFFFFFF
#_ REGISTER_IN r5 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 1
test_divw_9_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 1
test_divw_10:
#_ REGISTER_IN r4 0x000000007FFFFFFF
#_ REGISTER_IN r5 0x000000007FFFFFFF
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divw_10_constant:
li r4, -1
clrldi r4, r4, 33
mr r5, r4
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divw_11:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0x000000007FFFFFFF
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divw_11_constant:
li r4, 1
li r5, -1
clrldi r5, r5, 33
divw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
# TODO(benvanik): integer overflow (=0)
#test_divw_12:
# #_ REGISTER_IN r4 0x80000000
# #_ REGISTER_IN r5 -1
# divw r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 0x80000000
# #_ REGISTER_OUT r5 -1
# TODO(benvanik): integer overflow (=0)
#test_divw_12_constant:
# li r4, 1
# srdi r4, 31
# li r5, -1
# divw r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 0x80000000
# #_ REGISTER_OUT r5 -1
|
xenia-project/xenia | 7,743 | src/xenia/cpu/ppc/testing/instr_td.s | test_tdlt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlt_1_constant:
li r3, 24
li r4, 16
tdlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlt_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdlt_2_constant:
li r3, 24
li r4, 0
tdlt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdle_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdle_1_constant:
li r3, 24
li r4, 16
tdle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdle_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdle_2_constant:
li r3, 24
li r4, 0
tdle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdeq_1:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 24
tdeq r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 24
test_tdeq_1_constant:
li r3, 0
li r4, 24
tdeq r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 24
test_tdeq_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdeq r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdeq_2_constant:
li r3, 24
li r4, 0
tdeq r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdge_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
tdge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdge_1_constant:
li r3, 24
li r4, 48
tdge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdge_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
tdge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdge_2_constant:
li r3, 0
li r4, 48
tdge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdge_3:
#_ REGISTER_IN r3 -1
#_ REGISTER_IN r4 0
tdge r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_tdge_3_constant:
li r3, -1
li r4, 0
tdge r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_tdgt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
tdgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdgt_1_constant:
li r3, 24
li r4, 48
tdgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdgt_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
tdgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdgt_2_constant:
li r3, 0
li r4, 48
tdgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdgt_3:
#_ REGISTER_IN r3 -1
#_ REGISTER_IN r4 0
tdgt r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_tdgt_3_constant:
li r3, -1
li r4, 0
tdgt r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_tdnl_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
tdnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdnl_1_constant:
li r3, 24
li r4, 48
tdnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdnl_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
tdnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdnl_2_constant:
li r3, 0
li r4, 48
tdnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdnl_3:
#_ REGISTER_IN r3 -1
#_ REGISTER_IN r4 0
tdnl r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_tdnl_3_constant:
li r3, -1
li r4, 0
tdnl r3, r4
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_tdne_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 24
tdne r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 24
test_tdne_1_constant:
li r3, 24
li r4, 24
tdne r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 24
test_tdne_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 0
tdne r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
test_tdne_2_constant:
li r3, 0
li r4, 0
tdne r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
test_tdng_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdng_1_constant:
li r3, 24
li r4, 16
tdng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdng_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdng_2_constant:
li r3, 24
li r4, 0
tdng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdng_3:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 -1
tdng r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 -1
test_tdng_3_constant:
li r3, 0
li r4, -1
tdng r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 -1
test_tdllt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdllt_1_constant:
li r3, 24
li r4, 16
tdllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdllt_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdllt_2_constant:
li r3, 24
li r4, 0
tdllt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdlle_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlle_1_constant:
li r3, 24
li r4, 16
tdlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlle_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdlle_2_constant:
li r3, 24
li r4, 0
tdlle r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdlge_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
tdlge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdlge_1_constant:
li r3, 24
li r4, 48
tdlge r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdlge_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
tdlge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdlge_2_constant:
li r3, 0
li r4, 48
tdlge r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdlgt_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
tdlgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdlgt_1_constant:
li r3, 24
li r4, 48
tdlgt r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdlgt_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
tdlgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdlgt_2_constant:
li r3, 0
li r4, 48
tdlgt r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdlnl_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 48
tdlnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdlnl_1_constant:
li r3, 24
li r4, 48
tdlnl r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 48
test_tdlnl_2:
#_ REGISTER_IN r3 0
#_ REGISTER_IN r4 48
tdlnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdlnl_2_constant:
li r3, 0
li r4, 48
tdlnl r3, r4
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 48
test_tdlng_1:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 16
tdlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlng_1_constant:
li r3, 24
li r4, 16
tdlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 16
test_tdlng_2:
#_ REGISTER_IN r3 24
#_ REGISTER_IN r4 0
tdlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
test_tdlng_2_constant:
li r3, 24
li r4, 0
tdlng r3, r4
blr
#_ REGISTER_OUT r3 24
#_ REGISTER_OUT r4 0
|
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_vsro.s | test_vsro_1:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsro v3, v3, v4
blr
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsro_2:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
vsro v3, v3, v4
blr
#_ REGISTER_OUT v3 [00001122, 33445566, 778899AA, BBCCDDEE]
#_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
test_vsro_3:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [12121212, 12121212, 12121212, 12121212]
vsro v3, v3, v4
blr
#_ REGISTER_OUT v3 [00000011, 22334455, 66778899, AABBCCDD]
#_ REGISTER_OUT v4 [12121212, 12121212, 12121212, 12121212]
test_vsro_4:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
vsro v3, v3, v4
blr
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
test_vsro_5:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsro v3, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
xenia-project/xenia | 2,535 | src/xenia/cpu/ppc/testing/instr_eqv.s | test_eqv_1:
#_ REGISTER_IN r4 0
#_ REGISTER_IN r5 1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_eqv_1_constant:
li r4, 0
li r5, 1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_eqv_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_eqv_2_constant:
li r4, -1
li r5, 0
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_eqv_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_3_constant:
li r4, -1
li r5, -1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_4:
#_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
#_ REGISTER_IN r5 0xDEADBEEFDEADBEEF
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
test_eqv_4_constant:
lis r4, 0xDEAD
ori r4, r4, 0xBEEF
sldi r5, r4, 32
clrldi r4, r4, 32
or r4, r5, r4
mr r5, r4
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xDEADBEEFDEADBEEF
test_eqv_5:
#_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_5_constant:
lis r4, 0xDEAD
ori r4, r4, 0xBEEF
sldi r5, r4, 32
clrldi r4, r4, 32
or r4, r5, r4
li r5, -1
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_eqv_6:
#_ REGISTER_IN r4 0xDEADBEEFDEADBEEF
#_ REGISTER_IN r5 0
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0x2152411021524110
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0
test_eqv_6_constant:
lis r4, 0xDEAD
ori r4, r4, 0xBEEF
sldi r5, r4, 32
clrldi r4, r4, 32
or r4, r5, r4
li r5, 0
eqv r3, r4, r5
blr
#_ REGISTER_OUT r3 0x2152411021524110
#_ REGISTER_OUT r4 0xDEADBEEFDEADBEEF
#_ REGISTER_OUT r5 0
|
xenia-project/xenia | 1,817 | src/xenia/cpu/ppc/testing/instr_srawi.s | test_srawi_1:
#_ REGISTER_IN r4 1
srawi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_srawi_1_constant:
li r4, 1
srawi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_srawi_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
srawi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
test_srawi_2_constant:
li r4, -1
srawi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
test_srawi_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
srawi r3, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_srawi_3_constant:
li r4, -1
srawi r3, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_srawi_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
srawi r3, r4, 30
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_srawi_4_constant:
li r4, -1
srawi r3, r4, 30
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_srawi_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
srawi r3, r4, 31
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_srawi_5_constant:
li r4, -1
srawi r3, r4, 31
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
|
xenia-project/xenia | 2,847 | src/xenia/cpu/ppc/testing/instr_stvew.s | test_stvew_1:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x10001050
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001050
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
test_stvew_1_constant:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
lis r4, 0x1000
ori r4, r4, 0x1050
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001050
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
test_stvew_2:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x10001054
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001054
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
test_stvew_2_constant:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
lis r4, 0x1000
ori r4, r4, 0x1054
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001054
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
test_stvew_3:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x10001058
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001058
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
test_stvew_3_constant:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
lis r4, 0x1000
ori r4, r4, 0x1058
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001058
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
test_stvew_4:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x1000105C
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x1000105C
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F
test_stvew_4_constant:
#_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
lis r4, 0x1000
ori r4, r4, 0x105C
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x1000105C
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F
|
xenia-project/xenia | 1,219 | src/xenia/cpu/ppc/testing/instr_vpkshss.s | test_vpkshss_1:
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vpkshss v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vpkshss_2:
#_ REGISTER_IN v3 [7FFF8000, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
vpkshss v5, v3, v4
blr
#_ REGISTER_OUT v3 [7FFF8000, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vpkshss_3:
# {-1, -128, 0, 127, -2, -129, 1, 128}
#_ REGISTER_IN v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
# {-3, -130, 2, 129, -4, -131, 3, 130}
#_ REGISTER_IN v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vpkshss v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
# {-1, -128, 0, 127, -2, -128, 1, 127,
# -3, -128, 2, 127, -4, -128, 3, 127}
#_ REGISTER_OUT v5 [FF80007F, FE80017F, FD80027F, FC80037F]
|
xenia-project/xenia | 6,555 | src/xenia/cpu/ppc/testing/instr_addze.s | test_addze_1:
#_ REGISTER_IN r4 1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_addze_1_constant:
li r4, 1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_addze_2:
#_ REGISTER_IN r4 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_addze_2_constant:
li r4, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_addze_3:
#_ REGISTER_IN r4 12
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
test_addze_3_constant:
li r4, 12
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
test_addze_4:
#_ REGISTER_IN r4 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 13
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
test_addze_4_constant:
li r4, 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 13
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
test_addze_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
test_addze_5_constant:
li r4, -1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
test_addze_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addze_6_constant:
li r4, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addze_7:
#_ REGISTER_IN r4 0
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addze_7_constant:
li r4, 0
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addze_8:
#_ REGISTER_IN r4 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addze_8_constant:
li r4, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze r3, r4
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addze_cr_1:
#_ REGISTER_IN r4 1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_1_constant:
li r4, 1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_2:
#_ REGISTER_IN r4 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_2_constant:
li r4, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_3:
#_ REGISTER_IN r4 12
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_3_constant:
li r4, 12
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_4:
#_ REGISTER_IN r4 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 13
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_4_constant:
li r4, 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 13
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addze_cr_5_constant:
li r4, -1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addze_cr_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_6_constant:
li r4, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_7:
#_ REGISTER_IN r4 0
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_7_constant:
li r4, 0
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_8:
#_ REGISTER_IN r4 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_8_constant:
li r4, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 1,049 | src/xenia/cpu/ppc/testing/instr_vmrglh.s | test_vmrglh_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
vmrglh v5, v3, v4
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [08091819, 0a0b1a1b, 0c0d1c1d, 0e0f1e1f]
test_vmrglh_2:
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vmrglh v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [0004000C, 0005000D, 0006000E, 0007000F]
test_vmrglh_3:
#_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
#_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007]
vmrglh v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
#_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v5 [FFFC0004, FFFD0005, FFFE0006, FFFF0007]
|
xenia-project/xenia | 2,195 | src/xenia/cpu/ppc/testing/instr_vctsxs.s | # 0 * 2^31
test_vctsxs_1:
#_ REGISTER_IN v0 [00000000, 00000000, 00000000, 00000000]
vctsxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# -0 ^ 2^31
test_vctsxs_2:
#_ REGISTER_IN v0 [80000000, 80000000, 80000000, 80000000]
vctsxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [80000000, 80000000, 80000000, 80000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# smallest positive subnormal * 2^31
test_vctsxs_3:
#_ REGISTER_IN v0 [00000001, 00000001, 00000001, 00000001]
vctsxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# largest subnormal * 2^31
test_vctsxs_4:
#_ REGISTER_IN v0 [007FFFFF, 007FFFFF, 007FFFFF, 007FFFFF]
vctsxs v3, v0, 31
blr
#_ REGISTER_OUT v0 [007FFFFF, 007FFFFF, 007FFFFF, 007FFFFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
# +1 * 2^0
test_vctsxs_5:
#_ REGISTER_IN v0 [3F800000, 3F800000, 3F800000, 3F800000]
vctsxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [3F800000, 3F800000, 3F800000, 3F800000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
# -1 * 2^0
test_vctsxs_6:
#_ REGISTER_IN v0 [BF800000, BF800000, BF800000, BF800000]
vctsxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [BF800000, BF800000, BF800000, BF800000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
# 2^31 * 2^0
test_vctsxs_7:
#_ REGISTER_IN v0 [4F000000, 4F000000, 4F000000, 4F000000]
vctsxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [4F000000, 4F000000, 4F000000, 4F000000]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
# +infinity * 2^0
test_vctsxs_8:
#_ REGISTER_IN v0 [7F800000, 7F800000, 7F800000, 7F800000]
vctsxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [7F800000, 7F800000, 7F800000, 7F800000]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
# -infinity * 2^0
test_vctsxs_9:
#_ REGISTER_IN v0 [FF800000, FF800000, FF800000, FF800000]
vctsxs v3, v0, 0
blr
#_ REGISTER_OUT v0 [FF800000, FF800000, FF800000, FF800000]
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_vslb.s | test_vslb_1:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
vslb v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
test_vslb_2:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
vslb v3, v3, v4
blr
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
test_vslb_3:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
vslb v3, v3, v4
blr
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
test_vslb_4:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
vslb v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
test_vslb_5:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [09090909, 09090909, 09090909, 09090909]
vslb v3, v3, v4
blr
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v4 [09090909, 09090909, 09090909, 09090909]
|
xenia-project/xenia | 1,703 | src/xenia/cpu/ppc/testing/instr_vslw.s | test_vslw_1:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
test_vslw_2:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
test_vslw_3:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [0000001F, 0000001F, 0000001F, 0000001F]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
#_ REGISTER_OUT v4 [0000001F, 0000001F, 0000001F, 0000001F]
test_vslw_4:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000020, 00000020, 00000020, 00000020]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v4 [00000020, 00000020, 00000020, 00000020]
test_vslw_5:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000009, 00000009, 00000009, 00000009]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFE00, FFFFFE00, FFFFFE00, FFFFFE00]
#_ REGISTER_OUT v4 [00000009, 00000009, 00000009, 00000009]
test_vslw_6:
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v4 [00000021, 00000021, 00000021, 00000021]
vslw v3, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
#_ REGISTER_OUT v4 [00000021, 00000021, 00000021, 00000021]
|
xenia-project/xenia | 3,946 | src/xenia/cpu/ppc/testing/instr_srw.s | test_srw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srw_1_constant:
li r4, 1
li r5, 0
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srw_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_srw_2_constant:
li r4, -1
li r5, 0
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_srw_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_srw_3_constant:
li r4, -1
li r5, 1
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_srw_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_srw_4_constant:
li r4, -1
li r5, 63
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_srw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_srw_5_constant:
li r4, -1
li r5, 64
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_srw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
test_srw_6_constant:
li r4, -1
li r5, 100
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
test_srw_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 30
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000003
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
test_srw_7_constant:
li r4, -1
li r5, 30
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000003
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
test_srw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 31
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
test_srw_8_constant:
li r4, -1
li r5, 31
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
test_srw_9:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 32
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
test_srw_9_constant:
li r4, -1
li r5, 32
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
test_srw_10:
#_ REGISTER_IN r4 0x0000000090003000
#_ REGISTER_IN r5 36
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x0000000090003000
#_ REGISTER_OUT r5 36
test_srw_10_constant:
lis r4, 0x9000
ori r4, r4, 0x3000
li r5, 36
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFF90003000
#_ REGISTER_OUT r5 36
test_srw_11:
#_ REGISTER_IN r4 0x00000000B0043001
#_ REGISTER_IN r5 4
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000000B004300
#_ REGISTER_OUT r4 0x00000000B0043001
#_ REGISTER_OUT r5 4
test_srw_11_constant:
lis r4, 0xB004
ori r4, r4, 0x3001
li r5, 4
srw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000000B004300
#_ REGISTER_OUT r4 0xFFFFFFFFB0043001
#_ REGISTER_OUT r5 4
|
xenia-project/xenia | 2,527 | src/xenia/cpu/ppc/testing/instr_vcmpxxfp.s | test_vcmpxxfp_1:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
vcmpeqfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [ffffffff, ffffffff, ffffffff, ffffffff]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT r3 0x00000080
test_vcmpxxfp_2:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800001, 3f800000, 3f800000, 3f800000]
vcmpeqfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [00000000, ffffffff, ffffffff, ffffffff]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800001, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT r3 0x00000000
test_vcmpxxfp_3:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800001, 3f800001, 3f800001, 3f800001]
vcmpeqfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800001, 3f800001, 3f800001, 3f800001]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp_1:
# [5.0, 5.0, 5.0, 5.0]
#_ REGISTER_IN v4 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp_2:
# [-5.0, -5.0, -5.0, -5.0]
#_ REGISTER_IN v4 [C0A00000, C0A00000, C0A00000, C0A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [C0A00000, C0A00000, C0A00000, C0A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp_3:
# [7.0, -7.0, 5.0, 5.0]
#_ REGISTER_IN v4 [40E00000, C0E00000, 40A00000, 40A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [40E00000, C0E00000, 40A00000, 40A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [80000000, 40000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000000
|
xenia-project/xenia | 4,625 | src/xenia/cpu/ppc/testing/instr_divwu.s | test_divwu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
test_divwu_1_constant:
li r4, 1
li r5, 2
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
# TODO(benvanik): x64 ignore divide by zero (=0)
#test_divwu_2:
# #_ REGISTER_IN r4 1
# #_ REGISTER_IN r5 0
# divwu r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 0
# TODO(benvanik): x64 ignore divide by zero (=0)
#test_divwu_2_constant:
# li r4, 1
# li r5, 0
# divwu r3, r4, r5
# blr
# #_ REGISTER_OUT r3 0
# #_ REGISTER_OUT r4 1
# #_ REGISTER_OUT r5 0
test_divwu_3:
#_ REGISTER_IN r4 2
#_ REGISTER_IN r5 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 1
test_divwu_3_constant:
li r4, 2
li r5, 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r5 1
test_divwu_4:
#_ REGISTER_IN r4 35
#_ REGISTER_IN r5 7
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 35
#_ REGISTER_OUT r5 7
test_divwu_4_constant:
li r4, 35
li r5, 7
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 5
#_ REGISTER_OUT r4 35
#_ REGISTER_OUT r5 7
test_divwu_5:
#_ REGISTER_IN r4 0
#_ REGISTER_IN r5 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_divwu_5_constant:
li r4, 0
li r5, 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r5 1
test_divwu_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_divwu_6_constant:
li r4, -1
li r5, 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_divwu_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divwu_7_constant:
li r4, -1
li r5, -1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divwu_8:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divwu_8_constant:
li r4, 1
li r5, -1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
test_divwu_9:
#_ REGISTER_IN r4 0x000000007FFFFFFF
#_ REGISTER_IN r5 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 1
test_divwu_9_constant:
li r4, -1
clrldi r4, r4, 33
li r5, 1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 1
test_divwu_10:
#_ REGISTER_IN r4 0x000000007FFFFFFF
#_ REGISTER_IN r5 0x000000007FFFFFFF
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divwu_10_constant:
li r4, -1
clrldi r4, r4, 33
mr r5, r4
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0x000000007FFFFFFF
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divwu_11:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0x000000007FFFFFFF
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divwu_11_constant:
li r4, 1
li r5, -1
clrldi r5, r5, 33
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_divwu_12:
#_ REGISTER_IN r4 0x80000000
#_ REGISTER_IN r5 -1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x80000000
#_ REGISTER_OUT r5 -1
test_divwu_12_constant:
li r4, 1
sldi r4, r4, 31
li r5, -1
divwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x80000000
#_ REGISTER_OUT r5 -1
test_divwu_13:
#_ REGISTER_IN r0 0x1
#_ REGISTER_IN r3 0xFFFFFFFF
divwu. r0, r3, r0
blr
#_ REGISTER_OUT r0 0xFFFFFFFF
#_ REGISTER_OUT r3 0xFFFFFFFF
#_ REGISTER_OUT cr 0x0000000080000000
test_divwu_14:
#_ REGISTER_IN r0 0x1
#_ REGISTER_IN r3 0xFFFFFFFF
divwu. r0, r0, r3
blr
#_ REGISTER_OUT r0 0
#_ REGISTER_OUT r3 0xFFFFFFFF
#_ REGISTER_OUT cr 0x0000000020000000
|
xenia-project/xenia | 4,054 | src/xenia/cpu/ppc/testing/instr_sraw.s | test_sraw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_1_constant:
li r4, 1
li r5, 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_2_constant:
li r4, -1
li r5, 0
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_sraw_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_sraw_3_constant:
li r4, -1
li r5, 1
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_sraw_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_sraw_4_constant:
li r4, -1
li r5, 63
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
#_ REGISTER_OUT r6 1
test_sraw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 0
test_sraw_5_constant:
li r4, -1
li r5, 64
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
#_ REGISTER_OUT r6 0
test_sraw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
test_sraw_6_constant:
li r4, -1
li r5, 100
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
#_ REGISTER_OUT r6 1
test_sraw_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 30
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
#_ REGISTER_OUT r6 1
test_sraw_7_constant:
li r4, -1
li r5, 30
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 30
#_ REGISTER_OUT r6 1
test_sraw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 31
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
#_ REGISTER_OUT r6 1
test_sraw_8_constant:
li r4, -1
li r5, 31
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 31
#_ REGISTER_OUT r6 1
test_sraw_9:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 32
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT r6 1
test_sraw_9_constant:
li r4, -1
li r5, 32
sraw r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 32
#_ REGISTER_OUT r6 1
|
xenia-project/xenia | 1,088 | src/xenia/cpu/ppc/testing/instr_vpermwi128.s | test_vpermwi128_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
# to 0,1,2,3
# vpermwi128 v4, v3, 0x1B
.long 0x189B1A10
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vpermwi128_2:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
# to 3,2,1,0
# vpermwi128 v4, v3, 0xE4
.long 0x18841BD0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [0C0D0E0F, 08090A0B, 04050607, 00010203]
test_vpermwi128_3:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
# to 0,0,0,0
# vpermwi128 v4, v3, 0
.long 0x18801A10
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [00010203, 00010203, 00010203, 00010203]
test_vpermwi128_4:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
# to 3,3,3,3
# vpermwi128 v4, v3, 0xFF
.long 0x189F1BD0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [0C0D0E0F, 0C0D0E0F, 0C0D0E0F, 0C0D0E0F]
|
xenia-project/xenia | 2,399 | src/xenia/cpu/ppc/testing/instr_extsb.s | test_extsb_1:
#_ REGISTER_IN r4 0x0F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsb_1_constant:
li r4, 0x0F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsb_2:
#_ REGISTER_IN r4 0x7F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x7F
#_ REGISTER_OUT r4 0x7F
test_extsb_2_constant:
li r4, 0x7F
extsb r3, r4
blr
#_ REGISTER_OUT r3 0x7F
#_ REGISTER_OUT r4 0x7F
test_extsb_3:
#_ REGISTER_IN r4 0x80
extsb r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0x80
test_extsb_3_constant:
li r4, 0x80
extsb r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0x80
test_extsb_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFF080
extsb r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
test_extsb_4_constant:
li r4, 0xF7F
not r4, r4
extsb r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
test_extsb_cr_1:
#_ REGISTER_IN r4 0x0F
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
#_ REGISTER_OUT r12 0x40000000
test_extsb_cr_1_constant:
li r4, 0x0F
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
#_ REGISTER_OUT r12 0x40000000
test_extsb_cr_2:
#_ REGISTER_IN r4 0x7F
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x7F
#_ REGISTER_OUT r4 0x7F
#_ REGISTER_OUT r12 0x40000000
test_extsb_cr_2_constant:
li r4, 0x7F
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x7F
#_ REGISTER_OUT r4 0x7F
#_ REGISTER_OUT r12 0x40000000
test_extsb_cr_3:
#_ REGISTER_IN r4 0x80
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0x80
#_ REGISTER_OUT r12 0x80000000
test_extsb_cr_3_constant:
li r4, 0x80
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0x80
#_ REGISTER_OUT r12 0x80000000
test_extsb_cr_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFF080
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
#_ REGISTER_OUT r12 0x80000000
test_extsb_cr_4_constant:
li r4, 0xF7F
not r4, r4
extsb. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFF080
#_ REGISTER_OUT r12 0x80000000
|
xenia-project/xenia | 5,509 | src/xenia/cpu/ppc/testing/instr_addc.s | test_addc_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_addc_1_constant:
li r4, 1
li r5, 2
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
test_addc_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_addc_2_constant:
li r4, -1
li r5, 0
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
test_addc_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_addc_3_constant:
li r4, -1
li r5, 1
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
test_addc_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_addc_4_constant:
li r4, -1
li r5, 123
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
test_addc_5:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addc_5_constant:
li r5, -1
srdi r4, r5, 1
addc r3, r4, r5
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_addc_cr_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 2
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addc_cr_1_constant:
li r4, 1
li r5, 2
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 3
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addc_cr_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addc_cr_2_constant:
li r4, -1
li r5, 0
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addc_cr_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addc_cr_3_constant:
li r4, -1
li r5, 1
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addc_cr_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 123
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addc_cr_4_constant:
li r4, -1
li r5, 123
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x000000000000007A
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 123
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addc_cr_5:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addc_cr_5_constant:
li r5, -1
srdi r4, r5, 1
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x80000000
test_addc_cr_6:
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x8000000000000001
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
test_addc_cr_6_constant:
li r4, -1
srdi r4, r4, 1
li r5, 2
addc. r3, r4, r5
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0x8000000000000001
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 5,237 | src/xenia/cpu/ppc/testing/instr_tdi.s | test_tdlti_1:
#_ REGISTER_IN r3 24
tdlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlti_1_constant:
li r3, 24
tdlti r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlti_2:
#_ REGISTER_IN r3 24
tdlti r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdlti_2_constant:
li r3, 24
tdlti r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdlei_1:
#_ REGISTER_IN r3 24
tdlei r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlei_1_constant:
li r3, 24
tdlei r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlei_2:
#_ REGISTER_IN r3 24
tdlei r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdlei_2_constant:
li r3, 24
tdlei r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdeqi_1:
#_ REGISTER_IN r3 0
tdeqi r3, 24
blr
#_ REGISTER_OUT r3 0
test_tdeqi_1_constant:
li r3, 0
tdeqi r3, 24
blr
#_ REGISTER_OUT r3 0
test_tdeqi_2:
#_ REGISTER_IN r3 24
tdeqi r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdeqi_2_constant:
li r3, 24
tdeqi r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdgei_1:
#_ REGISTER_IN r3 24
tdgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdgei_1_constant:
li r3, 24
tdgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdgei_2:
#_ REGISTER_IN r3 0
tdgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdgei_2_constant:
li r3, 0
tdgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdgei_3:
#_ REGISTER_IN r3 -1
tdgei r3, 0
blr
#_ REGISTER_OUT r3 -1
test_tdgei_3_constant:
li r3, -1
tdgei r3, 0
blr
#_ REGISTER_OUT r3 -1
test_tdgti_1:
#_ REGISTER_IN r3 24
tdgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdgti_1_constant:
li r3, 24
tdgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdgti_2:
#_ REGISTER_IN r3 0
tdgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdgti_2_constant:
li r3, 0
tdgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdgti_3:
#_ REGISTER_IN r3 -1
tdgti r3, 0
blr
#_ REGISTER_OUT r3 -1
test_tdgti_3_constant:
li r3, -1
tdgti r3, 0
blr
#_ REGISTER_OUT r3 -1
test_tdnli_1:
#_ REGISTER_IN r3 24
tdnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdnli_1_constant:
li r3, 24
tdnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdnli_2:
#_ REGISTER_IN r3 0
tdnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdnli_2_constant:
li r3, 0
tdnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdnli_3:
#_ REGISTER_IN r3 -1
tdnli r3, 0
blr
#_ REGISTER_OUT r3 -1
test_tdnli_3_constant:
li r3, -1
tdnli r3, 0
blr
#_ REGISTER_OUT r3 -1
test_tdnei_1:
#_ REGISTER_IN r3 24
tdnei r3, 24
blr
#_ REGISTER_OUT r3 24
test_tdnei_1_constant:
li r3, 24
tdnei r3, 24
blr
#_ REGISTER_OUT r3 24
test_tdnei_2:
#_ REGISTER_IN r3 0
tdnei r3, 0
blr
#_ REGISTER_OUT r3 0
test_tdnei_2_constant:
li r3, 0
tdnei r3, 0
blr
#_ REGISTER_OUT r3 0
test_tdngi_1:
#_ REGISTER_IN r3 24
tdngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdngi_1_constant:
li r3, 24
tdngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdngi_2:
#_ REGISTER_IN r3 24
tdngi r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdngi_2_constant:
li r3, 24
tdngi r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdngi_3:
#_ REGISTER_IN r3 0
tdngi r3, -1
blr
#_ REGISTER_OUT r3 0
test_tdngi_3_constant:
li r3, 0
tdngi r3, -1
blr
#_ REGISTER_OUT r3 0
test_tdllti_1:
#_ REGISTER_IN r3 24
tdllti r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdllti_1_constant:
li r3, 24
tdllti r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdllti_2:
#_ REGISTER_IN r3 24
tdllti r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdllti_2_constant:
li r3, 24
tdllti r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdllei_1:
#_ REGISTER_IN r3 24
tdllei r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdllei_1_constant:
li r3, 24
tdllei r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdllei_2:
#_ REGISTER_IN r3 24
tdllei r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdllei_2_constant:
li r3, 24
tdllei r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdlgei_1:
#_ REGISTER_IN r3 24
tdlgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdlgei_1_constant:
li r3, 24
tdlgei r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdlgei_2:
#_ REGISTER_IN r3 0
tdlgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdlgei_2_constant:
li r3, 0
tdlgei r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdlgti_1:
#_ REGISTER_IN r3 24
tdlgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdlgti_1_constant:
li r3, 24
tdlgti r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdlgti_2:
#_ REGISTER_IN r3 0
tdlgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdlgti_2_constant:
li r3, 0
tdlgti r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdlnli_1:
#_ REGISTER_IN r3 24
tdlnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdlnli_1_constant:
li r3, 24
tdlnli r3, 48
blr
#_ REGISTER_OUT r3 24
test_tdlnli_2:
#_ REGISTER_IN r3 0
tdlnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdlnli_2_constant:
li r3, 0
tdlnli r3, 48
blr
#_ REGISTER_OUT r3 0
test_tdlngi_1:
#_ REGISTER_IN r3 24
tdlngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlngi_1_constant:
li r3, 24
tdlngi r3, 16
blr
#_ REGISTER_OUT r3 24
test_tdlngi_2:
#_ REGISTER_IN r3 24
tdlngi r3, 0
blr
#_ REGISTER_OUT r3 24
test_tdlngi_2_constant:
li r3, 24
tdlngi r3, 0
blr
#_ REGISTER_OUT r3 24
|
xenia-project/xenia | 1,817 | src/xenia/cpu/ppc/testing/instr_sradi.s | test_sradi_1:
#_ REGISTER_IN r4 1
sradi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_sradi_1_constant:
li r4, 1
sradi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
test_sradi_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
sradi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
test_sradi_2_constant:
li r4, -1
sradi r3, r4, 0
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
test_sradi_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
sradi r3, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_sradi_3_constant:
li r4, -1
sradi r3, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_sradi_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
sradi r3, r4, 62
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_sradi_4_constant:
li r4, -1
sradi r3, r4, 62
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_sradi_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
sradi r3, r4, 63
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
test_sradi_5_constant:
li r4, -1
sradi r3, r4, 63
adde r6, r0, r0
blr
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
|
xenia-project/xenia | 3,952 | src/xenia/cpu/ppc/testing/instr_mullw.s | test_mullw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_1_constant:
li r4, 1
li r5, 0
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mullw_2_constant:
li r4, 1
li r5, 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mullw_3:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_3_constant:
li r4, 1
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_4:
#_ REGISTER_IN r4 123
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mullw_4_constant:
li r4, 123
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mullw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mullw_5_constant:
li r4, -1
li r5, 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mullw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mullw_6_constant:
li r4, -1
li r5, 2
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mullw_7:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_7_constant:
li r4, 1
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mullw_8_constant:
li r4, -1
li r5, -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mullw_9:
#_ REGISTER_IN r4 0xFFFFFFFF00000000
#_ REGISTER_IN r5 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFF00000000
#_ REGISTER_OUT r5 1
test_mullw_9_constant:
li r4, -1
sldi r4, r4, 32
li r5, 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFF00000000
#_ REGISTER_OUT r5 1
test_mullw_10:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0xFFFFFFFF00000000
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
test_mullw_10_constant:
li r4, 1
li r5, -1
sldi r5, r5, 32
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
test_mullw_11:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0x000000007FFFFFFF
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_mullw_11_constant:
li r4, 1
li r5, -1
clrldi r5, r5, 33
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF
test_mullw_12:
#_ REGISTER_IN r0 0x1
#_ REGISTER_IN r8 0x0123456789ABCDEF
mullw r0, r8, r8
blr
#_ REGISTER_OUT r0 0x36B1B9D890F2A521
#_ REGISTER_OUT r8 0x0123456789ABCDEF
blr
|
xenia-project/xenia | 1,237 | src/xenia/cpu/ppc/testing/instr_vpkshss128.s | test_vpkshss128_1:
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vpkshss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vpkshss128_2:
#_ REGISTER_IN v3 [7FFF8000, 00020003, 00040005, 00060007]
#_ REGISTER_IN v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
vpkshss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [7FFF8000, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [7FFF8000, 000A000B, 000C000D, 000E000F]
#_ REGISTER_OUT v5 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vpkshss128_3:
# {-1, -128, 0, 127, -2, -129, 1, 128}
#_ REGISTER_IN v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
# {-3, -130, 2, 129, -4, -131, 3, 130}
#_ REGISTER_IN v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vpkshss128 v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v4 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
# {-1, -128, 0, 127, -2, -128, 1, 127,
# -3, -128, 2, 127, -4, -128, 3, 127}
#_ REGISTER_OUT v5 [FF80007F, FE80017F, FD80027F, FC80037F]
|
xenia-project/xenia | 8,426 | src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s | /**
******************************************************************************
* Xenia : Xbox 360 Emulator Research Project *
******************************************************************************
* Copyright 2017 Ben Vanik. All rights reserved. *
* Released under the BSD license - see LICENSE in the root for more details. *
******************************************************************************
*/
# r3 = context
# this does not touch r1, r3, r4, r13
.load_registers_ctx:
lwz r2, 0x400(r3) # CR
mtcrf 0xFF, r2
lfd f0, 0x404(r3) # FPSCR
mtfsf 0xFF, f0
li r2, 0
mtxer r2
# Altivec registers (up to 32)
li r2, 0x200
lvx v0, r3, r2
addi r2, r2, 16
lvx v1, r3, r2
addi r2, r2, 16
lvx v2, r3, r2
addi r2, r2, 16
lvx v3, r3, r2
addi r2, r2, 16
lvx v4, r3, r2
addi r2, r2, 16
lvx v5, r3, r2
addi r2, r2, 16
lvx v6, r3, r2
addi r2, r2, 16
lvx v7, r3, r2
addi r2, r2, 16
lvx v8, r3, r2
addi r2, r2, 16
lvx v9, r3, r2
addi r2, r2, 16
lvx v10, r3, r2
addi r2, r2, 16
lvx v11, r3, r2
addi r2, r2, 16
lvx v12, r3, r2
addi r2, r2, 16
lvx v13, r3, r2
addi r2, r2, 16
lvx v14, r3, r2
addi r2, r2, 16
lvx v15, r3, r2
addi r2, r2, 16
lvx v16, r3, r2
addi r2, r2, 16
lvx v17, r3, r2
addi r2, r2, 16
lvx v18, r3, r2
addi r2, r2, 16
lvx v19, r3, r2
addi r2, r2, 16
lvx v20, r3, r2
addi r2, r2, 16
lvx v21, r3, r2
addi r2, r2, 16
lvx v22, r3, r2
addi r2, r2, 16
lvx v23, r3, r2
addi r2, r2, 16
lvx v24, r3, r2
addi r2, r2, 16
lvx v25, r3, r2
addi r2, r2, 16
lvx v26, r3, r2
addi r2, r2, 16
lvx v27, r3, r2
addi r2, r2, 16
lvx v28, r3, r2
addi r2, r2, 16
lvx v29, r3, r2
addi r2, r2, 16
lvx v30, r3, r2
addi r2, r2, 16
lvx v31, r3, r2
ld r0, 0x00(r3)
# r1 cannot be used
ld r2, 0x10(r3)
# r3 will be loaded before the call
# r4 will be loaded before the call
ld r5, 0x28(r3)
ld r6, 0x30(r3)
ld r7, 0x38(r3)
ld r8, 0x40(r3)
ld r9, 0x48(r3)
ld r10, 0x50(r3)
ld r11, 0x58(r3)
ld r12, 0x60(r3)
# r13 cannot be used (OS use only)
ld r14, 0x70(r3)
ld r15, 0x78(r3)
ld r16, 0x80(r3)
ld r17, 0x88(r3)
ld r18, 0x90(r3)
ld r19, 0x98(r3)
ld r20, 0xA0(r3)
ld r21, 0xA8(r3)
ld r22, 0xB0(r3)
ld r23, 0xB8(r3)
ld r24, 0xC0(r3)
ld r25, 0xC8(r3)
ld r26, 0xD0(r3)
ld r27, 0xD8(r3)
ld r28, 0xE0(r3)
ld r29, 0xE8(r3)
ld r30, 0xF0(r3)
ld r31, 0xF8(r3)
lfd f0, 0x100(r3)
lfd f1, 0x108(r3)
lfd f2, 0x110(r3)
lfd f3, 0x118(r3)
lfd f4, 0x120(r3)
lfd f5, 0x128(r3)
lfd f6, 0x130(r3)
lfd f7, 0x138(r3)
lfd f8, 0x140(r3)
lfd f9, 0x148(r3)
lfd f10, 0x150(r3)
lfd f11, 0x158(r3)
lfd f12, 0x160(r3)
lfd f13, 0x168(r3)
lfd f14, 0x170(r3)
lfd f15, 0x178(r3)
lfd f16, 0x180(r3)
lfd f17, 0x188(r3)
lfd f18, 0x190(r3)
lfd f19, 0x198(r3)
lfd f20, 0x1A0(r3)
lfd f21, 0x1A8(r3)
lfd f22, 0x1B0(r3)
lfd f23, 0x1B8(r3)
lfd f24, 0x1C0(r3)
lfd f25, 0x1C8(r3)
lfd f26, 0x1D0(r3)
lfd f27, 0x1D8(r3)
lfd f28, 0x1E0(r3)
lfd f29, 0x1E8(r3)
lfd f30, 0x1F0(r3)
lfd f31, 0x1F8(r3)
blr
# r3 = context
# this does not save r1, r3, r13
.save_registers_ctx:
std r0, 0x00(r3)
# r1 cannot be used
std r2, 0x10(r3)
# r3 will be saved later
std r4, 0x20(r3)
std r5, 0x28(r3)
std r6, 0x30(r3)
std r7, 0x38(r3)
std r8, 0x40(r3)
std r9, 0x48(r3)
std r10, 0x50(r3)
std r11, 0x58(r3)
std r12, 0x60(r3)
# r13 cannot be used (OS use only)
std r14, 0x70(r3)
std r15, 0x78(r3)
std r16, 0x80(r3)
std r17, 0x88(r3)
std r18, 0x90(r3)
std r19, 0x98(r3)
std r20, 0xA0(r3)
std r21, 0xA8(r3)
std r22, 0xB0(r3)
std r23, 0xB8(r3)
std r24, 0xC0(r3)
std r25, 0xC8(r3)
std r26, 0xD0(r3)
std r27, 0xD8(r3)
std r28, 0xE0(r3)
std r29, 0xE8(r3)
std r30, 0xF0(r3)
std r31, 0xF8(r3)
stfd f0, 0x100(r3)
stfd f1, 0x108(r3)
stfd f2, 0x110(r3)
stfd f3, 0x118(r3)
stfd f4, 0x120(r3)
stfd f5, 0x128(r3)
stfd f6, 0x130(r3)
stfd f7, 0x138(r3)
stfd f8, 0x140(r3)
stfd f9, 0x148(r3)
stfd f10, 0x150(r3)
stfd f11, 0x158(r3)
stfd f12, 0x160(r3)
stfd f13, 0x168(r3)
stfd f14, 0x170(r3)
stfd f15, 0x178(r3)
stfd f16, 0x180(r3)
stfd f17, 0x188(r3)
stfd f18, 0x190(r3)
stfd f19, 0x198(r3)
stfd f20, 0x1A0(r3)
stfd f21, 0x1A8(r3)
stfd f22, 0x1B0(r3)
stfd f23, 0x1B8(r3)
stfd f24, 0x1C0(r3)
stfd f25, 0x1C8(r3)
stfd f26, 0x1D0(r3)
stfd f27, 0x1D8(r3)
stfd f28, 0x1E0(r3)
stfd f29, 0x1E8(r3)
stfd f30, 0x1F0(r3)
stfd f31, 0x1F8(r3)
# Altivec registers (up to 32)
li r2, 0x200
stvx v0, r3, r2
addi r2, r2, 16
stvx v1, r3, r2
addi r2, r2, 16
stvx v2, r3, r2
addi r2, r2, 16
stvx v3, r3, r2
addi r2, r2, 16
stvx v4, r3, r2
addi r2, r2, 16
stvx v5, r3, r2
addi r2, r2, 16
stvx v6, r3, r2
addi r2, r2, 16
stvx v7, r3, r2
addi r2, r2, 16
stvx v8, r3, r2
addi r2, r2, 16
stvx v9, r3, r2
addi r2, r2, 16
stvx v10, r3, r2
addi r2, r2, 16
stvx v11, r3, r2
addi r2, r2, 16
stvx v12, r3, r2
addi r2, r2, 16
stvx v13, r3, r2
addi r2, r2, 16
stvx v14, r3, r2
addi r2, r2, 16
stvx v15, r3, r2
addi r2, r2, 16
stvx v16, r3, r2
addi r2, r2, 16
stvx v17, r3, r2
addi r2, r2, 16
stvx v18, r3, r2
addi r2, r2, 16
stvx v19, r3, r2
addi r2, r2, 16
stvx v20, r3, r2
addi r2, r2, 16
stvx v21, r3, r2
addi r2, r2, 16
stvx v22, r3, r2
addi r2, r2, 16
stvx v23, r3, r2
addi r2, r2, 16
stvx v24, r3, r2
addi r2, r2, 16
stvx v25, r3, r2
addi r2, r2, 16
stvx v26, r3, r2
addi r2, r2, 16
stvx v27, r3, r2
addi r2, r2, 16
stvx v28, r3, r2
addi r2, r2, 16
stvx v29, r3, r2
addi r2, r2, 16
stvx v30, r3, r2
addi r2, r2, 16
stvx v31, r3, r2
mfcr r2 # CR
stw r2, 0x400(r3)
mffs f0 # FPSCR
stfd f0, 0x404(r3)
blr
# void xe_call_native(Context* ctx, void* func)
.globl xe_call_native
xe_call_native:
mflr r12
stw r12, -0x8(r1)
stwu r1, -0x380(r1) # 0x200(gpr + fp) + 0x200(vr)
# Save nonvolatile registers on the stack.
std r2, 0x110(r1)
std r3, 0x118(r1) # Store the context, this will be needed later.
std r14, 0x170(r1)
std r15, 0x178(r1)
std r16, 0x180(r1)
std r17, 0x188(r1)
std r18, 0x190(r1)
std r19, 0x198(r1)
std r20, 0x1A0(r1)
std r21, 0x1A8(r1)
std r22, 0x1B0(r1)
std r23, 0x1B8(r1)
std r24, 0x1C0(r1)
std r25, 0x1C8(r1)
std r26, 0x1D0(r1)
std r27, 0x1D8(r1)
std r28, 0x1E0(r1)
std r29, 0x1E8(r1)
std r30, 0x1F0(r1)
std r31, 0x1F8(r1)
stfd f14, 0x270(r1)
stfd f15, 0x278(r1)
stfd f16, 0x280(r1)
stfd f17, 0x288(r1)
stfd f18, 0x290(r1)
stfd f19, 0x298(r1)
stfd f20, 0x2A0(r1)
stfd f21, 0x2A8(r1)
stfd f22, 0x2B0(r1)
stfd f23, 0x2B8(r1)
stfd f24, 0x2C0(r1)
stfd f25, 0x2C8(r1)
stfd f26, 0x2D0(r1)
stfd f27, 0x2D8(r1)
stfd f28, 0x2E0(r1)
stfd f29, 0x2E8(r1)
stfd f30, 0x2F0(r1)
stfd f31, 0x2F8(r1)
# Load registers from context (except r3/r4)
bl .load_registers_ctx
# Call the test routine
mtctr r4
ld r4, 0x20(r3)
ld r3, 0x18(r3)
bctrl
# Temporarily store r3 into the stack (in the place of r0)
std r3, 0x100(r1)
# Store registers into context (except r3)
ld r3, 0x118(r1)
bl .save_registers_ctx
# Now store r3
ld r4, 0x100(r1)
std r4, 0x18(r3)
# Restore nonvolatile registers from the stack
ld r2, 0x110(r1)
ld r14, 0x170(r1)
ld r15, 0x178(r1)
ld r16, 0x180(r1)
ld r17, 0x188(r1)
ld r18, 0x190(r1)
ld r19, 0x198(r1)
ld r20, 0x1A0(r1)
ld r21, 0x1A8(r1)
ld r22, 0x1B0(r1)
ld r23, 0x1B8(r1)
ld r24, 0x1C0(r1)
ld r25, 0x1C8(r1)
ld r26, 0x1D0(r1)
ld r27, 0x1D8(r1)
ld r28, 0x1E0(r1)
ld r29, 0x1E8(r1)
ld r30, 0x1F0(r1)
ld r31, 0x1F8(r1)
lfd f14, 0x270(r1)
lfd f15, 0x278(r1)
lfd f16, 0x280(r1)
lfd f17, 0x288(r1)
lfd f18, 0x290(r1)
lfd f19, 0x298(r1)
lfd f20, 0x2A0(r1)
lfd f21, 0x2A8(r1)
lfd f22, 0x2B0(r1)
lfd f23, 0x2B8(r1)
lfd f24, 0x2C0(r1)
lfd f25, 0x2C8(r1)
lfd f26, 0x2D0(r1)
lfd f27, 0x2D8(r1)
lfd f28, 0x2E0(r1)
lfd f29, 0x2E8(r1)
lfd f30, 0x2F0(r1)
lfd f31, 0x2F8(r1)
addi r1, r1, 0x380
lwz r12, -0x8(r1)
mtlr r12
blr
|
xenia-project/xenia | 1,978 | src/xenia/cpu/ppc/testing/instr_cmpi.s | test_cmpdi_1:
#_ REGISTER_IN r3 0x0000000100000000
cmpdi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_cmpdi_1_constant:
li r3, 1
sldi r3, r3, 32
cmpdi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x40000000
test_cmpdi_2:
#_ REGISTER_IN r3 1
cmpdi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x80000000
test_cmpdi_2_constant:
li r3, 1
cmpdi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x80000000
test_cmpwi_1:
#_ REGISTER_IN r3 0x0000000100000000
cmpwi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x80000000
test_cmpwi_1_constant:
li r3, 1
sldi r3, r3, 32
cmpwi r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000000
#_ REGISTER_OUT r12 0x80000000
test_cmpwi_2:
#_ REGISTER_IN r3 2
cmpwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x40000000
test_cmpwi_2_constant:
li r3, 2
cmpwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x40000000
test_cmpwi_5:
#_ REGISTER_IN r3 0x0000000100000002
cmpwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000002
#_ REGISTER_OUT r12 0x40000000
test_cmpwi_5_constant:
li r3, 1
sldi r3, r3, 32
sldi r4, r3, 1
addi r3, r3, 2
cmpwi r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 0x0000000100000002
#_ REGISTER_OUT r12 0x40000000
test_cmpi_1:
#_ REGISTER_IN r3 1
cmpi 5, 0, r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x00000800
test_cmpi_1_constant:
li r3, 1
cmpi 5, 0, r3, 2
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r12 0x00000800
test_cmpi_2:
#_ REGISTER_IN r3 2
cmpi 3, 0, r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x00040000
test_cmpi_2_constant:
li r3, 2
cmpi 3, 0, r3, 1
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r12 0x00040000
|
xenia-project/xenia | 3,627 | src/xenia/cpu/ppc/testing/instr_subfme.s | test_subfme_one_ca_1:
#_ REGISTER_IN r10 0x00000000000103BF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc40
#_ REGISTER_OUT r4 1
test_subfme_one_ca_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc40
#_ REGISTER_OUT r4 1
test_subfme_one_ca_2:
#_ REGISTER_IN r10 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_subfme_one_ca_2_constant:
li r10, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_subfme_one_ca_3:
#_ REGISTER_IN r10 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 1
test_subfme_one_ca_3_constant:
li r10, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 1
test_subfme_one_ca_4:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfme_one_ca_4_constant:
li r10, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_1:
#_ REGISTER_IN r10 0x00000000000103BF
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc3f
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefc3f
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_2:
#_ REGISTER_IN r10 0
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_2_constant:
li r10, 0
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0xfffffffffffffffe
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_3:
#_ REGISTER_IN r10 1
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 0xfffffffffffffffd
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_3_constant:
li r10, 1
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 0xfffffffffffffffd
#_ REGISTER_OUT r4 1
test_subfme_zero_ca_4:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0
test_subfme_zero_ca_4_constant:
li r10, -1
xor r3, r3, r3
addic r3, r3, 1
subfme r3, r10
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0xffffffffffffffff
#_ REGISTER_OUT r4 0
|
xenia-project/xenia | 2,426 | src/xenia/cpu/ppc/testing/instr_vupkd3d128.s | # vupkd3d128 dest, src, type
# type:
# 0 = PACK_TYPE_D3DCOLOR
# 1 = PACK_TYPE_SHORT_2
# 3 = PACK_TYPE_FLOAT16_2
# 5 = PACK_TYPE_FLOAT16_4
# vupkd3d128 is broken in binutils, so these are hand coded
test_vupkd3d128_d3dcolor:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
# vupkd3d128 v3, v3, 0
.long 0x18601FF0
blr
#_ REGISTER_OUT v3 [3f800001, 3f800002, 3f800003, 3f800004]
test_vupkd3d128_short2_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40407fff, 403f8001, 00000000, 3f800000]
test_vupkd3d128_short2_1:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40404000, 403FC000, 00000000, 3f800000]
test_vupkd3d128_short2_2:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40407FFF, 403FF333, 00000000, 3f800000]
test_vupkd3d128_short2_3:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00008000]
# vupkd3d128 v3, v3, 1
.long 0x18641FF0
blr
#_ REGISTER_OUT v3 [40400000, 7FC00000, 00000000, 3f800000]
test_vupkd3d128_short4_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, 7FFFFFFF, 007FFFF8]
# vupkd3d128 v3, v3, 4
.long 0x18701FF0
blr
#_ REGISTER_OUT v3 [40407FFF, 403FFFFF, 4040007F, 403FFFF8]
test_vupkd3d128_float16_2_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]
# vupkd3d128 v3, v3, 3
.long 0x186C1FF0
blr
#_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 3f800000]
test_vupkd3d128_float16_4_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, 3800B801, 3802B803]
# vupkd3d128 v3, v3, 5
.long 0x18741FF0
blr
#_ REGISTER_OUT v3 [3F000000, bf002000, 3f004000, bf006000]
test_vupkd3d128_uint_2101010_0:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 400001FF]
# vupkd3d128 v3, v3, 2
.long 0x18681FF0
blr
#_ REGISTER_OUT v3 [404001FF, 40400000, 40400000, 3F800001]
test_vupkd3d128_uint_2101010_1:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 40000201]
# vupkd3d128 v3, v3, 2
.long 0x18681FF0
blr
#_ REGISTER_OUT v3 [403FFE01, 40400000, 40400000, 3F800001]
test_vupkd3d128_uint_2101010_2:
#_ REGISTER_IN v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 40000200]
# vupkd3d128 v3, v3, 2
.long 0x18681FF0
blr
#_ REGISTER_OUT v3 [7FC00000, 40400000, 40400000, 3F800001]
|
xenia-project/xenia | 1,447 | src/xenia/cpu/ppc/testing/instr_vmaddfp.s | test_vmaddfp_1:
#_ REGISTER_IN v4 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
# 1.0, 1.5, 1.1, 1.9
vmaddfp v3, v4, v4, v4
blr
#_ REGISTER_OUT v3 [40000000, 40700000, 4013d70a, 40b051eb]
#_ REGISTER_OUT v4 [3f800000, 3fc00000, 3f8ccccd, 3ff33333]
# 2.0, 3.75, 2.31, 5.51
# 40b051eb is actually 5.50999975, not 5.51?
# 40b051ec is 5.51
test_vmaddfp_2:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v6 [3f800000, 3f800000, 3f800000, 3f800000]
# 1.0, 1.5, 1.1, 1.9
vmaddfp v3, v4, v5, v6
blr
#_ REGISTER_OUT v3 [40000000, 40000000, 40000000, 40000000]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v6 [3f800000, 3f800000, 3f800000, 3f800000]
test_vmaddfp_3:
# v4 = 5, 5, 1, 1
# v5 = 5, 5, 1, 1
# v6 = 1, 1, 1, 1
#_ REGISTER_IN v4 [40a00000, 40a00000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [40a00000, 40a00000, 3f800000, 3f800000]
#_ REGISTER_IN v6 [3f800000, 3f800000, 3f800000, 3f800000]
# 1.0, 1.5, 1.1, 1.9
vmaddfp v3, v4, v5, v6
blr
# v3 = 26.0, 26.0, 2.0, 2.0
#_ REGISTER_OUT v3 [41d00000, 41d00000, 40000000, 40000000]
#_ REGISTER_OUT v4 [40a00000, 40a00000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [40a00000, 40a00000, 3f800000, 3f800000]
#_ REGISTER_OUT v6 [3f800000, 3f800000, 3f800000, 3f800000]
|
xenia-project/xenia | 2,242 | src/xenia/cpu/ppc/testing/instr_stvr.s | test_stvr_1:
#_ MEMORY_IN 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_IN 10001050 00000000 00000000 00000000 00000000
#_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN r5 0x10
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_OUT 10001050 00000000 00000000 00000000 00000000
test_stvr_1_constant:
#_ MEMORY_IN 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_IN 10001050 00000000 00000000 00000000 00000000
lis r4, 0x1000
ori r4, r4, 0x1040
li r5, 0x10
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_OUT 10001050 00000000 00000000 00000000 00000000
test_stvr_2:
#_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
#_ REGISTER_IN r4 0x10001044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvrx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 10001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F
test_stvr_2_constant:
#_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
lis r4, 0x1000
ori r4, r4, 0x1044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvrx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 10001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F
test_stvr_3:
#_ REGISTER_IN r4 0x10010000
#_ REGISTER_IN r5 0x0
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvrx v3, r4, r5
blr
#_ REGISTER_OUT r4 0x10010000
#_ REGISTER_OUT r5 0x0
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
test_stvr_3_constant:
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
lis r4, 0x1001
stvrx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10010000
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
|
xenia-project/xenia | 1,536 | src/xenia/cpu/ppc/testing/instr_addic.s | test_addic_1:
#_ REGISTER_IN r4 1
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r6 0
test_addic_1_constant:
li r4, 1
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r6 0
test_addic_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
test_addic_2_constant:
li r4, -1
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
test_addic_3:
#_ REGISTER_IN r4 0xFFFFFFFF
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 0x0000000100000000
#_ REGISTER_OUT r6 1
test_addic_3_constant:
li r4, 0xFFFFFFFF
srwi r4, r4, 0
addic r4, r4, 1
adde r6, r0, r0
blr
#_ REGISTER_OUT r4 0x0000000100000000
#_ REGISTER_OUT r6 1
test_addic_cr_1:
#_ REGISTER_IN r4 1
addic. r4, r4, 1
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addic_cr_1_constant:
li r4, 1
addic. r4, r4, 1
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r4 2
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addic_cr_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addic. r4, r4, 1
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addic_cr_2_constant:
li r4, -1
addic. r4, r4, 1
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
|
xenia-project/xenia | 2,615 | src/xenia/cpu/ppc/testing/instr_extsw.s | test_extsw_1:
#_ REGISTER_IN r4 0x0F
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsw_1_constant:
li r4, 0x0F
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
test_extsw_2:
#_ REGISTER_IN r4 0x7FFFFFFF
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x7FFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFF
test_extsw_2_constant:
lis r4, 0x7FFF
ori r4, r4, 0xFFFF
extsw r3, r4
blr
#_ REGISTER_OUT r3 0x7FFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFF
test_extsw_3:
#_ REGISTER_IN r4 0x80000000
extsw r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0x80000000
test_extsw_3_constant:
li r4, 0x80
sldi r4, r4, 24
extsw r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0x80000000
test_extsw_4:
#_ REGISTER_IN r4 0xFFFFFFF080000000
extsw r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0xFFFFFFF080000000
test_extsw_4_constant:
li r4, 0xF7F
not r4, r4
sldi r4, r4, 24
extsw r3, r4
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0xFFFFFFF080000000
test_extsw_cr_1:
#_ REGISTER_IN r4 0x0F
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
#_ REGISTER_OUT r12 0x40000000
test_extsw_cr_1_constant:
li r4, 0x0F
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x0F
#_ REGISTER_OUT r4 0x0F
#_ REGISTER_OUT r12 0x40000000
test_extsw_cr_2:
#_ REGISTER_IN r4 0x7FFFFFFF
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFF
#_ REGISTER_OUT r12 0x40000000
test_extsw_cr_2_constant:
lis r4, 0x7FFF
ori r4, r4, 0xFFFF
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0x7FFFFFFF
#_ REGISTER_OUT r4 0x7FFFFFFF
#_ REGISTER_OUT r12 0x40000000
test_extsw_cr_3:
#_ REGISTER_IN r4 0x80000000
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0x80000000
#_ REGISTER_OUT r12 0x80000000
test_extsw_cr_3_constant:
li r4, 0x80
sldi r4, r4, 24
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0x80000000
#_ REGISTER_OUT r12 0x80000000
test_extsw_cr_4:
#_ REGISTER_IN r4 0xFFFFFFF080000000
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0xFFFFFFF080000000
#_ REGISTER_OUT r12 0x80000000
test_extsw_cr_4_constant:
li r4, 0xF7F
not r4, r4
sldi r4, r4, 24
extsw. r3, r4
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFF80000000
#_ REGISTER_OUT r4 0xFFFFFFF080000000
#_ REGISTER_OUT r12 0x80000000
|
xenia-project/xenia | 1,243 | src/xenia/cpu/ppc/testing/instr_vsldoi.s | test_vsldoi_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsldoi v5, v3, v4, 0
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsldoi_2:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsldoi v5, v3, v4, 1
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [01020304, 05060708, 090A0B0C, 0D0E0F10]
test_vsldoi_3:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsldoi v5, v3, v4, 0xF
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [0F101112, 13141516, 1718191A, 1B1C1D1E]
|
xenia-project/xenia | 1,482 | src/xenia/cpu/ppc/testing/instr_vpkuhum.s | test_vpkuhum_1:
# {0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
# {8, 9, 10, 11, 12, 13, 14, 15}
#_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
vpkuhum v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
# {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
blr
test_vpkuhum_2:
# {-8, -7, -6, -5, -4, -3, -2, -1}
#_ REGISTER_IN v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
# {0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_IN v4 [00000001, 00020003, 00040005, 00060007]
vpkuhum v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFF8FFF9, FFFAFFFB, FFFCFFFD, FFFEFFFF]
#_ REGISTER_OUT v4 [00000001, 00020003, 00040005, 00060007]
# {-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}
#_ REGISTER_OUT v5 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
blr
test_vpkuhum_3:
# {0, 65535, 65535, 0, 0, 0, 65535, 0}
#_ REGISTER_IN v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
# {65535, 0, 0, 65535, 65535, 65535, 0, 65535}
#_ REGISTER_IN v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
vpkuhum v5, v3, v4
blr
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v4 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
# {0, 255, 255, 0, 0, 0, 255, 0, 255, 0, 0, 255, 255, 255, 0, 255}
#_ REGISTER_OUT v5 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
blr
|
xenia-project/xenia | 1,854 | src/xenia/cpu/ppc/testing/instr_andi.s | test_andi_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andi. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0x0000CAFE
#_ REGISTER_OUT r12 0x40000000
test_andi_cr_1_constant:
li r5, -1
andi. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0x0000CAFE
#_ REGISTER_OUT r12 0x40000000
test_andi_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andi. r11, r5, 0
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andi_cr_2_constant:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andi. r11, r5, 0
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andi_cr_3:
#_ REGISTER_IN r5 0
andi. r11, r5, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andi_cr_3_constant:
li r5, 0
andi. r11, r5, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_andi_cr_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
andi. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0x0000CAFE
#_ REGISTER_OUT r12 0x40000000
test_andi_cr_4_constant:
li r5, -1
andi. r11, r5, 0xCAFE
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0x0000CAFE
#_ REGISTER_OUT r12 0x40000000
test_andi_cr_5:
#_ REGISTER_IN r0 0x100000FF
andi. r11, r0, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r11 0x000000FF
#_ REGISTER_OUT r12 0x40000000
test_andi_cr_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
andi. r11, r0, 0xFFFF
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r11 0x000000FF
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 4,259 | src/xenia/cpu/ppc/testing/instr_fctixz.s | # Credits: These tests stolen from https://github.com/dolphin-emu/hwtests
# +0
test_fctiwz_1:
#_ REGISTER_IN f0 0x0000000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x0000000000000000
#_ REGISTER_OUT f1 0x0000000000000000
# -0
test_fctiwz_2:
#_ REGISTER_IN f0 0x8000000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x8000000000000000
#_ REGISTER_OUT f1 0x0000000000000000
# smallest positive subnormal
test_fctiwz_3:
#_ REGISTER_IN f0 0x0000000000000001
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x0000000000000001
#_ REGISTER_OUT f1 0x0000000000000000
# largest subnormal
test_fctiwz_4:
#_ REGISTER_IN f0 0x000fffffffffffff
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x000fffffffffffff
#_ REGISTER_OUT f1 0x0000000000000000
# +1
test_fctiwz_5:
#_ REGISTER_IN f0 0x3ff0000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x3ff0000000000000
#_ REGISTER_OUT f1 0x0000000000000001
# -1
test_fctiwz_6:
#_ REGISTER_IN f0 0xbff0000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0xbff0000000000000
#_ REGISTER_OUT f1 0xffffffffffffffff
# -(2^31)
test_fctiwz_7:
#_ REGISTER_IN f0 0xc1e0000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0xc1e0000000000000
#_ REGISTER_OUT f1 0xFFFFFFFF80000000
# 2^31 - 1
test_fctiwz_8:
#_ REGISTER_IN f0 0x41dfffffffc00000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x41dfffffffc00000
#_ REGISTER_OUT f1 0x000000007fffffff
# +infinity
test_fctiwz_9:
#_ REGISTER_IN f0 0x7ff0000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0x7ff0000000000000
#_ REGISTER_OUT f1 0x000000007fffffff
# -infinity
test_fctiwz_10:
#_ REGISTER_IN f0 0xfff0000000000000
fctiwz f1, f0
blr
#_ REGISTER_OUT f0 0xfff0000000000000
#_ REGISTER_OUT f1 0xFFFFFFFF80000000
# TODO(DrChat): Xenia doesn't handle NaNs yet.
# # QNaN
# test_fctiwz_11:
# #_ REGISTER_IN f0 0xfff8000000000000
# fctiwz f1, f0
# blr
# #_ REGISTER_OUT f0 0xfff8000000000000
# #_ REGISTER_OUT f1 0xFFFFFFFF80000000
#
# # SNaN
# test_fctiwz_12:
# #_ REGISTER_IN f0 0xfff4000000000000
# fctiwz f1, f0
# blr
# #_ REGISTER_OUT f0 0xfff4000000000000
# #_ REGISTER_OUT f1 0xFFFFFFFF80000000
# +0
test_fctidz_1:
#_ REGISTER_IN f0 0x0000000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x0000000000000000
#_ REGISTER_OUT f1 0x0000000000000000
# -0
test_fctidz_2:
#_ REGISTER_IN f0 0x8000000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x8000000000000000
#_ REGISTER_OUT f1 0x0000000000000000
# smallest positive subnormal
test_fctidz_3:
#_ REGISTER_IN f0 0x0000000000000001
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x0000000000000001
#_ REGISTER_OUT f1 0x0000000000000000
# largest subnormal
test_fctidz_4:
#_ REGISTER_IN f0 0x000fffffffffffff
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x000fffffffffffff
#_ REGISTER_OUT f1 0x0000000000000000
# +1
test_fctidz_5:
#_ REGISTER_IN f0 0x3ff0000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x3ff0000000000000
#_ REGISTER_OUT f1 0x0000000000000001
# -1
test_fctidz_6:
#_ REGISTER_IN f0 0xbff0000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0xbff0000000000000
#_ REGISTER_OUT f1 0xffffffffffffffff
# -(2^31)
test_fctidz_7:
#_ REGISTER_IN f0 0xc1e0000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0xc1e0000000000000
#_ REGISTER_OUT f1 0xffffffff80000000
# 2^31 - 1
test_fctidz_8:
#_ REGISTER_IN f0 0x41dfffffffc00000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x41dfffffffc00000
#_ REGISTER_OUT f1 0x000000007fffffff
# +infinity
test_fctidz_9:
#_ REGISTER_IN f0 0x7ff0000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0x7ff0000000000000
#_ REGISTER_OUT f1 0x7fffffffffffffff
# -infinity
test_fctidz_10:
#_ REGISTER_IN f0 0xfff0000000000000
fctidz f1, f0
blr
#_ REGISTER_OUT f0 0xfff0000000000000
#_ REGISTER_OUT f1 0x8000000000000000
# TODO(DrChat): Xenia doesn't handle NaNs yet.
# # QNaN
# test_fctidz_11:
# #_ REGISTER_IN f0 0xfff8000000000000
# fctidz f1, f0
# blr
# #_ REGISTER_OUT f0 0xfff8000000000000
# #_ REGISTER_OUT f1 0x8000000000000000
#
# # SNaN
# test_fctidz_12:
# #_ REGISTER_IN f0 0xfff4000000000000
# fctidz f1, f0
# blr
# #_ REGISTER_OUT f0 0xfff4000000000000
# #_ REGISTER_OUT f1 0x8000000000000000
|
xenia-project/xenia | 4,393 | src/xenia/cpu/ppc/testing/instr_and.s | test_and_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_and_1_constant:
li r5, -1
li r25, -1
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_and_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
test_and_2_constant:
li r5, -1
li r25, 0
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
test_and_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_and_3_constant:
li r5, 0
li r25, -1
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_and_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
test_and_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
test_and_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
and r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
test_and_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
and r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
test_and_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_and_cr_1_constant:
li r5, -1
li r25, -1
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_and_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_2_constant:
li r5, -1
li r25, 0
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_3_constant:
li r5, 0
li r25, -1
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
#_ REGISTER_OUT r12 0x40000000
test_and_cr_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
#_ REGISTER_OUT r12 0x40000000
test_and_cr_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
and. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
#_ REGISTER_OUT r12 0x40000000
test_and_cr_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
and. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
#_ REGISTER_OUT r12 0x40000000
|
xenia-project/xenia | 1,338 | src/xenia/cpu/ppc/testing/instr_addis.s | test_addis_1:
#_ REGISTER_IN r0 1234
#_ REGISTER_IN r4 1
addis r3, r0, 1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0x10000
#_ REGISTER_OUT r4 1
test_addis_1_constant:
li r0, 1234
li r4, 1
addis r3, r0, 1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0x10000
#_ REGISTER_OUT r4 1
test_addis_2:
#_ REGISTER_IN r4 1234
#_ REGISTER_IN r5 1
addis r3, r4, 1
blr
#_ REGISTER_OUT r3 0x104D2
#_ REGISTER_OUT r4 1234
test_addis_2_constant:
li r4, 1234
li r5, 1
addis r3, r4, 1
blr
#_ REGISTER_OUT r3 0x104D2
#_ REGISTER_OUT r4 1234
test_lis_1:
#_ REGISTER_IN r0 1234
lis r3, 1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0x10000
test_lis_1_constant:
li r0, 1234
lis r3, 1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0x10000
test_lis_2:
#_ REGISTER_IN r0 1234
lis r3, -1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF0000
test_lis_2_constant:
li r0, 1234
lis r3, -1
blr
#_ REGISTER_OUT r0 1234
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF0000
test_subis_1:
#_ REGISTER_IN r4 1234
#_ REGISTER_IN r5 1
subis r3, r4, 1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF04D2
#_ REGISTER_OUT r4 1234
test_subis_1_constant:
li r4, 1234
li r5, 1
subis r3, r4, 1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFF04D2
#_ REGISTER_OUT r4 1234
|
xenia-project/xenia | 1,127 | src/xenia/cpu/ppc/testing/instr_vsr.s | test_vsr_1:
#_ REGISTER_IN v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsr v3, v3, v4
blr
#_ REGISTER_OUT v3 [0FEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFEF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsr_2:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vsr v3, v3, v4
blr
#_ REGISTER_OUT v3 [00011223, 34455667, 78899AAB, BCCDDEEF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vsr_3:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [07070707, 07070707, 07070707, 07070707]
vsr v3, v3, v4
blr
#_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
test_vsr_4:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v3, v4
blr
#_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
xenia-project/xenia | 3,943 | src/xenia/cpu/ppc/testing/instr_lvexx.s | test_lvebx_1:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001000
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_1_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1000
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_2:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001004
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_2_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1004
lvebx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_1:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001000
lvehx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_1_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1000
lvehx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_2:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001004
lvehx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_2_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1004
lvehx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_1:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001000
lvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_1_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1000
lvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_2:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001004
lvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_2_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1004
lvewx v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_1:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001000
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_1_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1000
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_2:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x10001004
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx128_2_constant:
#_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
lis r4, 0x1000
ori r4, r4, 0x1004
lvewx128 v3, r0, r4
blr
#_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_vslo.s | test_vslo_1:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [04040404, 04040404, 04040404, 04040404]
vslo v3, v3, v4
blr
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v4 [04040404, 04040404, 04040404, 04040404]
test_vslo_2:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [08080808, 08080808, 08080808, 08080808]
vslo v3, v3, v4
blr
#_ REGISTER_OUT v3 [11223344, 55667788, 99AABBCC, DDEEFF00]
#_ REGISTER_OUT v4 [08080808, 08080808, 08080808, 08080808]
test_vslo_3:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [12121212, 12121212, 12121212, 12121212]
vslo v3, v3, v4
blr
#_ REGISTER_OUT v3 [22334455, 66778899, AABBCCDD, EEFF0000]
#_ REGISTER_OUT v4 [12121212, 12121212, 12121212, 12121212]
test_vslo_4:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
vslo v3, v3, v4
blr
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
test_vslo_5:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vslo v3, v3, v4
blr
#_ REGISTER_OUT v3 [FF000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
xenia-project/xenia | 2,563 | src/xenia/cpu/ppc/testing/instr_vcmpxxfp128.s | test_vcmpxxfp128_1:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800000, 3f800000, 3f800000, 3f800000]
vcmpeqfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [ffffffff, ffffffff, ffffffff, ffffffff]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT r3 0x00000080
test_vcmpxxfp128_2:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800001, 3f800000, 3f800000, 3f800000]
vcmpeqfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [00000000, ffffffff, ffffffff, ffffffff]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800001, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT r3 0x00000000
test_vcmpxxfp128_3:
#_ REGISTER_IN v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_IN v5 [3f800001, 3f800001, 3f800001, 3f800001]
vcmpeqfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v4 [3f800000, 3f800000, 3f800000, 3f800000]
#_ REGISTER_OUT v5 [3f800001, 3f800001, 3f800001, 3f800001]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp128_1:
# [5.0, 5.0, 5.0, 5.0]
#_ REGISTER_IN v4 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp128_2:
# [-5.0, -5.0, -5.0, -5.0]
#_ REGISTER_IN v4 [C0A00000, C0A00000, C0A00000, C0A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [C0A00000, C0A00000, C0A00000, C0A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000020
test_vcmpbfp128_3:
# [7.0, -7.0, 5.0, 5.0]
#_ REGISTER_IN v4 [40E00000, C0E00000, 40A00000, 40A00000]
#_ REGISTER_IN v5 [40A00000, 40A00000, 40A00000, 40A00000]
vcmpbfp128. v3, v4, v5
mfocrf r3, 2 # cr6
blr
#_ REGISTER_OUT v4 [40E00000, C0E00000, 40A00000, 40A00000]
#_ REGISTER_OUT v5 [40A00000, 40A00000, 40A00000, 40A00000]
#_ REGISTER_OUT v3 [80000000, 40000000, 00000000, 00000000]
#_ REGISTER_OUT r3 0x00000000
|
xenia-project/xenia | 2,462 | src/xenia/cpu/ppc/testing/instr_srd.s | test_srd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srd_1_constant:
li r4, 1
li r5, 0
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_srd_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_srd_2_constant:
li r4, -1
li r5, 0
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0
test_srd_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_srd_3_constant:
li r4, -1
li r5, 1
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_srd_4:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 62
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000003
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
test_srd_4_constant:
li r4, -1
li r5, 62
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000003
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 62
test_srd_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 63
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_srd_5_constant:
li r4, -1
li r5, 63
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 63
test_srd_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 64
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_srd_6_constant:
li r4, -1
li r5, 64
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 64
test_srd_7:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 100
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
test_srd_7_constant:
li r4, -1
li r5, 100
srd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 100
|
xenia-project/xenia | 3,285 | src/xenia/cpu/ppc/testing/instr_add.s | test_add_1:
#_ REGISTER_IN r5 0x00100000
#_ REGISTER_IN r25 0x0000FFFF
add r11, r5, r25
blr
#_ REGISTER_OUT r5 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
test_add_1_constant:
lis r5, 0x10
li r25, -1
clrldi r25, r25, 48
add r11, r5, r25
blr
#_ REGISTER_OUT r5 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
test_add_2:
#_ REGISTER_IN r0 0x00100000
#_ REGISTER_IN r25 0x0000FFFF
add r11, r0, r25
blr
#_ REGISTER_OUT r0 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
test_add_2_constant:
lis r0, 0x10
li r25, -1
clrldi r25, r25, 48
add r11, r0, r25
blr
#_ REGISTER_OUT r0 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
test_add_cr_1:
#_ REGISTER_IN r5 0x00100000
#_ REGISTER_IN r25 0x0000FFFF
add. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
#_ REGISTER_OUT r12 0x40000000
test_add_cr_1_constant:
lis r5, 0x10
li r25, -1
clrldi r25, r25, 48
add. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
#_ REGISTER_OUT r12 0x40000000
test_add_cr_2:
#_ REGISTER_IN r0 0x00100000
#_ REGISTER_IN r25 0x0000FFFF
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
#_ REGISTER_OUT r12 0x40000000
test_add_cr_2_constant:
lis r0, 0x10
li r25, -1
clrldi r25, r25, 48
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x00100000
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0010FFFF
#_ REGISTER_OUT r12 0x40000000
test_add_cr_3:
#_ REGISTER_IN r0 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x000000000000FFFF
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x000000000000FFFF
#_ REGISTER_OUT r11 0x000000000000FFFE
#_ REGISTER_OUT r12 0x40000000
test_add_cr_3_constant:
li r0, -1
li r25, -1
clrldi r25, r25, 48
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x000000000000FFFF
#_ REGISTER_OUT r11 0x000000000000FFFE
#_ REGISTER_OUT r12 0x40000000
test_add_cr_4:
#_ REGISTER_IN r0 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000000000000001
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000000000000001
#_ REGISTER_OUT r11 0x0000000000000000
#_ REGISTER_OUT r12 0x20000000
test_add_cr_4_constant:
li r0, -1
li r25, 1
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000000000000001
#_ REGISTER_OUT r11 0x0000000000000000
#_ REGISTER_OUT r12 0x20000000
test_add_cr_5:
#_ REGISTER_IN r0 -50
#_ REGISTER_IN r25 -25
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 -50
#_ REGISTER_OUT r25 -25
#_ REGISTER_OUT r11 -75
#_ REGISTER_OUT r12 0x80000000
test_add_cr_5_constant:
li r0, -50
li r25, -25
add. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 -50
#_ REGISTER_OUT r25 -25
#_ REGISTER_OUT r11 -75
#_ REGISTER_OUT r12 0x80000000
|
xenia-project/xenia | 1,768 | src/xenia/cpu/ppc/testing/instr_subf.s | test_subf_1:
#_ REGISTER_IN r10 0x00000000000103BF
#_ REGISTER_IN r11 0x00000000000103C0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 0x1
test_subf_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
lis r11, 1
ori r11, r11, 0x03C0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r11 0x00000000000103C0
#_ REGISTER_OUT r3 0x1
test_subf_2:
#_ REGISTER_IN r10 0
#_ REGISTER_IN r11 0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0
test_subf_2_constant:
li r10, 0
li r11, 0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 0
test_subf_3:
#_ REGISTER_IN r10 1
#_ REGISTER_IN r11 0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 -1
test_subf_3_constant:
li r10, 1
li r11, 0
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r3 -1
test_subf_4:
#_ REGISTER_IN r10 0
#_ REGISTER_IN r11 1
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 1
#_ REGISTER_OUT r3 1
test_subf_4_constant:
li r10, 0
li r11, 1
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r11 1
#_ REGISTER_OUT r3 1
test_subf_5:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r11 0xFFFFFFFFFFFFFFFF
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0x0
test_subf_5_constant:
li r10, -1
li r11, -1
subf r3, r10, r11
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0x0
|
xenia-project/xenia | 1,977 | src/xenia/cpu/ppc/testing/instr_mulli.s | test_mulli_1:
#_ REGISTER_IN r4 1
mulli r3, r4, 0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_1_constant:
li r4, 1
mulli r3, r4, 0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_2:
#_ REGISTER_IN r4 1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_mulli_2_constant:
li r4, 1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_mulli_3:
#_ REGISTER_IN r4 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_mulli_3_constant:
li r4, 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_mulli_4:
#_ REGISTER_IN r4 123
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
test_mulli_4_constant:
li r4, 123
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
test_mulli_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_5_constant:
li r4, -1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, 2
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_6_constant:
li r4, -1
mulli r3, r4, 2
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_7:
#_ REGISTER_IN r4 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
test_mulli_7_constant:
li r4, 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
test_mulli_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_8_constant:
li r4, -1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
xenia-project/xenia | 1,419 | src/xenia/cpu/ppc/testing/instr_stvl.s | test_stvlx_1:
#_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
#_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvlx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
test_stvlx_1_constant:
#_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
lis r4, 0x1000
ori r4, r4, 0x1040
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvlx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
test_stvlx_2:
#_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
#_ REGISTER_IN r4 0x10001044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvlx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 10001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB
test_stvlx_2_constant:
#_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
lis r4, 0x1000
ori r4, r4, 0x1044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvlx v3, r4, r0
blr
#_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 10001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB
|
xenia-project/xenia | 5,413 | src/xenia/cpu/ppc/testing/instr_rldicl.s | .macro make_full_test_constant dest, a, b, c, d
lis \dest, \a
ori \dest, \dest, \b
sldi \dest, \dest, 32
lis r3, \c
ori r3, r3, \d
clrldi r3, r3, 32
or \dest, \dest, r3
.endm
test_rldicl_1:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_1_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 24, 0
blr
#_ REGISTER_OUT r3 0x6789abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_2:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 8
blr
#_ REGISTER_OUT r3 0x0089abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_2_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 24, 8
blr
#_ REGISTER_OUT r3 0x0089abcdef012345
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_3:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 24, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_3_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 24, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_4:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 0, 0
blr
#_ REGISTER_OUT r3 0x0123456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_4_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 0, 0
blr
#_ REGISTER_OUT r3 0x0123456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_5:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 0, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_5_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 0, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_6:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 0, 8
blr
#_ REGISTER_OUT r3 0x0023456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_6_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 0, 8
blr
#_ REGISTER_OUT r3 0x0023456789abcdef
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_7:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 63, 0
blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_7_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 63, 0
blr
#_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_8:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 63, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_8_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 63, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_9:
#_ REGISTER_IN r4 0x0123456789ABCDEF
rldicl r3, r4, 31, 0
blr
#_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_9_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
rldicl r3, r4, 31, 0
blr
#_ REGISTER_OUT r3 0xc4d5e6f78091a2b3
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_rldicl_10:
#_ REGISTER_IN r4 0x16300000
rldicl r3, r4, 58, 6
blr
#_ REGISTER_OUT r3 0x58C000
#_ REGISTER_OUT r4 0x16300000
test_rldicl_10_constant:
lis r4, 0x1630
rldicl r3, r4, 58, 6
blr
#_ REGISTER_OUT r3 0x58C000
#_ REGISTER_OUT r4 0x16300000
test_srdi_1:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
srdi r3, r3, 0
srdi r4, r4, 0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_srdi_1_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
srdi r3, r3, 0
srdi r4, r4, 0
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x0123456789ABCDEF
test_srdi_2:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
srdi r3, r3, 1
srdi r4, r4, 1
blr
#_ REGISTER_OUT r3 0x7fffffffffffffff
#_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
test_srdi_2_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
srdi r3, r3, 1
srdi r4, r4, 1
blr
#_ REGISTER_OUT r3 0x7fffffffffffffff
#_ REGISTER_OUT r4 0x0091a2b3c4d5e6f7
test_srdi_3:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
srdi r3, r3, 32
srdi r4, r4, 32
blr
#_ REGISTER_OUT r3 0x00000000ffffffff
#_ REGISTER_OUT r4 0x0000000001234567
test_srdi_3_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
srdi r3, r3, 32
srdi r4, r4, 32
blr
#_ REGISTER_OUT r3 0x00000000ffffffff
#_ REGISTER_OUT r4 0x0000000001234567
test_srdi_4:
#_ REGISTER_IN r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r4 0x0123456789ABCDEF
srdi r3, r3, 63
srdi r4, r4, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0000000000000000
test_srdi_4_constant:
make_full_test_constant r4, 0x0123, 0x4567, 0x89AB, 0xCDEF
li r3, -1
srdi r3, r3, 63
srdi r4, r4, 63
blr
#_ REGISTER_OUT r3 0x0000000000000001
#_ REGISTER_OUT r4 0x0000000000000000
|
xenia-project/xenia | 2,111 | src/xenia/cpu/ppc/testing/instr_subfic.s | test_subfic_1:
#_ REGISTER_IN r10 0x00000000000103BF
subfic r3, r10, 0x3C0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xffffffffffff0001
#_ REGISTER_OUT r4 0
test_subfic_1_constant:
lis r10, 1
ori r10, r10, 0x03BF
subfic r3, r10, 0x3C0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xffffffffffff0001
#_ REGISTER_OUT r4 0
test_subfic_2:
#_ REGISTER_IN r10 0x00000000000103BF
subfic r3, r10, -234
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefb57
#_ REGISTER_OUT r4 1
test_subfic_2_constant:
lis r10, 1
ori r10, r10, 0x03BF
subfic r3, r10, -234
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0x00000000000103BF
#_ REGISTER_OUT r3 0xfffffffffffefb57
#_ REGISTER_OUT r4 1
test_subfic_3:
#_ REGISTER_IN r10 0
subfic r3, r10, 0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfic_3_constant:
li r10, 0
subfic r3, r10, 0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfic_4:
#_ REGISTER_IN r10 1
subfic r3, r10, 0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_subfic_4_constant:
li r10, 1
subfic r3, r10, 0
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 1
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 0
test_subfic_5:
#_ REGISTER_IN r10 0
subfic r3, r10, 1
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfic_5_constant:
li r10, 0
subfic r3, r10, 1
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_subfic_6:
#_ REGISTER_IN r10 0xFFFFFFFFFFFFFFFF
subfic r3, r10, -1
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_subfic_6_constant:
li r10, -1
subfic r3, r10, -1
adde r4, r0, r0
blr
#_ REGISTER_OUT r10 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
|
xenia-project/xenia | 1,399 | src/xenia/cpu/ppc/testing/instr_vmrglw.s | test_vmrglw_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
vmrglw v5, v3, v4
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [08090a0b, 18191a1b, 0c0d0e0f, 1c1d1e1f]
test_vmrglw_2:
#_ REGISTER_IN v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_IN v4 [00000004, 00000005, 00000006, 00000007]
vmrglw v5, v3, v4
blr
#_ REGISTER_OUT v3 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v4 [00000004, 00000005, 00000006, 00000007]
#_ REGISTER_OUT v5 [00000002, 00000006, 00000003, 00000007]
test_vmrglw_3:
#_ REGISTER_IN v3 [C0800000, C0400000, C0000000, BF800000]
#_ REGISTER_IN v4 [00000000, 3F800000, 40000000, 40400000]
vmrglw v5, v3, v4
blr
#_ REGISTER_OUT v3 [C0800000, C0400000, C0000000, BF800000]
#_ REGISTER_OUT v4 [00000000, 3F800000, 40000000, 40400000]
#_ REGISTER_OUT v5 [C0000000, 40000000, BF800000, 40400000]
test_vmrglw_4:
#_ REGISTER_IN v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_IN v4 [00000000, 00000001, 00000002, 00000003]
vmrglw v5, v3, v4
blr
#_ REGISTER_OUT v3 [FFFFFFFC, FFFFFFFD, FFFFFFFE, FFFFFFFF]
#_ REGISTER_OUT v4 [00000000, 00000001, 00000002, 00000003]
#_ REGISTER_OUT v5 [FFFFFFFE, 00000002, FFFFFFFF, 00000003]
|
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