repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
xhawk18/s_task | 13,207 | projects/stm32f103/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 16,132 | projects/stm32f103/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 12,521 | projects/stm32f103/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 15,733 | projects/stm32f103/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for EWARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR address,
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FSMC_IRQHandler
SECTION .text:CODE:REORDER(1)
FSMC_IRQHandler
B FSMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 16,119 | projects/stm32f103/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics *******************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for
;* EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_IRQHandler
B TIM6_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 12,581 | projects/stm32f103/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 10,511 | projects/m051/M051SeriesBSP/LibM051Series/CMSIS/CM0/DeviceSupport/Nuvoton/M051Series/startup/arm/startup_M051Series.s | ;/**************************************************************************//**
; * @file startup_M051Series.s
; * @version V2.00
; * $Revision: 2 $
; * $Date: 4/09/12 2:22p $
; * @brief M051 Series Startup Source File
; *
; * @note
; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
; *
; ******************************************************************************/
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
; maximum of 32 External Interrupts are possible
DCD BOD_IRQHandler
DCD WDT_IRQHandler
DCD EINT0_IRQHandler
DCD EINT1_IRQHandler
DCD GPIOP0P1_IRQHandler
DCD GPIOP2P3P4_IRQHandler
DCD PWMA_IRQHandler
DCD PWMB_IRQHandler
DCD TMR0_IRQHandler
DCD TMR1_IRQHandler
DCD TMR2_IRQHandler
DCD TMR3_IRQHandler
DCD UART0_IRQHandler
DCD UART1_IRQHandler
DCD SPI0_IRQHandler
DCD SPI1_IRQHandler
DCD Default_Handler
DCD Default_Handler
DCD I2C0_IRQHandler
DCD I2C1_IRQHandler
DCD Default_Handler
DCD Default_Handler
DCD Default_Handler
DCD Default_Handler
DCD Default_Handler
DCD ACMP0_IRQHandler
DCD ACMP1_IRQHandler
DCD Default_Handler
DCD PWRWU_IRQHandler
DCD ADC_IRQHandler
DCD Default_Handler
DCD RTC_IRQHandler
AREA |.text|, CODE, READONLY
; Reset Handler
ENTRY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =0x50000100
; Unlock Register
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Init POR
LDR R2, =0x50000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
IF :DEF:DEBUG_ENABLE_SEMIHOST
; Check if the interrupt comes from thread or not
; When enterring interrupt hander
; if CurrentMode==Mode_Handler then
; LR = 0xFFFFFFF1; (previous stack: MSP)
; else
; if CONTROL<1> == '0' then
; LR = 0xFFFFFFF9; (previous stack: MSP)
; else
; LR = 0xFFFFFFFD; (previous stack: PSP)
MOV R0, LR
LSLS R0, R0, #29 ; Check bit 2
BMI SP_is_PSP ; previous stack is PSP
MRS R0, MSP ; previous stack is MSP, read MSP
B SP_Read_Ready
SP_is_PSP
MRS R0, PSP ; Read PSP
SP_Read_Ready
LDR R1, [R0, #24] ; Get previous PC
LDRH R3, [R1] ; Get instruction
LDR R2, =0xBEAB ; The sepcial BKPT instruction
CMP R3, R2 ; Test if the instruction at previous PC is BKPT
BNE HardFault_Handler_Ret ; Not BKPT
ADDS R1, #4 ; Skip BKPT and next line
STR R1, [R0, #24] ; Save previous PC
BX LR
HardFault_Handler_Ret
ENDIF
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT GPIOP0P1_IRQHandler [WEAK]
EXPORT GPIOP2P3P4_IRQHandler [WEAK]
EXPORT PWMA_IRQHandler [WEAK]
EXPORT PWMB_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT ACMP0_IRQHandler [WEAK]
EXPORT ACMP1_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPIOP0P1_IRQHandler
GPIOP2P3P4_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
ACMP0_IRQHandler
ACMP1_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
IF :DEF:DEBUG_ENABLE_SEMIHOST
ALIGN
; int SH_DoCommand(int n32In_R0, int n32In_R1, int *pn32Out_R0);
; Input
; R0,n32In_R0: semihost register 0
; R1,n32In_R1: semihost register 1
; Output
; R2,*pn32Out_R0: semihost register 0
; Return
; 0: No ICE debug
; 1: ICE debug
SH_DoCommand PROC
EXPORT SH_DoCommand
BKPT 0xAB ; Wait ICE or HardFault
; ICE will step over BKPT directly
; HardFault will step BKPT and the next line
B SH_ICE
SH_HardFault ; Captured by HardFault
MOVS R0, #0 ; Set return value to 0
BX lr ; Return
SH_ICE ; Captured by ICE
; Save return value
CMP R2, #0
BEQ SH_End
STR R0, [R2] ; Save the return value to *pn32Out_R0
SH_End
MOVS R0, #1 ; Set return value to 1
BX lr ; Return
ALIGN
ENDP
ENDIF
END
|
xhawk18/s_task | 2,782 | projects/m051/M051SeriesBSP/LibM051Series/CMSIS/CM0/DeviceSupport/Nuvoton/M051Series/startup/gcc/semihost.s | /******************************************************************************
* @file: semihost.s
* @author: xhchen
*****************************************************************************/
.code 16
.syntax unified
.text
.thumb_func
.ifdef DEBUG_ENABLE_SEMIHOST
.type SH_DoCommand, function
.type HardFault_Handler, function
/* int SH_DoCommand(int n32In_R0, int n32In_R1, int *pn32Out_R0); */
/* Input */
/* R0,n32In_R0: semihost register 0 */
/* R1,n32In_R1: semihost register 1 */
/* Output */
/* R2,*pn32Out_R0: semihost register 0 */
/* Return */
/* 0: No ICE debug */
/* 1: ICE debug */
.global SH_DoCommand
SH_DoCommand:
BKPT 0xAB /* Wait ICE or HardFault */
/* ICE will step over BKPT directly */
/* HardFault will step BKPT and the next line */
B SH_ICE
SH_HardFault: /* Captured by HardFault */
MOVS R0, #0 /* Set return value to 0 */
BX lr /* Return */
SH_ICE: /* Captured by ICE
/* Save return value
CMP R2, #0
BEQ SH_End
STR R0, [R2] /* Save the return value to *pn32Out_R0 */
SH_End:
MOVS R0, #1 /* Set return value to 1 */
BX lr /* Return */
/* HardFault_Handler */
/* Skip the semihost command in free run mode. */
.global HardFault_Handler
HardFault_Handler:
/* Check if the interrupt comes from thread or not */
/* When enterring interrupt hander */
/* if CurrentMode==Mode_Handler then */
/* LR = 0xFFFFFFF1; (previous stack: MSP) */
/* else */
/* if CONTROL<1> == '0' then */
/* LR = 0xFFFFFFF9; (previous stack: MSP) */
/* else */
/* LR = 0xFFFFFFFD; (previous stack: PSP) */
MOV R0, LR
LSLS R0, R0, #29
BMI SP_is_PSP
MRS R0, MSP
B SP_Read_Ready
SP_is_PSP:
MRS R0, PSP
SP_Read_Ready:
LDR R1, [R0, #24] /* Get previous PC */
LDRH R3, [R1] /* Get instruction */
LDR R2, =0xBEAB /* The sepcial BKPT instruction */
CMP R3, R2 /* Test if the instruction at previous PC is BKPT */
BNE HardFault_Handler_Ret /* Not BKPT */
ADDS R1, #4 /* Skip BKPT and next line */
STR R1, [R0, #24] /* Save previous PC */
BX LR
HardFault_Handler_Ret:
B .
.endif
.end
|
xhawk18/s_task | 8,586 | projects/m051/M051SeriesBSP/LibM051Series/CMSIS/CM0/DeviceSupport/Nuvoton/M051Series/startup/iar/startup_M051Series.s | ;/**************************************************************************//**
; * @file startup_M051Series.s
; * @version V2.00
; * $Revision: 2 $
; * $Date: 12/04/24 11:46a $
; * @brief M051 Series Startup Source File for IAR Platform
; *
; * @note
; * Copyright (C) 2011 Nuvoton Technology Corp. All rights reserved.
; *
; ******************************************************************************/
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
EXTERN SystemInit
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD __iar_program_start
DCD NMI_Handler
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD BOD_IRQHandler ; Brownout low voltage detected interrupt
DCD WDT_IRQHandler ; Watch Dog Timer interrupt
DCD EINT0_IRQHandler ; External signal interrupt from PB.14 pin
DCD EINT1_IRQHandler ; External signal interrupt from PB.15 pin
DCD GPIOP0P1_IRQHandler ; External signal interrupt from P0[15:0] / P1[13:0]
DCD GPIOP2P3P4_IRQHandler ; External interrupt from P2[15:0]/P3[15:0]/P4[15:0]
DCD PWMA_IRQHandler ; PWM0 or PWM2 interrupt
DCD PWMB_IRQHandler ; PWM1 or PWM3 interrupt
DCD TMR0_IRQHandler ; Timer 0 interrupt
DCD TMR1_IRQHandler ; Timer 1 interrupt
DCD TMR2_IRQHandler ; Timer 2 interrupt
DCD TMR3_IRQHandler ; Timer 3 interrupt
DCD UART0_IRQHandler ; UART0 interrupt
DCD UART1_IRQHandler ; UART1 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD Default_Handler ; SPI2 interrupt
DCD Default_Handler ; SPI3 interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD Default_Handler ; Reserved
DCD ACMP0_IRQHandler ; ACMP0 interrupt
DCD ACMP1_IRQHandler ; ACMP1 interrupt
DCD Default_Handler ; Reserved
DCD PWRWU_IRQHandler ; Clock controller interrupt for chip wake up from power-
DCD ADC_IRQHandler ; ADC interrupt
DCD Default_Handler ; Reserved
DCD RTC_IRQHandler ; Real time clock interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2) ; 4 bytes alignment
Reset_Handler
LDR R0, =0x50000100
; Unlock Register
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
; Init POR
LDR R2, =0x50000024
LDR R1, =0x00005AA5
STR R1, [R2]
; Disable NMI (Assign to reserved IRQ)
LDR R2, =0x50000380
LDR R1, =0x0000001F
STR R1, [R2]
; Lock register
MOVS R1, #0
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
PUBWEAK SVC_Handler
PUBWEAK PendSV_Handler
PUBWEAK SysTick_Handler
PUBWEAK BOD_IRQHandler
PUBWEAK WDT_IRQHandler
PUBWEAK EINT0_IRQHandler
PUBWEAK EINT1_IRQHandler
PUBWEAK GPIOP0P1_IRQHandler
PUBWEAK GPIOP2P3P4_IRQHandler
PUBWEAK PWMA_IRQHandler
PUBWEAK PWMB_IRQHandler
PUBWEAK TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler
PUBWEAK TMR3_IRQHandler
PUBWEAK UART0_IRQHandler
PUBWEAK UART1_IRQHandler
PUBWEAK SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C1_IRQHandler
PUBWEAK ACMP0_IRQHandler
PUBWEAK ACMP1_IRQHandler
PUBWEAK PWRWU_IRQHandler
PUBWEAK ADC_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(2)
HardFault_Handler
#ifdef DEBUG_ENABLE_SEMIHOST
; Check if the interrupt comes from thread or not
; When enterring interrupt hander
; if CurrentMode==Mode_Handler then
; LR = 0xFFFFFFF1; (previous stack: MSP)
; else
; if CONTROL<1> == '0' then
; LR = 0xFFFFFFF9; (previous stack: MSP)
; else
; LR = 0xFFFFFFFD; (previous stack: PSP)
MOV R0, LR
LSLS R0, R0, #29 ; Check bit 2
BMI SP_is_PSP ; previous stack is PSP
MRS R0, MSP ; previous stack is MSP, read MSP
B SP_Read_Ready
SP_is_PSP
MRS R0, PSP ; Read PSP
SP_Read_Ready
LDR R1, [R0, #24] ; Get previous PC
LDRH R3, [R1] ; Get instruction
LDR R2, =0xBEAB ; The sepcial BKPT instruction
CMP R3, R2 ; Test if the instruction at previous PC is BKPT
BNE HardFault_Handler_Ret ; Not BKPT
ADDS R1, #4 ; Skip BKPT and next line
STR R1, [R0, #24] ; Save previous PC
BX LR
HardFault_Handler_Ret
#endif
NMI_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
BOD_IRQHandler
WDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
GPIOP0P1_IRQHandler
GPIOP2P3P4_IRQHandler
PWMA_IRQHandler
PWMB_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
ACMP0_IRQHandler
ACMP1_IRQHandler
PWRWU_IRQHandler
ADC_IRQHandler
RTC_IRQHandler
Default_Handler
B Default_Handler
#ifdef DEBUG_ENABLE_SEMIHOST
; int SH_DoCommand(int n32In_R0, int n32In_R1, int *pn32Out_R0);
; Input
; R0,n32In_R0: semihost register 0
; R1,n32In_R1: semihost register 1
; Output
; R2,*pn32Out_R0: semihost register 0
; Return
; 0: No ICE debug
; 1: ICE debug
SH_DoCommand
EXPORT SH_DoCommand
BKPT 0xAB ; Wait ICE or HardFault
; ICE will step over BKPT directly
; HardFault will step BKPT and the next line
B SH_ICE
SH_HardFault ; Captured by HardFault
MOVS R0, #0 ; Set return value to 0
BX lr ; Return
SH_ICE ; Captured by ICE
; Save return value
CMP R2, #0
BEQ SH_End
STR R0, [R2] ; Save the return value to *pn32Out_R0
SH_End
MOVS R0, #1 ; Set return value to 1
BX lr ; Return
#endif
END
|
xhawk18/s_task | 12,698 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/gcc_ride7/startup_stm32f30x.s | /**
******************************************************************************
* @file startup_stm32f30x.s
* @author MCD Application Team
* @version V1.2.2
* @date 27-February-2015
* @brief STM32F30x Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3230C-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 25,940 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f30x.s | ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f30x.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F30x devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
xhawk18/s_task | 25,944 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f303xc.s | ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f303xc.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F303xC devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
xhawk18/s_task | 23,432 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f302x8.s | ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f302x8.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F302x8 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD 0 ; Reserved
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT COMP2_IRQHandler [WEAK]
EXPORT COMP4_6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
SPI3_IRQHandler
TIM6_DAC_IRQHandler
COMP2_IRQHandler
COMP4_6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
xhawk18/s_task | 26,892 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f303xe.s | ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f303xe.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F303xE devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD TIM20_BRK_IRQHandler ; TIM20 Break
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ADC4_IRQHandler [WEAK]
EXPORT COMP1_2_3_IRQHandler [WEAK]
EXPORT COMP4_5_6_IRQHandler [WEAK]
EXPORT COMP7_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
EXPORT TIM20_BRK_IRQHandler [WEAK]
EXPORT TIM20_UP_IRQHandler [WEAK]
EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
EXPORT TIM20_CC_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FMC_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ADC4_IRQHandler
COMP1_2_3_IRQHandler
COMP4_5_6_IRQHandler
COMP7_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
USBWakeUp_RMP_IRQHandler
TIM20_BRK_IRQHandler
TIM20_UP_IRQHandler
TIM20_TRG_COM_IRQHandler
TIM20_CC_IRQHandler
FPU_IRQHandler
SPI4_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
xhawk18/s_task | 21,791 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/arm/startup_stm32f334x8.s | ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f334x8.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F334 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event and EXTI Line 23
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1 and EXTI Line 25
DCD USART2_IRQHandler ; USART2 and EXTI Line 26
DCD USART3_IRQHandler ; USART3 and EXTI Line 28
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4, COMP6
DCD 0 ; Reserved
DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
DCD HRTIM1_TIMA_IRQHandler ; Reserved
DCD HRTIM1_TIMB_IRQHandler ; Reserved
DCD HRTIM1_TIMC_IRQHandler ; Reserved
DCD HRTIM1_TIMD_IRQHandler ; Reserved
DCD HRTIM1_TIME_IRQHandler ; Reserved
DCD HRTIM1_FLT_IRQHandler ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_TS_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT TIM6_DAC1_IRQHandler [WEAK]
EXPORT TIM7_DAC2_IRQHandler [WEAK]
EXPORT COMP2_IRQHandler [WEAK]
EXPORT COMP4_6_IRQHandler [WEAK]
EXPORT HRTIM1_Master_IRQHandler [WEAK]
EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
EXPORT HRTIM1_TIME_IRQHandler [WEAK]
EXPORT HRTIM1_FLT_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_TS_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
TIM6_DAC1_IRQHandler
TIM7_DAC2_IRQHandler
COMP2_IRQHandler
COMP4_6_IRQHandler
HRTIM1_Master_IRQHandler
HRTIM1_TIMA_IRQHandler
HRTIM1_TIMB_IRQHandler
HRTIM1_TIMC_IRQHandler
HRTIM1_TIMD_IRQHandler
HRTIM1_TIME_IRQHandler
HRTIM1_FLT_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
xhawk18/s_task | 12,498 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f30x.s | /**
******************************************************************************
* @file startup_stm32f30x.s
* @author MCD Application Team
* @version V1.2.2
* @date 27-February-2015
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 12,500 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f303xc.s | /**
******************************************************************************
* @file startup_stm32f303xC.s
* @author MCD Application Team
* @version V1.2.2
* @date 27-February-2015
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 11,020 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f302x8.s | /**
******************************************************************************
* @file startup_stm32f302x8.s
* @author MCD Application Team
* @version V1.2.2
* @date 27-February-2015
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word 0
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word 0
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SPI3_IRQHandler
.word 0
.word 0
.word TIM6_DAC_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word COMP2_IRQHandler
.word COMP4_6_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak COMP2_IRQHandler
.thumb_set COMP2_IRQHandler,Default_Handler
.weak COMP4_6_IRQHandler
.thumb_set COMP4_6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 13,288 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f303xe.s | /**
******************************************************************************
* @file startup_stm32f303xe.s
* @author MCD Application Team
* @version V1.2.2
* @date 27-February-2015
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word 0
.word 0
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ADC4_IRQHandler
.word 0
.word 0
.word COMP1_2_3_IRQHandler
.word COMP4_5_6_IRQHandler
.word COMP7_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word USB_HP_IRQHandler
.word USB_LP_IRQHandler
.word USBWakeUp_RMP_IRQHandler
.word TIM20_BRK_IRQHandler
.word TIM20_UP_IRQHandler
.word TIM20_TRG_COM_IRQHandler
.word TIM20_CC_IRQHandler
.word FPU_IRQHandler
.word 0
.word 0
.word SPI4_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ADC4_IRQHandler
.thumb_set ADC4_IRQHandler,Default_Handler
.weak COMP1_2_3_IRQHandler
.thumb_set COMP1_2_3_IRQHandler,Default_Handler
.weak COMP4_5_6_IRQHandler
.thumb_set COMP4_5_6_IRQHandler,Default_Handler
.weak COMP7_IRQHandler
.thumb_set COMP7_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak USBWakeUp_RMP_IRQHandler
.thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
.weak TIM20_BRK_IRQHandler
.thumb_set TIM20_BRK_IRQHandler,Default_Handler
.weak TIM20_UP_IRQHandler
.thumb_set TIM20_UP_IRQHandler,Default_Handler
.weak TIM20_TRG_COM_IRQHandler
.thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
.weak TIM20_CC_IRQHandler
.thumb_set TIM20_CC_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 11,634 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/TrueSTUDIO/startup_stm32f334x8.s | /**
******************************************************************************
* @file startup_stm32f334x8.s
* @author MCD Application Team
* @version V1.2.2
* @date 27-February-2015
* @brief stm32f30x vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_TS_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM6_DAC1_IRQHandler
.word TIM7_DAC2_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word COMP2_IRQHandler
.word COMP4_6_IRQHandler
.word 0
.word HRTIM1_Master_IRQHandler
.word HRTIM1_TIMA_IRQHandler
.word HRTIM1_TIMB_IRQHandler
.word HRTIM1_TIMC_IRQHandler
.word HRTIM1_TIMD_IRQHandler
.word HRTIM1_TIME_IRQHandler
.word HRTIM1_FLT_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word FPU_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_STAMP_IRQHandler
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_TS_IRQHandler
.thumb_set EXTI2_TS_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak TIM6_DAC1_IRQHandler
.thumb_set TIM6_DAC1_IRQHandler,Default_Handler
.weak TIM7_DAC2_IRQHandler
.thumb_set TIM7_DAC2_IRQHandler,Default_Handler
.weak COMP2_IRQHandler
.thumb_set COMP2_IRQHandler,Default_Handler
.weak COMP4_6_IRQHandler
.thumb_set COMP4_6_IRQHandler,Default_Handler
.weak HRTIM1_Master_IRQHandler
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
.weak HRTIM1_TIMA_IRQHandler
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
.weak HRTIM1_TIMB_IRQHandler
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
.weak HRTIM1_TIMC_IRQHandler
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
.weak HRTIM1_TIMD_IRQHandler
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
.weak HRTIM1_TIME_IRQHandler
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
.weak HRTIM1_FLT_IRQHandler
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 22,993 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f30x.s | ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f30x.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F30x devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 22,997 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f303xc.s | ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f303xc.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F303xC devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 20,717 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f302x8.s | ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f302x8.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F302x8 devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD 0 ; Reserved
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4 and COMP6
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK COMP2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP2_IRQHandler
B COMP2_IRQHandler
PUBWEAK COMP4_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_6_IRQHandler
B COMP4_6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 24,260 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f303xe.s | ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f334x8.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB Device High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Device Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event through EXTI Line 23
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1 through EXTI Line 25
DCD USART2_IRQHandler ; USART2 through EXTI Line 26
DCD USART3_IRQHandler ; USART3 through EXTI Line 28
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FMC_IRQHandler ; FMC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD ADC4_IRQHandler ; ADC4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
DCD COMP7_IRQHandler ; COMP7
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C3_EV_IRQHandler ; I2C3 Event
DCD I2C3_ER_IRQHandler ; I2C3 Error
DCD USB_HP_IRQHandler ; USB High Priority remap
DCD USB_LP_IRQHandler ; USB Low Priority remap
DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
DCD TIM20_BRK_IRQHandler ; TIM20 Break
DCD TIM20_UP_IRQHandler ; TIM20 Update
DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK USB_HP_CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_HP_CAN1_TX_IRQHandler
B USB_HP_CAN1_TX_IRQHandler
PUBWEAK USB_LP_CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USB_LP_CAN1_RX0_IRQHandler
B USB_LP_CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK USBWakeUp_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USBWakeUp_IRQHandler
B USBWakeUp_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK ADC4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC4_IRQHandler
B ADC4_IRQHandler
PUBWEAK COMP1_2_3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP1_2_3_IRQHandler
B COMP1_2_3_IRQHandler
PUBWEAK COMP4_5_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_5_6_IRQHandler
B COMP4_5_6_IRQHandler
PUBWEAK COMP7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP7_IRQHandler
B COMP7_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK USB_HP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_HP_IRQHandler
B USB_HP_IRQHandler
PUBWEAK USB_LP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_LP_IRQHandler
B USB_LP_IRQHandler
PUBWEAK USBWakeUp_RMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBWakeUp_RMP_IRQHandler
B USBWakeUp_RMP_IRQHandler
PUBWEAK TIM20_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_BRK_IRQHandler
B TIM20_BRK_IRQHandler
PUBWEAK TIM20_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_UP_IRQHandler
B TIM20_UP_IRQHandler
PUBWEAK TIM20_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_TRG_COM_IRQHandler
B TIM20_TRG_COM_IRQHandler
PUBWEAK TIM20_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM20_CC_IRQHandler
B TIM20_CC_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI4_IRQHandler
B SPI4_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 20,833 | projects/stm32f302/Libraries/CMSIS/Device/ST/STM32F30x/Source/Templates/iar/startup_stm32f334x8.s | ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f334x8.s
;* Author : MCD Application Team
;* Version : V1.2.2
;* Date : 27-February-2015
;* Description : STM32F334x8 devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
;* You may not use this file except in compliance with the License.
;* You may obtain a copy of the License at:
;*
;* http://www.st.com/software_license_agreement_liberty_v2
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMPER_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_TS_IRQHandler ; EXTI Line2 and Touch Sense
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event through EXTI Line 23
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1 through EXTI Line 25
DCD USART2_IRQHandler ; USART2 through EXTI Line 26
DCD USART3_IRQHandler ; USART3 through EXTI Line 28
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC1_IRQHandler ; TIM6 and DAC1 underrun errors
DCD TIM7_DAC2_IRQHandler ; TIM7 and DAC2 underrun errors
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP2_IRQHandler ; COMP2
DCD COMP4_6_IRQHandler ; COMP4, COMP6
DCD 0 ; Reserved
DCD HRTIM1_Master_IRQHandler ; HRTIM1 master timer
DCD HRTIM1_TIMA_IRQHandler ; HRTIM1 timer A
DCD HRTIM1_TIMB_IRQHandler ; HRTIM1 timer B
DCD HRTIM1_TIMC_IRQHandler ; HRTIM1 timer C
DCD HRTIM1_TIMD_IRQHandler ; HRTIM1 timer D
DCD HRTIM1_TIME_IRQHandler ; HRTIM1 timer E
DCD HRTIM1_FLT_IRQHandler ; HRTIM1 fault
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMPER_STAMP_IRQHandler
B TAMPER_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_TS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_TS_IRQHandler
B EXTI2_TS_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK TIM6_DAC1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC1_IRQHandler
B TIM6_DAC1_IRQHandler
PUBWEAK TIM7_DAC2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_DAC2_IRQHandler
B TIM7_DAC2_IRQHandler
PUBWEAK COMP2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP2_IRQHandler
B COMP2_IRQHandler
PUBWEAK COMP4_6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
COMP4_6_IRQHandler
B COMP4_6_IRQHandler
PUBWEAK HRTIM1_Master_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_Master_IRQHandler
B HRTIM1_Master_IRQHandler
PUBWEAK HRTIM1_TIMA_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMA_IRQHandler
B HRTIM1_TIMA_IRQHandler
PUBWEAK HRTIM1_TIMB_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMB_IRQHandler
B HRTIM1_TIMB_IRQHandler
PUBWEAK HRTIM1_TIMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMC_IRQHandler
B HRTIM1_TIMC_IRQHandler
PUBWEAK HRTIM1_TIMD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIMD_IRQHandler
B HRTIM1_TIMD_IRQHandler
PUBWEAK HRTIM1_TIME_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_TIME_IRQHandler
B HRTIM1_TIME_IRQHandler
PUBWEAK HRTIM1_FLT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HRTIM1_FLT_IRQHandler
B HRTIM1_FLT_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xhawk18/s_task | 17,102 | projects/stm32l431cc/MDK-ARM/startup_stm32l431xx.s | ;*******************************************************************************
;* File Name : startup_stm32l431xx.s
;* Author : MCD Application Team
;* Description : STM32L431xx Ultra Low Power devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SDMMC1_IRQHandler ; SDMMC1
DCD 0 ; Reserved
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD 0 ; Reserved
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD 0 ; Reserved
DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_PVM_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT SDMMC1_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT LPTIM1_IRQHandler [WEAK]
EXPORT LPTIM2_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SWPMI1_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT CRS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_PVM_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
SDMMC1_IRQHandler
SPI3_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
COMP_IRQHandler
LPTIM1_IRQHandler
LPTIM2_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
LPUART1_IRQHandler
QUADSPI_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
SAI1_IRQHandler
SWPMI1_IRQHandler
TSC_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
CRS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
Xharlie/DISN | 15,136 | isosurface/tbb/tbb-2018_U6/src/tbb/ia64-gas/atomic_support.s | // Copyright (c) 2005-2018 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
//
//
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchadd1__TBB_full_fence#
.global __TBB_machine_fetchadd1__TBB_full_fence#
__TBB_machine_fetchadd1__TBB_full_fence:
{
mf
br __TBB_machine_fetchadd1acquire
}
.endp __TBB_machine_fetchadd1__TBB_full_fence#
.proc __TBB_machine_fetchadd1acquire#
.global __TBB_machine_fetchadd1acquire#
__TBB_machine_fetchadd1acquire:
ld1 r9=[r32]
;;
Retry_1acquire:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg1.acq r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_1acquire
br.ret.sptk.many b0
# 49 "<stdin>"
.endp __TBB_machine_fetchadd1acquire#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore1__TBB_full_fence#
.global __TBB_machine_fetchstore1__TBB_full_fence#
__TBB_machine_fetchstore1__TBB_full_fence:
mf
;;
xchg1 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore1__TBB_full_fence#
.proc __TBB_machine_fetchstore1acquire#
.global __TBB_machine_fetchstore1acquire#
__TBB_machine_fetchstore1acquire:
xchg1 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore1acquire#
# 88 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_cmpswp1__TBB_full_fence#
.global __TBB_machine_cmpswp1__TBB_full_fence#
__TBB_machine_cmpswp1__TBB_full_fence:
{
mf
br __TBB_machine_cmpswp1acquire
}
.endp __TBB_machine_cmpswp1__TBB_full_fence#
.proc __TBB_machine_cmpswp1acquire#
.global __TBB_machine_cmpswp1acquire#
__TBB_machine_cmpswp1acquire:
zxt1 r34=r34
;;
mov ar.ccv=r34
;;
cmpxchg1.acq r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp1acquire#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchadd2__TBB_full_fence#
.global __TBB_machine_fetchadd2__TBB_full_fence#
__TBB_machine_fetchadd2__TBB_full_fence:
{
mf
br __TBB_machine_fetchadd2acquire
}
.endp __TBB_machine_fetchadd2__TBB_full_fence#
.proc __TBB_machine_fetchadd2acquire#
.global __TBB_machine_fetchadd2acquire#
__TBB_machine_fetchadd2acquire:
ld2 r9=[r32]
;;
Retry_2acquire:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg2.acq r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_2acquire
br.ret.sptk.many b0
# 49 "<stdin>"
.endp __TBB_machine_fetchadd2acquire#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore2__TBB_full_fence#
.global __TBB_machine_fetchstore2__TBB_full_fence#
__TBB_machine_fetchstore2__TBB_full_fence:
mf
;;
xchg2 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore2__TBB_full_fence#
.proc __TBB_machine_fetchstore2acquire#
.global __TBB_machine_fetchstore2acquire#
__TBB_machine_fetchstore2acquire:
xchg2 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore2acquire#
# 88 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_cmpswp2__TBB_full_fence#
.global __TBB_machine_cmpswp2__TBB_full_fence#
__TBB_machine_cmpswp2__TBB_full_fence:
{
mf
br __TBB_machine_cmpswp2acquire
}
.endp __TBB_machine_cmpswp2__TBB_full_fence#
.proc __TBB_machine_cmpswp2acquire#
.global __TBB_machine_cmpswp2acquire#
__TBB_machine_cmpswp2acquire:
zxt2 r34=r34
;;
mov ar.ccv=r34
;;
cmpxchg2.acq r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp2acquire#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchadd4__TBB_full_fence#
.global __TBB_machine_fetchadd4__TBB_full_fence#
__TBB_machine_fetchadd4__TBB_full_fence:
{
mf
br __TBB_machine_fetchadd4acquire
}
.endp __TBB_machine_fetchadd4__TBB_full_fence#
.proc __TBB_machine_fetchadd4acquire#
.global __TBB_machine_fetchadd4acquire#
__TBB_machine_fetchadd4acquire:
cmp.eq p6,p0=1,r33
cmp.eq p8,p0=-1,r33
(p6) br.cond.dptk Inc_4acquire
(p8) br.cond.dpnt Dec_4acquire
;;
ld4 r9=[r32]
;;
Retry_4acquire:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg4.acq r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_4acquire
br.ret.sptk.many b0
Inc_4acquire:
fetchadd4.acq r8=[r32],1
br.ret.sptk.many b0
Dec_4acquire:
fetchadd4.acq r8=[r32],-1
br.ret.sptk.many b0
.endp __TBB_machine_fetchadd4acquire#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore4__TBB_full_fence#
.global __TBB_machine_fetchstore4__TBB_full_fence#
__TBB_machine_fetchstore4__TBB_full_fence:
mf
;;
xchg4 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore4__TBB_full_fence#
.proc __TBB_machine_fetchstore4acquire#
.global __TBB_machine_fetchstore4acquire#
__TBB_machine_fetchstore4acquire:
xchg4 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore4acquire#
# 88 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_cmpswp4__TBB_full_fence#
.global __TBB_machine_cmpswp4__TBB_full_fence#
__TBB_machine_cmpswp4__TBB_full_fence:
{
mf
br __TBB_machine_cmpswp4acquire
}
.endp __TBB_machine_cmpswp4__TBB_full_fence#
.proc __TBB_machine_cmpswp4acquire#
.global __TBB_machine_cmpswp4acquire#
__TBB_machine_cmpswp4acquire:
zxt4 r34=r34
;;
mov ar.ccv=r34
;;
cmpxchg4.acq r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp4acquire#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchadd8__TBB_full_fence#
.global __TBB_machine_fetchadd8__TBB_full_fence#
__TBB_machine_fetchadd8__TBB_full_fence:
{
mf
br __TBB_machine_fetchadd8acquire
}
.endp __TBB_machine_fetchadd8__TBB_full_fence#
.proc __TBB_machine_fetchadd8acquire#
.global __TBB_machine_fetchadd8acquire#
__TBB_machine_fetchadd8acquire:
cmp.eq p6,p0=1,r33
cmp.eq p8,p0=-1,r33
(p6) br.cond.dptk Inc_8acquire
(p8) br.cond.dpnt Dec_8acquire
;;
ld8 r9=[r32]
;;
Retry_8acquire:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg8.acq r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_8acquire
br.ret.sptk.many b0
Inc_8acquire:
fetchadd8.acq r8=[r32],1
br.ret.sptk.many b0
Dec_8acquire:
fetchadd8.acq r8=[r32],-1
br.ret.sptk.many b0
.endp __TBB_machine_fetchadd8acquire#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore8__TBB_full_fence#
.global __TBB_machine_fetchstore8__TBB_full_fence#
__TBB_machine_fetchstore8__TBB_full_fence:
mf
;;
xchg8 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore8__TBB_full_fence#
.proc __TBB_machine_fetchstore8acquire#
.global __TBB_machine_fetchstore8acquire#
__TBB_machine_fetchstore8acquire:
xchg8 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore8acquire#
# 88 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_cmpswp8__TBB_full_fence#
.global __TBB_machine_cmpswp8__TBB_full_fence#
__TBB_machine_cmpswp8__TBB_full_fence:
{
mf
br __TBB_machine_cmpswp8acquire
}
.endp __TBB_machine_cmpswp8__TBB_full_fence#
.proc __TBB_machine_cmpswp8acquire#
.global __TBB_machine_cmpswp8acquire#
__TBB_machine_cmpswp8acquire:
mov ar.ccv=r34
;;
cmpxchg8.acq r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp8acquire#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
# 19 "<stdin>"
.proc __TBB_machine_fetchadd1release#
.global __TBB_machine_fetchadd1release#
__TBB_machine_fetchadd1release:
ld1 r9=[r32]
;;
Retry_1release:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg1.rel r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_1release
br.ret.sptk.many b0
# 49 "<stdin>"
.endp __TBB_machine_fetchadd1release#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore1release#
.global __TBB_machine_fetchstore1release#
__TBB_machine_fetchstore1release:
mf
;;
xchg1 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore1release#
# 88 "<stdin>"
.section .text
.align 16
# 101 "<stdin>"
.proc __TBB_machine_cmpswp1release#
.global __TBB_machine_cmpswp1release#
__TBB_machine_cmpswp1release:
zxt1 r34=r34
;;
mov ar.ccv=r34
;;
cmpxchg1.rel r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp1release#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
# 19 "<stdin>"
.proc __TBB_machine_fetchadd2release#
.global __TBB_machine_fetchadd2release#
__TBB_machine_fetchadd2release:
ld2 r9=[r32]
;;
Retry_2release:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg2.rel r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_2release
br.ret.sptk.many b0
# 49 "<stdin>"
.endp __TBB_machine_fetchadd2release#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore2release#
.global __TBB_machine_fetchstore2release#
__TBB_machine_fetchstore2release:
mf
;;
xchg2 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore2release#
# 88 "<stdin>"
.section .text
.align 16
# 101 "<stdin>"
.proc __TBB_machine_cmpswp2release#
.global __TBB_machine_cmpswp2release#
__TBB_machine_cmpswp2release:
zxt2 r34=r34
;;
mov ar.ccv=r34
;;
cmpxchg2.rel r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp2release#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
# 19 "<stdin>"
.proc __TBB_machine_fetchadd4release#
.global __TBB_machine_fetchadd4release#
__TBB_machine_fetchadd4release:
cmp.eq p6,p0=1,r33
cmp.eq p8,p0=-1,r33
(p6) br.cond.dptk Inc_4release
(p8) br.cond.dpnt Dec_4release
;;
ld4 r9=[r32]
;;
Retry_4release:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg4.rel r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_4release
br.ret.sptk.many b0
Inc_4release:
fetchadd4.rel r8=[r32],1
br.ret.sptk.many b0
Dec_4release:
fetchadd4.rel r8=[r32],-1
br.ret.sptk.many b0
.endp __TBB_machine_fetchadd4release#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore4release#
.global __TBB_machine_fetchstore4release#
__TBB_machine_fetchstore4release:
mf
;;
xchg4 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore4release#
# 88 "<stdin>"
.section .text
.align 16
# 101 "<stdin>"
.proc __TBB_machine_cmpswp4release#
.global __TBB_machine_cmpswp4release#
__TBB_machine_cmpswp4release:
zxt4 r34=r34
;;
mov ar.ccv=r34
;;
cmpxchg4.rel r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp4release#
// DO NOT EDIT - AUTOMATICALLY GENERATED FROM tools/generate_atomic/ipf_generate.sh
# 1 "<stdin>"
# 1 "<built-in>"
# 1 "<command line>"
# 1 "<stdin>"
.section .text
.align 16
# 19 "<stdin>"
.proc __TBB_machine_fetchadd8release#
.global __TBB_machine_fetchadd8release#
__TBB_machine_fetchadd8release:
cmp.eq p6,p0=1,r33
cmp.eq p8,p0=-1,r33
(p6) br.cond.dptk Inc_8release
(p8) br.cond.dpnt Dec_8release
;;
ld8 r9=[r32]
;;
Retry_8release:
mov ar.ccv=r9
mov r8=r9;
add r10=r9,r33
;;
cmpxchg8.rel r9=[r32],r10,ar.ccv
;;
cmp.ne p7,p0=r8,r9
(p7) br.cond.dpnt Retry_8release
br.ret.sptk.many b0
Inc_8release:
fetchadd8.rel r8=[r32],1
br.ret.sptk.many b0
Dec_8release:
fetchadd8.rel r8=[r32],-1
br.ret.sptk.many b0
.endp __TBB_machine_fetchadd8release#
# 62 "<stdin>"
.section .text
.align 16
.proc __TBB_machine_fetchstore8release#
.global __TBB_machine_fetchstore8release#
__TBB_machine_fetchstore8release:
mf
;;
xchg8 r8=[r32],r33
br.ret.sptk.many b0
.endp __TBB_machine_fetchstore8release#
# 88 "<stdin>"
.section .text
.align 16
# 101 "<stdin>"
.proc __TBB_machine_cmpswp8release#
.global __TBB_machine_cmpswp8release#
__TBB_machine_cmpswp8release:
mov ar.ccv=r34
;;
cmpxchg8.rel r8=[r32],r33,ar.ccv
br.ret.sptk.many b0
.endp __TBB_machine_cmpswp8release#
|
Xharlie/DISN | 2,699 | isosurface/tbb/tbb-2018_U6/src/tbb/ia64-gas/ia64_misc.s | // Copyright (c) 2005-2018 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
//
//
// RSE backing store pointer retrieval
.section .text
.align 16
.proc __TBB_get_bsp#
.global __TBB_get_bsp#
__TBB_get_bsp:
mov r8=ar.bsp
br.ret.sptk.many b0
.endp __TBB_get_bsp#
.section .text
.align 16
.proc __TBB_machine_load8_relaxed#
.global __TBB_machine_load8_relaxed#
__TBB_machine_load8_relaxed:
ld8 r8=[r32]
br.ret.sptk.many b0
.endp __TBB_machine_load8_relaxed#
.section .text
.align 16
.proc __TBB_machine_store8_relaxed#
.global __TBB_machine_store8_relaxed#
__TBB_machine_store8_relaxed:
st8 [r32]=r33
br.ret.sptk.many b0
.endp __TBB_machine_store8_relaxed#
.section .text
.align 16
.proc __TBB_machine_load4_relaxed#
.global __TBB_machine_load4_relaxed#
__TBB_machine_load4_relaxed:
ld4 r8=[r32]
br.ret.sptk.many b0
.endp __TBB_machine_load4_relaxed#
.section .text
.align 16
.proc __TBB_machine_store4_relaxed#
.global __TBB_machine_store4_relaxed#
__TBB_machine_store4_relaxed:
st4 [r32]=r33
br.ret.sptk.many b0
.endp __TBB_machine_store4_relaxed#
.section .text
.align 16
.proc __TBB_machine_load2_relaxed#
.global __TBB_machine_load2_relaxed#
__TBB_machine_load2_relaxed:
ld2 r8=[r32]
br.ret.sptk.many b0
.endp __TBB_machine_load2_relaxed#
.section .text
.align 16
.proc __TBB_machine_store2_relaxed#
.global __TBB_machine_store2_relaxed#
__TBB_machine_store2_relaxed:
st2 [r32]=r33
br.ret.sptk.many b0
.endp __TBB_machine_store2_relaxed#
.section .text
.align 16
.proc __TBB_machine_load1_relaxed#
.global __TBB_machine_load1_relaxed#
__TBB_machine_load1_relaxed:
ld1 r8=[r32]
br.ret.sptk.many b0
.endp __TBB_machine_load1_relaxed#
.section .text
.align 16
.proc __TBB_machine_store1_relaxed#
.global __TBB_machine_store1_relaxed#
__TBB_machine_store1_relaxed:
st1 [r32]=r33
br.ret.sptk.many b0
.endp __TBB_machine_store1_relaxed#
|
Xharlie/DISN | 1,282 | isosurface/tbb/tbb-2018_U6/src/tbb/ia64-gas/lock_byte.s | // Copyright (c) 2005-2018 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
//
//
// Support for class TinyLock
.section .text
.align 16
// unsigned int __TBB_machine_trylockbyte( byte& flag );
// r32 = address of flag
.proc __TBB_machine_trylockbyte#
.global __TBB_machine_trylockbyte#
ADDRESS_OF_FLAG=r32
RETCODE=r8
FLAG=r9
BUSY=r10
SCRATCH=r11
__TBB_machine_trylockbyte:
ld1.acq FLAG=[ADDRESS_OF_FLAG]
mov BUSY=1
mov RETCODE=0
;;
cmp.ne p6,p0=0,FLAG
mov ar.ccv=r0
(p6) br.ret.sptk.many b0
;;
cmpxchg1.acq SCRATCH=[ADDRESS_OF_FLAG],BUSY,ar.ccv // Try to acquire lock
;;
cmp.eq p6,p0=0,SCRATCH
;;
(p6) mov RETCODE=1
br.ret.sptk.many b0
.endp __TBB_machine_trylockbyte#
|
Xharlie/DISN | 1,316 | isosurface/tbb/tbb-2018_U6/src/tbb/ia64-gas/log2.s | // Copyright (c) 2005-2018 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
//
//
.section .text
.align 16
// unsigned long __TBB_machine_lg( unsigned long x );
// r32 = x
.proc __TBB_machine_lg#
.global __TBB_machine_lg#
__TBB_machine_lg:
shr r16=r32,1 // .x
;;
shr r17=r32,2 // ..x
or r32=r32,r16 // xx
;;
shr r16=r32,3 // ...xx
or r32=r32,r17 // xxx
;;
shr r17=r32,5 // .....xxx
or r32=r32,r16 // xxxxx
;;
shr r16=r32,8 // ........xxxxx
or r32=r32,r17 // xxxxxxxx
;;
shr r17=r32,13
or r32=r32,r16 // 13x
;;
shr r16=r32,21
or r32=r32,r17 // 21x
;;
shr r17=r32,34
or r32=r32,r16 // 34x
;;
shr r16=r32,55
or r32=r32,r17 // 55x
;;
or r32=r32,r16 // 64x
;;
popcnt r8=r32
;;
add r8=-1,r8
br.ret.sptk.many b0
.endp __TBB_machine_lg#
|
xi816/gc16x | 1,501 | fun/gpaint.s | main:
mov %ax $0060
mov %si 0
mov %cx 64600
call bg_fill
bg_fill:
int $0C
inx %si
loop bg_fill
int $11
call draw_panel
jmp program_loop
draw_panel:
mov %ax *color
mov %si 64600
sub %si 6800
mov %cx 6800
.loop:
int $0C
inx %si
loop .loop
int $11
ret
program_loop:
call draw_panel
int $01
pop %ax
cmp %ax 'q' ; Quit
jme term
; cmp %ax '$' ; Draw a square
cmp %ax 'w' ; Go up
jme up
cmp %ax 'a' ; Go left
jme left
cmp %ax 's' ; Go down
jme down
cmp %ax 'd' ; Go right
jme right
cmp %ax 'x' ; Change the color to previous
jme prev_color
cmp %ax 'c' ; Change the color to next
jme next_color
jmp program_loop
square:
mov %si *x
mov %bx *y
mul %bx 340
add %si %bx ; Address to write
mov %ax *color
int $0C
inx %si
int $0C
add %si 340
int $0C
dex %si
int $0C
sub %si 340
int $11
ret
up:
dex y
dex y
call square
jmp program_loop
down:
inx y
inx y
call square
jmp program_loop
left:
dex x
dex x
call square
jmp program_loop
right:
inx x
inx x
call square
jmp program_loop
prev_color:
dex color
mov %bx *color
cmp %bx $FF
jmne program_loop
mov %si color
mov %ax $0F
storb %ax
jmp program_loop
next_color:
inx color
mov %bx *color
cmp %bx $10
jmne program_loop
mov %si color
mov %ax $00
storb %ax
jmp program_loop
term:
pop %x
ret
x: reserve 1 bytes ; 256x256 drawing square
y: reserve 1 bytes
color: reserve 1 bytes
|
xi816/gc16x | 4,572 | GovnPy/libgovn/font.s | res:
.underline: bytes $00 $00 $00 $00 $00 $00 $00 $FF
.font: bytes $00 $00 $00 $00 $00 $00 $00 $00 $07 $01 $57 $54 $77 $50 $50 $00 $07 $01 $57 $54 $27 $50 $50 $00 $07 $01 $53 $51 $27 $50 $50 $00 $07 $01 $73 $21 $27 $20 $20 $00 $07 $01 $73 $51 $57 $70 $20 $00 $07 $05 $57 $55 $35 $50 $50 $00 $03 $05 $13 $15 $13 $10 $70 $00 $03 $05 $73 $15 $73 $40 $70 $00 $05 $05 $77 $25 $25 $20 $20 $00 $01 $01 $71 $11 $37 $10 $10 $00 $05 $05 $75 $25 $22 $20 $20 $00 $07 $01 $73 $11 $31 $10 $10 $00 $07 $01 $71 $51 $77 $30 $50 $00 $07 $01 $77 $54 $57 $50 $70 $00 $07 $01 $77 $24 $27 $20 $70 $00 $03 $05 $15 $15 $13 $10 $70 $00 $03 $05 $25 $35 $23 $20 $70 $00 $03 $05 $75 $45 $73 $10 $70 $00 $03 $05 $75 $45 $63 $40 $70 $00 $03 $05 $55 $55 $73 $40 $40 $00 $07 $05 $55 $55 $35 $50 $50 $00 $07 $01 $57 $54 $77 $20 $20 $00 $07 $01 $33 $51 $37 $50 $30 $00 $07 $01 $71 $51 $57 $50 $50 $00 $07 $01 $53 $71 $57 $50 $50 $00 $3C $66 $66 $0C $18 $00 $18 $00 $07 $01 $73 $11 $17 $10 $70 $00 $07 $01 $73 $11 $71 $40 $70 $00 $07 $01 $75 $15 $77 $40 $70 $00 $07 $05 $77 $13 $75 $40 $70 $00 $05 $05 $75 $15 $77 $40 $70 $00 $00 $00 $00 $00 $00 $00 $00 $00 $08 $08 $08 $08 $00 $00 $08 $00 $24 $24 $24 $00 $00 $00 $00 $00 $24 $24 $7E $24 $7E $24 $24 $00 $08 $3C $0A $1C $28 $1E $08 $00 $00 $46 $26 $10 $08 $64 $62 $00 $0C $12 $12 $0C $52 $22 $5C $00 $10 $08 $04 $00 $00 $00 $00 $00 $10 $08 $04 $04 $04 $08 $10 $00 $04 $08 $10 $10 $10 $08 $04 $00 $08 $2A $1C $08 $1C $2A $08 $00 $00 $08 $08 $3E $08 $08 $00 $00 $00 $00 $00 $00 $00 $10 $10 $08 $00 $00 $00 $00 $3E $00 $00 $00 $00 $00 $00 $00 $00 $00 $08 $00 $40 $20 $10 $08 $04 $02 $01 $00 $1C $22 $32 $2A $26 $22 $1C $00 $08 $0C $0A $08 $08 $08 $3E $00 $1C $22 $20 $10 $0C $02 $3E $00 $1C $22 $20 $18 $20 $22 $1C $00 $10 $18 $14 $12 $3E $10 $10 $00 $3E $02 $1E $20 $20 $22 $1C $00 $38 $04 $02 $1E $22 $22 $1C $00 $3E $20 $10 $08 $04 $04 $04 $00 $1C $22 $22 $1C $22 $22 $1C $00 $1C $22 $22 $3C $20 $10 $0E $00 $00 $00 $08 $00 $00 $08 $00 $00 $00 $00 $08 $00 $00 $08 $08 $04 $10 $08 $04 $02 $04 $08 $10 $00 $00 $00 $3E $00 $3E $00 $00 $00 $04 $08 $10 $20 $10 $08 $04 $00 $3C $42 $20 $10 $10 $00 $10 $00 $3C $42 $52 $6A $32 $02 $3C $00 $18 $24 $42 $7E $42 $42 $42 $00 $3E $42 $42 $3E $42 $42 $3E $00 $3C $42 $02 $02 $02 $42 $3C $00 $1E $22 $42 $42 $42 $22 $1E $00 $7E $02 $02 $1E $02 $02 $7E $00 $7E $02 $02 $1E $02 $02 $02 $00 $3C $42 $02 $72 $42 $42 $3C $00 $42 $42 $42 $7E $42 $42 $42 $00 $1C $08 $08 $08 $08 $08 $1C $00 $20 $20 $20 $20 $20 $22 $1C $00 $42 $22 $12 $0E $12 $22 $42 $00 $02 $02 $02 $02 $02 $02 $7E $00 $42 $66 $5A $42 $42 $42 $42 $00 $42 $46 $4A $52 $62 $42 $42 $00 $3C $42 $42 $42 $42 $42 $3C $00 $3E $42 $42 $3E $02 $02 $02 $00 $3C $42 $42 $42 $52 $22 $5C $00 $3E $42 $42 $3E $12 $22 $42 $00 $3C $42 $02 $3C $40 $42 $3C $00 $3E $08 $08 $08 $08 $08 $08 $00 $42 $42 $42 $42 $42 $42 $3C $00 $42 $42 $42 $42 $42 $24 $18 $00 $42 $42 $42 $42 $5A $66 $42 $00 $42 $42 $24 $18 $24 $42 $42 $00 $22 $22 $22 $1C $08 $08 $08 $00 $3E $20 $10 $08 $04 $02 $3E $00 $1C $04 $04 $04 $04 $04 $1C $00 $01 $02 $04 $08 $10 $20 $40 $00 $1C $10 $10 $10 $10 $10 $1C $00 $08 $14 $22 $00 $00 $00 $00 $00 $00 $00 $00 $00 $00 $00 $00 $3E $04 $08 $10 $00 $00 $00 $00 $00 $00 $00 $1C $20 $3C $22 $3C $00 $02 $02 $1E $22 $22 $22 $1E $00 $00 $00 $1C $22 $02 $22 $1C $00 $20 $20 $3C $22 $22 $22 $3C $00 $00 $00 $1C $22 $3E $02 $1C $00 $30 $48 $08 $3E $08 $08 $08 $00 $00 $00 $3C $22 $22 $3C $20 $1C $02 $02 $1E $22 $22 $22 $22 $00 $08 $00 $0C $08 $08 $08 $1C $00 $20 $00 $30 $20 $20 $20 $24 $18 $02 $02 $22 $12 $0E $12 $22 $00 $0C $08 $08 $08 $08 $08 $1C $00 $00 $00 $16 $2A $2A $2A $2A $00 $00 $00 $1E $22 $22 $22 $22 $00 $00 $00 $1C $22 $22 $22 $1C $00 $00 $00 $1E $22 $22 $1E $02 $02 $00 $00 $3C $22 $22 $3C $20 $20 $00 $00 $3A $06 $02 $02 $02 $00 $00 $00 $3C $02 $1C $20 $1E $00 $04 $04 $1E $04 $04 $24 $18 $00 $00 $00 $22 $22 $22 $22 $1C $00 $00 $00 $22 $22 $22 $14 $08 $00 $00 $00 $22 $2A $2A $2A $14 $00 $00 $00 $22 $14 $08 $14 $22 $00 $00 $00 $22 $22 $22 $3C $20 $1C $00 $00 $3E $10 $08 $04 $3E $00 $18 $04 $04 $02 $04 $04 $18 $00 $08 $08 $08 $08 $08 $08 $08 $08 $0C $10 $10 $20 $10 $10 $0C $00 $04 $2A $10 $00 $00 $00 $00 $00 $03 $05 $75 $25 $23 $20 $20 $00 $72 $65 $74 $75 $72 $6E $20 $72 $65 $74 $75 $72 $6E $28 $29 $20 $7B $0A $20 $20 $72 $65 $74 $75 $72 $6E $20 $72 $65 $74 $75 $72 $6E $20 $3D $20 $30 $3B $0A $20 $20 $72 $65 $74 $75 $72 $6E $20 $72 $65 $74 $75 $72 $6E $20 $3D $20 $30 $3B $0A $20 $20 $72 $65 $74 $75 $72 $6E $20 $72 $65 $74 $75 $72 $6E $20 $3D $20 $2A $72 $65 $74 $75 $72 $6E $3B $0A $0A $20 $20 $72 $65 $74 $75 $72 $6E $20 $30 $3B $0A $7D $00
|
xi816/gc16x | 1,290 | GovnPy/libgovn/gdi9x.s | border: ; (x, y, w, h, pat)
pop %bp
pop %gi
pop %dx
pop %bx
pop %si
pop %ax
mul %si 340
add %si %ax
call border_asm
push 0
push %bp
ret
border_asm:
push %si
.bloop:
lda *%gi
cmp %ax $10
jme .fill
cmp %ax $20
jme .middle
cmp %ax $30
jme .eline
cmp %ax $F0
jme .end
int $C
inx %si
inx %gi
jmp .bloop
.fill:
inx %gi
lda *%gi
ldc %bx
dex %cx
.floop:
int $C
inx %si
loop .floop
inx %gi
jmp .bloop
.eline:
pop %si
add %si 340
push %si
inx %gi
jmp .bloop
.middle:
inx %gi
push %gi
ldc %dx
dex %cx
.mloop:
lda *%gi
cmp %ax $10
jme .mfill
cmp %ax $F0
jme .mend
int $C
inx %si
inx %gi
jmp .mloop
.mend:
lda %gi
pop %gi
pop %si
add %si 340
push %si
push %gi
loop .mloop
pop %gi
ldg %ax
inx %gi
jmp .bloop
.mfill:
add %si %bx
inx %gi
jmp .mloop
.end:
pop %ax
ret
taskbar:
pop %bp
lds 58480
lda 7
ldc 340
.floop:
int $C
inx %si
loop .floop
lda 15
ldc 340
.sloop:
int $C
inx %si
loop .sloop
lda 7
ldc 5440
.tloop:
int $C
inx %si
loop .tloop
push %bp
ret
|
xi816/gc16x | 2,068 | GovnPy/libgovn/std.s | call main
lds endmsg
push %si
call puts
pop %ax
; exit code left on stack
int $0
endmsg: bytes "Destroying GovnPy runtime data...$^@"
; GovnPy Standard Library
puti:
pop %bp
pop %ax
cmp %ax 0
jme .zer
ldb 10000
ldg 0
.loop:
ldc %ax
div %ax %bx
div %ax 10
cmp %dx %gi
jme .next
add %dx $30
ldg %dx ; so that cmp fails
push %dx
int 2
.next:
lda %cx
cmp %bx 1
jme .end
div %bx 10
jmp .loop
.zer:
push $30
int 2
.end:
push 0
push %bp
ret
puts:
pop %bp
pop %si
.loop:
cmp *%si 0
jme .end
push *%si
int 2
inx %si
jmp .loop
.end:
push %si
push %bp
ret
gets:
pop %bp
pop %si
ldg %si
.loop:
int 1
pop %ax
cmp %ax $1B
jme .esc
cmp %ax 8
jme .bs
cmp %ax 127
jme .bs
push %ax
int 2
cmp %ax 10
jme .end
storb %ax
inx %si
jmp .loop
.esc:
lda 94
push %ax
int 2
storb %ax
inx %si
lda '['
push %ax
int 2
storb %ax
inx %si
jmp .loop
.bs:
cmp %si %gi
jme .loop
lda 0
storb %ax
dex %si
; Check if we're overwriting a non-first byte
lda *%si
div %ax 64
cmp %ax 2
jme .bs
push 8
int $2
push 32
int $2
push 8
int $2
jmp .loop
.end:
lda 0
storb %ax
push %si
push %bp
ret
exit:
pop %bp
int $0
hlt
memcmp:
pop %bp
pop %si
pop %gi
pop %cx
dex %cx
.loop:
lda *%si
ldb *%gi
cmp %ax %bx
jmne .fail
inx %si
inx %gi
loop .loop
push 1
push %bp
ret
.fail:
push 0
push %bp
ret
scmp:
pop %bp
pop %si
pop %gi
.loop:
lda *%si
ldb *%gi
cmp %ax %bx
jmne .fail
cmp %bx 0
jme .ok
inx %si
inx %gi
jmp .loop
.fail:
push 0
push %bp
ret
.ok:
push 1
push %bp
ret
s2i:
pop %bp
pop %si
lda 0
.loop:
ldb *%si
cmp %bx 0
jme .end
sub %bx $30
mul %ax 10
add %ax %bx
inx %si
jmp .loop
.end:
push %ax
push %bp
ret
putc:
pop %bp
int 2
push 0
push %bp
ret
getch:
pop %bp
int 1
push %bp
ret
msleep:
pop %bp
pop %dx
int $22
push 0
push %bp
ret
rand:
pop %bp
int $21
push %dx
push %bp
ret
|
xi816/gc16x | 2,015 | GovnPy/libgovn/gui.s | vputs: ; (x,y,c,t)
pop %bp
pop %gi
pop %ax
pop %dx
pop %si
mul %dx 340
add %si %dx
call vputs-
push %dx
push %bp
ret
cls: ; (c)
pop %bp
pop %ax
call cls-
push 0
push %bp
ret
box: ; (x,y,w,h,c)
pop %bp
pop %ax
pop %dx
pop %bx
pop %cx
pop %si
mul %cx 340
add %si %cx
call box-
push 0
push %bp
ret
show:
pop %bp
int $11
push 0
push %bp
ret
spr: ; (x, y, c, data)
pop %bp
pop %gi
pop %ax
pop %si
pop %dx
mul %si 340
add %si %dx
call spr-
push 0
push %bp
ret
vputs-: ; G: char
push %si
.line:
push %gi
lodgb
cmp %gi 0
jme .end
cmp %gi 10
jme .ln
cmp %gi 27
jme .undr
cmp %gi $D0
jme .gu8_d0
cmp %gi $D1
jme .gu8_d1
sub %gi $20
.pchar:
mul %gi 9
ldd res.font
add %gi %dx
call spr-
ldd *%gi
sub %si 2720
;add %si %dx
add %si 6
pop %gi
inx %gi
jmp .line
.gu8_d0:
pop %gi
inx %gi
push %gi
lodgb
sub %gi $20
jmp .pchar
.gu8_d1:
pop %gi
inx %gi
push %gi
lodgb
add %gi $20 ; $40 - $20
jmp .pchar
.ln:
pop %gi
pop %si
add %si 2720
inx %gi
jmp vputs-
.undr:
ldg res.underline
call spr-
sub %si 2720
pop %gi
inx %gi
jmp .line
.end:
pop %gi
ldd %si
pop %si
ret
; Gravno Display Interface 16
cls-: ; A: color
lds 0
ldc 64599
.loop:
int $C
inx %si
loop .loop
ret
box-: ; A: color, B: width, D: height, S: start
ldc %bx
dex %cx
.pix:
int $C
inx %si
loop .pix
sub %si %bx
add %si 340
dex %dx
cmp %dx 0
jmne box-
ret
spr-: ; A: color, G: sprite data
ldb 8
.line:
push %gi
lodgb
ldc 7
.pix:
div %gi 2
cmp %dx 0
jme .pix_next
int $C
;inx %si
;int $C
;dex %si
.pix_next:
inx %si
loop .pix
pop %gi
inx %gi
add %si 332
dex %bx
cmp %bx 0
jmne .line
ret
|
xi816/gc16x | 2,359 | GovnPy/progs/compiled/source.s | ; libgovn/std.s
call main
lds endmsg
push %si
call puts
pop %ax
; exit code left on stack
int $0
endmsg: bytes "Destroying GovnPy runtime data...$^@"
; GovnPy Standard Library
puti:
pop %bp
pop %ax
cmp %ax 0
jme .zer
ldb 10000
ldg 0
.loop:
ldc %ax
div %ax %bx
div %ax 10
cmp %dx %gi
jme .next
add %dx $30
ldg %dx ; so that cmp fails
push %dx
int 2
.next:
lda %cx
cmp %bx 1
jme .end
div %bx 10
jmp .loop
.zer:
push $30
int 2
.end:
push 0
push %bp
ret
puts:
pop %bp
pop %si
.loop:
cmp *%si 0
jme .end
push *%si
int 2
inx %si
jmp .loop
.end:
push %si
push %bp
ret
gets:
pop %bp
pop %si
ldg %si
.loop:
int 1
pop %ax
cmp %ax $1B
jme .esc
cmp %ax 8
jme .bs
cmp %ax 127
jme .bs
push %ax
int 2
cmp %ax 10
jme .end
storb %ax
inx %si
jmp .loop
.esc:
lda 94
push %ax
int 2
storb %ax
inx %si
lda '['
push %ax
int 2
storb %ax
inx %si
jmp .loop
.bs:
cmp %si %gi
jme .loop
lda 0
storb %ax
dex %si
; Check if we're overwriting a non-first byte
lda *%si
div %ax 64
cmp %ax 2
jme .bs
push 8
int $2
push 32
int $2
push 8
int $2
jmp .loop
.end:
lda 0
storb %ax
push %si
push %bp
ret
exit:
pop %bp
int $0
hlt
memcmp:
pop %bp
pop %si
pop %gi
pop %cx
dex %cx
.loop:
lda *%si
ldb *%gi
cmp %ax %bx
jmne .fail
inx %si
inx %gi
loop .loop
push 1
push %bp
ret
.fail:
push 0
push %bp
ret
scmp:
pop %bp
pop %si
pop %gi
.loop:
lda *%si
ldb *%gi
cmp %ax %bx
jmne .fail
cmp %bx 0
jme .ok
inx %si
inx %gi
jmp .loop
.fail:
push 0
push %bp
ret
.ok:
push 1
push %bp
ret
s2i:
pop %bp
pop %si
lda 0
.loop:
ldb *%si
cmp %bx 0
jme .end
sub %bx $30
mul %ax 10
add %ax %bx
inx %si
jmp .loop
.end:
push %ax
push %bp
ret
putc:
pop %bp
int 2
push 0
push %bp
ret
getch:
pop %bp
int 1
push %bp
ret
msleep:
pop %bp
pop %dx
int $22
push 0
push %bp
ret
rand:
pop %bp
int $21
push %dx
push %bp
ret
main:
mov %bp 0
add %sp %bp
mov %bp %sp
inx %bp
push %bp
mov %ax str0
push %ax
call puts
pop %ax
pop %bp
push 0
.ret:
pop %dx
lds 2
add %sp %si
lds 0
add %si %bp
; lodsw
bytes $8A
push %dx
push %ax
ret
str0: bytes "Hello, World!^@"
|
xia-chu/webrtc_apm | 7,686 | apm/src/main/jni/webrtc/webrtc/common_audio/signal_processing/filter_ar_fast_q12_armv7.S | @
@ Copyright (c) 2012 The WebRTC project authors. All Rights Reserved.
@
@ Use of this source code is governed by a BSD-style license
@ that can be found in the LICENSE file in the root of the source
@ tree. An additional intellectual property rights grant can be found
@ in the file PATENTS. All contributing project authors may
@ be found in the AUTHORS file in the root of the source tree.
@
@ This file contains the function WebRtcSpl_FilterARFastQ12(), optimized for
@ ARMv7 platform. The description header can be found in
@ signal_processing_library.h
@
@ Output is bit-exact with the generic C code as in filter_ar_fast_q12.c, and
@ the reference C code at end of this file.
@ Assumptions:
@ (1) data_length > 0
@ (2) coefficients_length > 1
@ Register usage:
@
@ r0: &data_in[i]
@ r1: &data_out[i], for result ouput
@ r2: &coefficients[0]
@ r3: coefficients_length
@ r4: Iteration counter for the outer loop.
@ r5: data_out[j] as multiplication inputs
@ r6: Calculated value for output data_out[]; interation counter for inner loop
@ r7: Partial sum of a filtering multiplication results
@ r8: Partial sum of a filtering multiplication results
@ r9: &data_out[], for filtering input; data_in[i]
@ r10: coefficients[j]
@ r11: Scratch
@ r12: &coefficients[j]
#include "webrtc/system_wrappers/interface/asm_defines.h"
GLOBAL_FUNCTION WebRtcSpl_FilterARFastQ12
.align 2
DEFINE_FUNCTION WebRtcSpl_FilterARFastQ12
push {r4-r11}
ldrsh r12, [sp, #32] @ data_length
subs r4, r12, #1
beq ODD_LENGTH @ jump if data_length == 1
LOOP_LENGTH:
add r12, r2, r3, lsl #1
sub r12, #4 @ &coefficients[coefficients_length - 2]
sub r9, r1, r3, lsl #1
add r9, #2 @ &data_out[i - coefficients_length + 1]
ldr r5, [r9], #4 @ data_out[i - coefficients_length + {1,2}]
mov r7, #0 @ sum1
mov r8, #0 @ sum2
subs r6, r3, #3 @ Iteration counter for inner loop.
beq ODD_A_LENGTH @ branch if coefficients_length == 3
blt POST_LOOP_A_LENGTH @ branch if coefficients_length == 2
LOOP_A_LENGTH:
ldr r10, [r12], #-4 @ coefficients[j - 1], coefficients[j]
subs r6, #2
smlatt r8, r10, r5, r8 @ sum2 += coefficients[j] * data_out[i - j + 1];
smlatb r7, r10, r5, r7 @ sum1 += coefficients[j] * data_out[i - j];
smlabt r7, r10, r5, r7 @ coefficients[j - 1] * data_out[i - j + 1];
ldr r5, [r9], #4 @ data_out[i - j + 2], data_out[i - j + 3]
smlabb r8, r10, r5, r8 @ coefficients[j - 1] * data_out[i - j + 2];
bgt LOOP_A_LENGTH
blt POST_LOOP_A_LENGTH
ODD_A_LENGTH:
ldrsh r10, [r12, #2] @ Filter coefficients coefficients[2]
sub r12, #2 @ &coefficients[0]
smlabb r7, r10, r5, r7 @ sum1 += coefficients[2] * data_out[i - 2];
smlabt r8, r10, r5, r8 @ sum2 += coefficients[2] * data_out[i - 1];
ldr r5, [r9, #-2] @ data_out[i - 1], data_out[i]
POST_LOOP_A_LENGTH:
ldr r10, [r12] @ coefficients[0], coefficients[1]
smlatb r7, r10, r5, r7 @ sum1 += coefficients[1] * data_out[i - 1];
ldr r9, [r0], #4 @ data_in[i], data_in[i + 1]
smulbb r6, r10, r9 @ output1 = coefficients[0] * data_in[i];
sub r6, r7 @ output1 -= sum1;
sbfx r11, r6, #12, #16
ssat r7, #16, r6, asr #12
cmp r7, r11
addeq r6, r6, #2048
ssat r6, #16, r6, asr #12
strh r6, [r1], #2 @ Store data_out[i]
smlatb r8, r10, r6, r8 @ sum2 += coefficients[1] * data_out[i];
smulbt r6, r10, r9 @ output2 = coefficients[0] * data_in[i + 1];
sub r6, r8 @ output1 -= sum1;
sbfx r11, r6, #12, #16
ssat r7, #16, r6, asr #12
cmp r7, r11
addeq r6, r6, #2048
ssat r6, #16, r6, asr #12
strh r6, [r1], #2 @ Store data_out[i + 1]
subs r4, #2
bgt LOOP_LENGTH
blt END @ For even data_length, it's done. Jump to END.
@ Process i = data_length -1, for the case of an odd length.
ODD_LENGTH:
add r12, r2, r3, lsl #1
sub r12, #4 @ &coefficients[coefficients_length - 2]
sub r9, r1, r3, lsl #1
add r9, #2 @ &data_out[i - coefficients_length + 1]
mov r7, #0 @ sum1
mov r8, #0 @ sum1
subs r6, r3, #2 @ inner loop counter
beq EVEN_A_LENGTH @ branch if coefficients_length == 2
LOOP2_A_LENGTH:
ldr r10, [r12], #-4 @ coefficients[j - 1], coefficients[j]
ldr r5, [r9], #4 @ data_out[i - j], data_out[i - j + 1]
subs r6, #2
smlatb r7, r10, r5, r7 @ sum1 += coefficients[j] * data_out[i - j];
smlabt r8, r10, r5, r8 @ coefficients[j - 1] * data_out[i - j + 1];
bgt LOOP2_A_LENGTH
addlt r12, #2
blt POST_LOOP2_A_LENGTH
EVEN_A_LENGTH:
ldrsh r10, [r12, #2] @ Filter coefficients coefficients[1]
ldrsh r5, [r9] @ data_out[i - 1]
smlabb r7, r10, r5, r7 @ sum1 += coefficients[1] * data_out[i - 1];
POST_LOOP2_A_LENGTH:
ldrsh r10, [r12] @ Filter coefficients coefficients[0]
ldrsh r9, [r0] @ data_in[i]
smulbb r6, r10, r9 @ output1 = coefficients[0] * data_in[i];
sub r6, r7 @ output1 -= sum1;
sub r6, r8 @ output1 -= sum1;
sbfx r8, r6, #12, #16
ssat r7, #16, r6, asr #12
cmp r7, r8
addeq r6, r6, #2048
ssat r6, #16, r6, asr #12
strh r6, [r1] @ Store the data_out[i]
END:
pop {r4-r11}
bx lr
@Reference C code:
@
@void WebRtcSpl_FilterARFastQ12(int16_t* data_in,
@ int16_t* data_out,
@ int16_t* __restrict coefficients,
@ size_t coefficients_length,
@ size_t data_length) {
@ size_t i = 0;
@ size_t j = 0;
@
@ assert(data_length > 0);
@ assert(coefficients_length > 1);
@
@ for (i = 0; i < data_length - 1; i += 2) {
@ int32_t output1 = 0;
@ int32_t sum1 = 0;
@ int32_t output2 = 0;
@ int32_t sum2 = 0;
@
@ for (j = coefficients_length - 1; j > 2; j -= 2) {
@ sum1 += coefficients[j] * data_out[i - j];
@ sum1 += coefficients[j - 1] * data_out[i - j + 1];
@ sum2 += coefficients[j] * data_out[i - j + 1];
@ sum2 += coefficients[j - 1] * data_out[i - j + 2];
@ }
@
@ if (j == 2) {
@ sum1 += coefficients[2] * data_out[i - 2];
@ sum2 += coefficients[2] * data_out[i - 1];
@ }
@
@ sum1 += coefficients[1] * data_out[i - 1];
@ output1 = coefficients[0] * data_in[i];
@ output1 -= sum1;
@ // Saturate and store the output.
@ output1 = WEBRTC_SPL_SAT(134215679, output1, -134217728);
@ data_out[i] = (int16_t)((output1 + 2048) >> 12);
@
@ sum2 += coefficients[1] * data_out[i];
@ output2 = coefficients[0] * data_in[i + 1];
@ output2 -= sum2;
@ // Saturate and store the output.
@ output2 = WEBRTC_SPL_SAT(134215679, output2, -134217728);
@ data_out[i + 1] = (int16_t)((output2 + 2048) >> 12);
@ }
@
@ if (i == data_length - 1) {
@ int32_t output1 = 0;
@ int32_t sum1 = 0;
@
@ for (j = coefficients_length - 1; j > 1; j -= 2) {
@ sum1 += coefficients[j] * data_out[i - j];
@ sum1 += coefficients[j - 1] * data_out[i - j + 1];
@ }
@
@ if (j == 1) {
@ sum1 += coefficients[1] * data_out[i - 1];
@ }
@
@ output1 = coefficients[0] * data_in[i];
@ output1 -= sum1;
@ // Saturate and store the output.
@ output1 = WEBRTC_SPL_SAT(134215679, output1, -134217728);
@ data_out[i] = (int16_t)((output1 + 2048) >> 12);
@ }
@}
|
xia-chu/webrtc_apm | 2,882 | apm/src/main/jni/webrtc/webrtc/common_audio/signal_processing/spl_sqrt_floor_arm.S | @
@ Written by Wilco Dijkstra, 1996. The following email exchange establishes the
@ license.
@
@ From: Wilco Dijkstra <Wilco.Dijkstra@ntlworld.com>
@ Date: Fri, Jun 24, 2011 at 3:20 AM
@ Subject: Re: sqrt routine
@ To: Kevin Ma <kma@google.com>
@ Hi Kevin,
@ Thanks for asking. Those routines are public domain (originally posted to
@ comp.sys.arm a long time ago), so you can use them freely for any purpose.
@ Cheers,
@ Wilco
@
@ ----- Original Message -----
@ From: "Kevin Ma" <kma@google.com>
@ To: <Wilco.Dijkstra@ntlworld.com>
@ Sent: Thursday, June 23, 2011 11:44 PM
@ Subject: Fwd: sqrt routine
@ Hi Wilco,
@ I saw your sqrt routine from several web sites, including
@ http://www.finesse.demon.co.uk/steven/sqrt.html.
@ Just wonder if there's any copyright information with your Successive
@ approximation routines, or if I can freely use it for any purpose.
@ Thanks.
@ Kevin
@ Minor modifications in code style for WebRTC, 2012.
@ Output is bit-exact with the reference C code in spl_sqrt_floor.c.
@ Input : r0 32 bit unsigned integer
@ Output: r0 = INT (SQRT (r0)), precision is 16 bits
@ Registers touched: r1, r2
#include "webrtc/system_wrappers/interface/asm_defines.h"
GLOBAL_FUNCTION WebRtcSpl_SqrtFloor
.align 2
DEFINE_FUNCTION WebRtcSpl_SqrtFloor
mov r1, #3 << 30
mov r2, #1 << 30
@ unroll for i = 0 .. 15
cmp r0, r2, ror #2 * 0
subhs r0, r0, r2, ror #2 * 0
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 1
subhs r0, r0, r2, ror #2 * 1
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 2
subhs r0, r0, r2, ror #2 * 2
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 3
subhs r0, r0, r2, ror #2 * 3
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 4
subhs r0, r0, r2, ror #2 * 4
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 5
subhs r0, r0, r2, ror #2 * 5
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 6
subhs r0, r0, r2, ror #2 * 6
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 7
subhs r0, r0, r2, ror #2 * 7
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 8
subhs r0, r0, r2, ror #2 * 8
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 9
subhs r0, r0, r2, ror #2 * 9
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 10
subhs r0, r0, r2, ror #2 * 10
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 11
subhs r0, r0, r2, ror #2 * 11
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 12
subhs r0, r0, r2, ror #2 * 12
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 13
subhs r0, r0, r2, ror #2 * 13
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 14
subhs r0, r0, r2, ror #2 * 14
adc r2, r1, r2, lsl #1
cmp r0, r2, ror #2 * 15
subhs r0, r0, r2, ror #2 * 15
adc r2, r1, r2, lsl #1
bic r0, r2, #3 << 30 @ for rounding add: cmp r0, r2 adc r2, #1
bx lr
|
xia-chu/webrtc_apm | 4,623 | apm/src/main/jni/webrtc/webrtc/common_audio/signal_processing/complex_bit_reverse_arm.S | @
@ Copyright (c) 2012 The WebRTC project authors. All Rights Reserved.
@
@ Use of this source code is governed by a BSD-style license
@ that can be found in the LICENSE file in the root of the source
@ tree. An additional intellectual property rights grant can be found
@ in the file PATENTS. All contributing project authors may
@ be found in the AUTHORS file in the root of the source tree.
@
@ This file contains the function WebRtcSpl_ComplexBitReverse(), optimized
@ for ARMv5 platforms.
@ Reference C code is in file complex_bit_reverse.c. Bit-exact.
#include "webrtc/system_wrappers/interface/asm_defines.h"
GLOBAL_FUNCTION WebRtcSpl_ComplexBitReverse
.align 2
DEFINE_FUNCTION WebRtcSpl_ComplexBitReverse
push {r4-r7}
cmp r1, #7
adr r3, index_7 @ Table pointer.
mov r4, #112 @ Number of interations.
beq PRE_LOOP_STAGES_7_OR_8
cmp r1, #8
adr r3, index_8 @ Table pointer.
mov r4, #240 @ Number of interations.
beq PRE_LOOP_STAGES_7_OR_8
mov r3, #1 @ Initialize m.
mov r1, r3, asl r1 @ n = 1 << stages;
subs r6, r1, #1 @ nn = n - 1;
ble END
mov r5, r0 @ &complex_data
mov r4, #0 @ ml
LOOP_GENERIC:
rsb r12, r4, r6 @ l > nn - mr
mov r2, r1 @ n
LOOP_SHIFT:
asr r2, #1 @ l >>= 1;
cmp r2, r12
bgt LOOP_SHIFT
sub r12, r2, #1
and r4, r12, r4
add r4, r2 @ mr = (mr & (l - 1)) + l;
cmp r4, r3 @ mr <= m ?
ble UPDATE_REGISTERS
mov r12, r4, asl #2
ldr r7, [r5, #4] @ complex_data[2 * m, 2 * m + 1].
@ Offset 4 due to m incrementing from 1.
ldr r2, [r0, r12] @ complex_data[2 * mr, 2 * mr + 1].
str r7, [r0, r12]
str r2, [r5, #4]
UPDATE_REGISTERS:
add r3, r3, #1
add r5, #4
cmp r3, r1
bne LOOP_GENERIC
b END
PRE_LOOP_STAGES_7_OR_8:
add r4, r3, r4, asl #1
LOOP_STAGES_7_OR_8:
ldrsh r2, [r3], #2 @ index[m]
ldrsh r5, [r3], #2 @ index[m + 1]
ldr r1, [r0, r2] @ complex_data[index[m], index[m] + 1]
ldr r12, [r0, r5] @ complex_data[index[m + 1], index[m + 1] + 1]
cmp r3, r4
str r1, [r0, r5]
str r12, [r0, r2]
bne LOOP_STAGES_7_OR_8
END:
pop {r4-r7}
bx lr
@ The index tables. Note the values are doubles of the actual indexes for 16-bit
@ elements, different from the generic C code. It actually provides byte offsets
@ for the indexes.
.align 2
index_7: @ Indexes for stages == 7.
.short 4, 256, 8, 128, 12, 384, 16, 64, 20, 320, 24, 192, 28, 448, 36, 288
.short 40, 160, 44, 416, 48, 96, 52, 352, 56, 224, 60, 480, 68, 272, 72, 144
.short 76, 400, 84, 336, 88, 208, 92, 464, 100, 304, 104, 176, 108, 432, 116
.short 368, 120, 240, 124, 496, 132, 264, 140, 392, 148, 328, 152, 200, 156
.short 456, 164, 296, 172, 424, 180, 360, 184, 232, 188, 488, 196, 280, 204
.short 408, 212, 344, 220, 472, 228, 312, 236, 440, 244, 376, 252, 504, 268
.short 388, 276, 324, 284, 452, 300, 420, 308, 356, 316, 484, 332, 404, 348
.short 468, 364, 436, 380, 500, 412, 460, 444, 492
index_8: @ Indexes for stages == 8.
.short 4, 512, 8, 256, 12, 768, 16, 128, 20, 640, 24, 384, 28, 896, 32, 64
.short 36, 576, 40, 320, 44, 832, 48, 192, 52, 704, 56, 448, 60, 960, 68, 544
.short 72, 288, 76, 800, 80, 160, 84, 672, 88, 416, 92, 928, 100, 608, 104
.short 352, 108, 864, 112, 224, 116, 736, 120, 480, 124, 992, 132, 528, 136
.short 272, 140, 784, 148, 656, 152, 400, 156, 912, 164, 592, 168, 336, 172
.short 848, 176, 208, 180, 720, 184, 464, 188, 976, 196, 560, 200, 304, 204
.short 816, 212, 688, 216, 432, 220, 944, 228, 624, 232, 368, 236, 880, 244
.short 752, 248, 496, 252, 1008, 260, 520, 268, 776, 276, 648, 280, 392, 284
.short 904, 292, 584, 296, 328, 300, 840, 308, 712, 312, 456, 316, 968, 324
.short 552, 332, 808, 340, 680, 344, 424, 348, 936, 356, 616, 364, 872, 372
.short 744, 376, 488, 380, 1000, 388, 536, 396, 792, 404, 664, 412, 920, 420
.short 600, 428, 856, 436, 728, 440, 472, 444, 984, 452, 568, 460, 824, 468
.short 696, 476, 952, 484, 632, 492, 888, 500, 760, 508, 1016, 524, 772, 532
.short 644, 540, 900, 548, 580, 556, 836, 564, 708, 572, 964, 588, 804, 596
.short 676, 604, 932, 620, 868, 628, 740, 636, 996, 652, 788, 668, 916, 684
.short 852, 692, 724, 700, 980, 716, 820, 732, 948, 748, 884, 764, 1012, 796
.short 908, 812, 844, 828, 972, 860, 940, 892, 1004, 956, 988
|
xiangxud/webrtc_H265player | 27,922 | test/prod_decoder/codec/3rdparty/de265/libde265/arm/hevcdsp_qpel_neon.S | /*
* Copyright (c) 2014 - 2015 Seppo Tomperi <seppo.tomperi@vtt.fi>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* This is commit 63ca0fe8288dbd300c9bb814cb671e5d889f691c from
* https://github.com/FFmpeg/FFmpeg/blob/master/libavcodec/arm/hevcdsp_qpel_neon.S
*/
#include "asm.S"
#include "neon.S"
#define MAX_PB_SIZE #64
.macro regshuffle_d8
vmov d16, d17
vmov d17, d18
vmov d18, d19
vmov d19, d20
vmov d20, d21
vmov d21, d22
vmov d22, d23
.endm
.macro regshuffle_q8
vmov q0, q1
vmov q1, q2
vmov q2, q3
vmov q3, q4
vmov q4, q5
vmov q5, q6
vmov q6, q7
.endm
.macro vextin8
pld [r2]
vld1.8 {q11}, [r2], r3
vext.8 d16, d22, d23, #1
vext.8 d17, d22, d23, #2
vext.8 d18, d22, d23, #3
vext.8 d19, d22, d23, #4
vext.8 d20, d22, d23, #5
vext.8 d21, d22, d23, #6
vext.8 d22, d22, d23, #7
.endm
.macro loadin8
pld [r2]
vld1.8 {d16}, [r2], r3
pld [r2]
vld1.8 {d17}, [r2], r3
pld [r2]
vld1.8 {d18}, [r2], r3
pld [r2]
vld1.8 {d19}, [r2], r3
pld [r2]
vld1.8 {d20}, [r2], r3
pld [r2]
vld1.8 {d21}, [r2], r3
pld [r2]
vld1.8 {d22}, [r2], r3
pld [r2]
vld1.8 {d23}, [r2], r3
.endm
.macro qpel_filter_1_32b
vmov.i16 d16, #58
vmov.i16 d17, #10
vmull.s16 q9, d6, d16 // 58 * d0
vmull.s16 q10, d7, d16 // 58 * d1
vmov.i16 d16, #17
vmull.s16 q11, d4, d17 // 10 * c0
vmull.s16 q12, d5, d17 // 10 * c1
vmov.i16 d17, #5
vmull.s16 q13, d8, d16 // 17 * e0
vmull.s16 q14, d9, d16 // 17 * e1
vmull.s16 q15, d10, d17 // 5 * f0
vmull.s16 q8, d11, d17 // 5 * f1
vsub.s32 q9, q11 // 58 * d0 - 10 * c0
vsub.s32 q10, q12 // 58 * d1 - 10 * c1
vshll.s16 q11, d2, #2 // 4 * b0
vshll.s16 q12, d3, #2 // 4 * b1
vadd.s32 q9, q13 // 58 * d0 - 10 * c0 + 17 * e0
vadd.s32 q10, q14 // 58 * d1 - 10 * c1 + 17 * e1
vsubl.s16 q13, d12, d0 // g0 - a0
vsubl.s16 q14, d13, d1 // g1 - a1
vadd.s32 q9, q11 // 58 * d0 - 10 * c0 + 17 * e0 + 4 * b0
vadd.s32 q10, q12 // 58 * d1 - 10 * c1 + 17 * e1 + 4 * b1
vsub.s32 q13, q15 // g0 - a0 - 5 * f0
vsub.s32 q14, q8 // g1 - a1 - 5 * f1
vadd.s32 q9, q13 // 58 * d0 - 10 * c0 + 17 * e0 + 4 * b0 + g0 - a0 - 5 * f0
vadd.s32 q10, q14 // 58 * d1 - 10 * c1 + 17 * e1 + 4 * b1 + g1 - a1 - 5 * f1
vqshrn.s32 d16, q9, #6
vqshrn.s32 d17, q10, #6
.endm
// input q0 - q7
// output q8
.macro qpel_filter_2_32b
vmov.i32 q8, #11
vaddl.s16 q9, d6, d8 // d0 + e0
vaddl.s16 q10, d7, d9 // d1 + e1
vaddl.s16 q11, d4, d10 // c0 + f0
vaddl.s16 q12, d5, d11 // c1 + f1
vmul.s32 q11, q8 // 11 * (c0 + f0)
vmul.s32 q12, q8 // 11 * (c1 + f1)
vmov.i32 q8, #40
vaddl.s16 q15, d2, d12 // b0 + g0
vmul.s32 q9, q8 // 40 * (d0 + e0)
vmul.s32 q10, q8 // 40 * (d1 + e1)
vaddl.s16 q8, d3, d13 // b1 + g1
vaddl.s16 q13, d0, d14 // a0 + h0
vaddl.s16 q14, d1, d15 // a1 + h1
vshl.s32 q15, #2 // 4*(b0+g0)
vshl.s32 q8, #2 // 4*(b1+g1)
vadd.s32 q11, q13 // 11 * (c0 + f0) + a0 + h0
vadd.s32 q12, q14 // 11 * (c1 + f1) + a1 + h1
vadd.s32 q9, q15 // 40 * (d0 + e0) + 4*(b0+g0)
vadd.s32 q10, q8 // 40 * (d1 + e1) + 4*(b1+g1)
vsub.s32 q9, q11 // 40 * (d0 + e0) + 4*(b0+g0) - (11 * (c0 + f0) + a0 + h0)
vsub.s32 q10, q12 // 40 * (d1 + e1) + 4*(b1+g1) - (11 * (c1 + f1) + a1 + h1)
vqshrn.s32 d16, q9, #6
vqshrn.s32 d17, q10, #6
.endm
.macro qpel_filter_3_32b
vmov.i16 d16, #58
vmov.i16 d17, #10
vmull.s16 q9, d8, d16 // 58 * d0
vmull.s16 q10, d9, d16 // 58 * d1
vmov.i16 d16, #17
vmull.s16 q11, d10, d17 // 10 * c0
vmull.s16 q12, d11, d17 // 10 * c1
vmov.i16 d17, #5
vmull.s16 q13, d6, d16 // 17 * e0
vmull.s16 q14, d7, d16 // 17 * e1
vmull.s16 q15, d4, d17 // 5 * f0
vmull.s16 q8, d5, d17 // 5 * f1
vsub.s32 q9, q11 // 58 * d0 - 10 * c0
vsub.s32 q10, q12 // 58 * d1 - 10 * c1
vshll.s16 q11, d12, #2 // 4 * b0
vshll.s16 q12, d13, #2 // 4 * b1
vadd.s32 q9, q13 // 58 * d0 - 10 * c0 + 17 * e0
vadd.s32 q10, q14 // 58 * d1 - 10 * c1 + 17 * e1
vsubl.s16 q13, d2, d14 // g0 - a0
vsubl.s16 q14, d3, d15 // g1 - a1
vadd.s32 q9, q11 // 58 * d0 - 10 * c0 + 17 * e0 + 4 * b0
vadd.s32 q10, q12 // 58 * d1 - 10 * c1 + 17 * e1 + 4 * b1
vsub.s32 q13, q15 // g0 - a0 - 5 * f0
vsub.s32 q14, q8 // g1 - a1 - 5 * f1
vadd.s32 q9, q13 // 58 * d0 - 10 * c0 + 17 * e0 + 4 * b0 + g0 - a0 - 5 * f0
vadd.s32 q10, q14 // 58 * d1 - 10 * c1 + 17 * e1 + 4 * b1 + g1 - a1 - 5 * f1
vqshrn.s32 d16, q9, #6
vqshrn.s32 d17, q10, #6
.endm
.macro qpel_filter_1 out=q7
vmov.u8 d24, #58
vmov.u8 d25, #10
vshll.u8 q13, d20, #4 // 16*e
vshll.u8 q14, d21, #2 // 4*f
vmull.u8 \out, d19, d24 // 58*d
vaddw.u8 q13, q13, d20 // 17*e
vmull.u8 q15, d18, d25 // 10*c
vaddw.u8 q14, q14, d21 // 5*f
vsubl.u8 q12, d22, d16 // g - a
vadd.u16 \out, q13 // 58d + 17e
vshll.u8 q13, d17, #2 // 4*b
vadd.u16 q15, q14 // 10*c + 5*f
vadd.s16 q13, q12 // - a + 4*b + g
vsub.s16 \out, q15 // -10*c + 58*d + 17*e -5*f
vadd.s16 \out, q13 // -a + 4*b -10*c + 58*d + 17*e -5*f
.endm
.macro qpel_filter_2 out=q7
vmov.i16 q12, #10
vmov.i16 q14, #11
vaddl.u8 q13, d19, d20 // d + e
vaddl.u8 q15, d18, d21 // c + f
vmul.u16 q13, q12 // 10 * (d+e)
vmul.u16 q15, q14 // 11 * ( c + f)
vaddl.u8 \out, d17, d22 // b + g
vaddl.u8 q12, d16, d23 // a + h
vadd.u16 \out, q13 // b + 10 * (d + e) + g
vadd.s16 q12, q15
vshl.u16 \out, #2 // 4 * (b + 10 * (d + e) + g)
vsub.s16 \out, q12
.endm
.macro qpel_filter_3 out=q7
vmov.u8 d24, #58
vmov.u8 d25, #10
vshll.u8 q13, d19, #4 // 16*e
vshll.u8 q14, d18, #2 // 4*f
vmull.u8 \out, d20, d24 // 58*d
vaddw.u8 q13, q13, d19 // 17*e
vmull.u8 q15, d21, d25 // 10*c
vaddw.u8 q14, q14, d18 // 5*f
vsubl.u8 q12, d17, d23 // g - a
vadd.u16 \out, q13 // 58d + 17e
vshll.u8 q13, d22, #2 // 4*b
vadd.u16 q15, q14 // 10*c + 5*f
vadd.s16 q13, q12 // - a + 4*b + g
vsub.s16 \out, q15 // -10*c + 58*d + 17*e -5*f
vadd.s16 \out, q13 // -a + 4*b -10*c + 58*d + 17*e -5*f
.endm
.macro hevc_put_qpel_vX_neon_8 filter
push {r4, r5, r6, r7}
ldr r4, [sp, #16] // height
ldr r5, [sp, #20] // width
vpush {d8-d15}
sub r2, r2, r3, lsl #1
sub r2, r3
mov r12, r4
mov r6, r0
mov r7, r2
lsl r1, #1
0: loadin8
cmp r5, #4
beq 4f
8: subs r4, #1
\filter
vst1.16 {q7}, [r0], r1
regshuffle_d8
vld1.8 {d23}, [r2], r3
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #16
mov r0, r6
add r7, #8
mov r2, r7
b 0b
4: subs r4, #1
\filter
vst1.16 d14, [r0], r1
regshuffle_d8
vld1.32 {d23[0]}, [r2], r3
bne 4b
99: vpop {d8-d15}
pop {r4, r5, r6, r7}
bx lr
.endm
.macro hevc_put_qpel_uw_vX_neon_8 filter
push {r4-r10}
ldr r5, [sp, #28] // width
ldr r4, [sp, #32] // height
ldr r8, [sp, #36] // src2
ldr r9, [sp, #40] // src2stride
vpush {d8-d15}
sub r2, r2, r3, lsl #1
sub r2, r3
mov r12, r4
mov r6, r0
mov r7, r2
cmp r8, #0
bne .Lbi\@
0: loadin8
cmp r5, #4
beq 4f
8: subs r4, #1
\filter
vqrshrun.s16 d0, q7, #6
vst1.8 d0, [r0], r1
regshuffle_d8
vld1.8 {d23}, [r2], r3
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #8
mov r0, r6
add r7, #8
mov r2, r7
b 0b
4: subs r4, #1
\filter
vqrshrun.s16 d0, q7, #6
vst1.32 d0[0], [r0], r1
regshuffle_d8
vld1.32 {d23[0]}, [r2], r3
bne 4b
b 99f
.Lbi\@: lsl r9, #1
mov r10, r8
0: loadin8
cmp r5, #4
beq 4f
8: subs r4, #1
\filter
vld1.16 {q0}, [r8], r9
vqadd.s16 q0, q7
vqrshrun.s16 d0, q0, #7
vst1.8 d0, [r0], r1
regshuffle_d8
vld1.8 {d23}, [r2], r3
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #8
mov r0, r6
add r10, #16
mov r8, r10
add r7, #8
mov r2, r7
b 0b
4: subs r4, #1
\filter
vld1.16 d0, [r8], r9
vqadd.s16 d0, d14
vqrshrun.s16 d0, q0, #7
vst1.32 d0[0], [r0], r1
regshuffle_d8
vld1.32 {d23[0]}, [r2], r3
bne 4b
99: vpop {d8-d15}
pop {r4-r10}
bx lr
.endm
function ff_hevc_put_qpel_v1_neon_8, export=1
hevc_put_qpel_vX_neon_8 qpel_filter_1
endfunc
function ff_hevc_put_qpel_v2_neon_8, export=1
hevc_put_qpel_vX_neon_8 qpel_filter_2
endfunc
function ff_hevc_put_qpel_v3_neon_8, export=1
hevc_put_qpel_vX_neon_8 qpel_filter_3
endfunc
function ff_hevc_put_qpel_uw_v1_neon_8, export=1
hevc_put_qpel_uw_vX_neon_8 qpel_filter_1
endfunc
function ff_hevc_put_qpel_uw_v2_neon_8, export=1
hevc_put_qpel_uw_vX_neon_8 qpel_filter_2
endfunc
function ff_hevc_put_qpel_uw_v3_neon_8, export=1
hevc_put_qpel_uw_vX_neon_8 qpel_filter_3
endfunc
.macro hevc_put_qpel_hX_neon_8 filter
push {r4, r5, r6, r7}
ldr r4, [sp, #16] // height
ldr r5, [sp, #20] // width
vpush {d8-d15}
sub r2, #4
lsl r1, #1
mov r12, r4
mov r6, r0
mov r7, r2
cmp r5, #4
beq 4f
8: subs r4, #1
vextin8
\filter
vst1.16 {q7}, [r0], r1
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #16
mov r0, r6
add r7, #8
mov r2, r7
cmp r5, #4
bne 8b
4: subs r4, #1
vextin8
\filter
vst1.16 d14, [r0], r1
bne 4b
99: vpop {d8-d15}
pop {r4, r5, r6, r7}
bx lr
.endm
.macro hevc_put_qpel_uw_hX_neon_8 filter
push {r4-r10}
ldr r5, [sp, #28] // width
ldr r4, [sp, #32] // height
ldr r8, [sp, #36] // src2
ldr r9, [sp, #40] // src2stride
vpush {d8-d15}
sub r2, #4
mov r12, r4
mov r6, r0
mov r7, r2
cmp r8, #0
bne .Lbi\@
cmp r5, #4
beq 4f
8: subs r4, #1
vextin8
\filter
vqrshrun.s16 d0, q7, #6
vst1.8 d0, [r0], r1
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #8
mov r0, r6
add r7, #8
mov r2, r7
cmp r5, #4
bne 8b
4: subs r4, #1
vextin8
\filter
vqrshrun.s16 d0, q7, #6
vst1.32 d0[0], [r0], r1
bne 4b
b 99f
.Lbi\@:
lsl r9, #1
cmp r5, #4
beq 4f
mov r10, r8
8: subs r4, #1
vextin8
\filter
vld1.16 {q0}, [r8], r9
vqadd.s16 q0, q7
vqrshrun.s16 d0, q0, #7
vst1.8 d0, [r0], r1
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #8
add r10, #16
mov r8, r10
mov r0, r6
add r7, #8
mov r2, r7
cmp r5, #4
bne 8b
4: subs r4, #1
vextin8
\filter
vld1.16 d0, [r8], r9
vqadd.s16 d0, d14
vqrshrun.s16 d0, q0, #7
vst1.32 d0[0], [r0], r1
bne 4b
99: vpop {d8-d15}
pop {r4-r10}
bx lr
.endm
function ff_hevc_put_qpel_h1_neon_8, export=1
hevc_put_qpel_hX_neon_8 qpel_filter_1
endfunc
function ff_hevc_put_qpel_h2_neon_8, export=1
hevc_put_qpel_hX_neon_8 qpel_filter_2
endfunc
function ff_hevc_put_qpel_h3_neon_8, export=1
hevc_put_qpel_hX_neon_8 qpel_filter_3
endfunc
function ff_hevc_put_qpel_uw_h1_neon_8, export=1
hevc_put_qpel_uw_hX_neon_8 qpel_filter_1
endfunc
function ff_hevc_put_qpel_uw_h2_neon_8, export=1
hevc_put_qpel_uw_hX_neon_8 qpel_filter_2
endfunc
function ff_hevc_put_qpel_uw_h3_neon_8, export=1
hevc_put_qpel_uw_hX_neon_8 qpel_filter_3
endfunc
.macro hevc_put_qpel_hXvY_neon_8 filterh filterv
push {r4, r5, r6, r7}
ldr r4, [sp, #16] // height
ldr r5, [sp, #20] // width
vpush {d8-d15}
sub r2, #4
sub r2, r2, r3, lsl #1
sub r2, r3 // extra_before 3
lsl r1, #1
mov r12, r4
mov r6, r0
mov r7, r2
0: vextin8
\filterh q0
vextin8
\filterh q1
vextin8
\filterh q2
vextin8
\filterh q3
vextin8
\filterh q4
vextin8
\filterh q5
vextin8
\filterh q6
vextin8
\filterh q7
cmp r5, #4
beq 4f
8: subs r4, #1
\filterv
vst1.16 {q8}, [r0], r1
regshuffle_q8
vextin8
\filterh q7
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #16
mov r0, r6
add r7, #8
mov r2, r7
b 0b
4: subs r4, #1
\filterv
vst1.16 d16, [r0], r1
regshuffle_q8
vextin8
\filterh q7
bne 4b
99: vpop {d8-d15}
pop {r4, r5, r6, r7}
bx lr
.endm
.macro hevc_put_qpel_uw_hXvY_neon_8 filterh filterv
push {r4-r10}
ldr r5, [sp, #28] // width
ldr r4, [sp, #32] // height
ldr r8, [sp, #36] // src2
ldr r9, [sp, #40] // src2stride
vpush {d8-d15}
sub r2, #4
sub r2, r2, r3, lsl #1
sub r2, r3 // extra_before 3
mov r12, r4
mov r6, r0
mov r7, r2
cmp r8, #0
bne .Lbi\@
0: vextin8
\filterh q0
vextin8
\filterh q1
vextin8
\filterh q2
vextin8
\filterh q3
vextin8
\filterh q4
vextin8
\filterh q5
vextin8
\filterh q6
vextin8
\filterh q7
cmp r5, #4
beq 4f
8: subs r4, #1
\filterv
vqrshrun.s16 d0, q8, #6
vst1.8 d0, [r0], r1
regshuffle_q8
vextin8
\filterh q7
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #8
mov r0, r6
add r7, #8
mov r2, r7
b 0b
4: subs r4, #1
\filterv
vqrshrun.s16 d0, q8, #6
vst1.32 d0[0], [r0], r1
regshuffle_q8
vextin8
\filterh q7
bne 4b
b 99f
.Lbi\@: lsl r9, #1
mov r10, r8
0: vextin8
\filterh q0
vextin8
\filterh q1
vextin8
\filterh q2
vextin8
\filterh q3
vextin8
\filterh q4
vextin8
\filterh q5
vextin8
\filterh q6
vextin8
\filterh q7
cmp r5, #4
beq 4f
8: subs r4, #1
\filterv
vld1.16 {q0}, [r8], r9
vqadd.s16 q0, q8
vqrshrun.s16 d0, q0, #7
vst1.8 d0, [r0], r1
regshuffle_q8
vextin8
\filterh q7
bne 8b
subs r5, #8
beq 99f
mov r4, r12
add r6, #8
mov r0, r6
add r10, #16
mov r8, r10
add r7, #8
mov r2, r7
b 0b
4: subs r4, #1
\filterv
vld1.16 d0, [r8], r9
vqadd.s16 d0, d16
vqrshrun.s16 d0, q0, #7
vst1.32 d0[0], [r0], r1
regshuffle_q8
vextin8
\filterh q7
bne 4b
99: vpop {d8-d15}
pop {r4-r10}
bx lr
.endm
function ff_hevc_put_qpel_h1v1_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_1 qpel_filter_1_32b
endfunc
function ff_hevc_put_qpel_h2v1_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_2 qpel_filter_1_32b
endfunc
function ff_hevc_put_qpel_h3v1_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_3 qpel_filter_1_32b
endfunc
function ff_hevc_put_qpel_h1v2_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_1 qpel_filter_2_32b
endfunc
function ff_hevc_put_qpel_h2v2_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_2 qpel_filter_2_32b
endfunc
function ff_hevc_put_qpel_h3v2_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_3 qpel_filter_2_32b
endfunc
function ff_hevc_put_qpel_h1v3_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_1 qpel_filter_3_32b
endfunc
function ff_hevc_put_qpel_h2v3_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_2 qpel_filter_3_32b
endfunc
function ff_hevc_put_qpel_h3v3_neon_8, export=1
hevc_put_qpel_hXvY_neon_8 qpel_filter_3 qpel_filter_3_32b
endfunc
function ff_hevc_put_qpel_uw_h1v1_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_1 qpel_filter_1_32b
endfunc
function ff_hevc_put_qpel_uw_h2v1_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_2 qpel_filter_1_32b
endfunc
function ff_hevc_put_qpel_uw_h3v1_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_3 qpel_filter_1_32b
endfunc
function ff_hevc_put_qpel_uw_h1v2_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_1 qpel_filter_2_32b
endfunc
function ff_hevc_put_qpel_uw_h2v2_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_2 qpel_filter_2_32b
endfunc
function ff_hevc_put_qpel_uw_h3v2_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_3 qpel_filter_2_32b
endfunc
function ff_hevc_put_qpel_uw_h1v3_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_1 qpel_filter_3_32b
endfunc
function ff_hevc_put_qpel_uw_h2v3_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_2 qpel_filter_3_32b
endfunc
function ff_hevc_put_qpel_uw_h3v3_neon_8, export=1
hevc_put_qpel_uw_hXvY_neon_8 qpel_filter_3 qpel_filter_3_32b
endfunc
.macro init_put_pixels
pld [r1]
pld [r1, r2]
mov r12, MAX_PB_SIZE
lsl r12, #1
.endm
function ff_hevc_put_pixels_w2_neon_8, export=1
init_put_pixels
vmov.u8 d5, #255
vshr.u64 d5, #32
0: subs r3, #1
vld1.32 {d0[0]}, [r1], r2
pld [r1]
vld1.32 d6, [r0]
vshll.u8 q0, d0, #6
vbit d6, d0, d5
vst1.32 d6, [r0], r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w4_neon_8, export=1
init_put_pixels
0: subs r3, #2
vld1.32 {d0[0]}, [r1], r2
vld1.32 {d0[1]}, [r1], r2
pld [r1]
pld [r1, r2]
vshll.u8 q0, d0, #6
vst1.64 {d0}, [r0], r12
vst1.64 {d1}, [r0], r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w6_neon_8, export=1
init_put_pixels
vmov.u8 q10, #255
vshr.u64 d21, #32
0: subs r3, #1
vld1.16 {d0}, [r1], r2
pld [r1]
vshll.u8 q0, d0, #6
vld1.8 {q12}, [r0]
vbit q12, q0, q10
vst1.8 {q12}, [r0], r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w8_neon_8, export=1
init_put_pixels
0: subs r3, #2
vld1.8 {d0}, [r1], r2
vld1.8 {d2}, [r1], r2
pld [r1]
pld [r1, r2]
vshll.u8 q0, d0, #6
vshll.u8 q1, d2, #6
vst1.16 {q0}, [r0], r12
vst1.16 {q1}, [r0], r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w12_neon_8, export=1
init_put_pixels
0: subs r3, #2
vld1.64 {d0}, [r1]
add r1, #8
vld1.32 {d1[0]}, [r1], r2
sub r1, #8
vld1.64 {d2}, [r1]
add r1, #8
vld1.32 {d1[1]}, [r1], r2
sub r1, #8
pld [r1]
pld [r1, r2]
vshll.u8 q8, d0, #6
vshll.u8 q9, d1, #6
vshll.u8 q10, d2, #6
vmov d22, d19
vst1.64 {d16, d17, d18}, [r0], r12
vst1.64 {d20, d21, d22}, [r0], r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w16_neon_8, export=1
init_put_pixels
0: subs r3, #2
vld1.8 {q0}, [r1], r2
vld1.8 {q1}, [r1], r2
pld [r1]
pld [r1, r2]
vshll.u8 q8, d0, #6
vshll.u8 q9, d1, #6
vshll.u8 q10, d2, #6
vshll.u8 q11, d3, #6
vst1.8 {q8, q9}, [r0], r12
vst1.8 {q10, q11}, [r0], r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w24_neon_8, export=1
init_put_pixels
0: subs r3, #1
vld1.8 {d0, d1, d2}, [r1], r2
pld [r1]
vshll.u8 q10, d0, #6
vshll.u8 q11, d1, #6
vshll.u8 q12, d2, #6
vstm r0, {q10, q11, q12}
add r0, r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w32_neon_8, export=1
init_put_pixels
0: subs r3, #1
vld1.8 {q0, q1}, [r1], r2
pld [r1]
vshll.u8 q8, d0, #6
vshll.u8 q9, d1, #6
vshll.u8 q10, d2, #6
vshll.u8 q11, d3, #6
vstm r0, {q8, q9, q10, q11}
add r0, r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w48_neon_8, export=1
init_put_pixels
0: subs r3, #1
vld1.8 {q0, q1}, [r1]
add r1, #32
vld1.8 {q2}, [r1], r2
sub r1, #32
pld [r1]
vshll.u8 q8, d0, #6
vshll.u8 q9, d1, #6
vshll.u8 q10, d2, #6
vshll.u8 q11, d3, #6
vshll.u8 q12, d4, #6
vshll.u8 q13, d5, #6
vstm r0, {q8, q9, q10, q11, q12, q13}
add r0, r12
bne 0b
bx lr
endfunc
function ff_hevc_put_pixels_w64_neon_8, export=1
init_put_pixels
0: subs r3, #1
vld1.8 {q0, q1}, [r1]
add r1, #32
vld1.8 {q2, q3}, [r1], r2
sub r1, #32
pld [r1]
vshll.u8 q8, d0, #6
vshll.u8 q9, d1, #6
vshll.u8 q10, d2, #6
vshll.u8 q11, d3, #6
vshll.u8 q12, d4, #6
vshll.u8 q13, d5, #6
vshll.u8 q14, d6, #6
vshll.u8 q15, d7, #6
vstm r0, {q8, q9, q10, q11, q12, q13, q14, q15}
add r0, r12
bne 0b
bx lr
endfunc
function ff_hevc_put_qpel_uw_pixels_neon_8, export=1
push {r4-r9}
ldr r5, [sp, #24] // width
ldr r4, [sp, #28] // height
ldr r8, [sp, #32] // src2
ldr r9, [sp, #36] // src2stride
vpush {d8-d15}
cmp r8, #0
bne 2f
1: subs r4, #1
vld1.8 {d0}, [r2], r3
vst1.8 d0, [r0], r1
bne 1b
vpop {d8-d15}
pop {r4-r9}
bx lr
2: subs r4, #1
vld1.8 {d0}, [r2], r3
vld1.16 {q1}, [r8], r9
vshll.u8 q0, d0, #6
vqadd.s16 q0, q1
vqrshrun.s16 d0, q0, #7
vst1.8 d0, [r0], r1
bne 2b
vpop {d8-d15}
pop {r4-r9}
bx lr
endfunc
.macro put_qpel_uw_pixels width, regs, regs2, regs3, regs4
function ff_hevc_put_qpel_uw_pixels_w\width\()_neon_8, export=1
ldr r12, [sp] // height
1: subs r12, #4
vld1.32 {\regs} , [r2], r3
vld1.32 {\regs2} , [r2], r3
vld1.32 {\regs3} , [r2], r3
vld1.32 {\regs4} , [r2], r3
vst1.32 {\regs} , [r0], r1
vst1.32 {\regs2} , [r0], r1
vst1.32 {\regs3} , [r0], r1
vst1.32 {\regs4} , [r0], r1
bne 1b
bx lr
endfunc
.endm
.macro put_qpel_uw_pixels_m width, regs, regs2, regs3, regs4
function ff_hevc_put_qpel_uw_pixels_w\width\()_neon_8, export=1
push {r4-r5}
ldr r12, [sp, #8] // height
1: subs r12, #2
mov r4, r2
vld1.32 {\regs} , [r2]!
vld1.32 {\regs2} , [r2]
add r2, r4, r3
mov r4, r2
vld1.32 {\regs3} , [r2]!
vld1.32 {\regs4} , [r2]
add r2, r4, r3
mov r5, r0
vst1.32 {\regs} , [r0]!
vst1.32 {\regs2} , [r0]
add r0, r5, r1
mov r5, r0
vst1.32 {\regs3} , [r0]!
vst1.32 {\regs4} , [r0]
add r0, r5, r1
bne 1b
pop {r4-r5}
bx lr
endfunc
.endm
put_qpel_uw_pixels 4, d0[0], d0[1], d1[0], d1[1]
put_qpel_uw_pixels 8, d0, d1, d2, d3
put_qpel_uw_pixels_m 12, d0, d1[0], d2, d3[0]
put_qpel_uw_pixels 16, q0, q1, q2, q3
put_qpel_uw_pixels 24, d0-d2, d3-d5, d16-d18, d19-d21
put_qpel_uw_pixels 32, q0-q1, q2-q3, q8-q9, q10-q11
put_qpel_uw_pixels_m 48, q0-q1, q2, q8-q9, q10
put_qpel_uw_pixels_m 64, q0-q1, q2-q3, q8-q9, q10-q11
|
xiangxud/webrtc_H265player | 1,028 | test/prod_decoder/codec/3rdparty/de265/libde265/arm/cpudetect.S | /*
* H.265 video codec.
* Copyright (c) 2013-2015 struktur AG, Joachim Bauch <bauch@struktur.de>
*
* This file is part of libde265.
*
* libde265 is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation, either version 3 of
* the License, or (at your option) any later version.
*
* libde265 is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with libde265. If not, see <http://www.gnu.org/licenses/>.
*/
#include "asm.S"
#include "neon.S"
// we execute a simple NEON instruction and check if SIGILL is triggered to
// detect if the CPU support NEON code
function libde265_detect_neon, export=1
vand q0, q0, q0
bx lr
endfunc
|
xiangxud/webrtc_H265player | 8,035 | test/prod_decoder/codec/3rdparty/de265/libde265/arm/asm.S | /*
* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "config.h"
#ifdef __ELF__
# define ELF
#else
# define ELF @
#endif
#if CONFIG_THUMB
# define A @
# define T
#else
# define A
# define T @
#endif
#if HAVE_AS_FUNC
# define FUNC
#else
# define FUNC @
#endif
#if HAVE_NEON
.arch armv7-a
#elif HAVE_ARMV6T2
.arch armv6t2
#elif HAVE_ARMV6
.arch armv6
#elif HAVE_ARMV5TE
.arch armv5te
#endif
#if HAVE_NEON
.fpu neon
#elif HAVE_VFP
.fpu vfp
#endif
.syntax unified
T .thumb
ELF .eabi_attribute 25, 1 @ Tag_ABI_align_preserved
ELF .section .note.GNU-stack,"",%progbits @ Mark stack as non-executable
.macro function name, export=0, align=2
.set .Lpic_idx, 0
.set .Lpic_gp, 0
.macro endfunc
.if .Lpic_idx
.align 2
.altmacro
put_pic %(.Lpic_idx - 1)
.noaltmacro
.endif
ELF .size \name, . - \name
FUNC .endfunc
.purgem endfunc
.endm
.text
.align \align
.if \export
.global EXTERN_ASM\name
ELF .type EXTERN_ASM\name, %function
FUNC .func EXTERN_ASM\name
EXTERN_ASM\name:
.else
ELF .type \name, %function
FUNC .func \name
\name:
.endif
.endm
.macro const name, align=2, relocate=0
.macro endconst
ELF .size \name, . - \name
.purgem endconst
.endm
.if HAVE_SECTION_DATA_REL_RO && \relocate
.section .data.rel.ro
.else
.section .rodata
.endif
.align \align
\name:
.endm
#if !HAVE_ARMV6T2_EXTERNAL
.macro movw rd, val
mov \rd, \val & 255
orr \rd, \val & ~255
.endm
#endif
.macro mov32 rd, val
#if HAVE_ARMV6T2_EXTERNAL
movw \rd, #(\val) & 0xffff
.if (\val) >> 16
movt \rd, #(\val) >> 16
.endif
#else
ldr \rd, =\val
#endif
.endm
.macro put_pic num
put_pic_\num
.endm
.macro do_def_pic num, val, label
.macro put_pic_\num
.if \num
.altmacro
put_pic %(\num - 1)
.noaltmacro
.endif
\label: .word \val
.purgem put_pic_\num
.endm
.endm
.macro def_pic val, label
.altmacro
do_def_pic %.Lpic_idx, \val, \label
.noaltmacro
.set .Lpic_idx, .Lpic_idx + 1
.endm
.macro ldpic rd, val, indir=0
ldr \rd, .Lpicoff\@
.Lpic\@:
.if \indir
A ldr \rd, [pc, \rd]
T add \rd, pc
T ldr \rd, [\rd]
.else
add \rd, pc
.endif
def_pic \val - (.Lpic\@ + (8 >> CONFIG_THUMB)), .Lpicoff\@
.endm
.macro movrel rd, val
#if CONFIG_PIC
ldpic \rd, \val
#elif HAVE_ARMV6T2_EXTERNAL && !defined(__APPLE__)
movw \rd, #:lower16:\val
movt \rd, #:upper16:\val
#else
ldr \rd, =\val
#endif
.endm
.macro movrelx rd, val, gp
#if CONFIG_PIC && defined(__ELF__)
.ifnb \gp
.if .Lpic_gp
.unreq gp
.endif
gp .req \gp
ldpic gp, _GLOBAL_OFFSET_TABLE_
.elseif !.Lpic_gp
gp .req r12
ldpic gp, _GLOBAL_OFFSET_TABLE_
.endif
.set .Lpic_gp, 1
ldr \rd, .Lpicoff\@
ldr \rd, [gp, \rd]
def_pic \val(GOT), .Lpicoff\@
#elif CONFIG_PIC && defined(__APPLE__)
ldpic \rd, .Lpic\@, indir=1
.non_lazy_symbol_pointer
.Lpic\@:
.indirect_symbol \val
.word 0
.text
#else
movrel \rd, \val
#endif
.endm
.macro add_sh rd, rn, rm, sh:vararg
A add \rd, \rn, \rm, \sh
T mov \rm, \rm, \sh
T add \rd, \rn, \rm
.endm
.macro ldr_pre rt, rn, rm:vararg
A ldr \rt, [\rn, \rm]!
T add \rn, \rn, \rm
T ldr \rt, [\rn]
.endm
.macro ldr_dpre rt, rn, rm:vararg
A ldr \rt, [\rn, -\rm]!
T sub \rn, \rn, \rm
T ldr \rt, [\rn]
.endm
.macro ldr_nreg rt, rn, rm:vararg
A ldr \rt, [\rn, -\rm]
T sub \rt, \rn, \rm
T ldr \rt, [\rt]
.endm
.macro ldr_post rt, rn, rm:vararg
A ldr \rt, [\rn], \rm
T ldr \rt, [\rn]
T add \rn, \rn, \rm
.endm
.macro ldrc_pre cc, rt, rn, rm:vararg
A ldr\cc \rt, [\rn, \rm]!
T itt \cc
T add\cc \rn, \rn, \rm
T ldr\cc \rt, [\rn]
.endm
.macro ldrd_reg rt, rt2, rn, rm
A ldrd \rt, \rt2, [\rn, \rm]
T add \rt, \rn, \rm
T ldrd \rt, \rt2, [\rt]
.endm
.macro ldrd_post rt, rt2, rn, rm
A ldrd \rt, \rt2, [\rn], \rm
T ldrd \rt, \rt2, [\rn]
T add \rn, \rn, \rm
.endm
.macro ldrh_pre rt, rn, rm
A ldrh \rt, [\rn, \rm]!
T add \rn, \rn, \rm
T ldrh \rt, [\rn]
.endm
.macro ldrh_dpre rt, rn, rm
A ldrh \rt, [\rn, -\rm]!
T sub \rn, \rn, \rm
T ldrh \rt, [\rn]
.endm
.macro ldrh_post rt, rn, rm
A ldrh \rt, [\rn], \rm
T ldrh \rt, [\rn]
T add \rn, \rn, \rm
.endm
.macro ldrb_post rt, rn, rm
A ldrb \rt, [\rn], \rm
T ldrb \rt, [\rn]
T add \rn, \rn, \rm
.endm
.macro str_post rt, rn, rm:vararg
A str \rt, [\rn], \rm
T str \rt, [\rn]
T add \rn, \rn, \rm
.endm
.macro strb_post rt, rn, rm:vararg
A strb \rt, [\rn], \rm
T strb \rt, [\rn]
T add \rn, \rn, \rm
.endm
.macro strd_post rt, rt2, rn, rm
A strd \rt, \rt2, [\rn], \rm
T strd \rt, \rt2, [\rn]
T add \rn, \rn, \rm
.endm
.macro strh_pre rt, rn, rm
A strh \rt, [\rn, \rm]!
T add \rn, \rn, \rm
T strh \rt, [\rn]
.endm
.macro strh_dpre rt, rn, rm
A strh \rt, [\rn, -\rm]!
T sub \rn, \rn, \rm
T strh \rt, [\rn]
.endm
.macro strh_post rt, rn, rm
A strh \rt, [\rn], \rm
T strh \rt, [\rn]
T add \rn, \rn, \rm
.endm
.macro strh_dpost rt, rn, rm
A strh \rt, [\rn], -\rm
T strh \rt, [\rn]
T sub \rn, \rn, \rm
.endm
#if HAVE_VFP_ARGS
ELF .eabi_attribute 28, 1
# define VFP
# define NOVFP @
#else
# define VFP @
# define NOVFP
#endif
#define GLUE(a, b) a ## b
#define JOIN(a, b) GLUE(a, b)
#define X(s) JOIN(EXTERN_ASM, s)
|
xiangxud/webrtc_H265player | 1,975 | test/prod_decoder/codec/3rdparty/de265/libde265/arm/neon.S | /*
* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
.macro transpose_8x8 r0, r1, r2, r3, r4, r5, r6, r7
vtrn.32 \r0, \r4
vtrn.32 \r1, \r5
vtrn.32 \r2, \r6
vtrn.32 \r3, \r7
vtrn.16 \r0, \r2
vtrn.16 \r1, \r3
vtrn.16 \r4, \r6
vtrn.16 \r5, \r7
vtrn.8 \r0, \r1
vtrn.8 \r2, \r3
vtrn.8 \r4, \r5
vtrn.8 \r6, \r7
.endm
.macro transpose_4x4 r0, r1, r2, r3
vtrn.16 \r0, \r2
vtrn.16 \r1, \r3
vtrn.8 \r0, \r1
vtrn.8 \r2, \r3
.endm
.macro swap4 r0, r1, r2, r3, r4, r5, r6, r7
vswp \r0, \r4
vswp \r1, \r5
vswp \r2, \r6
vswp \r3, \r7
.endm
.macro transpose16_4x4 r0, r1, r2, r3, r4, r5, r6, r7
vtrn.32 \r0, \r2
vtrn.32 \r1, \r3
vtrn.32 \r4, \r6
vtrn.32 \r5, \r7
vtrn.16 \r0, \r1
vtrn.16 \r2, \r3
vtrn.16 \r4, \r5
vtrn.16 \r6, \r7
.endm
|
xiangxud/webrtc_H265player | 30,541 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm/reconstruct_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro LOAD_4x4_DATA_FOR_DCT arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: \arg0~\arg3, src1*, src1_stride, src2*, src2_stride
vld2.16 {\arg0[0],\arg1[0]}, [\arg4], \arg5
vld2.16 {\arg2[0],\arg3[0]}, [\arg6], \arg7
vld2.16 {\arg0[1],\arg1[1]}, [\arg4], \arg5
vld2.16 {\arg2[1],\arg3[1]}, [\arg6], \arg7
vld2.16 {\arg0[2],\arg1[2]}, [\arg4], \arg5
vld2.16 {\arg2[2],\arg3[2]}, [\arg6], \arg7
vld2.16 {\arg0[3],\arg1[3]}, [\arg4], \arg5
vld2.16 {\arg2[3],\arg3[3]}, [\arg6], \arg7
// }
.endm
.macro LOAD_8x8_DATA_FOR_DCT arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
// { // input: \arg0~\arg3, src1*, src2*; untouched r2:src1_stride &r4:src2_stride
vld1.64 {\arg0}, [\arg8], r2
vld1.64 {\arg4}, [\arg9], r4
vld1.64 {\arg1}, [\arg8], r2
vld1.64 {\arg5}, [\arg9], r4
vld1.64 {\arg2}, [\arg8], r2
vld1.64 {\arg6}, [\arg9], r4
vld1.64 {\arg3}, [\arg8], r2
vld1.64 {\arg7}, [\arg9], r4
// }
.endm
.macro DCT_ROW_TRANSFORM_TOTAL_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_d[0]~[3], working: [4]~[7]
vadd.s16 \arg4, \arg0, \arg3 //int16 s[0] = data[i] + data[i3];
vsub.s16 \arg7, \arg0, \arg3 //int16 s[3] = data[i] - data[i3];
vadd.s16 \arg5, \arg1, \arg2 //int16 s[1] = data[i1] + data[i2];
vsub.s16 \arg6, \arg1, \arg2 //int16 s[2] = data[i1] - data[i2];
vadd.s16 \arg0, \arg4, \arg5 //int16 dct[i ] = s[0] + s[1];
vsub.s16 \arg2, \arg4, \arg5 //int16 dct[i2] = s[0] - s[1];
vshl.s16 \arg1, \arg7, #1
vshl.s16 \arg3, \arg6, #1
vadd.s16 \arg1, \arg1, \arg6 //int16 dct[i1] = (s[3] << 1) + s[2];
vsub.s16 \arg3, \arg7, \arg3 //int16 dct[i3] = s[3] - (s[2] << 1);
// }
.endm
.macro MATRIX_TRANSFORM_EACH_16BITS arg0, arg1, arg2, arg3
// { // input & output: src_d[0]~[3];[0 1 2 3]+[4 5 6 7]+[8 9 10 11]+[12 13 14 15]
vtrn.s16 \arg0, \arg1 //[0 1 2 3]+[4 5 6 7]-->[0 4 2 6]+[1 5 3 7]
vtrn.s16 \arg2, \arg3 //[8 9 10 11]+[12 13 14 15]-->[8 12 10 14]+[9 13 11 15]
vtrn.32 \arg0, \arg2 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14]
vtrn.32 \arg1, \arg3 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15]
// }
.endm
.macro NEWQUANT_COEF_EACH_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input: coef, ff (dst), ff_d0, ff_d1, mf_d0, md_d1
veor.s16 \arg6, \arg6 // init 0 , and keep 0;
vaba.s16 \arg1, \arg0, \arg6 // f + abs(coef - 0)
vmull.s16 \arg7, \arg2, \arg4
vmull.s16 \arg8, \arg3, \arg5
vshr.s32 \arg7, #16
vshr.s32 \arg8, #16
vmovn.s32 \arg2, \arg7
vmovn.s32 \arg3, \arg8
vcgt.s16 \arg7, \arg0, #0 // if true, location of coef == 11111111
vbif.s16 \arg6, \arg1, \arg7 // if (x<0) reserved part; else keep 0 untouched
vshl.s16 \arg6, #1
vsub.s16 \arg1, \arg1, \arg6 // if x > 0, -= 0; else x-= 2x
// }
.endm
.macro NEWQUANT_COEF_EACH_16BITS_MAX arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
// { // input: coef, ff (dst), ff_d0, ff_d1, mf_d0(max), md_d1
veor.s16 \arg6, \arg6 // init 0 , and keep 0;
vaba.s16 \arg1, \arg0, \arg6 // f + abs(coef - 0)
vmull.s16 \arg7, \arg2, \arg4
vmull.s16 \arg8, \arg3, \arg5
vshr.s32 \arg7, #16
vshr.s32 \arg8, #16
vmovn.s32 \arg2, \arg7
vmovn.s32 \arg3, \arg8
vcgt.s16 \arg7, \arg0, #0 // if true, location of coef == 11111111
vbif.s16 \arg6, \arg1, \arg7 // if (x<0) reserved part; else keep 0 untouched
vshl.s16 \arg6, #1
vmax.s16 \arg9, \arg2, \arg3
vsub.s16 \arg1, \arg1, \arg6 // if x > 0, -= 0; else x-= 2x
// }
.endm
.macro QUANT_DUALWORD_COEF_EACH_16BITS arg0, arg1, arg2, arg3, arg4
// { // input: coef, ff (dst), mf , working_d (all 0), working_q
vaba.s16 \arg1, \arg0, \arg3 // f + abs(coef - 0)
vmull.s16 \arg4, \arg1, \arg2 // *= mf
vshr.s32 \arg4, #16
vmovn.s32 \arg1, \arg4 // >> 16
vcgt.s16 \arg2, \arg0, #0 // if true, location of coef == 11111111
vbif.s16 \arg3, \arg1, \arg2 // if (x<0) reserved part; else keep 0 untouched
vshl.s16 \arg3, #1
vsub.s16 \arg1, \arg1, \arg3 // if x > 0, -= 0; else x-= 2x
// }
.endm
.macro DC_ZERO_COUNT_IN_DUALWORD arg0, arg1, arg2
// { // input: coef, dst_d, working_d (all 0x01)
vceq.s16 \arg1, \arg0, #0
vand.s16 \arg1, \arg2
vpadd.s16 \arg1, \arg1, \arg1
vpadd.s16 \arg1, \arg1, \arg1
// }
.endm
.macro SELECT_MAX_IN_ABS_COEF arg0, arg1, arg2, arg3, arg4
// { // input: coef_0, coef_1, max_q (identy to follow two), output: max_d0, max_d1
vmax.s16 \arg2, \arg0, \arg1 // max 1st in \arg3 & max 2nd in \arg4
vpmax.s16 \arg3, \arg3, \arg4 // max 1st in \arg3[0][1] & max 2nd in \arg3[2][3]
vpmax.s16 \arg3, \arg3, \arg4 // max 1st in \arg3[0][1]
// }
.endm
.macro ZERO_COUNT_IN_2_QUARWORD arg0, arg1, arg2, arg3, arg4, arg5, arg6
// { // input: coef_0 (identy to \arg3 \arg4), coef_1(identy to \arg5 \arg6), mask_q
vceq.s16 \arg0, #0
vceq.s16 \arg1, #0
vand.s16 \arg0, \arg2
vand.s16 \arg1, \arg2
vpadd.s16 \arg3, \arg3, \arg5
vpadd.s16 \arg4, \arg4, \arg6
vpadd.s16 \arg3, \arg3, \arg4 // 8-->4
vpadd.s16 \arg3, \arg3, \arg3
vpadd.s16 \arg3, \arg3, \arg3
// }
.endm
.macro HDM_QUANT_2x2_TOTAL_16BITS arg0, arg1, arg2
// { // input: src_d[0]~[3], working_d, dst_d
vshr.s64 \arg1, \arg0, #32
vadd.s16 \arg2, \arg0, \arg1 // [0] = rs[0] + rs[32];[1] = rs[16] + rs[48];
vsub.s16 \arg1, \arg0, \arg1 // [0] = rs[0] - rs[32];[1] = rs[16] - rs[48];
vtrn.s16 \arg2, \arg1
vtrn.s32 \arg2, \arg1
// }
.endm
.macro IHDM_4x4_TOTAL_16BITS arg0, arg1, arg2
// { // input: each src_d[0]~[3](dst), working_q0, working_q1, working_q2
vshr.s64 \arg1, \arg0, #32
vadd.s16 \arg2, \arg0, \arg1 // [0] = rs[0] + rs[2];[1] = rs[1] + rs[3];
vsub.s16 \arg1, \arg0, \arg1 // [0] = rs[0] - rs[2];[1] = rs[1] - rs[3];
vtrn.s16 \arg2, \arg1
vrev32.16 \arg1, \arg1
vtrn.s32 \arg2, \arg1 // [0] = rs[0] + rs[2];[1] = rs[0] - rs[2];[2] = rs[1] - rs[3];[3] = rs[1] + rs[3];
vrev64.16 \arg1, \arg2
vadd.s16 \arg0, \arg2, \arg1 // [0] = rs[0] + rs[3];[1] = rs[1] + rs[2];
vsub.s16 \arg1, \arg2, \arg1
vrev32.16 \arg1, \arg1 // [0] = rs[1] - rs[2];[1] = rs[0] - rs[3];
vtrn.s32 \arg0, \arg1 // [0] = rs[0] + rs[3];[1] = rs[1] + rs[2];[2] = rs[1] - rs[2];[3] = rs[0] - rs[3];
// }
.endm
.macro MB_PRED_8BITS_ADD_DCT_16BITS_CLIP arg0, arg1, arg2, arg3, arg4, arg5
// { // input: pred_d[0]/[1](output), dct_q0/1, working_q0/1;
vmovl.u8 \arg4,\arg0
vmovl.u8 \arg5,\arg1
vadd.s16 \arg4,\arg2
vadd.s16 \arg5,\arg3
vqmovun.s16 \arg0,\arg4
vqmovun.s16 \arg1,\arg5
// }
.endm
.macro ROW_TRANSFORM_1_STEP_TOTAL_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_d[0]~[3], output: e_d[0]~[3];
vadd.s16 \arg4, \arg0, \arg2 //int16 e[i][0] = src[0] + src[2];
vsub.s16 \arg5, \arg0, \arg2 //int16 e[i][1] = src[0] - src[2];
vshr.s16 \arg6, \arg1, #1
vshr.s16 \arg7, \arg3, #1
vsub.s16 \arg6, \arg6, \arg3 //int16 e[i][2] = (src[1]>>1)-src[3];
vadd.s16 \arg7, \arg1, \arg7 //int16 e[i][3] = src[1] + (src[3]>>1);
// }
.endm
.macro TRANSFORM_TOTAL_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7 // both row & col transform used
// { // output: f_q[0]~[3], input: e_q[0]~[3];
vadd.s16 \arg0, \arg4, \arg7 //int16 f[i][0] = e[i][0] + e[i][3];
vadd.s16 \arg1, \arg5, \arg6 //int16 f[i][1] = e[i][1] + e[i][2];
vsub.s16 \arg2, \arg5, \arg6 //int16 f[i][2] = e[i][1] - e[i][2];
vsub.s16 \arg3, \arg4, \arg7 //int16 f[i][3] = e[i][0] - e[i][3];
// }
.endm
.macro ROW_TRANSFORM_0_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_d[0]~[3], output: e_q[0]~[3];
vaddl.s16 \arg4, \arg0, \arg2 //int32 e[i][0] = src[0] + src[2];
vsubl.s16 \arg5, \arg0, \arg2 //int32 e[i][1] = src[0] - src[2];
vsubl.s16 \arg6, \arg1, \arg3 //int32 e[i][2] = src[1] - src[3];
vaddl.s16 \arg7, \arg1, \arg3 //int32 e[i][3] = src[1] + src[3];
// }
.endm
.macro ROW_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: \arg8 \arg9
vaddl.s16 \arg4, \arg0, \arg2 //int32 e[i][0] = src[0] + src[2];
vsubl.s16 \arg5, \arg0, \arg2 //int32 e[i][1] = src[0] - src[2];
vshr.s16 \arg8, \arg1, #1
vshr.s16 \arg9, \arg3, #1
vsubl.s16 \arg6, \arg8, \arg3 //int32 e[i][2] = (src[1]>>1)-src[3];
vaddl.s16 \arg7, \arg1, \arg9 //int32 e[i][3] = src[1] + (src[3]>>1);
// }
.endm
.macro TRANSFORM_4BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7 // both row & col transform used
// { // output: f_q[0]~[3], input: e_q[0]~[3];
vadd.s32 \arg0, \arg4, \arg7 //int16 f[i][0] = e[i][0] + e[i][3];
vadd.s32 \arg1, \arg5, \arg6 //int16 f[i][1] = e[i][1] + e[i][2];
vsub.s32 \arg2, \arg5, \arg6 //int16 f[i][2] = e[i][1] - e[i][2];
vsub.s32 \arg3, \arg4, \arg7 //int16 f[i][3] = e[i][0] - e[i][3];
// }
.endm
.macro COL_TRANSFORM_0_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_q[0]~[3], output: e_q[0]~[3];
vadd.s32 \arg4, \arg0, \arg2 //int32 e[0][j] = f[0][j] + f[2][j];
vsub.s32 \arg5, \arg0, \arg2 //int32 e[1][j] = f[0][j] - f[2][j];
vsub.s32 \arg6, \arg1, \arg3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
vadd.s32 \arg7, \arg1, \arg3 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
// }
.endm
.macro COL_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_q[0]~[3], output: e_q[0]~[3];
vadd.s32 \arg4, \arg0, \arg2 //int32 e[0][j] = f[0][j] + f[2][j];
vsub.s32 \arg5, \arg0, \arg2 //int32 e[1][j] = f[0][j] - f[2][j];
vshr.s32 \arg6, \arg1, #1
vshr.s32 \arg7, \arg3, #1
vsub.s32 \arg6, \arg6, \arg3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
vadd.s32 \arg7, \arg1, \arg7 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
// }
.endm
WELS_ASM_FUNC_BEGIN WelsDctT4_neon
push {r4}
ldr r4, [sp, #4]
LOAD_4x4_DATA_FOR_DCT d4, d5, d6, d7, r1, r2, r3, r4
vsubl.u8 q0, d4, d6
vsubl.u8 q1, d5, d7
vtrn.s32 q0, q1
vswp d1, d2
// horizontal transform
DCT_ROW_TRANSFORM_TOTAL_16BITS d0, d1, d2, d3, d4, d5, d6, d7
// transform element
MATRIX_TRANSFORM_EACH_16BITS d0, d1, d2, d3
// vertical transform
DCT_ROW_TRANSFORM_TOTAL_16BITS d0, d1, d2, d3, d4, d5, d6, d7
// transform element
MATRIX_TRANSFORM_EACH_16BITS d0, d1, d2, d3
vst1.s16 {q0, q1}, [r0]!
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDctFourT4_neon
push {r4}
ldr r4, [sp, #4]
LOAD_8x8_DATA_FOR_DCT d16, d17, d18, d19, d20, d21, d22, d23, r1, r3
vsubl.u8 q0, d16, d20
vsubl.u8 q1, d17, d21
vsubl.u8 q2, d18, d22
vsubl.u8 q3, d19, d23
MATRIX_TRANSFORM_EACH_16BITS q0, q1, q2, q3
// horizontal transform
DCT_ROW_TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
// transform element
MATRIX_TRANSFORM_EACH_16BITS q0, q1, q2, q3
// vertical transform
DCT_ROW_TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
vswp d1, d2
vswp d5, d6
vswp q1, q2
vst1.s16 {q0, q1}, [r0]!
vst1.s16 {q2, q3}, [r0]!
////////////////
LOAD_8x8_DATA_FOR_DCT d16, d17, d18, d19, d20, d21, d22, d23, r1, r3
vsubl.u8 q0, d16, d20
vsubl.u8 q1, d17, d21
vsubl.u8 q2, d18, d22
vsubl.u8 q3, d19, d23
MATRIX_TRANSFORM_EACH_16BITS q0, q1, q2, q3
// horizontal transform
DCT_ROW_TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
// transform element
MATRIX_TRANSFORM_EACH_16BITS q0, q1, q2, q3
// vertical transform
DCT_ROW_TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
vswp d1, d2
vswp d5, d6
vswp q1, q2
vst1.s16 {q0, q1}, [r0]!
vst1.s16 {q2, q3}, [r0]!
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsQuant4x4_neon
vld1.s16 {q2}, [r1]
vld1.s16 {q0, q1}, [r0]
vld1.s16 {q3}, [r2]
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q0, q2, d4, d5, d6, d7, q9, q10, q11
vst1.s16 {q2}, [r0]!
NEWQUANT_COEF_EACH_16BITS q1, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r0]!
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsQuant4x4Dc_neon
vld1.s16 {q0, q1}, [r0]
vdup.s16 q2, r1 // even ff range [0, 768]
vdup.s16 q3, r2
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q0, q2, d4, d5, d6, d7, q9, q10, q11
vst1.s16 {q2}, [r0]!
NEWQUANT_COEF_EACH_16BITS q1, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r0]!
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsQuantFour4x4_neon
vld1.s16 {q2}, [r1]
vld1.s16 {q3}, [r2]
mov r1, r0
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q0, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q1, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q0, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q1, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q0, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q1, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q0, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS q1, q8, d16, d17, d6, d7, q9, q10, q11
vst1.s16 {q8}, [r1]!
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsQuantFour4x4Max_neon
vld1.s16 {q2}, [r1]
vld1.s16 {q3}, [r2]
mov r1, r0
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS_MAX q0, q8, d16, d17, d6, d7, q9, q10, q11, d26
vst1.s16 {q8}, [r1]!
vmov q12, q2
NEWQUANT_COEF_EACH_16BITS_MAX q1, q12, d24, d25, d6, d7, q9, q10, q11, d28
vst1.s16 {q12}, [r1]! // then 1st 16 elem in d26 & d28
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS_MAX q0, q8, d16, d17, d6, d7, q9, q10, q11, d27
vst1.s16 {q8}, [r1]!
vmov q12, q2
NEWQUANT_COEF_EACH_16BITS_MAX q1, q12, d24, d25, d6, d7, q9, q10, q11, d29
vst1.s16 {q12}, [r1]! // then 2nd 16 elem in d27 & d29
SELECT_MAX_IN_ABS_COEF q13, q14, q0, d0, d1
vst1.s32 {d0[0]}, [r3]!
///////////
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS_MAX q0, q8, d16, d17, d6, d7, q9, q10, q11, d26
vst1.s16 {q8}, [r1]!
vmov q12, q2
NEWQUANT_COEF_EACH_16BITS_MAX q1, q12, d24, d25, d6, d7, q9, q10, q11, d28
vst1.s16 {q12}, [r1]! // then 3rd 16 elem in d26 & d28
vld1.s16 {q0, q1}, [r0]!
vmov q8, q2
NEWQUANT_COEF_EACH_16BITS_MAX q0, q8, d16, d17, d6, d7, q9, q10, q11, d27
vst1.s16 {q8}, [r1]!
vmov q12, q2
NEWQUANT_COEF_EACH_16BITS_MAX q1, q12, d24, d25, d6, d7, q9, q10, q11, d29
vst1.s16 {q12}, [r1]! // then 4th 16 elem in d27 & d29
SELECT_MAX_IN_ABS_COEF q13, q14, q0, d0, d1
vst1.s32 {d0[0]}, [r3]!
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsHadamardT4Dc_neon
push {r2,r3}
mov r2, #64 // 2*16*sizeof(int16_t)
add r3, r1, #32
vld1.s16 {d0}, [r1], r2
vld1.s16 {d1}, [r3], r2
vld1.s16 {d4}, [r1], r2
vld1.s16 {d5}, [r3], r2
vld1.s16 {d2}, [r1], r2
vld1.s16 {d3}, [r3], r2
vld1.s16 {d6}, [r1], r2
vld1.s16 {d7}, [r3], r2
vtrn.16 q0, q2 // d0[0 4], d1[1 5]
vtrn.16 q1, q3 // d2[2 6], d3[3 7]
vld1.s16 {d16}, [r1], r2
vld1.s16 {d17}, [r3], r2
vld1.s16 {d20}, [r1], r2
vld1.s16 {d21}, [r3], r2
vld1.s16 {d18}, [r1], r2
vld1.s16 {d19}, [r3], r2
vld1.s16 {d22}, [r1], r2
vld1.s16 {d23}, [r3], r2
vtrn.16 q8, q10 //d16[08 12],d17[09 13]
vtrn.16 q9, q11 //d18[10 14],d19[11 15]
vtrn.32 q0, q8 // d0 [0 4 08 12] = dct[idx], d1[1 5 09 13] = dct[idx+16]
vtrn.32 q1, q9 // d2 [2 6 10 14] = dct[idx+64], d3[3 7 11 15] = dct[idx+80]
ROW_TRANSFORM_0_STEP d0, d1, d3, d2, q8, q11, q10, q9
TRANSFORM_4BYTES q0, q1, q3, q2, q8, q11, q10, q9
// transform element 32bits
vtrn.s32 q0, q1 //[0 1 2 3]+[4 5 6 7]-->[0 4 2 6]+[1 5 3 7]
vtrn.s32 q2, q3 //[8 9 10 11]+[12 13 14 15]-->[8 12 10 14]+[9 13 11 15]
vswp d1, d4 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14]
vswp d3, d6 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15]
COL_TRANSFORM_0_STEP q0, q1, q3, q2, q8, q11, q10, q9
TRANSFORM_4BYTES q0, q1, q3, q2, q8, q11, q10, q9
vrshrn.s32 d16, q0, #1
vrshrn.s32 d17, q1, #1
vrshrn.s32 d18, q2, #1
vrshrn.s32 d19, q3, #1
vst1.16 {q8, q9}, [r0] //store
pop {r2,r3}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsHadamardQuant2x2_neon
vdup.s16 d1, r1 //ff
vdup.s16 d2, r2 //mf
veor d3, d3
mov r1, #32
mov r2, r0
vld1.s16 {d0[0]}, [r0], r1 //rs[00]
vst1.s16 {d3[0]}, [r2], r1 //rs[00]=0
vld1.s16 {d0[1]}, [r0], r1 //rs[16]
vst1.s16 {d3[0]}, [r2], r1 //rs[16]=0
vld1.s16 {d0[2]}, [r0], r1 //rs[32]
vst1.s16 {d3[0]}, [r2], r1 //rs[32]=0
vld1.s16 {d0[3]}, [r0], r1 //rs[48]
vst1.s16 {d3[0]}, [r2], r1 //rs[48]=0
HDM_QUANT_2x2_TOTAL_16BITS d0, d4, d5 // output d5
HDM_QUANT_2x2_TOTAL_16BITS d5, d4, d0 // output d0
QUANT_DUALWORD_COEF_EACH_16BITS d0, d1, d2, d3, q2
vst1.s16 d1, [r3] // store to dct
ldr r2, [sp, #0]
vst1.s16 d1, [r2] // store to block
mov r1, #1
vdup.s16 d3, r1
DC_ZERO_COUNT_IN_DUALWORD d1, d0, d3
vmov r0, r1, d0
and r0, #0x07 // range [0~4]
rsb r0, #4
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsHadamardQuant2x2SkipKernel_neon
vdup.s16 d3, r1
mov r1, #32
vld1.s16 {d0[0]}, [r0], r1 //rs[00]
vld1.s16 {d0[1]}, [r0], r1 //rs[16]
vld1.s16 {d0[2]}, [r0], r1 //rs[32]
vld1.s16 {d0[3]}, [r0], r1 //rs[48]
HDM_QUANT_2x2_TOTAL_16BITS d0, d1, d2 // output d2
HDM_QUANT_2x2_TOTAL_16BITS d2, d1, d0 // output d0
vabs.s16 d1, d0
vcgt.s16 d1, d1, d3 // abs(dct[i])>threshold;
vmov r0, r1, d1
orr r0, r1
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsGetNoneZeroCount_neon
push {r1}
vld1.s16 {q0, q1}, [r0]
vmov.s16 q8, #1
ZERO_COUNT_IN_2_QUARWORD q0, q1, q8, d0, d1, d2, d3
vmov r0, r1, d0
and r0, #0x1F // range [0~16]
rsb r0, #16
pop {r1}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDequant4x4_neon
vld1.s16 {q0, q1}, [r0]
vld1.u16 {q2}, [r1]
vmul.s16 q8, q0, q2
vmul.s16 q9, q1, q2
vst1.s16 {q8, q9}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDequantFour4x4_neon
vld1.u16 {q12}, [r1]
mov r1, r0
vld1.s16 {q0, q1}, [r0]!
vld1.s16 {q2, q3}, [r0]!
vmul.s16 q0, q0, q12
vld1.s16 {q8, q9}, [r0]!
vmul.s16 q1, q1, q12
vld1.s16 {q10, q11}, [r0]!
vst1.s16 {q0, q1}, [r1]!
vmul.s16 q2, q2, q12
vmul.s16 q3, q3, q12
vmul.s16 q8, q8, q12
vst1.s16 {q2, q3}, [r1]!
vmul.s16 q9, q9, q12
vmul.s16 q10, q10, q12
vmul.s16 q11, q11, q12
vst1.s16 {q8, q9}, [r1]!
vst1.s16 {q10, q11}, [r1]!
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDequantIHadamard4x4_neon
vld1.s16 {q0, q1}, [r0]
vdup.s16 q8, r1
IHDM_4x4_TOTAL_16BITS q0, q2, q3
IHDM_4x4_TOTAL_16BITS q1, q2, q3
MATRIX_TRANSFORM_EACH_16BITS d0, d1, d2, d3
IHDM_4x4_TOTAL_16BITS q0, q2, q3
vmul.s16 q0, q8
IHDM_4x4_TOTAL_16BITS q1, q2, q3
vmul.s16 q1, q8
MATRIX_TRANSFORM_EACH_16BITS d0, d1, d2, d3
vst1.s16 {q0, q1}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIDctT4Rec_neon
vld1.u32 {d16[0]}, [r2], r3
push {r4}
ldr r4, [sp, #4]
vld1.u32 {d16[1]}, [r2], r3
vld4.s16 {d0, d1, d2, d3}, [r4] // cost 3 cycles!
vld1.u32 {d17[0]}, [r2], r3
vld1.u32 {d17[1]}, [r2], r3 // q7 is pred
ROW_TRANSFORM_1_STEP_TOTAL_16BITS d0, d1, d2, d3, d4, d5, d6, d7
TRANSFORM_TOTAL_16BITS d0, d1, d2, d3, d4, d5, d6, d7
MATRIX_TRANSFORM_EACH_16BITS d0, d1, d2, d3
ROW_TRANSFORM_1_STEP_TOTAL_16BITS d0, d1, d2, d3, d4, d5, d6, d7
TRANSFORM_TOTAL_16BITS d0, d1, d2, d3, d4, d5, d6, d7
vrshr.s16 d0, d0, #6
vrshr.s16 d1, d1, #6
vrshr.s16 d2, d2, #6
vrshr.s16 d3, d3, #6
//after rounding 6, clip into [0, 255]
vmovl.u8 q2,d16
vadd.s16 q0,q2
vqmovun.s16 d16,q0
vst1.32 {d16[0]},[r0],r1
vst1.32 {d16[1]},[r0],r1
vmovl.u8 q2,d17
vadd.s16 q1,q2
vqmovun.s16 d17,q1
vst1.32 {d17[0]},[r0],r1
vst1.32 {d17[1]},[r0]
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIDctFourT4Rec_neon
vld1.u64 {d24}, [r2], r3
push {r4}
ldr r4, [sp, #4]
vld1.u64 {d25}, [r2], r3
vld4.s16 {d0, d1, d2, d3}, [r4]! // cost 3 cycles!
vld1.u64 {d26}, [r2], r3
vld1.u64 {d27}, [r2], r3
vld4.s16 {d4, d5, d6, d7}, [r4]! // cost 3 cycles!
vswp d1, d4
vswp d3, d6
vswp q1, q2 // q0~q3
ROW_TRANSFORM_1_STEP_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
MATRIX_TRANSFORM_EACH_16BITS q0, q1, q2, q3
ROW_TRANSFORM_1_STEP_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
vrshr.s16 q0, q0, #6
vrshr.s16 q1, q1, #6
vrshr.s16 q2, q2, #6
vrshr.s16 q3, q3, #6
//after rounding 6, clip into [0, 255]
vmovl.u8 q8,d24
vadd.s16 q0,q8
vqmovun.s16 d24,q0
vst1.u8 {d24},[r0],r1
vmovl.u8 q8,d25
vadd.s16 q1,q8
vqmovun.s16 d25,q1
vst1.u8 {d25},[r0],r1
vmovl.u8 q8,d26
vadd.s16 q2,q8
vqmovun.s16 d26,q2
vst1.u8 {d26},[r0],r1
vmovl.u8 q8,d27
vadd.s16 q3,q8
vqmovun.s16 d27,q3
vst1.u8 {d27},[r0],r1
vld1.u64 {d24}, [r2], r3
vld1.u64 {d25}, [r2], r3
vld4.s16 {d0, d1, d2, d3}, [r4]! // cost 3 cycles!
vld1.u64 {d26}, [r2], r3
vld1.u64 {d27}, [r2], r3
vld4.s16 {d4, d5, d6, d7}, [r4]! // cost 3 cycles!
vswp d1, d4
vswp d3, d6
vswp q1, q2 // q0~q3
ROW_TRANSFORM_1_STEP_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
MATRIX_TRANSFORM_EACH_16BITS q0, q1, q2, q3
ROW_TRANSFORM_1_STEP_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
TRANSFORM_TOTAL_16BITS q0, q1, q2, q3, q8, q9, q10, q11
vrshr.s16 q0, q0, #6
vrshr.s16 q1, q1, #6
vrshr.s16 q2, q2, #6
vrshr.s16 q3, q3, #6
//after rounding 6, clip into [0, 255]
vmovl.u8 q8,d24
vadd.s16 q0,q8
vqmovun.s16 d24,q0
vst1.u8 {d24},[r0],r1
vmovl.u8 q8,d25
vadd.s16 q1,q8
vqmovun.s16 d25,q1
vst1.u8 {d25},[r0],r1
vmovl.u8 q8,d26
vadd.s16 q2,q8
vqmovun.s16 d26,q2
vst1.u8 {d26},[r0],r1
vmovl.u8 q8,d27
vadd.s16 q3,q8
vqmovun.s16 d27,q3
vst1.u8 {d27},[r0],r1
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIDctRecI16x16Dc_neon
push {r4}
ldr r4, [sp, #4]
vld1.s16 {q8,q9}, [r4]
vrshr.s16 q8, q8, #6
vrshr.s16 q9, q9, #6
vdup.s16 d20, d16[0]
vdup.s16 d21, d16[1]
vdup.s16 d22, d16[2]
vdup.s16 d23, d16[3]
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vdup.s16 d20, d17[0]
vdup.s16 d21, d17[1]
vdup.s16 d22, d17[2]
vdup.s16 d23, d17[3]
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vdup.s16 d20, d18[0]
vdup.s16 d21, d18[1]
vdup.s16 d22, d18[2]
vdup.s16 d23, d18[3]
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vdup.s16 d20, d19[0]
vdup.s16 d21, d19[1]
vdup.s16 d22, d19[2]
vdup.s16 d23, d19[3]
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
vld1.u8 {q0}, [r2], r3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP d0, d1, q10, q11, q12, q13
vst1.u8 {q0}, [r0], r1
pop {r4}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 8,888 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm/svc_motion_estimation.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
WELS_ASM_FUNC_BEGIN SumOf8x8SingleBlock_neon
vld1.64 {d0}, [r0], r1
vld1.64 {d1}, [r0], r1
vld1.64 {d2}, [r0], r1
vld1.64 {d3}, [r0], r1
vld1.64 {d4}, [r0], r1
vld1.64 {d5}, [r0], r1
vld1.64 {d6}, [r0], r1
vld1.64 {d7}, [r0]
vpaddl.u8 q0, q0
vpadal.u8 q0, q1
vpadal.u8 q0, q2
vpadal.u8 q0, q3
vpaddl.u16 q0, q0
vpadd.i32 d0, d1
vpadd.i32 d0, d0
vmov r0, r1, d0
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN SumOf16x16SingleBlock_neon
vld1.64 {q0}, [r0], r1
vpaddl.u8 q0, q0
.rept 15
vld1.64 {q1}, [r0], r1
vpadal.u8 q0, q1
.endr
vpaddl.u16 q0, q0
vpadd.i32 d0, d1
vpadd.i32 d0, d0
vmov r0, r1, d0
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN SumOf8x8BlockOfFrame_neon
//(uint8_t* pRefPicture, const int32_t kiWidth, const int32_t kiHeight,const int32_t kiRefStride,uint16_t* pFeatureOfBlock, uint32_t pTimesOfFeatureValue[])
stmdb sp!, {r4-r12}
ldr r5, [sp, #40] //pTimesOfFeatureValue
ldr r4, [sp, #36] //pFeatureOfBlock
mov r8, r0
mov r6, r1
add r8, r6
add r4, r4, r6, lsl #1
mov r7, r6
_width_loop8x8_1:
subs r0, r8, r7
vld1.64 {d0}, [r0], r3
vld1.64 {d1}, [r0], r3
vld1.64 {d2}, [r0], r3
vld1.64 {d3}, [r0], r3
vld1.64 {d4}, [r0], r3
vld1.64 {d5}, [r0], r3
vld1.64 {d6}, [r0], r3
vld1.64 {d7}, [r0]
vpaddl.u8 q0, q0
vpadal.u8 q0, q1
vpadal.u8 q0, q2
vpadal.u8 q0, q3
vpaddl.u16 q0, q0
vpadd.i32 d0, d1
vpadd.i32 d0, d0
subs r1, r4, r7, lsl #1
vst1.16 {d0[0]}, [r1] // sum -> pFeatureOfBlock[i]
vmov r0, r1, d0
add r1, r5, r0, lsl #2
ldr r0, [r1]
add r0, #1
str r0, [r1]
subs r7, #1
bne _width_loop8x8_1
add r8, r3
add r4, r4, r6, lsl #1
subs r2, #1
beq _SumOf8x8BlockOfFrame_end
_height_loop8x8:
mov r7, r6
_width_loop8x8_2:
subs r0, r8, r7
subs r1, r4, r7, lsl #1
subs r9, r1, r6, lsl #1 // last line of pFeatureOfBlock[i]
ldrh r10, [r9] // sum of last line of pFeatureOfBlock[i]
subs r11, r0, r3
vld1.64 {d1}, [r11]
add r0, r11, r3, lsl #3
vld1.64 {d0}, [r0] //
vpaddl.u8 q0, q0
vpadd.u16 d0, d0, d1
vpaddl.u16 d0, d0
vmov r11, r12, d0
subs r10, r12
add r0, r10, r11
strh r0, [r1] // sum -> pFeatureOfBlock[i]
add r1, r5, r0, lsl #2
ldr r0, [r1]
add r0, #1
str r0, [r1]
subs r7, #1
bne _width_loop8x8_2
add r8, r3
add r4, r4, r6, lsl #1
subs r2, #1
bne _height_loop8x8
_SumOf8x8BlockOfFrame_end:
ldmia sp!, {r4-r12}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN SumOf16x16BlockOfFrame_neon
//(uint8_t* pRefPicture, const int32_t kiWidth, const int32_t kiHeight,const int32_t kiRefStride,uint16_t* pFeatureOfBlock, uint32_t pTimesOfFeatureValue[])
stmdb sp!, {r4-r12}
ldr r5, [sp, #40] //pTimesOfFeatureValue
ldr r4, [sp, #36] //pFeatureOfBlock
mov r8, r0
mov r6, r1
add r8, r6
add r4, r4, r6, lsl #1
mov r7, r6
_width_loop16x16_1:
subs r0, r8, r7
vld1.64 {q0}, [r0], r3
vpaddl.u8 q0, q0
.rept 15
vld1.64 {q1}, [r0], r3
vpadal.u8 q0, q1
.endr
vpaddl.u16 q0, q0
vpadd.i32 d0, d1
vpadd.i32 d0, d0
subs r1, r4, r7, lsl #1
vst1.16 {d0[0]}, [r1] // sum -> pFeatureOfBlock[i]
vmov r0, r1, d0
add r1, r5, r0, lsl #2
ldr r0, [r1]
add r0, #1
str r0, [r1]
subs r7, #1
bne _width_loop16x16_1
add r8, r3
add r4, r4, r6, lsl #1
subs r2, #1
beq _SumOf16x16BlockOfFrame_neon_end
_height_loop16x16:
mov r7, r6
_width_loop16x16_2:
subs r0, r8, r7
subs r1, r4, r7, lsl #1
subs r9, r1, r6, lsl #1 // last line of pFeatureOfBlock[i]
ldrh r10, [r9] // sum of last line of pFeatureOfBlock[i]
subs r11, r0, r3
vld1.64 {q1}, [r11]
add r0, r11, r3, lsl #4
vld1.64 {q0}, [r0] //
vpaddl.u8 q0, q0
vpaddl.u8 q1, q1
vpadd.u16 d0, d0, d1
vpadd.u16 d1, d2, d3
vpadd.u16 d0, d0, d1
vpaddl.u16 d0, d0
vmov r11, r12, d0
subs r10, r12
add r0, r10, r11
strh r0, [r1] // sum -> pFeatureOfBlock[i]
add r1, r5, r0, lsl #2
ldr r0, [r1]
add r0, #1
str r0, [r1]
subs r7, #1
bne _width_loop16x16_2
add r8, r3
add r4, r4, r6, lsl #1
subs r2, #1
bne _height_loop16x16
_SumOf16x16BlockOfFrame_neon_end:
ldmia sp!, {r4-r12}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN InitializeHashforFeature_neon
// (uint32_t* pTimesOfFeatureValue, uint16_t* pBuf, const int32_t kiListSize, uint16_t** pLocationOfFeature, uint16_t** pFeatureValuePointerList);
stmdb sp!, {r4-r7}
ldr r4, [sp, #16] //pFeatureValuePointerList
bic r5, r2, #3
_hash_assign_loop_x4:
vld1.64 {q0}, [r0]!
vshl.u32 q0, q0, #2
vceq.u32 q1, q0, #0
vand.i32 d2, d2, d3
vmov r6, r7, d2
and r6, r6, r7
cmp r6, #0xffffffff
beq _hash_assign_with_copy_x4
veor q1, q1
vext.32 q2, q1, q0, #3
vext.32 q3, q1, q0, #2
vext.32 q4, q1, q0, #1
vadd.u32 q0, q0, q2
vadd.u32 q0, q0, q3
vadd.u32 q0, q0, q4
vext.32 q2, q1, q0, #3
vdup.32 q3, r1
vadd.u32 q2, q2, q3
vst1.64 {q2}, [r3]!
vst1.64 {q2}, [r4]!
vmov.32 r6, d1[1]
add r1, r1, r6
b _assign_next
_hash_assign_with_copy_x4:
vdup.32 q2, r1
vst1.64 {q2}, [r3]!
vst1.64 {q2}, [r4]!
_assign_next:
subs r5, r5, #4
bne _hash_assign_loop_x4
and r5, r2, #3
cmp r5, #0
beq _hash_assign_end
_hash_assign_loop_x4_rem:
str r1, [r3], #4
str r1, [r4], #4
ldr r7, [r0], #4
lsl r7, r7, #2
add r1, r1, r7
subs r5, r5, #1
bne _hash_assign_loop_x4_rem
_hash_assign_end:
ldmia sp!, {r4-r7}
WELS_ASM_FUNC_END
.align 4
mv_x_inc_x4: .short 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00
mv_y_inc_x4: .short 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00
mx_x_offset_x4: .short 0x00, 0x04, 0x08, 0x0c, 0x00, 0x00, 0x00, 0x00
WELS_ASM_FUNC_BEGIN FillQpelLocationByFeatureValue_neon
// void (uint16_t* pFeatureOfBlock, const int32_t kiWidth, const int32_t kiHeight, uint16_t** pFeatureValuePointerList)
stmdb sp!, {r4-r8}
vpush {q4-q7}
adr r7, mv_x_inc_x4
vld1.64 {q7}, [r7]
adr r7, mv_y_inc_x4
vld1.64 {q6}, [r7]
adr r7, mx_x_offset_x4
vld1.64 {q5}, [r7]
veor q4, q4
veor q3, q3
vdup.32 q8, r3
_hash_height_loop:
mov r7, r1
vmov q2, q5 //mx_x_offset_x4
_hash_width_loop:
vld1.64 {d0}, [r0]!
vshll.u16 q0, d0, #2
vadd.u32 q0, q8
vmov q1, q2
vmov q4, q3
vzip.16 q1, q4
vmov.32 r4, d0[0]
ldr r5, [r4]
vmov.32 r6, d2[0]
str r6, [r5]
add r5, r5, #4
pld [r5] // cache miss?
str r5, [r4]
vmov.32 r4, d0[1]
ldr r5, [r4]
vmov.32 r6, d2[1]
str r6, [r5]
add r5, r5, #4
pld [r5] // cache miss?
str r5, [r4]
vmov.32 r4, d1[0]
ldr r5, [r4]
vmov.32 r6, d3[0]
str r6, [r5]
add r5, r5, #4
pld [r5] // cache miss?
str r5, [r4]
vmov.32 r4, d1[1]
ldr r5, [r4]
vmov.32 r6, d3[1]
str r6, [r5]
add r5, r5, #4
pld [r5] // cache miss?
str r5, [r4]
vadd.u16 q2, q2, q7
subs r7, #4
bne _hash_width_loop
vadd.u16 q3, q3, q6
subs r2, #1
bne _hash_height_loop
vpop {q4-q7}
ldmia sp!, {r4-r8}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 19,200 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm/intra_pred_sad_3_opt_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
//The data sequence will be used
.macro GET_8BYTE_DATA_L0 arg0, arg1, arg2
vld1.8 {\arg0[0]}, [\arg1], \arg2
vld1.8 {\arg0[1]}, [\arg1], \arg2
vld1.8 {\arg0[2]}, [\arg1], \arg2
vld1.8 {\arg0[3]}, [\arg1], \arg2
vld1.8 {\arg0[4]}, [\arg1], \arg2
vld1.8 {\arg0[5]}, [\arg1], \arg2
vld1.8 {\arg0[6]}, [\arg1], \arg2
vld1.8 {\arg0[7]}, [\arg1], \arg2
.endm
.macro HDM_TRANSFORM_4X4_L0 arg0, arg1, arg2,arg3, arg4, arg5, arg6, arg7, arg8
//Do the vertical transform
vaddl.u8 q0, \arg0, \arg1 //{0,4,8,12,1,5,9,13}
vsubl.u8 q1, \arg0, \arg1 //{2,6,10,14,3,7,11,15}
vswp d1, d2
vadd.s16 q2, q0, q1 //{0,1,2,3,4,5,6,7}
vsub.s16 q1, q0, q1 //{12,13,14,15,8,9,10,11}
//Do the horizontal transform
vtrn.32 q2, q1
vadd.s16 q0, q2, q1
vsub.s16 q1, q2, q1
vtrn.16 q0, q1
vadd.s16 q2, q0, q1
vsub.s16 q1, q0, q1
vmov.s16 d0, d4
vmov.s16 d1, d2
vabs.s16 d3, d3
//16x16_v
vtrn.32 d0, d1 //{0,1,3,2}
vaba.s16 \arg5, d0, \arg2 //16x16_v
vaba.s16 \arg5, d1, \arg8
vaba.s16 \arg5, d5, \arg8
vadd.u16 \arg5, d3
//16x16_h
vtrn.16 d4, d5 //{0,4,12,8}
vaba.s16 \arg6, d4, \arg3 //16x16_h
vabs.s16 d2, d2
vabs.s16 d5, d5
vadd.u16 d2, d3
vadd.u16 d2, d5
vadd.u16 \arg6, d2
//16x16_dc_both
vaba.s16 \arg7, d4, \arg4 //16x16_dc_both
vadd.u16 \arg7, d2
.endm
WELS_ASM_FUNC_BEGIN WelsIntra16x16Combined3Satd_neon
stmdb sp!, {r4-r7, lr}
vpush {q4-q7}
//Get the top line data to 'q15'(16 bytes)
sub r7, r0, r1
vld1.8 {q15}, [r7]
//Get the left colume data to 'q14' (16 bytes)
sub r7, r0, #1
GET_8BYTE_DATA_L0 d28, r7, r1
GET_8BYTE_DATA_L0 d29, r7, r1
//Calculate the mean value and save to 'q13->d27(reserve the d26)' (2 bytes)
//Calculate the 16x16_dc_both mode SATD
vaddl.u8 q0, d30, d31
vaddl.u8 q1, d28, d29
vadd.u16 q0, q1
vadd.u16 d0, d1
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
//Calculate the mean value
vrshr.u16 d0, #5
vshl.u16 d27, d0, #4
//Calculate the 16x16_v mode SATD and save to "q11, 12"
vshll.u8 q0, d30, #2
vshll.u8 q1, d31, #2
vtrn.32 q0, q1
vadd.s16 q2, q0, q1
vsub.s16 q1, q0, q1
vtrn.16 q2, q1
vadd.s16 q12, q2, q1
vsub.s16 q11, q2, q1
vtrn.32 q12, q11 //{0,1,3,2, 4,5,7,6} q12
//{8,9,11,10, 12,13,15,14} q11
//Calculate the 16x16_h mode SATD and save to "q9, q10"
vshll.u8 q0, d28, #2
vshll.u8 q1, d29, #2
vtrn.32 q0, q1
vadd.s16 q2, q0, q1
vsub.s16 q1, q0, q1
vtrn.16 q2, q1
vadd.s16 q10, q2, q1
vsub.s16 q9, q2, q1
vtrn.32 q10, q9 //{0,1,3,2, 4,5,7,6} q10
//{8,9,11,10, 12,13,15,14} q9
vmov.i32 d17, #0//Save the SATD of DC_BOTH
vmov.i32 d16, #0//Save the SATD of H
vmov.i32 d15, #0//Save the SATD of V
vmov.i32 d14, #0//For zero D register
//Load the p_enc data and save to "q3 ~ q6"--- 16X4 bytes
vld1.32 {q3}, [r2], r3
vld1.32 {q4}, [r2], r3
vld1.32 {q5}, [r2], r3
vld1.32 {q6}, [r2], r3
vtrn.32 q3, q4
vtrn.32 q5, q6
HDM_TRANSFORM_4X4_L0 d6, d10, d24, d20, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d7, d11, d22, d20, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d8, d12, d25, d20, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d9, d13, d23, d20, d27, d15, d16, d17, d14
//Load the p_enc data and save to "q3 ~ q6"--- 16X4 bytes
vld1.32 {q3}, [r2], r3
vld1.32 {q4}, [r2], r3
vld1.32 {q5}, [r2], r3
vld1.32 {q6}, [r2], r3
vtrn.32 q3, q4
vtrn.32 q5, q6
HDM_TRANSFORM_4X4_L0 d6, d10, d24, d21, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d7, d11, d22, d21, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d8, d12, d25, d21, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d9, d13, d23, d21, d27, d15, d16, d17, d14
//Load the p_enc data and save to "q3 ~ q6"--- 16X4 bytes
vld1.32 {q3}, [r2], r3
vld1.32 {q4}, [r2], r3
vld1.32 {q5}, [r2], r3
vld1.32 {q6}, [r2], r3
vtrn.32 q3, q4
vtrn.32 q5, q6
HDM_TRANSFORM_4X4_L0 d6, d10, d24, d18, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d7, d11, d22, d18, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d8, d12, d25, d18, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d9, d13, d23, d18, d27, d15, d16, d17, d14
//Load the p_enc data and save to "q3 ~ q6"--- 16X4 bytes
vld1.32 {q3}, [r2], r3
vld1.32 {q4}, [r2], r3
vld1.32 {q5}, [r2], r3
vld1.32 {q6}, [r2], r3
vtrn.32 q3, q4
vtrn.32 q5, q6
HDM_TRANSFORM_4X4_L0 d6, d10, d24, d19, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d7, d11, d22, d19, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d8, d12, d25, d19, d27, d15, d16, d17, d14
HDM_TRANSFORM_4X4_L0 d9, d13, d23, d19, d27, d15, d16, d17, d14
//Get the data from stack
ldr r5, [sp, #84] //the addr of Best_mode
ldr r6, [sp, #88] //the value of i_lambda
//vadd.u16 d24, d25
vrshr.u16 d15, #1
vpaddl.u16 d15, d15
vpaddl.u32 d15, d15
vmov.u32 r0, d15[0]
//vadd.u16 d22, d23
vrshr.u16 d16, #1
vpaddl.u16 d16, d16
vpaddl.u32 d16, d16
vmov.u32 r1, d16[0]
add r1, r1, r6, lsl #1
//vadd.u16 d20, d21
vrshr.u16 d17, #1
vpaddl.u16 d17, d17
vpaddl.u32 d17, d17
vmov.u32 r2, d17[0]
add r2, r2, r6, lsl #1
mov r4, #0
cmp r1, r0
movcc r0, r1
movcc r4, #1
cmp r2, r0
movcc r0, r2
movcc r4, #2
str r4, [r5]
vpop {q4-q7}
ldmia sp!, {r4-r7, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIntra16x16Combined3Sad_neon
stmdb sp!, {r4-r7, lr}
//Get the top line data to 'q15'(16 bytes)
sub r4, r0, r1
vld1.8 {q15}, [r4]
//Get the left colume data to 'q14' (16 bytes)
sub r4, r0, #1
GET_8BYTE_DATA_L0 d28, r4, r1
GET_8BYTE_DATA_L0 d29, r4, r1
//Calculate the mean value and save to 'q13' (8 bytes)
//Calculate the 16x16_dc_both mode SATD
vaddl.u8 q0, d30, d31
vaddl.u8 q1, d28, d29
vadd.u16 q0, q1
vadd.u16 d0, d1
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
//Calculate the mean value
vrshr.u16 d0, d0, #5
vdup.8 q13, d0[0]
sub r4, r0, #1
vmov.i32 q12, #0//Save the SATD of DC_BOTH
vmov.i32 q11, #0//Save the SATD of H
vmov.i32 q10, #0//Save the SATD of V
mov lr, #16
sad_intra_16x16_x3_opt_loop0:
//Get the left colume data to 'd0' (16 bytes)
vld1.8 {d0[]}, [r4], r1
//Load the p_enc data and save to "q1 ~ q2"--- 16X4 bytes
vld1.8 {q1}, [r2], r3
subs lr, #1
//Do the SAD for top colume
vabal.u8 q12, d30, d2
vabal.u8 q12, d31, d3
//Do the SAD for left colume
vabal.u8 q11, d0, d2
vabal.u8 q11, d0, d3
//Do the SAD for mean value
vabal.u8 q10, d26, d2
vabal.u8 q10, d26, d3
bne sad_intra_16x16_x3_opt_loop0
//Get the data from stack
ldr r5, [sp, #20] //the addr of Best_mode
ldr r6, [sp, #24] //the value of i_lambda
vadd.u16 d24, d25
vpaddl.u16 d24, d24
vpaddl.u32 d24, d24
vmov.u32 r0, d24[0]
vadd.u16 d22, d23
vpaddl.u16 d22, d22
vpaddl.u32 d22, d22
vmov.u32 r1, d22[0]
add r1, r1, r6, lsl #1
vadd.u16 d20, d21
vpaddl.u16 d20, d20
vpaddl.u32 d20, d20
vmov.u32 r2, d20[0]
add r2, r2, r6, lsl #1
mov r4, #0
cmp r1, r0
movcc r0, r1
movcc r4, #1
cmp r2, r0
movcc r0, r2
movcc r4, #2
str r4, [r5]
ldmia sp!, {r4-r7, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIntra8x8Combined3Sad_neon
stmdb sp!, {r4-r7, lr}
//Get the data from stack
ldr r4, [sp, #32] //p_dec_cr
ldr r5, [sp, #36] //p_enc_cr
//Get the left colume data to 'd28(cb), d30(cr)' (16 bytes)
sub r6, r0, #1
GET_8BYTE_DATA_L0 d28, r6, r1
sub r6, r4, #1
GET_8BYTE_DATA_L0 d30, r6, r1
//Get the top line data to 'd29(cb), d31(cr)'(16 bytes)
sub r6, r0, r1
vld1.8 {d29}, [r6]
sub r6, r4, r1
vld1.8 {d31}, [r6]
//Calculate the sum of left column and top row
vmov.i32 q0, q14
vpaddl.u8 q0, q0
vpaddl.u16 q0, q0
vadd.u32 d2, d0, d1 //'m1' save to d2
vrshr.u32 q0, q0, #2 //calculate 'm2','m3'
vrshr.u32 d2, d2, #3 //calculate 'm4'
//duplicate the 'mx' to a vector line
vdup.8 d27, d2[0]
vdup.8 d26, d1[4]
vtrn.32 d27, d26
vdup.8 d26, d0[4]
vdup.8 d25, d2[4]
vtrn.32 d26, d25 //Save to "d27, d26"
vmov.i32 q0, q15
vpaddl.u8 q0, q0
vpaddl.u16 q0, q0
vadd.u32 d2, d0, d1 //'m1' save to d2
vrshr.u32 q0, q0, #2 //calculate 'm2','m3'
vrshr.u32 d2, d2, #3 //calculate 'm4'
//duplicate the 'mx' to a vector line
vdup.8 d25, d2[0]
vdup.8 d24, d1[4]
vtrn.32 d25, d24
vdup.8 d24, d0[4]
vdup.8 d23, d2[4]
vtrn.32 d24, d23 //Save to "d25, d24"
vmov.i32 q11, #0//Save the SATD of DC_BOTH
vmov.i32 q10, #0//Save the SATD of H
vmov.i32 q9 , #0//Save the SATD of V
sub r6, r0, #1
sub r7, r4, #1
mov lr, #4
sad_intra_8x8_x3_opt_loop0:
//Load the p_enc data and save to "q1 ~ q2"--- 16X4 bytes
vld1.8 {d0}, [r2], r3
vld1.8 {d1}, [r5], r3
//Get the left colume data to 'd0' (16 bytes)
vld1.8 {d2[]}, [r6], r1
vld1.8 {d3[]}, [r7], r1
subs lr, #1
//Do the SAD for top colume
vabal.u8 q11, d29, d0
vabal.u8 q11, d31, d1
//Do the SAD for left colume
vabal.u8 q10, d2, d0
vabal.u8 q10, d3, d1
//Do the SAD for mean value
vabal.u8 q9, d27, d0
vabal.u8 q9, d25, d1
bne sad_intra_8x8_x3_opt_loop0
mov lr, #4
sad_intra_8x8_x3_opt_loop1:
//Load the p_enc data and save to "q1 ~ q2"--- 16X4 bytes
vld1.8 {d0}, [r2], r3
vld1.8 {d1}, [r5], r3
//Get the left colume data to 'd0' (16 bytes)
vld1.8 {d2[]}, [r6], r1
vld1.8 {d3[]}, [r7], r1
subs lr, #1
//Do the SAD for top colume
vabal.u8 q11, d29, d0
vabal.u8 q11, d31, d1
//Do the SAD for left colume
vabal.u8 q10, d2, d0
vabal.u8 q10, d3, d1
//Do the SAD for mean value
vabal.u8 q9, d26, d0
vabal.u8 q9, d24, d1
bne sad_intra_8x8_x3_opt_loop1
//Get the data from stack
ldr r5, [sp, #20] //the addr of Best_mode
ldr r6, [sp, #24] //the value of i_lambda
vadd.u16 d22, d23
vpaddl.u16 d22, d22
vpaddl.u32 d22, d22
vmov.u32 r0, d22[0]
add r0, r0, r6, lsl #1
vadd.u16 d20, d21
vpaddl.u16 d20, d20
vpaddl.u32 d20, d20
vmov.u32 r1, d20[0]
add r1, r1, r6, lsl #1
vadd.u16 d18, d19
vpaddl.u16 d18, d18
vpaddl.u32 d18, d18
vmov.u32 r2, d18[0]
mov r4, #2
cmp r1, r0
movcc r0, r1
movcc r4, #1
cmp r2, r0
movcc r0, r2
movcc r4, #0
str r4, [r5]
ldmia sp!, {r4-r7, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIntra8x8Combined3Satd_neon
stmdb sp!, {r4-r7, lr}
vpush {q4-q7}
//Get the data from stack
ldr r4, [sp, #96] //p_dec_cr
ldr r5, [sp, #100] //p_enc_cr
//Get the top line data to 'd29(cb), d31(cr)'(16 bytes)
sub r6, r0, r1
vld1.8 {d29}, [r6]
sub r6, r4, r1
vld1.8 {d31}, [r6]
//Get the left colume data to 'd28(cb), d30(cr)' (16 bytes)
sub r6, r0, #1
GET_8BYTE_DATA_L0 d28, r6, r1
sub r6, r4, #1
GET_8BYTE_DATA_L0 d30, r6, r1
//Calculate the 16x16_v mode SATD and save to "q12, 13"
vshll.u8 q0, d29, #2
vshll.u8 q1, d31, #2
vtrn.32 q0, q1
vadd.s16 q2, q0, q1
vsub.s16 q1, q0, q1
vtrn.16 q2, q1
vadd.s16 q13, q2, q1
vsub.s16 q12, q2, q1
vtrn.32 q13, q12 //{0,1,3,2, 4,5,7,6} q13
//{8,9,11,10, 12,13,15,14} q12
//Calculate the 16x16_h mode SATD and save to "q10, q11"
vshll.u8 q0, d28, #2
vshll.u8 q1, d30, #2
vtrn.32 q0, q1
vadd.s16 q2, q0, q1
vsub.s16 q1, q0, q1
vtrn.16 q2, q1
vadd.s16 q11, q2, q1
vsub.s16 q10, q2, q1
vtrn.32 q11, q10 //{0,1,3,2, 4,5,7,6} q11
//{8,9,11,10, 12,13,15,14} q10
//Calculate the sum of left column and top row
//vmov.i32 q0, q14
vpaddl.u8 q0, q14
vpaddl.u16 q0, q0
vadd.u32 d2, d0, d1
vpaddl.u8 q2, q15
vpaddl.u16 q2, q2
vadd.u32 d3, d4, d5
vtrn.32 q0, q2
vrshr.u32 q1, #3
vrshr.u32 q2, #2
vshll.u32 q9, d4, #4 // {2cb, 2cr} q9
vshll.u32 q8, d5, #4 // {1cb, 1cr} q8
vshll.u32 q7, d2, #4 // {0cb, 3cb} q7
vshll.u32 q6, d3, #4 // {0cr, 3cr} q6
vmov.i32 d28, #0//Save the SATD of DC_BOTH
vmov.i32 d10, #0//Save the SATD of H
vmov.i32 d11, #0//Save the SATD of V
vmov.i32 d30, #0//For zero D register
//Load the p_enc data and save to "q3 ~ q6"--- 16X4 bytes
vld1.32 {d6}, [r2], r3
vld1.32 {d7}, [r2], r3
vld1.32 {d8}, [r2], r3
vld1.32 {d9}, [r2], r3
vtrn.32 d6, d7
vtrn.32 d8, d9
HDM_TRANSFORM_4X4_L0 d6, d8, d26, d22, d14, d11, d10, d28, d30
HDM_TRANSFORM_4X4_L0 d7, d9, d27, d22, d16, d11, d10, d28, d30
vld1.32 {d6}, [r5], r3
vld1.32 {d7}, [r5], r3
vld1.32 {d8}, [r5], r3
vld1.32 {d9}, [r5], r3
vtrn.32 d6, d7
vtrn.32 d8, d9
HDM_TRANSFORM_4X4_L0 d6, d8, d24, d20, d12, d11, d10, d28, d30
HDM_TRANSFORM_4X4_L0 d7, d9, d25, d20, d17, d11, d10, d28, d30
//Load the p_enc data and save to "q3 ~ q6"--- 16X4 bytes
vld1.32 {d6}, [r2], r3
vld1.32 {d7}, [r2], r3
vld1.32 {d8}, [r2], r3
vld1.32 {d9}, [r2], r3
vtrn.32 d6, d7
vtrn.32 d8, d9
HDM_TRANSFORM_4X4_L0 d6, d8, d26, d23, d18, d11, d10, d28, d30
HDM_TRANSFORM_4X4_L0 d7, d9, d27, d23, d15, d11, d10, d28, d30
vld1.32 {d6}, [r5], r3
vld1.32 {d7}, [r5], r3
vld1.32 {d8}, [r5], r3
vld1.32 {d9}, [r5], r3
vtrn.32 d6, d7
vtrn.32 d8, d9
HDM_TRANSFORM_4X4_L0 d6, d8, d24, d21, d19, d11, d10, d28, d30
HDM_TRANSFORM_4X4_L0 d7, d9, d25, d21, d13, d11, d10, d28, d30
//Get the data from stack
ldr r5, [sp, #84] //the addr of Best_mode
ldr r6, [sp, #88] //the value of i_lambda
vrshr.u16 d11, #1
vpaddl.u16 d11, d11
vpaddl.u32 d11, d11
vmov.u32 lr, d11[0]
add lr, lr, r6, lsl #1
vrshr.u16 d10, #1
vpaddl.u16 d10, d10
vpaddl.u32 d10, d10
vmov.u32 r3, d10[0]
add r3, r3, r6, lsl #1
vrshr.u16 d28, #1
vpaddl.u16 d28, d28
vpaddl.u32 d28, d28
vmov.u32 r2, d28[0]
mov r6, #2
cmp r3, lr
movcc lr, r3
movcc r6, #1
cmp r2, lr
movcc lr, r2
movcc r6, #0
str r6, [r5]
mov r0, lr
vpop {q4-q7}
ldmia sp!, {r4-r7, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIntra4x4Combined3Satd_neon
stmdb sp!, {r4-r7, lr}
//Get the top line data to 'd31[0~3]'(4 bytes)
sub r7, r0, r1
vld1.32 {d31[0]}, [r7]
//Get the left colume data to 'd31[4~7]' (4 bytes)
sub r7, r0, #1
vld1.8 {d31[4]}, [r7], r1
vld1.8 {d31[5]}, [r7], r1
vld1.8 {d31[6]}, [r7], r1
vld1.8 {d31[7]}, [r7], r1
//Calculate the mean value and save to 'd30' (2 bytes)
vpaddl.u8 d0, d31
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
//Calculate the mean value
vrshr.u16 d0, #3
vshl.u16 d30, d0, #4
//Calculate the 16x16_v mode SATD and save to "d29"
//Calculate the 16x16_h mode SATD and save to "d28"
vshll.u8 q0, d31, #2
vtrn.32 d0, d1
vadd.s16 d2, d0, d1
vsub.s16 d1, d0, d1
vtrn.16 d2, d1
vadd.s16 d29, d2, d1
vsub.s16 d28, d2, d1
vtrn.32 d29, d28 //{0,1,3,2 top} d29
//{0,1,3,2 left} d28
vmov.i32 d27, #0//Save the SATD of DC_BOTH
vmov.i32 d26, #0//Save the SATD of H
vmov.i32 d25, #0//Save the SATD of V
vmov.i32 d24, #0//For zero D register
//Load the p_enc data and save to "d22,d23"--- 4X4 bytes
vld1.32 {d23[0]}, [r2], r3
vld1.32 {d23[1]}, [r2], r3
vld1.32 {d22[0]}, [r2], r3
vld1.32 {d22[1]}, [r2], r3
HDM_TRANSFORM_4X4_L0 d23, d22, d29, d28, d30, d25, d26, d27, d24
//Get the data from stack
ldr r5, [sp, #28] //the value of lambda2
ldr r6, [sp, #32] //the value of lambda1
ldr r7, [sp, #36] //the value of lambda0
vrshr.u16 d25, #1
vpaddl.u16 d25, d25
vpaddl.u32 d25, d25
vmov.u32 r0, d25[0]
add r0, r7
vrshr.u16 d26, #1
vpaddl.u16 d26, d26
vpaddl.u32 d26, d26
vmov.u32 r1, d26[0]
add r1, r6
vrshr.u16 d27, #1
vpaddl.u16 d27, d27
vpaddl.u32 d27, d27
vmov.u32 r2, d27[0]
add r2, r5
ldr r5, [sp, #20] //p_dst
ldr r6, [sp, #24] //the addr of Best_mode
mov r4, r0
cmp r1, r4
movcc r4, r1
cmp r2, r4
movcc r4, r2
//The compare sequence affect the resule
cmp r4, r2
bne satd_intra_4x4_x3_opt_jump0
mov r0, #2
str r0, [r6]
vshr.u32 d0, d30, #4 // {2cb, 2cr} q9
vdup.8 q1, d0[0]
vst1.8 {q1}, [r5]
//...
bl satd_intra_4x4_x3_opt_end
satd_intra_4x4_x3_opt_jump0:
cmp r4, r1
bne satd_intra_4x4_x3_opt_jump1
mov r0, #1
str r0, [r6]
vdup.8 d0, d31[4]
vdup.8 d1, d31[5]
vdup.8 d2, d31[6]
vdup.8 d3, d31[7]
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r5]
bl satd_intra_4x4_x3_opt_end
satd_intra_4x4_x3_opt_jump1:
mov r0, #0
str r0, [r6]
vst1.32 {d31[0]}, [r5]!
vst1.32 {d31[0]}, [r5]!
vst1.32 {d31[0]}, [r5]!
vst1.32 {d31[0]}, [r5]!
satd_intra_4x4_x3_opt_end:
mov r0, r4
ldmia sp!, {r4-r7, lr}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 18,374 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm/pixel_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro SATD_16x4
vld1.64 {q0}, [r0,:128], r1
vld1.64 {q1}, [r2], r3
vsubl.u8 q8, d0, d2
vld1.64 {q2}, [r0,:128], r1
vsubl.u8 q10, d1, d3
vld1.64 {q3}, [r2], r3
vsubl.u8 q9, d4, d6
vld1.64 {q0}, [r0,:128], r1
vsubl.u8 q11, d5, d7
vld1.64 {q1}, [r2], r3
vsubl.u8 q12, d0, d2
vld1.64 {q2}, [r0,:128], r1
vsubl.u8 q14, d1, d3
vadd.s16 q0, q8, q9
vld1.64 {q3}, [r2], r3
vsub.s16 q1, q8, q9
vsubl.u8 q13, d4, d6
vsubl.u8 q15, d5, d7
vadd.s16 q2, q12, q13
vsub.s16 q3, q12, q13
vadd.s16 q8, q10, q11
vsub.s16 q9, q10, q11
vadd.s16 q10, q14, q15
vsub.s16 q11, q14, q15
vadd.s16 q12, q0, q2
vsub.s16 q14, q0, q2
vadd.s16 q13, q8, q10
vsub.s16 q15, q8, q10
vsub.s16 q0, q1, q3
vadd.s16 q2, q1, q3
vsub.s16 q1, q9, q11
vadd.s16 q3, q9, q11
vtrn.16 q12, q14
vtrn.16 q13, q15
vadd.s16 q8, q12, q14
vabd.s16 q10, q12, q14
vadd.s16 q9, q13, q15
vabd.s16 q11, q13, q15
vabs.s16 q8, q8
vabs.s16 q9, q9
vtrn.16 q0, q2
vtrn.16 q1, q3
vadd.s16 q12, q0, q2
vabd.s16 q14, q0, q2
vadd.s16 q13, q1, q3
vabd.s16 q15, q1, q3
vabs.s16 q12, q12
vabs.s16 q13, q13
vtrn.32 q8, q10
vtrn.32 q9, q11
vtrn.32 q12, q14
vtrn.32 q13, q15
vmax.s16 q0, q8, q10
vmax.s16 q1, q9, q11
vmax.s16 q2, q12, q14
vmax.s16 q3, q13, q15
vadd.u16 q0, q0, q1
vadd.u16 q2, q2, q3
.endm
.macro SATD_8x4
vld1.64 {d0}, [r0,:64], r1
vld1.64 {d1}, [r2], r3
vld1.64 {d2}, [r0,:64], r1
vsubl.u8 q8, d0, d1
vld1.64 {d3}, [r2], r3
vsubl.u8 q9, d2, d3
vld1.64 {d4}, [r0,:64], r1
vld1.64 {d5}, [r2], r3
vadd.s16 q12, q8, q9
vsubl.u8 q10, d4, d5
vld1.64 {d6}, [r0,:64], r1
vld1.64 {d7}, [r2], r3
vsubl.u8 q11, d6, d7
vsub.s16 q13, q8, q9
vadd.s16 q14, q10, q11
vsub.s16 q15, q10, q11
vadd.s16 q0, q12, q14
vsub.s16 q1, q12, q14
vsub.s16 q2, q13, q15
vadd.s16 q3, q13, q15
vtrn.16 q0, q1
vtrn.16 q2, q3
vadd.s16 q8, q0, q1
vabd.s16 q9, q0, q1
vabs.s16 q8, q8
vadd.s16 q10, q2, q3
vabd.s16 q11, q2, q3
vabs.s16 q10, q10
vtrn.32 q8, q9
vtrn.32 q10, q11
vmax.s16 q0, q8, q9
vmax.s16 q1, q10, q11
.endm
.macro SAD_16x4
vld1.64 {q6}, [r0, :128], r1
vabal.u8 q10, d8, d10
vld1.64 {q7}, [r2], r3
vabal.u8 q11, d9, d11
vld1.64 {q0}, [r0, :128], r1
vabal.u8 q12, d12, d14
vld1.64 {q1}, [r2], r3
vabal.u8 q13, d13, d15
vld1.64 {q2}, [r0, :128], r1
vabal.u8 q10, d0, d2
vld1.64 {q3}, [r2], r3
vabal.u8 q11, d1, d3
vld1.64 {q4}, [r0, :128], r1
vabal.u8 q12, d4, d6
vld1.64 {q5}, [r2], r3
vabal.u8 q13, d5, d7
.endm
.macro SAD_8x4
vld1.64 {d0}, [r0, :64], r1
vld1.64 {d1}, [r2], r3
vabal.u8 q10, d0, d1
vld1.64 {d2}, [r0, :64], r1
vld1.64 {d3}, [r2], r3
vabal.u8 q11, d2, d3
vld1.64 {d4}, [r0, :64], r1
vld1.64 {d5}, [r2], r3
vabal.u8 q12, d4, d5
vld1.64 {d6}, [r0, :64], r1
vld1.64 {d7}, [r2], r3
vabal.u8 q13, d6, d7
.endm
WELS_ASM_FUNC_BEGIN WelsSampleSad16x16_neon
vpush {q4-q7}
vld1.64 {q0}, [r0, :128], r1
vld1.64 {q1}, [r2], r3
vabdl.u8 q10, d0, d2
vld1.64 {q2}, [r0, :128], r1
vabdl.u8 q11, d1, d3
vld1.64 {q3}, [r2], r3
vld1.64 {q4}, [r0, :128], r1
vabdl.u8 q12, d4, d6
vld1.64 {q5}, [r2], r3
vabdl.u8 q13, d5, d7
SAD_16x4
SAD_16x4
SAD_16x4
vld1.64 {q6}, [r0, :128], r1
vabal.u8 q10, d8, d10
vld1.64 {q7}, [r2], r3
vabal.u8 q11, d9, d11
vabal.u8 q12, d12, d14
vabal.u8 q13, d13, d15
vadd.u16 q14, q10, q11
vadd.u16 q15, q12, q13
vadd.u16 q15, q14, q15
vadd.u16 d0, d30, d31
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.u32 r0, d0[0]
vpop {q4-q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSad16x8_neon
vpush {q4-q7}
vld1.64 {q0}, [r0, :128], r1
vld1.64 {q1}, [r2], r3
vabdl.u8 q10, d0, d2
vld1.64 {q2}, [r0, :128], r1
vabdl.u8 q11, d1, d3
vld1.64 {q3}, [r2], r3
vld1.64 {q4}, [r0, :128], r1
vabdl.u8 q12, d4, d6
vld1.64 {q5}, [r2], r3
vabdl.u8 q13, d5, d7
SAD_16x4
vld1.64 {q6}, [r0, :128], r1
vabal.u8 q10, d8, d10
vld1.64 {q7}, [r2], r3
vabal.u8 q11, d9, d11
vabal.u8 q12, d12, d14
vabal.u8 q13, d13, d15
vadd.u16 q14, q10, q11
vadd.u16 q15, q12, q13
vadd.u16 q15, q14, q15
vadd.u16 d0, d30, d31
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.u32 r0, d0[0]
vpop {q4-q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSad8x16_neon
vld1.64 {d0}, [r0, :64], r1
vld1.64 {d1}, [r2], r3
vabdl.u8 q10, d0, d1
vld1.64 {d2}, [r0, :64], r1
vld1.64 {d3}, [r2], r3
vabdl.u8 q11, d2, d3
vld1.64 {d4}, [r0, :64], r1
vld1.64 {d5}, [r2], r3
vabdl.u8 q12, d4, d5
vld1.64 {d6}, [r0, :64], r1
vld1.64 {d7}, [r2], r3
vabdl.u8 q13, d6, d7
SAD_8x4
SAD_8x4
SAD_8x4
vadd.u16 q14, q10, q11
vadd.u16 q15, q12, q13
vadd.u16 q15, q15, q14
vadd.u16 d0, d30, d31
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.u32 r0, d0[0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSad8x8_neon
vld1.64 {d0}, [r0, :64], r1
vld1.64 {d1}, [r2], r3
vabdl.u8 q10, d0, d1
vld1.64 {d2}, [r0, :64], r1
vld1.64 {d3}, [r2], r3
vabdl.u8 q11, d2, d3
vld1.64 {d4}, [r0, :64], r1
vld1.64 {d5}, [r2], r3
vabdl.u8 q12, d4, d5
vld1.64 {d6}, [r0, :64], r1
vld1.64 {d7}, [r2], r3
vabdl.u8 q13, d6, d7
SAD_8x4
vadd.u16 q14, q10, q11
vadd.u16 q15, q12, q13
vadd.u16 q15, q15, q14
vadd.u16 d0, d30, d31
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.u32 r0, d0[0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSad4x4_neon
stmdb sp!, {r4-r5, lr}
//Loading a horizontal line data (4 bytes)
//line 0
ldr r4, [r0], r1
ldr r5, [r2], r3
usad8 lr, r4, r5
//line 1
ldr r4, [r0], r1
ldr r5, [r2], r3
usada8 lr, r4, r5, lr
//line 2
ldr r4, [r0], r1
ldr r5, [r2], r3
usada8 lr, r4, r5, lr
//line 3
ldr r4, [r0]
ldr r5, [r2]
usada8 r0, r4, r5, lr
ldmia sp!, {r4-r5, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSadFour16x16_neon
stmdb sp!, {r4-r5, lr}
//Generate the pix2 start addr
sub r4, r2, #1
add r5, r2, #1
sub r2, r3
//Loading a horizontal line data (16 bytes)
vld1.8 {q0}, [r0], r1 //save pix1
vld1.8 {q1}, [r2], r3 //save pix2 - stride
vld1.8 {q10}, [r2], r3 //save pix2
vld1.8 {q2}, [r2], r3 //save pix2 + stride
vld1.8 {q3}, [r4], r3 //save pix2 - 1
vld1.8 {q8}, [r5], r3 //save pix2 + 1
//Do the SAD for 16 bytes
vabdl.u8 q15, d0, d2
vabal.u8 q15, d1, d3
vabdl.u8 q13, d0, d4
vabal.u8 q13, d1, d5
vabdl.u8 q11, d0, d6
vabal.u8 q11, d1, d7
vabdl.u8 q9, d0, d16
vabal.u8 q9, d1, d17
mov lr, #15
pixel_sad_4_16x16_loop_0:
//Loading a horizontal line data (16 bytes)
vld1.8 {q0}, [r0], r1 //save pix1
vmov.8 q1, q10 //save pix2 - stride
vmov.8 q10, q2
vabal.u8 q15, d0, d2
vld1.8 {q2}, [r2], r3 //save pix2 + stride
vabal.u8 q15, d1, d3
vld1.8 {q3}, [r4], r3 //save pix2 - 1
vabal.u8 q13, d0, d4
vld1.8 {q8}, [r5], r3 //save pix2 + 1
vabal.u8 q13, d1, d5
subs lr, #1
vabal.u8 q11, d0, d6
vabal.u8 q11, d1, d7
vabal.u8 q9, d0, d16
vabal.u8 q9, d1, d17
bne pixel_sad_4_16x16_loop_0
//Save SAD to 'r0'
ldr r0, [sp, #12]
vadd.u16 d0, d30, d31
vadd.u16 d1, d26, d27
vadd.u16 d2, d22, d23
vadd.u16 d3, d18, d19
vpaddl.u16 q0, q0
vpaddl.u16 q1, q1
vpaddl.u32 q0, q0
vpaddl.u32 q1, q1
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
ldmia sp!, {r4-r5, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSadFour16x8_neon
stmdb sp!, {r4-r5, lr}
//Generate the pix2 start addr
sub r4, r2, #1
add r5, r2, #1
sub r2, r3
//Loading a horizontal line data (16 bytes)
vld1.8 {q0}, [r0], r1 //save pix1
vld1.8 {q1}, [r2], r3 //save pix2 - stride
vld1.8 {q10}, [r2], r3 //save pix2
vld1.8 {q2}, [r2], r3 //save pix2 + stride
vld1.8 {q3}, [r4], r3 //save pix2 - 1
vld1.8 {q8}, [r5], r3 //save pix2 + 1
//Do the SAD for 16 bytes
vabdl.u8 q15, d0, d2
vabal.u8 q15, d1, d3
vabdl.u8 q13, d0, d4
vabal.u8 q13, d1, d5
vabdl.u8 q11, d0, d6
vabal.u8 q11, d1, d7
vabdl.u8 q9, d0, d16
vabal.u8 q9, d1, d17
mov lr, #7
pixel_sad_4_16x8_loop_0:
//Loading a horizontal line data (16 bytes)
vld1.8 {q0}, [r0], r1 //save pix1
vmov.8 q1, q10 //save pix2 - stride
vmov.8 q10, q2
vabal.u8 q15, d0, d2
vld1.8 {q2}, [r2], r3 //save pix2 + stride
vabal.u8 q15, d1, d3
vld1.8 {q3}, [r4], r3 //save pix2 - 1
vabal.u8 q13, d0, d4
vld1.8 {q8}, [r5], r3 //save pix2 + 1
vabal.u8 q13, d1, d5
subs lr, #1
vabal.u8 q11, d0, d6
vabal.u8 q11, d1, d7
vabal.u8 q9, d0, d16
vabal.u8 q9, d1, d17
bne pixel_sad_4_16x8_loop_0
//Save SAD to 'r0'
ldr r0, [sp, #12]
vadd.u16 d0, d30, d31
vadd.u16 d1, d26, d27
vadd.u16 d2, d22, d23
vadd.u16 d3, d18, d19
vpaddl.u16 q0, q0
vpaddl.u16 q1, q1
vpaddl.u32 q0, q0
vpaddl.u32 q1, q1
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
ldmia sp!, {r4-r5, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSadFour8x16_neon
stmdb sp!, {r4-r5, lr}
//Generate the pix2 start addr
sub r4, r2, #1
add r5, r2, #1
sub r2, r3
//Loading a horizontal line data (8 bytes)
vld1.8 {d0}, [r0], r1 //save pix1
vld1.8 {d1}, [r2], r3 //save pix2 - stride
vld1.8 {d6}, [r2], r3 //save pix2
vld1.8 {d2}, [r2], r3 //save pix2 + stride
vld1.8 {d3}, [r4], r3 //save pix2 - 1
vld1.8 {d4}, [r5], r3 //save pix2 + 1
//Do the SAD for 8 bytes
vabdl.u8 q15, d0, d1
vabdl.u8 q14, d0, d2
vabdl.u8 q13, d0, d3
vabdl.u8 q12, d0, d4
mov lr, #15
pixel_sad_4_8x16_loop_0:
//Loading a horizontal line data (8 bytes)
vld1.8 {d0}, [r0], r1 //save pix1
vmov.8 d1, d6 //save pix2 - stride
vmov.8 d6, d2
vld1.8 {d2}, [r2], r3 //save pix2 + stride
vld1.8 {d3}, [r4], r3 //save pix2 - 1
vabal.u8 q15, d0, d1
vld1.8 {d4}, [r5], r3 //save pix2 + 1
//Do the SAD for 8 bytes
vabal.u8 q14, d0, d2
vabal.u8 q13, d0, d3
vabal.u8 q12, d0, d4
subs lr, #1
bne pixel_sad_4_8x16_loop_0
//Save SAD to 'r0'
ldr r0, [sp, #12]
vadd.u16 d0, d30, d31
vadd.u16 d1, d28, d29
vadd.u16 d2, d26, d27
vadd.u16 d3, d24, d25
vpaddl.u16 q0, q0
vpaddl.u16 q1, q1
vpaddl.u32 q0, q0
vpaddl.u32 q1, q1
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
ldmia sp!, {r4-r5, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSadFour8x8_neon
stmdb sp!, {r4-r5, lr}
//Generate the pix2 start addr
sub r4, r2, #1
add r5, r2, #1
sub r2, r3
//Loading a horizontal line data (8 bytes)
vld1.8 {d0}, [r0], r1 //save pix1
vld1.8 {d1}, [r2], r3 //save pix2 - stride
vld1.8 {d6}, [r2], r3 //save pix2
vld1.8 {d2}, [r2], r3 //save pix2 + stride
vld1.8 {d3}, [r4], r3 //save pix2 - 1
vld1.8 {d4}, [r5], r3 //save pix2 + 1
//Do the SAD for 8 bytes
vabdl.u8 q15, d0, d1
vabdl.u8 q14, d0, d2
vabdl.u8 q13, d0, d3
vabdl.u8 q12, d0, d4
mov lr, #7
pixel_sad_4_8x8_loop_0:
//Loading a horizontal line data (8 bytes)
vld1.8 {d0}, [r0], r1 //save pix1
vmov.8 d1, d6 //save pix2 - stride
vmov.8 d6, d2
vld1.8 {d2}, [r2], r3 //save pix2 + stride
vld1.8 {d3}, [r4], r3 //save pix2 - 1
vabal.u8 q15, d0, d1
vld1.8 {d4}, [r5], r3 //save pix2 + 1
//Do the SAD for 8 bytes
vabal.u8 q14, d0, d2
vabal.u8 q13, d0, d3
vabal.u8 q12, d0, d4
subs lr, #1
bne pixel_sad_4_8x8_loop_0
//Save SAD to 'r0'
ldr r0, [sp, #12]
vadd.u16 d0, d30, d31
vadd.u16 d1, d28, d29
vadd.u16 d2, d26, d27
vadd.u16 d3, d24, d25
vpaddl.u16 q0, q0
vpaddl.u16 q1, q1
vpaddl.u32 q0, q0
vpaddl.u32 q1, q1
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
ldmia sp!, {r4-r5, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSadFour4x4_neon
vld1.32 {d0[0]}, [r0], r1
vld1.32 {d0[1]}, [r0], r1
vld1.32 {d1[0]}, [r0], r1
vld1.32 {d1[1]}, [r0]
sub r0, r2, r3
vld1.32 {d2[0]}, [r0], r3
vld1.32 {d2[1]}, [r0], r3
vld1.32 {d3[0]}, [r0], r3
vld1.32 {d3[1]}, [r0], r3
vld1.32 {d4[0]}, [r0], r3
vld1.32 {d4[1]}, [r0]
sub r0, r2, #1
vld1.32 {d5[0]}, [r0], r3
vld1.32 {d5[1]}, [r0], r3
vld1.32 {d6[0]}, [r0], r3
vld1.32 {d6[1]}, [r0]
add r0, r2, #1
vld1.32 {d7[0]}, [r0], r3
vld1.32 {d7[1]}, [r0], r3
vld1.32 {d8[0]}, [r0], r3
vld1.32 {d8[1]}, [r0]
vabdl.u8 q15, d0, d2
vabdl.u8 q14, d1, d3
vabdl.u8 q13, d0, d3
vabdl.u8 q12, d1, d4
vabdl.u8 q11, d0, d5
vabdl.u8 q10, d1, d6
vabdl.u8 q9, d0, d7
vabdl.u8 q8, d1, d8
//Save SAD to 'r4'
ldr r0, [sp]
vadd.u16 q0, q14, q15
vadd.u16 q1, q12, q13
vadd.u16 q2, q10, q11
vadd.u16 q3, q8 , q9
vadd.u16 d0, d1
vadd.u16 d1, d2, d3
vadd.u16 d2, d4, d5
vadd.u16 d3, d6, d7
vpaddl.u16 q0, q0
vpaddl.u16 q1, q1
vpaddl.u32 q0, q0
vpaddl.u32 q1, q1
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSatd16x16_neon
vpush {q7}
SATD_16x4
vadd.u16 q7, q0, q2
SATD_16x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q2
SATD_16x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q2
SATD_16x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q2
vadd.u16 d0, d14, d15
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.32 r0, d0[0]
vpop {q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSatd16x8_neon
vpush {q7}
SATD_16x4
vadd.u16 q7, q0, q2
SATD_16x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q2
vadd.u16 d0, d14, d15
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.32 r0, d0[0]
vpop {q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSatd8x16_neon
vpush {q7}
SATD_8x4
vadd.u16 q7, q0, q1
SATD_8x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q1
SATD_8x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q1
SATD_8x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q1
vadd.u16 d0, d14, d15
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.32 r0, d0[0]
vpop {q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSatd8x8_neon
vpush {q7}
SATD_8x4
vadd.u16 q7, q0, q1
SATD_8x4
vadd.u16 q7, q7, q0
vadd.u16 q7, q7, q1
vadd.u16 d0, d14, d15
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.32 r0, d0[0]
vpop {q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsSampleSatd4x4_neon
//Load the pix1 data --- 16 bytes
vld1.32 {d0[0]}, [r0], r1
vld1.32 {d0[1]}, [r0], r1
vld1.32 {d1[0]}, [r0], r1
vld1.32 {d1[1]}, [r0]
//Load the pix2 data --- 16 bytes
vld1.32 {d2[0]}, [r2], r3
vld1.32 {d2[1]}, [r2], r3
vld1.32 {d3[0]}, [r2], r3
vld1.32 {d3[1]}, [r2]
//Get the difference
vsubl.u8 q15, d0, d2 //{0,1,2,3,4,5,6,7}
vsubl.u8 q14, d1, d3 //{8,9,10,11,12,13,14,15}
//Do the vertical transform
vadd.s16 q13, q15, q14 //{0,4,8,12,1,5,9,13}
vsub.s16 q12, q15, q14 //{2,6,10,14,3,7,11,15}
vswp d27, d24
vadd.s16 q15, q13, q12 //{0,1,2,3,4,5,6,7}
vsub.s16 q14, q13, q12 //{12,13,14,15,8,9,10,11}
//Do the horizontal transform
vtrn.32 q15, q14
vadd.s16 q13, q15, q14
vsub.s16 q12, q15, q14
vtrn.16 q13, q12
vadd.s16 q15, q13, q12
//Do the SAD
vabs.s16 q15, q15
vabd.s16 q14, q13, q12
vadd.u16 q0, q15, q14
vrhadd.u16 d0, d1
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
vmov.u32 r0, d0[0]
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 15,468 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm/intra_pred_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
//Global macro
.macro GET_8BYTE_DATA arg0, arg1, arg2
vld1.8 {\arg0[0]}, [\arg1], \arg2
vld1.8 {\arg0[1]}, [\arg1], \arg2
vld1.8 {\arg0[2]}, [\arg1], \arg2
vld1.8 {\arg0[3]}, [\arg1], \arg2
vld1.8 {\arg0[4]}, [\arg1], \arg2
vld1.8 {\arg0[5]}, [\arg1], \arg2
vld1.8 {\arg0[6]}, [\arg1], \arg2
vld1.8 {\arg0[7]}, [\arg1], \arg2
.endm
WELS_ASM_FUNC_BEGIN WelsI16x16LumaPredDc_neon
//stmdb sp!, { r2-r5, lr}
//Get the left vertical line data
sub r3, r1, #1
GET_8BYTE_DATA d0, r3, r2
GET_8BYTE_DATA d1, r3, r2
//Get the top horizontal line data
sub r3, r1, r2
vldm r3, {d2, d3}
//Calculate the sum of top horizontal line data and vertical line data
vpaddl.u8 q0, q0
vpaddl.u8 q1, q1
vadd.u16 q0, q0, q1
vadd.u16 d0, d0, d1
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
//Calculate the mean value
vrshr.u16 d0, d0, #5
vdup.8 q0, d0[0]
//Set the mean value to the all of member of MB
mov r3, #4
loop_0_get_i16x16_luma_pred_dc_both:
vst1.8 {d0,d1}, [r0]!
vst1.8 {d0,d1}, [r0]!
vst1.8 {d0,d1}, [r0]!
vst1.8 {d0,d1}, [r0]!
subs r3, #1
bne loop_0_get_i16x16_luma_pred_dc_both
WELS_ASM_FUNC_END
//The table for SIMD instruction {(8,7,6,5,4,3,2,1) * 5}
CONST0_GET_I16X16_LUMA_PRED_PLANE: .long 0x191e2328, 0x050a0f14
//The table for SIMD instruction {-7,-6,-5,-4,-3,-2,-1,0}
CONST1_GET_I16X16_LUMA_PRED_PLANE: .long 0xfcfbfaf9, 0x00fffefd
WELS_ASM_FUNC_BEGIN WelsI16x16LumaPredPlane_neon
//stmdb sp!, { r4, lr}
//Load the table {(8,7,6,5,4,3,2,1) * 5}
adr r3, CONST0_GET_I16X16_LUMA_PRED_PLANE
vldr d0, [r3]
//Pack the top[-1] ~ top[6] to d1
sub r3, r1, r2
sub r1, r3, #1
vld1.8 d1, [r1]
//Pack the top[8] ~ top[15] to d2
add r1, #9
vld1.8 d2, [r1]
//Save the top[15] to d6 for next step
vdup.u8 d6, d2[7]
//Get and pack left[-1] ~ left[6] to d4
sub r1, r3, #1
GET_8BYTE_DATA d4, r1, r2
//Get and pack left[8] ~ left[15] to d3
add r1, r2
GET_8BYTE_DATA d3, r1, r2
//Save the left[15] to d7 for next step
vdup.u8 d7, d3[7]
//revert the sequence of d2,d3
vrev64.8 q1, q1
vsubl.u8 q2, d3, d4 //q2={left[8]-left[6],left[9]-left[5],left[10]-left[4], ...}
vsubl.u8 q1, d2, d1 //q1={top[8]-top[6],top[9]-top[5],top[10]-top[4], ...}
vmovl.u8 q0, d0
vmul.s16 q1, q0, q1 //q1 = q1*{(8,7,6,5,4,3,2,1) * 5}
vmul.s16 q2, q0, q2 //q2 = q2*{(8,7,6,5,4,3,2,1) * 5}
//Calculate the sum of items of q1, q2
vpadd.s16 d0, d2, d3
vpadd.s16 d1, d4, d5
vpaddl.s16 q0, q0
vpaddl.s32 q0, q0
//Get the value of 'b', 'c' and extend to q1, q2.
vrshr.s64 q0, #6
vdup.s16 q1, d0[0]
vdup.s16 q2, d1[0]
//Load the table {-7,-6,-5,-4,-3,-2,-1,0} to d0
adr r3, CONST1_GET_I16X16_LUMA_PRED_PLANE
vld1.32 {d0}, [r3]
//Get the value of 'a' and save to q3
vaddl.u8 q3, d6, d7
vshl.u16 q3, #4
//calculate a+'b'*{-7,-6,-5,-4,-3,-2,-1,0} + c*{-7}
vmovl.s8 q0, d0
vmla.s16 q3, q0, q1
vmla.s16 q3, q2, d0[0]
//Calculate a+'b'*{1,2,3,4,5,6,7,8} + c*{-7}
vshl.s16 q8, q1, #3
vadd.s16 q8, q3
//right shift 5 bits and rounding
vqrshrun.s16 d0, q3, #5
vqrshrun.s16 d1, q8, #5
//Set the line of MB
vst1.u32 {d0,d1}, [r0]!
//Do the same processing for setting other lines
mov r3, #15
loop_0_get_i16x16_luma_pred_plane:
vadd.s16 q3, q2
vadd.s16 q8, q2
vqrshrun.s16 d0, q3, #5
vqrshrun.s16 d1, q8, #5
vst1.u32 {d0,d1}, [r0]!
subs r3, #1
bne loop_0_get_i16x16_luma_pred_plane
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredV_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (4 bytes)
sub r3, r1, r2
ldr r3, [r3]
//Set the luma MB using top line
str r3, [r0], #4
str r3, [r0], #4
str r3, [r0], #4
str r3, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredH_neon
//stmdb sp!, { r2-r5, lr}
//Load the left column (4 bytes)
sub r3, r1, #1
vld1.8 {d0[]}, [r3], r2
vld1.8 {d1[]}, [r3], r2
vld1.8 {d2[]}, [r3], r2
vld1.8 {d3[]}, [r3]
//Set the luma MB using the left side byte
vst1.32 {d0[0]}, [r0]!
vst1.32 {d1[0]}, [r0]!
vst1.32 {d2[0]}, [r0]!
vst1.32 {d3[0]}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredDDL_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row data(8 bytes)
sub r3, r1, r2
vld1.32 {d0}, [r3]
//For "t7 + (t7<<1)"
vdup.8 d1, d0[7]
//calculate "t0+t1,t1+t2,t2+t3...t6+t7,t7+t7"
vext.8 d1, d0, d1, #1
vaddl.u8 q1, d1, d0
//calculate "x,t0+t1+t1+t2,t1+t2+t2+t3,...t5+t6+t6+t7,t6+t7+t7+t7"
vext.8 q2, q1, q1, #14
vadd.u16 q0, q1, q2
//right shift 2 bits and rounding
vqrshrn.u16 d0, q0, #2
//Save "ddl0, ddl1, ddl2, ddl3"
vext.8 d1, d0, d0, #1
vst1.32 d1[0], [r0]!
//Save "ddl1, ddl2, ddl3, ddl4"
vext.8 d1, d0, d0, #2
vst1.32 d1[0], [r0]!
//Save "ddl2, ddl3, ddl4, ddl5"
vext.8 d1, d0, d0, #3
vst1.32 d1[0], [r0]!
//Save "ddl3, ddl4, ddl5, ddl6"
vst1.32 d0[1], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredDDR_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (4 bytes)
sub r3, r1, r2
vld1.32 {d0[1]}, [r3]
//Load the left column (5 bytes)
sub r3, #1
vld1.8 {d0[3]}, [r3], r2
vld1.8 {d0[2]}, [r3], r2
vld1.8 {d0[1]}, [r3], r2
vld1.8 {d0[0]}, [r3], r2
vld1.8 {d1[7]}, [r3] //For packing the right sequence to do SIMD processing
vext.8 d2, d1, d0, #7 //d0:{L2,L1,L0,LT,T0,T1,T2,T3}
//d2:{L3,L2,L1,L0,LT,T0,T1,T2}
//q2:{L2+L3,L1+L2,L0+L1...T1+T2,T2+T3}
vaddl.u8 q2, d2, d0
//q1:{TL0+LT0,LT0+T01,...L12+L23}
vext.8 q3, q3, q2, #14
vadd.u16 q1, q2, q3
//right shift 2 bits and rounding
vqrshrn.u16 d0, q1, #2
//Adjust the data sequence for setting luma MB of 'pred'
vst1.32 d0[1], [r0]!
vext.8 d0, d0, d0, #7
vst1.32 d0[1], [r0]!
vext.8 d0, d0, d0, #7
vst1.32 d0[1], [r0]!
vext.8 d0, d0, d0, #7
vst1.32 d0[1], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredVL_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (8 bytes)
sub r3, r1, r2
vld1.32 {d0}, [r3]
vext.8 d1, d0, d0, #1
vaddl.u8 q1, d1, d0 //q1:{t0+t1,t1+t2,t2+t3...t5+t6,x,x}
vext.8 q2, q1, q1, #2
vadd.u16 q2, q1, q2 //q2:{t0+t1+t1+t2,t1+t2+t2+t3,...t4+t5+t5+t6,x,x}
//calculate the "vl0,vl1,vl2,vl3,vl4"
vqrshrn.u16 d0, q1, #1
//calculate the "vl5,vl6,vl7,vl8,vl9"
vqrshrn.u16 d1, q2, #2
//Adjust the data sequence for setting the luma MB
vst1.32 d0[0], [r0]!
vst1.32 d1[0], [r0]!
vext.8 d0, d0, d0, #1
vext.8 d1, d1, d1, #1
vst1.32 d0[0], [r0]!
vst1.32 d1[0], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredVR_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (4 bytes)
sub r3, r1, r2
vld1.32 {d0[1]}, [r3]
//Load the left column (4 bytes)
sub r3, #1
vld1.8 {d0[3]}, [r3], r2
vld1.8 {d0[2]}, [r3], r2
vld1.8 {d0[1]}, [r3], r2
vld1.8 {d0[0]}, [r3]
vext.8 d1, d0, d0, #7
vaddl.u8 q1, d0, d1 //q1:{X,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1,T1+T2,T2+T3}
vext.u8 q2, q1, q1, #14
vadd.u16 q2, q2, q1 //q2:{X,L2+L1+L1+L0,L1+L0+L0+LT,...T1+T2+T2+T3}
//Calculate the vr0 ~ vr9
vqrshrn.u16 d1, q2, #2
vqrshrn.u16 d0, q1, #1
//Adjust the data sequence for setting the luma MB
vst1.32 d0[1], [r0]!
vst1.32 d1[1], [r0]!
//add r2, r0, r1
vst1.8 d1[3], [r0]!
vst1.16 d0[2], [r0]!
vst1.8 d0[6], [r0]!
vst1.8 d1[2], [r0]!
vst1.16 d1[2], [r0]!
vst1.8 d1[6], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredHU_neon
//stmdb sp!, { r4, lr}
//Load the left column data
sub r3, r1, #1
mov r1, #3
mul r1, r2
add r1, r3
vld1.8 {d0[]}, [r1]
vld1.8 {d0[4]}, [r3], r2
vld1.8 {d0[5]}, [r3], r2
vld1.8 {d0[6]}, [r3], r2 //d0:{L3,L3,L3,L3,L0,L1,L2,L3}
vext.8 d1, d0, d0, #1
vaddl.u8 q2, d0, d1 //q2:{L3+L3,L3+L3,L3+L3,L3+L0,L0+L1,L1+L2,L2+L3,L3+L3}
vext.u8 d2, d5, d4, #2
vadd.u16 d3, d2, d5 //d3:{L0+L1+L1+L2,L1+L2+L2+L3,L2+L3+L3+L3,L3+L3+L3+L3}
//Calculate the hu0 ~ hu5
vqrshrn.u16 d2, q2, #1
vqrshrn.u16 d1, q1, #2
//Adjust the data sequence for setting the luma MB
vzip.8 d2, d1
vst1.32 d1[0], [r0]!
vext.8 d2, d1, d1, #2
vst1.32 d2[0], [r0]!
vst1.32 d1[1], [r0]!
vst1.32 d0[0], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI4x4LumaPredHD_neon
//stmdb sp!, { r2-r5, lr}
//Load the data
sub r3, r1, r2
sub r3, #1
vld1.32 {d0[1]}, [r3], r2
vld1.8 {d0[3]}, [r3], r2
vld1.8 {d0[2]}, [r3], r2
vld1.8 {d0[1]}, [r3], r2
vld1.8 {d0[0]}, [r3] //d0:{L3,L2,L1,L0,LT,T0,T1,T2}
vext.8 d1, d0, d0, #7
vaddl.u8 q1, d0, d1 //q1:{x,L3+L2,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1,T1+T2}
vext.u8 q2, q1, q1, #14 //q2:{x,x, L3+L2,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1}
vadd.u16 q3, q2, q1 //q3:{x,x,L3+L2+L2+L1,L2+L1+L1+L0,L1+L0+L0+LT,L0+LT+LT+T0,LT+T0+T0+T1,T0+T1+T1+T2}
//Calculate the hd0~hd9
vqrshrn.u16 d1, q3, #2
vqrshrn.u16 d0, q2, #1
//Adjust the data sequence for setting the luma MB
vmov d3, d1
vtrn.8 d0, d1
vext.u8 d2, d1, d1, #6
vst2.16 {d2[3], d3[3]}, [r0]!
vst2.16 {d0[2], d1[2]}, [r0]!
vmov d3, d0
vst2.16 {d2[2], d3[2]}, [r0]!
vst2.16 {d0[1], d1[1]}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIChromaPredV_neon
//stmdb sp!, { r2-r5, lr}
//Get the top row (8 byte)
sub r3, r1, r2
vldr d0, [r3]
//Set the chroma MB using top row data
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]!
vst1.8 {d0}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIChromaPredH_neon
//stmdb sp!, { r2-r5, lr}
////Get the left column (8 byte)
sub r3, r1, #1
vld1.8 {d0[]}, [r3], r2
vld1.8 {d1[]}, [r3], r2
vld1.8 {d2[]}, [r3], r2
vld1.8 {d3[]}, [r3], r2
vld1.8 {d4[]}, [r3], r2
vld1.8 {d5[]}, [r3], r2
vld1.8 {d6[]}, [r3], r2
vld1.8 {d7[]}, [r3]
//Set the chroma MB using left column data
vst1.8 {d0}, [r0]!
vst1.8 {d1}, [r0]!
vst1.8 {d2}, [r0]!
vst1.8 {d3}, [r0]!
vst1.8 {d4}, [r0]!
vst1.8 {d5}, [r0]!
vst1.8 {d6}, [r0]!
vst1.8 {d7}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsIChromaPredDc_neon
//stmdb sp!, { r2-r5, lr}
//Load the left column data (8 bytes)
sub r3, r1, #1
GET_8BYTE_DATA d0, r3, r2
//Load the top row data (8 bytes)
sub r3, r1, r2
vldr d1, [r3]
//Calculate the sum of left column and top row
vpaddl.u8 q0, q0
vpaddl.u16 q0, q0
vadd.u32 d2, d0, d1 //'m1' save to d2
vrshr.u32 q0, q0, #2 //calculate 'm2','m3'
vrshr.u32 d2, d2, #3 //calculate 'm4'
//duplicate the 'mx' to a vector line
vdup.8 d4, d2[0]
vdup.8 d5, d1[4]
vdup.8 d6, d0[4]
vdup.8 d7, d2[4]
//Set the chroma MB
vst2.32 {d4[0],d5[0]}, [r0]!
vst2.32 {d4[0],d5[0]}, [r0]!
vst2.32 {d4[0],d5[0]}, [r0]!
vst2.32 {d4[0],d5[0]}, [r0]!
vst2.32 {d6[0],d7[0]}, [r0]!
vst2.32 {d6[0],d7[0]}, [r0]!
vst2.32 {d6[0],d7[0]}, [r0]!
vst2.32 {d6[0],d7[0]}, [r0]
WELS_ASM_FUNC_END
//Table {{1,2,3,4,1,2,3,4}*17}
CONST0_GET_I_CHROMA_PRED_PLANE: .long 0x44332211, 0x44332211//0x140f0a05, 0x28231e19
//Table {-3,-2,-1,0,1,2,3,4}
CONST1_GET_I_CHROMA_PRED_PLANE: .long 0xfffefffd, 0x0000ffff,0x00020001,0x00040003
WELS_ASM_FUNC_BEGIN WelsIChromaPredPlane_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row data
sub r3, r1, #1
sub r3, r2
vld1.32 {d1[0]}, [r3]
add r3, #5
vld1.32 {d0[0]}, [r3]
//Load the left column data
sub r3, #5
vld1.8 {d1[4]}, [r3], r2
vld1.8 {d1[5]}, [r3], r2
vld1.8 {d1[6]}, [r3], r2
vld1.8 {d1[7]}, [r3], r2 //d1:{LT,T0,T1,T2,LT,L0,L1,L2}
add r3, r2
vld1.8 {d0[4]}, [r3], r2
vld1.8 {d0[5]}, [r3], r2
vld1.8 {d0[6]}, [r3], r2
vld1.8 {d0[7]}, [r3] //d0:{T4,T5,T6,T7,L4,L5,L6.L7}
//Save T7 to d3 for next step
vdup.u8 d3, d0[3]
//Save L7 to d4 for next step
vdup.u8 d4, d0[7]
//Calculate the value of 'a' and save to q2
vaddl.u8 q2, d3, d4
vshl.u16 q2, #4
//Load the table {{1,2,3,4,1,2,3,4}*17}
adr r3, CONST0_GET_I_CHROMA_PRED_PLANE
vld1.32 {d2}, [r3]
//Calculate the 'b','c', and save to q0
vrev32.8 d1, d1
vsubl.u8 q0, d0, d1
vmovl.u8 q1, d2
vmul.s16 q0, q1
vpaddl.s16 q0, q0
vpaddl.s32 q0, q0
vrshr.s64 q0, #5
//Load the table {-3,-2,-1,0,1,2,3,4} to q3
adr r3, CONST1_GET_I_CHROMA_PRED_PLANE
vld1.32 {d6, d7}, [r3]
//Duplicate the 'b','c' to q0, q1 for SIMD instruction
vdup.s16 q1, d1[0]
vdup.s16 q0, d0[0]
//Calculate the "(a + b * (j - 3) + c * (- 3) + 16) >> 5;"
vmla.s16 q2, q0, q3
vmla.s16 q2, q1, d6[0]
vqrshrun.s16 d0, q2, #5
//Set a line of chroma MB
vst1.u32 {d0}, [r0]!
//Do the same processing for each line.
mov r3, #7
loop_0_get_i_chroma_pred_plane:
vadd.s16 q2, q1
vqrshrun.s16 d0, q2, #5
vst1.u32 {d0}, [r0]!
subs r3, #1
bne loop_0_get_i_chroma_pred_plane
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,042 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm/memory_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
WELS_ASM_FUNC_BEGIN WelsSetMemZero_neon
veor q0, q0
cmp r1, #32
beq mem_zero_32_neon_start
blt mem_zero_24_neon_start
mem_zero_loop:
subs r1, r1, #64
vst1.64 {q0}, [r0]!
vst1.64 {q0}, [r0]!
vst1.64 {q0}, [r0]!
vst1.64 {q0}, [r0]!
bne mem_zero_loop
bx lr
mem_zero_32_neon_start:
vst1.64 {q0}, [r0]!
vst1.64 {q0}, [r0]!
bx lr
mem_zero_24_neon_start:
vst1.64 {q0}, [r0]!
vst1.64 {d0}, [r0]!
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 18,514 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm64/intra_pred_sad_3_opt_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro LOAD_LUMA_DATA
sub x7, x0, x1
ld1 {v0.16b}, [x7] //top
sub x7, x0, #1
ld1 {v1.b}[0], [x7], x1
ld1 {v1.b}[1], [x7], x1
ld1 {v1.b}[2], [x7], x1
ld1 {v1.b}[3], [x7], x1
ld1 {v1.b}[4], [x7], x1
ld1 {v1.b}[5], [x7], x1
ld1 {v1.b}[6], [x7], x1
ld1 {v1.b}[7], [x7], x1
ld1 {v1.b}[8], [x7], x1
ld1 {v1.b}[9], [x7], x1
ld1 {v1.b}[10], [x7], x1
ld1 {v1.b}[11], [x7], x1
ld1 {v1.b}[12], [x7], x1
ld1 {v1.b}[13], [x7], x1
ld1 {v1.b}[14], [x7], x1
ld1 {v1.b}[15], [x7] //left
.endm
.macro LOAD_16X4_DATA
//Load the p_enc data and save to "v22 ~ v25"--- 16X4 bytes
ld1 {v0.16b}, [x2], x3
ld1 {v1.16b}, [x2], x3
ld1 {v20.16b}, [x2], x3
ld1 {v21.16b}, [x2], x3
trn1 v22.4s, v0.4s, v1.4s
trn2 v23.4s, v0.4s, v1.4s
trn1 v24.4s, v20.4s, v21.4s
trn2 v25.4s, v20.4s, v21.4s
.endm
.macro GET_16X16_V_SATD
trn1 v6.4s, v4.4s, v5.4s
trn2 v7.4s, v4.4s, v5.4s
add v4.8h, v6.8h, v7.8h
sub v5.8h, v6.8h, v7.8h
trn1 v6.8h, v4.8h, v5.8h
trn2 v7.8h, v4.8h, v5.8h
add v4.8h, v6.8h, v7.8h
sub v5.8h, v6.8h, v7.8h
trn1 v6.4s, v4.4s, v5.4s
trn2 v7.4s, v4.4s, v5.4s //{0,1,3,2, 4,5,7,6} v6 {8,9,11,10, 12,13,15,14} v7
.endm
.macro GET_16X16_H_SATD
trn1 v16.4s, v4.4s, v5.4s
trn2 v17.4s, v4.4s, v5.4s
add v4.8h, v16.8h, v17.8h
sub v5.8h, v16.8h, v17.8h
trn1 v16.8h, v4.8h, v5.8h
trn2 v17.8h, v4.8h, v5.8h
add v4.8h, v16.8h, v17.8h
sub v5.8h, v16.8h, v17.8h
trn1 v16.4s, v4.4s, v5.4s
trn2 v17.4s, v4.4s, v5.4s //{0,1,3,2, 4,5,7,6} v16 {8,9,11,10, 12,13,15,14} v17
.endm
.macro SELECT_BEST_COST arg0, arg1, arg2
cmp w1, \arg0
csel \arg0, \arg0, w1, \arg2
cset w7, \arg1
cmp w2, \arg0
mov w6, #2
csel \arg0, \arg0, w2, \arg2
csel w7, w7, w6, \arg2
.endm
.macro SELECT_BEST_COST_PREFER_HIGHER arg0
SELECT_BEST_COST \arg0, ls, hi
.endm
.macro SELECT_BEST_COST_PREFER_LOWER arg0
SELECT_BEST_COST \arg0, lo, hs
.endm
.macro LOAD_CHROMA_DATA arg0, arg1, arg2
sub x9, \arg0, x1
ld1 {\arg1}, [x9] //top_cb
sub x9, \arg0, #1
ld1 {\arg2}[8], [x9], x1
ld1 {\arg2}[9], [x9], x1
ld1 {\arg2}[10], [x9], x1
ld1 {\arg2}[11], [x9], x1
ld1 {\arg2}[12], [x9], x1
ld1 {\arg2}[13], [x9], x1
ld1 {\arg2}[14], [x9], x1
ld1 {\arg2}[15], [x9], x1 //left_cb
.endm
.macro LOAD_8X4_DATA arg0
//Load the p_enc data and save to "v20 ~ v21"--- 8X4 bytes
ld1 {v0.8b}, [\arg0], x3
ld1 {v1.8b}, [\arg0], x3
ld1 {v0.d}[1], [\arg0], x3
ld1 {v1.d}[1], [\arg0], x3
trn1 v2.4s, v0.4s, v1.4s
trn2 v1.4s, v0.4s, v1.4s
trn1 v20.2d, v2.2d, v1.2d
trn2 v21.2d, v2.2d, v1.2d
.endm
.macro HDM_TRANSFORM_4X4_L0 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
//Do the vertical transform
uadd\arg9\() v0.8h, \arg0, \arg1
usub\arg9\() v1.8h, \arg0, \arg1
trn1 v3.2d, v0.2d, v1.2d
trn2 v1.2d, v0.2d, v1.2d
add v4.8h, v3.8h, v1.8h //{0,1,2,3,4,5,6,7}
sub v5.8h, v3.8h, v1.8h //{12,13,14,15,8,9,10,11}
//Do the horizontal transform
trn1 v0.4s, v4.4s, v5.4s
trn2 v1.4s, v4.4s, v5.4s
add v4.8h, v0.8h, v1.8h
sub v5.8h, v0.8h, v1.8h
trn1 v0.8h, v4.8h, v5.8h
trn2 v1.8h, v4.8h, v5.8h
add v4.8h, v0.8h, v1.8h
sub v5.8h, v0.8h, v1.8h
//16x16_v
trn1 v0.2s, v4.2s, v5.2s
trn2 v1.2s, v4.2s, v5.2s
sabal \arg5, v0.4h, \arg2
sabal \arg5, v1.4h, \arg8\().4h
sabal2 \arg5, v4.8h, \arg8\().8h
sabal2 \arg5, v5.8h, \arg8\().8h
//16x16_h
ins v3.d[0], v4.d[1]
trn1 v0.4h, v4.4h, v3.4h
trn2 v1.4h, v4.4h, v3.4h
sabal \arg6, v0.4h, \arg3
sabdl v4.4s, v1.4h, \arg8\().4h
sabal v4.4s, v5.4h, \arg8\().4h
sabal2 v4.4s, v5.8h, \arg8\().8h
add \arg6, \arg6, v4.4s
//16x16_dc_both
sabal \arg7, v0.4h, \arg4
add \arg7, \arg7, v4.4s
.endm
//int32_t WelsIntra8x8Combined3Sad_AArch64_neon (uint8_t*, int32_t, uint8_t*, int32_t, int32_t*, int32_t, uint8_t*, uint8_t*,uint8_t*);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIntra8x8Combined3Sad_AArch64_neon
ldr x11, [sp, #0]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
LOAD_CHROMA_DATA x0, v0.8b, v0.b
uaddlp v1.8h, v0.16b
uaddlp v2.4s, v1.8h
ins v3.d[0], v2.d[1]
add v3.2s, v2.2s, v3.2s
urshr v2.4s, v2.4s, #2
urshr v3.2s, v3.2s, #3
dup v20.8b, v3.b[0]
dup v21.8b, v2.b[4]
dup v22.8b, v2.b[12]
dup v23.8b, v3.b[4]
ins v20.s[1], v21.s[0]
ins v22.s[1], v23.s[0]
LOAD_CHROMA_DATA x7, v4.8b, v4.b
uaddlp v5.8h, v4.16b
uaddlp v6.4s, v5.8h
ins v7.d[0], v6.d[1]
add v7.2s, v6.2s, v7.2s
urshr v6.4s, v6.4s, #2
urshr v7.2s, v7.2s, #3
dup v24.8b, v7.b[0]
dup v25.8b, v6.b[4]
dup v26.8b, v6.b[12]
dup v27.8b, v7.b[4]
ins v24.s[1], v25.s[0]
ins v26.s[1], v27.s[0]
sub x9, x0, #1
sub x10, x7, #1
ld1 {v3.8b}, [x2], x3
ld1 {v5.8b}, [x11], x3
ld1r {v6.8b}, [x9], x1
ld1r {v7.8b}, [x10], x1
uabdl v29.8h, v0.8b, v3.8b
uabal v29.8h, v4.8b, v5.8b //top
uabdl v30.8h, v6.8b, v3.8b
uabal v30.8h, v7.8b, v5.8b //left
uabdl v31.8h, v20.8b, v3.8b
uabal v31.8h, v24.8b, v5.8b //Dc
.rept 3
ld1 {v3.8b}, [x2], x3
ld1 {v5.8b}, [x11], x3
ld1r {v6.8b}, [x9], x1
ld1r {v7.8b}, [x10], x1
uabal v29.8h, v0.8b, v3.8b
uabal v29.8h, v4.8b, v5.8b //top
uabal v30.8h, v6.8b, v3.8b
uabal v30.8h, v7.8b, v5.8b //left
uabal v31.8h, v20.8b, v3.8b
uabal v31.8h, v24.8b, v5.8b //Dc
.endr
.rept 4
ld1 {v3.8b}, [x2], x3
ld1 {v5.8b}, [x11], x3
ld1r {v6.8b}, [x9], x1
ld1r {v7.8b}, [x10], x1
uabal v29.8h, v0.8b, v3.8b
uabal v29.8h, v4.8b, v5.8b //top
uabal v30.8h, v6.8b, v3.8b
uabal v30.8h, v7.8b, v5.8b //left
uabal v31.8h, v22.8b, v3.8b
uabal v31.8h, v26.8b, v5.8b //Dc
.endr
saddlv s29, v29.8h
fmov w2, s29
add w2, w2, w5, lsl #1
saddlv s30, v30.8h
fmov w1, s30
add w1, w1, w5, lsl #1
saddlv s31, v31.8h
fmov w0, s31
SELECT_BEST_COST_PREFER_HIGHER w0
str w7, [x4]
WELS_ASM_AARCH64_FUNC_END
//int32_t WelsIntra16x16Combined3Sad_AArch64_neon (uint8_t*, int32_t, uint8_t*, int32_t, int32_t*, int32_t, uint8_t*);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIntra16x16Combined3Sad_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
LOAD_LUMA_DATA
uaddlv h2, v0.16b
uaddlv h3, v1.16b
add v2.8h, v2.8h, v3.8h
uqrshrn b2, h2, #5
dup v2.16b, v2.b[0] //Dc
sub x7, x0, #1
ld1 {v3.16b}, [x2], x3
ld1r {v4.16b}, [x7], x1
uabdl v29.8h, v0.8b, v3.8b
uabal2 v29.8h, v0.16b,v3.16b //top
uabdl v30.8h, v4.8b, v3.8b
uabal2 v30.8h, v4.16b,v3.16b //left
uabdl v31.8h, v2.8b, v3.8b
uabal2 v31.8h, v2.16b,v3.16b //Dc
mov x6, #15
sad_intra_16x16_x3_opt_loop0:
ld1 {v3.16b}, [x2], x3
ld1r {v4.16b}, [x7], x1
uabal v29.8h, v0.8b, v3.8b
uabal2 v29.8h, v0.16b,v3.16b //top
uabal v30.8h, v4.8b, v3.8b
uabal2 v30.8h, v4.16b,v3.16b //left
uabal v31.8h, v2.8b, v3.8b
uabal2 v31.8h, v2.16b,v3.16b //Dc
sub x6, x6, #1
cbnz x6, sad_intra_16x16_x3_opt_loop0
saddlv s29, v29.8h
fmov w0, s29
saddlv s30, v30.8h
fmov w1, s30
add w1, w1, w5, lsl #1
saddlv s31, v31.8h
fmov w2, s31
add w2, w2, w5, lsl #1
SELECT_BEST_COST_PREFER_LOWER w0
str w7, [x4]
WELS_ASM_AARCH64_FUNC_END
//int32_t WelsIntra4x4Combined3Satd_AArch64_neon (uint8_t*, int32_t, uint8_t*, int32_t, uint8_t*, int32_t*, int32_t, int32_t,int32_t);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIntra4x4Combined3Satd_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x6,w6
SIGN_EXTENSION x7,w7
sub x9, x0, x1
ld1 {v16.s}[0], [x9] //top
sub x9, x0, #1
ld1 {v16.b}[4], [x9], x1
ld1 {v16.b}[5], [x9], x1
ld1 {v16.b}[6], [x9], x1
ld1 {v16.b}[7], [x9], x1
uaddlv h2, v16.8b
uqrshrn b17, h2, #3
urshr v2.4h, v2.4h, #3
shl v2.4h, v2.4h, #4
//Calculate the 4x4_v 4x4_h mode SATD and save to "v6, v7"
ushll v4.8h, v16.8b, #2
ins v5.d[0], v4.d[1]
trn1 v6.2s, v4.2s, v5.2s
trn2 v7.2s, v4.2s, v5.2s
add v4.4h, v6.4h, v7.4h
sub v5.4h, v6.4h, v7.4h
trn1 v6.4h, v4.4h, v5.4h
trn2 v7.4h, v4.4h, v5.4h
add v4.4h, v6.4h, v7.4h
sub v5.4h, v6.4h, v7.4h
trn1 v6.2s, v4.2s, v5.2s
trn2 v7.2s, v4.2s, v5.2s //{0,1,3,2,top} v6 {0,1,3,2,left} v7
eor v31.16b, v31.16b, v31.16b //Save the SATD of DC_BOTH
eor v30.16b, v30.16b, v30.16b //Save the SATD of H
eor v29.16b, v29.16b, v29.16b //Save the SATD of V
eor v28.16b, v28.16b, v28.16b //For zero register
//Load the p_enc data and save to "v22 ~ v23"--- 16X4 bytes
ld1 {v22.s}[0], [x2], x3
ld1 {v22.s}[1], [x2], x3
ld1 {v23.s}[0], [x2], x3
ld1 {v23.s}[1], [x2], x3
HDM_TRANSFORM_4X4_L0 v22.8b, v23.8b, v6.4h, v7.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
ldr x11, [sp, #0]
urshr v29.4s, v29.4s, #1
addv s29, v29.4s
fmov w0, s29
add w0, w0, w11
urshr v30.4s, v30.4s, #1
addv s30, v30.4s
fmov w1, s30
add w1, w1, w7
urshr v31.4s, v31.4s, #1
addv s31, v31.4s
fmov w2, s31
add w2, w2, w6
mov w10, w0
SELECT_BEST_COST_PREFER_HIGHER w10
str w7, [x5]
sub w9, w10, w2
cbnz w9, satd_intra_4x4_x3_opt_jump0
dup v0.16b, v17.b[0]
st1 {v0.16b}, [x4]
b satd_intra_4x4_x3_opt_end
satd_intra_4x4_x3_opt_jump0:
sub w8, w10, w1
cbnz w8, satd_intra_4x4_x3_opt_jump1
dup v0.16b, v16.b[4]
dup v1.16b, v16.b[5]
dup v2.16b, v16.b[6]
dup v3.16b, v16.b[7]
st4 {v0.s,v1.s,v2.s,v3.s}[0], [x4]
b satd_intra_4x4_x3_opt_end
satd_intra_4x4_x3_opt_jump1:
st1 {v16.S}[0], [x4], #4
st1 {v16.S}[0], [x4], #4
st1 {v16.S}[0], [x4], #4
st1 {v16.S}[0], [x4]
satd_intra_4x4_x3_opt_end:
mov w0, w10
WELS_ASM_AARCH64_FUNC_END
//int32_t WelsIntra8x8Combined3Satd_AArch64_neon (uint8_t*, int32_t, uint8_t*, int32_t, int32_t*, int32_t, uint8_t*, uint8_t*,uint8_t*);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIntra8x8Combined3Satd_AArch64_neon
ldr x11, [sp, #0]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
LOAD_CHROMA_DATA x0, v0.8b, v0.b
LOAD_CHROMA_DATA x7, v1.8b, v1.b
//Calculate the 16x16_v mode SATD and save to "v6, v7"
ushll v4.8h, v0.8b, #2
ushll v5.8h, v1.8b, #2
GET_16X16_V_SATD
//Calculate the 16x16_h mode SATD and save to "v16, v17"
ushll2 v4.8h, v0.16b, #2
ushll2 v5.8h, v1.16b, #2
GET_16X16_H_SATD
uaddlp v0.8h, v0.16b
uaddlp v2.4s, v0.8h
ins v3.d[0], v2.d[1]
add v3.2s, v2.2s, v3.2s
uaddlp v1.8h, v1.16b
uaddlp v4.4s, v1.8h
ins v5.d[0], v4.d[1]
add v5.2s, v4.2s, v5.2s
trn2 v0.4s, v2.4s, v4.4s
urshr v0.4s, v0.4s, #2
urshr v3.2s, v3.2s, #3
urshr v5.2s, v5.2s, #3
ushll v22.2d, v0.2s, #4 //{1cb, 1cr}
ushll2 v23.2d, v0.4s, #4 //{2cb, 2cr}
ushll v24.2d, v3.2s, #4 //{0cb, 3cb}
ushll v25.2d, v5.2s, #4 //{0cr, 3cr}
eor v31.16b, v31.16b, v31.16b //Save the SATD of DC_BOTH
eor v30.16b, v30.16b, v30.16b //Save the SATD of H
eor v29.16b, v29.16b, v29.16b //Save the SATD of V
eor v28.16b, v28.16b, v28.16b //For zero register
ins v18.d[0], v6.d[1]
ins v19.d[0], v7.d[1]
ins v26.d[0], v16.d[1]
ins v27.d[0], v17.d[1]
LOAD_8X4_DATA x2
HDM_TRANSFORM_4X4_L0 v20.8b, v21.8b, v6.4h, v16.4h, v24.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v20.16b, v21.16b, v18.4h, v16.4h, v22.4h, v29.4s, v30.4s, v31.4s, v28, l2
LOAD_8X4_DATA x11
ins v22.d[0], v22.d[1]
HDM_TRANSFORM_4X4_L0 v20.8b, v21.8b, v7.4h, v17.4h, v25.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v20.16b, v21.16b, v19.4h, v17.4h, v22.4h, v29.4s, v30.4s, v31.4s, v28, l2
LOAD_8X4_DATA x2
ins v24.d[0], v24.d[1]
HDM_TRANSFORM_4X4_L0 v20.8b, v21.8b, v6.4h, v26.4h, v23.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v20.16b, v21.16b, v18.4h, v26.4h, v24.4h, v29.4s, v30.4s, v31.4s, v28, l2
LOAD_8X4_DATA x11
ins v23.d[0], v23.d[1]
ins v25.d[0], v25.d[1]
HDM_TRANSFORM_4X4_L0 v20.8b, v21.8b, v7.4h, v27.4h, v23.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v20.16b, v21.16b, v19.4h, v27.4h, v25.4h, v29.4s, v30.4s, v31.4s, v28, l2
urshr v29.4s, v29.4s, #1
addv s29, v29.4s
fmov w2, s29
add w2, w2, w5, lsl #1
urshr v30.4s, v30.4s, #1
addv s30, v30.4s
fmov w1, s30
add w1, w1, w5, lsl #1
urshr v31.4s, v31.4s, #1
addv s31, v31.4s
fmov w0, s31
SELECT_BEST_COST_PREFER_HIGHER w0
str w7, [x4]
WELS_ASM_AARCH64_FUNC_END
//int32_t WelsIntra16x16Combined3Satd_AArch64_neon (uint8_t*, int32_t, uint8_t*, int32_t, int32_t*, int32_t, uint8_t*);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIntra16x16Combined3Satd_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
LOAD_LUMA_DATA
uaddlv h2, v0.16b
uaddlv h3, v1.16b
add v2.8h, v2.8h, v3.8h
urshr v2.4h, v2.4h, #5
shl v2.4h, v2.4h, #4
//Calculate the 16x16_v mode SATD and save to "v6, v7"
ushll v4.8h, v0.8b, #2
ushll2 v5.8h, v0.16b, #2
GET_16X16_V_SATD
//Calculate the 16x16_h mode SATD and save to "v16, v17"
ushll v4.8h, v1.8b, #2
ushll2 v5.8h, v1.16b, #2
GET_16X16_H_SATD
eor v31.16b, v31.16b, v31.16b //Save the SATD of DC_BOTH
eor v30.16b, v30.16b, v30.16b //Save the SATD of H
eor v29.16b, v29.16b, v29.16b //Save the SATD of V
eor v28.16b, v28.16b, v28.16b //For zero register
ins v18.d[0], v6.d[1]
ins v19.d[0], v7.d[1]
ins v26.d[0], v16.d[1]
ins v27.d[0], v17.d[1]
LOAD_16X4_DATA
HDM_TRANSFORM_4X4_L0 v22.8b, v24.8b, v6.4h, v16.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v22.16b, v24.16b, v7.4h, v16.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
HDM_TRANSFORM_4X4_L0 v23.8b, v25.8b, v18.4h, v16.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v23.16b, v25.16b, v19.4h, v16.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
LOAD_16X4_DATA
HDM_TRANSFORM_4X4_L0 v22.8b, v24.8b, v6.4h, v26.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v22.16b, v24.16b, v7.4h, v26.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
HDM_TRANSFORM_4X4_L0 v23.8b, v25.8b, v18.4h, v26.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v23.16b, v25.16b, v19.4h, v26.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
LOAD_16X4_DATA
HDM_TRANSFORM_4X4_L0 v22.8b, v24.8b, v6.4h, v17.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v22.16b, v24.16b, v7.4h, v17.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
HDM_TRANSFORM_4X4_L0 v23.8b, v25.8b, v18.4h, v17.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v23.16b, v25.16b, v19.4h, v17.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
LOAD_16X4_DATA
HDM_TRANSFORM_4X4_L0 v22.8b, v24.8b, v6.4h, v27.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v22.16b, v24.16b, v7.4h, v27.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
HDM_TRANSFORM_4X4_L0 v23.8b, v25.8b, v18.4h, v27.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l
HDM_TRANSFORM_4X4_L0 v23.16b, v25.16b, v19.4h, v27.4h, v2.4h, v29.4s, v30.4s, v31.4s, v28, l2
urshr v29.4s, v29.4s, #1
addv s29, v29.4s
fmov w0, s29
urshr v30.4s, v30.4s, #1
addv s30, v30.4s
fmov w1, s30
add w1, w1, w5, lsl #1
urshr v31.4s, v31.4s, #1
addv s31, v31.4s
fmov w2, s31
add w2, w2, w5, lsl #1
SELECT_BEST_COST_PREFER_LOWER w0
str w7, [x4]
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 16,009 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm64/pixel_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro CALC_AND_STORE_SAD
saddlv s2, v2.8h
fmov w0, s2
.endm
.macro CALC_AND_STORE_SAD_FOUR
saddlv s28, v28.8h
saddlv s29, v29.8h
saddlv s30, v30.8h
saddlv s31, v31.8h
st4 {v28.s, v29.s, v30.s, v31.s}[0], [x4]
.endm
.macro LOAD_8X8_1
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x0], x1
ld1 {v2.8b}, [x0], x1
ld1 {v3.8b}, [x0], x1
ld1 {v4.8b}, [x0], x1
ld1 {v5.8b}, [x0], x1
ld1 {v6.8b}, [x0], x1
ld1 {v7.8b}, [x0], x1
.endm
.macro LOAD_16X8_1
ld1 {v0.16b}, [x0], x1
ld1 {v1.16b}, [x0], x1
ld1 {v2.16b}, [x0], x1
ld1 {v3.16b}, [x0], x1
ld1 {v4.16b}, [x0], x1
ld1 {v5.16b}, [x0], x1
ld1 {v6.16b}, [x0], x1
ld1 {v7.16b}, [x0], x1
.endm
.macro LOAD_8X8_2 arg0
ld1 {v16.8b}, [\arg0], x3
ld1 {v17.8b}, [\arg0], x3
ld1 {v18.8b}, [\arg0], x3
ld1 {v19.8b}, [\arg0], x3
ld1 {v20.8b}, [\arg0], x3
ld1 {v21.8b}, [\arg0], x3
ld1 {v22.8b}, [\arg0], x3
ld1 {v23.8b}, [\arg0], x3
.endm
.macro CALC_ABS_8X8_1 arg0, arg1
uab\arg1\()l \arg0, v0.8b, v16.8b
uabal \arg0, v1.8b, v17.8b
uabal \arg0, v2.8b, v18.8b
uabal \arg0, v3.8b, v19.8b
uabal \arg0, v4.8b, v20.8b
uabal \arg0, v5.8b, v21.8b
uabal \arg0, v6.8b, v22.8b
uabal \arg0, v7.8b, v23.8b
.endm
.macro CALC_ABS_8X8_2 arg0
uab\arg0\()l v29.8h, v0.8b, v18.8b
uabal v29.8h, v1.8b, v19.8b
uabal v29.8h, v2.8b, v20.8b
uabal v29.8h, v3.8b, v21.8b
uabal v29.8h, v4.8b, v22.8b
uabal v29.8h, v5.8b, v23.8b
uabal v29.8h, v6.8b, v24.8b
uabal v29.8h, v7.8b, v25.8b
.endm
.macro LOAD_16X8_2 arg0
ld1 {v16.16b}, [\arg0], x3
ld1 {v17.16b}, [\arg0], x3
ld1 {v18.16b}, [\arg0], x3
ld1 {v19.16b}, [\arg0], x3
ld1 {v20.16b}, [\arg0], x3
ld1 {v21.16b}, [\arg0], x3
ld1 {v22.16b}, [\arg0], x3
ld1 {v23.16b}, [\arg0], x3
.endm
.macro CALC_ABS_16X8_1 arg0, arg1
uab\arg1\()l \arg0, v0.8b, v16.8b
uabal2 \arg0, v0.16b,v16.16b
uabal \arg0, v1.8b, v17.8b
uabal2 \arg0, v1.16b,v17.16b
uabal \arg0, v2.8b, v18.8b
uabal2 \arg0, v2.16b,v18.16b
uabal \arg0, v3.8b, v19.8b
uabal2 \arg0, v3.16b,v19.16b
uabal \arg0, v4.8b, v20.8b
uabal2 \arg0, v4.16b,v20.16b
uabal \arg0, v5.8b, v21.8b
uabal2 \arg0, v5.16b,v21.16b
uabal \arg0, v6.8b, v22.8b
uabal2 \arg0, v6.16b,v22.16b
uabal \arg0, v7.8b, v23.8b
uabal2 \arg0, v7.16b,v23.16b
.endm
.macro CALC_ABS_16X8_2 arg0
uab\arg0\()l v29.8h, v0.8b, v18.8b
uabal2 v29.8h, v0.16b,v18.16b
uabal v29.8h, v1.8b, v19.8b
uabal2 v29.8h, v1.16b,v19.16b
uabal v29.8h, v2.8b, v20.8b
uabal2 v29.8h, v2.16b,v20.16b
uabal v29.8h, v3.8b, v21.8b
uabal2 v29.8h, v3.16b,v21.16b
uabal v29.8h, v4.8b, v22.8b
uabal2 v29.8h, v4.16b,v22.16b
uabal v29.8h, v5.8b, v23.8b
uabal2 v29.8h, v5.16b,v23.16b
uabal v29.8h, v6.8b, v24.8b
uabal2 v29.8h, v6.16b,v24.16b
uabal v29.8h, v7.8b, v25.8b
uabal2 v29.8h, v7.16b,v25.16b
.endm
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSad4x4_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.s}[0], [x0], x1
ld1 {v1.s}[0], [x2], x3
uabdl v2.8h, v0.8b, v1.8b
.rept 3
ld1 {v0.s}[0], [x0], x1
ld1 {v1.s}[0], [x2], x3
uabal v2.8h, v0.8b, v1.8b
.endr
saddlv s2, v2.4h
fmov w0, s2
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSad8x8_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
uabdl v2.8h, v0.8b, v1.8b
.rept 7
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
uabal v2.8h, v0.8b, v1.8b
.endr
CALC_AND_STORE_SAD
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSad8x16_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
uabdl v2.8h, v0.8b, v1.8b
.rept 15
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
uabal v2.8h, v0.8b, v1.8b
.endr
CALC_AND_STORE_SAD
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSad16x8_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.16b}, [x0], x1
ld1 {v1.16b}, [x2], x3
uabdl v2.8h, v0.8b, v1.8b
uabal2 v2.8h, v0.16b, v1.16b
.rept 7
ld1 {v0.16b}, [x0], x1
ld1 {v1.16b}, [x2], x3
uabal v2.8h, v0.8b, v1.8b
uabal2 v2.8h, v0.16b, v1.16b
.endr
CALC_AND_STORE_SAD
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSad16x16_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.16b}, [x0], x1
ld1 {v1.16b}, [x2], x3
uabdl v2.8h, v0.8b, v1.8b
uabal2 v2.8h, v0.16b, v1.16b
.rept 15
ld1 {v0.16b}, [x0], x1
ld1 {v1.16b}, [x2], x3
uabal v2.8h, v0.8b, v1.8b
uabal2 v2.8h, v0.16b, v1.16b
.endr
CALC_AND_STORE_SAD
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSadFour4x4_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.s}[0], [x0], x1
ld1 {v0.s}[1], [x0], x1
ld1 {v1.s}[0], [x0], x1
ld1 {v1.s}[1], [x0]
sub x0, x2, x3
ld1 {v2.s}[0], [x0], x3
ld1 {v2.s}[1], [x0], x3
ld1 {v3.s}[0], [x0], x3
ld1 {v3.s}[1], [x0], x3
ld1 {v4.s}[0], [x0], x3
ld1 {v4.s}[1], [x0], x3
uabdl v28.8h, v0.8b, v2.8b
uabal v28.8h, v1.8b, v3.8b
uabdl v29.8h, v0.8b, v3.8b
uabal v29.8h, v1.8b, v4.8b
sub x0, x2, #1
ld1 {v2.s}[0], [x0], x3
ld1 {v2.s}[1], [x0], x3
ld1 {v3.s}[0], [x0], x3
ld1 {v3.s}[1], [x0]
uabdl v30.8h, v0.8b, v2.8b
uabal v30.8h, v1.8b, v3.8b
add x0, x2, #1
ld1 {v2.s}[0], [x0], x3
ld1 {v2.s}[1], [x0], x3
ld1 {v3.s}[0], [x0], x3
ld1 {v3.s}[1], [x0]
uabdl v31.8h, v0.8b, v2.8b
uabal v31.8h, v1.8b, v3.8b
CALC_AND_STORE_SAD_FOUR
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSadFour8x8_AArch64_neon
sxtw x1, w1
sxtw x3, w3
LOAD_8X8_1
sub x0, x2, x3
LOAD_8X8_2 x0
ld1 {v24.8b}, [x0], x3
ld1 {v25.8b}, [x0]
CALC_ABS_8X8_1 v28.8h, d
CALC_ABS_8X8_2 d
sub x0, x2, #1
LOAD_8X8_2 x0
CALC_ABS_8X8_1 v30.8h, d
add x0, x2, #1
LOAD_8X8_2 x0
CALC_ABS_8X8_1 v31.8h, d
CALC_AND_STORE_SAD_FOUR
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSadFour8x16_AArch64_neon
sxtw x1, w1
sxtw x3, w3
LOAD_8X8_1
sub x5, x2, x3
LOAD_8X8_2 x5
ld1 {v24.8b}, [x5], x3
ld1 {v25.8b}, [x5], x3
CALC_ABS_8X8_1 v28.8h, d
CALC_ABS_8X8_2 d
sub x6, x2, #1
LOAD_8X8_2 x6
CALC_ABS_8X8_1 v30.8h, d
add x7, x2, #1
LOAD_8X8_2 x7
CALC_ABS_8X8_1 v31.8h, d
LOAD_8X8_1
sub x5, x5, x3
sub x5, x5, x3
LOAD_8X8_2 x5
ld1 {v24.8b}, [x5], x3
ld1 {v25.8b}, [x5]
CALC_ABS_8X8_1 v28.8h, a
CALC_ABS_8X8_2 a
LOAD_8X8_2 x6
CALC_ABS_8X8_1 v30.8h, a
LOAD_8X8_2 x7
CALC_ABS_8X8_1 v31.8h, a
CALC_AND_STORE_SAD_FOUR
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSadFour16x8_AArch64_neon
sxtw x1, w1
sxtw x3, w3
LOAD_16X8_1
sub x0, x2, x3
LOAD_16X8_2 x0
ld1 {v24.16b}, [x0], x3
ld1 {v25.16b}, [x0]
CALC_ABS_16X8_1 v28.8h, d
CALC_ABS_16X8_2 d
sub x0, x2, #1
LOAD_16X8_2 x0
CALC_ABS_16X8_1 v30.8h, d
add x0, x2, #1
LOAD_16X8_2 x0
CALC_ABS_16X8_1 v31.8h, d
CALC_AND_STORE_SAD_FOUR
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSadFour16x16_AArch64_neon
sxtw x1, w1
sxtw x3, w3
LOAD_16X8_1
sub x5, x2, x3
LOAD_16X8_2 x5
ld1 {v24.16b}, [x5], x3
ld1 {v25.16b}, [x5], x3
CALC_ABS_16X8_1 v28.8h, d
CALC_ABS_16X8_2 d
sub x6, x2, #1
LOAD_16X8_2 x6
CALC_ABS_16X8_1 v30.8h, d
add x7, x2, #1
LOAD_16X8_2 x7
CALC_ABS_16X8_1 v31.8h, d
LOAD_16X8_1
sub x5, x5, x3
sub x5, x5, x3
LOAD_16X8_2 x5
ld1 {v24.16b}, [x5], x3
ld1 {v25.16b}, [x5]
CALC_ABS_16X8_1 v28.8h, a
CALC_ABS_16X8_2 a
LOAD_16X8_2 x6
CALC_ABS_16X8_1 v30.8h, a
LOAD_16X8_2 x7
CALC_ABS_16X8_1 v31.8h, a
CALC_AND_STORE_SAD_FOUR
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSatd4x4_AArch64_neon
sxtw x1, w1
sxtw x3, w3
ld1 {v0.s}[0], [x0], x1
ld1 {v0.s}[1], [x0], x1
ld1 {v1.s}[0], [x0], x1
ld1 {v1.s}[1], [x0]
ld1 {v2.s}[0], [x2], x3
ld1 {v2.s}[1], [x2], x3
ld1 {v3.s}[0], [x2], x3
ld1 {v3.s}[1], [x2]
usubl v4.8h, v0.8b, v2.8b //{0,1,2,3,4,5,6,7}
usubl v5.8h, v1.8b, v3.8b //{8,9,10,11,12,13,14,15}
//Do the vertical transform
add v6.8h, v4.8h, v5.8h //{0,4,8,12,1,5,9,13}
sub v7.8h, v4.8h, v5.8h //{2,6,10,14,3,7,11,15}
mov x4, v6.d[1]
mov v6.d[1], v7.d[0]
ins v7.d[0], x4
add v4.8h, v6.8h, v7.8h
sub v5.8h, v6.8h, v7.8h
//Do the horizontal transform
trn1 v6.4s, v4.4s, v5.4s
trn2 v7.4s, v4.4s, v5.4s
add v4.8h, v6.8h, v7.8h
sub v5.8h, v6.8h, v7.8h
trn1 v6.8h, v4.8h, v5.8h
trn2 v7.8h, v4.8h, v5.8h
add v4.8h, v6.8h, v7.8h
abs v4.8h, v4.8h
saba v4.8h, v6.8h, v7.8h
uaddlv s4, v4.8h
fmov w0, s4
add w0, w0, #1
lsr w0, w0, #1
WELS_ASM_AARCH64_FUNC_END
.macro SATD_8x4
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
ld1 {v2.8b}, [x0], x1
usubl v16.8h, v0.8b, v1.8b
ld1 {v3.8b}, [x2], x3
usubl v17.8h, v2.8b, v3.8b
ld1 {v4.8b}, [x0], x1
ld1 {v5.8b}, [x2], x3
add v25.8h, v16.8h, v17.8h
usubl v18.8h, v4.8b, v5.8b
ld1 {v6.8b}, [x0], x1
ld1 {v7.8b}, [x2], x3
usubl v19.8h, v6.8b, v7.8b
sub v26.8h, v16.8h, v17.8h
add v27.8h, v18.8h, v19.8h
sub v28.8h, v18.8h, v19.8h
add v0.8h, v25.8h, v27.8h
sub v1.8h, v25.8h, v27.8h
add v2.8h, v26.8h, v28.8h
sub v3.8h, v26.8h, v28.8h
trn1 v4.8h, v0.8h, v1.8h
trn2 v5.8h, v0.8h, v1.8h
trn1 v6.8h, v2.8h, v3.8h
trn2 v7.8h, v2.8h, v3.8h
add v16.8h, v4.8h, v5.8h
sabd v17.8h, v4.8h, v5.8h
abs v16.8h, v16.8h
add v18.8h, v6.8h, v7.8h
sabd v19.8h, v6.8h, v7.8h
abs v18.8h, v18.8h
trn1 v4.4s, v16.4s, v17.4s
trn2 v5.4s, v16.4s, v17.4s
trn1 v6.4s, v18.4s, v19.4s
trn2 v7.4s, v18.4s, v19.4s
smax v0.8h, v4.8h, v5.8h
smax v1.8h, v6.8h, v7.8h
.endm
.macro SATD_16x4
ld1 {v0.16b}, [x0], x1
ld1 {v1.16b}, [x2], x3
ld1 {v2.16b}, [x0], x1
usubl v16.8h, v0.8b, v1.8b
usubl2 v24.8h, v0.16b, v1.16b
ld1 {v3.16b}, [x2], x3
usubl v17.8h, v2.8b, v3.8b
usubl2 v25.8h, v2.16b, v3.16b
ld1 {v4.16b}, [x0], x1
ld1 {v5.16b}, [x2], x3
usubl v18.8h, v4.8b, v5.8b
usubl2 v26.8h, v4.16b, v5.16b
ld1 {v6.16b}, [x0], x1
ld1 {v7.16b}, [x2], x3
usubl v19.8h, v6.8b, v7.8b
usubl2 v27.8h, v6.16b, v7.16b
add v0.8h, v16.8h, v17.8h
sub v1.8h, v16.8h, v17.8h
add v2.8h, v18.8h, v19.8h
sub v3.8h, v18.8h, v19.8h
add v4.8h, v24.8h, v25.8h
sub v5.8h, v24.8h, v25.8h
add v6.8h, v26.8h, v27.8h
sub v7.8h, v26.8h, v27.8h
add v16.8h, v0.8h, v2.8h
sub v18.8h, v0.8h, v2.8h
add v17.8h, v4.8h, v6.8h
sub v19.8h, v4.8h, v6.8h
add v0.8h, v1.8h, v3.8h
sub v2.8h, v1.8h, v3.8h
add v1.8h, v5.8h, v7.8h
sub v3.8h, v5.8h, v7.8h
trn1 v4.8h, v16.8h, v18.8h
trn2 v6.8h, v16.8h, v18.8h
trn1 v5.8h, v17.8h, v19.8h
trn2 v7.8h, v17.8h, v19.8h
add v16.8h, v4.8h, v6.8h
sabd v18.8h, v4.8h, v6.8h
add v17.8h, v5.8h, v7.8h
sabd v19.8h, v5.8h, v7.8h
abs v16.8h, v16.8h
abs v17.8h, v17.8h
trn1 v4.8h, v0.8h, v2.8h
trn2 v6.8h, v0.8h, v2.8h
trn1 v5.8h, v1.8h, v3.8h
trn2 v7.8h, v1.8h, v3.8h
add v0.8h, v4.8h, v6.8h
sabd v2.8h, v4.8h, v6.8h
add v1.8h, v5.8h, v7.8h
sabd v3.8h, v5.8h, v7.8h
abs v0.8h, v0.8h
abs v1.8h, v1.8h
trn1 v4.4s, v16.4s, v18.4s
trn2 v6.4s, v16.4s, v18.4s
trn1 v5.4s, v17.4s, v19.4s
trn2 v7.4s, v17.4s, v19.4s
trn1 v16.4s, v0.4s, v2.4s
trn2 v18.4s, v0.4s, v2.4s
trn1 v17.4s, v1.4s, v3.4s
trn2 v19.4s, v1.4s, v3.4s
smax v0.8h, v4.8h, v6.8h
smax v1.8h, v5.8h, v7.8h
smax v2.8h, v16.8h, v18.8h
smax v3.8h, v17.8h, v19.8h
add v0.8h, v0.8h, v1.8h
add v2.8h, v2.8h, v3.8h
.endm
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSatd16x16_AArch64_neon
sxtw x1, w1
sxtw x3, w3
SATD_16x4
add v31.8h, v0.8h, v2.8h
.rept 3
SATD_16x4
add v31.8h, v31.8h, v0.8h
add v31.8h, v31.8h, v2.8h
.endr
uaddlv s4, v31.8h
fmov w0, s4
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSatd16x8_AArch64_neon
sxtw x1, w1
sxtw x3, w3
SATD_16x4
add v31.8h, v0.8h, v2.8h
SATD_16x4
add v31.8h, v31.8h, v0.8h
add v31.8h, v31.8h, v2.8h
uaddlv s4, v31.8h
fmov w0, s4
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSatd8x16_AArch64_neon
sxtw x1, w1
sxtw x3, w3
SATD_8x4
add v31.8h, v0.8h, v1.8h
.rept 3
SATD_8x4
add v31.8h, v31.8h, v0.8h
add v31.8h, v31.8h, v1.8h
.endr
uaddlv s4, v31.8h
fmov w0, s4
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsSampleSatd8x8_AArch64_neon
sxtw x1, w1
sxtw x3, w3
SATD_8x4
add v31.8h, v0.8h, v1.8h
SATD_8x4
add v31.8h, v31.8h, v0.8h
add v31.8h, v31.8h, v1.8h
uaddlv s4, v31.8h
fmov w0, s4
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 15,981 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm64/intra_pred_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
// for Luma 4x4
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredH_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, #1
.rept 4
ld1r {v0.8b}, [x3], x2
st1 {v0.S}[0], [x0], 4
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredDc_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
sub x4, x1, #1
ldr s0, [x3]
ld1 {v0.b}[4], [x4], x2
ld1 {v0.b}[5], [x4], x2
ld1 {v0.b}[6], [x4], x2
ld1 {v0.b}[7], [x4]
uaddlv h0, v0.8b
uqrshrn b0, h0, #3
dup v0.8b, v0.b[0]
.rept 4
st1 {v0.S}[0], [x0], 4
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredDcTop_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
sub v0.8b, v0.8b, v0.8b
ldr s0, [x3]
uaddlv h0, v0.8b
uqrshrn v0.8b, v0.8h, #2
dup v0.8b, v0.b[0]
.rept 4
st1 {v0.S}[0], [x0], 4
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredDDL_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.8b}, [x3]
dup v1.8b, v0.b[7]
ext v2.8b, v0.8b, v1.8b, #1
ext v3.8b, v0.8b, v1.8b, #2
ushll v2.8h, v2.8b, #1
uaddl v1.8h, v3.8b, v0.8b
add v1.8h, v1.8h, v2.8h
uqrshrn v1.8b, v1.8h, #2
st1 {v1.S}[0], [x0], 4
ext v0.8b, v1.8b, v2.8b, #1
st1 {v0.S}[0], [x0], 4
ext v0.8b, v1.8b, v2.8b, #2
st1 {v0.S}[0], [x0], 4
ext v0.8b, v1.8b, v2.8b, #3
st1 {v0.S}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredDDLTop_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.8b}, [x3]
dup v1.8b, v0.b[3]
mov v0.S[1], v1.S[0]
ext v2.8b, v0.8b, v1.8b, #1
ext v3.8b, v0.8b, v1.8b, #2
ushll v2.8h, v2.8b, #1
uaddl v1.8h, v3.8b, v0.8b
add v1.8h, v1.8h, v2.8h
uqrshrn v1.8b, v1.8h, #2
st1 {v1.S}[0], [x0], 4
ext v0.8b, v1.8b, v2.8b, #1
st1 {v0.S}[0], [x0], 4
ext v0.8b, v1.8b, v2.8b, #2
st1 {v0.S}[0], [x0], 4
ext v0.8b, v1.8b, v2.8b, #3
st1 {v0.S}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredVL_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.8b}, [x3]
ext v1.8b, v0.8b, v0.8b, #1
uaddl v1.8h, v1.8b, v0.8b
uqrshrn v0.8b, v1.8h, #1 // v0.8b is VL0, VL1, VL2, VL3, VL4, ...
ext v2.16b, v1.16b, v1.16b, #2
add v1.8h, v2.8h, v1.8h
uqrshrn v1.8b, v1.8h, #2 // v1.8b is VL5, VL6, VL7, VL8, VL9
st1 {v0.s}[0], [x0], 4 // write the first row
st1 {v1.s}[0], [x0], 4 // write the second row
ext v3.8b, v0.8b, v0.8b, #1
ext v2.8b, v1.8b, v1.8b, #1
st1 {v3.s}[0], [x0], 4 // write the third row
st1 {v2.s}[0], [x0] // write the fourth row
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredVLTop_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.8b}, [x3]
dup v1.8b, v0.b[3]
mov v0.s[1], v1.s[0]
ext v1.8b, v0.8b, v0.8b, #1
uaddl v1.8h, v1.8b, v0.8b
uqrshrn v0.8b, v1.8h, #1 // v0.8b is VL0, VL1, VL2, VL3, VL4, ...
ext v2.16b, v1.16b, v1.16b, #2
add v1.8h, v2.8h, v1.8h
uqrshrn v1.8b, v1.8h, #2 // v1.8b is VL5, VL6, VL7, VL8, VL9
st1 {v0.s}[0], [x0], 4 // write the first row
st1 {v1.s}[0], [x0], 4 // write the second row
ext v3.8b, v0.8b, v0.8b, #1
ext v2.8b, v1.8b, v1.8b, #1
st1 {v3.s}[0], [x0], 4 // write the third row
st1 {v2.s}[0], [x0] // write the fourth row
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredVR_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.s}[1], [x3]
sub x3, x3, #1
ld1 {v0.b}[3], [x3], x2
ld1 {v0.b}[2], [x3], x2
ld1 {v0.b}[1], [x3], x2
ld1 {v0.b}[0], [x3] // v0.8b l2, l1, l0, lt, t0, t1, t2, t3
ext v1.8b, v0.8b, v0.8b, #7
uaddl v2.8h, v1.8b, v0.8b //v2:{X,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1,T1+T2,T2+T3}
ext v1.16b, v2.16b, v2.16b, #14
add v3.8h, v2.8h, v1.8h //v3:{X,L2+L1+L1+L0,L1+L0+L0+LT,...T1+T2+T2+T3}
uqrshrn v3.8b, v3.8h, #2
uqrshrn v2.8b, v2.8h, #1
st1 {v2.s}[1], [x0], 4
st1 {v3.s}[1], [x0], 4
ext v2.8b, v2.8b, v2.8b, #7
ins v2.b[4], v3.b[3]
st1 {v2.s}[1], [x0], 4
ext v3.8b, v3.8b, v3.8b, #7
ins v3.b[4], v3.b[3]
st1 {v3.s}[1], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredHU_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, #1
mov x4, #3
mul x4, x4, x2
add x4, x4, x3
ld1r {v0.8b}, [x4]
ld1 {v0.b}[4], [x3], x2
ld1 {v0.b}[5], [x3], x2
ld1 {v0.b}[6], [x3], x2 //d0:{L3,L3,L3,L3,L0,L1,L2,L3}
ext v1.8b, v0.8b, v0.8b, #1
uaddl v2.8h, v0.8b, v1.8b //v2:{L3+L3,L3+L3,L3+L3,L3+L0,L0+L1,L1+L2,L2+L3,L3+L3}
ext v3.16b, v2.16b, v2.16b, #2
add v3.8h, v3.8h, v2.8h //v2:{x, HU1, HU3, HU5, x}
uqrshrn v2.8b, v2.8h, #1 // HU0, HU2, HU4
uqrshrn v3.8b, v3.8h, #2 // HU1, HU3, HU5
zip2 v3.8b, v2.8b, v3.8b // HU0, HU1, HU2, HU3, HU4, HU5
mov v3.h[3], v0.h[0] // v0.8b is hu0, hu1, hu2, hu3, hu4, hu5, l3, l3
ext v2.8b, v3.8b, v0.8b, #2
st1 {v3.s}[0], [x0], 4
st1 {v2.s}[0], [x0], 4
st1 {v3.s}[1], [x0], 4
st1 {v0.s}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI4x4LumaPredHD_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, #1
sub x3, x3, x2 // x2 points to top left
ld1 {v0.s}[1], [x3], x2
ld1 {v0.b}[3], [x3], x2
ld1 {v0.b}[2], [x3], x2
ld1 {v0.b}[1], [x3], x2
ld1 {v0.b}[0], [x3] // v0.8b: l3, l2, l1, l0, lt, t0, t1, t2
ext v1.8b, v0.8b, v0.8b, #1 // v1.8b: l2, l1, l0, lt, t0, t1, t2, l3
uaddl v2.8h, v0.8b, v1.8b
ext v3.16b, v2.16b, v2.16b, #2
add v3.8h, v3.8h, v2.8h
uqrshrn v2.8b, v2.8h, #1 // hd8, hd6, hd4, hd0, xxx
uqrshrn v3.8b, v3.8h, #2 // hd9, hd7, hd5, hd1, hd2, hd3
zip1 v2.8b, v2.8b, v3.8b // hd8, hd9, hd6, hd7, hd4, hd5, hd0, hd1
mov v1.h[0], v3.h[2]
ext v3.8b, v2.8b, v1.8b, #6
st1 {v3.s}[0], [x0], 4
st1 {v2.s}[1], [x0], 4
ext v3.8b, v2.8b, v1.8b, #2
st1 {v3.s}[0], [x0], 4
st1 {v2.s}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
// for Chroma 8x8
WELS_ASM_AARCH64_FUNC_BEGIN WelsIChromaPredV_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.8b}, [x3]
.rept 8
st1 {v0.8b}, [x0], 8
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsIChromaPredH_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, #1
.rept 8
ld1r {v0.8b}, [x3], x2
st1 {v0.8b}, [x0], 8
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsIChromaPredDc_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
sub x4, x1, #1
ld1 {v0.8b}, [x3]
ld1 {v0.b}[8], [x4], x2
ld1 {v0.b}[9], [x4], x2
ld1 {v0.b}[10], [x4], x2
ld1 {v0.b}[11], [x4], x2
ld1 {v0.b}[12], [x4], x2
ld1 {v0.b}[13], [x4], x2
ld1 {v0.b}[14], [x4], x2
ld1 {v0.b}[15], [x4]
uaddlp v1.8h, v0.16b
uaddlp v2.4s, v1.8h
ins v3.d[0], v2.d[1]
add v3.2s, v2.2s, v3.2s
urshr v2.4s, v2.4s, #2
urshr v3.2s, v3.2s, #3
dup v0.8b, v3.b[0]
dup v1.8b, v2.b[4]
dup v2.8b, v2.b[12]
dup v3.8b, v3.b[4]
ins v0.s[1], v1.s[0]
ins v2.s[1], v3.s[0]
.rept 4
st1 {v0.8b}, [x0], 8
.endr
.rept 4
st1 {v2.8b}, [x0], 8
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsIChromaPredDcTop_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.8b}, [x3]
uaddlp v0.4h, v0.8b
addp v0.8h, v0.8h, v0.8h
dup v1.8h, v0.h[0]
dup v2.8h, v0.h[1]
mov v1.D[1], v2.D[0]
uqrshrn v1.8b, v1.8h, #2
.rept 8
st1 {v1.8b}, [x0], 8
.endr
WELS_ASM_AARCH64_FUNC_END
.align 4
intra_1_to_4: .short 17*1, 17*2, 17*3, 17*4, 17*1, 17*2, 17*3, 17*4
intra_m3_to_p4: .short -3, -2, -1, 0, 1, 2, 3, 4
WELS_ASM_AARCH64_FUNC_BEGIN WelsIChromaPredPlane_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
sub x3, x3, #1
mov x4, x3
// load pTop[2-i] and pLeft[(2-i)*kiStride]
ld1 {v1.b}[3], [x3], #1
ld1 {v1.b}[2], [x3], #1
ld1 {v1.b}[1], [x3], #1
ld1 {v1.b}[0], [x3], #1
ld1 {v1.b}[7], [x4], x2
ld1 {v1.b}[6], [x4], x2
ld1 {v1.b}[5], [x4], x2
ld1 {v1.b}[4], [x4], x2
add x3, x3, #1
add x4, x4, x2
// load pTop[4+i] and pLeft[(4+i)*kiStride]
ld1 {v0.b}[0], [x3], #1
ld1 {v0.b}[1], [x3], #1
ld1 {v0.b}[2], [x3], #1
ld1 {v0.b}[3], [x3], #1
ld1 {v0.b}[4], [x4], x2
ld1 {v0.b}[5], [x4], x2
ld1 {v0.b}[6], [x4], x2
ld1 {v0.b}[7], [x4], x2
uxtl v1.8h, v1.8b
uxtl v0.8h, v0.8b
ldr q2, intra_1_to_4
ldr q3, intra_m3_to_p4
dup v4.8h, v0.h[3]
dup v5.8h, v0.h[7]
add v4.8h, v4.8h, v5.8h
sub v0.8h, v0.8h, v1.8h
shl v4.8h, v4.8h, #4 // v4.8h is a
mul v0.8h, v0.8h, v2.8h // v0.h[0-3] is H, v0.h[4-7] is V
saddlp v0.4s, v0.8h
addp v0.4s, v0.4s, v0.4s // v0.s[0] is H, v0.s[1] is V
sqrshrn v0.4h, v0.4s, #5
dup v1.8h, v0.h[0] // v1.8h is b
dup v0.8h, v0.h[1] // v0.8h is c
mla v4.8h, v1.8h, v3.8h
mla v4.8h, v0.8h, v3.h[0]
sqrshrun v1.8b, v4.8h, #5
st1 {v1.8b}, [x0], 8
.rept 7
add v4.8h, v4.8h, v0.8h
sqrshrun v1.8b, v4.8h, #5
st1 {v1.8b}, [x0], 8
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI16x16LumaPredDc_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
sub x4, x1, #1
ld1 {v0.16b}, [x3]
ld1 {v1.b}[0], [x4], x2
ld1 {v1.b}[1], [x4], x2
ld1 {v1.b}[2], [x4], x2
ld1 {v1.b}[3], [x4], x2
ld1 {v1.b}[4], [x4], x2
ld1 {v1.b}[5], [x4], x2
ld1 {v1.b}[6], [x4], x2
ld1 {v1.b}[7], [x4], x2
ld1 {v1.b}[8], [x4], x2
ld1 {v1.b}[9], [x4], x2
ld1 {v1.b}[10], [x4], x2
ld1 {v1.b}[11], [x4], x2
ld1 {v1.b}[12], [x4], x2
ld1 {v1.b}[13], [x4], x2
ld1 {v1.b}[14], [x4], x2
ld1 {v1.b}[15], [x4]
// reduce instruction
uaddlv h0, v0.16b
uaddlv h1, v1.16b
add v0.8h, v0.8h, v1.8h
uqrshrn b0, h0, #5
dup v0.16b, v0.b[0]
.rept 16
st1 {v0.16b}, [x0], 16
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI16x16LumaPredDcTop_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.16b}, [x3]
// reduce instruction
uaddlv h0, v0.16b
uqrshrn v0.8b, v0.8h, 4
dup v0.16b, v0.b[0]
.rept 16
st1 {v0.16b}, [x0], 16
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsI16x16LumaPredDcLeft_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, #1
ld1 {v1.b}[0], [x3], x2
ld1 {v1.b}[1], [x3], x2
ld1 {v1.b}[2], [x3], x2
ld1 {v1.b}[3], [x3], x2
ld1 {v1.b}[4], [x3], x2
ld1 {v1.b}[5], [x3], x2
ld1 {v1.b}[6], [x3], x2
ld1 {v1.b}[7], [x3], x2
ld1 {v1.b}[8], [x3], x2
ld1 {v1.b}[9], [x3], x2
ld1 {v1.b}[10], [x3], x2
ld1 {v1.b}[11], [x3], x2
ld1 {v1.b}[12], [x3], x2
ld1 {v1.b}[13], [x3], x2
ld1 {v1.b}[14], [x3], x2
ld1 {v1.b}[15], [x3]
// reduce instruction
uaddlv h1, v1.16b
uqrshrn v0.8b, v1.8h, #4
dup v0.16b, v0.b[0]
.rept 16
st1 {v0.16b}, [x0], 16
.endr
WELS_ASM_AARCH64_FUNC_END
.align 4
intra_1_to_8: .short 5, 10, 15, 20, 25, 30, 35, 40
intra_m7_to_p8: .short -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8
//void WelsI16x16LumaPredPlane_AArch64_neon (uint8_t* pPred, uint8_t* pRef, const int32_t kiStride);
WELS_ASM_AARCH64_FUNC_BEGIN WelsI16x16LumaPredPlane_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
sub x3, x3, #1
mov x4, x3
ld1 {v0.8b}, [x4] // v0 low 8 bit in top(reverse order)
add x4, x4, #9
rev64 v0.8b, v0.8b // reverse v0
ld1 {v1.8b}, [x4] // v1 high 8 bit in top
uxtl v0.8h, v0.8b // extend to 16 bit integer
uxtl v1.8h, v1.8b // extend to 16 bit integer
ld1 {v2.b}[7], [x3], x2
ld1 {v2.b}[6], [x3], x2
ld1 {v2.b}[5], [x3], x2
ld1 {v2.b}[4], [x3], x2
ld1 {v2.b}[3], [x3], x2
ld1 {v2.b}[2], [x3], x2
ld1 {v2.b}[1], [x3], x2
ld1 {v2.b}[0], [x3], x2 // v2.8b low 8 bit in left
add x3, x3, x2
ld1 {v3.b}[0], [x3], x2
ld1 {v3.b}[1], [x3], x2
ld1 {v3.b}[2], [x3], x2
ld1 {v3.b}[3], [x3], x2
ld1 {v3.b}[4], [x3], x2
ld1 {v3.b}[5], [x3], x2
ld1 {v3.b}[6], [x3], x2
ld1 {v3.b}[7], [x3] // v3.8b high 8bit in left
uxtl v2.8h, v2.8b
uxtl v3.8h, v3.8b
sub v0.8h, v1.8h, v0.8h
sub v2.8h, v3.8h, v2.8h
ldr q4, intra_1_to_8
mul v0.8h, v0.8h, v4.8h
mul v2.8h, v2.8h, v4.8h
saddlv s0, v0.8h
saddlv s2, v2.8h
add v1.8h, v1.8h, v3.8h
sqrshrn v0.4h, v0.4S, #6 // b is in v0.h[0]
sqrshrn v2.4h, v2.4S, #6 // c is in v2.h[0]
shl v1.8h, v1.8h, #4 // a is in v1.h[7]
ldr q4, intra_m7_to_p8
ldr q5, intra_m7_to_p8 + 16
dup v1.8h, v1.h[7]
dup v3.8h, v1.h[7]
mla v1.8h, v4.8h, v0.h[0]
mla v3.8h, v5.8h, v0.h[0]
dup v2.8h, v2.h[0] // v2.8h is [cccccccc]
mla v1.8h, v2.8h, v4.h[0]
mla v3.8h, v2.8h, v4.h[0]
sqrshrun v4.8b, v1.8h, #5
sqrshrun2 v4.16b, v3.8h, #5
st1 {v4.16b}, [x0], 16
.rept 15
add v1.8h, v1.8h, v2.8h
add v3.8h, v3.8h, v2.8h
sqrshrun v4.8b, v1.8h, #5
sqrshrun2 v4.16b, v3.8h, #5
st1 {v4.16b}, [x0], 16
.endr
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 9,447 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm64/svc_motion_estimation_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
//int32_t SumOf8x8SingleBlock_AArch64_neon (uint8_t* pRef, const int32_t kiRefStride);
WELS_ASM_AARCH64_FUNC_BEGIN SumOf8x8SingleBlock_AArch64_neon
SIGN_EXTENSION x1,w1
ld1 {v0.d}[0], [x0], x1
ld1 {v0.d}[1], [x0], x1
ld1 {v1.d}[0], [x0], x1
ld1 {v1.d}[1], [x0], x1
ld1 {v2.d}[0], [x0], x1
ld1 {v2.d}[1], [x0], x1
ld1 {v3.d}[0], [x0], x1
ld1 {v3.d}[1], [x0]
uaddlp v0.8h, v0.16b
uadalp v0.8h, v1.16b
uadalp v0.8h, v2.16b
uadalp v0.8h, v3.16b
uaddlv s0, v0.8h
mov x0, v0.d[0]
WELS_ASM_AARCH64_FUNC_END
//int32_t SumOf16x16SingleBlock_AArch64_neon (uint8_t* pRef, const int32_t kiRefStride);
WELS_ASM_AARCH64_FUNC_BEGIN SumOf16x16SingleBlock_AArch64_neon
SIGN_EXTENSION x1,w1
ld1 {v0.16b}, [x0], x1
uaddlp v0.8h, v0.16b
.rept 15
ld1 {v1.16b}, [x0], x1
uadalp v0.8h, v1.16b
.endr
uaddlv s0, v0.8h
mov x0, v0.d[0]
WELS_ASM_AARCH64_FUNC_END
//void SumOf8x8BlockOfFrame_AArch64_neon (uint8_t* pRefPicture, const int32_t kiWidth, const int32_t kiHeight,
// const int32_t kiRefStride,
// uint16_t* pFeatureOfBlock, uint32_t pTimesOfFeatureValue[]);
WELS_ASM_AARCH64_FUNC_BEGIN SumOf8x8BlockOfFrame_AArch64_neon
//(uint8_t* pRefPicture, const int32_t kiWidth, const int32_t kiHeight,const int32_t kiRefStride,uint16_t* pFeatureOfBlock, uint32_t pTimesOfFeatureValue[])
//x5: pTimesOfFeatureValue
//x4: pFeatureOfBlock
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x2,w2
SIGN_EXTENSION x3,w3
mov x8, x0
mov x6, x1
add x8, x8, x6
add x4, x4, x6, lsl #1
mov x7, x6
_width_loop8x8_1:
subs x0, x8, x7
ld1 {v0.d}[0], [x0], x3
ld1 {v0.d}[1], [x0], x3
ld1 {v1.d}[0], [x0], x3
ld1 {v1.d}[1], [x0], x3
ld1 {v2.d}[0], [x0], x3
ld1 {v2.d}[1], [x0], x3
ld1 {v3.d}[0], [x0], x3
ld1 {v3.d}[1], [x0]
uaddlp v0.8h, v0.16b
uadalp v0.8h, v1.16b
uadalp v0.8h, v2.16b
uadalp v0.8h, v3.16b
uaddlv s0, v0.8h
subs x1, x4, x7, lsl #1
st1 {v0.h}[0], [x1] // sum -> pFeatureOfBlock[i]
mov w0, #0
ins v0.s[1], w0
mov x0, v0.d[0]
add x1, x5, x0, lsl #2
ldr w0, [x1]
add w0, w0, #1
str w0, [x1]
subs x7, x7, #1
cbnz x7, _width_loop8x8_1
add x8, x8, x3
add x4, x4, x6, lsl #1
subs x2, x2, #1
cbz x2, _SumOf8x8BlockOfFrame_AArch64_neon_end
_height_loop8x8:
mov x7, x6
_width_loop8x8_2:
subs x0, x8, x7
subs x1, x4, x7, lsl #1
subs x9, x1, x6, lsl #1 // last line of pFeatureOfBlock[i]
ldrh w10, [x9] // sum of last line of pFeatureOfBlock[i]
subs x11, x0, x3
ld1 {v0.d}[1], [x11]
add x0, x11, x3, lsl #3
ld1 {v0.d}[0], [x0] //
uaddlp v0.8h, v0.16b
addp v0.8h, v0.8h, v1.8h
uaddlp v0.4s, v0.8h
umov w11, v0.s[0]
umov w12, v0.s[1]
subs w10, w10, w12
mov x0, #0
add w0, w10, w11
strh w0, [x1] // sum -> pFeatureOfBlock[i]
add x1, x5, x0, lsl #2
ldr w0, [x1]
add w0, w0, #1
str w0, [x1]
subs x7, x7, #1
cbnz x7, _width_loop8x8_2
add x8, x8, x3
add x4, x4, x6, lsl #1
subs x2, x2, #1
cbnz x2, _height_loop8x8
_SumOf8x8BlockOfFrame_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN SumOf16x16BlockOfFrame_AArch64_neon
//(uint8_t* pRefPicture, const int32_t kiWidth, const int32_t kiHeight,const int32_t kiRefStride,uint16_t* pFeatureOfBlock, uint32_t pTimesOfFeatureValue[])
//x5: pTimesOfFeatureValue
//x4: pFeatureOfBlock
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x2,w2
SIGN_EXTENSION x3,w3
mov x8, x0
mov x6, x1
add x8, x8, x6
add x4, x4, x6, lsl #1
mov x7, x6
_width_loop16x16_1:
subs x0, x8, x7
ld1 {v0.16b}, [x0], x3
uaddlp v0.8h, v0.16b
.rept 15
ld1 {v1.16b}, [x0], x3
uadalp v0.8h, v1.16b
.endr
uaddlv s0, v0.8h
subs x1, x4, x7, lsl #1
st1 {v0.h}[0], [x1] // sum -> pFeatureOfBlock[i]
mov w0, #0
ins v0.s[1], w0
mov x0, v0.d[0]
add x1, x5, x0, lsl #2
ldr w0, [x1]
add w0, w0, #1
str w0, [x1]
subs x7, x7, #1
cbnz x7, _width_loop16x16_1
add x8, x8, x3
add x4, x4, x6, lsl #1
subs x2, x2, #1
cbz x2, _SumOf16x16BlockOfFrame_AArch64_neon_end
_height_loop16x16:
mov x7, x6
_width_loop16x16_2:
subs x0, x8, x7
subs x1, x4, x7, lsl #1
subs x9, x1, x6, lsl #1 // last line of pFeatureOfBlock[i]
ldrh w10, [x9] // sum of last line of pFeatureOfBlock[i]
subs x11, x0, x3
ld1 {v1.16b}, [x11]
add x0, x11, x3, lsl #4
ld1 {v0.16b}, [x0] //
uaddlv h0, v0.16b
uaddlv h1, v1.16b
umov w11, v0.h[0]
umov w12, v1.h[0]
subs w10, w10, w12
mov x0, #0
add w0, w10, w11
strh w0, [x1] // sum -> pFeatureOfBlock[i]
add x1, x5, x0, lsl #2
ldr w0, [x1]
add w0, w0, #1
str w0, [x1]
subs x7, x7, #1
cbnz x7, _width_loop16x16_2
add x8, x8, x3
add x4, x4, x6, lsl #1
subs x2, x2, #1
cbnz x2, _height_loop16x16
_SumOf16x16BlockOfFrame_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN InitializeHashforFeature_AArch64_neon
// (uint32_t* pTimesOfFeatureValue, uint16_t* pBuf, const int32_t kiListSize, uint16_t** pLocationOfFeature, uint16_t** pFeatureValuePointerList);
SIGN_EXTENSION x2,w2
mov x9, #3
bic x5, x2, x9
mov x8, #0
_hash_assign_loop_x4:
ld1 {v0.16b}, [x0], #16
shl v0.4s, v0.4s, #2
addv s1, v0.4s
umov w7, v1.s[0]
cbz w7, _hash_assign_with_copy_x4
ins v2.d[0], x1
umov w8, v0.s[0]
add x1, x1, x8
ins v2.d[1], x1
umov w8, v0.s[1]
add x1, x1, x8
ins v3.d[0], x1
umov w8, v0.s[2]
add x1, x1, x8
ins v3.d[1], x1
umov w8, v0.s[3]
add x1, x1, x8
st1 {v2.16b, v3.16b}, [x3], #32
st1 {v2.16b, v3.16b}, [x4], #32
b _assign_next
_hash_assign_with_copy_x4:
dup v2.2d, x1
dup v3.2d, x1
st1 {v2.16b, v3.16b}, [x3], #32
st1 {v2.16b, v3.16b}, [x4], #32
_assign_next:
subs x5, x5, #4
cbnz x5, _hash_assign_loop_x4
and x5, x2, x9
cbz x5, _hash_assign_end
_hash_assign_loop_x4_rem:
str x1, [x3], #8
str x1, [x4], #8
ldr w8, [x0], #4
lsl w8, w8, #2
add x1, x1, x8
subs x5, x5, #1
cbnz x5, _hash_assign_loop_x4_rem
_hash_assign_end:
WELS_ASM_AARCH64_FUNC_END
.align 4
mv_x_inc_x4: .short 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00
mv_y_inc_x4: .short 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00
mx_x_offset_x4: .short 0x00, 0x04, 0x08, 0x0c, 0x00, 0x00, 0x00, 0x00
WELS_ASM_AARCH64_FUNC_BEGIN FillQpelLocationByFeatureValue_AArch64_neon
// void (uint16_t* pFeatureOfBlock, const int32_t kiWidth, const int32_t kiHeight, uint16_t** pFeatureValuePointerList)
ldr q7, mv_x_inc_x4
ldr q6, mv_y_inc_x4
ldr q5, mx_x_offset_x4
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x2,w2
eor v4.16b, v4.16b, v4.16b
eor v3.16b, v3.16b, v3.16b
dup v16.2d, x3 // v8->v16
_hash_height_loop:
mov x7, x1
mov v2.16b, v5.16b //mx_x_offset_x4
_hash_width_loop:
ld1 {v0.d}[0], [x0], #8
ushll v0.4s, v0.4h, #3
uaddw v17.2d, v16.2d, v0.2s
uaddw2 v18.2d, v16.2d, v0.4s
zip1 v1.8h, v2.8h, v3.8h
umov x4, v17.d[0]
ldr x5, [x4]
umov w6, v1.s[0]
str w6, [x5]
add x5, x5, #4
str x5, [x4]
umov x4, v17.d[1]
ldr x5, [x4]
umov w6, v1.s[1]
str w6, [x5]
add x5, x5, #4
str x5, [x4]
umov x4, v18.d[0]
ldr x5, [x4]
umov w6, v1.s[2]
str w6, [x5]
add x5, x5, #4
str x5, [x4]
umov x4, v18.d[1]
ldr x5, [x4]
umov w6, v1.s[3]
str w6, [x5]
add x5, x5, #4
str x5, [x4]
add v2.8h, v2.8h, v7.8h
subs x7, x7, #4
cbnz x7, _hash_width_loop
add v3.8h, v3.8h, v6.8h
subs x2, x2, #1
cbnz x2, _hash_height_loop
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,243 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm64/memory_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
//void WelsSetMemZero_AArch64_neon (void* pDst, int32_t iSize);
WELS_ASM_AARCH64_FUNC_BEGIN WelsSetMemZero_AArch64_neon
eor v0.16b, v0.16b, v0.16b
SIGN_EXTENSION x1,w1
cmp x1, #32
b.eq mem_zero_32_neon_start
b.lt mem_zero_24_neon_start
mem_zero_loop:
subs x1, x1, #64
st1 {v0.16b}, [x0], #16
st1 {v0.16b}, [x0], #16
st1 {v0.16b}, [x0], #16
st1 {v0.16b}, [x0], #16
b.ne mem_zero_loop
b mem_zero_end
mem_zero_32_neon_start:
st1 {v0.16b}, [x0], #16
st1 {v0.16b}, [x0], #16
b mem_zero_end
mem_zero_24_neon_start:
st1 {v0.16b}, [x0], #16
st1 {v0.8b}, [x0], #8
mem_zero_end:
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 26,960 | test/prod_decoder/codec/3rdparty/openh264/codec/encoder/core/arm64/reconstruct_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro ZERO_COUNT_IN_2_QUARWORD arg0, arg1, arg2
// { // input: coef_0 (identy to \arg3\() \arg4\()), coef_1(identy to \arg5\() \arg6\()), mask_q
cmeq \arg0\().8h, \arg0\().8h, #0
cmeq \arg1\().8h, \arg1\().8h, #0
uzp1 \arg0\().16b, \arg0\().16b, \arg1\().16b
ushr \arg0\().16b, \arg0\().16b, 7
addv \arg2\(), \arg0\().16b
// }
.endm
.macro NEWQUANT_COEF_EACH_16BITS arg0, arg1, arg2, arg3, arg4, arg5
// if coef <= 0, - coef; else , coef;
// { // input: coef, ff (dst), mf
eor \arg3\().16b, \arg3\().16b, \arg3\().16b // init 0 , and keep 0;
saba \arg1\().8h, \arg0\().8h, \arg3\().8h // f + abs(coef - 0)
smull \arg4\().4s, \arg1\().4h, \arg2\().4h
smull2 \arg5\().4s, \arg1\().8h, \arg2\().8h
shrn \arg1\().4h, \arg4\().4s, #16
shrn2 \arg1\().8h, \arg5\().4s, #16
cmgt \arg4\().8h, \arg0\().8h, #0 // if true, location of coef == 11111111
bif \arg3\().16b, \arg1\().16b, \arg4\().16b // if (x<0) reserved part; else keep 0 untouched
shl \arg3\().8h, \arg3\().8h, #1
sub \arg1\().8h, \arg1\().8h, \arg3\().8h // if x > 0, -= 0; else x-= 2x
// }
.endm
.macro NEWQUANT_COEF_EACH_16BITS_MAX arg0, arg1, arg2, arg3, arg4, arg5, arg6
// if coef <= 0, - coef; else , coef;
// { // input: coef, ff (dst), mf
eor \arg3\().16b, \arg3\().16b, \arg3\().16b // init 0 , and keep 0;
saba \arg1\().8h, \arg0\().8h, \arg3\().8h // f + abs(coef - 0)
smull \arg4\().4s, \arg1\().4h, \arg2\().4h
smull2 \arg5\().4s, \arg1\().8h, \arg2\().8h
shrn \arg1\().4h, \arg4\().4s, #16
shrn2 \arg1\().8h, \arg5\().4s, #16
cmgt \arg4\().8h, \arg0\().8h, #0 // if true, location of coef == 11111111
bif \arg3\().16b, \arg1\().16b, \arg4\().16b // if (x<0) reserved part; else keep 0 untouched
shl \arg3\().8h, \arg3\().8h, #1
mov \arg6\().16b, \arg1\().16b
sub \arg1\().8h, \arg1\().8h, \arg3\().8h // if x > 0, -= 0; else x-= 2x
// }
.endm
.macro QUANT_DUALWORD_COEF_EACH_16BITS arg0, arg1, arg2, arg3, arg4
// if coef <= 0, - coef; else , coef;
// { // input: coef, ff (dst), mf
saba \arg1\().8h, \arg0\().8h, \arg3\().8h // f + abs(coef - 0)
smull \arg4\().4s, \arg1\().4h, \arg2\().4h
shrn \arg1\().4h, \arg4\().4s, #16
cmgt \arg4\().8h, \arg0\().8h, #0 // if true, location of coef == 11111111
bif \arg3\().16b, \arg1\().16b, \arg4\().16b // if (x<0) reserved part; else keep 0 untouched
shl \arg3\().8h, \arg3\().8h, #1
sub \arg1\().8h, \arg1\().8h, \arg3\().8h // if x > 0, -= 0; else x-= 2x
// }
.endm
.macro SELECT_MAX_IN_ABS_COEF arg0, arg1, arg2, arg3, arg4, arg5
// { // input: coef_0, coef_1, coef_2, coef_3, max_q (identy to follow two)
umax \arg0\().8h, \arg0\().8h, \arg1\().8h
umaxv \arg4\(), \arg0\().8h
umax \arg2\().8h, \arg2\().8h, \arg3\().8h
umaxv \arg5\(), \arg2\().8h
// }
.endm
.macro HDM_QUANT_2x2_TOTAL_16BITS arg0, arg1, arg2
// { // input: src_d[0][16][32][48], dst_d[0][16][32][48], working
sshr \arg1\().2d, \arg0\().2d, #32
add \arg2\().4h, \arg0\().4h, \arg1\().4h // [0] = rs[0] + rs[32];[1] = rs[16] + rs[48];
sub \arg1\().4h, \arg0\().4h, \arg1\().4h // [0] = rs[0] - rs[32];[1] = rs[16] - rs[48];
zip1 \arg1\().4h, \arg2\().4h, \arg1\().4h
// }
.endm
.macro DC_ZERO_COUNT_IN_DUALWORD arg0, arg1, arg2
// { // input: coef, dst_d, working_d (all 0x01)
cmeq \arg0\().4h, \arg0\().4h, #0
and \arg0\().8b, \arg0\().8b, \arg2\().8b
addv \arg1\(), \arg0\().4h
// }
.endm
.macro IHDM_4x4_TOTAL_16BITS arg0, arg1, arg2
// { // input: each src_d[0]~[3](dst), working_q0, working_q1
uzp2 \arg1\().4s, \arg0\().4s, \arg0\().4s
uzp1 \arg0\().4s, \arg0\().4s, \arg0\().4s
add \arg2\().8h, \arg0\().8h, \arg1\().8h // [0] = rs[0] + rs[2];[1] = rs[1] + rs[3];[2] = rs[4] + rs[6];[3] = rs[5] + rs[7];
sub \arg1\().8h, \arg0\().8h, \arg1\().8h // [0] = rs[0] - rs[2];[1] = rs[1] - rs[3];[2] = rs[4] - rs[6];[3] = rs[5] - rs[7];
zip1 \arg2\().8h, \arg2\().8h, \arg1\().8h // [0] = rs[0] + rs[2]; [1] = rs[0] - rs[2]; ... [2]; [3]
uzp2 \arg1\().4s, \arg2\().4s, \arg2\().4s
uzp1 \arg0\().4s, \arg2\().4s, \arg2\().4s
add \arg2\().8h, \arg0\().8h, \arg1\().8h // [0] = rs[0] + rs[2];[1] = rs[1] + rs[3];[2] = rs[4] + rs[6];[3] = rs[5] + rs[7];
sub \arg1\().8h, \arg0\().8h, \arg1\().8h // [0] = rs[0] - rs[2];[1] = rs[1] - rs[3];[2] = rs[4] - rs[6];[3] = rs[5] - rs[7];
rev32 \arg1\().4h, \arg1\().4h // [0] = rs[1] - rs[3];[1] = rs[0] - rs[2];[2] = rs[5] - rs[7];[3] = rs[4] - rs[6];
zip1 \arg0\().4s, \arg2\().4s, \arg1\().4s
// }
.endm
.macro MATRIX_TRANSFORM_EACH_16BITS_2x8_OUT2 arg0, arg1, arg2, arg3
// { // input & output: src_d[0]~[3];[0 1 2 3]+[4 5 6 7]+[8 9 10 11]+[12 13 14 15]
uzp1 \arg2\().4s, \arg0\().4s, \arg1\().4s //[0 1 4 5]+[8 9 12 13]
uzp2 \arg3\().4s, \arg0\().4s, \arg1\().4s //[2 3 6 7]+[10 11 14 15]
uzp1 \arg0\().8h, \arg2\().8h, \arg3\().8h //[0 4 8 12]+[2 6 10 14]
uzp2 \arg2\().8h, \arg2\().8h, \arg3\().8h //[1 5 9 13]+[3 7 11 15]
zip2 \arg1\().2d, \arg0\().2d, \arg2\().2d //[2 6 10 14]+[3 7 11 15]
zip1 \arg0\().2d, \arg0\().2d, \arg2\().2d //[0 4 8 12]+[1 5 9 13]
// }
.endm
.macro MATRIX_TRANSFORM_EACH_16BITS_OUT4 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input & output: src_d[0]~[3];[0 4 8 12],[1 5 9 13],[2 6 10 14],[3 7 11 15]
trn1 \arg4\().8h, v0.8h, v1.8h
trn2 \arg5\().8h, v0.8h, v1.8h
trn1 \arg6\().8h, v2.8h, v3.8h
trn2 \arg7\().8h, v2.8h, v3.8h
trn1 \arg0\().4s, v4.4s, v6.4s
trn2 \arg2\().4s, v4.4s, v6.4s
trn1 \arg1\().4s, v5.4s, v7.4s
trn2 \arg3\().4s, v5.4s, v7.4s
// }
.endm
.macro MATRIX_TRANSFORM_EACH_16BITS_4x4_OUT2 arg0, arg1, arg2, arg3
// { // input & output: src_d[0]~[3];[0 1 2 3],[4 5 6 7],[8 9 10 11],[12 13 14 15]
mov \arg0\().d[1], \arg1\().d[0] //[0 1 2 3]+[4 5 6 7]
mov \arg2\().d[1], \arg3\().d[0] //[8 9 10 11]+[12 13 14 15]
uzp1 \arg1\().4s, \arg0\().4s, \arg2\().4s //[0 1 4 5]+[8 9 12 13]
uzp2 \arg3\().4s, \arg0\().4s, \arg2\().4s //[2 3 6 7]+[10 11 14 15]
uzp1 \arg0\().8h, \arg1\().8h, \arg3\().8h //[0 4 8 12]+[2 6 10 14]
uzp2 \arg2\().8h, \arg1\().8h, \arg3\().8h //[1 5 9 13]+[3 7 11 15]
zip2 \arg1\().2d, \arg0\().2d, \arg2\().2d //[2 6 10 14]+[3 7 11 15]
zip1 \arg0\().2d, \arg0\().2d, \arg2\().2d //[0 4 8 12]+[1 5 9 13]
// }
.endm
.macro LOAD_4x4_DATA_FOR_DCT arg0, arg1, arg2, arg3, arg4, arg5
ld1 {\arg0\().s}[0], [\arg2\()], \arg3\()
ld1 {\arg0\().s}[1], [\arg2\()], \arg3\()
ld1 {\arg0\().s}[2], [\arg2\()], \arg3\()
ld1 {\arg0\().s}[3], [\arg2\()]
ld1 {\arg1\().s}[0], [\arg4\()], \arg5\()
ld1 {\arg1\().s}[1], [\arg4\()], \arg5\()
ld1 {\arg1\().s}[2], [\arg4\()], \arg5\()
ld1 {\arg1\().s}[3], [\arg4\()]
.endm
.macro DCT_ROW_TRANSFORM_TOTAL_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_d[0]~[3], working: [4]~[7]
add \arg4\().8h, \arg0\().8h, \arg3\().8h //int16 s[0] = data[i] + data[i3];
sub \arg7\().8h, \arg0\().8h, \arg3\().8h //int16 s[3] = data[i] - data[i3];
add \arg5\().8h, \arg1\().8h, \arg2\().8h //int16 s[1] = data[i1] + data[i2];
sub \arg6\().8h, \arg1\().8h, \arg2\().8h //int16 s[2] = data[i1] - data[i2];
add \arg0\().8h, \arg4\().8h, \arg5\().8h //int16 dct[i ] = s[0] + s[1];
sub \arg2\().8h, \arg4\().8h, \arg5\().8h //int16 dct[i2] = s[0] - s[1];
shl \arg1\().8h, \arg7\().8h, #1
shl \arg3\().8h, \arg6\().8h, #1
add \arg1\().8h, \arg1\().8h, \arg6\().8h //int16 dct[i1] = (s[3] << 1) + s[2];
sub \arg3\().8h, \arg7\().8h, \arg3\().8h //int16 dct[i3] = s[3] - (s[2] << 1);
// }
.endm
.macro LOAD_8x4_DATA_FOR_DCT arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
// { // input: \arg0\()~\arg3\(), src1*, src2*; untouched r2:src1_stride &r4:src2_stride
ld1 {\arg0\().d}[0], [\arg8\()], x2
ld1 {\arg1\().d}[0], [\arg8\()], x2
ld1 {\arg2\().d}[0], [\arg8\()], x2
ld1 {\arg3\().d}[0], [\arg8\()], x2
ld1 {\arg4\().d}[0], [\arg9\()], x4
ld1 {\arg5\().d}[0], [\arg9\()], x4
ld1 {\arg6\().d}[0], [\arg9\()], x4
ld1 {\arg7\().d}[0], [\arg9\()], x4
// }
.endm
.macro ROW_TRANSFORM_1_STEP_TOTAL_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_d[0]~[3], output: e_d[0]~[3];
add \arg4\().8h, \arg0\().8h, \arg2\().8h //int16 e[i][0] = src[0] + src[2];
sub \arg5\().8h, \arg0\().8h, \arg2\().8h //int16 e[i][1] = src[0] - src[2];
sshr \arg6\().8h, \arg1\().8h, #1
sshr \arg7\().8h, \arg3\().8h, #1
sub \arg6\().8h, \arg6\().8h, \arg3\().8h //int16 e[i][2] = (src[1]>>1)-src[3];
add \arg7\().8h, \arg1\().8h, \arg7\().8h //int16 e[i][3] = src[1] + (src[3]>>1);
// }
.endm
.macro TRANSFORM_TOTAL_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// both row & col transform used
// { // output: f_q[0]~[3], input: e_q[0]~[3];
add \arg0\().8h, \arg4\().8h, \arg7\().8h //int16 f[i][0] = e[i][0] + e[i][3];
add \arg1\().8h, \arg5\().8h, \arg6\().8h //int16 f[i][1] = e[i][1] + e[i][2];
sub \arg2\().8h, \arg5\().8h, \arg6\().8h //int16 f[i][2] = e[i][1] - e[i][2];
sub \arg3\().8h, \arg4\().8h, \arg7\().8h //int16 f[i][3] = e[i][0] - e[i][3];
// }
.endm
.macro ROW_TRANSFORM_0_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_d[0]~[3], output: e_q[0]~[3];
saddl \arg4\().4s, \arg0\().4h, \arg2\().4h //int32 e[i][0] = src[0] + src[2];
ssubl \arg5\().4s, \arg0\().4h, \arg2\().4h //int32 e[i][1] = src[0] - src[2];
ssubl \arg6\().4s, \arg1\().4h, \arg3\().4h //int32 e[i][2] = src[1] - src[3];
saddl \arg7\().4s, \arg1\().4h, \arg3\().4h //int32 e[i][3] = src[1] + src[3];
// }
.endm
.macro COL_TRANSFORM_0_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_q[0]~[3], output: e_q[0]~[3];
add \arg4\().4s, \arg0\().4s, \arg2\().4s //int32 e[0][j] = f[0][j] + f[2][j];
sub \arg5\().4s, \arg0\().4s, \arg2\().4s //int32 e[1][j] = f[0][j] - f[2][j];
sub \arg6\().4s, \arg1\().4s, \arg3\().4s //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
add \arg7\().4s, \arg1\().4s, \arg3\().4s //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
// }
.endm
.macro TRANSFORM_4BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// both row & col transform used
// { // output: f_q[0]~[3], input: e_q[0]~[3];
add \arg0\().4s, \arg4\().4s, \arg7\().4s //int16 f[i][0] = e[i][0] + e[i][3];
add \arg1\().4s, \arg5\().4s, \arg6\().4s //int16 f[i][1] = e[i][1] + e[i][2];
sub \arg2\().4s, \arg5\().4s, \arg6\().4s //int16 f[i][2] = e[i][1] - e[i][2];
sub \arg3\().4s, \arg4\().4s, \arg7\().4s //int16 f[i][3] = e[i][0] - e[i][3];
// }
.endm
.macro MB_PRED_8BITS_ADD_DCT_16BITS_CLIP arg0, arg1, arg2, arg3, arg4
// { // input: pred_d[0](output), dct_q0/1, working_q0/1;
uxtl \arg3\().8h, \arg0\().8b
uxtl2 \arg4\().8h, \arg0\().16b
add \arg3\().8h, \arg3\().8h, \arg1\().8h
add \arg4\().8h, \arg4\().8h, \arg2\().8h
sqxtun \arg0\().8b, \arg3\().8h
sqxtun2 \arg0\().16b,\arg4\().8h
// }
.endm
WELS_ASM_AARCH64_FUNC_BEGIN WelsGetNoneZeroCount_AArch64_neon
ld1 {v0.8h, v1.8h}, [x0]
ZERO_COUNT_IN_2_QUARWORD v0, v1, b0
mov x0, v0.d[0]
mov x1, #16
subs x0, x1, x0
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsQuant4x4_AArch64_neon
ld1 {v2.8h}, [x1]
ld1 {v0.8h, v1.8h}, [x0]
ld1 {v3.8h}, [x2]
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS v0, v2, v3, v5, v6, v7
st1 {v2.8h}, [x0], #16
NEWQUANT_COEF_EACH_16BITS v1, v4, v3, v5, v6, v7
st1 {v4.8h}, [x0], #16
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsQuant4x4Dc_AArch64_neon
ld1 {v0.8h, v1.8h}, [x0]
dup v2.8h, w1 // even ff range [0, 768]
dup v3.8h, w2
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS v0, v2, v3, v5, v6, v7
st1 {v2.8h}, [x0], #16
NEWQUANT_COEF_EACH_16BITS v1, v4, v3, v5, v6, v7
st1 {v4.8h}, [x0], #16
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsQuantFour4x4_AArch64_neon
ld1 {v2.8h}, [x1]
ld1 {v3.8h}, [x2]
mov x1, x0
.rept 4
ld1 {v0.8h, v1.8h}, [x0], #32
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS v0, v4, v3, v5, v6, v7
st1 {v4.8h}, [x1], #16
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS v1, v4, v3, v5, v6, v7
st1 {v4.8h}, [x1], #16
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsQuantFour4x4Max_AArch64_neon
ld1 {v2.8h}, [x1]
ld1 {v3.8h}, [x2]
mov x1, x0
ld1 {v0.8h, v1.8h}, [x0], #32
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v0, v4, v3, v5, v6, v7, v16
st1 {v4.8h}, [x1], #16
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v1, v4, v3, v5, v6, v7, v17
st1 {v4.8h}, [x1], #16 // then 1st 16 elem in v16 & v17
ld1 {v0.8h, v1.8h}, [x0], #32
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v0, v4, v3, v5, v6, v7, v18
st1 {v4.8h}, [x1], #16
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v1, v4, v3, v5, v6, v7, v19
st1 {v4.8h}, [x1], #16 // then 2st 16 elem in v18 & v19
SELECT_MAX_IN_ABS_COEF v16, v17, v18, v19, h20, h21
ld1 {v0.8h, v1.8h}, [x0], #32
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v0, v4, v3, v5, v6, v7, v16
st1 {v4.8h}, [x1], #16
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v1, v4, v3, v5, v6, v7, v17
st1 {v4.8h}, [x1], #16 // then 1st 16 elem in v16 & v17
ld1 {v0.8h, v1.8h}, [x0], #32
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v0, v4, v3, v5, v6, v7, v18
st1 {v4.8h}, [x1], #16
mov v4.16b, v2.16b
NEWQUANT_COEF_EACH_16BITS_MAX v1, v4, v3, v5, v6, v7, v19
st1 {v4.8h}, [x1], #16 // then 2st 16 elem in v18 & v19
SELECT_MAX_IN_ABS_COEF v16, v17, v18, v19, h22, h23
st4 {v20.h,v21.h,v22.h,v23.h}[0], [x3]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDequant4x4_AArch64_neon
ld1 {v0.8h, v1.8h}, [x0]
ld1 {v2.8h}, [x1]
mul v3.8h, v0.8h, v2.8h
mul v4.8h, v1.8h, v2.8h
st1 {v3.8h, v4.8h}, [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDequantFour4x4_AArch64_neon
ld1 {v2.8h}, [x1]
mov x1, x0
.rept 4
ld1 {v0.8h,v1.8h}, [x0], #32
mul v3.8h, v0.8h, v2.8h
mul v4.8h, v1.8h, v2.8h
st1 {v3.8h,v4.8h}, [x1], #32
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsHadamardQuant2x2SkipKernel_AArch64_neon
dup v4.8h, w1
mov x1, #32
ld1 {v0.h}[0], [x0], x1 //rs[0]
ld1 {v0.h}[1], [x0], x1 //rs[16]
ld1 {v0.h}[2], [x0], x1 //rs[32]
ld1 {v0.h}[3], [x0], x1 //rs[48]
HDM_QUANT_2x2_TOTAL_16BITS v0, v1, v2 // output v1
HDM_QUANT_2x2_TOTAL_16BITS v1, v0, v2 // output v0
abs v1.4h, v0.4h
cmhi v0.4h, v1.4h, v4.4h // abs(dct[i])>threshold;
mov w0, v0.s[0]
mov w1, v0.s[1]
orr w0, w0, w1
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsHadamardQuant2x2_AArch64_neon
dup v1.8h, w1 //ff
dup v2.8h, w2 //mf
eor v3.16b, v3.16b, v3.16b
mov x1, #32
mov x2, x0
ld1 {v0.h}[0], [x0], x1 //rs[0]
st1 {v3.h}[0], [x2], x1 //rs[00]=0
ld1 {v0.h}[1], [x0], x1 //rs[16]
st1 {v3.h}[1], [x2], x1 //rs[16]=0
ld1 {v0.h}[2], [x0], x1 //rs[32]
st1 {v3.h}[2], [x2], x1 //rs[32]=0
ld1 {v0.h}[3], [x0], x1 //rs[48]
st1 {v3.h}[3], [x2], x1 //rs[48]=0
HDM_QUANT_2x2_TOTAL_16BITS v0, v4, v5 // output v4
HDM_QUANT_2x2_TOTAL_16BITS v4, v0, v5 // output v0
QUANT_DUALWORD_COEF_EACH_16BITS v0, v1, v2, v3, v4
st1 {v1.d}[0], [x3] // store to dct
st1 {v1.d}[0], [x4] // store to block
movi v3.8h, #1, lsl #0
movi v0.16b, #255
DC_ZERO_COUNT_IN_DUALWORD v1, h0, v3
mov x0, v0.d[0]
mov x1, #4
subs x0, x1, x0
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDequantIHadamard4x4_AArch64_neon
ld1 {v0.8h, v1.8h}, [x0]
dup v4.8h, w1
IHDM_4x4_TOTAL_16BITS v0, v2, v3
IHDM_4x4_TOTAL_16BITS v1, v2, v3
MATRIX_TRANSFORM_EACH_16BITS_2x8_OUT2 v0, v1, v2, v3
IHDM_4x4_TOTAL_16BITS v0, v2, v3
mul v0.8h, v0.8h, v4.8h
IHDM_4x4_TOTAL_16BITS v1, v2, v3
mul v1.8h, v1.8h, v4.8h
MATRIX_TRANSFORM_EACH_16BITS_2x8_OUT2 v0, v1, v2, v3
st1 {v0.16b, v1.16b}, [x0]
WELS_ASM_AARCH64_FUNC_END
//void WelsDctT4_AArch64_neon (int16_t* pDct, uint8_t* pPixel1, int32_t iStride1, uint8_t* pPixel2, int32_t iStride2);
WELS_ASM_AARCH64_FUNC_BEGIN WelsDctT4_AArch64_neon
SIGN_EXTENSION x2, w2
SIGN_EXTENSION x4, w4
LOAD_4x4_DATA_FOR_DCT v0, v1, x1, x2, x3, x4
usubl v2.8h, v0.8b, v1.8b
usubl2 v4.8h, v0.16b, v1.16b
uzp1 v3.8h, v2.8h, v4.8h
uzp2 v5.8h, v2.8h, v4.8h
uzp2 v2.8h, v3.8h, v5.8h // s[2, 6, 10, 14] [3, 7, 11, 15]
uzp1 v0.8h, v3.8h, v5.8h // s[0, 4, 8, 12] [1, 5, 9, 13]
mov v3.d[0], v2.d[1] // s[3, 7, 11, 15]
mov v1.d[0], v0.d[1] // s[1, 5, 9, 13]
// horizontal transform
DCT_ROW_TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
// transform element
MATRIX_TRANSFORM_EACH_16BITS_OUT4 v0, v1, v2, v3, v4, v5, v6, v7
// vertical transform
DCT_ROW_TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
st4 {v0.d, v1.d, v2.d, v3.d}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
//void WelsDctFourT4_AArch64_neon (int16_t* pDct, uint8_t* pPixel1, int32_t iStride1, uint8_t* pPixel2, int32_t iStride2);
WELS_ASM_AARCH64_FUNC_BEGIN WelsDctFourT4_AArch64_neon
SIGN_EXTENSION x2,w2
SIGN_EXTENSION x4,w4
.rept 2
LOAD_8x4_DATA_FOR_DCT v0, v1, v2, v3, v4, v5, v6, v7, x1, x3
usubl v0.8h, v0.8b, v4.8b
usubl v1.8h, v1.8b, v5.8b
usubl v2.8h, v2.8b, v6.8b
usubl v3.8h, v3.8b, v7.8b
MATRIX_TRANSFORM_EACH_16BITS_OUT4 v0, v1, v2, v3, v4, v5, v6, v7
// horizontal transform
DCT_ROW_TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
// transform element
MATRIX_TRANSFORM_EACH_16BITS_OUT4 v0, v1, v2, v3, v4, v5, v6, v7
// vertical transform
DCT_ROW_TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
uzp1 v4.2d, v0.2d, v1.2d
uzp2 v6.2d, v0.2d, v1.2d
uzp1 v5.2d, v2.2d, v3.2d
uzp2 v7.2d, v2.2d, v3.2d
st1 {v4.16b, v5.16b}, [x0], #32
st1 {v6.16b, v7.16b}, [x0], #32
.endr
WELS_ASM_AARCH64_FUNC_END
//void WelsIDctT4Rec_AArch64_neon (uint8_t* pRec, int32_t iStride, uint8_t* pPrediction, int32_t iPredStride, int16_t* pDct)
WELS_ASM_AARCH64_FUNC_BEGIN WelsIDctT4Rec_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
ld1 {v16.s}[0], [x2], x3
ld1 {v16.s}[1], [x2], x3
ld1 {v16.s}[2], [x2], x3
ld1 {v16.s}[3], [x2], x3 // Pred
ld4 {v0.4h, v1.4h, v2.4h, v3.4h}, [x4] // dct coeff
ROW_TRANSFORM_1_STEP_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
MATRIX_TRANSFORM_EACH_16BITS_OUT4 v0, v1, v2, v3, v4, v5, v6, v7
ROW_TRANSFORM_1_STEP_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
ins v0.d[1], v1.d[0]
ins v2.d[1], v3.d[0]
srshr v0.8h, v0.8h, #6
srshr v2.8h, v2.8h, #6
//after rounding 6, clip into [0, 255]
uxtl v1.8h, v16.8b
add v0.8h, v0.8h, v1.8h
sqxtun v1.8b, v0.8h
st1 {v1.s}[0],[x0],x1
st1 {v1.s}[1],[x0],x1
uxtl2 v1.8h, v16.16b
add v2.8h, v2.8h, v1.8h
sqxtun v1.8b, v2.8h
st1 {v1.s}[0],[x0],x1
st1 {v1.s}[1],[x0],x1
WELS_ASM_AARCH64_FUNC_END
//void WelsIDctFourT4Rec_AArch64_neon (uint8_t* pRec, int32_t iStride, uint8_t* pPrediction, int32_t iPredStride, int16_t* pDct);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIDctFourT4Rec_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
.rept 2
ld1 {v16.d}[0], [x2], x3
ld1 {v16.d}[1], [x2], x3
ld1 {v17.d}[0], [x2], x3
ld1 {v17.d}[1], [x2], x3 // Pred
ld4 {v0.8h, v1.8h, v2.8h, v3.8h}, [x4], #64 // dct coeff
ROW_TRANSFORM_1_STEP_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
MATRIX_TRANSFORM_EACH_16BITS_OUT4 v0, v1, v2, v3, v4, v5, v6, v7
ROW_TRANSFORM_1_STEP_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
TRANSFORM_TOTAL_16BITS v0, v1, v2, v3, v4, v5, v6, v7
srshr v0.8h, v0.8h, #6
srshr v1.8h, v1.8h, #6
srshr v2.8h, v2.8h, #6
srshr v3.8h, v3.8h, #6
//after rounding 6, clip into [0, 255]
uxtl v4.8h, v16.8b
add v0.8h, v0.8h, v4.8h
sqxtun v0.8b, v0.8h
st1 {v0.d}[0],[x0],x1
uxtl2 v5.8h, v16.16b
add v1.8h, v1.8h, v5.8h
sqxtun v1.8b, v1.8h
st1 {v1.d}[0],[x0],x1
uxtl v6.8h, v17.8b
add v2.8h, v2.8h, v6.8h
sqxtun v2.8b, v2.8h
st1 {v2.d}[0],[x0],x1
uxtl2 v7.8h, v17.16b
add v3.8h, v3.8h, v7.8h
sqxtun v3.8b, v3.8h
st1 {v3.d}[0],[x0],x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsHadamardT4Dc_AArch64_neon
mov x2, #32
ld1 {v0.h}[0], [x1], x2
ld1 {v1.h}[0], [x1], x2
ld1 {v0.h}[1], [x1], x2
ld1 {v1.h}[1], [x1], x2
ld1 {v2.h}[0], [x1], x2
ld1 {v3.h}[0], [x1], x2
ld1 {v2.h}[1], [x1], x2
ld1 {v3.h}[1], [x1], x2
ld1 {v0.h}[2], [x1], x2
ld1 {v1.h}[2], [x1], x2
ld1 {v0.h}[3], [x1], x2
ld1 {v1.h}[3], [x1], x2
ld1 {v2.h}[2], [x1], x2
ld1 {v3.h}[2], [x1], x2
ld1 {v2.h}[3], [x1], x2
ld1 {v3.h}[3], [x1], x2 // v0[0 4 08 12],v1[1 5 09 13],v2[2 6 10 14],v3[3 7 11 15]
ROW_TRANSFORM_0_STEP v0, v1, v3, v2, v4, v7, v6, v5
TRANSFORM_4BYTES v0, v1, v3, v2, v4, v7, v6, v5
// transform element 32bits
uzp1 v4.4s, v0.4s, v1.4s // 0 2 4 6
uzp2 v5.4s, v0.4s, v1.4s // 1 3 5 7
uzp1 v6.4s, v2.4s, v3.4s // 8 10 12 14
uzp2 v7.4s, v2.4s, v3.4s // 9 11 13 15
uzp1 v0.4s, v4.4s, v6.4s // 0 4 8 12
uzp2 v2.4s, v4.4s, v6.4s // 2 6 10 14
uzp1 v1.4s, v5.4s, v7.4s // 1 5 9 13
uzp2 v3.4s, v5.4s, v7.4s // 3 7 11 15
COL_TRANSFORM_0_STEP v0, v1, v3, v2, v4, v7, v6, v5
TRANSFORM_4BYTES v0, v1, v3, v2, v4, v7, v6, v5
sqrshrn v4.4h, v0.4s, #1
sqrshrn2 v4.8h, v1.4s, #1
sqrshrn v5.4h, v2.4s, #1
sqrshrn2 v5.8h, v3.4s, #1
st1 {v4.16b, v5.16b}, [x0] //store
WELS_ASM_AARCH64_FUNC_END
//void WelsIDctRecI16x16Dc_AArch64_neon (uint8_t* pRec, int32_t iStride, uint8_t* pPrediction, int32_t iPredStride,
// int16_t* pDctDc);
WELS_ASM_AARCH64_FUNC_BEGIN WelsIDctRecI16x16Dc_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
ld1 {v16.16b,v17.16b}, [x4]
srshr v16.8h, v16.8h, #6
srshr v17.8h, v17.8h, #6
dup v0.8h, v16.h[0]
dup v1.8h, v16.h[1]
ins v0.d[1], v1.d[0]
dup v1.8h, v16.h[2]
dup v2.8h, v16.h[3]
ins v1.d[1], v2.d[0]
.rept 4
ld1 {v3.16b}, [x2], x3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP v3, v0, v1, v4, v5
st1 {v3.16b}, [x0], x1
.endr
dup v0.8h, v16.h[4]
dup v1.8h, v16.h[5]
ins v0.d[1], v1.d[0]
dup v1.8h, v16.h[6]
dup v2.8h, v16.h[7]
ins v1.d[1], v2.d[0]
.rept 4
ld1 {v3.16b}, [x2], x3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP v3, v0, v1, v4, v5
st1 {v3.16b}, [x0], x1
.endr
dup v0.8h, v17.h[0]
dup v1.8h, v17.h[1]
ins v0.d[1], v1.d[0]
dup v1.8h, v17.h[2]
dup v2.8h, v17.h[3]
ins v1.d[1], v2.d[0]
.rept 4
ld1 {v3.16b}, [x2], x3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP v3, v0, v1, v4, v5
st1 {v3.16b}, [x0], x1
.endr
dup v0.8h, v17.h[4]
dup v1.8h, v17.h[5]
ins v0.d[1], v1.d[0]
dup v1.8h, v17.h[6]
dup v2.8h, v17.h[7]
ins v1.d[1], v2.d[0]
.rept 4
ld1 {v3.16b}, [x2], x3
MB_PRED_8BITS_ADD_DCT_16BITS_CLIP v3, v0, v1, v4, v5
st1 {v3.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,610 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm/intra_pred_common_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
WELS_ASM_FUNC_BEGIN WelsI16x16LumaPredV_neon
//Get the top line data to 'q0'
sub r3, r1, r2
vldm r3, {d0, d1}
//mov r2, #16
mov r3, #4
//Set the top line to the each line of MB(16*16)
loop_0_get_i16x16_luma_pred_v:
vst1.8 {d0,d1}, [r0]!
vst1.8 {d0,d1}, [r0]!
vst1.8 {d0,d1}, [r0]!
vst1.8 {d0,d1}, [r0]!
subs r3, #1
bne loop_0_get_i16x16_luma_pred_v
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsI16x16LumaPredH_neon
//stmdb sp!, {r4, lr}
sub r1, r1, #1
mov r3, #4
loop_0_get_i16x16_luma_pred_h:
//Get one byte data from left side
vld1.8 {d0[],d1[]}, [r1], r2
vld1.8 {d2[],d3[]}, [r1], r2
vld1.8 {d4[],d5[]}, [r1], r2
vld1.8 {d6[],d7[]}, [r1], r2
//Set the line of MB using the left side byte data
vst1.8 {d0,d1}, [r0]!
//add r0, #16
vst1.8 {d2,d3}, [r0]!
//add r0, #16
vst1.8 {d4,d5}, [r0]!
//add r0, #16
vst1.8 {d6,d7}, [r0]!
//add r0, #16
subs r3, #1
bne loop_0_get_i16x16_luma_pred_h
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,026 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm/arm_arch_common_macro.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
.syntax unified
#ifdef __APPLE__
.text
.macro WELS_ASM_FUNC_BEGIN
.align 2
.arm
.globl _$0
_$0:
.endm
.macro WELS_ASM_FUNC_END
mov pc, lr
.endm
#else
.section .note.GNU-stack,"",%progbits // Mark stack as non-executable
.text
.arch armv7-a
.fpu neon
.macro WELS_ASM_FUNC_BEGIN funcName
.align 2
.arm
.global \funcName
.type \funcName, %function
#ifndef __clang__
.func \funcName
#endif
\funcName:
.endm
.macro WELS_ASM_FUNC_END
mov pc, lr
#ifndef __clang__
.endfunc
#endif
.endm
#endif
#endif
|
xiangxud/webrtc_H265player | 23,685 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm/deblocking_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro JMP_IF_128BITS_IS_ZERO arg0, arg1, arg2
vorr.s16 \arg2, \arg0, \arg1
vmov r3, r2, \arg2
orr r3, r3, r2
cmp r3, #0
.endm
.macro MASK_MATRIX arg0, arg1, arg2, arg3, arg4, arg5, arg6
vabd.u8 \arg6, \arg1, \arg2
vcgt.u8 \arg6, \arg4, \arg6
vabd.u8 \arg4, \arg0, \arg1
vclt.u8 \arg4, \arg4, \arg5
vand.u8 \arg6, \arg6, \arg4
vabd.u8 \arg4, \arg3, \arg2
vclt.u8 \arg4, \arg4, \arg5
vand.u8 \arg6, \arg6, \arg4
.endm
.macro DIFF_LUMA_LT4_P1_Q1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
vmov.i8 \arg9, #128
vrhadd.u8 \arg8, \arg2, \arg3
vhadd.u8 \arg8, \arg0, \arg8
vsub.s8 \arg8, \arg8, \arg9
vsub.s8 \arg9, \arg1, \arg9
vqsub.s8 \arg8, \arg8, \arg9
vmax.s8 \arg8, \arg8, \arg5
vmin.s8 \arg8, \arg8, \arg6
vabd.u8 \arg9, \arg0, \arg2
vclt.u8 \arg9, \arg9, \arg4
vand.s8 \arg8, \arg8, \arg9
vand.s8 \arg8, \arg8, \arg7
vadd.u8 \arg8, \arg1, \arg8
vabs.s8 \arg9, \arg9
.endm
.macro DIFF_LUMA_LT4_P0_Q0 arg0, arg1, arg2, arg3, arg4, arg5, arg6
vsubl.u8 \arg5, \arg0, \arg3
vsubl.u8 \arg6, \arg2, \arg1
vshl.s16 \arg6, \arg6, #2
vadd.s16 \arg5, \arg5, \arg6
vqrshrn.s16 \arg4, \arg5, #3
.endm
.macro DIFF_LUMA_EQ4_P2P1P0 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
vaddl.u8 q4, \arg1, \arg2
vaddl.u8 q5, \arg3, \arg4
vadd.u16 q5, q4, q5
vaddl.u8 q4, \arg0, \arg1
vshl.u16 q4, q4, #1
vadd.u16 q4, q5, q4
vrshrn.u16 \arg0, q5, #2
vrshrn.u16 \arg7, q4, #3
vshl.u16 q5, q5, #1
vsubl.u8 q4, \arg5, \arg1
vadd.u16 q5, q4,q5
vaddl.u8 q4, \arg2, \arg5
vaddw.u8 q4, q4, \arg2
vaddw.u8 q4, q4, \arg3
vrshrn.u16 d10,q5, #3
vrshrn.u16 d8, q4, #2
vbsl.u8 \arg6, d10, d8
.endm
.macro DIFF_LUMA_EQ4_MASK arg0, arg1, arg2, arg3
vmov \arg3, \arg2
vbsl.u8 \arg3, \arg0, \arg1
.endm
.macro DIFF_CHROMA_EQ4_P0Q0 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
vaddl.u8 \arg4, \arg0, \arg3
vaddw.u8 \arg5, \arg4, \arg1
vaddw.u8 \arg6, \arg4, \arg2
vaddw.u8 \arg5, \arg5, \arg0
vaddw.u8 \arg6, \arg6, \arg3
vrshrn.u16 \arg7, \arg5, #2
vrshrn.u16 \arg8, \arg6, #2
.endm
.macro LOAD_CHROMA_DATA_4 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
vld4.u8 {\arg0[\arg8],\arg1[\arg8],\arg2[\arg8],\arg3[\arg8]}, [r0], r2
vld4.u8 {\arg4[\arg8],\arg5[\arg8],\arg6[\arg8],\arg7[\arg8]}, [r1], r2
.endm
.macro STORE_CHROMA_DATA_4 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
vst4.u8 {\arg0[\arg8],\arg1[\arg8],\arg2[\arg8],\arg3[\arg8]}, [r0], r2
vst4.u8 {\arg4[\arg8],\arg5[\arg8],\arg6[\arg8],\arg7[\arg8]}, [r1], r2
.endm
.macro LOAD_LUMA_DATA_3 arg0, arg1, arg2, arg3, arg4, arg5, arg6
vld3.u8 {\arg0[\arg6],\arg1[\arg6],\arg2[\arg6]}, [r2], r1
vld3.u8 {\arg3[\arg6],\arg4[\arg6],\arg5[\arg6]}, [r0], r1
.endm
.macro STORE_LUMA_DATA_4 arg0, arg1, arg2, arg3, arg4, arg5
vst4.u8 {\arg0[\arg4],\arg1[\arg4],\arg2[\arg4],\arg3[\arg4]}, [r0], r1
vst4.u8 {\arg0[\arg5],\arg1[\arg5],\arg2[\arg5],\arg3[\arg5]}, [r2], r1
.endm
.macro STORE_LUMA_DATA_3 arg0, arg1, arg2, arg3, arg4, arg5, arg6
vst3.u8 {\arg0[\arg6],\arg1[\arg6],\arg2[\arg6]}, [r3], r1
vst3.u8 {\arg3[\arg6],\arg4[\arg6],\arg5[\arg6]}, [r0], r1
.endm
.macro EXTRACT_DELTA_INTO_TWO_PART arg0, arg1
vcge.s8 \arg1, \arg0, #0
vand \arg1, \arg0, \arg1
vsub.s8 \arg0, \arg1, \arg0
.endm
WELS_ASM_FUNC_BEGIN DeblockLumaLt4V_neon
vpush {q4-q7}
vdup.u8 q11, r2
vdup.u8 q9, r3
add r2, r1, r1, lsl #1
sub r2, r0, r2
vld1.u8 {q0}, [r2], r1
vld1.u8 {q3}, [r0], r1
vld1.u8 {q1}, [r2], r1
vld1.u8 {q4}, [r0], r1
vld1.u8 {q2}, [r2]
vld1.u8 {q5}, [r0]
sub r2, r2, r1
ldr r3, [sp, #64]
vld1.s8 {d31}, [r3]
vdup.s8 d28, d31[0]
vdup.s8 d30, d31[1]
vdup.s8 d29, d31[2]
vdup.s8 d31, d31[3]
vtrn.32 d28, d30
vtrn.32 d29, d31
vcge.s8 q10, q14, #0
MASK_MATRIX q1, q2, q3, q4, q11, q9, q15
vand.u8 q10, q10, q15
veor q15, q15
vsub.i8 q15,q15,q14
DIFF_LUMA_LT4_P1_Q1 q0, q1, q2, q3, q9, q15, q14, q10, q6, q12
vst1.u8 {q6}, [r2], r1
DIFF_LUMA_LT4_P1_Q1 q5, q4, q3, q2, q9, q15, q14, q10, q7, q13
vabs.s8 q12, q12
vabs.s8 q13, q13
vadd.u8 q14,q14,q12
vadd.u8 q14,q14,q13
veor q15, q15
vsub.i8 q15,q15,q14
DIFF_LUMA_LT4_P0_Q0 d2, d4, d6, d8, d16, q12, q13
DIFF_LUMA_LT4_P0_Q0 d3, d5, d7, d9, d17, q12, q13
vmax.s8 q8, q8, q15
vmin.s8 q8, q8, q14
vand.s8 q8, q8, q10
EXTRACT_DELTA_INTO_TWO_PART q8, q9
vqadd.u8 q2, q2, q9
vqsub.u8 q2, q2, q8
vst1.u8 {q2}, [r2], r1
vqsub.u8 q3, q3, q9
vqadd.u8 q3, q3, q8
vst1.u8 {q3}, [r2] , r1
vst1.u8 {q7}, [r2]
vpop {q4-q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockLumaEq4V_neon
vpush {q4-q7}
vdup.u8 q5, r2
vdup.u8 q4, r3
sub r3, r0, r1, lsl #2
vld1.u8 {q8}, [r3], r1
vld1.u8 {q12}, [r0], r1
vld1.u8 {q9}, [r3], r1
vld1.u8 {q13}, [r0], r1
vld1.u8 {q10}, [r3], r1
vld1.u8 {q14}, [r0], r1
vld1.u8 {q11}, [r3]
vld1.u8 {q15}, [r0]
sub r3, r3, r1 , lsl #1
MASK_MATRIX q10, q11, q12, q13, q5, q4, q6
mov r2, r2, lsr #2
add r2, r2, #2
vdup.u8 q5, r2
vabd.u8 q0, q11, q12
vclt.u8 q7, q0, q5
vabd.u8 q1, q9, q11
vclt.u8 q1, q1, q4
vand.s8 q1, q1, q7
vabd.u8 q2, q14,q12
vclt.u8 q2, q2, q4
vand.s8 q2, q2, q7
vand.u8 q7, q7, q6
vmov q3, q1
DIFF_LUMA_EQ4_P2P1P0 d16, d18, d20, d22, d24, d26, d2, d0
DIFF_LUMA_EQ4_P2P1P0 d17, d19, d21, d23, d25, d27, d3, d1
vand.u8 q3, q7, q3
DIFF_LUMA_EQ4_MASK q0, q9, q3, q4
vst1.u8 {q4}, [r3], r1
DIFF_LUMA_EQ4_MASK q8,q10, q3, q4
vst1.u8 {q4}, [r3], r1
DIFF_LUMA_EQ4_MASK q1,q11, q6, q4
vst1.u8 {q4}, [r3], r1
vmov q0, q2
DIFF_LUMA_EQ4_P2P1P0 d30, d28, d26, d24, d22, d20, d4, d6
DIFF_LUMA_EQ4_P2P1P0 d31, d29, d27, d25, d23, d21, d5, d7
vand.u8 q0, q7, q0
DIFF_LUMA_EQ4_MASK q2, q12, q6, q4
vst1.u8 {q4}, [r3], r1
DIFF_LUMA_EQ4_MASK q15, q13, q0, q4
vst1.u8 {q4}, [r3], r1
DIFF_LUMA_EQ4_MASK q3, q14, q0, q4
vst1.u8 {q4}, [r3], r1
vpop {q4-q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockLumaLt4H_neon
vpush {q4-q7}
vdup.u8 q11, r2
vdup.u8 q9, r3
sub r2, r0, #3
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 0
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 1
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 2
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 3
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 4
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 5
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 6
LOAD_LUMA_DATA_3 d0, d1, d2, d6, d7, d8, 7
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 0
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 1
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 2
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 3
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 4
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 5
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 6
LOAD_LUMA_DATA_3 d3, d4, d5, d9, d10, d11, 7
vswp d1, d2
vswp d3, d4
vswp d1, d4
vswp d7, d8
vswp d9, d10
vswp d7, d10
sub r0, r0, r1, lsl #4
ldr r3, [sp, #64]
vld1.s8 {d31}, [r3]
vdup.s8 d28, d31[0]
vdup.s8 d30, d31[1]
vdup.s8 d29, d31[2]
vdup.s8 d31, d31[3]
vtrn.32 d28, d30
vtrn.32 d29, d31
vcge.s8 q10, q14, #0
MASK_MATRIX q1, q2, q3, q4, q11, q9, q15
vand.u8 q10, q10, q15
veor q15, q15
vsub.i8 q15,q15,q14
DIFF_LUMA_LT4_P1_Q1 q0, q1, q2, q3, q9, q15, q14, q10, q6, q12
DIFF_LUMA_LT4_P1_Q1 q5, q4, q3, q2, q9, q15, q14, q10, q7, q13
vabs.s8 q12, q12
vabs.s8 q13, q13
vadd.u8 q14,q14,q12
vadd.u8 q14,q14,q13
veor q15, q15
vsub.i8 q15,q15,q14
DIFF_LUMA_LT4_P0_Q0 d2, d4, d6, d8, d16, q12, q13
DIFF_LUMA_LT4_P0_Q0 d3, d5, d7, d9, d17, q12, q13
vmax.s8 q8, q8, q15
vmin.s8 q8, q8, q14
vand.s8 q8, q8, q10
EXTRACT_DELTA_INTO_TWO_PART q8, q9
vqadd.u8 q2, q2, q9
vqsub.u8 q2, q2, q8
vqsub.u8 q3, q3, q9
vqadd.u8 q3, q3, q8
sub r0, #2
add r2, r0, r1
lsl r1, #1
vmov q1, q6
vmov q4, q7
vswp q2, q3
vswp d3, d6
vswp d5, d8
STORE_LUMA_DATA_4 d2, d3, d4, d5, 0, 1
STORE_LUMA_DATA_4 d2, d3, d4, d5, 2, 3
STORE_LUMA_DATA_4 d2, d3, d4, d5, 4, 5
STORE_LUMA_DATA_4 d2, d3, d4, d5, 6, 7
STORE_LUMA_DATA_4 d6, d7, d8, d9, 0, 1
STORE_LUMA_DATA_4 d6, d7, d8, d9, 2, 3
STORE_LUMA_DATA_4 d6, d7, d8, d9, 4, 5
STORE_LUMA_DATA_4 d6, d7, d8, d9, 6, 7
vpop {q4-q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockLumaEq4H_neon
vpush {q4-q7}
vdup.u8 q5, r2
vdup.u8 q4, r3
sub r3, r0, #4 // pix -= 4
vld1.u8 {d16}, [r3], r1
vld1.u8 {d17}, [r3], r1
vld1.u8 {d18}, [r3], r1
vld1.u8 {d19}, [r3], r1
vld1.u8 {d20}, [r3], r1
vld1.u8 {d21}, [r3], r1
vld1.u8 {d22}, [r3], r1
vld1.u8 {d23}, [r3], r1
vld1.u8 {d24}, [r3], r1
vld1.u8 {d25}, [r3], r1
vld1.u8 {d26}, [r3], r1
vld1.u8 {d27}, [r3], r1
vld1.u8 {d28}, [r3], r1
vld1.u8 {d29}, [r3], r1
vld1.u8 {d30}, [r3], r1
vld1.u8 {d31}, [r3], r1
vtrn.u32 d16, d20
vtrn.u32 d17, d21
vtrn.u32 d18, d22
vtrn.u32 d19, d23
vtrn.u32 d24, d28
vtrn.u32 d25, d29
vtrn.u32 d26, d30
vtrn.u32 d27, d31
vtrn.u16 d16, d18
vtrn.u16 d17, d19
vtrn.u16 d20, d22
vtrn.u16 d21, d23
vtrn.u16 d24, d26
vtrn.u16 d25, d27
vtrn.u16 d28, d30
vtrn.u16 d29, d31
vtrn.u8 d16, d17
vtrn.u8 d18, d19
vtrn.u8 d20, d21
vtrn.u8 d22, d23
vtrn.u8 d24, d25
vtrn.u8 d26, d27
vtrn.u8 d28, d29
vtrn.u8 d30, d31
vswp d17, d24
vswp d19, d26
vswp d21, d28
vswp d23, d30
vswp q12, q9
vswp q14, q11
vswp q12, q10
vswp q13, q11
MASK_MATRIX q10, q11, q12, q13, q5, q4, q6
mov r2, r2, lsr #2
add r2, r2, #2
vdup.u8 q5, r2
vabd.u8 q0, q11, q12
vclt.u8 q7, q0, q5
vabd.u8 q1, q9, q11
vclt.u8 q1, q1, q4
vand.s8 q1, q1, q7
vabd.u8 q2, q14,q12
vclt.u8 q2, q2, q4
vand.s8 q2, q2, q7
vand.u8 q7, q7, q6
vmov q3, q1
DIFF_LUMA_EQ4_P2P1P0 d16, d18, d20, d22, d24, d26, d2, d0
DIFF_LUMA_EQ4_P2P1P0 d17, d19, d21, d23, d25, d27, d3, d1
vand.u8 q3, q7, q3
DIFF_LUMA_EQ4_MASK q0, q9, q3, q4
vmov q9, q4
vbsl.u8 q3, q8, q10
DIFF_LUMA_EQ4_MASK q1,q11, q6, q8
vand.u8 q7, q7, q2
DIFF_LUMA_EQ4_P2P1P0 d30, d28, d26, d24, d22, d20, d4, d0
DIFF_LUMA_EQ4_P2P1P0 d31, d29, d27, d25, d23, d21, d5, d1
vbsl.u8 q6, q2, q12
DIFF_LUMA_EQ4_MASK q15, q13, q7, q4
vbsl.u8 q7, q0, q14
vmov q5, q6
vmov q2, q9
vmov q6, q4
vmov q4, q8
vswp d8, d6
vswp d5, d7
vswp d5, d8
vswp d14, d12
vswp d11, d13
vswp d11, d14
sub r3, r0, #3
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,0
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,1
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,2
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,3
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,4
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,5
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,6
STORE_LUMA_DATA_3 d4,d5,d6,d10,d11,d12,7
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,0
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,1
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,2
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,3
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,4
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,5
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,6
STORE_LUMA_DATA_3 d7,d8,d9,d13,d14,d15,7
vpop {q4-q7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockChromaLt4V_neon
vdup.u8 q11, r3
ldr r3, [sp, #0]
sub r0, r0, r2 , lsl #1
sub r1, r1, r2, lsl #1
vdup.u8 q9, r3
ldr r3, [sp, #4]
vld1.u8 {d0}, [r0], r2
vld1.u8 {d1}, [r1], r2
vld1.u8 {d2}, [r0], r2
vld1.u8 {d3}, [r1], r2
vld1.u8 {d4}, [r0], r2
vld1.u8 {d5}, [r1], r2
vld1.u8 {d6}, [r0]
vld1.u8 {d7}, [r1]
sub r0, r0, r2, lsl #1
sub r1, r1, r2, lsl #1
vld1.s8 {d31}, [r3]
vmovl.u8 q14,d31
vshl.u64 d29,d28,#8
vorr d28,d29
vmov d29, d28
veor q15, q15
vsub.i8 q15,q15,q14
MASK_MATRIX q0, q1, q2, q3, q11, q9, q10
DIFF_LUMA_LT4_P0_Q0 d0, d2, d4, d6, d16, q12, q13
DIFF_LUMA_LT4_P0_Q0 d1, d3, d5, d7, d17, q12, q13
vmax.s8 q8, q8, q15
vmin.s8 q8, q8, q14
vand.s8 q8, q8, q10
vcge.s8 q14, q14, #0
vand.s8 q8, q8, q14
EXTRACT_DELTA_INTO_TWO_PART q8, q10
vqadd.u8 q1, q1, q10
vqsub.u8 q1, q1, q8
vst1.u8 {d2}, [r0], r2
vst1.u8 {d3}, [r1], r2
vqsub.u8 q2, q2, q10
vqadd.u8 q2, q2, q8
vst1.u8 {d4}, [r0]
vst1.u8 {d5}, [r1]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockChromaEq4V_neon
vpush {q4-q5}
vdup.u8 q11, r3
ldr r3, [sp, #32]
sub r0, r0, r2 , lsl #1
sub r1, r1, r2, lsl #1
vdup.u8 q9, r3
vld1.u8 {d0}, [r0], r2 // q0::p1
vld1.u8 {d1}, [r1], r2
vld1.u8 {d2}, [r0], r2 // q1::p0
vld1.u8 {d3}, [r1], r2
vld1.u8 {d4}, [r0], r2 // q2::q0
vld1.u8 {d5}, [r1], r2
vld1.u8 {d6}, [r0] // q3::q1
vld1.u8 {d7}, [r1]
sub r0, r0, r2, lsl #1 // pix = [-1*src_stride]
sub r1, r1, r2, lsl #1
MASK_MATRIX q0, q1, q2, q3, q11, q9, q10
vmov q11, q10
DIFF_CHROMA_EQ4_P0Q0 d0, d2, d4, d6, q4, q5, q8, d30, d0 // Cb::p0' q0'
DIFF_CHROMA_EQ4_P0Q0 d1, d3, d5, d7, q12, q13, q14, d31, d1 // Cr::p0' q0'
vbsl.u8 q10, q15, q1
vst1.u8 {d20}, [r0], r2
vst1.u8 {d21}, [r1], r2
vbsl.u8 q11, q0, q2
vst1.u8 {d22}, [r0]
vst1.u8 {d23}, [r1]
vpop {q4-q5}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockChromaLt4H_neon
vdup.u8 q11, r3
ldr r3, [sp, #0]
sub r0, r0, #2
vdup.u8 q9, r3
ldr r3, [sp, #4]
sub r1, r1, #2
vld1.s8 {d31}, [r3]
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 0
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 1
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 2
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 3
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 4
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 5
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 6
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 7
vswp q1, q2
vswp d1, d2
vswp d6, d5
vmovl.u8 q14, d31
vshl.u64 d29,d28,#8
vorr d28,d29
vmov d29, d28
veor q15, q15
vsub.i8 q15,q15,q14
MASK_MATRIX q0, q1, q2, q3, q11, q9, q10
DIFF_LUMA_LT4_P0_Q0 d0, d2, d4, d6, d16, q12, q13
DIFF_LUMA_LT4_P0_Q0 d1, d3, d5, d7, d17, q12, q13
vmax.s8 q8, q8, q15
vmin.s8 q8, q8, q14
vand.s8 q8, q8, q10
vcge.s8 q14, q14, #0
vand.s8 q8, q8, q14
EXTRACT_DELTA_INTO_TWO_PART q8, q10
vqadd.u8 q1, q1, q10
vqsub.u8 q1, q1, q8
vqsub.u8 q2, q2, q10
vqadd.u8 q2, q2, q8
sub r0, r0, r2, lsl #3
sub r1, r1, r2, lsl #3
vswp d1, d2
vswp d6, d5
vswp q1, q2
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 0
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 1
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 2
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 3
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 4
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 5
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 6
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 7
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DeblockChromaEq4H_neon
vpush {q4-q5}
vdup.u8 q11, r3
ldr r3, [sp, #32]
sub r0, r0, #2
sub r1, r1, #2
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 0
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 1
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 2
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 3
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 4
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 5
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 6
LOAD_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 7
vswp q1, q2
vswp d1, d2
vswp d6, d5
vdup.u8 q9, r3
MASK_MATRIX q0, q1, q2, q3, q11, q9, q10
vmov q11, q10
DIFF_CHROMA_EQ4_P0Q0 d0, d2, d4, d6, q8, q9, q12, d8, d10
DIFF_CHROMA_EQ4_P0Q0 d1, d3, d5, d7, q13, q14, q15, d9, d11
vbsl.u8 q10, q4, q1
vbsl.u8 q11, q5, q2
sub r0, r0, r2, lsl #3 // pix: 0th row [-2]
sub r1, r1, r2, lsl #3
vmov q1, q10
vmov q2, q11
vswp d1, d2
vswp d6, d5
vswp q1, q2
// Cb:d0d1d2d3, Cr:d4d5d6d7
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 0
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 1
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 2
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 3
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 4
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 5
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 6
STORE_CHROMA_DATA_4 d0, d1, d2, d3, d4, d5, d6, d7, 7
vpop {q4-q5}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsNonZeroCount_neon
mov r1, #1
vdup.8 q2, r1
vld1.64 {d0,d1,d2}, [r0]
vmin.s8 q0, q0, q2
vmin.s8 d2, d2, d4
vst1.64 {d0,d1,d2}, [r0]
WELS_ASM_FUNC_END
.macro BS_NZC_CHECK arg0, arg1, arg2, arg3, arg4
vld1.8 {d0,d1}, [\arg0]
/* Arrenge the input data --- TOP */
ands r6, \arg1, #2
beq bs_nzc_check_jump0
sub r6, \arg0, \arg2, lsl #4
sub r6, r6, \arg2, lsl #3
add r6, #12
vld1.32 d3[1], [r6]
bs_nzc_check_jump0:
vext.8 q1, q1, q0, #12
vadd.u8 \arg3, q0, q1
/* Arrenge the input data --- LEFT */
ands r6, \arg1, #1
beq bs_nzc_check_jump1
sub r6, \arg0, #21
add r7, r6, #4
vld1.8 d3[4], [r6]
add r6, r7, #4
vld1.8 d3[5], [r7]
add r7, r6, #4
vld1.8 d3[6], [r6]
vld1.8 d3[7], [r7]
bs_nzc_check_jump1:
vzip.8 d0, d1
vzip.8 d0, d1
vext.8 q1, q1, q0, #12
vadd.u8 \arg4, q0, q1
.endm
.macro BS_COMPARE_MV arg0, arg1, arg2, arg3, arg4, arg5, arg6 //in: $0,$1(const),$2(const),$3(const),$4(const); out:$5, $6
mov r6, #4
vabd.s16 q8, \arg0, \arg1
vabd.s16 q9, \arg1, \arg2
vdup.s16 \arg0, r6
vabd.s16 q10, \arg2, \arg3
vabd.s16 q11, \arg3, \arg4
vcge.s16 q8, \arg0
vcge.s16 q9, \arg0
vcge.s16 q10, \arg0
vcge.s16 q11, \arg0
vpadd.i16 d16, d16, d17
vpadd.i16 d17, d18, d19
vpadd.i16 d18, d20, d21
vpadd.i16 d19, d22, d23
vaddhn.i16 \arg5, q8, q8
vaddhn.i16 \arg6, q9, q9
.endm
.macro BS_MV_CHECK arg0, arg1, arg2, arg3, arg4, arg5, arg6
vldm \arg0, {q0,q1,q2,q3}
/* Arrenge the input data --- TOP */
ands r6, \arg1, #2
beq bs_mv_check_jump0
sub r6, \arg0, \arg2, lsl #6
add r6, #48
vld1.8 {d8, d9}, [r6]
bs_mv_check_jump0:
BS_COMPARE_MV q4, q0, q1, q2, q3, \arg3, \arg4
/* Arrenge the input data --- LEFT */
ands r6, \arg1, #1
beq bs_mv_check_jump1
sub r6, \arg0, #52
add r7, r6, #16
vld1.32 d8[0], [r6]
add r6, r7, #16
vld1.32 d8[1], [r7]
add r7, r6, #16
vld1.32 d9[0], [r6]
vld1.32 d9[1], [r7]
bs_mv_check_jump1:
vzip.32 q0, q2
vzip.32 q1, q3
vzip.32 q0, q1
vzip.32 q2, q3
BS_COMPARE_MV q4, q0, q1, q2, q3, \arg5, \arg6
.endm
WELS_ASM_FUNC_BEGIN DeblockingBSCalcEnc_neon
stmdb sp!, {r5-r7}
vpush {q4}
ldr r5, [sp, #28] //Save BS to r5
/* Checking the nzc status */
BS_NZC_CHECK r0, r2, r3, q14, q15 //q14,q15 save the nzc status
/* For checking bS[I] = 2 */
mov r6, #2
vcgt.s8 q14, q14, #0
vdup.u8 q0, r6
vcgt.s8 q15, q15, #0
vand.u8 q14, q14, q0 //q14 save the nzc check result all the time --- for dir is top
vand.u8 q15, q15, q0 //q15 save the nzc check result all the time --- for dir is left
/* Checking the mv status*/
BS_MV_CHECK r1, r2, r3, d24, d25, d26, d27//q12, q13 save the mv status
/* For checking bS[I] = 1 */
mov r6, #1
vdup.u8 q0, r6
vand.u8 q12, q12, q0 //q12 save the nzc check result all the time --- for dir is top
vand.u8 q13, q13, q0 //q13 save the nzc check result all the time --- for dir is left
/* Check bS[I] is '1' or '2' */
vmax.u8 q1, q12, q14
vmax.u8 q0, q13, q15
//vstm r5, {q0, q1}
vst1.32 {q0, q1}, [r5]
vpop {q4}
ldmia sp!, {r5-r7}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 5,029 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm/copy_mb_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro LOAD_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: \arg0~\arg3, src*, src_stride
vld1.64 {\arg0}, [\arg4,:128], \arg5
vld1.64 {\arg1}, [\arg4,:128], \arg5
vld1.64 {\arg2}, [\arg4,:128], \arg5
vld1.64 {\arg3}, [\arg4,:128], \arg5
// }
.endm
.macro STORE_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: \arg0~\arg3, dst*, dst_stride
vst1.64 {\arg0}, [\arg4,:128], \arg5
vst1.64 {\arg1}, [\arg4,:128], \arg5
vst1.64 {\arg2}, [\arg4,:128], \arg5
vst1.64 {\arg3}, [\arg4,:128], \arg5
// }
.endm
.macro LOAD_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: \arg0~\arg3, src*, src_stride
vld1.64 {\arg0}, [\arg4], \arg5
vld1.64 {\arg1}, [\arg4], \arg5
vld1.64 {\arg2}, [\arg4], \arg5
vld1.64 {\arg3}, [\arg4], \arg5
// }
.endm
.macro STORE_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: \arg0~\arg3, dst*, dst_stride
vst1.64 {\arg0}, [\arg4], \arg5
vst1.64 {\arg1}, [\arg4], \arg5
vst1.64 {\arg2}, [\arg4], \arg5
vst1.64 {\arg3}, [\arg4], \arg5
// }
.endm
WELS_ASM_FUNC_BEGIN WelsCopy8x8_neon
LOAD_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r0, r1
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsCopy16x16_neon
LOAD_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
STORE_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
LOAD_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
STORE_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
LOAD_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
STORE_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
LOAD_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
STORE_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsCopy16x16NotAligned_neon
LOAD_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsCopy16x8NotAligned_neon
LOAD_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsCopy8x16_neon
LOAD_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r0, r1
LOAD_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r2, r3
STORE_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r0, r1
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 3,864 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm/expand_picture_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
WELS_ASM_FUNC_BEGIN ExpandPictureLuma_neon
stmdb sp!, {r4-r8}
//Save the dst
mov r7, r0
mov r8, r3
add r4, r7, r2
sub r4, #1
//For the left and right expand
_expand_picture_luma_loop2:
sub r5, r7, #32
add r6, r4, #1
vld1.8 {d0[], d1[]}, [r7], r1
vld1.8 {d2[], d3[]}, [r4], r1
vst1.8 {q0}, [r5]!
vst1.8 {q0}, [r5]
vst1.8 {q1}, [r6]!
vst1.8 {q1}, [r6]
subs r8, #1
bne _expand_picture_luma_loop2
//for the top and bottom expand
add r2, #64
sub r0, #32
mla r4, r1, r3, r0
sub r4, r1
_expand_picture_luma_loop0:
mov r5, #32
mls r5, r5, r1, r0
add r6, r4, r1
vld1.8 {q0}, [r0]!
vld1.8 {q1}, [r4]!
mov r8, #32
_expand_picture_luma_loop1:
vst1.8 {q0}, [r5], r1
vst1.8 {q1}, [r6], r1
subs r8, #1
bne _expand_picture_luma_loop1
subs r2, #16
bne _expand_picture_luma_loop0
//vldreq.32 d0, [r0]
ldmia sp!, {r4-r8}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN ExpandPictureChroma_neon
stmdb sp!, {r4-r9}
//Save the dst
mov r7, r0
mov r8, r3
add r4, r7, r2
sub r4, #1
//For the left and right expand
_expand_picture_chroma_loop2:
sub r5, r7, #16
add r6, r4, #1
vld1.8 {d0[], d1[]}, [r7], r1
vld1.8 {d2[], d3[]}, [r4], r1
vst1.8 {q0}, [r5]
vst1.8 {q1}, [r6]
subs r8, #1
bne _expand_picture_chroma_loop2
//for the top and bottom expand
add r2, #32
mov r9, r2
bic r2, #15
sub r0, #16
mla r4, r1, r3, r0
sub r4, r1
_expand_picture_chroma_loop0:
mov r5, #16
mls r5, r5, r1, r0
add r6, r4, r1
vld1.8 {q0}, [r0]!
vld1.8 {q1}, [r4]!
mov r8, #16
_expand_picture_chroma_loop1:
vst1.8 {q0}, [r5], r1
vst1.8 {q1}, [r6], r1
subs r8, #1
bne _expand_picture_chroma_loop1
subs r2, #16
bne _expand_picture_chroma_loop0
//vldreq.32 d0, [r0]
and r9, #15
cmp r9, #8
bne _expand_picture_chroma_end
mov r5, #16
mls r5, r5, r1, r0
add r6, r4, r1
vld1.8 {d0}, [r0]!
vld1.8 {d2}, [r4]!
mov r8, #16
_expand_picture_chroma_loop3:
vst1.8 {d0}, [r5], r1
vst1.8 {d2}, [r6], r1
subs r8, #1
bne _expand_picture_chroma_loop3
_expand_picture_chroma_end:
ldmia sp!, {r4-r9}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 75,114 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm/mc_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro AVERAGE_TWO_8BITS arg0, arg1, arg2
// { // input:dst_d, src_d A and B; working: q13
vaddl.u8 q13, \arg2, \arg1
vrshrn.u16 \arg0, q13, #1
// }
.endm
.macro FILTER_6TAG_8BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: q12, q13
vaddl.u8 q12, \arg0, \arg5 //q12=src[-2]+src[3]
vaddl.u8 q13, \arg2, \arg3 //src[0]+src[1]
vmla.u16 q12, q13, \arg7 //q12 += 20*(src[0]+src[1]), 2 cycles
vaddl.u8 q13, \arg1, \arg4 //src[-1]+src[2]
vmls.s16 q12, q13, \arg8 //q12 -= 5*(src[-1]+src[2]), 2 cycles
vqrshrun.s16 \arg6, q12, #5
// }
.endm
.macro FILTER_SINGLE_TAG_8BITS arg0, arg1,arg2, arg3, arg4 // when width=17/9, used
// { // input: src_d{Y[0][1][2][3][4][5]X, the even of working_q2}
vrev64.8 \arg2, \arg0 // X[5][4][3][2][1][0]O
vaddl.u8 \arg3, \arg0, \arg2 // each 16bits, *[50][41][32][23][14][05]*
vmul.s16 \arg0, \arg2, \arg1 // 0+1*[50]-5*[41]+20[32]
vpadd.s16 \arg0, \arg0, \arg0
vpadd.s16 \arg0, \arg0, \arg0
vqrshrun.s16 \arg0, \arg4, #5
// }
.endm
.macro FILTER_6TAG_8BITS_AVERAGE_WITH_0 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: q12, q13
vaddl.u8 q12, \arg0, \arg5 //q12=src[-2]+src[3]
vaddl.u8 q13, \arg2, \arg3 //src[0]+src[1]
vmla.u16 q12, q13, \arg7 //q12 += 20*(src[0]+src[1]), 2 cycles
vaddl.u8 q13, \arg1, \arg4 //src[-1]+src[2]
vmls.s16 q12, q13, \arg8 //q12 -= 5*(src[-1]+src[2]), 2 cycles
vqrshrun.s16 \arg6, q12, #5
vaddl.u8 q13, \arg2, \arg6
vrshrn.u16 \arg6, q13, #1
// }
.endm
.macro FILTER_6TAG_8BITS_AVERAGE_WITH_1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: q12, q13
vaddl.u8 q12, \arg0, \arg5 //q12=src[-2]+src[3]
vaddl.u8 q13, \arg2, \arg3 //src[0]+src[1]
vmla.u16 q12, q13, \arg7 //q12 += 20*(src[0]+src[1]), 2 cycles
vaddl.u8 q13, \arg1, \arg4 //src[-1]+src[2]
vmls.s16 q12, q13, \arg8 //q12 -= 5*(src[-1]+src[2]), 2 cycles
vqrshrun.s16 \arg6, q12, #5
vaddl.u8 q13, \arg3, \arg6
vrshrn.u16 \arg6, q13, #1
// }
.endm
.macro FILTER_6TAG_8BITS_TO_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:d_src[-2], d_src[-1], d_src[0], d_src[1], d_src[2], d_src[3], dst_q, multiplier a/b; working:q13
vaddl.u8 \arg6, \arg0, \arg5 //dst_q=src[-2]+src[3]
vaddl.u8 q13, \arg2, \arg3 //src[0]+src[1]
vmla.u16 \arg6, q13, \arg7 //dst_q += 20*(src[0]+src[1]), 2 cycles
vaddl.u8 q13, \arg1, \arg4 //src[-1]+src[2]
vmls.s16 \arg6, q13, \arg8 //dst_q -= 5*(src[-1]+src[2]), 2 cycles
// }
.endm
.macro FILTER_3_IN_16BITS_TO_8BITS arg0, arg1, arg2, arg3
// { // input:a, b, c, dst_d;
vsub.s16 \arg0, \arg0, \arg1 //a-b
vshr.s16 \arg0, \arg0, #2 //(a-b)/4
vsub.s16 \arg0, \arg0, \arg1 //(a-b)/4-b
vadd.s16 \arg0, \arg0, \arg2 //(a-b)/4-b+c
vshr.s16 \arg0, \arg0, #2 //((a-b)/4-b+c)/4
vadd.s16 \arg0, \arg0, \arg2 //((a-b)/4-b+c)/4+c = (a-5*b+20*c)/16
vqrshrun.s16 \arg3, \arg0, #6 //(+32)>>6
// }
.endm
.macro UNPACK_2_16BITS_TO_ABC arg0, arg1, arg2, arg3, arg4
// { // input:q_src[-2:5], q_src[6:13](avail 8+5)/q_src[6:**](avail 4+5), dst_a, dst_b, dst_c;
vext.16 \arg4, \arg0, \arg1, #2 //src[0]
vext.16 \arg3, \arg0, \arg1, #3 //src[1]
vadd.s16 \arg4, \arg3 //c=src[0]+src[1]
vext.16 \arg3, \arg0, \arg1, #1 //src[-1]
vext.16 \arg2, \arg0, \arg1, #4 //src[2]
vadd.s16 \arg3,\arg2 //b=src[-1]+src[2]
vext.16 \arg2, \arg0, \arg1, #5 //src[3]
vadd.s16 \arg2, \arg0 //a=src[-2]+src[3]
// }
.endm
.macro UNPACK_1_IN_8x16BITS_TO_8BITS arg0, arg1,arg2, arg3
// { // each 16bits; input: d_dst, d_src[0:3] (even), d_src[4:5]+%% (odd)
vext.16 \arg3, \arg3, \arg3, #7 // 0x????, [0][1][2][3][4][5]
vrev64.16 \arg1, \arg1
vadd.u16 \arg2, \arg1 // C[2+3],B[1+4],A[0+5]
vshr.s64 \arg1, \arg2, #16
vshr.s64 \arg0, \arg2, #32 // Output: C \arg2, B \arg1, A \arg0
vsub.s16 \arg0, \arg0, \arg1 //a-b
vshr.s16 \arg0, \arg0, #2 //(a-b)/4
vsub.s16 \arg0, \arg0, \arg1 //(a-b)/4-b
vadd.s16 \arg0, \arg0, \arg2 //(a-b)/4-b+c
vshr.s16 \arg0, \arg0, #2 //((a-b)/4-b+c)/4
vadd.s16 \arg1, \arg0, \arg2 //((a-b)/4-b+c)/4+c = (a-5*b+20*c)/16
vqrshrun.s16 \arg0, \arg3, #6 //(+32)>>6
// }
.endm
WELS_ASM_FUNC_BEGIN McHorVer20WidthEq16_neon
push {r4}
ldr r4, [sp, #4]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w16_h_mc_luma_loop:
vld1.u8 {d0,d1,d2}, [r0], r1 //only use 21(16+5); q0=src[-2]
pld [r0]
pld [r0, #16]
vext.8 q2, q0, q1, #1 //q2=src[-1]
vext.8 q3, q0, q1, #2 //q3=src[0]
vext.8 q8, q0, q1, #3 //q8=src[1]
vext.8 q9, q0, q1, #4 //q9=src[2]
vext.8 q10, q0, q1, #5 //q10=src[3]
FILTER_6TAG_8BITS d0, d4, d6, d16, d18, d20, d2, q14, q15
FILTER_6TAG_8BITS d1, d5, d7, d17, d19, d21, d3, q14, q15
sub r4, #1
vst1.u8 {d2, d3}, [r2], r3 //write 16Byte
cmp r4, #0
bne w16_h_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer20WidthEq8_neon
push {r4}
ldr r4, [sp, #4]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w8_h_mc_luma_loop:
vld1.u8 {d0,d1}, [r0], r1 //only use 13(8+5); q0=src[-2]
pld [r0]
vext.8 d2, d0, d1, #1 //d2=src[-1]
vext.8 d3, d0, d1, #2 //d3=src[0]
vext.8 d4, d0, d1, #3 //d4=src[1]
vext.8 d5, d0, d1, #4 //d5=src[2]
vext.8 d6, d0, d1, #5 //d6=src[3]
FILTER_6TAG_8BITS d0, d2, d3, d4, d5, d6, d1, q14, q15
sub r4, #1
vst1.u8 {d1}, [r2], r3
cmp r4, #0
bne w8_h_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer20WidthEq4_neon
push {r4, r5, r6}
ldr r6, [sp, #12]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w4_h_mc_luma_loop:
vld1.u8 {d0, d1}, [r0], r1 //only use 9(4+5);d0: 1st row src[-2:5]
pld [r0]
vld1.u8 {d2, d3}, [r0], r1 //d2: 2nd row src[-2:5]
pld [r0]
vext.8 d4, d0, d1, #1 //d4: 1st row src[-1:6]
vext.8 d5, d2, d3, #1 //d5: 2nd row src[-1:6]
vext.8 q3, q2, q2, #1 //src[0:6 *]
vext.8 q8, q2, q2, #2 //src[1:6 * *]
vtrn.32 q3, q8 //q3::d6:1st row [0:3]+[1:4]; d7:2nd row [0:3]+[1:4]
vtrn.32 d6, d7 //d6:[0:3]; d7[1:4]
vtrn.32 d0, d2 //d0:[-2:1]; d2[2:5]
vtrn.32 d4, d5 //d4:[-1:2]; d5[3:6]
FILTER_6TAG_8BITS d0, d4, d6, d7, d2, d5, d1, q14, q15
vmov r4, r5, d1
str r4, [r2], r3
str r5, [r2], r3
sub r6, #2
cmp r6, #0
bne w4_h_mc_luma_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer10WidthEq16_neon
push {r4}
ldr r4, [sp, #4]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w16_xy_10_mc_luma_loop:
vld1.u8 {d0,d1,d2}, [r0], r1 //only use 21(16+5); q0=src[-2]
pld [r0]
pld [r0, #16]
vext.8 q2, q0, q1, #1 //q2=src[-1]
vext.8 q3, q0, q1, #2 //q3=src[0]
vext.8 q8, q0, q1, #3 //q8=src[1]
vext.8 q9, q0, q1, #4 //q9=src[2]
vext.8 q10, q0, q1, #5 //q10=src[3]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d4, d6, d16, d18, d20, d2, q14, q15
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d1, d5, d7, d17, d19, d21, d3, q14, q15
sub r4, #1
vst1.u8 {d2, d3}, [r2], r3 //write 16Byte
cmp r4, #0
bne w16_xy_10_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer10WidthEq8_neon
push {r4}
ldr r4, [sp, #4]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w8_xy_10_mc_luma_loop:
vld1.u8 {d0,d1}, [r0], r1 //only use 13(8+5); q0=src[-2]
pld [r0]
vext.8 d2, d0, d1, #1 //d2=src[-1]
vext.8 d3, d0, d1, #2 //d3=src[0]
vext.8 d4, d0, d1, #3 //d4=src[1]
vext.8 d5, d0, d1, #4 //d5=src[2]
vext.8 d6, d0, d1, #5 //d6=src[3]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d2, d3, d4, d5, d6, d1, q14, q15
sub r4, #1
vst1.u8 {d1}, [r2], r3
cmp r4, #0
bne w8_xy_10_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer10WidthEq4_neon
push {r4, r5, r6}
ldr r6, [sp, #12]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w4_xy_10_mc_luma_loop:
vld1.u8 {d0, d1}, [r0], r1 //only use 9(4+5);d0: 1st row src[-2:5]
pld [r0]
vld1.u8 {d2, d3}, [r0], r1 //d2: 2nd row src[-2:5]
pld [r0]
vext.8 d4, d0, d1, #1 //d4: 1st row src[-1:6]
vext.8 d5, d2, d3, #1 //d5: 2nd row src[-1:6]
vext.8 q3, q2, q2, #1 //src[0:6 *]
vext.8 q8, q2, q2, #2 //src[1:6 * *]
vtrn.32 q3, q8 //q3::d6:1st row [0:3]+[1:4]; d7:2nd row [0:3]+[1:4]
vtrn.32 d6, d7 //d6:[0:3]; d7[1:4]
vtrn.32 d0, d2 //d0:[-2:1]; d2[2:5]
vtrn.32 d4, d5 //d4:[-1:2]; d5[3:6]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d4, d6, d7, d2, d5, d1, q14, q15
vmov r4, r5, d1
str r4, [r2], r3
str r5, [r2], r3
sub r6, #2
cmp r6, #0
bne w4_xy_10_mc_luma_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer30WidthEq16_neon
push {r4}
ldr r4, [sp, #4]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w16_xy_30_mc_luma_loop:
vld1.u8 {d0,d1,d2}, [r0], r1 //only use 21(16+5); q0=src[-2]
pld [r0]
pld [r0, #16]
vext.8 q2, q0, q1, #1 //q2=src[-1]
vext.8 q3, q0, q1, #2 //q3=src[0]
vext.8 q8, q0, q1, #3 //q8=src[1]
vext.8 q9, q0, q1, #4 //q9=src[2]
vext.8 q10, q0, q1, #5 //q10=src[3]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d4, d6, d16, d18, d20, d2, q14, q15
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d1, d5, d7, d17, d19, d21, d3, q14, q15
sub r4, #1
vst1.u8 {d2, d3}, [r2], r3 //write 16Byte
cmp r4, #0
bne w16_xy_30_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer30WidthEq8_neon
push {r4}
ldr r4, [sp, #4]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w8_xy_30_mc_luma_loop:
vld1.u8 {d0,d1}, [r0], r1 //only use 13(8+5); q0=src[-2]
pld [r0]
vext.8 d2, d0, d1, #1 //d2=src[-1]
vext.8 d3, d0, d1, #2 //d3=src[0]
vext.8 d4, d0, d1, #3 //d4=src[1]
vext.8 d5, d0, d1, #4 //d5=src[2]
vext.8 d6, d0, d1, #5 //d6=src[3]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d2, d3, d4, d5, d6, d1, q14, q15
sub r4, #1
vst1.u8 {d1}, [r2], r3
cmp r4, #0
bne w8_xy_30_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer30WidthEq4_neon
push {r4, r5, r6}
ldr r6, [sp, #12]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w4_xy_30_mc_luma_loop:
vld1.u8 {d0, d1}, [r0], r1 //only use 9(4+5);d0: 1st row src[-2:5]
pld [r0]
vld1.u8 {d2, d3}, [r0], r1 //d2: 2nd row src[-2:5]
pld [r0]
vext.8 d4, d0, d1, #1 //d4: 1st row src[-1:6]
vext.8 d5, d2, d3, #1 //d5: 2nd row src[-1:6]
vext.8 q3, q2, q2, #1 //src[0:6 *]
vext.8 q8, q2, q2, #2 //src[1:6 * *]
vtrn.32 q3, q8 //q3::d6:1st row [0:3]+[1:4]; d7:2nd row [0:3]+[1:4]
vtrn.32 d6, d7 //d6:[0:3]; d7[1:4]
vtrn.32 d0, d2 //d0:[-2:1]; d2[2:5]
vtrn.32 d4, d5 //d4:[-1:2]; d5[3:6]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d4, d6, d7, d2, d5, d1, q14, q15
vmov r4, r5, d1
str r4, [r2], r3
str r5, [r2], r3
sub r6, #2
cmp r6, #0
bne w4_xy_30_mc_luma_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer01WidthEq16_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //q0=src[-2]
vld1.u8 {q1}, [r0], r1 //q1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //q2=src[0]
vld1.u8 {q3}, [r0], r1 //q3=src[1]
vld1.u8 {q8}, [r0], r1 //q8=src[2]
w16_xy_01_luma_loop:
vld1.u8 {q9}, [r0], r1 //q9=src[3]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 2nd row
vst1.u8 {q10}, [r2], r3 //write 1st 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d3, d5, d7, d17, d19, d1, d21, q14, q15
vld1.u8 {q1}, [r0], r1 //read 3rd row
vst1.u8 {q10}, [r2], r3 //write 2nd 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d4, d6, d16, d18, d0, d2, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d5, d7, d17, d19, d1, d3, d21, q14, q15
vld1.u8 {q2}, [r0], r1 //read 4th row
vst1.u8 {q10}, [r2], r3 //write 3rd 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d6, d16, d18, d0, d2, d4, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d7, d17, d19, d1, d3, d5, d21, q14, q15
vld1.u8 {q3}, [r0], r1 //read 5th row
vst1.u8 {q10}, [r2], r3 //write 4th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d16, d18, d0, d2, d4, d6, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d17, d19, d1, d3, d5, d7, d21, q14, q15
vld1.u8 {q8}, [r0], r1 //read 6th row
vst1.u8 {q10}, [r2], r3 //write 5th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d18, d0, d2, d4, d6, d16, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d19, d1, d3, d5, d7, d17, d21, q14, q15
vld1.u8 {q9}, [r0], r1 //read 7th row
vst1.u8 {q10}, [r2], r3 //write 6th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 8th row
vst1.u8 {q10}, [r2], r3 //write 7th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d3, d5, d7, d17, d19, d1, d21, q14, q15
vst1.u8 {q10}, [r2], r3 //write 8th 16Byte
//q2, q3, q4, q5, q0 --> q0~q4
vswp q0, q8
vswp q0, q2
vmov q1, q3
vmov q3, q9 //q0~q4
sub r4, #8
cmp r4, #0
bne w16_xy_01_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer01WidthEq8_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0}, [r0], r1 //d0=src[-2]
vld1.u8 {d1}, [r0], r1 //d1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d2}, [r0], r1 //d2=src[0]
vld1.u8 {d3}, [r0], r1 //d3=src[1]
vld1.u8 {d4}, [r0], r1 //d4=src[2]
vld1.u8 {d5}, [r0], r1 //d5=src[3]
w8_xy_01_mc_luma_loop:
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d1, d2, d3, d4, d5, d16, q14, q15
vld1.u8 {d0}, [r0], r1 //read 2nd row
vst1.u8 {d16}, [r2], r3 //write 1st 8Byte
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d1, d2, d3, d4, d5, d0, d16, q14, q15
vld1.u8 {d1}, [r0], r1 //read 3rd row
vst1.u8 {d16}, [r2], r3 //write 2nd 8Byte
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d2, d3, d4, d5, d0, d1, d16, q14, q15
vld1.u8 {d2}, [r0], r1 //read 4th row
vst1.u8 {d16}, [r2], r3 //write 3rd 8Byte
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d3, d4, d5, d0, d1, d2, d16, q14, q15
vld1.u8 {d3}, [r0], r1 //read 5th row
vst1.u8 {d16}, [r2], r3 //write 4th 8Byte
//d4, d5, d0, d1, d2, d3 --> d0, d1, d2, d3, d4, d5
vswp q0, q2
vswp q1, q2
sub r4, #4
cmp r4, #0
bne w8_xy_01_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer01WidthEq4_neon
push {r4, r5, r6, r7}
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
ldr r4, [r0], r1 //r4=src[-2]
ldr r5, [r0], r1 //r5=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
ldr r6, [r0], r1 //r6=src[0]
ldr r7, [r0], r1 //r7=src[1]
vmov d0, r4, r5
vmov d1, r5, r6
vmov d2, r6, r7
ldr r4, [r0], r1 //r4=src[2]
vmov d3, r7, r4
ldr r7, [sp, #16]
w4_xy_01_mc_luma_loop:
// pld [r0]
//using reserving r4
ldr r5, [r0], r1 //r5=src[3]
ldr r6, [r0], r1 //r6=src[0]
vmov d4, r4, r5
vmov d5, r5, r6 //reserved r6
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d0, d1, d2, d3, d4, d5, d16, q14, q15
vmov r4, r5, d16
str r4, [r2], r3 //write 1st 4Byte
str r5, [r2], r3 //write 2nd 4Byte
ldr r5, [r0], r1 //r5=src[1]
ldr r4, [r0], r1 //r4=src[2]
vmov d0, r6, r5
vmov d1, r5, r4 //reserved r4
FILTER_6TAG_8BITS_AVERAGE_WITH_0 d2, d3, d4, d5, d0, d1, d16, q14, q15
vmov r5, r6, d16
str r5, [r2], r3 //write 3rd 4Byte
str r6, [r2], r3 //write 4th 4Byte
//d4, d5, d0, d1 --> d0, d1, d2, d3
vmov q1, q0
vmov q0, q2
sub r7, #4
cmp r7, #0
bne w4_xy_01_mc_luma_loop
pop {r4, r5, r6, r7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer03WidthEq16_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //q0=src[-2]
vld1.u8 {q1}, [r0], r1 //q1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //q2=src[0]
vld1.u8 {q3}, [r0], r1 //q3=src[1]
vld1.u8 {q8}, [r0], r1 //q8=src[2]
w16_xy_03_luma_loop:
vld1.u8 {q9}, [r0], r1 //q9=src[3]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 2nd row
vst1.u8 {q10}, [r2], r3 //write 1st 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d3, d5, d7, d17, d19, d1, d21, q14, q15
vld1.u8 {q1}, [r0], r1 //read 3rd row
vst1.u8 {q10}, [r2], r3 //write 2nd 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d4, d6, d16, d18, d0, d2, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d5, d7, d17, d19, d1, d3, d21, q14, q15
vld1.u8 {q2}, [r0], r1 //read 4th row
vst1.u8 {q10}, [r2], r3 //write 3rd 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d6, d16, d18, d0, d2, d4, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d7, d17, d19, d1, d3, d5, d21, q14, q15
vld1.u8 {q3}, [r0], r1 //read 5th row
vst1.u8 {q10}, [r2], r3 //write 4th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d16, d18, d0, d2, d4, d6, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d17, d19, d1, d3, d5, d7, d21, q14, q15
vld1.u8 {q8}, [r0], r1 //read 6th row
vst1.u8 {q10}, [r2], r3 //write 5th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d18, d0, d2, d4, d6, d16, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d19, d1, d3, d5, d7, d17, d21, q14, q15
vld1.u8 {q9}, [r0], r1 //read 7th row
vst1.u8 {q10}, [r2], r3 //write 6th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 8th row
vst1.u8 {q10}, [r2], r3 //write 7th 16Byte
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d3, d5, d7, d17, d19, d1, d21, q14, q15
vst1.u8 {q10}, [r2], r3 //write 8th 16Byte
//q2, q3, q8, q9, q0 --> q0~q8
vswp q0, q8
vswp q0, q2
vmov q1, q3
vmov q3, q9 //q0~q8
sub r4, #8
cmp r4, #0
bne w16_xy_03_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer03WidthEq8_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0}, [r0], r1 //d0=src[-2]
vld1.u8 {d1}, [r0], r1 //d1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d2}, [r0], r1 //d2=src[0]
vld1.u8 {d3}, [r0], r1 //d3=src[1]
vld1.u8 {d4}, [r0], r1 //d4=src[2]
vld1.u8 {d5}, [r0], r1 //d5=src[3]
w8_xy_03_mc_luma_loop:
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d1, d2, d3, d4, d5, d16, q14, q15
vld1.u8 {d0}, [r0], r1 //read 2nd row
vst1.u8 {d16}, [r2], r3 //write 1st 8Byte
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d1, d2, d3, d4, d5, d0, d16, q14, q15
vld1.u8 {d1}, [r0], r1 //read 3rd row
vst1.u8 {d16}, [r2], r3 //write 2nd 8Byte
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d2, d3, d4, d5, d0, d1, d16, q14, q15
vld1.u8 {d2}, [r0], r1 //read 4th row
vst1.u8 {d16}, [r2], r3 //write 3rd 8Byte
pld [r0]
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d3, d4, d5, d0, d1, d2, d16, q14, q15
vld1.u8 {d3}, [r0], r1 //read 5th row
vst1.u8 {d16}, [r2], r3 //write 4th 8Byte
//d4, d5, d0, d1, d2, d3 --> d0, d1, d2, d3, d4, d5
vswp q0, q2
vswp q1, q2
sub r4, #4
cmp r4, #0
bne w8_xy_03_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer03WidthEq4_neon
push {r4, r5, r6, r7}
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
ldr r4, [r0], r1 //r4=src[-2]
ldr r5, [r0], r1 //r5=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
ldr r6, [r0], r1 //r6=src[0]
ldr r7, [r0], r1 //r7=src[1]
vmov d0, r4, r5
vmov d1, r5, r6
vmov d2, r6, r7
ldr r4, [r0], r1 //r4=src[2]
vmov d3, r7, r4
ldr r7, [sp, #16]
w4_xy_03_mc_luma_loop:
// pld [r0]
//using reserving r4
ldr r5, [r0], r1 //r5=src[3]
ldr r6, [r0], r1 //r6=src[0]
vmov d4, r4, r5
vmov d5, r5, r6 //reserved r6
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d0, d1, d2, d3, d4, d5, d16, q14, q15
vmov r4, r5, d16
str r4, [r2], r3 //write 1st 4Byte
str r5, [r2], r3 //write 2nd 4Byte
ldr r5, [r0], r1 //r5=src[1]
ldr r4, [r0], r1 //r4=src[2]
vmov d0, r6, r5
vmov d1, r5, r4 //reserved r4
FILTER_6TAG_8BITS_AVERAGE_WITH_1 d2, d3, d4, d5, d0, d1, d16, q14, q15
vmov r5, r6, d16
str r5, [r2], r3 //write 3rd 4Byte
str r6, [r2], r3 //write 4th 4Byte
//d4, d5, d0, d1 --> d0, d1, d2, d3
vmov q1, q0
vmov q0, q2
sub r7, #4
cmp r7, #0
bne w4_xy_03_mc_luma_loop
pop {r4, r5, r6, r7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer02WidthEq16_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //q0=src[-2]
vld1.u8 {q1}, [r0], r1 //q1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //q2=src[0]
vld1.u8 {q3}, [r0], r1 //q3=src[1]
vld1.u8 {q8}, [r0], r1 //q8=src[2]
w16_v_mc_luma_loop:
vld1.u8 {q9}, [r0], r1 //q9=src[3]
FILTER_6TAG_8BITS d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 2nd row
vst1.u8 {q10}, [r2], r3 //write 1st 16Byte
FILTER_6TAG_8BITS d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d3, d5, d7, d17, d19, d1, d21, q14, q15
vld1.u8 {q1}, [r0], r1 //read 3rd row
vst1.u8 {q10}, [r2], r3 //write 2nd 16Byte
FILTER_6TAG_8BITS d4, d6, d16, d18, d0, d2, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d5, d7, d17, d19, d1, d3, d21, q14, q15
vld1.u8 {q2}, [r0], r1 //read 4th row
vst1.u8 {q10}, [r2], r3 //write 3rd 16Byte
FILTER_6TAG_8BITS d6, d16, d18, d0, d2, d4, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d7, d17, d19, d1, d3, d5, d21, q14, q15
vld1.u8 {q3}, [r0], r1 //read 5th row
vst1.u8 {q10}, [r2], r3 //write 4th 16Byte
FILTER_6TAG_8BITS d16, d18, d0, d2, d4, d6, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d17, d19, d1, d3, d5, d7, d21, q14, q15
vld1.u8 {q8}, [r0], r1 //read 6th row
vst1.u8 {q10}, [r2], r3 //write 5th 16Byte
FILTER_6TAG_8BITS d18, d0, d2, d4, d6, d16, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d19, d1, d3, d5, d7, d17, d21, q14, q15
vld1.u8 {q9}, [r0], r1 //read 7th row
vst1.u8 {q10}, [r2], r3 //write 6th 16Byte
FILTER_6TAG_8BITS d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 8th row
vst1.u8 {q10}, [r2], r3 //write 7th 16Byte
FILTER_6TAG_8BITS d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d3, d5, d7, d17, d19, d1, d21, q14, q15
vst1.u8 {q10}, [r2], r3 //write 8th 16Byte
//q2, q3, q8, q9, q0 --> q0~q8
vswp q0, q8
vswp q0, q2
vmov q1, q3
vmov q3, q9 //q0~q8
sub r4, #8
cmp r4, #0
bne w16_v_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer02WidthEq8_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0}, [r0], r1 //d0=src[-2]
vld1.u8 {d1}, [r0], r1 //d1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d2}, [r0], r1 //d2=src[0]
vld1.u8 {d3}, [r0], r1 //d3=src[1]
vld1.u8 {d4}, [r0], r1 //d4=src[2]
vld1.u8 {d5}, [r0], r1 //d5=src[3]
w8_v_mc_luma_loop:
pld [r0]
FILTER_6TAG_8BITS d0, d1, d2, d3, d4, d5, d16, q14, q15
vld1.u8 {d0}, [r0], r1 //read 2nd row
vst1.u8 {d16}, [r2], r3 //write 1st 8Byte
pld [r0]
FILTER_6TAG_8BITS d1, d2, d3, d4, d5, d0, d16, q14, q15
vld1.u8 {d1}, [r0], r1 //read 3rd row
vst1.u8 {d16}, [r2], r3 //write 2nd 8Byte
pld [r0]
FILTER_6TAG_8BITS d2, d3, d4, d5, d0, d1, d16, q14, q15
vld1.u8 {d2}, [r0], r1 //read 4th row
vst1.u8 {d16}, [r2], r3 //write 3rd 8Byte
pld [r0]
FILTER_6TAG_8BITS d3, d4, d5, d0, d1, d2, d16, q14, q15
vld1.u8 {d3}, [r0], r1 //read 5th row
vst1.u8 {d16}, [r2], r3 //write 4th 8Byte
//d4, d5, d0, d1, d2, d3 --> d0, d1, d2, d3, d4, d5
vswp q0, q2
vswp q1, q2
sub r4, #4
cmp r4, #0
bne w8_v_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer02WidthEq4_neon
push {r4, r5, r6, r7}
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
ldr r4, [r0], r1 //r4=src[-2]
ldr r5, [r0], r1 //r5=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
ldr r6, [r0], r1 //r6=src[0]
ldr r7, [r0], r1 //r7=src[1]
vmov d0, r4, r5
vmov d1, r5, r6
vmov d2, r6, r7
ldr r4, [r0], r1 //r4=src[2]
vmov d3, r7, r4
ldr r7, [sp, #16]
w4_v_mc_luma_loop:
// pld [r0]
//using reserving r4
ldr r5, [r0], r1 //r5=src[3]
ldr r6, [r0], r1 //r6=src[0]
vmov d4, r4, r5
vmov d5, r5, r6 //reserved r6
FILTER_6TAG_8BITS d0, d1, d2, d3, d4, d5, d16, q14, q15
vmov r4, r5, d16
str r4, [r2], r3 //write 1st 4Byte
str r5, [r2], r3 //write 2nd 4Byte
ldr r5, [r0], r1 //r5=src[1]
ldr r4, [r0], r1 //r4=src[2]
vmov d0, r6, r5
vmov d1, r5, r4 //reserved r4
FILTER_6TAG_8BITS d2, d3, d4, d5, d0, d1, d16, q14, q15
vmov r5, r6, d16
str r5, [r2], r3 //write 3rd 4Byte
str r6, [r2], r3 //write 4th 4Byte
//d4, d5, d0, d1 --> d0, d1, d2, d3
vmov q1, q0
vmov q0, q2
sub r7, #4
cmp r7, #0
bne w4_v_mc_luma_loop
pop {r4, r5, r6, r7}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer22WidthEq16_neon
push {r4}
vpush {q4-q7}
ldr r4, [sp, #68]
sub r0, #2 //src[-2]
sub r0, r0, r1, lsl #1 //src[-2*src_stride-2]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0-d2}, [r0], r1 //use 21(16+5), =src[-2]
vld1.u8 {d3-d5}, [r0], r1 //use 21(16+5), =src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d6-d8}, [r0], r1 //use 21(16+5), =src[0]
vld1.u8 {d9-d11}, [r0], r1 //use 21(16+5), =src[1]
pld [r0]
pld [r0, r1]
vld1.u8 {d12-d14}, [r0], r1 //use 21(16+5), =src[2]
w16_hv_mc_luma_loop:
vld1.u8 {d15-d17}, [r0], r1 //use 21(16+5), =src[3]
//the 1st row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d3, d6, d9, d12, d15, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d4, d7,d10, d13, d16,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d0 //output to q0[0]
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d2, d5, d8,d11, d14, d17,q11, q14, q15 // only 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d1 //output to q0[1]
vst1.u8 {q0}, [r2], r3 //write 16Byte
vld1.u8 {d0-d2}, [r0], r1 //read 2nd row
//the 2nd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d3, d6, d9, d12, d15, d0, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d4, d7,d10, d13, d16, d1,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d3 //output to d3
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d5, d8,d11, d14, d17, d2,q11, q14, q15 // only 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d4 //output to d4
vst1.u8 {d3, d4}, [r2], r3 //write 16Byte
vld1.u8 {d3-d5}, [r0], r1 //read 3rd row
//the 3rd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d6, d9, d12, d15, d0, d3, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d7,d10, d13, d16, d1, d4,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d6 //output to d6
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d8,d11, d14, d17, d2, d5,q11, q14, q15 // only 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d7 //output to d7
vst1.u8 {d6, d7}, [r2], r3 //write 16Byte
vld1.u8 {d6-d8}, [r0], r1 //read 4th row
//the 4th row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d9, d12, d15, d0, d3, d6, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d10, d13, d16, d1, d4, d7,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d9 //output to d9
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d11, d14, d17, d2, d5, d8,q11, q14, q15 // only 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d10 //output to d10
vst1.u8 {d9, d10}, [r2], r3 //write 16Byte
//d12~d17(q6~q8), d0~d8(q0~q3+d8), --> d0~d14
vswp q0, q6
vswp q6, q3
vmov q5, q2
vmov q2, q8
vmov d20,d8
vmov q4, q1
vmov q1, q7
vmov d14,d20
sub r4, #4
cmp r4, #0
bne w16_hv_mc_luma_loop
vpop {q4-q7}
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer22WidthEq8_neon
push {r4}
vpush {q4}
ldr r4, [sp, #20]
sub r0, #2 //src[-2]
sub r0, r0, r1, lsl #1 //src[-2*src_stride-2]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //use 13(8+5), =src[-2]
vld1.u8 {q1}, [r0], r1 //use 13(8+5), =src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //use 13(8+5), =src[0]
vld1.u8 {q3}, [r0], r1 //use 13(8+5), =src[1]
pld [r0]
pld [r0, r1]
vld1.u8 {q4}, [r0], r1 //use 13(8+5), =src[2]
w8_hv_mc_luma_loop:
vld1.u8 {q8}, [r0], r1 //use 13(8+5), =src[3]
//the 1st row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d2, d4, d6, d8, d16, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d3, d5, d7, d9, d17, q10, q14, q15 // 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2], r3 //write 8Byte
vld1.u8 {q0}, [r0], r1 //read 2nd row
//the 2nd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d2, d4, d6, d8, d16, d0, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d3, d5, d7, d9, d17, d1, q10, q14, q15 // 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2], r3 //write 8Byte
vld1.u8 {q1}, [r0], r1 //read 3rd row
//the 3rd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d4, d6, d8, d16, d0, d2, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d5, d7, d9, d17, d1, d3, q10, q14, q15 // 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2], r3 //write 8Byte
vld1.u8 {q2}, [r0], r1 //read 4th row
//the 4th row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d6, d8, d16, d0, d2, d4, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d7, d9, d17, d1, d3, d5, q10, q14, q15 // 5 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2], r3 //write 8Byte
//q4~q5, q0~q2, --> q0~q4
vswp q0, q4
vswp q2, q4
vmov q3, q1
vmov q1, q8
sub r4, #4
cmp r4, #0
bne w8_hv_mc_luma_loop
vpop {q4}
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer22WidthEq4_neon
push {r4 ,r5, r6}
vpush {q4-q7}
ldr r6, [sp, #76]
sub r0, #2 //src[-2]
sub r0, r0, r1, lsl #1 //src[-2*src_stride-2]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //use 9(4+5), =src[-2]
vld1.u8 {q1}, [r0], r1 //use 9(4+5), =src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //use 9(4+5), =src[0]
vld1.u8 {q3}, [r0], r1 //use 9(4+5), =src[1]
pld [r0]
pld [r0, r1]
vld1.u8 {q4}, [r0], r1 //use 9(4+5), =src[2]
w4_hv_mc_luma_loop:
vld1.u8 {q5}, [r0], r1 //use 9(4+5), =src[3]
vld1.u8 {q6}, [r0], r1 //use 9(4+5), =src[4]
//the 1st&2nd row
pld [r0]
pld [r0, r1]
// vertical filtered
FILTER_6TAG_8BITS_TO_16BITS d0, d2, d4, d6, d8, d10, q7, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d3, d5, d7, d9, d11, q8, q14, q15 // 1 avail
FILTER_6TAG_8BITS_TO_16BITS d2, d4, d6, d8,d10, d12, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d3, d5, d7, d9,d11, d13,q10, q14, q15 // 1 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q7, q8, q11, q12, q13 //4 avail
UNPACK_2_16BITS_TO_ABC q9,q10, q0, q7, q8 //4 avail
vmov d23, d0
vmov d25, d14
vmov d27, d16
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d22 //output to q11[0]
vmov r4 ,r5, d22
str r4, [r2], r3 //write 4Byte
str r5, [r2], r3 //write 4Byte
//the 3rd&4th row
vld1.u8 {q0}, [r0], r1 //use 9(4+5), =src[3]
vld1.u8 {q1}, [r0], r1 //use 9(4+5), =src[4]
pld [r0]
pld [r0, r1]
// vertical filtered
FILTER_6TAG_8BITS_TO_16BITS d4, d6, d8, d10, d12, d0, q7, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d5, d7, d9, d11, d13, d1, q8, q14, q15 // 1 avail
FILTER_6TAG_8BITS_TO_16BITS d6, d8,d10, d12, d0, d2, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d7, d9,d11, d13, d1, d3,q10, q14, q15 // 1 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q7, q8, q11, q12, q13 //4 avail
UNPACK_2_16BITS_TO_ABC q9,q10, q2, q7, q8 //4 avail
vmov d23, d4
vmov d25, d14
vmov d27, d16
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d22 //output to q11[0]
vmov r4 ,r5, d22
str r4, [r2], r3 //write 4Byte
str r5, [r2], r3 //write 4Byte
//q4~q6, q0~q1, --> q0~q4
vswp q4, q0
vmov q3, q4
vmov q4, q1
vmov q1, q5
vmov q2, q6
sub r6, #4
cmp r6, #0
bne w4_hv_mc_luma_loop
vpop {q4-q7}
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McCopyWidthEq16_neon
push {r4}
ldr r4, [sp, #4]
w16_copy_loop:
vld1.u8 {q0}, [r0], r1
sub r4, #2
vld1.u8 {q1}, [r0], r1
vst1.u8 {q0}, [r2], r3
cmp r4, #0
vst1.u8 {q1}, [r2], r3
bne w16_copy_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McCopyWidthEq8_neon
push {r4}
ldr r4, [sp, #4]
w8_copy_loop:
vld1.u8 {d0}, [r0], r1
vld1.u8 {d1}, [r0], r1
vst1.u8 {d0}, [r2], r3
vst1.u8 {d1}, [r2], r3
sub r4, #2
cmp r4, #0
bne w8_copy_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McCopyWidthEq4_neon
push {r4, r5, r6}
ldr r4, [sp, #12]
w4_copy_loop:
ldr r5, [r0], r1
ldr r6, [r0], r1
str r5, [r2], r3
str r6, [r2], r3
sub r4, #2
cmp r4, #0
bne w4_copy_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN PixelAvgWidthEq16_neon
push {r4}
ldr r4, [sp, #4]
w16_pix_avg_loop:
vld1.u8 {q0}, [r2]!
vld1.u8 {q1}, [r3]!
vld1.u8 {q2}, [r2]!
vld1.u8 {q3}, [r3]!
vld1.u8 {q8}, [r2]!
vld1.u8 {q9}, [r3]!
vld1.u8 {q10}, [r2]!
vld1.u8 {q11}, [r3]!
AVERAGE_TWO_8BITS d0, d0, d2
AVERAGE_TWO_8BITS d1, d1, d3
vst1.u8 {q0}, [r0], r1
AVERAGE_TWO_8BITS d4, d4, d6
AVERAGE_TWO_8BITS d5, d5, d7
vst1.u8 {q2}, [r0], r1
AVERAGE_TWO_8BITS d16, d16, d18
AVERAGE_TWO_8BITS d17, d17, d19
vst1.u8 {q8}, [r0], r1
AVERAGE_TWO_8BITS d20, d20, d22
AVERAGE_TWO_8BITS d21, d21, d23
vst1.u8 {q10}, [r0], r1
sub r4, #4
cmp r4, #0
bne w16_pix_avg_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN PixelAvgWidthEq8_neon
push {r4, r5}
ldr r4, [sp, #8]
mov r5, #16
w8_pix_avg_loop:
vld1.u8 {d0}, [r2], r5
vld1.u8 {d2}, [r3], r5
vld1.u8 {d1}, [r2], r5
vld1.u8 {d3}, [r3], r5
AVERAGE_TWO_8BITS d0, d0, d2
AVERAGE_TWO_8BITS d1, d1, d3
vst1.u8 {d0}, [r0], r1
vst1.u8 {d1}, [r0], r1
vld1.u8 {d4}, [r2], r5
vld1.u8 {d6}, [r3], r5
vld1.u8 {d5}, [r2], r5
vld1.u8 {d7}, [r3], r5
AVERAGE_TWO_8BITS d4, d4, d6
AVERAGE_TWO_8BITS d5, d5, d7
vst1.u8 {d4}, [r0], r1
vst1.u8 {d5}, [r0], r1
sub r4, #4
cmp r4, #0
bne w8_pix_avg_loop
pop {r4, r5}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN PixelAvgWidthEq4_neon
push {r4-r8}
ldr r4, [sp, #20]
w4_pix_avg_loop:
ldr r5, [r2]
ldr r6, [r2, #16]
ldr r7, [r3]
ldr r8, [r3, #16]
add r2, #32
add r3, #32
vmov d0, r5, r6
vmov d1, r7, r8
AVERAGE_TWO_8BITS d0, d0, d1
vmov r5, r6, d0
str r5, [r0], r1
str r6, [r0], r1
sub r4, #2
cmp r4, #0
bne w4_pix_avg_loop
pop {r4-r8}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McChromaWidthEq8_neon
push {r4, r5}
ldr r4, [sp, #8]
ldr r5, [sp, #12]
// normal case: {cA*src[x] + cB*src[x+1]} + {cC*src[x+stride] + cD*srcp[x+stride+1]}
// we can opti it by adding vert only/ hori only cases, to be continue
vld1.u8 {d31}, [r4] //load A/B/C/D
vld1.u8 {q0}, [r0], r1 //src[x]
vdup.u8 d28, d31[0] //A
vdup.u8 d29, d31[1] //B
vdup.u8 d30, d31[2] //C
vdup.u8 d31, d31[3] //D
vext.u8 d1, d0, d1, #1 //src[x+1]
w8_mc_chroma_loop: // each two pxl row
vld1.u8 {q1}, [r0], r1 //src[x+stride]
vld1.u8 {q2}, [r0], r1 //src[x+2*stride]
vext.u8 d3, d2, d3, #1 //src[x+stride+1]
vext.u8 d5, d4, d5, #1 //src[x+2*stride+1]
vmull.u8 q3, d0, d28 //(src[x] * A)
vmlal.u8 q3, d1, d29 //+=(src[x+1] * B)
vmlal.u8 q3, d2, d30 //+=(src[x+stride] * C)
vmlal.u8 q3, d3, d31 //+=(src[x+stride+1] * D)
vrshrn.u16 d6, q3, #6
vst1.u8 d6, [r2], r3
vmull.u8 q3, d2, d28 //(src[x] * A)
vmlal.u8 q3, d3, d29 //+=(src[x+1] * B)
vmlal.u8 q3, d4, d30 //+=(src[x+stride] * C)
vmlal.u8 q3, d5, d31 //+=(src[x+stride+1] * D)
vrshrn.u16 d6, q3, #6
vst1.u8 d6, [r2], r3
vmov q0, q2
sub r5, #2
cmp r5, #0
bne w8_mc_chroma_loop
pop {r4, r5}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McChromaWidthEq4_neon
push {r4, r5, r6}
ldr r4, [sp, #12]
ldr r6, [sp, #16]
// normal case: {cA*src[x] + cB*src[x+1]} + {cC*src[x+stride] + cD*srcp[x+stride+1]}
// we can opti it by adding vert only/ hori only cases, to be continue
vld1.u8 {d31}, [r4] //load A/B/C/D
vdup.u8 d28, d31[0] //A
vdup.u8 d29, d31[1] //B
vdup.u8 d30, d31[2] //C
vdup.u8 d31, d31[3] //D
w4_mc_chroma_loop: // each two pxl row
vld1.u8 {d0}, [r0], r1 //a::src[x]
vld1.u8 {d2}, [r0], r1 //b::src[x+stride]
vld1.u8 {d4}, [r0] //c::src[x+2*stride]
vshr.u64 d1, d0, #8
vshr.u64 d3, d2, #8
vshr.u64 d5, d4, #8
vmov q3, q1 //b::[0:7]+b::[1~8]
vtrn.32 q0, q1 //d0{a::[0:3]+b::[0:3]}; d1{a::[1:4]+b::[1:4]}
vtrn.32 q3, q2 //d6{b::[0:3]+c::[0:3]}; d7{b::[1:4]+c::[1:4]}
vmull.u8 q1, d0, d28 //(src[x] * A)
vmlal.u8 q1, d1, d29 //+=(src[x+1] * B)
vmlal.u8 q1, d6, d30 //+=(src[x+stride] * C)
vmlal.u8 q1, d7, d31 //+=(src[x+stride+1] * D)
vrshrn.u16 d2, q1, #6
vmov r4, r5, d2
str r4, [r2], r3
str r5, [r2], r3
sub r6, #2
cmp r6, #0
bne w4_mc_chroma_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer20Width17_neon
push {r4-r5}
mov r4, #20
mov r5, #1
sub r4, r4, r4, lsl #(16-2)
lsl r5, #16
ror r4, #16
vmov d3, r5, r4 // 0x0014FFFB00010000
sub r3, #16
ldr r4, [sp, #8]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w17_h_mc_luma_loop:
vld1.u8 {d0,d1,d2}, [r0], r1 //only use 22(17+5); q0=src[-2]
vext.8 q2, q0, q1, #1 //q2=src[-1]
vext.8 q3, q0, q1, #2 //q3=src[0]
vext.8 q8, q0, q1, #3 //q8=src[1]
vext.8 q9, q0, q1, #4 //q9=src[2]
vext.8 q10, q0, q1, #5 //q10=src[3]
FILTER_6TAG_8BITS d0, d4, d6, d16, d18, d20, d22, q14, q15
FILTER_6TAG_8BITS d1, d5, d7, d17, d19, d21, d23, q14, q15
vst1.u8 {d22, d23}, [r2]! //write [0:15] Byte
vsli.64 d2, d2, #8 // [0][1][2][3][4][5]XO-->O[0][1][2][3][4][5]X
FILTER_SINGLE_TAG_8BITS d2, d3, d22, q11, q1
vst1.u8 {d2[0]}, [r2], r3 //write 16th Byte
sub r4, #1
cmp r4, #0
bne w17_h_mc_luma_loop
pop {r4-r5}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer20Width9_neon
push {r4-r5}
mov r4, #20
mov r5, #1
sub r4, r4, r4, lsl #(16-2)
lsl r5, #16
ror r4, #16
vmov d7, r5, r4 // 0x0014FFFB00010000
sub r3, #8
ldr r4, [sp, #8]
sub r0, #2
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w9_h_mc_luma_loop:
vld1.u8 {d0,d1}, [r0], r1 //only use 14(9+5); q0=src[-2]
pld [r0]
vext.8 d2, d0, d1, #1 //d2=src[-1]
vext.8 d3, d0, d1, #2 //d3=src[0]
vext.8 d4, d0, d1, #3 //d4=src[1]
vext.8 d5, d0, d1, #4 //d5=src[2]
vext.8 d6, d0, d1, #5 //d6=src[3]
FILTER_6TAG_8BITS d0, d2, d3, d4, d5, d6, d16, q14, q15
sub r4, #1
vst1.u8 {d16}, [r2]! //write [0:7] Byte
vsli.64 d2, d1, #8 // [0][1][2][3][4][5]XO-->O[0][1][2][3][4][5]X
FILTER_SINGLE_TAG_8BITS d2, d7, d18, q9, q1
vst1.u8 {d2[0]}, [r2], r3 //write 8th Byte
cmp r4, #0
bne w9_h_mc_luma_loop
pop {r4-r5}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer20Width5_neon
push {r4}
sub r3, #4
sub r0, #2
ldr r4, [sp, #4]
vmov.u16 q14, #0x0014 // 20
vshr.u16 q15, q14, #2 // 5
w5_h_mc_luma_loop:
vld1.u8 {d0,d1}, [r0], r1 //only use 10(5+5); q0=src[-2]
pld [r0]
vext.8 d2, d0, d1, #1 //d2=src[-1]
vext.8 d3, d0, d1, #2 //d3=src[0]
vext.8 d4, d0, d1, #3 //d4=src[1]
vext.8 d5, d0, d1, #4 //d5=src[2]
vext.8 d6, d0, d1, #5 //d6=src[3]
FILTER_6TAG_8BITS d0, d2, d3, d4, d5, d6, d16, q14, q15
sub r4, #1
vst1.u32 {d16[0]}, [r2]! //write [0:3] Byte
vst1.u8 {d16[4]}, [r2], r3 //write 5th Byte
cmp r4, #0
bne w5_h_mc_luma_loop
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer02Height17_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //q0=src[-2]
vld1.u8 {q1}, [r0], r1 //q1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //q2=src[0]
vld1.u8 {q3}, [r0], r1 //q3=src[1]
vld1.u8 {q8}, [r0], r1 //q8=src[2]
w17_v_mc_luma_loop:
vld1.u8 {q9}, [r0], r1 //q9=src[3]
FILTER_6TAG_8BITS d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 2nd row
vst1.u8 {q10}, [r2], r3 //write 1st 16Byte
FILTER_6TAG_8BITS d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d3, d5, d7, d17, d19, d1, d21, q14, q15
vld1.u8 {q1}, [r0], r1 //read 3rd row
vst1.u8 {q10}, [r2], r3 //write 2nd 16Byte
FILTER_6TAG_8BITS d4, d6, d16, d18, d0, d2, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d5, d7, d17, d19, d1, d3, d21, q14, q15
vld1.u8 {q2}, [r0], r1 //read 4th row
vst1.u8 {q10}, [r2], r3 //write 3rd 16Byte
FILTER_6TAG_8BITS d6, d16, d18, d0, d2, d4, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d7, d17, d19, d1, d3, d5, d21, q14, q15
vld1.u8 {q3}, [r0], r1 //read 5th row
vst1.u8 {q10}, [r2], r3 //write 4th 16Byte
FILTER_6TAG_8BITS d16, d18, d0, d2, d4, d6, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d17, d19, d1, d3, d5, d7, d21, q14, q15
vld1.u8 {q8}, [r0], r1 //read 6th row
vst1.u8 {q10}, [r2], r3 //write 5th 16Byte
FILTER_6TAG_8BITS d18, d0, d2, d4, d6, d16, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d19, d1, d3, d5, d7, d17, d21, q14, q15
vld1.u8 {q9}, [r0], r1 //read 7th row
vst1.u8 {q10}, [r2], r3 //write 6th 16Byte
FILTER_6TAG_8BITS d0, d2, d4, d6, d16, d18, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d1, d3, d5, d7, d17, d19, d21, q14, q15
vld1.u8 {q0}, [r0], r1 //read 8th row
vst1.u8 {q10}, [r2], r3 //write 7th 16Byte
FILTER_6TAG_8BITS d2, d4, d6, d16, d18, d0, d20, q14, q15
pld [r0]
FILTER_6TAG_8BITS d3, d5, d7, d17, d19, d1, d21, q14, q15
vst1.u8 {q10}, [r2], r3 //write 8th 16Byte
//q2, q3, q8, q9, q0 --> q0~q8
vswp q0, q8
vswp q0, q2
vmov q1, q3
vmov q3, q9 //q0~q8
sub r4, #8
cmp r4, #1
bne w17_v_mc_luma_loop
// the last 16Bytes
vld1.u8 {q9}, [r0], r1 //q9=src[3]
FILTER_6TAG_8BITS d0, d2, d4, d6, d16, d18, d20, q14, q15
FILTER_6TAG_8BITS d1, d3, d5, d7, d17, d19, d21, q14, q15
vst1.u8 {q10}, [r2], r3 //write 1st 16Byte
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer02Height9_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0}, [r0], r1 //d0=src[-2]
vld1.u8 {d1}, [r0], r1 //d1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d2}, [r0], r1 //d2=src[0]
vld1.u8 {d3}, [r0], r1 //d3=src[1]
vld1.u8 {d4}, [r0], r1 //d4=src[2]
vld1.u8 {d5}, [r0], r1 //d5=src[3]
w9_v_mc_luma_loop:
pld [r0]
FILTER_6TAG_8BITS d0, d1, d2, d3, d4, d5, d16, q14, q15
vld1.u8 {d0}, [r0], r1 //read 2nd row
vst1.u8 {d16}, [r2], r3 //write 1st 8Byte
pld [r0]
FILTER_6TAG_8BITS d1, d2, d3, d4, d5, d0, d16, q14, q15
vld1.u8 {d1}, [r0], r1 //read 3rd row
vst1.u8 {d16}, [r2], r3 //write 2nd 8Byte
pld [r0]
FILTER_6TAG_8BITS d2, d3, d4, d5, d0, d1, d16, q14, q15
vld1.u8 {d2}, [r0], r1 //read 4th row
vst1.u8 {d16}, [r2], r3 //write 3rd 8Byte
pld [r0]
FILTER_6TAG_8BITS d3, d4, d5, d0, d1, d2, d16, q14, q15
vld1.u8 {d3}, [r0], r1 //read 5th row
vst1.u8 {d16}, [r2], r3 //write 4th 8Byte
//d4, d5, d0, d1, d2, d3 --> d0, d1, d2, d3, d4, d5
vswp q0, q2
vswp q1, q2
sub r4, #4
cmp r4, #1
bne w9_v_mc_luma_loop
FILTER_6TAG_8BITS d0, d1, d2, d3, d4, d5, d16, q14, q15
vst1.u8 {d16}, [r2], r3 //write last 8Byte
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer02Height5_neon
push {r4}
ldr r4, [sp, #4]
sub r0, r0, r1, lsl #1 //src[-2*src_stride]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0}, [r0], r1 //d0=src[-2]
vld1.u8 {d1}, [r0], r1 //d1=src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d2}, [r0], r1 //d2=src[0]
vld1.u8 {d3}, [r0], r1 //d3=src[1]
vld1.u8 {d4}, [r0], r1 //d4=src[2]
vld1.u8 {d5}, [r0], r1 //d5=src[3]
w5_v_mc_luma_loop:
pld [r0]
FILTER_6TAG_8BITS d0, d1, d2, d3, d4, d5, d16, q14, q15
vld1.u8 {d0}, [r0], r1 //read 2nd row
vst1.u32 {d16[0]}, [r2], r3 //write 1st 4Byte
pld [r0]
FILTER_6TAG_8BITS d1, d2, d3, d4, d5, d0, d16, q14, q15
vld1.u8 {d1}, [r0], r1 //read 3rd row
vst1.u32 {d16[0]}, [r2], r3 //write 2nd 4Byte
pld [r0]
FILTER_6TAG_8BITS d2, d3, d4, d5, d0, d1, d16, q14, q15
vld1.u8 {d2}, [r0], r1 //read 4th row
vst1.u32 {d16[0]}, [r2], r3 //write 3rd 4Byte
pld [r0]
FILTER_6TAG_8BITS d3, d4, d5, d0, d1, d2, d16, q14, q15
vld1.u8 {d3}, [r0], r1 //read 5th row
vst1.u32 {d16[0]}, [r2], r3 //write 4th 8Byte
//d4, d5, d0, d1, d2, d3 --> d0, d1, d2, d3, d4, d5
vswp q0, q2
vswp q1, q2
sub r4, #4
cmp r4, #1
bne w5_v_mc_luma_loop
FILTER_6TAG_8BITS d0, d1, d2, d3, d4, d5, d16, q14, q15
vst1.u32 {d16[0]}, [r2], r3 //write last 4Byte
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer22Width17_neon
push {r4}
vpush {q4-q7}
ldr r4, [sp, #68]
sub r0, #2 //src[-2]
sub r0, r0, r1, lsl #1 //src[-2*src_stride-2]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {d0-d2}, [r0], r1 //use 21(17+5), =src[-2]
vld1.u8 {d3-d5}, [r0], r1 //use 21(17+5), =src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {d6-d8}, [r0], r1 //use 21(17+5), =src[0]
vld1.u8 {d9-d11}, [r0], r1 //use 21(17+5), =src[1]
pld [r0]
pld [r0, r1]
vld1.u8 {d12-d14}, [r0], r1 //use 21(17+5), =src[2]
sub r3, #16
w17_hv_mc_luma_loop:
vld1.u8 {d15-d17}, [r0], r1 //use 21(17+5), =src[3]
//the 1st row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d3, d6, d9, d12, d15, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d4, d7,d10, d13, d16,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d0 //output to q0[0]
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d2, d5, d8,d11, d14, d17,q11, q14, q15 // only 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d1 //output to q0[1]
vst1.u8 {d0, d1}, [r2]! //write 16Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d2, d22, d23, q11 //output to d2[0]
vst1.u8 {d2[0]}, [r2], r3 //write 16th Byte
vld1.u8 {d0-d2}, [r0], r1 //read 2nd row
//the 2nd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d3, d6, d9, d12, d15, d0, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d4, d7,d10, d13, d16, d1,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d3 //output to d3
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d5, d8,d11, d14, d17, d2,q11, q14, q15 // only 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d4 //output to d4
vst1.u8 {d3, d4}, [r2]! //write 16Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d5, d22, d23, q11 //output to d5[0]
vst1.u8 {d5[0]}, [r2], r3 //write 16th Byte
vld1.u8 {d3-d5}, [r0], r1 //read 3rd row
//the 3rd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d6, d9, d12, d15, d0, d3, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d7,d10, d13, d16, d1, d4,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d6 //output to d6
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d8,d11, d14, d17, d2, d5,q11, q14, q15 // only 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d7 //output to d7
vst1.u8 {d6, d7}, [r2]! //write 16Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d8, d22, d23, q11 //output to d8[0]
vst1.u8 {d8[0]}, [r2], r3 //write 16th Byte
vld1.u8 {d6-d8}, [r0], r1 //read 4th row
//the 4th row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d9, d12, d15, d0, d3, d6, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d10, d13, d16, d1, d4, d7,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d9 //output to d9
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d11, d14, d17, d2, d5, d8,q11, q14, q15 // only 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d10 //output to d10
vst1.u8 {d9, d10}, [r2]! //write 16Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d11, d22, d23, q11 //output to d11[0]
vst1.u8 {d11[0]}, [r2], r3 //write 16th Byte
//d12~d17(q6~q8), d0~d8(q0~q3+d8), --> d0~d14
vswp q0, q6
vswp q6, q3
vmov q5, q2
vmov q2, q8
vmov d20,d8
vmov q4, q1
vmov q1, q7
vmov d14,d20
sub r4, #4
cmp r4, #1
bne w17_hv_mc_luma_loop
//the last row
vld1.u8 {d15-d17}, [r0], r1 //use 21(17+5), =src[3]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d3, d6, d9, d12, d15, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d4, d7,d10, d13, d16,q10, q14, q15 // 8 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d0 //output to q0[0]
// vertical filtered into q10/q11
FILTER_6TAG_8BITS_TO_16BITS d2, d5, d8,d11, d14, d17,q11, q14, q15 // only 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q10, q11, q9, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q9, q12, q13, d1 //output to q0[1]
vst1.u8 {q0}, [r2]! //write 16Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d2, d22, d23, q11 //output to d2[0]
vst1.u8 {d2[0]}, [r2], r3 //write 16th Byte
vpop {q4-q7}
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer22Width9_neon
push {r4}
vpush {q4}
ldr r4, [sp, #20]
sub r0, #2 //src[-2]
sub r0, r0, r1, lsl #1 //src[-2*src_stride-2]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //use 14(9+5), =src[-2]
vld1.u8 {q1}, [r0], r1 //use 14(9+5), =src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //use 14(9+5), =src[0]
vld1.u8 {q3}, [r0], r1 //use 14(9+5), =src[1]
pld [r0]
pld [r0, r1]
vld1.u8 {q4}, [r0], r1 //use 14(9+5), =src[2]
sub r3, #8
w9_hv_mc_luma_loop:
vld1.u8 {q8}, [r0], r1 //use 14(9+5), =src[3]
//the 1st row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d2, d4, d6, d8, d16, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d3, d5, d7, d9, d17, q10, q14, q15 // 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2]! //write 8Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d19, d20, d21, q10 //output to d19[0]
vst1.u8 {d19[0]}, [r2], r3 //write 8th Byte
vld1.u8 {q0}, [r0], r1 //read 2nd row
//the 2nd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d2, d4, d6, d8, d16, d0, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d3, d5, d7, d9, d17, d1, q10, q14, q15 // 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2]! //write 8Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d19, d20, d21, q10 //output to d19[0]
vst1.u8 {d19[0]}, [r2], r3 //write 8th Byte
vld1.u8 {q1}, [r0], r1 //read 3rd row
//the 3rd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d4, d6, d8, d16, d0, d2, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d5, d7, d9, d17, d1, d3, q10, q14, q15 // 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2]! //write 8Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d19, d20, d21, q10 //output to d19[0]
vst1.u8 {d19[0]}, [r2], r3 //write 8th Byte
vld1.u8 {q2}, [r0], r1 //read 4th row
//the 4th row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d6, d8, d16, d0, d2, d4, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d7, d9, d17, d1, d3, d5, q10, q14, q15 // 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2]! //write 8Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d19, d20, d21, q10 //output to d19[0]
vst1.u8 {d19[0]}, [r2], r3 //write 8th Byte
//q4~q8, q0~q2, --> q0~q4
vswp q0, q4
vswp q2, q4
vmov q3, q1
vmov q1, q8
sub r4, #4
cmp r4, #1
bne w9_hv_mc_luma_loop
//the last row
vld1.u8 {q8}, [r0], r1 //use 14(9+5), =src[3]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d2, d4, d6, d8, d16, q9, q14, q15 // 8 avail
FILTER_6TAG_8BITS_TO_16BITS d1, d3, d5, d7, d9, d17, q10, q14, q15 // 6 avail
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18 //output to q9[0]
vst1.u8 d18, [r2]! //write 8Byte
UNPACK_1_IN_8x16BITS_TO_8BITS d19, d20, d21, q10 //output to d19[0]
vst1.u8 {d19[0]}, [r2], r3 //write 8th Byte
vpop {q4}
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN McHorVer22Width5_neon
push {r4}
vpush {q4}
ldr r4, [sp, #20]
sub r0, #2 //src[-2]
sub r0, r0, r1, lsl #1 //src[-2*src_stride-2]
pld [r0]
pld [r0, r1]
vmov.u16 q14, #0x0014 // 20
vld1.u8 {q0}, [r0], r1 //use 10(5+5), =src[-2]
vld1.u8 {q1}, [r0], r1 //use 10(5+5), =src[-1]
pld [r0]
pld [r0, r1]
vshr.u16 q15, q14, #2 // 5
vld1.u8 {q2}, [r0], r1 //use 10(5+5), =src[0]
vld1.u8 {q3}, [r0], r1 //use 10(5+5), =src[1]
pld [r0]
pld [r0, r1]
vld1.u8 {q4}, [r0], r1 //use 10(5+5), =src[2]
sub r3, #4
w5_hv_mc_luma_loop:
vld1.u8 {q8}, [r0], r1 //use 10(5+5), =src[3]
//the 1st row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d2, d4, d6, d8, d16, q9, q14, q15
FILTER_6TAG_8BITS_TO_16BITS d1, d3, d5, d7, d9, d17, q10, q14, q15
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18
vst1.u32 {d18[0]}, [r2]! //write 4Byte
vst1.u8 {d18[4]}, [r2], r3 //write 5th Byte
vld1.u8 {q0}, [r0], r1 //read 2nd row
//the 2nd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d2, d4, d6, d8, d16, d0, q9, q14, q15
FILTER_6TAG_8BITS_TO_16BITS d3, d5, d7, d9, d17, d1, q10, q14, q15
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18
vst1.u32 {d18[0]}, [r2]! //write 4Byte
vst1.u8 {d18[4]}, [r2], r3 //write 5th Byte
vld1.u8 {q1}, [r0], r1 //read 3rd row
//the 3rd row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d4, d6, d8, d16, d0, d2, q9, q14, q15
FILTER_6TAG_8BITS_TO_16BITS d5, d7, d9, d17, d1, d3, q10, q14, q15
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18
vst1.u32 {d18[0]}, [r2]! //write 4Byte
vst1.u8 {d18[4]}, [r2], r3 //write 5th Byte
vld1.u8 {q2}, [r0], r1 //read 4th row
//the 4th row
pld [r0]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d6, d8, d16, d0, d2, d4, q9, q14, q15
FILTER_6TAG_8BITS_TO_16BITS d7, d9, d17, d1, d3, d5, q10, q14, q15
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18
vst1.u32 {d18[0]}, [r2]! //write 4Byte
vst1.u8 {d18[4]}, [r2], r3 //write 5th Byte
//q4~q8, q0~q2, --> q0~q4
vswp q0, q4
vswp q2, q4
vmov q3, q1
vmov q1, q8
sub r4, #4
cmp r4, #1
bne w5_hv_mc_luma_loop
//the last row
vld1.u8 {q8}, [r0], r1 //use 10(5+5), =src[3]
// vertical filtered into q9/q10
FILTER_6TAG_8BITS_TO_16BITS d0, d2, d4, d6, d8, d16, q9, q14, q15
FILTER_6TAG_8BITS_TO_16BITS d1, d3, d5, d7, d9, d17, q10, q14, q15
// horizon filtered
UNPACK_2_16BITS_TO_ABC q9, q10, q11, q12, q13
FILTER_3_IN_16BITS_TO_8BITS q11, q12, q13, d18
vst1.u32 {d18[0]}, [r2]! //write 4Byte
vst1.u8 {d18[4]}, [r2], r3 //write 5th Byte
vpop {q4}
pop {r4}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN PixStrideAvgWidthEq16_neon
push {r4, r5, r6}
ldr r4, [sp, #12]
ldr r5, [sp, #16]
ldr r6, [sp, #20]
enc_w16_pix_avg_loop:
vld1.u8 {q0}, [r2], r3
vld1.u8 {q1}, [r4], r5
vld1.u8 {q2}, [r2], r3
vld1.u8 {q3}, [r4], r5
vld1.u8 {q8}, [r2], r3
vld1.u8 {q9}, [r4], r5
vld1.u8 {q10}, [r2], r3
vld1.u8 {q11}, [r4], r5
AVERAGE_TWO_8BITS d0, d0, d2
AVERAGE_TWO_8BITS d1, d1, d3
vst1.u8 {q0}, [r0], r1
AVERAGE_TWO_8BITS d4, d4, d6
AVERAGE_TWO_8BITS d5, d5, d7
vst1.u8 {q2}, [r0], r1
AVERAGE_TWO_8BITS d16, d16, d18
AVERAGE_TWO_8BITS d17, d17, d19
vst1.u8 {q8}, [r0], r1
AVERAGE_TWO_8BITS d20, d20, d22
AVERAGE_TWO_8BITS d21, d21, d23
vst1.u8 {q10}, [r0], r1
sub r6, #4
cmp r6, #0
bne enc_w16_pix_avg_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN PixStrideAvgWidthEq8_neon
push {r4, r5, r6}
ldr r4, [sp, #12]
ldr r5, [sp, #16]
ldr r6, [sp, #20]
enc_w8_pix_avg_loop:
vld1.u8 {d0}, [r2], r3
vld1.u8 {d2}, [r4], r5
vld1.u8 {d1}, [r2], r3
vld1.u8 {d3}, [r4], r5
AVERAGE_TWO_8BITS d0, d0, d2
AVERAGE_TWO_8BITS d1, d1, d3
vst1.u8 {d0}, [r0], r1
vst1.u8 {d1}, [r0], r1
vld1.u8 {d4}, [r2], r3
vld1.u8 {d6}, [r4], r5
vld1.u8 {d5}, [r2], r3
vld1.u8 {d7}, [r4], r5
AVERAGE_TWO_8BITS d4, d4, d6
AVERAGE_TWO_8BITS d5, d5, d7
vst1.u8 {d4}, [r0], r1
vst1.u8 {d5}, [r0], r1
sub r6, #4
cmp r6, #0
bne enc_w8_pix_avg_loop
pop {r4, r5, r6}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 6,689 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm64/copy_mb_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro LOAD_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, src*, src_stride
ld1 {\arg0\().d}[0], [\arg4], \arg5
ld1 {\arg1\().d}[0], [\arg4], \arg5
ld1 {\arg2\().d}[0], [\arg4], \arg5
ld1 {\arg3\().d}[0], [\arg4], \arg5
// }
.endm
.macro STORE_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, dst*, dst_stride
st1 {\arg0\().d}[0], [\arg4], \arg5
st1 {\arg1\().d}[0], [\arg4], \arg5
st1 {\arg2\().d}[0], [\arg4], \arg5
st1 {\arg3\().d}[0], [\arg4], \arg5
// }
.endm
.macro LOAD_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, src*, src_stride
ld1 {\arg0\().8b}, [\arg4], \arg5
ld1 {\arg1\().8b}, [\arg4], \arg5
ld1 {\arg2\().8b}, [\arg4], \arg5
ld1 {\arg3\().8b}, [\arg4], \arg5
// }
.endm
.macro STORE_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, dst*, dst_stride
st1 {\arg0\().8b}, [\arg4], \arg5
st1 {\arg1\().8b}, [\arg4], \arg5
st1 {\arg2\().8b}, [\arg4], \arg5
st1 {\arg3\().8b}, [\arg4], \arg5
// }
.endm
.macro LOAD16_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, src*, src_stride
ld1 {\arg0\().2d}, [\arg4], \arg5
ld1 {\arg1\().2d}, [\arg4], \arg5
ld1 {\arg2\().2d}, [\arg4], \arg5
ld1 {\arg3\().2d}, [\arg4], \arg5
// }
.endm
.macro STORE16_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, dst*, dst_stride
st1 {\arg0\().2d}, [\arg4], \arg5
st1 {\arg1\().2d}, [\arg4], \arg5
st1 {\arg2\().2d}, [\arg4], \arg5
st1 {\arg3\().2d}, [\arg4], \arg5
// }
.endm
.macro LOAD16_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, src*, src_stride
ld1 {\arg0\().16b}, [\arg4], \arg5
ld1 {\arg1\().16b}, [\arg4], \arg5
ld1 {\arg2\().16b}, [\arg4], \arg5
ld1 {\arg3\().16b}, [\arg4], \arg5
// }
.endm
.macro STORE16_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
// { // input: $0~$3, dst*, dst_stride
st1 {\arg0\().16b}, [\arg4], \arg5
st1 {\arg1\().16b}, [\arg4], \arg5
st1 {\arg2\().16b}, [\arg4], \arg5
st1 {\arg3\().16b}, [\arg4], \arg5
// }
.endm
//void WelsCopy8x8_AArch64_neon (uint8_t* pDst, int32_t iStrideD, uint8_t* pSrc, int32_t iStrideS);
WELS_ASM_AARCH64_FUNC_BEGIN WelsCopy8x8_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
LOAD_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD_UNALIGNED_DATA_WITH_STRIDE v4, v5, v6, v7, x2, x3
STORE_UNALIGNED_DATA_WITH_STRIDE v4, v5, v6, v7, x0, x1
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsCopy16x16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
LOAD16_ALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE16_ALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD16_ALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x2, x3
STORE16_ALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x0, x1
LOAD16_ALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE16_ALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD16_ALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x2, x3
STORE16_ALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x0, x1
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsCopy16x16NotAligned_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
LOAD16_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE16_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD16_UNALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x2, x3
STORE16_UNALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x0, x1
LOAD16_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE16_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD16_UNALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x2, x3
STORE16_UNALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x0, x1
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsCopy16x8NotAligned_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
LOAD16_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE16_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD16_UNALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x2, x3
STORE16_UNALIGNED_DATA_WITH_STRIDE v16, v17, v18, v19, x0, x1
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsCopy8x16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
LOAD_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD_UNALIGNED_DATA_WITH_STRIDE v4, v5, v6, v7, x2, x3
STORE_UNALIGNED_DATA_WITH_STRIDE v4, v5, v6, v7, x0, x1
LOAD_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x2, x3
STORE_UNALIGNED_DATA_WITH_STRIDE v0, v1, v2, v3, x0, x1
LOAD_UNALIGNED_DATA_WITH_STRIDE v4, v5, v6, v7, x2, x3
STORE_UNALIGNED_DATA_WITH_STRIDE v4, v5, v6, v7, x0, x1
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 101,814 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm64/mc_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.align 4
filter_para: .short 0, 1, -5, 20, 0, 0, 0, 0
.macro FILTER_6TAG_8BITS1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: v18, v19
uaddl v18.8h, \arg0\().8b, \arg5\().8b //v18=src[-2]+src[3]
uaddl v19.8h, \arg2\().8b, \arg3\().8b //src[0]+src[1]
mla v18.8h, v19.8h, \arg7\().8h //v18 += 20*(src[0]+src[1]), 2 cycles
uaddl v19.8h, \arg1\().8b, \arg4\().8b //src[-1]+src[2]
mls v18.8h, v19.8h, \arg8\().8h //v18 -= 5*(src[-1]+src[2]), 2 cycles
sqrshrun \arg6\().8b, v18.8h, #5
// }
.endm
.macro FILTER_6TAG_8BITS2 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: v18, v19
uaddl2 v18.8h, \arg0\().16b, \arg5\().16b //v18=src[-2]+src[3]
uaddl2 v19.8h, \arg2\().16b, \arg3\().16b //src[0]+src[1]
mla v18.8h, v19.8h, \arg7\().8h //v18 += 20*(src[0]+src[1]), 2 cycles
uaddl2 v19.8h, \arg1\().16b, \arg4\().16b //src[-1]+src[2]
mls v18.8h, v19.8h, \arg8\().8h //v18 -= 5*(src[-1]+src[2]), 2 cycles
sqrshrun2 \arg6\().16b, v18.8h, #5
// }
.endm
.macro FILTER_6TAG_8BITS1_AVERAGE_WITH_0 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: v18, v19
uaddl v18.8h, \arg0\().8b, \arg5\().8b //v18=src[-2]+src[3]
uaddl v19.8h, \arg2\().8b, \arg3\().8b //src[0]+src[1]
mla v18.8h, v19.8h, \arg7\().8h //v18 += 20*(src[0]+src[1]), 2 cycles
uaddl v19.8h, \arg1\().8b, \arg4\().8b //src[-1]+src[2]
mls v18.8h, v19.8h, \arg8\().8h //v18 -= 5*(src[-1]+src[2]), 2 cycles
sqrshrun \arg6\().8b, v18.8h, #5
uaddl v19.8h, \arg2\().8b, \arg6\().8b
rshrn \arg6\().8b, v19.8h, #1
// }
.endm
.macro FILTER_6TAG_8BITS2_AVERAGE_WITH_0 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: v18, v19
uaddl2 v18.8h, \arg0\().16b, \arg5\().16b //v18=src[-2]+src[3]
uaddl2 v19.8h, \arg2\().16b, \arg3\().16b //src[0]+src[1]
mla v18.8h, v19.8h, \arg7\().8h //v18 += 20*(src[0]+src[1]), 2 cycles
uaddl2 v19.8h, \arg1\().16b, \arg4\().16b //src[-1]+src[2]
mls v18.8h, v19.8h, \arg8\().8h //v18 -= 5*(src[-1]+src[2]), 2 cycles
sqrshrun2 \arg6\().16b, v18.8h, #5
uaddl2 v19.8h, \arg2\().16b, \arg6\().16b
rshrn2 \arg6\().16b, v19.8h, #1
// }
.endm
.macro FILTER_6TAG_8BITS1_AVERAGE_WITH_1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: v18, v19
uaddl v18.8h, \arg0\().8b, \arg5\().8b //v18=src[-2]+src[3]
uaddl v19.8h, \arg2\().8b, \arg3\().8b //src[0]+src[1]
mla v18.8h, v19.8h, \arg7\().8h //v18 += 20*(src[0]+src[1]), 2 cycles
uaddl v19.8h, \arg1\().8b, \arg4\().8b //src[-1]+src[2]
mls v18.8h, v19.8h, \arg8\().8h //v18 -= 5*(src[-1]+src[2]), 2 cycles
sqrshrun \arg6\().8b, v18.8h, #5
uaddl v19.8h, \arg3\().8b, \arg6\().8b
rshrn \arg6\().8b, v19.8h, #1
// }
.endm
.macro FILTER_6TAG_8BITS2_AVERAGE_WITH_1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:src[-2], src[-1], src[0], src[1], src[2], src[3], dst_d, multiplier a/b; working: v18, v19
uaddl2 v18.8h, \arg0\().16b, \arg5\().16b //v18=src[-2]+src[3]
uaddl2 v19.8h, \arg2\().16b, \arg3\().16b //src[0]+src[1]
mla v18.8h, v19.8h, \arg7\().8h //v18 += 20*(src[0]+src[1]), 2 cycles
uaddl2 v19.8h, \arg1\().16b, \arg4\().16b //src[-1]+src[2]
mls v18.8h, v19.8h, \arg8\().8h //v18 -= 5*(src[-1]+src[2]), 2 cycles
sqrshrun2 \arg6\().16b, v18.8h, #5
uaddl2 v19.8h, \arg3\().16b, \arg6\().16b
rshrn2 \arg6\().16b, v19.8h, #1
// }
.endm
.macro FILTER_6TAG_8BITS_TO_16BITS1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:d_src[-2], d_src[-1], d_src[0], d_src[1], d_src[2], d_src[3], dst_q, multiplier a/b; working:v31
uaddl \arg6\().8h, \arg0\().8b, \arg5\().8b //dst_q=src[-2]+src[3]
uaddl v31.8h, \arg2\().8b, \arg3\().8b //src[0]+src[1]
mla \arg6\().8h, v31.8h, \arg7\().8h //dst_q += 20*(src[0]+src[1]), 2 cycles
uaddl v31.8h, \arg1\().8b, \arg4\().8b //src[-1]+src[2]
mls \arg6\().8h, v31.8h, \arg8\().8h //dst_q -= 5*(src[-1]+src[2]), 2 cycles
// }
.endm
.macro FILTER_6TAG_8BITS_TO_16BITS2 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
// { // input:d_src[-2], d_src[-1], d_src[0], d_src[1], d_src[2], d_src[3], dst_q, multiplier a/b; working:v31
uaddl2 \arg6\().8h, \arg0\().16b, \arg5\().16b //dst_q=src[-2]+src[3]
uaddl2 v31.8h, \arg2\().16b, \arg3\().16b //src[0]+src[1]
mla \arg6\().8h, v31.8h, \arg7\().8h //dst_q += 20*(src[0]+src[1]), 2 cycles
uaddl2 v31.8h, \arg1\().16b, \arg4\().16b //src[-1]+src[2]
mls \arg6\().8h, v31.8h, \arg8\().8h //dst_q -= 5*(src[-1]+src[2]), 2 cycles
// }
.endm
.macro FILTER_3_IN_16BITS_TO_8BITS1 arg0, arg1, arg2, arg3
// { // input:a, b, c, dst_d;
sub \arg0\().8h, \arg0\().8h, \arg1\().8h //a-b
sshr \arg0\().8h, \arg0\().8h, #2 //(a-b)/4
sub \arg0\().8h, \arg0\().8h, \arg1\().8h //(a-b)/4-b
add \arg0\().8h, \arg0\().8h, \arg2\().8h //(a-b)/4-b+c
sshr \arg0\().8h, \arg0\().8h, #2 //((a-b)/4-b+c)/4
add \arg0\().8h, \arg0\().8h, \arg2\().8h //((a-b)/4-b+c)/4+c = (a-5*b+20*c)/16
sqrshrun \arg3\().8b, \arg0\().8h, #6 //(+32)>>6
// }
.endm
.macro FILTER_3_IN_16BITS_TO_8BITS2 arg0, arg1, arg2, arg3
// { // input:a, b, c, dst_d;
sub \arg0\().8h, \arg0\().8h, \arg1\().8h //a-b
sshr \arg0\().8h, \arg0\().8h, #2 //(a-b)/4
sub \arg0\().8h, \arg0\().8h, \arg1\().8h //(a-b)/4-b
add \arg0\().8h, \arg0\().8h, \arg2\().8h //(a-b)/4-b+c
sshr \arg0\().8h, \arg0\().8h, #2 //((a-b)/4-b+c)/4
add \arg0\().8h, \arg0\().8h, \arg2\().8h //((a-b)/4-b+c)/4+c = (a-5*b+20*c)/16
sqrshrun2 \arg3\().16b, \arg0\().8h, #6 //(+32)>>6
// }
.endm
.macro UNPACK_2_16BITS_TO_ABC arg0, arg1, arg2, arg3, arg4
// { // input:q_src[-2:5], q_src[6:13](avail 8+5)/q_src[6:**](avail 4+5), dst_a, dst_b, dst_c;
ext \arg4\().16b, \arg0\().16b, \arg1\().16b, #4 //src[0]
ext \arg3\().16b, \arg0\().16b, \arg1\().16b, #6 //src[1]
add \arg4\().8h, \arg4\().8h, \arg3\().8h //c=src[0]+src[1]
ext \arg3\().16b, \arg0\().16b, \arg1\().16b, #2 //src[-1]
ext \arg2\().16b, \arg0\().16b, \arg1\().16b, #8 //src[2]
add \arg3\().8h, \arg3\().8h, \arg2\().8h //b=src[-1]+src[2]
ext \arg2\().16b, \arg0\().16b, \arg1\().16b, #10 //src[3]
add \arg2\().8h, \arg2\().8h, \arg0\().8h //a=src[-2]+src[3]
// }
.endm
.macro AVERAGE_TWO_8BITS1 arg0, arg1, arg2
// { // input:dst_d, src_d A and B; working: v5
uaddl v30.8h, \arg2\().8b, \arg1\().8b
rshrn \arg0\().8b, v30.8h, #1
// }
.endm
.macro AVERAGE_TWO_8BITS2 arg0, arg1, arg2
// { // input:dst_d, src_d A and B; working: v5
uaddl2 v30.8h, \arg2\().16b, \arg1\().16b
rshrn2 \arg0\().16b, v30.8h, #1
// }
.endm
.macro FILTER_SINGLE_TAG_8BITS arg0, arg1, arg2, arg3
// when width=17/9, used
// { // input: src_d{Y[0][1][2][3][4][5]X},
rev64 \arg2\().8b, \arg0\().8b // X[5][4][3][2][1][0]O
uaddl \arg2\().8h, \arg0\().8b, \arg2\().8b // each 16bits, *[50][41][32][23][14][05]*
mul \arg2\().4h, \arg2\().4h, \arg1\().4h // 0+1*[50]-5*[41]+20[32]
addv \arg3, \arg2\().4h
sqrshrun \arg0\().8b, \arg0\().8h, #5
// }
.endm
.macro UNPACK_FILTER_SINGLE_TAG_16BITS arg0, arg1, arg2, arg3, arg4, arg5
// { // each 16bits; input: d_dst, d_src[0:5], para, working, working, d(low part of d_dst)
ext \arg3\().16b, \arg1\().16b, \arg1\().16b, #14 // X[0][1][2][3][4][5]O
ext \arg4\().16b, \arg3\().16b, \arg3\().16b, #8 // [3][4][5]OX[0][1][2]
rev64 \arg4\().8h, \arg4\().8h // X[5][4][3][2][1][0]O
add \arg3\().8h, \arg3\().8h, \arg4\().8h // each 16bits, *[50][41][32][23][14][05]*
smull \arg3\().4s, \arg3\().4h, \arg2\().4h // 0+1*[50]-5*[41]+20[32]
saddlv \arg5, \arg3\().4s
//sshr \arg0\().2d, \arg0\().2d, #4
sqrshrun \arg0\().2s, \arg0\().2d, #10
uqxtn \arg0\().4h, \arg0\().4s
uqxtn \arg0\().8b, \arg0\().8h
// }
.endm
.macro VEC4_LD1_8BITS_16ELEMENT arg0, arg1, arg2, arg3, arg4, arg5
//{//load 16bytes * 4rows
ld1 {\arg2\().16b}, [\arg0], \arg1
ld1 {\arg3\().16b}, [\arg0], \arg1
ld1 {\arg4\().16b}, [\arg0], \arg1
ld1 {\arg5\().16b}, [\arg0], \arg1
//}
.endm
.macro VEC4_ST1_8BITS_8ELEMENT arg0, arg1, arg2, arg3, arg4, arg5
//{
st1 {\arg2\().8b}, [\arg0], \arg1
st1 {\arg3\().8b}, [\arg0], \arg1
st1 {\arg4\().8b}, [\arg0], \arg1
st1 {\arg5\().8b}, [\arg0], \arg1
//}
.endm
.macro VEC4_UADDL_8BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11
//{
uaddl \arg8\().8h, \arg0\().8b, \arg1\().8b
uaddl \arg9\().8h, \arg2\().8b, \arg3\().8b
uaddl \arg10\().8h, \arg4\().8b, \arg5\().8b
uaddl \arg11\().8h, \arg6\().8b, \arg7\().8b
//}
.endm
.macro VEC4_UADDL2_8BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11
//{
uaddl \arg8\().8h, \arg0\().16b, \arg1\().16b
uaddl \arg9\().8h, \arg2\().16b, \arg3\().16b
uaddl \arg10\().8h, \arg4\().16b, \arg5\().16b
uaddl \arg11\().8h, \arg6\().16b, \arg7\().16b
//}
.endm
.macro VEC4_MLS_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11
//{
mls \arg8\().8h, \arg0\().8h, \arg1\().8h
mls \arg9\().8h, \arg2\().8h, \arg3\().8h
mls \arg10\().8h, \arg4\().8h, \arg5\().8h
mls \arg11\().8h, \arg6\().8h, \arg7\().8h
//}
.endm
.macro VEC4_MLA_16BITS arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11
//{
mla \arg8\().8h, \arg0\().8h, \arg1\().8h
mla \arg9\().8h, \arg2\().8h, \arg3\().8h
mla \arg10\().8h, \arg4\().8h, \arg5\().8h
mla \arg11\().8h, \arg6\().8h, \arg7\().8h
//}
.endm
.macro VEC4_SQRSHRUN_16BITS_SHIFT5 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
//{
sqrshrun \arg4\().8b, \arg0\().8h, #5
sqrshrun \arg5\().8b, \arg1\().8h, #5
sqrshrun \arg6\().8b, \arg2\().8h, #5
sqrshrun \arg7\().8b, \arg3\().8h, #5
//}
.endm
.macro VEC4_SQRSHRUN2_16BITS_SHIFT5 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
//{
sqrshrun2 \arg4\().16b, \arg0\().8h, #5
sqrshrun2 \arg5\().16b, \arg1\().8h, #5
sqrshrun2 \arg6\().16b, \arg2\().8h, #5
sqrshrun2 \arg7\().16b, \arg3\().8h, #5
//}
.endm
.macro VEC4_RSHRN_16BITS_SHIFT1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
//{
rshrn \arg4\().8b, \arg0\().8h, #1
rshrn \arg5\().8b, \arg1\().8h, #1
rshrn \arg6\().8b, \arg2\().8h, #1
rshrn \arg7\().8b, \arg3\().8h, #1
//}
.endm
//(const uint8_t* pSrc {x0}, int32_t iSrcStride{x1}, uint8_t* pDst{x2}, int32_t iDstStride{x3}, int32_t iHeight{x4})
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer20WidthEq16_AArch64_neon
sub x0, x0, #2
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w16_h_mc_luma_loop:
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 //only use 21(16+5); v2=src[-2]
trn1 v2.2d, v2.2d, v3.2d
//prfm pldl1strm, [x0]
ext v5.16b, v2.16b, v4.16b, #1 //v5=src[-1]
ext v6.16b, v2.16b, v4.16b, #2 //v6=src[0]
ext v7.16b, v2.16b, v4.16b, #3 //v7=src[1]
ext v16.16b, v2.16b, v4.16b, #4 //v16=src[2]
ext v17.16b, v2.16b, v4.16b, #5 //v17=src[3]
FILTER_6TAG_8BITS1 v2, v5, v6, v7, v16, v17, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v5, v6, v7, v16, v17, v20, v0, v1
sub x4, x4, #1
st1 {v20.16b}, [x2], x3 //write 16Byte
cbnz x4, w16_h_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer20WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer20WidthEq8_AArch64_neon
sub x0, x0, #2
stp d8,d9, [sp,#-16]!
movi v8.8h, #20, lsl #0
movi v9.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w8_h_mc_luma_loop:
VEC4_LD1_8BITS_16ELEMENT x0, x1, v16, v20, v24, v28 //load src[-2] in v16,v20,v24,v28 for 4 row; only use 13(8+5);
sub x4, x4, #4
//1st row:
ext v17.16b, v16.16b, v16.16b, #5 //src[3]
ext v18.16b, v16.16b, v16.16b, #1 //src[-1]
ext v19.16b, v16.16b, v16.16b, #4 //src[2]
//2nd row:
ext v21.16b, v20.16b, v20.16b, #5 //src[3]
ext v22.16b, v20.16b, v20.16b, #1 //src[-1]
ext v23.16b, v20.16b, v20.16b, #4 //src[2]
//3rd row:
ext v25.16b, v24.16b, v24.16b, #5 //src[3]
ext v26.16b, v24.16b, v24.16b, #1 //src[-1]
ext v27.16b, v24.16b, v24.16b, #4 //src[2]
//4th row:
ext v29.16b, v28.16b, v28.16b, #5 //src[3]
ext v30.16b, v28.16b, v28.16b, #1 //src[-1]
ext v31.16b, v28.16b, v28.16b, #4 //src[2]
VEC4_UADDL_8BITS v16, v17, v20, v21, v24, v25, v28, v29, v0, v2, v4, v6 //v0/v2/v4/v6=src[-2]+src[3]
VEC4_UADDL_8BITS v18, v19, v22, v23, v26, v27, v30, v31, v1, v3, v5, v7 //v1/v3/v5/v7=src[-1]+src[2]
VEC4_MLS_16BITS v1, v9, v3, v9, v5, v9, v7, v9, v0, v2, v4, v6 //v0/v2/v4/v6 -= 5*(src[-1]+src[2])
//1st row:
ext v18.16b, v16.16b, v16.16b, #2 //src[0]
ext v19.16b, v16.16b, v16.16b, #3 //src[1]
//2nd row:
ext v22.16b, v20.16b, v20.16b, #2 //src[0]
ext v23.16b, v20.16b, v20.16b, #3 //src[1]
//3rd row:
ext v26.16b, v24.16b, v24.16b, #2 //src[0]
ext v27.16b, v24.16b, v24.16b, #3 //src[1]
//4th row:
ext v30.16b, v28.16b, v28.16b, #2 //src[0]
ext v31.16b, v28.16b, v28.16b, #3 //src[1]
VEC4_UADDL_8BITS v18, v19, v22, v23, v26, v27, v30, v31, v1, v3, v5, v7 //v1/v3/v5/v7=src[0]+src[1]
VEC4_MLA_16BITS v1, v8, v3, v8, v5, v8, v7, v8, v0, v2, v4, v6 //v0/v2/v4/v6+=20*(src[0]+src[1])
VEC4_SQRSHRUN_16BITS_SHIFT5 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_ST1_8BITS_8ELEMENT x2, x3, v1, v3, v5, v7
cbnz x4, w8_h_mc_luma_loop
ldp d8,d9,[sp],#16
WELS_ASM_AARCH64_FUNC_END
//void McHorVer20WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer20WidthEq4_AArch64_neon
sub x0, x0, #2
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
asr x4, x4, #1
w4_h_mc_luma_loop:
ld1 {v2.16b}, [x0], x1 //only use 9(4+5); 1st row src[-2:6]
//prfm pldl1strm, [x0]
ld1 {v3.16b}, [x0], x1 //only use 9(4+5); 2nd row src[-2:6]
//prfm pldl1strm, [x0]
zip1 v4.4s, v2.4s, v3.4s // v4=src[-2] 1st:2nd
ext v17.16b, v4.16b, v4.16b, #8 // v17=src[2:5] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[-1:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[-1:6]
zip1 v5.4s, v2.4s, v3.4s // v5=src[-1:2] 1st:2nd
ext v7.16b, v5.16b, v4.16b, #8 //v7=src[3:6] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[0:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[0:6]
zip1 v6.4s, v2.4s, v3.4s // v6=src[0:3] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[1:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[1:6]
zip1 v16.4s, v2.4s, v3.4s // v16=src[1:4] 1st:2nd
FILTER_6TAG_8BITS1 v4, v5, v6, v16, v17, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte
st1 {v20.s}[1], [x2], x3 //write 4Byte
sub x4, x4, #1
cbnz x4, w4_h_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer10WidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer10WidthEq16_AArch64_neon
sub x0, x0, #2
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w16_xy_10_mc_luma_loop:
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 //only use 21(16+5); v2=src[-2]
trn1 v2.2d, v2.2d, v3.2d
//prfm pldl1strm, [x0]
ext v5.16b, v2.16b, v4.16b, #1 //v5=src[-1]
ext v6.16b, v2.16b, v4.16b, #2 //v6=src[0]
ext v7.16b, v2.16b, v4.16b, #3 //v7=src[1]
ext v16.16b, v2.16b, v4.16b, #4 //v16=src[2]
ext v17.16b, v2.16b, v4.16b, #5 //v17=src[3]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v2, v5, v6, v7, v16, v17, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v2, v5, v6, v7, v16, v17, v20, v0, v1
sub x4, x4, #1
st1 {v20.16b}, [x2], x3 //write 16Byte
cbnz x4, w16_xy_10_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer10WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer10WidthEq8_AArch64_neon
sub x0, x0, #2
stp d8,d9, [sp,#-16]!
movi v8.8h, #20, lsl #0
movi v9.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w8_xy_10_mc_luma_loop:
VEC4_LD1_8BITS_16ELEMENT x0, x1, v16, v20, v24, v28 //load src[-2] in v16,v20,v24,v28 for 4 row; only use 13(8+5);
sub x4, x4, #4
//1st row:
ext v17.16b, v16.16b, v16.16b, #5 //src[3]
ext v18.16b, v16.16b, v16.16b, #1 //src[-1]
ext v19.16b, v16.16b, v16.16b, #4 //src[2]
//2nd row:
ext v21.16b, v20.16b, v20.16b, #5 //src[3]
ext v22.16b, v20.16b, v20.16b, #1 //src[-1]
ext v23.16b, v20.16b, v20.16b, #4 //src[2]
//3rd row:
ext v25.16b, v24.16b, v24.16b, #5 //src[3]
ext v26.16b, v24.16b, v24.16b, #1 //src[-1]
ext v27.16b, v24.16b, v24.16b, #4 //src[2]
//4th row:
ext v29.16b, v28.16b, v28.16b, #5 //src[3]
ext v30.16b, v28.16b, v28.16b, #1 //src[-1]
ext v31.16b, v28.16b, v28.16b, #4 //src[2]
VEC4_UADDL_8BITS v16, v17, v20, v21, v24, v25, v28, v29, v0, v2, v4, v6 //v0/v2/v4/v6=src[-2]+src[3]
VEC4_UADDL_8BITS v18, v19, v22, v23, v26, v27, v30, v31, v1, v3, v5, v7 //v1/v3/v5/v7=src[-1]+src[2]
VEC4_MLS_16BITS v1, v9, v3, v9, v5, v9, v7, v9, v0, v2, v4, v6 //v0/v2/v4/v6 -= 5*(src[-1]+src[2])
//1st row:
ext v18.16b, v16.16b, v16.16b, #2 //src[0]
ext v19.16b, v16.16b, v16.16b, #3 //src[1]
//2nd row:
ext v22.16b, v20.16b, v20.16b, #2 //src[0]
ext v23.16b, v20.16b, v20.16b, #3 //src[1]
//3rd row:
ext v26.16b, v24.16b, v24.16b, #2 //src[0]
ext v27.16b, v24.16b, v24.16b, #3 //src[1]
//4th row:
ext v30.16b, v28.16b, v28.16b, #2 //src[0]
ext v31.16b, v28.16b, v28.16b, #3 //src[1]
VEC4_UADDL_8BITS v18, v19, v22, v23, v26, v27, v30, v31, v1, v3, v5, v7 //v1/v3/v5/v7=src[0]+src[1]
VEC4_MLA_16BITS v1, v8, v3, v8, v5, v8, v7, v8, v0, v2, v4, v6 //v0/v2/v4/v6+=20*(src[0]+src[1])
VEC4_SQRSHRUN_16BITS_SHIFT5 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_UADDL_8BITS v1, v18, v3, v22, v5, v26, v7, v30, v0, v2, v4, v6 //average with arc[0]
VEC4_RSHRN_16BITS_SHIFT1 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_ST1_8BITS_8ELEMENT x2, x3, v1, v3, v5, v7
cbnz x4, w8_xy_10_mc_luma_loop
ldp d8,d9,[sp],#16
WELS_ASM_AARCH64_FUNC_END
//void McHorVer10WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer10WidthEq4_AArch64_neon
sub x0, x0, #2
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
asr x4, x4, #1
w4_xy_10_mc_luma_loop:
ld1 {v2.16b}, [x0], x1 //only use 9(4+5); 1st row src[-2:6]
//prfm pldl1strm, [x0]
ld1 {v3.16b}, [x0], x1 //only use 9(4+5); 2nd row src[-2:6]
//prfm pldl1strm, [x0]
zip1 v4.4s, v2.4s, v3.4s // v4=src[-2] 1st:2nd
ext v17.16b, v4.16b, v4.16b, #8 // v17=src[2:5] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[-1:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[-1:6]
zip1 v5.4s, v2.4s, v3.4s // v5=src[-1:2] 1st:2nd
ext v7.16b, v5.16b, v4.16b, #8 //v7=src[3:6] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[0:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[0:6]
zip1 v6.4s, v2.4s, v3.4s // v6=src[0:3] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[1:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[1:6]
zip1 v16.4s, v2.4s, v3.4s // v16=src[1:4] 1st:2nd
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v4, v5, v6, v16, v17, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte
st1 {v20.s}[1], [x2], x3 //write 4Byte
sub x4, x4, #1
cbnz x4, w4_xy_10_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer30WidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer30WidthEq16_AArch64_neon
sub x0, x0, #2
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w16_xy_30_mc_luma_loop:
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 //only use 21(16+5); v2=src[-2]
trn1 v2.2d, v2.2d, v3.2d
//prfm pldl1strm, [x0]
ext v5.16b, v2.16b, v4.16b, #1 //v5=src[-1]
ext v6.16b, v2.16b, v4.16b, #2 //v6=src[0]
ext v7.16b, v2.16b, v4.16b, #3 //v7=src[1]
ext v16.16b, v2.16b, v4.16b, #4 //v16=src[2]
ext v17.16b, v2.16b, v4.16b, #5 //v17=src[3]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v2, v5, v6, v7, v16, v17, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v2, v5, v6, v7, v16, v17, v20, v0, v1
sub x4, x4, #1
st1 {v20.16b}, [x2], x3 //write 16Byte
cbnz x4, w16_xy_30_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer30WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer30WidthEq8_AArch64_neon
sub x0, x0, #2
stp d8,d9, [sp,#-16]!
movi v8.8h, #20, lsl #0
movi v9.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w8_xy_30_mc_luma_loop:
VEC4_LD1_8BITS_16ELEMENT x0, x1, v16, v20, v24, v28 //load src[-2] in v16,v20,v24,v28 for 4 row; only use 13(8+5);
sub x4, x4, #4
//1st row:
ext v17.16b, v16.16b, v16.16b, #5 //src[3]
ext v18.16b, v16.16b, v16.16b, #1 //src[-1]
ext v19.16b, v16.16b, v16.16b, #4 //src[2]
//2nd row:
ext v21.16b, v20.16b, v20.16b, #5 //src[3]
ext v22.16b, v20.16b, v20.16b, #1 //src[-1]
ext v23.16b, v20.16b, v20.16b, #4 //src[2]
//3rd row:
ext v25.16b, v24.16b, v24.16b, #5 //src[3]
ext v26.16b, v24.16b, v24.16b, #1 //src[-1]
ext v27.16b, v24.16b, v24.16b, #4 //src[2]
//4th row:
ext v29.16b, v28.16b, v28.16b, #5 //src[3]
ext v30.16b, v28.16b, v28.16b, #1 //src[-1]
ext v31.16b, v28.16b, v28.16b, #4 //src[2]
VEC4_UADDL_8BITS v16, v17, v20, v21, v24, v25, v28, v29, v0, v2, v4, v6 //v0/v2/v4/v6=src[-2]+src[3]
VEC4_UADDL_8BITS v18, v19, v22, v23, v26, v27, v30, v31, v1, v3, v5, v7 //v1/v3/v5/v7=src[-1]+src[2]
VEC4_MLS_16BITS v1, v9, v3, v9, v5, v9, v7, v9, v0, v2, v4, v6 //v0/v2/v4/v6 -= 5*(src[-1]+src[2])
//1st row:
ext v18.16b, v16.16b, v16.16b, #2 //src[0]
ext v19.16b, v16.16b, v16.16b, #3 //src[1]
//2nd row:
ext v22.16b, v20.16b, v20.16b, #2 //src[0]
ext v23.16b, v20.16b, v20.16b, #3 //src[1]
//3rd row:
ext v26.16b, v24.16b, v24.16b, #2 //src[0]
ext v27.16b, v24.16b, v24.16b, #3 //src[1]
//4th row:
ext v30.16b, v28.16b, v28.16b, #2 //src[0]
ext v31.16b, v28.16b, v28.16b, #3 //src[1]
VEC4_UADDL_8BITS v18, v19, v22, v23, v26, v27, v30, v31, v1, v3, v5, v7 //v1/v3/v5/v7=src[0]+src[1]
VEC4_MLA_16BITS v1, v8, v3, v8, v5, v8, v7, v8, v0, v2, v4, v6 //v0/v2/v4/v6+=20*(src[0]+src[1])
VEC4_SQRSHRUN_16BITS_SHIFT5 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_UADDL_8BITS v1, v19, v3, v23, v5, v27, v7, v31, v0, v2, v4, v6 //average with arc[0]
VEC4_RSHRN_16BITS_SHIFT1 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_ST1_8BITS_8ELEMENT x2, x3, v1, v3, v5, v7
cbnz x4, w8_xy_30_mc_luma_loop
ldp d8,d9,[sp],#16
WELS_ASM_AARCH64_FUNC_END
//void McHorVer30WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer30WidthEq4_AArch64_neon
sub x0, x0, #2
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
asr x4, x4, #1
w4_xy_30_mc_luma_loop:
ld1 {v2.16b}, [x0], x1 //only use 9(4+5); 1st row src[-2:6]
//prfm pldl1strm, [x0]
ld1 {v3.16b}, [x0], x1 //only use 9(4+5); 2nd row src[-2:6]
//prfm pldl1strm, [x0]
zip1 v4.4s, v2.4s, v3.4s // v4=src[-2] 1st:2nd
ext v17.16b, v4.16b, v4.16b, #8 // v17=src[2:5] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[-1:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[-1:6]
zip1 v5.4s, v2.4s, v3.4s // v5=src[-1:2] 1st:2nd
ext v7.16b, v5.16b, v4.16b, #8 //v7=src[3:6] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[0:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[0:6]
zip1 v6.4s, v2.4s, v3.4s // v6=src[0:3] 1st:2nd
ext v2.16b, v2.16b, v4.16b, #1 //1st row src[1:6]
ext v3.16b, v3.16b, v4.16b, #1 //2nd row src[1:6]
zip1 v16.4s, v2.4s, v3.4s // v16=src[1:4] 1st:2nd
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v4, v5, v6, v16, v17, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte
st1 {v20.s}[1], [x2], x3 //write 4Byte
sub x4, x4, #1
cbnz x4, w4_xy_30_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer01WidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer01WidthEq16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[2*stride]
w16_xy_01_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v5, v6, v7, v2, v3, v4, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 3 line
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v6, v7, v2, v3, v4, v5, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v6, v7, v2, v3, v4, v5, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 4 line
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v7, v2, v3, v4, v5, v6, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v7, v2, v3, v4, v5, v6, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 5 line
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 6 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_0 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 7 line
mov v3.16b, v5.16b
mov v5.16b, v7.16b
mov v7.16b, v2.16b
mov v2.16b, v4.16b
mov v4.16b, v6.16b
mov v6.16b, v7.16b
sub x4, x4, #8
cbnz x4, w16_xy_01_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer01WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer01WidthEq8_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v30.8h, #20, lsl #0
movi v31.8h, #5, lsl #0
ld1 {v16.8b}, [x0], x1 // v16=src[-2*stride]
ld1 {v17.8b}, [x0], x1 // v17=src[-1*stride]
ld1 {v18.8b}, [x0], x1 // v18=src[0*stride]
ld1 {v19.8b}, [x0], x1 // v19=src[1*stride]
ld1 {v20.8b}, [x0], x1 // v20=src[2*stride]
w8_xy_01_mc_luma_loop:
ld1 {v21.8b}, [x0], x1 // v21=src[3*stride]
ld1 {v22.8b}, [x0], x1 // v22=src[4*stride]
ld1 {v23.8b}, [x0], x1 // v23=src[5*stride]
ld1 {v24.8b}, [x0], x1 // v24=src[6*stride]
VEC4_UADDL_8BITS v16, v21, v17, v22, v18, v23, v19, v24, v0, v2, v4, v6 //v0/v2/v4/v6 =src[-2]+src[3]
VEC4_UADDL_8BITS v17, v20, v18, v21, v19, v22, v20, v23, v1, v3, v5, v7 //v1/v3/v5/v7 =src[-1]+src[2]
VEC4_MLS_16BITS v1, v31, v3, v31, v5, v31, v7, v31, v0, v2, v4, v6 //v0/v2/v4/v6 -=5*(src[-1]+src[2])
VEC4_UADDL_8BITS v18, v19, v19, v20, v20, v21, v21, v22, v1, v3, v5, v7 //v1/v3/v5/v7 =src[0]+src[1]
VEC4_MLA_16BITS v1, v30, v3, v30, v5, v30, v7, v30, v0, v2, v4, v6 //v0/v2/v4/v6 += 20*(src[0]+src[1])
VEC4_SQRSHRUN_16BITS_SHIFT5 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_UADDL_8BITS v1, v18, v3, v19, v5, v20, v7, v21, v0, v2, v4, v6 //v0/v2/v4/v6 = average with src[0]
VEC4_RSHRN_16BITS_SHIFT1 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_ST1_8BITS_8ELEMENT x2, x3, v1, v3, v5, v7 //store 8bytes*4row
sub x4, x4, #4
mov v16.16b, v20.16b
mov v17.16b, v21.16b
mov v18.16b, v22.16b
mov v19.16b, v23.16b
mov v20.16b, v24.16b
cbnz x4, w8_xy_01_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer01WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer01WidthEq4_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.s}[0], [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.s}[0], [x0], x1 // v3=src[-1*stride]
mov v2.s[1], v3.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v4.s}[0], [x0], x1 // v4=src[0*stride]
mov v3.s[1], v4.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v5.s}[0], [x0], x1 // v5=src[1*stride]
mov v4.s[1], v5.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v6.s}[0], [x0], x1 // v6=src[2*stride]
mov v5.s[1], v6.s[0]
w4_xy_01_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.s}[0], [x0], x1 // v7=src[3*stride]
mov v6.s[1], v7.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v7.s}[1], [x0], x1 // v7=src[4*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 0 line
st1 {v20.s}[1], [x2], x3 //write 4Byte : 1 line
mov v2.s[0], v7.s[1]
//prfm pldl1strm, [x0, x1]
ld1 {v2.s}[1], [x0], x1 // v2=src[5*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.s}[1], [x0], x1 // v2=src[6*stride]
mov v3.s[0], v2.s[1]
FILTER_6TAG_8BITS1_AVERAGE_WITH_0 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 2 line
st1 {v20.s}[1], [x2], x3 //write 4Byte : 3 line
mov v4.s[0], v3.s[1]
mov v21.8b, v6.8b
mov v6.8b, v4.8b
mov v4.8b, v2.8b
mov v2.8b, v21.8b
mov v21.8b, v3.8b
mov v3.8b, v7.8b
mov v7.8b, v5.8b
mov v5.8b, v21.8b
sub x4, x4, #4
cbnz x4, w4_xy_01_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer03WidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer03WidthEq16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[2*stride]
w16_xy_03_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v5, v6, v7, v2, v3, v4, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 3 line
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v6, v7, v2, v3, v4, v5, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v6, v7, v2, v3, v4, v5, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 4 line
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v7, v2, v3, v4, v5, v6, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v7, v2, v3, v4, v5, v6, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 5 line
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 6 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2_AVERAGE_WITH_1 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 7 line
mov v3.16b, v5.16b
mov v5.16b, v7.16b
mov v7.16b, v2.16b
mov v2.16b, v4.16b
mov v4.16b, v6.16b
mov v6.16b, v7.16b
sub x4, x4, #8
cbnz x4, w16_xy_03_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer03WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer03WidthEq8_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v30.8h, #20, lsl #0
movi v31.8h, #5, lsl #0
ld1 {v16.8b}, [x0], x1 // v16=src[-2*stride]
ld1 {v17.8b}, [x0], x1 // v17=src[-1*stride]
ld1 {v18.8b}, [x0], x1 // v18=src[0*stride]
ld1 {v19.8b}, [x0], x1 // v19=src[1*stride]
ld1 {v20.8b}, [x0], x1 // v20=src[2*stride]
w8_xy_03_mc_luma_loop:
ld1 {v21.8b}, [x0], x1 // v21=src[3*stride]
ld1 {v22.8b}, [x0], x1 // v22=src[4*stride]
ld1 {v23.8b}, [x0], x1 // v23=src[5*stride]
ld1 {v24.8b}, [x0], x1 // v24=src[6*stride]
VEC4_UADDL_8BITS v16, v21, v17, v22, v18, v23, v19, v24, v0, v2, v4, v6 //v0/v2/v4/v6 =src[-2]+src[3]
VEC4_UADDL_8BITS v17, v20, v18, v21, v19, v22, v20, v23, v1, v3, v5, v7 //v1/v3/v5/v7 =src[-1]+src[2]
VEC4_MLS_16BITS v1, v31, v3, v31, v5, v31, v7, v31, v0, v2, v4, v6 //v0/v2/v4/v6 -=5*(src[-1]+src[2])
VEC4_UADDL_8BITS v18, v19, v19, v20, v20, v21, v21, v22, v1, v3, v5, v7 //v1/v3/v5/v7 =src[0]+src[1]
VEC4_MLA_16BITS v1, v30, v3, v30, v5, v30, v7, v30, v0, v2, v4, v6 //v0/v2/v4/v6 += 20*(src[0]+src[1])
VEC4_SQRSHRUN_16BITS_SHIFT5 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_UADDL_8BITS v1, v19, v3, v20, v5, v21, v7, v22, v0, v2, v4, v6 //v0/v2/v4/v6 = average with src[0]
VEC4_RSHRN_16BITS_SHIFT1 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_ST1_8BITS_8ELEMENT x2, x3, v1, v3, v5, v7 //store 8bytes*4row
sub x4, x4, #4
mov v16.16b, v20.16b
mov v17.16b, v21.16b
mov v18.16b, v22.16b
mov v19.16b, v23.16b
mov v20.16b, v24.16b
cbnz x4, w8_xy_03_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer03WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer03WidthEq4_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.s}[0], [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.s}[0], [x0], x1 // v3=src[-1*stride]
mov v2.s[1], v3.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v4.s}[0], [x0], x1 // v4=src[0*stride]
mov v3.s[1], v4.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v5.s}[0], [x0], x1 // v5=src[1*stride]
mov v4.s[1], v5.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v6.s}[0], [x0], x1 // v6=src[2*stride]
mov v5.s[1], v6.s[0]
w4_xy_03_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.s}[0], [x0], x1 // v7=src[3*stride]
mov v6.s[1], v7.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v7.s}[1], [x0], x1 // v7=src[4*stride]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 0 line
st1 {v20.s}[1], [x2], x3 //write 4Byte : 1 line
mov v2.s[0], v7.s[1]
//prfm pldl1strm, [x0, x1]
ld1 {v2.s}[1], [x0], x1 // v2=src[5*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.s}[1], [x0], x1 // v2=src[6*stride]
mov v3.s[0], v2.s[1]
FILTER_6TAG_8BITS1_AVERAGE_WITH_1 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 2 line
st1 {v20.s}[1], [x2], x3 //write 4Byte : 3 line
mov v4.s[0], v3.s[1]
mov v21.8b, v6.8b
mov v6.8b, v4.8b
mov v4.8b, v2.8b
mov v2.8b, v21.8b
mov v21.8b, v3.8b
mov v3.8b, v7.8b
mov v7.8b, v5.8b
mov v5.8b, v21.8b
sub x4, x4, #4
cbnz x4, w4_xy_03_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer02WidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer02WidthEq16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[2*stride]
w16_xy_02_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
FILTER_6TAG_8BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[3*stride]
FILTER_6TAG_8BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS2 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[3*stride]
FILTER_6TAG_8BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS2 v5, v6, v7, v2, v3, v4, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 3 line
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[3*stride]
FILTER_6TAG_8BITS1 v6, v7, v2, v3, v4, v5, v20, v0, v1
FILTER_6TAG_8BITS2 v6, v7, v2, v3, v4, v5, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 4 line
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[3*stride]
FILTER_6TAG_8BITS1 v7, v2, v3, v4, v5, v6, v20, v0, v1
FILTER_6TAG_8BITS2 v7, v2, v3, v4, v5, v6, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 5 line
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 6 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
FILTER_6TAG_8BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 7 line
mov v3.16b, v5.16b
mov v5.16b, v7.16b
mov v7.16b, v2.16b
mov v2.16b, v4.16b
mov v4.16b, v6.16b
mov v6.16b, v7.16b
sub x4, x4, #8
cbnz x4, w16_xy_02_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer02WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer02WidthEq8_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v30.8h, #20, lsl #0
movi v31.8h, #5, lsl #0
ld1 {v16.8b}, [x0], x1 // v16=src[-2*stride]
ld1 {v17.8b}, [x0], x1 // v17=src[-1*stride]
ld1 {v18.8b}, [x0], x1 // v18=src[0*stride]
ld1 {v19.8b}, [x0], x1 // v19=src[1*stride]
ld1 {v20.8b}, [x0], x1 // v20=src[2*stride]
w8_xy_02_mc_luma_loop:
ld1 {v21.8b}, [x0], x1 // v21=src[3*stride]
ld1 {v22.8b}, [x0], x1 // v22=src[4*stride]
ld1 {v23.8b}, [x0], x1 // v23=src[5*stride]
ld1 {v24.8b}, [x0], x1 // v24=src[6*stride]
VEC4_UADDL_8BITS v16, v21, v17, v22, v18, v23, v19, v24, v0, v2, v4, v6 //v0/v2/v4/v6 =src[-2]+src[3]
VEC4_UADDL_8BITS v17, v20, v18, v21, v19, v22, v20, v23, v1, v3, v5, v7 //v1/v3/v5/v7 =src[-1]+src[2]
VEC4_MLS_16BITS v1, v31, v3, v31, v5, v31, v7, v31, v0, v2, v4, v6 //v0/v2/v4/v6 -=5*(src[-1]+src[2])
VEC4_UADDL_8BITS v18, v19, v19, v20, v20, v21, v21, v22, v1, v3, v5, v7 //v1/v3/v5/v7 =src[0]+src[1]
VEC4_MLA_16BITS v1, v30, v3, v30, v5, v30, v7, v30, v0, v2, v4, v6 //v0/v2/v4/v6 += 20*(src[0]+src[1])
VEC4_SQRSHRUN_16BITS_SHIFT5 v0, v2, v4, v6, v1, v3, v5, v7
VEC4_ST1_8BITS_8ELEMENT x2, x3, v1, v3, v5, v7 //store 8bytes*4row
sub x4, x4, #4
mov v16.16b, v20.16b
mov v17.16b, v21.16b
mov v18.16b, v22.16b
mov v19.16b, v23.16b
mov v20.16b, v24.16b
cbnz x4, w8_xy_02_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer02WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer02WidthEq4_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.s}[0], [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.s}[0], [x0], x1 // v3=src[-1*stride]
mov v2.s[1], v3.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v4.s}[0], [x0], x1 // v4=src[0*stride]
mov v3.s[1], v4.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v5.s}[0], [x0], x1 // v5=src[1*stride]
mov v4.s[1], v5.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v6.s}[0], [x0], x1 // v6=src[2*stride]
mov v5.s[1], v6.s[0]
w4_xy_02_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.s}[0], [x0], x1 // v7=src[3*stride]
mov v6.s[1], v7.s[0]
//prfm pldl1strm, [x0, x1]
ld1 {v7.s}[1], [x0], x1 // v7=src[4*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 0 line
st1 {v20.s}[1], [x2], x3 //write 4Byte : 1 line
mov v2.s[0], v7.s[1]
//prfm pldl1strm, [x0, x1]
ld1 {v2.s}[1], [x0], x1 // v2=src[5*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.s}[1], [x0], x1 // v2=src[6*stride]
mov v3.s[0], v2.s[1]
FILTER_6TAG_8BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 2 line
st1 {v20.s}[1], [x2], x3 //write 4Byte : 3 line
mov v4.s[0], v3.s[1]
mov v21.8b, v6.8b
mov v6.8b, v4.8b
mov v4.8b, v2.8b
mov v2.8b, v21.8b
mov v21.8b, v3.8b
mov v3.8b, v7.8b
mov v7.8b, v5.8b
mov v5.8b, v21.8b
sub x4, x4, #4
cbnz x4, w4_xy_02_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer22WidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer22WidthEq16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
stp d8, d9, [sp,#-16]!
stp d10, d11, [sp,#-16]!
stp d12, d13, [sp,#-16]!
stp d14, d15, [sp,#-16]!
sub x0, x0, #2
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.8b, v6.8b, v7.8b}, [x0], x1 // v5=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v8.8b, v9.8b, v10.8b}, [x0], x1 // v8=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v11.8b, v12.8b, v13.8b}, [x0], x1 // v11=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v14.8b, v15.8b, v16.8b}, [x0], x1 // v14=src[2*stride]
w16_hv_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v17.8b, v18.8b, v19.8b}, [x0], x1 // v17=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v5, v8, v11, v14, v17, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v3, v6, v9, v12, v15, v18, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v4, v7, v10, v13, v16, v19, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v8, v11, v14, v17, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v6, v9, v12, v15, v18, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v7, v10, v13, v16, v19, v4, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v5.8b, v6.8b, v7.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v8, v11, v14, v17, v2, v5, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v9, v12, v15, v18, v3, v6, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v10, v13, v16, v19, v4, v7, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v8.8b, v9.8b, v10.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v11, v14, v17, v2, v5, v8, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v12, v15, v18, v3, v6, v9, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v13, v16, v19, v4, v7, v10, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 3 line
//prfm pldl1strm, [x0, x1]
ld1 {v11.8b, v12.8b, v13.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v14, v17, v2, v5, v8, v11, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v15, v18, v3, v6, v9, v12, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v16, v19, v4, v7, v10, v13, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 4 line
//prfm pldl1strm, [x0, x1]
ld1 {v14.8b, v15.8b, v16.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v17, v2, v5, v8, v11, v14, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v18, v3, v6, v9, v12, v15, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v19, v4, v7, v10, v13, v16, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 5 line
//prfm pldl1strm, [x0, x1]
ld1 {v17.8b, v18.8b, v19.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v5, v8, v11, v14, v17, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v3, v6, v9, v12, v15, v18, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v4, v7, v10, v13, v16, v19, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 6 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v8, v11, v14, v17, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v6, v9, v12, v15, v18, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v7, v10, v13, v16, v19, v4, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x3 //write 16Byte : 7 line
mov v5.16b, v11.16b
mov v11.16b, v17.16b
mov v30.16b, v2.16b
mov v2.16b, v8.16b
mov v8.16b, v14.16b
mov v14.16b, v30.16b
mov v6.16b, v12.16b
mov v12.16b, v18.16b
mov v30.16b, v3.16b
mov v3.16b, v9.16b
mov v9.16b, v15.16b
mov v15.16b, v30.16b
mov v7.16b, v13.16b
mov v13.16b, v19.16b
mov v30.16b, v4.16b
mov v4.16b, v10.16b
mov v10.16b, v16.16b
mov v16.16b, v30.16b
sub x4, x4, #8
cbnz x4, w16_hv_mc_luma_loop
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
WELS_ASM_AARCH64_FUNC_END
//void McHorVer22WidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer22WidthEq8_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v5=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v8=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v11=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v14=src[2*stride]
w8_hv_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v2, v3, v4, v5, v6, v7, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x3 //write 8Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v3, v4, v5, v6, v7, v2, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x3 //write 8Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v4, v5, v6, v7, v2, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x3 //write 8Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v5, v6, v7, v2, v3, v4, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x3 //write 8Byte : 3 line
mov v5.16b, v3.16b
mov v3.16b, v7.16b
mov v30.16b, v2.16b
mov v2.16b, v6.16b
mov v6.16b, v4.16b
mov v4.16b, v30.16b
sub x4, x4, #4
cbnz x4, w8_hv_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer22WidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer22WidthEq4_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[2*stride]
w4_hv_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
// vertical filtered into v20/v21 1st line
FILTER_6TAG_8BITS_TO_16BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v2, v3, v4, v5, v6, v7, v21, v0, v1
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v16=src[4*stride]
// vertical filtered into v22/v23 2nd line
FILTER_6TAG_8BITS_TO_16BITS1 v3, v4, v5, v6, v7, v2, v22, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v3, v4, v5, v6, v7, v2, v23, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v24, v25, v26
UNPACK_2_16BITS_TO_ABC v22, v23, v28, v29, v30
zip1 v24.2d, v24.2d, v28.2d
zip1 v25.2d, v25.2d, v29.2d
zip1 v26.2d, v26.2d, v30.2d
FILTER_3_IN_16BITS_TO_8BITS1 v24, v25, v26, v27 //output to v27[0]
st1 {v27.s}[0], [x2], x3 //write 4Byte : 0 line
st1 {v27.s}[1], [x2], x3 //write 4Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[5*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v4, v5, v6, v7, v2, v3, v21, v0, v1
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[6*stride]
FILTER_6TAG_8BITS_TO_16BITS1 v5, v6, v7, v2, v3, v4, v22, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v5, v6, v7, v2, v3, v4, v23, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v24, v25, v26
UNPACK_2_16BITS_TO_ABC v22, v23, v28, v29, v30
zip1 v24.2d, v24.2d, v28.2d
zip1 v25.2d, v25.2d, v29.2d
zip1 v26.2d, v26.2d, v30.2d
FILTER_3_IN_16BITS_TO_8BITS1 v24, v25, v26, v27 //output to v27[0]
st1 {v27.s}[0], [x2], x3 //write 4Byte : 2 line
st1 {v27.s}[1], [x2], x3 //write 4Byte : 3 line
mov v5.16b, v3.16b
mov v3.16b, v7.16b
mov v30.16b, v2.16b
mov v2.16b, v6.16b
mov v6.16b, v4.16b
mov v4.16b, v30.16b
sub x4, x4, #4
cbnz x4, w4_hv_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McCopyWidthEq16_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McCopyWidthEq16_AArch64_neon
//prfm pldl1strm, [x0]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w16_copy_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v0.16b}, [x0], x1 //read 16Byte : 0 line
st1 {v0.16b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v1.16b}, [x0], x1 //read 16Byte : 1 line
st1 {v1.16b}, [x2], x3 //write 16Byte : 1 line
sub x4, x4, #2
cbnz x4, w16_copy_loop
WELS_ASM_AARCH64_FUNC_END
//void McCopyWidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McCopyWidthEq8_AArch64_neon
//prfm pldl1strm, [x0]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w8_copy_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v0.8b}, [x0], x1 //read 16Byte : 0 line
st1 {v0.8b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v1.8b}, [x0], x1 //read 16Byte : 1 line
st1 {v1.8b}, [x2], x3 //write 16Byte : 1 line
sub x4, x4, #2
cbnz x4, w8_copy_loop
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN McCopyWidthEq4_AArch64_neon
//prfm pldl1strm, [x0]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
w4_copy_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v0.s}[0], [x0], x1 //read 16Byte : 0 line
st1 {v0.s}[0], [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v1.s}[0], [x0], x1 //read 16Byte : 1 line
st1 {v1.s}[0], [x2], x3 //write 16Byte : 1 line
sub x4, x4, #2
cbnz x4, w4_copy_loop
WELS_ASM_AARCH64_FUNC_END
//void PixStrideAvgWidthEq16_AArch64_neon (uint8_t* pDst, int32_t iDstStride, const uint8_t* pSrcA, int32_t iSrcStrideA,
//const uint8_t* pSrcB, int32_t iSrcStrideB, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN PixStrideAvgWidthEq16_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
SIGN_EXTENSION x6,w6
enc_w16_pix_avg_loop:
ld1 {v0.16b}, [x2], x3 //read 16Byte : src0: 0 line
ld1 {v1.16b}, [x4], x5 //read 16Byte : src1: 0 line
ld1 {v2.16b}, [x2], x3 //read 16Byte : src0: 1 line
ld1 {v3.16b}, [x4], x5 //read 16Byte : src1: 1 line
ld1 {v4.16b}, [x2], x3 //read 16Byte : src0: 2 line
ld1 {v5.16b}, [x4], x5 //read 16Byte : src1: 2 line
ld1 {v6.16b}, [x2], x3 //read 16Byte : src0: 3 line
ld1 {v7.16b}, [x4], x5 //read 16Byte : src1: 3 line
AVERAGE_TWO_8BITS1 v16, v0, v1
AVERAGE_TWO_8BITS2 v16, v0, v1
st1 {v16.16b}, [x0], x1 //write 16Byte : 0 line
AVERAGE_TWO_8BITS1 v16, v2, v3
AVERAGE_TWO_8BITS2 v16, v2, v3
st1 {v16.16b}, [x0], x1 //write 16Byte : 1 line
AVERAGE_TWO_8BITS1 v16, v4, v5
AVERAGE_TWO_8BITS2 v16, v4, v5
st1 {v16.16b}, [x0], x1 //write 16Byte : 2 line
AVERAGE_TWO_8BITS1 v16, v6, v7
AVERAGE_TWO_8BITS2 v16, v6, v7
st1 {v16.16b}, [x0], x1 //write 16Byte : 3 line
sub x6, x6, #4
cbnz x6, enc_w16_pix_avg_loop
WELS_ASM_AARCH64_FUNC_END
//void PixStrideAvgWidthEq8_AArch64_neon (uint8_t* pDst, int32_t iDstStride, const uint8_t* pSrcA, int32_t iSrcStrideA,
// const uint8_t* pSrcB, int32_t iSrcStrideB, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN PixStrideAvgWidthEq8_AArch64_neon
//prfm pldl1strm, [x2]
//prfm pldl1strm, [x4]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
SIGN_EXTENSION x6,w6
enc_w8_pix_avg_loop:
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v0.8b}, [x2], x3 //read 8Byte : src0: 0 line
ld1 {v1.8b}, [x4], x5 //read 8Byte : src1: 0 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v2.8b}, [x2], x3 //read 8Byte : src0: 1 line
ld1 {v3.8b}, [x4], x5 //read 8Byte : src1: 1 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v4.8b}, [x2], x3 //read 8Byte : src0: 2 line
ld1 {v5.8b}, [x4], x5 //read 8Byte : src1: 2 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v6.8b}, [x2], x3 //read 8Byte : src0: 3 line
ld1 {v7.8b}, [x4], x5 //read 8Byte : src1: 3 line
AVERAGE_TWO_8BITS1 v16, v0, v1
st1 {v16.8b}, [x0], x1 //write 8Byte : 0 line
AVERAGE_TWO_8BITS1 v16, v2, v3
st1 {v16.8b}, [x0], x1 //write 8Byte : 1 line
AVERAGE_TWO_8BITS1 v16, v4, v5
st1 {v16.8b}, [x0], x1 //write 8Byte : 2 line
AVERAGE_TWO_8BITS1 v16, v6, v7
st1 {v16.8b}, [x0], x1 //write 8Byte : 3 line
sub x6, x6, #4
cbnz x6, enc_w8_pix_avg_loop
WELS_ASM_AARCH64_FUNC_END
//void PixelAvgWidthEq16_AArch64_neon (uint8_t* pDst, int32_t iDstStride, const uint8_t* pSrcA, int32_t iSrcAStride,
// const uint8_t* pSrcB, int32_t iSrcBStride, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN PixelAvgWidthEq16_AArch64_neon
//prfm pldl1strm, [x2]
//prfm pldl1strm, [x4]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
SIGN_EXTENSION x6,w6
w16_pix_avg_loop:
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v0.16b}, [x2], x3 //read 16Byte : src0: 0 line
ld1 {v1.16b}, [x4], x5 //read 16Byte : src1: 0 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v2.16b}, [x2], x3 //read 16Byte : src0: 1 line
ld1 {v3.16b}, [x4], x5 //read 16Byte : src1: 1 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v4.16b}, [x2], x3 //read 16Byte : src0: 2 line
ld1 {v5.16b}, [x4], x5 //read 16Byte : src1: 2 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v6.16b}, [x2], x3 //read 16Byte : src0: 3 line
ld1 {v7.16b}, [x4], x5 //read 16Byte : src1: 3 line
AVERAGE_TWO_8BITS1 v16, v0, v1
AVERAGE_TWO_8BITS2 v16, v0, v1
st1 {v16.16b}, [x0], x1 //write 16Byte : 0 line
AVERAGE_TWO_8BITS1 v16, v2, v3
AVERAGE_TWO_8BITS2 v16, v2, v3
st1 {v16.16b}, [x0], x1 //write 16Byte : 1 line
AVERAGE_TWO_8BITS1 v16, v4, v5
AVERAGE_TWO_8BITS2 v16, v4, v5
st1 {v16.16b}, [x0], x1 //write 16Byte : 2 line
AVERAGE_TWO_8BITS1 v16, v6, v7
AVERAGE_TWO_8BITS2 v16, v6, v7
st1 {v16.16b}, [x0], x1 //write 16Byte : 3 line
sub x6, x6, #4
cbnz x6, w16_pix_avg_loop
WELS_ASM_AARCH64_FUNC_END
//void PixelAvgWidthEq8_AArch64_neon (uint8_t* pDst, int32_t iDstStride, const uint8_t* pSrcA, int32_t iSrcAStride,
// const uint8_t* pSrcB, int32_t iSrcBStride, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN PixelAvgWidthEq8_AArch64_neon
//prfm pldl1strm, [x2]
//prfm pldl1strm, [x4]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
SIGN_EXTENSION x6,w6
w8_pix_avg_loop:
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v0.8b}, [x2], x3 //read 8Byte : src0: 0 line
ld1 {v1.8b}, [x4], x5 //read 8Byte : src1: 0 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v2.8b}, [x2], x3 //read 8Byte : src0: 1 line
ld1 {v3.8b}, [x4], x5 //read 8Byte : src1: 1 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v4.8b}, [x2], x3 //read 8Byte : src0: 2 line
ld1 {v5.8b}, [x4], x5 //read 8Byte : src1: 2 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v6.8b}, [x2], x3 //read 8Byte : src0: 3 line
ld1 {v7.8b}, [x4], x5 //read 8Byte : src1: 3 line
AVERAGE_TWO_8BITS1 v16, v0, v1
st1 {v16.8b}, [x0], x1 //write 8Byte : 0 line
AVERAGE_TWO_8BITS1 v16, v2, v3
st1 {v16.8b}, [x0], x1 //write 8Byte : 1 line
AVERAGE_TWO_8BITS1 v16, v4, v5
st1 {v16.8b}, [x0], x1 //write 8Byte : 2 line
AVERAGE_TWO_8BITS1 v16, v6, v7
st1 {v16.8b}, [x0], x1 //write 8Byte : 3 line
sub x6, x6, #4
cbnz x6, w8_pix_avg_loop
WELS_ASM_AARCH64_FUNC_END
//void PixelAvgWidthEq4_AArch64_neon (uint8_t* pDst, int32_t iDstStride, const uint8_t* pSrcA, int32_t iSrcAStride,
// const uint8_t* pSrcB, int32_t iSrcBStride, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN PixelAvgWidthEq4_AArch64_neon
//prfm pldl1strm, [x2]
//prfm pldl1strm, [x4]
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
SIGN_EXTENSION x6,w6
w4_pix_avg_loop:
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v0.s}[0], [x2], x3 //read 4Byte : src0: 0 line
ld1 {v1.s}[0], [x4], x5 //read 4Byte : src1: 0 line
//prfm pldl1strm, [x2, x3]
//prfm pldl1strm, [x4, x5]
ld1 {v0.s}[1], [x2], x3 //read 4Byte : src0: 1 line
ld1 {v1.s}[1], [x4], x5 //read 4Byte : src1: 1 line
AVERAGE_TWO_8BITS1 v2, v0, v1
st1 {v2.s}[0], [x0], x1 //write 4Byte : 0 line
st1 {v2.s}[1], [x0], x1 //write 4Byte : 1 line
sub x6, x6, #2
cbnz x6, w4_pix_avg_loop
WELS_ASM_AARCH64_FUNC_END
//void McChromaWidthEq8_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t* pWeights, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McChromaWidthEq8_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
ld4r {v28.8b, v29.8b, v30.8b, v31.8b}, [x4] //load A/B/C/D
ld1 {v16.16b}, [x0], x1 // src[x]
ext v17.16b, v16.16b, v16.16b, #1 // src[x+1]
w8_mc_chroma_loop:
ld1 {v18.16b}, [x0], x1 // src[x+stride]
ext v19.16b, v18.16b, v18.16b, #1 // src[x+stride+1]
ld1 {v20.16b}, [x0], x1 // src[x+2*stride]
ext v21.16b, v20.16b, v20.16b, #1 // src[x+2*stride+1]
ld1 {v22.16b}, [x0], x1 // src[x+3*stride]
ext v23.16b, v22.16b, v22.16b, #1 // src[x+3*stride+1]
ld1 {v24.16b}, [x0], x1 // src[x+4*stride]
ext v25.16b, v24.16b, v24.16b, #1 // src[x+4*stride+1]
umull v0.8h, v16.8b, v28.8b
umull v2.8h, v18.8b, v28.8b
umull v4.8h, v20.8b, v28.8b
umull v6.8h, v22.8b, v28.8b
umlal v0.8h, v17.8b, v29.8b
umlal v2.8h, v19.8b, v29.8b
umlal v4.8h, v21.8b, v29.8b
umlal v6.8h, v23.8b, v29.8b
umlal v0.8h, v18.8b, v30.8b
umlal v2.8h, v20.8b, v30.8b
umlal v4.8h, v22.8b, v30.8b
umlal v6.8h, v24.8b, v30.8b
umlal v0.8h, v19.8b, v31.8b
umlal v2.8h, v21.8b, v31.8b
umlal v4.8h, v23.8b, v31.8b
umlal v6.8h, v25.8b, v31.8b
rshrn v1.8b, v0.8h, #6
st1 {v1.8b}, [x2], x3
rshrn v3.8b, v2.8h, #6
st1 {v3.8b}, [x2], x3
rshrn v5.8b, v4.8h, #6
st1 {v5.8b}, [x2], x3
rshrn v7.8b, v6.8h, #6
st1 {v7.8b}, [x2], x3
mov v16.16b, v24.16b
mov v17.16b, v25.16b
sub x5, x5, #4
cbnz x5, w8_mc_chroma_loop
WELS_ASM_AARCH64_FUNC_END
//void McChromaWidthEq4_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t* pWeights, int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McChromaWidthEq4_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x5,w5
ld4r {v4.8b, v5.8b, v6.8b, v7.8b}, [x4] //load A/B/C/D
ld1 {v0.8b}, [x0], x1 // src[x]
ext v1.8b, v0.8b, v0.8b, #1 // src[x+1]
w4_mc_chroma_loop:
ld1 {v2.8b}, [x0], x1 // src[x+stride]
ext v3.8b, v2.8b, v2.8b, #1 // src[x+stride+1]
ld1 {v18.8b}, [x0], x1 // src[x+2*stride]
ext v19.8b, v18.8b, v18.8b, #1 // src[x+2*stride+1]
zip1 v0.4s, v0.4s, v2.4s
zip1 v1.4s, v1.4s, v3.4s
zip1 v2.4s, v2.4s, v18.4s
zip1 v3.4s, v3.4s, v19.4s
umull v16.8h, v0.8b, v4.8b
umlal v16.8h, v1.8b, v5.8b
umlal v16.8h, v2.8b, v6.8b
umlal v16.8h, v3.8b, v7.8b
rshrn v17.8b, v16.8h, #6
st1 {v17.s}[0], [x2], x3
st1 {v17.s}[1], [x2], x3
mov v0.8b, v18.8b
mov v1.8b, v19.8b
sub x5, x5, #2
cbnz x5, w4_mc_chroma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer20Width17_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);// width+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer20Width17_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x3, x3, #16
mov x5, #16
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
ldr q22, filter_para
w17_h_mc_luma_loop:
ld1 {v2.16b, v3.16b}, [x0], x1 //only use 22(17+5); v2=src[-2]
//prfm pldl1strm, [x0]
ext v5.16b, v2.16b, v3.16b, #1 //v5=src[-1]
ext v6.16b, v2.16b, v3.16b, #2 //v6=src[0]
ext v7.16b, v2.16b, v3.16b, #3 //v7=src[1]
ext v16.16b, v2.16b, v3.16b, #4 //v16=src[2]
ext v17.16b, v2.16b, v3.16b, #5 //v17=src[3]
FILTER_6TAG_8BITS1 v2, v5, v6, v7, v16, v17, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v5, v6, v7, v16, v17, v20, v0, v1
st1 {v20.16b}, [x2], x5 //write 16Byte
ext v21.8b, v3.8b, v3.8b, #7 // [0][1][2][3][4][5]XY-->O[0][1][2][3][4][5]X
FILTER_SINGLE_TAG_8BITS v21, v22, v23, h21
st1 {v21.b}[0], [x2], x3 //write 16th Byte
sub x4, x4, #1
cbnz x4, w17_h_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer20Width9_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);// width+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer20Width9_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x3, x3, #8
mov x5, #8
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
ldr q22, filter_para
w9_h_mc_luma_loop:
ld1 {v2.16b}, [x0], x1 //only use 14(9+5); v2=src[-2]
mov v3.d[0], v2.d[1]
//prfm pldl1strm, [x0]
ext v5.16b, v2.16b, v4.16b, #1 //v5=src[-1]
ext v6.16b, v2.16b, v4.16b, #2 //v6=src[0]
ext v7.16b, v2.16b, v4.16b, #3 //v7=src[1]
ext v16.16b, v2.16b, v4.16b, #4 //v16=src[2]
ext v17.16b, v2.16b, v4.16b, #5 //v17=src[3]
FILTER_6TAG_8BITS1 v2, v5, v6, v7, v16, v17, v20, v0, v1
st1 {v20.8b}, [x2], x5 //write 8Byte
ext v21.8b, v3.8b, v3.8b, #7 // [0][1][2][3][4][5]XY-->O[0][1][2][3][4][5]X
FILTER_SINGLE_TAG_8BITS v21, v22, v23, h21
st1 {v21.b}[0], [x2], x3 //write 9th Byte
sub x4, x4, #1
cbnz x4, w9_h_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer20Width5_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);// width+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer20Width5_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x3, x3, #4
mov x5, #4
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
w5_h_mc_luma_loop:
ld1 {v2.16b}, [x0], x1 //only use 10(5+5); v2=src[-2]
ext v5.16b, v2.16b, v4.16b, #1 //v5=src[-1]
ext v6.16b, v2.16b, v4.16b, #2 //v6=src[0]
ext v7.16b, v2.16b, v4.16b, #3 //v7=src[1]
ext v16.16b, v2.16b, v4.16b, #4 //v16=src[2]
ext v17.16b, v2.16b, v4.16b, #5 //v17=src[3]
FILTER_6TAG_8BITS1 v2, v5, v6, v7, v16, v17, v20, v0, v1
st1 {v20.s}[0], [x2], x5 //write 4Byte
st1 {v20.b}[4], [x2], x3 //write 5th Byte
sub x4, x4, #1
cbnz x4, w5_h_mc_luma_loop
WELS_ASM_AARCH64_FUNC_END
//void McHorVer22Width17_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer22Width17_AArch64_neon
stp d8, d9, [sp,#-16]!
stp d10, d11, [sp,#-16]!
stp d12, d13, [sp,#-16]!
stp d14, d15, [sp,#-16]!
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
sub x3, x3, #16
mov x5, #16
ldr q29, filter_para
sub x4, x4, #1
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.8b, v6.8b, v7.8b}, [x0], x1 // v5=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v8.8b, v9.8b, v10.8b}, [x0], x1 // v8=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v11.8b, v12.8b, v13.8b}, [x0], x1 // v11=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v14.8b, v15.8b, v16.8b}, [x0], x1 // v14=src[2*stride]
w17_hv_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v17.8b, v18.8b, v19.8b}, [x0], x1 // v17=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v5, v8, v11, v14, v17, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v3, v6, v9, v12, v15, v18, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v4, v7, v10, v13, v16, v19, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15 Byte : 0 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 // v2=src[4*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v8, v11, v14, v17, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v6, v9, v12, v15, v18, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v7, v10, v13, v16, v19, v4, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 1 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v5.8b, v6.8b, v7.8b}, [x0], x1 // v2=src[5*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v8, v11, v14, v17, v2, v5, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v9, v12, v15, v18, v3, v6, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v10, v13, v16, v19, v4, v7, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 2 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v8.8b, v9.8b, v10.8b}, [x0], x1 // v2=src[6*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v11, v14, v17, v2, v5, v8, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v12, v15, v18, v3, v6, v9, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v13, v16, v19, v4, v7, v10, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 3 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 3 line
//prfm pldl1strm, [x0, x1]
ld1 {v11.8b, v12.8b, v13.8b}, [x0], x1 // v2=src[7*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v14, v17, v2, v5, v8, v11, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v15, v18, v3, v6, v9, v12, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v16, v19, v4, v7, v10, v13, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 4 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 4 line
//prfm pldl1strm, [x0, x1]
ld1 {v14.8b, v15.8b, v16.8b}, [x0], x1 // v2=src[8*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v17, v2, v5, v8, v11, v14, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v18, v3, v6, v9, v12, v15, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v19, v4, v7, v10, v13, v16, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 5 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 5 line
//prfm pldl1strm, [x0, x1]
ld1 {v17.8b, v18.8b, v19.8b}, [x0], x1 // v2=src[9*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v5, v8, v11, v14, v17, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v3, v6, v9, v12, v15, v18, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v4, v7, v10, v13, v16, v19, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 6 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 6 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b, v3.8b, v4.8b}, [x0], x1 // v2=src[10*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v8, v11, v14, v17, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v6, v9, v12, v15, v18, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v7, v10, v13, v16, v19, v4, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15Byte : 7 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 7 line
mov v5.16b, v11.16b
mov v11.16b, v17.16b
mov v30.16b, v2.16b
mov v2.16b, v8.16b
mov v8.16b, v14.16b
mov v14.16b, v30.16b
mov v6.16b, v12.16b
mov v12.16b, v18.16b
mov v30.16b, v3.16b
mov v3.16b, v9.16b
mov v9.16b, v15.16b
mov v15.16b, v30.16b
mov v7.16b, v13.16b
mov v13.16b, v19.16b
mov v30.16b, v4.16b
mov v4.16b, v10.16b
mov v10.16b, v16.16b
mov v16.16b, v30.16b
sub x4, x4, #8
cbnz x4, w17_hv_mc_luma_loop
//prfm pldl1strm, [x0, x1]
ld1 {v17.8b, v18.8b, v19.8b}, [x0], x1 // v17=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v5, v8, v11, v14, v17, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS1 v3, v6, v9, v12, v15, v18, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
// vertical filtered into v21/v22
FILTER_6TAG_8BITS_TO_16BITS1 v4, v7, v10, v13, v16, v19, v22, v0, v1
UNPACK_2_16BITS_TO_ABC v21, v22, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS2 v23, v24, v25, v26 //output to v26[1]
st1 {v26.16b}, [x2], x5 //write 0:15 Byte : 0 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v22, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 16th Byte : 0 line
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
WELS_ASM_AARCH64_FUNC_END
//void McHorVer22Width9_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);//width+1&&height+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer22Width9_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
sub x3, x3, #8
mov x5, #8
ldr q29, filter_para
sub x4, x4, #1
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v5=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v8=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v11=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v14=src[2*stride]
w9_hv_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v2, v3, v4, v5, v6, v7, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x5 //write 0:7Byte : 0 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v21, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 8th Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[4*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v3, v4, v5, v6, v7, v2, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x5 //write 0:7Byte : 1 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v21, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 8th Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[5*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v4, v5, v6, v7, v2, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x5 //write 0:7Byte : 2 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v21, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 8th Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[6*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v5, v6, v7, v2, v3, v4, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x5 //write 0:7Byte : 3 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v21, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 8th Byte : 3 line
mov v5.16b, v3.16b
mov v3.16b, v7.16b
mov v30.16b, v2.16b
mov v2.16b, v6.16b
mov v6.16b, v4.16b
mov v4.16b, v30.16b
sub x4, x4, #4
cbnz x4, w9_hv_mc_luma_loop
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v2, v3, v4, v5, v6, v7, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.8b}, [x2], x5 //write 0:7Byte : 0 line
UNPACK_FILTER_SINGLE_TAG_16BITS v26, v21, v29, v27, v28, d26
st1 {v26.b}[0], [x2], x3 //write 8th Byte : 0 line
WELS_ASM_AARCH64_FUNC_END
//void McHorVer22Width5_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);//width+1&&height+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer22Width5_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, #2
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
sub x3, x3, #4
mov x5, #4
ldr q29, filter_para
sub x4, x4, #1
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v5=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v8=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v11=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v14=src[2*stride]
w5_hv_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v2, v3, v4, v5, v6, v7, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.s}[0], [x2], x5 //write 0:3Byte : 0 line
st1 {v26.b}[4], [x2], x3 //write 5th Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[4*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v3, v4, v5, v6, v7, v2, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.s}[0], [x2], x5 //write 0:3Byte : 1 line
st1 {v26.b}[4], [x2], x3 //write 5th Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[5*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v4, v5, v6, v7, v2, v3, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.s}[0], [x2], x5 //write 0:3Byte : 2 line
st1 {v26.b}[4], [x2], x3 //write 5th Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[6*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v5, v6, v7, v2, v3, v4, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.s}[0], [x2], x5 //write 0:3Byte : 3 line
st1 {v26.b}[4], [x2], x3 //write 5th Byte : 3 line
mov v5.16b, v3.16b
mov v3.16b, v7.16b
mov v30.16b, v2.16b
mov v2.16b, v6.16b
mov v6.16b, v4.16b
mov v4.16b, v30.16b
sub x4, x4, #4
cbnz x4, w5_hv_mc_luma_loop
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
// vertical filtered into v20/v21
FILTER_6TAG_8BITS_TO_16BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS_TO_16BITS2 v2, v3, v4, v5, v6, v7, v21, v0, v1
// horizon filtered
UNPACK_2_16BITS_TO_ABC v20, v21, v23, v24, v25
FILTER_3_IN_16BITS_TO_8BITS1 v23, v24, v25, v26 //output to v26[0]
st1 {v26.s}[0], [x2], x5 //write 0:3Byte : 0 line
st1 {v26.b}[4], [x2], x3 //write 5th Byte : 0 line
WELS_ASM_AARCH64_FUNC_END
//void McHorVer02Height17_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);// height+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer02Height17_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
sub x4, x4, #1
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[2*stride]
w17_v_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[4*stride]
FILTER_6TAG_8BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.16b}, [x0], x1 // v3=src[5*stride]
FILTER_6TAG_8BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
FILTER_6TAG_8BITS2 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.16b}, [x0], x1 // v4=src[6*stride]
FILTER_6TAG_8BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
FILTER_6TAG_8BITS2 v5, v6, v7, v2, v3, v4, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 3 line
//prfm pldl1strm, [x0, x1]
ld1 {v5.16b}, [x0], x1 // v5=src[7*stride]
FILTER_6TAG_8BITS1 v6, v7, v2, v3, v4, v5, v20, v0, v1
FILTER_6TAG_8BITS2 v6, v7, v2, v3, v4, v5, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 4 line
//prfm pldl1strm, [x0, x1]
ld1 {v6.16b}, [x0], x1 // v6=src[8*stride]
FILTER_6TAG_8BITS1 v7, v2, v3, v4, v5, v6, v20, v0, v1
FILTER_6TAG_8BITS2 v7, v2, v3, v4, v5, v6, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 5 line
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[9*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 6 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.16b}, [x0], x1 // v2=src[10*stride]
FILTER_6TAG_8BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
FILTER_6TAG_8BITS2 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : 7 line
mov v3.16b, v5.16b
mov v5.16b, v7.16b
mov v7.16b, v2.16b
mov v2.16b, v4.16b
mov v4.16b, v6.16b
mov v6.16b, v7.16b
sub x4, x4, #8
cbnz x4, w17_v_mc_luma_loop
//prfm pldl1strm, [x0, x1]
ld1 {v7.16b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
FILTER_6TAG_8BITS2 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.16b}, [x2], x3 //write 16Byte : last line
WELS_ASM_AARCH64_FUNC_END
//void McHorVer02Height9_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);// height+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer02Height9_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
sub x4, x4, #1
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.8b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.8b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.8b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.8b}, [x0], x1 // v6=src[2*stride]
w9_v_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.8b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.8b}, [x2], x3 //write 8Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b}, [x0], x1 // v2=src[4*stride]
FILTER_6TAG_8BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.8b}, [x2], x3 //write 8Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.8b}, [x0], x1 // v3=src[5*stride]
FILTER_6TAG_8BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.8b}, [x2], x3 //write 8Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.8b}, [x0], x1 // v4=src[6*stride]
FILTER_6TAG_8BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
st1 {v20.8b}, [x2], x3 //write 8Byte : 3 line
mov v5.16b, v3.16b
mov v3.16b, v7.16b
mov v7.16b, v2.16b
mov v2.16b, v6.16b
mov v6.16b, v4.16b
mov v4.16b, v7.16b
sub x4, x4, #4
cbnz x4, w9_v_mc_luma_loop
//prfm pldl1strm, [x0, x1]
ld1 {v7.8b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.8b}, [x2], x3 //write 8Byte : 0 line
WELS_ASM_AARCH64_FUNC_END
//void McHorVer02Height5_AArch64_neon (const uint8_t* pSrc, int32_t iSrcStride, uint8_t* pDst, int32_t iDstStride,
// int32_t iHeight);// height+1
WELS_ASM_AARCH64_FUNC_BEGIN McHorVer02Height5_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x3,w3
SIGN_EXTENSION x4,w4
sub x0, x0, x1, lsl #1
movi v0.8h, #20, lsl #0
movi v1.8h, #5, lsl #0
sub x4, x4, #1
//prfm pldl1strm, [x0]
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b}, [x0], x1 // v2=src[-2*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v3.8b}, [x0], x1 // v3=src[-1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v4.8b}, [x0], x1 // v4=src[0*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v5.8b}, [x0], x1 // v5=src[1*stride]
//prfm pldl1strm, [x0, x1]
ld1 {v6.8b}, [x0], x1 // v6=src[2*stride]
w5_v_mc_luma_loop:
//prfm pldl1strm, [x0, x1]
ld1 {v7.8b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 0 line
//prfm pldl1strm, [x0, x1]
ld1 {v2.8b}, [x0], x1 // v2=src[4*stride]
FILTER_6TAG_8BITS1 v3, v4, v5, v6, v7, v2, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 1 line
//prfm pldl1strm, [x0, x1]
ld1 {v3.8b}, [x0], x1 // v3=src[5*stride]
FILTER_6TAG_8BITS1 v4, v5, v6, v7, v2, v3, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 2 line
//prfm pldl1strm, [x0, x1]
ld1 {v4.8b}, [x0], x1 // v4=src[6*stride]
FILTER_6TAG_8BITS1 v5, v6, v7, v2, v3, v4, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 3 line
mov v5.16b, v3.16b
mov v3.16b, v7.16b
mov v7.16b, v2.16b
mov v2.16b, v6.16b
mov v6.16b, v4.16b
mov v4.16b, v7.16b
sub x4, x4, #4
cbnz x4, w5_v_mc_luma_loop
//prfm pldl1strm, [x0, x1]
ld1 {v7.8b}, [x0], x1 // v7=src[3*stride]
FILTER_6TAG_8BITS1 v2, v3, v4, v5, v6, v7, v20, v0, v1
st1 {v20.s}[0], [x2], x3 //write 4Byte : 0 line
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 30,585 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm64/deblocking_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro MASK_MATRIX arg0, arg1, arg2, arg3, arg4, arg5, arg6
uabd \arg6\().16b, \arg1\().16b, \arg2\().16b
cmhi \arg6\().16b, \arg4\().16b, \arg6\().16b
uabd \arg4\().16b, \arg0\().16b, \arg1\().16b
cmhi \arg4\().16b, \arg5\().16b, \arg4\().16b
and \arg6\().16b, \arg6\().16b, \arg4\().16b
uabd \arg4\().16b, \arg3\().16b, \arg2\().16b
cmhi \arg4\().16b, \arg5\().16b, \arg4\().16b
and \arg6\().16b, \arg6\().16b, \arg4\().16b
.endm
.macro DIFF_LUMA_LT4_P1_Q1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
//v0, v1, v2, v3, v17(beta), v18(-Tc0), v6(Tc0), v7(flag), v19, v20
urhadd \arg8\().16b, \arg2\().16b, \arg3\().16b
uhadd \arg8\().16b, \arg0\().16b, \arg8\().16b
usubl \arg9\().8h, \arg8\().8b, \arg1\().8b
sqxtn \arg9\().8b, \arg9\().8h
usubl2 \arg8\().8h, \arg8\().16b, \arg1\().16b
sqxtn2 \arg9\().16b, \arg8\().8h
smax \arg8\().16b, \arg9\().16b, \arg5\().16b
//
smin \arg8\().16b, \arg8\().16b, \arg6\().16b
uabd \arg9\().16b, \arg0\().16b, \arg2\().16b
cmhi \arg9\().16b, \arg4\().16b, \arg9\().16b
and \arg8\().16b, \arg8\().16b, \arg9\().16b
and \arg8\().16b, \arg8\().16b, \arg7\().16b
add \arg8\().16b, \arg1\().16b, \arg8\().16b
abs \arg9\().16b, \arg9\().16b
.endm
.macro DIFF_LUMA_LT4_P0_Q0_1 arg0, arg1, arg2, arg3, arg4, arg5, arg6
usubl \arg5\().8h, \arg0\().8b, \arg3\().8b
usubl \arg6\().8h, \arg2\().8b, \arg1\().8b
shl \arg6\().8h, \arg6\().8h, #2
add \arg5\().8h, \arg5\().8h, \arg6\().8h
sqrshrn \arg4\().8b, \arg5\().8h, #3
.endm
.macro DIFF_LUMA_LT4_P0_Q0_2 arg0, arg1, arg2, arg3, arg4, arg5, arg6
usubl2 \arg5\().8h, \arg0\().16b, \arg3\().16b
usubl2 \arg6\().8h, \arg2\().16b, \arg1\().16b
shl \arg6\().8h, \arg6\().8h, #2
add \arg5\().8h, \arg5\().8h, \arg6\().8h
sqrshrn2 \arg4\().16b, \arg5\().8h, #3
.endm
.macro EXTRACT_DELTA_INTO_TWO_PART arg0, arg1
cmge \arg1\().16b, \arg0\().16b, #0
and \arg1\().16b, \arg0\().16b, \arg1\().16b
sub \arg0\().16b, \arg1\().16b, \arg0\().16b
.endm
.macro DIFF_LUMA_EQ4_P2P1P0_1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
uaddl \arg8\().8h, \arg1\().8b, \arg2\().8b
uaddl \arg9\().8h, \arg3\().8b, \arg4\().8b
add \arg9\().8h, \arg9\().8h, \arg8\().8h
uaddl \arg8\().8h, \arg0\().8b, \arg1\().8b
shl \arg8\().8h, \arg8\().8h, #1
add \arg8\().8h, \arg9\().8h, \arg8\().8h
rshrn \arg0\().8b, \arg9\().8h, #2
rshrn \arg7\().8b, \arg8\().8h, #3
shl \arg9\().8h, \arg9\().8h, #1
usubl \arg8\().8h, \arg5\().8b, \arg1\().8b
add \arg9\().8h, \arg8\().8h, \arg9\().8h
uaddl \arg8\().8h, \arg2\().8b, \arg5\().8b
uaddw \arg8\().8h, \arg8\().8h, \arg2\().8b
uaddw \arg8\().8h, \arg8\().8h, \arg3\().8b
rshrn \arg9\().8b, \arg9\().8h, #3
rshrn \arg8\().8b, \arg8\().8h, #2
bsl \arg6\().8b, \arg9\().8b, \arg8\().8b
.endm
.macro DIFF_LUMA_EQ4_P2P1P0_2 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
uaddl2 \arg8\().8h, \arg1\().16b, \arg2\().16b
uaddl2 \arg9\().8h, \arg3\().16b, \arg4\().16b
add \arg9\().8h, \arg9\().8h, \arg8\().8h
uaddl2 \arg8\().8h, \arg0\().16b, \arg1\().16b
shl \arg8\().8h, \arg8\().8h, #1
add \arg8\().8h, \arg9\().8h, \arg8\().8h
rshrn2 \arg0\().16b, \arg9\().8h, #2
rshrn2 \arg7\().16b, \arg8\().8h, #3
shl \arg9\().8h, \arg9\().8h, #1
usubl2 \arg8\().8h, \arg5\().16b, \arg1\().16b
add \arg9\().8h, \arg8\().8h, \arg9\().8h
uaddl2 \arg8\().8h, \arg2\().16b, \arg5\().16b
uaddw2 \arg8\().8h, \arg8\().8h, \arg2\().16b
uaddw2 \arg8\().8h, \arg8\().8h, \arg3\().16b
rshrn2 \arg9\().16b, \arg9\().8h, #3
rshrn2 \arg8\().16b, \arg8\().8h, #2
bsl \arg6\().16b, \arg9\().16b, \arg8\().16b
.endm
.macro DIFF_CHROMA_EQ4_P0Q0_1 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
uaddl \arg4\().8h, \arg0\().8b, \arg3\().8b
shl \arg4\().8h, \arg4\().8h, #1
usubl \arg5\().8h, \arg1\().8b, \arg3\().8b
add \arg5\().8h, \arg5\().8h, \arg4\().8h
rshrn \arg6\().8b, \arg5\().8h, #2
usubl \arg5\().8h, \arg2\().8b, \arg0\().8b
add \arg5\().8h, \arg5\().8h, \arg4\().8h
rshrn \arg7\().8b, \arg5\().8h, #2
.endm
.macro DIFF_CHROMA_EQ4_P0Q0_2 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
uaddl2 \arg4\().8h, \arg0\().16b, \arg3\().16b
shl \arg4\().8h, \arg4\().8h, #1
usubl2 \arg5\().8h, \arg1\().16b, \arg3\().16b
add \arg5\().8h, \arg5\().8h, \arg4\().8h
rshrn2 \arg6\().16b, \arg5\().8h, #2
usubl2 \arg5\().8h, \arg2\().16b, \arg0\().16b
add \arg5\().8h, \arg5\().8h, \arg4\().8h
rshrn2 \arg7\().16b, \arg5\().8h, #2
.endm
.macro DIFF_LUMA_EQ4_MASK arg0, arg1, arg2, arg3
mov \arg3\().16b, \arg2\().16b
bsl \arg3\().16b, \arg0\().16b, \arg1\().16b
.endm
.macro LOAD_LUMA_DATA_3 arg0, arg1, arg2, arg3, arg4, arg5, arg6
ld3 {\arg0\().b, \arg1\().b, \arg2\().b} [\arg6], [x2], x1
ld3 {\arg3\().b, \arg4\().b, \arg5\().b} [\arg6], [x0], x1
.endm
.macro LOAD_LUMA_DATA_4 arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8
ld4 {\arg0\().b, \arg1\().b, \arg2\().b, \arg3\().b} [\arg8], [x3], x1
ld4 {\arg4\().b, \arg5\().b, \arg6\().b, \arg7\().b} [\arg8], [x0], x1
.endm
.macro STORE_LUMA_DATA_4 arg0, arg1, arg2, arg3, arg4, arg5
st4 {\arg0\().b, \arg1\().b, \arg2\().b, \arg3\().b} [\arg4], [x0], x1
st4 {\arg0\().b, \arg1\().b, \arg2\().b, \arg3\().b} [\arg5], [x2], x1
.endm
.macro STORE_LUMA_DATA_3 arg0, arg1, arg2, arg3, arg4, arg5, arg6
st3 {\arg0\().b, \arg1\().b, \arg2\().b} [\arg6], [x3], x1
st3 {\arg3\().b, \arg4\().b, \arg5\().b} [\arg6], [x0], x1
.endm
.macro LOAD_CHROMA_DATA_4 arg0, arg1, arg2, arg3, arg4, arg5
ld4 {\arg0\().b, \arg1\().b, \arg2\().b, \arg3\().b} [\arg5], [\arg4], x2
.endm
.macro STORE_CHROMA_DATA_2 arg0, arg1, arg2, arg3
st2 {\arg0\().b, \arg1\().b} [\arg3], [\arg2], x2
.endm
.macro ZERO_JUMP_END arg0, arg1, arg2, arg3
mov \arg1, \arg0\().d[0]
mov \arg2, \arg0\().d[1]
orr \arg1, \arg1, \arg2
cbz \arg1, \arg3
.endm
.macro BS_NZC_CHECK arg0, arg1, arg2, arg3, arg4
ld1 {v0.16b}, [\arg0]
//Arrange the input data --- TOP
ands x6, \arg1, #2
cbz x6, bs_nzc_check_jump0
sub x6, \arg0, \arg2, lsl #4
sub x6, x6, \arg2, lsl #3
add x6, x6, #12
ld1 {v1.s} [3], [x6]
bs_nzc_check_jump0:
ext v1.16b, v1.16b, v0.16b, #12
add \arg3\().16b, v0.16b, v1.16b
// Arrange the input data --- LEFT
ands x6, \arg1, #1
cbz x6, bs_nzc_check_jump1
sub x6, \arg0, #21
add x7, x6, #4
ld1 {v1.b} [12], [x6]
add x6, x7, #4
ld1 {v1.b} [13], [x7]
add x7, x6, #4
ld1 {v1.b} [14], [x6]
ld1 {v1.b} [15], [x7]
bs_nzc_check_jump1:
ins v2.d[0], v0.d[1]
zip1 v0.16b, v0.16b, v2.16b
ins v2.d[0], v0.d[1]
zip1 v0.16b, v0.16b, v2.16b
ext v1.16b, v1.16b, v0.16b, #12
add \arg4\().16b, v0.16b, v1.16b
.endm
.macro BS_COMPARE_MV arg0, arg1, arg2, arg3, arg4, arg5
//in: \arg0,\arg1(const),\arg2(const),\arg3(const),\arg4(const); out:\arg5
mov w6, #4
sabd v20.8h, \arg0\().8h, \arg1\().8h
sabd v21.8h, \arg1\().8h, \arg2\().8h
dup \arg0\().8h, w6
sabd v22.8h, \arg2\().8h, \arg3\().8h
sabd v23.8h, \arg3\().8h, \arg4\().8h
cmge v20.8h, v20.8h, \arg0\().8h
cmge v21.8h, v21.8h, \arg0\().8h
cmge v22.8h, v22.8h, \arg0\().8h
cmge v23.8h, v23.8h, \arg0\().8h
addp v20.8h, v20.8h, v21.8h
addp v21.8h, v22.8h, v23.8h
addhn \arg5\().8b, v20.8h, v20.8h
addhn2 \arg5\().16b, v21.8h, v21.8h
.endm
.macro BS_MV_CHECK arg0, arg1, arg2, arg3, arg4, arg5, arg6
ldp q0, q1, [\arg0], #32
ldp q2, q3, [\arg0]
sub \arg0, \arg0, #32
// Arrenge the input data --- TOP
ands x6, \arg1, #2
cbz x6, bs_mv_check_jump0
sub x6, \arg0, \arg2, lsl #6
add x6, x6, #48
ld1 {v4.16b}, [x6]
bs_mv_check_jump0:
BS_COMPARE_MV v4, v0, v1, v2, v3, \arg3
// Arrange the input data --- LEFT
ands x6, \arg1, #1
cbz x6, bs_mv_check_jump1
sub x6, \arg0, #52
add x7, x6, #16
ld1 {v4.s} [0], [x6]
add x6, x7, #16
ld1 {v4.s} [1], [x7]
add x7, x6, #16
ld1 {v4.s} [2], [x6]
ld1 {v4.s} [3], [x7]
bs_mv_check_jump1:
zip1 \arg5\().4s, v0.4s, v2.4s
zip2 \arg6\().4s, v0.4s, v2.4s
zip1 v0.4s, v1.4s, v3.4s
zip2 v2.4s, v1.4s, v3.4s
zip2 v1.4s, \arg5\().4s, v0.4s
zip1 v0.4s, \arg5\().4s, v0.4s
zip2 v3.4s, \arg6\().4s, v2.4s
zip1 v2.4s, \arg6\().4s, v2.4s
BS_COMPARE_MV v4, v0, v1, v2, v3, \arg4
.endm
WELS_ASM_AARCH64_FUNC_BEGIN WelsNonZeroCount_AArch64_neon
mov w1, #1
dup v3.8b, w1
ld1 {v0.8b, v1.8b, v2.8b}, [x0]
umin v0.8b, v0.8b, v3.8b
umin v1.8b, v1.8b, v3.8b
umin v2.8b, v2.8b, v3.8b
st1 {v0.8b, v1.8b, v2.8b}, [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockLumaLt4V_AArch64_neon //uint8_t* pPix, int32_t iStride, int32_t iAlpha, int32_t iBeta, int8_t* tc
dup v16.16b, w2 //alpha
dup v17.16b, w3 //beta
SIGN_EXTENSION x1,w1
add x2, x1, x1, lsl #1
sub x2, x0, x2
movi v23.16b, #128
ld1 {v0.16b}, [x2], x1
ld1 {v1.16b}, [x2], x1
ld1 {v2.16b}, [x2]
ld1 {v3.16b}, [x0], x1
ld1 {v4.16b}, [x0], x1
ld1 {v5.16b}, [x0]
sub x2, x2, x1
ld4r {v18.8b, v19.8b, v20.8b, v21.8b}, [x4]
trn1 v18.2s, v18.2s, v19.2s
trn1 v20.2s, v20.2s, v21.2s
trn1 v6.2d, v18.2d, v20.2d // iTc0: 0000, 1111, 2222, 3333
cmge v7.16b, v6.16b, #0 // iTc0 Flag
MASK_MATRIX v1, v2, v3, v4, v16, v17, v18
and v7.16b, v7.16b, v18.16b // need filter flag
ZERO_JUMP_END v7, x3, x4, DeblockLumaLt4V_AArch64_neon_end
eor v18.16b, v18.16b, v18.16b
sub v18.16b, v18.16b, v6.16b // -iTc0: 0000, 1111, 2222, 3333
DIFF_LUMA_LT4_P1_Q1 v0, v1, v2, v3, v17, v18, v6, v7, v19, v20
st1 {v19.16b}, [x2], x1
DIFF_LUMA_LT4_P1_Q1 v5, v4, v3, v2, v17, v18, v6, v7, v21, v22
abs v20.16b, v20.16b
abs v22.16b, v22.16b
add v6.16b, v6.16b, v20.16b
add v6.16b, v6.16b, v22.16b
eor v18.16b, v18.16b, v18.16b
sub v18.16b, v18.16b, v6.16b
DIFF_LUMA_LT4_P0_Q0_1 v1, v2, v3, v4, v19, v20, v22
DIFF_LUMA_LT4_P0_Q0_2 v1, v2, v3, v4, v19, v20, v22
smax v19.16b, v19.16b, v18.16b
smin v19.16b, v19.16b, v6.16b
and v19.16b, v19.16b, v7.16b
EXTRACT_DELTA_INTO_TWO_PART v19, v20
uqadd v2.16b, v2.16b, v20.16b
uqsub v2.16b, v2.16b, v19.16b
st1 {v2.16b}, [x2], x1
uqsub v3.16b, v3.16b, v20.16b
uqadd v3.16b, v3.16b, v19.16b
st1 {v3.16b}, [x2], x1
st1 {v21.16b}, [x2]
DeblockLumaLt4V_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockLumaEq4V_AArch64_neon
dup v16.16b, w2 //alpha
dup v17.16b, w3 //beta
SIGN_EXTENSION x1,w1
sub x3, x0, x1, lsl #2
ld1 {v0.16b}, [x3], x1
ld1 {v4.16b}, [x0], x1
ld1 {v1.16b}, [x3], x1
ld1 {v5.16b}, [x0], x1
ld1 {v2.16b}, [x3], x1
ld1 {v6.16b}, [x0], x1
ld1 {v3.16b}, [x3]
ld1 {v7.16b}, [x0]
sub x3, x3, x1, lsl #1
MASK_MATRIX v2, v3, v4, v5, v16, v17, v18
lsr w2, w2, #2
add w2, w2, #2
dup v16.16b, w2 //((alpha >> 2) + 2)
uabd v19.16b, v3.16b, v4.16b
cmhi v20.16b, v16.16b, v19.16b //iDetaP0Q0 < ((iAlpha >> 2) + 2)
uabd v21.16b, v1.16b, v3.16b
cmhi v21.16b, v17.16b, v21.16b //bDetaP2P0
and v21.16b, v21.16b, v20.16b //(iDetaP0Q0 < ((iAlpha >> 2) + 2))&&bDetaP2P0
uabd v22.16b, v6.16b, v4.16b
cmhi v22.16b, v17.16b, v22.16b //bDetaQ2Q0
and v22.16b, v22.16b, v20.16b //(iDetaP0Q0 < ((iAlpha >> 2) + 2))&&bDetaQ2Q0
and v20.16b, v20.16b, v18.16b //(iDetaP0Q0 < iAlpha) && bDetaP1P0 && bDetaQ1Q0&&(iDetaP0Q0 < ((iAlpha >> 2) + 2))
mov v23.16b, v21.16b
mov v24.16b, v21.16b
mov v25.16b, v0.16b
DIFF_LUMA_EQ4_P2P1P0_1 v0, v1, v2, v3, v4, v5, v23, v19, v17, v16
DIFF_LUMA_EQ4_P2P1P0_2 v25, v1, v2, v3, v4, v5, v24, v19, v17, v16
ins v0.d[1], v25.d[1]
ins v23.d[1], v24.d[1]
and v21.16b, v20.16b, v21.16b
DIFF_LUMA_EQ4_MASK v19, v1, v21, v17
st1 {v17.16b}, [x3], x1
DIFF_LUMA_EQ4_MASK v0, v2, v21, v17
st1 {v17.16b}, [x3], x1
DIFF_LUMA_EQ4_MASK v23, v3, v18, v17
st1 {v17.16b}, [x3], x1
mov v23.16b, v22.16b
mov v24.16b, v22.16b
mov v25.16b, v7.16b
DIFF_LUMA_EQ4_P2P1P0_1 v7, v6, v5, v4, v3, v2, v23, v19, v17, v16
DIFF_LUMA_EQ4_P2P1P0_2 v25, v6, v5, v4, v3, v2, v24, v19, v17, v16
ins v7.d[1], v25.d[1]
ins v23.d[1], v24.d[1]
and v22.16b, v20.16b, v22.16b
DIFF_LUMA_EQ4_MASK v23, v4, v18, v17
st1 {v17.16b}, [x3], x1
DIFF_LUMA_EQ4_MASK v7, v5, v22, v17
st1 {v17.16b}, [x3], x1
DIFF_LUMA_EQ4_MASK v19, v6, v22, v17
st1 {v17.16b}, [x3], x1
DeblockLumaEq4V_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockLumaLt4H_AArch64_neon //uint8_t* pPix, int32_t iStride, int32_t iAlpha, int32_t iBeta, int8_t* tc
dup v16.16b, w2 //alpha
dup v17.16b, w3 //beta
sub x2, x0, #3
movi v23.16b, #128
SIGN_EXTENSION x1,w1
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 0
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 1
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 2
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 3
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 4
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 5
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 6
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 7
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 8
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 9
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 10
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 11
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 12
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 13
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 14
LOAD_LUMA_DATA_3 v0, v1, v2, v3, v4, v5, 15
sub x0, x0, x1, lsl #4
ld4r {v18.8b, v19.8b, v20.8b, v21.8b}, [x4]
trn1 v18.2s, v18.2s, v19.2s
trn1 v20.2s, v20.2s, v21.2s
trn1 v6.2d, v18.2d, v20.2d // iTc0: 0000, 1111, 2222, 3333
cmge v7.16b, v6.16b, #0 // iTc0 Flag
MASK_MATRIX v1, v2, v3, v4, v16, v17, v18
and v7.16b, v7.16b, v18.16b // need filter flag
ZERO_JUMP_END v7, x3, x4, DeblockLumaLt4H_AArch64_neon_end
eor v18.16b, v18.16b, v18.16b
sub v18.16b, v18.16b, v6.16b // -iTc0: 0000, 1111, 2222, 3333
DIFF_LUMA_LT4_P1_Q1 v0, v1, v2, v3, v17, v18, v6, v7, v19, v20 //Use Tmp v23,v24
mov v25.16b, v19.16b
DIFF_LUMA_LT4_P1_Q1 v5, v4, v3, v2, v17, v18, v6, v7, v21, v22 //Use Tmp v23,v24
abs v20.16b, v20.16b
abs v22.16b, v22.16b
add v6.16b, v6.16b, v20.16b
add v6.16b, v6.16b, v22.16b
eor v18.16b, v18.16b, v18.16b
sub v18.16b, v18.16b, v6.16b
DIFF_LUMA_LT4_P0_Q0_1 v1, v2, v3, v4, v19, v20, v22
DIFF_LUMA_LT4_P0_Q0_2 v1, v2, v3, v4, v19, v20, v22
smax v19.16b, v19.16b, v18.16b
smin v19.16b, v19.16b, v6.16b
and v19.16b, v19.16b, v7.16b
EXTRACT_DELTA_INTO_TWO_PART v19, v20
uqadd v2.16b, v2.16b, v20.16b
uqsub v2.16b, v2.16b, v19.16b
mov v26.16b, v2.16b
uqsub v3.16b, v3.16b, v20.16b
uqadd v3.16b, v3.16b, v19.16b
mov v27.16b, v3.16b
mov v28.16b, v21.16b
sub x0, x0, #2
add x2, x0, x1
lsl x1, x1, #1
STORE_LUMA_DATA_4 v25, v26, v27, v28, 0, 1
STORE_LUMA_DATA_4 v25, v26, v27, v28, 2, 3
STORE_LUMA_DATA_4 v25, v26, v27, v28, 4, 5
STORE_LUMA_DATA_4 v25, v26, v27, v28, 6, 7
STORE_LUMA_DATA_4 v25, v26, v27, v28, 8, 9
STORE_LUMA_DATA_4 v25, v26, v27, v28, 10, 11
STORE_LUMA_DATA_4 v25, v26, v27, v28, 12, 13
STORE_LUMA_DATA_4 v25, v26, v27, v28, 14, 15
DeblockLumaLt4H_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockLumaEq4H_AArch64_neon
dup v16.16b, w2 //alpha
dup v17.16b, w3 //beta
sub x3, x0, #4
SIGN_EXTENSION x1,w1
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 0
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 1
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 2
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 3
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 4
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 5
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 6
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 7
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 8
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 9
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 10
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 11
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 12
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 13
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 14
LOAD_LUMA_DATA_4 v0, v1, v2, v3, v4, v5, v6, v7, 15
sub x0, x0, x1, lsl #4
sub x3, x0, #3
MASK_MATRIX v2, v3, v4, v5, v16, v17, v18
ZERO_JUMP_END v18, x4, x5, DeblockLumaEq4H_AArch64_neon_end
lsr w2, w2, #2
add w2, w2, #2
dup v16.16b, w2 //((alpha >> 2) + 2)
uabd v19.16b, v3.16b, v4.16b
cmhi v20.16b, v16.16b, v19.16b //iDetaP0Q0 < ((iAlpha >> 2) + 2)
uabd v21.16b, v1.16b, v3.16b
cmhi v21.16b, v17.16b, v21.16b //bDetaP2P0
and v21.16b, v21.16b, v20.16b //(iDetaP0Q0 < ((iAlpha >> 2) + 2))&&bDetaP2P0
uabd v22.16b, v6.16b, v4.16b
cmhi v22.16b, v17.16b, v22.16b //bDetaQ2Q0
and v22.16b, v22.16b, v20.16b //(iDetaP0Q0 < ((iAlpha >> 2) + 2))&&bDetaQ2Q0
and v20.16b, v20.16b, v18.16b //(iDetaP0Q0 < iAlpha) && bDetaP1P0 && bDetaQ1Q0&&(iDetaP0Q0 < ((iAlpha >> 2) + 2))
mov v23.16b, v21.16b
mov v24.16b, v21.16b
mov v25.16b, v0.16b
DIFF_LUMA_EQ4_P2P1P0_1 v0, v1, v2, v3, v4, v5, v23, v19, v17, v16
DIFF_LUMA_EQ4_P2P1P0_2 v25, v1, v2, v3, v4, v5, v24, v19, v17, v16
ins v0.d[1], v25.d[1]
ins v23.d[1], v24.d[1]
and v21.16b, v20.16b, v21.16b
DIFF_LUMA_EQ4_MASK v19, v1, v21, v17
mov v26.16b, v17.16b
DIFF_LUMA_EQ4_MASK v0, v2, v21, v17
mov v27.16b, v17.16b
DIFF_LUMA_EQ4_MASK v23, v3, v18, v17
mov v28.16b, v17.16b
mov v23.16b, v22.16b
mov v24.16b, v22.16b
mov v25.16b, v7.16b
DIFF_LUMA_EQ4_P2P1P0_1 v7, v6, v5, v4, v3, v2, v23, v19, v17, v16
DIFF_LUMA_EQ4_P2P1P0_2 v25, v6, v5, v4, v3, v2, v24, v19, v17, v16
ins v7.d[1], v25.d[1]
ins v23.d[1], v24.d[1]
and v22.16b, v20.16b, v22.16b
DIFF_LUMA_EQ4_MASK v23, v4, v18, v17
mov v29.16b, v17.16b
DIFF_LUMA_EQ4_MASK v7, v5, v22, v17
mov v30.16b, v17.16b
DIFF_LUMA_EQ4_MASK v19, v6, v22, v17
mov v31.16b, v17.16b
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 0
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 1
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 2
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 3
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 4
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 5
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 6
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 7
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 8
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 9
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 10
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 11
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 12
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 13
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 14
STORE_LUMA_DATA_3 v26, v27, v28, v29, v30, v31, 15
DeblockLumaEq4H_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockChromaLt4V_AArch64_neon //uint8_t* pPixCb, uint8_t* pPixCr, int32_t iStrideX, int32_t iAlpha, int32_t iBeta, int8_t* pTc
dup v16.16b, w3 //alpha
dup v17.16b, w4 //beta
lsl x3, x2, #1
sub x6, x0, x3 //pPixCb-2*Stride
sub x7, x1, x3 //pPixCr-2*Stride
ld1 {v0.d} [0], [x6], x2
ld1 {v1.d} [0], [x6]
ld1 {v2.d} [0], [x0], x2
ld1 {v3.d} [0], [x0]
ld1 {v0.d} [1], [x7], x2
ld1 {v1.d} [1], [x7]
ld1 {v2.d} [1], [x1], x2
ld1 {v3.d} [1], [x1]
ld4r {v18.8b, v19.8b, v20.8b, v21.8b}, [x5]
trn1 v18.4h, v18.4h, v19.4h //0011,0011,
trn1 v20.4h, v20.4h, v21.4h //2233,2233
zip1 v6.4s, v18.4s, v20.4s //iTc0: 0011,2233,0011,2233
cmgt v7.16b, v6.16b, #0 // iTc0 Flag
MASK_MATRIX v0, v1, v2, v3, v16, v17, v18
and v7.16b, v7.16b, v18.16b // need filter flag
ZERO_JUMP_END v7, x4, x5, DeblockChromaLt4V_AArch64_neon_end
eor v18.16b, v18.16b, v18.16b
sub v18.16b, v18.16b, v6.16b //-iTc0: 0011,2233,0011,2233
DIFF_LUMA_LT4_P0_Q0_1 v0, v1, v2, v3, v19, v20, v22
DIFF_LUMA_LT4_P0_Q0_2 v0, v1, v2, v3, v19, v20, v22
smax v19.16b, v19.16b, v18.16b
smin v19.16b, v19.16b, v6.16b
and v19.16b, v19.16b, v7.16b
EXTRACT_DELTA_INTO_TWO_PART v19, v20
uqadd v1.16b, v1.16b, v20.16b
uqsub v1.16b, v1.16b, v19.16b
st1 {v1.d} [0], [x6], x2
st1 {v1.d} [1], [x7], x2
uqsub v2.16b, v2.16b, v20.16b
uqadd v2.16b, v2.16b, v19.16b
st1 {v2.d} [0], [x6]
st1 {v2.d} [1], [x7]
DeblockChromaLt4V_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockChromaLt4H_AArch64_neon //uint8_t* pPixCb, uint8_t* pPixCr, int32_t iStrideX, int32_t iAlpha, int32_t iBeta, int8_t* pTc
dup v16.16b, w3 //alpha
dup v17.16b, w4 //beta
sub x6, x0, #2 //pPixCb-2
sub x7, x1, #2 //pPixCr-2
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 0
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 1
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 2
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 3
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 4
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 5
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 6
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 7
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 8
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 9
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 10
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 11
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 12
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 13
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 14
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 15
sub x0, x0, #1
sub x1, x1, #1
ld4r {v18.8b, v19.8b, v20.8b, v21.8b}, [x5]
trn1 v18.4h, v18.4h, v19.4h //0011,0011,
trn1 v20.4h, v20.4h, v21.4h //2233,2233
zip1 v6.4s, v18.4s, v20.4s //iTc0: 0011,2233,0011,2233
cmgt v7.16b, v6.16b, #0 // iTc0 Flag
MASK_MATRIX v0, v1, v2, v3, v16, v17, v18
and v7.16b, v7.16b, v18.16b // need filter flag
ZERO_JUMP_END v7, x4, x5, DeblockChromaLt4H_AArch64_neon_end
eor v18.16b, v18.16b, v18.16b
sub v18.16b, v18.16b, v6.16b //-iTc0: 0011,2233,0011,2233
DIFF_LUMA_LT4_P0_Q0_1 v0, v1, v2, v3, v19, v20, v22
DIFF_LUMA_LT4_P0_Q0_2 v0, v1, v2, v3, v19, v20, v22
smax v19.16b, v19.16b, v18.16b
smin v19.16b, v19.16b, v6.16b
and v19.16b, v19.16b, v7.16b
EXTRACT_DELTA_INTO_TWO_PART v19, v20
uqadd v1.16b, v1.16b, v20.16b
uqsub v1.16b, v1.16b, v19.16b
uqsub v2.16b, v2.16b, v20.16b
uqadd v2.16b, v2.16b, v19.16b
STORE_CHROMA_DATA_2 v1, v2, x0, 0
STORE_CHROMA_DATA_2 v1, v2, x0, 1
STORE_CHROMA_DATA_2 v1, v2, x0, 2
STORE_CHROMA_DATA_2 v1, v2, x0, 3
STORE_CHROMA_DATA_2 v1, v2, x0, 4
STORE_CHROMA_DATA_2 v1, v2, x0, 5
STORE_CHROMA_DATA_2 v1, v2, x0, 6
STORE_CHROMA_DATA_2 v1, v2, x0, 7
STORE_CHROMA_DATA_2 v1, v2, x1, 8
STORE_CHROMA_DATA_2 v1, v2, x1, 9
STORE_CHROMA_DATA_2 v1, v2, x1, 10
STORE_CHROMA_DATA_2 v1, v2, x1, 11
STORE_CHROMA_DATA_2 v1, v2, x1, 12
STORE_CHROMA_DATA_2 v1, v2, x1, 13
STORE_CHROMA_DATA_2 v1, v2, x1, 14
STORE_CHROMA_DATA_2 v1, v2, x1, 15
DeblockChromaLt4H_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockChromaEq4V_AArch64_neon //uint8_t* pPixCb, uint8_t* pPixCr, int32_t iStrideX, int32_t iAlpha, int32_t iBeta
dup v16.16b, w3 //alpha
dup v17.16b, w4 //beta
lsl x3, x2, #1
sub x6, x0, x3 //pPixCb-2*Stride
sub x7, x1, x3 //pPixCr-2*Stride
ld1 {v0.d} [0], [x6], x2
ld1 {v1.d} [0], [x6]
ld1 {v2.d} [0], [x0], x2
ld1 {v3.d} [0], [x0]
ld1 {v0.d} [1], [x7], x2
ld1 {v1.d} [1], [x7]
ld1 {v2.d} [1], [x1], x2
ld1 {v3.d} [1], [x1]
MASK_MATRIX v0, v1, v2, v3, v16, v17, v7
ZERO_JUMP_END v7, x3, x4, DeblockChromaEq4V_AArch64_neon_end
DIFF_CHROMA_EQ4_P0Q0_1 v0, v1, v2, v3, v18, v19, v20, v21
DIFF_CHROMA_EQ4_P0Q0_2 v0, v1, v2, v3, v18, v19, v20, v21
mov v6.16b, v7.16b
bsl v6.16b, v20.16b, v1.16b
bsl v7.16b, v21.16b, v2.16b
st1 {v6.d} [0], [x6], x2
st1 {v6.d} [1], [x7], x2
st1 {v7.d} [0], [x6]
st1 {v7.d} [1], [x7]
DeblockChromaEq4V_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockChromaEq4H_AArch64_neon //uint8_t* pPixCb, uint8_t* pPixCr, int32_t iStrideX, int32_t iAlpha, int32_t iBeta
dup v16.16b, w3 //alpha
dup v17.16b, w4 //beta
sub x6, x0, #2 //pPixCb-2
sub x7, x1, #2 //pPixCr-2
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 0
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 1
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 2
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 3
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 4
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 5
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 6
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x6, 7
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 8
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 9
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 10
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 11
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 12
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 13
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 14
LOAD_CHROMA_DATA_4 v0, v1, v2, v3, x7, 15
sub x0, x0, #1
sub x1, x1, #1
MASK_MATRIX v0, v1, v2, v3, v16, v17, v7
ZERO_JUMP_END v7, x3, x4, DeblockChromaEq4H_AArch64_neon_end
DIFF_CHROMA_EQ4_P0Q0_1 v0, v1, v2, v3, v18, v19, v20, v21
DIFF_CHROMA_EQ4_P0Q0_2 v0, v1, v2, v3, v18, v19, v20, v21
mov v6.16b, v7.16b
bsl v6.16b, v20.16b, v1.16b
bsl v7.16b, v21.16b, v2.16b
STORE_CHROMA_DATA_2 v6, v7, x0, 0
STORE_CHROMA_DATA_2 v6, v7, x0, 1
STORE_CHROMA_DATA_2 v6, v7, x0, 2
STORE_CHROMA_DATA_2 v6, v7, x0, 3
STORE_CHROMA_DATA_2 v6, v7, x0, 4
STORE_CHROMA_DATA_2 v6, v7, x0, 5
STORE_CHROMA_DATA_2 v6, v7, x0, 6
STORE_CHROMA_DATA_2 v6, v7, x0, 7
STORE_CHROMA_DATA_2 v6, v7, x1, 8
STORE_CHROMA_DATA_2 v6, v7, x1, 9
STORE_CHROMA_DATA_2 v6, v7, x1, 10
STORE_CHROMA_DATA_2 v6, v7, x1, 11
STORE_CHROMA_DATA_2 v6, v7, x1, 12
STORE_CHROMA_DATA_2 v6, v7, x1, 13
STORE_CHROMA_DATA_2 v6, v7, x1, 14
STORE_CHROMA_DATA_2 v6, v7, x1, 15
DeblockChromaEq4H_AArch64_neon_end:
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DeblockingBSCalcEnc_AArch64_neon
// Checking the nzc status
BS_NZC_CHECK x0, x2, x3, v16, v17 //v16,v17 save the nzc status
// For checking bS[I] = 2
movi v0.16b, #0
cmgt v16.16b, v16.16b, v0.16b
cmgt v17.16b, v17.16b, v0.16b
movi v0.16b, #2
and v16.16b, v16.16b, v0.16b //v16 save the nzc check result all the time --- for dir is top
and v17.16b, v17.16b, v0.16b //v17 save the nzc check result all the time --- for dir is left
// Checking the mv status
BS_MV_CHECK x1, x2, x3, v18, v19, v5 , v6 //v18, v19 save the mv status
// For checking bS[I] = 1
movi v0.16b, #1
and v18.16b, v18.16b, v0.16b //v18 save the nzc check result all the time --- for dir is top
and v19.16b, v19.16b, v0.16b //v19 save the nzc check result all the time --- for dir is left
// Check bS[I] is '1' or '2'
umax v1.16b, v18.16b, v16.16b
umax v0.16b, v19.16b, v17.16b
st1 {v0.16b, v1.16b}, [x4]
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,028 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm64/arm_arch64_common_macro.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef __APPLE__
.text
.macro WELS_ASM_AARCH64_FUNC_BEGIN
.align 2
.globl _$0
_$0:
.endm
.macro WELS_ASM_AARCH64_FUNC_END
ret
.endm
#else
.section .note.GNU-stack,"",%progbits // Mark stack as non-executable
.text
.macro WELS_ASM_AARCH64_FUNC_BEGIN funcName
.align 2
.global \funcName
.type \funcName, %function
#ifndef __clang__
.func \funcName
#endif
\funcName:
.endm
.macro WELS_ASM_AARCH64_FUNC_END
ret
#ifndef __clang__
.endfunc
#endif
.endm
#endif
.macro SIGN_EXTENSION arg0, arg1
sxtw \arg0, \arg1
.endm
|
xiangxud/webrtc_H265player | 4,382 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm64/expand_picture_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
//void ExpandPictureLuma_AArch64_neon (uint8_t* pDst, const int32_t kiStride, const int32_t kiPicW, const int32_t kiPicH);
WELS_ASM_AARCH64_FUNC_BEGIN ExpandPictureLuma_AArch64_neon
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x2,w2
SIGN_EXTENSION x3,w3
mov x7, x0
mov x8, x3
add x4, x7, x2
sub x4, x4, #1
mov x10, #16
//For the left and right expand
_expand_picture_luma_loop2:
sub x5, x7, #32
add x6, x4, #1
ld1r {v0.16b}, [x7], x1
ld1r {v2.16b}, [x4], x1
mov v1.16b, v0.16b
mov v3.16b, v2.16b
st2 {v0.16b, v1.16b}, [x5]
st2 {v2.16b, v3.16b}, [x6]
sub x8, x8, #1
cbnz x8, _expand_picture_luma_loop2
//for the top and bottom expand
add x2, x2, #64
sub x0, x0, #32
madd x4, x1, x3, x0
sub x4, x4, x1
_expand_picture_luma_loop0:
mov x5, #32
msub x5, x5, x1, x0
add x6, x4, x1
ld1 {v0.16b}, [x0], x10
ld1 {v1.16b}, [x4], x10
mov x8, #32
_expand_picture_luma_loop1:
st1 {v0.16b}, [x5], x1
st1 {v1.16b}, [x6], x1
sub x8, x8, #1
cbnz x8, _expand_picture_luma_loop1
sub x2, x2, #16
cbnz x2, _expand_picture_luma_loop0
WELS_ASM_AARCH64_FUNC_END
//void ExpandPictureChroma_AArch64_neon (uint8_t* pDst, const int32_t kiStride, const int32_t kiPicW,
// const int32_t kiPicH);
WELS_ASM_AARCH64_FUNC_BEGIN ExpandPictureChroma_AArch64_neon
//Save the dst
SIGN_EXTENSION x1,w1
SIGN_EXTENSION x2,w2
SIGN_EXTENSION x3,w3
mov x7, x0
mov x8, x3
mov x10, #16
add x4, x7, x2
sub x4, x4, #1
//For the left and right expand
_expand_picture_chroma_loop2:
sub x5, x7, #16
add x6, x4, #1
ld1r {v0.16b}, [x7], x1
ld1r {v1.16b}, [x4], x1
st1 {v0.16b}, [x5]
st1 {v1.16b}, [x6]
sub x8, x8, #1
cbnz x8, _expand_picture_chroma_loop2
//for the top and bottom expand
add x2, x2, #32
//
mov x9, x2
mov x11, #15
bic x2, x2, x11
//
sub x0, x0, #16
madd x4, x1, x3, x0
sub x4, x4, x1
_expand_picture_chroma_loop0:
mov x5, #16
msub x5, x5, x1, x0
add x6, x4, x1
ld1 {v0.16b}, [x0], x10
ld1 {v1.16b}, [x4], x10
mov x8, #16
_expand_picture_chroma_loop1:
st1 {v0.16b}, [x5], x1
st1 {v1.16b}, [x6], x1
sub x8, x8, #1
cbnz x8, _expand_picture_chroma_loop1
sub x2, x2, #16
cbnz x2, _expand_picture_chroma_loop0
and x9, x9, #15
sub x9, x9, #8
cbnz x9, _expand_picture_chroma_end
mov x5, #16
msub x5, x5, x1, x0
add x6, x4, x1
ld1 {v0.8b}, [x0]
ld1 {v1.8b}, [x4]
mov x8, #16
_expand_picture_chroma_loop3:
st1 {v0.8b}, [x5], x1
st1 {v1.8b}, [x6], x1
sub x8, x8, #1
cbnz x8, _expand_picture_chroma_loop3
_expand_picture_chroma_end:
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,211 | test/prod_decoder/codec/3rdparty/openh264/codec/common/arm64/intra_pred_common_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
//for Luma 16x16
//void WelsI16x16LumaPredV_AArch64_neon (uint8_t* pPred, uint8_t* pRef, const int32_t kiStride);
WELS_ASM_AARCH64_FUNC_BEGIN WelsI16x16LumaPredV_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, x2
ld1 {v0.16b}, [x3]
.rept 16
st1 {v0.16b}, [x0], 16
.endr
WELS_ASM_AARCH64_FUNC_END
//void WelsI16x16LumaPredH_AArch64_neon (uint8_t* pPred, uint8_t* pRef, const int32_t kiStride);
WELS_ASM_AARCH64_FUNC_BEGIN WelsI16x16LumaPredH_AArch64_neon
SIGN_EXTENSION x2,w2
sub x3, x1, #1
.rept 16
ld1r {v0.16b}, [x3], x2
st1 {v0.16b}, [x0], 16
.endr
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 16,716 | test/prod_decoder/codec/3rdparty/openh264/codec/decoder/core/arm/intra_pred_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
//Global macro
#include "arm_arch_common_macro.S"
//Global macro
.macro GET_8BYTE_DATA arg0, arg1, arg2
vld1.8 {\arg0[0]}, [\arg1], \arg2
vld1.8 {\arg0[1]}, [\arg1], \arg2
vld1.8 {\arg0[2]}, [\arg1], \arg2
vld1.8 {\arg0[3]}, [\arg1], \arg2
vld1.8 {\arg0[4]}, [\arg1], \arg2
vld1.8 {\arg0[5]}, [\arg1], \arg2
vld1.8 {\arg0[6]}, [\arg1], \arg2
vld1.8 {\arg0[7]}, [\arg1], \arg2
.endm
WELS_ASM_FUNC_BEGIN WelsDecoderI16x16LumaPredV_neon
//Get the top line data to 'q0'
sub r2, r0, r1
vldm r2, {d0, d1}
mov r2, r0
mov r3, #4
//Set the top line to the each line of MB(16*16)
loop_0_get_i16x16_luma_pred_v:
vst1.8 {d0,d1}, [r2], r1
vst1.8 {d0,d1}, [r2], r1
vst1.8 {d0,d1}, [r2], r1
vst1.8 {d0,d1}, [r2], r1
subs r3, #1
bne loop_0_get_i16x16_luma_pred_v
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI16x16LumaPredH_neon
sub r2, r0, #1
mov r3, #4
loop_0_get_i16x16_luma_pred_h:
//Get one byte data from left side
vld1.8 {d0[],d1[]}, [r2], r1
vld1.8 {d2[],d3[]}, [r2], r1
vld1.8 {d4[],d5[]}, [r2], r1
vld1.8 {d6[],d7[]}, [r2], r1
//Set the line of MB using the left side byte data
vst1.8 {d0,d1}, [r0], r1
vst1.8 {d2,d3}, [r0], r1
vst1.8 {d4,d5}, [r0], r1
vst1.8 {d6,d7}, [r0], r1
subs r3, #1
bne loop_0_get_i16x16_luma_pred_h
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI16x16LumaPredDc_neon
//stmdb sp!, { r2-r5, lr}
//Get the left vertical line data
sub r2, r0, #1
GET_8BYTE_DATA d0, r2, r1
GET_8BYTE_DATA d1, r2, r1
//Get the top horizontal line data
sub r2, r0, r1
vldm r2, {d2, d3}
//Calculate the sum of top horizontal line data and vertical line data
vpaddl.u8 q0, q0
vpaddl.u8 q1, q1
vadd.u16 q0, q0, q1
vadd.u16 d0, d0, d1
vpaddl.u16 d0, d0
vpaddl.u32 d0, d0
//Calculate the mean value
vrshr.u16 d0, d0, #5
vdup.8 q0, d0[0]
//Set the mean value to the all of member of MB
mov r2, #4
loop_0_get_i16x16_luma_pred_dc_both:
vst1.8 {d0,d1}, [r0], r1
vst1.8 {d0,d1}, [r0], r1
vst1.8 {d0,d1}, [r0], r1
vst1.8 {d0,d1}, [r0], r1
subs r2, #1
bne loop_0_get_i16x16_luma_pred_dc_both
WELS_ASM_FUNC_END
//The table for SIMD instruction {(8,7,6,5,4,3,2,1) * 5}
CONST0_GET_I16X16_LUMA_PRED_PLANE: .long 0x191e2328, 0x050a0f14
//The table for SIMD instruction {-7,-6,-5,-4,-3,-2,-1,0}
CONST1_GET_I16X16_LUMA_PRED_PLANE: .long 0xfcfbfaf9, 0x00fffefd
WELS_ASM_FUNC_BEGIN WelsDecoderI16x16LumaPredPlane_neon
//stmdb sp!, { r2-r5, lr}
//Load the table {(8,7,6,5,4,3,2,1) * 5}
adr r2, CONST0_GET_I16X16_LUMA_PRED_PLANE
vldr d0, [r2]
//Pack the top[-1] ~ top[6] to d1
sub r2, r0, r1
sub r3, r2, #1
vld1.8 d1, [r3]
//Pack the top[8] ~ top[15] to d2
add r3, #9
vld1.8 d2, [r3]
//Save the top[15] to d6 for next step
vdup.u8 d6, d2[7]
//Get and pack left[-1] ~ left[6] to d4
sub r3, r2, #1
GET_8BYTE_DATA d4, r3, r1
//Get and pack left[8] ~ left[15] to d3
add r3, r1
GET_8BYTE_DATA d3, r3, r1
//Save the left[15] to d7 for next step
vdup.u8 d7, d3[7]
//revert the sequence of d2,d3
vrev64.8 q1, q1
vsubl.u8 q2, d3, d4 //q2={left[8]-left[6],left[9]-left[5],left[10]-left[4], ...}
vsubl.u8 q1, d2, d1 //q1={top[8]-top[6],top[9]-top[5],top[10]-top[4], ...}
vmovl.u8 q0, d0
vmul.s16 q1, q0, q1 //q1 = q1*{(8,7,6,5,4,3,2,1) * 5}
vmul.s16 q2, q0, q2 //q2 = q2*{(8,7,6,5,4,3,2,1) * 5}
//Calculate the sum of items of q1, q2
vpadd.s16 d0, d2, d3
vpadd.s16 d1, d4, d5
vpaddl.s16 q0, q0
vpaddl.s32 q0, q0
//Get the value of 'b', 'c' and extend to q1, q2.
vrshr.s64 q0, #6
vdup.s16 q1, d0[0]
vdup.s16 q2, d1[0]
//Load the table {-7,-6,-5,-4,-3,-2,-1,0} to d0
adr r2, CONST1_GET_I16X16_LUMA_PRED_PLANE
vld1.32 {d0}, [r2]
//Get the value of 'a' and save to q3
vaddl.u8 q3, d6, d7
vshl.u16 q3, #4
//calculate a+'b'*{-7,-6,-5,-4,-3,-2,-1,0} + c*{-7}
vmovl.s8 q0, d0
vmla.s16 q3, q0, q1
vmla.s16 q3, q2, d0[0]
//Calculate a+'b'*{1,2,3,4,5,6,7,8} + c*{-7}
vshl.s16 q8, q1, #3
vadd.s16 q8, q3
//right shift 5 bits and rounding
vqrshrun.s16 d0, q3, #5
vqrshrun.s16 d1, q8, #5
//Set the line of MB
vst1.u32 {d0,d1}, [r0], r1
//Do the same processing for setting other lines
mov r2, #15
loop_0_get_i16x16_luma_pred_plane:
vadd.s16 q3, q2
vadd.s16 q8, q2
vqrshrun.s16 d0, q3, #5
vqrshrun.s16 d1, q8, #5
vst1.u32 {d0,d1}, [r0], r1
subs r2, #1
bne loop_0_get_i16x16_luma_pred_plane
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredV_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (4 bytes)
sub r2, r0, r1
ldr r2, [r2]
//Set the luma MB using top line
str r2, [r0], r1
str r2, [r0], r1
str r2, [r0], r1
str r2, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredH_neon
//stmdb sp!, { r2-r5, lr}
//Load the left column (4 bytes)
sub r2, r0, #1
vld1.8 {d0[]}, [r2], r1
vld1.8 {d1[]}, [r2], r1
vld1.8 {d2[]}, [r2], r1
vld1.8 {d3[]}, [r2]
//Set the luma MB using the left side byte
vst1.32 {d0[0]}, [r0], r1
vst1.32 {d1[0]}, [r0], r1
vst1.32 {d2[0]}, [r0], r1
vst1.32 {d3[0]}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredDDL_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row data(8 bytes)
sub r2, r0, r1
vld1.32 {d0}, [r2]
//For "t7 + (t7<<1)"
vdup.8 d1, d0[7]
//calculate "t0+t1,t1+t2,t2+t3...t6+t7,t7+t7"
vext.8 d1, d0, d1, #1
vaddl.u8 q1, d1, d0
//calculate "x,t0+t1+t1+t2,t1+t2+t2+t3,...t5+t6+t6+t7,t6+t7+t7+t7"
vext.8 q2, q1, q1, #14
vadd.u16 q0, q1, q2
//right shift 2 bits and rounding
vqrshrn.u16 d0, q0, #2
//Save "ddl0, ddl1, ddl2, ddl3"
vext.8 d1, d0, d0, #1
vst1.32 d1[0], [r0], r1
//Save "ddl1, ddl2, ddl3, ddl4"
vext.8 d1, d0, d0, #2
vst1.32 d1[0], [r0], r1
//Save "ddl2, ddl3, ddl4, ddl5"
vext.8 d1, d0, d0, #3
vst1.32 d1[0], [r0], r1
//Save "ddl3, ddl4, ddl5, ddl6"
vst1.32 d0[1], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredDDR_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (4 bytes)
sub r2, r0, r1
vld1.32 {d0[1]}, [r2]
//Load the left column (5 bytes)
sub r2, #1
vld1.8 {d0[3]}, [r2], r1
vld1.8 {d0[2]}, [r2], r1
vld1.8 {d0[1]}, [r2], r1
vld1.8 {d0[0]}, [r2], r1
vld1.8 {d1[7]}, [r2] //For packing the right sequence to do SIMD processing
vext.8 d2, d1, d0, #7 //d0:{L2,L1,L0,LT,T0,T1,T2,T3}
//d2:{L3,L2,L1,L0,LT,T0,T1,T2}
//q2:{L2+L3,L1+L2,L0+L1...T1+T2,T2+T3}
vaddl.u8 q2, d2, d0
//q1:{TL0+LT0,LT0+T01,...L12+L23}
vext.8 q3, q3, q2, #14
vadd.u16 q1, q2, q3
//right shift 2 bits and rounding
vqrshrn.u16 d0, q1, #2
//Adjust the data sequence for setting luma MB of 'pred'
vst1.32 d0[1], [r0], r1
vext.8 d0, d0, d0, #7
vst1.32 d0[1], [r0], r1
vext.8 d0, d0, d0, #7
vst1.32 d0[1], [r0], r1
vext.8 d0, d0, d0, #7
vst1.32 d0[1], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredVL_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (8 bytes)
sub r2, r0, r1
vld1.32 {d0}, [r2]
vext.8 d1, d0, d0, #1
vaddl.u8 q1, d1, d0 //q1:{t0+t1,t1+t2,t2+t3...t5+t6,x,x}
vext.8 q2, q1, q1, #2
vadd.u16 q2, q1, q2 //q2:{t0+t1+t1+t2,t1+t2+t2+t3,...t4+t5+t5+t6,x,x}
//calculate the "vl0,vl1,vl2,vl3,vl4"
vqrshrn.u16 d0, q1, #1
//calculate the "vl5,vl6,vl7,vl8,vl9"
vqrshrn.u16 d1, q2, #2
//Adjust the data sequence for setting the luma MB
vst1.32 d0[0], [r0], r1
vst1.32 d1[0], [r0], r1
vext.8 d0, d0, d0, #1
vext.8 d1, d1, d1, #1
vst1.32 d0[0], [r0], r1
vst1.32 d1[0], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredVR_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row (4 bytes)
sub r2, r0, r1
vld1.32 {d0[1]}, [r2]
//Load the left column (4 bytes)
sub r2, #1
vld1.8 {d0[3]}, [r2], r1
vld1.8 {d0[2]}, [r2], r1
vld1.8 {d0[1]}, [r2], r1
vld1.8 {d0[0]}, [r2]
vext.8 d1, d0, d0, #7
vaddl.u8 q1, d0, d1 //q1:{X,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1,T1+T2,T2+T3}
vext.u8 q2, q1, q1, #14
vadd.u16 q2, q2, q1 //q2:{X,L2+L1+L1+L0,L1+L0+L0+LT,...T1+T2+T2+T3}
//Calculate the vr0 ~ vr9
vqrshrn.u16 d1, q2, #2
vqrshrn.u16 d0, q1, #1
//Adjust the data sequence for setting the luma MB
vst1.32 d0[1], [r0], r1
vst1.32 d1[1], [r0], r1
add r2, r0, r1
vst1.8 d1[3], [r0]!
vst1.16 d0[2], [r0]!
vst1.8 d0[6], [r0]!
vst1.8 d1[2], [r2]!
vst1.16 d1[2], [r2]!
vst1.8 d1[6], [r2]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredHU_neon
//stmdb sp!, { r2-r5, lr}
//Load the left column data
sub r2, r0, #1
mov r3, #3
mul r3, r1
add r3, r2
vld1.8 {d0[]}, [r3]
vld1.8 {d0[4]}, [r2], r1
vld1.8 {d0[5]}, [r2], r1
vld1.8 {d0[6]}, [r2], r1 //d0:{L3,L3,L3,L3,L0,L1,L2,L3}
vext.8 d1, d0, d0, #1
vaddl.u8 q2, d0, d1 //q2:{L3+L3,L3+L3,L3+L3,L3+L0,L0+L1,L1+L2,L2+L3,L3+L3}
vext.u8 d2, d5, d4, #2
vadd.u16 d3, d2, d5 //d3:{L0+L1+L1+L2,L1+L2+L2+L3,L2+L3+L3+L3,L3+L3+L3+L3}
//Calculate the hu0 ~ hu5
vqrshrn.u16 d2, q2, #1
vqrshrn.u16 d1, q1, #2
//Adjust the data sequence for setting the luma MB
vzip.8 d2, d1
vst1.32 d1[0], [r0], r1
vext.8 d2, d1, d1, #2
vst1.32 d2[0], [r0], r1
vst1.32 d1[1], [r0], r1
vst1.32 d0[0], [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderI4x4LumaPredHD_neon
//stmdb sp!, { r2-r5, lr}
//Load the data
sub r2, r0, r1
sub r2, #1
vld1.32 {d0[1]}, [r2], r1
vld1.8 {d0[3]}, [r2], r1
vld1.8 {d0[2]}, [r2], r1
vld1.8 {d0[1]}, [r2], r1
vld1.8 {d0[0]}, [r2] //d0:{L3,L2,L1,L0,LT,T0,T1,T2}
vext.8 d1, d0, d0, #7
vaddl.u8 q1, d0, d1 //q1:{x,L3+L2,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1,T1+T2}
vext.u8 q2, q1, q1, #14 //q2:{x,x, L3+L2,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1}
vadd.u16 q3, q2, q1 //q3:{x,x,L3+L2+L2+L1,L2+L1+L1+L0,L1+L0+L0+LT,L0+LT+LT+T0,LT+T0+T0+T1,T0+T1+T1+T2}
//Calculate the hd0~hd9
vqrshrn.u16 d1, q3, #2
vqrshrn.u16 d0, q2, #1
//Adjust the data sequence for setting the luma MB
vmov d3, d1
vtrn.8 d0, d1
vext.u8 d2, d1, d1, #6
vst2.16 {d2[3], d3[3]}, [r0], r1
vst2.16 {d0[2], d1[2]}, [r0], r1
vmov d3, d0
vst2.16 {d2[2], d3[2]}, [r0], r1
vst2.16 {d0[1], d1[1]}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderIChromaPredV_neon
//stmdb sp!, { r2-r5, lr}
//Get the top row (8 byte)
sub r2, r0, r1
vldr d0, [r2]
//Set the chroma MB using top row data
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0], r1
vst1.8 {d0}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderIChromaPredH_neon
//stmdb sp!, { r2-r5, lr}
////Get the left column (8 byte)
sub r2, r0, #1
vld1.8 {d0[]}, [r2], r1
vld1.8 {d1[]}, [r2], r1
vld1.8 {d2[]}, [r2], r1
vld1.8 {d3[]}, [r2], r1
vld1.8 {d4[]}, [r2], r1
vld1.8 {d5[]}, [r2], r1
vld1.8 {d6[]}, [r2], r1
vld1.8 {d7[]}, [r2]
//Set the chroma MB using left column data
vst1.8 {d0}, [r0], r1
vst1.8 {d1}, [r0], r1
vst1.8 {d2}, [r0], r1
vst1.8 {d3}, [r0], r1
vst1.8 {d4}, [r0], r1
vst1.8 {d5}, [r0], r1
vst1.8 {d6}, [r0], r1
vst1.8 {d7}, [r0]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsDecoderIChromaPredDc_neon
//stmdb sp!, { r2-r5, lr}
//Load the left column data (8 bytes)
sub r2, r0, #1
GET_8BYTE_DATA d0, r2, r1
//Load the top row data (8 bytes)
sub r2, r0, r1
vldr d1, [r2]
//Calculate the sum of left column and top row
vpaddl.u8 q0, q0
vpaddl.u16 q0, q0
vadd.u32 d2, d0, d1 //'m1' save to d2
vrshr.u32 q0, q0, #2 //calculate 'm2','m3'
vrshr.u32 d2, d2, #3 //calculate 'm4'
//duplicate the 'mx' to a vector line
vdup.8 d4, d2[0]
vdup.8 d5, d1[4]
vdup.8 d6, d0[4]
vdup.8 d7, d2[4]
//Set the chroma MB
vst2.32 {d4[0],d5[0]}, [r0], r1
vst2.32 {d4[0],d5[0]}, [r0], r1
vst2.32 {d4[0],d5[0]}, [r0], r1
vst2.32 {d4[0],d5[0]}, [r0], r1
vst2.32 {d6[0],d7[0]}, [r0], r1
vst2.32 {d6[0],d7[0]}, [r0], r1
vst2.32 {d6[0],d7[0]}, [r0], r1
vst2.32 {d6[0],d7[0]}, [r0]
WELS_ASM_FUNC_END
//Table {{1,2,3,4,1,2,3,4}*17}
CONST0_GET_I_CHROMA_PRED_PLANE: .long 0x44332211, 0x44332211//0x140f0a05, 0x28231e19
//Table {-3,-2,-1,0,1,2,3,4}
CONST1_GET_I_CHROMA_PRED_PLANE: .long 0xfffefffd, 0x0000ffff,0x00020001,0x00040003
WELS_ASM_FUNC_BEGIN WelsDecoderIChromaPredPlane_neon
//stmdb sp!, { r2-r5, lr}
//Load the top row data
sub r2, r0, #1
sub r2, r1
vld1.32 {d1[0]}, [r2]
add r2, #5
vld1.32 {d0[0]}, [r2]
//Load the left column data
sub r2, #5
vld1.8 {d1[4]}, [r2], r1
vld1.8 {d1[5]}, [r2], r1
vld1.8 {d1[6]}, [r2], r1
vld1.8 {d1[7]}, [r2], r1 //d1:{LT,T0,T1,T2,LT,L0,L1,L2}
add r2, r1
vld1.8 {d0[4]}, [r2], r1
vld1.8 {d0[5]}, [r2], r1
vld1.8 {d0[6]}, [r2], r1
vld1.8 {d0[7]}, [r2] //d0:{T4,T5,T6,T7,L4,L5,L6.L7}
//Save T7 to d3 for next step
vdup.u8 d3, d0[3]
//Save L7 to d4 for next step
vdup.u8 d4, d0[7]
//Calculate the value of 'a' and save to q2
vaddl.u8 q2, d3, d4
vshl.u16 q2, #4
//Load the table {{1,2,3,4,1,2,3,4}*17}
adr r2, CONST0_GET_I_CHROMA_PRED_PLANE
vld1.32 {d2}, [r2]
//Calculate the 'b','c', and save to q0
vrev32.8 d1, d1
vsubl.u8 q0, d0, d1
vmovl.u8 q1, d2
vmul.s16 q0, q1
vpaddl.s16 q0, q0
vpaddl.s32 q0, q0
vrshr.s64 q0, #5
//Load the table {-3,-2,-1,0,1,2,3,4} to q3
adr r2, CONST1_GET_I_CHROMA_PRED_PLANE
vld1.32 {d6, d7}, [r2]
//Duplicate the 'b','c' to q0, q1 for SIMD instruction
vdup.s16 q1, d1[0]
vdup.s16 q0, d0[0]
//Calculate the "(a + b * (j - 3) + c * (- 3) + 16) >> 5;"
vmla.s16 q2, q0, q3
vmla.s16 q2, q1, d6[0]
vqrshrun.s16 d0, q2, #5
//Set a line of chroma MB
vst1.u32 {d0}, [r0], r1
//Do the same processing for each line.
mov r2, #7
loop_0_get_i_chroma_pred_plane:
vadd.s16 q2, q1
vqrshrun.s16 d0, q2, #5
vst1.u32 {d0}, [r0], r1
subs r2, #1
bne loop_0_get_i_chroma_pred_plane
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 4,979 | test/prod_decoder/codec/3rdparty/openh264/codec/decoder/core/arm/block_add_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro ROW_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: $8 $9
vaddl.s16 \arg4, \arg0, \arg2 //int32 e[i][0] = src[0] + src[2];
vsubl.s16 \arg5, \arg0, \arg2 //int32 e[i][1] = src[0] - src[2];
vshr.s16 \arg8, \arg1, #1
vshr.s16 \arg9, \arg3, #1
vsubl.s16 \arg6, \arg8, \arg3 //int32 e[i][2] = (src[1]>>1)-src[3];
vaddl.s16 \arg7, \arg1, \arg9 //int32 e[i][3] = src[1] + (src[3]>>1);
// }
.endm
.macro TRANSFORM_4BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7 // both row & col transform used
// { // output: f_q[0]~[3], input: e_q[0]~[3];
vadd.s32 \arg0, \arg4, \arg7 //int16 f[i][0] = e[i][0] + e[i][3];
vadd.s32 \arg1, \arg5, \arg6 //int16 f[i][1] = e[i][1] + e[i][2];
vsub.s32 \arg2, \arg5, \arg6 //int16 f[i][2] = e[i][1] - e[i][2];
vsub.s32 \arg3, \arg4, \arg7 //int16 f[i][3] = e[i][0] - e[i][3];
// }
.endm
.macro COL_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_q[0]~[3], output: e_q[0]~[3];
vadd.s32 \arg4, \arg0, \arg2 //int32 e[0][j] = f[0][j] + f[2][j];
vsub.s32 \arg5, \arg0, \arg2 //int32 e[1][j] = f[0][j] - f[2][j];
vshr.s32 \arg6, \arg1, #1
vshr.s32 \arg7, \arg3, #1
vsub.s32 \arg6, \arg6, \arg3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
vadd.s32 \arg7, \arg1, \arg7 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
// }
.endm
// uint8_t *pred, const int32_t stride, int16_t *rs
WELS_ASM_FUNC_BEGIN IdctResAddPred_neon
vld4.s16 {d0, d1, d2, d3}, [r2] // cost 3 cycles!
ROW_TRANSFORM_1_STEP d0, d1, d2, d3, q8, q9, q10, q11, d4, d5
TRANSFORM_4BYTES q0, q1, q2, q3, q8, q9, q10, q11
// transform element 32bits
vtrn.s32 q0, q1 //[0 1 2 3]+[4 5 6 7]-->[0 4 2 6]+[1 5 3 7]
vtrn.s32 q2, q3 //[8 9 10 11]+[12 13 14 15]-->[8 12 10 14]+[9 13 11 15]
vswp d1, d4 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14]
vswp d3, d6 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15]
COL_TRANSFORM_1_STEP q0, q1, q2, q3, q8, q9, q10, q11
TRANSFORM_4BYTES q0, q1, q2, q3, q8, q9, q10, q11
//after clip_table[MAX_NEG_CROP] into [0, 255]
mov r2, r0
vld1.32 {d20[0]},[r0],r1
vld1.32 {d20[1]},[r0],r1
vld1.32 {d22[0]},[r0],r1
vld1.32 {d22[1]},[r0]
vrshrn.s32 d16, q0, #6
vrshrn.s32 d17, q1, #6
vrshrn.s32 d18, q2, #6
vrshrn.s32 d19, q3, #6
vmovl.u8 q0,d20
vmovl.u8 q1,d22
vadd.s16 q0,q8
vadd.s16 q1,q9
vqmovun.s16 d20,q0
vqmovun.s16 d22,q1
vst1.32 {d20[0]},[r2],r1
vst1.32 {d20[1]},[r2],r1
vst1.32 {d22[0]},[r2],r1
vst1.32 {d22[1]},[r2]
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsBlockZero16x16_neon
veor q0, q0
veor q1, q1
lsl r1, r1, 1
.rept 16
vst1.64 {q0, q1}, [r0], r1
.endr
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN WelsBlockZero8x8_neon
veor q0, q0
lsl r1, r1, 1
.rept 8
vst1.64 {q0}, [r0], r1
.endr
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 16,376 | test/prod_decoder/codec/3rdparty/openh264/codec/decoder/core/arm64/intra_pred_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
// for Luma 4x4
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredH_AArch64_neon
sxtw x1, w1
sub x2, x0, #1
.rept 4
ld1r {v0.8b}, [x2], x1
st1 {v0.S}[0], [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredDc_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
sub x3, x0, #1
ldr s0, [x2]
ld1 {v0.b}[4], [x3], x1
ld1 {v0.b}[5], [x3], x1
ld1 {v0.b}[6], [x3], x1
ld1 {v0.b}[7], [x3]
uaddlv h0, v0.8b
uqrshrn b0, h0, #3
dup v0.8b, v0.b[0]
.rept 4
st1 {v0.S}[0], [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredDcTop_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
sub v0.8b, v0.8b, v0.8b
ldr s0, [x2]
uaddlv h0, v0.8b
uqrshrn v0.8b, v0.8h, #2
dup v0.8b, v0.b[0]
.rept 4
st1 {v0.S}[0], [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredDDL_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.8b}, [x2]
dup v1.8b, v0.b[7]
ext v2.8b, v0.8b, v1.8b, #1
ext v3.8b, v0.8b, v1.8b, #2
ushll v2.8h, v2.8b, #1
uaddl v1.8h, v3.8b, v0.8b
add v1.8h, v1.8h, v2.8h
uqrshrn v1.8b, v1.8h, #2
st1 {v1.S}[0], [x0], x1
ext v0.8b, v1.8b, v2.8b, #1
st1 {v0.S}[0], [x0], x1
ext v0.8b, v1.8b, v2.8b, #2
st1 {v0.S}[0], [x0], x1
ext v0.8b, v1.8b, v2.8b, #3
st1 {v0.S}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredDDLTop_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.8b}, [x2]
dup v1.8b, v0.b[3]
mov v0.S[1], v1.S[0]
ext v2.8b, v0.8b, v1.8b, #1
ext v3.8b, v0.8b, v1.8b, #2
ushll v2.8h, v2.8b, #1
uaddl v1.8h, v3.8b, v0.8b
add v1.8h, v1.8h, v2.8h
uqrshrn v1.8b, v1.8h, #2
st1 {v1.S}[0], [x0], x1
ext v0.8b, v1.8b, v2.8b, #1
st1 {v0.S}[0], [x0], x1
ext v0.8b, v1.8b, v2.8b, #2
st1 {v0.S}[0], [x0], x1
ext v0.8b, v1.8b, v2.8b, #3
st1 {v0.S}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredVL_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.8b}, [x2]
ext v1.8b, v0.8b, v0.8b, #1
uaddl v1.8h, v1.8b, v0.8b
uqrshrn v0.8b, v1.8h, #1 // v0.8b is VL0, VL1, VL2, VL3, VL4, ...
ext v2.16b, v1.16b, v1.16b, #2
add v1.8h, v2.8h, v1.8h
uqrshrn v1.8b, v1.8h, #2 // v1.8b is VL5, VL6, VL7, VL8, VL9
st1 {v0.s}[0], [x0], x1 // write the first row
st1 {v1.s}[0], [x0], x1 // write the second row
ext v3.8b, v0.8b, v0.8b, #1
ext v2.8b, v1.8b, v1.8b, #1
st1 {v3.s}[0], [x0], x1 // write the third row
st1 {v2.s}[0], [x0] // write the fourth row
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredVLTop_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.8b}, [x2]
dup v1.8b, v0.b[3]
mov v0.s[1], v1.s[0]
ext v1.8b, v0.8b, v0.8b, #1
uaddl v1.8h, v1.8b, v0.8b
uqrshrn v0.8b, v1.8h, #1 // v0.8b is VL0, VL1, VL2, VL3, VL4, ...
ext v2.16b, v1.16b, v1.16b, #2
add v1.8h, v2.8h, v1.8h
uqrshrn v1.8b, v1.8h, #2 // v1.8b is VL5, VL6, VL7, VL8, VL9
st1 {v0.s}[0], [x0], x1 // write the first row
st1 {v1.s}[0], [x0], x1 // write the second row
ext v3.8b, v0.8b, v0.8b, #1
ext v2.8b, v1.8b, v1.8b, #1
st1 {v3.s}[0], [x0], x1 // write the third row
st1 {v2.s}[0], [x0] // write the fourth row
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredVR_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.s}[1], [x2]
sub x2, x2, #1
ld1 {v0.b}[3], [x2], x1
ld1 {v0.b}[2], [x2], x1
ld1 {v0.b}[1], [x2], x1
ld1 {v0.b}[0], [x2] // v0.8b l2, l1, l0, lt, t0, t1, t2, t3
ext v1.8b, v0.8b, v0.8b, #7
uaddl v2.8h, v1.8b, v0.8b //v2:{X,L2+L1,L1+L0,L0+LT,LT+T0,T0+T1,T1+T2,T2+T3}
ext v1.16b, v2.16b, v2.16b, #14
add v3.8h, v2.8h, v1.8h //v3:{X,L2+L1+L1+L0,L1+L0+L0+LT,...T1+T2+T2+T3}
uqrshrn v3.8b, v3.8h, #2
uqrshrn v2.8b, v2.8h, #1
st1 {v2.s}[1], [x0], x1
st1 {v3.s}[1], [x0], x1
ext v2.8b, v2.8b, v2.8b, #7
ins v2.b[4], v3.b[3]
st1 {v2.s}[1], [x0], x1
ext v3.8b, v3.8b, v3.8b, #7
ins v3.b[4], v3.b[3]
st1 {v3.s}[1], [x0], x1
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredHU_AArch64_neon
sxtw x1, w1
sub x2, x0, #1
mov x3, #3
mul x3, x3, x1
add x3, x3, x2
ld1r {v0.8b}, [x3]
ld1 {v0.b}[4], [x2], x1
ld1 {v0.b}[5], [x2], x1
ld1 {v0.b}[6], [x2], x1 //d0:{L3,L3,L3,L3,L0,L1,L2,L3}
ext v1.8b, v0.8b, v0.8b, #1
uaddl v2.8h, v0.8b, v1.8b //v2:{L3+L3,L3+L3,L3+L3,L3+L0,L0+L1,L1+L2,L2+L3,L3+L3}
ext v3.16b, v2.16b, v2.16b, #2
add v3.8h, v3.8h, v2.8h //v2:{x, HU1, HU3, HU5, x}
uqrshrn v2.8b, v2.8h, #1 // HU0, HU2, HU4
uqrshrn v3.8b, v3.8h, #2 // HU1, HU3, HU5
zip2 v3.8b, v2.8b, v3.8b // HU0, HU1, HU2, HU3, HU4, HU5
mov v3.h[3], v0.h[0] // v0.8b is hu0, hu1, hu2, hu3, hu4, hu5, l3, l3
ext v2.8b, v3.8b, v0.8b, #2
st1 {v3.s}[0], [x0], x1
st1 {v2.s}[0], [x0], x1
st1 {v3.s}[1], [x0], x1
st1 {v0.s}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI4x4LumaPredHD_AArch64_neon
sxtw x1, w1
sub x2, x0, #1
sub x2, x2, x1 // x2 points to top left
ld1 {v0.s}[1], [x2], x1
ld1 {v0.b}[3], [x2], x1
ld1 {v0.b}[2], [x2], x1
ld1 {v0.b}[1], [x2], x1
ld1 {v0.b}[0], [x2] // v0.8b: l3, l2, l1, l0, lt, t0, t1, t2
ext v1.8b, v0.8b, v0.8b, #1 // v1.8b: l2, l1, l0, lt, t0, t1, t2, l3
uaddl v2.8h, v0.8b, v1.8b
ext v3.16b, v2.16b, v2.16b, #2
add v3.8h, v3.8h, v2.8h
uqrshrn v2.8b, v2.8h, #1 // hd8, hd6, hd4, hd0, xxx
uqrshrn v3.8b, v3.8h, #2 // hd9, hd7, hd5, hd1, hd2, hd3
zip1 v2.8b, v2.8b, v3.8b // hd8, hd9, hd6, hd7, hd4, hd5, hd0, hd1
mov v1.h[0], v3.h[2]
ext v3.8b, v2.8b, v1.8b, #6
st1 {v3.s}[0], [x0], x1
st1 {v2.s}[1], [x0], x1
ext v3.8b, v2.8b, v1.8b, #2
st1 {v3.s}[0], [x0], x1
st1 {v2.s}[0], [x0]
WELS_ASM_AARCH64_FUNC_END
// for Chroma 8x8
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderIChromaPredV_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.8b}, [x2]
.rept 8
st1 {v0.8b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderIChromaPredH_AArch64_neon
sxtw x1, w1
sub x2, x0, #1
.rept 8
ld1r {v0.8b}, [x2], x1
st1 {v0.8b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderIChromaPredDc_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
sub x3, x0, #1
ld1 {v0.8b}, [x2]
ld1 {v0.b}[8], [x3], x1
ld1 {v0.b}[9], [x3], x1
ld1 {v0.b}[10], [x3], x1
ld1 {v0.b}[11], [x3], x1
ld1 {v0.b}[12], [x3], x1
ld1 {v0.b}[13], [x3], x1
ld1 {v0.b}[14], [x3], x1
ld1 {v0.b}[15], [x3]
uaddlp v1.8h, v0.16b
uaddlp v2.4s, v1.8h
ins v3.d[0], v2.d[1]
add v3.2s, v2.2s, v3.2s
urshr v2.4s, v2.4s, #2
urshr v3.2s, v3.2s, #3
dup v0.8b, v3.b[0]
dup v1.8b, v2.b[4]
dup v2.8b, v2.b[12]
dup v3.8b, v3.b[4]
ins v0.s[1], v1.s[0]
ins v2.s[1], v3.s[0]
.rept 4
st1 {v0.8b}, [x0], x1
.endr
.rept 4
st1 {v2.8b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderIChromaPredDcTop_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.8b}, [x2]
uaddlp v0.4h, v0.8b
addp v0.8h, v0.8h, v0.8h
dup v1.8h, v0.h[0]
dup v2.8h, v0.h[1]
mov v1.D[1], v2.D[0]
uqrshrn v1.8b, v1.8h, #2
.rept 8
st1 {v1.8b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
.align 4
intra_1_to_4: .short 17*1, 17*2, 17*3, 17*4, 17*1, 17*2, 17*3, 17*4
intra_m3_to_p4: .short -3, -2, -1, 0, 1, 2, 3, 4
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderIChromaPredPlane_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
sub x2, x2, #1
mov x3, x2
// load pTop[2-i] and pLeft[(2-i)*kiStride]
ld1 {v1.b}[3], [x2], #1
ld1 {v1.b}[2], [x2], #1
ld1 {v1.b}[1], [x2], #1
ld1 {v1.b}[0], [x2], #1
ld1 {v1.b}[7], [x3], x1
ld1 {v1.b}[6], [x3], x1
ld1 {v1.b}[5], [x3], x1
ld1 {v1.b}[4], [x3], x1
add x2, x2, #1
add x3, x3, x1
// load pTop[4+i] and pLeft[(4+i)*kiStride]
ld1 {v0.b}[0], [x2], #1
ld1 {v0.b}[1], [x2], #1
ld1 {v0.b}[2], [x2], #1
ld1 {v0.b}[3], [x2], #1
ld1 {v0.b}[4], [x3], x1
ld1 {v0.b}[5], [x3], x1
ld1 {v0.b}[6], [x3], x1
ld1 {v0.b}[7], [x3], x1
uxtl v1.8h, v1.8b
uxtl v0.8h, v0.8b
ldr q2, intra_1_to_4
ldr q3, intra_m3_to_p4
dup v4.8h, v0.h[3]
dup v5.8h, v0.h[7]
add v4.8h, v4.8h, v5.8h
sub v0.8h, v0.8h, v1.8h
shl v4.8h, v4.8h, #4 // v4.8h is a
mul v0.8h, v0.8h, v2.8h // v0.h[0-3] is H, v0.h[4-7] is V
saddlp v0.4s, v0.8h
addp v0.4s, v0.4s, v0.4s // v0.s[0] is H, v0.s[1] is V
sqrshrn v0.4h, v0.4s, #5
dup v1.8h, v0.h[0] // v1.8h is b
dup v0.8h, v0.h[1] // v0.8h is c
mla v4.8h, v1.8h, v3.8h
mla v4.8h, v0.8h, v3.h[0]
sqrshrun v1.8b, v4.8h, #5
st1 {v1.8b}, [x0], x1
.rept 7
add v4.8h, v4.8h, v0.8h
sqrshrun v1.8b, v4.8h, #5
st1 {v1.8b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
//for Luma 16x16
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI16x16LumaPredV_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.16b}, [x2]
.rept 16
st1 {v0.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI16x16LumaPredH_AArch64_neon
sxtw x1, w1
sub x2, x0, #1
.rept 16
ld1r {v0.16b}, [x2], x1
st1 {v0.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI16x16LumaPredDc_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
sub x3, x0, #1
ld1 {v0.16b}, [x2]
ld1 {v1.b}[0], [x3], x1
ld1 {v1.b}[1], [x3], x1
ld1 {v1.b}[2], [x3], x1
ld1 {v1.b}[3], [x3], x1
ld1 {v1.b}[4], [x3], x1
ld1 {v1.b}[5], [x3], x1
ld1 {v1.b}[6], [x3], x1
ld1 {v1.b}[7], [x3], x1
ld1 {v1.b}[8], [x3], x1
ld1 {v1.b}[9], [x3], x1
ld1 {v1.b}[10], [x3], x1
ld1 {v1.b}[11], [x3], x1
ld1 {v1.b}[12], [x3], x1
ld1 {v1.b}[13], [x3], x1
ld1 {v1.b}[14], [x3], x1
ld1 {v1.b}[15], [x3]
// reduce instruction
uaddlv h0, v0.16b
uaddlv h1, v1.16b
add v0.8h, v0.8h, v1.8h
uqrshrn b0, h0, #5
dup v0.16b, v0.b[0]
.rept 16
st1 {v0.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI16x16LumaPredDcTop_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
ld1 {v0.16b}, [x2]
// reduce instruction
uaddlv h0, v0.16b
uqrshrn v0.8b, v0.8h, 4
dup v0.16b, v0.b[0]
.rept 16
st1 {v0.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI16x16LumaPredDcLeft_AArch64_neon
sxtw x1, w1
sub x3, x0, #1
ld1 {v1.b}[0], [x3], x1
ld1 {v1.b}[1], [x3], x1
ld1 {v1.b}[2], [x3], x1
ld1 {v1.b}[3], [x3], x1
ld1 {v1.b}[4], [x3], x1
ld1 {v1.b}[5], [x3], x1
ld1 {v1.b}[6], [x3], x1
ld1 {v1.b}[7], [x3], x1
ld1 {v1.b}[8], [x3], x1
ld1 {v1.b}[9], [x3], x1
ld1 {v1.b}[10], [x3], x1
ld1 {v1.b}[11], [x3], x1
ld1 {v1.b}[12], [x3], x1
ld1 {v1.b}[13], [x3], x1
ld1 {v1.b}[14], [x3], x1
ld1 {v1.b}[15], [x3]
// reduce instruction
uaddlv h1, v1.16b
uqrshrn v0.8b, v1.8h, #4
dup v0.16b, v0.b[0]
.rept 16
st1 {v0.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
.align 4
intra_1_to_8: .short 5, 10, 15, 20, 25, 30, 35, 40
intra_m7_to_p8: .short -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8
WELS_ASM_AARCH64_FUNC_BEGIN WelsDecoderI16x16LumaPredPlane_AArch64_neon
sxtw x1, w1
sub x2, x0, x1
sub x2, x2, #1
mov x3, x2
ld1 {v0.8b}, [x3] // v0 low 8 bit in top(reverse order)
add x3, x3, #9
rev64 v0.8b, v0.8b // reverse v0
ld1 {v1.8b}, [x3] // v1 high 8 bit in top
uxtl v0.8h, v0.8b // extend to 16 bit integer
uxtl v1.8h, v1.8b // extend to 16 bit integer
ld1 {v2.b}[7], [x2], x1
ld1 {v2.b}[6], [x2], x1
ld1 {v2.b}[5], [x2], x1
ld1 {v2.b}[4], [x2], x1
ld1 {v2.b}[3], [x2], x1
ld1 {v2.b}[2], [x2], x1
ld1 {v2.b}[1], [x2], x1
ld1 {v2.b}[0], [x2], x1 // v2.8b low 8 bit in left
add x2, x2, x1
ld1 {v3.b}[0], [x2], x1
ld1 {v3.b}[1], [x2], x1
ld1 {v3.b}[2], [x2], x1
ld1 {v3.b}[3], [x2], x1
ld1 {v3.b}[4], [x2], x1
ld1 {v3.b}[5], [x2], x1
ld1 {v3.b}[6], [x2], x1
ld1 {v3.b}[7], [x2] // v3.8b high 8bit in left
uxtl v2.8h, v2.8b
uxtl v3.8h, v3.8b
sub v0.8h, v1.8h, v0.8h
sub v2.8h, v3.8h, v2.8h
ldr q4, intra_1_to_8
mul v0.8h, v0.8h, v4.8h
mul v2.8h, v2.8h, v4.8h
saddlv s0, v0.8h
saddlv s2, v2.8h
add v1.8h, v1.8h, v3.8h
sqrshrn v0.4h, v0.4S, #6 // b is in v0.h[0]
sqrshrn v2.4h, v2.4S, #6 // c is in v2.h[0]
shl v1.8h, v1.8h, #4 // a is in v1.h[7]
ldr q4, intra_m7_to_p8
ldr q5, intra_m7_to_p8 + 16
dup v1.8h, v1.h[7]
dup v3.8h, v1.h[7]
mla v1.8h, v4.8h, v0.h[0]
mla v3.8h, v5.8h, v0.h[0]
dup v2.8h, v2.h[0] // v2.8h is [cccccccc]
mla v1.8h, v2.8h, v4.h[0]
mla v3.8h, v2.8h, v4.h[0]
sqrshrun v4.8b, v1.8h, #5
sqrshrun2 v4.16b, v3.8h, #5
st1 {v4.16b}, [x0], x1
.rept 15
add v1.8h, v1.8h, v2.8h
add v3.8h, v3.8h, v2.8h
sqrshrun v4.8b, v1.8h, #5
sqrshrun2 v4.16b, v3.8h, #5
st1 {v4.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 5,648 | test/prod_decoder/codec/3rdparty/openh264/codec/decoder/core/arm64/block_add_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro ROW_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: \arg8\() \arg9\()
saddl \arg4\().4s, \arg0\().4h, \arg2\().4h //int32 e[i][0] = src[0] + src[2];
ssubl \arg5\().4s, \arg0\().4h, \arg2\().4h //int32 e[i][1] = src[0] - src[2];
sshr \arg8\().4h, \arg1\().4h, #1
sshr \arg9\().4h, \arg3\().4h, #1
ssubl \arg6\().4s, \arg8\().4h, \arg3\().4h //int32 e[i][2] = (src[1]>>1)-src[3];
saddl \arg7\().4s, \arg1\().4h, \arg9\().4h //int32 e[i][3] = src[1] + (src[3]>>1);
// }
.endm
.macro TRANSFORM_4BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// both row & col transform used
// { // output: f_q[0]~[3], input: e_q[0]~[3];
add \arg0\().4s, \arg4\().4s, \arg7\().4s //int16 f[i][0] = e[i][0] + e[i][3];
add \arg1\().4s, \arg5\().4s, \arg6\().4s //int16 f[i][1] = e[i][1] + e[i][2];
sub \arg2\().4s, \arg5\().4s, \arg6\().4s //int16 f[i][2] = e[i][1] - e[i][2];
sub \arg3\().4s, \arg4\().4s, \arg7\().4s //int16 f[i][3] = e[i][0] - e[i][3];
// }
.endm
.macro COL_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
// { // input: src_q[0]~[3], output: e_q[0]~[3];
add \arg4\().4s, \arg0\().4s, \arg2\().4s //int32 e[0][j] = f[0][j] + f[2][j];
sub \arg5\().4s, \arg0\().4s, \arg2\().4s //int32 e[1][j] = f[0][j] - f[2][j];
sshr \arg6\().4s, \arg1\().4s, #1
sshr \arg7\().4s, \arg3\().4s, #1
sub \arg6\().4s, \arg6\().4s, \arg3\().4s //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
add \arg7\().4s, \arg1\().4s, \arg7\().4s //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
// }
.endm
// uint8_t *pred, const int32_t stride, int16_t *rs
WELS_ASM_AARCH64_FUNC_BEGIN IdctResAddPred_AArch64_neon
SIGN_EXTENSION x1,w1
ld4 {v0.4h, v1.4h, v2.4h, v3.4h}, [x2] // cost 3 cycles!
ROW_TRANSFORM_1_STEP v0, v1, v2, v3, v16, v17, v18, v19, v4, v5
TRANSFORM_4BYTES v0, v1, v2, v3, v16, v17, v18, v19
// transform element 32bits
trn1 v16.4s, v0.4s, v1.4s //[0 1 2 3]+[4 5 6 7]-->[0 4 2 6]
trn2 v17.4s, v0.4s, v1.4s //[0 1 2 3]+[4 5 6 7]-->[1 5 3 7]
trn1 v18.4s, v2.4s, v3.4s //[8 9 10 11]+[12 13 14 15]-->[8 12 10 14]
trn2 v19.4s, v2.4s, v3.4s //[8 9 10 11]+[12 13 14 15]-->[9 13 11 15]
trn1 v0.2d, v16.2d, v18.2d //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]
trn2 v2.2d, v16.2d, v18.2d //[0 4 2 6]+[8 12 10 14]-->[2 6 10 14]
trn1 v1.2d, v17.2d, v19.2d //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]
trn2 v3.2d, v17.2d, v19.2d //[1 5 3 7]+[9 13 11 15]-->[3 7 11 15]
COL_TRANSFORM_1_STEP v0, v1, v2, v3, v16, v17, v18, v19
TRANSFORM_4BYTES v0, v1, v2, v3, v16, v17, v18, v19
//after clip_table[MAX_NEG_CROP] into [0, 255]
mov x2, x0
ld1 {v16.s}[0],[x0],x1
ld1 {v16.s}[1],[x0],x1
ld1 {v17.s}[0],[x0],x1
ld1 {v17.s}[1],[x0]
rshrn v0.4h, v0.4s, #6
rshrn2 v0.8h, v1.4s, #6
rshrn v1.4h, v2.4s, #6
rshrn2 v1.8h, v3.4s, #6
uxtl v2.8h,v16.8b
uxtl v3.8h,v17.8b
add v2.8h, v2.8h, v0.8h
add v3.8h, v3.8h, v1.8h
sqxtun v0.8b,v2.8h
sqxtun v1.8b,v3.8h
st1 {v0.s}[0],[x2],x1
st1 {v0.s}[1],[x2],x1
st1 {v1.s}[0],[x2],x1
st1 {v1.s}[1],[x2]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsBlockZero16x16_AArch64_neon
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
SIGN_EXTENSION x1,w1
lsl x1, x1, 1
.rept 16
st1 {v0.16b, v1.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN WelsBlockZero8x8_AArch64_neon
eor v0.16b, v0.16b, v0.16b
SIGN_EXTENSION x1, w1
lsl x1, x1, 1
.rept 8
st1 {v0.16b}, [x0], x1
.endr
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 20,397 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm/vaa_calc_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro ABS_SUB_SUM_16BYTES arg0, arg1, arg2, arg3, arg4
vld1.32 {q15}, [\arg0], \arg2
vld1.32 {q14}, [\arg1], \arg2
vabal.u8 \arg3, d30, d28
vabal.u8 \arg4, d31, d29
.endm
.macro ABS_SUB_SUM_8x16BYTES arg0, arg1, arg2, arg3, arg4
vld1.32 {q15}, [\arg0], \arg2
vld1.32 {q14}, [\arg1], \arg2
vabdl.u8 \arg3, d30, d28
vabdl.u8 \arg4, d31, d29
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
.endm
.macro SAD_8X16BITS arg0, arg1, arg2
vadd.u16 d31, \arg0, \arg1
vpaddl.u16 d31, d31
vpaddl.u32 \arg2, d31
.endm
WELS_ASM_FUNC_BEGIN VAACalcSad_neon
stmdb sp!, {r4-r8}
ldr r4, [sp, #20] //load pic_stride
ldr r5, [sp, #28] //load psad8x8
//Initial the Q8 register for save the "psadframe"
vmov.s64 q8, #0
//Get the jump distance to use on loop codes
lsl r8, r4, #4
sub r7, r8, #16 //R7 keep the 16*pic_stride-16
sub r8, r2 //R8 keep the 16*pic_stride-pic_width
vaa_calc_sad_loop0:
//R6 keep the pic_width
mov r6, r2
vaa_calc_sad_loop1:
//Process the 16x16 bytes
ABS_SUB_SUM_8x16BYTES r0, r1, r4, q0, q1
ABS_SUB_SUM_8x16BYTES r0, r1, r4, q2, q3
//Do the SAD
SAD_8X16BITS d0, d1, d0
SAD_8X16BITS d2, d3, d1
SAD_8X16BITS d4, d5, d2
SAD_8X16BITS d6, d7, d3
//Write to "psad8x8" buffer
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r5]!
//Adjust the input address
sub r0, r7
sub r1, r7
subs r6, #16
//Save to calculate "psadframe"
vadd.u32 q0, q1
vadd.u32 q8, q0
bne vaa_calc_sad_loop1
//Adjust the input address
add r0, r8
add r1, r8
subs r3, #16
bne vaa_calc_sad_loop0
ldr r6, [sp, #24] //load psadframe
vadd.u32 d16, d17
vst1.32 {d16[0]}, [r6]
ldmia sp!, {r4-r8}
WELS_ASM_FUNC_END
.macro SAD_SD_MAD_16BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6
vld1.32 {q0}, [\arg0], \arg2
vld1.32 {q1}, [\arg1], \arg2
vpadal.u8 \arg3, q0
vpadal.u8 \arg4, q1
vabd.u8 q0, q0, q1
vmax.u8 \arg5, q0
vpadal.u8 \arg6, q0
.endm
.macro SAD_SD_MAD_8x16BYTES arg0, arg1, arg2, arg3, arg4, arg5
vld1.32 {q0}, [\arg0], \arg2
vld1.32 {q1}, [\arg1], \arg2
vpaddl.u8 q2, q0
vpaddl.u8 q3, q1
vabd.u8 \arg3, q0, q1
vpaddl.u8 \arg4, \arg3 //abs_diff
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
vsub.u16 \arg5, q2, q3
.endm
.macro SAD_SD_MAD_CALC arg0, arg1, arg2, arg3, arg4
vpmax.u8 d0, \arg0, \arg1 //8bytes
vpmax.u8 d0, d0, d0 //4bytes
vpmax.u8 \arg2, d0, d0 //2bytes
vpaddl.u16 \arg3, \arg3
vpaddl.u32 \arg3, \arg3
vpaddl.s16 \arg4, \arg4
vpaddl.s32 \arg4, \arg4
.endm
WELS_ASM_FUNC_BEGIN VAACalcSadBgd_neon
stmdb sp!, {r4-r10}
ldr r4, [sp, #28] //load pic_stride
ldr r5, [sp, #36] //load psad8x8
ldr r6, [sp, #40] //load psd8x8
ldr r7, [sp, #44] //load pmad8x8
//Initial the Q4 register for save the "psadframe"
vmov.s64 q15, #0
//Get the jump distance to use on loop codes
lsl r10, r4, #4
sub r9, r10, #16 //R9 keep the 16*pic_stride-16
sub r10, r2 //R10 keep the 16*pic_stride-pic_width
vaa_calc_sad_bgd_loop0:
//R6 keep the pic_width
mov r8, r2
vaa_calc_sad_bgd_loop1:
//Process the 16x16 bytes pmad psad psd
SAD_SD_MAD_8x16BYTES r0, r1, r4, q13, q11, q9
SAD_SD_MAD_8x16BYTES r0, r1, r4, q14, q12, q10
SAD_SD_MAD_CALC d26, d27, d16, q11, q9
SAD_SD_MAD_CALC d28, d29, d17, q12, q10
//Write to "psad8x8" buffer
vst4.32 {d22[0],d23[0],d24[0],d25[0]}, [r5]!
//Adjust the input address
sub r0, r9
sub r1, r9
//Write to "psd8x8" buffer
vst4.32 {d18[0],d19[0],d20[0],d21[0]}, [r6]!
subs r8, #16
//Write to "pmad8x8" buffer
vst2.16 {d16[0],d17[0]}, [r7]!
//Save to calculate "psadframe"
vadd.u32 q11, q12
vadd.u32 q15, q11
bne vaa_calc_sad_bgd_loop1
//Adjust the input address
add r0, r10
add r1, r10
subs r3, #16
bne vaa_calc_sad_bgd_loop0
ldr r8, [sp, #32] //load psadframe
vadd.u32 d30, d31
vst1.32 {d30[0]}, [r8]
ldmia sp!, {r4-r10}
WELS_ASM_FUNC_END
.macro SSD_MUL_SUM_16BYTES_RESET arg0, arg1, arg2, arg3
vmull.u8 \arg3, \arg0, \arg0
vpaddl.u16 \arg2, \arg3
vmull.u8 \arg3, \arg1, \arg1
vpadal.u16 \arg2, \arg3
.endm
.macro SSD_MUL_SUM_16BYTES arg0, arg1, arg2, arg3
vmull.u8 \arg3, \arg0, \arg0
vpadal.u16 \arg2, \arg3
vmull.u8 \arg3, \arg1, \arg1
vpadal.u16 \arg2, \arg3
.endm
.macro SAD_SSD_BGD_16 arg0, arg1, arg2, arg3
vld1.8 {q0}, [\arg0], \arg2 //load cur_row
vpadal.u8 q3, q0 //add cur_row together
vpadal.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vmax.u8 q5, q2 //l_mad for 16 bytes reset for every 8x16
vpadal.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
vld1.8 {q1}, [\arg1], \arg2 //load ref_row
vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
.endm
//the last row of a 16x16 block
.macro SAD_SSD_BGD_16_end arg0, arg1, arg2
vld1.8 {q0}, [\arg0], \arg1 //load cur_row
vpadal.u8 q3, q0 //add cur_row together
vpadal.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vmax.u8 q5, q2 //l_mad for 16 bytes reset for every 8x16
vpadal.u8 \arg2, q2 //l_sad for 16 bytes reset for every 8x16
SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
.endm
//for the begin of a 8x16 block, use some instructions to reset the register
.macro SAD_SSD_BGD_16_RESET_8x8 arg0, arg1, arg2, arg3
vld1.8 {q0}, [\arg0], \arg2 //load cur_row
vpaddl.u8 q3, q0 //add cur_row together
vpaddl.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vmov q5,q2 //calculate max and avoid reset to zero, l_mad for 16 bytes reset for every 8x16
vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
vld1.8 {q1}, [\arg1], \arg2 //load ref_row
vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
.endm
//for the begin of a 16x16 block, use some instructions to reset the register
.macro SAD_SSD_BGD_16_RESET_16x16 arg0, arg1, arg2, arg3
vld1.8 {q0}, [\arg0], \arg2 //load cur_row
vld1.8 {q1}, [\arg1], \arg2 //load ref_row
vpaddl.u8 q3, q0 //add cur_row together
vpaddl.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vmov q5,q2 //calculate max and avoid reset to zero, l_mad for 16 bytes reset for every 8x16
vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
SSD_MUL_SUM_16BYTES_RESET d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
vld1.8 {q1}, [\arg1], \arg2 //load ref_row
vpaddl.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES_RESET d0,d1,q10,q11 //q10 for lsqsum reset for every 16x16
.endm
//for each 8x16 block
.macro SAD_SSD_BGD_CALC_8x16 arg0, arg1, arg2
vpmax.u8 d10, d10, d11 //4 numbers
vpmax.u8 d10, d10, d10 //2 numbers
vpmax.u8 d10, d10, d10 //1 number1
vmov \arg0, d10 //d26 d27 keeps the l_mad
//p_sd8x8
vpaddl.u16 q3, q3
vpaddl.u16 q4, q4
vsub.i32 \arg1, q3, q4
vpaddl.u32 \arg1, \arg1
//psad8x8
vpaddl.u16 \arg2, \arg2
vpaddl.u32 \arg2, \arg2
//psadframe
vadd.i32 q12, \arg2
.endm
.macro SAD_SSD_BGD_16x16 arg0, arg1, arg2
//for one 8x16
SAD_SSD_BGD_16_RESET_16x16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_BGD_CALC_8x16 d26, q14, q6
//for another 8x16
SAD_SSD_BGD_16_RESET_8x8 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_BGD_16_end \arg0, \arg2, q7
SAD_SSD_BGD_CALC_8x16 d27, q15, q7
.endm
.macro SSD_SAD_SD_MAD_PADDL arg0, arg1, arg2
vpaddl.s16 \arg0, \arg0
vpaddl.s32 \arg0, \arg0
vadd.i32 \arg1, \arg1, \arg2
.endm
WELS_ASM_FUNC_BEGIN VAACalcSadSsdBgd_neon
stmdb sp!, {r0-r12, r14}
vpush {q4-q7}
ldr r4, [sp, #120] //r4 keeps the pic_stride
sub r5, r4, #1
lsl r5, r5, #4 //r5 keeps the little step
lsl r6, r4, #4
sub r6, r2, r6 //r6 keeps the big step
ldr r8, [sp, #128]//psad8x8
ldr r9, [sp, #132]//psum16x16
ldr r10, [sp, #136]//psqsum16x16
ldr r11, [sp, #140]//psqdiff16x16
ldr r12, [sp, #144]//p_sd8x8
ldr r14, [sp, #148]//p_mad8x8
vmov.i8 q12, #0
vaa_calc_sad_ssd_bgd_height_loop:
mov r7, r2
vaa_calc_sad_ssd_bgd_width_loop:
//l_sd q14&q15, l_mad q13, l_sad q6 & q7, l_sqdiff q8, l_sum q9, l_sqsum q10
SAD_SSD_BGD_16x16 r0,r1,r4
//psad8x8
vst4.32 {d12[0], d13[0], d14[0], d15[0]}, [r8]!
sub r0, r0, r5 //jump to next 16x16
sub r1, r1, r5 //jump to next 16x16
//p_sd8x8
vst4.32 {d28[0], d29[0],d30[0], d31[0]}, [r12]!
//p_mad8x8
vst2.16 {d26[0], d27[0]}, [r14]!
//psqdiff16x16
vpaddl.s32 q8, q8
vadd.i32 d16, d16, d17
vst1.32 {d16[0]}, [r11]! //psqdiff16x16
//psum16x16
SSD_SAD_SD_MAD_PADDL q9, d18, d19
vst1.32 {d18[0]}, [r9]! //psum16x16
//psqsum16x16
vpaddl.s32 q10, q10
vadd.i32 d20, d20, d21
vst1.32 {d20[0]}, [r10]! //psqsum16x16
subs r7, #16
bne vaa_calc_sad_ssd_bgd_width_loop
sub r0, r0, r6 //jump to next 16 x width
sub r1, r1, r6 //jump to next 16 x width
subs r3, #16
bne vaa_calc_sad_ssd_bgd_height_loop
//psadframe
ldr r7, [sp, #124]//psadframe
vadd.i32 d24, d24, d25
vst1.32 {d24[0]}, [r7]
vpop {q4-q7}
ldmia sp!, {r0-r12, r14}
WELS_ASM_FUNC_END
.macro SAD_VAR_16 arg0, arg1, arg2, arg3
vld1.8 {q0}, [\arg0], \arg2 //load cur_row
vpadal.u8 q3, q0 //add cur_row together
vpadal.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vpadal.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
vld1.8 {q1}, [\arg1], \arg2
vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
.endm
.macro SAD_VAR_16_END arg0, arg1, arg2
vld1.8 {q0}, [\arg0], \arg1 //load cur_row
vpadal.u8 q3, q0 //add cur_row together
vpadal.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vpadal.u8 \arg2, q2 //l_sad for 16 bytes reset for every 8x16
vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
.endm
.macro SAD_VAR_16_RESET_16x16 arg0, arg1, arg2, arg3
vld1.8 {q0}, [\arg0], \arg2 //load cur_row
vld1.8 {q1}, [\arg1], \arg2
vpaddl.u8 q3, q0 //add cur_row together
vpaddl.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
vld1.8 {q1}, [\arg1], \arg2
vpaddl.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES_RESET d0,d1, q10, q11
.endm
.macro SAD_VAR_16_RESET_8x8 arg0, arg1, arg2, arg3
vld1.8 {q0}, [\arg0], \arg2 //load cur_row
vpaddl.u8 q3, q0 //add cur_row together
vpaddl.u8 q4, q1 //add ref_row together
vabd.u8 q2, q0, q1 //abs_diff
vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
vld1.8 {q1}, [\arg1], \arg2
vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
.endm
.macro SAD_VAR_16x16 arg0, arg1, arg2
//for one 8x16
SAD_VAR_16_RESET_16x16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
SAD_VAR_16 \arg0, \arg1, \arg2, q6
vpaddl.u16 q6, q6
vpaddl.u32 q6, q6
vadd.i32 q12, q6
//for another 8x16
SAD_VAR_16_RESET_8x8 \arg0, \arg1, \arg2, q7
SAD_VAR_16 \arg0, \arg1, \arg2, q7
SAD_VAR_16 \arg0, \arg1, \arg2, q7
SAD_VAR_16 \arg0, \arg1, \arg2, q7
SAD_VAR_16 \arg0, \arg1, \arg2, q7
SAD_VAR_16 \arg0, \arg1, \arg2, q7
SAD_VAR_16 \arg0, \arg1, \arg2, q7
SAD_VAR_16_END \arg0, \arg2, q7
vpaddl.u16 q7, q7
vpaddl.u32 q7, q7
vadd.i32 q12, q7
.endm
WELS_ASM_FUNC_BEGIN VAACalcSadVar_neon
stmdb sp!, {r4-r11}
vpush {q4}
vpush {q6-q7}
ldr r4, [sp, #80] //r4 keeps the pic_stride
sub r5, r4, #1
lsl r5, r5, #4 //r5 keeps the little step
lsl r6, r4, #4
sub r6, r2, r6 //r6 keeps the big step
ldr r7, [sp, #84] //psadframe
ldr r8, [sp, #88] //psad8x8
ldr r9, [sp, #92] //psum16x16
ldr r10, [sp, #96] //psqsum16x16
vmov.i8 q12, #0
vaa_calc_sad_var_height_loop:
mov r11, r2
vaa_calc_sad_var_width_loop:
SAD_VAR_16x16 r0,r1,r4
//psad8x8
vst4.32 {d12[0], d13[0], d14[0], d15[0]}, [r8]!
sub r0, r0, r5 //jump to next 16x16
sub r1, r1, r5 //jump to next 16x16
//psum16x16
SSD_SAD_SD_MAD_PADDL q9, d18, d19
vst1.32 {d18[0]}, [r9]! //psum16x16
//psqsum16x16
vpaddl.s32 q10, q10
subs r11, #16
vadd.i32 d20, d20, d21
vst1.32 {d20[0]}, [r10]! //psqsum16x16
bne vaa_calc_sad_var_width_loop
sub r0, r0, r6 //jump to next 16 x width
sub r1, r1, r6 //jump to next 16 x width
subs r3, #16
bne vaa_calc_sad_var_height_loop
vadd.i32 d24, d24, d25
vst1.32 {d24[0]}, [r7]
vpop {q6-q7}
vpop {q4}
ldmia sp!, {r4-r11}
WELS_ASM_FUNC_END
.macro SAD_SSD_16 arg0, arg1, arg2, arg3
SAD_VAR_16 \arg0, \arg1, \arg2, \arg3
SSD_MUL_SUM_16BYTES d4,d5,q8, q11
.endm
.macro SAD_SSD_16_END arg0, arg1, arg2
SAD_VAR_16_END \arg0, \arg1, \arg2
SSD_MUL_SUM_16BYTES d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
.endm
.macro SAD_SSD_16_RESET_16x16 arg0, arg1, arg2, arg3
SAD_VAR_16_RESET_16x16 \arg0, \arg1, \arg2, \arg3
SSD_MUL_SUM_16BYTES_RESET d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
.endm
.macro SAD_SSD_16_RESET_8x8 arg0, arg1, arg2, arg3
SAD_VAR_16_RESET_8x8 \arg0, \arg1, \arg2, \arg3
SSD_MUL_SUM_16BYTES d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
.endm
.macro SAD_SSD_16x16 arg0, arg1, arg2
//for one 8x16
SAD_SSD_16_RESET_16x16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
SAD_SSD_16 \arg0, \arg1, \arg2, q6
vpaddl.u16 q6, q6
vpaddl.u32 q6, q6
vadd.i32 q12, q6
//for another 8x16
SAD_SSD_16_RESET_8x8 \arg0, \arg1, \arg2, q7
SAD_SSD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_16 \arg0, \arg1, \arg2, q7
SAD_SSD_16_END \arg0, \arg2, q7
vpaddl.u16 q7, q7
vpaddl.u32 q7, q7
vadd.i32 q12, q7
.endm
WELS_ASM_FUNC_BEGIN VAACalcSadSsd_neon
stmdb sp!, {r4-r12}
vpush {q4}
vpush {q6-q7}
ldr r4, [sp, #84] //r4 keeps the pic_stride
sub r5, r4, #1
lsl r5, r5, #4 //r5 keeps the little step
lsl r6, r4, #4
sub r6, r2, r6 //r6 keeps the big step
ldr r7, [sp, #88] //psadframe
ldr r8, [sp, #92] //psad8x8
ldr r9, [sp, #96] //psum16x16
ldr r10, [sp, #100] //psqsum16x16
ldr r11, [sp, #104] //psqdiff16x16
vmov.i8 q12, #0
vaa_calc_sad_ssd_height_loop:
mov r12, r2
vaa_calc_sad_ssd_width_loop:
SAD_SSD_16x16 r0,r1,r4
//psad8x8
vst4.32 {d12[0], d13[0], d14[0], d15[0]}, [r8]!
sub r0, r0, r5 //jump to next 16x16
sub r1, r1, r5 //jump to next 16x16
//psum16x16
vpaddl.s16 q9, q9
vpaddl.s32 q9, q9
vadd.i32 d18, d18, d19
vst1.32 {d18[0]}, [r9]! //psum16x16
//psqsum16x16
vpaddl.s32 q10, q10
vadd.i32 d20, d20, d21
vst1.32 {d20[0]}, [r10]! //psqsum16x16
//psqdiff16x16
vpaddl.s32 q8, q8
vadd.i32 d16, d16, d17
subs r12, #16
vst1.32 {d16[0]}, [r11]! //psqdiff16x16
bne vaa_calc_sad_ssd_width_loop
sub r0, r0, r6 //jump to next 16 x width
sub r1, r1, r6 //jump to next 16 x width
subs r3, #16
bne vaa_calc_sad_ssd_height_loop
vadd.i32 d24, d24, d25
vst1.32 {d24[0]}, [r7]
vpop {q6-q7}
vpop {q4}
ldmia sp!, {r4-r12}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,171 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm/pixel_sad_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
WELS_ASM_FUNC_BEGIN WelsProcessingSampleSad8x8_neon
stmdb sp!, {lr}
//Loading a horizontal line data (8 bytes)
vld1.8 {d0}, [r0], r1
vld1.8 {d1}, [r2], r3
//Do the SAD for 8 bytes
vabdl.u8 q1, d0, d1
mov lr, #7
pixel_sad_8x8_loop0:
//Loading a horizontal line data (8 bytes)
vld1.8 {d0}, [r0], r1
vld1.8 {d1}, [r2], r3
subs lr, #1
//Do the SAD for 8 bytes
vabal.u8 q1, d0, d1
bne pixel_sad_8x8_loop0
vadd.u16 d2, d3
vpaddl.u16 d2, d2
vpaddl.u32 d2, d2
vmov.u32 r0, d2[0]//TBO...
ldmia sp!, {lr}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 10,534 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm/down_sample_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
WELS_ASM_FUNC_BEGIN DyadicBilinearDownsampler_neon
stmdb sp!, {r4-r8, lr}
//Get the width and height
ldr r4, [sp, #24] //src_width
ldr r5, [sp, #28] //src_height
//Initialize the register
mov r6, r2
mov r8, r0
mov lr, #0
lsr r5, #1
//Save the tailer for the unasigned size
mla r7, r1, r5, r0
vld1.32 {q15}, [r7]
add r7, r2, r3
//processing a colume data
comp_ds_bilinear_loop0:
vld1.8 {q0,q1}, [r2]!
vld1.8 {q2,q3}, [r7]!
vuzp.8 q0, q1
vuzp.8 q2, q3
vrhadd.u8 q0, q0, q1
vrhadd.u8 q2, q2, q3
vrhadd.u8 q0, q0, q2
vst1.32 {q0}, [r0]!
add lr, #32
cmp lr, r4
movcs lr, #0
addcs r6, r6, r3, lsl #1
movcs r2, r6
addcs r7, r2, r3
addcs r8, r1
movcs r0, r8
subscs r5, #1
bne comp_ds_bilinear_loop0
//restore the tailer for the unasigned size
vst1.32 {q15}, [r0]
ldmia sp!, {r4-r8,lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN comp_ds_bilinear_w_x8_neon
stmdb sp!, {r4-r7, lr}
//Get the width and height
ldr r4, [sp, #20] //src_width
ldr r5, [sp, #24] //src_height
//Get the difference
sub lr, r3, r4
sub r1, r1, r4, lsr #1
lsr r5, #1
//processing a colume data
comp_ds_bilinear_w_x8_loop0:
lsr r6, r4, #3
add r7, r2, r3
//processing a line data
comp_ds_bilinear_w_x8_loop1:
vld1.8 {d0}, [r2]!
vld1.8 {d1}, [r7]!
vpaddl.u8 q0, q0
vrshr.u16 q0, #1
vrhadd.u16 d0, d1
vmovn.u16 d0, q0
vst1.32 {d0[0]}, [r0]!
subs r6, #1
bne comp_ds_bilinear_w_x8_loop1
add r2, r7, lr
add r0, r1
subs r5, #1
bne comp_ds_bilinear_w_x8_loop0
ldmia sp!, {r4-r7,lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN comp_ds_bilinear_w_x16_neon
stmdb sp!, {r4-r7, lr}
//Get the width and height
ldr r4, [sp, #20] //src_width
ldr r5, [sp, #24] //src_height
//Get the difference
sub lr, r3, r4
sub r1, r1, r4, lsr #1
lsr r5, #1
//processing a colume data
comp_ds_bilinear_w_x16_loop0:
lsr r6, r4, #4
add r7, r2, r3
//processing a line data
comp_ds_bilinear_w_x16_loop1:
vld1.8 {q0}, [r2]!
vld1.8 {q1}, [r7]!
vpaddl.u8 q0, q0
vpaddl.u8 q1, q1
vrshr.u16 q0, #1
vrshr.u16 q1, #1
vrhadd.u16 q0, q1
vmovn.u16 d0, q0
vst1.32 {d0}, [r0]!
subs r6, #1
bne comp_ds_bilinear_w_x16_loop1
add r2, r7, lr
add r0, r1
subs r5, #1
bne comp_ds_bilinear_w_x16_loop0
ldmia sp!, {r4-r7,lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DyadicBilinearDownsamplerWidthx32_neon
stmdb sp!, {r4-r7, lr}
//Get the width and height
ldr r4, [sp, #20] //src_width
ldr r5, [sp, #24] //src_height
//Get the difference
sub lr, r3, r4
sub r1, r1, r4, lsr #1
lsr r5, #1
//processing a colume data
comp_ds_bilinear_w_x32_loop0:
lsr r6, r4, #5
add r7, r2, r3
//processing a line data
comp_ds_bilinear_w_x32_loop1:
vld1.8 {q0,q1}, [r2]!
vld1.8 {q2,q3}, [r7]!
vuzp.8 q0, q1
vuzp.8 q2, q3
vrhadd.u8 q0, q0, q1
vrhadd.u8 q2, q2, q3
vrhadd.u8 q0, q0, q2
vst1.32 {q0}, [r0]!
subs r6, #1
bne comp_ds_bilinear_w_x32_loop1
add r2, r7, lr
add r0, r1
subs r5, #1
bne comp_ds_bilinear_w_x32_loop0
ldmia sp!, {r4-r7,lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN GeneralBilinearAccurateDownsampler_neon
stmdb sp!, {r4-r12, lr}
//Get the data from stack
ldr r4, [sp, #40] //the addr of src
ldr r5, [sp, #44] //the value of src_stride
ldr r6, [sp, #48] //the value of scaleX
ldr r7, [sp, #52] //the value of scaleY
mov r10, #32768
sub r10, #1
and r8, r6, r10 // r8 uinc(scaleX mod 32767)
mov r11, #-1
mul r11, r8 // r11 -uinc
vdup.s16 d2, r8
vdup.s16 d0, r11
vzip.s16 d0, d2 // uinc -uinc uinc -uinc
and r9, r7, r10 // r9 vinc(scaleY mod 32767)
mov r11, #-1
mul r11, r9 // r11 -vinc
vdup.s16 d2, r9
vdup.s16 d3, r11
vext.8 d5, d3, d2, #4 // vinc vinc -vinc -vinc
mov r11, #0x40000000
mov r12, #0x4000
sub r12, #1
add r11, r12
vdup.s32 d1, r11; //init u 16384 16383 16384 16383
mov r11, #16384
vdup.s16 d16, r11
sub r11, #1
vdup.s16 d17, r11
vext.8 d7, d17, d16, #4 //init v 16384 16384 16383 16383
veor q14, q14
sub r1, r2 // stride - width
mov r8, #16384 // yInverse
sub r3, #1
_HEIGHT:
ldr r4, [sp, #40] //the addr of src
mov r11, r8
lsr r11, #15
mul r11, r5
add r11, r4 // get current row address
mov r12, r11
add r12, r5
mov r9, #16384 // xInverse
sub r10, r2, #1
vmov.s16 d6, d1
_WIDTH:
mov lr, r9
lsr lr, #15
add r4, r11,lr
vld2.8 {d28[0],d29[0]}, [r4] //q14: 0000000b0000000a;
add r4, r12,lr
vld2.8 {d28[4],d29[4]}, [r4] //q14: 000d000b000c000a;
vzip.32 d28, d29 //q14: 000d000c000b000a;
vmull.u16 q13, d6, d7 //q13: init u * init v
vmull.u32 q12, d26,d28
vmlal.u32 q12, d27,d29
vqadd.u64 d24, d24,d25
vrshr.u64 d24, #30
vst1.8 {d24[0]}, [r0]!
add r9, r6
vadd.u16 d6, d0 // inc u
vshl.u16 d6, #1
vshr.u16 d6, #1
subs r10, #1
bne _WIDTH
WIDTH_END:
lsr r9, #15
add r4,r11,r9
vld1.8 {d24[0]}, [r4]
vst1.8 {d24[0]}, [r0]
add r0, #1
add r8, r7
add r0, r1
vadd.s16 d7, d5 // inc v
vshl.u16 d7, #1
vshr.u16 d7, #1
subs r3, #1
bne _HEIGHT
LAST_ROW:
ldr r4, [sp, #40] //the addr of src
lsr r8, #15
mul r8, r5
add r4, r8 // get current row address
mov r9, #16384
_LAST_ROW_WIDTH:
mov r11, r9
lsr r11, #15
add r3, r4,r11
vld1.8 {d0[0]}, [r3]
vst1.8 {d0[0]}, [r0]
add r0, #1
add r9, r6
subs r2, #1
bne _LAST_ROW_WIDTH
ldmia sp!, {r4-r12, lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DyadicBilinearOneThirdDownsampler_neon
stmdb sp!, {r4-r8, lr}
//Get the width and height
ldr r4, [sp, #24] //src_width
ldr r5, [sp, #28] //src_height
//Initialize the register
mov r6, r2
mov r8, r0
mov lr, #0
//Save the tailer for the un-aligned size
mla r7, r1, r5, r0
vld1.32 {q15}, [r7]
add r7, r2, r3
//processing a colume data
comp_ds_bilinear_onethird_loop0:
vld3.8 {d0, d1, d2}, [r2]!
vld3.8 {d3, d4, d5}, [r2]!
vld3.8 {d16, d17, d18}, [r7]!
vld3.8 {d19, d20, d21}, [r7]!
vaddl.u8 q11, d0, d1
vaddl.u8 q12, d3, d4
vaddl.u8 q13, d16, d17
vaddl.u8 q14, d19, d20
vrshr.u16 q11, #1
vrshr.u16 q12, #1
vrshr.u16 q13, #1
vrshr.u16 q14, #1
vrhadd.u16 q11, q13
vrhadd.u16 q12, q14
vmovn.u16 d0, q11
vmovn.u16 d1, q12
vst1.8 {q0}, [r0]!
add lr, #48
cmp lr, r4
movcs lr, #0
addcs r6, r6, r3, lsl #1
addcs r6, r6, r3
movcs r2, r6
addcs r7, r2, r3
addcs r8, r1
movcs r0, r8
subscs r5, #1
bne comp_ds_bilinear_onethird_loop0
//restore the tailer for the un-aligned size
vst1.32 {q15}, [r0]
ldmia sp!, {r4-r8,lr}
WELS_ASM_FUNC_END
WELS_ASM_FUNC_BEGIN DyadicBilinearQuarterDownsampler_neon
stmdb sp!, {r4-r8, lr}
//Get the width and height
ldr r4, [sp, #24] //src_width
ldr r5, [sp, #28] //src_height
//Initialize the register
mov r6, r2
mov r8, r0
mov lr, #0
lsr r5, #2
//Save the tailer for the un-aligned size
mla r7, r1, r5, r0
vld1.32 {q15}, [r7]
add r7, r2, r3
//processing a colume data
comp_ds_bilinear_quarter_loop0:
vld2.16 {q0, q1}, [r2]!
vld2.16 {q2, q3}, [r2]!
vld2.16 {q8, q9}, [r7]!
vld2.16 {q10, q11}, [r7]!
vpaddl.u8 q0, q0
vpaddl.u8 q2, q2
vpaddl.u8 q8, q8
vpaddl.u8 q10, q10
vrshr.u16 q0, #1
vrshr.u16 q2, #1
vrshr.u16 q8, #1
vrshr.u16 q10, #1
vrhadd.u16 q0, q8
vrhadd.u16 q2, q10
vmovn.u16 d0, q0
vmovn.u16 d1, q2
vst1.8 {q0}, [r0]!
add lr, #64
cmp lr, r4
movcs lr, #0
addcs r6, r6, r3, lsl #2
movcs r2, r6
addcs r7, r2, r3
addcs r8, r1
movcs r0, r8
subscs r5, #1
bne comp_ds_bilinear_quarter_loop0
//restore the tailer for the un-aligned size
vst1.32 {q15}, [r0]
ldmia sp!, {r4-r8,lr}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 3,070 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm/adaptive_quantization.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON
#include "arm_arch_common_macro.S"
.macro SQR_ADD_16BYTES arg0, arg1, arg2
vmull.u8 q3, \arg0, \arg0
vmull.u8 q8, \arg1, \arg1
vpadal.u16 \arg2, q3
vpadal.u16 \arg2, q8
.endm
WELS_ASM_FUNC_BEGIN SampleVariance16x16_neon
stmdb sp!, {r4}
vld1.8 {q15}, [r0], r1 //save the ref data (16bytes)
vld1.8 {q14}, [r2], r3 //save the src data (16bytes)
vabd.u8 q13, q14, q15
vmull.u8 q12, d27, d27
vmull.u8 q11, d26, d26
vaddl.u16 q12, d24, d25
vpadal.u16 q12, q11 //sqr
vaddl.u8 q13, d26, d27 //sum
vaddl.u8 q10, d28, d29 //sum_cur
vmull.u8 q9, d29, d29
vmull.u8 q8, d28, d28
vaddl.u16 q9, d18, d19 //sqr_cur
vpadal.u16 q9, q8
mov r4, #15
pixel_var_16x16_loop0:
vld1.8 {q0}, [r0], r1 //save the ref data (16bytes)
vld1.8 {q1}, [r2], r3 //save the src data (16bytes)
vabd.u8 q2, q0, q1
//q10 save sum_cur
vpadal.u8 q10, q1
//q12 save sqr
SQR_ADD_16BYTES d4, d5, q12
//q13 save sum
vpadal.u8 q13, q2
subs r4, #1
//q9 save sqr_cur
SQR_ADD_16BYTES d2, d3, q9
bne pixel_var_16x16_loop0
vadd.u16 d0, d26, d27 //sum
vadd.u16 d1, d20, d21 //sum_cur
vpaddl.u16 q0, q0
vadd.u32 d2, d24, d25 //sqr
vadd.u32 d3, d18, d19 //sqr_cur
vpadd.u32 d0, d0, d1
vpadd.u32 d1, d2, d3
ldr r4, [sp, #4]
vshr.u32 q0, q0, #8
vmul.u32 d0, d0
vsub.u32 d0, d1, d0
vmovl.u32 q0, d0
vst2.16 {d0[0], d1[0]}, [r4]
ldmia sp!, {r4}
WELS_ASM_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 2,052 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm64/pixel_sad_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
//int32_t WelsProcessingSampleSad8x8_AArch64_neon (uint8_t*, int32_t, uint8_t*, int32_t);
WELS_ASM_AARCH64_FUNC_BEGIN WelsProcessingSampleSad8x8_AArch64_neon
SIGN_EXTENSION x1, w1
SIGN_EXTENSION x3, w3
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
uabdl v2.8h, v0.8b, v1.8b
.rept 7
ld1 {v0.8b}, [x0], x1
ld1 {v1.8b}, [x2], x3
uabal v2.8h, v0.8b, v1.8b
.endr
saddlv s2, v2.8h
fmov w0, s2
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 3,145 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm64/adaptive_quantization_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
WELS_ASM_AARCH64_FUNC_BEGIN SampleVariance16x16_AArch64_neon
SIGN_EXTENSION x1, w1
SIGN_EXTENSION x3, w3
ld1 {v1.16b}, [x0], x1 //save the ref data (16bytes)
ld1 {v0.16b}, [x2], x3 //save the src data (16bytes)
uabd v2.16b, v0.16b, v1.16b
umull v3.8h, v2.8b, v2.8b
umull2 v4.8h, v2.16b, v2.16b
uaddlp v4.4s, v4.8h
uadalp v4.4s, v3.8h //sqr
uaddlp v2.8h, v2.16b //sum
uaddlp v1.8h, v0.16b //sum_cur
umull v3.8h, v0.8b, v0.8b
umull2 v5.8h, v0.16b, v0.16b
uaddlp v3.4s, v3.8h
uadalp v3.4s, v5.8h //sqr_cur
.rept 15
ld1 {v5.16b}, [x0], x1 //save the ref data (16bytes)
ld1 {v0.16b}, [x2], x3 //save the src data (16bytes)
uabd v6.16b, v0.16b, v5.16b
//v1 save sum_cur
uadalp v1.8h, v0.16b
//v4 save sqr
umull v5.8h, v6.8b, v6.8b
umull2 v7.8h, v6.16b, v6.16b
uadalp v4.4s, v5.8h //sqr
uadalp v4.4s, v7.8h //sqr
//v2 save sum
uadalp v2.8h, v6.16b
//v3 save sqr_cur
umull v5.8h, v0.8b, v0.8b
umull2 v7.8h, v0.16b, v0.16b
uadalp v3.4s, v5.8h //sqr_cur
uadalp v3.4s, v7.8h //sqr_cur
.endr
uaddlv s2, v2.8h //sum
uaddlv s1, v1.8h //sum_cur
ins v2.s[1], v1.s[0] // sum, sum_cur
shrn v2.4h, v2.4s, #8 // sum, sum_cur>>8
mul v2.4h, v2.4h, v2.4h//// sum*sum, sum_cur*sum_cur
uaddlv d4, v4.4s //sqr
uaddlv d3, v3.4s //sqr_cur
ins v4.s[1], v3.s[0] // sqr, sqr_cur
shrn v4.4h, v4.4s, #8 // sqr, sqr_cur>>8
sub v4.4h, v4.4h, v2.4h
st1 {v4.s}[0], [x4]
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 16,627 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm64/vaa_calc_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
.macro ABS_SUB_SUM_16BYTES arg0, arg1
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabal \arg0, v0.8b, v1.8b
uabal2 \arg1, v0.16b,v1.16b
.endm
.macro ABS_SUB_SUM_8x16BYTES arg0, arg1
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabdl \arg0, v0.8b, v1.8b
uabdl2 \arg1, v0.16b,v1.16b
ABS_SUB_SUM_16BYTES \arg0, \arg1
ABS_SUB_SUM_16BYTES \arg0, \arg1
ABS_SUB_SUM_16BYTES \arg0, \arg1
ABS_SUB_SUM_16BYTES \arg0, \arg1
ABS_SUB_SUM_16BYTES \arg0, \arg1
ABS_SUB_SUM_16BYTES \arg0, \arg1
ABS_SUB_SUM_16BYTES \arg0, \arg1
.endm
/*
* void vaa_calc_sad_neon(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
* int32_t *psadframe, int32_t *psad8x8)
*/
WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSad_AArch64_neon
eor v31.16b, v31.16b, v31.16b
SIGN_EXTENSION x4, w4
lsl x9, x4, #4
sub x10, x9, #16 //x10 keep the 16*pic_stride-16
sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
vaa_calc_sad_loop0:
mov w11, w2
vaa_calc_sad_loop1:
ABS_SUB_SUM_8x16BYTES v2.8h, v3.8h
ABS_SUB_SUM_8x16BYTES v4.8h, v5.8h
uaddlv s2, v2.8h
uaddlv s3, v3.8h
uaddlv s4, v4.8h
uaddlv s5, v5.8h
st4 {v2.s, v3.s, v4.s, v5.s}[0], [x6], #16
sub x0, x0, x10
sub x1, x1, x10
sub w11, w11, #16
add v6.2s, v2.2s, v3.2s
add v7.2s, v4.2s, v5.2s
add v6.2s, v6.2s, v7.2s
add v31.2s, v31.2s, v6.2s
cbnz w11, vaa_calc_sad_loop1
add x0, x0, x9
add x1, x1, x9
sub w3, w3, #16
cbnz w3, vaa_calc_sad_loop0
str s31, [x5]
WELS_ASM_AARCH64_FUNC_END
.macro SAD_SD_MAD_8x16BYTES
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v31.16b, v0.16b, v1.16b
uaddlp v2.8h, v31.16b
uaddlp v4.8h, v0.16b
uaddlp v5.8h, v1.16b
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v30.16b, v0.16b, v1.16b
umax v31.16b, v31.16b,v30.16b
uadalp v2.8h, v30.16b
uadalp v4.8h, v0.16b
uadalp v5.8h, v1.16b
.endr
.endm
/*
* void vaa_calc_sad_bgd_neon(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
* int32_t *psadframe, int32_t *psad8x8, int32_t *p_sd8x8, uint8_t *p_mad8x8)
*/
WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadBgd_AArch64_neon
ldr x15, [sp, #0]
eor v28.16b, v28.16b, v28.16b
SIGN_EXTENSION x4, w4
lsl x9, x4, #4
sub x10, x9, #16 //x10 keep the 16*pic_stride-16
sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
vaa_calc_sad_bgd_loop0:
mov w11, w2
vaa_calc_sad_bgd_loop1:
SAD_SD_MAD_8x16BYTES
umaxv b24, v31.8b
ins v31.d[0], v31.d[1]
umaxv b25, v31.8b
uaddlv s20, v2.4h
ins v2.d[0], v2.d[1]
uaddlv s21, v2.4h
usubl v6.4s, v4.4h, v5.4h
usubl2 v7.4s, v4.8h, v5.8h
addv s16, v6.4s
addv s17, v7.4s
SAD_SD_MAD_8x16BYTES
umaxv b26, v31.8b
ins v31.d[0], v31.d[1]
umaxv b27, v31.8b
uaddlv s22, v2.4h
ins v2.d[0], v2.d[1]
uaddlv s23, v2.4h
usubl v6.4s, v4.4h, v5.4h
usubl2 v7.4s, v4.8h, v5.8h
addv s18, v6.4s
addv s19, v7.4s
st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
sub x0, x0, x10
sub x1, x1, x10
st4 {v16.s, v17.s, v18.s, v19.s}[0], [x7], #16
sub w11, w11, #16
st4 {v24.b, v25.b, v26.b, v27.b}[0], [x15], #4
add v29.2s, v20.2s, v21.2s
add v30.2s, v22.2s, v23.2s
add v29.2s, v29.2s, v30.2s
add v28.2s, v28.2s, v29.2s
cbnz w11, vaa_calc_sad_bgd_loop1
add x0, x0, x9
add x1, x1, x9
sub w3, w3, #16
cbnz w3, vaa_calc_sad_bgd_loop0
str s28, [x5]
WELS_ASM_AARCH64_FUNC_END
.macro SAD_SSD_BGD_8x16BYTES_1
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v31.16b, v0.16b, v1.16b
umull v30.8h, v31.8b, v31.8b
uaddlp v29.4s, v30.8h
umull2 v30.8h, v31.16b, v31.16b
uadalp v29.4s, v30.8h // p_sqdiff
uaddlp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uaddlp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uaddlp v2.8h, v31.16b // p_sad
uaddlp v4.8h, v0.16b
uaddlp v5.8h, v1.16b
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v3.16b, v0.16b, v1.16b
umax v31.16b, v31.16b,v3.16b //p_mad
umull v30.8h, v3.8b, v3.8b
uadalp v29.4s, v30.8h
umull2 v30.8h, v3.16b, v3.16b
uadalp v29.4s, v30.8h // p_sqdiff
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uadalp v2.8h, v3.16b //p_sad
uadalp v4.8h, v0.16b
uadalp v5.8h, v1.16b //p_sd
.endr
.endm
.macro SAD_SSD_BGD_8x16BYTES_2
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v26.16b, v0.16b, v1.16b
umull v30.8h, v26.8b, v26.8b
uadalp v29.4s, v30.8h
umull2 v30.8h, v26.16b, v26.16b
uadalp v29.4s, v30.8h // p_sqdiff
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uaddlp v16.8h,v26.16b // p_sad
uaddlp v6.8h, v0.16b
uaddlp v7.8h, v1.16b
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v3.16b, v0.16b, v1.16b
umax v26.16b, v26.16b,v3.16b //p_mad
umull v30.8h, v3.8b, v3.8b
uadalp v29.4s, v30.8h
umull2 v30.8h, v3.16b, v3.16b
uadalp v29.4s, v30.8h // p_sqdiff
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uadalp v16.8h, v3.16b //p_sad
uadalp v6.8h, v0.16b
uadalp v7.8h, v1.16b //p_sd
.endr
.endm
/*
* void vaa_calc_sad_ssd_bgd_c(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
* int32_t *psadframe,int32_t *psad8x8, int32_t *psum16x16, int32_t *psqsum16x16, int32_t *psqdiff16x16, int32_t *p_sd8x8, uint8_t *p_mad8x8)
*/
WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadSsdBgd_AArch64_neon
ldr x12, [sp, #0] //psqsum16x16
ldr x13, [sp, #8] //psqdiff16x16
ldr x14, [sp, #16] //p_sd8x8
ldr x15, [sp, #24] //p_mad8x8
eor v17.16b, v17.16b, v17.16b
SIGN_EXTENSION x4, w4
lsl x9, x4, #4
sub x10, x9, #16 //x10 keep the 16*pic_stride-16
sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
vaa_calc_sad_ssd_bgd_height_loop:
mov w11, w2
vaa_calc_sad_ssd_bgd_width_loop:
SAD_SSD_BGD_8x16BYTES_1 //psad:v2, v16, psum:v28, psqsum:v27, psqdiff:v29, psd:v4, v5, v6, v7, pmad:v31, v26
SAD_SSD_BGD_8x16BYTES_2
umaxv b22, v31.8b
ins v31.d[0], v31.d[1]
umaxv b23, v31.8b
umaxv b24, v26.8b
ins v26.d[0], v26.d[1]
umaxv b25, v26.8b
st4 {v22.b, v23.b, v24.b, v25.b}[0], [x15], #4
usubl v20.4s, v4.4h, v5.4h
usubl2 v21.4s, v4.8h, v5.8h
addv s20, v20.4s
addv s21, v21.4s
usubl v22.4s, v6.4h, v7.4h
usubl2 v23.4s, v6.8h, v7.8h
addv s22, v22.4s
addv s23, v23.4s
st4 {v20.s, v21.s, v22.s, v23.s}[0], [x14], #16
uaddlv s20, v2.4h
ins v2.d[0], v2.d[1]
uaddlv s21, v2.4h
uaddlv s22, v16.4h
ins v16.d[0], v16.d[1]
uaddlv s23, v16.4h
st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
uaddlv s28, v28.8h
str s28, [x7], #4
addv s27, v27.4s
str s27, [x12], #4
addv s29, v29.4s
str s29, [x13], #4
sub x0, x0, x10
sub x1, x1, x10
sub w11, w11, #16
add v29.2s, v20.2s, v21.2s
add v30.2s, v22.2s, v23.2s
add v29.2s, v29.2s, v30.2s
add v17.2s, v17.2s, v29.2s
cbnz w11, vaa_calc_sad_ssd_bgd_width_loop
add x0, x0, x9
add x1, x1, x9
sub w3, w3, #16
cbnz w3, vaa_calc_sad_ssd_bgd_height_loop
str s17, [x5]
WELS_ASM_AARCH64_FUNC_END
.macro SAD_SSD_8x16BYTES_1
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v31.16b, v0.16b, v1.16b
umull v30.8h, v31.8b, v31.8b
uaddlp v29.4s, v30.8h
umull2 v30.8h, v31.16b, v31.16b
uadalp v29.4s, v30.8h // p_sqdiff
uaddlp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uaddlp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uaddlp v2.8h, v31.16b // p_sad
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v3.16b, v0.16b, v1.16b
umull v30.8h, v3.8b, v3.8b
uadalp v29.4s, v30.8h
umull2 v30.8h, v3.16b, v3.16b
uadalp v29.4s, v30.8h // p_sqdiff
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uadalp v2.8h, v3.16b //p_sad
.endr
.endm
.macro SAD_SSD_8x16BYTES_2
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v26.16b, v0.16b, v1.16b
umull v30.8h, v26.8b, v26.8b
uadalp v29.4s, v30.8h
umull2 v30.8h, v26.16b, v26.16b
uadalp v29.4s, v30.8h // p_sqdiff
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uaddlp v16.8h,v26.16b // p_sad
uaddlp v6.8h, v0.16b
uaddlp v7.8h, v1.16b
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v3.16b, v0.16b, v1.16b
umull v30.8h, v3.8b, v3.8b
uadalp v29.4s, v30.8h
umull2 v30.8h, v3.16b, v3.16b
uadalp v29.4s, v30.8h // p_sqdiff
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
uadalp v16.8h, v3.16b //p_sad
.endr
.endm
/*
* void vaa_calc_sad_ssd_c(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
* int32_t *psadframe,int32_t *psad8x8, int32_t *psum16x16, int32_t *psqsum16x16, int32_t *psqdiff16x16)
*/
WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadSsd_AArch64_neon
ldr x12, [sp, #0] //psqsum16x16
ldr x13, [sp, #8] //psqdiff16x16
eor v17.16b, v17.16b, v17.16b
SIGN_EXTENSION x4, w4
lsl x9, x4, #4
sub x10, x9, #16 //x10 keep the 16*pic_stride-16
sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
vaa_calc_sad_ssd_height_loop:
mov w11, w2
vaa_calc_sad_ssd_width_loop:
SAD_SSD_8x16BYTES_1 //psad:v2, v16, psum:v28, psqsum:v27, psqdiff:v29
SAD_SSD_8x16BYTES_2
uaddlv s20, v2.4h
ins v2.d[0], v2.d[1]
uaddlv s21, v2.4h
uaddlv s22, v16.4h
ins v16.d[0], v16.d[1]
uaddlv s23, v16.4h
st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
uaddlv s28, v28.8h
str s28, [x7], #4
addv s27, v27.4s
str s27, [x12], #4
addv s29, v29.4s
str s29, [x13], #4
sub x0, x0, x10
sub x1, x1, x10
sub w11, w11, #16
add v29.2s, v20.2s, v21.2s
add v30.2s, v22.2s, v23.2s
add v29.2s, v29.2s, v30.2s
add v17.2s, v17.2s, v29.2s
cbnz w11, vaa_calc_sad_ssd_width_loop
add x0, x0, x9
add x1, x1, x9
sub w3, w3, #16
cbnz w3, vaa_calc_sad_ssd_height_loop
str s17, [x5]
WELS_ASM_AARCH64_FUNC_END
.macro SAD_VAR_8x16BYTES_1
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v31.16b, v0.16b, v1.16b
uaddlp v2.8h, v31.16b // p_sad
uaddlp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uaddlp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v3.16b, v0.16b, v1.16b
uadalp v2.8h, v3.16b //p_sad
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
.endr
.endm
.macro SAD_VAR_8x16BYTES_2
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v26.16b, v0.16b, v1.16b
uaddlp v16.8h,v26.16b // p_sad
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
.rept 7
ld1 {v0.16b}, [x0], x4
ld1 {v1.16b}, [x1], x4
uabd v3.16b, v0.16b, v1.16b
uadalp v16.8h, v3.16b //p_sad
uadalp v28.8h, v0.16b // p_sum
umull v30.8h, v0.8b, v0.8b
uadalp v27.4s, v30.8h
umull2 v30.8h, v0.16b, v0.16b
uadalp v27.4s, v30.8h // p_sqsum
.endr
.endm
/*
* void vaa_calc_sad_var_c(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
* int32_t *psadframe,int32_t *psad8x8, int32_t *psum16x16, int32_t *psqsum16x16)
*/
WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadVar_AArch64_neon
ldr x12, [sp, #0] //psqsum16x16
eor v17.16b, v17.16b, v17.16b
SIGN_EXTENSION x4, w4
lsl x9, x4, #4
sub x10, x9, #16 //x10 keep the 16*pic_stride-16
sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
vaa_calc_sad_var_height_loop:
mov w11, w2
vaa_calc_sad_var_width_loop:
SAD_VAR_8x16BYTES_1 //psad:v2, v16, psum:v28, psqsum:v27
SAD_VAR_8x16BYTES_2
uaddlv s20, v2.4h
ins v2.d[0], v2.d[1]
uaddlv s21, v2.4h
uaddlv s22, v16.4h
ins v16.d[0], v16.d[1]
uaddlv s23, v16.4h
st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
uaddlv s28, v28.8h
str s28, [x7], #4
addv s27, v27.4s
str s27, [x12], #4
sub x0, x0, x10
sub x1, x1, x10
sub w11, w11, #16
add v29.2s, v20.2s, v21.2s
add v30.2s, v22.2s, v23.2s
add v29.2s, v29.2s, v30.2s
add v17.2s, v17.2s, v29.2s
cbnz w11, vaa_calc_sad_var_width_loop
add x0, x0, x9
add x1, x1, x9
sub w3, w3, #16
cbnz w3, vaa_calc_sad_var_height_loop
str s17, [x5]
WELS_ASM_AARCH64_FUNC_END
#endif
|
xiangxud/webrtc_H265player | 9,186 | test/prod_decoder/codec/3rdparty/openh264/codec/processing/src/arm64/down_sample_aarch64_neon.S | /*!
* \copy
* Copyright (c) 2013, Cisco Systems
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifdef HAVE_NEON_AARCH64
#include "arm_arch64_common_macro.S"
WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearDownsampler_AArch64_neon
//Initialize the register
mov x6, x2
mov x8, x0
mov w9, #0
lsr w5, w5, #1
//Save the tailer for the unasigned size
smaddl x7, w1, w5, x0
ld1 {v4.16b}, [x7]
add x7, x2, w3, sxtw
//processing a colume data
comp_ds_bilinear_loop0:
ld1 {v0.16b, v1.16b}, [x2], #32
ld1 {v2.16b, v3.16b}, [x7], #32
uzp1 v4.16b, v0.16b, v1.16b
uzp2 v5.16b, v0.16b, v1.16b
uzp1 v6.16b, v2.16b, v3.16b
uzp2 v7.16b, v2.16b, v3.16b
urhadd v0.16b, v4.16b, v5.16b
urhadd v1.16b, v6.16b, v7.16b
urhadd v2.16b, v0.16b, v1.16b
st1 {v2.16b}, [x0], #16
add w9, w9, #32
cmp w9, w4
b.cc comp_ds_bilinear_loop0
mov w9, #0
add x6, x6, w3, sxtw #1
mov x2, x6
add x7, x2, w3, sxtw
add x8, x8, w1, sxtw
mov x0, x8
sub w5, w5, #1
cbnz w5, comp_ds_bilinear_loop0
//restore the tailer for the unasigned size
st1 {v4.16b}, [x0]
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearDownsamplerWidthx32_AArch64_neon
sub w9, w3, w4
sub w1, w1, w4, lsr #1
lsr w5, w5, #1
//processing a colume data
comp_ds_bilinear_w_x32_loop0:
lsr w6, w4, #5
add x7, x2, w3, sxtw
//processing a line data
comp_ds_bilinear_w_x32_loop1:
ld1 {v0.16b, v1.16b}, [x2], #32
ld1 {v2.16b, v3.16b}, [x7], #32
uzp1 v4.16b, v0.16b, v1.16b
uzp2 v5.16b, v0.16b, v1.16b
uzp1 v6.16b, v2.16b, v3.16b
uzp2 v7.16b, v2.16b, v3.16b
urhadd v0.16b, v4.16b, v5.16b
urhadd v1.16b, v6.16b, v7.16b
urhadd v2.16b, v0.16b, v1.16b
st1 {v2.16b}, [x0], #16
sub w6, w6, #1
cbnz w6, comp_ds_bilinear_w_x32_loop1
add x2, x7, w9, sxtw
add x0, x0, w1, sxtw
sub w5, w5, #1
cbnz w5, comp_ds_bilinear_w_x32_loop0
WELS_ASM_AARCH64_FUNC_END
WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearOneThirdDownsampler_AArch64_neon
//Initialize the register
mov x6, x2
mov x8, x0
mov w9, #0
//Save the tailer for the unasigned size
smaddl x7, w1, w5, x0
ld1 {v16.16b}, [x7]
add x7, x2, w3, sxtw
//processing a colume data
comp_ds_bilinear_onethird_loop0:
ld3 {v0.16b, v1.16b, v2.16b}, [x2], #48
ld3 {v4.16b, v5.16b, v6.16b}, [x7], #48
uaddl v2.8h, v0.8b, v1.8b
uaddl2 v3.8h, v0.16b, v1.16b
uaddl v6.8h, v4.8b, v5.8b
uaddl2 v7.8h, v4.16b, v5.16b
urshr v2.8h, v2.8h, #1
urshr v3.8h, v3.8h, #1
urshr v6.8h, v6.8h, #1
urshr v7.8h, v7.8h, #1
urhadd v0.8h, v2.8h, v6.8h
urhadd v1.8h, v3.8h, v7.8h
xtn v0.8b, v0.8h
xtn v1.8b, v1.8h
st1 {v0.8b,v1.8b}, [x0], #16
add w9, w9, #48
cmp w9, w4
b.cc comp_ds_bilinear_onethird_loop0
mov w9, #0
add x6, x6, w3, sxtw #1
add x6, x6, w3, sxtw
mov x2, x6
add x7, x2, w3, sxtw
add x8, x8, w1, sxtw
mov x0, x8
sub w5, w5, #1
cbnz w5, comp_ds_bilinear_onethird_loop0
//restore the tailer for the unasigned size
st1 {v16.16b}, [x0]
WELS_ASM_AARCH64_FUNC_END
//void DyadicBilinearQuarterDownsampler_AArch64_neon(uint8_t* pDst, const int32_t kiDstStride,
//uint8_t* pSrc, const int32_t kiSrcStride,
//const int32_t kiSrcWidth, const int32_t kiHeight);
WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearQuarterDownsampler_AArch64_neon
//Initialize the register
mov x6, x2
mov x8, x0
mov w9, #0
lsr w5, w5, #2
//Save the tailer for the unasigned size
smaddl x7, w1, w5, x0
ld1 {v16.16b}, [x7]
add x7, x2, w3, sxtw
//processing a colume data
comp_ds_bilinear_quarter_loop0:
ld2 {v0.8h, v1.8h}, [x2], #32
ld2 {v2.8h, v3.8h}, [x2], #32
ld2 {v4.8h, v5.8h}, [x7], #32
ld2 {v6.8h, v7.8h}, [x7], #32
uaddlp v0.8h, v0.16b
uaddlp v1.8h, v2.16b
uaddlp v4.8h, v4.16b
uaddlp v5.8h, v6.16b
urshr v0.8h, v0.8h, #1
urshr v1.8h, v1.8h, #1
urshr v4.8h, v4.8h, #1
urshr v5.8h, v5.8h, #1
urhadd v0.8h, v0.8h, v4.8h
urhadd v1.8h, v1.8h, v5.8h
xtn v0.8b, v0.8h
xtn v1.8b, v1.8h
st1 {v0.8b,v1.8b}, [x0], #16
add w9, w9, #64
cmp w9, w4
b.cc comp_ds_bilinear_quarter_loop0
mov w9, #0
add x6, x6, w3, sxtw #2
mov x2, x6
add x7, x2, w3, sxtw
add x8, x8, w1, sxtw
mov x0, x8
sub w5, w5, #1
cbnz w5, comp_ds_bilinear_quarter_loop0
//restore the tailer for the unasigned size
st1 {v16.16b}, [x0]
WELS_ASM_AARCH64_FUNC_END
//void GeneralBilinearAccurateDownsampler_AArch64_neon (uint8_t* pDst, const int32_t kiDstStride,
// const int32_t kiDstWidth, const int32_t kiDstHeight,
// uint8_t* pSrc, const int32_t kiSrcStride, const uint32_t kuiScaleX, const uint32_t kuiScaleY);
WELS_ASM_AARCH64_FUNC_BEGIN GeneralBilinearAccurateDownsampler_AArch64_neon
mov w10, #32767
and w8, w6, w10
mov w11, #-1
mul w12, w11, w8
dup v2.4h, w8
dup v0.4h, w12
zip1 v0.4h, v0.4h, v2.4h // uinc -uinc uinc -uinc
and w9, w7, w10
mul w12, w11, w9
dup v2.4h, w9
dup v5.4h, w12
ins v5.s[1], v2.s[0] // vinc vinc -vinc -vinc
mov w11, #0x40000000
mov w12, #0x3FFF
add w11, w11, w12
dup v1.2s, w11 //init u 16384 16383 16384 16383
mov w8, #16384
dup v7.4h, w8
sub w11, w8, #1
dup v2.4h, w11
ins v7.s[0], v2.s[0] //init v 16384 16384 16383 16383
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
SIGN_EXTENSION x1, w1
SIGN_EXTENSION x2, w2
SIGN_EXTENSION x3, w3
SIGN_EXTENSION x5, w5
SIGN_EXTENSION x6, w6
SIGN_EXTENSION x7, w7
sub x1, x1, x2
sub x3, x3, #1
_HEIGHT:
lsr w11, w8, #15
mul w11, w11, w5
add x15, x4, w11, sxtw
add x12, x15, w5, sxtw
mov x9, #16384
sub x10, x2, #1
orr v6.8b, v1.8b, v1.8b
_WIDTH:
lsr x13, x9, #15
add x14, x15, x13
ld2 {v26.b, v27.b}[0], [x14] //q14: 0000000b0000000a;
add x14, x12, x13
ld2 {v26.b, v27.b}[4], [x14] //q14: 000d000b000c000a;
zip1 v28.2s, v26.2s, v27.2s
zip2 v29.2s, v26.2s, v27.2s
umull v20.4s, v6.4h, v7.4h
umull v21.2d, v28.2s, v20.2s
ins v20.d[0], v20.d[1]
umlal v21.2d, v29.2s, v20.2s
addp d21, v21.2d
urshr d21, d21, #30
st1 {v21.b}[0], [x0], #1
add x9, x9, x6
add v6.4h, v6.4h, v0.4h
shl v6.4h, v6.4h, #1
ushr v6.4h, v6.4h, #1
sub x10, x10, #1
cbnz x10, _WIDTH
WIDTH_END:
lsr x9, x9, #15
add x14, x15, x9
ld1 {v21.b}[0], [x14]
st1 {v21.b}[0], [x0], #1
add w8, w8, w7
add x0, x0, x1
add v7.4h, v7.4h, v5.4h
shl v7.4h, v7.4h, #1
ushr v7.4h, v7.4h, #1
sub x3, x3, #1
cbnz x3, _HEIGHT
LAST_ROW:
lsr w8, w8, #15
mul w8, w8, w5
add x4, x4, w8, sxtw
mov x9, #16384
_LAST_ROW_WIDTH:
mov x11, x9
lsr x11, x11, #15
add x3, x4, x11
ld1 {v21.b}[0], [x3]
st1 {v21.b}[0], [x0], #1
add x9, x9, x6
sub x2, x2, #1
cbnz x2, _LAST_ROW_WIDTH
WELS_ASM_AARCH64_FUNC_END
#endif
|
Xiaodao-chen/fly-pig | 25,463 | f401/STARTUP/startup_stm32f401xx.s | ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f401xx.s
;* Author : MCD Application Team
;* @version : V1.8.0
;* @date : 09-November-2016
;* Description : STM32F401xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD OS_CPU_PendSVHandler ; PendSV Handler
DCD OS_CPU_SysTickHandler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD 0 ; Reserved
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
OS_CPU_PendSVHandler PROC
EXPORT OS_CPU_PendSVHandler [WEAK]
B .
ENDP
OS_CPU_SysTickHandler PROC
EXPORT OS_CPU_SysTickHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
DMA1_Stream7_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
FPU_IRQHandler
SPI4_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
Xiaodao-chen/fly-pig | 11,110 | Sysemview/SEGGER/SEGGER_RTT_ASM_ARMv7M.S | /*********************************************************************
* (c) SEGGER Microcontroller GmbH *
* The Embedded Experts *
* www.segger.com *
**********************************************************************
-------------------------- END-OF-HEADER -----------------------------
File : SEGGER_RTT_ASM_ARMv7M.S
Purpose : Assembler implementation of RTT functions for ARMv7M
Additional information:
This module is written to be assembler-independent and works with
GCC and clang (Embedded Studio) and IAR.
*/
#define SEGGER_RTT_ASM // Used to control processed input from header file
#include "SEGGER_RTT.h"
/*********************************************************************
*
* Defines, fixed
*
**********************************************************************
*/
#define _CCIAR 0
#define _CCCLANG 1
#if (defined __SES_ARM) || (defined __GNUC__) || (defined __clang__)
#define _CC_TYPE _CCCLANG
#define _PUB_SYM .global
#define _EXT_SYM .extern
#define _END .end
#define _WEAK .weak
#define _THUMB_FUNC .thumb_func
#define _THUMB_CODE .code 16
#define _WORD .word
#define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax"
#define _ALIGN(Exp) .align Exp
#define _PLACE_LITS .ltorg
#define _DATA_SECT_START
#define _C_STARTUP _start
#define _STACK_END __stack_end__
#define _RAMFUNC
//
// .text => Link to flash
// .fast => Link to RAM
// OtherSect => Usually link to RAM
// Alignment is 2^x
//
#elif defined (__IASMARM__)
#define _CC_TYPE _CCIAR
#define _PUB_SYM PUBLIC
#define _EXT_SYM EXTERN
#define _END END
#define _WEAK _WEAK
#define _THUMB_FUNC
#define _THUMB_CODE THUMB
#define _WORD DCD
#define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp)
#define _ALIGN(Exp) alignrom Exp
#define _PLACE_LITS
#define _DATA_SECT_START DATA
#define _C_STARTUP __iar_program_start
#define _STACK_END sfe(CSTACK)
#define _RAMFUNC SECTION_TYPE SHT_PROGBITS, SHF_WRITE | SHF_EXECINSTR
//
// .text => Link to flash
// .textrw => Link to RAM
// OtherSect => Usually link to RAM
// NOROOT => Allows linker to throw away the function, if not referenced
// Alignment is 2^x
//
#endif
#if (_CC_TYPE == _CCIAR)
NAME SEGGER_RTT_ASM_ARMv7M
#else
.syntax unified
#endif
#if defined (RTT_USE_ASM) && (RTT_USE_ASM == 1)
#define SHT_PROGBITS 0x1
/*********************************************************************
*
* Public / external symbols
*
**********************************************************************
*/
_EXT_SYM __aeabi_memcpy
_EXT_SYM __aeabi_memcpy4
_EXT_SYM _SEGGER_RTT
_PUB_SYM SEGGER_RTT_ASM_WriteSkipNoLock
/*********************************************************************
*
* SEGGER_RTT_WriteSkipNoLock
*
* Function description
* Stores a specified number of characters in SEGGER RTT
* control block which is then read by the host.
* SEGGER_RTT_WriteSkipNoLock does not lock the application and
* skips all data, if the data does not fit into the buffer.
*
* Parameters
* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal").
* pBuffer Pointer to character array. Does not need to point to a \0 terminated string.
* NumBytes Number of bytes to be stored in the SEGGER RTT control block.
* MUST be > 0!!!
* This is done for performance reasons, so no initial check has do be done.
*
* Return value
* 1: Data has been copied
* 0: No space, data has not been copied
*
* Notes
* (1) If there is not enough space in the "Up"-buffer, all data is dropped.
* (2) For performance reasons this function does not call Init()
* and may only be called after RTT has been initialized.
* Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
*/
_SECTION(.text, CODE, 2)
_ALIGN(2)
_THUMB_FUNC
SEGGER_RTT_ASM_WriteSkipNoLock: // unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pData, unsigned NumBytes) {
//
// Cases:
// 1) RdOff <= WrOff => Space until wrap-around is sufficient
// 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks)
// 3) RdOff < WrOff => No space in buf
// 4) RdOff > WrOff => Space is sufficient
// 5) RdOff > WrOff => No space in buf
//
// 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
//
// Register usage:
// R0 Temporary needed as RdOff, <Tmp> register later on
// R1 pData
// R2 <NumBytes>
// R3 <Tmp> register. Hold free for subroutine calls
// R4 <Rem>
// R5 pRing->pBuffer
// R6 pRing (Points to active struct SEGGER_RTT_BUFFER_DOWN)
// R7 WrOff
//
PUSH {R4-R7}
ADD R3,R0,R0, LSL #+1
LDR.W R0,=_SEGGER_RTT // pRing = &_SEGGER_RTT.aUp[BufferIndex];
ADD R0,R0,R3, LSL #+3
ADD R6,R0,#+24
LDR R0,[R6, #+16] // RdOff = pRing->RdOff;
LDR R7,[R6, #+12] // WrOff = pRing->WrOff;
LDR R5,[R6, #+4] // pRing->pBuffer
CMP R7,R0
BCC.N _CheckCase4 // if (RdOff <= WrOff) { => Case 1), 2) or 3)
//
// Handling for case 1, later on identical to case 4
//
LDR R3,[R6, #+8] // Avail = pRing->SizeOfBuffer - WrOff - 1u; => Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
SUBS R4,R3,R7 // <Rem> (Used in case we jump into case 2 afterwards)
SUBS R3,R4,#+1 // <Avail>
CMP R3,R2
BCC.N _CheckCase2 // if (Avail >= NumBytes) { => Case 1)?
_Case4:
ADDS R5,R7,R5 // pBuffer += WrOff
ADDS R0,R2,R7 // v = WrOff + NumBytes
//
// 2x unrolling for the copy loop that is used most of the time
// This is a special optimization for small SystemView packets and makes them even faster
//
_ALIGN(2)
_LoopCopyStraight: // memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
LDRB R3,[R1], #+1
STRB R3,[R5], #+1 // *pDest++ = *pSrc++
SUBS R2,R2,#+1
BEQ _CSDone
LDRB R3,[R1], #+1
STRB R3,[R5], #+1 // *pDest++ = *pSrc++
SUBS R2,R2,#+1
BNE _LoopCopyStraight
_CSDone:
#if _CORE_NEEDS_DMB // Do not slow down cores that do not need a DMB instruction here
DMB // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
#endif
STR R0,[R6, #+12] // pRing->WrOff = WrOff + NumBytes;
MOVS R0,#+1
POP {R4-R7}
BX LR // Return 1
_CheckCase2:
ADDS R0,R0,R3 // Avail += RdOff; => Space incl. wrap-around
CMP R0,R2
BCC.N _Case3 // if (Avail >= NumBytes) { => Case 2? => If not, we have case 3) (does not fit)
//
// Handling for case 2
//
ADDS R0,R7,R5 // v = pRing->pBuffer + WrOff => Do not change pRing->pBuffer here because 2nd chunk needs org. value
SUBS R2,R2,R4 // NumBytes -= Rem; (Rem = pRing->SizeOfBuffer - WrOff; => Space until end of buffer)
_LoopCopyBeforeWrapAround: // memcpy(pRing->pBuffer + WrOff, pData, Rem); => Copy 1st chunk
LDRB R3,[R1], #+1
STRB R3,[R0], #+1 // *pDest++ = *pSrc++
SUBS R4,R4,#+1
BNE _LoopCopyBeforeWrapAround
//
// Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used
// But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element
// In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks
// Therefore, check if 2nd memcpy is necessary at all
//
ADDS R4,R2,#+0 // Save <NumBytes> (needed as counter in loop but must be written to <WrOff> after the loop). Also use this inst to update the flags to skip 2nd loop if possible
BEQ.N _No2ChunkNeeded // if (NumBytes) {
_LoopCopyAfterWrapAround: // memcpy(pRing->pBuffer, pData + Rem, NumBytes);
LDRB R3,[R1], #+1 // pData already points to the next src byte due to copy loop increment before this loop
STRB R3,[R5], #+1 // *pDest++ = *pSrc++
SUBS R2,R2,#+1
BNE _LoopCopyAfterWrapAround
_No2ChunkNeeded:
#if _CORE_NEEDS_DMB // Do not slow down cores that do not need a DMB instruction here
DMB // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
#endif
STR R4,[R6, #+12] // pRing->WrOff = NumBytes; => Must be written after copying data because J-Link may read control block asynchronously while writing into buffer
MOVS R0,#+1
POP {R4-R7}
BX LR // Return 1
_CheckCase4:
SUBS R0,R0,R7
SUBS R0,R0,#+1 // Avail = RdOff - WrOff - 1u;
CMP R0,R2
BCS.N _Case4 // if (Avail >= NumBytes) { => Case 4) == 1) ? => If not, we have case 5) == 3) (does not fit)
_Case3:
MOVS R0,#+0
POP {R4-R7}
BX LR // Return 0
_PLACE_LITS
#endif // defined (RTT_USE_ASM) && (RTT_USE_ASM == 1)
_END
/*************************** End of file ****************************/
|
XiaoHai11111/REF_Base | 22,518 | 2.Firmware/OLED_RTOS_Demo/startup/startup_stm32f405xx.s | /**
******************************************************************************
* @file startup_stm32f405xx.s
* @author MCD Application Team
* @brief STM32F405xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
|
XiaoHai11111/REF_Base | 22,518 | 2.Firmware/IMU_RTOS_Demo/startup/startup_stm32f405xx.s | /**
******************************************************************************
* @file startup_stm32f405xx.s
* @author MCD Application Team
* @brief STM32F405xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
|
XiaoHai11111/REF_Base | 22,518 | 2.Firmware/F405_Demo/startup/startup_stm32f405xx.s | /**
******************************************************************************
* @file startup_stm32f405xx.s
* @author MCD Application Team
* @brief STM32F405xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
|
XiaoHai11111/REF_Base | 22,518 | 2.Firmware/OLED_Demo/startup/startup_stm32f405xx.s | /**
******************************************************************************
* @file startup_stm32f405xx.s
* @author MCD Application Team
* @brief STM32F405xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
|
XiaoHai11111/REF_Base | 22,518 | 2.Firmware/OLED_AstraUI/startup/startup_stm32f405xx.s | /**
******************************************************************************
* @file startup_stm32f405xx.s
* @author MCD Application Team
* @brief STM32F405xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
|
XiaojiaoChen/F7_Ethercat_RTOS | 27,427 | startup/startup_stm32f767xx.s | /**
******************************************************************************
* @file startup_stm32f767xx.s
* @author MCD Application Team
* @brief STM32F767xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M7 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system initialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M7. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* RNG */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word QUADSPI_IRQHandler /* QUADSPI */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */
.word SDMMC2_IRQHandler /* SDMMC2 */
.word CAN3_TX_IRQHandler /* CAN3 TX */
.word CAN3_RX0_IRQHandler /* CAN3 RX0 */
.word CAN3_RX1_IRQHandler /* CAN3 RX1 */
.word CAN3_SCE_IRQHandler /* CAN3 SCE */
.word JPEG_IRQHandler /* JPEG */
.word MDIOS_IRQHandler /* MDIOS */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak CAN3_TX_IRQHandler
.thumb_set CAN3_TX_IRQHandler,Default_Handler
.weak CAN3_RX0_IRQHandler
.thumb_set CAN3_RX0_IRQHandler,Default_Handler
.weak CAN3_RX1_IRQHandler
.thumb_set CAN3_RX1_IRQHandler,Default_Handler
.weak CAN3_SCE_IRQHandler
.thumb_set CAN3_SCE_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
xiaoliang314/eventRTOS | 5,926 | arch/cortex-m/gcc/preempt_fp.s | /*
* Copyright (C) 2021 xiaoliang<1296283984@qq.com>.
*/
.thumb
.syntax unified
.text
.fpu vfpv2
.global PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
/* PendSV异常处理程序通过插入伪造的异常返回上下文实现抢占被中断的线程的CPU
* 并在抢占结束后手动的回复被中断线程的上下文
*/
/* 当发生异常时，当前的LR与被压栈的xPSR指示了被中断的线程某些配置和状态，
* LR:
* BIT4: 当这个位被清除时，指示被中断线程使用了浮点上下文，并在栈中预留的浮点上下文的空间
* BIT3: 当这个位被设置时，指示异常返回到Thread模式，否则返回到Handler模式，PendSV异常发生时，这个位应该为1
* BIT2: 当这个位被设置时，指示异常返回使用PSP恢复线程上下文，否则使用MSP
*/
/* 已压栈的xPSR:
* BIT24: 当这个位被设置时，异常返回后进入Thumb模式，否则返回到ARM模式
* BIT9: 当这个位被设置时，表示栈已开启8Byte对齐，并指示在弹出线程上下文后SP+4
*/
/* 备份LR的状态 */
MOV R0, LR
/* 检查LR BIT4确定线程是否使用了浮点上下文 */
LSLS R1, R0, #27
BMI thread_use_fp_endif
/* 当线程使用了浮点功能时，我们需要执行一条浮点指令，触发Lazy Stacking做浮点上下文保存 */
VCMP.F32 S0, #0.0
/* 我们需要插入伪造的无浮点上下文的异常返回现场，因此我们设置LR的BIT4和清除CONTROL的BIT2(FPCA) */
ORRS LR, #0x10
MRS R1, CONTROL
BICS R1, #4
MSR CONTROL, R1
thread_use_fp_endif:
/* 我们需要插入异常返回现场需要使用的空间，并获取它的栈顶 */
/* 检查LR BIT2确定异常返回使用PSP还是MSP */
LSLS R1, R0, #29
BMI insert_fake_exc_return_context_space_use_psp
/* 因为当前处于Handler模式，因此我们可以直接使用SP来操作MSP */
SUB SP, #32
MOV R2, SP
B insert_fake_exc_return_context_space_endif
insert_fake_exc_return_context_space_use_psp:
/* 在Handler模式下，需要使用MRS与MSR指令操作PSP */
MRS R2, PSP
SUBS R2, #32
MSR PSP, R2
insert_fake_exc_return_context_space_endif:
/* 我们需要保存LR的状态，在异常返回后使用它，因此将LR设置到返回后的R0中 */
STR R0, [R2, #0]
/* 我们设置堆栈中返回后的位置为pendsv_exc_return_handler */
ADR R0, pendsv_exc_return_handler
STR R0, [R2, #24]
/* 我们设置堆栈中xPSR，使异常返回后进入Thumb模式并恢复以前的IPSR状态 */
MOVS R1, #1
LSLS R1, #24
/* 读取返回上下文中的IPSR */
LDR R0, [R2, #60]
LSLS R0, #26
LSRS R0, #26
/* 设置xPSR为BIT24 + IPSR */
ORRS R1, R0
STR R1, [R2, #28]
/* 异常返回，进入pendsv_exc_return_handler */
BX LR
pendsv_exc_return_handler:
/* 保存异常时的LR的状态 */
PUSH {R0}
/* 调用调度程序 */
BL k_schedule
/* 当抢占程序执行结束之后，我们需要恢复抢占前的上下文
* 我们先对浮点上下文做恢复，此后再恢复非浮点部分的上下文
* 我们还需要检查栈对齐STKALIGN标志，确定恢复之后的栈顶位置
*/
POP {R0}
/* 我们使用R3表示线程上下文恢复之后的栈顶位置
* 现在我们先跳过非浮点部分的上下文
*/
ADD R3, SP, #32
/* 检查是否使用浮点上下文 */
LSLS R1, R0, #27
BMI thread_restore_use_fp_endif
/* 恢复浮点上下文，并将空位弹出 */
VLDMIA.F32 R3!, {S0-S15}
LDMIA R3!, {R1}
VMSR FPSCR, R1
ADDS R3, #4
/* 清除浮点使用状态 */
MRS R1, CONTROL
BICS R1, #4
MSR CONTROL, R1
thread_restore_use_fp_endif:
/* 读取xPSR */
LDR R0, [SP, #28]
/* 判断xPSR的BIT9，若置位则栈顶需要+4 */
LSLS R1, R0, #22
LSRS R1, #31
LSLS R1, #2
ADDS R3, R1
/* 读取线程的PC，并根据xPSR的BIT24设置Thumb或者ARM模式 */
LDR R1, [SP, #24]
LSLS R2, R0, #7
LSRS R2, #31
ORRS R1, R2
/* 我们总是需要在R0-R12，LR，SP恢复之后才能执行返回
* 此时，我们没有可以使用的寄存器保存PC，
* 因此需要将PC存入栈中，使用POP指令进行恢复
* 同时我们也无法在恢复R0-R3之后，再保存栈顶的位置
* 因此我们必须使用R4记录栈顶，因此还需要对R4做保存
*/
STMDB R3!, {R1}
STMDB R3!, {R4}
MOV R4, R3
/* 恢复R12，LR，xPSR */
MSR APSR_nzcvq, R0
LDRD R12, LR, [SP, #16]
/* 恢复R0-R3，SP */
POP {R0-R3}
MOV SP, R4
/* 返回抢占线程 */
POP {R4, PC}
|
xiaoliang314/eventRTOS | 4,503 | arch/cortex-m/gcc/preempt_nofp.s | /*
* Copyright (C) 2021 xiaoliang<1296283984@qq.com>.
*/
.thumb
.syntax unified
.text
.global PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
/* PendSV异常处理程序通过插入伪造的异常返回上下文实现抢占被中断的线程的CPU
* 并在抢占结束后手动的回复被中断线程的上下文
*/
/* 当发生异常时，当前的LR与被压栈的xPSR指示了被中断的线程某些配置和状态，
* LR:
* BIT3: 当这个位被设置时，指示异常返回到Thread模式，否则返回到Handler模式，PendSV异常发生时，这个位应该为1
* BIT2: 当这个位被设置时，指示异常返回使用PSP恢复线程上下文，否则使用MSP
*
* 已压栈的xPSR:
* BIT24: 当这个位被设置时，异常返回后进入Thumb模式，否则返回到ARM模式
* BIT9: 当这个位被设置时，表示栈已开启8Byte对齐，并指示在弹出线程上下文后SP+4
*/
/* 备份LR的状态 */
MOV R0, LR
/* 我们需要插入异常返回现场需要使用的空间，并获取它的栈顶 */
/* 检查LR BIT2确定异常返回使用PSP还是MSP */
LSLS R1, R0, #29
BMI insert_fake_exc_return_context_space_use_psp
/* 因为当前处于Handler模式，因此我们可以直接使用SP来操作MSP */
SUB SP, #32
MOV R2, SP
B insert_fake_exc_return_context_space_endif
insert_fake_exc_return_context_space_use_psp:
/* 在Handler模式下，需要使用MRS与MSR指令操作PSP */
MRS R2, PSP
SUBS R2, #32
MSR PSP, R2
insert_fake_exc_return_context_space_endif:
/* 我们设置堆栈中返回后的位置为pendsv_exc_return_handler */
ADR R0, pendsv_exc_return_handler
STR R0, [R2, #24]
/* 我们设置堆栈中xPSR，使异常返回后进入Thumb模式并恢复以前的IPSR状态 */
MOVS R1, #1
LSLS R1, #24
/* 读取返回上下文中的IPSR */
LDR R0, [R2, #60]
LSLS R0, #26
LSRS R0, #26
/* 设置xPSR为BIT24 + IPSR */
ORRS R1, R0
STR R1, [R2, #28]
/* 异常返回，进入pendsv_exc_return_handler */
BX LR
NOP
pendsv_exc_return_handler:
/* 调用调度程序 */
BL k_schedule
/* 当抢占程序执行结束之后，我们需要恢复抢占前的上下文
* 我们还需要检查xPSR的BIT9，确定恢复之后的栈顶位置
*/
/* 我们将R3指向线程恢复后栈顶的前两个字的位置，用于存放R4与PC */
ADD R3, SP, #24
/* 读取xPSR */
LDR R0, [SP, #28]
/* 判断xPSR的BIT9，若置位则栈顶需要+4 */
LSLS R1, R0, #22
LSRS R1, #31
LSLS R1, #2
ADDS R3, R1
/* 读取线程的PC，并根据xPSR的BIT24设置Thumb或者ARM模式 */
LDR R1, [SP, #24]
LSLS R2, R0, #7
LSRS R2, #31
ORRS R1, R2
/* 我们总是需要在R0-R12，LR，SP恢复之后才能执行返回
* 此时，我们没有可以使用的寄存器保存PC，
* 因此需要将PC存入栈中，使用POP指令进行恢复
* 同时我们也无法在恢复R0-R3之后，再保存栈顶的位置
* 因此我们必须使用R4记录栈顶，因此还需要对R4做保存
*/
STR R1, [R3, #4]
STR R4, [R3, #0]
MOV R4, R3
/* 恢复R12，LR，xPSR
* 为了兼容M0，我们不使用LDRD指令来恢复R12与LR
*/
MSR APSR_nzcvq, R0
ADD R0, SP, #16
LDM R0!, {R1-R2}
MOV R12, R1
MOV LR, R2
/* 恢复R0-R3，SP */
POP {R0-R3}
MOV SP, R4
/* 返回被抢占的线程 */
POP {R4, PC}
|
xiaoliang314/eventRTOS | 5,657 | arch/cortex-m/armcc/preempt_fp.s | ;Copyright (C) 2021 xiaoliang<1296283984@qq.com>.
PRESERVE8
THUMB
AREA |.text|, CODE, READONLY
PendSV_Handler PROC
IMPORT kevent_schedule
EXPORT PendSV_Handler
;PendSV异常处理程序通过插入伪造的异常返回上下文实现抢占被中断的线程的CPU
;并在抢占结束后手动的回复被中断线程的上下文
;当发生异常时，当前的LR与被压栈的xPSR指示了被中断的线程某些配置和状态，
;LR:
;BIT4: 当这个位被清除时，指示被中断线程使用了浮点上下文，并在栈中预留的浮点上下文的空间
;BIT3: 当这个位被设置时，指示异常返回到Thread模式，否则返回到Handler模式，PendSV异常发生时，这个位应该为1
;BIT2: 当这个位被设置时，指示异常返回使用PSP恢复线程上下文，否则使用MSP
;
;已压栈的xPSR:
;BIT24: 当这个位被设置时，异常返回后进入Thumb模式，否则返回到ARM模式
;BIT9: 当这个位被设置时，表示栈已开启8Byte对齐，并指示在弹出线程上下文后SP+4
;备份LR的状态
MOV R0, LR
;检查LR BIT4确定线程是否使用了浮点上下文
LSLS R1, R0, #27
BMI THREAD_USE_FP_ENDIF
;当线程使用了浮点功能时，我们需要执行一条浮点指令，触发Lazy Stacking做浮点上下文保存
VCMP.F32 S0, #0.0
;我们需要插入伪造的无浮点上下文的异常返回现场，因此我们设置LR的BIT4和清除CONTROL的BIT2(FPCA)
ORRS LR, #0x10
MRS R1, CONTROL
BICS R1, #4
MSR CONTROL, R1
THREAD_USE_FP_ENDIF
;我们需要插入异常返回现场需要使用的空间，并获取它的栈顶
;检查LR BIT2确定异常返回使用PSP还是MSP
LSLS R1, R0, #29
BMI INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_USE_PSP
;因为当前处于Handler模式，因此我们可以直接使用SP来操作MSP
SUB SP, #32
MOV R2, SP
B INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_ENDIF
INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_USE_PSP
;在Handler模式下，需要使用MRS与MSR指令操作PSP
MRS R2, PSP
SUBS R2, #32
MSR PSP, R2
INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_ENDIF
;我们需要保存LR的状态，在异常返回后使用它，因此将LR设置到返回后的R0中
STR R0, [R2, #0]
;我们设置堆栈中返回后的位置为PendSV_ExcReturnHandler
ADR R0, PENDSV_EXC_RETURN_HANDLER
STR R0, [R2, #24]
;我们设置堆栈中xPSR，使异常返回后进入Thumb模式并恢复以前的IPSR状态
MOVS R1, #1
LSLS R1, #24
;读取返回上下文中的IPSR
LDR R0, [R2, #60]
LSLS R0, #26
LSRS R0, #26
;设置xPSR为BIT24 + IPSR
ORRS R1, R0
STR R1, [R2, #28]
;异常返回，进入PendSV_ExcReturnHandler
BX LR
PENDSV_EXC_RETURN_HANDLER
;保存异常时的LR的状态
PUSH {R0}
;调用调度程序
BL k_schedule
;当抢占程序执行结束之后，我们需要恢复抢占前的上下文
;我们先对浮点上下文做恢复，此后再恢复非浮点部分的上下文
;我们还需要检查栈对齐STKALIGN标志，确定恢复之后的栈顶位置
POP {R0}
;我们使用R3表示线程上下文恢复之后的栈顶位置
;现在我们先跳过非浮点部分的上下文
ADD R3, SP, #32
;检查是否使用浮点上下文
LSLS R1, R0, #27
BMI THREAD_RESTORE_USE_FP_ENDIF
;恢复浮点上下文，并将空位弹出
VLDMIA.F32 R3!, {S0-S15}
LDMIA R3!, {R1}
VMSR FPSCR, R1
ADDS R3, #4
;清除浮点使用状态
MRS R1, CONTROL
BICS R1, #4
MSR CONTROL, R1
THREAD_RESTORE_USE_FP_ENDIF
;读取xPSR
LDR R0, [SP, #28]
;判断xPSR的BIT9，若置位则栈顶需要+4
LSLS R1, R0, #22
LSRS R1, #31
LSLS R1, #2
ADDS R3, R1
;读取线程的PC，并根据xPSR的BIT24设置Thumb或者ARM模式
LDR R1, [SP, #24]
LSLS R2, R0, #7
LSRS R2, #31
ORRS R1, R2
;我们总是需要在R0-R12，LR，SP恢复之后才能执行返回
;此时，我们没有可以使用的寄存器保存PC，
;因此需要将PC存入栈中，使用POP指令进行恢复
;同时我们也无法在恢复R0-R3之后，再保存栈顶的位置
;因此我们必须使用R4记录栈顶，因此还需要对R4做保存
STMDB R3!, {R1}
STMDB R3!, {R4}
MOV R4, R3
;恢复R12，LR，xPSR
MSR xPSR, R0
LDRD R12, LR, [SP, #16]
;恢复R0-R3，SP
POP {R0-R3}
MOV SP, R4
;返回抢占线程
POP {R4, PC}
ENDP
END
|
xiaoliang314/eventRTOS | 4,337 | arch/cortex-m/armcc/preempt_nofp.s | ;Copyright (C) 2021 xiaoliang<1296283984@qq.com>.
PRESERVE8
THUMB
AREA |.text|, CODE, READONLY
PendSV_Handler PROC
IMPORT kevent_schedule
EXPORT PendSV_Handler
;PendSV异常处理程序通过插入伪造的异常返回上下文实现抢占被中断的线程的CPU
;并在抢占结束后手动的回复被中断线程的上下文
;当发生异常时，当前的LR与被压栈的xPSR指示了被中断的线程某些配置和状态，
;LR:
;BIT3: 当这个位被设置时，指示异常返回到Thread模式，否则返回到Handler模式，PendSV异常发生时，这个位应该为1
;BIT2: 当这个位被设置时，指示异常返回使用PSP恢复线程上下文，否则使用MSP
;
;已压栈的xPSR:
;BIT24: 当这个位被设置时，异常返回后进入Thumb模式，否则返回到ARM模式
;BIT9: 当这个位被设置时，表示栈已开启8Byte对齐，并指示在弹出线程上下文后SP+4
;备份LR的状态
MOV R0, LR
;我们需要插入异常返回现场需要使用的空间，并获取它的栈顶
;检查LR BIT2确定异常返回使用PSP还是MSP
LSLS R1, R0, #29
BMI INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_USE_PSP
;因为当前处于Handler模式，因此我们可以直接使用SP来操作MSP
SUB SP, #32
MOV R2, SP
B INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_ENDIF
INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_USE_PSP
;在Handler模式下，需要使用MRS与MSR指令操作PSP
MRS R2, PSP
SUBS R2, #32
MSR PSP, R2
INSERT_FAKE_EXC_RETURN_CONTEXT_SPACE_ENDIF
;我们设置堆栈中返回后的位置为PENDSV_EXCRETURNHANDLER
ADR R0, PENDSV_EXC_RETURN_HANDLER
STR R0, [R2, #24]
;我们设置堆栈中xPSR，使异常返回后进入Thumb模式并恢复以前的IPSR状态
MOVS R1, #1
LSLS R1, #24
;读取返回上下文中的IPSR
LDR R0, [R2, #60]
LSLS R0, #26
LSRS R0, #26
;设置xPSR为BIT24 + IPSR
ORRS R1, R0
STR R1, [R2, #28]
;异常返回，进入PENDSV_EXCRETURNHANDLER
BX LR
NOP
PENDSV_EXC_RETURN_HANDLER
;调用调度程序
BL kevent_schedule
;当抢占程序执行结束之后，我们需要恢复抢占前的上下文
;我们还需要检查xPSR的BIT9，确定恢复之后的栈顶位置
;我们将R3指向线程恢复后栈顶的前两个字的位置，用于存放R4与PC
ADD R3, SP, #24
;读取xPSR
LDR R0, [SP, #28]
;判断xPSR的BIT9，若置位则栈顶需要+4
LSLS R1, R0, #22
LSRS R1, #31
LSLS R1, #2
ADDS R3, R1
;读取线程的PC，并根据xPSR的BIT24设置Thumb或者ARM模式
LDR R1, [SP, #24]
LSLS R2, R0, #7
LSRS R2, #31
ORRS R1, R2
;我们总是需要在R0-R12，LR，SP恢复之后才能执行返回
;此时，我们没有可以使用的寄存器保存PC，
;因此需要将PC存入栈中，使用POP指令进行恢复
;同时我们也无法在恢复R0-R3之后，再保存栈顶的位置
;因此我们必须使用R4记录栈顶，因此还需要对R4做保存
STR R1, [R3, #4]
STR R4, [R3, #0]
MOV R4, R3
;恢复R12，LR，xPSR
;为了兼容M0，我们不使用LDRD指令来恢复R12与LR
MSR xPSR, R0
ADD R0, SP, #16
LDM R0!, {R1-R2}
MOV R12, R1
MOV LR, R2
;恢复R0-R3，SP
POP {R0-R3}
MOV SP, R4
;返回被抢占的线程
POP {R4, PC}
ENDP
END
|
xiaoliang314/eventRTOS | 15,145 | samples/STM32F103/Device/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
XiaoMi/nnlib | 6,657 | hexagon/asm_src/gemsumb_h.S |
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*======================================================================*/
/* FUNCTIONS : gemsumb_asm */
/* */
/* DESCRIPTION */
/* Sum Y matrix vertically and multiply by a_offset */
/* */
/* ARCHITECTURE : QDSP6V6 + HVX */
/*======================================================================*/
/* REVISION HISTORY: */
/* ================= */
/* */
/* Author Date Comments */
/* ------------------------------------------------------------- */
/* DJH 03/07/16 created */
/* DJH 07/10/16 modified input tranpose operation*/
/*======================================================================*/
/* IDEAL-CYCLE-COUNT: */
/* -> M*K/128+13 */
/* */
/* MEMORY */
/* CODESIZE = 352 bytes */
/* STACK = 0 bytes */
/* ASSUMPTIONS */
/* y 128 byte aligned */
/* x is 8byte aligned */
/* K%8=0 M%128=0 */
/* C MODEL */
/* K = Klen | Kstride */
/* M = Mlen | Mstride */
/* write output into blocks width same as size to save memory */
/*======================================================================*/
#if 0
void gemsumb_cn(uint8 * b, uint8 * c, int K, int a_offset) {
int j, k;
int32 sumb;
uint8 b_val;
if(a_offset != 0)
for (j=0; j < 32; j++) {
sumb = 0;
for (k=0; k < K; k++) {
b_val = b[k*M+j];
sumb += b_val;
}
c[j] = sumb*a_offset;
}
else
for (j=0; j < 32; j++) c[j] = 0;
return;
}
#endif
/*======================================================================*/
.text
.file "gemsumb_h.S"
.global gemsumb_asm
.balign 32
.type gemsumb_asm, @function
gemsumb_asm:
/*======================================================================*/
#define ptr_y r0 //Y matrix aligned to 128bytes
#define ptr_z r1 //integer accumulation of row of Y * xoffset
#define k r2 //k
#define x_offset r3 //input offset
#define dotp r4
#define c16 r5 //
/*======================================================================*/
#define z0 v0 //
#define vx_offset v1
#define y0 v2 //
#define z1 v3 //
/*======================================================================*/
{
k = lsr(k, #2) //inherent /4
vx_offset = vsplat(x_offset) //replicate words
dotp = ##0x01010101 //
p0 = cmp.eq(x_offset, #0)
} {
if(p0) jump .L_zero_offset //
z0 = #0 //
loop0(.L_loopK, k) //[P, 2]ki is k/8 - 1
c16 = #16 //
}
/*======================================================================*/
.balign 32
.L_loopK:
{
y0.tmp = vmem(ptr_y++#1) //[1, 0]
z0.uw += vrmpy(y0.ub, dotp.ub) //[1, 8]
}:endloop0
/*=======================================================================*/
.L_zero_offset:
{
z1.w = vmpyio(z0.w, vx_offset.h) //do full 32bit
} {
} {
z1.w = vasl(z1.w, c16) //
} {
z1.w += vmpyie(z0.w, vx_offset.uh) //
vmem(ptr_z+#0) = z1.new //
}{
jumpr r31 //
}
/* ===================================================================== */
.L_end:
.size gemsumb_asm, .L_end-gemsumb_asm
|
XiaoMi/nnlib | 17,581 | hexagon/asm_src/getstats_h.S | /*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
Compute sum of data and sum of squares of data for each depth position
used for later mean and sd. convert result to qf16 format.
*/
#if 0
for (d = 0; d < depth; d++) { sumg[d] = sum2g[d] = 0; }
for (h = 0; h < height; h++) {
for (w = 0; w < width; w++) {
for (d = 0; d < depth; d++) {
tmp = *in_data++;
sumg[d] += tmp; //23bits
sum2g[d] += tmp*tmp; //30bits
}
}
}
#endif
/*======================================================================*/
.global getstats_asm
.balign 32
.type getstats_asm, @function
getstats_asm:
/*======================================================================*/
#define in_data r0
#define width32 r1
#define next_width r2
#define height r3
#define ptr_mean r4
#define ptr_var r5
#define ptr_max r8
#define ptr_min r9
#define n r1
#define byte r6
#define hwrd r7
#define dprd r15
#define c31 r11
#define next_width2 r12
#define in_data1 r13
#define in_data2 r14
#define exp0hi_expnt0 v21:20
#define exp2hi_expnt2 v23:22
#define sum0_sum0lo v25:24
#define sum2_sum2lo v27:26
#define u v26
#define expnt0 v20
#define expnt2 v22
#define sum0 v25
#define sum1 v26
#define sum2 v27
#define lsum v28
#define gsuml_prev v31 //previous global sum low
#define gsuml v29 //global 64bit sum low half
#define gsumh v30 //global 64bit sum high half
#define din v0
#define vzero v1
#define vones v2
#define delta v3
#define pr1 v4
#define pr2 v5
#define d7d6d5d4 v7
#define d3d2d1d0 v6
#define a7a6a5a4a3a2a1a0 v9:8
#define a7a6a5a4 v9
#define a3a2a1a0 v8
#define b7b6b5b4b3b2b1b0 v13:12
#define b7b6b5b4 v13
#define b3b2b1b0 v12
#define vc31 v15
#define maxo_maxe v17:16
#define maxo v17
#define maxe v16
#define max_exp v7
#define mino_mine v19:18
#define mino v19
#define mine v18
#define min_exp v6
#define PV(VSRC) .word (0x1DFFE020+VSRC)
/*======================================================================*/
{
byte = #-1 //
n = lsr(width32, #7) //1/128
dprd = ##0x01010101 //
} {
n = add(n, #-1) //
next_width2 = add(next_width, next_width) //
height = lsr(height, #1) //
lsum = #0 //
} {
loop0(.L_width, n) //
c31 = #31 //31
q0 = and(q0, !q0) //clear q0
p2 = cmp.eq(n, #0) //
} {
d3d2d1d0 = vmem(in_data+#0) //[P,0]b3 b2 b1 b0
in_data1 = add(in_data, #128) //
in_data2 = add(in_data, next_width) //
height = add(height, #-1) //
} {
vc31 = vsplat(c31) //
vzero = #0 //
gsuml = #0 //
gsumh = #0 //
} {
d7d6d5d4.cur = vmem(in_data2++#1) //[0,0]b3 b2 b1 b0
a7a6a5a4a3a2a1a0=vshuff(d7d6d5d4,d3d2d1d0,byte) //[0,0]
loop1(.L_height, height) //
sum0 = #0 //clear mean
} {
gsuml_prev = #0 //
maxe = d3d2d1d0 //[0,1]
mine = d3d2d1d0 //[0,1]
d3d2d1d0 = vmem(in_data1++#1) //[0,1]b3 b2 b1 b0
} {
b7b6b5b4b3b2b1b0 =vshuff(a7a6a5a4,a3a2a1a0,byte) //[0,2]
in_data = add(in_data, next_width2) //
sum1 = #0 //clear mean
c31 = #1 //
} {
maxe.ub = vmax(maxe.ub, d7d6d5d4.ub) //[0,3]
mine.ub = vmin(mine.ub, d7d6d5d4.ub) //[0,3]
sum2 = #0 //
vones = vsplat(c31) //set incre reg
}
/*======================================================================*/
.balign 32
.L_height:
{
if(p2) jump .L_skip
gsuml.w = vadd(gsuml.w, lsum.w) //new sum
}
.L_width:
{ sum0.uw += vrmpy(b3b2b1b0.ub, dprd.ub) //[0,4]
d7d6d5d4.cur = vmem(in_data2++#1) //[1,0]b3 b2 b1 b0
a7a6a5a4a3a2a1a0=vshuff(d7d6d5d4,d3d2d1d0,byte) //[1,0]
} {
sum0.uw += vrmpy(b7b6b5b4.ub, dprd.ub) //[0,5]
maxe.ub = vmax(maxe.ub, d3d2d1d0.ub) //[1,1]
mine.ub = vmin(mine.ub, d3d2d1d0.ub) //[1,1]
d3d2d1d0 = vmem(in_data1++#1) //[1,1]b3 b2 b1 b0
} {
pr1.uw = vrmpy(b3b2b1b0.ub, b3b2b1b0.ub) //[0,6]
pr2.uw = vrmpy(b7b6b5b4.ub, b7b6b5b4.ub) //[0,6]
b7b6b5b4b3b2b1b0 =vshuff(a7a6a5a4,a3a2a1a0,byte) //[1,2]
} {
sum1.w = vadd(sum1.w, pr1.w) //[0,7]
sum2.w = vadd(sum2.w, pr2.w) //[0,7]
maxe.ub = vmax(maxe.ub, d7d6d5d4.ub) //[1,3]
mine.ub = vmin(mine.ub, d7d6d5d4.ub) //[1,3]
}:endloop0
/*======================================================================*/
.L_skip:
{ d3d2d1d0 = vmem(in_data+#0) //[P,0]b3 b2 b1 b0
in_data1 = add(in_data, #128) //[P,0]
in_data2 = add(in_data, next_width) //[P,0]
q0 = vcmp.gt(gsuml_prev.uw, gsuml.uw) //
} {
loop0(.L_width, n) //[P,0]
in_data = add(in_data, next_width2) //[P,0]
delta = vmux(q0, vones, vzero) //
gsuml_prev = gsuml //record for next time
} {
d7d6d5d4.cur = vmem(in_data2++#1) //[P,0]b3 b2 b1 b0
sum0.uw += vrmpy(b3b2b1b0.ub, dprd.ub) //[1,4]
a7a6a5a4a3a2a1a0=vshuff(d7d6d5d4,d3d2d1d0,byte) //[P,0]
} {
sum0.uw += vrmpy(b7b6b5b4.ub, dprd.ub) //[1,5]
maxe.ub = vmax(maxe.ub, d3d2d1d0.ub) //[P,1]
mine.ub = vmin(mine.ub, d3d2d1d0.ub) //[P,1]
d3d2d1d0 = vmem(in_data1++#1) //[P,1]b3 b2 b1 b0
} {
pr1.uw = vrmpy(b3b2b1b0.ub, b3b2b1b0.ub) //[1,6]
pr2.uw = vrmpy(b7b6b5b4.ub, b7b6b5b4.ub) //[1,6]
b7b6b5b4b3b2b1b0 =vshuff(a7a6a5a4,a3a2a1a0,byte) //[P,2]
} {
sum1.w = vadd(sum1.w, pr1.w) //[0,7]
sum2.w = vadd(sum2.w, pr2.w) //[0,7]
maxe.ub = vmax(maxe.ub, d7d6d5d4.ub) //[P,3]
mine.ub = vmin(mine.ub, d7d6d5d4.ub) //[P,3]
} {
gsumh.w = vadd(gsumh.w, delta.w) //
lsum.w = vadd(sum2.w, sum1.w) //line sum
sum1 = #0 //clear mean
sum2 = #0 //clear mean
}:endloop1
{ gsuml.w = vadd(gsuml.w, lsum.w) //new sum
loop0(.L_width1, n) //[P,0]
if(p2) jump .L_skip2 //
}
/*======================================================================*/
.L_width1:
{ sum0.uw += vrmpy(b3b2b1b0.ub, dprd.ub) //[0,4]
d7d6d5d4.cur = vmem(in_data2++#1) //[1,0]b3 b2 b1 b0
a7a6a5a4a3a2a1a0=vshuff(d7d6d5d4,d3d2d1d0,byte) //[1,0]
} {
sum0.uw += vrmpy(b7b6b5b4.ub, dprd.ub) //[0,5]
maxe.ub = vmax(maxe.ub, d3d2d1d0.ub) //[1,1]
mine.ub = vmin(mine.ub, d3d2d1d0.ub) //[1,1]
d3d2d1d0 = vmem(in_data1++#1) //[1,1]b3 b2 b1 b0
} {
pr1.uw = vrmpy(b3b2b1b0.ub, b3b2b1b0.ub) //[0,6]
pr2.uw = vrmpy(b7b6b5b4.ub, b7b6b5b4.ub) //[0,6]
b7b6b5b4b3b2b1b0 =vshuff(a7a6a5a4,a3a2a1a0,byte) //[1,2]
} {
sum1.w = vadd(sum1.w, pr1.w) //[0,7]
sum2.w = vadd(sum2.w, pr2.w) //[0,7]
maxe.ub = vmax(maxe.ub, d7d6d5d4.ub) //[1,3]
mine.ub = vmin(mine.ub, d7d6d5d4.ub) //[1,3]
}:endloop0
/*======================================================================*/
.L_skip2:
{ q0 = vcmp.gt(gsuml_prev.uw, gsuml.uw) //
} {
delta = vmux(q0, vones, vzero) //
gsuml_prev = gsuml //record for next time
} {
sum0.uw += vrmpy(b3b2b1b0.ub, dprd.ub) //[1,4]
} {
sum0.uw += vrmpy(b7b6b5b4.ub, dprd.ub) //[1,5]
} {
pr1.uw = vrmpy(b3b2b1b0.ub, b3b2b1b0.ub) //[1,6]
pr2.uw = vrmpy(b7b6b5b4.ub, b7b6b5b4.ub) //[1,6]
} {
sum1.w = vadd(sum1.w, pr1.w) //[0,7]
sum2.w = vadd(sum2.w, pr2.w) //[0,7]
} {
gsumh.w = vadd(gsumh.w, delta.w) //
lsum.w = vadd(sum2.w, sum1.w) //line sum
} {
gsuml.w = vadd(gsuml.w, lsum.w)
} {
q0 = vcmp.gt(gsuml_prev.uw, gsuml.uw) //
gsuml_prev = gsuml //record for next time
} {
delta = vmux(q0, vones, vzero) //
} {
gsumh.w = vadd(gsumh.w, delta.w) //
maxo_maxe =vshuff(vzero, maxe, byte)
} {
maxe.uh = vmax(maxe.uh, maxo.uh)
mino_mine =vshuff(vzero, mine, byte)
} {
mine.uh = vmin(mine.uh, mino.uh)
hwrd = #-2
} {
maxo_maxe =vshuff(vzero, maxe, hwrd)
} {
mino_mine =vshuff(vzero, mine, hwrd)
} {
maxe.w = vmax(maxe.w, maxo.w)
mine.w = vmin(mine.w, mino.w)
expnt0.w = vnormamt(sum0.w) //convert to qf16
} {
q0 = vcmp.eq(mine.w, maxe.w) //are max and min same
} {
mine = vmux(q0, vzero, mine) //then clamp min to 0
} {
max_exp.w = vnormamt(maxe.w)
ptr_max = memw(sp+#0<<2)
} {
min_exp.w = vnormamt(mine.w)
ptr_min = memw(sp+#1<<2)
} {
maxe.w = vasl(maxe.w, max_exp.w)
max_exp.w = vsub(max_exp.w, vc31.w)
} {
mine.w = vasl(mine.w, min_exp.w)
min_exp.w = vsub(min_exp.w, vc31.w)
} {
exp2hi_expnt2 = vdeal(max_exp, max_exp, hwrd) //(short)expnt pack 2xdepth
vmem(ptr_max+#1) = expnt2.new //
} {
maxo_maxe = vdeal(maxe, maxe, hwrd)
vmem(ptr_max+#0) = maxo.new //
} {
exp2hi_expnt2 = vdeal(min_exp, min_exp, hwrd) //(short)expnt pack 2xdepth
vmem(ptr_min+#1) = expnt2.new //
} {
mino_mine = vdeal(mine, mine, hwrd)
vmem(ptr_min+#0) = mino.new //
} {
sum0.w = vasl(sum0.w, expnt0.w) //sum << norml
expnt0.w = vsub(expnt0.w, vc31.w)
q0 = vcmp.eq(gsumh.w, vzero.w) //is hi = 0 convert 64bit into qf16
} {
u = vmux(q0, gsuml, gsumh) //u = xlo else xhi
} {
exp0hi_expnt0 = vdeal(expnt0, expnt0, hwrd) //(short)expnt pack 2xdepth
vmem(ptr_mean+#1) = expnt0.new //exp of sum 16bits
} {
expnt2.uw = vcl0(u.uw) //count lead zero
} {
vc31.w = vadd(vc31.w, vones.w) //31+1
} {
u.w = vasl(u.w, expnt2.w) //sum << exp
expnt2.w = vsub(expnt2.w, vc31.w) //exp - 32
expnt0.w = vsub(vc31.w, expnt2.w) //32 - exp
} {
sum0_sum0lo = vdeal(sum0, sum0, hwrd) //sum0 >> 16, pack 2xdepth
vmem(ptr_mean+#0) = sum0.new //mant of sum0 16bits
} {
gsuml.w = vlsr(gsuml.w, expnt0.w) //sum >> 32-exp
vc31 = vmux(q0, vzero, vc31) //if hi !=0 sub 32
} {
expnt2.w = vsub(expnt2.w, vc31.w) //
gsuml = vmux(q0, vzero, gsuml) //
} {
exp2hi_expnt2 = vdeal(expnt2, expnt2, hwrd) //(short)expnt pack 2xdepth
vmem(ptr_var+#1) = expnt2.new //exponenet of sum2 16bits
u = vor(u, gsuml) //
} {
u.w = vlsr(u.w, vones.w) //sum << norml
} {
sum2_sum2lo = vdeal(u, u, hwrd) //sum2 >> 16, pack 2xdepth
vmem(ptr_var+#0) = sum2.new //mant of sum2 16bits
} {
jumpr r31 //
}
/*======================================================================*/
/* End fo File */
/*======================================================================*/
|
XiaoMi/nnlib | 14,388 | hexagon/asm_src/gvmmpybbw_h.S | /*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*======================================================================*/
/* FUNCTIONS : gvmmpybbw_asm */
/* */
/* DESCRIPTION */
/* Perform gvm vector matrix multiply, result left at */
/* 32bits */
/* */
/* ARCHITECTURE : QDSP6V6 + HVX */
/*======================================================================*/
/* REVISION HISTORY: */
/* ================= */
/* */
/* Author Date Comments */
/* ------------------------------------------------------------- */
/* DJH 03/07/16 created */
/* DJH 05/10/16 added post add for x and y offset*/
/* DJH 07/10/16 rewrote pre-transpose */
/* DJH 09/16/16 fix over prefetch by 16 now 8 */
/*======================================================================*/
/* CYCLE-COUNT: */
/* -> K*N/256+11*N/4+24 */
/* */
/* MEMORY */
/* CODESIZE = 960 bytes */
/* STACK = 48 bytes */
/* ASSUMPTIONS */
/* y and z are 128 byte aligned */
/* x is 8byte aligned */
/* N%4=0 K%16=0 M%32=0 */
/* C MODEL */
/*======================================================================*/
#if 0
void gvmmpybbw_cn(uint8 * a, uint8 * b, int * c, int N, int M, int K) {
int i, j, k;
int32 sum;
uint8 a_val, b_val;
for (j=0; j < M; j++) {
for (i=0; i < N; i++) {
sum = 0;
for (k=0; k < K; k++) {
a_val = a[i*K+k];
b_val = b[k*M+j];
sum += a_val * b_val ;
}
c[i*M+j] = sum;
}
}
return;
}
#endif
/*=============================================================================*/
.text
.file "gvmmpybbw_h.S"
.global gvmmpybbw_asm
.balign 32
.type gvmmpybbw_asm, @function
gvmmpybbw_asm:
/*=============================================================================*/
#define ptr_x r0 //data
#define ptr_yi r1 //weights
#define ptr_z r2 //results
#define out_width r3 //out_width
#define skip_back r4 //(out_width4 - outwidth-1)*skip back*stride*depth
#define m r5 //is stride of the output matrix always mult of 32
#define stride r6 //stride*depth
#define filt_width r7 //depth*filt_width
#define out_height r8 //number of vertical lines to perform
#define PREFETCH 64 //how far ahead of load should prefetch be
/*=============================================================================*/
#define ki r9
#define ptr_x0 r21
#define ptr_x1 r20
#define ptr_x2 r22
#define ptr_x3 r11
#define ptr_y r10 //
#define out_width4 r24
#define col_count r23
//01234567
#define x07x04x03x00 r13:12 //11-----1
#define x07x04 r13 //11-----1
#define x03x00 r12 //1------1
#define x0fx0cx0bx08 r15:14 //1111---1
#define x0fx0c r15 //1111---1
#define x0bx08 r14 //111----1
#define x17x14x13x10 r19:18 //11------
#define x17x14 r19 //11------
#define x13x10 r18 //1-------
#define x1fx1cx1bx18 r17:16 //1111----
#define x1fx1c r17 //1111----
#define x1bx18 r16 //111-----
#define x27x24x23x20 r13:12 //---111--
#define x27x24 r13 //---111--
#define x23x20 r12 //---11---
#define x2fx2cx2bx28 r19:18 //---1111-
#define x2fx2c r19 //---11111
#define x2bx28 r18 //---1111-
#define x37x34x33x30 r15:14 //----11--
#define x37x34 r15 //----11--
#define x33x30 r14 //----1---
#define x3fx3cx3bx38 r17:16 //----1111
#define x3fx3c r17 //----1111
#define x3bx38 r16 //----111-
/*=============================================================================*/
#define z0 v0 //
#define z1 v1 //
#define z1z0 v1:0 //
#define z2 v2 //
#define z3 v3 //
#define z3z2 v3:2 //
#define y0 v8 //
#define y1 v9 //
#define y2 v10 //
#define y3 v11 //
#define vzero v12 //
#define WO 1
/*=============================================================================*/
{
stride = memw(sp+#0<<2) //extract stride*depth
filt_width = memw(sp+#1<<2) //extract filt_width*depth
m = asl(m, #2) //ints
} {
out_height = memw(sp+#2<<2) //number of output lines
allocframe(#64) //
vzero = #0 //
} {
M0 = m //
memd(sp+#32) = r25:24 //
memd(sp+#0) = r17:16 //
} {
ki = lsr(filt_width, #4) //k / 16
memd(sp+#16) = r21:20 //
memd(sp+#24) = r23:22 //
out_width4 = add(out_width, #3)
} {
ki = add(ki, #-1) //
memd(sp+#8) = r19:18 //
memd(sp+#40) = r27:26 //
out_width4 = lsr(out_width4, #2)
}
/*============================================================================*/
.balign 32
.L_height:
{
loop1(.L_width, out_width4) //[ , P]for(i=0; i < n; i+=4){
col_count = out_width
out_height = add(out_height, #-1)
ptr_y = ptr_yi //[ , P]
}
.balign 32
.L_width:
{
#if WO
y0 = vmem(ptr_y++#2) //[0, 0]32x4
#endif
dcfetch(ptr_x+#PREFETCH) //[0, 0]prefetch next line
ptr_x0 = ptr_x
z1z0 = vcombine(vzero, vzero) //[P, 0]
} {
#if WO
y1 = vmem(ptr_y+#-1) //[0, 1]32x4
#endif
dcfetch(ptr_x1+#PREFETCH) //[0, 1]prefetch next line
ptr_x1 = add(ptr_x, stride) // x1 = x0 + depth*stride
z3z2 = vcombine(vzero, vzero) //[P, 0]
} {
x0fx0cx0bx08 = memd(ptr_x0+#8) //[0, 2]
x07x04x03x00 = memd(ptr_x0++#16) //[0, 2]
#if WO
#endif
ptr_x2 = add(ptr_x1, stride) // x2 = x1 + depth*stride
ptr_x3 = addasl(ptr_x1, stride, #1)// x3 = x2 + depth*stride
} {
x1fx1cx1bx18 = memd(ptr_x1+#8) //[0, 3]
x17x14x13x10 = memd(ptr_x1++#16) //[0, 3]
#if WO
#endif
ptr_x = addasl(ptr_x, stride, #2) //ptr_x += 4*stride
loop0(.L_filt_width, ki) //[P, 9]ki is k1/4 - 2
}
.L_filt_width:
{
dcfetch(ptr_x2+#PREFETCH) //[0, 4]prefetch next line
z0.uw += vrmpy(y0.ub, x03x00.ub) //[0, 4]
z1.uw += vrmpy(y0.ub, x13x10.ub) //[0, 4]
#if WO
y2 = vmem(ptr_y++#2) //[0, 4]32x4
#endif
} {
dcfetch(ptr_x3+#PREFETCH) //[0, 5]prefetch next line
z0.uw += vrmpy(y1.ub, x07x04.ub) //[0, 5]
z1.uw += vrmpy(y1.ub, x17x14.ub) //[0, 5]
#if WO
y3 = vmem(ptr_y+#-1) //[0, 5]32x4
#endif
} {
z0.uw += vrmpy(y2.ub, x0bx08.ub) //[0, 6]
z1.uw += vrmpy(y2.ub, x1bx18.ub) //[0, 6]
x2fx2cx2bx28 = memd(ptr_x2+#8) //[0, 6]
x27x24x23x20 = memd(ptr_x2++#16) //[0, 6]
#if WO
#endif
} {
z0.uw += vrmpy(y3.ub, x0fx0c.ub) //[0, 7]
z1.uw += vrmpy(y3.ub, x1fx1c.ub) //[0, 7]
x3fx3cx3bx38 = memd(ptr_x3+#8) //[0, 7]
x37x34x33x30 = memd(ptr_x3++#16) //[0, 7]
#if WO
#endif
} {
z2.uw += vrmpy(y0.ub, x23x20.ub) //[0, 8]
z3.uw += vrmpy(y0.ub, x33x30.ub) //[0, 8]
#if WO
y0 = vmem(ptr_y++#2) //[1, 0]32x4
#endif
dcfetch(ptr_x0+#PREFETCH) //[1, 0]prefetch next line
} {
z2.uw += vrmpy(y1.ub, x27x24.ub) //[0, 9]
z3.uw += vrmpy(y1.ub, x37x34.ub) //[0, 9]
#if WO
y1 = vmem(ptr_y+#-1) //[1, 1]32x4
#endif
dcfetch(ptr_x1+#PREFETCH) //[1, 1]prefetch next line
} {
z2.uw += vrmpy(y2.ub, x2bx28.ub) //[0,10]
z3.uw += vrmpy(y2.ub, x3bx38.ub) //[0,10]
x0fx0cx0bx08 = memd(ptr_x0+#8) //[1, 2]
x07x04x03x00 = memd(ptr_x0++#16) //[1, 2]
#if WO
#endif
} {
z2.uw += vrmpy(y3.ub, x2fx2c.ub) //[0,11]
z3.uw += vrmpy(y3.ub, x3fx3c.ub) //[0,11]
x1fx1cx1bx18 = memd(ptr_x1+#8) //[1, 3]
x17x14x13x10 = memd(ptr_x1++#16) //[1, 3]
#if WO
#endif
}:endloop0
{
dcfetch(ptr_x2+#PREFETCH) //[1, 4]prefetch next line
z0.uw += vrmpy(y0.ub, x03x00.ub) //[1, 4]
z1.uw += vrmpy(y0.ub, x13x10.ub) //[1, 4]
#if WO
y2 = vmem(ptr_y++#2) //[1, 4]32x4
#endif
} {
dcfetch(ptr_x3+#PREFETCH) //[1, 5]prefetch next line
z0.uw += vrmpy(y1.ub, x07x04.ub) //[1, 5]
z1.uw += vrmpy(y1.ub, x17x14.ub) //[1, 5]
#if WO
y3 = vmem(ptr_y+#-1) //[1, 5]32x4
#endif
} {
z0.uw += vrmpy(y2.ub, x0bx08.ub) //[1, 6]
z1.uw += vrmpy(y2.ub, x1bx18.ub) //[1, 6]
x2fx2cx2bx28 = memd(ptr_x2+#8) //[1, 6]
x27x24x23x20 = memd(ptr_x2++#16) //[1, 6]
#if WO
#endif
} {
z0.uw += vrmpy(y3.ub, x0fx0c.ub) //[1, 7]
z1.uw += vrmpy(y3.ub, x1fx1c.ub) //[1, 7]
x3fx3cx3bx38 = memd(ptr_x3+#8) //[1, 7]
x37x34x33x30 = memd(ptr_x3++#16) //[1, 7]
} {
vmem(ptr_z++M0) = z0 //[E, ]
#if WO
#endif
z2.uw += vrmpy(y0.ub, x23x20.ub) //[1, 8]
z3.uw += vrmpy(y0.ub, x33x30.ub) //[1, 8]
p0 = cmp.gt(col_count, #1)
} {
if(p0)vmem(ptr_z++M0) = z1 //[E, ]
#if WO
#endif
z2.uw += vrmpy(y1.ub, x27x24.ub) //[1, 9]
z3.uw += vrmpy(y1.ub, x37x34.ub) //[1, 9]
p0 = cmp.gt(col_count, #2)
} {
z2.uw += vrmpy(y2.ub, x2bx28.ub) //[1,10]
z3.uw += vrmpy(y2.ub, x3bx38.ub) //[1,10]
} {
z2.uw += vrmpy(y3.ub, x2fx2c.ub) //[1,11]
z3.uw += vrmpy(y3.ub, x3fx3c.ub) //[1,11]
if(p0)vmem(ptr_z++M0) = z2.new //[E, ]
#if WO
#endif
p0 = cmp.gt(col_count, #3)
} {
if(p0)vmem(ptr_z++M0) = z3 //[E, ]
#if WO
#endif
col_count = add(col_count, #-4)
ptr_y = ptr_yi //[ , P]
}:endloop1
{
ptr_x = add(ptr_x, skip_back) //[E, ]next line
p1 = cmp.eq(out_height, #0)
if(!p1.new) jump:t .L_height
}
/*=============================================================================*/
{ r17:16 = memd(sp+#0) //restore stack
r19:18 = memd(sp+#8) //Q
} {
r21:20 = memd(sp+#16) //Q
r23:22 = memd(sp+#24) //Q
} {
r25:24 = memd(sp+#32) //Q
r27:26 = memd(sp+#40) //Q
} {
dealloc_return //Q
}
.L_end:
/*=============================================================================*/
.size gvmmpybbw_asm, .L_end-gvmmpybbw_asm
|
XiaoMi/nnlib | 4,292 | hexagon/asm_src/avgpool_aligned_hvx.S |
/*
* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
*/
#if 0
for (z = 0; z < out_depth; z++) {
/* foreach window y * foreach window x */
sum = 0;
for (in_y = start_y; in_y < end_y; in_y++) {
for (in_x = start_x; in_x < end_x; in_x++) {
uint32_t data = in0[z + in_depth * in_x + in_depth * in_width * in_y];
sum += data;
}
}
out0[z] = (sum / count);
}
#endif
.text
.global avgpool_aligned_hvx
.type avgpool_aligned_hvx, @function
.balign 32
avgpool_aligned_hvx:
/* ============================================================================ */
#define dsto r0 //dest ptr
#define srco r1 //src ptr
#define image_depth r2 //num bytes
#define win_width r3
#define win_height r4
#define image_width r5
#define scale r6
#define stride r7
#define stride0 r8
#define c0101 r9
#define src r10
#define z1z0 v1:0
#define z0 v0
#define z1 v1
#define x0 v2
#define y0 v3
#define z2 v4
#define z3 v5
#define vzero v6
/* ============================================================================ */
{
scale = memw(sp+#0)
M0 = image_depth
stride = sub(image_width, win_width)
} {
stride = mpyi(stride, image_depth)
c0101 = ##0x01010101
scale = combine(scale.L, scale.L)
} {
loop1(.L_vert, win_height)
vzero = #0
src = srco
srco = add(srco, #128)
} {
loop0(.L_horz, win_width)
z1z0 = vcombine(vzero, vzero)
}
/* ============================================================================ */
.balign 32
.L_vert:
.L_horz:
{
x0.tmp = vmem(src++M0) //+in_depth* in_x
z1z0.uh += vmpy(x0.ub, c0101.ub) //multiply vy 1 to uh
}:endloop0
{
src = add(src, stride)
loop0(.L_horz, win_width)
}:endloop1
{
z2.h = vmpy(z0.h, scale.h):<<1:rnd:sat
src = srco
image_depth = add(image_depth, #-128)
loop1(.L_vert, win_height)
} {
z3.h = vmpy(z1.h, scale.h):<<1:rnd:sat
z1z0 = vcombine(vzero, vzero)
srco = add(srco, #128)
p0 = !cmp.eq(image_depth, #0)
} {
y0.ub = vsat(z3.h, z2.h)
vmem(dsto++#1) = y0.new
if(p0) jump .L_vert
}
jumpr r31
.L_end:
/*==============================================================================*/
.size avgpool_aligned_hvx, .L_end-avgpool_aligned_hvx
|
XiaoMi/nnlib | 11,299 | hexagon/asm_src/renorm_h.S | /*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#if 0
Apply final combined requant and adjust channels
y = (gamma*(x / sigma - u / sigma) - beta) - gmin) * 255 / (gmax-gmin)
#endif
/* =================================================================================== */
.global renorm_asm
.balign 32
.type renorm_asm, @function
/* =================================================================================== */
renorm_asm:
/* =================================================================================== */
#define in_data r0 //ptr raw input
#define width32 r1 //num points in current d32 line
#define next_width r2 //next depth32 chunk stride
#define height r3 //hieght of acts
#define out_data r4 //ptr normalized result
#define ptr_mean r5 //mean mantissa / exponent
#define ptr_rsd r6 //1/sqrt mantissa / exponent
#define c15 r10 //constants 15
#define n r9 //number of itns
#define in_data1 r11 //ptr to input
#define out_data1 r8 //ptr to output
#define cm2 r7 //-2 for dealing hwords
#define cm128 r12 //-128
#define mean_shift r3 //value to shift left mean
#define rsd_shift r13 //value to shift right qrsd
#define l2cntrl r15:14 //l2 fetch controls
#define l2cntrl_h r15 //
#define l2cntrl_l r14 //
#define fetch r6 //
/* =================================================================================== */
#define vzero v21 //nil
#define qrsd_mant v4 //recip stdev mantissa
#define qrsd_exp v5 //recip stdev exponent
#define vc15 v16 //rounding value 1 << (qe+14)
#define qmean_exp v12 //mean exponent
#define qmean_mant v14 //mean mantissa
#define data127_0b v20 //data in bytes
#define data127_0h v1:0 //expanded to hwords after * -128
#define data127_0h_hi v1 //hi reg
#define data127_0h_lo v0 //lo reg
#define phi v7 //products
#define plo v2 //products
#define phis v8 //products
#define plos v3 //products
#define nhis v18 //products
#define nlos v13 //products
#define phic v9 //products
#define ploc v6 //products
#define pb v16 //final values to be stored
#define vmean_shift v30 //mean adjust
#define vrsd_shift v19 //1/sd adjust
#define qmean v26 //temp
#define qmean_mant_o_e v23:22 //mean mantissas
#define qmean_mant_e v22 //mean mantissas
#define qmean_mant_o v23 //mean mantissas
#define qrsd_mant_o_e v25:24 //1/sd mantissas
#define qrsd_mant_e v24 //1/sd mantissas
#define qrsd_mant_o v25 //1/sd mantissas
#define qrsd_exp_o_e v29:28 //1/sd exponents
#define qrsd_exp_o v29 //1/sd exponents
#define qrsd_exp_e v28 //1/sd exponents
#define PV(VSRC) .word (0x1DFFE020+VSRC)
#if __HEXAGON_ARCH__ > 60
#define MSHIFT 0x00010001 //1 bits of fraction for mean
#define QSHIFT 0x00060006 //increase right shift by 6
#else
#define MSHIFT 0x00010001 //expose 1 bit of fraction of mean
#define QSHIFT 0x00060006 //make -ve shift rights go away
#endif
/* =================================================================================== */
{ ptr_rsd = memw(sp+#0<<2) //[S,0]ptr to recip sqrt sd
c15 = ##0x000f000f //[S,0]15
vzero = #0 //[S,1]nil
} {
vc15 = vsplat(c15); //[S,1]constant 15
qrsd_mant = vmem(ptr_rsd+#0) //[S,1]load recip sd mant
cm128 = ##0x80808080 //-128 splatted
} {
loop1(.L_height, height) //[S,4]iterate over hegith lines
qrsd_exp = vmem(ptr_rsd+#1) //[S,2]
cm2 = #-2 //hwords
l2cntrl_l = #1 //1 line at a time
} {
rsd_shift = ##QSHIFT //assert rsd exp rightt by some
mean_shift = ##MSHIFT //assert mean left by some
} {
vmean_shift = vsplat(mean_shift) //mean exp adjust
l2cntrl_h = next_width //stride
l2cntrl_l = combine(width32.L, l2cntrl_l.L) //width , height
} {
qmean.tmp = vmem(ptr_mean+#1) //[S,3]load mean exp
qmean_exp.h = vadd(qmean.h, vc15.h) //[S,3]float -> int
n = lsr(width32, #7) //[S,3]128 bytes per itn.
} {
fetch = addasl(in_data, next_width, #1) //2 lines ahead
vrsd_shift = vsplat(rsd_shift) //splat the rsd expoent adjust
qmean_exp.h = vsub(qmean_exp.h, vmean_shift.h) //decrese mean exp
} {
l2fetch(fetch, l2cntrl) //fetch initial line
} {
qmean.tmp = vmem(ptr_mean+#0) //[S,4]loaf mean mant
qmean_mant.h = vasr(qmean.h, qmean_exp.h) //[S,4]convert to int mant >> exp
qrsd_exp.h = vadd(qrsd_exp.h, vrsd_shift.h) //add extra right shift to exp
q0 = vcmp.gt(qmean_exp.h, vc15.h) //if mean_exp > 15 flush to 0
} {
qrsd_mant_o_e = vdeal(qrsd_mant, qrsd_mant, cm2) //match the input o/e data
qmean_mant.h = vsub(vzero.h, qmean_mant.h) //mean = -mean
qrsd_exp.h = vmin(qrsd_exp.h, vc15.h) //[S,2]prevent wrap if > 15
} {
qrsd_exp_o_e = vdeal(qrsd_exp, qrsd_exp, cm2) //match the input o/e data
qmean_mant = vmux(q0, vzero, qmean_mant) //if exp > 15 flush mant
p3 = sp1loop0(.L_renorm, n) //start new loop
} {
qmean_mant_o_e = vdeal(qmean_mant, qmean_mant, cm2) //match the input o/e data
data127_0b.tmp = vmem(in_data+#0) //[P, 0]in_data += 128;
data127_0h.h = vmpy(data127_0b.ub, cm128.b) //[P, 0]
in_data1 = add(in_data, #128) //[P, 1]
}
/* =========================================================================== */
.balign 32
.L_height:
.L_renorm: //for (i = 0; i < height*width/4; i++) {
{ plo.h = vmpy(qrsd_mant_e.h, data127_0h_lo.h):<<1:rnd:sat //[0, 0](x * qrsd_mant)>>15
if(!p3) in_data = add(in_data, next_width) //[P, 1]update in ptr
if(!p3) out_data1 = out_data //[P, 1]
} {
phi.h = vmpy(qrsd_mant_o.h, data127_0h_hi.h):<<1:rnd:sat //[0, 1](x * qrsd_mant)>>15
pb.ub = vasr(phic.h, ploc.h, mean_shift):rnd:sat //[0, 1]
if(p3) vmem(out_data1++#1):nt = pb.new //[0, 1]out_data+=128;
} {
plos.h = vasr(plo.h, qrsd_exp_e.h) //[0, 2]apply exponent shift
if(!p3) out_data = add(out_data, next_width) //[P, 1]update line ptr
} {
phis.h = vasr(phi.h, qrsd_exp_o.h) //[0, 3]apply exponent shift
data127_0b.tmp = vmem(in_data1++#1) //[0, 3]in_data += 128;
data127_0h.h = vmpy(data127_0b.ub, cm128.b) //[0, 3] * 128 (-1 <<7)
} {
ploc.h = vsub(qmean_mant_e.h, plos.h) //[0, 4]x/sigma - u / sigma
phic.h = vsub(qmean_mant_o.h, phis.h) //[0, 4]
}:endloop0
/* =========================================================================== */
{ p3 = sp1loop0(.L_renorm, n) //start new loop
data127_0b.tmp = vmem(in_data+#0) //[P, 0]in_data += 128;
data127_0h.h = vmpy(data127_0b.ub, cm128.b) //[P, 0]*-128 for << 7
in_data1 = add(in_data, #128) //[P, 1]
} {
l2fetch(fetch, l2cntrl) //fetch next line
fetch = add(fetch, next_width) //lines ahead
} {
pb.ub = vasr(phic.h, ploc.h, mean_shift):rnd:sat //[E, 1]correct for shift
vmem(out_data1+#0):nt = pb.new //[E, 0]out_data+=128;
}:endloop1
/* =========================================================================== */
jumpr r31 //return
/* =========================================================================== */
.L_end:
.size renorm_asm, .L_end-renorm_asm
|
XiaoMi/nnlib | 24,029 | hexagon/asm_src/inconv2dbbb_s1_d32_v60_h.S | /*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
* FUNCTIONS : gvconv2dbbb_s1_v60_asm
*
* DESCRIPTION
* Perform 2d convolution using elements of size in_depth < 32. Results are
* scaled and saturated to 8bits. Max and Min accumulations are kept.
* Horizontal stride is 1 and depth = 4
*
* ARCHITECTURE : QDSP6V60 + HVX
*
* REVISION HISTORY:
* =================
*
* Author Date Comments
* -------------------------------------------------------------
* DJH 10/13/17 created
*
* CYCLE-COUNT:
*
* MEMORY
* CODESIZE = 848 bytes
* STACK = 80 bytes
* ASSUMPTIONS
* Input depth assumed 4 stride horz assumed 1
*/
/*=============================================================================*/
.text
.file "inconv2dbbb_s1_d32_v60_h.S"
.global inconv2dbbb_s1_v60_asm
.balign 32
.type inconv2dbbb_s1_v60_asm, @function
/* parameters:
* r0 ( const uint8_t * input,
* r1 const uint8_t * weights,
* r2 uint8_t * output,
* r3 int in_width_pad,
* r4 int next_out_width_row,
* r5 int out_width,
* PARMW(0) int indepth,
* PARMW(1) int filt_width,
* PARMW(2) int filt_height,
* PARMW(3) int num_out_lines,
* PARMW(4) int32_t * minmax_buf,
* PARMW(5) int recip_level,
* PARMW(6) const int32_t *biasbuf,
* PARMW(7) const int32_t *ptr_suma,
* PARMW(8) int next_suma,
* PARMW(9) int stride_height_width,
* PARMW(10) int recip_shamt);
*/
inconv2dbbb_s1_v60_asm:
/*=============================================================================*/
#define ptr_xi r0 //data
#define ptr_wi r1 //weights
#define ptr_zi r2 //results
#define in_width r3 //(pad_l+in_width+pad_r)
#define out_width_stride_depth r4 //next line amount
#define out_width r5 //is amount of work to be done
#define in_depth r26 //0 is always 4 so not really needed
#define filt_width r17 //1 horizontal fuilter width
#define filt_height r8 //2 filt_height lines per filter
#define out_height r9 //3 number of vertical lines to perform
#define ptr_max r13 //4 maximum and minum buffer
#define recip_level r14 //5 255 / (MAX - MIN) - used to scale to bytes
#define filt_sum r15 //6 gemsumb
#define ptr_suma r18 //7 gemsuma activations
#define next_suma_buf r1 //8 stride for suma buffer
#define stride_v_h r10 //9 stride_vert | stride_horz=1 ->M0
#define sum0 r19 //temp sum of activations
#define sum1 r19 //temp sum of activations
#define sum2 r19 //temp sum of activations
#define sum3 r19 //temp sum of activations
/*=============================================================================*/
#define fetch_ptr r6 //horizontal fetch ptr
#define fetch_ptr0 r2 //vertical fetch ptr
#define in_width_stride_depth r15 //in_width * stride * in_depth for next output
#define ptr_x0 r16 //tmp pointer to activations
#define ptr_x1 r23 //dynamic pointer to activations
#define next_outputs r27 //jump to input ptr for next set of outputs
#define ptr_w r20 //pointer to weights
#define in_width_depth r22 //width of input image in bytes
#define recip_shamt r7 //left shift in result
#define ptr_z r24 //pointer to outputs
#define col_count r25 //column count, how much of width used
#define x13x10_x03x00 r11:10 //8 activations output 1 0/4
#define x13x10 r11 //4 activations output 1
#define x03x00 r10 //4 activations output 0
#define x33x30_x23x20 r13:12 //8 activations output 2 3
#define x33x30 r13 //4 activations output 3
#define x23x20 r12 //4 activations output 2
#define x43x40 r21
/*=============================================================================*/
#define PV(VSRC) .word (0x1DFFE020+VSRC) //debug vec reg
#define PS(SSRC) .word (0x1DFFE100+SSRC) //debug sca reg
#define s0 v0 //accumulator for output 0
#define s1 v1 //accumulator for output 1
#define s1s0 v1:0 //accumulator
#define s2 v2 //accumulator for output 2
#define s3 v3 //accumulator for output 3
#define s3s2 v3:2 //
#define y0 v8 //weights/quantized output
#define y1 v9 //weights/quantized output
#define y2 v10 ///quantized output
#define y3 v11 ///quantized output
#define wsum v14 //initialzed to in_offsey*wsum + biasoffset
#define maxomaxe v13:12 //
#define maxe v12 //
#define maxo v13 //
#define minomine v19:18 //
#define mine v18 //
#define mino v19 //
#define recipvec v15 //7f80000000 / max
#define SSR <<1:rnd:sat:shift //simplfy mpy instruction
/*=============================================================================*/
#define FRAMESIZE 72
#define PARMW(n) sp+#(8+FRAMESIZE+4*(n))
{ allocframe(#FRAMESIZE) // 0th entry on stack is (72+8)/4 =20 ints
} {
memd(sp+#0) = r17:16 //
memd(sp+#8) = r19:18 //
} {
memd(sp+#16) = r21:20 //
memd(sp+#24) = r23:22 //
r23 = ##0x7fffffff //max pos
} {
memd(sp+#32) = r25:24 //
memd(sp+#40) = r27:26 //
mine = vsplat(r23)
} {
memw(sp+#52) = ptr_wi //
maxe = vnot(mine) // all -0x80000000
} {
in_depth = memw(PARMW(0)) //
filt_height = memw(PARMW(2)) //extract filt_height
} {
filt_width = memw(PARMW(1)) //extract filt_width
memw(sp+#56) = ptr_zi //
p3 = cmp.eq(filt_height, #1) //is filt height 1?
} {
p2 = cmp.eq(filt_width, #1) //is filt width = 1?
p0 = !tstbit(filt_width, #0) //is filt 1xN? - even?
filt_width = lsr(filt_width, #1) //
out_height = memw(PARMW(3)) //number of output lines
} {
recip_level = memw(PARMW(5)) //
filt_sum = memw(PARMW(6)) //
in_width_depth = mpyi(in_width, in_depth) //in_depth * in_width line
} {
wsum = vmem(filt_sum+#0) //
recipvec = vsplat(recip_level) //
stride_v_h = memw(PARMW(9)) //
} {
next_suma_buf = memw(PARMW(8)) //
ptr_suma = memw(PARMW(7)) //
in_width_stride_depth=mpy(in_width_depth.L,stride_v_h.H)//
stride_v_h = zxth(stride_v_h) //
} {
in_depth = mpyi(in_depth, stride_v_h) //
stride_v_h = asl(stride_v_h, #2) //v-h = 1 1
memw(sp+#60) = ptr_suma //
recip_shamt = memw(PARMW(10))
} {
next_outputs=mpyi(filt_height,in_width_depth)//filt_height*in_width*in_depth
filt_height = add(filt_height, #-1) //
M0 = stride_v_h //
} {
next_outputs += mpyi(stride_v_h, #-4) //
memw(sp+#60) += next_suma_buf //
}
/* ---------------------------------------------------------------------------- */
.balign 32
.L_height:
{ sum0 = memw(ptr_suma++M0) //stride = 1
loop1(.L_filt_height, filt_height) //[P, 0]for(fil=0;fil<h*depth/32;fil+=1){
out_height = add(out_height, #-1) //
} {
s0 = vsplat(sum0) //
sum1 = memw(ptr_suma++M0) //stride = 1
ptr_w = memw(sp+#52) //[P, 0]ptr_wi initialize filter pointer
col_count = out_width //end for height
} {
s0.w = vadd(wsum.w, s0.w) //
s1 = vsplat(sum1) //
sum2 = memw(ptr_suma++M0) //stride = 1
ptr_x0 = ptr_xi //ptr_xi
} {
s1.w = vadd(wsum.w, s1.w) //
s2 = vsplat(sum2) //
sum3 = memw(ptr_suma++M0) //stride = 1
fetch_ptr0 = add(ptr_x0, in_width_depth) //l1 fetch from next lin
} {
ptr_z = memw(sp+#56) //ptr_zi
memw(sp+#56) += out_width_stride_depth //ptr_zi += out_width_stride_depth
s2.w = vadd(wsum.w, s2.w) //
s3 = vsplat(sum3) //
} {
ptr_xi = add(ptr_xi, in_width_stride_depth) //ptr_xi+=in_width_stride_depth in_width*stride*in_depth)
s3.w = vadd(wsum.w, s3.w) //
y0 = vmem(ptr_w++#1) //[P,-1]
fetch_ptr = fetch_ptr0 //[P,-1]
}
/* ---------------------------------------------------------------------------- */
.balign 32
.L_width:
{
p1 = cmp.eq(recip_shamt,#0)
if(p3) jump .L_filt_heighteq1 //[P, 0]
}
.L_filt_height:
{ loop0(.L_filt_widthN_1, filt_width) //[P, 0]ki is k1/32 - 0
x13x10_x03x00 = memd(ptr_x0+#0<<3) //[P, 0]stride = 1
ptr_x1 = add(ptr_x0, #8) //[P, 0]
if(p2) jump .L_epi_onlyN_1 //[P, 0]if width = 1 skip kernel
}
.balign 32
.L_filt_widthN_1:
{ s0.uw += vrmpy(y0.ub, x03x00.ub) //[0, 0]
s1.uw += vrmpy(y0.ub, x13x10.ub) //[0, 0]
x33x30_x23x20 = memd(ptr_x1++#1<<3) //[0, 0]
} {
y1.cur = vmem(ptr_w++#1) //[0, 1]
s0.uw += vrmpy(y1.ub, x13x10.ub) //[0, 1]
s1.uw += vrmpy(y1.ub, x23x20.ub) //[0, 1]
x43x40 = memw(ptr_x1+#0<<3) //
} {
s2.uw += vrmpy(y0.ub, x23x20.ub) //[0, 2]
s3.uw += vrmpy(y0.ub, x33x30.ub) //[0, 2]
y0 = vmem(ptr_w++#1) //[0, 2]
x13x10_x03x00 = combine(x33x30,x23x20) //[0, 2]x13x10_x03x00 = memd(ptr_x1++#1<<3)
} {
s2.uw += vrmpy(y1.ub, x33x30.ub) //[0, 3]
s3.uw += vrmpy(y1.ub, x43x40.ub) //[0, 3]
dcfetch(fetch_ptr+#0<<5) //[0, 3]
fetch_ptr = add(fetch_ptr, #32) //[0, 3]
}:endloop0
/* ---------------------------------------------------------------------------- */
if(p0) jump .L_skipN_1
.L_epi_onlyN_1:
{ s0.uw += vrmpy(y0.ub, x03x00.ub) //[E, 0]
s1.uw += vrmpy(y0.ub, x13x10.ub) //[E, 0]
fetch_ptr = add(fetch_ptr0, in_width_depth) //[E, 0]
x33x30_x23x20 = memd(ptr_x1+#0<<3) //[E, 1]
} {
fetch_ptr0 = add(fetch_ptr0, in_width_depth) //[E, 0]
s2.uw += vrmpy(y0.ub, x23x20.ub) //[E, 1]
s3.uw += vrmpy(y0.ub, x33x30.ub) //[E, 1]
y0 = vmem(ptr_w++#1) //[P, 1]
}
.L_skipN_1:
{
ptr_x0 = add(ptr_x0, in_width_depth) //[P, 0]
}:endloop1
/* ---------------------------------------------------------------------------- */
.balign 32
.L_filt_heighteq1:
{ loop0(.L_filt_width1, filt_width) //[P, 0]ki is k1/32 - 0
x13x10_x03x00 = memd(ptr_x0+#0<<3) //[P, 0]stride = 1
ptr_x1 = add(ptr_x0, #8) //[P, 0]
if(p2) jump .L_epi_only1 //[P, 0]if width = 1 skip kernel
}
.balign 32
.L_filt_width1:
{ s0.uw += vrmpy(y0.ub, x03x00.ub) //[0, 0]
s1.uw += vrmpy(y0.ub, x13x10.ub) //[0, 0]
x33x30_x23x20 = memd(ptr_x1++#1<<3) //[0, 0]
} {
y1.cur = vmem(ptr_w++#1) //[0, 1]
s0.uw += vrmpy(y1.ub, x13x10.ub) //[0, 1]
s1.uw += vrmpy(y1.ub, x23x20.ub) //[0, 1]
x43x40 = memw(ptr_x1+#0<<3) //
} {
s2.uw += vrmpy(y0.ub, x23x20.ub) //[0, 2]
s3.uw += vrmpy(y0.ub, x33x30.ub) //[0, 2]
y0 = vmem(ptr_w++#1) //[0, 2]
x13x10_x03x00 = combine(x33x30,x23x20) //[0, 2]x13x10_x03x00 = memd(ptr_x1++#1<<3)
} {
s2.uw += vrmpy(y1.ub, x33x30.ub) //[0, 3]
s3.uw += vrmpy(y1.ub, x43x40.ub) //[0, 3]
dcfetch(fetch_ptr+#0<<5) //[0, 3]
fetch_ptr = add(fetch_ptr, #32) //[0, 3]
}:endloop0
/* ---------------------------------------------------------------------------- */
.L_epi_only1:
{
ptr_x0 = add(ptr_x0, in_width_depth) //[P, 0]
if(!p1) jump .L_go_apply_shamt /// alternate path if shamt !=0
if(p0) jump .L_skip1
}
{ s0.uw += vrmpy(y0.ub, x03x00.ub) //[E, 0]
s1.uw += vrmpy(y0.ub, x13x10.ub) //[E, 0]
x33x30_x23x20 = memd(ptr_x1+#0<<3) //[E, 0]
} {
s2.uw += vrmpy(y0.ub, x23x20.ub) //[E, 1]
s3.uw += vrmpy(y0.ub, x33x30.ub) //[E, 1]
}
// *** NOTE: the code at L_go_apply_shamt needs to replicate effects of
// code above the ".L_back_from_apply_shamt" label.
/* ---------------------------------------------------------------------------- */
.L_skip1:
{ y0.w = vmpye(s0.w, recipvec.uh) //[E, 2]
maxe.w = vmax(maxe.w, s0.w) //[E, 2]see if s0 is max
mine.w = vmin(mine.w, s0.w) //[E, 2]see if s0 is max
ptr_x0 = sub(ptr_x0, next_outputs) //[E, 2]reset data ptr to next 4
} {
y0.w+= vmpyo(s0.w, recipvec.h):SSR //[E, 3]
maxe.w = vmax(maxe.w, s1.w) //[E, 3]
mine.w = vmin(mine.w, s1.w) //[E, 3]see if s1 is max
fetch_ptr0 = sub(fetch_ptr0, next_outputs) //[E, 0]
}
.L_back_from_apply_shamt:
{
y1.w = vmpye(s1.w, recipvec.uh) //[E, 4]
mine.w = vmin(mine.w, s2.w) //[E, 4]see if s2 is max
maxe.w = vmax(maxe.w, s2.w) //[E, 4]
sum0 = memw(ptr_suma++M0) //[P, 4]stride = 1
} {
y1.w+= vmpyo(s1.w, recipvec.h):SSR //[E, 5]
mine.w = vmin(mine.w, s3.w) //[E, 5]see if s3 is max
maxe.w = vmax(maxe.w, s3.w) //[E, 5]
dcfetch(fetch_ptr0+#0<<5) //[E, 1]
} {
y2.w = vmpye(s2.w, recipvec.uh) //[E, 6]
ptr_w = memw(sp+#52) //[P, 6]ptr_wi initialize filter pointer
} {
s0 = vsplat(sum0) //[P, 7]
sum1 = memw(ptr_suma++M0) //[P, 7]stride = 1
fetch_ptr = fetch_ptr0 //[P, 7]
} {
s0.w = vadd(wsum.w, s0.w) //[P, 8]
s1 = vsplat(sum1) //[P, 8]
sum2 = memw(ptr_suma++M0) //[P, 8]stride = 1
} {
y1.h = vpack(y1.w, y0.w):sat //[E, 9]#>>16
y2.w+= vmpyo(s2.w, recipvec.h):SSR //[E, 9]
loop1(.L_filt_height, filt_height) //[P, 9]for(fil=0;fil<h*depth/32;fil+=1){
} {
y3.w = vmpye(s3.w, recipvec.uh) //[E,10]#
y0 = vmem(ptr_w++#1) //[P,10]
dcfetch(fetch_ptr0+#1<<5) //[E, 3]
} {
y3.w+= vmpyo(s3.w, recipvec.h):SSR //[E,11]
s1.w = vadd(wsum.w, s1.w) //[P,11]
fetch_ptr0 = add(ptr_x0, in_width_depth) //[P, 6]l1 fetch from next lin
} {
s2 = vsplat(sum2) //[P,12]
sum3 = memw(ptr_suma++M0) //[P,12]stride = 1
col_count = add(col_count, #-4) //[E,12]
y3.h = vpack(y3.w, y2.w):sat //[E,12]#sat8 <0, >255
} {
p1 = cmp.eq(col_count, #0) //[E,13]
s2.w = vadd(wsum.w, s2.w) //[P,13]
s3 = vsplat(sum3) //[P,13]
} {
s3.w = vadd(wsum.w, s3.w) //[P,14]
y3.ub = vpack(y3.h, y1.h):sat //[E,14]#sat8 <0, >255
vmem(ptr_z++#1) = y3.new //[E,14]next weidthstore 4*32bytes
if(!p1) jump:t .L_width //[E,14]
}//end cols per line
/* ---------------------------------------------------------------------------- */
{
ptr_suma = memw(sp+#60) //next suma line
memw(sp+#60) += next_suma_buf //
p1 = cmp.eq(out_height, #0) //
if(!p1.new) jump:t .L_height //next height
}//end lines per block
/* ---------------------------------------------------------------------------- */
/* scale mine, maxe according to recipvec ; apply to overall range */
{
mino.w = vmpye(mine.w, recipvec.uh)
ptr_max = memw(PARMW(4)) //ptr pre computed max value in output
} {
mine = vmem(ptr_max+#1)
mino.w+= vmpyo(mine.w, recipvec.h):SSR
} {
mine.w = vmin( mine.w, mino.w)
vmem(ptr_max+#1) = mine.new //[E, 2]
maxo.w = vmpye(maxe.w, recipvec.uh)
} {
maxo.w+= vmpyo(maxe.w, recipvec.h):SSR
maxe = vmem(ptr_max+#0)
} {
maxe.w = vmax( maxe.w, maxo.w)
vmem(ptr_max+#0) = maxe.new //[E, 1]
}
/*=============================================================================*/
{ r17:16 = memd(sp+#0) //restore stack
r19:18 = memd(sp+#8) //Q
} {
r21:20 = memd(sp+#16) //Q
r23:22 = memd(sp+#24) //Q
} {
r25:24 = memd(sp+#32) //Q
r27:26 = memd(sp+#40) //Q
} {
dealloc_return //Q
}
/*=============================================================================*/
.L_go_apply_shamt: // still need to process 'if(p0) jump skip'
if(p0) jump .L_skip1x
{ s0.uw += vrmpy(y0.ub, x03x00.ub) //[E, 0]
s1.uw += vrmpy(y0.ub, x13x10.ub) //[E, 0]
x33x30_x23x20 = memd(ptr_x1+#0<<3) //[E, 0]
} {
s2.uw += vrmpy(y0.ub, x23x20.ub) //[E, 1]
s3.uw += vrmpy(y0.ub, x33x30.ub) //[E, 1]
}
/* ---------------------------------------------------------------------------- */
.L_skip1x:
// shift s0,s1,s2,s3 << recip_shamt
// and:
// find y0 = prod s0*recip_shamt
// apply s0,s1 to min/max
// adjust ptr_x0 and fetch_ptr0
//
{
ptr_x0 = sub(ptr_x0, next_outputs) //[E, 2]reset data ptr to next 4
fetch_ptr0 = sub(fetch_ptr0, next_outputs) //[E, 0]
s0.w = vasl(s0.w,recip_shamt)
} {
maxe.w = vmax(maxe.w, s0.w) //[E, 2]see if s0 is max
mine.w = vmin(mine.w, s0.w) //[E, 2]see if s0 is max
s1.w = vasl(s1.w,recip_shamt)
} {
maxe.w = vmax(maxe.w, s1.w) //[E, 2]see if s1 is max
y0.w = vmpye(s0.w, recipvec.uh) //[E, 2]
s2.w = vasl(s2.w,recip_shamt)
} {
mine.w = vmin(mine.w, s1.w) //[E, 2]see if s1 is max
y0.w+= vmpyo(s0.w, recipvec.h):SSR //[E, 3]
s3.w = vasl(s3.w,recip_shamt)
jump .L_back_from_apply_shamt
}
.L_end:
/*=============================================================================*/
.size inconv2dbbb_s1_v60_asm, .L_end-inconv2dbbb_s1_v60_asm
/*=============================================================================*/
|
XiaoMi/nnlib | 3,782 | hexagon/asm_src/l2pref.S | /*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
*/
/*======================================================================*/
/* FUNCTIONS : l2fetch driver */
/* */
/* DESCRIPTION */
/* Make l2fetch instruciton a little easier to use */
/* Fetch a block of data height * width with stride */
/* ARCHITECTURE : QDSP6V6 + HVX */
/*======================================================================*/
/* REVISION HISTORY: */
/* ================= */
/* */
/* Author Date Comments */
/* ------------------------------------------------------------- */
/* DJH 03/07/16 created */
/*======================================================================*/
.text
.global l2pref
.type l2pref, @function
/*======================================================================*/
#define ptr r0
#define height r1
#define width r2
#define stride r3
#define prehprel r3:2
#define preh r3
#define prel r2
/*======================================================================*/
.balign 32
l2pref:
/*======================================================================*/
{
preh = zxth(stride)
prel = combine(width.L, height.L)
} {
l2fetch(ptr, prehprel)
} {
jumpr r31
}
/*======================================================================*/
.L_end:
/*======================================================================*/
.size l2pref, .L_end-l2pref
|
XiaoMi/nnlib | 41,430 | hexagon/asm_src/gvconv2dbbb_circ6_d64_v65_h.S | /*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted (subject to the limitations in the
* disclaimer below) provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
Memory
CODESIZE 1408 bytes
STACK 112 bytes
Description
Utilize the v65 vrmpy instructions. Common wiehgts with 2 inputs and 2 outputs. 2 data inputs
are in a pair. Key is to feed each input with a different stream. Solution is to shuffle the
stream with a delayed version of itself. This doubles the size of the activations so a
smaller circular buffer of size filt_height*input depth*width*2.
Example depth = 16 shuffle blocks of 4 bytes together e.g. x00 =[x00.0,x00.1,x00.2,x00.3]
x00 x01 x02 x03|x10 x11 x12 x13|x20 x21 x22 x23|x30 x31 x32 x33
x40 x41 x42 x43|x50 x51 x52 x53|x60 x61 x62 x63|x70 x71 x72 x73
x80 x81 x82 x83|x90 x91 x92 x93|xa0 xa1 xa2 xa3|xb0 xb1 xb2 xb3
xc0 xc1 xc2 xc3|xd0 xd1 xd2 xd3|xe0 xe1 xe2 xe3|xf0 xf1 xf2 xf3
to
x00 x40 x01 x41 x02 x42 x03 x43|x10 x50 x11 x51 x12 x52 x13 x53|
x20 x60 x21 x61 x22 x62 x23 x63|x30 x70 x31 x71 x32 x72 x33 x73|
x40 x80 x41 x81 x42 x82 x43 x83|x50 x90 x51 x91 x52 x92 x53 x93|
x60 xa0 x61 xa1 x62 xa2 x63 xa3|x70 xb0 x71 xb1 x72 xb2 x73 xb3|
x80 xc0 x81 xc1 x82 xc2 x83 xc3|x90 xd0 x91 xd1 x92 xd2 x93 xd3|
xa0 xe0 xa1 xe1 xa2 xe2 xa3 xe3|xb0 xf0 xb1 xf1 xb2 xf2 xb3 xf3|
xc0 xc1 xc2 xc3 |xd0 xd1 xd2 xd3 |
xe0 xe1 xe2 xe3 |xf0 xf1 xf2 xf3 |
So each memd access into the buffer access two streams which are delayed from each other.
While this is occuring the sequence can be aligned so that the extra computation on the
ends can be minimized.
To further minimize memory the circular buffer is updated inside the kernel each
line.
This version consumes 2 sets fo weights (64) each time and produces 2
rows of the output at once.
*/
/*===============================================================================*/
.text
.file "gvconv2dbbb_circ6_d64_v65_h.S"
.global gvconv2dbbb_circ6_d64_v65_asm
.balign 32
.type gvconv2dbbb_circ6_d64_v65_asm, @function
gvconv2dbbb_circ6_d64_v65_asm:
/*===============================================================================*/
#define PV(VSRC) .word (0x1DFFE020+VSRC) //debug vec reg
#define PS(SSRC) .word (0x1DFFE100+SSRC) //debug vec reg
/*===============================================================================*/
/* ---------------------------------- CALL REGS -------------------------------- */
#define ptr_xi r0 //12 activation data
#define ptr_wi r1 //13 weights
#define ptr_zi r2 //14 results
#define next_inbuf_width r3 //(pad_l+in_width+pad_r)
#define out_width_depth r4 //next line amount
#define out_width r5 //15 amount of work to be done
#define stride_h_w r6 //30 stride_height, stride_width
#define in_depth r22 //31 input depth multiples of 32
#define filt_width r23 //32 horizontal fuilter width
#define filt_height r8 //33 filt_height lines per filter
#define out_height r9 //34 number of vertical lines to perform
#define ptr_filtsum r24 //35 includes the computation filt_sum * in_offset + biasvec
#define ptr_max r31 //36 maximum and minum buffer
#define recip_level r26 //37 255 / (MAX - MIN) - used to scale to bytes
#define out_width_32 r7 //38 actual out_width in depth32
#define ptr_cbufi r16 //39 read buffer pointer
#define zshift r6 //40 extra shift on output before quantization
#define in_zero r25 //41
#define store_cntrl r11 //42
//#define ptr_equalize r17 //43
#define cbuf_eob r27 //18 end of cuirc buffer
#define cbuf_size r28 //19 size in bytes of circ buf -1
#define weight_stride r15 //20 distance to next set of weights
/* --------------------------------- SCALER REGS ------------------------------- */
#define cm4 r2 //shuffle/deal ints
#define col_count r2 //horizontal counter
#define in_width_32 r3 //total input width in bytes in buffer
#define x50_x20 r17:16 //1-----1
#define x40_x10 r19:18 //111----
#define x30_x00 r17:16 //-111---
#define x51_x21 r15:14 //--11---
#define x41_x11 r19:18 //---1111
#define x31_x01 r15:14 //----111
#define ptr_wi_ptr_xi r1:0 //
#define fetch_ptr_base r1 //base pointer for l1 prefetch
#define fetch_ptr r10 //current pointer for l1 prefetch
#define stride r12 //current to next input
#define ptr_x0 r26 //base input pointer
#define ptr_x1 r13 //current input ptr
#define ptr_w0 r20 //even output depth 32 weights
#define ptr_w1 r21 //odd output depth 32 weights
#define ptr_z0 r0 //even output depth 32 outputs
#define ptr_z1 r25 //21 write buffer sp position and odd output depth 32 outputs
#define out_width_64 r22 //
#define adjust r10 //
#define delta r7 //difference between filt height and stride height
#define align r11 //temp alignment of output
#define vplut r18 //vector pred lookup
#define ones r19 //0x01010101
/* ---------------------------------- VEC REGS -------------------------------- */
#define tmax v18
#define tmin v19
//#define wscale0 v0 //
#define wscale1 v23 //
#define vin_zero v9 //
#define vpred0 v24 //
#define vpred1 v25 //
#define vpred2 v31 //
#define s15_s12 v23:22 //odd output accs 2,6
#define s14_s11 v21:20 //odd output accs 1,5
#define s13_s10 v19:18 //odd output accs 0,4
#define s05_s02 v15:14 //even output accs 2,6
#define s04_s01 v13:12 //even output accs 1,5
#define s03_s00 v11:10 //even output accs 0,4
#define s15 v23 //odd acc 5
#define s12 v22 //odd acc 2
#define s14 v21 //odd acc 4
#define s11 v20 //odd acc 1
#define s13 v19 //odd acc 3
#define s10 v18 //odd acc 0
#define s05 v15 //even acc 5
#define s02 v14 //even acc 2
#define s04 v13 //even acc 4
#define s01 v12 //even acc 1
#define s03 v11 //even acc 3
#define s00 v10 //even acc 0
#define w00 v27 //weights even 0-31
// note w01,w10,w11 are only used as .tmp destinations.
#define w01 v0 //weights even 32-63
#define w10 v0 //weights odd 0-31
#define w11 v0 //weights odd 32-63
#define vrecip0 v1 //reciprocal 255/MAx replicated
#define vrecip1 v30 //reciprocal 255/MAx replicated
#define s0_sh v8 //shifted value
#define s1_sh v26 //shifted value
#define wsum0 v8 //2 //sum of weights column + bias add 0-31
#define wsum1 v26 //3 //sum of weights column + bias add 32-63
#define d010 v27 //even lines upper 16bit packed accs 0,1
#define d032 v28 //even lines upper 16bit packed accs 2,3
#define d03210 v28 //8bit shifted, packed saturated 0-3
#define d054 v29 //even lines upper 16bit packed accs 4,5
#define d110 v27 //odd lines upper 16bit packed accs 0,1
#define d132 v28 //odd lines upper 16bit packed accs 2,3
#define d13210 v28 //8bit shifted, packed saturated 0-3
#define d154 v29 //odd lines upper 16bit packed accs 4,5
#define maxo_maxe v5:4 //packed maxes
#define maxo v5 //odd maxes
#define maxe v4 //even maxes
#define mino_mine v7:6 //packed mins
#define mino v7 //odd mins
#define mine v6 //even mins
#define gmax v2 //odd mins
#define gmin v3 //even mins
#define SSR <<1:rnd:sat:shift //simplfy mpy instruction
/* --------------------------------------------------------------------------- */
{ allocframe(#112) //0th entry on stack is 112+8)/4=30 ints
stride_h_w = memw(sp+#0<<2) //stride horizontl and vertical
} {
memd(sp+#4<<2) = r21:20 //save 20,21
memd(sp+#6<<2) = r23:22 //save 22,23
r23 = #0x80000001
} {
memd(sp+#0<<2) = r17:16 //save 16,17
memd(sp+#2<<2) = r19:18 //save 18,19
maxe = vsplat(r23) // maxe <- -0x7fffffff
} {
memd(sp+#8<<2) = r25:24 //save 24,25
memd(sp+#10<<2) = r27:26 //save 26,27
mine.w = vabs(maxe.w) // mine <- +0x7fffffff
} {
memd(sp+#12<<2) = ptr_wi_ptr_xi //save weights: activation
memw(sp+#14<<2) = ptr_zi //save output ptr
maxo = maxe //
mino = mine
} {
filt_height = memw(sp+#33<<2) //filter height
memw(sp+#15<<2) = out_width //save output width
stride = zxth(stride_h_w) //horizontal stride
//nop //
} {
ptr_max = memw(sp+#36<<2) //get max/min ptr
in_depth = memw(sp+#31<<2) //input depth
} {
filt_width = memw(sp+#32<<2) //filter width
out_height = memw(sp+#34<<2) //height of output
stride = asl(stride, #5) //32 * stride_w
} {
cbuf_size = mpyi(filt_height, in_depth) //circular buffer size
gmax = vmem(ptr_max+#0) //
in_zero = memw(sp+#41<<2) //
} {
gmin = vmem(ptr_max+#1) //
store_cntrl = memw(sp+#42<<2) //
} {
in_zero = vsplatb(in_zero) //
cbuf_size = mpyi(cbuf_size, next_inbuf_width) //circular buffer size
ptr_cbufi = memw(sp+#39<<2) //circular buffer
dcfetch(ptr_xi+#0<<6)
} {
cbuf_size = add(cbuf_size, cbuf_size) //x2
vin_zero = vsplat(in_zero) //
recip_level = memw(sp+#37<<2) //255/max
dcfetch(ptr_xi+#1<<6)
} {
weight_stride=mpy(filt_width.L,filt_height.L) //offset between filter rows
memw(sp+#21<<2) = ptr_cbufi //cbuf write ptr
out_width_32 = memw(sp+#38<<2) //total width of output
filt_width = asl(filt_width, #2) //*32/8
} {
weight_stride=mpy(weight_stride.L,in_depth.L) //distance between weight rows
vrecip0 = vmem(recip_level++#2) //used to compress to 8bits 255/max
filt_width = add(filt_width, #-1) //account for epilog
dcfetch(ptr_xi+#2<<6)
} {
ptr_wi += asl(weight_stride,#5) //weights stride
cbuf_eob = add(ptr_cbufi, cbuf_size) //end of circ buffer marker
vpred1 = vmem(store_cntrl+#1) //
dcfetch(ptr_xi+#3<<6)
} {
filt_height = mpyi(filt_height, in_depth) //total number of depth32 filter rows
vpred2 = vmem(store_cntrl+#2) //
weight_stride = asl(weight_stride, #6) //
cbuf_eob = add(cbuf_eob, #-4) //make so comparison is >= eob
} {
filt_height = lsr(filt_height, #5) //num d32 rows in filter
out_width_64 = add(out_width_32, out_width_32) //
memw(sp+#20<<2) = ptr_wi //spill weight stride for later
memw(sp+#24<<2) = weight_stride //
} {
in_width_32 = asl(next_inbuf_width, #6) //next d32 line x 2
filt_height = add(filt_height, #-1)
ptr_filtsum = memw(sp+#35<<2) //ptr to the sum of filters+offset
col_count = memw(sp+#15<<2) //initialize width count
} {
vrecip1 = vmem(recip_level+#-1)
memw(sp+#37<<2) = recip_level //255/max
}
/* -------------------------------------------------------------------------- */
.balign 32
.L_height:
{ wsum0 = vmem(ptr_filtsum+#0) //set 1st weight offset
ptr_x0 = memw(sp+#12<<2) //ptr_x0=ptr_cbufi read circ buffer
loop1(.L_filt_height, filt_height) //setup vertical filte rloop
out_height = add(out_height, #-1) //decrement height count
} { //buffer read ptr if ptr_xi >= buf_size-=size
wsum1 = vmem(ptr_filtsum+#1) //set 2nd weight offset
fetch_ptr_base = add(ptr_x0, in_width_32) //fetch is next row ahead
ptr_z0 = memw(sp+#14<<2) //output ptr for even lines
p3 = sp1loop0(.L_filt_width, filt_width) //set up inne rloop for next time
} {
ptr_z1 = add(ptr_z0, out_width_32) //
s03_s00 = vcombine(wsum0,wsum0) //init sum0 and 4
s04_s01 = vcombine(wsum0,wsum0) //init sum1 and 5
p1 = cmp.gt(fetch_ptr_base, cbuf_eob) //if prefetch >= circ buffer wrap around
} {
s15_s12 = vcombine(wsum1,wsum1) //init sum 2 and 6
s05_s02 = vcombine(wsum0,wsum0) //init sum2 and 6
ptr_w0 = memw(sp+#13<<2) //access ptr weight
memw(sp+#14<<2) += out_width_64 //update output ptr to next out_width_32
} {
s13_s10 = vcombine(wsum1,wsum1) //init sum 0 and 4
s14_s11 = vcombine(wsum1,wsum1) //init sum 1 and 5
ptr_w1 = memw(sp+#20<<2) //access weights stride
if(p1)fetch_ptr_base=sub(fetch_ptr_base,cbuf_size)//wrap fetch ptr around independently
}
.L_width:
{ x50_x20 = memd(ptr_x0+stride<<#2) //[0, 0]load pt 2 and 6
w00 = vmem(ptr_w0++#1) //[0, 0]1st 32 weights of out depth
p0 = cmp.eq(filt_height, #0)
if(p0.new) jump:nt .L_last1
}
.balign 32
.L_filt_height:
{ ptr_x1 = ptr_x0 //set up currne tinput ptr
ptr_x0 = add(ptr_x0, in_width_32) //if >= buf_size -= buf_size
fetch_ptr_base=add(fetch_ptr_base,in_width_32) //if >= buf_size -= buf_size
x40_x10 = memd(ptr_x0+stride<<#1) //[0, 1]load pt 1 5
} {
dcfetch(fetch_ptr_base+#0<<6) //[0, 6]fetch 64bytes-2 lots 8 x 4 bytes
fetch_ptr = add(fetch_ptr_base, #64) //initial fetch ptr
p0 = cmp.gt(ptr_x0, cbuf_eob) //[E,10]
if(p0.new)ptr_x0 = sub(ptr_x0, cbuf_size) //[E,10]wrap around end of buffer
}
.balign 32
.L_filt_width:
{ s05_s02.w += vrmpy(w00.b, x50_x20.ub) //[0, 2]macc 2,6 out 0
w10.tmp = vmem(ptr_w1+#0) //[0, 2]1st 32 weights stream 1
s15_s12.w += vrmpy(w10.b, x50_x20.ub) //[0, 2]acc 2,6 out 1
x30_x00 = memd(ptr_x1++#1<<3) //[0, 2]load pts 0, 4
} {
w10.tmp = vmem(ptr_w1++#1) //[0, 3]same 1st 32weight stream 1
s13_s10.w += vrmpy(w10.b, x30_x00.ub) //[0, 3]acc 0,4,1,5 stream 1
s14_s11.w += vrmpy(w10.b, x40_x10.ub) //[0, 3]
x51_x21 = memd(ptr_x1+stride<<#2) //[0, 3]
} {
s04_s01.w += vrmpy(w00.b, x40_x10.ub) //[0, 4]
w01.tmp = vmem(ptr_w0+#0) //[0, 4]2nd 32weights stream 0
s05_s02.w += vrmpy(w01.b, x51_x21.ub) //[0, 4]acc 2,3,6,7
x41_x11 = memd(ptr_x1+stride<<#1) //[0, 4]
} {
s03_s00.w += vrmpy(w00.b, x30_x00.ub) //[0, 5]acc 0,4,1,5 out 0
w11.tmp = vmem(ptr_w1+#0) //[0, 5]2nd 32weights of stream 1
s15_s12.w += vrmpy(w11.b, x51_x21.ub) //[0, 5]
x31_x01 = memd(ptr_x1++#1<<3) //[0, 5]
} {
w01.tmp = vmem(ptr_w0++#1) //[0, 6]same 2nd 32weights stream 0
s03_s00.w += vrmpy(w01.b, x31_x01.ub) //[0, 6]
s04_s01.w += vrmpy(w01.b, x41_x11.ub) //[0, 6]
dcfetch(fetch_ptr+#0<<6) //[0, 6]fetch 64bytes-2 lots 8 x 4 bytes
} {
fetch_ptr = add(fetch_ptr, #64) //[0, 7]inc fetch by 32/64 bytes (1 line)
x50_x20 = memd(ptr_x1+stride<<#2) //[1, 0]load pt 2 and 6
w00 = vmem(ptr_w0++#1) //[1, 0]1st 32 weights of out depth
nop //
} {
w11.tmp = vmem(ptr_w1++#1) //[0, 8]same 2nd 32weights stream 1
s13_s10.w += vrmpy(w11.b, x31_x01.ub) //[0, 8]
s14_s11.w += vrmpy(w11.b, x41_x11.ub) //[0, 8]
x40_x10 = memd(ptr_x1+stride<<#1) //[1, 1]load pt 1 5
}:endloop0
{ s05_s02.w+= vrmpy(w00.b, x50_x20.ub) //[1, 2]macc 2,6 out 0
w10.tmp = vmem(ptr_w1+#0) //[1, 2]1st 32 weights stream 1
s15_s12.w += vrmpy(w10.b, x50_x20.ub) //[1, 2]acc 2,6 out 1
x30_x00 = memd(ptr_x1++#1<<3) //[1, 2]load pts 0, 4
} {
w10.tmp = vmem(ptr_w1++#1) //[1, 3]same 1st 32weight stream 1
s13_s10.w += vrmpy(w10.b, x30_x00.ub) //[1, 3]acc 0,4,1,5 stream 1
s14_s11.w += vrmpy(w10.b, x40_x10.ub) //[1, 3]
x51_x21 = memd(ptr_x1+stride<<#2) //[1, 3]
} {
s04_s01.w += vrmpy(w00.b, x40_x10.ub) //[1, 4]
w01.tmp = vmem(ptr_w0+#0) //[1, 4]2nd 32weights stream 0
s05_s02.w += vrmpy(w01.b, x51_x21.ub) //[1, 4]acc 2,3,6,7
x41_x11 = memd(ptr_x1+stride<<#1) //[1, 4]
} {
s03_s00.w += vrmpy(w00.b, x30_x00.ub) //[1, 5]acc 0,4,1,5 out 0
w11.tmp = vmem(ptr_w1+#0) //[1, 5]2nd 32weights of stream 1
s15_s12.w += vrmpy(w11.b, x51_x21.ub) //[1, 5]
x31_x01 = memd(ptr_x1++#1<<3) //[1, 5]
} {
w01.tmp = vmem(ptr_w0++#1) //[1, 6]same 2nd 32weights stream 0
s03_s00.w += vrmpy(w01.b, x31_x01.ub) //[1, 6]
s04_s01.w += vrmpy(w01.b, x41_x11.ub) //[1, 6]
//dcfetch(fetch_ptr+#0<<6) //[1, 6]fetch 64bytes-2 lots 8 x 4 bytes
} {
w00 = vmem(ptr_w0++#1) //[E, 0]1st 32 weights of out depth
x50_x20 = memd(ptr_x0+stride<<#2) //[E, 0]load pt 2 and 6
p1 = cmp.gt(fetch_ptr_base, cbuf_eob) //[E,10]
p3 = sp1loop0(.L_filt_width, filt_width) //set up inne rloop for next time
} {
w11.tmp = vmem(ptr_w1++#1) //[1, 8]same 2nd 32weights stream 1
s13_s10.w += vrmpy(w11.b, x31_x01.ub) //[1, 8]
s14_s11.w += vrmpy(w11.b, x41_x11.ub) //[1, 8]
if(p1)fetch_ptr_base=sub(fetch_ptr_base,cbuf_size)//[E,10]wrap around end fetch ptr
}:endloop1
.L_last1:
{ ptr_x1 = ptr_x0 //set up currne tinput ptr
ptr_x0 = add(ptr_x0, in_width_32) //if >= buf_size -= buf_size
} {
p3 = sp1loop0(.L_filt_width1, filt_width) //set up inne rloop for next time
p0 = cmp.gt(ptr_x0, cbuf_eob) //[E,10]
if(p0.new)ptr_x0 = sub(ptr_x0, cbuf_size) //[E,10]wrap around end of buffer
} {
fetch_ptr = addasl(ptr_x0, stride, #4) //initial fetch ptr
x40_x10 = memd(ptr_x1+stride<<#1) //[0, 1]load pt 1 5
nop; nop
}
.balign 32
.L_filt_width1:
{ s05_s02.w+= vrmpy(w00.b, x50_x20.ub) //[0, 2]macc 2,6 out 0
w10.tmp = vmem(ptr_w1+#0) //[0, 2]1st 32 weights stream 1
s15_s12.w += vrmpy(w10.b, x50_x20.ub) //[0, 2]acc 2,6 out 1
x30_x00 = memd(ptr_x1++#1<<3) //[0, 2]load pts 0, 4
} {
w10.tmp = vmem(ptr_w1++#1) //[0, 3]same 1st 32weight stream 1
s13_s10.w += vrmpy(w10.b, x30_x00.ub) //[0, 3]acc 0,4,1,5 stream 1
s14_s11.w += vrmpy(w10.b, x40_x10.ub) //[0, 3]
x51_x21 = memd(ptr_x1+stride<<#2) //[0, 3]
} {
s04_s01.w += vrmpy(w00.b, x40_x10.ub) //[0, 4]
w01.tmp = vmem(ptr_w0+#0) //[0, 4]2nd 32weights stream 0
s05_s02.w += vrmpy(w01.b, x51_x21.ub) //[0, 4]acc 2,3,6,7
x41_x11 = memd(ptr_x1+stride<<#1) //[0, 4]
} {
s03_s00.w += vrmpy(w00.b, x30_x00.ub) //[0, 5]acc 0,4,1,5 out 0
w11.tmp = vmem(ptr_w1+#0) //[0, 5]2nd 32weights of stream 1
s15_s12.w += vrmpy(w11.b, x51_x21.ub) //[0, 5]
x31_x01 = memd(ptr_x1++#1<<3) //[0, 5]
} {
w01.tmp = vmem(ptr_w0++#1) //[0, 6]same 2nd 32weights stream 0
s03_s00.w += vrmpy(w01.b, x31_x01.ub) //[0, 6]
s04_s01.w += vrmpy(w01.b, x41_x11.ub) //[0, 6]
dcfetch(fetch_ptr+#0<<6) //[0, 6]fetch 64bytes-2 lots 8 x 4 bytes
} {
fetch_ptr = add(fetch_ptr, #64) //[1, 7]inc fetch by 32/64 bytes (1 line)
x50_x20 = memd(ptr_x1+stride<<#2) //[0, 0]load pt 2 and 6
w00 = vmem(ptr_w0++#1) //[0, 0]1st 32 weights of out depth
} {
x40_x10 = memd(ptr_x1+stride<<#1) //[1, 1]load pt 1 5
w11.tmp = vmem(ptr_w1++#1) //[0, 7]same 2nd 32weights stream 1
s13_s10.w += vrmpy(w11.b, x31_x01.ub) //[0, 7]
s14_s11.w += vrmpy(w11.b, x41_x11.ub) //[0, 7]
}:endloop0
{ s05_s02.w+= vrmpy(w00.b, x50_x20.ub) //[1, 2]macc 2,6 out 0
w10.tmp = vmem(ptr_w1+#0) //[1, 2]1st 32 weights stream 1
s15_s12.w += vrmpy(w10.b, x50_x20.ub) //[1, 2]acc 2,6 out 1
x30_x00 = memd(ptr_x1++#1<<3) //[1, 2]load pts 0, 4
} {
w10.tmp = vmem(ptr_w1++#1) //[1, 3]same 1st 32weight stream 1
s13_s10.w += vrmpy(w10.b, x30_x00.ub) //[1, 3]acc 0,4,1,5 stream 1
s14_s11.w += vrmpy(w10.b, x40_x10.ub) //[1, 3]
x51_x21 = memd(ptr_x1+stride<<#2) //[1, 3]
} {
s04_s01.w += vrmpy(w00.b, x40_x10.ub) //[1, 4]
w01.tmp = vmem(ptr_w0+#0) //[1, 4]2nd 32weights stream 0
s05_s02.w += vrmpy(w01.b, x51_x21.ub) //[1, 4]acc 2,3,6,7
x41_x11 = memd(ptr_x1+stride<<#1) //[1, 4]
} {
s03_s00.w += vrmpy(w00.b, x30_x00.ub) //[1, 5]acc 0,4,1,5 out 0
w11.tmp = vmem(ptr_w1+#0) //[1, 5]2nd 32weights of stream 1
s15_s12.w += vrmpy(w11.b, x51_x21.ub) //[1, 5]
x31_x01 = memd(ptr_x1++#1<<3) //[1, 5]
} {
w01.tmp = vmem(ptr_w0++#1) //[1, 6]same 2nd 32weights stream 0
s03_s00.w += vrmpy(w01.b, x31_x01.ub) //[1, 6]
s04_s01.w += vrmpy(w01.b, x41_x11.ub) //[1, 6]
dcfetch(fetch_ptr+#0<<6) //[1, 6]fetch 64bytes-2 lots 8 x 4 bytes
} {
w11.tmp = vmem(ptr_w1++#1) //[1, 7]same 2nd 32weights stream 1
s13_s10.w += vrmpy(w11.b, x31_x01.ub) //[1, 7]
s14_s11.w += vrmpy(w11.b, x41_x11.ub) //[1, 7]
p2 = cmp.ge(col_count,#6) // Do we have a full 6 cols?
}
/* ------------------------------------------------------------------------ */
// q2 q1 q0
// 0 --54 3210
// 0000 0011 1111 3210 = if(q0) vmem = 3210 --54 = vmux(q0, --54,3210) if(q1) vmem = --54 if(q2) vmem = ----
// 1 -54- 2103
// 0000 0111 1110 210- = if(q0) vmem = 2103 2543 = vmux(q0, -54-,2103) if(q1) vmem = 2543 if(q2) vmem = ----
// 2 54-- 1032
// 0000 1111 1100 10-- = if(q0) vmem = 1032 5432 = vmux(q0, 54--,1032) if(q1) vmem = 5432 if(q2) vmem = ----
// 3 4--5 0321
// 0001 1111 1000 0--- = if(q0) vmem = 0321 4321 = vmux(q0, 4--5,0321) if(q1) vmem = 4321 if(q2) vmem = ---5
/* ------------------------------------------------------------------------ */
{ zshift = memw(sp+#40<<2) //final shift 7 + 16
mine.w = vmin(mine.w, s00.w) //min accumulation
maxe.w = vmax(maxe.w, s00.w) //max accumulation
if (!p2) s05 = s00 //
} {
s0_sh.w = vasl(s00.w, zshift) //
maxe.w = vmax(maxe.w, s01.w) //max accumulation
mine.w = vmin(mine.w, s01.w) //min accumulation
if (!p2) s15 = s00 //
} {
s1_sh.w = vasl(s01.w, zshift) //
maxe.w = vmax(maxe.w, s02.w) //max accumulation
mine.w = vmin(mine.w, s02.w) //min accumulation
// adjust = memw(sp+#23<<2) //
} {
s00.w = vmpye(s0_sh.w, vrecip0.uh) //
maxe.w = vmax(maxe.w, s03.w) //max accumulation
mine.w = vmin(mine.w, s03.w) //min accumulation
col_count = add(col_count, #-6) //decrement width count by 8
} {
s00.w += vmpyo(s0_sh.w, vrecip0.h):SSR //
mine.w = vmin(mine.w, s04.w) //min accumulation
maxe.w = vmax(maxe.w, s04.w) //max accumulation
// ptr_x0 = sub(ptr_x0, adjust) //-=filt_height if stride_height > filt_height
} {
s01.w = vmpye(s1_sh.w, vrecip0.uh) //
s0_sh.w = vasl(s02.w, zshift) //
mine.w = vmin(mine.w, s05.w) //min accumulation
} {
s01.w += vmpyo(s1_sh.w, vrecip0.h):SSR //
maxe.w = vmax(maxe.w, s05.w) //max accumulation
mino.w = vmin(mino.w, s11.w) //min accumulation
ones.L = #0x0101 //
} {
s02.w = vmpye(s0_sh.w, vrecip0.uh) //
s1_sh.w = vasl(s03.w, zshift) //
mino.w = vmin(mino.w, s13.w) //min accumulation
ones.H = #0x0101 //
} {
s02.w += vmpyo(s0_sh.w, vrecip0.h):SSR //
mino.w = vmin(mino.w, s10.w) //min accumulation
maxo.w = vmax(maxo.w, s11.w) //max accumulation
vplut = extractu(ptr_z0, #2, #5) //1100000 -> 0x08080808
} {
d010.h = vpack(s01.w, s00.w):sat //pack high 16bits of accs
s03.w = vmpye(s1_sh.w, vrecip0.uh) //
s0_sh.w = vasl(s04.w, zshift) //
align = sub(#128, ptr_z0) //
} {
s03.w += vmpyo(s1_sh.w, vrecip0.h):SSR //
maxo.w = vmax(maxo.w, s10.w) //max accumulation
mino.w = vmin(mino.w, s15.w) //min accumulation
ptr_x0 += mpyi(stride, #12) //stride*2*3 advance buffer by 6 outputs
} {
s04.w = vmpye(s0_sh.w, vrecip0.uh) //
s1_sh.w = vasl(s05.w, zshift) //
mino.w = vmin(mino.w, s14.w) //min accumulation
vplut = asl(ones, vplut) // 3,2,1,0
} {
d032.h = vpack(s03.w, s02.w):sat //pack high 16bits of accs
s04.w += vmpyo(s0_sh.w, vrecip0.h):SSR //
s0_sh.w = vasl(s10.w, zshift) //
} {
s05.w = vmpye(s1_sh.w, vrecip0.uh) //
mino.w = vmin(mino.w, s12.w) //min accumulation
p3 = sp1loop0(.L_filt_width, filt_width) //set up inne rloop for next time
} {
maxo.w = vmax(maxo.w, s12.w) //max accumulation
s05.w += vmpyo(s1_sh.w, vrecip0.h):SSR //
d03210.ub = vpack(d032.h, d010.h):sat //shift 16bits by zshift
} {
vmemu(ptr_z0+#0) = d03210 //
maxo.w = vmax(maxo.w, s13.w) //max accumulation
s10.w = vmpye(s0_sh.w, vrecip1.uh) //
} {
d054.h = vpack(s05.w, s04.w):sat //pack high 16bits of accs
s1_sh.w = vasl(s11.w, zshift) //
s10.w += vmpyo(s0_sh.w, vrecip1.h):SSR //
} {
s11.w = vmpye(s1_sh.w, vrecip1.uh) //
s0_sh.w = vasl(s12.w, zshift) //
maxo.w = vmax(maxo.w, s15.w) //max accumulation
} {
s11.w += vmpyo(s1_sh.w, vrecip1.h):SSR //
d054.ub = vpack(vin_zero.h, d054.h):sat //shift 16bits by zshift
s1_sh.w = vasl(s13.w, zshift) //
} {
maxo.w = vmax(maxo.w, s14.w) //max accumulation
s12.w = vmpye(s0_sh.w, vrecip1.uh) //
} {
s12.w += vmpyo(s0_sh.w, vrecip1.h):SSR //
d054 = vror(d054, align) //
} {
s13.w = vmpye(s1_sh.w, vrecip1.uh) //
loop1(.L_filt_height, filt_height) //setup vertical filte rloop
} {
q1 = vand(vpred1, vplut) //
q2 = vand(vpred2, vplut) //
d110.h = vpack(s11.w, s10.w):sat //pack high 16bits of accs
} {
if(q1) vmem(ptr_z0+#1):nt = d054 //
s0_sh.w = vasl(s14.w, zshift) //
p1 = cmp.gt(col_count, #0) //
} {
if(q2) vmem(ptr_z0+#2):nt = d054 //
s13.w += vmpyo(s1_sh.w, vrecip1.h):SSR //
ptr_z0 = add(ptr_z0, #192) //
} {
s14.w = vmpye(s0_sh.w, vrecip1.uh) //
s1_sh.w = vasl(s15.w, zshift) //
p3 = sp1loop0(.L_filt_width, filt_width) //setup inner filter loop
} {
d132.h = vpack(s13.w, s12.w):sat //pack high 16bits of accs
s14.w += vmpyo(s0_sh.w, vrecip1.h):SSR //
vplut = extractu(ptr_z1, #2, #5) //1100000 -> 0x08080808
align = sub(#128, ptr_z1) //
} {
ones = ##0x01010101 //
s15.w = vmpye(s1_sh.w, vrecip1.uh) //
wsum0 = vmem(ptr_filtsum+#0) //set 2nd weight offset
} {
s15.w += vmpyo(s1_sh.w, vrecip1.h):SSR //
d13210.ub = vpack(d132.h, d110.h):sat //shift 16bits by zshift
ptr_w0 = memw(sp+#13<<2) //access ptr weight
ptr_w1 = memw(sp+#20<<2) //access weights stride
} {
s05_s02 = vcombine(wsum0,wsum0) //init sum1 and 5
fetch_ptr_base = add(ptr_x0, in_width_32) //fetch is next row ahead
vplut = asl(ones, vplut) // 3,2,1,0
wsum1 = vmem(ptr_filtsum+#1) //set 2nd weight offset
} {
s03_s00 = vcombine(wsum0,wsum0) //init sum0 and 4
d154.h = vpack(s15.w, s14.w):sat //pack high 16bits of accs
p2 = cmp.gt(fetch_ptr_base, cbuf_eob) //[E,10]
if(p2.new)fetch_ptr_base=sub(fetch_ptr_base,cbuf_size)//[E,10]wrap around end fetch ptr
} {
if(p1) zshift = #0 // clear zshift (except last loop)
vmemu(ptr_z1+#0) = d13210 //
s10 = wsum1 //init sum 0 and 4
} {
maxe.w = vasl(maxe.w,zshift) // maxe <<= zshift (on last only)
s14_s11 = vcombine(wsum1,wsum1) //init sum 1 and 5
d154.ub = vpack(vin_zero.h, d154.h):sat //shift 16bits by zshift
} {
s15_s12 = vcombine(wsum1,wsum1) //init sum 1 and 5
s04_s01 = vcombine(wsum0,wsum0) //init sum1 and 5
//ptr_equalize = memw(sp+#43<<2) //
} {
s13 = wsum1 //init sum 0 and 4
d154 = vror( d154, align) //
q1 = vand(vpred1, vplut) //
// if(!p1) wscale0 = vrecip0 //
} {
if(q1) vmem(ptr_z1+#1):nt = d154 //
q2 = vand(vpred2, vplut) //
} {
if(q2) vmem(ptr_z1+#2):nt = d154 //
ptr_z1 = add(ptr_z1, #192) //
if (p1) jump .L_width //next 2 rows 8 points per row
}//endloop width
/* --------------------------------------------------------------------------- */
// need to apply << zshift to mine, maxo, mino;
// maxe has been done already
// The below then scales these by the per-depth gains, applies to gmin/gmax,
// and resets mine:maxe and mino:maxo to +7fffffff : -7fffffff
{ p0 = cmp.eq(out_height, #0) //are vertical lines done?
tmax.w = vmpye(maxe.w, vrecip0.uh) //
mine.w = vasl(mine.w,zshift) //
} {
tmax.w+= vmpyo(maxe.w, vrecip0.h):SSR //
maxe = #0
ptr_filtsum = add(ptr_filtsum, #256) //
wscale1 = vrecip1
} {
gmax.w = vmax(gmax.w, tmax.w)
tmin.w = vmpye(mine.w, vrecip0.uh) //
maxo.w = vasl(maxo.w,zshift) //
} {
// memw(sp+#43<<2) = ptr_equalize //
tmin.w+= vmpyo(mine.w, vrecip0.h):SSR //
mine = vnot(maxe) // 0xfffffff
col_count = memw(sp+#15<<2) //initialize width count
} {
mino.w = vasl(mino.w,zshift) //
gmin.w = vmin(gmin.w, tmin.w)
tmax.w = vmpye(maxo.w, wscale1.uh) //
recip_level = memw(sp+#37<<2) //255/max
} {
tmax.w+= vmpyo(maxo.w, wscale1.h):SSR //
mine.uw = vavg(mine.uw,maxe.uw) // 0x7fffffff
if(!p0)vrecip0 = vmem(recip_level++#1)
weight_stride = memw(sp+#24<<2) //
} {
gmax.w = vmax(gmax.w, tmax.w)
tmin.w = vmpye(mino.w, wscale1.uh) //
if(!p0)vrecip1 = vmem(recip_level++#1)
memw(sp+#13<<2) += weight_stride //ptr_w0 access ptr weight
} {
mino = mine
memw(sp+#37<<2) = recip_level //255/max
tmin.w+= vmpyo(mino.w, wscale1.h):SSR //
maxe.w = vsub(maxe.w,mine.w) // -0x7fffffff
} {
maxo = maxe
gmin.w = vmin(gmin.w, tmin.w)
memw(sp+#20<<2) += weight_stride //ptr_w1 access weights stride
if(!p0) jump .L_height //then go again
}
/* ------------------------------------------------------------------------ */
#if 0
.L_domax:
{ ptr_max = memw(sp+#36<<2) //get max/min ptr
cm4 = #-4 //define int based deal
} {
loop0(.L_peak, #4) //set up vec reduce
maxo_maxe = vdeal(maxe, maxe, cm4) //deal out odd and even
}
.L_peak:
{ maxe.w = vmax(maxe.w, maxo.w) //reduce
mino_mine = vdeal(mine, mine, cm4) //split out and and even min
} {
mine.w = vmin(mine.w, mino.w) //reduce mins by 2
} {
maxo_maxe = vdeal(maxe, maxe, cm4) //split out odd and even max
}:endloop0
{ maxe.w = vmax(maxo.w, maxe.w) //reduce max
vmem(ptr_max+#0) = maxe.new //store max
mino_mine = vdeal(mine, mine, cm4) //split out mins
} {
mine.w = vmin(mino.w, mine.w) //reduce mins to final 1
vmem(ptr_max+#1) = mine.new //store min
}
/* ------------------------------------------------------------------------ */
{ r17:16 = memd(sp+#0) //restore stack
r19:18 = memd(sp+#2<<2) //18,19
#else
{ vmem(ptr_max+#0) = gmax //store max
r17:16 = memd(sp+#0) //restore stack
} {
vmem(ptr_max+#1) = gmin //store min
r19:18 = memd(sp+#2<<2) //18,19
#endif
} {
r21:20 = memd(sp+#4<<2) //20,21
r23:22 = memd(sp+#6<<2) //22,23
} {
r25:24 = memd(sp+#8<<2) //24,25
r27:26 = memd(sp+#10<<2) //26,27
} {
dealloc_return //
}
/* ------------------------------------------------------------------------ */
.L_end:
/* ======================================================================== */
.size gvconv2dbbb_circ6_d64_v65_asm, .L_end-gvconv2dbbb_circ6_d64_v65_asm
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.