repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
wuxx/nanoDAP | 24,888 | software/v2.3c/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s | ;/**
; * @file startup_MK20D5.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD DMA_Error_IRQHandler ; DMA error interrupt
DCD Reserved21_IRQHandler ; Reserved interrupt 21
DCD FTFL_IRQHandler ; FTFL interrupt
DCD Read_Collision_IRQHandler ; Read collision interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD SWI_IRQHandler ; Software interrupt
DCD DefaultISR ; 62
DCD DefaultISR ; 63
DCD DefaultISR ; 64
DCD DefaultISR ; 65
DCD DefaultISR ; 66
DCD DefaultISR ; 67
DCD DefaultISR ; 68
DCD DefaultISR ; 69
DCD DefaultISR ; 70
DCD DefaultISR ; 71
DCD DefaultISR ; 72
DCD DefaultISR ; 73
DCD DefaultISR ; 74
DCD DefaultISR ; 75
DCD DefaultISR ; 76
DCD DefaultISR ; 77
DCD DefaultISR ; 78
DCD DefaultISR ; 79
DCD DefaultISR ; 80
DCD DefaultISR ; 81
DCD DefaultISR ; 82
DCD DefaultISR ; 83
DCD DefaultISR ; 84
DCD DefaultISR ; 85
DCD DefaultISR ; 86
DCD DefaultISR ; 87
DCD DefaultISR ; 88
DCD DefaultISR ; 89
DCD DefaultISR ; 90
DCD DefaultISR ; 91
DCD DefaultISR ; 92
DCD DefaultISR ; 93
DCD DefaultISR ; 94
DCD DefaultISR ; 95
DCD DefaultISR ; 96
DCD DefaultISR ; 97
DCD DefaultISR ; 98
DCD DefaultISR ; 99
DCD DefaultISR ; 100
DCD DefaultISR ; 101
DCD DefaultISR ; 102
DCD DefaultISR ; 103
DCD DefaultISR ; 104
DCD DefaultISR ; 105
DCD DefaultISR ; 106
DCD DefaultISR ; 107
DCD DefaultISR ; 108
DCD DefaultISR ; 109
DCD DefaultISR ; 110
DCD DefaultISR ; 111
DCD DefaultISR ; 112
DCD DefaultISR ; 113
DCD DefaultISR ; 114
DCD DefaultISR ; 115
DCD DefaultISR ; 116
DCD DefaultISR ; 117
DCD DefaultISR ; 118
DCD DefaultISR ; 119
DCD DefaultISR ; 120
DCD DefaultISR ; 121
DCD DefaultISR ; 122
DCD DefaultISR ; 123
DCD DefaultISR ; 124
DCD DefaultISR ; 125
DCD DefaultISR ; 126
DCD DefaultISR ; 127
DCD DefaultISR ; 128
DCD DefaultISR ; 129
DCD DefaultISR ; 130
DCD DefaultISR ; 131
DCD DefaultISR ; 132
DCD DefaultISR ; 133
DCD DefaultISR ; 134
DCD DefaultISR ; 135
DCD DefaultISR ; 136
DCD DefaultISR ; 137
DCD DefaultISR ; 138
DCD DefaultISR ; 139
DCD DefaultISR ; 140
DCD DefaultISR ; 141
DCD DefaultISR ; 142
DCD DefaultISR ; 143
DCD DefaultISR ; 144
DCD DefaultISR ; 145
DCD DefaultISR ; 146
DCD DefaultISR ; 147
DCD DefaultISR ; 148
DCD DefaultISR ; 149
DCD DefaultISR ; 150
DCD DefaultISR ; 151
DCD DefaultISR ; 152
DCD DefaultISR ; 153
DCD DefaultISR ; 154
DCD DefaultISR ; 155
DCD DefaultISR ; 156
DCD DefaultISR ; 157
DCD DefaultISR ; 158
DCD DefaultISR ; 159
DCD DefaultISR ; 160
DCD DefaultISR ; 161
DCD DefaultISR ; 162
DCD DefaultISR ; 163
DCD DefaultISR ; 164
DCD DefaultISR ; 165
DCD DefaultISR ; 166
DCD DefaultISR ; 167
DCD DefaultISR ; 168
DCD DefaultISR ; 169
DCD DefaultISR ; 170
DCD DefaultISR ; 171
DCD DefaultISR ; 172
DCD DefaultISR ; 173
DCD DefaultISR ; 174
DCD DefaultISR ; 175
DCD DefaultISR ; 176
DCD DefaultISR ; 177
DCD DefaultISR ; 178
DCD DefaultISR ; 179
DCD DefaultISR ; 180
DCD DefaultISR ; 181
DCD DefaultISR ; 182
DCD DefaultISR ; 183
DCD DefaultISR ; 184
DCD DefaultISR ; 185
DCD DefaultISR ; 186
DCD DefaultISR ; 187
DCD DefaultISR ; 188
DCD DefaultISR ; 189
DCD DefaultISR ; 190
DCD DefaultISR ; 191
DCD DefaultISR ; 192
DCD DefaultISR ; 193
DCD DefaultISR ; 194
DCD DefaultISR ; 195
DCD DefaultISR ; 196
DCD DefaultISR ; 197
DCD DefaultISR ; 198
DCD DefaultISR ; 199
DCD DefaultISR ; 200
DCD DefaultISR ; 201
DCD DefaultISR ; 202
DCD DefaultISR ; 203
DCD DefaultISR ; 204
DCD DefaultISR ; 205
DCD DefaultISR ; 206
DCD DefaultISR ; 207
DCD DefaultISR ; 208
DCD DefaultISR ; 209
DCD DefaultISR ; 210
DCD DefaultISR ; 211
DCD DefaultISR ; 212
DCD DefaultISR ; 213
DCD DefaultISR ; 214
DCD DefaultISR ; 215
DCD DefaultISR ; 216
DCD DefaultISR ; 217
DCD DefaultISR ; 218
DCD DefaultISR ; 219
DCD DefaultISR ; 220
DCD DefaultISR ; 221
DCD DefaultISR ; 222
DCD DefaultISR ; 223
DCD DefaultISR ; 224
DCD DefaultISR ; 225
DCD DefaultISR ; 226
DCD DefaultISR ; 227
DCD DefaultISR ; 228
DCD DefaultISR ; 229
DCD DefaultISR ; 230
DCD DefaultISR ; 231
DCD DefaultISR ; 232
DCD DefaultISR ; 233
DCD DefaultISR ; 234
DCD DefaultISR ; 235
DCD DefaultISR ; 236
DCD DefaultISR ; 237
DCD DefaultISR ; 238
DCD DefaultISR ; 239
DCD DefaultISR ; 240
DCD DefaultISR ; 241
DCD DefaultISR ; 242
DCD DefaultISR ; 243
DCD DefaultISR ; 244
DCD DefaultISR ; 245
DCD DefaultISR ; 246
DCD DefaultISR ; 247
DCD DefaultISR ; 248
DCD DefaultISR ; 249
DCD DefaultISR ; 250
DCD DefaultISR ; 251
DCD DefaultISR ; 252
DCD DefaultISR ; 253
DCD DefaultISR ; 254
DCD DefaultISR ; 255
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFD
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x8400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT Reserved21_IRQHandler [WEAK]
EXPORT FTFL_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA_Error_IRQHandler
Reserved21_IRQHandler
FTFL_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
Watchdog_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
I2S0_Tx_IRQHandler
I2S0_Rx_IRQHandler
UART0_LON_IRQHandler
UART0_RX_TX_IRQHandler
UART0_ERR_IRQHandler
UART1_RX_TX_IRQHandler
UART1_ERR_IRQHandler
UART2_RX_TX_IRQHandler
UART2_ERR_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
DefaultISR
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 14,055 | software/v2.3c/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s | ;/**
; * @file startup_MKL26Z.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD Reserved20_IRQHandler ; Reserved interrupt 20
DCD FTFA_IRQHandler ; FTFA interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C0 interrupt 25
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD UART0_IRQHandler ; UART0 status/error interrupt
DCD UART1_IRQHandler ; UART1 status/error interrupt
DCD UART2_IRQHandler ; UART2 status/error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT_IRQHandler ; PIT timer interrupt
DCD Reserved39_IRQHandler ; Reserved interrupt 39
DCD USB0_IRQHandler ; USB0 interrupt
DCD DAC0_IRQHandler ; DAC interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved45_IRQHandler ; Reserved interrupt 45
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTD_IRQHandler ; Port D interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
; <1=> RESET pin is dedicated
; <o.3> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x8400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved39_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
DefaultISR
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 10,458 | software/v2.3c/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s | ;/***********************************************************************
; * $Id: startup_LPC18xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
; *
; * Project: LPC18xx CMSIS Package
; *
; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 M0 Core
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD EZH_IRQHandler ; 19 EZH/EDM
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD M0s_IRQHandler ; 66 M0s
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
IF :LNOT::DEF:NO_CRP
#if defined(DAPLINK_BL)
AREA |.ARM.__at_0x1A0002FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
#endif
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0CORE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT EZH_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
; EXPORT RESERVED3 [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
; EXPORT RESERVED4 [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT M0s_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
EZH_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
;RESERVED3
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
;RESERVED4
WDT_IRQHandler
M0s_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 13,653 | software/v2.3c/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s | ;/**
; * @file startup_LPC11Uxx.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
IF :DEF:MBED_BOOTLOADER
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
ENDIF
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Power on RAM1 and USBRAM area
LDR R0, =0x40048080 ; System clock control
LDR R1, =0x0C00485F ; boot default + RAM1, USBRAM
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 13,491 | software/v2.3c/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S | ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Version : V4.1.0
;* Date : 29-April-2016
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* COPYRIGHT(c) 2016 STMicroelectronics
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 12,079 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_ld.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 15,346 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_hd_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 13,758 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_md_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 15,597 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_xl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 12,490 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_md.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0xdeadbeef ; Reserved
DCD __initial_sp ; Reserved
DCD Reset_Handler ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 15,145 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_hd.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 15,398 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_cl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 13,352 | software/test/led_test/Libraries/CMSIS/startup/startup_stm32f10x_ld_vl.s | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 1,100 | software/v2.3a/DAPLink/source/daplink/bootloader/SVC_Table.s | ;/**
; * @file SVC_Table.s
; * @brief SVC functions
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
AREA SVC_TABLE, CODE, READONLY
EXPORT SVC_Count
SVC_Cnt EQU (SVC_End-SVC_Table)/4
SVC_Count DCD SVC_Cnt
; Import user SVC functions here.
EXPORT SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
SVC_End
END
|
wuxx/nanoDAP | 1,113 | software/v2.3a/DAPLink/source/daplink/interface/SVC_Table.s | ;/**
; * @file SVC_Table.s
; * @brief SVC config for application
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
AREA SVC_TABLE, CODE, READONLY
EXPORT SVC_Count
SVC_Cnt EQU (SVC_End-SVC_Table)/4
SVC_Count DCD SVC_Cnt
; Import user SVC functions here.
EXPORT SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
SVC_End
END
|
wuxx/nanoDAP | 13,613 | software/v2.3a/DAPLink/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S | ;*******************************************************************************
; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
; OTHER DEALINGS IN THE SOFTWARE.
;
; Except as contained in this notice, the name of Maxim Integrated
; Products, Inc. shall not be used except as stated in the Maxim Integrated
; Products, Inc. Branding Policy.
;
; The mere transfer of this software does not imply any licenses
; of trade secrets, proprietary technology, copyrights, patents,
; trademarks, maskwork rights, or any other form of intellectual
; property whatsoever. Maxim Integrated Products, Inc. retains all
; ownership rights.
;*******************************************************************************
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __initial_sp
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Reserved
DCD DAPLINK_HIC_ID ; Reserved
DCD DAPLINK_VERSION ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; Ptr to Board info, family info other target details
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Maxim 32620 Externals interrupts
DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */
DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */
DCD FLC_IRQHandler /* 18:03 Flash Controller */
DCD RTC0_IRQHandler /* 19:04 RTC INT0 */
DCD RTC1_IRQHandler /* 20:05 RTC INT1 */
DCD RTC2_IRQHandler /* 21:06 RTC INT2 */
DCD RTC3_IRQHandler /* 22:07 RTC INT3 */
DCD PMU_IRQHandler /* 23:08 PMU */
DCD USB_IRQHandler /* 24:09 USB */
DCD AES_IRQHandler /* 25:10 AES */
DCD MAA_IRQHandler /* 26:11 MAA */
DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */
DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */
DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
DCD TMR0_IRQHandler /* 38:23 Timer32-0 */
DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
DCD TMR1_IRQHandler /* 40:25 Timer32-1 */
DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
DCD TMR2_IRQHandler /* 42:27 Timer32-2 */
DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
DCD TMR3_IRQHandler /* 44:29 Timer32-3 */
DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
DCD TMR4_IRQHandler /* 46:31 Timer32-4 */
DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
DCD TMR5_IRQHandler /* 48:33 Timer32-5 */
DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
DCD UART0_IRQHandler /* 50:35 UART0 */
DCD UART1_IRQHandler /* 51:36 UART1 */
DCD UART2_IRQHandler /* 52:37 UART0 */
DCD UART3_IRQHandler /* 53:38 UART1 */
DCD PT_IRQHandler /* 54:39 PT */
DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */
DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */
DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */
DCD I2CS_IRQHandler /* 58:43 I2C Slave */
DCD SPI0_IRQHandler /* 59:44 SPI0 */
DCD SPI1_IRQHandler /* 60:45 SPI1 */
DCD SPI2_IRQHandler /* 61:46 SPI2 */
DCD SPIB_IRQHandler /* 62:47 SPI Bridge */
DCD OWM_IRQHandler /* 63:48 1-Wire Master */
DCD AFE_IRQHandler /* 64:49 AFE */
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT PreInit
IMPORT SystemInit
IMPORT __main
LDR R0, =PreInit
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
MemManage_Handler PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
DefaultIRQ_Handler PROC
EXPORT CLKMAN_IRQHandler [WEAK]
EXPORT PWRMAN_IRQHandler [WEAK]
EXPORT FLC_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT RTC3_IRQHandler [WEAK]
EXPORT PMU_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT MAA_IRQHandler [WEAK]
EXPORT WDT0_IRQHandler [WEAK]
EXPORT WDT0_P_IRQHandler [WEAK]
EXPORT WDT1_IRQHandler [WEAK]
EXPORT WDT1_P_IRQHandler [WEAK]
EXPORT GPIO_P0_IRQHandler [WEAK]
EXPORT GPIO_P1_IRQHandler [WEAK]
EXPORT GPIO_P2_IRQHandler [WEAK]
EXPORT GPIO_P3_IRQHandler [WEAK]
EXPORT GPIO_P4_IRQHandler [WEAK]
EXPORT GPIO_P5_IRQHandler [WEAK]
EXPORT GPIO_P6_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR16_0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR16_1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR16_2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR16_3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT TMR16_4_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT TMR16_5_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PT_IRQHandler [WEAK]
EXPORT I2CM0_IRQHandler [WEAK]
EXPORT I2CM1_IRQHandler [WEAK]
EXPORT I2CM2_IRQHandler [WEAK]
EXPORT I2CS_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPIB_IRQHandler [WEAK]
EXPORT OWM_IRQHandler [WEAK]
EXPORT AFE_IRQHandler [WEAK]
CLKMAN_IRQHandler
PWRMAN_IRQHandler
FLC_IRQHandler
RTC0_IRQHandler
RTC1_IRQHandler
RTC2_IRQHandler
RTC3_IRQHandler
PMU_IRQHandler
USB_IRQHandler
AES_IRQHandler
MAA_IRQHandler
WDT0_IRQHandler
WDT0_P_IRQHandler
WDT1_IRQHandler
WDT1_P_IRQHandler
GPIO_P0_IRQHandler
GPIO_P1_IRQHandler
GPIO_P2_IRQHandler
GPIO_P3_IRQHandler
GPIO_P4_IRQHandler
GPIO_P5_IRQHandler
GPIO_P6_IRQHandler
TMR0_IRQHandler
TMR16_0_IRQHandler
TMR1_IRQHandler
TMR16_1_IRQHandler
TMR2_IRQHandler
TMR16_2_IRQHandler
TMR3_IRQHandler
TMR16_3_IRQHandler
TMR4_IRQHandler
TMR16_4_IRQHandler
TMR5_IRQHandler
TMR16_5_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PT_IRQHandler
I2CM0_IRQHandler
I2CM1_IRQHandler
I2CM2_IRQHandler
I2CS_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPIB_IRQHandler
OWM_IRQHandler
AFE_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 14,117 | software/v2.3a/DAPLink/source/hic_hal/maxim/max32625/armcc/startup_MAX32625.S | ;*******************************************************************************
; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
; OTHER DEALINGS IN THE SOFTWARE.
;
; Except as contained in this notice, the name of Maxim Integrated
; Products, Inc. shall not be used except as stated in the Maxim Integrated
; Products, Inc. Branding Policy.
;
; The mere transfer of this software does not imply any licenses
; of trade secrets, proprietary technology, copyrights, patents,
; trademarks, maskwork rights, or any other form of intellectual
; property whatsoever. Maxim Integrated Products, Inc. retains all
; ownership rights.
;*******************************************************************************
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __initial_sp
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Reserved
DCD DAPLINK_HIC_ID ; Reserved
DCD DAPLINK_VERSION ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; Ptr to Board info, family info other target details
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Maxim 32625 Externals interrupts
DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */
DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */
DCD FLC_IRQHandler /* 18:03 Flash Controller */
DCD RTC0_IRQHandler /* 19:04 RTC INT0 */
DCD RTC1_IRQHandler /* 20:05 RTC INT1 */
DCD RTC2_IRQHandler /* 21:06 RTC INT2 */
DCD RTC3_IRQHandler /* 22:07 RTC INT3 */
DCD PMU_IRQHandler /* 23:08 PMU */
DCD USB_IRQHandler /* 24:09 USB */
DCD AES_IRQHandler /* 25:10 AES */
DCD MAA_IRQHandler /* 26:11 MAA */
DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */
DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */
DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
DCD TMR0_IRQHandler /* 38:23 Timer32-0 */
DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
DCD TMR1_IRQHandler /* 40:25 Timer32-1 */
DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
DCD TMR2_IRQHandler /* 42:27 Timer32-2 */
DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
DCD TMR3_IRQHandler /* 44:29 Timer32-3 */
DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
DCD TMR4_IRQHandler /* 46:31 Timer32-4 */
DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
DCD TMR5_IRQHandler /* 48:33 Timer32-5 */
DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
DCD UART0_IRQHandler /* 50:35 UART0 */
DCD UART1_IRQHandler /* 51:36 UART1 */
DCD UART2_IRQHandler /* 52:37 UART0 */
DCD UART3_IRQHandler /* 53:38 UART1 */
DCD PT_IRQHandler /* 54:39 PT */
DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */
DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */
DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */
DCD I2CS_IRQHandler /* 58:43 I2C Slave */
DCD SPI0_IRQHandler /* 59:44 SPI0 */
DCD SPI1_IRQHandler /* 60:45 SPI1 */
DCD SPI2_IRQHandler /* 61:46 SPI2 */
DCD SPIB_IRQHandler /* 62:47 SPI Bridge */
DCD OWM_IRQHandler /* 63:48 1-Wire Master */
DCD AFE_IRQHandler /* 64:49 AFE */
DCD SPIS_IRQHandler ; 65:50 SPI Slave
DCD GPIO_P7_IRQHandler ; 66:51 GPIO Port 7
DCD GPIO_P8_IRQHandler ; 67:52 GPIO Port 8
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT PreInit
IMPORT SystemInit
IMPORT __main
LDR R0, =PreInit
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
MemManage_Handler PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
DefaultIRQ_Handler PROC
EXPORT CLKMAN_IRQHandler [WEAK]
EXPORT PWRMAN_IRQHandler [WEAK]
EXPORT FLC_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT RTC3_IRQHandler [WEAK]
EXPORT PMU_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT MAA_IRQHandler [WEAK]
EXPORT WDT0_IRQHandler [WEAK]
EXPORT WDT0_P_IRQHandler [WEAK]
EXPORT WDT1_IRQHandler [WEAK]
EXPORT WDT1_P_IRQHandler [WEAK]
EXPORT GPIO_P0_IRQHandler [WEAK]
EXPORT GPIO_P1_IRQHandler [WEAK]
EXPORT GPIO_P2_IRQHandler [WEAK]
EXPORT GPIO_P3_IRQHandler [WEAK]
EXPORT GPIO_P4_IRQHandler [WEAK]
EXPORT GPIO_P5_IRQHandler [WEAK]
EXPORT GPIO_P6_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR16_0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR16_1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR16_2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR16_3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT TMR16_4_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT TMR16_5_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PT_IRQHandler [WEAK]
EXPORT I2CM0_IRQHandler [WEAK]
EXPORT I2CM1_IRQHandler [WEAK]
EXPORT I2CM2_IRQHandler [WEAK]
EXPORT I2CS_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPIB_IRQHandler [WEAK]
EXPORT OWM_IRQHandler [WEAK]
EXPORT AFE_IRQHandler [WEAK]
EXPORT SPIS_IRQHandler [WEAK]
EXPORT GPIO_P7_IRQHandler [WEAK]
EXPORT GPIO_P8_IRQHandler [WEAK]
CLKMAN_IRQHandler
PWRMAN_IRQHandler
FLC_IRQHandler
RTC0_IRQHandler
RTC1_IRQHandler
RTC2_IRQHandler
RTC3_IRQHandler
PMU_IRQHandler
USB_IRQHandler
AES_IRQHandler
MAA_IRQHandler
WDT0_IRQHandler
WDT0_P_IRQHandler
WDT1_IRQHandler
WDT1_P_IRQHandler
GPIO_P0_IRQHandler
GPIO_P1_IRQHandler
GPIO_P2_IRQHandler
GPIO_P3_IRQHandler
GPIO_P4_IRQHandler
GPIO_P5_IRQHandler
GPIO_P6_IRQHandler
TMR0_IRQHandler
TMR16_0_IRQHandler
TMR1_IRQHandler
TMR16_1_IRQHandler
TMR2_IRQHandler
TMR16_2_IRQHandler
TMR3_IRQHandler
TMR16_3_IRQHandler
TMR4_IRQHandler
TMR16_4_IRQHandler
TMR5_IRQHandler
TMR16_5_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PT_IRQHandler
I2CM0_IRQHandler
I2CM1_IRQHandler
I2CM2_IRQHandler
I2CS_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPIB_IRQHandler
OWM_IRQHandler
AFE_IRQHandler
SPIS_IRQHandler
GPIO_P7_IRQHandler
GPIO_P8_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 9,839 | software/v2.3a/DAPLink/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s | ;/*****************************************************************************
; * @file: startup_SAM3U.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Atmel SAM3U Device Series
; * @version: V1.10
; * @date: 17. April 2013
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT g_board_info
__Vectors DCD __initial_sp ; 0: Top of Stack
DCD Reset_Handler ; 1: Reset Handler
DCD NMI_Handler ; 2: NMI Handler
DCD HardFault_Handler ; 3: Hard Fault Handler
DCD MemManage_Handler ; 4: MPU Fault Handler
DCD BusFault_Handler ; 5: Bus Fault Handler
DCD UsageFault_Handler ; 6: Usage Fault Handler
DCD 0 ; 7: Reserved
DCD DAPLINK_BUILD_KEY ; 8: Build type - BL/IF
DCD DAPLINK_HIC_ID ; 9: Compatibility
DCD DAPLINK_VERSION ; 10:Version
DCD SVC_Handler ; 11: SVCall Handler
DCD DebugMon_Handler ; 12: Debug Monitor Handler
DCD g_board_info ; 13: Ptr to Board info, family info other target details
DCD PendSV_Handler ; 14: PendSV Handler
DCD SysTick_Handler ; 15: SysTick Handler
; External Interrupts
DCD SUPC_IRQHandler ; 0: Supply Controller
DCD RSTC_IRQHandler ; 1: Reset Controller
DCD RTC_IRQHandler ; 2: Real Time Clock
DCD RTT_IRQHandler ; 3: Real Time Timer
DCD WDT_IRQHandler ; 4: Watchdog Timer
DCD PMC_IRQHandler ; 5: Power Management Controller
DCD EEFC0_IRQHandler ; 6: Enhanced Embedded Flash Controller 0
DCD EEFC1_IRQHandler ; 7: Enhanced Embedded Flash Controller 1
DCD UART_IRQHandler ; 8: UART
DCD SMC_IRQHandler ; 9: Static Memory Controller
DCD PIOA_IRQHandler ; 10: Parallel I/O Controller A
DCD PIOB_IRQHandler ; 11: Parallel I/O Controller B
DCD PIOC_IRQHandler ; 12: Parallel I/O Controller C
DCD USART0_IRQHandler ; 13: USART 0
DCD USART1_IRQHandler ; 14: USART 1
DCD USART2_IRQHandler ; 15: USART 2
DCD USART3_IRQHandler ; 16: USART 3
DCD HSMCI_IRQHandler ; 17: High Speed Multimedia Card Interface
DCD TWI0_IRQHandler ; 18: Two-wire Interface 0
DCD TWI1_IRQHandler ; 19: Two-wire Interface 1
DCD SPI_IRQHandler ; 20: Synchronous Peripheral Interface
DCD SSC_IRQHandler ; 21: Synchronous Serial Controller
DCD TC0_IRQHandler ; 22: Timer Counter 0
DCD TC1_IRQHandler ; 23: Timer Counter 1
DCD TC2_IRQHandler ; 24: Timer Counter 2
DCD PWM_IRQHandler ; 25: Pulse Width Modulation Controller
DCD ADC12B_IRQHandler ; 26: 12-bit ADC Controller
DCD ADC_IRQHandler ; 27: 10-bit ADC Controller
DCD DMAC_IRQHandler ; 28: DMA Controller
DCD UDPHS_IRQHandler ; 29: USB Device High Speed
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SUPC_IRQHandler [WEAK]
EXPORT RSTC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTT_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT PMC_IRQHandler [WEAK]
EXPORT EEFC0_IRQHandler [WEAK]
EXPORT EEFC1_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT SMC_IRQHandler [WEAK]
EXPORT PIOA_IRQHandler [WEAK]
EXPORT PIOB_IRQHandler [WEAK]
EXPORT PIOC_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT HSMCI_IRQHandler [WEAK]
EXPORT TWI0_IRQHandler [WEAK]
EXPORT TWI1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT SSC_IRQHandler [WEAK]
EXPORT TC0_IRQHandler [WEAK]
EXPORT TC1_IRQHandler [WEAK]
EXPORT TC2_IRQHandler [WEAK]
EXPORT PWM_IRQHandler [WEAK]
EXPORT ADC12B_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DMAC_IRQHandler [WEAK]
EXPORT UDPHS_IRQHandler [WEAK]
SUPC_IRQHandler
RSTC_IRQHandler
RTC_IRQHandler
RTT_IRQHandler
WDT_IRQHandler
PMC_IRQHandler
EEFC0_IRQHandler
EEFC1_IRQHandler
UART_IRQHandler
SMC_IRQHandler
PIOA_IRQHandler
PIOB_IRQHandler
PIOC_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
HSMCI_IRQHandler
TWI0_IRQHandler
TWI1_IRQHandler
SPI_IRQHandler
SSC_IRQHandler
TC0_IRQHandler
TC1_IRQHandler
TC2_IRQHandler
PWM_IRQHandler
ADC12B_IRQHandler
ADC_IRQHandler
DMAC_IRQHandler
UDPHS_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 24,980 | software/v2.3a/DAPLink/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s | ;/**
; * @file startup_MK20D5.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; Ptr to Board info, family info other target details
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD DMA_Error_IRQHandler ; DMA error interrupt
DCD Reserved21_IRQHandler ; Reserved interrupt 21
DCD FTFL_IRQHandler ; FTFL interrupt
DCD Read_Collision_IRQHandler ; Read collision interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD SWI_IRQHandler ; Software interrupt
DCD DefaultISR ; 62
DCD DefaultISR ; 63
DCD DefaultISR ; 64
DCD DefaultISR ; 65
DCD DefaultISR ; 66
DCD DefaultISR ; 67
DCD DefaultISR ; 68
DCD DefaultISR ; 69
DCD DefaultISR ; 70
DCD DefaultISR ; 71
DCD DefaultISR ; 72
DCD DefaultISR ; 73
DCD DefaultISR ; 74
DCD DefaultISR ; 75
DCD DefaultISR ; 76
DCD DefaultISR ; 77
DCD DefaultISR ; 78
DCD DefaultISR ; 79
DCD DefaultISR ; 80
DCD DefaultISR ; 81
DCD DefaultISR ; 82
DCD DefaultISR ; 83
DCD DefaultISR ; 84
DCD DefaultISR ; 85
DCD DefaultISR ; 86
DCD DefaultISR ; 87
DCD DefaultISR ; 88
DCD DefaultISR ; 89
DCD DefaultISR ; 90
DCD DefaultISR ; 91
DCD DefaultISR ; 92
DCD DefaultISR ; 93
DCD DefaultISR ; 94
DCD DefaultISR ; 95
DCD DefaultISR ; 96
DCD DefaultISR ; 97
DCD DefaultISR ; 98
DCD DefaultISR ; 99
DCD DefaultISR ; 100
DCD DefaultISR ; 101
DCD DefaultISR ; 102
DCD DefaultISR ; 103
DCD DefaultISR ; 104
DCD DefaultISR ; 105
DCD DefaultISR ; 106
DCD DefaultISR ; 107
DCD DefaultISR ; 108
DCD DefaultISR ; 109
DCD DefaultISR ; 110
DCD DefaultISR ; 111
DCD DefaultISR ; 112
DCD DefaultISR ; 113
DCD DefaultISR ; 114
DCD DefaultISR ; 115
DCD DefaultISR ; 116
DCD DefaultISR ; 117
DCD DefaultISR ; 118
DCD DefaultISR ; 119
DCD DefaultISR ; 120
DCD DefaultISR ; 121
DCD DefaultISR ; 122
DCD DefaultISR ; 123
DCD DefaultISR ; 124
DCD DefaultISR ; 125
DCD DefaultISR ; 126
DCD DefaultISR ; 127
DCD DefaultISR ; 128
DCD DefaultISR ; 129
DCD DefaultISR ; 130
DCD DefaultISR ; 131
DCD DefaultISR ; 132
DCD DefaultISR ; 133
DCD DefaultISR ; 134
DCD DefaultISR ; 135
DCD DefaultISR ; 136
DCD DefaultISR ; 137
DCD DefaultISR ; 138
DCD DefaultISR ; 139
DCD DefaultISR ; 140
DCD DefaultISR ; 141
DCD DefaultISR ; 142
DCD DefaultISR ; 143
DCD DefaultISR ; 144
DCD DefaultISR ; 145
DCD DefaultISR ; 146
DCD DefaultISR ; 147
DCD DefaultISR ; 148
DCD DefaultISR ; 149
DCD DefaultISR ; 150
DCD DefaultISR ; 151
DCD DefaultISR ; 152
DCD DefaultISR ; 153
DCD DefaultISR ; 154
DCD DefaultISR ; 155
DCD DefaultISR ; 156
DCD DefaultISR ; 157
DCD DefaultISR ; 158
DCD DefaultISR ; 159
DCD DefaultISR ; 160
DCD DefaultISR ; 161
DCD DefaultISR ; 162
DCD DefaultISR ; 163
DCD DefaultISR ; 164
DCD DefaultISR ; 165
DCD DefaultISR ; 166
DCD DefaultISR ; 167
DCD DefaultISR ; 168
DCD DefaultISR ; 169
DCD DefaultISR ; 170
DCD DefaultISR ; 171
DCD DefaultISR ; 172
DCD DefaultISR ; 173
DCD DefaultISR ; 174
DCD DefaultISR ; 175
DCD DefaultISR ; 176
DCD DefaultISR ; 177
DCD DefaultISR ; 178
DCD DefaultISR ; 179
DCD DefaultISR ; 180
DCD DefaultISR ; 181
DCD DefaultISR ; 182
DCD DefaultISR ; 183
DCD DefaultISR ; 184
DCD DefaultISR ; 185
DCD DefaultISR ; 186
DCD DefaultISR ; 187
DCD DefaultISR ; 188
DCD DefaultISR ; 189
DCD DefaultISR ; 190
DCD DefaultISR ; 191
DCD DefaultISR ; 192
DCD DefaultISR ; 193
DCD DefaultISR ; 194
DCD DefaultISR ; 195
DCD DefaultISR ; 196
DCD DefaultISR ; 197
DCD DefaultISR ; 198
DCD DefaultISR ; 199
DCD DefaultISR ; 200
DCD DefaultISR ; 201
DCD DefaultISR ; 202
DCD DefaultISR ; 203
DCD DefaultISR ; 204
DCD DefaultISR ; 205
DCD DefaultISR ; 206
DCD DefaultISR ; 207
DCD DefaultISR ; 208
DCD DefaultISR ; 209
DCD DefaultISR ; 210
DCD DefaultISR ; 211
DCD DefaultISR ; 212
DCD DefaultISR ; 213
DCD DefaultISR ; 214
DCD DefaultISR ; 215
DCD DefaultISR ; 216
DCD DefaultISR ; 217
DCD DefaultISR ; 218
DCD DefaultISR ; 219
DCD DefaultISR ; 220
DCD DefaultISR ; 221
DCD DefaultISR ; 222
DCD DefaultISR ; 223
DCD DefaultISR ; 224
DCD DefaultISR ; 225
DCD DefaultISR ; 226
DCD DefaultISR ; 227
DCD DefaultISR ; 228
DCD DefaultISR ; 229
DCD DefaultISR ; 230
DCD DefaultISR ; 231
DCD DefaultISR ; 232
DCD DefaultISR ; 233
DCD DefaultISR ; 234
DCD DefaultISR ; 235
DCD DefaultISR ; 236
DCD DefaultISR ; 237
DCD DefaultISR ; 238
DCD DefaultISR ; 239
DCD DefaultISR ; 240
DCD DefaultISR ; 241
DCD DefaultISR ; 242
DCD DefaultISR ; 243
DCD DefaultISR ; 244
DCD DefaultISR ; 245
DCD DefaultISR ; 246
DCD DefaultISR ; 247
DCD DefaultISR ; 248
DCD DefaultISR ; 249
DCD DefaultISR ; 250
DCD DefaultISR ; 251
DCD DefaultISR ; 252
DCD DefaultISR ; 253
DCD DefaultISR ; 254
DCD DefaultISR ; 255
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFD
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x8400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT Reserved21_IRQHandler [WEAK]
EXPORT FTFL_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA_Error_IRQHandler
Reserved21_IRQHandler
FTFL_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
Watchdog_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
I2S0_Tx_IRQHandler
I2S0_Rx_IRQHandler
UART0_LON_IRQHandler
UART0_RX_TX_IRQHandler
UART0_ERR_IRQHandler
UART1_RX_TX_IRQHandler
UART1_ERR_IRQHandler
UART2_RX_TX_IRQHandler
UART2_ERR_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
DefaultISR
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 14,147 | software/v2.3a/DAPLink/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s | ;/**
; * @file startup_MKL26Z.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD g_board_info ; Ptr to Board info, family info other target details
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD Reserved20_IRQHandler ; Reserved interrupt 20
DCD FTFA_IRQHandler ; FTFA interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C0 interrupt 25
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD UART0_IRQHandler ; UART0 status/error interrupt
DCD UART1_IRQHandler ; UART1 status/error interrupt
DCD UART2_IRQHandler ; UART2 status/error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT_IRQHandler ; PIT timer interrupt
DCD Reserved39_IRQHandler ; Reserved interrupt 39
DCD USB0_IRQHandler ; USB0 interrupt
DCD DAC0_IRQHandler ; DAC interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved45_IRQHandler ; Reserved interrupt 45
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTD_IRQHandler ; Port D interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
; <1=> RESET pin is dedicated
; <o.3> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x8400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved39_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
DefaultISR
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 47,830 | software/v2.3a/DAPLink/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s | ; * ---------------------------------------------------------------------------------------
; * @file: startup_MK26F18.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * MK26F18
; * @version: 2.0
; * @date: 2015-3-25
; * @build: b151210
; * ---------------------------------------------------------------------------------------
; *
; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; *
; * o Redistributions of source code must retain the above copyright notice, this list
; * of conditions and the following disclaimer.
; *
; * o Redistributions in binary form must reproduce the above copyright notice, this
; * list of conditions and the following disclaimer in the documentation and/or
; * other materials provided with the distribution.
; *
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
; * contributors may be used to endorse or promote products derived from this
; * software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
DCD 0 ;Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA Channel 0, 16 Transfer Complete
DCD DMA1_DMA17_IRQHandler ;DMA Channel 1, 17 Transfer Complete
DCD DMA2_DMA18_IRQHandler ;DMA Channel 2, 18 Transfer Complete
DCD DMA3_DMA19_IRQHandler ;DMA Channel 3, 19 Transfer Complete
DCD DMA4_DMA20_IRQHandler ;DMA Channel 4, 20 Transfer Complete
DCD DMA5_DMA21_IRQHandler ;DMA Channel 5, 21 Transfer Complete
DCD DMA6_DMA22_IRQHandler ;DMA Channel 6, 22 Transfer Complete
DCD DMA7_DMA23_IRQHandler ;DMA Channel 7, 23 Transfer Complete
DCD DMA8_DMA24_IRQHandler ;DMA Channel 8, 24 Transfer Complete
DCD DMA9_DMA25_IRQHandler ;DMA Channel 9, 25 Transfer Complete
DCD DMA10_DMA26_IRQHandler ;DMA Channel 10, 26 Transfer Complete
DCD DMA11_DMA27_IRQHandler ;DMA Channel 11, 27 Transfer Complete
DCD DMA12_DMA28_IRQHandler ;DMA Channel 12, 28 Transfer Complete
DCD DMA13_DMA29_IRQHandler ;DMA Channel 13, 29 Transfer Complete
DCD DMA14_DMA30_IRQHandler ;DMA Channel 14, 30 Transfer Complete
DCD DMA15_DMA31_IRQHandler ;DMA Channel 15, 31 Transfer Complete
DCD DMA_Error_IRQHandler ;DMA Error Interrupt
DCD MCM_IRQHandler ;Normal Interrupt
DCD FTFE_IRQHandler ;FTFE Command complete interrupt
DCD Read_Collision_IRQHandler ;Read Collision Interrupt
DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning
DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit
DCD WDOG_EWM_IRQHandler ;WDOG Interrupt
DCD RNG_IRQHandler ;RNG Interrupt
DCD I2C0_IRQHandler ;I2C0 interrupt
DCD I2C1_IRQHandler ;I2C1 interrupt
DCD SPI0_IRQHandler ;SPI0 Interrupt
DCD SPI1_IRQHandler ;SPI1 Interrupt
DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt
DCD Reserved46_IRQHandler ;Reserved interrupt 46
DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt
DCD UART0_ERR_IRQHandler ;UART0 Error interrupt
DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt
DCD UART1_ERR_IRQHandler ;UART1 Error interrupt
DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt
DCD UART2_ERR_IRQHandler ;UART2 Error interrupt
DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt
DCD UART3_ERR_IRQHandler ;UART3 Error interrupt
DCD ADC0_IRQHandler ;ADC0 interrupt
DCD CMP0_IRQHandler ;CMP0 interrupt
DCD CMP1_IRQHandler ;CMP1 interrupt
DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ;CMT interrupt
DCD RTC_IRQHandler ;RTC interrupt
DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ;PDB0 Interrupt
DCD USB0_IRQHandler ;USB0 interrupt
DCD USBDCD_IRQHandler ;USBDCD Interrupt
DCD Reserved71_IRQHandler ;Reserved interrupt 71
DCD DAC0_IRQHandler ;DAC0 interrupt
DCD MCG_IRQHandler ;MCG Interrupt
DCD LPTMR0_IRQHandler ;LPTimer interrupt
DCD PORTA_IRQHandler ;Port A interrupt
DCD PORTB_IRQHandler ;Port B interrupt
DCD PORTC_IRQHandler ;Port C interrupt
DCD PORTD_IRQHandler ;Port D interrupt
DCD PORTE_IRQHandler ;Port E interrupt
DCD SWI_IRQHandler ;Software interrupt
DCD SPI2_IRQHandler ;SPI2 Interrupt
DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt
DCD UART4_ERR_IRQHandler ;UART4 Error interrupt
DCD Reserved84_IRQHandler ;Reserved interrupt 84
DCD Reserved85_IRQHandler ;Reserved interrupt 85
DCD CMP2_IRQHandler ;CMP2 interrupt
DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt
DCD DAC1_IRQHandler ;DAC1 interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
DCD I2C2_IRQHandler ;I2C2 interrupt
DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt
DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt
DCD CAN0_Error_IRQHandler ;CAN0 error interrupt
DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt
DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt
DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt
DCD SDHC_IRQHandler ;SDHC interrupt
DCD Reserved98_IRQHandler ;Reserved Interrupt 98
DCD Reserved99_IRQHandler ;Reserved Interrupt 99
DCD Reserved100_IRQHandler ;Reserved Interrupt 100
DCD Reserved101_IRQHandler ;Reserved Interrupt 101
DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt
DCD TSI0_IRQHandler ;TSI0 interrupt
DCD TPM1_IRQHandler ;TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ;TPM2 fault, overflow and channels interrupt
DCD USBHSDCD_IRQHandler ;USBHSDCD, USBHS Phy Interrupt
DCD I2C3_IRQHandler ;I2C3 interrupt
DCD CMP3_IRQHandler ;CMP3 interrupt
DCD USBHS_IRQHandler ;USB high speed OTG interrupt
DCD CAN1_ORed_Message_buffer_IRQHandler ;CAN1 OR'd message buffers interrupt
DCD CAN1_Bus_Off_IRQHandler ;CAN1 bus off interrupt
DCD CAN1_Error_IRQHandler ;CAN1 error interrupt
DCD CAN1_Tx_Warning_IRQHandler ;CAN1 Tx warning interrupt
DCD CAN1_Rx_Warning_IRQHandler ;CAN1 Rx warning interrupt
DCD CAN1_Wake_Up_IRQHandler ;CAN1 wake up interrupt
DCD DefaultISR ;116
DCD DefaultISR ;117
DCD DefaultISR ;118
DCD DefaultISR ;119
DCD DefaultISR ;120
DCD DefaultISR ;121
DCD DefaultISR ;122
DCD DefaultISR ;123
DCD DefaultISR ;124
DCD DefaultISR ;125
DCD DefaultISR ;126
DCD DefaultISR ;127
DCD DefaultISR ;128
DCD DefaultISR ;129
DCD DefaultISR ;130
DCD DefaultISR ;131
DCD DefaultISR ;132
DCD DefaultISR ;133
DCD DefaultISR ;134
DCD DefaultISR ;135
DCD DefaultISR ;136
DCD DefaultISR ;137
DCD DefaultISR ;138
DCD DefaultISR ;139
DCD DefaultISR ;140
DCD DefaultISR ;141
DCD DefaultISR ;142
DCD DefaultISR ;143
DCD DefaultISR ;144
DCD DefaultISR ;145
DCD DefaultISR ;146
DCD DefaultISR ;147
DCD DefaultISR ;148
DCD DefaultISR ;149
DCD DefaultISR ;150
DCD DefaultISR ;151
DCD DefaultISR ;152
DCD DefaultISR ;153
DCD DefaultISR ;154
DCD DefaultISR ;155
DCD DefaultISR ;156
DCD DefaultISR ;157
DCD DefaultISR ;158
DCD DefaultISR ;159
DCD DefaultISR ;160
DCD DefaultISR ;161
DCD DefaultISR ;162
DCD DefaultISR ;163
DCD DefaultISR ;164
DCD DefaultISR ;165
DCD DefaultISR ;166
DCD DefaultISR ;167
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
DCD DefaultISR ;240
DCD DefaultISR ;241
DCD DefaultISR ;242
DCD DefaultISR ;243
DCD DefaultISR ;244
DCD DefaultISR ;245
DCD DefaultISR ;246
DCD DefaultISR ;247
DCD DefaultISR ;248
DCD DefaultISR ;249
DCD DefaultISR ;250
DCD DefaultISR ;251
DCD DefaultISR ;252
DCD DefaultISR ;253
DCD DefaultISR ;254
DCD 0xFFFFFFFF ; Reserved for user TRIM value
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict access to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program Flash Region Protect Register 0
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> Normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is disabled
; <1=> EzPort operation is enabled
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI_b pin/interrupts reset default to enabled
FOPT EQU 0xF9
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor Key Security Enable
FSEC EQU 0xFE
; </h>
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x20400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
DCB FSEC , FOPT , FEPROT , FDPROT
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__Vectors
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
CPSIE i ; Unmask interrupts
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
DMA0_DMA16_IRQHandler\
PROC
EXPORT DMA0_DMA16_IRQHandler [WEAK]
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
ENDP
DMA1_DMA17_IRQHandler\
PROC
EXPORT DMA1_DMA17_IRQHandler [WEAK]
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
ENDP
DMA2_DMA18_IRQHandler\
PROC
EXPORT DMA2_DMA18_IRQHandler [WEAK]
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
ENDP
DMA3_DMA19_IRQHandler\
PROC
EXPORT DMA3_DMA19_IRQHandler [WEAK]
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
ENDP
DMA4_DMA20_IRQHandler\
PROC
EXPORT DMA4_DMA20_IRQHandler [WEAK]
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
ENDP
DMA5_DMA21_IRQHandler\
PROC
EXPORT DMA5_DMA21_IRQHandler [WEAK]
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
ENDP
DMA6_DMA22_IRQHandler\
PROC
EXPORT DMA6_DMA22_IRQHandler [WEAK]
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
ENDP
DMA7_DMA23_IRQHandler\
PROC
EXPORT DMA7_DMA23_IRQHandler [WEAK]
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
ENDP
DMA8_DMA24_IRQHandler\
PROC
EXPORT DMA8_DMA24_IRQHandler [WEAK]
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
ENDP
DMA9_DMA25_IRQHandler\
PROC
EXPORT DMA9_DMA25_IRQHandler [WEAK]
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
ENDP
DMA10_DMA26_IRQHandler\
PROC
EXPORT DMA10_DMA26_IRQHandler [WEAK]
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
ENDP
DMA11_DMA27_IRQHandler\
PROC
EXPORT DMA11_DMA27_IRQHandler [WEAK]
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
ENDP
DMA12_DMA28_IRQHandler\
PROC
EXPORT DMA12_DMA28_IRQHandler [WEAK]
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
ENDP
DMA13_DMA29_IRQHandler\
PROC
EXPORT DMA13_DMA29_IRQHandler [WEAK]
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
ENDP
DMA14_DMA30_IRQHandler\
PROC
EXPORT DMA14_DMA30_IRQHandler [WEAK]
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
ENDP
DMA15_DMA31_IRQHandler\
PROC
EXPORT DMA15_DMA31_IRQHandler [WEAK]
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
ENDP
DMA_Error_IRQHandler\
PROC
EXPORT DMA_Error_IRQHandler [WEAK]
LDR R0, =DMA_Error_DriverIRQHandler
BX R0
ENDP
I2C0_IRQHandler\
PROC
EXPORT I2C0_IRQHandler [WEAK]
LDR R0, =I2C0_DriverIRQHandler
BX R0
ENDP
I2C1_IRQHandler\
PROC
EXPORT I2C1_IRQHandler [WEAK]
LDR R0, =I2C1_DriverIRQHandler
BX R0
ENDP
SPI0_IRQHandler\
PROC
EXPORT SPI0_IRQHandler [WEAK]
LDR R0, =SPI0_DriverIRQHandler
BX R0
ENDP
SPI1_IRQHandler\
PROC
EXPORT SPI1_IRQHandler [WEAK]
LDR R0, =SPI1_DriverIRQHandler
BX R0
ENDP
I2S0_Tx_IRQHandler\
PROC
EXPORT I2S0_Tx_IRQHandler [WEAK]
LDR R0, =I2S0_Tx_DriverIRQHandler
BX R0
ENDP
I2S0_Rx_IRQHandler\
PROC
EXPORT I2S0_Rx_IRQHandler [WEAK]
LDR R0, =I2S0_Rx_DriverIRQHandler
BX R0
ENDP
UART0_RX_TX_IRQHandler\
PROC
EXPORT UART0_RX_TX_IRQHandler [WEAK]
LDR R0, =UART0_RX_TX_DriverIRQHandler
BX R0
ENDP
UART0_ERR_IRQHandler\
PROC
EXPORT UART0_ERR_IRQHandler [WEAK]
LDR R0, =UART0_ERR_DriverIRQHandler
BX R0
ENDP
UART1_RX_TX_IRQHandler\
PROC
EXPORT UART1_RX_TX_IRQHandler [WEAK]
LDR R0, =UART1_RX_TX_DriverIRQHandler
BX R0
ENDP
UART1_ERR_IRQHandler\
PROC
EXPORT UART1_ERR_IRQHandler [WEAK]
LDR R0, =UART1_ERR_DriverIRQHandler
BX R0
ENDP
UART2_RX_TX_IRQHandler\
PROC
EXPORT UART2_RX_TX_IRQHandler [WEAK]
LDR R0, =UART2_RX_TX_DriverIRQHandler
BX R0
ENDP
UART2_ERR_IRQHandler\
PROC
EXPORT UART2_ERR_IRQHandler [WEAK]
LDR R0, =UART2_ERR_DriverIRQHandler
BX R0
ENDP
UART3_RX_TX_IRQHandler\
PROC
EXPORT UART3_RX_TX_IRQHandler [WEAK]
LDR R0, =UART3_RX_TX_DriverIRQHandler
BX R0
ENDP
UART3_ERR_IRQHandler\
PROC
EXPORT UART3_ERR_IRQHandler [WEAK]
LDR R0, =UART3_ERR_DriverIRQHandler
BX R0
ENDP
SPI2_IRQHandler\
PROC
EXPORT SPI2_IRQHandler [WEAK]
LDR R0, =SPI2_DriverIRQHandler
BX R0
ENDP
UART4_RX_TX_IRQHandler\
PROC
EXPORT UART4_RX_TX_IRQHandler [WEAK]
LDR R0, =UART4_RX_TX_DriverIRQHandler
BX R0
ENDP
UART4_ERR_IRQHandler\
PROC
EXPORT UART4_ERR_IRQHandler [WEAK]
LDR R0, =UART4_ERR_DriverIRQHandler
BX R0
ENDP
I2C2_IRQHandler\
PROC
EXPORT I2C2_IRQHandler [WEAK]
LDR R0, =I2C2_DriverIRQHandler
BX R0
ENDP
CAN0_ORed_Message_buffer_IRQHandler\
PROC
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Bus_Off_IRQHandler\
PROC
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Error_IRQHandler\
PROC
EXPORT CAN0_Error_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Tx_Warning_IRQHandler\
PROC
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Rx_Warning_IRQHandler\
PROC
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Wake_Up_IRQHandler\
PROC
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
SDHC_IRQHandler\
PROC
EXPORT SDHC_IRQHandler [WEAK]
LDR R0, =SDHC_DriverIRQHandler
BX R0
ENDP
LPUART0_IRQHandler\
PROC
EXPORT LPUART0_IRQHandler [WEAK]
LDR R0, =LPUART0_DriverIRQHandler
BX R0
ENDP
I2C3_IRQHandler\
PROC
EXPORT I2C3_IRQHandler [WEAK]
LDR R0, =I2C3_DriverIRQHandler
BX R0
ENDP
CAN1_ORed_Message_buffer_IRQHandler\
PROC
EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Bus_Off_IRQHandler\
PROC
EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Error_IRQHandler\
PROC
EXPORT CAN1_Error_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Tx_Warning_IRQHandler\
PROC
EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Rx_Warning_IRQHandler\
PROC
EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Wake_Up_IRQHandler\
PROC
EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
Default_Handler\
PROC
EXPORT DMA0_DMA16_DriverIRQHandler [WEAK]
EXPORT DMA1_DMA17_DriverIRQHandler [WEAK]
EXPORT DMA2_DMA18_DriverIRQHandler [WEAK]
EXPORT DMA3_DMA19_DriverIRQHandler [WEAK]
EXPORT DMA4_DMA20_DriverIRQHandler [WEAK]
EXPORT DMA5_DMA21_DriverIRQHandler [WEAK]
EXPORT DMA6_DMA22_DriverIRQHandler [WEAK]
EXPORT DMA7_DMA23_DriverIRQHandler [WEAK]
EXPORT DMA8_DMA24_DriverIRQHandler [WEAK]
EXPORT DMA9_DMA25_DriverIRQHandler [WEAK]
EXPORT DMA10_DMA26_DriverIRQHandler [WEAK]
EXPORT DMA11_DMA27_DriverIRQHandler [WEAK]
EXPORT DMA12_DMA28_DriverIRQHandler [WEAK]
EXPORT DMA13_DMA29_DriverIRQHandler [WEAK]
EXPORT DMA14_DMA30_DriverIRQHandler [WEAK]
EXPORT DMA15_DMA31_DriverIRQHandler [WEAK]
EXPORT DMA_Error_DriverIRQHandler [WEAK]
EXPORT MCM_IRQHandler [WEAK]
EXPORT FTFE_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLWU_IRQHandler [WEAK]
EXPORT WDOG_EWM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT I2C0_DriverIRQHandler [WEAK]
EXPORT I2C1_DriverIRQHandler [WEAK]
EXPORT SPI0_DriverIRQHandler [WEAK]
EXPORT SPI1_DriverIRQHandler [WEAK]
EXPORT I2S0_Tx_DriverIRQHandler [WEAK]
EXPORT I2S0_Rx_DriverIRQHandler [WEAK]
EXPORT Reserved46_IRQHandler [WEAK]
EXPORT UART0_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART0_ERR_DriverIRQHandler [WEAK]
EXPORT UART1_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART1_ERR_DriverIRQHandler [WEAK]
EXPORT UART2_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART2_ERR_DriverIRQHandler [WEAK]
EXPORT UART3_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART3_ERR_DriverIRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT FTM2_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT Reserved71_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTMR0_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT SPI2_DriverIRQHandler [WEAK]
EXPORT UART4_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART4_ERR_DriverIRQHandler [WEAK]
EXPORT Reserved84_IRQHandler [WEAK]
EXPORT Reserved85_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT FTM3_IRQHandler [WEAK]
EXPORT DAC1_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT I2C2_DriverIRQHandler [WEAK]
EXPORT CAN0_DriverIRQHandler [WEAK]
EXPORT SDHC_DriverIRQHandler [WEAK]
EXPORT Reserved98_IRQHandler [WEAK]
EXPORT Reserved99_IRQHandler [WEAK]
EXPORT Reserved100_IRQHandler [WEAK]
EXPORT Reserved101_IRQHandler [WEAK]
EXPORT LPUART0_DriverIRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT USBHSDCD_IRQHandler [WEAK]
EXPORT I2C3_DriverIRQHandler [WEAK]
EXPORT CMP3_IRQHandler [WEAK]
EXPORT USBHS_IRQHandler [WEAK]
EXPORT CAN1_DriverIRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_Error_DriverIRQHandler
MCM_IRQHandler
FTFE_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLWU_IRQHandler
WDOG_EWM_IRQHandler
RNG_IRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
SPI0_DriverIRQHandler
SPI1_DriverIRQHandler
I2S0_Tx_DriverIRQHandler
I2S0_Rx_DriverIRQHandler
Reserved46_IRQHandler
UART0_RX_TX_DriverIRQHandler
UART0_ERR_DriverIRQHandler
UART1_RX_TX_DriverIRQHandler
UART1_ERR_DriverIRQHandler
UART2_RX_TX_DriverIRQHandler
UART2_ERR_DriverIRQHandler
UART3_RX_TX_DriverIRQHandler
UART3_ERR_DriverIRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved71_IRQHandler
DAC0_IRQHandler
MCG_IRQHandler
LPTMR0_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
SPI2_DriverIRQHandler
UART4_RX_TX_DriverIRQHandler
UART4_ERR_DriverIRQHandler
Reserved84_IRQHandler
Reserved85_IRQHandler
CMP2_IRQHandler
FTM3_IRQHandler
DAC1_IRQHandler
ADC1_IRQHandler
I2C2_DriverIRQHandler
CAN0_DriverIRQHandler
SDHC_DriverIRQHandler
Reserved98_IRQHandler
Reserved99_IRQHandler
Reserved100_IRQHandler
Reserved101_IRQHandler
LPUART0_DriverIRQHandler
TSI0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
USBHSDCD_IRQHandler
I2C3_DriverIRQHandler
CMP3_IRQHandler
USBHS_IRQHandler
CAN1_DriverIRQHandler
DefaultISR
B DefaultISR
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 10,542 | software/v2.3a/DAPLink/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s | ;/***********************************************************************
; * $Id: startup_LPC18xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
; *
; * Project: LPC18xx CMSIS Package
; *
; * Description: Cortex-M3 Core Device Startup File for the NXP LPC18xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT g_board_info
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD g_board_info ; 13 Ptr to Board info, family info other target details
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 M0 Core
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD EZH_IRQHandler ; 19 EZH/EDM
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD M0s_IRQHandler ; 66 M0s
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
IF :LNOT::DEF:NO_CRP
#if defined(DAPLINK_BL)
AREA |.ARM.__at_0x1A0002FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
#endif
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0CORE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT EZH_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
; EXPORT RESERVED3 [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
; EXPORT RESERVED4 [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT M0s_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
EZH_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
;RESERVED3
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
;RESERVED4
WDT_IRQHandler
M0s_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 13,732 | software/v2.3a/DAPLink/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s | ;/**
; * @file startup_LPC11Uxx.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD g_board_info ; Ptr to Board info, family info other target details
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
IF :DEF:MBED_BOOTLOADER
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
ENDIF
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Power on RAM1 and USBRAM area
LDR R0, =0x40048080 ; System clock control
LDR R1, =0x0C00485F ; boot default + RAM1, USBRAM
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 13,570 | software/v2.3a/DAPLink/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S | ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Version : V4.1.0
;* Date : 29-April-2016
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* COPYRIGHT(c) 2016 STMicroelectronics
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; Ptr to Board info, family info other target details
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 20,265 | software/v2.3a/DAPLink/source/hic_hal/nuvoton/m48ssidae/Device/Nuvoton/M480/Source/ARM/startup_M480.s | ;/******************************************************************************
; * @file startup_M480.s
; * @version V1.00
; * @brief CMSIS Cortex-M4 Core Device Startup File for M480
; *
; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; * 1. Redistributions of source code must retain the above copyright notice,
; * this list of conditions and the following disclaimer.
; * 2. Redistributions in binary form must reproduce the above copyright notice,
; * this list of conditions and the following disclaimer in the documentation
; * and/or other materials provided with the distribution.
; * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
; * may be used to endorse or promote products derived from this software
; * without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Stack_Size
Stack_Size EQU 0x00006000
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Heap_Size
Heap_Size EQU 0x00000100
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; Build type - BL/IF
DCD DAPLINK_HIC_ID ; Compatibility
DCD DAPLINK_VERSION ; Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power down wake up
DCD RAMPE_IRQHandler ; 3: RAM parity error
DCD CKFAIL_IRQHandler ; 4: Clock detection fail
DCD Default_Handler ; 5: Reserved
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD WDT_IRQHandler ; 8: Watchdog timer
DCD WWDT_IRQHandler ; 9: Window watchdog timer
DCD EINT0_IRQHandler ; 10: External Input 0
DCD EINT1_IRQHandler ; 11: External Input 1
DCD EINT2_IRQHandler ; 12: External Input 2
DCD EINT3_IRQHandler ; 13: External Input 3
DCD EINT4_IRQHandler ; 14: External Input 4
DCD EINT5_IRQHandler ; 15: External Input 5
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD QSPI0_IRQHandler ; 22: QSPI0
DCD SPI0_IRQHandler ; 23: SPI0
DCD BRAKE0_IRQHandler ; 24:
DCD EPWM0P0_IRQHandler ; 25:
DCD EPWM0P1_IRQHandler ; 26:
DCD EPWM0P2_IRQHandler ; 27:
DCD BRAKE1_IRQHandler ; 28:
DCD EPWM1P0_IRQHandler ; 29:
DCD EPWM1P1_IRQHandler ; 30:
DCD EPWM1P2_IRQHandler ; 31:
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD UART0_IRQHandler ; 36: UART0
DCD UART1_IRQHandler ; 37: UART1
DCD I2C0_IRQHandler ; 38: I2C0
DCD I2C1_IRQHandler ; 39: I2C1
DCD PDMA_IRQHandler ; 40: Peripheral DMA
DCD DAC_IRQHandler ; 41: DAC
DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
DCD Default_Handler ; 45: Reserved
DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
DCD UART2_IRQHandler ; 48: UART2
DCD UART3_IRQHandler ; 49: UART3
DCD Default_Handler ; 50: Reserved
DCD SPI1_IRQHandler ; 51: SPI1
DCD SPI2_IRQHandler ; 52: SPI2
DCD USBD_IRQHandler ; 53: USB device
DCD OHCI_IRQHandler ; 54: OHCI
DCD USBOTG_IRQHandler ; 55: USB OTG
DCD CAN0_IRQHandler ; 56: CAN0
DCD CAN1_IRQHandler ; 57: CAN1
DCD SC0_IRQHandler ; 58:
DCD SC1_IRQHandler ; 59:
DCD SC2_IRQHandler ; 60:
DCD Default_Handler ; 61:
DCD SPI3_IRQHandler ; 62: SPI3
DCD Default_Handler ; 63:
DCD SDH0_IRQHandler ; 64: SDH0
DCD USBD20_IRQHandler ; 65: USBD20
DCD EMAC_TX_IRQHandler ; 66: EMAC_TX
DCD EMAC_RX_IRQHandler ; 67: EMAX_RX
DCD I2S0_IRQHandler ; 68: I2S0
DCD Default_Handler ; 69: ToDo: Add description to this Interrupt
DCD OPA0_IRQHandler ; 70: OPA0
DCD CRYPTO_IRQHandler ; 71: CRYPTO
DCD GPG_IRQHandler ; 72:
DCD EINT6_IRQHandler ; 73:
DCD UART4_IRQHandler ; 74: UART4
DCD UART5_IRQHandler ; 75: UART5
DCD USCI0_IRQHandler ; 76: USCI0
DCD USCI1_IRQHandler ; 77: USCI1
DCD BPWM0_IRQHandler ; 78: BPWM0
DCD BPWM1_IRQHandler ; 79: BPWM1
DCD SPIM_IRQHandler ; 80: SPIM
DCD Default_Handler ; 81: ToDo: Add description to this Interrupt
DCD I2C2_IRQHandler ; 82: I2C2
DCD Default_Handler ; 83:
DCD QEI0_IRQHandler ; 84: QEI0
DCD QEI1_IRQHandler ; 85: QEI1
DCD ECAP0_IRQHandler ; 86: ECAP0
DCD ECAP1_IRQHandler ; 87: ECAP1
DCD GPH_IRQHandler ; 88:
DCD EINT7_IRQHandler ; 89:
DCD SDH1_IRQHandler ; 90: SDH1
DCD Default_Handler ; 91:
DCD EHCI_IRQHandler ; 92: EHCI
DCD USBOTG20_IRQHandler ; 93:
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Unlock Register
LDR R0, =0x40000100
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
IF :LNOT: :DEF: ENABLE_SPIM_CACHE
LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
ORR R1, R1, #0x4000
STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
ENDIF
LDR R0, =SystemInit
BLX R0
; Init POR
; LDR R2, =0x40000024
; LDR R1, =0x00005AA5
; STR R1, [R2]
; Lock
LDR R0, =0x40000100
LDR R1, =0
STR R1, [R0]
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT IRC_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT RAMPE_IRQHandler [WEAK]
EXPORT CKFAIL_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT EINT5_IRQHandler [WEAK]
EXPORT GPA_IRQHandler [WEAK]
EXPORT GPB_IRQHandler [WEAK]
EXPORT GPC_IRQHandler [WEAK]
EXPORT GPD_IRQHandler [WEAK]
EXPORT GPE_IRQHandler [WEAK]
EXPORT GPF_IRQHandler [WEAK]
EXPORT QSPI0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT BRAKE0_IRQHandler [WEAK]
EXPORT EPWM0P0_IRQHandler [WEAK]
EXPORT EPWM0P1_IRQHandler [WEAK]
EXPORT EPWM0P2_IRQHandler [WEAK]
EXPORT BRAKE1_IRQHandler [WEAK]
EXPORT EPWM1P0_IRQHandler [WEAK]
EXPORT EPWM1P1_IRQHandler [WEAK]
EXPORT EPWM1P2_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT PDMA_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT ADC00_IRQHandler [WEAK]
EXPORT ADC01_IRQHandler [WEAK]
EXPORT ACMP01_IRQHandler [WEAK]
EXPORT ADC02_IRQHandler [WEAK]
EXPORT ADC03_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT OHCI_IRQHandler [WEAK]
EXPORT USBOTG_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT SC0_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT SC2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT SDH0_IRQHandler [WEAK]
EXPORT USBD20_IRQHandler [WEAK]
EXPORT EMAC_TX_IRQHandler [WEAK]
EXPORT EMAC_RX_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT OPA0_IRQHandler [WEAK]
EXPORT CRYPTO_IRQHandler [WEAK]
EXPORT GPG_IRQHandler [WEAK]
EXPORT EINT6_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT USCI0_IRQHandler [WEAK]
EXPORT USCI1_IRQHandler [WEAK]
EXPORT BPWM0_IRQHandler [WEAK]
EXPORT BPWM1_IRQHandler [WEAK]
EXPORT SPIM_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT QEI0_IRQHandler [WEAK]
EXPORT QEI1_IRQHandler [WEAK]
EXPORT ECAP0_IRQHandler [WEAK]
EXPORT ECAP1_IRQHandler [WEAK]
EXPORT GPH_IRQHandler [WEAK]
EXPORT EINT7_IRQHandler [WEAK]
EXPORT SDH1_IRQHandler [WEAK]
EXPORT EHCI_IRQHandler [WEAK]
EXPORT USBOTG20_IRQHandler [WEAK]
Default__IRQHandler
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
RAMPE_IRQHandler
CKFAIL_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
QSPI0_IRQHandler
SPI0_IRQHandler
BRAKE0_IRQHandler
EPWM0P0_IRQHandler
EPWM0P1_IRQHandler
EPWM0P2_IRQHandler
BRAKE1_IRQHandler
EPWM1P0_IRQHandler
EPWM1P1_IRQHandler
EPWM1P2_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
PDMA_IRQHandler
DAC_IRQHandler
ADC00_IRQHandler
ADC01_IRQHandler
ACMP01_IRQHandler
ADC02_IRQHandler
ADC03_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USBD_IRQHandler
OHCI_IRQHandler
USBOTG_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SPI3_IRQHandler
SDH0_IRQHandler
USBD20_IRQHandler
EMAC_TX_IRQHandler
EMAC_RX_IRQHandler
I2S0_IRQHandler
OPA0_IRQHandler
CRYPTO_IRQHandler
GPG_IRQHandler
EINT6_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
USCI0_IRQHandler
USCI1_IRQHandler
BPWM0_IRQHandler
BPWM1_IRQHandler
SPIM_IRQHandler
I2C2_IRQHandler
QEI0_IRQHandler
QEI1_IRQHandler
ECAP0_IRQHandler
ECAP1_IRQHandler
GPH_IRQHandler
EINT7_IRQHandler
SDH1_IRQHandler
EHCI_IRQHandler
USBOTG20_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
wuxx/nanoDAP | 1,716 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/erase_check/armv7m_erase_check.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
loop:
ldrb r3, [r0]
adds r0, #1
ands r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end
|
wuxx/nanoDAP | 1,716 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/erase_check/armv7m_0_erase_check.s | /***************************************************************************
* Copyright (C) 2014 by Jeff Ciesielski *
* jeffciesielski@gmail.com *
* *
* Based on the armv7m erase checker by: *
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
loop:
ldrb r3, [r0]
adds r0, #1
orrs r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end
|
wuxx/nanoDAP | 1,646 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/erase_check/armv4_5_erase_check.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.arm
loop:
ldrb r3, [r0], #1
and r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end
|
wuxx/nanoDAP | 3,186 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32f2x.S | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (16bit words)
* r4 = flash base
*
* Clobbered:
* r6 - temp
* r7 - rp
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
ldr r6, STM32_PROG16
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
dsb
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
bne error /* fail... */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement halfword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
|
wuxx/nanoDAP | 2,667 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_16.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end
|
wuxx/nanoDAP | 2,709 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32lx.S | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2011 Clement Burin des Roziers *
* clement.burin-des-roziers@hikob.com *
* *
* Copyright (C) 2017 Armin van der Togt *
* armin@otheruse.nl *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
// Build : arm-eabi-gcc -c stm32lx.S
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/*
r0 - destination address
r1 - source address
r2 - count
*/
// r2 = source + count * 4
lsls r2, r2, #2
adds r2, r1, r2
// Go to compare
b test_done
write_word:
// load word from address in r1 and increase r1 by 4
ldmia r1!, {r3}
// store word to address in r0 and increase r0 by 4
stmia r0!, {r3}
test_done:
// compare r1 and r2
cmp r1, r2
// loop if not equal
bne write_word
// Set breakpoint to exit
bkpt #0x00
|
wuxx/nanoDAP | 2,107 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_intel_8.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrb r4, [r0], #1
strb r3, [r1]
strb r4, [r1]
busy:
ldrb r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #1
b loop
done:
b done
.end
|
wuxx/nanoDAP | 3,878 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/efm32.S | /***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (word-32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
/* offsets of registers from flash reg base */
#define EFM32_MSC_WRITECTRL_OFFSET 0x008
#define EFM32_MSC_WRITECMD_OFFSET 0x00c
#define EFM32_MSC_ADDRB_OFFSET 0x010
#define EFM32_MSC_WDATA_OFFSET 0x018
#define EFM32_MSC_STATUS_OFFSET 0x01c
#define EFM32_MSC_LOCK_OFFSET 0x03c
/* unlock MSC */
ldr r6, =#0x1b71
str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
/* set WREN to 1 */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
/* store address in MSC_ADDRB */
str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
/* set LADDRIM bit */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
/* check status for INVADDR and/or LOCKED */
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #6
tst r6, r7
bne error
/* wait for WDATAREADY */
wait_wdataready:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #8
tst r6, r7
beq wait_wdataready
/* load data to WDATA */
ldr r6, [r5]
str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
/* set WRITEONCE bit */
movs r6, #8
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
adds r5, #4 /* rp++ */
adds r4, #4 /* target_address++ */
/* wait until BUSY flag is reset */
busy:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #1
tst r6, r7
bne busy
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
|
wuxx/nanoDAP | 2,778 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stellaris.s | /***************************************************************************
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start
* r1 = workarea end
* r2 = target address
* r3 = count (32bit words)
*
* Clobbered:
* r4 = pFLASH_CTRL_BASE
* r5 = FLASHWRITECMD
* r7 - rp
* r8 - wp, tmp
*/
write:
ldr r4, pFLASH_CTRL_BASE
ldr r5, FLASHWRITECMD
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
mainloop:
str r2, [r4, #0] /* FMA - write address */
add r2, r2, #4 /* increment target address */
ldr r8, [r7], #4
str r8, [r4, #4] /* FMD - write data */
str r5, [r4, #8] /* FMC - enable write */
busy:
ldr r8, [r4, #8]
tst r8, #1
bne busy
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement word count */
cbz r3, exit /* loop if not done */
b wait_fifo
exit:
bkpt #0
pFLASH_CTRL_BASE: .word 0x400FD000
FLASHWRITECMD: .word 0xA4420001
|
wuxx/nanoDAP | 2,797 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/cortex-m0.S | /***************************************************************************
* Copyright (C) 2014 by Angus Gratton *
* Derived from stm32f1x.S:
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
* very generic (CPU blocks during flash writes), so this is actually
* just a generic word-oriented copy routine for Cortex-M0 (also
* suitable for Cortex-M0+/M3/M4.)
*
* To assemble:
* arm-none-eabi-gcc -c cortex-m0.S
*
* To disassemble:
* arm-none-eabi-objdump -o cortex-m0.o
*
* Thanks to Jens Bauer for providing advice on some of the tweaks.
*/
/* Params:
* r0 - byte count (in)
* r1 - workarea start
* r2 - workarea end
* r3 - target address
* Clobbered:
* r4 - rp
* r5 - wp, tmp
*/
wait_fifo:
ldr r5, [r1, #0] /* read wp */
cmp r5, #0 /* abort if wp == 0 */
beq exit
ldr r4, [r1, #4] /* read rp */
cmp r4, r5 /* wait until rp != wp */
beq wait_fifo
ldmia r4!, {r5} /* "*target_address++ = *rp++" */
stmia r3!, {r5}
cmp r4, r2 /* wrap rp at end of work area buffer */
bcc no_wrap
mov r4, r1
adds r4, #8 /* skip rp,wp at start of work area */
no_wrap:
str r4, [r1, #4] /* write back rp */
subs r0, #4 /* decrement byte count */
bne wait_fifo /* loop if not done */
exit:
bkpt #0
|
wuxx/nanoDAP | 2,451 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
bne busy
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end
|
wuxx/nanoDAP | 2,665 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32f1x.S | /***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (halfword-16bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldrh r6, [r5] /* "*target_address++ = *rp++" */
strh r6, [r4]
adds r5, #2
adds r4, #2
busy:
ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
movs r7, #1
tst r6, r7
bne busy
movs r7, #0x14 /* check the error bits */
tst r6, r7
bne error
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement halfword count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
|
wuxx/nanoDAP | 2,481 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/sim3x.s | /***************************************************************************
* Copyright (C) 2014 by Ladislav Bábel *
* ladababel@seznam.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
#define INITIAL_UNLOCK 0x5A
#define MULTIPLE_UNLOCK 0xF2
#define FLASHCTRL_KEY 0x4002E0C0
#define FLASHCTRL_CONFIG 0x4002E000
#define FLASHCTRL_WRADDR 0x4002E0A0
#define FLASHCTRL_WRDATA 0x4002E0B0
#define BUSYF 0x00100000
/* Write the initial unlock value to KEY (0xA5) */
movs r6, #INITIAL_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
/* Write the multiple unlock value to KEY (0xF2) */
movs r6, #MULTIPLE_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
wait_fifo:
ldr r6, [r2, #0]
cmp r6, #0
beq exit
ldr r5, [r2, #4]
cmp r5, r6
beq wait_fifo
/* wait for BUSYF flag */
wait_busy1:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy1
/* Write the destination address to WRADDR */
str r4, [r0, #FLASHCTRL_WRADDR]
/* Write the data half-word to WRDATA in right-justified format */
ldrh r6, [r5]
str r6, [r0, #FLASHCTRL_WRDATA]
adds r5, #2
adds r4, #2
/* wrap rp at end of buffer */
cmp r5, r3
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4]
subs r1, r1, #1
cmp r1, #0
beq exit
b wait_fifo
exit:
movs r6, #MULTIPLE_LOCK
str r6, [r0, #FLASHCTRL_KEY]
/* wait for BUSYF flag */
wait_busy2:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy2
bkpt #0
|
wuxx/nanoDAP | 2,717 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv7m_cfi_span_16.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end
|
wuxx/nanoDAP | 2,305 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/str7x.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4t
.section .init
/*
r0 source address
r1 address
r2 FLASH_CR0
r3 dword count
r4 result
r5 busy mask
*/
write:
mov r4, #0x10000000 /* set DWPG bit */
str r4, [r2, #0x0] /* FLASH_CR0 */
str r1, [r2, #0x10] /* FLASH_AR */
ldr r4, [r0], #4 /* load data */
str r4, [r2, #0x8] /* FLASH_DR0 */
ldr r4, [r0], #4 /* load data */
str r4, [r2, #0xc] /* FLASH_DR1 */
mov r4, #0x90000000 /* set DWPG and WMS bits */
str r4, [r2, #0x0] /* FLASH_CR0 */
busy:
ldr r4, [r2, #0x0] /* FLASH_CR0 */
tst r4, r5
bne busy
ldr r4, [r2, #0x14] /* FLASH_ER */
tst r4, #0xff /* do we have errors */
tsteq r4, #0x100 /* write protection set */
bne exit
add r1, r1, #0x8 /* next 8 bytes */
subs r3, r3, #1 /* decremment dword count */
bne write
exit:
b exit
.end
|
wuxx/nanoDAP | 3,655 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/pic32mx.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arch m4k
.set noreorder
.set noat
/* params:
* $a0 src adr - ram + result
* $a1 dest adr - flash
* $a2 count (32bit words)
* vars
*
* temps:
* $t0, $t1, $t2, $t3, $t4, $t5
* $s0, $s1, $s3, $s4, $s5
*/
.type main, @function
.global main
.ent main
main:
/* setup constants */
lui $t0, 0xaa99
ori $t0, 0x6655 /* NVMKEY1 */
lui $t1, 0x5566
ori $t1, 0x99AA /* NVMKEY2 */
lui $t2, 0xBF80
ori $t2, 0xF400 /* NVMCON */
ori $t3, $zero, 0x4003 /* NVMCON row write cmd */
ori $t4, $zero, 0x8000 /* NVMCON start cmd */
write_row:
/* can we perform a row write: 128 32bit words */
sltiu $s3, $a2, 128
bne $s3, $zero, write_word
ori $t5, $zero, 0x4000 /* NVMCON clear cmd */
/* perform row write 512 bytes */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
sw $a0, 64($t2) /* set NVMSRCADDR with src addr - real addr */
bal progflash
addiu $a0, $a0, 512
addiu $a1, $a1, 512
beq $zero, $zero, write_row
addiu $a2, $a2, -128
write_word:
/* write 32bit words */
lui $s5, 0xa000
ori $s5, 0x0000
or $a0, $a0, $s5 /* convert to virtual addr */
beq $zero, $zero, next_word
ori $t3, $zero, 0x4001 /* NVMCON word write cmd */
prog_word:
lw $s4, 0($a0) /* load data - from virtual addr */
sw $s4, 48($t2) /* set NVMDATA with data */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
bal progflash
addiu $a0, $a0, 4
addiu $a1, $a1, 4
addiu $a2, $a2, -1
next_word:
bne $a2, $zero, prog_word
nop
done:
beq $zero, $zero, exit
addiu $a0, $zero, 0
error:
/* save result to $a0 */
addiu $a0, $s1, 0
exit:
sdbbp
.end main
.type progflash, @function
.global progflash
.ent progflash
progflash:
sw $t3, 0($t2) /* set NVMWREN */
sw $t0, 16($t2) /* write NVMKEY1 */
sw $t1, 16($t2) /* write NVMKEY2 */
sw $t4, 8($t2) /* start operation */
waitflash:
lw $s0, 0($t2)
and $s0, $s0, $t4
bne $s0, $zero, waitflash
nop
/* following is to comply with errata #34
* 500ns delay required */
nop
nop
nop
nop
/* check for errors */
lw $s1, 0($t2)
andi $s1, $zero, 0x3000
bne $s1, $zero, error
sw $t5, 4($t2) /* clear NVMWREN */
jr $ra
nop
.end progflash
|
wuxx/nanoDAP | 2,667 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_32.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldr r5, [r0], #4
str r9, [r8]
str r11, [r10]
str r3, [r8]
str r5, [r1]
nop
busy:
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #4 /* 0x4 */
b code
done:
b done
.end
|
wuxx/nanoDAP | 2,431 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, #0x80
bne busy
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end
|
wuxx/nanoDAP | 7,671 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/lpcspifi_write.S | /***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - temp
* r11 - current page end address
*/
/*
* This code is embedded within: src/flash/nor/lpcspifi.c as a "C" array.
*
* To rebuild:
* arm-none-eabi-gcc -c lpcspifi_write.S
* arm-none-eabi-objcopy -O binary lpcspifi_write.o lpcspifi_write.bin
* xxd -c 8 -i lpcspifi_write.bin > lpcspifi_write.txt
*
* Then read and edit this result into the "C" source.
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
mov.w r11, #0x00
find_next_page_boundary:
add r11, r4 /* Increment to the next page */
cmp r11, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
page_program:
bl cs_down
mov.w r9, #0x02 /* Send the page program command */
bl write_data
write_address:
lsr r9, r2, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r2, #8
bl write_data
mov.w r9, r2
bl write_data
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cbz r3, exit /* Exit if we have written everything */
add r2, #1 /* Increment flash address by 1 */
cmp r11, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
bl cs_up /* Otherwise, end the command and keep going w/ the next page */
add r11, r4 /* Move up the end-of-page address by the page size*/
wait_flash_busy: /* Wait for the flash to finish the previous page write */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
b write_enable /* If it is done, start a new page write */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
bl cs_up /* end the command before returning */
mov r0, r6
bkpt #0x00
.end
|
wuxx/nanoDAP | 2,107 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_intel_32.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldr r4, [r0], #4
str r3, [r1]
str r4, [r1]
busy:
ldr r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #4
b loop
done:
b done
.end
|
wuxx/nanoDAP | 2,667 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_8.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrb r5, [r0], #1
strb r9, [r8]
strb r11, [r10]
strb r3, [r8]
strb r5, [r1]
nop
busy:
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #1 /* 0x1 */
b code
done:
b done
.end
|
wuxx/nanoDAP | 3,409 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/k1921vk01t.S | /***************************************************************************
* Copyright (C) 2015 by Bogdan Kolbov *
* kolbov@niiet.ru *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
/* K1921VK01T has 128-bitwidth flash, so it`s able to load 4x32-bit words at the time.
* And only after all words loaded we can start write
*/
/* Registers addresses */
#define FLASH_FMA 0x00 /* Address reg */
#define FLASH_FMD1 0x04 /* Data1 reg */
#define FLASH_FMC 0x08 /* Command reg */
#define FLASH_FCIS 0x0C /* Operation Status reg */
#define FLASH_FCIC 0x14 /* Operation Status Clear reg */
#define FLASH_FMD2 0x50 /* Data2 reg */
#define FLASH_FMD3 0x54 /* Data3 reg */
#define FLASH_FMD4 0x58 /* Data4 reg*/
/* Params:
* r0 - write cmd (in), status (out)
* r1 - count
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - flash base
*/
ldr r7, =#0xA001C000 /* Flash reg base*/
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
load_data:
ldr r6, [r5] /* read data1 */
str r6, [r7, #FLASH_FMD1]
adds r5, #4
ldr r6, [r5] /* read data2 */
str r6, [r7, #FLASH_FMD2]
adds r5, #4
ldr r6, [r5] /* read data3 */
str r6, [r7, #FLASH_FMD3]
adds r5, #4
ldr r6, [r5] /* read data4 */
str r6, [r7, #FLASH_FMD4]
adds r5, #4
start_write:
str r4, [r7, #FLASH_FMA] /* set addr */
adds r4, #16
str r0, [r7, #FLASH_FMC] /* write cmd */
busy:
ldr r6, [r7, #FLASH_FCIS] /* wait until flag set */
cmp r6, #0x0
beq busy
cmp r6, #2 /* check the error bit */
beq error
movs r6, #1 /* clear flags */
str r6, [r7, #FLASH_FCIC]
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement 16-byte block count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
|
wuxx/nanoDAP | 2,128 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/str9x.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv5t
.section .init
/*
r0 source address (in)
r1 target address (in)
r2 word count (in)
r3 result (out)
*/
write:
bic r4, r1, #3 /* word address */
mov r3, #0x40 /* write command */
strh r3, [r4, #0]
ldrh r3, [r0], #2 /* read data */
strh r3, [r1], #2 /* write data */
mov r3, #0x70 /* status command */
strh r3, [r4, #0]
busy:
ldrb r3, [r4, #0] /* status */
tst r3, #0x80
beq busy
mov r5, #0x50 /* clear status command */
strh r5, [r4, #0]
mov r5, #0xFF /* read array */
strh r5, [r4, #0]
tst r3, #0x12
bne exit
subs r2, r2, #1 /* decremment word count */
bne write
exit:
bkpt #0
.end
|
wuxx/nanoDAP | 3,704 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/mdr32fx.S | /***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* Copyright (C) 2013 by Paul Fertser *
* fercerpav@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - current FLASH_CMD
*/
#define FLASH_CMD 0x00
#define FLASH_ADR 0x04
#define FLASH_DI 0x08
#define FLASH_NVSTR (1 << 13)
#define FLASH_PROG (1 << 12)
#define FLASH_MAS1 (1 << 11)
#define FLASH_ERASE (1 << 10)
#define FLASH_SE (1 << 8)
#define FLASH_YE (1 << 7)
#define FLASH_XE (1 << 6)
ldr r7, [r0, #FLASH_CMD]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldr r6, [r5] /* "*target_address++ = *rp++" */
str r4, [r0, #FLASH_ADR]
str r6, [r0, #FLASH_DI]
ldr r6, =(FLASH_XE | FLASH_PROG)
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 5us
movs r6, #5
bl delay
ldr r6, =#FLASH_NVSTR
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 10us
movs r6, #13
bl delay
movs r6, #FLASH_YE
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 40us
movs r6, #61
bl delay
movs r6, #FLASH_YE
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
ldr r6, =#FLASH_PROG
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 5us
movs r6, #5
bl delay
ldr r6, =#(FLASH_XE | FLASH_NVSTR)
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
adds r5, #4
adds r4, #4
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
/* r6 - in
* for r6 == 1 it'll take:
* 1 (prepare operand) + 4 (bl) + 2 (subs+cmp) + 1 (bne) + 3 (b) ->
* 11 tacts == 1.4us with 8MHz
* every extra iteration will take 5 tacts == 0.6us */
delay:
subs r6, r6, #1
cmp r6, #0
bne delay
bx lr
|
wuxx/nanoDAP | 4,289 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/lpcspifi_init.S | /***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/***************************************************************************
* This is an algorithm for the LPC43xx family (and probably the LPC18xx *
* family as well, though they have not been tested) that will initialize *
* memory-mapped SPI flash accesses. Unfortunately NXP has published *
* neither the ROM source code that performs this initialization nor the *
* register descriptions necessary to do so, so this code is necessary to *
* call into the ROM SPIFI API. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/*
* Params :
* r0 = spifi clock speed
*/
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
#define SPIFI_ROM_TABLE_BASE_LOW 0x0118
code:
mov.w r8, r0
sub sp, #0x84
add r7, sp, #0x0
/* Initialize SPIFI pins */
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0xf3
str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #IOCONFIG_BASE_LOW
movt r2, #IOCONFIG_BASE_HIGH
mov.w r1, #IOCONFIG_BASE_LOW
movt r1, #IOCONFIG_BASE_HIGH
mov.w r0, #IOCONFIG_BASE_LOW
movt r0, #IOCONFIG_BASE_HIGH
mov.w r4, #0xd3
str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
mov r0, r4
str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
mov r1, r0
str.w r1, [r2, #IOCONFIG_WP_OFFSET]
str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0x13
str.w r2, [r3, #IOCONFIG_CS_OFFSET]
/* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
/* on initialization arguments. */
movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
ldr r3, [r3, #0x0]
ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
/* Set up function arguments */
movw r0, #0x3b4
movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
mov.w r3, r8 /* SPIFI clock speed (12MHz) */
blx r4 /* Call the init function */
b done
done:
bkpt #0
.end
|
wuxx/nanoDAP | 1,928 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv7m_io.s | /***************************************************************************
* Copyright (C) 2013 by Henrik Nilsson *
* henrik.nilsson@bytequest.se *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 4
/* Inputs:
* r0 buffer address
* r1 NAND data address (byte wide)
* r2 buffer length
*/
read:
ldrb r3, [r1]
strb r3, [r0], #1
subs r2, r2, #1
bne read
done_read:
bkpt #0
.align 4
/* Inputs:
* r0 NAND data address (byte wide)
* r1 buffer address
* r2 buffer length
*/
write:
ldrb r3, [r1], #1
strb r3, [r0]
subs r2, r2, #1
bne write
done_write:
bkpt #0
.end
|
wuxx/nanoDAP | 3,759 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32l4x.S | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2015 Uwe Bonnes *
* bon@elektron.ikp.physik.tu-darmstadt.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
/* To assemble:
* arm-none-eabi-gcc -c stm32l4x.S
*
* To disassemble:
* arm-none-eabi-objdump -o stm32l4x.o
*
* To generate binary file:
* arm-none-eabi-objcopy -O binary stm32l4x.o stm32l4_flash_write_code.bin
*
* To generate include file:
* xxd -i stm32l4_flash_write_code.bin
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (64bit words)
* r4 = flash base
*
* Clobbered:
* r5 - rp
* r6/7 - temp (64-bit)
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r0, #4] /* read rp */
subs r6, r8, r5 /* number of bytes available for read in r6*/
itt mi /* if wrapped around*/
addmi r6, r1 /* add size of buffer */
submi r6, r0
cmp r6, #8 /* wait until 8 bytes are available */
bcc wait_fifo
ldr r6, STM32_PROG
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */
strd r6, [r2], #0x08 /* write one word to dst, increment ptr */
dsb
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xfa /* PGSERR | PGPERR | PGAERR | WRPERR | PROGERR*/
bne error /* fail... */
cmp r5, r1 /* wrap rp at end of buffer */
it cs
addcs r5, r0, #8 /* skip loader args */
str r5, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement dword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG: .word 0x1 /* PG */
|
wuxx/nanoDAP | 6,486 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/mrvlqspi_write.S | /***************************************************************************
* Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com> *
* *
* Adapted from (contrib/loaders/flash/lpcspifi_write.S): *
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* For compilation:
* arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c contrib/loaders/flash/mrvlqspi_write.S
* arm-none-eabi-objcopy -O binary mrvlqspi_write.o code.bin
* Copy code.bin into mrvlqspi flash driver
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* r5 = qspi base address
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - current page end address
*/
#define CNTL 0x0
#define CONF 0x4
#define DOUT 0x8
#define DIN 0xc
#define INSTR 0x10
#define ADDR 0x14
#define RDMODE 0x18
#define HDRCNT 0x1c
#define DINCNT 0x20
#define SS_EN (1 << 0)
#define XFER_RDY (1 << 1)
#define RFIFO_EMPTY (1 << 4)
#define WFIFO_EMPTY (1 << 6)
#define WFIFO_FULL (1 << 7)
#define FIFO_FLUSH (1 << 9)
#define RW_EN (1 << 13)
#define XFER_STOP (1 << 14)
#define XFER_START (1 << 15)
#define INS_WRITE_ENABLE 0x06
#define INS_READ_STATUS 0x05
#define INS_PAGE_PROGRAM 0x02
init:
mov.w r10, #0x00
find_next_page_boundary:
add r10, r4 /* Increment to the next page */
cmp r10, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
/* Flush read/write fifo's */
bl flush_fifo
/* Instruction byte 1 */
movs r8, #0x1
str r8, [r5, #HDRCNT]
/* Set write enable instruction */
movs r8, #INS_WRITE_ENABLE
str r8, [r5, #INSTR]
movs r9, #0x1
bl start_tx
bl stop_tx
page_program:
/* Instruction byte 1, Addr byte 3 */
movs r8, #0x31
str r8, [r5, #HDRCNT]
/* Todo: set addr and data pin to single */
write_address:
mov r8, r2
str r8, [r5, #ADDR]
/* Set page program instruction */
movs r8, #INS_PAGE_PROGRAM
str r8, [r5, #INSTR]
/* Start write transfer */
movs r9, #0x1
bl start_tx
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cmp r3, #0 /* Exit if we have written everything */
beq write_wait
add r2, #1 /* Increment flash address by 1 */
cmp r10, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
write_wait:
bl stop_tx /* Otherwise, end the command and keep going w/ the next page */
add r10, r4 /* Move up the end-of-page address by the page size*/
check_flash_busy: /* Wait for the flash to finish the previous page write */
/* Flush read/write fifo's */
bl flush_fifo
/* Instruction byte 1 */
movs r8, #0x1
str r8, [r5, #HDRCNT]
/* Continuous data in of status register */
movs r8, #0x0
str r8, [r5, #DINCNT]
/* Set write enable instruction */
movs r8, #INS_READ_STATUS
str r8, [r5, #INSTR]
/* Start read transfer */
movs r9, #0x0
bl start_tx
wait_flash_busy:
bl read_data
and.w r9, r9, #0x1
cmp r9, #0x0
bne.n wait_flash_busy
bl stop_tx
cmp r3, #0
bne.n write_enable /* If it is done, start a new page write */
b exit /* All data written, exit */
write_data: /* Send/receive 1 byte of data over QSPI */
ldr r8, [r5, #CNTL]
lsls r8, r8, #24
bmi.n write_data
str r9, [r5, #DOUT]
bx lr
read_data: /* Read 1 byte of data over QSPI */
ldr r8, [r5, #CNTL]
lsls r8, r8, #27
bmi.n read_data
ldr r9, [r5, #DIN]
bx lr
flush_fifo: /* Flush read write fifos */
ldr r8, [r5, #CONF]
orr.w r8, r8, #FIFO_FLUSH
str r8, [r5, #CONF]
flush_reset:
ldr r8, [r5, #CONF]
lsls r8, r8, #22
bmi.n flush_reset
bx lr
start_tx:
ldr r8, [r5, #CNTL]
orr.w r8, r8, #SS_EN
str r8, [r5, #CNTL]
xfer_rdy:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n xfer_rdy
ldr r8, [r5, #CONF]
bfi r8, r9, #13, #1
orr.w r8, r8, #XFER_START
str r8, [r5, #CONF]
bx lr
stop_tx:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n stop_tx
wfifo_wait:
ldr r8, [r5, #CNTL]
lsls r8, r8, #25
bpl.n wfifo_wait
ldr r8, [r5, #CONF]
orr.w r8, r8, #XFER_STOP
str r8, [r5, #CONF]
xfer_start:
ldr r8, [r5, #CONF]
lsls r8, r8, #16
bmi.n xfer_start
ss_disable:
# Disable SS_EN
ldr r8, [r5, #CNTL]
bic.w r8, r8, #SS_EN
str r8, [r5, #CNTL]
wait:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n wait
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6
bkpt #0x00
.end
|
wuxx/nanoDAP | 5,997 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/lpcspifi_erase.S | /***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = start address, status (out)
* r1 = count
* r2 = erase command
* r3 = block size
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
erase:
bl cs_down
mov.w r9, r2 /* Send the erase command */
bl write_data
write_address:
lsr r9, r0, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r0, #8
bl write_data
mov.w r9, r0
bl write_data
bl cs_up
wait_flash_busy: /* Wait for the flash to finish the previous erase */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
subs r1, r1, #1 /* decrement count */
cbz r1, exit /* Exit if we have written everything */
add r0, r3 /* Move the address up by the block size */
b write_enable /* Start a new block erase */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
exit:
bkpt #0x00
.end
|
wuxx/nanoDAP | 2,107 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_intel_16.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrh r4, [r0], #2
strh r3, [r1]
strh r4, [r1]
busy:
ldrh r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #2
b loop
done:
b done
.end
|
wuxx/nanoDAP | 2,240 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/watchdog/armv7m_kinetis_wdog.s | /***************************************************************************
* Copyright (C) 2015 Tomas Vanek *
* vanekt@fbl.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
/*
Disable watchdog for Kinetis Kx and KVx
Parameters: none
Used instruction set should work on both Cortex-M4 and M0+
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
WDOG_ADDR = 0x40052000
/* WDOG registers offsets */
WDOG_STCTRLH = 0
WDOG_UNLOCK = 0x0e
WDOG_KEY1 = 0xc520
WDOG_KEY2 = 0xd928
.thumb_func
start:
/* WDOG_UNLOCK = 0xC520 */
ldr r3, =WDOG_ADDR
ldr r2, =WDOG_KEY1
strh r2, [r3, WDOG_UNLOCK]
/* WDOG_UNLOCK = 0xD928 */
ldr r2, =WDOG_KEY2
strh r2, [r3, WDOG_UNLOCK]
/* WDOG_STCTRLH clear bit 0 */
movs r4, #1
ldrh r2, [r3, WDOG_STCTRLH]
bics r2, r4
strh r2, [r3, WDOG_STCTRLH]
/* OpenOCD checks exit point address. Jump to the very end. */
b done
.pool
/* Avoid padding at .text segment end. Otherwise exit point check fails. */
.skip ( . - start + 2) & 2, 0
done:
bkpt #0
.end
|
wuxx/nanoDAP | 2,376 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/checksum/mips32.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.global main
.text
.set noreorder
/* params:
* $a0 address in
* $a1 byte count
* vars
* $a0 crc
* $a1 crc data byte
* temps:
* t3 v0 a3 a2 t0 v1
*/
.ent main
main:
addiu $t4, $a0, 0 /* address in */
addiu $t2, $a1, 0 /* count */
addiu $a0, $zero, 0xffffffff /* a0 crc - result */
beq $zero, $zero, ncomp
addiu $t3, $zero, 0 /* clear bytes read */
nbyte:
lb $a1, ($t4) /* load byte from source address */
addi $t4, $t4, 1 /* inc byte count */
crc:
sll $a1, $a1, 24
lui $v0, 0x04c1
xor $a0, $a0, $a1
ori $a3, $v0, 0x1db7
addu $a2, $zero, $zero /* clear bit count */
loop:
sll $t0, $a0, 1
addiu $a2, $a2, 1 /* inc bit count */
slti $a0, $a0, 0
xor $t1, $t0, $a3
movn $t0, $t1, $a0
slti $v1, $a2, 8 /* 8bits processed */
bne $v1, $zero, loop
addu $a0, $t0, $zero
ncomp:
bne $t2, $t3, nbyte /* all bytes processed */
addiu $t3, $t3, 1
wait:
sdbbp
.end main
|
wuxx/nanoDAP | 1,919 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/checksum/armv4_5_crc.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
r0 - address in - crc out
r1 - char count
*/
.text
.arm
_start:
main:
mov r2, r0
mov r0, #0xffffffff /* crc */
mov r3, r1
mov r4, #0
b ncomp
nbyte:
ldrb r1, [r2, r4]
ldr r7, CRC32XOR
eor r0, r0, r1, asl #24
mov r5, #0
loop:
cmp r0, #0
mov r6, r0, asl #1
add r5, r5, #1
mov r0, r6
eorlt r0, r6, r7
cmp r5, #8
bne loop
add r4, r4, #1
ncomp:
cmp r4, r3
bne nbyte
end:
bkpt #0
CRC32XOR: .word 0x04c11db7
.end
|
wuxx/nanoDAP | 2,035 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/checksum/armv7m_crc.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in - crc out
r1 - char count
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
_start:
main:
mov r2, r0
movs r0, #0
mvns r0, r0
ldr r6, CRC32XOR
mov r3, r1
movs r4, #0
b ncomp
nbyte:
ldrb r1, [r2, r4]
lsls r1, r1, #24
eors r0, r0, r1
movs r5, #0
loop:
cmp r0, #0
bge notset
lsls r0, r0, #1
eors r0, r0, r6
b cont
notset:
lsls r0, r0, #1
cont:
adds r5, r5, #1
cmp r5, #8
bne loop
adds r4, r4, #1
ncomp:
cmp r4, r3
bne nbyte
bkpt #0
.align 2
CRC32XOR: .word 0x04c11db7
.end
|
wuxx/nanoDAP | 1,239 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/xmc1xxx/erase_check.S | /*
* Infineon XMC1000 flash sector erase check
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
*
* License: GPL-2.0+
*/
#include "xmc1xxx.S"
.macro verify_block, nvmbase, addr, tmp, tmp2
movs \tmp, #0x00
mvns \tmp, \tmp
str \tmp, [\addr, #0x0]
str \tmp, [\addr, #0x4]
str \tmp, [\addr, #0x8]
str \tmp, [\addr, #0xC]
busy_wait \nvmbase, \tmp, \tmp2
.endm
.macro erase_check, nvmbase, addr, end, tmp, tmp2
ldrh \tmp, [\nvmbase, #NVMCONF]
movs \tmp2, #NVMCONF_HRLEV_MASK
mvns \tmp2, \tmp2
ands \tmp, \tmp, \tmp2
movs \tmp2, #NVMCONF_HRLEV_HRE
orrs \tmp, \tmp, \tmp2
strh \tmp, [\nvmbase, #NVMCONF]
movs \tmp, #NVMPROG_ACTION_VERIFY_CONTINUOUS
strh \tmp, [\nvmbase, #NVMPROG]
2001:
verify_block \nvmbase, \addr, \tmp, \tmp2
ldrh \tmp, [\nvmbase, #NVMSTATUS]
movs \tmp2, #NVMSTATUS_VERR_MASK
ands \tmp, \tmp, \tmp2
cmp \tmp, #NVMSTATUS_VERR_NOFAIL
bne 2010f
adds \addr, \addr, #NVM_BLOCK_SIZE
cmp \addr, \end
blt 2001b
2010:
movs \tmp, #NVMPROG_ACTION_IDLE
strh \tmp, [\nvmbase, #NVMPROG]
.endm
/*
* r0 = 0x40050000
* r1 = e.g. 0x10001000
* r2 = e.g. 0x10002000
* NVMPROG.ACTION = 0x00
*/
erase_check:
erase_check r0, r1, r2, r3, r4
bkpt #0
|
wuxx/nanoDAP | 1,023 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/xmc1xxx/write.S | /*
* Infineon XMC1000 flash write
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
*
* License: GPL-2.0+
*/
#include "xmc1xxx.S"
.macro write_block, nvmbase, dest, src, tmp, tmp2
ldr \tmp, [\src, #0x0]
str \tmp, [\dest, #0x0]
ldr \tmp, [\src, #0x4]
str \tmp, [\dest, #0x4]
ldr \tmp, [\src, #0x8]
str \tmp, [\dest, #0x8]
ldr \tmp, [\src, #0xc]
str \tmp, [\dest, #0xc]
busy_wait \nvmbase, \tmp, \tmp2
.endm
.macro write, nvmbase, dest, src, count, tmp, tmp2
movs \tmp, #NVMPROG_ACTION_WRITE_CONTINUOUS
strh \tmp, [\nvmbase, #NVMPROG]
1001:
write_block \nvmbase, \dest, \src, \tmp, \tmp2
adds \dest, \dest, #NVM_BLOCK_SIZE
adds \src, \src, #NVM_BLOCK_SIZE
subs \count, \count, #1
cmp \count, #0
bgt 1001b
movs \tmp, #NVMPROG_ACTION_IDLE
strh \tmp, [\nvmbase, #NVMPROG]
.endm
/*
* r0 = 0x40050000
* r1 = e.g. 0x10001000
* r2 = e.g. 0x20000000
* r3 = e.g. 1
* NVMPROG.ACTION = 0x00
*/
write:
write r0, r1, r2, r3, r4, r5
bkpt #0
|
wuxx/nanoDAP | 1,238 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/fm4/erase.S | /*
* Spansion FM4 flash sector erase algorithm
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
#include "fm4.h"
#define RESULT_OKAY 0
#define RESULT_NONE 1
#define RESULT_TIMEOUT 2
.macro busy_wait, res, addr, tmp1, tmp2, tmp3
ldrb \tmp1, [\addr] /* ignore */
1001:
ldrb \tmp1, [\addr]
ldrb \tmp2, [\addr]
and \tmp3, \tmp1, #FLASH_TOGG
and \tmp2, \tmp2, #FLASH_TOGG
cmp \tmp3, \tmp2
beq 1010f
and \tmp2, \tmp1, #FLASH_TLOV
cmp \tmp2, #0
beq 1001b
ldrb \tmp1, [\addr]
ldrb \tmp2, [\addr]
and \tmp3, \tmp1, #FLASH_TOGG
and \tmp2, \tmp2, #FLASH_TOGG
cmp \tmp3, \tmp2
beq 1010f
mov \res, #RESULT_TIMEOUT
bkpt #0
1010:
mov \res, #RESULT_OKAY
.endm
.macro erase, cmdseqaddr1, cmdseqaddr2, sa, res, tmp1, tmp2, tmp3
mov \res, #RESULT_NONE
mov \tmp1, #0xAA
strh \tmp1, [\cmdseqaddr1]
mov \tmp2, #0x55
strh \tmp2, [\cmdseqaddr2]
mov \tmp3, #0x80
strh \tmp3, [\cmdseqaddr1]
strh \tmp1, [\cmdseqaddr1]
strh \tmp2, [\cmdseqaddr2]
mov \tmp3, #0x30
strh \tmp3, [\sa]
busy_wait \res, \sa, \tmp1, \tmp2, \tmp3
.endm
/* r0 = 0xAA8
* r1 = 0x554
* r2 = SA
* r3 = result
*/
erase:
erase r0, r1, r2, r3, r4, r5, r6
bkpt #0
data:
|
wuxx/nanoDAP | 1,433 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/fm4/write.S | /*
* Spansion FM4 flash write algorithm
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
#include "fm4.h"
#define RESULT_OKAY 0
#define RESULT_NONE 1
#define RESULT_TIMEOUT 2
.macro busy_wait, res, addr, data, tmp1, tmp2, tmp3
ldrb \tmp1, [\addr] /* ignore */
and \tmp2, \data, #FLASH_DPOL
1001:
ldrb \tmp1, [\addr]
and \tmp3, \tmp1, #FLASH_DPOL
cmp \tmp3, \tmp2
beq 1010f
and \tmp3, \tmp1, #FLASH_TLOV
cmp \tmp3, #0
beq 1001b
ldrb \tmp1, [\addr]
and \tmp3, \tmp1, #FLASH_DPOL
cmp \tmp3, \tmp2
beq 1010f
mov \res, #RESULT_TIMEOUT
bkpt #0
1010:
.endm
.macro write_one, res, cmdseqaddr1, cmdseqaddr2, pa, pd, tmp1, tmp2, tmp3
mov \tmp1, #0xAA
strh \tmp1, [\cmdseqaddr1]
mov \tmp1, #0x55
strh \tmp1, [\cmdseqaddr2]
mov \tmp1, #0xA0
strh \tmp1, [\cmdseqaddr1]
strh \pd, [\pa]
busy_wait \res, \pa, \pd, \tmp1, \tmp2, \tmp3
.endm
.macro write, cmdseqaddr1, cmdseqaddr2, dest, src, cnt, res, tmp1, tmp2, tmp3, tmp4
mov \res, #RESULT_NONE
2001:
cbz \cnt, 2010f
ldrh \tmp1, [\src]
write_one \res, \cmdseqaddr1, \cmdseqaddr2, \dest, \tmp1, \tmp2, \tmp3, \tmp4
sub \cnt, \cnt, #1
add \dest, \dest, #2
add \src, \src, #2
b 2001b
2010:
mov \res, #RESULT_OKAY
.endm
/* r0 = 0xAA8
* r1 = 0x554
* r2 = dest
* r3 = src
* r4 = cnt
* r5 = result
*/
write:
write r0, r1, r2, r3, r4, r5, r6, r7, r8, r9
bkpt #0
data:
|
wuxx/nanoDAP | 2,767 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/kinetis/kinetis_flash.s | /***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* Copyright (C) 2016 by Tomas Vanek *
* vanekt@fbl.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
/* Params:
* r0 = flash destination address in/out
* r1 = longword count
* r2 = workarea start address
* r3 = workarea end address
* r4 = FTFx base
*/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
/* r5 = rp
* r6 = wp, tmp
* r7 = tmp
*/
/* old longword algo: 6.680 KiB/s @ adapter_khz 2000
* this async algo: 19.808 KiB/s @ adapter_khz 2000
*/
FTFx_FSTAT = 0
FTFx_FCCOB3 = 4
FTFx_FCCOB0 = 7
FTFx_FCCOB7 = 8
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
str r0, [r4, #FTFx_FCCOB3] /* set flash address */
mov r7, #6
strb r7, [r4, #FTFx_FCCOB0] /* flash command */
ldr r7, [r5] /* set longword data = *rp */
str r7, [r4, #FTFx_FCCOB7]
mov r7, #128
strb r7, [r4, #FTFx_FSTAT]
add r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc no_wrap
mov r5, r2
add r5, #8
no_wrap:
str r5, [r2, #4] /* Store rp */
wait_ccif:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldrb r6, [r4, #FTFx_FSTAT]
tst r6, r7
beq wait_ccif
mov r7, #0x70
tst r6, r7
bne error
add r0, #4 /* flash address += 4, do not increment before err check */
sub r1, #1 /* word_count-- */
cmp r1, #0
bne wait_fifo
b exit
error:
mov r5, #0
str r5, [r2, #4] /* set rp = 0 on error */
exit:
bkpt #0
|
wuxx/nanoDAP | 6,878 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/at91sam7x/crt.s | /****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 18.12.06 mifi First Version
* The hardware initialization is based on the startup file
* crtat91sam7x256_rom.S from NutOS 4.2.1.
* Therefore partial copyright by egnite Software GmbH.
****************************************************************************/
/*
* Some defines for the program status registers
*/
ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F
I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */
/*
* Register Base Address
*/
AIC_BASE = 0xFFFFF000
AIC_EOICR_OFF = 0x130
AIC_IDCR_OFF = 0x124
RSTC_MR = 0xFFFFFD08
RSTC_KEY = 0xA5000000
RSTC_URSTEN = 0x00000001
WDT_BASE = 0xFFFFFD40
WDT_MR_OFF = 0x00000004
WDT_WDDIS = 0x00008000
MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100
.section .vectors,"ax"
.code 32
/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
_vectors:
ldr pc, ResetAddr /* Reset */
ldr pc, UndefAddr /* Undefined instruction */
ldr pc, SWIAddr /* Software interrupt */
ldr pc, PAbortAddr /* Prefetch abort */
ldr pc, DAbortAddr /* Data abort */
ldr pc, ReservedAddr /* Reserved */
ldr pc, IRQAddr /* IRQ interrupt */
ldr pc, FIQAddr /* FIQ interrupt */
ResetAddr: .word ResetHandler
UndefAddr: .word UndefHandler
SWIAddr: .word SWIHandler
PAbortAddr: .word PAbortHandler
DAbortAddr: .word DAbortHandler
ReservedAddr: .word 0
IRQAddr: .word IRQHandler
FIQAddr: .word FIQHandler
.ltorg
.section .init, "ax"
.code 32
.global ResetHandler
.global ExitFunction
.extern main
/****************************************************************************/
/* Reset handler */
/****************************************************************************/
ResetHandler:
/*
* The watchdog is enabled after processor reset. Disable it.
*/
ldr r1, =WDT_BASE
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]
/*
* Enable user reset: assertion length programmed to 1ms
*/
ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
ldr r1, =RSTC_MR
str r0, [r1, #0]
/*
* Use 2 cycles for flash access.
*/
ldr r1, =MC_BASE
ldr r0, =MC_FWS_1FWS
str r0, [r1, #MC_FMR_OFF]
/*
* Disable all interrupts. Useful for debugging w/o target reset.
*/
ldr r1, =AIC_BASE
mvn r0, #0
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]
/*
* Setup a stack for each mode
*/
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end
/*
* Clear .bss section
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
ldr r3, =0
bss_clear_loop:
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop
/*
* Jump to main
*/
mrs r0, cpsr
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
msr cpsr, r0
mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, =main
mov lr, pc
bx r2 /* And jump... */
ExitFunction:
nop
nop
nop
b ExitFunction
/****************************************************************************/
/* Default interrupt handler */
/****************************************************************************/
UndefHandler:
b UndefHandler
SWIHandler:
b SWIHandler
PAbortHandler:
b PAbortHandler
DAbortHandler:
b DAbortHandler
IRQHandler:
b IRQHandler
FIQHandler:
b FIQHandler
.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler
.ltorg
/*** EOF ***/
|
wuxx/nanoDAP | 4,230 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s | /***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
/* Params:
* r0 = flash destination address, status
* r1 = longword count
* r2 = workarea start address
* r3 = workarea end address
*/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
/* r5 = rp
* r6 = wp, tmp
* r7 = tmp
*/
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldr r6, fstat /* Clear error flags */
mov r7, #48
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 0 */
mov r7, #0
strb r7, [r6]
ldr r6, fccobhi /* Program FLASH command */
mov r7, #6 /* FCCOBHI = 6 */
strb r7, [r6]
lsr r7, r0, #16 /* FCCOBLO = flash destination address >> 16 */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* Index for lower byte address bits[15:0] */
mov r7, #1
strb r7, [r6] /* FCCOBIX = 1*/
uxtb r7, r0 /* Memory address bits[15:0] */
ldr r6, fccoblo
strb r7, [r6] /* FCCOBLO = flash destination address */
lsr r7, r0, #8
ldr r6, fccobhi
strb r7, [r6] /* FCCOBHI = flash destination address >> 8 */
ldr r6, fccobix /* FCCOBIX = 2 */
mov r7, #2
strb r7, [r6]
ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5] /* FCCOBLO = rp */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 3 */
mov r7, #3
strb r7, [r6]
ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
ldr r6, fccoblo
strb r7, [r6]
sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
add r0, r0, #4 /* flash address += 4 */
add r5, r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc no_wrap
mov r5, r2
add r5, r5, #8
no_wrap:
cmp r1, #0 /* Done? */
beq execute
ldr r6, [r2, #0] /* read wp */
cmp r6, r5
beq execute /* execute if rp == wp */
ldr r6, fccobix /* FCCOBIX = 4 */
mov r7, #4
strb r7, [r6]
ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5] /* FCCOBLO = rp */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 5 */
mov r7, #5
strb r7, [r6]
ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
ldr r6, fccoblo
strb r7, [r6]
sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
add r0, r0, #4 /* flash address += 4 */
add r5, r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc execute
mov r5, r2
add r5, r5, #8
execute:
ldr r6, fstat /* Launch the command */
mov r7, #128
strb r7, [r6]
wait_busy:
ldr r6, fstat
ldrb r6, [r6] /* Wait until finished */
tst r6, r7
beq wait_busy
mov r7, #48 /* Check error */
tst r6, r7
bne error
mov r6, #0 /* Clear error */
str r5, [r2, #4] /* Store rp */
cmp r1, #0 /* Done? */
beq done
b wait_fifo
error:
mov r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
done:
mov r0, r6 /* Set result code */
bkpt #0
.align 2
fstat:
.word 0
fccobix:
.word 0
fccobhi:
.word 0
fccoblo:
.word 0
|
wuxx/nanoDAP | 1,584 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s | /***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
ldr r3, wdog_cs1
mov r2, #127
ldrb r5, [r3]
ldrb r4, [r3, #1]
and r2, r5
ldr r5, unlock1
ldrh r0, [r3, #4]
ldrh r1, [r3, #6]
strh r5, [r3, #2]
ldr r5, unlock2
strh r5, [r3, #2]
strb r4, [r3, #1]
strh r0, [r3, #4]
strh r1, [r3, #6]
strb r2, [r3]
bkpt #0
.align 2
wdog_cs1:
.word 0x40052000 // Watchdog Control and Status Register 1
unlock1:
.word 0x20C5 // 1st unlock word
unlock2:
.word 0x28D9 // 2nd unlock word
|
wuxx/nanoDAP | 13,426 | software/OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/debug/xscale/debug_handler.S | /***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "protocol.h"
.text
.align 4
@ Disable thumb mode
.code 32
@ send word to debugger
.macro m_send_to_debugger reg
1:
mrc p14, 0, r15, c14, c0, 0
bvs 1b
mcr p14, 0, \reg, c8, c0, 0
.endm
@ receive word from debugger
.macro m_receive_from_debugger reg
1:
mrc p14, 0, r15, c14, c0, 0
bpl 1b
mrc p14, 0, \reg, c9, c0, 0
.endm
@ save register on debugger, small
.macro m_small_save_reg reg
mov r0, \reg
bl send_to_debugger
.endm
@ save status register on debugger, small
.macro m_small_save_psr
mrs r0, spsr
bl send_to_debugger
.endm
@ wait for all outstanding coprocessor accesses to complete
.macro m_cpwait
mrc p15, 0, r0, c2, c0, 0
mov r0, r0
sub pc, pc, #4
.endm
.global reset_handler
.global undef_handler
.global swi_handler
.global prefetch_abort_handler
.global data_abort_handler
.global irq_handler
.global fiq_handler
.section .part1 , "ax"
reset_handler:
@ read DCSR
mrc p14, 0, r13, c10, c0
@ check if global enable bit (GE) is set
ands r13, r13, #0x80000000
bne debug_handler
@ set global enable bit (GE)
mov r13, #0xc0000000
mcr p14, 0, r13, c10, c0
debug_handler:
@ save r0 without modifying other registers
m_send_to_debugger r0
@ save lr (program PC) without branching (use macro)
m_send_to_debugger r14
@ save non-banked registers and spsr (program CPSR)
m_small_save_reg r1
m_small_save_reg r2
m_small_save_reg r3
m_small_save_reg r4
m_small_save_reg r5
m_small_save_reg r6
m_small_save_reg r7
m_small_save_psr
mrs r0, spsr
@ prepare program PSR for debug use (clear Thumb, set I/F to disable interrupts)
bic r0, r0, #PSR_T
orr r0, r0, #(PSR_I | PSR_F)
@ examine mode bits
and r1, r0, #MODE_MASK
cmp r1, #MODE_USR
bne not_user_mode
@ replace USR mode with SYS
bic r0, r0, #MODE_MASK
orr r0, r0, #MODE_SYS
not_user_mode:
b save_banked_registers
@ command loop
@ wait for command from debugger, than execute desired function
get_command:
bl receive_from_debugger
@ 0x0n - register access
cmp r0, #0x0
beq get_banked_registers
cmp r0, #0x1
beq set_banked_registers
@ 0x1n - read memory
cmp r0, #0x11
beq read_byte
cmp r0, #0x12
beq read_half_word
cmp r0, #0x14
beq read_word
@ 0x2n - write memory
cmp r0, #0x21
beq write_byte
cmp r0, #0x22
beq write_half_word
cmp r0, #0x24
beq write_word
@ 0x3n - program execution
cmp r0, #0x30
beq resume
cmp r0, #0x31
beq resume_w_trace
@ 0x4n - coprocessor access
cmp r0, #0x40
beq read_cp_reg
cmp r0, #0x41
beq write_cp_reg
@ 0x5n - cache and mmu functions
cmp r0, #0x50
beq clean_d_cache
cmp r0, #0x51
beq invalidate_d_cache
cmp r0, #0x52
beq invalidate_i_cache
cmp r0, #0x53
beq cpwait
@ 0x6n - misc functions
cmp r0, #0x60
beq clear_sa
cmp r0, #0x61
beq read_trace_buffer
cmp r0, #0x62
beq clean_trace_buffer
@ return (back to get_command)
b get_command
@ ----
@ resume program execution
resume:
@ restore CPSR (SPSR_dbg)
bl receive_from_debugger
msr spsr, r0
@ restore registers (r7 - r0)
bl receive_from_debugger @ r7
mov r7, r0
bl receive_from_debugger @ r6
mov r6, r0
bl receive_from_debugger @ r5
mov r5, r0
bl receive_from_debugger @ r4
mov r4, r0
bl receive_from_debugger @ r3
mov r3, r0
bl receive_from_debugger @ r2
mov r2, r0
bl receive_from_debugger @ r1
mov r1, r0
bl receive_from_debugger @ r0
@ resume addresss
m_receive_from_debugger lr
@ branch back to application code, restoring CPSR
subs pc, lr, #0
@ get banked registers
@ receive mode bits from host, then run into save_banked_registers to
get_banked_registers:
bl receive_from_debugger
@ save banked registers
@ r0[4:0]: desired mode bits
save_banked_registers:
@ backup CPSR
mrs r7, cpsr
msr cpsr_c, r0
nop
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ backup banked registers
m_send_to_debugger r8
m_send_to_debugger r9
m_send_to_debugger r10
m_send_to_debugger r11
m_send_to_debugger r12
m_send_to_debugger r13
m_send_to_debugger r14
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_save
@ backup SPSR
mrs r0, spsr
m_send_to_debugger r0
no_spsr_to_save:
@ restore CPSR for SDS
msr cpsr_c, r7
nop
@ return
b get_command
@ ----
@ set banked registers
@ receive mode bits from host, then run into save_banked_registers to
set_banked_registers:
bl receive_from_debugger
@ restore banked registers
@ r0[4:0]: desired mode bits
restore_banked_registers:
@ backup CPSR
mrs r7, cpsr
msr cpsr_c, r0
nop
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ set banked registers
m_receive_from_debugger r8
m_receive_from_debugger r9
m_receive_from_debugger r10
m_receive_from_debugger r11
m_receive_from_debugger r12
m_receive_from_debugger r13
m_receive_from_debugger r14
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_restore
@ set SPSR
m_receive_from_debugger r0
msr spsr, r0
no_spsr_to_restore:
@ restore CPSR for SDS
msr cpsr_c, r7
nop
@ return
b get_command
@ ----
read_byte:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
rb_loop:
ldrb r0, [r2], #1
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
bl send_to_debugger
subs r1, r1, #1
bne rb_loop
@ return
b get_command
@ ----
read_half_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
rh_loop:
ldrh r0, [r2], #2
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
bl send_to_debugger
subs r1, r1, #1
bne rh_loop
@ return
b get_command
@ ----
read_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
rw_loop:
ldr r0, [r2], #4
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
bl send_to_debugger
subs r1, r1, #1
bne rw_loop
@ return
b get_command
@ ----
write_byte:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
wb_loop:
bl receive_from_debugger
strb r0, [r2], #1
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne wb_loop
@ return
b get_command
@ ----
write_half_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
wh_loop:
bl receive_from_debugger
strh r0, [r2], #2
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne wh_loop
@ return
b get_command
@ ----
write_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
ww_loop:
bl receive_from_debugger
str r0, [r2], #4
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne ww_loop
@ return
b get_command
@ ----
clear_sa:
@ read DCSR
mrc p14, 0, r0, c10, c0
@ clear SA bit
bic r0, r0, #0x20
@ write DCSR
mcr p14, 0, r0, c10, c0
@ return
b get_command
@ ----
clean_d_cache:
@ r0: cache clean area
bl receive_from_debugger
mov r1, #1024
clean_loop:
mcr p15, 0, r0, c7, c2, 5
add r0, r0, #32
subs r1, r1, #1
bne clean_loop
@ return
b get_command
@ ----
invalidate_d_cache:
mcr p15, 0, r0, c7, c6, 0
@ return
b get_command
@ ----
invalidate_i_cache:
mcr p15, 0, r0, c7, c5, 0
@ return
b get_command
@ ----
cpwait:
m_cpwait
@return
b get_command
@ ----
.section .part2 , "ax"
read_cp_reg:
@ requested cp register
bl receive_from_debugger
adr r1, read_cp_table
add pc, r1, r0, lsl #3
read_cp_table:
mrc p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID
b read_cp_reg_reply
mrc p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE
b read_cp_reg_reply
mrc p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL
b read_cp_reg_reply
mrc p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL
b read_cp_reg_reply
mrc p15, 0, r0, c2, c0, 0 @ XSCALE_TTB
b read_cp_reg_reply
mrc p15, 0, r0, c3, c0, 0 @ XSCALE_DAC
b read_cp_reg_reply
mrc p15, 0, r0, c5, c0, 0 @ XSCALE_FSR
b read_cp_reg_reply
mrc p15, 0, r0, c6, c0, 0 @ XSCALE_FAR
b read_cp_reg_reply
mrc p15, 0, r0, c13, c0, 0 @ XSCALE_PID
b read_cp_reg_reply
mrc p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS
b read_cp_reg_reply
mrc p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0
b read_cp_reg_reply
mrc p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1
b read_cp_reg_reply
mrc p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0
b read_cp_reg_reply
mrc p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1
b read_cp_reg_reply
mrc p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON
b read_cp_reg_reply
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
b read_cp_reg_reply
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0
b read_cp_reg_reply
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1
b read_cp_reg_reply
mrc p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR
b read_cp_reg_reply
read_cp_reg_reply:
bl send_to_debugger
@ return
b get_command
@ ----
write_cp_reg:
@ requested cp register
bl receive_from_debugger
mov r1, r0
@ value to be written
bl receive_from_debugger
adr r2, write_cp_table
add pc, r2, r1, lsl #3
write_cp_table:
mcr p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID (0x0)
b get_command
mcr p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE (0x1)
b get_command
mcr p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL (0x2)
b get_command
mcr p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL (0x3)
b get_command
mcr p15, 0, r0, c2, c0, 0 @ XSCALE_TTB (0x4)
b get_command
mcr p15, 0, r0, c3, c0, 0 @ XSCALE_DAC (0x5)
b get_command
mcr p15, 0, r0, c5, c0, 0 @ XSCALE_FSR (0x6)
b get_command
mcr p15, 0, r0, c6, c0, 0 @ XSCALE_FAR (0x7)
b get_command
mcr p15, 0, r0, c13, c0, 0 @ XSCALE_PID (0x8)
b get_command
mcr p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS (0x9)
b get_command
mcr p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0 (0xa)
b get_command
mcr p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1 (0xb)
b get_command
mcr p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0 (0xc)
b get_command
mcr p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1 (0xd)
b get_command
mcr p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON (0xe)
b get_command
mcr p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG (0xf)
b get_command
mcr p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
b get_command
mcr p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
b get_command
mcr p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR (0x12)
b get_command
@ ----
read_trace_buffer:
@ dump 256 entries from trace buffer
mov r1, #256
read_tb_loop:
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
bl send_to_debugger
subs r1, r1, #1
bne read_tb_loop
@ dump checkpoint register 0
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
bl send_to_debugger
@ dump checkpoint register 1
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
bl send_to_debugger
@ return
b get_command
@ ----
clean_trace_buffer:
@ clean 256 entries from trace buffer
mov r1, #256
clean_tb_loop:
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
subs r1, r1, #1
bne clean_tb_loop
@ return
b get_command
@ ----
@ resume program execution with trace buffer enabled
resume_w_trace:
@ restore CPSR (SPSR_dbg)
bl receive_from_debugger
msr spsr, r0
@ restore registers (r7 - r0)
bl receive_from_debugger @ r7
mov r7, r0
bl receive_from_debugger @ r6
mov r6, r0
bl receive_from_debugger @ r5
mov r5, r0
bl receive_from_debugger @ r4
mov r4, r0
bl receive_from_debugger @ r3
mov r3, r0
bl receive_from_debugger @ r2
mov r2, r0
bl receive_from_debugger @ r1
mov r1, r0
bl receive_from_debugger @ r0
@ resume addresss
m_receive_from_debugger lr
mrc p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
orr r13, r13, #1
mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
@ branch back to application code, restoring CPSR
subs pc, lr, #0
undef_handler:
swi_handler:
prefetch_abort_handler:
data_abort_handler:
irq_handler:
fiq_handler:
1:
b 1b
send_to_debugger:
m_send_to_debugger r0
mov pc, lr
receive_from_debugger:
m_receive_from_debugger r0
mov pc, lr
|
wware/stuff | 14,907 | arm-hacks/sam7/common/flash-crt.s | /* ****************************************************************************************************** */
/* crt.s */
/* */
/* Assembly Language Startup Code for Atmel AT91SAM7S256 */
/* */
/* */
/* */
/* */
/* Author: James P Lynch May 12, 2007 */
/* ****************************************************************************************************** */
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000010 /* stack for "undefined instruction" interrupts is 16 bytes */
.set ABT_STACK_SIZE, 0x00000010 /* stack for "abort" interrupts is 16 bytes */
.set FIQ_STACK_SIZE, 0x00000080 /* stack for "FIQ" interrupts is 128 bytes */
.set IRQ_STACK_SIZE, 0X00000080 /* stack for "IRQ" normal interrupts is 128 bytes */
.set SVC_STACK_SIZE, 0x00000080 /* stack for "SVC" supervisor mode is 128 bytes */
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs (program status registers) */
.set ARM_MODE_USR, 0x10 /* Normal User Mode */
.set ARM_MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
.set ARM_MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
.set ARM_MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
.set ARM_MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
.set ARM_MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
.set ARM_MODE_SYS, 0x1F /* System Running Priviledged Operating System Tasks Mode */
.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled (program status registers) */
.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled (program status registers) */
/* Addresses and offsets of AIC */
.set AT91C_BASE_AIC, 0xFFFFF000 /* (AIC) Base Address */
.set AT91C_AIC_IVR, 0xFFFFF100 /* (AIC) IRQ Interrupt Vector Register */
.set AT91C_AIC_FVR, 0xFFFFF104 /* (AIC) FIQ Interrupt Vector Register */
.set AIC_IVR, 256 /* IRQ Vector Register offset from base above */
.set AIC_FVR, 260 /* FIQ Vector Register offset from base above */
.set AIC_EOICR, 304 /* End of Interrupt Command Register */
/* Addresses and offsets of PIO */
.set AT91C_PIOA_PER, 0xFFFFF400 /* PIO Enable Register */
.set AT91C_PIOA_PDR, 0xFFFFF404 /* PIO Disable Register */
.set AT91C_PIOA_PSR, 0xFFFFF408 /* PIO Status Register */
.set AT91C_PIOA_OER, 0xFFFFF410 /* PIO Output Enable Register */
.set AT91C_PIOA_ODR, 0xFFFFF414 /* PIO Output Disable Register */
.set AT91C_PIOA_OSR, 0xFFFFF418 /* PIO Output Status Register */
.set AT91C_PIOA_IFER, 0xFFFFF420 /* PIO Input Filter Enable Register */
.set AT91C_PIOA_IFDR, 0xFFFFF424 /* PIO Input Filter Disable Register */
.set AT91C_PIOA_IFSR, 0xFFFFF428 /* PIO Input Filter Status Register */
.set AT91C_PIOA_SODR, 0xFFFFF430 /* PIO Set Output Data Register */
.set AT91C_PIOA_CODR, 0xFFFFF434 /* PIO Clear Output Data Register */
.set AT91C_PIOA_ODSR, 0xFFFFF438 /* PIO Output Data Status Register */
.set AT91C_PIOA_PDSR, 0xFFFFF43C /* PIO Pin Data Status Register */
.set AT91C_PIOA_IER, 0xFFFFF440 /* PIO Interrupt Enable Register */
.set AT91C_PIOA_IDR, 0xFFFFF444 /* PIO Interrupt Disable Register */
.set AT91C_PIOA_IMR, 0xFFFFF448 /* PIO Interrupt Status Register */
.set AT91C_PIOA_ISR, 0xFFFFF44C /* PIO Interrupt Status Register */
.set AT91C_PIOA_MDER, 0xFFFFF450 /* PIO Multi-driver Enable Register */
.set AT91C_PIOA_MDDR, 0xFFFFF454 /* PIO Multi-driver Disable Register */
.set AT91C_PIOA_MDSR, 0xFFFFF458 /* PIO Multi-driver Status Register */
.set AT91C_PIOA_PPUDR, 0xFFFFF460 /* PIO Pull-up Disable Register */
.set AT91C_PIOA_PPUER, 0xFFFFF464 /* PIO Pull-up Enable Register */
.set AT91C_PIOA_PPUSR, 0xFFFFF468 /* PIO Pull-up Status Register */
/* identify all GLOBAL symbols */
.global _vec_reset
.global _vec_undef
.global _vec_swi
.global _vec_pabt
.global _vec_dabt
.global _vec_rsv
.global _vec_irq
.global _vec_fiq
.global AT91F_Irq_Handler
.global AT91F_Fiq_Handler
.global AT91F_Default_FIQ_handler
.global AT91F_Default_IRQ_handler
.global AT91F_Spurious_handler
.global AT91F_Dabt_Handler
.global AT91F_Pabt_Handler
.global AT91F_Undef_Handler
/* GNU assembler controls */
.text /* all assembler code that follows will go into .text section */
.arm /* compile for 32-bit ARM instruction set */
.align /* align section on 32-bit boundary */
/* ============================================================ */
/* VECTOR TABLE */
/* */
/* Must be located in FLASH at address 0x00000000 */
/* */
/* Easy to do if this file crt.s is first in the list */
/* for the linker step in the makefile, e.g. */
/* */
/* $(LD) $(LFLAGS) -o main.out crt.o main.o */
/* */
/* ============================================================ */
_vec_reset: b _init_reset /* RESET vector - must be at 0x00000000 */
_vec_undef: b AT91F_Undef_Handler /* Undefined Instruction vector */
_vec_swi: b _vec_swi /* Software Interrupt vector */
_vec_pabt: b AT91F_Pabt_Handler /* Prefetch abort vector */
_vec_dabt: b AT91F_Dabt_Handler /* Data abort vector */
_vec_rsv: nop /* Reserved vector */
_vec_irq: b AT91F_Irq_Handler /* Interrupt Request (IRQ) vector */
_vec_fiq: /* Fast interrupt request (FIQ) vector */
/* ==================================================================== */
/* Function: AT91F_Fiq_Handler */
/* */
/* The FIQ interrupt asserts when switch SW1 is pressed. */
/* */
/* This simple FIQ handler turns on LED3 (Port PA2). The LED3 will be */
/* turned off by the background loop in main() thus giving a visual */
/* indication that the interrupt has occurred. */
/* */
/* This FIQ_Handler supports non-nested FIQ interrupts (a FIQ interrupt */
/* cannot itself be interrupted). */
/* */
/* The Fast Interrupt Vector Register (AIC_FVR) is read to clear the */
/* interrupt. */
/* */
/* A global variable FiqCount is also incremented. */
/* */
/* Remember that switch SW1 is not debounced, so the FIQ interrupt may */
/* occur more than once for a single button push. */
/* */
/* Programmer: James P Lynch */
/* ==================================================================== */
AT91F_Fiq_Handler:
/* Adjust LR_irq */
sub lr, lr, #4
/* Read the AIC Fast Interrupt Vector register to clear the interrupt */
ldr r12, =AT91C_AIC_FVR
ldr r11, [r12]
/* Turn on LED3 (write 0x0008 to PIOA_CODR at 0xFFFFF434) */
ldr r12, =AT91C_PIOA_CODR
mov r11, #0x04
str r11, [r12]
/* Increment the _FiqCount variable */
/*
ldr r12, =FiqCount
ldr r11, [r12]
add r11, r11, #1
str r11, [r12]
*/
/* Return from Fiq interrupt */
movs pc, lr
/* ==================================================================================== */
/* _init_reset Handler */
/* */
/* RESET vector 0x00000000 branches to here. */
/* */
/* ARM microprocessor begins execution after RESET at address 0x00000000 */
/* in Supervisor mode with interrupts disabled! */
/* */
/* _init_reset handler: creates a stack for each ARM mode. */
/* sets up a stack pointer for each ARM mode. */
/* turns off interrupts in each mode. */
/* leaves CPU in SYS (System) mode. */
/* */
/* block copies the initializers to .data section */
/* clears the .bss section to zero */
/* */
/* branches to main( ) */
/* ==================================================================================== */
.text /* all assembler code that follows will go into .text section */
.align /* align section on 32-bit boundary */
.global _init_reset
_init_reset:
/* Setup a stack for each mode with interrupts initially disabled. */
ldr r0, =_stack_end /* r0 = top-of-stack */
msr CPSR_c, #ARM_MODE_UND|I_BIT|F_BIT /* switch to Undefined Instruction Mode */
mov sp, r0 /* set stack pointer for UND mode */
sub r0, r0, #UND_STACK_SIZE /* adjust r0 past UND stack */
msr CPSR_c, #ARM_MODE_ABT|I_BIT|F_BIT /* switch to Abort Mode */
mov sp, r0 /* set stack pointer for ABT mode */
sub r0, r0, #ABT_STACK_SIZE /* adjust r0 past ABT stack */
msr CPSR_c, #ARM_MODE_FIQ|I_BIT|F_BIT /* switch to FIQ Mode */
mov sp, r0 /* set stack pointer for FIQ mode */
sub r0, r0, #FIQ_STACK_SIZE /* adjust r0 past FIQ stack */
msr CPSR_c, #ARM_MODE_IRQ|I_BIT|F_BIT /* switch to IRQ Mode */
mov sp, r0 /* set stack pointer for IRQ mode */
sub r0, r0, #IRQ_STACK_SIZE /* adjust r0 past IRQ stack */
msr CPSR_c, #ARM_MODE_SVC|I_BIT|F_BIT /* switch to Supervisor Mode */
mov sp, r0 /* set stack pointer for SVC mode */
sub r0, r0, #SVC_STACK_SIZE /* adjust r0 past SVC stack */
msr CPSR_c, #ARM_MODE_SYS|I_BIT|F_BIT /* switch to System Mode */
mov sp, r0 /* set stack pointer for SYS mode */
/* Start execution in SYSTEM mode. This is exactly like USER mode */
/* (same stack) but SYSTEM mode has more privileges. */
/* copy initialized variables .data section (Copy from ROM to RAM) */
ldr R1, =_etext
ldr R2, =_data
ldr R3, =_edata
1: cmp R2, R3
ldrlo R0, [R1], #4
strlo R0, [R2], #4
blo 1b
/* Clear uninitialized variables .bss section (Zero init) */
mov R0, #0
ldr R1, =_bss_start
ldr R2, =_bss_end
2: cmp R1, R2
strlo R0, [R1], #4
blo 2b
/* Enter the C code */
b main
/* ============================================================================ */
/* Function: AT91F_Irq_Handler */
/* */
/* This IRQ_Handler supports nested interrupts (an IRQ interrupt can itself */
/* be interrupted). */
/* */
/* This handler re-enables interrupts and switches to "Supervisor" mode to */
/* prevent any corruption to the link and IP registers. */
/* */
/* The Interrupt Vector Register (AIC_IVR) is read to determine the address */
/* of the required interrupt service routine. The ISR routine can be a */
/* standard C function since this handler minds all the save/restore */
/* protocols. */
/* */
/* */
/* Programmers: */
/*------------------------------------------------------------------------------*/
/* ATMEL Microcontroller Software Support - ROUSSET - */
/*------------------------------------------------------------------------------*/
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS */
/* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
/* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND */
/* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR */
/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */
/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT */
/* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */
/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* File source : Cstartup.s79 */
/* Object : Generic CStartup to AT91SAM7S256 */
/* 1.0 09/May/06 JPP : Creation */
/* */
/* */
/* Note: taken from Atmel web site (www.at91.com) */
/* Keil example project: AT91SAM7S-Interrupt_SAM7S */
/* ============================================================================ */
AT91F_Irq_Handler:
/* Manage Exception Entry */
/* Adjust and save LR_irq in IRQ stack */
sub lr, lr, #4
stmfd sp!, {lr}
/* Save r0 and SPSR (need to be saved for nested interrupt) */
mrs r14, SPSR
stmfd sp!, {r0,r14}
/* Write in the IVR to support Protect Mode */
/* No effect in Normal Mode */
/* De-assert the NIRQ and clear the source in Protect Mode */
ldr r14, =AT91C_BASE_AIC
ldr r0 , [r14, #AIC_IVR]
str r14, [r14, #AIC_IVR]
/* Enable Interrupt and Switch in Supervisor Mode */
msr CPSR_c, #ARM_MODE_SVC
/* Save scratch/used registers and LR in User Stack */
stmfd sp!, { r1-r3, r12, r14}
/* Branch to the routine pointed by the AIC_IVR */
mov r14, pc
bx r0
/* Manage Exception Exit */
/* Restore scratch/used registers and LR from User Stack */
ldmia sp!, { r1-r3, r12, r14}
/* Disable Interrupt and switch back in IRQ mode */
msr CPSR_c, #I_BIT | ARM_MODE_IRQ
/* Mark the End of Interrupt on the AIC */
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_EOICR]
/* Restore SPSR_irq and r0 from IRQ stack */
ldmia sp!, {r0,r14}
msr SPSR_cxsf, r14
/* Restore adjusted LR_irq from IRQ stack directly in the PC */
ldmia sp!, {pc}^
/*
* What makes sense with these abort handlers and other troubles is to do five
* sets of flashes. The first set shows which trouble it is. The next four are
* the four low hex digits of the location where the trouble happened. Maybe
* that should be six hex digits? And they should be done like Morse code, so
* a 7 is short-long-long-long and a C is long-long-short-short.
*
* How do I get that address? It would be in the link register, right? In fact
* the link register is 8 bytes ahead of the address where the problem occurred
* so subtract 8 first, then pass it into a function that does the blinking.
*/
/* ============================================================================ */
/* Function: AT91F_Dabt_Handler */
/* */
/* Entered on Data Abort exception. */
/* Enters blink routine (3 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* ============================================================================ */
AT91F_Dabt_Handler:
mov R0, #3
mov R1, lr
b blink_number
/* ============================================================================ */
/* Function: AT91F_Pabt_Handler */
/* */
/* Entered on Prefetch Abort exception. */
/* Enters blink routine (2 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* ============================================================================ */
AT91F_Pabt_Handler:
mov R0, #2
mov R1, lr
b blink_number
/* ============================================================================ */
/* Function: AT91F_Undef_Handler */
/* */
/* Entered on Undefined Instruction exception. */
/* Enters blink routine (1 blinks followed by a pause) */
/* processor hangs in the blink loop forever */
/* */
/* ============================================================================ */
AT91F_Undef_Handler:
mov R0, #1
mov R1, lr
b blink_number
AT91F_Default_FIQ_handler:
mov pc, lr
AT91F_Default_IRQ_handler:
mov pc, lr
AT91F_Spurious_handler:
mov pc, lr
.end
|
wware/stuff | 14,780 | arm-hacks/sam7/interrupt-hacks/startup_SAM7S.S | /***********************************************************************/
/* */
/* startup_SAM7S.S: Startup file for Atmel AT91SAM7S device series */
/* */
/***********************************************************************/
/* ported to arm-elf-gcc / WinARM by Martin Thomas, KL, .de */
/* <eversmith@heizung-thomas.de> */
/* modifications Copyright Martin Thomas 2005 */
/* */
/* Based on file that has been a part of the uVision/ARM development */
/* tools, Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
/***********************************************************************/
/*
Modifications by Martin Thomas:
- added handling of execption vectors in RAM ("ramfunc")
- added options to remap the interrupt vectors to RAM
(see makefile for switch-option)
- replaced all ";" and "#" for comments with // of / * * /
- added C++ ctor handling
*/
// mt: this file should not be used with the Configuration Wizard
// since a lot of changes have been done for the WinARM/gcc example
/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
// *** Startup Code (executed after Reset) ***
// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
// Internal Memory Base Addresses
.equ FLASH_BASE, 0x00100000
.equ RAM_BASE, 0x00200000
/*
// <h> Stack Configuration
// <o> Top of Stack Address <0x0-0xFFFFFFFF:4>
// <h> Stack Sizes (in Bytes)
// <o1> Undefined Mode <0x0-0xFFFFFFFF:4>
// <o2> Supervisor Mode <0x0-0xFFFFFFFF:4>
// <o3> Abort Mode <0x0-0xFFFFFFFF:4>
// <o4> Fast Interrupt Mode <0x0-0xFFFFFFFF:4>
// <o5> Interrupt Mode <0x0-0xFFFFFFFF:4>
// <o6> User/System Mode <0x0-0xFFFFFFFF:4>
// </h>
// </h>
*/
.equ Top_Stack, 0x00204000
.equ UND_Stack_Size, 0x00000004
.equ SVC_Stack_Size, 0x00000100
.equ ABT_Stack_Size, 0x00000004
.equ FIQ_Stack_Size, 0x00000004
.equ IRQ_Stack_Size, 0x00000100
.equ USR_Stack_Size, 0x00000400
// Embedded Flash Controller (EFC) definitions
.equ EFC_BASE, 0xFFFFFF00 /* EFC Base Address */
.equ EFC_FMR, 0x60 /* EFC_FMR Offset */
/*
// <e> Embedded Flash Controller (EFC)
// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
// <i> Number of Master Clock Cycles in 1us
// <o1.8..9> FWS: Flash Wait State
// <0=> Read: 1 cycle / Write: 2 cycles
// <1=> Read: 2 cycle / Write: 3 cycles
// <2=> Read: 3 cycle / Write: 4 cycles
// <3=> Read: 4 cycle / Write: 4 cycles
// </e>
*/
.equ EFC_SETUP, 1
.equ EFC_FMR_Val, 0x00320100
// Watchdog Timer (WDT) definitions
.equ WDT_BASE, 0xFFFFFD40 /* WDT Base Address */
.equ WDT_MR, 0x04 /* WDT_MR Offset */
/*
// <e> Watchdog Timer (WDT)
// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable
// <o1.13> WDRSTEN: Watchdog Reset Enable
// <o1.14> WDRPROC: Watchdog Reset Processor
// <o1.28> WDDBGHLT: Watchdog Debug Halt
// <o1.29> WDIDLEHLT: Watchdog Idle Halt
// <o1.15> WDDIS: Watchdog Disable
// </e>
*/
.equ WDT_SETUP, 1
.equ WDT_MR_Val, 0x00008000
// Power Mangement Controller (PMC) definitions
.equ PMC_BASE, 0xFFFFFC00 /* PMC Base Address */
.equ PMC_MOR, 0x20 /* PMC_MOR Offset */
.equ PMC_MCFR, 0x24 /* PMC_MCFR Offset */
.equ PMC_PLLR, 0x2C /* PMC_PLLR Offset */
.equ PMC_MCKR, 0x30 /* PMC_MCKR Offset */
.equ PMC_SR, 0x68 /* PMC_SR Offset */
.equ PMC_MOSCEN, (1<<0) /* Main Oscillator Enable */
.equ PMC_OSCBYPASS, (1<<1) /* Main Oscillator Bypass */
.equ PMC_OSCOUNT, (0xFF<<8) /* Main OScillator Start-up Time */
.equ PMC_DIV, (0xFF<<0) /* PLL Divider */
.equ PMC_PLLCOUNT, (0x3F<<8) /* PLL Lock Counter */
.equ PMC_OUT, (0x03<<14) /* PLL Clock Frequency Range */
.equ PMC_MUL, (0x7FF<<16) /* PLL Multiplier */
.equ PMC_USBDIV, (0x03<<28) /* USB Clock Divider */
.equ PMC_CSS, (3<<0) /* Clock Source Selection */
.equ PMC_PRES, (7<<2) /* Prescaler Selection */
.equ PMC_MOSCS, (1<<0) /* Main Oscillator Stable */
.equ PMC_LOCK, (1<<2) /* PLL Lock Status */
/*
// <e> Power Mangement Controller (PMC)
// <h> Main Oscillator
// <o1.0> MOSCEN: Main Oscillator Enable
// <o1.1> OSCBYPASS: Oscillator Bypass
// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255>
// </h>
// <h> Phase Locked Loop (PLL)
// <o2.0..7> DIV: PLL Divider <0-255>
// <o2.16..26> MUL: PLL Multiplier <0-2047>
// <i> PLL Output is multiplied by MUL+1
// <o2.14..15> OUT: PLL Clock Frequency Range
// <0=> 80..160MHz <1=> Reserved
// <2=> 150..220MHz <3=> Reserved
// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
// <o2.28..29> USBDIV: USB Clock Divider
// <0=> None <1=> 2 <2=> 4 <3=> Reserved
// </h>
// <o3.0..1> CSS: Clock Source Selection
// <0=> Slow Clock
// <1=> Main Clock
// <2=> Reserved
// <3=> PLL Clock
// <o3.2..4> PRES: Prescaler
// <0=> None
// <1=> Clock / 2 <2=> Clock / 4
// <3=> Clock / 8 <4=> Clock / 16
// <5=> Clock / 32 <6=> Clock / 64
// <7=> Reserved
// </e>
*/
/*
* Note the values of PMC_PLLR_Val (0x00191C05) and PMC_MCKR_VAL
* (0x07), and look at datasheet sections 24.4 and 25.7. Breaking
* down the two registers into bit fields we have:
* 25.7 step 3 => DIV = 0x05
* OUT = 0x00
* MUL = 0x19
* PLLCOUNT = 0x1C
* and looking at diagram 24-3 we get PLLCK = 95.8464 MHz, then
* 25.7 step 4 => PRES = 0x01
* CSS = 0x00
* and looking at diagram 25-1 we get MCK = PLLCK/2 = 47.9232 MHz
* or pretty close to 48 MHz.
*/
.equ PMC_SETUP, 1
.equ PMC_MOR_Val, 0x00000601
/*
* PLLIN = 18.432 MHz (crystal)
* MUL = 0x19 = 25, DIV = 0x05
* PLLCK = ((MUL + 1) / DIV) * PLLIN = 95.8464 MHz
*/
.equ PMC_PLLR_Val, 0x00191C05
/*
* CS = 0b11 -> select PLLCK to drive MCK
* PRES = 0x001 -> divide by 2 -> MCK = 47.9232 MHz
*/
.equ PMC_MCKR_Val, 0x00000007
#ifdef VECTORS_IN_RAM
/*
Exception Vectors to be placed in RAM - added by mt
-> will be used after remapping
Mapped to Address 0 after remapping.
Absolute addressing mode must be used.
Dummy Handlers are implemented as infinite loops which can be modified.
VECTORS_IN_RAM defined in makefile/by commandline
*/
.text
.arm
.section .vectram, "ax"
VectorsRAM: LDR PC,Reset_AddrR
LDR PC,Undef_AddrR
LDR PC,SWI_AddrR
LDR PC,PAbt_AddrR
LDR PC,DAbt_AddrR
NOP /* Reserved Vector */
LDR PC,[PC,#-0xF20] /* Vector From AIC_IVR */
LDR PC,[PC,#-0xF20] /* Vector From AIC_FVR */
Reset_AddrR: .word Reset_Handler
Undef_AddrR: .word Undef_HandlerR
SWI_AddrR: .word SWI_HandlerR
PAbt_AddrR: .word PAbt_HandlerR
DAbt_AddrR: .word DAbt_HandlerR
// .word 0xdeadbeef /* Test Reserved Address */
.word 0 /* Reserved Address */
IRQ_AddrR: .word IRQ_HandlerR
FIQ_AddrR: .word FIQ_HandlerR
Undef_HandlerR: B Undef_HandlerR
SWI_HandlerR: B SWI_HandlerR
PAbt_HandlerR: B PAbt_HandlerR
DAbt_HandlerR: B DAbt_HandlerR
IRQ_HandlerR: B IRQ_HandlerR
FIQ_HandlerR: B FIQ_HandlerR
#endif /* VECTORS_IN_RAM */
/*
Exception Vectors in ROM
-> will be used during startup if remapping is done
-> will be used "always" in code without remapping
Mapped to Address 0.
Absolute addressing mode must be used.
Dummy Handlers are implemented as infinite loops which can be modified.
*/
.text
.arm
.section .vectrom, "ax"
Vectors: LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP /* Reserved Vector */
// LDR PC,IRQ_Addr
LDR PC,[PC,#-0xF20] /* Vector From AIC_IVR */
// LDR PC,FIQ_Addr
LDR PC,[PC,#-0xF20] /* Vector From AIC_FVR */
Reset_Addr: .word Reset_Handler
Undef_Addr: .word Undef_Handler
SWI_Addr: .word SWI_Handler
PAbt_Addr: .word PAbt_Handler
DAbt_Addr: .word DAbt_Handler
.word 0 /* Reserved Address */
IRQ_Addr: .word IRQ_Handler
FIQ_Addr: .word FIQ_Handler
Undef_Handler: B Undef_Handler
SWI_Handler: B SWI_Handler
PAbt_Handler: B PAbt_Handler
DAbt_Handler: B DAbt_Handler
IRQ_Handler: B IRQ_Handler
FIQ_Handler: B FIQ_Handler
// Starupt Code must be linked first at Address at which it expects to run.
.text
.arm
.section .init, "ax"
.global _startup
.func _startup
_startup:
// Reset Handler
LDR pc, =Reset_Handler
Reset_Handler:
// Setup EFC
.if EFC_SETUP
LDR R0, =EFC_BASE
LDR R1, =EFC_FMR_Val
STR R1, [R0, #EFC_FMR]
.endif
// Setup WDT
.if WDT_SETUP
LDR R0, =WDT_BASE
LDR R1, =WDT_MR_Val
STR R1, [R0, #WDT_MR]
.endif
// Setup PMC
.if PMC_SETUP
LDR R0, =PMC_BASE
// Setup Main Oscillator
LDR R1, =PMC_MOR_Val
STR R1, [R0, #PMC_MOR]
// Wait until Main Oscillator is stablilized
.if (PMC_MOR_Val & PMC_MOSCEN)
MOSCS_Loop: LDR R2, [R0, #PMC_SR]
ANDS R2, R2, #PMC_MOSCS
BEQ MOSCS_Loop
.endif
// Setup the PLL
.if (PMC_PLLR_Val & PMC_MUL)
LDR R1, =PMC_PLLR_Val
STR R1, [R0, #PMC_PLLR]
// Wait until PLL is stabilized
PLL_Loop: LDR R2, [R0, #PMC_SR]
ANDS R2, R2, #PMC_LOCK
BEQ PLL_Loop
.endif
// Select Clock
LDR R1, =PMC_MCKR_Val
STR R1, [R0, #PMC_MCKR]
.endif
// Setup Stack for each mode
LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
// Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
// Setup a default Stack Limit (when compiled with "-mapcs-stack-check")
SUB SL, SP, #USR_Stack_Size
// Relocate .data section (Copy from ROM to RAM)
LDR R1, =_etext
LDR R2, =_data
LDR R3, =_edata
LoopRel: CMP R2, R3
LDRLO R0, [R1], #4
STRLO R0, [R2], #4
BLO LoopRel
// Clear .bss section (Zero init)
MOV R0, #0
LDR R1, =__bss_start__
LDR R2, =__bss_end__
LoopZI: CMP R1, R2
STRLO R0, [R1], #4
BLO LoopZI
#ifdef VECTORS_IN_RAM
/*
remap - exception vectors for RAM have been already copied
to 0x00200000 by the .data copy-loop
*/
.equ MC_BASE,0xFFFFFF00 /* MC Base Address */
.equ MC_RCR, 0x00 /* MC_RCR Offset */
LDR R0, =MC_BASE
MOV R1, #1
STR R1, [R0, #MC_RCR] // Remap
#endif /* VECTORS_IN_RAM */
/*
Call C++ constructors (for objects in "global scope")
added by Martin Thomas based on a Anglia Design
example-application for STR7 ARM
*/
LDR r0, =__ctors_start__
LDR r1, =__ctors_end__
ctor_loop:
CMP r0, r1
BEQ ctor_end
LDR r2, [r0], #4 /* this ctor's address */
STMFD sp!, {r0-r1} /* save loop counters */
MOV lr, pc /* set return address */
// MOV pc, r2
BX r2 /* call ctor */
LDMFD sp!, {r0-r1} /* restore loop counters */
B ctor_loop
ctor_end:
// Enter the C code
mov r0,#0 // no arguments (argc = 0)
mov r1,r0
mov r2,r0
mov fp,r0 // null frame pointer
mov r7,r0 // null frame pointer for thumb
ldr r10,=main
adr lr, __main_exit
bx r10 // enter main()
__main_exit: B __main_exit
.size _startup, . - _startup
.endfunc
.end
|
wware/stuff | 14,006 | arm-hacks/sam7/Examples/at91sam7s64_Hello/startup_SAM7S.S | /***********************************************************************/
/* */
/* startup_SAM7S.S: Startup file for Atmel AT91SAM7S device series */
/* */
/***********************************************************************/
/* ported to arm-elf-gcc / WinARM by Martin Thomas, KL, .de */
/* <eversmith@heizung-thomas.de> */
/* modifications Copyright Martin Thomas 2005 */
/* */
/* Based on file that has been a part of the uVision/ARM development */
/* tools, Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
/***********************************************************************/
/*
Modifications by Martin Thomas:
- added handling of execption vectors in RAM ("ramfunc")
- added options to remap the interrupt vectors to RAM
(see makefile for switch-option)
- replaced all ";" and "#" for comments with // of / * * /
- added C++ ctor handling
*/
// mt: this file should not be used with the Configuration Wizard
// since a lot of changes have been done for the WinARM/gcc example
/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
// *** Startup Code (executed after Reset) ***
// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
// Internal Memory Base Addresses
.equ FLASH_BASE, 0x00100000
.equ RAM_BASE, 0x00200000
/*
// <h> Stack Configuration
// <o> Top of Stack Address <0x0-0xFFFFFFFF:4>
// <h> Stack Sizes (in Bytes)
// <o1> Undefined Mode <0x0-0xFFFFFFFF:4>
// <o2> Supervisor Mode <0x0-0xFFFFFFFF:4>
// <o3> Abort Mode <0x0-0xFFFFFFFF:4>
// <o4> Fast Interrupt Mode <0x0-0xFFFFFFFF:4>
// <o5> Interrupt Mode <0x0-0xFFFFFFFF:4>
// <o6> User/System Mode <0x0-0xFFFFFFFF:4>
// </h>
// </h>
*/
.equ Top_Stack, 0x00204000
.equ UND_Stack_Size, 0x00000004
.equ SVC_Stack_Size, 0x00000100
.equ ABT_Stack_Size, 0x00000004
.equ FIQ_Stack_Size, 0x00000004
.equ IRQ_Stack_Size, 0x00000100
.equ USR_Stack_Size, 0x00000400
// Embedded Flash Controller (EFC) definitions
.equ EFC_BASE, 0xFFFFFF00 /* EFC Base Address */
.equ EFC_FMR, 0x60 /* EFC_FMR Offset */
/*
// <e> Embedded Flash Controller (EFC)
// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
// <i> Number of Master Clock Cycles in 1us
// <o1.8..9> FWS: Flash Wait State
// <0=> Read: 1 cycle / Write: 2 cycles
// <1=> Read: 2 cycle / Write: 3 cycles
// <2=> Read: 3 cycle / Write: 4 cycles
// <3=> Read: 4 cycle / Write: 4 cycles
// </e>
*/
.equ EFC_SETUP, 1
.equ EFC_FMR_Val, 0x00320100
// Watchdog Timer (WDT) definitions
.equ WDT_BASE, 0xFFFFFD40 /* WDT Base Address */
.equ WDT_MR, 0x04 /* WDT_MR Offset */
/*
// <e> Watchdog Timer (WDT)
// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable
// <o1.13> WDRSTEN: Watchdog Reset Enable
// <o1.14> WDRPROC: Watchdog Reset Processor
// <o1.28> WDDBGHLT: Watchdog Debug Halt
// <o1.29> WDIDLEHLT: Watchdog Idle Halt
// <o1.15> WDDIS: Watchdog Disable
// </e>
*/
.equ WDT_SETUP, 1
.equ WDT_MR_Val, 0x00008000
// Power Mangement Controller (PMC) definitions
.equ PMC_BASE, 0xFFFFFC00 /* PMC Base Address */
.equ PMC_MOR, 0x20 /* PMC_MOR Offset */
.equ PMC_MCFR, 0x24 /* PMC_MCFR Offset */
.equ PMC_PLLR, 0x2C /* PMC_PLLR Offset */
.equ PMC_MCKR, 0x30 /* PMC_MCKR Offset */
.equ PMC_SR, 0x68 /* PMC_SR Offset */
.equ PMC_MOSCEN, (1<<0) /* Main Oscillator Enable */
.equ PMC_OSCBYPASS, (1<<1) /* Main Oscillator Bypass */
.equ PMC_OSCOUNT, (0xFF<<8) /* Main OScillator Start-up Time */
.equ PMC_DIV, (0xFF<<0) /* PLL Divider */
.equ PMC_PLLCOUNT, (0x3F<<8) /* PLL Lock Counter */
.equ PMC_OUT, (0x03<<14) /* PLL Clock Frequency Range */
.equ PMC_MUL, (0x7FF<<16) /* PLL Multiplier */
.equ PMC_USBDIV, (0x03<<28) /* USB Clock Divider */
.equ PMC_CSS, (3<<0) /* Clock Source Selection */
.equ PMC_PRES, (7<<2) /* Prescaler Selection */
.equ PMC_MOSCS, (1<<0) /* Main Oscillator Stable */
.equ PMC_LOCK, (1<<2) /* PLL Lock Status */
/*
// <e> Power Mangement Controller (PMC)
// <h> Main Oscillator
// <o1.0> MOSCEN: Main Oscillator Enable
// <o1.1> OSCBYPASS: Oscillator Bypass
// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255>
// </h>
// <h> Phase Locked Loop (PLL)
// <o2.0..7> DIV: PLL Divider <0-255>
// <o2.16..26> MUL: PLL Multiplier <0-2047>
// <i> PLL Output is multiplied by MUL+1
// <o2.14..15> OUT: PLL Clock Frequency Range
// <0=> 80..160MHz <1=> Reserved
// <2=> 150..220MHz <3=> Reserved
// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
// <o2.28..29> USBDIV: USB Clock Divider
// <0=> None <1=> 2 <2=> 4 <3=> Reserved
// </h>
// <o3.0..1> CSS: Clock Source Selection
// <0=> Slow Clock
// <1=> Main Clock
// <2=> Reserved
// <3=> PLL Clock
// <o3.2..4> PRES: Prescaler
// <0=> None
// <1=> Clock / 2 <2=> Clock / 4
// <3=> Clock / 8 <4=> Clock / 16
// <5=> Clock / 32 <6=> Clock / 64
// <7=> Reserved
// </e>
*/
.equ PMC_SETUP, 1
.equ PMC_MOR_Val, 0x00000601
.equ PMC_PLLR_Val, 0x00191C05
.equ PMC_MCKR_Val, 0x00000007
#ifdef VECTORS_IN_RAM
/*
Exception Vectors to be placed in RAM - added by mt
-> will be used after remapping
Mapped to Address 0 after remapping.
Absolute addressing mode must be used.
Dummy Handlers are implemented as infinite loops which can be modified.
VECTORS_IN_RAM defined in makefile/by commandline
*/
.text
.arm
.section .vectram, "ax"
VectorsRAM: LDR PC,Reset_AddrR
LDR PC,Undef_AddrR
LDR PC,SWI_AddrR
LDR PC,PAbt_AddrR
LDR PC,DAbt_AddrR
NOP /* Reserved Vector */
LDR PC,[PC,#-0xF20] /* Vector From AIC_IVR */
LDR PC,[PC,#-0xF20] /* Vector From AIC_FVR */
Reset_AddrR: .word Reset_Handler
Undef_AddrR: .word Undef_HandlerR
SWI_AddrR: .word SWI_HandlerR
PAbt_AddrR: .word PAbt_HandlerR
DAbt_AddrR: .word DAbt_HandlerR
// .word 0xdeadbeef /* Test Reserved Address */
.word 0 /* Reserved Address */
IRQ_AddrR: .word IRQ_HandlerR
FIQ_AddrR: .word FIQ_HandlerR
Undef_HandlerR: B Undef_HandlerR
SWI_HandlerR: B SWI_HandlerR
PAbt_HandlerR: B PAbt_HandlerR
DAbt_HandlerR: B DAbt_HandlerR
IRQ_HandlerR: B IRQ_HandlerR
FIQ_HandlerR: B FIQ_HandlerR
#endif /* VECTORS_IN_RAM */
/*
Exception Vectors in ROM
-> will be used during startup if remapping is done
-> will be used "always" in code without remapping
Mapped to Address 0.
Absolute addressing mode must be used.
Dummy Handlers are implemented as infinite loops which can be modified.
*/
.text
.arm
.section .vectrom, "ax"
Vectors: LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP /* Reserved Vector */
// LDR PC,IRQ_Addr
LDR PC,[PC,#-0xF20] /* Vector From AIC_IVR */
// LDR PC,FIQ_Addr
LDR PC,[PC,#-0xF20] /* Vector From AIC_FVR */
Reset_Addr: .word Reset_Handler
Undef_Addr: .word Undef_Handler
SWI_Addr: .word SWI_Handler
PAbt_Addr: .word PAbt_Handler
DAbt_Addr: .word DAbt_Handler
.word 0 /* Reserved Address */
IRQ_Addr: .word IRQ_Handler
FIQ_Addr: .word FIQ_Handler
Undef_Handler: B Undef_Handler
SWI_Handler: B SWI_Handler
PAbt_Handler: B PAbt_Handler
DAbt_Handler: B DAbt_Handler
IRQ_Handler: B IRQ_Handler
FIQ_Handler: B FIQ_Handler
// Starupt Code must be linked first at Address at which it expects to run.
.text
.arm
.section .init, "ax"
.global _startup
.func _startup
_startup:
// Reset Handler
LDR pc, =Reset_Handler
Reset_Handler:
// Setup EFC
.if EFC_SETUP
LDR R0, =EFC_BASE
LDR R1, =EFC_FMR_Val
STR R1, [R0, #EFC_FMR]
.endif
// Setup WDT
.if WDT_SETUP
LDR R0, =WDT_BASE
LDR R1, =WDT_MR_Val
STR R1, [R0, #WDT_MR]
.endif
// Setup PMC
.if PMC_SETUP
LDR R0, =PMC_BASE
// Setup Main Oscillator
LDR R1, =PMC_MOR_Val
STR R1, [R0, #PMC_MOR]
// Wait until Main Oscillator is stablilized
.if (PMC_MOR_Val & PMC_MOSCEN)
MOSCS_Loop: LDR R2, [R0, #PMC_SR]
ANDS R2, R2, #PMC_MOSCS
BEQ MOSCS_Loop
.endif
// Setup the PLL
.if (PMC_PLLR_Val & PMC_MUL)
LDR R1, =PMC_PLLR_Val
STR R1, [R0, #PMC_PLLR]
// Wait until PLL is stabilized
PLL_Loop: LDR R2, [R0, #PMC_SR]
ANDS R2, R2, #PMC_LOCK
BEQ PLL_Loop
.endif
// Select Clock
LDR R1, =PMC_MCKR_Val
STR R1, [R0, #PMC_MCKR]
.endif
// Setup Stack for each mode
LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
// Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
// Setup a default Stack Limit (when compiled with "-mapcs-stack-check")
SUB SL, SP, #USR_Stack_Size
// Relocate .data section (Copy from ROM to RAM)
LDR R1, =_etext
LDR R2, =_data
LDR R3, =_edata
LoopRel: CMP R2, R3
LDRLO R0, [R1], #4
STRLO R0, [R2], #4
BLO LoopRel
// Clear .bss section (Zero init)
MOV R0, #0
LDR R1, =__bss_start__
LDR R2, =__bss_end__
LoopZI: CMP R1, R2
STRLO R0, [R1], #4
BLO LoopZI
#ifdef VECTORS_IN_RAM
/*
remap - exception vectors for RAM have been already copied
to 0x00200000 by the .data copy-loop
*/
.equ MC_BASE,0xFFFFFF00 /* MC Base Address */
.equ MC_RCR, 0x00 /* MC_RCR Offset */
LDR R0, =MC_BASE
MOV R1, #1
STR R1, [R0, #MC_RCR] // Remap
#endif /* VECTORS_IN_RAM */
/*
Call C++ constructors (for objects in "global scope")
added by Martin Thomas based on a Anglia Design
example-application for STR7 ARM
*/
LDR r0, =__ctors_start__
LDR r1, =__ctors_end__
ctor_loop:
CMP r0, r1
BEQ ctor_end
LDR r2, [r0], #4 /* this ctor's address */
STMFD sp!, {r0-r1} /* save loop counters */
MOV lr, pc /* set return address */
// MOV pc, r2
BX r2 /* call ctor */
LDMFD sp!, {r0-r1} /* restore loop counters */
B ctor_loop
ctor_end:
// Enter the C code
mov r0,#0 // no arguments (argc = 0)
mov r1,r0
mov r2,r0
mov fp,r0 // null frame pointer
mov r7,r0 // null frame pointer for thumb
ldr r10,=main
adr lr, __main_exit
bx r10 // enter main()
__main_exit: B __main_exit
.size _startup, . - _startup
.endfunc
.end
|
wware/stuff | 11,945 | arm-hacks/sam7/Examples/at91_usbfw_core_hid/startup.S | @ * ----------------------------------------------------------------------------
@ * ATMEL Microcontroller Software Support - ROUSSET -
@ * ----------------------------------------------------------------------------
@ * Copyright (c) 2006, Atmel Corporation
@
@ * All rights reserved.
@ *
@ * Redistribution and use in source and binary forms, with or without
@ * modification, are permitted provided that the following conditions are met:
@ *
@ * - Redistributions of source code must retain the above copyright notice,
@ * this list of conditions and the disclaiimer below.
@ *
@ * - Redistributions in binary form must reproduce the above copyright notice,
@ * this list of conditions and the disclaimer below in the documentation and/or
@ * other materials provided with the distribution.
@ *
@ * Atmel s name may not be used to endorse or promote products derived from
@ * this software without specific prior written permission.
@ *
@ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
@ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
@ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
@ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
@ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
@ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES@ LOSS OF USE, DATA,
@ * OR PROFITS@ OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
@ * ----------------------------------------------------------------------------
@ $Id: startup.s 106 2006-10-13 15:50:54Z jjoannic $
@ modified by Martin Thomas for GNU arm-elf-as compatiblity
@ this must be processed by the preprocessor before passed
@ to gnu-as (done automaticly thru compiler-frontend - see makefile)
@------------------------------------------------------------------------------
@ Includes
@------------------------------------------------------------------------------
#if 1
#include "AT91SAM7S64_inc.h"
#elif defined(AT91SAM7S321)
#include "AT91SAM7S321_inc.h"
#elif defined(AT91SAM7S64)
// #warning "jep"
#include "AT91SAM7S64_inc.h"
#elif defined(AT91SAM7S128)
#include "AT91SAM7S128_inc.h"
#elif defined(AT91SAM7S256)
#include "AT91SAM7S256_inc.h"
#elif defined(AT91SAM7S512)
#include "AT91SAM7S512_inc.h"
#elif defined(AT91SAM7SE32)
#include "AT91SAM7SE32_inc.h"
#elif defined(AT91SAM7SE256)
#include "AT91SAM7SE256_inc.h"
#elif defined(AT91SAM7SE512)
#include "AT91SAM7SE512_inc.h"
#elif defined(AT91SAM7X128)
#include "AT91SAM7X128_inc.h"
#elif defined(AT91SAM7X256)
#include "AT91SAM7X256_inc.h"
#elif defined(AT91SAM7X512)
#include "AT91SAM7X512_inc.h"
#elif defined(AT91SAM7A3)
#include "AT91SAM7A3_inc.h"
#elif defined(AT91RM9200)
#include "AT91RM9200_inc.h"
#elif defined(AT91SAM9260)
#include "AT91SAM9260_inc.h"
#elif defined(AT91SAM9261)
#include "AT91SAM9261_inc.h"
#elif defined(AT91SAM9263)
#include "AT91SAM9263_inc.h"
#elif defined(AT91SAM9265)
#include "AT91SAM9265_inc.h"
#elif defined(AT91SAM926C)
#include "AT91SAM926C_inc.h"
#else
#error "no defintion for target"
#endif
@-------------------------------------------------------------------------------
@ Constants
@-------------------------------------------------------------------------------
@-- ARM processor modes
.equ ARM_MODE_USER, 0x10
.equ ARM_MODE_FIQ, 0x11
.equ ARM_MODE_IRQ, 0x12
.equ ARM_MODE_SVC, 0x13
.equ ARM_MODE_ABORT, 0x17
.equ ARM_MODE_UNDEF, 0x1B
.equ ARM_MODE_SYS, 0x1F
@-- Status register bits
.equ I_BIT, 0x80
.equ F_BIT, 0x40
@-- Stack sizes
.equ IRQ_STACK_SIZE, (3*8*4) @( 3 stacks 8 vectors 4 bytes)
.equ FIQ_STACK_SIZE, 0x004
.equ ABT_STACK_SIZE, 0x004
.equ UND_STACK_SIZE, 0x004
.equ SVC_STACK_SIZE, 0x800
.equ SYS_STACK_SIZE, 0x400
@-------------------------------------------------------------------------------
@ Entry point
@-------------------------------------------------------------------------------
@@ AREA reset, CODE, READONLY
.section .init, "ax"
@@ EXPORT __ENTRY
@@__ENTRY
.global __ENTRY
__ENTRY:
@-------------------------------------------------------------------------------
@- Exception vectors ( before Remap )
@-------------------------------------------------------------------------------
@- These vectors are read at address 0.
@- They absolutely requires to be in relative addresssing mode in order to
@- guarantee a valid jump. For the moment, all are just looping (what may be
@- dangerous in a final system). If an exception occurs before remap, this
@- would result in an infinite loop.
@-------------------------------------------------------------------------------
B Reset @ 0x00 Reset handler
undefvec:
B undefvec @ 0x04 Undefined Instruction
swivec:
B swivec @ 0x08 Software Interrupt
pabtvec:
B pabtvec @ 0x0C Prefetch Abort
dabtvec:
B dabtvec @ 0x10 Data Abort
rsvdvec:
B rsvdvec @ 0x14 reserved
irqvec:
B IRQ_Handler @ 0x18 IRQ : read the AIC
fiqvec:
B fiqvec @ 0x1C FIQ
@-------------------------------------------------------------------------------
@ Reset routine
@-------------------------------------------------------------------------------
Reset:
@---- Stack setup
@---- End of RAM (start of stack) address in r1
@ IF :DEF:AT91SAM9261
#if defined(AT91SAM9261)
ldr r1, =AT91C_IRAM
add r1, r1, #AT91C_IRAM_SIZE
@ ELSE
@ IF :DEF:AT91SAM9260
#elif defined(AT91SAM9260)
ldr r1, =AT91C_IRAM_1
add r1, r1, #AT91C_IRAM_1_SIZE
@ ELSE
#else
ldr r1, =AT91C_ISRAM
add r1, r1, #AT91C_ISRAM_SIZE
@ ENDIF
@ ENDIF
#endif
@---- Interrupt mode stack setup
@ msr CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
mov sp, r1
sub r1, r1, #IRQ_STACK_SIZE
@---- Fast interrupt mode stack setup
@ msr CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
mov sp, r1
sub r1, r1, #FIQ_STACK_SIZE
@---- Abort mode stack setup
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT
mov sp, r1
sub r1, r1, #ABT_STACK_SIZE
@---- Undefined instruction mode stack setup
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT
mov sp, r1
sub r1, r1, #UND_STACK_SIZE
@---- User/System mode stack setup
msr CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT
mov sp, r1
sub r1, r1, #SYS_STACK_SIZE
@---- Supervisor mode stack setup
msr CPSR_c, #ARM_MODE_SVC | F_BIT
mov sp, r1
sub r1, r1, #SVC_STACK_SIZE
@-------------------------------------------------------------------------------
@ Low-level init
@-------------------------------------------------------------------------------
@ IMPORT DEV_Init
.extern DEV_Init
ldr r0, =DEV_Init
mov lr, pc
bx r0
@-------------------------------------------------------------------------------
@ Remap
@-------------------------------------------------------------------------------
@ IF :DEF:REMAP
#if defined(REMAP)
@---- copy the flash code to RAM
@---- Start of RAM in r0, end of stack space in r1, current address in r2
ldr r0, =AT91C_ISRAM
add r1, r0, #AT91C_ISRAM_SIZE
ldr r2, =AT91C_IFLASH
Remap_copy:
ldr r3, [r2], #4
str r3, [r0], #4
cmp r0, r1
bne Remap_copy
@---- Perform remap operation
ldr r0, =AT91C_MC_RCR
mov r1, #1
str r1, [r0]
#else
@-------------------------------------------------------------------------------
@ RW data preinitialization
@-------------------------------------------------------------------------------
@ IF :DEF:DEBUG
#if defined(DEBUG)
@ ELSE
#else
@---- Load addresses
add r0, pc, #-(8+.-RW_addresses)
ldmia r0, {r1, r2, r3}
@---- Initialize RW data
RW_loop:
cmp r2, r3
ldrne r0, [r1], #4
strne r0, [r2], #4
bne RW_loop
b RW_end
RW_addresses:
@ IMPORT |Image$$RO$$Limit| @ End of ROM code
@ IMPORT |Image$$RW$$Base| @ Start of RAM data
@ IMPORT |Image$$RW$$Limit| @ End of RAM data
@ DCD |Image$$RO$$Limit|
@ DCD |Image$$RW$$Base|
@ DCD |Image$$RW$$Limit|
.word _etext
.word __data_start
.word _edata
RW_end:
@ ENDIF
@ ENDIF
#endif
#endif
@-------------------------------------------------------------------------------
@ ZI data preinitialization
@-------------------------------------------------------------------------------
@---- Load addresses
add r0, pc, #-(8+.-ZI_addresses)
ldmia r0, {r1, r2}
mov r0, #0
@---- Initialize ZI data
ZI_loop:
cmp r1, r2
strcc r0, [r1], #4
bcc ZI_loop
b ZI_end
ZI_addresses:
@ IMPORT |Image$$ZI$$Base| @ Base and limit of area
@ IMPORT |Image$$ZI$$Limit| @ Top of zero init segment
@ DCD |Image$$ZI$$Base|
@ DCD |Image$$ZI$$Limit|
.word __bss_start__
.word __bss_end__
ZI_end:
@-------------------------------------------------------------------------------
@ Branch on C code Main function (with interworking)
@-------------------------------------------------------------------------------
@ Branch must be performed by an interworking call as either an ARM or Thumb
@ main C function must be supported. This makes the code not position-
@ independant. A Branch with link would generate errors
@-------------------------------------------------------------------------------
@ IMPORT main
.extern main
ldr r0, =main
mov lr, pc
bx r0
@---- Endless loop
End:
b End
@------------------------------------------------------------------------------
@- Function : IRQ_Handler_Entry
@- Treatments : IRQ Controller Interrupt Handler.
@- Called Functions : AIC_IVR[interrupt]
@------------------------------------------------------------------------------
IRQ_Handler:
@---- Adjust and save return address on the stack
sub lr, lr, #4
stmfd sp!, {lr}
@---- Save r0 and SPSR on the stack
mrs r14, SPSR
stmfd sp!, {r0, r14}
@---- Write in the IVR to support Protect mode
@---- No effect in Normal Mode
@---- De-assert NIRQ and clear the source in Protect mode
ldr r14, =AT91C_BASE_AIC
ldr r0, [r14, #AIC_IVR]
str r14, [r14, #AIC_IVR]
@---- Enable nested interrupts and switch to Supervisor mode
msr CPSR_c, #ARM_MODE_SVC
@---- Save scratch/used registers and LR on the stack
stmfd sp!, {r1-r3, r12, r14}
@---- Branch to the routine pointed by AIC_IVR
mov r14, pc
bx r0
@---- Restore scratch/used registers and LR from the stack
ldmia sp!, {r1-r3, r12, r14}
@---- Disable nested interrupts and switch back to IRQ mode
msr CPSR_c, #I_BIT | ARM_MODE_IRQ
@---- Acknowledge interrupt by writing AIC_EOICR
ldr r14, =AT91C_BASE_AIC
str r14, [r14, #AIC_EOICR]
@---- Restore SPSR and r0 from the stack
ldmia sp!, {r0, r14}
msr SPSR_cxsf, r14
@---- Return from interrupt handler
ldmia sp!, {pc}^
@ END
.end
|
wwivbbs/wwiv | 10,288 | deps/cl345/random/mvsent.s | **********************************************************************
*
* DESCRIPTION
* -----------
* THIS MODULE GATHERS DATA TO PROVIDE ENTROPY FOR THE CRYPTLIB
* RNDMVS.C MODULE.
*
* ENTROPY IS GATHERED BY OBTAINING THE TOD VALUE INTERMIXED WITH
* TASKS THAT PASS CONTROL BACK TO MVS TO PROCESS. ENTROPY IS
* INTRODUCED FROM THE FACT THAT THE AMOUNT OF TIME MVS TAKES TO
* PROCESS THE REQUESTS IS UNKNOWN AND DEPENDENT ON FACTORS NOT IN
* OUR CONTROL.
*
* NEWER VERSIONS OF THE ARCHITECTURE PROVIDE THE PPNO-SHA-512-DRNG,
* BUT THIS IS MERELY THE NIST DETERMINISTIC HASH-BASED GENERTOR,
* AND PROVIDES NO ENTROPY. SINCE WE ALREADY HAVE A DETERMINISTIC
* GENERATOR PRESENT, THERE'S NO POINT TO USING PPNO-SHA-512-DRNG.
*
* INPUT
* -----
* R1 = PARM ADDRESS
* +0 = LENGTH OF INPUT BUFFER. MUST BE IN THE RANGE OF 1 TO
* 2,000,000
* +4 = ADDRESS OF BUFFER TO PLACE THE RANDOM DATA.
*
* OUTPUT
* ------
* R15 = RETURN CODE
* 0 = SUCCESSFUL
* 1 = PARAMETER LIST ERROR
* 2 = O/S MACRO ERROR
*
* ENVIRONMENT
* -----------
* ENVIRONMENT: LANGUAGE ENVIRONMENT
* AUTHORIZATION: PROBLEM STATE
* CROSS MEMORY MODE: PASN=HASN=SASN
* AMODE: 31
* RMODE: 31
* INTERUPT STATUS: EXTERNAL INTERUPTS
* LOCKS: NONE
*
**********************************************************************
MVSENT CEEENTRY MAIN=NO,AUTO=LDSSZ
USING LDS,CEEDSA
**********************************************************************
*
* LOAD INPUT PARAMETERS.
*
**********************************************************************
L R3,0(,R1) LOAD LENGTH
LTR R3,R3 ZERO?
BNH EXIT01 YES
C R3,=F'2000000' MORE THAN MAX BYTES ?
BH EXIT01 YES, IS ERROR
ST R3,BUFLEN SAVE BUFFER LENGTH
*
ICM R3,B'1111',4(R1) LOAD ADR OF BUFFER
BZ EXIT01 IMPROPER PARAMETER LIST
ST R3,BUFADR SAVE BUFFER ADDRESS
**********************************************************************
*
* MAIN FUNCTION.
*
* OBTAIN THE TOD VALUE INTERMIXED WITH TASKS THAT PASS CONTROL
* BACK TO MVS TO PROCESS. ENTROPY IS INTRODUCED FROM THE FACT THAT
* THE AMOUNT OF TIME MVS TAKES TO PROCESS THE REQUESTS IS UNKNOWN
* AND DEPENDENT ON FACTORS NOT IN OUR CONTROL.
**********************************************************************
*
* EACH LOOP GATHERS 8 BYTES OF DATA.
*
ENLOOP DS 0H
LA R2,WBUF LOAD ADR OF WORKING BUFFER
*
MVC PLIST(#ATTACH),$ATTACH INIT PARM LIST
LA R4,0 LOAD NULL
ST R4,STECB ZERO ECB
LA R4,STECB LOAD A(ECB)
ATTACH ECB=(R4), +
SF=(E,PLIST)
LTR R15,R15 SUCCESSFUL?
BNZ EXIT02 FAILED
ST R1,STTCB SAVE ADR OF TCB
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
WAIT ECB=(R4) WAIT FOR TASK TO COMPLETE
LA R4,STTCB LOAD A TCB
DETACH (R4) DETACK TASK
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
GETMAIN RC,LV=50000,LOC=(31,31)
LTR R15,R15 SUCCESSFUL?
BNZ EXIT02 NO, EXIT
LR R4,R1
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
MVC PLIST(#GQSCAN),$GQSCAN INIT PARM LIST
GQSCAN AREA=((R4),50000), +
MF=(E,PLIST)
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
FREEMAIN RU,LV=50000,A=(R4)
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
LOAD EP=A@#$#@Z,ERRET=NOTFND
NOTFND DS 0H
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
MVC PLIST(#ENQ),$ENQ INIT PARM LIST
ENQ MF=(E,PLIST)
MVC PLIST(#DEQ),$DEQ INIT PARM LIST
DEQ MF=(E,PLIST)
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
MVC PLIST(#STIMERM),$STIMERM INIT PARM LIST
LA R4,TIMERID LOAD ADR OF TIME ID FIELD
XC TIMEECB,TIMEECB CLEAR ECB
LA R1,TIMEECB
ST R1,TIMEECB@ SAVE ADR ECB PARM
STIMERM SET, +
WAIT=NO, +
EXIT=TIMEEXIT, +
PARM=TIMEECB@, +
TUINTVL=WAITTIME, +
ID=(R4), +
MF=(E,PLIST)
LTR R15,R15 SUCCESSFUL?
BNZ EXIT02 NO, EXIT
LA R4,TIMEECB LOAD ADR OF ECB
WAIT ECB=(R4) WAIT FOR TIMER TO COMPLETE
*
STCK TOD OBTAIN TOD VALUE
MVC 0(1,R2),TODB7 SAVE BYTE 7
LA R2,1(,R2) INCR ADR
*
* COPY THE DATA TO THE USER BUFFER.
*
LA R1,WBUF LOAD ADR OF BUFFER
SR R2,R1 CALC LEN OF DATA
L R3,BUFLEN LOAD REMAINING BUF LEN
CR R2,R3 HOW MUCH ROOM LEFT?
BL COPYDATA ITS ENOUGH ROOM
LR R2,R3 SET LEN TO REMAINING ROOM
*
COPYDATA DS 0H
L R4,BUFADR LOAD ADR OF CALLER'S BUF
LR R5,R2 LOAD LEN OF DATA
LA R6,WBUF LOAD ADR OF DATA
LR R7,R5 LOAD LEN OF DATA
MVCL R4,R6
*
ST R4,BUFADR SAVE OFFSET INTO BUF
L R3,BUFLEN LOAD REMAINING LEN OF BUF
SR R3,R2 CALC NEW REMAINING LEN
ST R3,BUFLEN SAVE NEW REMAINING LEN
*
LTR R3,R3 END OF BUF
BH ENLOOP NO, CONTINUE
*
B EXIT00 EXIT
*
**********************************************************************
*
* RETURN TO CALLER.
*
**********************************************************************
EXIT01 DS 0H
LA R15,1
B EXIT
EXIT02 DS 0H
LA R15,2
B EXIT
EXIT00 DS 0H
LA R15,0
EXIT DS 0H
CEETERM RC=(R15)
**********************************************************************
*
* CONSTANTS
*
**********************************************************************
PPA CEEPPA ,
*
WAITTIME DC F'2' ~(2*26) MICROSECONDS
QNAME DC C'CRYPTLIB' ENQ QNAME
RNAME DC C'RANDOM' ENQ RNAME
*
$ATTACH ATTACH EP=IEFBR14, +
DPMOD=-255, +
SF=L
#ATTACH EQU *-$ATTACH
*
$GQSCAN GQSCAN SCOPE=ALL, +
XSYS=YES, +
MF=L
#GQSCAN EQU *-$GQSCAN
*
$ENQ ENQ (QNAME,RNAME,S,,SYSTEMS),MF=L
#ENQ EQU *-$ENQ
*
$DEQ DEQ (QNAME,RNAME,,SYSTEMS),MF=L
#DEQ EQU *-$ENQ
*
$STIMERM STIMERM SET,MF=L
#STIMERM EQU *-$STIMERM
*
LTORG ,
YREGS ,
*
**********************************************************************
*
* STIMERM ASYNC EXIT
*
**********************************************************************
DROP
TIMEEXIT DS 0H
USING TIMEEXIT,R15
L R2,4(,R1) LOAD ADR OF ECB
POST (R2) POST ECB
BR R14 RETURN TO CALLER
DROP R15
*
**********************************************************************
*
* DYNAMIC STORAGE AREA
*
**********************************************************************
LDS DSECT ,
DS XL(CEEDSASZ) DSA STORAGE
*
BUFADR DS A CALLER'S BUFFER ADR
BUFLEN DS H CALLER'S BUFFER LEN
*
TOD DS 0D TIME-OF-DAY VALUE
TODB1 DS B
TODB2 DS B
TODB3 DS B
TODB4 DS B
TODB5 DS B
TODB6 DS B
TODB7 DS B
TODB8 DS B
*
STECB DS F SUBTASK ECB
STTCB DS A SUBTASK ADR
TIMERID DS F STIMERM TIMER ID
TIMEECB DS F STIMERM ECB
TIMEECB@ DS A ADR OF STIMERM ECB
PLIST DS XL256 GENERAL PARM LIST
WBUF DS CL100 WORKING BUFFER
*
DS 0D END LDS ON DOUBLE WORD
LDSSZ EQU *-LDS
*
**********************************************************************
*
* MAPPING DSECTS
*
**********************************************************************
CEECAA , LE COMMON ANCHOR AREA
CEEDSA , LE DYNAMIC STORAGE AREA
*
END MVSENT
|
wwivbbs/wwiv | 14,169 | deps/infozip/zip30/match.S | /*
Copyright (c) 1990-2005 Info-ZIP. All rights reserved.
See the accompanying file LICENSE, version 2004-May-22 or later
(the contents of which are also included in zip.h) for terms of use.
If, for some reason, both of these files are missing, the Info-ZIP license
also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
*/
/*
* match.s by Jean-loup Gailly. Translated to 32 bit code by Kai Uwe Rommel.
* The 68020 version has been written by Francesco Potorti` <pot@cnuce.cnr.it>
* with adaptations by Carsten Steger <stegerc@informatik.tu-muenchen.de>,
* Andreas Schwab <schwab@lamothe.informatik.uni-dortmund.de> and
* Kristoffer Eriksson <ske@pkmab.se>
*/
/* This file is NOT used in conjunction with zlib. */
#ifndef USE_ZLIB
/* Preprocess with -DNO_UNDERLINE if your C compiler does not prefix
* external symbols with an underline character '_'.
*/
#if defined(NO_UNDERLINE) || defined(__ELF__)
# define _prev prev
# define _window window
# define _match_start match_start
# define _prev_length prev_length
# define _good_match good_match
# define _nice_match nice_match
# define _strstart strstart
# define _max_chain_length max_chain_length
# define _match_init match_init
# define _longest_match longest_match
#endif
#ifdef DYN_ALLOC
error: DYN_ALLOC not yet supported in match.s
#endif
/* Use 16-bytes alignment if your assembler supports it. Warning: gas
* uses a log(x) parameter (.align 4 means 16-bytes alignment). On SVR4
* the parameter is a number of bytes.
*/
#ifndef ALIGNMENT
# define ALIGNMENT 4
#endif
#ifndef WSIZE
# define WSIZE 32768
#endif
#define MIN_MATCH 3
#define MAX_MATCH 258
#define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1)
#define MAX_DIST (WSIZE - MIN_LOOKAHEAD)
#if defined(i386) || defined(_I386) || defined(_i386) || defined(__i386)
/* This version is for 386 Unix or OS/2 in 32 bit mode.
* Warning: it uses the AT&T syntax: mov source,dest
* This file is only optional. If you want to force the C version,
* add -DNO_ASM to CFLAGS in Makefile and set OBJA to an empty string.
* If you have reduced WSIZE in (g)zip.h, then make sure this is
* assembled with an equivalent -DWSIZE=<whatever>.
* This version assumes static allocation of the arrays (-DDYN_ALLOC not used).
*/
.file "match.S"
.globl _match_init
.globl _longest_match
.text
_match_init:
ret
/*-----------------------------------------------------------------------
* Set match_start to the longest match starting at the given string and
* return its length. Matches shorter or equal to prev_length are discarded,
* in which case the result is equal to prev_length and match_start is
* garbage.
* IN assertions: cur_match is the head of the hash chain for the current
* string (strstart) and its distance is <= MAX_DIST, and prev_length >= 1
*/
.align ALIGNMENT
_longest_match: /* int longest_match(cur_match) */
#define cur_match 20(%esp)
/* return address */ /* esp+16 */
push %ebp /* esp+12 */
push %edi /* esp+8 */
push %esi /* esp+4 */
push %ebx /* esp */
/*
* match equ esi
* scan equ edi
* chain_length equ ebp
* best_len equ ebx
* limit equ edx
*/
mov cur_match,%esi
mov _strstart,%edx
mov _max_chain_length,%ebp /* chain_length = max_chain_length */
mov %edx,%edi
sub $(MAX_DIST),%edx /* limit = strstart-MAX_DIST */
cld /* string ops increment si and di */
jae limit_ok
sub %edx,%edx /* limit = NIL */
limit_ok:
add $2+_window,%edi /* edi = offset(window+strstart+2) */
mov _prev_length,%ebx /* best_len = prev_length */
movw -2(%edi),%cx /* cx = scan[0..1] */
movw -3(%ebx,%edi),%ax /* ax = scan[best_len-1..best_len] */
cmp _good_match,%ebx /* do we have a good match already? */
jb do_scan
shr $2,%ebp /* chain_length >>= 2 */
jmp do_scan
.align ALIGNMENT
long_loop:
/* at this point, edi == scan+2, esi == cur_match */
movw -3(%ebx,%edi),%ax /* ax = scan[best_len-1..best_len] */
movw -2(%edi),%cx /* cx = scan[0..1] */
short_loop:
/*
* at this point, di == scan+2, si == cur_match,
* ax = scan[best_len-1..best_len] and cx = scan[0..1]
*/
and $(WSIZE-1), %esi
dec %ebp /* --chain_length */
movw _prev(,%esi,2),%si /* cur_match = prev[cur_match] */
/* top word of esi is still 0 */
jz the_end
cmp %edx,%esi /* cur_match <= limit ? */
jbe the_end
do_scan:
cmpw _window-1(%ebx,%esi),%ax/* check match at best_len-1 */
jne short_loop
cmpw _window(%esi),%cx /* check min_match_length match */
jne short_loop
add $2+_window,%esi /* si = match */
mov $((MAX_MATCH>>1)-1),%ecx/* scan for at most MAX_MATCH bytes */
mov %edi,%eax /* ax = scan+2 */
repe; cmpsw /* loop until mismatch */
je maxmatch /* match of length MAX_MATCH? */
mismatch:
movb -2(%edi),%cl /* mismatch on first or second byte? */
xchg %edi,%eax /* edi = scan+2, eax = end of scan */
subb -2(%esi),%cl /* cl = 0 if first bytes equal */
sub %edi,%eax /* eax = len */
sub $2+_window,%esi /* esi = cur_match + len */
sub %eax,%esi /* esi = cur_match */
subb $1,%cl /* set carry if cl == 0 (cannot use DEC) */
adc $0,%eax /* eax = carry ? len+1 : len */
cmp %ebx,%eax /* len > best_len ? */
jle long_loop
mov %esi,_match_start /* match_start = cur_match */
mov %eax,%ebx /* ebx = best_len = len */
#ifdef FULL_SEARCH
cmp $(MAX_MATCH),%eax /* len >= MAX_MATCH ? */
#else
cmp _nice_match,%eax /* len >= nice_match ? */
#endif
jl long_loop
the_end:
mov %ebx,%eax /* result = eax = best_len */
pop %ebx
pop %esi
pop %edi
pop %ebp
ret
.align ALIGNMENT
maxmatch:
cmpsb
jmp mismatch
#else /* !(i386 || _I386 || _i386 || __i386) */
/* ======================== 680x0 version ================================= */
#if defined(m68k)||defined(mc68k)||defined(__mc68000__)||defined(__MC68000__)
# ifndef mc68000
# define mc68000
# endif
#endif
#if defined(__mc68020__) || defined(__MC68020__) || defined(sysV68)
# ifndef mc68020
# define mc68020
# endif
#endif
#if defined(mc68020) || defined(mc68000)
#if (defined(mc68020) || defined(NeXT)) && !defined(UNALIGNED_OK)
# define UNALIGNED_OK
#endif
#ifdef sysV68 /* Try Motorola Delta style */
# define GLOBAL(symbol) global symbol
# define TEXT text
# define FILE(filename) file filename
# define invert_maybe(src,dst) dst,src
# define imm(data) &data
# define reg(register) %register
# define addl add.l
# define addql addq.l
# define blos blo.b
# define bhis bhi.b
# define bras bra.b
# define clrl clr.l
# define cmpmb cmpm.b
# define cmpw cmp.w
# define cmpl cmp.l
# define lslw lsl.w
# define lsrl lsr.l
# define movel move.l
# define movew move.w
# define moveb move.b
# define moveml movem.l
# define subl sub.l
# define subw sub.w
# define subql subq.l
# define IndBase(bd,An) (bd,An)
# define IndBaseNdxl(bd,An,Xn) (bd,An,Xn.l)
# define IndBaseNdxw(bd,An,Xn) (bd,An,Xn.w)
# define predec(An) -(An)
# define postinc(An) (An)+
#else /* default style (Sun 3, NeXT, Amiga, Atari) */
# define GLOBAL(symbol) .globl symbol
# define TEXT .text
# define FILE(filename) .even
# define invert_maybe(src,dst) src,dst
# if defined(sun) || defined(mc68k)
# define imm(data) #data
# else
# define imm(data) \#data
# endif
# define reg(register) register
# define blos bcss
# if defined(sun) || defined(mc68k)
# define movel movl
# define movew movw
# define moveb movb
# endif
# define IndBase(bd,An) An@(bd)
# define IndBaseNdxl(bd,An,Xn) An@(bd,Xn:l)
# define IndBaseNdxw(bd,An,Xn) An@(bd,Xn:w)
# define predec(An) An@-
# define postinc(An) An@+
#endif /* styles */
#define Best_Len reg(d0) /* unsigned */
#define Cur_Match reg(d1) /* Ipos */
#define Loop_Counter reg(d2) /* int */
#define Scan_Start reg(d3) /* unsigned short */
#define Scan_End reg(d4) /* unsigned short */
#define Limit reg(d5) /* IPos */
#define Chain_Length reg(d6) /* unsigned */
#define Scan_Test reg(d7)
#define Scan reg(a0) /* *uch */
#define Match reg(a1) /* *uch */
#define Prev_Address reg(a2) /* *Pos */
#define Scan_Ini reg(a3) /* *uch */
#define Match_Ini reg(a4) /* *uch */
#define Stack_Pointer reg(sp)
GLOBAL (_match_init)
GLOBAL (_longest_match)
TEXT
FILE ("match.S")
_match_init:
rts
/*-----------------------------------------------------------------------
* Set match_start to the longest match starting at the given string and
* return its length. Matches shorter or equal to prev_length are discarded,
* in which case the result is equal to prev_length and match_start is
* garbage.
* IN assertions: cur_match is the head of the hash chain for the current
* string (strstart) and its distance is <= MAX_DIST, and prev_length >= 1
*/
/* int longest_match (cur_match) */
#ifdef UNALIGNED_OK
# define pushreg 15928 /* d2-d6/a2-a4 */
# define popreg 7292
#else
# define pushreg 16184 /* d2-d7/a2-a4 */
# define popreg 7420
#endif
_longest_match:
movel IndBase(4,Stack_Pointer),Cur_Match
moveml imm(pushreg),predec(Stack_Pointer)
movel _max_chain_length,Chain_Length
movel _prev_length,Best_Len
movel imm(_prev),Prev_Address
movel imm(_window+MIN_MATCH),Match_Ini
movel _strstart,Limit
movel Match_Ini,Scan_Ini
addl Limit,Scan_Ini
subw imm(MAX_DIST),Limit
bhis L__limit_ok
clrl Limit
L__limit_ok:
cmpl invert_maybe(_good_match,Best_Len)
blos L__length_ok
lsrl imm(2),Chain_Length
L__length_ok:
subql imm(1),Chain_Length
#ifdef UNALIGNED_OK
movew IndBase(-MIN_MATCH,Scan_Ini),Scan_Start
movew IndBaseNdxw(-MIN_MATCH-1,Scan_Ini,Best_Len),Scan_End
#else
moveb IndBase(-MIN_MATCH,Scan_Ini),Scan_Start
lslw imm(8),Scan_Start
moveb IndBase(-MIN_MATCH+1,Scan_Ini),Scan_Start
moveb IndBaseNdxw(-MIN_MATCH-1,Scan_Ini,Best_Len),Scan_End
lslw imm(8),Scan_End
moveb IndBaseNdxw(-MIN_MATCH,Scan_Ini,Best_Len),Scan_End
#endif
bras L__do_scan
L__long_loop:
#ifdef UNALIGNED_OK
movew IndBaseNdxw(-MIN_MATCH-1,Scan_Ini,Best_Len),Scan_End
#else
moveb IndBaseNdxw(-MIN_MATCH-1,Scan_Ini,Best_Len),Scan_End
lslw imm(8),Scan_End
moveb IndBaseNdxw(-MIN_MATCH,Scan_Ini,Best_Len),Scan_End
#endif
L__short_loop:
lslw imm(1),Cur_Match
movew IndBaseNdxl(0,Prev_Address,Cur_Match),Cur_Match
cmpw invert_maybe(Limit,Cur_Match)
dbls Chain_Length,L__do_scan
bras L__return
L__do_scan:
movel Match_Ini,Match
addl Cur_Match,Match
#ifdef UNALIGNED_OK
cmpw invert_maybe(IndBaseNdxw(-MIN_MATCH-1,Match,Best_Len),Scan_End)
bne L__short_loop
cmpw invert_maybe(IndBase(-MIN_MATCH,Match),Scan_Start)
bne L__short_loop
#else
moveb IndBaseNdxw(-MIN_MATCH-1,Match,Best_Len),Scan_Test
lslw imm(8),Scan_Test
moveb IndBaseNdxw(-MIN_MATCH,Match,Best_Len),Scan_Test
cmpw invert_maybe(Scan_Test,Scan_End)
bne L__short_loop
moveb IndBase(-MIN_MATCH,Match),Scan_Test
lslw imm(8),Scan_Test
moveb IndBase(-MIN_MATCH+1,Match),Scan_Test
cmpw invert_maybe(Scan_Test,Scan_Start)
bne L__short_loop
#endif
movew imm((MAX_MATCH-MIN_MATCH+1)-1),Loop_Counter
movel Scan_Ini,Scan
L__scan_loop:
cmpmb postinc(Match),postinc(Scan)
dbne Loop_Counter,L__scan_loop
subl Scan_Ini,Scan
addql imm(MIN_MATCH-1),Scan
cmpl invert_maybe(Best_Len,Scan)
bls L__short_loop
movel Scan,Best_Len
movel Cur_Match,_match_start
#ifdef FULL_SEARCH
cmpl invert_maybe(imm(MAX_MATCH),Best_Len)
#else
cmpl invert_maybe(_nice_match,Best_Len)
#endif
blos L__long_loop
L__return:
moveml postinc(Stack_Pointer),imm(popreg)
rts
#else
error: this asm version is for 386 or 680x0 only
#endif /* mc68000 || mc68020 */
#endif /* i386 || _I386 || _i386 || __i386 */
#endif /* !USE_ZLIB */
|
wwivbbs/wwiv | 12,154 | deps/infozip/zip30/crc_i386.S | /*
Copyright (c) 1990-2007 Info-ZIP. All rights reserved.
See the accompanying file LICENSE, version 2000-Apr-09 or later
(the contents of which are also included in zip.h) for terms of use.
If, for some reason, all these files are missing, the Info-ZIP license
also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
*/
/*
* crc_i386.S, optimized CRC calculation function for Zip and UnZip,
* created by Paul Kienitz and Christian Spieler. Last revised 07 Jan 2007.
*
* GRR 961110: incorporated Scott Field optimizations from win32/crc_i386.asm
* => overall 6% speedup in "unzip -tq" on 9MB zipfile (486-66)
*
* SPC 970402: revised for Rodney Brown's optimizations (32-bit-wide
* aligned reads for most of the data from buffer), can be
* disabled by defining the macro NO_32_BIT_LOADS
*
* SPC 971012: added Rodney Brown's additional tweaks for 32-bit-optimized
* CPUs (like the Pentium Pro, Pentium II, and probably some
* Pentium clones). This optimization is controlled by the
* preprocessor switch "__686" and is disabled by default.
* (This default is based on the assumption that most users
* do not yet work on a Pentium Pro or Pentium II machine ...)
*
* COS 050116: Enabled the 686 build by default, because there are hardly any
* pre-686 CPUs in serious use nowadays. (See SPC 970402 above.)
*
* SPC 060103: Updated code to incorporate newer optimizations found in zlib.
*
* SPC 070107: Added conditional switch to deactivate crc32() compilation.
*
* FLAT memory model assumed. Calling interface:
* - args are pushed onto the stack from right to left,
* - return value is given in the EAX register,
* - all other registers (with exception of EFLAGS) are preserved. (With
* GNU C 2.7.x, %edx and %ecx are `scratch' registers, but preserving
* them nevertheless adds only 4 single byte instructions.)
*
* This source generates the function
* ulg crc32(ulg crc, ZCONST uch *buf, extent len).
*
* Loop unrolling can be disabled by defining the macro NO_UNROLLED_LOOPS.
* This results in shorter code at the expense of reduced performance.
*/
/* This file is NOT used in conjunction with zlib, or when only creation of
* the basic CRC_32_Table (for other purpose) is requested.
*/
#if !defined(USE_ZLIB) && !defined(CRC_TABLE_ONLY)
/* Preprocess with -DNO_UNDERLINE if your C compiler does not prefix
* external symbols with an underline character '_'.
*/
#if defined(NO_UNDERLINE) || defined(__ELF__)
# define _crc32 crc32
# define _get_crc_table get_crc_table
#endif
/* Use 16-byte alignment if your assembler supports it. Warning: gas
* uses a log(x) parameter (.align 4 means 16-byte alignment). On SVR4
* the parameter is a number of bytes.
*/
#ifndef ALIGNMENT
# define ALIGNMENT .align 4,0x90
#endif
#if defined(i386) || defined(_i386) || defined(_I386) || defined(__i386)
/* This version is for 386 Unix, OS/2, MSDOS in 32 bit mode (gcc & gas).
* Warning: it uses the AT&T syntax: mov source,dest
* This file is only optional. If you want to use the C version,
* remove -DASM_CRC from CFLAGS in Makefile and set OBJA to an empty string.
*/
.file "crc_i386.S"
#if !defined(PRE_686) && !defined(__686)
/* Optimize for Pentium Pro and compatible CPUs by default. */
# define __686
#endif
#if defined(NO_STD_STACKFRAME) && defined(USE_STD_STACKFRAME)
# undef USE_STACKFRAME
#else
/* The default is to use standard stack frame entry, because it
* results in smaller code!
*/
# ifndef USE_STD_STACKFRAME
# define USE_STD_STACKFRAME
# endif
#endif
#ifdef USE_STD_STACKFRAME
# define _STD_ENTRY pushl %ebp ; movl %esp,%ebp
# define arg1 8(%ebp)
# define arg2 12(%ebp)
# define arg3 16(%ebp)
# define _STD_LEAVE popl %ebp
#else /* !USE_STD_STACKFRAME */
# define _STD_ENTRY
# define arg1 24(%esp)
# define arg2 28(%esp)
# define arg3 32(%esp)
# define _STD_LEAVE
#endif /* ?USE_STD_STACKFRAME */
/*
* These two (three) macros make up the loop body of the CRC32 cruncher.
* registers modified:
* eax : crc value "c"
* esi : pointer to next data byte (or lword) "buf++"
* registers read:
* edi : pointer to base of crc_table array
* scratch registers:
* ebx : index into crc_table array
* (requires upper three bytes = 0 when __686 is undefined)
*/
#ifndef __686 /* optimize for 386, 486, Pentium */
#define Do_CRC /* c = (c >> 8) ^ table[c & 0xFF] */\
movb %al, %bl ;/* tmp = c & 0xFF */\
shrl $8, %eax ;/* c = (c >> 8) */\
xorl (%edi, %ebx, 4), %eax ;/* c ^= table[tmp] */
#else /* __686 : optimize for Pentium Pro and compatible CPUs */
#define Do_CRC /* c = (c >> 8) ^ table[c & 0xFF] */\
movzbl %al, %ebx ;/* tmp = c & 0xFF */\
shrl $8, %eax ;/* c = (c >> 8) */\
xorl (%edi, %ebx, 4), %eax ;/* c ^=table[tmp] */
#endif /* ?__686 */
#define Do_CRC_byte /* c = (c >> 8) ^ table[(c^*buf++)&0xFF] */\
xorb (%esi), %al ;/* c ^= *buf */\
incl %esi ;/* buf++ */\
Do_CRC
#define Do_CRC_byteof(ofs) /* c = (c >> 8) ^ table[(c^*buf++)&0xFF] */\
xorb ofs(%esi), %al ;/* c ^= *buf */\
incl %esi ;/* buf++ */\
Do_CRC
#ifndef NO_32_BIT_LOADS
# ifdef IZ_CRCOPTIM_UNFOLDTBL
/* the edx register is needed in crc calculation */
# define SavLen arg3
# define UpdCRC_lword \
movzbl %al, %ebx ; \
movl 3072(%edi,%ebx,4), %edx ; \
movzbl %ah, %ebx ; \
shrl $16, %eax ; \
xor 2048(%edi,%ebx,4), %edx ; \
movzbl %al, %ebx ; \
shrl $8,%eax ; \
xorl 1024(%edi,%ebx,4), %edx ; \
movl (%edi,%eax,4), %eax ; \
xorl %edx,%eax ;
# define UpdCRC_lword_sh(dwPtrIncr) \
movzbl %al, %ebx ; \
movl 3072(%edi,%ebx,4), %edx ; \
movzbl %ah, %ebx ; \
shrl $16, %eax ; \
xor 2048(%edi,%ebx,4), %edx ; \
movzbl %al, %ebx ; \
addl $4*(dwPtrIncr), %esi ;/* ((ulg *)buf)+=dwPtrIncr */\
shrl $8,%eax ; \
xorl 1024(%edi,%ebx,4), %edx ; \
movl (%edi,%eax,4),%eax ; \
xorl %edx,%eax ;
# else /* !IZ_CRCOPTIM_UNFOLDTBL */
/* the edx register is not needed anywhere else */
# define SavLen %edx
# define UpdCRC_lword \
Do_CRC \
Do_CRC \
Do_CRC \
Do_CRC
# define UpdCRC_lword_sh(dwPtrIncr) \
Do_CRC \
Do_CRC \
addl $4*(dwPtrIncr), %esi ;/* ((ulg *)buf)++ */\
Do_CRC \
Do_CRC
# endif /* ?IZ_CRCOPTIM_UNFOLDTBL */
#define Do_CRC_lword \
xorl (%esi), %eax ;/* c ^= *(ulg *)buf */\
UpdCRC_lword_sh(1) /* ... ((ulg *)buf)++ */
#define Do_CRC_4lword \
xorl (%esi), %eax ;/* c ^= *(ulg *)buf */\
UpdCRC_lword \
xorl 4(%esi), %eax ;/* c ^= *((ulg *)buf+1) */\
UpdCRC_lword \
xorl 8(%esi), %eax ;/* c ^= *((ulg *)buf+2) */\
UpdCRC_lword \
xorl 12(%esi), %eax ;/* c ^= *((ulg *)buf]+3 */\
UpdCRC_lword_sh(4) /* ... ((ulg *)buf)+=4 */
#endif /* !NO_32_BIT_LOADS */
.text
.globl _crc32
_crc32: /* ulg crc32(ulg crc, uch *buf, extent len) */
_STD_ENTRY
pushl %edi
pushl %esi
pushl %ebx
pushl %edx
pushl %ecx
movl arg2, %esi /* 2nd arg: uch *buf */
subl %eax, %eax /* > if (!buf) */
testl %esi, %esi /* > return 0; */
jz .L_fine /* > else { */
call _get_crc_table
movl %eax, %edi
movl arg1, %eax /* 1st arg: ulg crc */
#ifndef __686
subl %ebx, %ebx /* ebx=0; bl usable as dword */
#endif
movl arg3, %ecx /* 3rd arg: extent len */
notl %eax /* > c = ~crc; */
testl %ecx, %ecx
#ifndef NO_UNROLLED_LOOPS
jz .L_bail
# ifndef NO_32_BIT_LOADS
/* Assert now have positive length */
.L_align_loop:
testl $3, %esi /* Align buf on lword boundary */
jz .L_aligned_now
Do_CRC_byte
decl %ecx
jnz .L_align_loop
.L_aligned_now:
# endif /* !NO_32_BIT_LOADS */
movl %ecx, SavLen /* save current value of len */
shrl $4, %ecx /* ecx = len / 16 */
jz .L_No_Sixteens
/* align loop head at start of 486 internal cache line !! */
ALIGNMENT
.L_Next_Sixteen:
# ifndef NO_32_BIT_LOADS
Do_CRC_4lword
# else /* NO_32_BIT_LOADS */
Do_CRC_byteof(0)
Do_CRC_byteof(1)
Do_CRC_byteof(2)
Do_CRC_byteof(3)
Do_CRC_byteof(4)
Do_CRC_byteof(5)
Do_CRC_byteof(6)
Do_CRC_byteof(7)
Do_CRC_byteof(8)
Do_CRC_byteof(9)
Do_CRC_byteof(10)
Do_CRC_byteof(11)
Do_CRC_byteof(12)
Do_CRC_byteof(13)
Do_CRC_byteof(14)
Do_CRC_byteof(15)
addl $16,%esi ;/* buf += 16 */
# endif /* ?NO_32_BIT_LOADS */
decl %ecx
jnz .L_Next_Sixteen
.L_No_Sixteens:
movl SavLen, %ecx
andl $15, %ecx /* ecx = len % 16 */
# ifndef NO_32_BIT_LOADS
shrl $2,%ecx /* ecx = len / 4 */
jz .L_No_Fours
.L_Next_Four:
Do_CRC_lword
decl %ecx
jnz .L_Next_Four
.L_No_Fours:
movl SavLen,%ecx
andl $3,%ecx /* ecx = len % 4 */
# endif /* !NO_32_BIT_LOADS */
#endif /* !NO_UNROLLED_LOOPS */
jz .L_bail /* > if (len) */
/* align loop head at start of 486 internal cache line !! */
ALIGNMENT
.L_loupe: /* > do { */
Do_CRC_byte /* c = CRC32(c,*buf++,crctab);*/
decl %ecx /* > } while (--len); */
jnz .L_loupe
.L_bail: /* > } */
notl %eax /* > return ~c; */
.L_fine:
popl %ecx
popl %edx
popl %ebx
popl %esi
popl %edi
_STD_LEAVE
ret
#else
error: this asm version is for 386 only
#endif /* i386 || _i386 || _I386 || __i386 */
#endif /* !USE_ZLIB && !CRC_TABLE_ONLY */
|
wwivbbs/wwiv | 12,154 | deps/infozip/unzip60/crc_i386.S | /*
Copyright (c) 1990-2007 Info-ZIP. All rights reserved.
See the accompanying file LICENSE, version 2000-Apr-09 or later
(the contents of which are also included in zip.h) for terms of use.
If, for some reason, all these files are missing, the Info-ZIP license
also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
*/
/*
* crc_i386.S, optimized CRC calculation function for Zip and UnZip,
* created by Paul Kienitz and Christian Spieler. Last revised 07 Jan 2007.
*
* GRR 961110: incorporated Scott Field optimizations from win32/crc_i386.asm
* => overall 6% speedup in "unzip -tq" on 9MB zipfile (486-66)
*
* SPC 970402: revised for Rodney Brown's optimizations (32-bit-wide
* aligned reads for most of the data from buffer), can be
* disabled by defining the macro NO_32_BIT_LOADS
*
* SPC 971012: added Rodney Brown's additional tweaks for 32-bit-optimized
* CPUs (like the Pentium Pro, Pentium II, and probably some
* Pentium clones). This optimization is controlled by the
* preprocessor switch "__686" and is disabled by default.
* (This default is based on the assumption that most users
* do not yet work on a Pentium Pro or Pentium II machine ...)
*
* COS 050116: Enabled the 686 build by default, because there are hardly any
* pre-686 CPUs in serious use nowadays. (See SPC 970402 above.)
*
* SPC 060103: Updated code to incorporate newer optimizations found in zlib.
*
* SPC 070107: Added conditional switch to deactivate crc32() compilation.
*
* FLAT memory model assumed. Calling interface:
* - args are pushed onto the stack from right to left,
* - return value is given in the EAX register,
* - all other registers (with exception of EFLAGS) are preserved. (With
* GNU C 2.7.x, %edx and %ecx are `scratch' registers, but preserving
* them nevertheless adds only 4 single byte instructions.)
*
* This source generates the function
* ulg crc32(ulg crc, ZCONST uch *buf, extent len).
*
* Loop unrolling can be disabled by defining the macro NO_UNROLLED_LOOPS.
* This results in shorter code at the expense of reduced performance.
*/
/* This file is NOT used in conjunction with zlib, or when only creation of
* the basic CRC_32_Table (for other purpose) is requested.
*/
#if !defined(USE_ZLIB) && !defined(CRC_TABLE_ONLY)
/* Preprocess with -DNO_UNDERLINE if your C compiler does not prefix
* external symbols with an underline character '_'.
*/
#if defined(NO_UNDERLINE) || defined(__ELF__)
# define _crc32 crc32
# define _get_crc_table get_crc_table
#endif
/* Use 16-byte alignment if your assembler supports it. Warning: gas
* uses a log(x) parameter (.align 4 means 16-byte alignment). On SVR4
* the parameter is a number of bytes.
*/
#ifndef ALIGNMENT
# define ALIGNMENT .align 4,0x90
#endif
#if defined(i386) || defined(_i386) || defined(_I386) || defined(__i386)
/* This version is for 386 Unix, OS/2, MSDOS in 32 bit mode (gcc & gas).
* Warning: it uses the AT&T syntax: mov source,dest
* This file is only optional. If you want to use the C version,
* remove -DASM_CRC from CFLAGS in Makefile and set OBJA to an empty string.
*/
.file "crc_i386.S"
#if !defined(PRE_686) && !defined(__686)
/* Optimize for Pentium Pro and compatible CPUs by default. */
# define __686
#endif
#if defined(NO_STD_STACKFRAME) && defined(USE_STD_STACKFRAME)
# undef USE_STACKFRAME
#else
/* The default is to use standard stack frame entry, because it
* results in smaller code!
*/
# ifndef USE_STD_STACKFRAME
# define USE_STD_STACKFRAME
# endif
#endif
#ifdef USE_STD_STACKFRAME
# define _STD_ENTRY pushl %ebp ; movl %esp,%ebp
# define arg1 8(%ebp)
# define arg2 12(%ebp)
# define arg3 16(%ebp)
# define _STD_LEAVE popl %ebp
#else /* !USE_STD_STACKFRAME */
# define _STD_ENTRY
# define arg1 24(%esp)
# define arg2 28(%esp)
# define arg3 32(%esp)
# define _STD_LEAVE
#endif /* ?USE_STD_STACKFRAME */
/*
* These two (three) macros make up the loop body of the CRC32 cruncher.
* registers modified:
* eax : crc value "c"
* esi : pointer to next data byte (or lword) "buf++"
* registers read:
* edi : pointer to base of crc_table array
* scratch registers:
* ebx : index into crc_table array
* (requires upper three bytes = 0 when __686 is undefined)
*/
#ifndef __686 /* optimize for 386, 486, Pentium */
#define Do_CRC /* c = (c >> 8) ^ table[c & 0xFF] */\
movb %al, %bl ;/* tmp = c & 0xFF */\
shrl $8, %eax ;/* c = (c >> 8) */\
xorl (%edi, %ebx, 4), %eax ;/* c ^= table[tmp] */
#else /* __686 : optimize for Pentium Pro and compatible CPUs */
#define Do_CRC /* c = (c >> 8) ^ table[c & 0xFF] */\
movzbl %al, %ebx ;/* tmp = c & 0xFF */\
shrl $8, %eax ;/* c = (c >> 8) */\
xorl (%edi, %ebx, 4), %eax ;/* c ^=table[tmp] */
#endif /* ?__686 */
#define Do_CRC_byte /* c = (c >> 8) ^ table[(c^*buf++)&0xFF] */\
xorb (%esi), %al ;/* c ^= *buf */\
incl %esi ;/* buf++ */\
Do_CRC
#define Do_CRC_byteof(ofs) /* c = (c >> 8) ^ table[(c^*buf++)&0xFF] */\
xorb ofs(%esi), %al ;/* c ^= *buf */\
incl %esi ;/* buf++ */\
Do_CRC
#ifndef NO_32_BIT_LOADS
# ifdef IZ_CRCOPTIM_UNFOLDTBL
/* the edx register is needed in crc calculation */
# define SavLen arg3
# define UpdCRC_lword \
movzbl %al, %ebx ; \
movl 3072(%edi,%ebx,4), %edx ; \
movzbl %ah, %ebx ; \
shrl $16, %eax ; \
xor 2048(%edi,%ebx,4), %edx ; \
movzbl %al, %ebx ; \
shrl $8,%eax ; \
xorl 1024(%edi,%ebx,4), %edx ; \
movl (%edi,%eax,4), %eax ; \
xorl %edx,%eax ;
# define UpdCRC_lword_sh(dwPtrIncr) \
movzbl %al, %ebx ; \
movl 3072(%edi,%ebx,4), %edx ; \
movzbl %ah, %ebx ; \
shrl $16, %eax ; \
xor 2048(%edi,%ebx,4), %edx ; \
movzbl %al, %ebx ; \
addl $4*(dwPtrIncr), %esi ;/* ((ulg *)buf)+=dwPtrIncr */\
shrl $8,%eax ; \
xorl 1024(%edi,%ebx,4), %edx ; \
movl (%edi,%eax,4),%eax ; \
xorl %edx,%eax ;
# else /* !IZ_CRCOPTIM_UNFOLDTBL */
/* the edx register is not needed anywhere else */
# define SavLen %edx
# define UpdCRC_lword \
Do_CRC \
Do_CRC \
Do_CRC \
Do_CRC
# define UpdCRC_lword_sh(dwPtrIncr) \
Do_CRC \
Do_CRC \
addl $4*(dwPtrIncr), %esi ;/* ((ulg *)buf)++ */\
Do_CRC \
Do_CRC
# endif /* ?IZ_CRCOPTIM_UNFOLDTBL */
#define Do_CRC_lword \
xorl (%esi), %eax ;/* c ^= *(ulg *)buf */\
UpdCRC_lword_sh(1) /* ... ((ulg *)buf)++ */
#define Do_CRC_4lword \
xorl (%esi), %eax ;/* c ^= *(ulg *)buf */\
UpdCRC_lword \
xorl 4(%esi), %eax ;/* c ^= *((ulg *)buf+1) */\
UpdCRC_lword \
xorl 8(%esi), %eax ;/* c ^= *((ulg *)buf+2) */\
UpdCRC_lword \
xorl 12(%esi), %eax ;/* c ^= *((ulg *)buf]+3 */\
UpdCRC_lword_sh(4) /* ... ((ulg *)buf)+=4 */
#endif /* !NO_32_BIT_LOADS */
.text
.globl _crc32
_crc32: /* ulg crc32(ulg crc, uch *buf, extent len) */
_STD_ENTRY
pushl %edi
pushl %esi
pushl %ebx
pushl %edx
pushl %ecx
movl arg2, %esi /* 2nd arg: uch *buf */
subl %eax, %eax /* > if (!buf) */
testl %esi, %esi /* > return 0; */
jz .L_fine /* > else { */
call _get_crc_table
movl %eax, %edi
movl arg1, %eax /* 1st arg: ulg crc */
#ifndef __686
subl %ebx, %ebx /* ebx=0; bl usable as dword */
#endif
movl arg3, %ecx /* 3rd arg: extent len */
notl %eax /* > c = ~crc; */
testl %ecx, %ecx
#ifndef NO_UNROLLED_LOOPS
jz .L_bail
# ifndef NO_32_BIT_LOADS
/* Assert now have positive length */
.L_align_loop:
testl $3, %esi /* Align buf on lword boundary */
jz .L_aligned_now
Do_CRC_byte
decl %ecx
jnz .L_align_loop
.L_aligned_now:
# endif /* !NO_32_BIT_LOADS */
movl %ecx, SavLen /* save current value of len */
shrl $4, %ecx /* ecx = len / 16 */
jz .L_No_Sixteens
/* align loop head at start of 486 internal cache line !! */
ALIGNMENT
.L_Next_Sixteen:
# ifndef NO_32_BIT_LOADS
Do_CRC_4lword
# else /* NO_32_BIT_LOADS */
Do_CRC_byteof(0)
Do_CRC_byteof(1)
Do_CRC_byteof(2)
Do_CRC_byteof(3)
Do_CRC_byteof(4)
Do_CRC_byteof(5)
Do_CRC_byteof(6)
Do_CRC_byteof(7)
Do_CRC_byteof(8)
Do_CRC_byteof(9)
Do_CRC_byteof(10)
Do_CRC_byteof(11)
Do_CRC_byteof(12)
Do_CRC_byteof(13)
Do_CRC_byteof(14)
Do_CRC_byteof(15)
addl $16,%esi ;/* buf += 16 */
# endif /* ?NO_32_BIT_LOADS */
decl %ecx
jnz .L_Next_Sixteen
.L_No_Sixteens:
movl SavLen, %ecx
andl $15, %ecx /* ecx = len % 16 */
# ifndef NO_32_BIT_LOADS
shrl $2,%ecx /* ecx = len / 4 */
jz .L_No_Fours
.L_Next_Four:
Do_CRC_lword
decl %ecx
jnz .L_Next_Four
.L_No_Fours:
movl SavLen,%ecx
andl $3,%ecx /* ecx = len % 4 */
# endif /* !NO_32_BIT_LOADS */
#endif /* !NO_UNROLLED_LOOPS */
jz .L_bail /* > if (len) */
/* align loop head at start of 486 internal cache line !! */
ALIGNMENT
.L_loupe: /* > do { */
Do_CRC_byte /* c = CRC32(c,*buf++,crctab);*/
decl %ecx /* > } while (--len); */
jnz .L_loupe
.L_bail: /* > } */
notl %eax /* > return ~c; */
.L_fine:
popl %ecx
popl %edx
popl %ebx
popl %esi
popl %edi
_STD_LEAVE
ret
#else
error: this asm version is for 386 only
#endif /* i386 || _i386 || _I386 || __i386 */
#endif /* !USE_ZLIB && !CRC_TABLE_ONLY */
|
wwivbbs/wwiv | 2,804 | deps/infozip/zip30/acorn/sendbits.s | ;===========================================================================
; Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 1999-Oct-05 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, both of these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
;===========================================================================
; sendbits.s for ARM by Sergio Monesi and Darren Salt.
r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lr RN 14
pc RN 15
AREA |Asm$$Code|, CODE, READONLY
= "send_bits",0
ALIGN
& &FF00000C
IMPORT __rt_stkovf_split_small
IMPORT flush_outbuf
IMPORT bi_valid
IMPORT bi_buf
IMPORT out_size
IMPORT out_offset
IMPORT out_buf
EXPORT send_bits
send_bits
MOV ip,sp
STMDB sp!,{r4,r5,fp,ip,lr,pc}
SUB fp,ip,#4
LDR r5,=bi_buf
LDR r3,=bi_valid
LDR r4,[r5]
LDR r2,[r3]
ORR r4,r4,r0,LSL r2 ; |= value<<bi_valid
ADD r2,r2,r1 ; += length
CMP r2,#&10
STRLE r2,[r3] ; short? store & return
STRLE r4,[r5]
LDMLEDB fp,{r4,r5,fp,sp,pc}^
SUB r2,r2,#&10 ; adjust bi_valid, bi_buf
MOV ip,r4,LSR #16 ; (done early, keeping the old bi_buf
STR r2,[r3] ; in R4 for later storage)
STR ip,[r5]
LDR r0,=out_size
LDR r1,=out_offset
LDR r0,[r0]
LDR r2,[r1]
SUB r0,r0,#1
CMP r2,r0 ; if out_offset >= out_size-1
LDRHS r0,=out_buf
LDRHS r0,[r0]
BLHS flush_outbuf ; then flush the buffer
LDR r0,=out_buf
LDR r1,=out_offset
LDR r0,[r0]
LDR r2,[r1]
MOV r5,r4,LSR #8
STRB r4,[r0,r2]! ; store 'old' bi_buf
STRB r5,[r0,#1]
ADD r2,r2,#2
STR r2,[r1]
LDMDB fp,{r4,r5,fp,sp,pc}^
ptr_bi & bi_valid
& bi_buf
= "bi_reverse",0
ALIGN
& &FF00000C
EXPORT bi_reverse
bi_reverse
MOV r2,#0
loop MOVS r0,r0,LSR #1
ADCS r2,r2,r2
SUBS r1,r1,#1
BNE loop
MOV r0,r2
MOVS pc,lr
END
|
wwivbbs/wwiv | 6,532 | deps/infozip/zip30/acorn/swiven.s | ;===========================================================================
; Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 1999-Oct-05 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, both of these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
;===========================================================================
; SWI veneers used by Zip/Unzip
;
r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
r10 RN 10
r11 RN 11
r12 RN 12
sp RN 13
lr RN 14
pc RN 15
sl RN 10
fp RN 11
ip RN 12
XOS_Bit EQU &020000
OS_GBPB EQU &00000C
OS_File EQU &000008
OS_FSControl EQU &000029
OS_CLI EQU &000005
OS_ReadC EQU &000004
OS_ReadVarVal EQU &000023
DDEUtils_Prefix EQU &042580
Territory_ReadCurrentTimeZone EQU &043048
MACRO
STARTCODE $name
EXPORT $name
$name
MEND
AREA |C$$code|, CODE, READONLY
; os_error *SWI_OS_FSControl_26(char *source, char *dest, int actionmask);
STARTCODE SWI_OS_FSControl_26
MOV ip, lr
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #26
SWI OS_FSControl + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; os_error *SWI_OS_FSControl_27(char *filename, int actionmask);
STARTCODE SWI_OS_FSControl_27
MOV ip, lr
MOV r3, r1
MOV r1, r0
MOV r0, #27
SWI OS_FSControl + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; os_error *SWI_OS_GBPB_9(char *dirname, void *buf, int *number,
; int *offset, int size, char *match);
STARTCODE SWI_OS_GBPB_9
MOV ip, sp
STMFD sp!, {r2-r6,lr}
LDMIA ip, {r5,r6}
LDR r4, [r3]
LDR r3, [r2]
MOV r2, r1
MOV r1, r0
MOV r0, #9
SWI OS_GBPB + XOS_Bit
LDMVSFD sp!, {r2-r6,pc}^
MOV r0, #0
LDMFD sp, {r5,r6}
STR r3, [r5]
STR r4, [r6]
LDMFD sp!, {r2-r6,pc}^
; os_error *SWI_OS_File_1(char *filename, int loadaddr, int execaddr, int attrib);
STARTCODE SWI_OS_File_1
STMFD sp!, {r5,lr}
MOV r5, r3
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #1
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r5,pc}^
; os_error *SWI_OS_File_5(char *filename, int *objtype, int *loadaddr,
; int *execaddr, int *length, int *attrib);
STARTCODE SWI_OS_File_5
STMFD sp!, {r1-r5,lr}
MOV r1, r0
MOV r0, #5
SWI OS_File + XOS_Bit
LDMVSFD sp!, {r1-r5,pc}^
LDR lr, [sp]
TEQ lr, #0
STRNE r0, [lr]
LDR lr, [sp, #4]
TEQ lr ,#0
STRNE r2, [lr]
LDR lr, [sp, #8]
TEQ lr, #0
STRNE r3, [lr]
LDR lr, [sp ,#24]
TEQ lr, #0
STRNE r4, [lr]
LDR lr, [sp ,#28]
TEQ lr, #0
STRNE r5, [lr]
MOV r0, #0
LDMFD sp!, {r1-r5,pc}^
; os_error *SWI_OS_File_6(char *filename);
STARTCODE SWI_OS_File_6
STMFD sp!, {r4-r5,lr}
MOV r1, r0
MOV r0, #6
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r4-r5,pc}^
; os_error *SWI_OS_File_7(char *filename, int loadaddr, int execaddr, int size);
STARTCODE SWI_OS_File_7
STMFD sp!, {r4-r5,lr}
MOV r5, r3
MOV r4, #0
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #7
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r4-r5,pc}^
; os_error *SWI_OS_CLI(char *cmd);
STARTCODE SWI_OS_CLI
MOV ip, lr
SWI OS_CLI + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; int SWI_OS_ReadC(void);
STARTCODE SWI_OS_ReadC
MOV ip, lr
SWI OS_ReadC + XOS_Bit
MOVS pc, ip
; os_error *SWI_OS_ReadVarVal(char *var, char *buf, int len, int *bytesused);
STARTCODE SWI_OS_ReadVarVal
STMFD sp!, {r4,lr}
MOV ip, r3
MOV r3, #0
MOV r4, #0
SWI OS_ReadVarVal + XOS_Bit
LDMVSFD sp!, {r4,pc}^
TEQ ip, #0
STRNE r2, [ip]
MOV r0, #0
LDMFD sp!, {r4,pc}^
; os_error *SWI_OS_FSControl_54(char *buffer, int dir, char *fsname, int *size);
STARTCODE SWI_OS_FSControl_54
STMFD sp!, {r3-r6,lr}
LDR r5, [r3]
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #54
SWI OS_FSControl + XOS_Bit
LDMVSFD sp!, {r3-r6,pc}^
MOV r0, #0
LDMFD sp!, {r3}
STR r5, [r3]
LDMFD sp!, {r4-r6,pc}^
; os_error *SWI_OS_FSControl_37(char *pathname, char *buffer, int *size);
STARTCODE SWI_OS_FSControl_37
STMFD sp!, {r2,r3-r5,lr}
LDR r5, [r2]
MOV r3, #0
MOV r4, #0
MOV r2, r1
MOV r1, r0
MOV r0, #37
SWI OS_FSControl + XOS_Bit
LDMVSFD sp!, {r2,r3-r5,pc}^
MOV r0, #0
LDMFD sp!, {r2}
STR r5, [r2]
LDMFD sp!, {r3-r5,pc}^
; os_error *SWI_DDEUtils_Prefix(char *dir);
STARTCODE SWI_DDEUtils_Prefix
MOV ip, lr
SWI DDEUtils_Prefix + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; int SWI_Read_Timezone(void);
STARTCODE SWI_Read_Timezone
MOV ip, lr
SWI Territory_ReadCurrentTimeZone + XOS_Bit
MOVVC r0, r1
MOVVS r0, #0
MOVS pc, ip
END
|
wwivbbs/wwiv | 5,367 | deps/infozip/zip30/acorn/match.s | ;===========================================================================
; Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 1999-Oct-05 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, both of these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
;===========================================================================
; match.s for ARM by Sergio Monesi.
r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
sl RN 10
fp RN 11
ip RN 12
sp RN 13
lr RN 14
pc RN 15
MAX_DIST EQU 32506
WMASK EQU 32767
MAX_MATCH EQU 258
AREA |C$$code|, CODE, READONLY
; r1 = chain_lenght
; r2 = scan
; r3 = match
; r4 = len (tmp)
; r5 = best_len
; r6 = limit
; r7 = strend
; r8 = scan_end1
; r9 = scan_end
; lr = window
; fp = prev
|__max_chain_length|
IMPORT max_chain_length
DCD max_chain_length
|__window|
IMPORT window
DCD window
|__prev|
IMPORT prev
DCD prev
|__prev_length|
IMPORT prev_length
DCD prev_length
|__strstart|
IMPORT strstart
DCD strstart
|__good_match|
IMPORT good_match
DCD good_match
|__nice_match|
IMPORT nice_match
DCD nice_match
|__match_start|
IMPORT match_start
DCD match_start
DCB "longest_match"
DCB &00,&00,&00
DCD &ff000010
EXPORT longest_match
longest_match
STMFD sp!, {r4-r9,fp,lr}
LDR fp, [pc, #|__prev|-.-8]
LDR r1, [pc, #|__max_chain_length|-.-8]
LDR r1, [r1]
LDR lr, [pc, #|__window|-.-8]
LDR ip, [pc, #|__strstart|-.-8]
LDR ip, [ip]
ADD r2, lr, ip
LDR r5, [pc, #|__prev_length|-.-8]
LDR r5, [r5]
SUBS ip, ip, #MAX_DIST-250 ; if r6 > MAX_DIST
SUBCSS r6, ip, #250 ; r6 = r6 - MAXDIST
MOVLS r6, #0 ; else r6 = 0
ADD r7, r2, #MAX_MATCH-256
ADD r7, r7, #256 ; r7 = r2 + MAX_MATCH (=258);
SUB ip, r5, #1
LDRB r8, [r2, ip]
LDRB r9, [r2, r5]
LDR ip, [pc, #|__good_match|-.-8]
LDR ip, [ip]
CMP r5, ip
MOVCS r1, r1, LSR #2
cycle
ADD r3, lr, r0
LDRB ip, [r3, r5]
CMP ip, r9
BNE cycle_end
SUB ip, r5, #1
LDRB ip, [r3, ip]
CMP ip, r8
BNE cycle_end
LDRB ip, [r2]
LDRB r4, [r3]
CMP ip, r4
BNE cycle_end
LDRB ip, [r3, #1]
LDRB r4, [r2, #1]
CMP ip, r4
BNE cycle_end
ADD r2, r2, #2
ADD r3, r3, #2
inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
LDRB ip, [r2, #1]!
LDRB r4, [r3, #1]!
CMP ip, r4
BNE exit_inn_cycle
CMP r2, r7
BCC inn_cycle
exit_inn_cycle
SUB r4, r2, r7 ; len = MAX_MATCH - (int)(strend - scan);
ADD r4, r4, #MAX_MATCH-256
ADD r4, r4, #256
SUB r2, r2, r4 ; scan = strend - MAX_MATCH
CMP r4, r5 ; if (len > best_len) {
BLE cycle_end
LDR ip, [pc, #|__match_start|-.-8] ; match_start = cur_match;
STR r0, [ip]
MOV r5, r4 ; best_len = len;
LDR ip, [pc, #|__nice_match|-.-8] ; if (len >= nice_match)
LDR ip, [ip]
CMP r4, ip
BGE exit_match ; break;
SUB ip, r5, #1 ; scan_end1 = scan[best_len-1];
LDRB r8, [r2, ip]
LDRB r9, [r2, r5] ; scan_end = scan[best_len];
cycle_end
MOV ip, r0, LSL #17 ; cur_match & WMASK
MOV ip, ip, LSR #17
LDR r0, [fp, ip, ASL #1] ; cur_match = prev[cur_match & WMASK]
MOV r0, r0, ASL #16
MOV r0, r0, LSR #16
CMP r0, r6 ; cur_match > limit
BLS exit_match
SUBS r1, r1, #1 ; --chain_length
BNE cycle ; chain_length != 0
exit_match
MOV r0, r5
LDMFD sp!, {r4-r9,fp,pc}^
END
|
wwivbbs/wwiv | 3,087 | deps/infozip/zip30/qdos/config.s | ;===========================================================================
; Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 1999-Oct-05 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, both of these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
;===========================================================================
#
.globl _qlflag
.globl _qlwait
#ifdef ZIP
.globl _dtype
#endif
.data
ds.w 0
dc.b '<<QCFX>>01'
#ifdef ZIP
dc.w 8
dc.b 'Info-ZIP'
* 12345678901234567890
ds.w 0
dc.w 4
dc.b 'qdos'
ds.w 0
#else
dc.w 10
dc.b 'Info-UNZIP'
* 12345678901234567890
ds.w 0
dc.w 4
dc.b 'qdos'
ds.w 0
#endif
dc.b 10
dc.b 0
l_4: dc.w _qlwait-l_4
dc.w 0
dc.w 0
l_5: dc.w hpt-l_5
l_6: dc.w hxx-l_6
#ifdef ZIP
dc.b 10
dc.b 0
d_4: dc.w _dtype-d_4
dc.w 0
dc.w 0
d_5: dc.w dpt-d_5
d_6: dc.w dxx-d_6
#else
dc.b 4
dc.b 0
l5:
dc.w list1-l5
dc.w 0
l5a:
dc.w Postit-l5a ; post proc
l6:
dc.w apt-l6
l7:
dc.w axx-l7
* -------------------------------------
dc.b 4
dc.b 0
l8:
dc.w list2-l8
dc.w 0
l8a:
dc.w Postit-l8a ; post proc
l9:
dc.w bpt-l9
la:
dc.w bxx-la
* -------------------------------------
#endif
dc.w -1 ; end
_qlflag:
dc.w 0
_qlwait:
dc.w 250
_dtype:
dc.w 255
hpt: dc.w 10
dc.b 'Exit Delay'
* 12345678901234567890
ds.w 0
hxx: dc.w 0
dc.w $ffff
dc.w -1
#ifdef ZIP
dpt: dc.w 14
dc.b 'Directory Type'
* 12345678901234567890
ds.w 0
dxx: dc.w 3
dc.w $ff
dc.w -1
#else
list1:
dc.b 0
list2:
dc.b 0
apt:
dc.w 11
dc.b 'Unpack Mode'
* 12345678901234567890
.even
axx: dc.b 0
dc.b 0
dc.w 8
dc.b 'SMS/QDOS'
.even
dc.b 1
dc.b 0
dc.w 7
dc.b 'Default'
.even
dc.w -1
.even
bpt:
dc.w 12
dc.b 'Listing Mode'
* 12345678901234567890
.even
bxx:
dc.w 0
dc.w 7
dc.b 'Default'
.even
dc.b 2
dc.b 0
dc.w 8
dc.b 'SMS/QDOS'
* 12345678901234567890
.even
dc.w -1
Postit:
lea.l _qlflag,a0
move.b list1,d0
move.b d0,(a0)
move.b list2,d0
or.b d0,(a0)
moveq #0,d0
rts
#endif
end
|
wwivbbs/wwiv | 2,523 | deps/infozip/zip30/qdos/crc68.s | ;===========================================================================
; Copyright (c) 1990-2000 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
.text
.globl _crc32 ; (ulg val, uch *buf, extent bufsize)
.globl _get_crc_table ; ulg *get_crc_table(void)
_crc32:
move.l 8(sp),d0
bne valid
moveq #0,d0
rts
valid: movem.l d2/d3,-(sp)
jsr _get_crc_table
move.l d0,a0
move.l 12(sp),d0
move.l 16(sp),a1
move.l 20(sp),d1
not.l d0
move.l d1,d2
lsr.l #3,d1
bra decr8
loop8: moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
decr8: dbra d1,loop8
and.w #7,d2
bra decr1
loop1: moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
decr1: dbra d2,loop1
done: movem.l (sp)+,d2/d3
not.l d0
rts
|
wwivbbs/wwiv | 3,718 | deps/infozip/zip30/qdos/match.s | ;===========================================================================
; Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 1999-Oct-05 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, both of these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
;===========================================================================
; match.a -- optional optimized asm version of longest match in deflate.c
; Written by Jean-loup Gailly
;
; Adapted for the Amiga by Carsten Steger <stegerc@informatik.tu-muenchen.de>
; using the code in match.S.
; The major change in this code consists of removing all unaligned
; word accesses, because they cause 68000-based Amigas to crash.
; For maximum speed, UNALIGNED_OK can be defined in Makefile.sasc.
; The program will then only run on 68020-based Amigas, though.
;
; This code will run with registerized parameters too, unless SAS
; changes parameter passing conventions between new releases of SAS/C.
;;Cur_Match equr d0 ; Must be in d0!
;;Best_Len equr d1
;;Loop_Counter equr d2
;;Scan_Start equr d3
;;Scan_End equr d4
;;Limit equr d5
;;Chain_Length equr d6
;;Scan_Test equr d7
;;Scan equr a0
;;Match equr a1
;;Prev_Address equr a2
;;Scan_Ini equr a3
;;Match_Ini equr a4
MAX_MATCH equ 258
MIN_MATCH equ 3
WSIZE equ 32768
MAX_DIST equ WSIZE-MAX_MATCH-MIN_MATCH-1
.globl _max_chain_length
.globl _prev_length
.globl _prev
.globl _window
.globl _strstart
.globl _good_match
.globl _match_start
.globl _nice_match
.text
.globl _match_init
.globl _longest_match
_match_init:
rts
_longest_match:
move.l 4(sp),d0
movem.l d2-d7/a2-a4,-(sp)
move.l _max_chain_length,d6
move.l _prev_length,d1
lea _prev,a2
lea _window+MIN_MATCH,a4
move.l _strstart,d5
move.l a4,a3
add.l d5,a3
subi.w #MAX_DIST,d5
bhi limit_ok
moveq #0,d5
limit_ok:
cmp.l _good_match,d1
bcs length_ok
lsr.l #2,d6
length_ok:
subq.l #1,d6
move.b -MIN_MATCH(a3),d3
lsl.w #8,d3
move.b -MIN_MATCH+1(a3),d3
move.b -MIN_MATCH-1(a3,d1),d4
lsl.w #8,d4
move.b -MIN_MATCH(a3,d1),d4
bra do_scan
long_loop:
move.b -MIN_MATCH-1(a3,d1),d4
lsl.w #8,d4
move.b -MIN_MATCH(a3,d1),d4
short_loop:
lsl.w #1,d0
move.w 0(a2,d0.l),d0
cmp.w d5,d0
dbls d6,do_scan
bra return
do_scan:
move.l a4,a1
add.l d0,a1
move.b -MIN_MATCH-1(a1,d1),d7
lsl.w #8,d7
move.b -MIN_MATCH(a1,d1),d7
cmp.w d7,d4
bne short_loop
move.b -MIN_MATCH(a1),d7
lsl.w #8,d7
move.b -MIN_MATCH+1(a1),d7
cmp.w d7,d3
bne short_loop
move.w #(MAX_MATCH-MIN_MATCH),d2
move.l a3,a0
scan_loop:
cmpm.b (a1)+,(a0)+
dbne d2,scan_loop
sub.l a3,a0
addq.l #(MIN_MATCH-1),a0
cmp.l d1,a0
bls short_loop
move.l a0,d1
move.l d0,_match_start
cmp.l _nice_match,d1
bcs long_loop
return:
move.l d1,d0
movem.l (sp)+,d2-d7/a2-a4
rts
end
|
wwivbbs/wwiv | 4,143 | deps/infozip/zip30/human68k/crc_68.s | ;===========================================================================
; Copyright (c) 1990-2000 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
; crc_68 created by Paul Kienitz, last modified 04 Jan 96.
;
; Return an updated 32 bit CRC value, given the old value and a block of data.
; The CRC table used to compute the value is gotten by calling get_crc_table().
; This replaces the older updcrc() function used in Zip and fUnZip. The
; prototype of the function is:
;
; ulg crc32(ulg crcval, uch *text, extent textlen);
;
; On the Amiga, type extent is always unsigned long, not unsigned int, because
; int can be short or long at whim, but size_t is long.
;
; If using this source on a non-Amiga 680x0 system, note that we treat
; a0/a1/d0/d1 as scratch registers not preserved across function calls.
; We do not bother to support registerized arguments for crc32() -- the
; textlen parm is usually large enough so that savings outside the loop
; are pointless.
;
; Define NO_UNROLLED_LOOPS to use a simple short loop which might be more
; efficient on certain machines with dinky instruction caches ('020?), or for
; processing short strings. If loops are unrolled, the textlen parm must be
; less than 512K; if not unrolled, it must be less than 64K.
;
; 1999/09/23: for Human68k: Modified by Shimazaki Ryo.
xdef _crc32 ; (ulg val, uch *buf, extent bufsize)
DO_CRC0 MACRO
moveq #0,ltemp
move.b (textbuf)+,ltemp
eor.b crcval,ltemp
lsl.w #2,ltemp
move.l (crc_table,ltemp.w),ltemp
lsr.l #8,crcval
eor.l ltemp,crcval
ENDM
DO_CRC2 MACRO
move.b (textbuf)+,btemp
eor.b crcval,btemp
lsr.l #8,crcval
move.l (crc_table,btemp.w*4),ltemp
eor.l ltemp,crcval
ENDM
crc_table reg a0 array of unsigned long
crcval reg d0 unsigned long initial value
textbuf reg a1 array of unsigned char
textbufsize reg d1 unsigned long (count of bytes in textbuf)
btemp reg d2
ltemp reg d3
xref _get_crc_table ; ulg *get_crc_table(void)
quad
_crc32:
move.l 8(sp),d0
bne.s valid
;;;;; moveq #0,d0
rts
valid: movem.l btemp/ltemp,-(sp)
jsr _get_crc_table
movea.l d0,crc_table
move.l 12(sp),crcval
move.l 16(sp),textbuf
move.l 20(sp),textbufsize
not.l crcval
ifdef NO_UNROLLED_LOOPS
if CPU==68000
bra.s decr
loop: DO_CRC0
decr: dbra textbufsize,loop
bra.s done
else
twenty: moveq #0,btemp
bra.s decr2
loop2: DO_CRC2
decr2: dbra textbufsize,loop2
endif
ELSE ; !NO_UNROLLED_LOOPS
if CPU==68000
moveq #7,btemp
and textbufsize,btemp
lsr.l #3,textbufsize
bra decr8
loop8: DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
decr8: dbra textbufsize,loop8
bra.s decr1
loop1: DO_CRC0
decr1: dbra btemp,loop1
bra done
else
twenty: moveq #0,btemp
move.l textbufsize,-(sp)
lsr.l #3,textbufsize
bra decr82
quad
loop82: DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
decr82: dbra textbufsize,loop82
moveq #7,textbufsize
and.l (sp)+,textbufsize
bra.s decr12
loop12: DO_CRC2
decr12: dbra textbufsize,loop12
endif
ENDC ; ?NO_UNROLLED_LOOPS
done: movem.l (sp)+,btemp/ltemp
not.l crcval
;;;;; move.l crcval,d0 ; crcval already is d0
rts
|
wwivbbs/wwiv | 36,215 | deps/infozip/zip30/human68k/deflate.s | ;===========================================================================
; Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 1999-Oct-05 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, both of these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
;===========================================================================
; This is a 680x0 assembly language translation of the Info-ZIP source file
; deflate.c, by Paul Kienitz. No rights reserved. The function longest_match
; is based in part on match.a by Carsten Steger, which in turn is partly based
; on match.s for 386 by Jean-loup Gailly and Kai Uwe Rommel. Mostly, however,
; this material is based on deflate.c, by Gailly, Rommel, and Igor Mandrichenko.
; This code is not commented very much; see deflate.c for comments that explain
; what the functions are doing.
;
; The symbols that can be used to select different versions are as follows:
;
; CPU020 if defined, use 68020 instructions always.
;
; CPUTEST if defined, check at runtime for CPU type. Another symbol
; specifying the platform-specific test must be used with this.
; If neither of these is defined, use 68000 instructions only.
; Runtime test is nonportable; it is different for each OS.
;
; AMIGA use Amiga-specific test for 68020, if CPUTEST defined. Also
; tells it that registers d0/a0/d1/a1 are not preserved by
; function calls. At present, if AMIGA is not defined, it
; causes functions to preserve all registers. ALL OF THIS CODE
; CURRENTLY ASSUMES THAT REGISTERS D2-D7/A2-A6 WILL BE PRESERVED
; BY ANY FUNCTIONS THAT IT CALLS.
;
; DYN_ALLOC should be defined here if it is defined for C source; tells us
; that big arrays are allocated instead of static.
;
; WSIZE must be defined as the same number used for WSIZE in the C
; source, and must be a power of two <= 32768. As elsewhere,
; the default value is 32768.
;
; INT16 define this if ints are 16 bits; otherwise 32 bit ints assumed.
;
; SMALL_MEM define this if it is defined in the C source; otherwise it uses
; the MEDIUM_MEM model. BIG_MEM and MMAP are *not* supported.
; The FULL_SEARCH option in deflate.c is also not supported.
;
; DEBUG activates some tracing output, as in the C source.
;
; QUADLONG this selects a different version of the innermost longest_match
; loop code for 68020 operations, comparing bytes four at a time
; instead of two at a time. It seems to be a tiny bit faster on
; average, but it's slower often enough that one can't generalize.
;
; This code currently assumes that function results are returned in D0 for
; all platforms. It assumes that args to functions are pushed onto the stack,
; last arg first. It also currently assumes that all C symbols have an
; underscore prepended when referenced from assembly.
;
; 1999/09/23: for Human68k: Modified by Shimazaki Ryo.
IFNDEF CPU020
IFNDEF CPUTEST
CPU000 equ 1
ENDC
ENDC
; Use these macros for accessing variables of type int:
IFDEF INT16
MOVINT MACRO _1,_2
move.w _1,_2
ENDM
CLRINT MACRO _1
clr.w _1
ENDM
INTSIZE equ 2
ELSE ; !INT16
MOVINT MACRO _1,_2
move.l _1,_2
ENDM
CLRINT MACRO _1
clr.l _1
ENDM
INTSIZE equ 4
ENDC
IFDEF DYN_ALLOC
BASEPTR MACRO _1,_2
move.l _1,_2
ENDM
ELSE
BASEPTR MACRO _1,_2
lea _1,_2
ENDM
ENDC
; constants we use, many of them adjustable:
MAX_MATCH equ 258
MIN_MATCH equ 3
TOO_FAR equ 4096
IFNDEF WSIZE
WSIZE equ 32768
ENDC
WMASK equ WSIZE-1
MAX_DIST equ WSIZE-MAX_MATCH-MIN_MATCH-1
MIN_LOOKAHEAD equ MAX_MATCH+MIN_MATCH+1
; IFD BIG_MEM ; NOT supported -- type Pos needs to be 32 bits
;HASH_BITS equ 15
; ELSE
IFDEF SMALL_MEM
HASH_BITS equ 13
ELSE
HASH_BITS equ 14 ; default -- MEDIUM_MEM
ENDC
; ENDC ; BIG_MEM
HASH_SIZE equ 1<<HASH_BITS
HASH_MASK equ HASH_SIZE-1
H_SHIFT equ (HASH_BITS+MIN_MATCH-1)/MIN_MATCH
B_SLOW equ 1
B_FAST equ 2
ZE_MEM equ 4
EOF equ -1
; struct config is defined by these offsets:
Good_length equ 0
Max_lazy equ 2
Nice_length equ 4
Max_chain equ 6
Sizeof_config equ 8
; external functions we call:
xref _ct_tally ; int ct_tally(int, int)
xref _flush_block ; unsigned long F(char *, unsigned long, int)
xref _ziperr ; void ziperr(int, char *)
xref _error ; void error(char *)
xref _calloc ; stdlib function: void *calloc(size_t, size_t)
xref _free ; stdlib function: void free(void *)
IFDEF DEBUG
xref _fputc ; stdio function: int fputc(int, FILE *)
xref _stderr ; pointer to FILE, which we pass to fputc
ENDC
; our entry points:
xdef _lm_init ; void lm_init(int level, unsigned short *flags)
xdef _lm_free ; void lm_free(void)
xdef _deflate ; void deflate(void) ...the big one
xdef _fill_window ; this line is just for debugging
; ============================================================================
; Here is where we have our global variables.
;;; section deflatevars,data
; external global variables we reference:
xref _verbose ; signed int
xref _level ; signed int
xref _read_buf ; int (*read_buf)(char *, unsigned int)
; global variables we make available:
xdef _window
xdef _prev
xdef _head
xdef _window_size
xdef _block_start
xdef _strstart
bss
quad
IFDEF DYN_ALLOC
_prev: ds.l 1 ; pointer to calloc()'d unsigned short array
_head: ds.l 1 ; pointer to calloc()'d unsigned short array
_window: ds.l 1 ; pointer to calloc()'d unsigned char array
ELSE ; !DYN_ALLOC
_prev: ds.w WSIZE ; array of unsigned short
_head: ds.w HASH_SIZE ; array of unsigned short
_window: ds.b 2*WSIZE ; array of unsigned char
ENDC ; ?DYN_ALLOC
text
quad
_window_size: ds.l 1 ; unsigned long
_block_start: ds.l 1 ; unsigned long
_strstart: ds.w INTSIZE/2 ; unsigned int
; Now here are our private variables:
IFDEF CPUTEST
is020: ds.w 1 ; bool: CPU type is '020 or higher
ENDC
ins_h: ds.w 1 ; unsigned short
sliding: ds.w 1 ; bool: the file is read a piece at a time
eofile: ds.w 1 ; bool: we have read in the end of the file
max_lazy_match: ds.w 1 ; unsigned short
lookahead: ds.w 1 ; unsigned short
; These are NOT DECLARED AS STATIC in deflate.c, but currently could be:
max_chain_len: ds.w 1 ; unsigned short (unsigned int in deflate.c)
prev_length: ds.w 1 ; unsigned short (unsigned int in deflate.c)
good_match: ds.w 1 ; unsigned short (unsigned int in deflate.c)
nice_match: ds.w 1 ; unsigned short (signed int in deflate.c)
match_start: ds.w 1 ; unsigned short (unsigned int in deflate.c)
; This array of struct config is a constant and could be in the code section:
config_table: dc.w 0,0,0,0 ; level 0: store uncompressed
dc.w 4,4,8,4 ; level 1: fastest, loosest compression
dc.w 4,5,16,8 ; level 2
dc.w 4,6,32,32 ; level 3: highest to use deflate_fast
dc.w 4,4,16,16 ; level 4: lowest to use lazy matches
dc.w 8,16,32,32 ; level 5
dc.w 8,16,128,128 ; level 6: the default level
dc.w 8,32,128,256 ; level 7
dc.w 32,128,258,1024 ; level 8
dc.w 32,258,258,4096 ; level 9: maximum compression, slow
;;CAL_SH MACRO ; macro for calling zcalloc()
;; IFD INT16
;; move.w #2,-(sp)
;; move.w #\1,-(sp)
;; jsr _zcalloc
;; addq #4,sp
;; ELSE
;; pea 2
;; pea \1
;; jsr _zcalloc
;; addq #8,sp
;; ENDC
;; ENDM
CAL_SH MACRO _1 ; Okay, we're back to using regular calloc()...
movem.l d2/a2,-(sp)
pea 2
pea _1
jsr _calloc
addq #8,sp
movem.l (sp)+,d2/a2
ENDM
; ============================================================================
; And here we begin our functions. match_init is for internal use only:
;; section deflate,code
match_init:
IFDEF CPUTEST ; now check for platform type
IFDEF AMIGA ; Amiga specific test for '020 CPU:
xref _SysBase
NOLIST
INCLUDE 'exec/execbase.i'
LIST
clr.w is020 ; default value is 68000
move.l _SysBase,a0
btst #AFB_68020,AttnFlags+1(a0)
beq.s cheap
move.w #1,is020
cheap:
ELSE ; !AMIGA
FAIL Write an '020-detector for your system here!
; On the Macintosh, I believe GetEnvironment() provides the information.
ENDC ; AMIGA
ENDC ; CPUTEST
rts ; match_init consists only of rts if CPUTEST unset
; ============================================================================
; Here is longest_match(), the function that the rest of this was built up
; from, the hottest hot spot in the program and therefore the most heavily
; optimized. It has two different versions, one for '020 and higher CPUs, and
; one for 68000/68010. It can test at runtime which version to use if you
; create a test function in match_init for your platform. Currently such a
; test is implemented for the Amiga. It can also be assembled to use '000 or
; '020 code only.
Cur_Match reg d0 ; unsigned int, kept valid as long
Best_Len reg d1 ; unsigned int, kept valid as long
Scan_Start reg d3 ; pair of bytes
Scan_End reg d4 ; pair of bytes
Limit reg d5 ; unsigned int
Chain_Length reg d6 ; unsigned int
Scan_Test reg d7 ; counter, pair of bytes sometimes
Scan reg a0 ; pointer to unsigned char
Match reg a1 ; pointer to unsigned char
Prev_Address reg a2 ; pointer to unsigned short
Scan_Ini reg a3 ; pointer to unsigned char
Match_Ini reg a5 ; pointer to unsigned char
; Note: "pair of bytes" means the two low order bytes of the register in
; 68020 code, but means the lowest and third lowest bytes on the 68000.
SAVEREGS reg d3-d7/a2/a3/a5 ; don't protect d0/d1/a0/a1
; d2, a4, a6 not used... on Amiga, a4 is used by small-data memory model
longest_match:
movem.l SAVEREGS,-(sp)
; setup steps common to byte and word versions:
IFDEF INT16
and.l #$0000FFFF,Cur_Match ; upper half must be zero!
; we use an and.l down here for the sake of ATSIGN/REGARGS.
moveq #0,Limit ; so adding to Scan_Ini works
ENDC
move.w (max_chain_len,pc),Chain_Length
move.w (prev_length,pc),Best_Len
MOVINT (_strstart,pc),Limit
BASEPTR _prev,Prev_Address
BASEPTR _window,Match_Ini
move.l Match_Ini,Scan_Ini
addq #MIN_MATCH,Match_Ini ; optimizes inner loop
add.l Limit,Scan_Ini
sub.w #MAX_DIST,Limit
bhi.s limit_ok
moveq #0,Limit
limit_ok:
cmp.w (good_match,pc),Best_Len
blo.s length_ok
lsr.w #2,Chain_Length
length_ok:
subq.w #1,Chain_Length
IFDEF CPUTEST
tst.w is020 ; can we use '020 stuff today?
bne WORD_match
ENDC
IFNDEF CPU020
; for 68000 or 68010, use byte operations:
moveq #0,Scan_Start ; clear 2nd & 4th bytes, use 1st & 3rd
moveq #0,Scan_End ; likewise
moveq #0,Scan_Test ; likewise
move.b (Scan_Ini),Scan_Start
swap Scan_Start ; swap is faster than 8 bit shift
move.b 1(Scan_Ini),Scan_Start
move.b -1(Scan_Ini,Best_Len.w),Scan_End
swap Scan_End
move.b 0(Scan_Ini,Best_Len.w),Scan_End
bra.s bdo_scan
blong_loop:
move.b -1(Scan_Ini,Best_Len.w),Scan_End
swap Scan_End
move.b 0(Scan_Ini,Best_Len.w),Scan_End
bshort_loop:
add.w Cur_Match,Cur_Match ; assert value before doubling < 32K
IFNE 32768-WSIZE
and.w #(WMASK*2),Cur_Match
ENDC
move.w (Prev_Address,Cur_Match.l),Cur_Match
cmp.w Limit,Cur_Match
dbls Chain_Length,bdo_scan
bra return
bdo_scan:
move.l Match_Ini,Match
add.l Cur_Match,Match
move.b -MIN_MATCH-1(Match,Best_Len.w),Scan_Test
swap Scan_Test
move.b -MIN_MATCH(Match,Best_Len.w),Scan_Test
cmp.l Scan_Test,Scan_End
bne.s bshort_loop
move.b -MIN_MATCH(Match),Scan_Test
swap Scan_Test
move.b -MIN_MATCH+1(Match),Scan_Test
cmp.l Scan_Test,Scan_Start
bne.s bshort_loop
move.w #(MAX_MATCH-3),Scan_Test
lea MIN_MATCH(Scan_Ini),Scan ; offset optimizes inner loop
bscan_loop:
cmp.b (Match)+,(Scan)+
dbne Scan_Test,bscan_loop
subq #1,Scan
sub.l Scan_Ini,Scan ; assert difference is 16 bits
cmp.w Best_Len,Scan
bls.s bshort_loop
MOVINT Scan,Best_Len
move.w Cur_Match,match_start
cmp.w (nice_match,pc),Best_Len
blo.s blong_loop
IFDEF CPUTEST
bra return
ENDC
ENDC ; !CPU020
IFNDEF CPU000
;;; MACHINE MC68020
; for 68020 or higher, use word operations even on odd addresses:
WORD_match:
move.w (Scan_Ini),Scan_Start
move.w -1(Scan_Ini,Best_Len.w),Scan_End
bra.s wdo_scan
wlong_loop:
move.w -1(Scan_Ini,Best_Len.w),Scan_End
wshort_loop:
and.w #WMASK,Cur_Match
move.w (Prev_Address,Cur_Match.w*2),Cur_Match ; '020 addressing mode
cmp.w Limit,Cur_Match
dbls Chain_Length,wdo_scan
bra.s return
wdo_scan:
move.l Match_Ini,Match
add.l Cur_Match,Match
cmp.w -MIN_MATCH-1(Match,Best_Len.w),Scan_End
bne.s wshort_loop
cmp.w -MIN_MATCH(Match),Scan_Start
bne.s wshort_loop
IFDEF QUADLONG
; By some measurements, this version of the code is a little tiny bit faster.
; But on some files it's slower. It probably pays off only when there are
; long match strings, and costs in the most common case of three-byte matches.
moveq #((MAX_MATCH-MIN_MATCH)/16),Scan_Test ; value = 15
lea MIN_MATCH(Scan_Ini),Scan ; offset optimizes inner loop
wscan_loop:
cmp.l (Match)+,(Scan)+ ; test four bytes at a time
bne.s odd
cmp.l (Match)+,(Scan)+
bne.s odd
cmp.l (Match)+,(Scan)+
bne.s odd
cmp.l (Match)+,(Scan)+
dbne Scan_Test,wscan_loop ; '020 can cache a bigger loop
odd:
subq #4,Scan
subq #4,Match
cmp.b (Match)+,(Scan)+ ; find good bytes in bad longword
bne.s even
cmp.b (Match)+,(Scan)+
bne.s even
cmp.b (Match)+,(Scan)+
beq.s steven
even: subq #1,Scan
ELSE ; !QUADLONG
moveq #((MAX_MATCH-MIN_MATCH)/2),Scan_Test ; value = 127
lea MIN_MATCH(Scan_Ini),Scan ; offset optimizes inner loop
wscan_loop:
cmp.w (Match)+,(Scan)+
dbne Scan_Test,wscan_loop
subq #2,Scan
move.b -2(Match),Scan_Test
cmp.b (Scan),Scan_Test
bne.s steven
addq #1,Scan
ENDC ; ?QUADLONG
steven:
sub.l Scan_Ini,Scan ; assert: difference is 16 bits
cmp.w Best_Len,Scan
bls.s wshort_loop
MOVINT Scan,Best_Len
move.w Cur_Match,match_start
cmp.w (nice_match,pc),Best_Len
blo.s wlong_loop
;;; MACHINE MC68000
ENDC ; !CPU000
return:
MOVINT Best_Len,d0 ; return value (upper half should be clear)
movem.l (sp)+,SAVEREGS
rts
; =============================================================================
; This is the deflate() function itself, our main entry point. It calls
; longest_match, above, and some outside functions. It is a hot spot, but not
; as hot as longest_match. It uses no special '020 code.
; ================== Several macros used in deflate() and later functions:
; Arg 1 is D-reg that new ins_h value is to be left in,
; arg 2 is the byte value to be hashed into it, which must not be the same reg
UP_HASH MACRO _1,_2
move.w (ins_h,pc),_1
asl.w #H_SHIFT,_1
eor.b _2,_1
and.w #HASH_MASK,_1 ; ((ins_h << H_SHIFT) ^ c) & HASH_MASK
move.w _1,ins_h ; ins_h = that
ENDM
; Arg 1 is scratch A, arg 2 is scratch D
IN_STR MACRO _1,_2
move.l Strst,_2
addq.w #MIN_MATCH-1,_2
move.b (Window,_2.l),_2 ; window[strstart + MIN_MATCH - 1]
UP_HASH Head,_2
add.l Head,Head ; assert upper word is zero before add
BASEPTR _head,_1
add.l Head,_1
move.w (_1),Head ; hash_head = head[ins_h]
move.w Strst,(_1) ; head[ins_h] = strstart
move.l Strst,_2
IFNE WSIZE-32768
and.w #WMASK,_2
ENDC
add.w _2,_2 ; masks implicitly when WSIZE == 32768
move.w Head,(Prev,_2.l) ; prev[str_start & WMASK] = hash_head
ENDM
; Arg 1 is bool (int) EOF flag, flush_block result is in d0, trashes d1/a0/a1
FLUSH_B MACRO _1
local nenu,nun
movem.l d2/a2,-(sp)
IF _1==0
CLRINT -(sp)
ELSEIF (INTSIZE==4).and.(_1<$8000)
pea (_1).w
ELSE
MOVINT #_1,-(sp)
ENDC
move.l (_block_start,pc),d0
blt.s nenu
move.l Window,a0
add.l d0,a0
bra.s nun
nenu: sub.l a0,a0 ; if block_start < 0, push NULL
nun: sub.l Strst,d0
neg.l d0
move.l d0,-(sp)
move.l a0,-(sp)
jsr _flush_block
lea 8+INTSIZE(sp),sp
movem.l (sp)+,d2/a2
ENDM
; This expands to nothing unless DEBUG is defined.
; Arg 1 is a byte to be trace-outputted -- if it is d0 it must be a valid int
TRACE_C MACRO _1
local qui
IFDEF DEBUG
cmp.w #1,_verbose+INTSIZE-2 ; test lower word only
ble.s qui
moveq #0,d0
move.b ea,d0
movem.l d2/a2,-(sp)
move.l _stderr,-(sp)
MOVINT d0,-(sp)
jsr _fputc
addq.l #4+INTSIZE,sp
movem.l (sp)+,d2/a2
qui:
ENDC ; DEBUG
ENDM
; ================== Here are the register vars we use, and deflate() itself:
Window reg a2 ; cached address of window[]
Prev reg a3 ; cached address of prev[]
Strst reg d7 ; strstart cached as a longword
Look reg d6 ; lookahead cached as short
Head reg d5 ; local variable hash_head, short
PrevL reg d4 ; prev_length cached as short
MatchL reg d3 ; local variable match_length, unsigned short
Avail reg d2 ; local variable available_match, bool
PrevM reg a5 ; local variable prev_match, int in an A-reg
DEFREGS reg d3-d7/a3/a5
_deflate: ; first, setup steps common to deflate and deflate_fast:
movem.l DEFREGS,-(sp)
IFDEF INT16
moveq #0,Strst ; make sure strstart is valid as a long
ENDC
moveq #0,Head ; ditto for hash_head
MOVINT (_strstart,pc),Strst
move.w (lookahead,pc),Look
move.w (prev_length,pc),PrevL
BASEPTR _window,Window
BASEPTR _prev,Prev
MOVINT _level,d0
cmp.w #3,d0
ble deflate_fast
moveq #MIN_MATCH-1,MatchL
moveq #0,Avail
look_loop:
tst.w Look
beq last_tally
IN_STR a0,d0
move.w MatchL,PrevL
move.w (match_start,pc),PrevM
move.w #MIN_MATCH-1,MatchL
tst.w Head
beq.s no_new_match
cmp.w (max_lazy_match,pc),PrevL
bhs.s no_new_match
move.w Strst,d0
sub.w Head,d0
cmp.w #MAX_DIST,d0
bhi.s no_new_match
move.w PrevL,prev_length ; longest_match reads these variables
MOVINT Strst,_strstart
MOVINT Head,d0 ; parm for longest_match
bsr longest_match ; sets match_start
cmp.w Look,d0 ; does length exceed valid data?
bls.s stml
move.w Look,d0
stml: move.w d0,MatchL ; valid length of match
cmp.w #MIN_MATCH,MatchL ; is the match only three bytes?
bne.s no_new_match
move.w (match_start,pc),d0
sub.w Strst,d0
cmp.w #-TOO_FAR,d0
bge.s no_new_match
moveq #MIN_MATCH-1,MatchL ; mark the current match as no good
no_new_match:
cmp.w #MIN_MATCH,PrevL
blo literal
cmp.w MatchL,PrevL
blo literal
; CHECK_MATCH Strst-1,PrevM,PrevL
MOVINT Strst,_strstart ; ct_tally reads this variable
move.l PrevL,d0
subq.w #MIN_MATCH,d0
movem.l d2/a2,-(sp)
MOVINT d0,-(sp)
move.l Strst,d0
sub.w PrevM,d0
subq.w #1,d0
MOVINT d0,-(sp)
jsr _ct_tally ; sets d0 true if we have to flush
addq #2*INTSIZE,sp
movem.l (sp)+,d2/a2
subq.w #3,PrevL ; convert for dbra (prev_length - 2)
sub.w PrevL,Look
subq.w #2,Look
insertmatch:
addq.w #1,Strst
IN_STR a0,d1 ; don't clobber d0
dbra PrevL,insertmatch
moveq #0,Avail
moveq #0,PrevL ; not needed?
moveq #MIN_MATCH-1,MatchL
addq.w #1,Strst
tst.w d0
beq refill
FLUSH_B 0
move.l Strst,_block_start
bra.s refill
literal:
tst.w Avail
bne.s yeslit
moveq #1,Avail
bra.s skipliteral
yeslit: TRACE_C <-1(Window,Strst.l)>
MOVINT Strst,_strstart ; ct_tally reads this variable
moveq #0,d0
move.b -1(Window,Strst.l),d0
movem.l d2/a2,-(sp)
MOVINT d0,-(sp)
CLRINT -(sp)
jsr _ct_tally
addq #2*INTSIZE,sp
movem.l (sp)+,d2/a2
tst.w d0
beq.s skipliteral
FLUSH_B 0
move.l Strst,_block_start
skipliteral:
addq.w #1,Strst
subq.w #1,Look
refill:
cmp.w #MIN_LOOKAHEAD,Look
bhs look_loop
bsr fill_window
bra look_loop
last_tally:
tst.w Avail
beq last_flush
MOVINT Strst,_strstart ; ct_tally reads this variable
moveq #0,d0
move.b -1(Window,Strst.l),d0
movem.l d2/a2,-(sp)
MOVINT d0,-(sp)
CLRINT -(sp)
jsr _ct_tally
addq #2*INTSIZE,sp
movem.l (sp)+,d2/a2
last_flush:
FLUSH_B 1
bra deflate_exit
; ================== This is another version used for low compression levels:
deflate_fast:
moveq #0,MatchL
moveq #MIN_MATCH-1,PrevL
flook_loop:
tst.w Look
beq flast_flush
IN_STR a0,d0
tst.w Head
beq.s fno_new_match
move.w Strst,d0
sub.w Head,d0
cmp.w #MAX_DIST,d0
bhi.s fno_new_match
move.w PrevL,prev_length ; longest_match reads these variables
MOVINT Strst,_strstart
MOVINT Head,d0 ; parm for longest_match
bsr longest_match ; sets match_start
cmp.w Look,d0 ; does length exceed valid data?
bls.s fstml
move.w Look,d0
fstml: move.w d0,MatchL ; valid length of match
fno_new_match:
cmp.w #MIN_MATCH,MatchL
blo fliteral
; CHECK_MATCH Strst,match_start,MatchL
MOVINT Strst,_strstart ; ct_tally reads this variable
move.l MatchL,d0
subq.w #MIN_MATCH,d0
movem.l d2/a2,-(sp)
MOVINT d0,-(sp)
move.l Strst,d0
sub.w (match_start,pc),d0
MOVINT d0,-(sp)
jsr _ct_tally ; sets d0 true if we have to flush
addq #2*INTSIZE,sp
movem.l (sp)+,d2/a2
sub.w MatchL,Look
cmp.w (max_lazy_match,pc),MatchL
bhi ftoolong
subq.w #2,MatchL
finsertmatch:
addq.w #1,Strst
IN_STR a0,d1 ; preserve d0
dbra MatchL,finsertmatch
moveq #0,MatchL ; not needed?
addq.w #1,Strst
bra.s flushfill
ftoolong:
add.w MatchL,Strst
moveq #0,MatchL
moveq #0,d1 ; preserve d0
move.b (Window,Strst.l),d1
move.w d1,ins_h
; My assembler objects to passing <1(Window,Strst.l)> directly to UP_HASH...
move.b 1(Window,Strst.l),Avail ; Avail is not used in deflate_fast
UP_HASH d1,Avail ; preserve d0
IFNE MIN_MATCH-3
FAIL needs to UP_HASH another MIN_MATCH-3 times, but with what arg?
ENDC
bra.s flushfill
fliteral:
TRACE_C <(Window,Strst.l)>
MOVINT Strst,_strstart ; ct_tally reads this variable
moveq #0,d0
move.b (Window,Strst.l),d0
movem.l d2/a2,-(sp)
MOVINT d0,-(sp)
CLRINT -(sp)
jsr _ct_tally ; d0 set if we need to flush
addq #2*INTSIZE,sp
movem.l (sp)+,d2/a2
addq.w #1,Strst
subq.w #1,Look
flushfill:
tst.w d0
beq.s frefill
FLUSH_B 0
move.l Strst,_block_start
frefill:
cmp.w #MIN_LOOKAHEAD,Look
bhs flook_loop
bsr fill_window
bra flook_loop
flast_flush:
FLUSH_B 1 ; sets our return value
deflate_exit:
MOVINT Strst,_strstart ; save back cached values
move.w PrevL,prev_length
move.w Look,lookahead
movem.l (sp)+,DEFREGS
rts
; =========================================================================
; void fill_window(void) calls the input function to refill the sliding
; window that we use to find substring matches in.
More reg Head ; local variable in fill_window
WindTop reg Prev ; local variable used for sliding
SlidIx reg PrevL ; local variable used for sliding
FWREGS reg d2-d5/a2-a6 ; does NOT include Look and Strst
; all registers available to be clobbered by the sliding operation:
; we exclude More, WindTop, SlidIx, Look, Strst, Window, a4 and a7.
SPAREGS reg d0-d3/a0-a1/a5-a6
SPCOUNT equ 8 ; number of registers in SPAREGS
_fill_window: ; C-callable entry point
movem.l Look/Strst,-(sp)
IFDEF INT16
moveq #0,Strst ; Strst must be valid as a long
ENDC
MOVINT (_strstart,pc),Strst
move.w (lookahead,pc),Look
BASEPTR _window,Window
bsr.s fill_window
MOVINT Strst,_strstart
move.w Look,lookahead
movem.l (sp)+,Look/Strst
rts
; strstart, lookahead, and window must be cached in Strst, Look, and Window:
fill_window: ; asm-callable entry point
movem.l FWREGS,-(sp)
move.w (eofile,pc),d0 ; we put this up here for speed
bne fwdone
and.l #$FFFF,Look ; make sure Look is valid as long
fw_refill:
move.l (_window_size,pc),More ; <= 64K
sub.l Look,More
sub.l Strst,More ; Strst is already valid as long
cmp.w #EOF,More
bne.s notboundary
subq.w #1,More
bra checkend
notboundary:
move.w (sliding,pc),d0
beq checkend
cmp.w #WSIZE+MAX_DIST,Strst
blo checkend
IF (32768-WSIZE)>0
lea WSIZE(Window),WindTop ; WindTop is aligned when Window is
ELSE
move.l Window,WindTop
add.l #WSIZE,WindTop
ENDC
move.l Window,d0
and.w #3,d0
beq.s isaligned
subq.w #1,d0
align: move.b (WindTop)+,(Window)+ ; copy up to a longword boundary
dbra d0,align
isaligned:
; This is faster than a simple move.l (WindTop)+,(Window)+ / dbra loop:
move.w #(WSIZE-1)/(4*SPCOUNT),SlidIx
slide: movem.l (WindTop)+,SPAREGS ; copy, 32 bytes at a time!
movem.l SPAREGS,(Window) ; a slight overshoot doesn't matter.
lea 4*SPCOUNT(Window),Window ; can't use (aN)+ as movem.l dest
dbra SlidIx,slide
BASEPTR _window,Window ; restore cached value
sub.w #WSIZE,match_start
sub.w #WSIZE,Strst
sub.l #WSIZE,_block_start
add.w #WSIZE,More
BASEPTR _head,a0
move.w #HASH_SIZE-1,d0
fixhead:
move.w (a0),d1
sub.w #WSIZE,d1
bpl.s headok
moveq #0,d1
headok: move.w d1,(a0)+
dbra d0,fixhead
BASEPTR _prev,a0
move.w #WSIZE-1,d0
fixprev:
move.w (a0),d1
sub.w #WSIZE,d1
bpl.s prevok
moveq #0,d1
prevok: move.w d1,(a0)+
dbra d0,fixprev
TRACE_C #'.'
move _verbose+INTSIZE-2,d0
beq checkend
movem.l d2/a2,-(sp)
xref _print_period
jsr _print_period
movem.l (sp)+,d2/a2
checkend: ; assert eofile is false
movem.l d2/a2,-(sp)
MOVINT More,-(sp) ; assert More's upper word is zero
move.l Strst,d0
add.w Look,d0
add.l Window,d0
move.l d0,-(sp)
move.l _read_buf,a0
jsr (a0) ; refill the upper part of the window
addq #4+INTSIZE,sp
movem.l (sp)+,d2/a2
tst.w d0
beq.s iseof
cmp.w #EOF,d0
beq.s iseof
add.w d0,Look
cmp.w #MIN_LOOKAHEAD,Look
blo fw_refill ; eofile is still false
bra.s fwdone
iseof: move.w #1,eofile
fwdone: movem.l (sp)+,FWREGS
rts
; =========================================================================
; void lm_free(void) frees dynamic arrays in the DYN_ALLOC version.
;;; xdef _lm_free ; the entry point
_lm_free:
IFDEF DYN_ALLOC
move.l _window,d0
beq.s lf_no_window
movem.l d2/a2,-(sp)
move.l d0,-(sp)
jsr _free
addq #4,sp
movem.l (sp)+,d2/a2
clr.l _window
lf_no_window:
move.l _prev,d0
beq.s lf_no_prev
movem.l d2/a2,-(sp)
move.l d0,-(sp)
jsr _free
move.l _head,(sp) ; reuse the same stack arg slot
jsr _free
addq #4,sp
movem.l (sp)+,d2/a2
clr.l _prev
clr.l _head
lf_no_prev:
ENDC
rts
; ============================================================================
; void lm_init(int pack_level, unsigned short *flags) allocates dynamic arrays
; if any, and initializes all variables so that deflate() is ready to go.
;;; xdef _lm_init ; the entry point
Level reg d2
;Window reg a2 ; as in deflate()
_lm_init:
MOVINT 4(sp),d0
move.l 4+INTSIZE(sp),a0
move.w d0,Level
cmp.w #1,Level
blt.s levelerr
bgt.s try9
bset.b #B_FAST,1(a0)
try9: cmp.w #9,Level
bgt.s levelerr
blt.s levelok
bset.b #B_SLOW,1(a0)
bra.s levelok
levelerr:
pea (level_message,pc)
jsr _error ; never returns
levelok:
clr.w sliding
move.l (_window_size,pc),d0
bne.s gotawindowsize
move.w #1,sliding
move.l #2*WSIZE,_window_size
gotawindowsize:
BASEPTR _window,Window
IFDEF DYN_ALLOC
move.l Window,d0 ; fake tst.l
bne.s gotsomewind
CAL_SH WSIZE
move.l d0,Window
move.l d0,_window
bne.s gotsomewind
pea (window_message,pc)
bra error
gotsomewind:
tst.l _prev
bne.s gotsomehead
CAL_SH WSIZE
move.l d0,_prev
beq.s nohead
CAL_SH HASH_SIZE
move.l d0,_head
bne.s gotfreshhead ; newly calloc'd memory is zeroed
nohead: pea (hash_message,pc)
error: MOVINT #ZE_MEM,-(sp)
jsr _ziperr ; never returns
gotsomehead:
ENDC ; DYN_ALLOC
move.w #(HASH_SIZE/2)-1,d0 ; two shortwords per loop
BASEPTR _head,a0
wipeh: clr.l (a0)+
dbra d0,wipeh
gotfreshhead:
move.l Level,d0
IFEQ Sizeof_config-8
asl.l #3,d0
ELSE
mulu #Sizeof_config,d0
ENDC
lea (config_table,pc),a0
add.l d0,a0
move.w Max_lazy(a0),max_lazy_match
move.w Good_length(a0),good_match
move.w Nice_length(a0),nice_match
move.w Max_chain(a0),max_chain_len
CLRINT _strstart
clr.l _block_start
bsr match_init
clr.w eofile
movem.l d2/a2,-(sp)
MOVINT #WSIZE,-(sp) ; We read only 32K because lookahead is short
move.l Window,-(sp) ; even when int size is long, as if deflate.c
move.l _read_buf,a0 ; were compiled with MAXSEG_64K defined.
jsr (a0)
addq #4+INTSIZE,sp
movem.l (sp)+,d2/a2
move.w d0,lookahead
beq.s noread
cmp.w #EOF,d0
bne.s irefill
noread: move.w #1,eofile
clr.w lookahead
bra.s init_done
irefill:
move.w (lookahead,pc),d0
cmp.w #MIN_LOOKAHEAD,d0
bhs.s hashify
bsr _fill_window ; use the C-callable version
hashify:
clr.w ins_h
moveq #MIN_MATCH-2,d0
hash1: move.b (Window)+,d1
UP_HASH Level,d1
dbra d0,hash1
init_done:
rts
; strings for error messages:
IFDEF DYN_ALLOC
hash_message dc.b 'hash table allocation',0
window_message dc.b 'window allocation',0
ENDC
level_message dc.b 'bad pack level',0
end
|
wwivbbs/wwiv | 4,634 | deps/infozip/zip30/human68k/match.s | *===========================================================================
* Copyright (c) 1990-1999 Info-ZIP. All rights reserved.
*
* See the accompanying file LICENSE, version 1999-Oct-05 or later
* (the contents of which are also included in zip.h) for terms of use.
* If, for some reason, both of these files are missing, the Info-ZIP license
* also may be found at: ftp://ftp.cdrom.com/pub/infozip/license.html
*===========================================================================
*
* match.s -- optional optimized asm version of longest match in deflate.c
* Written by Jean-loup Gailly
*
* Adapted for X68000 by NIIMI Satoshi <a01309@cfi.waseda.ac.jp>
* Adapted for the Amiga by Carsten Steger <stegerc@informatik.tu-muenchen.de>
* using the code in match.S.
* The major change in this code consists of removing all unaligned
* word accesses, because they cause 68000-based machines to crash.
* For maximum speed, UNALIGNED_OK can be defined.
* The program will then only run on 68020-based machines, though.
Cur_Match reg d0 ; Must be in d0!
Best_Len reg d1
Loop_Counter reg d2
Scan_Start reg d3
Scan_End reg d4
Limit reg d5
Chain_Length reg d6
Scan_Test reg d7
Scan reg a0
Match reg a1
Prev_Address reg a2
Scan_Ini reg a3
Match_Ini reg a4
MAX_MATCH equ 258
MIN_MATCH equ 3
WSIZE equ 32768
MAX_DIST equ WSIZE-MAX_MATCH-MIN_MATCH-1
.xref _max_chain_length
.xref _prev_length
.xref _prev
.xref _window
.xref _strstart
.xref _good_match
.xref _match_start
.xref _nice_match
.xdef _match_init
.xdef _longest_match
.text
.even
_match_init:
rts
_longest_match:
move.l 4(sp),Cur_Match
.ifdef UNALIGNED_OK
movem.l d2-d6/a2-a4,-(sp)
.else
movem.l d2-d7/a2-a4,-(sp)
.endif
move.l _max_chain_length,Chain_Length
move.l _prev_length,Best_Len
lea _prev,Prev_Address
lea _window+MIN_MATCH,Match_Ini
move.l _strstart,Limit
move.l Match_Ini,Scan_Ini
add.l Limit,Scan_Ini
subi.w #MAX_DIST,Limit
bhi.b limit_ok
moveq #0,Limit
limit_ok:
cmp.l _good_match,Best_Len
bcs.b length_ok
lsr.l #2,Chain_Length
length_ok:
subq.l #1,Chain_Length
.ifdef UNALIGNED_OK
move.w -MIN_MATCH(Scan_Ini),Scan_Start
move.w -MIN_MATCH-1(Scan_Ini,Best_Len.w),Scan_End
.else
move.b -MIN_MATCH(Scan_Ini),Scan_Start
lsl.w #8,Scan_Start
move.b -MIN_MATCH+1(Scan_Ini),Scan_Start
move.b -MIN_MATCH-1(Scan_Ini,Best_Len.w),Scan_End
lsl.w #8,Scan_End
move.b -MIN_MATCH(Scan_Ini,Best_Len.w),Scan_End
.endif
bra.b do_scan
long_loop:
.ifdef UNALIGNED_OK
move.w -MIN_MATCH-1(Scan_Ini,Best_Len.w),Scan_End
.else
move.b -MIN_MATCH-1(Scan_Ini,Best_Len.w),Scan_End
lsl.w #8,Scan_End
move.b -MIN_MATCH(Scan_Ini,Best_Len.w),Scan_End
.endif
short_loop:
lsl.w #1,Cur_Match
move.w 0(Prev_Address,Cur_Match.l),Cur_Match
cmp.w Limit,Cur_Match
dbls Chain_Length,do_scan
bra.b return
do_scan:
move.l Match_Ini,Match
add.l Cur_Match,Match
.ifdef UNALIGNED_OK
cmp.w -MIN_MATCH-1(Match,Best_Len.w),Scan_End
bne.b short_loop
cmp.w -MIN_MATCH(Match),Scan_Start
bne.b short_loop
.else
move.b -MIN_MATCH-1(Match,Best_Len.w),Scan_Test
lsl.w #8,Scan_Test
move.b -MIN_MATCH(Match,Best_Len.w),Scan_Test
cmp.w Scan_Test,Scan_End
bne.b short_loop
move.b -MIN_MATCH(Match),Scan_Test
lsl.w #8,Scan_Test
move.b -MIN_MATCH+1(Match),Scan_Test
cmp.w Scan_Test,Scan_Start
bne.b short_loop
.endif
move.w #(MAX_MATCH-MIN_MATCH),Loop_Counter
move.l Scan_Ini,Scan
scan_loop:
cmpm.b (Match)+,(Scan)+
dbne Loop_Counter,scan_loop
sub.l Scan_Ini,Scan
addq.l #(MIN_MATCH-1),Scan
cmp.l Best_Len,Scan
bls.b short_loop
move.l Scan,Best_Len
move.l Cur_Match,_match_start
cmp.l _nice_match,Best_Len
bcs.b long_loop
return:
move.l Best_Len,d0
.ifdef UNALIGNED_OK
movem.l (sp)+,d2-d6/a2-a4
.else
movem.l (sp)+,d2-d7/a2-a4
.endif
rts
end
|
wwivbbs/wwiv | 5,199 | deps/infozip/unzip60/acorn/swiven.s | ;===========================================================================
; Copyright (c) 1990-2000 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in unzip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
; SWI veneers used by Zip/Unzip
;
r0 RN 0
r1 RN 1
r2 RN 2
r3 RN 3
r4 RN 4
r5 RN 5
r6 RN 6
r7 RN 7
r8 RN 8
r9 RN 9
r10 RN 10
r11 RN 11
r12 RN 12
sp RN 13
lr RN 14
pc RN 15
sl RN 10
fp RN 11
ip RN 12
XOS_Bit EQU &020000
OS_GBPB EQU &00000C
OS_File EQU &000008
OS_FSControl EQU &000029
OS_CLI EQU &000005
OS_ReadC EQU &000004
OS_ReadVarVal EQU &000023
DDEUtils_Prefix EQU &042580
Territory_ReadCurrentTimeZone EQU &043048
MimeMap_Translate EQU &050B00
MACRO
STARTCODE $name
EXPORT $name
$name
MEND
AREA |C$$code|, CODE, READONLY
; os_error *SWI_OS_FSControl_26(char *source, char *dest, int actionmask);
STARTCODE SWI_OS_FSControl_26
MOV ip, lr
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #26
SWI OS_FSControl + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; os_error *SWI_OS_FSControl_27(char *filename, int actionmask);
STARTCODE SWI_OS_FSControl_27
MOV ip, lr
MOV r3, r1
MOV r1, r0
MOV r0, #27
SWI OS_FSControl + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; os_error *SWI_OS_GBPB_9(char *dirname, void *buf, int *number,
; int *offset, int size, char *match);
STARTCODE SWI_OS_GBPB_9
MOV ip, sp
STMFD sp!, {r2-r6,lr}
LDMIA ip, {r5,r6}
LDR r4, [r3]
LDR r3, [r2]
MOV r2, r1
MOV r1, r0
MOV r0, #9
SWI OS_GBPB + XOS_Bit
LDMVSFD sp!, {r2-r6,pc}^
MOV r0, #0
LDMFD sp, {r5,r6}
STR r3, [r5]
STR r4, [r6]
LDMFD sp!, {r2-r6,pc}^
; os_error *SWI_OS_File_1(char *filename, int loadaddr, int execaddr, int attrib);
STARTCODE SWI_OS_File_1
STMFD sp!, {r5,lr}
MOV r5, r3
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #1
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r5,pc}^
; os_error *SWI_OS_File_5(char *filename, int *objtype, int *loadaddr,
; int *execaddr, int *length, int *attrib);
STARTCODE SWI_OS_File_5
STMFD sp!, {r1-r5,lr}
MOV r1, r0
MOV r0, #5
SWI OS_File + XOS_Bit
LDMVSFD sp!, {r1-r5,pc}^
LDR lr, [sp]
TEQ lr, #0
STRNE r0, [lr]
LDR lr, [sp, #4]
TEQ lr ,#0
STRNE r2, [lr]
LDR lr, [sp, #8]
TEQ lr, #0
STRNE r3, [lr]
LDR lr, [sp ,#24]
TEQ lr, #0
STRNE r4, [lr]
LDR lr, [sp ,#28]
TEQ lr, #0
STRNE r5, [lr]
MOV r0, #0
LDMFD sp!, {r1-r5,pc}^
; os_error *SWI_OS_File_6(char *filename);
STARTCODE SWI_OS_File_6
STMFD sp!, {r4-r5,lr}
MOV r1, r0
MOV r0, #6
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r4-r5,pc}^
; os_error *SWI_OS_File_7(char *filename, int loadaddr, int execaddr, int size);
STARTCODE SWI_OS_File_7
STMFD sp!, {r4-r5,lr}
MOV r5, r3
MOV r4, #0
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #7
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r4-r5,pc}^
; os_error *SWI_OS_File_8(char *dirname);
STARTCODE SWI_OS_File_8
STMFD sp!, {r4,lr}
MOV r1, r0
MOV r4, #0
MOV r0, #8
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r4,pc}^
; os_error *SWI_OS_File_18(char *filename, int filetype);
STARTCODE SWI_OS_File_18
STMFD sp!, {r4-r5,lr}
MOV r2, r1
MOV r1, r0
MOV r0, #18
SWI OS_File + XOS_Bit
MOVVC r0, #0
LDMFD sp!, {r4-r5,pc}^
; os_error *SWI_OS_CLI(char *cmd);
STARTCODE SWI_OS_CLI
MOV ip, lr
SWI OS_CLI + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; int SWI_OS_ReadC(void);
STARTCODE SWI_OS_ReadC
MOV ip, lr
SWI OS_ReadC + XOS_Bit
MOVS pc, ip
; os_error *SWI_OS_ReadVarVal(char *var, char *buf, int len, int *bytesused);
STARTCODE SWI_OS_ReadVarVal
STMFD sp!, {r4,lr}
MOV ip, r3
MOV r3, #0
MOV r4, #0
SWI OS_ReadVarVal + XOS_Bit
LDMVSFD sp!, {r4,pc}^
TEQ ip, #0
STRNE r2, [ip]
MOV r0, #0
LDMFD sp!, {r4,pc}^
; os_error *SWI_OS_FSControl_54(char *buffer, int dir, char *fsname, int *size);
STARTCODE SWI_OS_FSControl_54
STMFD sp!, {r3-r6,lr}
LDR r5, [r3]
MOV r3, r2
MOV r2, r1
MOV r1, r0
MOV r0, #54
SWI OS_FSControl + XOS_Bit
LDMVSFD sp!, {r3-r6,pc}^
MOV r0, #0
LDMFD sp!, {r3}
STR r5, [r3]
LDMFD sp!, {r4-r6,pc}^
; os_error *SWI_OS_FSControl_37(char *pathname, char *buffer, int *size);
STARTCODE SWI_OS_FSControl_37
STMFD sp!, {r2,r3-r5,lr}
LDR r5, [r2]
MOV r3, #0
MOV r4, #0
MOV r2, r1
MOV r1, r0
MOV r0, #37
SWI OS_FSControl + XOS_Bit
LDMVSFD sp!, {r2,r3-r5,pc}^
MOV r0, #0
LDMFD sp!, {r2}
STR r5, [r2]
LDMFD sp!, {r3-r5,pc}^
; os_error *SWI_DDEUtils_Prefix(char *dir);
STARTCODE SWI_DDEUtils_Prefix
MOV ip, lr
SWI DDEUtils_Prefix + XOS_Bit
MOVVC r0, #0
MOVS pc, ip
; int SWI_Read_Timezone(void);
STARTCODE SWI_Read_Timezone
MOV ip, lr
SWI Territory_ReadCurrentTimeZone + XOS_Bit
MOVVC r0, r1
MOVVS r0, #0
MOVS pc, ip
; int SWI_MimeMap_Translate(char *ext);
STARTCODE SWI_MimeMap_Translate
MOV ip,lr
MOV r1, r0
MOV r0, #3
MOV r2, #0
SWI MimeMap_Translate + XOS_Bit
MOVVC r0, r3
MVNVS r0, #0 ; return -1 on error
MOVS pc, ip
END
|
wwivbbs/wwiv | 3,087 | deps/infozip/unzip60/qdos/config.S | #
;===========================================================================
; Copyright (c) 1990-2000 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in unzip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
.globl _qlflag
.globl _qlwait
#ifdef ZIP
.globl _dtype
#endif
.data
ds.w 0
dc.b '<<QCFX>>01'
#ifdef ZIP
dc.w 8
dc.b 'Info-ZIP'
* 12345678901234567890
ds.w 0
dc.w 3
dc.b '?.?'
ds.w 0
#else
dc.w 10
dc.b 'Info-UNZIP'
* 12345678901234567890
ds.w 0
dc.w 3
dc.b '?.?'
ds.w 0
#endif
dc.b 10
dc.b 0
l_4: dc.w _qlwait-l_4
dc.w 0
dc.w 0
l_5: dc.w hpt-l_5
l_6: dc.w hxx-l_6
#ifdef ZIP
dc.b 10
dc.b 0
d_4: dc.w _dtype-d_4
dc.w 0
dc.w 0
d_5: dc.w dpt-d_5
d_6: dc.w dxx-d_6
#else
dc.b 4
dc.b 0
l5:
dc.w list1-l5
dc.w 0
l5a:
dc.w Postit-l5a ; post proc
l6:
dc.w apt-l6
l7:
dc.w axx-l7
* -------------------------------------
dc.b 4
dc.b 0
l8:
dc.w list2-l8
dc.w 0
l8a:
dc.w Postit-l8a ; post proc
l9:
dc.w bpt-l9
la:
dc.w bxx-la
* -------------------------------------
#endif
dc.w -1 ; end
_qlflag:
dc.w 0
_qlwait:
dc.w 250
_dtype:
dc.w 255
hpt: dc.w 10
dc.b 'Exit Delay'
* 12345678901234567890
ds.w 0
hxx: dc.w 0
dc.w $ffff
dc.w -1
#ifdef ZIP
dpt: dc.w 14
dc.b 'Directory Type'
* 12345678901234567890
ds.w 0
dxx: dc.w 3
dc.w $ff
dc.w -1
#else
list1:
dc.b 0
list2:
dc.b 0
apt:
dc.w 11
dc.b 'Unpack Mode'
* 12345678901234567890
.even
axx: dc.b 0
dc.b 0
dc.w 8
dc.b 'SMS/QDOS'
.even
dc.b 1
dc.b 0
dc.w 7
dc.b 'Default'
.even
dc.w -1
.even
bpt:
dc.w 12
dc.b 'Listing Mode'
* 12345678901234567890
.even
bxx:
dc.w 0
dc.w 7
dc.b 'Default'
.even
dc.b 2
dc.b 0
dc.w 8
dc.b 'SMS/QDOS'
* 12345678901234567890
.even
dc.w -1
Postit:
lea.l _qlflag,a0
move.b list1,d0
move.b d0,(a0)
move.b list2,d0
or.b d0,(a0)
moveq #0,d0
rts
#endif
end
|
wwivbbs/wwiv | 2,523 | deps/infozip/unzip60/qdos/crc68.s | ;===========================================================================
; Copyright (c) 1990-2000 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
.text
.globl _crc32 ; (ulg val, uch *buf, extent bufsize)
.globl _get_crc_table ; ulg *get_crc_table(void)
_crc32:
move.l 8(sp),d0
bne valid
moveq #0,d0
rts
valid: movem.l d2/d3,-(sp)
jsr _get_crc_table
move.l d0,a0
move.l 12(sp),d0
move.l 16(sp),a1
move.l 20(sp),d1
not.l d0
move.l d1,d2
lsr.l #3,d1
bra decr8
loop8: moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
decr8: dbra d1,loop8
and.w #7,d2
bra decr1
loop1: moveq #0,d3
move.b (a1)+,d3
eor.b d0,d3
lsl.w #2,d3
move.l 0(a0,d3.w),d3
lsr.l #8,d0
eor.l d3,d0
decr1: dbra d2,loop1
done: movem.l (sp)+,d2/d3
not.l d0
rts
|
wwivbbs/wwiv | 4,143 | deps/infozip/unzip60/human68k/crc_68.s | ;===========================================================================
; Copyright (c) 1990-2000 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in zip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
; crc_68 created by Paul Kienitz, last modified 04 Jan 96.
;
; Return an updated 32 bit CRC value, given the old value and a block of data.
; The CRC table used to compute the value is gotten by calling get_crc_table().
; This replaces the older updcrc() function used in Zip and fUnZip. The
; prototype of the function is:
;
; ulg crc32(ulg crcval, uch *text, extent textlen);
;
; On the Amiga, type extent is always unsigned long, not unsigned int, because
; int can be short or long at whim, but size_t is long.
;
; If using this source on a non-Amiga 680x0 system, note that we treat
; a0/a1/d0/d1 as scratch registers not preserved across function calls.
; We do not bother to support registerized arguments for crc32() -- the
; textlen parm is usually large enough so that savings outside the loop
; are pointless.
;
; Define NO_UNROLLED_LOOPS to use a simple short loop which might be more
; efficient on certain machines with dinky instruction caches ('020?), or for
; processing short strings. If loops are unrolled, the textlen parm must be
; less than 512K; if not unrolled, it must be less than 64K.
;
; 1999/09/23: for Human68k: Modified by Shimazaki Ryo.
xdef _crc32 ; (ulg val, uch *buf, extent bufsize)
DO_CRC0 MACRO
moveq #0,ltemp
move.b (textbuf)+,ltemp
eor.b crcval,ltemp
lsl.w #2,ltemp
move.l (crc_table,ltemp.w),ltemp
lsr.l #8,crcval
eor.l ltemp,crcval
ENDM
DO_CRC2 MACRO
move.b (textbuf)+,btemp
eor.b crcval,btemp
lsr.l #8,crcval
move.l (crc_table,btemp.w*4),ltemp
eor.l ltemp,crcval
ENDM
crc_table reg a0 array of unsigned long
crcval reg d0 unsigned long initial value
textbuf reg a1 array of unsigned char
textbufsize reg d1 unsigned long (count of bytes in textbuf)
btemp reg d2
ltemp reg d3
xref _get_crc_table ; ulg *get_crc_table(void)
quad
_crc32:
move.l 8(sp),d0
bne.s valid
;;;;; moveq #0,d0
rts
valid: movem.l btemp/ltemp,-(sp)
jsr _get_crc_table
movea.l d0,crc_table
move.l 12(sp),crcval
move.l 16(sp),textbuf
move.l 20(sp),textbufsize
not.l crcval
ifdef NO_UNROLLED_LOOPS
if CPU==68000
bra.s decr
loop: DO_CRC0
decr: dbra textbufsize,loop
bra.s done
else
twenty: moveq #0,btemp
bra.s decr2
loop2: DO_CRC2
decr2: dbra textbufsize,loop2
endif
ELSE ; !NO_UNROLLED_LOOPS
if CPU==68000
moveq #7,btemp
and textbufsize,btemp
lsr.l #3,textbufsize
bra decr8
loop8: DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
DO_CRC0
decr8: dbra textbufsize,loop8
bra.s decr1
loop1: DO_CRC0
decr1: dbra btemp,loop1
bra done
else
twenty: moveq #0,btemp
move.l textbufsize,-(sp)
lsr.l #3,textbufsize
bra decr82
quad
loop82: DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
DO_CRC2
decr82: dbra textbufsize,loop82
moveq #7,textbufsize
and.l (sp)+,textbufsize
bra.s decr12
loop12: DO_CRC2
decr12: dbra textbufsize,loop12
endif
ENDC ; ?NO_UNROLLED_LOOPS
done: movem.l (sp)+,btemp/ltemp
not.l crcval
;;;;; move.l crcval,d0 ; crcval already is d0
rts
|
wwivbbs/wwiv | 19,133 | deps/infozip/unzip60/human68k/flate.s | ;===========================================================================
; Copyright (c) 1990-2002 Info-ZIP. All rights reserved.
;
; See the accompanying file LICENSE, version 2000-Apr-09 or later
; (the contents of which are also included in unzip.h) for terms of use.
; If, for some reason, all these files are missing, the Info-ZIP license
; also may be found at: ftp://ftp.info-zip.org/pub/infozip/license.html
;===========================================================================
; flate.a created by Paul Kienitz, 20 June 94. Last modified 23 Mar 2002.
;
; 68000 assembly language version of inflate_codes(), for Amiga. Prototype:
;
; int inflate_codes(__GPRO__ struct huft *tl, struct huft *td,
; unsigned bl, unsigned bd);
;
; Where __GPRO__ expands to "Uz_Globs *G," if REENTRANT is defined,
; otherwise to nothing. In the latter case G is a global variable.
;
; Define the symbol FUNZIP if this is for fUnZip. It overrides REENTRANT.
;
; Define AZTEC to use the Aztec C macro version of getc() instead of the
; library getc() with FUNZIP. AZTEC is ignored if FUNZIP is not defined.
;
; Define NO_CHECK_EOF to not use the fancy paranoid version of NEEDBITS --
; this is equivalent to removing the #define CHECK_EOF from inflate.c.
;
; Define INT16 if ints are short, otherwise it assumes ints are long.
;
; Define USE_DEFLATE64 if we're supporting Deflate64 decompression.
;
; Do NOT define WSIZE; it is always 32K or 64K depending on USE_DEFLATE64.
;
; 1999/09/23: for Human68k: Modified by Shimazaki Ryo.
X: EQU $7ffe
IFDEF INT16
MOVINT MACRO _1,_2
move.w _1,_2
ENDM
INTSIZE equ 2
ELSE ; !INT16
MOVINT MACRO _1,_2
move.l _1,_2
ENDM
INTSIZE equ 4
ENDC
IFDEF REENTRANT
IFNDEF FUNZIP
REENT_G equ 1
ENDC
ENDC
; The following include file is generated from globals.h, and gives us equates
; that give the offsets in Uz_Globs of the fields we use, which are:
; ulg bb
; unsigned int bk, wp
; (either array of unsigned char, or pointer to unsigned char) redirslide
; For fUnZip:
; FILE *in
; For regular UnZip but not fUnZip:
; int incnt, mem_mode
; long csize
; uch *inptr
; It also defines a value SIZEOF_slide, which tells us whether the appropriate
; slide field in G (either area.Slide or redirect_pointer) is a pointer or an
; array instance. It is 4 in the former case and a large value in the latter.
; Lastly, this include will define CRYPT as 1 if appropriate.
IFDEF FUNZIP
INCLUDE human68k/G_offs_.mac
ELSE
IFDEF SFX
INCLUDE human68k/G_offsf.mac"
ELSE
INCLUDE human68k/G_offs.mac
ENDC
ENDC
; struct huft is defined as follows:
;
; struct huft {
; uch e; /* number of extra bits or operation */
; uch b; /* number of bits in this code or subcode */
; union {
; ush n; /* literal, length base, or distance base */
; struct huft *t; /* pointer to next level of table */
; } v;
; }; /* sizeof(struct huft) == 6 */
;
; The G_offs include defines offsets h_e, h_b, h_v_n, and h_v_t in this
; struct, plus SIZEOF_huft.
; G.bb is the global buffer that holds bits from the huffman code stream, which
; we cache in the register variable b. G.bk is the number of valid bits in it,
; which we cache in k. The macros NEEDBITS(n) and DUMPBITS(n) have side effects
; on b and k.
IFDEF REENT_G
G_SIZE equ 4
G_PUSH MACRO ; this macro passes "__G__" to functions
move.l G,-(sp)
ENDM
ELSE
xref _G ; Uz_Globs
G_SIZE equ 0
G_PUSH MACRO
ds.b 0 ; does nothing; the assembler dislikes MACRO ENDM
ENDM
ENDC ; REENT_G
;; xref _mask_bits ; const unsigned mask_bits[17];
IFDEF FUNZIP
IF CRYPT
xref _encrypted ; int -- boolean flag
xref _update_keys ; int update_keys(__GPRO__ int)
xref _decrypt_byte ; int decrypt_byte(__GPRO)
ENDC ; CRYPT
ELSE ; !FUNZIP
xref _memflush ; int memflush(__GPRO__ uch *, ulg)
xref _readbyte ; int readbyte(__GPRO)
ENDC ; FUNZIP
xref _flush ; if FUNZIP: int flush(__GPRO__ ulg)
; else: int flush(__GPRO__ uch *, ulg, int)
; Here are our register variables.
b reg d2 ; unsigned long
k reg d3 ; unsigned short <= 32
e reg d4 ; unsigned int, mostly used as unsigned char
w reg d5 ; unsigned long (was short before deflate64)
n reg d6 ; unsigned long (was short before deflate64)
d reg d7 ; unsigned int, used as unsigned short
t reg a2 ; struct huft *
lmask reg a3 ; ulg *
G reg a6 ; Uz_Globs *
; Couple other items we need:
savregs reg d2-d7/a2/a3/a6
IFDEF USE_DEFLATE64
WSIZE equ $10000 ; 64K... be careful not to treat as short!
ELSE
WSIZE equ $08000 ; 32K... be careful not to treat as negative!
ENDC
EOF equ -1
INVALID equ 99
; inflate_codes() returns one of the following status codes:
; 0 OK
; 1 internal inflate error or EOF on input stream
; the following return codes are passed through from FLUSH() errors
; 50 (PK_DISK) "overflow of output space"
; 80 (IZ_CTRLC) "canceled by user's request"
RET_OK equ 0
RET_ERR equ 1
IFDEF FUNZIP
; This does getc(in). LIBC version is based on #define getc(fp) in stdio.h
GETC MACRO
xref _fgetc ; int fgetc(FILE *)
move.l in-X(G),-(sp)
jsr _fgetc
addq.l #4,sp
ENDM
ENDC ; FUNZIP
; Input depends on the NEXTBYTE macro. This exists in three different forms.
; The first two are for fUnZip, with and without decryption. The last is for
; regular UnZip with or without decryption. The resulting byte is returned
; in d0 as a longword, and d1, a0, and a1 are clobbered.
; FLUSH also has different forms for UnZip and fUnZip. Arg must be a longword.
; The same scratch registers are trashed.
IFDEF FUNZIP
NEXTBYTE MACRO
move.l d2,-(sp)
GETC
IF CRYPT
tst.w _encrypted+INTSIZE-2 ; test low word if long
beq.s @nbe
MOVINT d0,-(sp) ; save thru next call
G_PUSH
jsr _decrypt_byte
eor.w d0,G_SIZE+INTSIZE-2(sp) ; becomes arg to update_keys
jsr _update_keys
addq #INTSIZE+G_SIZE,sp
@nbe:
ENDC ; !CRYPT
IFEQ INTSIZE-2
ext.l d0 ; assert -1 <= d0 <= 255
ENDC
move.l (sp)+,d2
ENDM
FLUSH MACRO _1
move.l d2,-(sp)
move.l _1,-(sp)
G_PUSH
jsr _flush
addq #4+G_SIZE,sp
move.l (sp)+,d2
ENDM
ELSE ; !FUNZIP
NEXTBYTE MACRO
subq.w #1,incnt+INTSIZE-2-X(G) ; treat as short
bge.s @nbs
IFNE INTSIZE-2
subq.w #1,incnt-X(G)
bge.s @nbs
ENDIF
move.l d2,-(sp)
G_PUSH
jsr _readbyte
IFNE G_SIZE
addq #G_SIZE,sp
ENDC
move.l (sp)+,d2
IFEQ 2-INTSIZE
ext.l d0 ; assert -1 <= d0 <= 255
ENDC
bra.s @nbe
@nbs: moveq #0,d0
move.l inptr-X(G),a0
move.b (a0)+,d0
move.l a0,inptr-X(G)
@nbe:
ENDM
FLUSH MACRO _1
move.l d2,-(sp)
clr.l -(sp) ; unshrink flag: always false
move.l _1,-(sp) ; length
IF SIZEOF_slide>4
pea redirslide-X(G) ; buffer to flush
ELSE
move.l redirslide-X(G),-(sp)
ENDC
G_PUSH
tst.w mem_mode+INTSIZE-2-X(G) ; test lower word if long
beq.s @fm
jsr _memflush ; ignores the unshrink flag
bra.s @fe
@fm: jsr _flush
@fe: lea 8+INTSIZE+G_SIZE(sp),sp
move.l (sp)+,d2
ENDM
ENDC ; ?FUNZIP
; Here are the two bit-grabbing macros, defined in their NO_CHECK_EOF form:
;
; #define NEEDBITS(n) {while(k<(n)){b|=((ulg)NEXTBYTE)<<k;k+=8;}}
; #define DUMPBITS(n) {b>>=(n);k-=(n);}
;
; Without NO_CHECK_EOF, NEEDBITS reads like this:
;
; {while((int)k<(int)(n)){int c=NEXTBYTE;
; if(c==EOF){if((int)k>=0)break;return 1};
; b|=((ulg)c)<<k;k+=8;}}
;
; NEEDBITS clobbers d0, d1, a0, and a1, none of which can be used as the arg to
; the macro specifying the number of bits. The arg can be a shortword memory
; address, or d2-d7. The result is copied into d1 as a word ready for masking.
; DUMPBITS has no side effects; the arg must be a d-register (or immediate in
; the range 1-8?) and only the lower byte is significant.
NEEDBITS MACRO _1
@nb: cmp.w _1,k ; assert 0 < k <= 32 ... arg may be 0
bge.s @ne ; signed compare!
@loop:
NEXTBYTE ; returns in d0.l
IFNDEF NO_CHECK_EOF
cmp.w #EOF,d0
bne.s @nok
tst.w k
bge.s @ne
bra error_return
ENDC ; !NO_CHECK_EOF
@nok: lsl.l k,d0
or.l d0,b
addq.w #8,k
cmp.w _1,k ;bra.s @nb
bcs @loop ;
@ne: move.l b,d1 ; return a copy of b in d1
ENDM
DUMPBITS MACRO _1
lsr.l _1,b ; upper bits of _1 are ignored??
sub.b _1,k
ENDM
; This is a longword version of the mask_bits constant array:
longmasks: dc.l $00000000,$00000001,$00000003,$00000007,$0000000F
dc.l $0000001F,$0000003F,$0000007F,$000000FF,$000001FF
dc.l $000003FF,$000007FF,$00000FFF,$00001FFF,$00003FFF
dc.l $00007FFF,$0000FFFF,0,0,0,0,0,0,0,0,0,0,0,0,0,0
; ******************************************************************************
; Here we go, finally:
xdef _inflate_codes
_inflate_codes:
link a5,#-8
movem.l savregs,-(sp)
; 8(a5) = tl, 12(a5) = td, 16(a5) = bl, 18|20(a5) = bd... add 4 for REENT_G
; -4(a5) = ml, -8(a5) = md, both unsigned long.
; Here we cache some globals and args:
IFDEF REENT_G
move.l 8(a5),G
ELSE
lea _G,G ; G is now a global instance
IFDEF X
lea (X,G),G
ENDIF
ENDC
lea longmasks,lmask
move.l bb-X(G),b
MOVINT bk-X(G),k
IFDEF INT16
moveq #0,w ; keep this usable as longword
ENDC
MOVINT wp-X(G),w
moveq #0,e ; keep this usable as longword too
MOVINT 16+G_SIZE(a5),d0
asl.w #2,d0
move.l (lmask,d0.w),-4(a5) ; ml = mask_bits[bl]
MOVINT 16+INTSIZE+G_SIZE(a5),d0
asl.w #2,d0
move.l (lmask,d0.w),-8(a5) ; md = mask_bits[bd]
main_loop:
NEEDBITS 14+INTSIZE+G_SIZE(a5) ; (unsigned) bl
and.l -4(a5),d1 ; ml
IFNE SIZEOF_huft-8
mulu #SIZEOF_huft,d1
ELSE
asl.l #3,d1
ENDC
move.l 8+G_SIZE(a5),t ; tl
add.l d1,t
newtop: move.b h_b(t),d0
DUMPBITS d0
move.b h_e(t),e
cmp.b #32,e ; is it a literal?
bne nonlit ; no
move.w h_v_n(t),d0 ; yes
IFGT SIZEOF_slide-4
lea redirslide-X(G),a0
ELSE
move.l redirslide-X(G),a0
ENDC
move.b d0,(a0,w.l) ; stick in the decoded byte
addq.l #1,w
cmp.l #WSIZE,w
blo main_loop
FLUSH w
ext.l d0 ; does a test as it casts long
bne return
moveq #0,w
bra main_loop ; break (newtop loop)
nonlit: cmp.b #31,e ; is it a length?
beq finish ; no, it's the end marker
bhi nonleng ; no, it's something else
NEEDBITS e ; yes: a duplicate string
move.w e,d0
asl.w #2,d0
and.l (lmask,d0.w),d1
moveq #0,n ; cast h_v_n(t) to long
move.w h_v_n(t),n
add.l d1,n ; length of block to copy
DUMPBITS e
NEEDBITS 14+(2*INTSIZE)+G_SIZE(a5) ; bd, lower word if long
and.l -8(a5),d1 ; md
IFNE SIZEOF_huft-8
mulu #SIZEOF_huft,d1
ELSE
asl.l #3,d1
ENDC
move.l 12+G_SIZE(a5),t ; td
add.l d1,t
distop: move.b h_b(t),d0
DUMPBITS d0
move.b h_e(t),e
cmp.b #32,e ; is it a literal?
blo.s disbrk ; then stop doing this
cmp.b #INVALID,e ; is it bogus?
bne.s disgo
bra error_return ; then fail
disgo: and.w #$001F,e
NEEDBITS e
move.w e,d0
asl.w #2,d0
and.l (lmask,d0.w),d1
IFNE SIZEOF_huft-8
mulu #SIZEOF_huft,d1
ELSE
asl.l #3,d1
ENDC
move.l h_v_t(t),t
add.l d1,t
bra distop
disbrk: NEEDBITS e
move.l e,d0
asl.w #2,d0
and.l (lmask,d0.w),d1
move.l w,d
move.w h_v_n(t),d0 ; assert top word of d0 is zero
sub.l d0,d
sub.l d1,d ; distance back to copy the block
DUMPBITS e
docopy: move.l #WSIZE,e ; copy the duplicated string
and.l #WSIZE-1,d ; ...but first check if the length
cmp.l d,w ; will overflow the window...
blo.s ddgw
sub.l w,e
bra.s dadw
ddgw: sub.l d,e
dadw: cmp.l #$08000,e ; also, only copy <= 32K, so we can
bls.s dnox ; use a dbra loop to do it
move.l #$08000,e
dnox: cmp.l n,e
bls.s delen
move.l n,e
delen: sub.l e,n ; size of sub-block to copy in this pass
IF SIZEOF_slide>4
lea redirslide-X(G),a0
ELSE
move.l redirslide-X(G),a0
ENDC
move.l a0,a1
add.l w,a0 ; w and d are valid longwords
add.l d,a1
; Now at this point we could do tests to see if we should use an optimized
; large block copying method such as movem's, but since (a) such methods require
; the source and destination to be compatibly aligned -- and odd bytes at each
; end have to be handled separately, (b) it's only worth checking for if the
; block is pretty large, and (c) most strings are only a few bytes long, we're
; just not going to bother. Therefore we check above to make sure we move at
; most 32K in one sub-block, so a dbra loop can handle it.
dshort: move.l e,d0
subq #1,d0 ; assert >= 0
dspin: move.b (a1)+,(a0)+
dbra d0,dspin
add.l e,w
add.l e,d
cmp.l #WSIZE,w
blo.s dnfl
FLUSH w
ext.l d0 ; does a test as it casts to long
bne return
moveq #0,w
dnfl: tst.l n ; need to do more sub-blocks?
bne docopy ; yes
moveq #0,e ; restore zeroness in upper bytes of e
bra main_loop ; break (newtop loop)
nonleng: cmp.w #INVALID,e ; bottom of newtop loop -- misc. code
bne.s tailgo ; invalid code?
bra error_return ; then fail
tailgo: and.w #$001F,e
NEEDBITS e
move.w e,d0
asl.w #2,d0
and.l (lmask,d0.w),d1
IFNE SIZEOF_huft-8
mulu #SIZEOF_huft,d1
ELSE
asl.l #3,d1
ENDC
move.l h_v_t(t),t
add.l d1,t
bra newtop
finish: MOVINT w,wp-X(G) ; done: restore cached globals
MOVINT k,bk-X(G)
move.l b,bb-X(G)
moveq #RET_OK,d0 ; return "no error"
return: movem.l (sp)+,savregs
unlk a5
rts
error_return:
moveq #RET_ERR,d0 ; return "error occured"
bra return
|
wyvernSemi/vproc | 3,678 | examples/riscv/interrupt/test.s | # =============================================================
#
# Copyright (c) 2021 Simon Southwell. All rights reserved.
#
# Date: 5th August 2021
#
# Test program to test external interrupts
#
# This file is part of the base RISC-V instruction set simulator
# (rv32_cpu).
#
# This code is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This code is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this code. If not, see <http://www.gnu.org/licenses/>.
#
# =============================================================
.file "test.s"
.text
.org 0
.equ CAUSE_EXT_INT, 0x8000000b
.equ HALT_ADDR, 0x00000040
.equ MSTATUS_MIE_BIT_MASK, 0x00000008
.equ MIE_MEIE_BIT_MASK, 0x00000800
.equ INT_ADDR, 0xaffffffc
# Program reset point
_start: .global _start
.global main
# Jump to reset code
jal reset_vector
# Trap vector
trap_vector:
csrr t5, mcause
li t6, CAUSE_EXT_INT
bne t5, t6, trap_end
# Clear the IRQ
sw zero, 0(t1)
li gp, 2
mret
trap_end:
j halt
# HALT location
.org HALT_ADDR
halt:
jal halt
# Reset routine
reset_vector:
li ra,0
li sp,0
li gp,0
li tp,0
li t0,0
li t1,0
li t2,0
li s0,0
li s1,0
li a0,0
li a1,0
li a2,0
li a3,0
li a4,0
li a5,0
li a6,0
li a7,0
li s2,0
li s3,0
li s4,0
li s5,0
li s6,0
li s7,0
li s8,0
li s9,0
li s10,0
li s11,0
li t3,0
li t4,0
li t5,0
li t6,0
la t0, trap_vector
csrw mtvec, t0
la t0, main
csrw mepc, t0
mret
# Main test code
main:
li gp, 1
csrr t1, mstatus
# Set MIE (machine global interrupt enable) in mstatus
ori t1, t1, MSTATUS_MIE_BIT_MASK
csrw mstatus, t1
# Set MEIP (machine external interrupt enable) in mie
csrr t1, mie
li t2, MIE_MEIE_BIT_MASK
or t1, t1, t2
csrw mie, t1
# Set the IRQ
la t1, INT_ADDR
li t2, 1
# This instruction should cause an interrupt on this
# or the next instruction (ISS executable versus co-simulation).
sw t2, 0(t1)
nop
# Check the interrupt was processed (gp set to 2)
li t6, 2
bne gp, t6, fail
beq zero, zero, pass
unimp
# Fail routine (after riscv-test-env standard)
fail:
beqz gp, fail
sll gp, gp, 1
or gp, gp, 1
li a7, 93
mv a0, gp
ecall
# Pass routine (after riscv-test-env standard)
pass:
li gp, 1
li a7, 93
li a0, 0
ecall
|
WyvernTKC/cpuminer-gr-avx2 | 41,850 | asm/sha2-arm.S | /*
* Copyright 2012 pooler@litecoinpool.org
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version. See COPYING for more details.
*/
#include <cpuminer-config.h>
#if defined(USE_ASM) && defined(__arm__) && defined(__APCS_32__)
.macro sha256_k
.align 2
.long 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
.long 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
.long 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
.long 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
.long 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
.long 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
.long 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
.long 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
.long 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
.long 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
.long 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
.long 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
.long 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
.long 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
.long 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
.long 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
.endm
.macro sha256_extend_doubleround_core i, rw, ra, rb, ry, rz
mov r12, \ry, ror #17
add r11, r11, \ra
eor r12, r12, \ry, ror #19
mov \ra, lr, ror #7
eor r12, r12, \ry, lsr #10
eor \ra, \ra, lr, ror #18
add r12, r12, r11
ldr r11, [\rw, #(\i+2)*4]
eor \ra, \ra, lr, lsr #3
add \ra, \ra, r12
mov r12, \rz, ror #17
str \ra, [\rw, #(\i+16)*4]
add lr, lr, \rb
eor r12, r12, \rz, ror #19
mov \rb, r11, ror #7
eor r12, r12, \rz, lsr #10
eor \rb, \rb, r11, ror #18
add lr, lr, r12
eor \rb, \rb, r11, lsr #3
add \rb, \rb, lr
.endm
.macro sha256_extend_doubleround_head i, rw, ra, rb, ry, rz
ldr lr, [\rw, #(\i+1)*4]
sha256_extend_doubleround_core \i, \rw, \ra, \rb, \ry, \rz
ldr lr, [\rw, #(\i+3)*4]
.endm
.macro sha256_extend_doubleround_body i, rw, ra, rb, ry, rz
str \rz, [\rw, #(\i+15)*4]
sha256_extend_doubleround_core \i, \rw, \ra, \rb, \ry, \rz
ldr lr, [\rw, #(\i+3)*4]
.endm
.macro sha256_extend_doubleround_foot i, rw, ra, rb, ry, rz
str \rz, [\rw, #(\i+15)*4]
sha256_extend_doubleround_core \i, \rw, \ra, \rb, \ry, \rz
str \rb, [\rw, #(\i+17)*4]
.endm
.macro sha256_main_round i, ka, rw, ra, rb, rc, rd, re, rf, rg, rh
ldr r12, [\rw, #(\i)*4]
and r3, \rf, \re
bic lr, \rg, \re
orr lr, lr, r3
ldr r3, \ka + (\i)*4
add \rh, \rh, lr
eor lr, \re, \re, ror #5
add \rh, \rh, r12
eor lr, lr, \re, ror #19
add \rh, \rh, r3
eor r3, \ra, \rb
add \rh, \rh, lr, ror #6
and r3, r3, \rc
eor r12, \ra, \ra, ror #11
and lr, \ra, \rb
eor r12, r12, \ra, ror #20
eor lr, lr, r3
add r3, \rh, lr
add \rh, \rh, \rd
add \rd, r3, r12, ror #2
.endm
.macro sha256_main_quadround i, ka, rw
sha256_main_round \i+0, \ka, \rw, r4, r5, r6, r7, r8, r9, r10, r11
sha256_main_round \i+1, \ka, \rw, r7, r4, r5, r6, r11, r8, r9, r10
sha256_main_round \i+2, \ka, \rw, r6, r7, r4, r5, r10, r11, r8, r9
sha256_main_round \i+3, \ka, \rw, r5, r6, r7, r4, r9, r10, r11, r8
.endm
.text
.code 32
.align 2
.globl sha256_transform
.globl _sha256_transform
#ifdef __ELF__
.type sha256_transform, %function
#endif
sha256_transform:
_sha256_transform:
stmfd sp!, {r4-r11, lr}
cmp r2, #0
sub sp, sp, #64*4
bne sha256_transform_swap
ldmia r1!, {r4-r11}
stmia sp, {r4-r11}
add r3, sp, #8*4
ldmia r1, {r4-r11}
stmia r3, {r4-r11}
b sha256_transform_extend
.macro bswap rd, rn
eor r12, \rn, \rn, ror #16
bic r12, r12, #0x00ff0000
mov \rd, \rn, ror #8
eor \rd, \rd, r12, lsr #8
.endm
sha256_transform_swap:
ldmia r1!, {r4-r11}
bswap r4, r4
bswap r5, r5
bswap r6, r6
bswap r7, r7
bswap r8, r8
bswap r9, r9
bswap r10, r10
bswap r11, r11
stmia sp, {r4-r11}
add r3, sp, #8*4
ldmia r1, {r4-r11}
bswap r4, r4
bswap r5, r5
bswap r6, r6
bswap r7, r7
bswap r8, r8
bswap r9, r9
bswap r10, r10
bswap r11, r11
stmia r3, {r4-r11}
sha256_transform_extend:
add r12, sp, #9*4
ldr r11, [sp, #0*4]
ldmia r12, {r4-r10}
sha256_extend_doubleround_head 0, sp, r4, r5, r9, r10
sha256_extend_doubleround_body 2, sp, r6, r7, r4, r5
sha256_extend_doubleround_body 4, sp, r8, r9, r6, r7
sha256_extend_doubleround_body 6, sp, r10, r4, r8, r9
sha256_extend_doubleround_body 8, sp, r5, r6, r10, r4
sha256_extend_doubleround_body 10, sp, r7, r8, r5, r6
sha256_extend_doubleround_body 12, sp, r9, r10, r7, r8
sha256_extend_doubleround_body 14, sp, r4, r5, r9, r10
sha256_extend_doubleround_body 16, sp, r6, r7, r4, r5
sha256_extend_doubleround_body 18, sp, r8, r9, r6, r7
sha256_extend_doubleround_body 20, sp, r10, r4, r8, r9
sha256_extend_doubleround_body 22, sp, r5, r6, r10, r4
sha256_extend_doubleround_body 24, sp, r7, r8, r5, r6
sha256_extend_doubleround_body 26, sp, r9, r10, r7, r8
sha256_extend_doubleround_body 28, sp, r4, r5, r9, r10
sha256_extend_doubleround_body 30, sp, r6, r7, r4, r5
sha256_extend_doubleround_body 32, sp, r8, r9, r6, r7
sha256_extend_doubleround_body 34, sp, r10, r4, r8, r9
sha256_extend_doubleround_body 36, sp, r5, r6, r10, r4
sha256_extend_doubleround_body 38, sp, r7, r8, r5, r6
sha256_extend_doubleround_body 40, sp, r9, r10, r7, r8
sha256_extend_doubleround_body 42, sp, r4, r5, r9, r10
sha256_extend_doubleround_body 44, sp, r6, r7, r4, r5
sha256_extend_doubleround_foot 46, sp, r8, r9, r6, r7
ldmia r0, {r4-r11}
sha256_main_quadround 0, sha256_transform_k, sp
sha256_main_quadround 4, sha256_transform_k, sp
sha256_main_quadround 8, sha256_transform_k, sp
sha256_main_quadround 12, sha256_transform_k, sp
sha256_main_quadround 16, sha256_transform_k, sp
sha256_main_quadround 20, sha256_transform_k, sp
sha256_main_quadround 24, sha256_transform_k, sp
sha256_main_quadround 28, sha256_transform_k, sp
b sha256_transform_k_over
sha256_transform_k:
sha256_k
sha256_transform_k_over:
sha256_main_quadround 32, sha256_transform_k, sp
sha256_main_quadround 36, sha256_transform_k, sp
sha256_main_quadround 40, sha256_transform_k, sp
sha256_main_quadround 44, sha256_transform_k, sp
sha256_main_quadround 48, sha256_transform_k, sp
sha256_main_quadround 52, sha256_transform_k, sp
sha256_main_quadround 56, sha256_transform_k, sp
sha256_main_quadround 60, sha256_transform_k, sp
ldmia r0, {r1, r2, r3, r12}
add r4, r4, r1
add r5, r5, r2
add r6, r6, r3
add r7, r7, r12
stmia r0!, {r4-r7}
ldmia r0, {r1, r2, r3, r12}
add r8, r8, r1
add r9, r9, r2
add r10, r10, r3
add r11, r11, r12
stmia r0, {r8-r11}
add sp, sp, #64*4
#ifdef __thumb__
ldmfd sp!, {r4-r11, lr}
bx lr
#else
ldmfd sp!, {r4-r11, pc}
#endif
.text
.code 32
.align 2
.globl sha256d_ms
.globl _sha256d_ms
#ifdef __ELF__
.type sha256d_ms, %function
#endif
sha256d_ms:
_sha256d_ms:
stmfd sp!, {r4-r11, lr}
sub sp, sp, #64*4
cmp r0, r0
ldr lr, [r1, #3*4]
ldr r6, [r1, #18*4]
ldr r7, [r1, #19*4]
mov r12, lr, ror #7
str r6, [sp, #18*4]
eor r12, r12, lr, ror #18
str r7, [sp, #19*4]
eor r12, r12, lr, lsr #3
ldr r8, [r1, #20*4]
add r6, r6, r12
ldr r10, [r1, #22*4]
add r7, r7, lr
str r6, [r1, #18*4]
mov r12, r6, ror #17
str r7, [r1, #19*4]
eor r12, r12, r6, ror #19
str r8, [sp, #20*4]
eor r12, r12, r6, lsr #10
ldr r4, [r1, #23*4]
add r8, r8, r12
ldr r5, [r1, #24*4]
mov r9, r7, ror #17
str r8, [r1, #20*4]
eor r9, r9, r7, ror #19
str r10, [sp, #21*4]
eor r9, r9, r7, lsr #10
str r4, [sp, #22*4]
mov r12, r8, ror #17
str r9, [r1, #21*4]
eor r12, r12, r8, ror #19
str r5, [sp, #23*4]
eor r12, r12, r8, lsr #10
mov lr, r9, ror #17
add r10, r10, r12
ldr r11, [r1, #30*4]
eor lr, lr, r9, ror #19
str r10, [r1, #22*4]
eor lr, lr, r9, lsr #10
str r11, [sp, #24*4]
add r4, r4, lr
mov r12, r10, ror #17
str r4, [r1, #23*4]
eor r12, r12, r10, ror #19
mov lr, r4, ror #17
eor r12, r12, r10, lsr #10
eor lr, lr, r4, ror #19
add r5, r5, r12
eor lr, lr, r4, lsr #10
str r5, [r1, #24*4]
add r6, r6, lr
mov r12, r5, ror #17
str r6, [r1, #25*4]
eor r12, r12, r5, ror #19
mov lr, r6, ror #17
eor r12, r12, r5, lsr #10
eor lr, lr, r6, ror #19
add r7, r7, r12
eor lr, lr, r6, lsr #10
str r7, [r1, #26*4]
add r8, r8, lr
mov r12, r7, ror #17
str r8, [r1, #27*4]
eor r12, r12, r7, ror #19
mov lr, r8, ror #17
eor r12, r12, r7, lsr #10
eor lr, lr, r8, ror #19
add r9, r9, r12
eor lr, lr, r8, lsr #10
str r9, [r1, #28*4]
add r10, r10, lr
ldr lr, [r1, #31*4]
mov r12, r9, ror #17
str r10, [r1, #29*4]
eor r12, r12, r9, ror #19
str lr, [sp, #25*4]
eor r12, r12, r9, lsr #10
add r11, r11, r12
add r5, r5, lr
mov r12, r10, ror #17
add r4, r4, r11
ldr r11, [r1, #16*4]
eor r12, r12, r10, ror #19
str r4, [r1, #30*4]
eor r12, r12, r10, lsr #10
add r5, r5, r12
ldr lr, [r1, #17*4]
sha256d_ms_extend_loop2:
sha256_extend_doubleround_body 16, r1, r6, r7, r4, r5
sha256_extend_doubleround_body 18, r1, r8, r9, r6, r7
sha256_extend_doubleround_body 20, r1, r10, r4, r8, r9
sha256_extend_doubleround_body 22, r1, r5, r6, r10, r4
sha256_extend_doubleround_body 24, r1, r7, r8, r5, r6
sha256_extend_doubleround_body 26, r1, r9, r10, r7, r8
sha256_extend_doubleround_body 28, r1, r4, r5, r9, r10
sha256_extend_doubleround_body 30, r1, r6, r7, r4, r5
sha256_extend_doubleround_body 32, r1, r8, r9, r6, r7
sha256_extend_doubleround_body 34, r1, r10, r4, r8, r9
sha256_extend_doubleround_body 36, r1, r5, r6, r10, r4
sha256_extend_doubleround_body 38, r1, r7, r8, r5, r6
sha256_extend_doubleround_body 40, r1, r9, r10, r7, r8
sha256_extend_doubleround_body 42, r1, r4, r5, r9, r10
bne sha256d_ms_extend_coda2
sha256_extend_doubleround_body 44, r1, r6, r7, r4, r5
sha256_extend_doubleround_foot 46, r1, r8, r9, r6, r7
ldr r4, [r3, #0*4]
ldr r9, [r3, #1*4]
ldr r10, [r3, #2*4]
ldr r11, [r3, #3*4]
ldr r8, [r3, #4*4]
ldr r5, [r3, #5*4]
ldr r6, [r3, #6*4]
ldr r7, [r3, #7*4]
b sha256d_ms_main_loop1
sha256d_ms_main_loop2:
sha256_main_round 0, sha256d_ms_k, r1, r4, r5, r6, r7, r8, r9, r10, r11
sha256_main_round 1, sha256d_ms_k, r1, r7, r4, r5, r6, r11, r8, r9, r10
sha256_main_round 2, sha256d_ms_k, r1, r6, r7, r4, r5, r10, r11, r8, r9
sha256d_ms_main_loop1:
sha256_main_round 3, sha256d_ms_k, r1, r5, r6, r7, r4, r9, r10, r11, r8
sha256_main_quadround 4, sha256d_ms_k, r1
sha256_main_quadround 8, sha256d_ms_k, r1
sha256_main_quadround 12, sha256d_ms_k, r1
sha256_main_quadround 16, sha256d_ms_k, r1
sha256_main_quadround 20, sha256d_ms_k, r1
sha256_main_quadround 24, sha256d_ms_k, r1
sha256_main_quadround 28, sha256d_ms_k, r1
b sha256d_ms_k_over
sha256d_ms_k:
sha256_k
sha256d_ms_k_over:
sha256_main_quadround 32, sha256d_ms_k, r1
sha256_main_quadround 36, sha256d_ms_k, r1
sha256_main_quadround 40, sha256d_ms_k, r1
sha256_main_quadround 44, sha256d_ms_k, r1
sha256_main_quadround 48, sha256d_ms_k, r1
sha256_main_quadround 52, sha256d_ms_k, r1
sha256_main_round 56, sha256d_ms_k, r1, r4, r5, r6, r7, r8, r9, r10, r11
bne sha256d_ms_finish
sha256_main_round 57, sha256d_ms_k, r1, r7, r4, r5, r6, r11, r8, r9, r10
sha256_main_round 58, sha256d_ms_k, r1, r6, r7, r4, r5, r10, r11, r8, r9
sha256_main_round 59, sha256d_ms_k, r1, r5, r6, r7, r4, r9, r10, r11, r8
sha256_main_quadround 60, sha256d_ms_k, r1
ldmia r2!, {r3, r12, lr}
add r4, r4, r3
add r5, r5, r12
add r6, r6, lr
stmia sp, {r4-r6}
ldmia r2, {r3, r4, r5, r6, r12}
add lr, sp, #3*4
add r7, r7, r3
add r8, r8, r4
add r9, r9, r5
add r10, r10, r6
add r11, r11, r12
add r12, sp, #18*4
stmia lr!, {r7-r11}
ldmia r12, {r4-r11}
str r4, [r1, #18*4]
str r5, [r1, #19*4]
str r6, [r1, #20*4]
str r7, [r1, #22*4]
str r8, [r1, #23*4]
str r9, [r1, #24*4]
str r10, [r1, #30*4]
str r11, [r1, #31*4]
mov r3, #0x80000000
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0x00000100
stmia lr, {r3-r10}
ldr lr, [sp, #1*4]
movs r1, sp
ldr r4, [sp, #0*4]
ldr r11, [sp, #2*4]
mov r12, lr, ror #7
eor r12, r12, lr, ror #18
add r5, lr, #0x00a00000
eor r12, r12, lr, lsr #3
mov lr, r11, ror #7
add r4, r4, r12
eor lr, lr, r11, ror #18
str r4, [sp, #16*4]
eor lr, lr, r11, lsr #3
mov r12, r4, ror #17
add r5, r5, lr
ldr lr, [sp, #3*4]
str r5, [sp, #17*4]
eor r12, r12, r4, ror #19
mov r6, lr, ror #7
eor r12, r12, r4, lsr #10
eor r6, r6, lr, ror #18
add r11, r11, r12
eor r6, r6, lr, lsr #3
mov r12, r5, ror #17
add r6, r6, r11
ldr r11, [sp, #4*4]
str r6, [sp, #18*4]
eor r12, r12, r5, ror #19
mov r7, r11, ror #7
eor r12, r12, r5, lsr #10
eor r7, r7, r11, ror #18
add lr, lr, r12
eor r7, r7, r11, lsr #3
mov r12, r6, ror #17
add r7, r7, lr
ldr lr, [sp, #5*4]
str r7, [sp, #19*4]
eor r12, r12, r6, ror #19
mov r8, lr, ror #7
eor r12, r12, r6, lsr #10
eor r8, r8, lr, ror #18
add r11, r11, r12
eor r8, r8, lr, lsr #3
mov r12, r7, ror #17
add r8, r8, r11
ldr r11, [sp, #6*4]
str r8, [sp, #20*4]
eor r12, r12, r7, ror #19
mov r9, r11, ror #7
eor r12, r12, r7, lsr #10
eor r9, r9, r11, ror #18
add lr, lr, r12
eor r9, r9, r11, lsr #3
mov r12, r8, ror #17
add r9, r9, lr
ldr lr, [sp, #7*4]
str r9, [sp, #21*4]
eor r12, r12, r8, ror #19
mov r10, lr, ror #7
eor r12, r12, r8, lsr #10
eor r10, r10, lr, ror #18
add r11, r11, r12
eor r10, r10, lr, lsr #3
mov r12, r9, ror #17
add r11, r11, #0x00000100
add lr, lr, r4
add r10, r10, r11
eor r12, r12, r9, ror #19
str r10, [sp, #22*4]
add lr, lr, #0x11000000
eor r12, r12, r9, lsr #10
add lr, lr, r12
mov r12, r10, ror #17
add r4, lr, #0x00002000
eor r12, r12, r10, ror #19
str r4, [sp, #23*4]
add r5, r5, #0x80000000
eor r12, r12, r10, lsr #10
add r5, r5, r12
mov r12, r4, ror #17
str r5, [sp, #24*4]
eor r12, r12, r4, ror #19
mov r11, r5, ror #17
eor r12, r12, r4, lsr #10
eor r11, r11, r5, ror #19
add r6, r6, r12
eor r11, r11, r5, lsr #10
str r6, [sp, #25*4]
add r7, r7, r11
mov r12, r6, ror #17
str r7, [sp, #26*4]
eor r12, r12, r6, ror #19
mov r11, r7, ror #17
eor r12, r12, r6, lsr #10
eor r11, r11, r7, ror #19
add r8, r8, r12
eor r11, r11, r7, lsr #10
str r8, [sp, #27*4]
add r9, r9, r11
mov lr, r8, ror #17
mov r12, r9, ror #17
str r9, [sp, #28*4]
add r4, r4, #0x00400000
eor lr, lr, r8, ror #19
eor r12, r12, r9, ror #19
eor lr, lr, r8, lsr #10
eor r12, r12, r9, lsr #10
add r4, r4, #0x00000022
add r10, r10, lr
add r4, r4, r12
ldr r11, [sp, #16*4]
add r5, r5, #0x00000100
str r4, [sp, #30*4]
mov lr, r11, ror #7
str r10, [sp, #29*4]
mov r12, r10, ror #17
eor lr, lr, r11, ror #18
eor r12, r12, r10, ror #19
eor lr, lr, r11, lsr #3
eor r12, r12, r10, lsr #10
add r5, r5, lr
ldr lr, [r1, #17*4]
add r5, r5, r12
b sha256d_ms_extend_loop2
sha256d_ms_extend_coda2:
str r5, [r1, #(44+15)*4]
mov r12, r4, ror #17
add r11, r11, r6
mov r6, lr, ror #7
eor r12, r12, r4, ror #19
eor r6, r6, lr, ror #18
eor r12, r12, r4, lsr #10
eor r6, r6, lr, lsr #3
add r12, r12, r11
add r6, r6, r12
str r6, [r1, #(44+16)*4]
adr r2, sha256d_ms_h
ldmia r2, {r4-r11}
b sha256d_ms_main_loop2
sha256d_ms_h:
.long 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a
.long 0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19
.macro sha256_main_round_red i, ka, rw, rd, re, rf, rg, rh
ldr r12, [\rw, #(\i)*4]
and r3, \rf, \re
bic lr, \rg, \re
add \rh, \rh, \rd
orr lr, lr, r3
ldr r3, \ka + (\i)*4
add \rh, \rh, lr
eor lr, \re, \re, ror #5
add \rh, \rh, r12
eor lr, lr, \re, ror #19
add \rh, \rh, r3
add \rh, \rh, lr, ror #6
.endm
sha256d_ms_finish:
sha256_main_round_red 57, sha256d_ms_k, r1, r6, r11, r8, r9, r10
sha256_main_round_red 58, sha256d_ms_k, r1, r5, r10, r11, r8, r9
sha256_main_round_red 59, sha256d_ms_k, r1, r4, r9, r10, r11, r8
ldr r5, [r2, #7*4]
sha256_main_round_red 60, sha256d_ms_k, r1, r7, r8, r9, r10, r11
add r11, r11, r5
str r11, [r0, #7*4]
add sp, sp, #64*4
#ifdef __thumb__
ldmfd sp!, {r4-r11, lr}
bx lr
#else
ldmfd sp!, {r4-r11, pc}
#endif
#ifdef __ARM_NEON__
.text
.code 32
.align 2
.globl sha256_init_4way
.globl _sha256_init_4way
#ifdef __ELF__
.type sha256_init_4way, %function
#endif
sha256_init_4way:
_sha256_init_4way:
adr r12, sha256_4h
vldmia r12, {q8-q15}
vstmia r0, {q8-q15}
bx lr
.align 4
sha256_4h:
.long 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667
.long 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85
.long 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372
.long 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a
.long 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f
.long 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c
.long 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab
.long 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19
.macro sha256_4k
.long 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98
.long 0x71374491, 0x71374491, 0x71374491, 0x71374491
.long 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf
.long 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5
.long 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b
.long 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1
.long 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4
.long 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5
.long 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98
.long 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01
.long 0x243185be, 0x243185be, 0x243185be, 0x243185be
.long 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3
.long 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74
.long 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe
.long 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7
.long 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174
.long 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1
.long 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786
.long 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6
.long 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc
.long 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f
.long 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa
.long 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc
.long 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da
.long 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152
.long 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d
.long 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8
.long 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7
.long 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3
.long 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147
.long 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351
.long 0x14292967, 0x14292967, 0x14292967, 0x14292967
.long 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85
.long 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138
.long 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc
.long 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13
.long 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354
.long 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb
.long 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e
.long 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85
.long 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1
.long 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b
.long 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70
.long 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3
.long 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819
.long 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624
.long 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585
.long 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070
.long 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116
.long 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08
.long 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c
.long 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5
.long 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3
.long 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a
.long 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f
.long 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3
.long 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee
.long 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f
.long 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814
.long 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208
.long 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa
.long 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb
.long 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7
.long 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2
.endm
.macro sha256_4way_extend_doubleround_core i, rr, rw, ra, rb, ry, rz
vadd.u32 q5, q5, \ra
veor.u32 q4, q4, q0
vshr.u32 q0, \ry, #19
vshl.u32 q1, \ry, #32-19
veor.u32 q4, q4, q0
vshr.u32 \ra, q6, #7
vshl.u32 q0, q6, #32-7
veor.u32 q4, q4, q1
veor.u32 \ra, \ra, q0
vshr.u32 q1, \ry, #10
vshr.u32 q0, q6, #18
veor.u32 q4, q4, q1
veor.u32 \ra, \ra, q0
vshl.u32 q1, q6, #32-18
vshr.u32 q0, q6, #3
veor.u32 \ra, \ra, q1
vadd.u32 q4, q4, q5
veor.u32 \ra, \ra, q0
vld1.u32 {q5}, [\rr]!
vadd.u32 \ra, \ra, q4
vshr.u32 q4, \rz, #17
vshl.u32 q0, \rz, #32-17
vadd.u32 q6, q6, \rb
vst1.u32 {\ra}, [\rw]!
veor.u32 q4, q4, q0
vshr.u32 q0, \rz, #19
vshl.u32 q1, \rz, #32-19
veor.u32 q4, q4, q0
vshr.u32 \rb, q5, #7
veor.u32 q4, q4, q1
vshl.u32 q0, q5, #32-7
vshr.u32 q1, \rz, #10
veor.u32 \rb, \rb, q0
vshr.u32 q0, q5, #18
veor.u32 q4, q4, q1
veor.u32 \rb, \rb, q0
vshl.u32 q1, q5, #32-18
vshr.u32 q0, q5, #3
veor.u32 \rb, \rb, q1
vadd.u32 q1, q6, q4
veor.u32 \rb, \rb, q0
.endm
.macro sha256_4way_extend_doubleround_head i, rr, rw, ra, rb, ry, rz
vld1.u32 {q6}, [\rr]!
vshr.u32 q4, \ry, #17
vshl.u32 q0, \ry, #32-17
sha256_4way_extend_doubleround_core \i, \rr, \rw, \ra, \rb, \ry, \rz
vld1.u32 {q6}, [\rr]!
vadd.u32 \rb, \rb, q1
.endm
.macro sha256_4way_extend_doubleround_body i, rr, rw, ra, rb, ry, rz
vshr.u32 q4, \ry, #17
vshl.u32 q0, \ry, #32-17
vst1.u32 {\rz}, [\rw]!
sha256_4way_extend_doubleround_core \i, \rr, \rw, \ra, \rb, \ry, \rz
vld1.u32 {q6}, [\rr]!
vadd.u32 \rb, \rb, q1
.endm
.macro sha256_4way_extend_doubleround_foot i, rr, rw, ra, rb, ry, rz
vshr.u32 q4, \ry, #17
vshl.u32 q0, \ry, #32-17
vst1.u32 {\rz}, [\rw]!
sha256_4way_extend_doubleround_core \i, \rr, \rw, \ra, \rb, \ry, \rz
vadd.u32 \rb, \rb, q1
vst1.u32 {\rb}, [\rw]!
.endm
.macro sha256_4way_main_round i, rk, rw, ra, rb, rc, rd, re, rf, rg, rh
vld1.u32 {q8}, [\rw]!
vand.u32 q9, \rf, \re
vbic.u32 q10, \rg, \re
vshr.u32 q11, \re, #5
vorr.u32 q10, q10, q9
vld1.u32 {q9}, [\rk]!
vadd.u32 \rh, \rh, q10
vshl.u32 q12, \re, #32-5
veor.u32 q10, \re, q11
vshr.u32 q11, \re, #19
veor.u32 q10, q10, q12
vshl.u32 q12, \re, #32-19
veor.u32 q10, q10, q11
vadd.u32 \rh, \rh, q8
veor.u32 q10, q10, q12
vadd.u32 \rh, \rh, q9
veor.u32 q9, \ra, \rb
vshr.u32 q11, q10, #6
vshl.u32 q13, q10, #32-6
vadd.u32 \rh, \rh, q11
vshr.u32 q11, \ra, #11
vshl.u32 q12, \ra, #32-11
veor.u32 q8, \ra, q11
vand.u32 q10, \ra, \rb
veor.u32 q8, q8, q12
vshr.u32 q11, \ra, #20
vshl.u32 q12, \ra, #32-20
veor.u32 q8, q8, q11
vand.u32 q9, q9, \rc
veor.u32 q8, q8, q12
vadd.u32 \rh, \rh, q13
veor.u32 q10, q10, q9
vshr.u32 q11, q8, #2
vshl.u32 q12, q8, #32-2
vadd.u32 q9, \rh, q10
vadd.u32 q12, q12, q11
vadd.u32 \rh, \rh, \rd
vadd.u32 \rd, q9, q12
.endm
.macro sha256_4way_main_quadround i, rk, rw
sha256_4way_main_round \i+0, \rk, \rw, q0, q1, q2, q3, q4, q5, q6, q7
sha256_4way_main_round \i+1, \rk, \rw, q3, q0, q1, q2, q7, q4, q5, q6
sha256_4way_main_round \i+2, \rk, \rw, q2, q3, q0, q1, q6, q7, q4, q5
sha256_4way_main_round \i+3, \rk, \rw, q1, q2, q3, q0, q5, q6, q7, q4
.endm
.text
.code 32
.align 2
.globl sha256_transform_4way
.globl _sha256_transform_4way
#ifdef __ELF__
.type sha256_transform_4way, %function
#endif
sha256_transform_4way:
_sha256_transform_4way:
stmfd sp!, {r4, lr}
vpush {q4-q7}
mov r12, sp
sub sp, sp, #64*16
bic sp, sp, #63
cmp r2, #0
bne sha256_transform_4way_swap
vldmia r1!, {q0-q7}
vstmia sp, {q0-q7}
add r3, sp, #8*16
vldmia r1, {q8-q15}
vstmia r3, {q8-q15}
b sha256_transform_4way_extend
sha256_transform_4way_swap:
vldmia r1!, {q0-q7}
vrev32.8 q0, q0
vrev32.8 q1, q1
vrev32.8 q2, q2
vrev32.8 q3, q3
vldmia r1, {q8-q15}
vrev32.8 q4, q4
vrev32.8 q5, q5
vrev32.8 q6, q6
vrev32.8 q7, q7
vstmia sp, {q0-q7}
vrev32.8 q8, q8
vrev32.8 q9, q9
vrev32.8 q10, q10
vrev32.8 q11, q11
vrev32.8 q12, q12
vrev32.8 q13, q13
vrev32.8 q14, q14
vrev32.8 q15, q15
add r3, sp, #8*16
vstmia r3, {q8-q15}
sha256_transform_4way_extend:
add r1, sp, #1*16
add r2, sp, #16*16
vmov.u32 q5, q0
sha256_4way_extend_doubleround_head 0, r1, r2, q9, q10, q14, q15
sha256_4way_extend_doubleround_body 2, r1, r2, q11, q12, q9, q10
sha256_4way_extend_doubleround_body 4, r1, r2, q13, q14, q11, q12
sha256_4way_extend_doubleround_body 6, r1, r2, q15, q9, q13, q14
sha256_4way_extend_doubleround_body 8, r1, r2, q10, q11, q15, q9
sha256_4way_extend_doubleround_body 10, r1, r2, q12, q13, q10, q11
sha256_4way_extend_doubleround_body 12, r1, r2, q14, q15, q12, q13
sha256_4way_extend_doubleround_body 14, r1, r2, q9, q10, q14, q15
sha256_4way_extend_doubleround_body 16, r1, r2, q11, q12, q9, q10
sha256_4way_extend_doubleround_body 18, r1, r2, q13, q14, q11, q12
sha256_4way_extend_doubleround_body 20, r1, r2, q15, q9, q13, q14
sha256_4way_extend_doubleround_body 22, r1, r2, q10, q11, q15, q9
sha256_4way_extend_doubleround_body 24, r1, r2, q12, q13, q10, q11
sha256_4way_extend_doubleround_body 26, r1, r2, q14, q15, q12, q13
sha256_4way_extend_doubleround_body 28, r1, r2, q9, q10, q14, q15
sha256_4way_extend_doubleround_body 30, r1, r2, q11, q12, q9, q10
sha256_4way_extend_doubleround_body 32, r1, r2, q13, q14, q11, q12
sha256_4way_extend_doubleround_body 34, r1, r2, q15, q9, q13, q14
sha256_4way_extend_doubleround_body 36, r1, r2, q10, q11, q15, q9
sha256_4way_extend_doubleround_body 38, r1, r2, q12, q13, q10, q11
sha256_4way_extend_doubleround_body 40, r1, r2, q14, q15, q12, q13
sha256_4way_extend_doubleround_body 42, r1, r2, q9, q10, q14, q15
sha256_4way_extend_doubleround_body 44, r1, r2, q11, q12, q9, q10
sha256_4way_extend_doubleround_foot 46, r1, r2, q13, q14, q11, q12
vldmia r0, {q0-q7}
adr r4, sha256_transform_4way_4k
b sha256_transform_4way_4k_over
.align 4
sha256_transform_4way_4k:
sha256_4k
sha256_transform_4way_4k_over:
sha256_4way_main_quadround 0, r4, sp
sha256_4way_main_quadround 4, r4, sp
sha256_4way_main_quadround 8, r4, sp
sha256_4way_main_quadround 12, r4, sp
sha256_4way_main_quadround 16, r4, sp
sha256_4way_main_quadround 20, r4, sp
sha256_4way_main_quadround 24, r4, sp
sha256_4way_main_quadround 28, r4, sp
sha256_4way_main_quadround 32, r4, sp
sha256_4way_main_quadround 36, r4, sp
sha256_4way_main_quadround 40, r4, sp
sha256_4way_main_quadround 44, r4, sp
sha256_4way_main_quadround 48, r4, sp
sha256_4way_main_quadround 52, r4, sp
sha256_4way_main_quadround 56, r4, sp
sha256_4way_main_quadround 60, r4, sp
vldmia r0, {q8-q15}
vadd.u32 q0, q0, q8
vadd.u32 q1, q1, q9
vadd.u32 q2, q2, q10
vadd.u32 q3, q3, q11
vadd.u32 q4, q4, q12
vadd.u32 q5, q5, q13
vadd.u32 q6, q6, q14
vadd.u32 q7, q7, q15
vstmia r0, {q0-q7}
mov sp, r12
vpop {q4-q7}
ldmfd sp!, {r4, pc}
.text
.code 32
.align 2
.globl sha256d_ms_4way
.globl _sha256d_ms_4way
#ifdef __ELF__
.type sha256d_ms_4way, %function
#endif
sha256d_ms_4way:
_sha256d_ms_4way:
stmfd sp!, {r4, lr}
vpush {q4-q7}
mov r12, sp
sub sp, sp, #64*16
bic sp, sp, #63
add r4, r1, #3*16
vld1.u32 {q6}, [r4]!
add r1, r1, #18*16
vldmia r1, {q11-q13}
cmp r0, r0
vshr.u32 q10, q6, #7
vshl.u32 q0, q6, #32-7
vshr.u32 q1, q6, #18
veor.u32 q10, q10, q0
vshl.u32 q0, q6, #32-18
veor.u32 q10, q10, q1
vshr.u32 q1, q6, #3
veor.u32 q10, q10, q0
vstmia sp!, {q11-q13}
veor.u32 q4, q10, q1
vadd.u32 q12, q12, q6
vadd.u32 q11, q11, q4
vshr.u32 q14, q12, #17
vshr.u32 q4, q11, #17
vshl.u32 q0, q11, #32-17
vst1.u32 {q11}, [r1]!
veor.u32 q4, q4, q0
vshr.u32 q0, q11, #19
vshl.u32 q1, q11, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q12}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q11, #10
vshl.u32 q0, q12, #32-17
veor.u32 q4, q4, q1
veor.u32 q14, q14, q0
vadd.u32 q13, q13, q4
vshr.u32 q0, q12, #19
vshl.u32 q1, q12, #32-19
veor.u32 q14, q14, q0
vst1.u32 {q13}, [r1]!
veor.u32 q14, q14, q1
vshr.u32 q1, q12, #10
vshr.u32 q4, q13, #17
vshl.u32 q0, q13, #32-17
veor.u32 q14, q14, q1
veor.u32 q4, q4, q0
vshr.u32 q0, q13, #19
vshl.u32 q1, q13, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q14}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q13, #10
vld1.u32 {q15}, [r1]
veor.u32 q4, q4, q1
vst1.u32 {q15}, [sp]!
vadd.u32 q15, q15, q4
vshr.u32 q4, q14, #17
vshl.u32 q0, q14, #32-17
vshl.u32 q1, q14, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q14, #19
vst1.u32 {q15}, [r1]!
veor.u32 q4, q4, q0
vld1.u32 {q9}, [r1]
veor.u32 q4, q4, q1
vshr.u32 q1, q14, #10
vst1.u32 {q9}, [sp]!
veor.u32 q5, q4, q1
vshr.u32 q4, q15, #17
vadd.u32 q9, q9, q5
vshl.u32 q0, q15, #32-17
vshl.u32 q1, q15, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q15, #19
vst1.u32 {q9}, [r1]!
veor.u32 q4, q4, q0
vld1.u32 {q10}, [r1]
veor.u32 q4, q4, q1
vshr.u32 q1, q15, #10
vst1.u32 {q10}, [sp]!
veor.u32 q4, q4, q1
vshl.u32 q0, q9, #32-17
vadd.u32 q10, q10, q4
vshr.u32 q4, q9, #17
vshl.u32 q1, q9, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q9, #19
veor.u32 q4, q4, q1
vshr.u32 q1, q9, #10
veor.u32 q4, q4, q0
vst1.u32 {q10}, [r1]!
veor.u32 q5, q4, q1
vshr.u32 q4, q10, #17
vshl.u32 q0, q10, #32-17
vadd.u32 q11, q11, q5
veor.u32 q4, q4, q0
vshr.u32 q0, q10, #19
vshl.u32 q1, q10, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q11}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q10, #10
vshl.u32 q0, q11, #32-17
veor.u32 q2, q4, q1
vshr.u32 q4, q11, #17
vadd.u32 q12, q12, q2
vshl.u32 q1, q11, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q11, #19
veor.u32 q4, q4, q1
vshr.u32 q1, q11, #10
veor.u32 q4, q4, q0
vst1.u32 {q12}, [r1]!
veor.u32 q5, q4, q1
vshr.u32 q4, q12, #17
vshl.u32 q0, q12, #32-17
vadd.u32 q13, q13, q5
veor.u32 q4, q4, q0
vshr.u32 q0, q12, #19
vshl.u32 q1, q12, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q13}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q12, #10
vshl.u32 q0, q13, #32-17
veor.u32 q2, q4, q1
vshr.u32 q4, q13, #17
vadd.u32 q14, q14, q2
vshl.u32 q1, q13, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q13, #19
veor.u32 q4, q4, q1
vshr.u32 q1, q13, #10
veor.u32 q4, q4, q0
vst1.u32 {q14}, [r1]!
veor.u32 q5, q4, q1
add r4, r4, #12*16
vshr.u32 q4, q14, #17
vshl.u32 q0, q14, #32-17
vadd.u32 q15, q15, q5
veor.u32 q4, q4, q0
vshr.u32 q0, q14, #19
vshl.u32 q1, q14, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q15}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q14, #10
vld1.u32 {q2}, [r1]
veor.u32 q4, q4, q1
vshl.u32 q0, q15, #32-17
vadd.u32 q9, q9, q4
vst1.u32 {q2}, [sp]!
vadd.u32 q9, q9, q2
vshr.u32 q4, q15, #17
vshr.u32 q2, q15, #19
veor.u32 q4, q4, q0
vst1.u32 {q9}, [r1]!
vshl.u32 q1, q15, #32-19
veor.u32 q4, q4, q2
vshr.u32 q0, q15, #10
veor.u32 q4, q4, q1
vld1.u32 {q5-q6}, [r4]!
veor.u32 q4, q4, q0
vld1.u32 {q2}, [r1]
vadd.u32 q10, q10, q4
vst1.u32 {q2}, [sp]!
vadd.u32 q10, q10, q2
sub sp, sp, #8*16
sha256d_ms_4way_extend_loop2:
sha256_4way_extend_doubleround_body 16, r4, r1, q11, q12, q9, q10
sha256_4way_extend_doubleround_body 18, r4, r1, q13, q14, q11, q12
sha256_4way_extend_doubleround_body 20, r4, r1, q15, q9, q13, q14
sha256_4way_extend_doubleround_body 22, r4, r1, q10, q11, q15, q9
sha256_4way_extend_doubleround_body 24, r4, r1, q12, q13, q10, q11
sha256_4way_extend_doubleround_body 26, r4, r1, q14, q15, q12, q13
sha256_4way_extend_doubleround_body 28, r4, r1, q9, q10, q14, q15
sha256_4way_extend_doubleround_body 30, r4, r1, q11, q12, q9, q10
sha256_4way_extend_doubleround_body 32, r4, r1, q13, q14, q11, q12
sha256_4way_extend_doubleround_body 34, r4, r1, q15, q9, q13, q14
sha256_4way_extend_doubleround_body 36, r4, r1, q10, q11, q15, q9
sha256_4way_extend_doubleround_body 38, r4, r1, q12, q13, q10, q11
sha256_4way_extend_doubleround_body 40, r4, r1, q14, q15, q12, q13
sha256_4way_extend_doubleround_body 42, r4, r1, q9, q10, q14, q15
sha256_4way_extend_doubleround_body 44, r4, r1, q11, q12, q9, q10
sha256_4way_extend_doubleround_foot 46, r4, r1, q13, q14, q11, q12
bne sha256d_ms_4way_extend_coda2
vldmia r3!, {q4-q7}
vldmia r3, {q0-q3}
vswp q0, q4
adr r3, sha256d_ms_4way_4k+3*16
sub r1, r1, #(64-3)*16
b sha256d_ms_4way_main_loop1
.align 4
sha256d_ms_4way_4k:
sha256_4k
sha256d_ms_4way_main_loop2:
sha256_4way_main_round 0, r3, r1, q0, q1, q2, q3, q4, q5, q6, q7
sha256_4way_main_round 1, r3, r1, q3, q0, q1, q2, q7, q4, q5, q6
sha256_4way_main_round 2, r3, r1, q2, q3, q0, q1, q6, q7, q4, q5
sha256d_ms_4way_main_loop1:
sha256_4way_main_round 3, r3, r1, q1, q2, q3, q0, q5, q6, q7, q4
sha256_4way_main_quadround 4, r3, r1
sha256_4way_main_quadround 8, r3, r1
sha256_4way_main_quadround 12, r3, r1
sha256_4way_main_quadround 16, r3, r1
sha256_4way_main_quadround 20, r3, r1
sha256_4way_main_quadround 24, r3, r1
sha256_4way_main_quadround 28, r3, r1
sha256_4way_main_quadround 32, r3, r1
sha256_4way_main_quadround 36, r3, r1
sha256_4way_main_quadround 40, r3, r1
sha256_4way_main_quadround 44, r3, r1
sha256_4way_main_quadround 48, r3, r1
sha256_4way_main_quadround 52, r3, r1
sha256_4way_main_round 56, r3, r1, q0, q1, q2, q3, q4, q5, q6, q7
bne sha256d_ms_4way_finish
sha256_4way_main_round 57, r3, r1, q3, q0, q1, q2, q7, q4, q5, q6
sha256_4way_main_round 58, r3, r1, q2, q3, q0, q1, q6, q7, q4, q5
sha256_4way_main_round 59, r3, r1, q1, q2, q3, q0, q5, q6, q7, q4
sha256_4way_main_quadround 60, r3, r1
vldmia r2, {q8-q15}
vadd.u32 q0, q0, q8
vadd.u32 q1, q1, q9
vadd.u32 q2, q2, q10
vadd.u32 q3, q3, q11
vadd.u32 q4, q4, q12
vadd.u32 q5, q5, q13
vadd.u32 q6, q6, q14
vadd.u32 q7, q7, q15
vldmia sp, {q8-q15}
sub r1, r1, #(64-18)*16
vstmia r1, {q8-q10}
add r1, r1, #4*16
vstmia r1, {q11-q13}
add r1, r1, #8*16
vstmia r1, {q14-q15}
vstmia sp, {q0-q7}
vmov.u32 q8, #0x80000000
vmov.u32 q9, #0
vmov.u32 q10, #0
vmov.u32 q11, #0
vmov.u32 q12, #0
vmov.u32 q13, #0
vmov.u32 q14, #0
vmov.u32 q15, #0x00000100
add r1, sp, #8*16
vstmia r1!, {q8-q15}
adds r4, sp, #2*16
vshr.u32 q9, q1, #7
vshl.u32 q2, q1, #32-7
vshr.u32 q4, q1, #18
veor.u32 q9, q9, q2
vshl.u32 q3, q1, #32-18
veor.u32 q9, q9, q4
vshr.u32 q2, q1, #3
veor.u32 q9, q9, q3
vld1.u32 {q5}, [r4]!
veor.u32 q9, q9, q2
vmov.u32 q7, #0x00a00000
vadd.u32 q9, q9, q0
vshr.u32 q10, q5, #7
vshl.u32 q0, q5, #32-7
vshl.u32 q3, q5, #32-18
veor.u32 q10, q10, q0
vshr.u32 q0, q5, #18
veor.u32 q10, q10, q3
vst1.u32 {q9}, [r1]!
vadd.u32 q3, q1, q7
veor.u32 q10, q10, q0
vshr.u32 q0, q5, #3
vld1.u32 {q6}, [r4]!
veor.u32 q10, q10, q0
vshr.u32 q4, q9, #17
vshl.u32 q0, q9, #32-17
vadd.u32 q10, q10, q3
veor.u32 q4, q4, q0
vshr.u32 q0, q9, #19
vshl.u32 q1, q9, #32-19
veor.u32 q4, q4, q0
vshr.u32 q11, q6, #7
vshl.u32 q0, q6, #32-7
veor.u32 q4, q4, q1
veor.u32 q11, q11, q0
vshr.u32 q1, q9, #10
vshr.u32 q0, q6, #18
veor.u32 q4, q4, q1
veor.u32 q11, q11, q0
vshl.u32 q1, q6, #32-18
vshr.u32 q0, q6, #3
veor.u32 q11, q11, q1
vadd.u32 q4, q4, q5
veor.u32 q11, q11, q0
vld1.u32 {q5}, [r4]!
vadd.u32 q11, q11, q4
vshr.u32 q4, q10, #17
vshl.u32 q0, q10, #32-17
vst1.u32 {q10}, [r1]!
veor.u32 q4, q4, q0
vshr.u32 q0, q10, #19
vshl.u32 q1, q10, #32-19
veor.u32 q4, q4, q0
vshr.u32 q12, q5, #7
veor.u32 q4, q4, q1
vshl.u32 q0, q5, #32-7
vshr.u32 q1, q10, #10
veor.u32 q12, q12, q0
vshr.u32 q0, q5, #18
veor.u32 q4, q4, q1
veor.u32 q12, q12, q0
vshl.u32 q1, q5, #32-18
vst1.u32 {q11}, [r1]!
veor.u32 q12, q12, q1
vshr.u32 q0, q5, #3
vadd.u32 q1, q6, q4
veor.u32 q12, q12, q0
vshr.u32 q4, q11, #17
vshl.u32 q0, q11, #32-17
vadd.u32 q12, q12, q1
vld1.u32 {q6}, [r4]!
veor.u32 q4, q4, q0
vshr.u32 q0, q11, #19
vshl.u32 q1, q11, #32-19
veor.u32 q4, q4, q0
vshr.u32 q13, q6, #7
vshl.u32 q0, q6, #32-7
veor.u32 q4, q4, q1
veor.u32 q13, q13, q0
vshr.u32 q1, q11, #10
vshr.u32 q0, q6, #18
veor.u32 q4, q4, q1
veor.u32 q13, q13, q0
vshl.u32 q1, q6, #32-18
vshr.u32 q0, q6, #3
veor.u32 q13, q13, q1
vadd.u32 q4, q4, q5
veor.u32 q13, q13, q0
vld1.u32 {q5}, [r4]!
vadd.u32 q13, q13, q4
vshr.u32 q4, q12, #17
vshl.u32 q0, q12, #32-17
vst1.u32 {q12}, [r1]!
veor.u32 q4, q4, q0
vshr.u32 q0, q12, #19
vshl.u32 q1, q12, #32-19
veor.u32 q4, q4, q0
vshr.u32 q14, q5, #7
veor.u32 q4, q4, q1
vshl.u32 q0, q5, #32-7
vshr.u32 q1, q12, #10
veor.u32 q14, q14, q0
vshr.u32 q0, q5, #18
veor.u32 q4, q4, q1
veor.u32 q14, q14, q0
vshl.u32 q1, q5, #32-18
vst1.u32 {q13}, [r1]!
veor.u32 q14, q14, q1
vshr.u32 q0, q5, #3
vadd.u32 q1, q6, q4
veor.u32 q14, q14, q0
vshr.u32 q4, q13, #17
vshl.u32 q0, q13, #32-17
vadd.u32 q14, q14, q1
vld1.u32 {q6}, [r4]!
vadd.u32 q5, q5, q15
veor.u32 q4, q4, q0
vshr.u32 q0, q13, #19
vshl.u32 q1, q13, #32-19
veor.u32 q4, q4, q0
vshr.u32 q15, q6, #7
vshl.u32 q0, q6, #32-7
veor.u32 q4, q4, q1
veor.u32 q15, q15, q0
vshr.u32 q1, q13, #10
vshr.u32 q0, q6, #18
veor.u32 q4, q4, q1
veor.u32 q15, q15, q0
vshl.u32 q1, q6, #32-18
vshr.u32 q0, q6, #3
veor.u32 q15, q15, q1
vadd.u32 q4, q4, q5
veor.u32 q15, q15, q0
vmov.u32 q5, #0x80000000
vadd.u32 q15, q15, q4
vshr.u32 q4, q14, #17
vshl.u32 q0, q14, #32-17
vadd.u32 q6, q6, q9
vst1.u32 {q14}, [r1]!
vmov.u32 q7, #0x11000000
veor.u32 q4, q4, q0
vshr.u32 q0, q14, #19
vshl.u32 q1, q14, #32-19
vadd.u32 q6, q6, q7
vmov.u32 q2, #0x00002000
veor.u32 q4, q4, q0
vst1.u32 {q15}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q14, #10
vadd.u32 q6, q6, q2
veor.u32 q1, q4, q1
add r4, r4, #8*16
vshr.u32 q4, q15, #17
vshl.u32 q0, q15, #32-17
vadd.u32 q9, q6, q1
veor.u32 q4, q4, q0
vshr.u32 q0, q15, #19
vshl.u32 q1, q15, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q9}, [r1]!
vadd.u32 q5, q5, q10
veor.u32 q4, q4, q1
vshr.u32 q1, q15, #10
vshl.u32 q0, q9, #32-17
veor.u32 q10, q4, q1
vshr.u32 q4, q9, #17
vadd.u32 q10, q10, q5
veor.u32 q4, q4, q0
vshr.u32 q0, q9, #19
vshl.u32 q1, q9, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q9, #10
veor.u32 q4, q4, q1
vst1.u32 {q10}, [r1]!
veor.u32 q1, q4, q0
vshr.u32 q4, q10, #17
vshl.u32 q0, q10, #32-17
vadd.u32 q11, q11, q1
veor.u32 q4, q4, q0
vshr.u32 q0, q10, #19
vshl.u32 q1, q10, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q11}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q10, #10
vshl.u32 q0, q11, #32-17
veor.u32 q1, q4, q1
vshr.u32 q4, q11, #17
vadd.u32 q12, q12, q1
veor.u32 q4, q4, q0
vshr.u32 q0, q11, #19
vshl.u32 q1, q11, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q11, #10
veor.u32 q4, q4, q1
vst1.u32 {q12}, [r1]!
veor.u32 q1, q4, q0
vshr.u32 q4, q12, #17
vshl.u32 q0, q12, #32-17
vadd.u32 q13, q13, q1
veor.u32 q4, q4, q0
vshr.u32 q0, q12, #19
vshl.u32 q1, q12, #32-19
veor.u32 q4, q4, q0
vst1.u32 {q13}, [r1]!
veor.u32 q4, q4, q1
vshr.u32 q1, q12, #10
vshl.u32 q0, q13, #32-17
veor.u32 q1, q4, q1
vshr.u32 q4, q13, #17
vadd.u32 q14, q14, q1
veor.u32 q4, q4, q0
vshr.u32 q0, q13, #19
vshl.u32 q1, q13, #32-19
veor.u32 q4, q4, q0
vshr.u32 q0, q13, #10
veor.u32 q4, q4, q1
vst1.u32 {q14}, [r1]!
veor.u32 q4, q4, q0
vmov.u32 q6, #0x00000100
vadd.u32 q15, q15, q4
vshr.u32 q4, q14, #17
vshl.u32 q0, q14, #32-17
vmov.u32 q7, #0x00400000
vst1.u32 {q15}, [r1]!
veor.u32 q4, q4, q0
vshr.u32 q0, q14, #19
vshl.u32 q1, q14, #32-19
veor.u32 q4, q4, q0
vadd.u32 q9, q9, q7
veor.u32 q4, q4, q1
vshr.u32 q1, q14, #10
vmov.u32 q2, #0x00000022
veor.u32 q4, q4, q1
vadd.u32 q9, q9, q2
vld1.u32 {q5}, [r4]!
vadd.u32 q9, q9, q4
vshr.u32 q4, q15, #17
vshl.u32 q0, q15, #32-17
vadd.u32 q6, q6, q10
vst1.u32 {q9}, [r1]!
veor.u32 q4, q4, q0
vshr.u32 q0, q15, #19
vshl.u32 q1, q15, #32-19
veor.u32 q4, q4, q0
vshr.u32 q10, q5, #7
veor.u32 q4, q4, q1
vshl.u32 q0, q5, #32-7
vshr.u32 q1, q15, #10
veor.u32 q10, q10, q0
vshr.u32 q0, q5, #18
veor.u32 q4, q4, q1
veor.u32 q10, q10, q0
vshl.u32 q1, q5, #32-18
vshr.u32 q0, q5, #3
veor.u32 q10, q10, q1
vadd.u32 q1, q6, q4
veor.u32 q10, q10, q0
vld1.u32 {q6}, [r4]!
vadd.u32 q10, q10, q1
b sha256d_ms_4way_extend_loop2
.align 4
sha256d_ms_4way_4h:
.long 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667
.long 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85
.long 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372
.long 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a
.long 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f
.long 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c
.long 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab
.long 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19
sha256d_ms_4way_extend_coda2:
adr r4, sha256d_ms_4way_4h
mov r1, sp
vldmia r4, {q0-q7}
vmov.u32 q15, q7
sub r3, r3, #64*16
b sha256d_ms_4way_main_loop2
.macro sha256_4way_main_round_red i, rk, rw, rd, re, rf, rg, rh
vld1.u32 {q8}, [\rw]!
vand.u32 q9, \rf, \re
vbic.u32 q10, \rg, \re
vshr.u32 q11, \re, #5
vorr.u32 q10, q10, q9
vshl.u32 q12, \re, #32-5
vadd.u32 \rh, \rh, q10
veor.u32 q10, \re, q11
vshr.u32 q11, \re, #19
veor.u32 q10, q10, q12
vshl.u32 q12, \re, #32-19
veor.u32 q10, q10, q11
vadd.u32 \rh, \rh, q8
veor.u32 q10, q10, q12
vld1.u32 {q9}, [\rk]!
vadd.u32 \rh, \rh, \rd
vshr.u32 q11, q10, #6
vadd.u32 \rh, \rh, q9
vshl.u32 q13, q10, #32-6
vadd.u32 \rh, \rh, q11
vadd.u32 \rh, \rh, q13
.endm
sha256d_ms_4way_finish:
sha256_4way_main_round_red 57, r3, r1, q2, q7, q4, q5, q6
sha256_4way_main_round_red 58, r3, r1, q1, q6, q7, q4, q5
sha256_4way_main_round_red 59, r3, r1, q0, q5, q6, q7, q4
sha256_4way_main_round_red 60, r3, r1, q3, q4, q5, q6, q7
vadd.u32 q7, q7, q15
add r0, r0, #7*16
vst1.u32 {q7}, [r0]
mov sp, r12
vpop {q4-q7}
ldmfd sp!, {r4, pc}
.text
.code 32
.align 2
.globl sha256_use_4way
.globl _sha256_use_4way
#ifdef __ELF__
.type sha256_use_4way, %function
#endif
sha256_use_4way:
_sha256_use_4way:
mov r0, #1
bx lr
#endif /* __ARM_NEON__ */
#endif
|
WyvernTKC/cpuminer-gr-avx2 | 17,247 | asm/scrypt-x86.S | /*
* Copyright 2011-2012, 2014 pooler@litecoinpool.org
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <cpuminer-config.h>
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(USE_ASM) && defined(__i386__)
.macro scrypt_shuffle src, so, dest, do
movl \so+60(\src), %eax
movl \so+44(\src), %ebx
movl \so+28(\src), %ecx
movl \so+12(\src), %edx
movl %eax, \do+12(\dest)
movl %ebx, \do+28(\dest)
movl %ecx, \do+44(\dest)
movl %edx, \do+60(\dest)
movl \so+40(\src), %eax
movl \so+8(\src), %ebx
movl \so+48(\src), %ecx
movl \so+16(\src), %edx
movl %eax, \do+8(\dest)
movl %ebx, \do+40(\dest)
movl %ecx, \do+16(\dest)
movl %edx, \do+48(\dest)
movl \so+20(\src), %eax
movl \so+4(\src), %ebx
movl \so+52(\src), %ecx
movl \so+36(\src), %edx
movl %eax, \do+4(\dest)
movl %ebx, \do+20(\dest)
movl %ecx, \do+36(\dest)
movl %edx, \do+52(\dest)
movl \so+0(\src), %eax
movl \so+24(\src), %ebx
movl \so+32(\src), %ecx
movl \so+56(\src), %edx
movl %eax, \do+0(\dest)
movl %ebx, \do+24(\dest)
movl %ecx, \do+32(\dest)
movl %edx, \do+56(\dest)
.endm
.macro salsa8_core_gen_quadround
movl 52(%esp), %ecx
movl 4(%esp), %edx
movl 20(%esp), %ebx
movl 8(%esp), %esi
leal (%ecx, %edx), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 4(%esp)
movl 36(%esp), %edi
leal (%edx, %ebx), %ebp
roll $9, %ebp
xorl %ebp, %edi
movl 24(%esp), %ebp
movl %edi, 8(%esp)
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 40(%esp), %ebx
movl %ecx, 20(%esp)
addl %edi, %ecx
roll $18, %ecx
leal (%esi, %ebp), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 24(%esp)
movl 56(%esp), %edi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %edi
movl %edi, 36(%esp)
movl 28(%esp), %ecx
movl %edx, 28(%esp)
movl 44(%esp), %edx
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %esi
movl 60(%esp), %ebx
movl %esi, 40(%esp)
addl %edi, %esi
roll $18, %esi
leal (%ecx, %edx), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 44(%esp)
movl 12(%esp), %edi
xorl %esi, %ebp
leal (%edx, %ebx), %esi
roll $9, %esi
xorl %esi, %edi
movl %edi, 12(%esp)
movl 48(%esp), %esi
movl %ebp, 48(%esp)
movl 64(%esp), %ebp
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 16(%esp), %ebx
movl %ecx, 16(%esp)
addl %edi, %ecx
roll $18, %ecx
leal (%esi, %ebp), %edi
roll $7, %edi
xorl %edi, %ebx
movl 32(%esp), %edi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %edi
movl %edi, 32(%esp)
movl %ebx, %ecx
movl %edx, 52(%esp)
movl 28(%esp), %edx
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %esi
movl 40(%esp), %ebx
movl %esi, 28(%esp)
addl %edi, %esi
roll $18, %esi
leal (%ecx, %edx), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 40(%esp)
movl 12(%esp), %edi
xorl %esi, %ebp
leal (%edx, %ebx), %esi
roll $9, %esi
xorl %esi, %edi
movl %edi, 12(%esp)
movl 4(%esp), %esi
movl %ebp, 4(%esp)
movl 48(%esp), %ebp
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 16(%esp), %ebx
movl %ecx, 16(%esp)
addl %edi, %ecx
roll $18, %ecx
leal (%esi, %ebp), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 48(%esp)
movl 32(%esp), %edi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %edi
movl %edi, 32(%esp)
movl 24(%esp), %ecx
movl %edx, 24(%esp)
movl 52(%esp), %edx
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %esi
movl 28(%esp), %ebx
movl %esi, 28(%esp)
addl %edi, %esi
roll $18, %esi
leal (%ecx, %edx), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 52(%esp)
movl 8(%esp), %edi
xorl %esi, %ebp
leal (%edx, %ebx), %esi
roll $9, %esi
xorl %esi, %edi
movl %edi, 8(%esp)
movl 44(%esp), %esi
movl %ebp, 44(%esp)
movl 4(%esp), %ebp
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 20(%esp), %ebx
movl %ecx, 4(%esp)
addl %edi, %ecx
roll $18, %ecx
leal (%esi, %ebp), %edi
roll $7, %edi
xorl %edi, %ebx
movl 36(%esp), %edi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %edi
movl %edi, 20(%esp)
movl %ebx, %ecx
movl %edx, 36(%esp)
movl 24(%esp), %edx
addl %edi, %ebx
roll $13, %ebx
xorl %ebx, %esi
movl 28(%esp), %ebx
movl %esi, 24(%esp)
addl %edi, %esi
roll $18, %esi
leal (%ecx, %edx), %edi
roll $7, %edi
xorl %edi, %ebx
movl %ebx, 28(%esp)
xorl %esi, %ebp
movl 8(%esp), %esi
leal (%edx, %ebx), %edi
roll $9, %edi
xorl %edi, %esi
movl 40(%esp), %edi
movl %ebp, 8(%esp)
movl 44(%esp), %ebp
movl %esi, 40(%esp)
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 4(%esp), %ebx
movl %ecx, 44(%esp)
addl %esi, %ecx
roll $18, %ecx
leal (%edi, %ebp), %esi
roll $7, %esi
xorl %esi, %ebx
movl %ebx, 4(%esp)
movl 20(%esp), %esi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %esi
movl %esi, 56(%esp)
movl 48(%esp), %ecx
movl %edx, 20(%esp)
movl 36(%esp), %edx
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %edi
movl 24(%esp), %ebx
movl %edi, 24(%esp)
addl %esi, %edi
roll $18, %edi
leal (%ecx, %edx), %esi
roll $7, %esi
xorl %esi, %ebx
movl %ebx, 60(%esp)
movl 12(%esp), %esi
xorl %edi, %ebp
leal (%edx, %ebx), %edi
roll $9, %edi
xorl %edi, %esi
movl %esi, 12(%esp)
movl 52(%esp), %edi
movl %ebp, 36(%esp)
movl 8(%esp), %ebp
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 16(%esp), %ebx
movl %ecx, 16(%esp)
addl %esi, %ecx
roll $18, %ecx
leal (%edi, %ebp), %esi
roll $7, %esi
xorl %esi, %ebx
movl 32(%esp), %esi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %esi
movl %esi, 32(%esp)
movl %ebx, %ecx
movl %edx, 48(%esp)
movl 20(%esp), %edx
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %edi
movl 24(%esp), %ebx
movl %edi, 20(%esp)
addl %esi, %edi
roll $18, %edi
leal (%ecx, %edx), %esi
roll $7, %esi
xorl %esi, %ebx
movl %ebx, 8(%esp)
movl 12(%esp), %esi
xorl %edi, %ebp
leal (%edx, %ebx), %edi
roll $9, %edi
xorl %edi, %esi
movl %esi, 12(%esp)
movl 28(%esp), %edi
movl %ebp, 52(%esp)
movl 36(%esp), %ebp
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 16(%esp), %ebx
movl %ecx, 16(%esp)
addl %esi, %ecx
roll $18, %ecx
leal (%edi, %ebp), %esi
roll $7, %esi
xorl %esi, %ebx
movl %ebx, 28(%esp)
movl 32(%esp), %esi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %esi
movl %esi, 32(%esp)
movl 4(%esp), %ecx
movl %edx, 4(%esp)
movl 48(%esp), %edx
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %edi
movl 20(%esp), %ebx
movl %edi, 20(%esp)
addl %esi, %edi
roll $18, %edi
leal (%ecx, %edx), %esi
roll $7, %esi
xorl %esi, %ebx
movl %ebx, 48(%esp)
movl 40(%esp), %esi
xorl %edi, %ebp
leal (%edx, %ebx), %edi
roll $9, %edi
xorl %edi, %esi
movl %esi, 36(%esp)
movl 60(%esp), %edi
movl %ebp, 24(%esp)
movl 52(%esp), %ebp
addl %esi, %ebx
roll $13, %ebx
xorl %ebx, %ecx
movl 44(%esp), %ebx
movl %ecx, 40(%esp)
addl %esi, %ecx
roll $18, %ecx
leal (%edi, %ebp), %esi
roll $7, %esi
xorl %esi, %ebx
movl %ebx, 52(%esp)
movl 56(%esp), %esi
xorl %ecx, %edx
leal (%ebp, %ebx), %ecx
roll $9, %ecx
xorl %ecx, %esi
movl %esi, 56(%esp)
addl %esi, %ebx
movl %edx, 44(%esp)
roll $13, %ebx
xorl %ebx, %edi
movl %edi, 60(%esp)
addl %esi, %edi
roll $18, %edi
xorl %edi, %ebp
movl %ebp, 64(%esp)
.endm
.text
.p2align 5
salsa8_core_gen:
salsa8_core_gen_quadround
salsa8_core_gen_quadround
ret
.text
.p2align 5
.globl scrypt_core
.globl _scrypt_core
scrypt_core:
_scrypt_core:
pushl %ebx
pushl %ebp
pushl %edi
pushl %esi
/* Check for SSE2 availability */
movl $1, %eax
cpuid
andl $0x04000000, %edx
jnz scrypt_core_sse2
scrypt_core_gen:
movl 20(%esp), %edi
movl 24(%esp), %esi
movl 28(%esp), %ecx
subl $72, %esp
.macro scrypt_core_macro1a p, q
movl \p(%edi), %eax
movl \q(%edi), %edx
movl %eax, \p(%esi)
movl %edx, \q(%esi)
xorl %edx, %eax
movl %eax, \p(%edi)
movl %eax, \p(%esp)
.endm
.macro scrypt_core_macro1b p, q
movl \p(%edi), %eax
xorl \p(%esi, %edx), %eax
movl \q(%edi), %ebx
xorl \q(%esi, %edx), %ebx
movl %ebx, \q(%edi)
xorl %ebx, %eax
movl %eax, \p(%edi)
movl %eax, \p(%esp)
.endm
.macro scrypt_core_macro2 p, q
movl \p(%esp), %eax
addl \p(%edi), %eax
movl %eax, \p(%edi)
xorl \q(%edi), %eax
movl %eax, \q(%edi)
movl %eax, \p(%esp)
.endm
.macro scrypt_core_macro3 p, q
movl \p(%esp), %eax
addl \q(%edi), %eax
movl %eax, \q(%edi)
.endm
shll $7, %ecx
addl %esi, %ecx
scrypt_core_gen_loop1:
movl %esi, 64(%esp)
movl %ecx, 68(%esp)
scrypt_core_macro1a 0, 64
scrypt_core_macro1a 4, 68
scrypt_core_macro1a 8, 72
scrypt_core_macro1a 12, 76
scrypt_core_macro1a 16, 80
scrypt_core_macro1a 20, 84
scrypt_core_macro1a 24, 88
scrypt_core_macro1a 28, 92
scrypt_core_macro1a 32, 96
scrypt_core_macro1a 36, 100
scrypt_core_macro1a 40, 104
scrypt_core_macro1a 44, 108
scrypt_core_macro1a 48, 112
scrypt_core_macro1a 52, 116
scrypt_core_macro1a 56, 120
scrypt_core_macro1a 60, 124
call salsa8_core_gen
movl 92(%esp), %edi
scrypt_core_macro2 0, 64
scrypt_core_macro2 4, 68
scrypt_core_macro2 8, 72
scrypt_core_macro2 12, 76
scrypt_core_macro2 16, 80
scrypt_core_macro2 20, 84
scrypt_core_macro2 24, 88
scrypt_core_macro2 28, 92
scrypt_core_macro2 32, 96
scrypt_core_macro2 36, 100
scrypt_core_macro2 40, 104
scrypt_core_macro2 44, 108
scrypt_core_macro2 48, 112
scrypt_core_macro2 52, 116
scrypt_core_macro2 56, 120
scrypt_core_macro2 60, 124
call salsa8_core_gen
movl 92(%esp), %edi
scrypt_core_macro3 0, 64
scrypt_core_macro3 4, 68
scrypt_core_macro3 8, 72
scrypt_core_macro3 12, 76
scrypt_core_macro3 16, 80
scrypt_core_macro3 20, 84
scrypt_core_macro3 24, 88
scrypt_core_macro3 28, 92
scrypt_core_macro3 32, 96
scrypt_core_macro3 36, 100
scrypt_core_macro3 40, 104
scrypt_core_macro3 44, 108
scrypt_core_macro3 48, 112
scrypt_core_macro3 52, 116
scrypt_core_macro3 56, 120
scrypt_core_macro3 60, 124
movl 64(%esp), %esi
movl 68(%esp), %ecx
addl $128, %esi
cmpl %ecx, %esi
jne scrypt_core_gen_loop1
movl 96(%esp), %esi
movl 100(%esp), %ecx
movl %ecx, %eax
subl $1, %eax
movl %eax, 100(%esp)
scrypt_core_gen_loop2:
movl %ecx, 68(%esp)
movl 64(%edi), %edx
andl 100(%esp), %edx
shll $7, %edx
scrypt_core_macro1b 0, 64
scrypt_core_macro1b 4, 68
scrypt_core_macro1b 8, 72
scrypt_core_macro1b 12, 76
scrypt_core_macro1b 16, 80
scrypt_core_macro1b 20, 84
scrypt_core_macro1b 24, 88
scrypt_core_macro1b 28, 92
scrypt_core_macro1b 32, 96
scrypt_core_macro1b 36, 100
scrypt_core_macro1b 40, 104
scrypt_core_macro1b 44, 108
scrypt_core_macro1b 48, 112
scrypt_core_macro1b 52, 116
scrypt_core_macro1b 56, 120
scrypt_core_macro1b 60, 124
call salsa8_core_gen
movl 92(%esp), %edi
scrypt_core_macro2 0, 64
scrypt_core_macro2 4, 68
scrypt_core_macro2 8, 72
scrypt_core_macro2 12, 76
scrypt_core_macro2 16, 80
scrypt_core_macro2 20, 84
scrypt_core_macro2 24, 88
scrypt_core_macro2 28, 92
scrypt_core_macro2 32, 96
scrypt_core_macro2 36, 100
scrypt_core_macro2 40, 104
scrypt_core_macro2 44, 108
scrypt_core_macro2 48, 112
scrypt_core_macro2 52, 116
scrypt_core_macro2 56, 120
scrypt_core_macro2 60, 124
call salsa8_core_gen
movl 92(%esp), %edi
movl 96(%esp), %esi
scrypt_core_macro3 0, 64
scrypt_core_macro3 4, 68
scrypt_core_macro3 8, 72
scrypt_core_macro3 12, 76
scrypt_core_macro3 16, 80
scrypt_core_macro3 20, 84
scrypt_core_macro3 24, 88
scrypt_core_macro3 28, 92
scrypt_core_macro3 32, 96
scrypt_core_macro3 36, 100
scrypt_core_macro3 40, 104
scrypt_core_macro3 44, 108
scrypt_core_macro3 48, 112
scrypt_core_macro3 52, 116
scrypt_core_macro3 56, 120
scrypt_core_macro3 60, 124
movl 68(%esp), %ecx
subl $1, %ecx
ja scrypt_core_gen_loop2
addl $72, %esp
popl %esi
popl %edi
popl %ebp
popl %ebx
ret
.macro salsa8_core_sse2_doubleround
movdqa %xmm1, %xmm4
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm3
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm3, %xmm3
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm1
pshufd $0x4e, %xmm2, %xmm2
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm0
pshufd $0x39, %xmm1, %xmm1
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm1
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm1, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm1, %xmm1
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm3
pshufd $0x4e, %xmm2, %xmm2
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
pshufd $0x39, %xmm3, %xmm3
pxor %xmm5, %xmm0
.endm
.macro salsa8_core_sse2
salsa8_core_sse2_doubleround
salsa8_core_sse2_doubleround
salsa8_core_sse2_doubleround
salsa8_core_sse2_doubleround
.endm
.p2align 5
scrypt_core_sse2:
movl 20(%esp), %edi
movl 24(%esp), %esi
movl %esp, %ebp
subl $128, %esp
andl $-16, %esp
scrypt_shuffle %edi, 0, %esp, 0
scrypt_shuffle %edi, 64, %esp, 64
movdqa 96(%esp), %xmm6
movdqa 112(%esp), %xmm7
movl %esi, %edx
movl 28(%ebp), %ecx
shll $7, %ecx
addl %esi, %ecx
scrypt_core_sse2_loop1:
movdqa 0(%esp), %xmm0
movdqa 16(%esp), %xmm1
movdqa 32(%esp), %xmm2
movdqa 48(%esp), %xmm3
movdqa 64(%esp), %xmm4
movdqa 80(%esp), %xmm5
pxor %xmm4, %xmm0
pxor %xmm5, %xmm1
movdqa %xmm0, 0(%edx)
movdqa %xmm1, 16(%edx)
pxor %xmm6, %xmm2
pxor %xmm7, %xmm3
movdqa %xmm2, 32(%edx)
movdqa %xmm3, 48(%edx)
movdqa %xmm4, 64(%edx)
movdqa %xmm5, 80(%edx)
movdqa %xmm6, 96(%edx)
movdqa %xmm7, 112(%edx)
salsa8_core_sse2
paddd 0(%edx), %xmm0
paddd 16(%edx), %xmm1
paddd 32(%edx), %xmm2
paddd 48(%edx), %xmm3
movdqa %xmm0, 0(%esp)
movdqa %xmm1, 16(%esp)
movdqa %xmm2, 32(%esp)
movdqa %xmm3, 48(%esp)
pxor 64(%esp), %xmm0
pxor 80(%esp), %xmm1
pxor %xmm6, %xmm2
pxor %xmm7, %xmm3
movdqa %xmm0, 64(%esp)
movdqa %xmm1, 80(%esp)
movdqa %xmm2, %xmm6
movdqa %xmm3, %xmm7
salsa8_core_sse2
paddd 64(%esp), %xmm0
paddd 80(%esp), %xmm1
paddd %xmm2, %xmm6
paddd %xmm3, %xmm7
movdqa %xmm0, 64(%esp)
movdqa %xmm1, 80(%esp)
addl $128, %edx
cmpl %ecx, %edx
jne scrypt_core_sse2_loop1
movdqa 64(%esp), %xmm4
movdqa 80(%esp), %xmm5
movl 28(%ebp), %ecx
movl %ecx, %eax
subl $1, %eax
scrypt_core_sse2_loop2:
movd %xmm4, %edx
movdqa 0(%esp), %xmm0
movdqa 16(%esp), %xmm1
movdqa 32(%esp), %xmm2
movdqa 48(%esp), %xmm3
andl %eax, %edx
shll $7, %edx
pxor 0(%esi, %edx), %xmm0
pxor 16(%esi, %edx), %xmm1
pxor 32(%esi, %edx), %xmm2
pxor 48(%esi, %edx), %xmm3
pxor %xmm4, %xmm0
pxor %xmm5, %xmm1
movdqa %xmm0, 0(%esp)
movdqa %xmm1, 16(%esp)
pxor %xmm6, %xmm2
pxor %xmm7, %xmm3
movdqa %xmm2, 32(%esp)
movdqa %xmm3, 48(%esp)
salsa8_core_sse2
paddd 0(%esp), %xmm0
paddd 16(%esp), %xmm1
paddd 32(%esp), %xmm2
paddd 48(%esp), %xmm3
movdqa %xmm0, 0(%esp)
movdqa %xmm1, 16(%esp)
movdqa %xmm2, 32(%esp)
movdqa %xmm3, 48(%esp)
pxor 64(%esi, %edx), %xmm0
pxor 80(%esi, %edx), %xmm1
pxor 96(%esi, %edx), %xmm2
pxor 112(%esi, %edx), %xmm3
pxor 64(%esp), %xmm0
pxor 80(%esp), %xmm1
pxor %xmm6, %xmm2
pxor %xmm7, %xmm3
movdqa %xmm0, 64(%esp)
movdqa %xmm1, 80(%esp)
movdqa %xmm2, %xmm6
movdqa %xmm3, %xmm7
salsa8_core_sse2
paddd 64(%esp), %xmm0
paddd 80(%esp), %xmm1
paddd %xmm2, %xmm6
paddd %xmm3, %xmm7
movdqa %xmm0, %xmm4
movdqa %xmm1, %xmm5
movdqa %xmm0, 64(%esp)
movdqa %xmm1, 80(%esp)
subl $1, %ecx
ja scrypt_core_sse2_loop2
movdqa %xmm6, 96(%esp)
movdqa %xmm7, 112(%esp)
scrypt_shuffle %esp, 0, %edi, 0
scrypt_shuffle %esp, 64, %edi, 64
movl %ebp, %esp
popl %esi
popl %edi
popl %ebp
popl %ebx
ret
#endif
|
WyvernTKC/cpuminer-gr-avx2 | 26,517 | asm/sha2-x86.S | /*
* Copyright 2012 pooler@litecoinpool.org
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version. See COPYING for more details.
*/
#include <cpuminer-config.h>
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(USE_ASM) && defined(__i386__)
.data
.p2align 7
sha256_4h:
.long 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667
.long 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85
.long 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372
.long 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a
.long 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f
.long 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c
.long 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab
.long 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19
.data
.p2align 7
sha256_4k:
.long 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98
.long 0x71374491, 0x71374491, 0x71374491, 0x71374491
.long 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf
.long 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5
.long 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b
.long 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1
.long 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4
.long 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5
.long 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98
.long 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01
.long 0x243185be, 0x243185be, 0x243185be, 0x243185be
.long 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3
.long 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74
.long 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe
.long 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7
.long 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174
.long 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1
.long 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786
.long 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6
.long 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc
.long 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f
.long 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa
.long 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc
.long 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da
.long 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152
.long 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d
.long 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8
.long 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7
.long 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3
.long 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147
.long 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351
.long 0x14292967, 0x14292967, 0x14292967, 0x14292967
.long 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85
.long 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138
.long 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc
.long 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13
.long 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354
.long 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb
.long 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e
.long 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85
.long 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1
.long 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b
.long 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70
.long 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3
.long 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819
.long 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624
.long 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585
.long 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070
.long 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116
.long 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08
.long 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c
.long 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5
.long 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3
.long 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a
.long 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f
.long 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3
.long 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee
.long 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f
.long 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814
.long 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208
.long 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa
.long 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb
.long 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7
.long 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2
.data
.p2align 6
sha256d_4preext2_15:
.long 0x00000100, 0x00000100, 0x00000100, 0x00000100
sha256d_4preext2_17:
.long 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000
sha256d_4preext2_23:
.long 0x11002000, 0x11002000, 0x11002000, 0x11002000
sha256d_4preext2_24:
.long 0x80000000, 0x80000000, 0x80000000, 0x80000000
sha256d_4preext2_30:
.long 0x00400022, 0x00400022, 0x00400022, 0x00400022
.text
.p2align 5
.globl sha256_init_4way
.globl _sha256_init_4way
sha256_init_4way:
_sha256_init_4way:
movl 4(%esp), %edx
movdqa sha256_4h+0, %xmm0
movdqa sha256_4h+16, %xmm1
movdqa sha256_4h+32, %xmm2
movdqa sha256_4h+48, %xmm3
movdqu %xmm0, 0(%edx)
movdqu %xmm1, 16(%edx)
movdqu %xmm2, 32(%edx)
movdqu %xmm3, 48(%edx)
movdqa sha256_4h+64, %xmm0
movdqa sha256_4h+80, %xmm1
movdqa sha256_4h+96, %xmm2
movdqa sha256_4h+112, %xmm3
movdqu %xmm0, 64(%edx)
movdqu %xmm1, 80(%edx)
movdqu %xmm2, 96(%edx)
movdqu %xmm3, 112(%edx)
ret
.macro sha256_sse2_extend_round i
movdqa (\i-15)*16(%eax), %xmm0
movdqa %xmm0, %xmm2
psrld $3, %xmm0
movdqa %xmm0, %xmm1
pslld $14, %xmm2
psrld $4, %xmm1
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
psrld $11, %xmm1
pslld $11, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
paddd (\i-16)*16(%eax), %xmm0
paddd (\i-7)*16(%eax), %xmm0
movdqa %xmm3, %xmm2
psrld $10, %xmm3
pslld $13, %xmm2
movdqa %xmm3, %xmm1
psrld $7, %xmm1
pxor %xmm1, %xmm3
pxor %xmm2, %xmm3
psrld $2, %xmm1
pslld $2, %xmm2
pxor %xmm1, %xmm3
pxor %xmm2, %xmm3
paddd %xmm0, %xmm3
movdqa %xmm3, \i*16(%eax)
.endm
.macro sha256_sse2_extend_doubleround i
movdqa (\i-15)*16(%eax), %xmm0
movdqa (\i-14)*16(%eax), %xmm4
movdqa %xmm0, %xmm2
movdqa %xmm4, %xmm6
psrld $3, %xmm0
psrld $3, %xmm4
movdqa %xmm0, %xmm1
movdqa %xmm4, %xmm5
pslld $14, %xmm2
pslld $14, %xmm6
psrld $4, %xmm1
psrld $4, %xmm5
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
psrld $11, %xmm1
psrld $11, %xmm5
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
pslld $11, %xmm2
pslld $11, %xmm6
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
paddd (\i-16)*16(%eax), %xmm0
paddd (\i-15)*16(%eax), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd (\i-7)*16(%eax), %xmm0
paddd (\i-6)*16(%eax), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, \i*16(%eax)
movdqa %xmm7, (\i+1)*16(%eax)
.endm
.macro sha256_sse2_main_round i
movdqa 16*(\i)(%eax), %xmm6
movdqa %xmm0, %xmm1
movdqa 16(%esp), %xmm2
pandn %xmm2, %xmm1
paddd 32(%esp), %xmm6
movdqa %xmm2, 32(%esp)
movdqa 0(%esp), %xmm2
movdqa %xmm2, 16(%esp)
pand %xmm0, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm0, 0(%esp)
paddd %xmm1, %xmm6
movdqa %xmm0, %xmm1
psrld $6, %xmm0
paddd 16*(\i)+sha256_4k, %xmm6
movdqa %xmm0, %xmm2
pslld $7, %xmm1
psrld $5, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $14, %xmm1
psrld $14, %xmm2
pxor %xmm1, %xmm0
pslld $5, %xmm1
pxor %xmm2, %xmm0
pxor %xmm1, %xmm0
movdqa %xmm5, %xmm1
paddd %xmm0, %xmm6
movdqa %xmm3, %xmm0
movdqa %xmm4, %xmm3
movdqa %xmm4, %xmm2
paddd %xmm6, %xmm0
pand %xmm5, %xmm2
pand %xmm7, %xmm1
pand %xmm7, %xmm4
pxor %xmm4, %xmm1
movdqa %xmm5, %xmm4
movdqa %xmm7, %xmm5
pxor %xmm2, %xmm1
paddd %xmm1, %xmm6
movdqa %xmm7, %xmm2
psrld $2, %xmm7
movdqa %xmm7, %xmm1
pslld $10, %xmm2
psrld $11, %xmm1
pxor %xmm2, %xmm7
pslld $9, %xmm2
pxor %xmm1, %xmm7
psrld $9, %xmm1
pxor %xmm2, %xmm7
pslld $11, %xmm2
pxor %xmm1, %xmm7
pxor %xmm2, %xmm7
paddd %xmm6, %xmm7
.endm
.macro sha256_sse2_main_quadround i
sha256_sse2_main_round \i+0
sha256_sse2_main_round \i+1
sha256_sse2_main_round \i+2
sha256_sse2_main_round \i+3
.endm
.macro p2bswap_esi_esp i
movdqu \i*16(%esi), %xmm0
movdqu (\i+1)*16(%esi), %xmm2
pshuflw $0xb1, %xmm0, %xmm0
pshuflw $0xb1, %xmm2, %xmm2
pshufhw $0xb1, %xmm0, %xmm0
pshufhw $0xb1, %xmm2, %xmm2
movdqa %xmm0, %xmm1
movdqa %xmm2, %xmm3
psrlw $8, %xmm1
psrlw $8, %xmm3
psllw $8, %xmm0
psllw $8, %xmm2
pxor %xmm1, %xmm0
pxor %xmm3, %xmm2
movdqa %xmm0, (\i+3)*16(%esp)
movdqa %xmm2, (\i+4)*16(%esp)
.endm
.text
.p2align 5
.globl sha256_transform_4way
.globl _sha256_transform_4way
sha256_transform_4way:
_sha256_transform_4way:
pushl %edi
pushl %esi
movl 12(%esp), %edi
movl 16(%esp), %esi
movl 20(%esp), %ecx
movl %esp, %edx
subl $67*16, %esp
andl $-128, %esp
testl %ecx, %ecx
jnz sha256_transform_4way_swap
movdqu 0*16(%esi), %xmm0
movdqu 1*16(%esi), %xmm1
movdqu 2*16(%esi), %xmm2
movdqu 3*16(%esi), %xmm3
movdqu 4*16(%esi), %xmm4
movdqu 5*16(%esi), %xmm5
movdqu 6*16(%esi), %xmm6
movdqu 7*16(%esi), %xmm7
movdqa %xmm0, 3*16(%esp)
movdqa %xmm1, 4*16(%esp)
movdqa %xmm2, 5*16(%esp)
movdqa %xmm3, 6*16(%esp)
movdqa %xmm4, 7*16(%esp)
movdqa %xmm5, 8*16(%esp)
movdqa %xmm6, 9*16(%esp)
movdqa %xmm7, 10*16(%esp)
movdqu 8*16(%esi), %xmm0
movdqu 9*16(%esi), %xmm1
movdqu 10*16(%esi), %xmm2
movdqu 11*16(%esi), %xmm3
movdqu 12*16(%esi), %xmm4
movdqu 13*16(%esi), %xmm5
movdqu 14*16(%esi), %xmm6
movdqu 15*16(%esi), %xmm7
movdqa %xmm0, 11*16(%esp)
movdqa %xmm1, 12*16(%esp)
movdqa %xmm2, 13*16(%esp)
movdqa %xmm3, 14*16(%esp)
movdqa %xmm4, 15*16(%esp)
movdqa %xmm5, 16*16(%esp)
movdqa %xmm6, 17*16(%esp)
movdqa %xmm7, 18*16(%esp)
jmp sha256_transform_4way_extend
.p2align 5
sha256_transform_4way_swap:
p2bswap_esi_esp 0
p2bswap_esi_esp 2
p2bswap_esi_esp 4
p2bswap_esi_esp 6
p2bswap_esi_esp 8
p2bswap_esi_esp 10
p2bswap_esi_esp 12
p2bswap_esi_esp 14
sha256_transform_4way_extend:
leal 19*16(%esp), %ecx
leal 48*16(%ecx), %eax
movdqa -2*16(%ecx), %xmm3
movdqa -1*16(%ecx), %xmm7
sha256_transform_4way_extend_loop:
movdqa -15*16(%ecx), %xmm0
movdqa -14*16(%ecx), %xmm4
movdqa %xmm0, %xmm2
movdqa %xmm4, %xmm6
psrld $3, %xmm0
psrld $3, %xmm4
movdqa %xmm0, %xmm1
movdqa %xmm4, %xmm5
pslld $14, %xmm2
pslld $14, %xmm6
psrld $4, %xmm1
psrld $4, %xmm5
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
psrld $11, %xmm1
psrld $11, %xmm5
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
pslld $11, %xmm2
pslld $11, %xmm6
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
paddd -16*16(%ecx), %xmm0
paddd -15*16(%ecx), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd -7*16(%ecx), %xmm0
paddd -6*16(%ecx), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, (%ecx)
movdqa %xmm7, 16(%ecx)
addl $2*16, %ecx
cmpl %ecx, %eax
jne sha256_transform_4way_extend_loop
movdqu 0(%edi), %xmm7
movdqu 16(%edi), %xmm5
movdqu 32(%edi), %xmm4
movdqu 48(%edi), %xmm3
movdqu 64(%edi), %xmm0
movdqu 80(%edi), %xmm1
movdqu 96(%edi), %xmm2
movdqu 112(%edi), %xmm6
movdqa %xmm1, 0(%esp)
movdqa %xmm2, 16(%esp)
movdqa %xmm6, 32(%esp)
xorl %eax, %eax
sha256_transform_4way_main_loop:
movdqa 3*16(%esp, %eax), %xmm6
paddd sha256_4k(%eax), %xmm6
paddd 32(%esp), %xmm6
movdqa %xmm0, %xmm1
movdqa 16(%esp), %xmm2
pandn %xmm2, %xmm1
movdqa %xmm2, 32(%esp)
movdqa 0(%esp), %xmm2
movdqa %xmm2, 16(%esp)
pand %xmm0, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm0, 0(%esp)
paddd %xmm1, %xmm6
movdqa %xmm0, %xmm1
psrld $6, %xmm0
movdqa %xmm0, %xmm2
pslld $7, %xmm1
psrld $5, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $14, %xmm1
psrld $14, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $5, %xmm1
pxor %xmm1, %xmm0
paddd %xmm0, %xmm6
movdqa %xmm3, %xmm0
paddd %xmm6, %xmm0
movdqa %xmm5, %xmm1
movdqa %xmm4, %xmm3
movdqa %xmm4, %xmm2
pand %xmm5, %xmm2
pand %xmm7, %xmm4
pand %xmm7, %xmm1
pxor %xmm4, %xmm1
movdqa %xmm5, %xmm4
movdqa %xmm7, %xmm5
pxor %xmm2, %xmm1
paddd %xmm1, %xmm6
movdqa %xmm7, %xmm2
psrld $2, %xmm7
movdqa %xmm7, %xmm1
pslld $10, %xmm2
psrld $11, %xmm1
pxor %xmm2, %xmm7
pxor %xmm1, %xmm7
pslld $9, %xmm2
psrld $9, %xmm1
pxor %xmm2, %xmm7
pxor %xmm1, %xmm7
pslld $11, %xmm2
pxor %xmm2, %xmm7
paddd %xmm6, %xmm7
addl $16, %eax
cmpl $16*64, %eax
jne sha256_transform_4way_main_loop
movdqu 0(%edi), %xmm1
movdqu 16(%edi), %xmm2
paddd %xmm1, %xmm7
paddd %xmm2, %xmm5
movdqu 32(%edi), %xmm1
movdqu 48(%edi), %xmm2
paddd %xmm1, %xmm4
paddd %xmm2, %xmm3
movdqu %xmm7, 0(%edi)
movdqu %xmm5, 16(%edi)
movdqu %xmm4, 32(%edi)
movdqu %xmm3, 48(%edi)
movdqu 64(%edi), %xmm1
movdqu 80(%edi), %xmm2
movdqu 96(%edi), %xmm6
movdqu 112(%edi), %xmm7
paddd %xmm1, %xmm0
paddd 0(%esp), %xmm2
paddd 16(%esp), %xmm6
paddd 32(%esp), %xmm7
movdqu %xmm0, 64(%edi)
movdqu %xmm2, 80(%edi)
movdqu %xmm6, 96(%edi)
movdqu %xmm7, 112(%edi)
movl %edx, %esp
popl %esi
popl %edi
ret
.text
.p2align 5
.globl sha256d_ms_4way
.globl _sha256d_ms_4way
sha256d_ms_4way:
_sha256d_ms_4way:
pushl %edi
pushl %esi
pushl %ebp
movl 16(%esp), %edi
movl 20(%esp), %esi
movl 24(%esp), %edx
movl 28(%esp), %ecx
movl %esp, %ebp
subl $67*16, %esp
andl $-128, %esp
leal 256(%esi), %eax
sha256d_ms_4way_extend_loop1:
movdqa 3*16(%esi), %xmm0
movdqa 2*16(%eax), %xmm3
movdqa 3*16(%eax), %xmm7
movdqa %xmm3, 5*16(%esp)
movdqa %xmm7, 6*16(%esp)
movdqa %xmm0, %xmm2
paddd %xmm0, %xmm7
psrld $3, %xmm0
movdqa %xmm0, %xmm1
pslld $14, %xmm2
psrld $4, %xmm1
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
psrld $11, %xmm1
pslld $11, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
paddd %xmm0, %xmm3
movdqa %xmm3, 2*16(%eax)
movdqa %xmm7, 3*16(%eax)
movdqa 4*16(%eax), %xmm0
movdqa %xmm0, 7*16(%esp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
movdqa %xmm3, 4*16(%eax)
movdqa %xmm7, 5*16(%eax)
movdqa 6*16(%eax), %xmm0
movdqa 7*16(%eax), %xmm4
movdqa %xmm0, 9*16(%esp)
movdqa %xmm4, 10*16(%esp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 6*16(%eax)
movdqa %xmm7, 7*16(%eax)
movdqa 8*16(%eax), %xmm0
movdqa 2*16(%eax), %xmm4
movdqa %xmm0, 11*16(%esp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 8*16(%eax)
movdqa %xmm7, 9*16(%eax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 3*16(%eax), %xmm3
paddd 4*16(%eax), %xmm7
movdqa %xmm3, 10*16(%eax)
movdqa %xmm7, 11*16(%eax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 5*16(%eax), %xmm3
paddd 6*16(%eax), %xmm7
movdqa %xmm3, 12*16(%eax)
movdqa %xmm7, 13*16(%eax)
movdqa 14*16(%eax), %xmm0
movdqa 15*16(%eax), %xmm4
movdqa %xmm0, 17*16(%esp)
movdqa %xmm4, 18*16(%esp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd 7*16(%eax), %xmm0
paddd 8*16(%eax), %xmm4
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 14*16(%eax)
movdqa %xmm7, 15*16(%eax)
sha256d_ms_4way_extend_loop2:
sha256_sse2_extend_doubleround 16
sha256_sse2_extend_doubleround 18
sha256_sse2_extend_doubleround 20
sha256_sse2_extend_doubleround 22
sha256_sse2_extend_doubleround 24
sha256_sse2_extend_doubleround 26
sha256_sse2_extend_doubleround 28
sha256_sse2_extend_doubleround 30
sha256_sse2_extend_doubleround 32
sha256_sse2_extend_doubleround 34
sha256_sse2_extend_doubleround 36
sha256_sse2_extend_doubleround 38
sha256_sse2_extend_doubleround 40
sha256_sse2_extend_doubleround 42
jz sha256d_ms_4way_extend_coda2
sha256_sse2_extend_doubleround 44
sha256_sse2_extend_doubleround 46
movdqa 0(%ecx), %xmm3
movdqa 16(%ecx), %xmm0
movdqa 32(%ecx), %xmm1
movdqa 48(%ecx), %xmm2
movdqa 64(%ecx), %xmm6
movdqa 80(%ecx), %xmm7
movdqa 96(%ecx), %xmm5
movdqa 112(%ecx), %xmm4
movdqa %xmm1, 0(%esp)
movdqa %xmm2, 16(%esp)
movdqa %xmm6, 32(%esp)
movl %esi, %eax
jmp sha256d_ms_4way_main_loop1
sha256d_ms_4way_main_loop2:
sha256_sse2_main_round 0
sha256_sse2_main_round 1
sha256_sse2_main_round 2
sha256d_ms_4way_main_loop1:
sha256_sse2_main_round 3
sha256_sse2_main_quadround 4
sha256_sse2_main_quadround 8
sha256_sse2_main_quadround 12
sha256_sse2_main_quadround 16
sha256_sse2_main_quadround 20
sha256_sse2_main_quadround 24
sha256_sse2_main_quadround 28
sha256_sse2_main_quadround 32
sha256_sse2_main_quadround 36
sha256_sse2_main_quadround 40
sha256_sse2_main_quadround 44
sha256_sse2_main_quadround 48
sha256_sse2_main_quadround 52
sha256_sse2_main_round 56
jz sha256d_ms_4way_finish
sha256_sse2_main_round 57
sha256_sse2_main_round 58
sha256_sse2_main_round 59
sha256_sse2_main_quadround 60
movdqa 5*16(%esp), %xmm1
movdqa 6*16(%esp), %xmm2
movdqa 7*16(%esp), %xmm6
movdqa %xmm1, 18*16(%esi)
movdqa %xmm2, 19*16(%esi)
movdqa %xmm6, 20*16(%esi)
movdqa 9*16(%esp), %xmm1
movdqa 10*16(%esp), %xmm2
movdqa 11*16(%esp), %xmm6
movdqa %xmm1, 22*16(%esi)
movdqa %xmm2, 23*16(%esi)
movdqa %xmm6, 24*16(%esi)
movdqa 17*16(%esp), %xmm1
movdqa 18*16(%esp), %xmm2
movdqa %xmm1, 30*16(%esi)
movdqa %xmm2, 31*16(%esi)
movdqa 0(%esp), %xmm1
movdqa 16(%esp), %xmm2
movdqa 32(%esp), %xmm6
paddd 0(%edx), %xmm7
paddd 16(%edx), %xmm5
paddd 32(%edx), %xmm4
paddd 48(%edx), %xmm3
paddd 64(%edx), %xmm0
paddd 80(%edx), %xmm1
paddd 96(%edx), %xmm2
paddd 112(%edx), %xmm6
movdqa %xmm7, 48+0(%esp)
movdqa %xmm5, 48+16(%esp)
movdqa %xmm4, 48+32(%esp)
movdqa %xmm3, 48+48(%esp)
movdqa %xmm0, 48+64(%esp)
movdqa %xmm1, 48+80(%esp)
movdqa %xmm2, 48+96(%esp)
movdqa %xmm6, 48+112(%esp)
movdqa sha256d_4preext2_15, %xmm1
movdqa sha256d_4preext2_24, %xmm2
pxor %xmm0, %xmm0
movdqa %xmm2, 48+128(%esp)
movdqa %xmm0, 48+144(%esp)
movdqa %xmm0, 48+160(%esp)
movdqa %xmm0, 48+176(%esp)
movdqa %xmm0, 48+192(%esp)
movdqa %xmm0, 48+208(%esp)
movdqa %xmm0, 48+224(%esp)
movdqa %xmm1, 48+240(%esp)
leal 19*16(%esp), %eax
cmpl %eax, %eax
movdqa -15*16(%eax), %xmm0
movdqa -14*16(%eax), %xmm4
movdqa %xmm0, %xmm2
movdqa %xmm4, %xmm6
psrld $3, %xmm0
psrld $3, %xmm4
movdqa %xmm0, %xmm1
movdqa %xmm4, %xmm5
pslld $14, %xmm2
pslld $14, %xmm6
psrld $4, %xmm1
psrld $4, %xmm5
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
psrld $11, %xmm1
psrld $11, %xmm5
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
pslld $11, %xmm2
pslld $11, %xmm6
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
paddd -16*16(%eax), %xmm0
paddd -15*16(%eax), %xmm4
paddd sha256d_4preext2_17, %xmm4
movdqa %xmm0, %xmm3
movdqa %xmm4, %xmm7
movdqa %xmm3, 0*16(%eax)
movdqa %xmm7, 1*16(%eax)
sha256_sse2_extend_doubleround 2
sha256_sse2_extend_doubleround 4
movdqa -9*16(%eax), %xmm0
movdqa sha256d_4preext2_23, %xmm4
movdqa %xmm0, %xmm2
psrld $3, %xmm0
movdqa %xmm0, %xmm1
pslld $14, %xmm2
psrld $4, %xmm1
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
psrld $11, %xmm1
pslld $11, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
paddd -10*16(%eax), %xmm0
paddd -9*16(%eax), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd -1*16(%eax), %xmm0
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd 0*16(%eax), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 6*16(%eax)
movdqa %xmm7, 7*16(%eax)
movdqa sha256d_4preext2_24, %xmm0
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd 1*16(%eax), %xmm0
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd 2*16(%eax), %xmm7
movdqa %xmm3, 8*16(%eax)
movdqa %xmm7, 9*16(%eax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 3*16(%eax), %xmm3
paddd 4*16(%eax), %xmm7
movdqa %xmm3, 10*16(%eax)
movdqa %xmm7, 11*16(%eax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 5*16(%eax), %xmm3
paddd 6*16(%eax), %xmm7
movdqa %xmm3, 12*16(%eax)
movdqa %xmm7, 13*16(%eax)
movdqa sha256d_4preext2_30, %xmm0
movdqa 0*16(%eax), %xmm4
movdqa %xmm4, %xmm6
psrld $3, %xmm4
movdqa %xmm4, %xmm5
pslld $14, %xmm6
psrld $4, %xmm5
pxor %xmm5, %xmm4
pxor %xmm6, %xmm4
psrld $11, %xmm5
pslld $11, %xmm6
pxor %xmm5, %xmm4
pxor %xmm6, %xmm4
paddd -1*16(%eax), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd 7*16(%eax), %xmm0
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd 8*16(%eax), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 14*16(%eax)
movdqa %xmm7, 15*16(%eax)
jmp sha256d_ms_4way_extend_loop2
sha256d_ms_4way_extend_coda2:
sha256_sse2_extend_round 44
movdqa sha256_4h+0, %xmm7
movdqa sha256_4h+16, %xmm5
movdqa sha256_4h+32, %xmm4
movdqa sha256_4h+48, %xmm3
movdqa sha256_4h+64, %xmm0
movdqa sha256_4h+80, %xmm1
movdqa sha256_4h+96, %xmm2
movdqa sha256_4h+112, %xmm6
movdqa %xmm1, 0(%esp)
movdqa %xmm2, 16(%esp)
movdqa %xmm6, 32(%esp)
leal 48(%esp), %eax
jmp sha256d_ms_4way_main_loop2
.macro sha256_sse2_main_round_red i, r7
movdqa 16*(\i)(%eax), %xmm6
paddd 16*(\i)+sha256_4k, %xmm6
paddd 32(%esp), %xmm6
movdqa %xmm0, %xmm1
movdqa 16(%esp), %xmm2
paddd \r7, %xmm6
pandn %xmm2, %xmm1
movdqa %xmm2, 32(%esp)
movdqa 0(%esp), %xmm2
movdqa %xmm2, 16(%esp)
pand %xmm0, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm0, 0(%esp)
paddd %xmm1, %xmm6
movdqa %xmm0, %xmm1
psrld $6, %xmm0
movdqa %xmm0, %xmm2
pslld $7, %xmm1
psrld $5, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $14, %xmm1
psrld $14, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $5, %xmm1
pxor %xmm1, %xmm0
paddd %xmm6, %xmm0
.endm
sha256d_ms_4way_finish:
sha256_sse2_main_round_red 57, %xmm3
sha256_sse2_main_round_red 58, %xmm4
sha256_sse2_main_round_red 59, %xmm5
sha256_sse2_main_round_red 60, %xmm7
paddd sha256_4h+112, %xmm0
movdqa %xmm0, 112(%edi)
movl %ebp, %esp
popl %ebp
popl %esi
popl %edi
ret
.text
.p2align 5
.globl sha256_use_4way
.globl _sha256_use_4way
sha256_use_4way:
_sha256_use_4way:
pushl %ebx
/* Check for SSE2 availability */
movl $1, %eax
cpuid
andl $0x04000000, %edx
jnz sha256_use_4way_sse2
xorl %eax, %eax
popl %ebx
ret
sha256_use_4way_sse2:
movl $1, %eax
popl %ebx
ret
#endif
|
WyvernTKC/cpuminer-gr-avx2 | 71,360 | asm/scrypt-x64.S | /*
* Copyright 2011-2014 pooler@litecoinpool.org
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <cpuminer-config.h>
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(USE_ASM) && defined(__x86_64__)
.text
.p2align 6
.globl scrypt_best_throughput
.globl _scrypt_best_throughput
scrypt_best_throughput:
_scrypt_best_throughput:
pushq %rbx
#if defined(USE_AVX2)
/* Check for AVX and OSXSAVE support */
movl $1, %eax
cpuid
andl $0x18000000, %ecx
cmpl $0x18000000, %ecx
jne scrypt_best_throughput_no_avx2
/* Check for AVX2 support */
movl $7, %eax
xorl %ecx, %ecx
cpuid
andl $0x00000020, %ebx
cmpl $0x00000020, %ebx
jne scrypt_best_throughput_no_avx2
/* Check for XMM and YMM state support */
xorl %ecx, %ecx
xgetbv
andl $0x00000006, %eax
cmpl $0x00000006, %eax
jne scrypt_best_throughput_no_avx2
movl $6, %eax
jmp scrypt_best_throughput_exit
scrypt_best_throughput_no_avx2:
#endif
/* Check for AuthenticAMD */
xorq %rax, %rax
cpuid
movl $3, %eax
cmpl $0x444d4163, %ecx
jne scrypt_best_throughput_not_amd
cmpl $0x69746e65, %edx
jne scrypt_best_throughput_not_amd
cmpl $0x68747541, %ebx
jne scrypt_best_throughput_not_amd
/* Check for AMD K8 or Bobcat */
movl $1, %eax
cpuid
andl $0x0ff00000, %eax
jz scrypt_best_throughput_one
cmpl $0x00500000, %eax
je scrypt_best_throughput_one
movl $3, %eax
jmp scrypt_best_throughput_exit
scrypt_best_throughput_not_amd:
/* Check for GenuineIntel */
cmpl $0x6c65746e, %ecx
jne scrypt_best_throughput_exit
cmpl $0x49656e69, %edx
jne scrypt_best_throughput_exit
cmpl $0x756e6547, %ebx
jne scrypt_best_throughput_exit
/* Check for Intel Atom */
movl $1, %eax
cpuid
movl %eax, %edx
andl $0x0ff00f00, %eax
cmpl $0x00000600, %eax
movl $3, %eax
jnz scrypt_best_throughput_exit
andl $0x000f00f0, %edx
cmpl $0x000100c0, %edx
je scrypt_best_throughput_one
cmpl $0x00020060, %edx
je scrypt_best_throughput_one
cmpl $0x00030060, %edx
jne scrypt_best_throughput_exit
scrypt_best_throughput_one:
movl $1, %eax
scrypt_best_throughput_exit:
popq %rbx
ret
.macro scrypt_shuffle src, so, dest, do
movl \so+60(\src), %eax
movl \so+44(\src), %ebx
movl \so+28(\src), %ecx
movl \so+12(\src), %edx
movl %eax, \do+12(\dest)
movl %ebx, \do+28(\dest)
movl %ecx, \do+44(\dest)
movl %edx, \do+60(\dest)
movl \so+40(\src), %eax
movl \so+8(\src), %ebx
movl \so+48(\src), %ecx
movl \so+16(\src), %edx
movl %eax, \do+8(\dest)
movl %ebx, \do+40(\dest)
movl %ecx, \do+16(\dest)
movl %edx, \do+48(\dest)
movl \so+20(\src), %eax
movl \so+4(\src), %ebx
movl \so+52(\src), %ecx
movl \so+36(\src), %edx
movl %eax, \do+4(\dest)
movl %ebx, \do+20(\dest)
movl %ecx, \do+36(\dest)
movl %edx, \do+52(\dest)
movl \so+0(\src), %eax
movl \so+24(\src), %ebx
movl \so+32(\src), %ecx
movl \so+56(\src), %edx
movl %eax, \do+0(\dest)
movl %ebx, \do+24(\dest)
movl %ecx, \do+32(\dest)
movl %edx, \do+56(\dest)
.endm
.macro salsa8_core_gen_doubleround
movq 72(%rsp), %r15
leaq (%r14, %rdx), %rbp
roll $7, %ebp
xorl %ebp, %r9d
leaq (%rdi, %r15), %rbp
roll $7, %ebp
xorl %ebp, %r10d
leaq (%rdx, %r9), %rbp
roll $9, %ebp
xorl %ebp, %r11d
leaq (%r15, %r10), %rbp
roll $9, %ebp
xorl %ebp, %r13d
leaq (%r9, %r11), %rbp
roll $13, %ebp
xorl %ebp, %r14d
leaq (%r10, %r13), %rbp
roll $13, %ebp
xorl %ebp, %edi
leaq (%r11, %r14), %rbp
roll $18, %ebp
xorl %ebp, %edx
leaq (%r13, %rdi), %rbp
roll $18, %ebp
xorl %ebp, %r15d
movq 48(%rsp), %rbp
movq %r15, 72(%rsp)
leaq (%rax, %rbp), %r15
roll $7, %r15d
xorl %r15d, %ebx
leaq (%rbp, %rbx), %r15
roll $9, %r15d
xorl %r15d, %ecx
leaq (%rbx, %rcx), %r15
roll $13, %r15d
xorl %r15d, %eax
leaq (%rcx, %rax), %r15
roll $18, %r15d
xorl %r15d, %ebp
movq 88(%rsp), %r15
movq %rbp, 48(%rsp)
leaq (%r12, %r15), %rbp
roll $7, %ebp
xorl %ebp, %esi
leaq (%r15, %rsi), %rbp
roll $9, %ebp
xorl %ebp, %r8d
leaq (%rsi, %r8), %rbp
roll $13, %ebp
xorl %ebp, %r12d
leaq (%r8, %r12), %rbp
roll $18, %ebp
xorl %ebp, %r15d
movq %r15, 88(%rsp)
movq 72(%rsp), %r15
leaq (%rsi, %rdx), %rbp
roll $7, %ebp
xorl %ebp, %edi
leaq (%r9, %r15), %rbp
roll $7, %ebp
xorl %ebp, %eax
leaq (%rdx, %rdi), %rbp
roll $9, %ebp
xorl %ebp, %ecx
leaq (%r15, %rax), %rbp
roll $9, %ebp
xorl %ebp, %r8d
leaq (%rdi, %rcx), %rbp
roll $13, %ebp
xorl %ebp, %esi
leaq (%rax, %r8), %rbp
roll $13, %ebp
xorl %ebp, %r9d
leaq (%rcx, %rsi), %rbp
roll $18, %ebp
xorl %ebp, %edx
leaq (%r8, %r9), %rbp
roll $18, %ebp
xorl %ebp, %r15d
movq 48(%rsp), %rbp
movq %r15, 72(%rsp)
leaq (%r10, %rbp), %r15
roll $7, %r15d
xorl %r15d, %r12d
leaq (%rbp, %r12), %r15
roll $9, %r15d
xorl %r15d, %r11d
leaq (%r12, %r11), %r15
roll $13, %r15d
xorl %r15d, %r10d
leaq (%r11, %r10), %r15
roll $18, %r15d
xorl %r15d, %ebp
movq 88(%rsp), %r15
movq %rbp, 48(%rsp)
leaq (%rbx, %r15), %rbp
roll $7, %ebp
xorl %ebp, %r14d
leaq (%r15, %r14), %rbp
roll $9, %ebp
xorl %ebp, %r13d
leaq (%r14, %r13), %rbp
roll $13, %ebp
xorl %ebp, %ebx
leaq (%r13, %rbx), %rbp
roll $18, %ebp
xorl %ebp, %r15d
movq %r15, 88(%rsp)
.endm
.text
.p2align 6
salsa8_core_gen:
/* 0: %rdx, %rdi, %rcx, %rsi */
movq 8(%rsp), %rdi
movq %rdi, %rdx
shrq $32, %rdi
movq 16(%rsp), %rsi
movq %rsi, %rcx
shrq $32, %rsi
/* 1: %r9, 72(%rsp), %rax, %r8 */
movq 24(%rsp), %r8
movq %r8, %r9
shrq $32, %r8
movq %r8, 72(%rsp)
movq 32(%rsp), %r8
movq %r8, %rax
shrq $32, %r8
/* 2: %r11, %r10, 48(%rsp), %r12 */
movq 40(%rsp), %r10
movq %r10, %r11
shrq $32, %r10
movq 48(%rsp), %r12
/* movq %r12, %r13 */
/* movq %r13, 48(%rsp) */
shrq $32, %r12
/* 3: %r14, %r13, %rbx, 88(%rsp) */
movq 56(%rsp), %r13
movq %r13, %r14
shrq $32, %r13
movq 64(%rsp), %r15
movq %r15, %rbx
shrq $32, %r15
movq %r15, 88(%rsp)
salsa8_core_gen_doubleround
salsa8_core_gen_doubleround
salsa8_core_gen_doubleround
salsa8_core_gen_doubleround
shlq $32, %rdi
xorq %rdi, %rdx
movq %rdx, 24(%rsp)
shlq $32, %rsi
xorq %rsi, %rcx
movq %rcx, 32(%rsp)
movl 72(%rsp), %edi
shlq $32, %rdi
xorq %rdi, %r9
movq %r9, 40(%rsp)
movl 48(%rsp), %ebp
shlq $32, %r8
xorq %r8, %rax
movq %rax, 48(%rsp)
shlq $32, %r10
xorq %r10, %r11
movq %r11, 56(%rsp)
shlq $32, %r12
xorq %r12, %rbp
movq %rbp, 64(%rsp)
shlq $32, %r13
xorq %r13, %r14
movq %r14, 72(%rsp)
movdqa 24(%rsp), %xmm0
shlq $32, %r15
xorq %r15, %rbx
movq %rbx, 80(%rsp)
movdqa 40(%rsp), %xmm1
movdqa 56(%rsp), %xmm2
movdqa 72(%rsp), %xmm3
ret
.text
.p2align 6
.globl scrypt_core
.globl _scrypt_core
scrypt_core:
_scrypt_core:
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
#if defined(_WIN64) || defined(__CYGWIN__)
subq $176, %rsp
movdqa %xmm6, 8(%rsp)
movdqa %xmm7, 24(%rsp)
movdqa %xmm8, 40(%rsp)
movdqa %xmm9, 56(%rsp)
movdqa %xmm10, 72(%rsp)
movdqa %xmm11, 88(%rsp)
movdqa %xmm12, 104(%rsp)
movdqa %xmm13, 120(%rsp)
movdqa %xmm14, 136(%rsp)
movdqa %xmm15, 152(%rsp)
pushq %rdi
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
#else
movq %rdx, %r8
#endif
.macro scrypt_core_cleanup
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
popq %rdi
movdqa 8(%rsp), %xmm6
movdqa 24(%rsp), %xmm7
movdqa 40(%rsp), %xmm8
movdqa 56(%rsp), %xmm9
movdqa 72(%rsp), %xmm10
movdqa 88(%rsp), %xmm11
movdqa 104(%rsp), %xmm12
movdqa 120(%rsp), %xmm13
movdqa 136(%rsp), %xmm14
movdqa 152(%rsp), %xmm15
addq $176, %rsp
#endif
popq %r15
popq %r14
popq %r13
popq %r12
popq %rbp
popq %rbx
.endm
/* GenuineIntel processors have fast SIMD */
xorl %eax, %eax
cpuid
cmpl $0x6c65746e, %ecx
jne scrypt_core_gen
cmpl $0x49656e69, %edx
jne scrypt_core_gen
cmpl $0x756e6547, %ebx
je scrypt_core_xmm
.p2align 6
scrypt_core_gen:
subq $136, %rsp
movdqa 0(%rdi), %xmm8
movdqa 16(%rdi), %xmm9
movdqa 32(%rdi), %xmm10
movdqa 48(%rdi), %xmm11
movdqa 64(%rdi), %xmm12
movdqa 80(%rdi), %xmm13
movdqa 96(%rdi), %xmm14
movdqa 112(%rdi), %xmm15
movq %r8, %rcx
shlq $7, %rcx
addq %rsi, %rcx
movq %r8, 96(%rsp)
movq %rdi, 104(%rsp)
movq %rsi, 112(%rsp)
movq %rcx, 120(%rsp)
scrypt_core_gen_loop1:
movdqa %xmm8, 0(%rsi)
movdqa %xmm9, 16(%rsi)
movdqa %xmm10, 32(%rsi)
movdqa %xmm11, 48(%rsi)
movdqa %xmm12, 64(%rsi)
movdqa %xmm13, 80(%rsi)
movdqa %xmm14, 96(%rsi)
movdqa %xmm15, 112(%rsi)
pxor %xmm12, %xmm8
pxor %xmm13, %xmm9
pxor %xmm14, %xmm10
pxor %xmm15, %xmm11
movdqa %xmm8, 0(%rsp)
movdqa %xmm9, 16(%rsp)
movdqa %xmm10, 32(%rsp)
movdqa %xmm11, 48(%rsp)
movq %rsi, 128(%rsp)
call salsa8_core_gen
paddd %xmm0, %xmm8
paddd %xmm1, %xmm9
paddd %xmm2, %xmm10
paddd %xmm3, %xmm11
pxor %xmm8, %xmm12
pxor %xmm9, %xmm13
pxor %xmm10, %xmm14
pxor %xmm11, %xmm15
movdqa %xmm12, 0(%rsp)
movdqa %xmm13, 16(%rsp)
movdqa %xmm14, 32(%rsp)
movdqa %xmm15, 48(%rsp)
call salsa8_core_gen
movq 128(%rsp), %rsi
paddd %xmm0, %xmm12
paddd %xmm1, %xmm13
paddd %xmm2, %xmm14
paddd %xmm3, %xmm15
addq $128, %rsi
movq 120(%rsp), %rcx
cmpq %rcx, %rsi
jne scrypt_core_gen_loop1
movq 96(%rsp), %r8
movq %r8, %rcx
subl $1, %r8d
movq %r8, 96(%rsp)
movd %xmm12, %edx
scrypt_core_gen_loop2:
movq 112(%rsp), %rsi
andl %r8d, %edx
shll $7, %edx
addq %rsi, %rdx
movdqa 0(%rdx), %xmm0
movdqa 16(%rdx), %xmm1
movdqa 32(%rdx), %xmm2
movdqa 48(%rdx), %xmm3
movdqa 64(%rdx), %xmm4
movdqa 80(%rdx), %xmm5
movdqa 96(%rdx), %xmm6
movdqa 112(%rdx), %xmm7
pxor %xmm0, %xmm8
pxor %xmm1, %xmm9
pxor %xmm2, %xmm10
pxor %xmm3, %xmm11
pxor %xmm4, %xmm12
pxor %xmm5, %xmm13
pxor %xmm6, %xmm14
pxor %xmm7, %xmm15
pxor %xmm12, %xmm8
pxor %xmm13, %xmm9
pxor %xmm14, %xmm10
pxor %xmm15, %xmm11
movdqa %xmm8, 0(%rsp)
movdqa %xmm9, 16(%rsp)
movdqa %xmm10, 32(%rsp)
movdqa %xmm11, 48(%rsp)
movq %rcx, 128(%rsp)
call salsa8_core_gen
paddd %xmm0, %xmm8
paddd %xmm1, %xmm9
paddd %xmm2, %xmm10
paddd %xmm3, %xmm11
pxor %xmm8, %xmm12
pxor %xmm9, %xmm13
pxor %xmm10, %xmm14
pxor %xmm11, %xmm15
movdqa %xmm12, 0(%rsp)
movdqa %xmm13, 16(%rsp)
movdqa %xmm14, 32(%rsp)
movdqa %xmm15, 48(%rsp)
call salsa8_core_gen
movq 96(%rsp), %r8
movq 128(%rsp), %rcx
addl 0(%rsp), %edx
paddd %xmm0, %xmm12
paddd %xmm1, %xmm13
paddd %xmm2, %xmm14
paddd %xmm3, %xmm15
subq $1, %rcx
ja scrypt_core_gen_loop2
movq 104(%rsp), %rdi
movdqa %xmm8, 0(%rdi)
movdqa %xmm9, 16(%rdi)
movdqa %xmm10, 32(%rdi)
movdqa %xmm11, 48(%rdi)
movdqa %xmm12, 64(%rdi)
movdqa %xmm13, 80(%rdi)
movdqa %xmm14, 96(%rdi)
movdqa %xmm15, 112(%rdi)
addq $136, %rsp
scrypt_core_cleanup
ret
.macro salsa8_core_xmm_doubleround
movdqa %xmm1, %xmm4
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm3
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm3, %xmm3
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm1
pshufd $0x4e, %xmm2, %xmm2
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm0
pshufd $0x39, %xmm1, %xmm1
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm1
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm1, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm1, %xmm1
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm3
pshufd $0x4e, %xmm2, %xmm2
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
pshufd $0x39, %xmm3, %xmm3
pxor %xmm5, %xmm0
.endm
.macro salsa8_core_xmm
salsa8_core_xmm_doubleround
salsa8_core_xmm_doubleround
salsa8_core_xmm_doubleround
salsa8_core_xmm_doubleround
.endm
.p2align 6
scrypt_core_xmm:
pcmpeqw %xmm1, %xmm1
psrlq $32, %xmm1
movdqa 0(%rdi), %xmm8
movdqa 16(%rdi), %xmm11
movdqa 32(%rdi), %xmm10
movdqa 48(%rdi), %xmm9
movdqa %xmm8, %xmm0
pxor %xmm11, %xmm8
pand %xmm1, %xmm8
pxor %xmm11, %xmm8
pxor %xmm10, %xmm11
pand %xmm1, %xmm11
pxor %xmm10, %xmm11
pxor %xmm9, %xmm10
pand %xmm1, %xmm10
pxor %xmm9, %xmm10
pxor %xmm0, %xmm9
pand %xmm1, %xmm9
pxor %xmm0, %xmm9
movdqa %xmm8, %xmm0
pshufd $0x4e, %xmm10, %xmm10
punpcklqdq %xmm10, %xmm8
punpckhqdq %xmm0, %xmm10
movdqa %xmm11, %xmm0
pshufd $0x4e, %xmm9, %xmm9
punpcklqdq %xmm9, %xmm11
punpckhqdq %xmm0, %xmm9
movdqa 64(%rdi), %xmm12
movdqa 80(%rdi), %xmm15
movdqa 96(%rdi), %xmm14
movdqa 112(%rdi), %xmm13
movdqa %xmm12, %xmm0
pxor %xmm15, %xmm12
pand %xmm1, %xmm12
pxor %xmm15, %xmm12
pxor %xmm14, %xmm15
pand %xmm1, %xmm15
pxor %xmm14, %xmm15
pxor %xmm13, %xmm14
pand %xmm1, %xmm14
pxor %xmm13, %xmm14
pxor %xmm0, %xmm13
pand %xmm1, %xmm13
pxor %xmm0, %xmm13
movdqa %xmm12, %xmm0
pshufd $0x4e, %xmm14, %xmm14
punpcklqdq %xmm14, %xmm12
punpckhqdq %xmm0, %xmm14
movdqa %xmm15, %xmm0
pshufd $0x4e, %xmm13, %xmm13
punpcklqdq %xmm13, %xmm15
punpckhqdq %xmm0, %xmm13
movq %rsi, %rdx
movq %r8, %rcx
shlq $7, %rcx
addq %rsi, %rcx
scrypt_core_xmm_loop1:
pxor %xmm12, %xmm8
pxor %xmm13, %xmm9
pxor %xmm14, %xmm10
pxor %xmm15, %xmm11
movdqa %xmm8, 0(%rdx)
movdqa %xmm9, 16(%rdx)
movdqa %xmm10, 32(%rdx)
movdqa %xmm11, 48(%rdx)
movdqa %xmm12, 64(%rdx)
movdqa %xmm13, 80(%rdx)
movdqa %xmm14, 96(%rdx)
movdqa %xmm15, 112(%rdx)
movdqa %xmm8, %xmm0
movdqa %xmm9, %xmm1
movdqa %xmm10, %xmm2
movdqa %xmm11, %xmm3
salsa8_core_xmm
paddd %xmm0, %xmm8
paddd %xmm1, %xmm9
paddd %xmm2, %xmm10
paddd %xmm3, %xmm11
pxor %xmm8, %xmm12
pxor %xmm9, %xmm13
pxor %xmm10, %xmm14
pxor %xmm11, %xmm15
movdqa %xmm12, %xmm0
movdqa %xmm13, %xmm1
movdqa %xmm14, %xmm2
movdqa %xmm15, %xmm3
salsa8_core_xmm
paddd %xmm0, %xmm12
paddd %xmm1, %xmm13
paddd %xmm2, %xmm14
paddd %xmm3, %xmm15
addq $128, %rdx
cmpq %rcx, %rdx
jne scrypt_core_xmm_loop1
movq %r8, %rcx
subl $1, %r8d
scrypt_core_xmm_loop2:
movd %xmm12, %edx
andl %r8d, %edx
shll $7, %edx
pxor 0(%rsi, %rdx), %xmm8
pxor 16(%rsi, %rdx), %xmm9
pxor 32(%rsi, %rdx), %xmm10
pxor 48(%rsi, %rdx), %xmm11
pxor %xmm12, %xmm8
pxor %xmm13, %xmm9
pxor %xmm14, %xmm10
pxor %xmm15, %xmm11
movdqa %xmm8, %xmm0
movdqa %xmm9, %xmm1
movdqa %xmm10, %xmm2
movdqa %xmm11, %xmm3
salsa8_core_xmm
paddd %xmm0, %xmm8
paddd %xmm1, %xmm9
paddd %xmm2, %xmm10
paddd %xmm3, %xmm11
pxor 64(%rsi, %rdx), %xmm12
pxor 80(%rsi, %rdx), %xmm13
pxor 96(%rsi, %rdx), %xmm14
pxor 112(%rsi, %rdx), %xmm15
pxor %xmm8, %xmm12
pxor %xmm9, %xmm13
pxor %xmm10, %xmm14
pxor %xmm11, %xmm15
movdqa %xmm12, %xmm0
movdqa %xmm13, %xmm1
movdqa %xmm14, %xmm2
movdqa %xmm15, %xmm3
salsa8_core_xmm
paddd %xmm0, %xmm12
paddd %xmm1, %xmm13
paddd %xmm2, %xmm14
paddd %xmm3, %xmm15
subq $1, %rcx
ja scrypt_core_xmm_loop2
pcmpeqw %xmm1, %xmm1
psrlq $32, %xmm1
movdqa %xmm8, %xmm0
pxor %xmm9, %xmm8
pand %xmm1, %xmm8
pxor %xmm9, %xmm8
pxor %xmm10, %xmm9
pand %xmm1, %xmm9
pxor %xmm10, %xmm9
pxor %xmm11, %xmm10
pand %xmm1, %xmm10
pxor %xmm11, %xmm10
pxor %xmm0, %xmm11
pand %xmm1, %xmm11
pxor %xmm0, %xmm11
movdqa %xmm8, %xmm0
pshufd $0x4e, %xmm10, %xmm10
punpcklqdq %xmm10, %xmm8
punpckhqdq %xmm0, %xmm10
movdqa %xmm9, %xmm0
pshufd $0x4e, %xmm11, %xmm11
punpcklqdq %xmm11, %xmm9
punpckhqdq %xmm0, %xmm11
movdqa %xmm8, 0(%rdi)
movdqa %xmm11, 16(%rdi)
movdqa %xmm10, 32(%rdi)
movdqa %xmm9, 48(%rdi)
movdqa %xmm12, %xmm0
pxor %xmm13, %xmm12
pand %xmm1, %xmm12
pxor %xmm13, %xmm12
pxor %xmm14, %xmm13
pand %xmm1, %xmm13
pxor %xmm14, %xmm13
pxor %xmm15, %xmm14
pand %xmm1, %xmm14
pxor %xmm15, %xmm14
pxor %xmm0, %xmm15
pand %xmm1, %xmm15
pxor %xmm0, %xmm15
movdqa %xmm12, %xmm0
pshufd $0x4e, %xmm14, %xmm14
punpcklqdq %xmm14, %xmm12
punpckhqdq %xmm0, %xmm14
movdqa %xmm13, %xmm0
pshufd $0x4e, %xmm15, %xmm15
punpcklqdq %xmm15, %xmm13
punpckhqdq %xmm0, %xmm15
movdqa %xmm12, 64(%rdi)
movdqa %xmm15, 80(%rdi)
movdqa %xmm14, 96(%rdi)
movdqa %xmm13, 112(%rdi)
scrypt_core_cleanup
ret
#if defined(USE_AVX)
.macro salsa8_core_3way_avx_doubleround
vpaddd %xmm0, %xmm1, %xmm4
vpaddd %xmm8, %xmm9, %xmm6
vpaddd %xmm12, %xmm13, %xmm7
vpslld $7, %xmm4, %xmm5
vpsrld $25, %xmm4, %xmm4
vpxor %xmm5, %xmm3, %xmm3
vpxor %xmm4, %xmm3, %xmm3
vpslld $7, %xmm6, %xmm5
vpsrld $25, %xmm6, %xmm6
vpxor %xmm5, %xmm11, %xmm11
vpxor %xmm6, %xmm11, %xmm11
vpslld $7, %xmm7, %xmm5
vpsrld $25, %xmm7, %xmm7
vpxor %xmm5, %xmm15, %xmm15
vpxor %xmm7, %xmm15, %xmm15
vpaddd %xmm3, %xmm0, %xmm4
vpaddd %xmm11, %xmm8, %xmm6
vpaddd %xmm15, %xmm12, %xmm7
vpslld $9, %xmm4, %xmm5
vpsrld $23, %xmm4, %xmm4
vpxor %xmm5, %xmm2, %xmm2
vpxor %xmm4, %xmm2, %xmm2
vpslld $9, %xmm6, %xmm5
vpsrld $23, %xmm6, %xmm6
vpxor %xmm5, %xmm10, %xmm10
vpxor %xmm6, %xmm10, %xmm10
vpslld $9, %xmm7, %xmm5
vpsrld $23, %xmm7, %xmm7
vpxor %xmm5, %xmm14, %xmm14
vpxor %xmm7, %xmm14, %xmm14
vpaddd %xmm2, %xmm3, %xmm4
vpaddd %xmm10, %xmm11, %xmm6
vpaddd %xmm14, %xmm15, %xmm7
vpslld $13, %xmm4, %xmm5
vpsrld $19, %xmm4, %xmm4
vpshufd $0x93, %xmm3, %xmm3
vpshufd $0x93, %xmm11, %xmm11
vpshufd $0x93, %xmm15, %xmm15
vpxor %xmm5, %xmm1, %xmm1
vpxor %xmm4, %xmm1, %xmm1
vpslld $13, %xmm6, %xmm5
vpsrld $19, %xmm6, %xmm6
vpxor %xmm5, %xmm9, %xmm9
vpxor %xmm6, %xmm9, %xmm9
vpslld $13, %xmm7, %xmm5
vpsrld $19, %xmm7, %xmm7
vpxor %xmm5, %xmm13, %xmm13
vpxor %xmm7, %xmm13, %xmm13
vpaddd %xmm1, %xmm2, %xmm4
vpaddd %xmm9, %xmm10, %xmm6
vpaddd %xmm13, %xmm14, %xmm7
vpslld $18, %xmm4, %xmm5
vpsrld $14, %xmm4, %xmm4
vpshufd $0x4e, %xmm2, %xmm2
vpshufd $0x4e, %xmm10, %xmm10
vpshufd $0x4e, %xmm14, %xmm14
vpxor %xmm5, %xmm0, %xmm0
vpxor %xmm4, %xmm0, %xmm0
vpslld $18, %xmm6, %xmm5
vpsrld $14, %xmm6, %xmm6
vpxor %xmm5, %xmm8, %xmm8
vpxor %xmm6, %xmm8, %xmm8
vpslld $18, %xmm7, %xmm5
vpsrld $14, %xmm7, %xmm7
vpxor %xmm5, %xmm12, %xmm12
vpxor %xmm7, %xmm12, %xmm12
vpaddd %xmm0, %xmm3, %xmm4
vpaddd %xmm8, %xmm11, %xmm6
vpaddd %xmm12, %xmm15, %xmm7
vpslld $7, %xmm4, %xmm5
vpsrld $25, %xmm4, %xmm4
vpshufd $0x39, %xmm1, %xmm1
vpxor %xmm5, %xmm1, %xmm1
vpxor %xmm4, %xmm1, %xmm1
vpslld $7, %xmm6, %xmm5
vpsrld $25, %xmm6, %xmm6
vpshufd $0x39, %xmm9, %xmm9
vpxor %xmm5, %xmm9, %xmm9
vpxor %xmm6, %xmm9, %xmm9
vpslld $7, %xmm7, %xmm5
vpsrld $25, %xmm7, %xmm7
vpshufd $0x39, %xmm13, %xmm13
vpxor %xmm5, %xmm13, %xmm13
vpxor %xmm7, %xmm13, %xmm13
vpaddd %xmm1, %xmm0, %xmm4
vpaddd %xmm9, %xmm8, %xmm6
vpaddd %xmm13, %xmm12, %xmm7
vpslld $9, %xmm4, %xmm5
vpsrld $23, %xmm4, %xmm4
vpxor %xmm5, %xmm2, %xmm2
vpxor %xmm4, %xmm2, %xmm2
vpslld $9, %xmm6, %xmm5
vpsrld $23, %xmm6, %xmm6
vpxor %xmm5, %xmm10, %xmm10
vpxor %xmm6, %xmm10, %xmm10
vpslld $9, %xmm7, %xmm5
vpsrld $23, %xmm7, %xmm7
vpxor %xmm5, %xmm14, %xmm14
vpxor %xmm7, %xmm14, %xmm14
vpaddd %xmm2, %xmm1, %xmm4
vpaddd %xmm10, %xmm9, %xmm6
vpaddd %xmm14, %xmm13, %xmm7
vpslld $13, %xmm4, %xmm5
vpsrld $19, %xmm4, %xmm4
vpshufd $0x93, %xmm1, %xmm1
vpshufd $0x93, %xmm9, %xmm9
vpshufd $0x93, %xmm13, %xmm13
vpxor %xmm5, %xmm3, %xmm3
vpxor %xmm4, %xmm3, %xmm3
vpslld $13, %xmm6, %xmm5
vpsrld $19, %xmm6, %xmm6
vpxor %xmm5, %xmm11, %xmm11
vpxor %xmm6, %xmm11, %xmm11
vpslld $13, %xmm7, %xmm5
vpsrld $19, %xmm7, %xmm7
vpxor %xmm5, %xmm15, %xmm15
vpxor %xmm7, %xmm15, %xmm15
vpaddd %xmm3, %xmm2, %xmm4
vpaddd %xmm11, %xmm10, %xmm6
vpaddd %xmm15, %xmm14, %xmm7
vpslld $18, %xmm4, %xmm5
vpsrld $14, %xmm4, %xmm4
vpshufd $0x4e, %xmm2, %xmm2
vpshufd $0x4e, %xmm10, %xmm10
vpxor %xmm5, %xmm0, %xmm0
vpxor %xmm4, %xmm0, %xmm0
vpslld $18, %xmm6, %xmm5
vpsrld $14, %xmm6, %xmm6
vpshufd $0x4e, %xmm14, %xmm14
vpshufd $0x39, %xmm11, %xmm11
vpxor %xmm5, %xmm8, %xmm8
vpxor %xmm6, %xmm8, %xmm8
vpslld $18, %xmm7, %xmm5
vpsrld $14, %xmm7, %xmm7
vpshufd $0x39, %xmm3, %xmm3
vpshufd $0x39, %xmm15, %xmm15
vpxor %xmm5, %xmm12, %xmm12
vpxor %xmm7, %xmm12, %xmm12
.endm
.macro salsa8_core_3way_avx
salsa8_core_3way_avx_doubleround
salsa8_core_3way_avx_doubleround
salsa8_core_3way_avx_doubleround
salsa8_core_3way_avx_doubleround
.endm
#endif /* USE_AVX */
.text
.p2align 6
.globl scrypt_core_3way
.globl _scrypt_core_3way
scrypt_core_3way:
_scrypt_core_3way:
pushq %rbx
pushq %rbp
#if defined(_WIN64) || defined(__CYGWIN__)
subq $176, %rsp
movdqa %xmm6, 8(%rsp)
movdqa %xmm7, 24(%rsp)
movdqa %xmm8, 40(%rsp)
movdqa %xmm9, 56(%rsp)
movdqa %xmm10, 72(%rsp)
movdqa %xmm11, 88(%rsp)
movdqa %xmm12, 104(%rsp)
movdqa %xmm13, 120(%rsp)
movdqa %xmm14, 136(%rsp)
movdqa %xmm15, 152(%rsp)
pushq %rdi
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
#else
movq %rdx, %r8
#endif
subq $392, %rsp
.macro scrypt_core_3way_cleanup
addq $392, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
popq %rdi
movdqa 8(%rsp), %xmm6
movdqa 24(%rsp), %xmm7
movdqa 40(%rsp), %xmm8
movdqa 56(%rsp), %xmm9
movdqa 72(%rsp), %xmm10
movdqa 88(%rsp), %xmm11
movdqa 104(%rsp), %xmm12
movdqa 120(%rsp), %xmm13
movdqa 136(%rsp), %xmm14
movdqa 152(%rsp), %xmm15
addq $176, %rsp
#endif
popq %rbp
popq %rbx
.endm
#if !defined(USE_AVX)
jmp scrypt_core_3way_xmm
#else
/* Check for AVX and OSXSAVE support */
movl $1, %eax
cpuid
andl $0x18000000, %ecx
cmpl $0x18000000, %ecx
jne scrypt_core_3way_xmm
/* Check for XMM and YMM state support */
xorl %ecx, %ecx
xgetbv
andl $0x00000006, %eax
cmpl $0x00000006, %eax
jne scrypt_core_3way_xmm
#if defined(USE_XOP)
/* Check for XOP support */
movl $0x80000001, %eax
cpuid
andl $0x00000800, %ecx
jnz scrypt_core_3way_xop
#endif
scrypt_core_3way_avx:
scrypt_shuffle %rdi, 0, %rsp, 0
scrypt_shuffle %rdi, 64, %rsp, 64
scrypt_shuffle %rdi, 128, %rsp, 128
scrypt_shuffle %rdi, 192, %rsp, 192
scrypt_shuffle %rdi, 256, %rsp, 256
scrypt_shuffle %rdi, 320, %rsp, 320
movdqa 64(%rsp), %xmm0
movdqa 80(%rsp), %xmm1
movdqa 96(%rsp), %xmm2
movdqa 112(%rsp), %xmm3
movdqa 128+64(%rsp), %xmm8
movdqa 128+80(%rsp), %xmm9
movdqa 128+96(%rsp), %xmm10
movdqa 128+112(%rsp), %xmm11
movdqa 256+64(%rsp), %xmm12
movdqa 256+80(%rsp), %xmm13
movdqa 256+96(%rsp), %xmm14
movdqa 256+112(%rsp), %xmm15
movq %rsi, %rbx
leaq (%r8, %r8, 2), %rax
shlq $7, %rax
addq %rsi, %rax
scrypt_core_3way_avx_loop1:
movdqa %xmm0, 64(%rbx)
movdqa %xmm1, 80(%rbx)
movdqa %xmm2, 96(%rbx)
movdqa %xmm3, 112(%rbx)
pxor 0(%rsp), %xmm0
pxor 16(%rsp), %xmm1
pxor 32(%rsp), %xmm2
pxor 48(%rsp), %xmm3
movdqa %xmm8, 128+64(%rbx)
movdqa %xmm9, 128+80(%rbx)
movdqa %xmm10, 128+96(%rbx)
movdqa %xmm11, 128+112(%rbx)
pxor 128+0(%rsp), %xmm8
pxor 128+16(%rsp), %xmm9
pxor 128+32(%rsp), %xmm10
pxor 128+48(%rsp), %xmm11
movdqa %xmm12, 256+64(%rbx)
movdqa %xmm13, 256+80(%rbx)
movdqa %xmm14, 256+96(%rbx)
movdqa %xmm15, 256+112(%rbx)
pxor 256+0(%rsp), %xmm12
pxor 256+16(%rsp), %xmm13
pxor 256+32(%rsp), %xmm14
pxor 256+48(%rsp), %xmm15
movdqa %xmm0, 0(%rbx)
movdqa %xmm1, 16(%rbx)
movdqa %xmm2, 32(%rbx)
movdqa %xmm3, 48(%rbx)
movdqa %xmm8, 128+0(%rbx)
movdqa %xmm9, 128+16(%rbx)
movdqa %xmm10, 128+32(%rbx)
movdqa %xmm11, 128+48(%rbx)
movdqa %xmm12, 256+0(%rbx)
movdqa %xmm13, 256+16(%rbx)
movdqa %xmm14, 256+32(%rbx)
movdqa %xmm15, 256+48(%rbx)
salsa8_core_3way_avx
paddd 0(%rbx), %xmm0
paddd 16(%rbx), %xmm1
paddd 32(%rbx), %xmm2
paddd 48(%rbx), %xmm3
paddd 128+0(%rbx), %xmm8
paddd 128+16(%rbx), %xmm9
paddd 128+32(%rbx), %xmm10
paddd 128+48(%rbx), %xmm11
paddd 256+0(%rbx), %xmm12
paddd 256+16(%rbx), %xmm13
paddd 256+32(%rbx), %xmm14
paddd 256+48(%rbx), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
pxor 64(%rbx), %xmm0
pxor 80(%rbx), %xmm1
pxor 96(%rbx), %xmm2
pxor 112(%rbx), %xmm3
pxor 128+64(%rbx), %xmm8
pxor 128+80(%rbx), %xmm9
pxor 128+96(%rbx), %xmm10
pxor 128+112(%rbx), %xmm11
pxor 256+64(%rbx), %xmm12
pxor 256+80(%rbx), %xmm13
pxor 256+96(%rbx), %xmm14
pxor 256+112(%rbx), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
salsa8_core_3way_avx
paddd 64(%rsp), %xmm0
paddd 80(%rsp), %xmm1
paddd 96(%rsp), %xmm2
paddd 112(%rsp), %xmm3
paddd 128+64(%rsp), %xmm8
paddd 128+80(%rsp), %xmm9
paddd 128+96(%rsp), %xmm10
paddd 128+112(%rsp), %xmm11
paddd 256+64(%rsp), %xmm12
paddd 256+80(%rsp), %xmm13
paddd 256+96(%rsp), %xmm14
paddd 256+112(%rsp), %xmm15
addq $3*128, %rbx
cmpq %rax, %rbx
jne scrypt_core_3way_avx_loop1
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
movq %r8, %rcx
subq $1, %r8
scrypt_core_3way_avx_loop2:
movd %xmm0, %ebp
movd %xmm8, %ebx
movd %xmm12, %eax
pxor 0(%rsp), %xmm0
pxor 16(%rsp), %xmm1
pxor 32(%rsp), %xmm2
pxor 48(%rsp), %xmm3
pxor 128+0(%rsp), %xmm8
pxor 128+16(%rsp), %xmm9
pxor 128+32(%rsp), %xmm10
pxor 128+48(%rsp), %xmm11
pxor 256+0(%rsp), %xmm12
pxor 256+16(%rsp), %xmm13
pxor 256+32(%rsp), %xmm14
pxor 256+48(%rsp), %xmm15
andl %r8d, %ebp
leaq (%rbp, %rbp, 2), %rbp
shll $7, %ebp
andl %r8d, %ebx
leaq 1(%rbx, %rbx, 2), %rbx
shll $7, %ebx
andl %r8d, %eax
leaq 2(%rax, %rax, 2), %rax
shll $7, %eax
pxor 0(%rsi, %rbp), %xmm0
pxor 16(%rsi, %rbp), %xmm1
pxor 32(%rsi, %rbp), %xmm2
pxor 48(%rsi, %rbp), %xmm3
pxor 0(%rsi, %rbx), %xmm8
pxor 16(%rsi, %rbx), %xmm9
pxor 32(%rsi, %rbx), %xmm10
pxor 48(%rsi, %rbx), %xmm11
pxor 0(%rsi, %rax), %xmm12
pxor 16(%rsi, %rax), %xmm13
pxor 32(%rsi, %rax), %xmm14
pxor 48(%rsi, %rax), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
salsa8_core_3way_avx
paddd 0(%rsp), %xmm0
paddd 16(%rsp), %xmm1
paddd 32(%rsp), %xmm2
paddd 48(%rsp), %xmm3
paddd 128+0(%rsp), %xmm8
paddd 128+16(%rsp), %xmm9
paddd 128+32(%rsp), %xmm10
paddd 128+48(%rsp), %xmm11
paddd 256+0(%rsp), %xmm12
paddd 256+16(%rsp), %xmm13
paddd 256+32(%rsp), %xmm14
paddd 256+48(%rsp), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
pxor 64(%rsi, %rbp), %xmm0
pxor 80(%rsi, %rbp), %xmm1
pxor 96(%rsi, %rbp), %xmm2
pxor 112(%rsi, %rbp), %xmm3
pxor 64(%rsi, %rbx), %xmm8
pxor 80(%rsi, %rbx), %xmm9
pxor 96(%rsi, %rbx), %xmm10
pxor 112(%rsi, %rbx), %xmm11
pxor 64(%rsi, %rax), %xmm12
pxor 80(%rsi, %rax), %xmm13
pxor 96(%rsi, %rax), %xmm14
pxor 112(%rsi, %rax), %xmm15
pxor 64(%rsp), %xmm0
pxor 80(%rsp), %xmm1
pxor 96(%rsp), %xmm2
pxor 112(%rsp), %xmm3
pxor 128+64(%rsp), %xmm8
pxor 128+80(%rsp), %xmm9
pxor 128+96(%rsp), %xmm10
pxor 128+112(%rsp), %xmm11
pxor 256+64(%rsp), %xmm12
pxor 256+80(%rsp), %xmm13
pxor 256+96(%rsp), %xmm14
pxor 256+112(%rsp), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
salsa8_core_3way_avx
paddd 64(%rsp), %xmm0
paddd 80(%rsp), %xmm1
paddd 96(%rsp), %xmm2
paddd 112(%rsp), %xmm3
paddd 128+64(%rsp), %xmm8
paddd 128+80(%rsp), %xmm9
paddd 128+96(%rsp), %xmm10
paddd 128+112(%rsp), %xmm11
paddd 256+64(%rsp), %xmm12
paddd 256+80(%rsp), %xmm13
paddd 256+96(%rsp), %xmm14
paddd 256+112(%rsp), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
subq $1, %rcx
ja scrypt_core_3way_avx_loop2
scrypt_shuffle %rsp, 0, %rdi, 0
scrypt_shuffle %rsp, 64, %rdi, 64
scrypt_shuffle %rsp, 128, %rdi, 128
scrypt_shuffle %rsp, 192, %rdi, 192
scrypt_shuffle %rsp, 256, %rdi, 256
scrypt_shuffle %rsp, 320, %rdi, 320
scrypt_core_3way_cleanup
ret
#if defined(USE_XOP)
.macro salsa8_core_3way_xop_doubleround
vpaddd %xmm0, %xmm1, %xmm4
vpaddd %xmm8, %xmm9, %xmm6
vpaddd %xmm12, %xmm13, %xmm7
vprotd $7, %xmm4, %xmm4
vprotd $7, %xmm6, %xmm6
vprotd $7, %xmm7, %xmm7
vpxor %xmm4, %xmm3, %xmm3
vpxor %xmm6, %xmm11, %xmm11
vpxor %xmm7, %xmm15, %xmm15
vpaddd %xmm3, %xmm0, %xmm4
vpaddd %xmm11, %xmm8, %xmm6
vpaddd %xmm15, %xmm12, %xmm7
vprotd $9, %xmm4, %xmm4
vprotd $9, %xmm6, %xmm6
vprotd $9, %xmm7, %xmm7
vpxor %xmm4, %xmm2, %xmm2
vpxor %xmm6, %xmm10, %xmm10
vpxor %xmm7, %xmm14, %xmm14
vpaddd %xmm2, %xmm3, %xmm4
vpaddd %xmm10, %xmm11, %xmm6
vpaddd %xmm14, %xmm15, %xmm7
vprotd $13, %xmm4, %xmm4
vprotd $13, %xmm6, %xmm6
vprotd $13, %xmm7, %xmm7
vpshufd $0x93, %xmm3, %xmm3
vpshufd $0x93, %xmm11, %xmm11
vpshufd $0x93, %xmm15, %xmm15
vpxor %xmm4, %xmm1, %xmm1
vpxor %xmm6, %xmm9, %xmm9
vpxor %xmm7, %xmm13, %xmm13
vpaddd %xmm1, %xmm2, %xmm4
vpaddd %xmm9, %xmm10, %xmm6
vpaddd %xmm13, %xmm14, %xmm7
vprotd $18, %xmm4, %xmm4
vprotd $18, %xmm6, %xmm6
vprotd $18, %xmm7, %xmm7
vpshufd $0x4e, %xmm2, %xmm2
vpshufd $0x4e, %xmm10, %xmm10
vpshufd $0x4e, %xmm14, %xmm14
vpxor %xmm6, %xmm8, %xmm8
vpxor %xmm4, %xmm0, %xmm0
vpxor %xmm7, %xmm12, %xmm12
vpaddd %xmm0, %xmm3, %xmm4
vpaddd %xmm8, %xmm11, %xmm6
vpaddd %xmm12, %xmm15, %xmm7
vprotd $7, %xmm4, %xmm4
vprotd $7, %xmm6, %xmm6
vprotd $7, %xmm7, %xmm7
vpshufd $0x39, %xmm1, %xmm1
vpshufd $0x39, %xmm9, %xmm9
vpshufd $0x39, %xmm13, %xmm13
vpxor %xmm4, %xmm1, %xmm1
vpxor %xmm6, %xmm9, %xmm9
vpxor %xmm7, %xmm13, %xmm13
vpaddd %xmm1, %xmm0, %xmm4
vpaddd %xmm9, %xmm8, %xmm6
vpaddd %xmm13, %xmm12, %xmm7
vprotd $9, %xmm4, %xmm4
vprotd $9, %xmm6, %xmm6
vprotd $9, %xmm7, %xmm7
vpxor %xmm4, %xmm2, %xmm2
vpxor %xmm6, %xmm10, %xmm10
vpxor %xmm7, %xmm14, %xmm14
vpaddd %xmm2, %xmm1, %xmm4
vpaddd %xmm10, %xmm9, %xmm6
vpaddd %xmm14, %xmm13, %xmm7
vprotd $13, %xmm4, %xmm4
vprotd $13, %xmm6, %xmm6
vprotd $13, %xmm7, %xmm7
vpshufd $0x93, %xmm1, %xmm1
vpshufd $0x93, %xmm9, %xmm9
vpshufd $0x93, %xmm13, %xmm13
vpxor %xmm4, %xmm3, %xmm3
vpxor %xmm6, %xmm11, %xmm11
vpxor %xmm7, %xmm15, %xmm15
vpaddd %xmm3, %xmm2, %xmm4
vpaddd %xmm11, %xmm10, %xmm6
vpaddd %xmm15, %xmm14, %xmm7
vprotd $18, %xmm4, %xmm4
vprotd $18, %xmm6, %xmm6
vprotd $18, %xmm7, %xmm7
vpshufd $0x4e, %xmm2, %xmm2
vpshufd $0x4e, %xmm10, %xmm10
vpshufd $0x4e, %xmm14, %xmm14
vpxor %xmm4, %xmm0, %xmm0
vpxor %xmm6, %xmm8, %xmm8
vpxor %xmm7, %xmm12, %xmm12
vpshufd $0x39, %xmm3, %xmm3
vpshufd $0x39, %xmm11, %xmm11
vpshufd $0x39, %xmm15, %xmm15
.endm
.macro salsa8_core_3way_xop
salsa8_core_3way_xop_doubleround
salsa8_core_3way_xop_doubleround
salsa8_core_3way_xop_doubleround
salsa8_core_3way_xop_doubleround
.endm
.p2align 6
scrypt_core_3way_xop:
scrypt_shuffle %rdi, 0, %rsp, 0
scrypt_shuffle %rdi, 64, %rsp, 64
scrypt_shuffle %rdi, 128, %rsp, 128
scrypt_shuffle %rdi, 192, %rsp, 192
scrypt_shuffle %rdi, 256, %rsp, 256
scrypt_shuffle %rdi, 320, %rsp, 320
movdqa 64(%rsp), %xmm0
movdqa 80(%rsp), %xmm1
movdqa 96(%rsp), %xmm2
movdqa 112(%rsp), %xmm3
movdqa 128+64(%rsp), %xmm8
movdqa 128+80(%rsp), %xmm9
movdqa 128+96(%rsp), %xmm10
movdqa 128+112(%rsp), %xmm11
movdqa 256+64(%rsp), %xmm12
movdqa 256+80(%rsp), %xmm13
movdqa 256+96(%rsp), %xmm14
movdqa 256+112(%rsp), %xmm15
movq %rsi, %rbx
leaq (%r8, %r8, 2), %rax
shlq $7, %rax
addq %rsi, %rax
scrypt_core_3way_xop_loop1:
movdqa %xmm0, 64(%rbx)
movdqa %xmm1, 80(%rbx)
movdqa %xmm2, 96(%rbx)
movdqa %xmm3, 112(%rbx)
pxor 0(%rsp), %xmm0
pxor 16(%rsp), %xmm1
pxor 32(%rsp), %xmm2
pxor 48(%rsp), %xmm3
movdqa %xmm8, 128+64(%rbx)
movdqa %xmm9, 128+80(%rbx)
movdqa %xmm10, 128+96(%rbx)
movdqa %xmm11, 128+112(%rbx)
pxor 128+0(%rsp), %xmm8
pxor 128+16(%rsp), %xmm9
pxor 128+32(%rsp), %xmm10
pxor 128+48(%rsp), %xmm11
movdqa %xmm12, 256+64(%rbx)
movdqa %xmm13, 256+80(%rbx)
movdqa %xmm14, 256+96(%rbx)
movdqa %xmm15, 256+112(%rbx)
pxor 256+0(%rsp), %xmm12
pxor 256+16(%rsp), %xmm13
pxor 256+32(%rsp), %xmm14
pxor 256+48(%rsp), %xmm15
movdqa %xmm0, 0(%rbx)
movdqa %xmm1, 16(%rbx)
movdqa %xmm2, 32(%rbx)
movdqa %xmm3, 48(%rbx)
movdqa %xmm8, 128+0(%rbx)
movdqa %xmm9, 128+16(%rbx)
movdqa %xmm10, 128+32(%rbx)
movdqa %xmm11, 128+48(%rbx)
movdqa %xmm12, 256+0(%rbx)
movdqa %xmm13, 256+16(%rbx)
movdqa %xmm14, 256+32(%rbx)
movdqa %xmm15, 256+48(%rbx)
salsa8_core_3way_xop
paddd 0(%rbx), %xmm0
paddd 16(%rbx), %xmm1
paddd 32(%rbx), %xmm2
paddd 48(%rbx), %xmm3
paddd 128+0(%rbx), %xmm8
paddd 128+16(%rbx), %xmm9
paddd 128+32(%rbx), %xmm10
paddd 128+48(%rbx), %xmm11
paddd 256+0(%rbx), %xmm12
paddd 256+16(%rbx), %xmm13
paddd 256+32(%rbx), %xmm14
paddd 256+48(%rbx), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
pxor 64(%rbx), %xmm0
pxor 80(%rbx), %xmm1
pxor 96(%rbx), %xmm2
pxor 112(%rbx), %xmm3
pxor 128+64(%rbx), %xmm8
pxor 128+80(%rbx), %xmm9
pxor 128+96(%rbx), %xmm10
pxor 128+112(%rbx), %xmm11
pxor 256+64(%rbx), %xmm12
pxor 256+80(%rbx), %xmm13
pxor 256+96(%rbx), %xmm14
pxor 256+112(%rbx), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
salsa8_core_3way_xop
paddd 64(%rsp), %xmm0
paddd 80(%rsp), %xmm1
paddd 96(%rsp), %xmm2
paddd 112(%rsp), %xmm3
paddd 128+64(%rsp), %xmm8
paddd 128+80(%rsp), %xmm9
paddd 128+96(%rsp), %xmm10
paddd 128+112(%rsp), %xmm11
paddd 256+64(%rsp), %xmm12
paddd 256+80(%rsp), %xmm13
paddd 256+96(%rsp), %xmm14
paddd 256+112(%rsp), %xmm15
addq $3*128, %rbx
cmpq %rax, %rbx
jne scrypt_core_3way_xop_loop1
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
movq %r8, %rcx
subq $1, %r8
scrypt_core_3way_xop_loop2:
movd %xmm0, %ebp
movd %xmm8, %ebx
movd %xmm12, %eax
pxor 0(%rsp), %xmm0
pxor 16(%rsp), %xmm1
pxor 32(%rsp), %xmm2
pxor 48(%rsp), %xmm3
pxor 128+0(%rsp), %xmm8
pxor 128+16(%rsp), %xmm9
pxor 128+32(%rsp), %xmm10
pxor 128+48(%rsp), %xmm11
pxor 256+0(%rsp), %xmm12
pxor 256+16(%rsp), %xmm13
pxor 256+32(%rsp), %xmm14
pxor 256+48(%rsp), %xmm15
andl %r8d, %ebp
leaq (%rbp, %rbp, 2), %rbp
shll $7, %ebp
andl %r8d, %ebx
leaq 1(%rbx, %rbx, 2), %rbx
shll $7, %ebx
andl %r8d, %eax
leaq 2(%rax, %rax, 2), %rax
shll $7, %eax
pxor 0(%rsi, %rbp), %xmm0
pxor 16(%rsi, %rbp), %xmm1
pxor 32(%rsi, %rbp), %xmm2
pxor 48(%rsi, %rbp), %xmm3
pxor 0(%rsi, %rbx), %xmm8
pxor 16(%rsi, %rbx), %xmm9
pxor 32(%rsi, %rbx), %xmm10
pxor 48(%rsi, %rbx), %xmm11
pxor 0(%rsi, %rax), %xmm12
pxor 16(%rsi, %rax), %xmm13
pxor 32(%rsi, %rax), %xmm14
pxor 48(%rsi, %rax), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
salsa8_core_3way_xop
paddd 0(%rsp), %xmm0
paddd 16(%rsp), %xmm1
paddd 32(%rsp), %xmm2
paddd 48(%rsp), %xmm3
paddd 128+0(%rsp), %xmm8
paddd 128+16(%rsp), %xmm9
paddd 128+32(%rsp), %xmm10
paddd 128+48(%rsp), %xmm11
paddd 256+0(%rsp), %xmm12
paddd 256+16(%rsp), %xmm13
paddd 256+32(%rsp), %xmm14
paddd 256+48(%rsp), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
pxor 64(%rsi, %rbp), %xmm0
pxor 80(%rsi, %rbp), %xmm1
pxor 96(%rsi, %rbp), %xmm2
pxor 112(%rsi, %rbp), %xmm3
pxor 64(%rsi, %rbx), %xmm8
pxor 80(%rsi, %rbx), %xmm9
pxor 96(%rsi, %rbx), %xmm10
pxor 112(%rsi, %rbx), %xmm11
pxor 64(%rsi, %rax), %xmm12
pxor 80(%rsi, %rax), %xmm13
pxor 96(%rsi, %rax), %xmm14
pxor 112(%rsi, %rax), %xmm15
pxor 64(%rsp), %xmm0
pxor 80(%rsp), %xmm1
pxor 96(%rsp), %xmm2
pxor 112(%rsp), %xmm3
pxor 128+64(%rsp), %xmm8
pxor 128+80(%rsp), %xmm9
pxor 128+96(%rsp), %xmm10
pxor 128+112(%rsp), %xmm11
pxor 256+64(%rsp), %xmm12
pxor 256+80(%rsp), %xmm13
pxor 256+96(%rsp), %xmm14
pxor 256+112(%rsp), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
salsa8_core_3way_xop
paddd 64(%rsp), %xmm0
paddd 80(%rsp), %xmm1
paddd 96(%rsp), %xmm2
paddd 112(%rsp), %xmm3
paddd 128+64(%rsp), %xmm8
paddd 128+80(%rsp), %xmm9
paddd 128+96(%rsp), %xmm10
paddd 128+112(%rsp), %xmm11
paddd 256+64(%rsp), %xmm12
paddd 256+80(%rsp), %xmm13
paddd 256+96(%rsp), %xmm14
paddd 256+112(%rsp), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
subq $1, %rcx
ja scrypt_core_3way_xop_loop2
scrypt_shuffle %rsp, 0, %rdi, 0
scrypt_shuffle %rsp, 64, %rdi, 64
scrypt_shuffle %rsp, 128, %rdi, 128
scrypt_shuffle %rsp, 192, %rdi, 192
scrypt_shuffle %rsp, 256, %rdi, 256
scrypt_shuffle %rsp, 320, %rdi, 320
scrypt_core_3way_cleanup
ret
#endif /* USE_XOP */
#endif /* USE_AVX */
.macro salsa8_core_3way_xmm_doubleround
movdqa %xmm1, %xmm4
movdqa %xmm9, %xmm6
movdqa %xmm13, %xmm7
paddd %xmm0, %xmm4
paddd %xmm8, %xmm6
paddd %xmm12, %xmm7
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm3
pxor %xmm5, %xmm3
movdqa %xmm0, %xmm4
movdqa %xmm6, %xmm5
pslld $7, %xmm6
psrld $25, %xmm5
pxor %xmm6, %xmm11
pxor %xmm5, %xmm11
movdqa %xmm8, %xmm6
movdqa %xmm7, %xmm5
pslld $7, %xmm7
psrld $25, %xmm5
pxor %xmm7, %xmm15
pxor %xmm5, %xmm15
movdqa %xmm12, %xmm7
paddd %xmm3, %xmm4
paddd %xmm11, %xmm6
paddd %xmm15, %xmm7
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm3, %xmm4
pshufd $0x93, %xmm3, %xmm3
pxor %xmm5, %xmm2
movdqa %xmm6, %xmm5
pslld $9, %xmm6
psrld $23, %xmm5
pxor %xmm6, %xmm10
movdqa %xmm11, %xmm6
pshufd $0x93, %xmm11, %xmm11
pxor %xmm5, %xmm10
movdqa %xmm7, %xmm5
pslld $9, %xmm7
psrld $23, %xmm5
pxor %xmm7, %xmm14
movdqa %xmm15, %xmm7
pxor %xmm5, %xmm14
pshufd $0x93, %xmm15, %xmm15
paddd %xmm2, %xmm4
paddd %xmm10, %xmm6
paddd %xmm14, %xmm7
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm2, %xmm4
pshufd $0x4e, %xmm2, %xmm2
pxor %xmm5, %xmm1
movdqa %xmm6, %xmm5
pslld $13, %xmm6
psrld $19, %xmm5
pxor %xmm6, %xmm9
movdqa %xmm10, %xmm6
pshufd $0x4e, %xmm10, %xmm10
pxor %xmm5, %xmm9
movdqa %xmm7, %xmm5
pslld $13, %xmm7
psrld $19, %xmm5
pxor %xmm7, %xmm13
movdqa %xmm14, %xmm7
pshufd $0x4e, %xmm14, %xmm14
pxor %xmm5, %xmm13
paddd %xmm1, %xmm4
paddd %xmm9, %xmm6
paddd %xmm13, %xmm7
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
pshufd $0x39, %xmm1, %xmm1
pxor %xmm5, %xmm0
movdqa %xmm3, %xmm4
movdqa %xmm6, %xmm5
pslld $18, %xmm6
psrld $14, %xmm5
pxor %xmm6, %xmm8
pshufd $0x39, %xmm9, %xmm9
pxor %xmm5, %xmm8
movdqa %xmm11, %xmm6
movdqa %xmm7, %xmm5
pslld $18, %xmm7
psrld $14, %xmm5
pxor %xmm7, %xmm12
movdqa %xmm15, %xmm7
pxor %xmm5, %xmm12
pshufd $0x39, %xmm13, %xmm13
paddd %xmm0, %xmm4
paddd %xmm8, %xmm6
paddd %xmm12, %xmm7
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm1
pxor %xmm5, %xmm1
movdqa %xmm0, %xmm4
movdqa %xmm6, %xmm5
pslld $7, %xmm6
psrld $25, %xmm5
pxor %xmm6, %xmm9
pxor %xmm5, %xmm9
movdqa %xmm8, %xmm6
movdqa %xmm7, %xmm5
pslld $7, %xmm7
psrld $25, %xmm5
pxor %xmm7, %xmm13
pxor %xmm5, %xmm13
movdqa %xmm12, %xmm7
paddd %xmm1, %xmm4
paddd %xmm9, %xmm6
paddd %xmm13, %xmm7
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm1, %xmm4
pshufd $0x93, %xmm1, %xmm1
pxor %xmm5, %xmm2
movdqa %xmm6, %xmm5
pslld $9, %xmm6
psrld $23, %xmm5
pxor %xmm6, %xmm10
movdqa %xmm9, %xmm6
pshufd $0x93, %xmm9, %xmm9
pxor %xmm5, %xmm10
movdqa %xmm7, %xmm5
pslld $9, %xmm7
psrld $23, %xmm5
pxor %xmm7, %xmm14
movdqa %xmm13, %xmm7
pshufd $0x93, %xmm13, %xmm13
pxor %xmm5, %xmm14
paddd %xmm2, %xmm4
paddd %xmm10, %xmm6
paddd %xmm14, %xmm7
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm2, %xmm4
pshufd $0x4e, %xmm2, %xmm2
pxor %xmm5, %xmm3
movdqa %xmm6, %xmm5
pslld $13, %xmm6
psrld $19, %xmm5
pxor %xmm6, %xmm11
movdqa %xmm10, %xmm6
pshufd $0x4e, %xmm10, %xmm10
pxor %xmm5, %xmm11
movdqa %xmm7, %xmm5
pslld $13, %xmm7
psrld $19, %xmm5
pxor %xmm7, %xmm15
movdqa %xmm14, %xmm7
pshufd $0x4e, %xmm14, %xmm14
pxor %xmm5, %xmm15
paddd %xmm3, %xmm4
paddd %xmm11, %xmm6
paddd %xmm15, %xmm7
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
pshufd $0x39, %xmm3, %xmm3
pxor %xmm5, %xmm0
movdqa %xmm6, %xmm5
pslld $18, %xmm6
psrld $14, %xmm5
pxor %xmm6, %xmm8
pshufd $0x39, %xmm11, %xmm11
pxor %xmm5, %xmm8
movdqa %xmm7, %xmm5
pslld $18, %xmm7
psrld $14, %xmm5
pxor %xmm7, %xmm12
pshufd $0x39, %xmm15, %xmm15
pxor %xmm5, %xmm12
.endm
.macro salsa8_core_3way_xmm
salsa8_core_3way_xmm_doubleround
salsa8_core_3way_xmm_doubleround
salsa8_core_3way_xmm_doubleround
salsa8_core_3way_xmm_doubleround
.endm
.p2align 6
scrypt_core_3way_xmm:
scrypt_shuffle %rdi, 0, %rsp, 0
scrypt_shuffle %rdi, 64, %rsp, 64
scrypt_shuffle %rdi, 128, %rsp, 128
scrypt_shuffle %rdi, 192, %rsp, 192
scrypt_shuffle %rdi, 256, %rsp, 256
scrypt_shuffle %rdi, 320, %rsp, 320
movdqa 64(%rsp), %xmm0
movdqa 80(%rsp), %xmm1
movdqa 96(%rsp), %xmm2
movdqa 112(%rsp), %xmm3
movdqa 128+64(%rsp), %xmm8
movdqa 128+80(%rsp), %xmm9
movdqa 128+96(%rsp), %xmm10
movdqa 128+112(%rsp), %xmm11
movdqa 256+64(%rsp), %xmm12
movdqa 256+80(%rsp), %xmm13
movdqa 256+96(%rsp), %xmm14
movdqa 256+112(%rsp), %xmm15
movq %rsi, %rbx
leaq (%r8, %r8, 2), %rax
shlq $7, %rax
addq %rsi, %rax
scrypt_core_3way_xmm_loop1:
movdqa %xmm0, 64(%rbx)
movdqa %xmm1, 80(%rbx)
movdqa %xmm2, 96(%rbx)
movdqa %xmm3, 112(%rbx)
pxor 0(%rsp), %xmm0
pxor 16(%rsp), %xmm1
pxor 32(%rsp), %xmm2
pxor 48(%rsp), %xmm3
movdqa %xmm8, 128+64(%rbx)
movdqa %xmm9, 128+80(%rbx)
movdqa %xmm10, 128+96(%rbx)
movdqa %xmm11, 128+112(%rbx)
pxor 128+0(%rsp), %xmm8
pxor 128+16(%rsp), %xmm9
pxor 128+32(%rsp), %xmm10
pxor 128+48(%rsp), %xmm11
movdqa %xmm12, 256+64(%rbx)
movdqa %xmm13, 256+80(%rbx)
movdqa %xmm14, 256+96(%rbx)
movdqa %xmm15, 256+112(%rbx)
pxor 256+0(%rsp), %xmm12
pxor 256+16(%rsp), %xmm13
pxor 256+32(%rsp), %xmm14
pxor 256+48(%rsp), %xmm15
movdqa %xmm0, 0(%rbx)
movdqa %xmm1, 16(%rbx)
movdqa %xmm2, 32(%rbx)
movdqa %xmm3, 48(%rbx)
movdqa %xmm8, 128+0(%rbx)
movdqa %xmm9, 128+16(%rbx)
movdqa %xmm10, 128+32(%rbx)
movdqa %xmm11, 128+48(%rbx)
movdqa %xmm12, 256+0(%rbx)
movdqa %xmm13, 256+16(%rbx)
movdqa %xmm14, 256+32(%rbx)
movdqa %xmm15, 256+48(%rbx)
salsa8_core_3way_xmm
paddd 0(%rbx), %xmm0
paddd 16(%rbx), %xmm1
paddd 32(%rbx), %xmm2
paddd 48(%rbx), %xmm3
paddd 128+0(%rbx), %xmm8
paddd 128+16(%rbx), %xmm9
paddd 128+32(%rbx), %xmm10
paddd 128+48(%rbx), %xmm11
paddd 256+0(%rbx), %xmm12
paddd 256+16(%rbx), %xmm13
paddd 256+32(%rbx), %xmm14
paddd 256+48(%rbx), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
pxor 64(%rbx), %xmm0
pxor 80(%rbx), %xmm1
pxor 96(%rbx), %xmm2
pxor 112(%rbx), %xmm3
pxor 128+64(%rbx), %xmm8
pxor 128+80(%rbx), %xmm9
pxor 128+96(%rbx), %xmm10
pxor 128+112(%rbx), %xmm11
pxor 256+64(%rbx), %xmm12
pxor 256+80(%rbx), %xmm13
pxor 256+96(%rbx), %xmm14
pxor 256+112(%rbx), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
salsa8_core_3way_xmm
paddd 64(%rsp), %xmm0
paddd 80(%rsp), %xmm1
paddd 96(%rsp), %xmm2
paddd 112(%rsp), %xmm3
paddd 128+64(%rsp), %xmm8
paddd 128+80(%rsp), %xmm9
paddd 128+96(%rsp), %xmm10
paddd 128+112(%rsp), %xmm11
paddd 256+64(%rsp), %xmm12
paddd 256+80(%rsp), %xmm13
paddd 256+96(%rsp), %xmm14
paddd 256+112(%rsp), %xmm15
addq $3*128, %rbx
cmpq %rax, %rbx
jne scrypt_core_3way_xmm_loop1
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
movq %r8, %rcx
subq $1, %r8
scrypt_core_3way_xmm_loop2:
movd %xmm0, %ebp
movd %xmm8, %ebx
movd %xmm12, %eax
pxor 0(%rsp), %xmm0
pxor 16(%rsp), %xmm1
pxor 32(%rsp), %xmm2
pxor 48(%rsp), %xmm3
pxor 128+0(%rsp), %xmm8
pxor 128+16(%rsp), %xmm9
pxor 128+32(%rsp), %xmm10
pxor 128+48(%rsp), %xmm11
pxor 256+0(%rsp), %xmm12
pxor 256+16(%rsp), %xmm13
pxor 256+32(%rsp), %xmm14
pxor 256+48(%rsp), %xmm15
andl %r8d, %ebp
leaq (%rbp, %rbp, 2), %rbp
shll $7, %ebp
andl %r8d, %ebx
leaq 1(%rbx, %rbx, 2), %rbx
shll $7, %ebx
andl %r8d, %eax
leaq 2(%rax, %rax, 2), %rax
shll $7, %eax
pxor 0(%rsi, %rbp), %xmm0
pxor 16(%rsi, %rbp), %xmm1
pxor 32(%rsi, %rbp), %xmm2
pxor 48(%rsi, %rbp), %xmm3
pxor 0(%rsi, %rbx), %xmm8
pxor 16(%rsi, %rbx), %xmm9
pxor 32(%rsi, %rbx), %xmm10
pxor 48(%rsi, %rbx), %xmm11
pxor 0(%rsi, %rax), %xmm12
pxor 16(%rsi, %rax), %xmm13
pxor 32(%rsi, %rax), %xmm14
pxor 48(%rsi, %rax), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
salsa8_core_3way_xmm
paddd 0(%rsp), %xmm0
paddd 16(%rsp), %xmm1
paddd 32(%rsp), %xmm2
paddd 48(%rsp), %xmm3
paddd 128+0(%rsp), %xmm8
paddd 128+16(%rsp), %xmm9
paddd 128+32(%rsp), %xmm10
paddd 128+48(%rsp), %xmm11
paddd 256+0(%rsp), %xmm12
paddd 256+16(%rsp), %xmm13
paddd 256+32(%rsp), %xmm14
paddd 256+48(%rsp), %xmm15
movdqa %xmm0, 0(%rsp)
movdqa %xmm1, 16(%rsp)
movdqa %xmm2, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm8, 128+0(%rsp)
movdqa %xmm9, 128+16(%rsp)
movdqa %xmm10, 128+32(%rsp)
movdqa %xmm11, 128+48(%rsp)
movdqa %xmm12, 256+0(%rsp)
movdqa %xmm13, 256+16(%rsp)
movdqa %xmm14, 256+32(%rsp)
movdqa %xmm15, 256+48(%rsp)
pxor 64(%rsi, %rbp), %xmm0
pxor 80(%rsi, %rbp), %xmm1
pxor 96(%rsi, %rbp), %xmm2
pxor 112(%rsi, %rbp), %xmm3
pxor 64(%rsi, %rbx), %xmm8
pxor 80(%rsi, %rbx), %xmm9
pxor 96(%rsi, %rbx), %xmm10
pxor 112(%rsi, %rbx), %xmm11
pxor 64(%rsi, %rax), %xmm12
pxor 80(%rsi, %rax), %xmm13
pxor 96(%rsi, %rax), %xmm14
pxor 112(%rsi, %rax), %xmm15
pxor 64(%rsp), %xmm0
pxor 80(%rsp), %xmm1
pxor 96(%rsp), %xmm2
pxor 112(%rsp), %xmm3
pxor 128+64(%rsp), %xmm8
pxor 128+80(%rsp), %xmm9
pxor 128+96(%rsp), %xmm10
pxor 128+112(%rsp), %xmm11
pxor 256+64(%rsp), %xmm12
pxor 256+80(%rsp), %xmm13
pxor 256+96(%rsp), %xmm14
pxor 256+112(%rsp), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
salsa8_core_3way_xmm
paddd 64(%rsp), %xmm0
paddd 80(%rsp), %xmm1
paddd 96(%rsp), %xmm2
paddd 112(%rsp), %xmm3
paddd 128+64(%rsp), %xmm8
paddd 128+80(%rsp), %xmm9
paddd 128+96(%rsp), %xmm10
paddd 128+112(%rsp), %xmm11
paddd 256+64(%rsp), %xmm12
paddd 256+80(%rsp), %xmm13
paddd 256+96(%rsp), %xmm14
paddd 256+112(%rsp), %xmm15
movdqa %xmm0, 64(%rsp)
movdqa %xmm1, 80(%rsp)
movdqa %xmm2, 96(%rsp)
movdqa %xmm3, 112(%rsp)
movdqa %xmm8, 128+64(%rsp)
movdqa %xmm9, 128+80(%rsp)
movdqa %xmm10, 128+96(%rsp)
movdqa %xmm11, 128+112(%rsp)
movdqa %xmm12, 256+64(%rsp)
movdqa %xmm13, 256+80(%rsp)
movdqa %xmm14, 256+96(%rsp)
movdqa %xmm15, 256+112(%rsp)
subq $1, %rcx
ja scrypt_core_3way_xmm_loop2
scrypt_shuffle %rsp, 0, %rdi, 0
scrypt_shuffle %rsp, 64, %rdi, 64
scrypt_shuffle %rsp, 128, %rdi, 128
scrypt_shuffle %rsp, 192, %rdi, 192
scrypt_shuffle %rsp, 256, %rdi, 256
scrypt_shuffle %rsp, 320, %rdi, 320
scrypt_core_3way_cleanup
ret
#if defined(USE_AVX2)
.macro salsa8_core_6way_avx2_doubleround
vpaddd %ymm0, %ymm1, %ymm4
vpaddd %ymm8, %ymm9, %ymm6
vpaddd %ymm12, %ymm13, %ymm7
vpslld $7, %ymm4, %ymm5
vpsrld $25, %ymm4, %ymm4
vpxor %ymm5, %ymm3, %ymm3
vpxor %ymm4, %ymm3, %ymm3
vpslld $7, %ymm6, %ymm5
vpsrld $25, %ymm6, %ymm6
vpxor %ymm5, %ymm11, %ymm11
vpxor %ymm6, %ymm11, %ymm11
vpslld $7, %ymm7, %ymm5
vpsrld $25, %ymm7, %ymm7
vpxor %ymm5, %ymm15, %ymm15
vpxor %ymm7, %ymm15, %ymm15
vpaddd %ymm3, %ymm0, %ymm4
vpaddd %ymm11, %ymm8, %ymm6
vpaddd %ymm15, %ymm12, %ymm7
vpslld $9, %ymm4, %ymm5
vpsrld $23, %ymm4, %ymm4
vpxor %ymm5, %ymm2, %ymm2
vpxor %ymm4, %ymm2, %ymm2
vpslld $9, %ymm6, %ymm5
vpsrld $23, %ymm6, %ymm6
vpxor %ymm5, %ymm10, %ymm10
vpxor %ymm6, %ymm10, %ymm10
vpslld $9, %ymm7, %ymm5
vpsrld $23, %ymm7, %ymm7
vpxor %ymm5, %ymm14, %ymm14
vpxor %ymm7, %ymm14, %ymm14
vpaddd %ymm2, %ymm3, %ymm4
vpaddd %ymm10, %ymm11, %ymm6
vpaddd %ymm14, %ymm15, %ymm7
vpslld $13, %ymm4, %ymm5
vpsrld $19, %ymm4, %ymm4
vpshufd $0x93, %ymm3, %ymm3
vpshufd $0x93, %ymm11, %ymm11
vpshufd $0x93, %ymm15, %ymm15
vpxor %ymm5, %ymm1, %ymm1
vpxor %ymm4, %ymm1, %ymm1
vpslld $13, %ymm6, %ymm5
vpsrld $19, %ymm6, %ymm6
vpxor %ymm5, %ymm9, %ymm9
vpxor %ymm6, %ymm9, %ymm9
vpslld $13, %ymm7, %ymm5
vpsrld $19, %ymm7, %ymm7
vpxor %ymm5, %ymm13, %ymm13
vpxor %ymm7, %ymm13, %ymm13
vpaddd %ymm1, %ymm2, %ymm4
vpaddd %ymm9, %ymm10, %ymm6
vpaddd %ymm13, %ymm14, %ymm7
vpslld $18, %ymm4, %ymm5
vpsrld $14, %ymm4, %ymm4
vpshufd $0x4e, %ymm2, %ymm2
vpshufd $0x4e, %ymm10, %ymm10
vpshufd $0x4e, %ymm14, %ymm14
vpxor %ymm5, %ymm0, %ymm0
vpxor %ymm4, %ymm0, %ymm0
vpslld $18, %ymm6, %ymm5
vpsrld $14, %ymm6, %ymm6
vpxor %ymm5, %ymm8, %ymm8
vpxor %ymm6, %ymm8, %ymm8
vpslld $18, %ymm7, %ymm5
vpsrld $14, %ymm7, %ymm7
vpxor %ymm5, %ymm12, %ymm12
vpxor %ymm7, %ymm12, %ymm12
vpaddd %ymm0, %ymm3, %ymm4
vpaddd %ymm8, %ymm11, %ymm6
vpaddd %ymm12, %ymm15, %ymm7
vpslld $7, %ymm4, %ymm5
vpsrld $25, %ymm4, %ymm4
vpshufd $0x39, %ymm1, %ymm1
vpxor %ymm5, %ymm1, %ymm1
vpxor %ymm4, %ymm1, %ymm1
vpslld $7, %ymm6, %ymm5
vpsrld $25, %ymm6, %ymm6
vpshufd $0x39, %ymm9, %ymm9
vpxor %ymm5, %ymm9, %ymm9
vpxor %ymm6, %ymm9, %ymm9
vpslld $7, %ymm7, %ymm5
vpsrld $25, %ymm7, %ymm7
vpshufd $0x39, %ymm13, %ymm13
vpxor %ymm5, %ymm13, %ymm13
vpxor %ymm7, %ymm13, %ymm13
vpaddd %ymm1, %ymm0, %ymm4
vpaddd %ymm9, %ymm8, %ymm6
vpaddd %ymm13, %ymm12, %ymm7
vpslld $9, %ymm4, %ymm5
vpsrld $23, %ymm4, %ymm4
vpxor %ymm5, %ymm2, %ymm2
vpxor %ymm4, %ymm2, %ymm2
vpslld $9, %ymm6, %ymm5
vpsrld $23, %ymm6, %ymm6
vpxor %ymm5, %ymm10, %ymm10
vpxor %ymm6, %ymm10, %ymm10
vpslld $9, %ymm7, %ymm5
vpsrld $23, %ymm7, %ymm7
vpxor %ymm5, %ymm14, %ymm14
vpxor %ymm7, %ymm14, %ymm14
vpaddd %ymm2, %ymm1, %ymm4
vpaddd %ymm10, %ymm9, %ymm6
vpaddd %ymm14, %ymm13, %ymm7
vpslld $13, %ymm4, %ymm5
vpsrld $19, %ymm4, %ymm4
vpshufd $0x93, %ymm1, %ymm1
vpshufd $0x93, %ymm9, %ymm9
vpshufd $0x93, %ymm13, %ymm13
vpxor %ymm5, %ymm3, %ymm3
vpxor %ymm4, %ymm3, %ymm3
vpslld $13, %ymm6, %ymm5
vpsrld $19, %ymm6, %ymm6
vpxor %ymm5, %ymm11, %ymm11
vpxor %ymm6, %ymm11, %ymm11
vpslld $13, %ymm7, %ymm5
vpsrld $19, %ymm7, %ymm7
vpxor %ymm5, %ymm15, %ymm15
vpxor %ymm7, %ymm15, %ymm15
vpaddd %ymm3, %ymm2, %ymm4
vpaddd %ymm11, %ymm10, %ymm6
vpaddd %ymm15, %ymm14, %ymm7
vpslld $18, %ymm4, %ymm5
vpsrld $14, %ymm4, %ymm4
vpshufd $0x4e, %ymm2, %ymm2
vpshufd $0x4e, %ymm10, %ymm10
vpxor %ymm5, %ymm0, %ymm0
vpxor %ymm4, %ymm0, %ymm0
vpslld $18, %ymm6, %ymm5
vpsrld $14, %ymm6, %ymm6
vpshufd $0x4e, %ymm14, %ymm14
vpshufd $0x39, %ymm11, %ymm11
vpxor %ymm5, %ymm8, %ymm8
vpxor %ymm6, %ymm8, %ymm8
vpslld $18, %ymm7, %ymm5
vpsrld $14, %ymm7, %ymm7
vpshufd $0x39, %ymm3, %ymm3
vpshufd $0x39, %ymm15, %ymm15
vpxor %ymm5, %ymm12, %ymm12
vpxor %ymm7, %ymm12, %ymm12
.endm
.macro salsa8_core_6way_avx2
salsa8_core_6way_avx2_doubleround
salsa8_core_6way_avx2_doubleround
salsa8_core_6way_avx2_doubleround
salsa8_core_6way_avx2_doubleround
.endm
.text
.p2align 6
.globl scrypt_core_6way
.globl _scrypt_core_6way
scrypt_core_6way:
_scrypt_core_6way:
pushq %rbx
pushq %rbp
#if defined(_WIN64) || defined(__CYGWIN__)
subq $176, %rsp
vmovdqa %xmm6, 8(%rsp)
vmovdqa %xmm7, 24(%rsp)
vmovdqa %xmm8, 40(%rsp)
vmovdqa %xmm9, 56(%rsp)
vmovdqa %xmm10, 72(%rsp)
vmovdqa %xmm11, 88(%rsp)
vmovdqa %xmm12, 104(%rsp)
vmovdqa %xmm13, 120(%rsp)
vmovdqa %xmm14, 136(%rsp)
vmovdqa %xmm15, 152(%rsp)
pushq %rdi
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
#else
movq %rdx, %r8
#endif
movq %rsp, %rdx
subq $768, %rsp
andq $-128, %rsp
.macro scrypt_core_6way_cleanup
movq %rdx, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
popq %rdi
vmovdqa 8(%rsp), %xmm6
vmovdqa 24(%rsp), %xmm7
vmovdqa 40(%rsp), %xmm8
vmovdqa 56(%rsp), %xmm9
vmovdqa 72(%rsp), %xmm10
vmovdqa 88(%rsp), %xmm11
vmovdqa 104(%rsp), %xmm12
vmovdqa 120(%rsp), %xmm13
vmovdqa 136(%rsp), %xmm14
vmovdqa 152(%rsp), %xmm15
addq $176, %rsp
#endif
popq %rbp
popq %rbx
.endm
.macro scrypt_shuffle_pack2 src, so, dest, do
vmovdqa \so+0*16(\src), %xmm0
vmovdqa \so+1*16(\src), %xmm1
vmovdqa \so+2*16(\src), %xmm2
vmovdqa \so+3*16(\src), %xmm3
vinserti128 $1, \so+128+0*16(\src), %ymm0, %ymm0
vinserti128 $1, \so+128+1*16(\src), %ymm1, %ymm1
vinserti128 $1, \so+128+2*16(\src), %ymm2, %ymm2
vinserti128 $1, \so+128+3*16(\src), %ymm3, %ymm3
vpblendd $0x33, %ymm0, %ymm2, %ymm4
vpblendd $0xcc, %ymm1, %ymm3, %ymm5
vpblendd $0x33, %ymm2, %ymm0, %ymm6
vpblendd $0xcc, %ymm3, %ymm1, %ymm7
vpblendd $0x55, %ymm7, %ymm6, %ymm3
vpblendd $0x55, %ymm6, %ymm5, %ymm2
vpblendd $0x55, %ymm5, %ymm4, %ymm1
vpblendd $0x55, %ymm4, %ymm7, %ymm0
vmovdqa %ymm0, \do+0*32(\dest)
vmovdqa %ymm1, \do+1*32(\dest)
vmovdqa %ymm2, \do+2*32(\dest)
vmovdqa %ymm3, \do+3*32(\dest)
.endm
.macro scrypt_shuffle_unpack2 src, so, dest, do
vmovdqa \so+0*32(\src), %ymm0
vmovdqa \so+1*32(\src), %ymm1
vmovdqa \so+2*32(\src), %ymm2
vmovdqa \so+3*32(\src), %ymm3
vpblendd $0x33, %ymm0, %ymm2, %ymm4
vpblendd $0xcc, %ymm1, %ymm3, %ymm5
vpblendd $0x33, %ymm2, %ymm0, %ymm6
vpblendd $0xcc, %ymm3, %ymm1, %ymm7
vpblendd $0x55, %ymm7, %ymm6, %ymm3
vpblendd $0x55, %ymm6, %ymm5, %ymm2
vpblendd $0x55, %ymm5, %ymm4, %ymm1
vpblendd $0x55, %ymm4, %ymm7, %ymm0
vmovdqa %xmm0, \do+0*16(\dest)
vmovdqa %xmm1, \do+1*16(\dest)
vmovdqa %xmm2, \do+2*16(\dest)
vmovdqa %xmm3, \do+3*16(\dest)
vextracti128 $1, %ymm0, \do+128+0*16(\dest)
vextracti128 $1, %ymm1, \do+128+1*16(\dest)
vextracti128 $1, %ymm2, \do+128+2*16(\dest)
vextracti128 $1, %ymm3, \do+128+3*16(\dest)
.endm
scrypt_core_6way_avx2:
scrypt_shuffle_pack2 %rdi, 0*256+0, %rsp, 0*128
scrypt_shuffle_pack2 %rdi, 0*256+64, %rsp, 1*128
scrypt_shuffle_pack2 %rdi, 1*256+0, %rsp, 2*128
scrypt_shuffle_pack2 %rdi, 1*256+64, %rsp, 3*128
scrypt_shuffle_pack2 %rdi, 2*256+0, %rsp, 4*128
scrypt_shuffle_pack2 %rdi, 2*256+64, %rsp, 5*128
vmovdqa 0*256+4*32(%rsp), %ymm0
vmovdqa 0*256+5*32(%rsp), %ymm1
vmovdqa 0*256+6*32(%rsp), %ymm2
vmovdqa 0*256+7*32(%rsp), %ymm3
vmovdqa 1*256+4*32(%rsp), %ymm8
vmovdqa 1*256+5*32(%rsp), %ymm9
vmovdqa 1*256+6*32(%rsp), %ymm10
vmovdqa 1*256+7*32(%rsp), %ymm11
vmovdqa 2*256+4*32(%rsp), %ymm12
vmovdqa 2*256+5*32(%rsp), %ymm13
vmovdqa 2*256+6*32(%rsp), %ymm14
vmovdqa 2*256+7*32(%rsp), %ymm15
movq %rsi, %rbx
leaq (%r8, %r8, 2), %rax
shlq $8, %rax
addq %rsi, %rax
scrypt_core_6way_avx2_loop1:
vmovdqa %ymm0, 0*256+4*32(%rbx)
vmovdqa %ymm1, 0*256+5*32(%rbx)
vmovdqa %ymm2, 0*256+6*32(%rbx)
vmovdqa %ymm3, 0*256+7*32(%rbx)
vpxor 0*256+0*32(%rsp), %ymm0, %ymm0
vpxor 0*256+1*32(%rsp), %ymm1, %ymm1
vpxor 0*256+2*32(%rsp), %ymm2, %ymm2
vpxor 0*256+3*32(%rsp), %ymm3, %ymm3
vmovdqa %ymm8, 1*256+4*32(%rbx)
vmovdqa %ymm9, 1*256+5*32(%rbx)
vmovdqa %ymm10, 1*256+6*32(%rbx)
vmovdqa %ymm11, 1*256+7*32(%rbx)
vpxor 1*256+0*32(%rsp), %ymm8, %ymm8
vpxor 1*256+1*32(%rsp), %ymm9, %ymm9
vpxor 1*256+2*32(%rsp), %ymm10, %ymm10
vpxor 1*256+3*32(%rsp), %ymm11, %ymm11
vmovdqa %ymm12, 2*256+4*32(%rbx)
vmovdqa %ymm13, 2*256+5*32(%rbx)
vmovdqa %ymm14, 2*256+6*32(%rbx)
vmovdqa %ymm15, 2*256+7*32(%rbx)
vpxor 2*256+0*32(%rsp), %ymm12, %ymm12
vpxor 2*256+1*32(%rsp), %ymm13, %ymm13
vpxor 2*256+2*32(%rsp), %ymm14, %ymm14
vpxor 2*256+3*32(%rsp), %ymm15, %ymm15
vmovdqa %ymm0, 0*256+0*32(%rbx)
vmovdqa %ymm1, 0*256+1*32(%rbx)
vmovdqa %ymm2, 0*256+2*32(%rbx)
vmovdqa %ymm3, 0*256+3*32(%rbx)
vmovdqa %ymm8, 1*256+0*32(%rbx)
vmovdqa %ymm9, 1*256+1*32(%rbx)
vmovdqa %ymm10, 1*256+2*32(%rbx)
vmovdqa %ymm11, 1*256+3*32(%rbx)
vmovdqa %ymm12, 2*256+0*32(%rbx)
vmovdqa %ymm13, 2*256+1*32(%rbx)
vmovdqa %ymm14, 2*256+2*32(%rbx)
vmovdqa %ymm15, 2*256+3*32(%rbx)
salsa8_core_6way_avx2
vpaddd 0*256+0*32(%rbx), %ymm0, %ymm0
vpaddd 0*256+1*32(%rbx), %ymm1, %ymm1
vpaddd 0*256+2*32(%rbx), %ymm2, %ymm2
vpaddd 0*256+3*32(%rbx), %ymm3, %ymm3
vpaddd 1*256+0*32(%rbx), %ymm8, %ymm8
vpaddd 1*256+1*32(%rbx), %ymm9, %ymm9
vpaddd 1*256+2*32(%rbx), %ymm10, %ymm10
vpaddd 1*256+3*32(%rbx), %ymm11, %ymm11
vpaddd 2*256+0*32(%rbx), %ymm12, %ymm12
vpaddd 2*256+1*32(%rbx), %ymm13, %ymm13
vpaddd 2*256+2*32(%rbx), %ymm14, %ymm14
vpaddd 2*256+3*32(%rbx), %ymm15, %ymm15
vmovdqa %ymm0, 0*256+0*32(%rsp)
vmovdqa %ymm1, 0*256+1*32(%rsp)
vmovdqa %ymm2, 0*256+2*32(%rsp)
vmovdqa %ymm3, 0*256+3*32(%rsp)
vmovdqa %ymm8, 1*256+0*32(%rsp)
vmovdqa %ymm9, 1*256+1*32(%rsp)
vmovdqa %ymm10, 1*256+2*32(%rsp)
vmovdqa %ymm11, 1*256+3*32(%rsp)
vmovdqa %ymm12, 2*256+0*32(%rsp)
vmovdqa %ymm13, 2*256+1*32(%rsp)
vmovdqa %ymm14, 2*256+2*32(%rsp)
vmovdqa %ymm15, 2*256+3*32(%rsp)
vpxor 0*256+4*32(%rbx), %ymm0, %ymm0
vpxor 0*256+5*32(%rbx), %ymm1, %ymm1
vpxor 0*256+6*32(%rbx), %ymm2, %ymm2
vpxor 0*256+7*32(%rbx), %ymm3, %ymm3
vpxor 1*256+4*32(%rbx), %ymm8, %ymm8
vpxor 1*256+5*32(%rbx), %ymm9, %ymm9
vpxor 1*256+6*32(%rbx), %ymm10, %ymm10
vpxor 1*256+7*32(%rbx), %ymm11, %ymm11
vpxor 2*256+4*32(%rbx), %ymm12, %ymm12
vpxor 2*256+5*32(%rbx), %ymm13, %ymm13
vpxor 2*256+6*32(%rbx), %ymm14, %ymm14
vpxor 2*256+7*32(%rbx), %ymm15, %ymm15
vmovdqa %ymm0, 0*256+4*32(%rsp)
vmovdqa %ymm1, 0*256+5*32(%rsp)
vmovdqa %ymm2, 0*256+6*32(%rsp)
vmovdqa %ymm3, 0*256+7*32(%rsp)
vmovdqa %ymm8, 1*256+4*32(%rsp)
vmovdqa %ymm9, 1*256+5*32(%rsp)
vmovdqa %ymm10, 1*256+6*32(%rsp)
vmovdqa %ymm11, 1*256+7*32(%rsp)
vmovdqa %ymm12, 2*256+4*32(%rsp)
vmovdqa %ymm13, 2*256+5*32(%rsp)
vmovdqa %ymm14, 2*256+6*32(%rsp)
vmovdqa %ymm15, 2*256+7*32(%rsp)
salsa8_core_6way_avx2
vpaddd 0*256+4*32(%rsp), %ymm0, %ymm0
vpaddd 0*256+5*32(%rsp), %ymm1, %ymm1
vpaddd 0*256+6*32(%rsp), %ymm2, %ymm2
vpaddd 0*256+7*32(%rsp), %ymm3, %ymm3
vpaddd 1*256+4*32(%rsp), %ymm8, %ymm8
vpaddd 1*256+5*32(%rsp), %ymm9, %ymm9
vpaddd 1*256+6*32(%rsp), %ymm10, %ymm10
vpaddd 1*256+7*32(%rsp), %ymm11, %ymm11
vpaddd 2*256+4*32(%rsp), %ymm12, %ymm12
vpaddd 2*256+5*32(%rsp), %ymm13, %ymm13
vpaddd 2*256+6*32(%rsp), %ymm14, %ymm14
vpaddd 2*256+7*32(%rsp), %ymm15, %ymm15
addq $6*128, %rbx
cmpq %rax, %rbx
jne scrypt_core_6way_avx2_loop1
vmovdqa %ymm0, 0*256+4*32(%rsp)
vmovdqa %ymm1, 0*256+5*32(%rsp)
vmovdqa %ymm2, 0*256+6*32(%rsp)
vmovdqa %ymm3, 0*256+7*32(%rsp)
vmovdqa %ymm8, 1*256+4*32(%rsp)
vmovdqa %ymm9, 1*256+5*32(%rsp)
vmovdqa %ymm10, 1*256+6*32(%rsp)
vmovdqa %ymm11, 1*256+7*32(%rsp)
vmovdqa %ymm12, 2*256+4*32(%rsp)
vmovdqa %ymm13, 2*256+5*32(%rsp)
vmovdqa %ymm14, 2*256+6*32(%rsp)
vmovdqa %ymm15, 2*256+7*32(%rsp)
movq %r8, %rcx
leaq -1(%r8), %r11
scrypt_core_6way_avx2_loop2:
vmovd %xmm0, %ebp
vmovd %xmm8, %ebx
vmovd %xmm12, %eax
vextracti128 $1, %ymm0, %xmm4
vextracti128 $1, %ymm8, %xmm5
vextracti128 $1, %ymm12, %xmm6
vmovd %xmm4, %r8d
vmovd %xmm5, %r9d
vmovd %xmm6, %r10d
vpxor 0*256+0*32(%rsp), %ymm0, %ymm0
vpxor 0*256+1*32(%rsp), %ymm1, %ymm1
vpxor 0*256+2*32(%rsp), %ymm2, %ymm2
vpxor 0*256+3*32(%rsp), %ymm3, %ymm3
vpxor 1*256+0*32(%rsp), %ymm8, %ymm8
vpxor 1*256+1*32(%rsp), %ymm9, %ymm9
vpxor 1*256+2*32(%rsp), %ymm10, %ymm10
vpxor 1*256+3*32(%rsp), %ymm11, %ymm11
vpxor 2*256+0*32(%rsp), %ymm12, %ymm12
vpxor 2*256+1*32(%rsp), %ymm13, %ymm13
vpxor 2*256+2*32(%rsp), %ymm14, %ymm14
vpxor 2*256+3*32(%rsp), %ymm15, %ymm15
andl %r11d, %ebp
leaq 0(%rbp, %rbp, 2), %rbp
shll $8, %ebp
andl %r11d, %ebx
leaq 1(%rbx, %rbx, 2), %rbx
shll $8, %ebx
andl %r11d, %eax
leaq 2(%rax, %rax, 2), %rax
shll $8, %eax
andl %r11d, %r8d
leaq 0(%r8, %r8, 2), %r8
shll $8, %r8d
andl %r11d, %r9d
leaq 1(%r9, %r9, 2), %r9
shll $8, %r9d
andl %r11d, %r10d
leaq 2(%r10, %r10, 2), %r10
shll $8, %r10d
vmovdqa 0*32(%rsi, %rbp), %xmm4
vinserti128 $1, 0*32+16(%rsi, %r8), %ymm4, %ymm4
vmovdqa 1*32(%rsi, %rbp), %xmm5
vinserti128 $1, 1*32+16(%rsi, %r8), %ymm5, %ymm5
vmovdqa 2*32(%rsi, %rbp), %xmm6
vinserti128 $1, 2*32+16(%rsi, %r8), %ymm6, %ymm6
vmovdqa 3*32(%rsi, %rbp), %xmm7
vinserti128 $1, 3*32+16(%rsi, %r8), %ymm7, %ymm7
vpxor %ymm4, %ymm0, %ymm0
vpxor %ymm5, %ymm1, %ymm1
vpxor %ymm6, %ymm2, %ymm2
vpxor %ymm7, %ymm3, %ymm3
vmovdqa 0*32(%rsi, %rbx), %xmm4
vinserti128 $1, 0*32+16(%rsi, %r9), %ymm4, %ymm4
vmovdqa 1*32(%rsi, %rbx), %xmm5
vinserti128 $1, 1*32+16(%rsi, %r9), %ymm5, %ymm5
vmovdqa 2*32(%rsi, %rbx), %xmm6
vinserti128 $1, 2*32+16(%rsi, %r9), %ymm6, %ymm6
vmovdqa 3*32(%rsi, %rbx), %xmm7
vinserti128 $1, 3*32+16(%rsi, %r9), %ymm7, %ymm7
vpxor %ymm4, %ymm8, %ymm8
vpxor %ymm5, %ymm9, %ymm9
vpxor %ymm6, %ymm10, %ymm10
vpxor %ymm7, %ymm11, %ymm11
vmovdqa 0*32(%rsi, %rax), %xmm4
vinserti128 $1, 0*32+16(%rsi, %r10), %ymm4, %ymm4
vmovdqa 1*32(%rsi, %rax), %xmm5
vinserti128 $1, 1*32+16(%rsi, %r10), %ymm5, %ymm5
vmovdqa 2*32(%rsi, %rax), %xmm6
vinserti128 $1, 2*32+16(%rsi, %r10), %ymm6, %ymm6
vmovdqa 3*32(%rsi, %rax), %xmm7
vinserti128 $1, 3*32+16(%rsi, %r10), %ymm7, %ymm7
vpxor %ymm4, %ymm12, %ymm12
vpxor %ymm5, %ymm13, %ymm13
vpxor %ymm6, %ymm14, %ymm14
vpxor %ymm7, %ymm15, %ymm15
vmovdqa %ymm0, 0*256+0*32(%rsp)
vmovdqa %ymm1, 0*256+1*32(%rsp)
vmovdqa %ymm2, 0*256+2*32(%rsp)
vmovdqa %ymm3, 0*256+3*32(%rsp)
vmovdqa %ymm8, 1*256+0*32(%rsp)
vmovdqa %ymm9, 1*256+1*32(%rsp)
vmovdqa %ymm10, 1*256+2*32(%rsp)
vmovdqa %ymm11, 1*256+3*32(%rsp)
vmovdqa %ymm12, 2*256+0*32(%rsp)
vmovdqa %ymm13, 2*256+1*32(%rsp)
vmovdqa %ymm14, 2*256+2*32(%rsp)
vmovdqa %ymm15, 2*256+3*32(%rsp)
salsa8_core_6way_avx2
vpaddd 0*256+0*32(%rsp), %ymm0, %ymm0
vpaddd 0*256+1*32(%rsp), %ymm1, %ymm1
vpaddd 0*256+2*32(%rsp), %ymm2, %ymm2
vpaddd 0*256+3*32(%rsp), %ymm3, %ymm3
vpaddd 1*256+0*32(%rsp), %ymm8, %ymm8
vpaddd 1*256+1*32(%rsp), %ymm9, %ymm9
vpaddd 1*256+2*32(%rsp), %ymm10, %ymm10
vpaddd 1*256+3*32(%rsp), %ymm11, %ymm11
vpaddd 2*256+0*32(%rsp), %ymm12, %ymm12
vpaddd 2*256+1*32(%rsp), %ymm13, %ymm13
vpaddd 2*256+2*32(%rsp), %ymm14, %ymm14
vpaddd 2*256+3*32(%rsp), %ymm15, %ymm15
vmovdqa %ymm0, 0*256+0*32(%rsp)
vmovdqa %ymm1, 0*256+1*32(%rsp)
vmovdqa %ymm2, 0*256+2*32(%rsp)
vmovdqa %ymm3, 0*256+3*32(%rsp)
vmovdqa %ymm8, 1*256+0*32(%rsp)
vmovdqa %ymm9, 1*256+1*32(%rsp)
vmovdqa %ymm10, 1*256+2*32(%rsp)
vmovdqa %ymm11, 1*256+3*32(%rsp)
vmovdqa %ymm12, 2*256+0*32(%rsp)
vmovdqa %ymm13, 2*256+1*32(%rsp)
vmovdqa %ymm14, 2*256+2*32(%rsp)
vmovdqa %ymm15, 2*256+3*32(%rsp)
vmovdqa 4*32(%rsi, %rbp), %xmm4
vinserti128 $1, 4*32+16(%rsi, %r8), %ymm4, %ymm4
vmovdqa 5*32(%rsi, %rbp), %xmm5
vinserti128 $1, 5*32+16(%rsi, %r8), %ymm5, %ymm5
vmovdqa 6*32(%rsi, %rbp), %xmm6
vinserti128 $1, 6*32+16(%rsi, %r8), %ymm6, %ymm6
vmovdqa 7*32(%rsi, %rbp), %xmm7
vinserti128 $1, 7*32+16(%rsi, %r8), %ymm7, %ymm7
vpxor %ymm4, %ymm0, %ymm0
vpxor %ymm5, %ymm1, %ymm1
vpxor %ymm6, %ymm2, %ymm2
vpxor %ymm7, %ymm3, %ymm3
vmovdqa 4*32(%rsi, %rbx), %xmm4
vinserti128 $1, 4*32+16(%rsi, %r9), %ymm4, %ymm4
vmovdqa 5*32(%rsi, %rbx), %xmm5
vinserti128 $1, 5*32+16(%rsi, %r9), %ymm5, %ymm5
vmovdqa 6*32(%rsi, %rbx), %xmm6
vinserti128 $1, 6*32+16(%rsi, %r9), %ymm6, %ymm6
vmovdqa 7*32(%rsi, %rbx), %xmm7
vinserti128 $1, 7*32+16(%rsi, %r9), %ymm7, %ymm7
vpxor %ymm4, %ymm8, %ymm8
vpxor %ymm5, %ymm9, %ymm9
vpxor %ymm6, %ymm10, %ymm10
vpxor %ymm7, %ymm11, %ymm11
vmovdqa 4*32(%rsi, %rax), %xmm4
vinserti128 $1, 4*32+16(%rsi, %r10), %ymm4, %ymm4
vmovdqa 5*32(%rsi, %rax), %xmm5
vinserti128 $1, 5*32+16(%rsi, %r10), %ymm5, %ymm5
vmovdqa 6*32(%rsi, %rax), %xmm6
vinserti128 $1, 6*32+16(%rsi, %r10), %ymm6, %ymm6
vmovdqa 7*32(%rsi, %rax), %xmm7
vinserti128 $1, 7*32+16(%rsi, %r10), %ymm7, %ymm7
vpxor %ymm4, %ymm12, %ymm12
vpxor %ymm5, %ymm13, %ymm13
vpxor %ymm6, %ymm14, %ymm14
vpxor %ymm7, %ymm15, %ymm15
vpxor 0*256+4*32(%rsp), %ymm0, %ymm0
vpxor 0*256+5*32(%rsp), %ymm1, %ymm1
vpxor 0*256+6*32(%rsp), %ymm2, %ymm2
vpxor 0*256+7*32(%rsp), %ymm3, %ymm3
vpxor 1*256+4*32(%rsp), %ymm8, %ymm8
vpxor 1*256+5*32(%rsp), %ymm9, %ymm9
vpxor 1*256+6*32(%rsp), %ymm10, %ymm10
vpxor 1*256+7*32(%rsp), %ymm11, %ymm11
vpxor 2*256+4*32(%rsp), %ymm12, %ymm12
vpxor 2*256+5*32(%rsp), %ymm13, %ymm13
vpxor 2*256+6*32(%rsp), %ymm14, %ymm14
vpxor 2*256+7*32(%rsp), %ymm15, %ymm15
vmovdqa %ymm0, 0*256+4*32(%rsp)
vmovdqa %ymm1, 0*256+5*32(%rsp)
vmovdqa %ymm2, 0*256+6*32(%rsp)
vmovdqa %ymm3, 0*256+7*32(%rsp)
vmovdqa %ymm8, 1*256+4*32(%rsp)
vmovdqa %ymm9, 1*256+5*32(%rsp)
vmovdqa %ymm10, 1*256+6*32(%rsp)
vmovdqa %ymm11, 1*256+7*32(%rsp)
vmovdqa %ymm12, 2*256+4*32(%rsp)
vmovdqa %ymm13, 2*256+5*32(%rsp)
vmovdqa %ymm14, 2*256+6*32(%rsp)
vmovdqa %ymm15, 2*256+7*32(%rsp)
salsa8_core_6way_avx2
vpaddd 0*256+4*32(%rsp), %ymm0, %ymm0
vpaddd 0*256+5*32(%rsp), %ymm1, %ymm1
vpaddd 0*256+6*32(%rsp), %ymm2, %ymm2
vpaddd 0*256+7*32(%rsp), %ymm3, %ymm3
vpaddd 1*256+4*32(%rsp), %ymm8, %ymm8
vpaddd 1*256+5*32(%rsp), %ymm9, %ymm9
vpaddd 1*256+6*32(%rsp), %ymm10, %ymm10
vpaddd 1*256+7*32(%rsp), %ymm11, %ymm11
vpaddd 2*256+4*32(%rsp), %ymm12, %ymm12
vpaddd 2*256+5*32(%rsp), %ymm13, %ymm13
vpaddd 2*256+6*32(%rsp), %ymm14, %ymm14
vpaddd 2*256+7*32(%rsp), %ymm15, %ymm15
vmovdqa %ymm0, 0*256+4*32(%rsp)
vmovdqa %ymm1, 0*256+5*32(%rsp)
vmovdqa %ymm2, 0*256+6*32(%rsp)
vmovdqa %ymm3, 0*256+7*32(%rsp)
vmovdqa %ymm8, 1*256+4*32(%rsp)
vmovdqa %ymm9, 1*256+5*32(%rsp)
vmovdqa %ymm10, 1*256+6*32(%rsp)
vmovdqa %ymm11, 1*256+7*32(%rsp)
vmovdqa %ymm12, 2*256+4*32(%rsp)
vmovdqa %ymm13, 2*256+5*32(%rsp)
vmovdqa %ymm14, 2*256+6*32(%rsp)
vmovdqa %ymm15, 2*256+7*32(%rsp)
subq $1, %rcx
ja scrypt_core_6way_avx2_loop2
scrypt_shuffle_unpack2 %rsp, 0*128, %rdi, 0*256+0
scrypt_shuffle_unpack2 %rsp, 1*128, %rdi, 0*256+64
scrypt_shuffle_unpack2 %rsp, 2*128, %rdi, 1*256+0
scrypt_shuffle_unpack2 %rsp, 3*128, %rdi, 1*256+64
scrypt_shuffle_unpack2 %rsp, 4*128, %rdi, 2*256+0
scrypt_shuffle_unpack2 %rsp, 5*128, %rdi, 2*256+64
scrypt_core_6way_cleanup
ret
#endif /* USE_AVX2 */
#endif
|
WyvernTKC/cpuminer-gr-avx2 | 23,107 | asm/scrypt-arm.S | /*
* Copyright 2012, 2014 pooler@litecoinpool.org
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version. See COPYING for more details.
*/
#include <cpuminer-config.h>
#if defined(USE_ASM) && defined(__arm__) && defined(__APCS_32__)
#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_6__) || \
defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || \
defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6T2__) || \
defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__)
#define __ARM_ARCH_5E_OR_6__
#endif
#if defined(__ARM_ARCH_5E_OR_6__) || defined(__ARM_ARCH_7__) || \
defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || \
defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define __ARM_ARCH_5E_OR_6_OR_7__
#endif
#ifdef __ARM_ARCH_5E_OR_6__
.macro scrypt_shuffle
add lr, r0, #9*4
ldmia r0, {r2-r7}
ldmia lr, {r2, r8-r12, lr}
str r3, [r0, #5*4]
str r5, [r0, #15*4]
str r6, [r0, #12*4]
str r7, [r0, #1*4]
ldr r5, [r0, #7*4]
str r2, [r0, #13*4]
str r8, [r0, #2*4]
strd r4, [r0, #10*4]
str r9, [r0, #7*4]
str r10, [r0, #4*4]
str r11, [r0, #9*4]
str lr, [r0, #3*4]
add r2, r0, #64+0*4
add lr, r0, #64+9*4
ldmia r2, {r2-r7}
ldmia lr, {r2, r8-r12, lr}
str r3, [r0, #64+5*4]
str r5, [r0, #64+15*4]
str r6, [r0, #64+12*4]
str r7, [r0, #64+1*4]
ldr r5, [r0, #64+7*4]
str r2, [r0, #64+13*4]
str r8, [r0, #64+2*4]
strd r4, [r0, #64+10*4]
str r9, [r0, #64+7*4]
str r10, [r0, #64+4*4]
str r11, [r0, #64+9*4]
str lr, [r0, #64+3*4]
.endm
.macro salsa8_core_doubleround_body
add r6, r2, r6
add r7, r3, r7
eor r10, r10, r6, ror #25
add r6, r0, r4
eor r11, r11, r7, ror #25
add r7, r1, r5
strd r10, [sp, #14*4]
eor r12, r12, r6, ror #25
eor lr, lr, r7, ror #25
ldrd r6, [sp, #10*4]
add r2, r10, r2
add r3, r11, r3
eor r6, r6, r2, ror #23
add r2, r12, r0
eor r7, r7, r3, ror #23
add r3, lr, r1
strd r6, [sp, #10*4]
eor r8, r8, r2, ror #23
eor r9, r9, r3, ror #23
ldrd r2, [sp, #6*4]
add r10, r6, r10
add r11, r7, r11
eor r2, r2, r10, ror #19
add r10, r8, r12
eor r3, r3, r11, ror #19
add r11, r9, lr
eor r4, r4, r10, ror #19
eor r5, r5, r11, ror #19
ldrd r10, [sp, #2*4]
add r6, r2, r6
add r7, r3, r7
eor r10, r10, r6, ror #14
add r6, r4, r8
eor r11, r11, r7, ror #14
add r7, r5, r9
eor r0, r0, r6, ror #14
eor r1, r1, r7, ror #14
ldrd r6, [sp, #14*4]
strd r2, [sp, #6*4]
strd r10, [sp, #2*4]
add r6, r11, r6
add r7, r0, r7
eor r4, r4, r6, ror #25
add r6, r1, r12
eor r5, r5, r7, ror #25
add r7, r10, lr
eor r2, r2, r6, ror #25
eor r3, r3, r7, ror #25
strd r2, [sp, #6*4]
add r10, r3, r10
ldrd r6, [sp, #10*4]
add r11, r4, r11
eor r8, r8, r10, ror #23
add r10, r5, r0
eor r9, r9, r11, ror #23
add r11, r2, r1
eor r6, r6, r10, ror #23
eor r7, r7, r11, ror #23
strd r6, [sp, #10*4]
add r2, r7, r2
ldrd r10, [sp, #14*4]
add r3, r8, r3
eor r12, r12, r2, ror #19
add r2, r9, r4
eor lr, lr, r3, ror #19
add r3, r6, r5
eor r10, r10, r2, ror #19
eor r11, r11, r3, ror #19
ldrd r2, [sp, #2*4]
add r6, r11, r6
add r7, r12, r7
eor r0, r0, r6, ror #14
add r6, lr, r8
eor r1, r1, r7, ror #14
add r7, r10, r9
eor r2, r2, r6, ror #14
eor r3, r3, r7, ror #14
.endm
.macro salsa8_core
ldmia sp, {r0-r12, lr}
ldrd r10, [sp, #14*4]
salsa8_core_doubleround_body
ldrd r6, [sp, #6*4]
strd r2, [sp, #2*4]
strd r10, [sp, #14*4]
salsa8_core_doubleround_body
ldrd r6, [sp, #6*4]
strd r2, [sp, #2*4]
strd r10, [sp, #14*4]
salsa8_core_doubleround_body
ldrd r6, [sp, #6*4]
strd r2, [sp, #2*4]
strd r10, [sp, #14*4]
salsa8_core_doubleround_body
stmia sp, {r0-r5}
strd r8, [sp, #8*4]
str r12, [sp, #12*4]
str lr, [sp, #13*4]
strd r10, [sp, #14*4]
.endm
#else
.macro scrypt_shuffle
.endm
.macro salsa8_core_doubleround_body
ldr r8, [sp, #8*4]
add r11, r11, r10
ldr lr, [sp, #13*4]
add r12, r12, r3
eor r2, r2, r11, ror #23
add r11, r4, r0
eor r7, r7, r12, ror #23
add r12, r9, r5
str r9, [sp, #9*4]
eor r8, r8, r11, ror #23
str r10, [sp, #14*4]
eor lr, lr, r12, ror #23
ldr r11, [sp, #11*4]
add r9, lr, r9
ldr r12, [sp, #12*4]
add r10, r2, r10
eor r1, r1, r9, ror #19
add r9, r7, r3
eor r6, r6, r10, ror #19
add r10, r8, r4
str r8, [sp, #8*4]
eor r11, r11, r9, ror #19
str lr, [sp, #13*4]
eor r12, r12, r10, ror #19
ldr r9, [sp, #10*4]
add r8, r12, r8
ldr r10, [sp, #15*4]
add lr, r1, lr
eor r0, r0, r8, ror #14
add r8, r6, r2
eor r5, r5, lr, ror #14
add lr, r11, r7
eor r9, r9, r8, ror #14
ldr r8, [sp, #9*4]
eor r10, r10, lr, ror #14
ldr lr, [sp, #14*4]
add r8, r9, r8
str r9, [sp, #10*4]
add lr, r10, lr
str r10, [sp, #15*4]
eor r11, r11, r8, ror #25
add r8, r0, r3
eor r12, r12, lr, ror #25
add lr, r5, r4
eor r1, r1, r8, ror #25
ldr r8, [sp, #8*4]
eor r6, r6, lr, ror #25
add r9, r11, r9
ldr lr, [sp, #13*4]
add r10, r12, r10
eor r8, r8, r9, ror #23
add r9, r1, r0
eor lr, lr, r10, ror #23
add r10, r6, r5
str r11, [sp, #11*4]
eor r2, r2, r9, ror #23
str r12, [sp, #12*4]
eor r7, r7, r10, ror #23
ldr r9, [sp, #9*4]
add r11, r8, r11
ldr r10, [sp, #14*4]
add r12, lr, r12
eor r9, r9, r11, ror #19
add r11, r2, r1
eor r10, r10, r12, ror #19
add r12, r7, r6
str r8, [sp, #8*4]
eor r3, r3, r11, ror #19
str lr, [sp, #13*4]
eor r4, r4, r12, ror #19
.endm
.macro salsa8_core
ldmia sp, {r0-r7}
ldr r12, [sp, #15*4]
ldr r8, [sp, #11*4]
ldr lr, [sp, #12*4]
ldr r9, [sp, #9*4]
add r8, r8, r12
ldr r11, [sp, #10*4]
add lr, lr, r0
eor r3, r3, r8, ror #25
add r8, r5, r1
ldr r10, [sp, #14*4]
eor r4, r4, lr, ror #25
add lr, r11, r6
eor r9, r9, r8, ror #25
eor r10, r10, lr, ror #25
salsa8_core_doubleround_body
ldr r11, [sp, #10*4]
add r8, r9, r8
ldr r12, [sp, #15*4]
add lr, r10, lr
eor r11, r11, r8, ror #14
add r8, r3, r2
eor r12, r12, lr, ror #14
add lr, r4, r7
eor r0, r0, r8, ror #14
ldr r8, [sp, #11*4]
eor r5, r5, lr, ror #14
ldr lr, [sp, #12*4]
add r8, r8, r12
str r11, [sp, #10*4]
add lr, lr, r0
str r12, [sp, #15*4]
eor r3, r3, r8, ror #25
add r8, r5, r1
eor r4, r4, lr, ror #25
add lr, r11, r6
str r9, [sp, #9*4]
eor r9, r9, r8, ror #25
str r10, [sp, #14*4]
eor r10, r10, lr, ror #25
salsa8_core_doubleround_body
ldr r11, [sp, #10*4]
add r8, r9, r8
ldr r12, [sp, #15*4]
add lr, r10, lr
eor r11, r11, r8, ror #14
add r8, r3, r2
eor r12, r12, lr, ror #14
add lr, r4, r7
eor r0, r0, r8, ror #14
ldr r8, [sp, #11*4]
eor r5, r5, lr, ror #14
ldr lr, [sp, #12*4]
add r8, r8, r12
str r11, [sp, #10*4]
add lr, lr, r0
str r12, [sp, #15*4]
eor r3, r3, r8, ror #25
add r8, r5, r1
eor r4, r4, lr, ror #25
add lr, r11, r6
str r9, [sp, #9*4]
eor r9, r9, r8, ror #25
str r10, [sp, #14*4]
eor r10, r10, lr, ror #25
salsa8_core_doubleround_body
ldr r11, [sp, #10*4]
add r8, r9, r8
ldr r12, [sp, #15*4]
add lr, r10, lr
eor r11, r11, r8, ror #14
add r8, r3, r2
eor r12, r12, lr, ror #14
add lr, r4, r7
eor r0, r0, r8, ror #14
ldr r8, [sp, #11*4]
eor r5, r5, lr, ror #14
ldr lr, [sp, #12*4]
add r8, r8, r12
str r11, [sp, #10*4]
add lr, lr, r0
str r12, [sp, #15*4]
eor r3, r3, r8, ror #25
add r8, r5, r1
eor r4, r4, lr, ror #25
add lr, r11, r6
str r9, [sp, #9*4]
eor r9, r9, r8, ror #25
str r10, [sp, #14*4]
eor r10, r10, lr, ror #25
salsa8_core_doubleround_body
ldr r11, [sp, #10*4]
add r8, r9, r8
ldr r12, [sp, #15*4]
add lr, r10, lr
str r9, [sp, #9*4]
eor r11, r11, r8, ror #14
eor r12, r12, lr, ror #14
add r8, r3, r2
str r10, [sp, #14*4]
add lr, r4, r7
str r11, [sp, #10*4]
eor r0, r0, r8, ror #14
str r12, [sp, #15*4]
eor r5, r5, lr, ror #14
stmia sp, {r0-r7}
.endm
#endif
.macro scrypt_core_macro1a_x4
ldmia r0, {r4-r7}
ldmia lr!, {r8-r11}
stmia r1!, {r4-r7}
stmia r3!, {r8-r11}
eor r4, r4, r8
eor r5, r5, r9
eor r6, r6, r10
eor r7, r7, r11
stmia r0!, {r4-r7}
stmia r12!, {r4-r7}
.endm
.macro scrypt_core_macro1b_x4
ldmia r3!, {r8-r11}
ldmia r2, {r4-r7}
eor r8, r8, r4
eor r9, r9, r5
eor r10, r10, r6
eor r11, r11, r7
ldmia r0, {r4-r7}
stmia r2!, {r8-r11}
eor r4, r4, r8
eor r5, r5, r9
eor r6, r6, r10
eor r7, r7, r11
ldmia r1!, {r8-r11}
eor r4, r4, r8
eor r5, r5, r9
eor r6, r6, r10
eor r7, r7, r11
stmia r0!, {r4-r7}
stmia r12!, {r4-r7}
.endm
.macro scrypt_core_macro2_x4
ldmia r12, {r4-r7}
ldmia r0, {r8-r11}
add r4, r4, r8
add r5, r5, r9
add r6, r6, r10
add r7, r7, r11
stmia r0!, {r4-r7}
ldmia r2, {r8-r11}
eor r4, r4, r8
eor r5, r5, r9
eor r6, r6, r10
eor r7, r7, r11
stmia r2!, {r4-r7}
stmia r12!, {r4-r7}
.endm
.macro scrypt_core_macro3_x4
ldmia r1!, {r4-r7}
ldmia r0, {r8-r11}
add r4, r4, r8
add r5, r5, r9
add r6, r6, r10
add r7, r7, r11
stmia r0!, {r4-r7}
.endm
.macro scrypt_core_macro3_x6
ldmia r1!, {r2-r7}
ldmia r0, {r8-r12, lr}
add r2, r2, r8
add r3, r3, r9
add r4, r4, r10
add r5, r5, r11
add r6, r6, r12
add r7, r7, lr
stmia r0!, {r2-r7}
.endm
.text
.code 32
.align 2
.globl scrypt_core
.globl _scrypt_core
#ifdef __ELF__
.type scrypt_core, %function
#endif
scrypt_core:
_scrypt_core:
stmfd sp!, {r4-r11, lr}
mov r12, sp
sub sp, sp, #22*4
bic sp, sp, #63
str r12, [sp, #20*4]
str r2, [sp, #21*4]
scrypt_shuffle
ldr r2, [sp, #21*4]
str r0, [sp, #16*4]
add r12, r1, r2, lsl #7
str r12, [sp, #18*4]
scrypt_core_loop1:
add lr, r0, #16*4
add r3, r1, #16*4
mov r12, sp
scrypt_core_macro1a_x4
scrypt_core_macro1a_x4
scrypt_core_macro1a_x4
scrypt_core_macro1a_x4
str r1, [sp, #17*4]
salsa8_core
ldr r0, [sp, #16*4]
mov r12, sp
add r2, r0, #16*4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
salsa8_core
ldr r0, [sp, #16*4]
mov r1, sp
add r0, r0, #16*4
scrypt_core_macro3_x6
scrypt_core_macro3_x6
ldr r3, [sp, #17*4]
ldr r12, [sp, #18*4]
scrypt_core_macro3_x4
add r1, r3, #16*4
sub r0, r0, #32*4
cmp r1, r12
bne scrypt_core_loop1
ldr r12, [sp, #21*4]
ldr r4, [r0, #16*4]
sub r2, r12, #1
str r2, [sp, #21*4]
sub r1, r1, r12, lsl #7
str r1, [sp, #17*4]
and r4, r4, r2
add r1, r1, r4, lsl #7
scrypt_core_loop2:
add r2, r0, #16*4
add r3, r1, #16*4
str r12, [sp, #18*4]
mov r12, sp
#ifdef __ARM_ARCH_5E_OR_6_OR_7__
pld [r1, #24*4]
pld [r1, #8*4]
#endif
scrypt_core_macro1b_x4
scrypt_core_macro1b_x4
scrypt_core_macro1b_x4
scrypt_core_macro1b_x4
salsa8_core
ldr r0, [sp, #16*4]
mov r12, sp
add r2, r0, #16*4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
salsa8_core
ldr r0, [sp, #16*4]
mov r1, sp
ldr r3, [sp, #17*4]
add r0, r0, #16*4
ldr r2, [sp, #21*4]
scrypt_core_macro3_x4
and r4, r4, r2
add r3, r3, r4, lsl #7
str r3, [sp, #19*4]
#ifdef __ARM_ARCH_5E_OR_6_OR_7__
pld [r3, #16*4]
pld [r3]
#endif
scrypt_core_macro3_x6
scrypt_core_macro3_x6
ldr r12, [sp, #18*4]
sub r0, r0, #32*4
ldr r1, [sp, #19*4]
subs r12, r12, #1
bne scrypt_core_loop2
scrypt_shuffle
ldr sp, [sp, #20*4]
#ifdef __thumb__
ldmfd sp!, {r4-r11, lr}
bx lr
#else
ldmfd sp!, {r4-r11, pc}
#endif
#ifdef __ARM_NEON__
.macro salsa8_core_3way_doubleround
ldrd r6, [sp, #6*4]
vadd.u32 q4, q0, q1
add r6, r2, r6
vadd.u32 q6, q8, q9
add r7, r3, r7
vshl.u32 q5, q4, #7
eor r10, r10, r6, ror #25
vshl.u32 q7, q6, #7
add r6, r0, r4
vshr.u32 q4, q4, #32-7
eor r11, r11, r7, ror #25
vshr.u32 q6, q6, #32-7
add r7, r1, r5
veor.u32 q3, q3, q5
strd r10, [sp, #14*4]
veor.u32 q11, q11, q7
eor r12, r12, r6, ror #25
veor.u32 q3, q3, q4
eor lr, lr, r7, ror #25
veor.u32 q11, q11, q6
ldrd r6, [sp, #10*4]
vadd.u32 q4, q3, q0
add r2, r10, r2
vadd.u32 q6, q11, q8
add r3, r11, r3
vshl.u32 q5, q4, #9
eor r6, r6, r2, ror #23
vshl.u32 q7, q6, #9
add r2, r12, r0
vshr.u32 q4, q4, #32-9
eor r7, r7, r3, ror #23
vshr.u32 q6, q6, #32-9
add r3, lr, r1
veor.u32 q2, q2, q5
strd r6, [sp, #10*4]
veor.u32 q10, q10, q7
eor r8, r8, r2, ror #23
veor.u32 q2, q2, q4
eor r9, r9, r3, ror #23
veor.u32 q10, q10, q6
ldrd r2, [sp, #6*4]
vadd.u32 q4, q2, q3
add r10, r6, r10
vadd.u32 q6, q10, q11
add r11, r7, r11
vext.u32 q3, q3, q3, #3
eor r2, r2, r10, ror #19
vshl.u32 q5, q4, #13
add r10, r8, r12
vext.u32 q11, q11, q11, #3
eor r3, r3, r11, ror #19
vshl.u32 q7, q6, #13
add r11, r9, lr
vshr.u32 q4, q4, #32-13
eor r4, r4, r10, ror #19
vshr.u32 q6, q6, #32-13
eor r5, r5, r11, ror #19
veor.u32 q1, q1, q5
veor.u32 q9, q9, q7
veor.u32 q1, q1, q4
veor.u32 q9, q9, q6
ldrd r10, [sp, #2*4]
vadd.u32 q4, q1, q2
add r6, r2, r6
vadd.u32 q6, q9, q10
add r7, r3, r7
vswp.u32 d4, d5
eor r10, r10, r6, ror #14
vshl.u32 q5, q4, #18
add r6, r4, r8
vswp.u32 d20, d21
eor r11, r11, r7, ror #14
vshl.u32 q7, q6, #18
add r7, r5, r9
vshr.u32 q4, q4, #32-18
eor r0, r0, r6, ror #14
vshr.u32 q6, q6, #32-18
eor r1, r1, r7, ror #14
veor.u32 q0, q0, q5
ldrd r6, [sp, #14*4]
veor.u32 q8, q8, q7
veor.u32 q0, q0, q4
veor.u32 q8, q8, q6
strd r2, [sp, #6*4]
vadd.u32 q4, q0, q3
strd r10, [sp, #2*4]
vadd.u32 q6, q8, q11
add r6, r11, r6
vext.u32 q1, q1, q1, #1
add r7, r0, r7
vshl.u32 q5, q4, #7
eor r4, r4, r6, ror #25
vext.u32 q9, q9, q9, #1
add r6, r1, r12
vshl.u32 q7, q6, #7
eor r5, r5, r7, ror #25
vshr.u32 q4, q4, #32-7
add r7, r10, lr
vshr.u32 q6, q6, #32-7
eor r2, r2, r6, ror #25
veor.u32 q1, q1, q5
eor r3, r3, r7, ror #25
veor.u32 q9, q9, q7
strd r2, [sp, #6*4]
veor.u32 q1, q1, q4
veor.u32 q9, q9, q6
add r10, r3, r10
vadd.u32 q4, q1, q0
ldrd r6, [sp, #10*4]
vadd.u32 q6, q9, q8
add r11, r4, r11
vshl.u32 q5, q4, #9
eor r8, r8, r10, ror #23
vshl.u32 q7, q6, #9
add r10, r5, r0
vshr.u32 q4, q4, #32-9
eor r9, r9, r11, ror #23
vshr.u32 q6, q6, #32-9
add r11, r2, r1
veor.u32 q2, q2, q5
eor r6, r6, r10, ror #23
veor.u32 q10, q10, q7
eor r7, r7, r11, ror #23
veor.u32 q2, q2, q4
strd r6, [sp, #10*4]
veor.u32 q10, q10, q6
add r2, r7, r2
vadd.u32 q4, q2, q1
ldrd r10, [sp, #14*4]
vadd.u32 q6, q10, q9
add r3, r8, r3
vext.u32 q1, q1, q1, #3
eor r12, r12, r2, ror #19
vshl.u32 q5, q4, #13
add r2, r9, r4
vext.u32 q9, q9, q9, #3
eor lr, lr, r3, ror #19
vshl.u32 q7, q6, #13
add r3, r6, r5
vshr.u32 q4, q4, #32-13
eor r10, r10, r2, ror #19
vshr.u32 q6, q6, #32-13
eor r11, r11, r3, ror #19
veor.u32 q3, q3, q5
veor.u32 q11, q11, q7
veor.u32 q3, q3, q4
veor.u32 q11, q11, q6
ldrd r2, [sp, #2*4]
vadd.u32 q4, q3, q2
add r6, r11, r6
vadd.u32 q6, q11, q10
add r7, r12, r7
vswp.u32 d4, d5
eor r0, r0, r6, ror #14
vshl.u32 q5, q4, #18
add r6, lr, r8
vswp.u32 d20, d21
eor r1, r1, r7, ror #14
vshl.u32 q7, q6, #18
add r7, r10, r9
vext.u32 q3, q3, q3, #1
eor r2, r2, r6, ror #14
vshr.u32 q4, q4, #32-18
eor r3, r3, r7, ror #14
vshr.u32 q6, q6, #32-18
strd r2, [sp, #2*4]
vext.u32 q11, q11, q11, #1
strd r10, [sp, #14*4]
veor.u32 q0, q0, q5
veor.u32 q8, q8, q7
veor.u32 q0, q0, q4
veor.u32 q8, q8, q6
.endm
.macro salsa8_core_3way
ldmia sp, {r0-r12, lr}
ldrd r10, [sp, #14*4]
salsa8_core_3way_doubleround
salsa8_core_3way_doubleround
salsa8_core_3way_doubleround
salsa8_core_3way_doubleround
stmia sp, {r0-r5}
strd r8, [sp, #8*4]
str r12, [sp, #12*4]
str lr, [sp, #13*4]
.endm
.text
.code 32
.align 2
.globl scrypt_core_3way
.globl _scrypt_core_3way
#ifdef __ELF__
.type scrypt_core_3way, %function
#endif
scrypt_core_3way:
_scrypt_core_3way:
stmfd sp!, {r4-r11, lr}
vpush {q4-q7}
mov r12, sp
sub sp, sp, #24*16
bic sp, sp, #63
str r2, [sp, #4*16+3*4]
str r12, [sp, #4*16+4*4]
mov r3, r0
vldmia r3!, {q8-q15}
vmov.u64 q0, #0xffffffff
vmov.u32 q1, q8
vmov.u32 q2, q12
vbif.u32 q8, q9, q0
vbif.u32 q12, q13, q0
vbif.u32 q9, q10, q0
vbif.u32 q13, q14, q0
vbif.u32 q10, q11, q0
vbif.u32 q14, q15, q0
vbif.u32 q11, q1, q0
vbif.u32 q15, q2, q0
vldmia r3!, {q0-q7}
vswp.u32 d17, d21
vswp.u32 d25, d29
vswp.u32 d18, d22
vswp.u32 d26, d30
vstmia r0, {q8-q15}
vmov.u64 q8, #0xffffffff
vmov.u32 q9, q0
vmov.u32 q10, q4
vbif.u32 q0, q1, q8
vbif.u32 q4, q5, q8
vbif.u32 q1, q2, q8
vbif.u32 q5, q6, q8
vbif.u32 q2, q3, q8
vbif.u32 q6, q7, q8
vbif.u32 q3, q9, q8
vbif.u32 q7, q10, q8
vldmia r3, {q8-q15}
vswp.u32 d1, d5
vswp.u32 d9, d13
vswp.u32 d2, d6
vswp.u32 d10, d14
add r12, sp, #8*16
vstmia r12!, {q0-q7}
vmov.u64 q0, #0xffffffff
vmov.u32 q1, q8
vmov.u32 q2, q12
vbif.u32 q8, q9, q0
vbif.u32 q12, q13, q0
vbif.u32 q9, q10, q0
vbif.u32 q13, q14, q0
vbif.u32 q10, q11, q0
vbif.u32 q14, q15, q0
vbif.u32 q11, q1, q0
vbif.u32 q15, q2, q0
vswp.u32 d17, d21
vswp.u32 d25, d29
vswp.u32 d18, d22
vswp.u32 d26, d30
vstmia r12, {q8-q15}
add lr, sp, #128
vldmia lr, {q0-q7}
add r2, r1, r2, lsl #7
str r0, [sp, #4*16+0*4]
str r2, [sp, #4*16+2*4]
scrypt_core_3way_loop1:
add lr, r0, #16*4
add r3, r1, #16*4
str r1, [sp, #4*16+1*4]
mov r12, sp
scrypt_core_macro1a_x4
scrypt_core_macro1a_x4
scrypt_core_macro1a_x4
ldr r2, [sp, #4*16+3*4]
scrypt_core_macro1a_x4
sub r1, r1, #4*16
add r1, r1, r2, lsl #7
vstmia r1, {q0-q7}
add r3, r1, r2, lsl #7
vstmia r3, {q8-q15}
add lr, sp, #128
veor.u32 q0, q0, q4
veor.u32 q1, q1, q5
veor.u32 q2, q2, q6
veor.u32 q3, q3, q7
vstmia lr, {q0-q3}
veor.u32 q8, q8, q12
veor.u32 q9, q9, q13
veor.u32 q10, q10, q14
veor.u32 q11, q11, q15
add r12, sp, #256
vstmia r12, {q8-q11}
salsa8_core_3way
ldr r0, [sp, #4*16+0*4]
mov r12, sp
add r2, r0, #16*4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
add lr, sp, #128
vldmia lr, {q4-q7}
vadd.u32 q4, q4, q0
vadd.u32 q5, q5, q1
vadd.u32 q6, q6, q2
vadd.u32 q7, q7, q3
add r12, sp, #256
vldmia r12, {q0-q3}
vstmia lr, {q4-q7}
vadd.u32 q8, q8, q0
vadd.u32 q9, q9, q1
vadd.u32 q10, q10, q2
vadd.u32 q11, q11, q3
add r4, sp, #128+4*16
vldmia r4, {q0-q3}
vstmia r12, {q8-q11}
veor.u32 q0, q0, q4
veor.u32 q1, q1, q5
veor.u32 q2, q2, q6
veor.u32 q3, q3, q7
vstmia r4, {q0-q3}
veor.u32 q8, q8, q12
veor.u32 q9, q9, q13
veor.u32 q10, q10, q14
veor.u32 q11, q11, q15
vmov q12, q8
vmov q13, q9
vmov q14, q10
vmov q15, q11
salsa8_core_3way
ldr r0, [sp, #4*16+0*4]
mov r1, sp
add r0, r0, #16*4
scrypt_core_macro3_x6
scrypt_core_macro3_x6
scrypt_core_macro3_x4
sub r0, r0, #8*16
ldr r1, [sp, #4*16+1*4]
ldr r2, [sp, #4*16+2*4]
add lr, sp, #128
add r4, sp, #128+4*16
vldmia r4, {q4-q7}
vadd.u32 q4, q4, q0
vadd.u32 q5, q5, q1
vadd.u32 q6, q6, q2
vadd.u32 q7, q7, q3
vstmia r4, {q4-q7}
vldmia lr, {q0-q3}
vadd.u32 q12, q12, q8
vadd.u32 q13, q13, q9
vadd.u32 q14, q14, q10
vadd.u32 q15, q15, q11
add r12, sp, #256
vldmia r12, {q8-q11}
add r1, r1, #8*16
cmp r1, r2
bne scrypt_core_3way_loop1
ldr r2, [sp, #4*16+3*4]
add r5, sp, #256+4*16
vstmia r5, {q12-q15}
sub r1, r1, r2, lsl #7
str r1, [sp, #4*16+1*4]
scrypt_core_3way_loop2:
str r2, [sp, #4*16+2*4]
ldr r0, [sp, #4*16+0*4]
ldr r1, [sp, #4*16+1*4]
ldr r2, [sp, #4*16+3*4]
ldr r4, [r0, #16*4]
sub r2, r2, #1
and r4, r4, r2
add r1, r1, r4, lsl #7
add r2, r0, #16*4
add r3, r1, #16*4
mov r12, sp
scrypt_core_macro1b_x4
scrypt_core_macro1b_x4
scrypt_core_macro1b_x4
scrypt_core_macro1b_x4
ldr r1, [sp, #4*16+1*4]
ldr r2, [sp, #4*16+3*4]
add r1, r1, r2, lsl #7
add r3, r1, r2, lsl #7
sub r2, r2, #1
vmov r6, r7, d8
and r6, r6, r2
add r6, r1, r6, lsl #7
vmov r7, r8, d24
add lr, sp, #128
vldmia lr, {q0-q3}
pld [r6]
pld [r6, #8*4]
pld [r6, #16*4]
pld [r6, #24*4]
vldmia r6, {q8-q15}
and r7, r7, r2
add r7, r3, r7, lsl #7
veor.u32 q8, q8, q0
veor.u32 q9, q9, q1
veor.u32 q10, q10, q2
veor.u32 q11, q11, q3
pld [r7]
pld [r7, #8*4]
pld [r7, #16*4]
pld [r7, #24*4]
veor.u32 q12, q12, q4
veor.u32 q13, q13, q5
veor.u32 q14, q14, q6
veor.u32 q15, q15, q7
vldmia r7, {q0-q7}
vstmia lr, {q8-q15}
add r12, sp, #256
vldmia r12, {q8-q15}
veor.u32 q8, q8, q0
veor.u32 q9, q9, q1
veor.u32 q10, q10, q2
veor.u32 q11, q11, q3
veor.u32 q12, q12, q4
veor.u32 q13, q13, q5
veor.u32 q14, q14, q6
veor.u32 q15, q15, q7
vldmia lr, {q0-q7}
veor.u32 q0, q0, q4
veor.u32 q1, q1, q5
veor.u32 q2, q2, q6
veor.u32 q3, q3, q7
vstmia lr, {q0-q3}
veor.u32 q8, q8, q12
veor.u32 q9, q9, q13
veor.u32 q10, q10, q14
veor.u32 q11, q11, q15
vstmia r12, {q8-q15}
salsa8_core_3way
ldr r0, [sp, #4*16+0*4]
mov r12, sp
add r2, r0, #16*4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
scrypt_core_macro2_x4
add lr, sp, #128
vldmia lr, {q4-q7}
vadd.u32 q4, q4, q0
vadd.u32 q5, q5, q1
vadd.u32 q6, q6, q2
vadd.u32 q7, q7, q3
add r12, sp, #256
vldmia r12, {q12-q15}
vstmia lr, {q4-q7}
vadd.u32 q12, q12, q8
vadd.u32 q13, q13, q9
vadd.u32 q14, q14, q10
vadd.u32 q15, q15, q11
add r4, sp, #128+4*16
vldmia r4, {q0-q3}
vstmia r12, {q12-q15}
veor.u32 q0, q0, q4
veor.u32 q1, q1, q5
veor.u32 q2, q2, q6
veor.u32 q3, q3, q7
add r5, sp, #256+4*16
vldmia r5, {q8-q11}
vstmia r4, {q0-q3}
veor.u32 q8, q8, q12
veor.u32 q9, q9, q13
veor.u32 q10, q10, q14
veor.u32 q11, q11, q15
vmov q12, q8
vmov q13, q9
vmov q14, q10
vmov q15, q11
salsa8_core_3way
ldr r0, [sp, #4*16+0*4]
ldr r3, [sp, #4*16+1*4]
ldr r2, [sp, #4*16+3*4]
mov r1, sp
add r0, r0, #16*4
sub r2, r2, #1
scrypt_core_macro3_x4
and r4, r4, r2
add r3, r3, r4, lsl #7
pld [r3, #16*4]
pld [r3]
pld [r3, #24*4]
pld [r3, #8*4]
scrypt_core_macro3_x6
scrypt_core_macro3_x6
add lr, sp, #128
add r4, sp, #128+4*16
vldmia r4, {q4-q7}
vadd.u32 q4, q4, q0
vadd.u32 q5, q5, q1
vadd.u32 q6, q6, q2
vadd.u32 q7, q7, q3
vstmia r4, {q4-q7}
vadd.u32 q12, q12, q8
vadd.u32 q13, q13, q9
vadd.u32 q14, q14, q10
vadd.u32 q15, q15, q11
add r5, sp, #256+4*16
vstmia r5, {q12-q15}
ldr r2, [sp, #4*16+2*4]
subs r2, r2, #1
bne scrypt_core_3way_loop2
ldr r0, [sp, #4*16+0*4]
vldmia r0, {q8-q15}
vmov.u64 q0, #0xffffffff
vmov.u32 q1, q8
vmov.u32 q2, q12
vbif.u32 q8, q9, q0
vbif.u32 q12, q13, q0
vbif.u32 q9, q10, q0
vbif.u32 q13, q14, q0
vbif.u32 q10, q11, q0
vbif.u32 q14, q15, q0
vbif.u32 q11, q1, q0
vbif.u32 q15, q2, q0
add r12, sp, #8*16
vldmia r12!, {q0-q7}
vswp.u32 d17, d21
vswp.u32 d25, d29
vswp.u32 d18, d22
vswp.u32 d26, d30
vstmia r0!, {q8-q15}
vmov.u64 q8, #0xffffffff
vmov.u32 q9, q0
vmov.u32 q10, q4
vbif.u32 q0, q1, q8
vbif.u32 q4, q5, q8
vbif.u32 q1, q2, q8
vbif.u32 q5, q6, q8
vbif.u32 q2, q3, q8
vbif.u32 q6, q7, q8
vbif.u32 q3, q9, q8
vbif.u32 q7, q10, q8
vldmia r12, {q8-q15}
vswp.u32 d1, d5
vswp.u32 d9, d13
vswp.u32 d2, d6
vswp.u32 d10, d14
vstmia r0!, {q0-q7}
vmov.u64 q0, #0xffffffff
vmov.u32 q1, q8
vmov.u32 q2, q12
vbif.u32 q8, q9, q0
vbif.u32 q12, q13, q0
vbif.u32 q9, q10, q0
vbif.u32 q13, q14, q0
vbif.u32 q10, q11, q0
vbif.u32 q14, q15, q0
vbif.u32 q11, q1, q0
vbif.u32 q15, q2, q0
vswp.u32 d17, d21
vswp.u32 d25, d29
vswp.u32 d18, d22
vswp.u32 d26, d30
vstmia r0, {q8-q15}
ldr sp, [sp, #4*16+4*4]
vpop {q4-q7}
ldmfd sp!, {r4-r11, pc}
#endif /* __ARM_NEON__ */
#endif
|
WyvernTKC/cpuminer-gr-avx2 | 1,339 | asm/aesb-x64.S | #include <cpuminer-config.h>
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
.text
.p2align 6
.globl fast_aesb_single_round
.globl _fast_aesb_single_round
fast_aesb_single_round:
_fast_aesb_single_round:
#if defined(_WIN64) || defined(__CYGWIN__)
movdqa (%rcx), %xmm1
aesenc (%r8), %xmm1
movdqa %xmm1, (%rdx)
#else
movdqa (%rdi), %xmm1
aesenc (%rdx), %xmm1
movdqa %xmm1, (%rsi)
#endif
ret
.text
.p2align 6
.globl fast_aesb_pseudo_round_mut
.globl _fast_aesb_pseudo_round_mut
fast_aesb_pseudo_round_mut:
_fast_aesb_pseudo_round_mut:
#if defined(_WIN64) || defined(__CYGWIN__)
mov %rdx, %r9
add $0xA0, %r9
movdqa (%rcx), %xmm1
.LOOP:
aesenc (%rdx), %xmm1
add $0x10, %rdx
cmp %r9, %rdx
jl .LOOP
movdqa %xmm1, (%rcx)
#else
mov %rsi, %r9
add $0xA0, %r9
movdqa (%rdi), %xmm1
.LOOP:
aesenc (%rsi), %xmm1
add $0x10, %rsi
cmp %r9, %rsi
jl .LOOP
movdqa %xmm1, (%rdi)
#endif
ret
.text
.globl mul128
.globl _mul128
mul128:
_mul128:
#if defined(_WIN64) || defined(__CYGWIN__)
mov %rcx, %rax
mul %rdx
mov %rdx, (%r8)
#else
mov %rdx, %r8
mov %rdi, %rax
mul %rsi
mov %rdx, (%r8)
#endif
ret
|
WyvernTKC/cpuminer-gr-avx2 | 95,935 | asm/sha2-x64.S | /*
* Copyright 2012-2013 pooler@litecoinpool.org
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version. See COPYING for more details.
*/
#include <cpuminer-config.h>
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(USE_ASM) && defined(__x86_64__)
.data
.p2align 7
sha256_4h:
.long 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667
.long 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85
.long 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372
.long 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a
.long 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f
.long 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c
.long 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab
.long 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19
.data
.p2align 7
sha256_4k:
.long 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98
.long 0x71374491, 0x71374491, 0x71374491, 0x71374491
.long 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf
.long 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5
.long 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b
.long 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1
.long 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4
.long 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5
.long 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98
.long 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01
.long 0x243185be, 0x243185be, 0x243185be, 0x243185be
.long 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3
.long 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74
.long 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe
.long 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7
.long 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174
.long 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1
.long 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786
.long 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6
.long 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc
.long 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f
.long 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa
.long 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc
.long 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da
.long 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152
.long 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d
.long 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8
.long 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7
.long 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3
.long 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147
.long 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351
.long 0x14292967, 0x14292967, 0x14292967, 0x14292967
.long 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85
.long 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138
.long 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc
.long 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13
.long 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354
.long 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb
.long 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e
.long 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85
.long 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1
.long 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b
.long 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70
.long 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3
.long 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819
.long 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624
.long 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585
.long 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070
.long 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116
.long 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08
.long 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c
.long 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5
.long 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3
.long 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a
.long 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f
.long 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3
.long 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee
.long 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f
.long 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814
.long 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208
.long 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa
.long 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb
.long 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7
.long 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2
.data
.p2align 6
sha256d_4preext2_17:
.long 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000
sha256d_4preext2_23:
.long 0x11002000, 0x11002000, 0x11002000, 0x11002000
sha256d_4preext2_24:
.long 0x80000000, 0x80000000, 0x80000000, 0x80000000
sha256d_4preext2_30:
.long 0x00400022, 0x00400022, 0x00400022, 0x00400022
#ifdef USE_AVX2
.data
.p2align 7
sha256_8h:
.long 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667, 0x6a09e667
.long 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85, 0xbb67ae85
.long 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372, 0x3c6ef372
.long 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a, 0xa54ff53a
.long 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f, 0x510e527f
.long 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c, 0x9b05688c
.long 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab, 0x1f83d9ab
.long 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19, 0x5be0cd19
.data
.p2align 7
sha256_8k:
.long 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98, 0x428a2f98
.long 0x71374491, 0x71374491, 0x71374491, 0x71374491, 0x71374491, 0x71374491, 0x71374491, 0x71374491
.long 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf, 0xb5c0fbcf
.long 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5, 0xe9b5dba5
.long 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b, 0x3956c25b
.long 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1, 0x59f111f1
.long 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4, 0x923f82a4
.long 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5, 0xab1c5ed5
.long 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98, 0xd807aa98
.long 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01, 0x12835b01
.long 0x243185be, 0x243185be, 0x243185be, 0x243185be, 0x243185be, 0x243185be, 0x243185be, 0x243185be
.long 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3, 0x550c7dc3
.long 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74, 0x72be5d74
.long 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe, 0x80deb1fe
.long 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7, 0x9bdc06a7
.long 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174, 0xc19bf174
.long 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1, 0xe49b69c1
.long 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786, 0xefbe4786
.long 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6, 0x0fc19dc6
.long 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc, 0x240ca1cc
.long 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f, 0x2de92c6f
.long 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa, 0x4a7484aa
.long 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc, 0x5cb0a9dc
.long 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da, 0x76f988da
.long 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152, 0x983e5152
.long 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d, 0xa831c66d
.long 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8, 0xb00327c8
.long 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7, 0xbf597fc7
.long 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3, 0xc6e00bf3
.long 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147, 0xd5a79147
.long 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351, 0x06ca6351
.long 0x14292967, 0x14292967, 0x14292967, 0x14292967, 0x14292967, 0x14292967, 0x14292967, 0x14292967
.long 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85, 0x27b70a85
.long 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138, 0x2e1b2138
.long 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc, 0x4d2c6dfc
.long 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13, 0x53380d13
.long 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354, 0x650a7354
.long 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb, 0x766a0abb
.long 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e, 0x81c2c92e
.long 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85, 0x92722c85
.long 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1, 0xa2bfe8a1
.long 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b, 0xa81a664b
.long 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70, 0xc24b8b70
.long 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3, 0xc76c51a3
.long 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819, 0xd192e819
.long 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624, 0xd6990624
.long 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585, 0xf40e3585
.long 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070, 0x106aa070
.long 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116, 0x19a4c116
.long 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08, 0x1e376c08
.long 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c, 0x2748774c
.long 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5, 0x34b0bcb5
.long 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3, 0x391c0cb3
.long 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a, 0x4ed8aa4a
.long 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f, 0x5b9cca4f
.long 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3, 0x682e6ff3
.long 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee, 0x748f82ee
.long 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f, 0x78a5636f
.long 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814, 0x84c87814
.long 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208, 0x8cc70208
.long 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa, 0x90befffa
.long 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb, 0xa4506ceb
.long 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7, 0xbef9a3f7
.long 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2, 0xc67178f2
.data
.p2align 6
sha256d_8preext2_17:
.long 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000
sha256d_8preext2_23:
.long 0x11002000, 0x11002000, 0x11002000, 0x11002000, 0x11002000, 0x11002000, 0x11002000, 0x11002000
sha256d_8preext2_24:
.long 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000
sha256d_8preext2_30:
.long 0x00400022, 0x00400022, 0x00400022, 0x00400022, 0x00400022, 0x00400022, 0x00400022, 0x00400022
#endif /* USE_AVX2 */
.text
.p2align 6
.globl sha256_init_4way
.globl _sha256_init_4way
sha256_init_4way:
_sha256_init_4way:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
movq %rcx, %rdi
#endif
movdqa sha256_4h+0(%rip), %xmm0
movdqa sha256_4h+16(%rip), %xmm1
movdqa sha256_4h+32(%rip), %xmm2
movdqa sha256_4h+48(%rip), %xmm3
movdqu %xmm0, 0(%rdi)
movdqu %xmm1, 16(%rdi)
movdqu %xmm2, 32(%rdi)
movdqu %xmm3, 48(%rdi)
movdqa sha256_4h+64(%rip), %xmm0
movdqa sha256_4h+80(%rip), %xmm1
movdqa sha256_4h+96(%rip), %xmm2
movdqa sha256_4h+112(%rip), %xmm3
movdqu %xmm0, 64(%rdi)
movdqu %xmm1, 80(%rdi)
movdqu %xmm2, 96(%rdi)
movdqu %xmm3, 112(%rdi)
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rdi
#endif
ret
#ifdef USE_AVX2
.text
.p2align 6
.globl sha256_init_8way
.globl _sha256_init_8way
sha256_init_8way:
_sha256_init_8way:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
movq %rcx, %rdi
#endif
vpbroadcastd sha256_4h+0(%rip), %ymm0
vpbroadcastd sha256_4h+16(%rip), %ymm1
vpbroadcastd sha256_4h+32(%rip), %ymm2
vpbroadcastd sha256_4h+48(%rip), %ymm3
vmovdqu %ymm0, 0*32(%rdi)
vmovdqu %ymm1, 1*32(%rdi)
vmovdqu %ymm2, 2*32(%rdi)
vmovdqu %ymm3, 3*32(%rdi)
vpbroadcastd sha256_4h+64(%rip), %ymm0
vpbroadcastd sha256_4h+80(%rip), %ymm1
vpbroadcastd sha256_4h+96(%rip), %ymm2
vpbroadcastd sha256_4h+112(%rip), %ymm3
vmovdqu %ymm0, 4*32(%rdi)
vmovdqu %ymm1, 5*32(%rdi)
vmovdqu %ymm2, 6*32(%rdi)
vmovdqu %ymm3, 7*32(%rdi)
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rdi
#endif
ret
#endif /* USE_AVX2 */
.macro sha256_sse2_extend_round i
movdqa (\i-15)*16(%rax), %xmm0
movdqa %xmm0, %xmm2
psrld $3, %xmm0
movdqa %xmm0, %xmm1
pslld $14, %xmm2
psrld $4, %xmm1
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
psrld $11, %xmm1
pslld $11, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
paddd (\i-16)*16(%rax), %xmm0
paddd (\i-7)*16(%rax), %xmm0
movdqa %xmm3, %xmm2
psrld $10, %xmm3
pslld $13, %xmm2
movdqa %xmm3, %xmm1
psrld $7, %xmm1
pxor %xmm1, %xmm3
pxor %xmm2, %xmm3
psrld $2, %xmm1
pslld $2, %xmm2
pxor %xmm1, %xmm3
pxor %xmm2, %xmm3
paddd %xmm0, %xmm3
movdqa %xmm3, \i*16(%rax)
.endm
.macro sha256_sse2_extend_doubleround i
movdqa (\i-15)*16(%rax), %xmm0
movdqa (\i-14)*16(%rax), %xmm4
movdqa %xmm0, %xmm2
movdqa %xmm4, %xmm6
psrld $3, %xmm0
psrld $3, %xmm4
movdqa %xmm0, %xmm1
movdqa %xmm4, %xmm5
pslld $14, %xmm2
pslld $14, %xmm6
psrld $4, %xmm1
psrld $4, %xmm5
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
psrld $11, %xmm1
psrld $11, %xmm5
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
pslld $11, %xmm2
pslld $11, %xmm6
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
paddd (\i-16)*16(%rax), %xmm0
paddd (\i-15)*16(%rax), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd (\i-7)*16(%rax), %xmm0
paddd (\i-6)*16(%rax), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, \i*16(%rax)
movdqa %xmm7, (\i+1)*16(%rax)
.endm
.macro sha256_sse2_main_round i
movdqa 16*(\i)(%rax), %xmm6
movdqa %xmm0, %xmm1
movdqa 16(%rsp), %xmm2
pandn %xmm2, %xmm1
paddd 32(%rsp), %xmm6
movdqa %xmm2, 32(%rsp)
movdqa 0(%rsp), %xmm2
movdqa %xmm2, 16(%rsp)
pand %xmm0, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm0, 0(%rsp)
paddd %xmm1, %xmm6
movdqa %xmm0, %xmm1
psrld $6, %xmm0
paddd 16*(\i)(%rcx), %xmm6
movdqa %xmm0, %xmm2
pslld $7, %xmm1
psrld $5, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $14, %xmm1
psrld $14, %xmm2
pxor %xmm1, %xmm0
pslld $5, %xmm1
pxor %xmm2, %xmm0
pxor %xmm1, %xmm0
movdqa %xmm5, %xmm1
paddd %xmm0, %xmm6
movdqa %xmm3, %xmm0
movdqa %xmm4, %xmm3
movdqa %xmm4, %xmm2
paddd %xmm6, %xmm0
pand %xmm5, %xmm2
pand %xmm7, %xmm1
pand %xmm7, %xmm4
pxor %xmm4, %xmm1
movdqa %xmm5, %xmm4
movdqa %xmm7, %xmm5
pxor %xmm2, %xmm1
paddd %xmm1, %xmm6
movdqa %xmm7, %xmm2
psrld $2, %xmm7
movdqa %xmm7, %xmm1
pslld $10, %xmm2
psrld $11, %xmm1
pxor %xmm2, %xmm7
pslld $9, %xmm2
pxor %xmm1, %xmm7
psrld $9, %xmm1
pxor %xmm2, %xmm7
pslld $11, %xmm2
pxor %xmm1, %xmm7
pxor %xmm2, %xmm7
paddd %xmm6, %xmm7
.endm
.macro sha256_sse2_main_quadround i
sha256_sse2_main_round \i+0
sha256_sse2_main_round \i+1
sha256_sse2_main_round \i+2
sha256_sse2_main_round \i+3
.endm
#if defined(USE_AVX)
.macro sha256_avx_extend_round i
vmovdqa (\i-15)*16(%rax), %xmm0
vpslld $14, %xmm0, %xmm2
vpsrld $3, %xmm0, %xmm0
vpsrld $4, %xmm0, %xmm1
vpxor %xmm1, %xmm0, %xmm0
vpxor %xmm2, %xmm0, %xmm0
vpsrld $11, %xmm1, %xmm1
vpslld $11, %xmm2, %xmm2
vpxor %xmm1, %xmm0, %xmm0
vpxor %xmm2, %xmm0, %xmm0
vpaddd (\i-16)*16(%rax), %xmm0, %xmm0
vpaddd (\i-7)*16(%rax), %xmm0, %xmm0
vpslld $13, %xmm3, %xmm2
vpsrld $10, %xmm3, %xmm3
vpsrld $7, %xmm3, %xmm1
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm2, %xmm3, %xmm3
vpsrld $2, %xmm1, %xmm1
vpslld $2, %xmm2, %xmm2
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm2, %xmm3, %xmm3
vpaddd %xmm0, %xmm3, %xmm3
vmovdqa %xmm3, \i*16(%rax)
.endm
.macro sha256_avx_extend_doubleround i
vmovdqa (\i-15)*16(%rax), %xmm0
vmovdqa (\i-14)*16(%rax), %xmm4
vpslld $14, %xmm0, %xmm2
vpslld $14, %xmm4, %xmm6
vpsrld $3, %xmm0, %xmm8
vpsrld $3, %xmm4, %xmm4
vpsrld $7, %xmm0, %xmm1
vpsrld $4, %xmm4, %xmm5
vpxor %xmm1, %xmm8, %xmm8
vpxor %xmm5, %xmm4, %xmm4
vpsrld $11, %xmm1, %xmm1
vpsrld $11, %xmm5, %xmm5
vpxor %xmm2, %xmm8, %xmm8
vpxor %xmm6, %xmm4, %xmm4
vpslld $11, %xmm2, %xmm2
vpslld $11, %xmm6, %xmm6
vpxor %xmm1, %xmm8, %xmm8
vpxor %xmm5, %xmm4, %xmm4
vpxor %xmm2, %xmm8, %xmm8
vpxor %xmm6, %xmm4, %xmm4
vpaddd %xmm0, %xmm4, %xmm4
vpaddd (\i-16)*16(%rax), %xmm8, %xmm0
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpaddd (\i-7)*16(%rax), %xmm0, %xmm0
vpaddd (\i-6)*16(%rax), %xmm4, %xmm4
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, \i*16(%rax)
vmovdqa %xmm7, (\i+1)*16(%rax)
.endm
.macro sha256_avx_main_round i, r0, r1, r2, r3, r4, r5, r6, r7
vpaddd 16*(\i)(%rax), \r0, %xmm6
vpaddd 16*(\i)(%rcx), %xmm6, %xmm6
vpandn \r1, \r3, %xmm1
vpand \r3, \r2, %xmm2
vpxor %xmm2, %xmm1, %xmm1
vpaddd %xmm1, %xmm6, %xmm6
vpslld $7, \r3, %xmm1
vpsrld $6, \r3, \r0
vpsrld $5, \r0, %xmm2
vpxor %xmm1, \r0, \r0
vpxor %xmm2, \r0, \r0
vpslld $14, %xmm1, %xmm1
vpsrld $14, %xmm2, %xmm2
vpxor %xmm1, \r0, \r0
vpxor %xmm2, \r0, \r0
vpslld $5, %xmm1, %xmm1
vpxor %xmm1, \r0, \r0
vpaddd \r0, %xmm6, %xmm6
vpaddd %xmm6, \r4, \r0
vpand \r6, \r5, %xmm2
vpand \r7, \r5, \r4
vpand \r7, \r6, %xmm1
vpxor \r4, %xmm1, %xmm1
vpxor %xmm2, %xmm1, %xmm1
vpaddd %xmm1, %xmm6, %xmm6
vpslld $10, \r7, %xmm2
vpsrld $2, \r7, \r4
vpsrld $11, \r4, %xmm1
vpxor %xmm2, \r4, \r4
vpxor %xmm1, \r4, \r4
vpslld $9, %xmm2, %xmm2
vpsrld $9, %xmm1, %xmm1
vpxor %xmm2, \r4, \r4
vpxor %xmm1, \r4, \r4
vpslld $11, %xmm2, %xmm2
vpxor %xmm2, \r4, \r4
vpaddd %xmm6, \r4, \r4
.endm
.macro sha256_avx_main_quadround i
sha256_avx_main_round \i+0, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3, %xmm4, %xmm5, %xmm7
sha256_avx_main_round \i+1, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4, %xmm5, %xmm7, %xmm3
sha256_avx_main_round \i+2, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5, %xmm7, %xmm3, %xmm4
sha256_avx_main_round \i+3, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7, %xmm3, %xmm4, %xmm5
.endm
#endif /* USE_AVX */
#if defined(USE_AVX2)
.macro sha256_avx2_extend_round i
vmovdqa (\i-15)*32(%rax), %ymm0
vpslld $14, %ymm0, %ymm2
vpsrld $3, %ymm0, %ymm0
vpsrld $4, %ymm0, %ymm1
vpxor %ymm1, %ymm0, %ymm0
vpxor %ymm2, %ymm0, %ymm0
vpsrld $11, %ymm1, %ymm1
vpslld $11, %ymm2, %ymm2
vpxor %ymm1, %ymm0, %ymm0
vpxor %ymm2, %ymm0, %ymm0
vpaddd (\i-16)*32(%rax), %ymm0, %ymm0
vpaddd (\i-7)*32(%rax), %ymm0, %ymm0
vpslld $13, %ymm3, %ymm2
vpsrld $10, %ymm3, %ymm3
vpsrld $7, %ymm3, %ymm1
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm2, %ymm3, %ymm3
vpsrld $2, %ymm1, %ymm1
vpslld $2, %ymm2, %ymm2
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm2, %ymm3, %ymm3
vpaddd %ymm0, %ymm3, %ymm3
vmovdqa %ymm3, \i*32(%rax)
.endm
.macro sha256_avx2_extend_doubleround i
vmovdqa (\i-15)*32(%rax), %ymm0
vmovdqa (\i-14)*32(%rax), %ymm4
vpslld $14, %ymm0, %ymm2
vpslld $14, %ymm4, %ymm6
vpsrld $3, %ymm0, %ymm8
vpsrld $3, %ymm4, %ymm4
vpsrld $7, %ymm0, %ymm1
vpsrld $4, %ymm4, %ymm5
vpxor %ymm1, %ymm8, %ymm8
vpxor %ymm5, %ymm4, %ymm4
vpsrld $11, %ymm1, %ymm1
vpsrld $11, %ymm5, %ymm5
vpxor %ymm2, %ymm8, %ymm8
vpxor %ymm6, %ymm4, %ymm4
vpslld $11, %ymm2, %ymm2
vpslld $11, %ymm6, %ymm6
vpxor %ymm1, %ymm8, %ymm8
vpxor %ymm5, %ymm4, %ymm4
vpxor %ymm2, %ymm8, %ymm8
vpxor %ymm6, %ymm4, %ymm4
vpaddd %ymm0, %ymm4, %ymm4
vpaddd (\i-16)*32(%rax), %ymm8, %ymm0
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpaddd (\i-7)*32(%rax), %ymm0, %ymm0
vpaddd (\i-6)*32(%rax), %ymm4, %ymm4
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vpaddd %ymm4, %ymm7, %ymm7
vmovdqa %ymm3, \i*32(%rax)
vmovdqa %ymm7, (\i+1)*32(%rax)
.endm
.macro sha256_avx2_main_round i, r0, r1, r2, r3, r4, r5, r6, r7
vpaddd 32*(\i)(%rax), \r0, %ymm6
vpaddd 32*(\i)(%rcx), %ymm6, %ymm6
vpandn \r1, \r3, %ymm1
vpand \r3, \r2, %ymm2
vpxor %ymm2, %ymm1, %ymm1
vpaddd %ymm1, %ymm6, %ymm6
vpslld $7, \r3, %ymm1
vpsrld $6, \r3, \r0
vpsrld $5, \r0, %ymm2
vpxor %ymm1, \r0, \r0
vpxor %ymm2, \r0, \r0
vpslld $14, %ymm1, %ymm1
vpsrld $14, %ymm2, %ymm2
vpxor %ymm1, \r0, \r0
vpxor %ymm2, \r0, \r0
vpslld $5, %ymm1, %ymm1
vpxor %ymm1, \r0, \r0
vpaddd \r0, %ymm6, %ymm6
vpaddd %ymm6, \r4, \r0
vpand \r6, \r5, %ymm2
vpand \r7, \r5, \r4
vpand \r7, \r6, %ymm1
vpxor \r4, %ymm1, %ymm1
vpxor %ymm2, %ymm1, %ymm1
vpaddd %ymm1, %ymm6, %ymm6
vpslld $10, \r7, %ymm2
vpsrld $2, \r7, \r4
vpsrld $11, \r4, %ymm1
vpxor %ymm2, \r4, \r4
vpxor %ymm1, \r4, \r4
vpslld $9, %ymm2, %ymm2
vpsrld $9, %ymm1, %ymm1
vpxor %ymm2, \r4, \r4
vpxor %ymm1, \r4, \r4
vpslld $11, %ymm2, %ymm2
vpxor %ymm2, \r4, \r4
vpaddd %ymm6, \r4, \r4
.endm
.macro sha256_avx2_main_quadround i
sha256_avx2_main_round \i+0, %ymm10, %ymm9, %ymm8, %ymm0, %ymm3, %ymm4, %ymm5, %ymm7
sha256_avx2_main_round \i+1, %ymm9, %ymm8, %ymm0, %ymm10, %ymm4, %ymm5, %ymm7, %ymm3
sha256_avx2_main_round \i+2, %ymm8, %ymm0, %ymm10, %ymm9, %ymm5, %ymm7, %ymm3, %ymm4
sha256_avx2_main_round \i+3, %ymm0, %ymm10, %ymm9, %ymm8, %ymm7, %ymm3, %ymm4, %ymm5
.endm
#endif /* USE_AVX2 */
#if defined(USE_XOP)
.macro sha256_xop_extend_round i
vmovdqa (\i-15)*16(%rax), %xmm0
vprotd $25, %xmm0, %xmm1
vprotd $14, %xmm0, %xmm2
vpsrld $3, %xmm0, %xmm0
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm2, %xmm0, %xmm0
vpaddd (\i-16)*16(%rax), %xmm0, %xmm0
vpaddd (\i-7)*16(%rax), %xmm0, %xmm0
vprotd $15, %xmm3, %xmm1
vprotd $13, %xmm3, %xmm2
vpsrld $10, %xmm3, %xmm3
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm2, %xmm3, %xmm3
vpaddd %xmm0, %xmm3, %xmm3
vmovdqa %xmm3, \i*16(%rax)
.endm
.macro sha256_xop_extend_doubleround i
vmovdqa (\i-15)*16(%rax), %xmm0
vmovdqa (\i-14)*16(%rax), %xmm4
vprotd $25, %xmm0, %xmm1
vprotd $25, %xmm4, %xmm5
vprotd $14, %xmm0, %xmm2
vprotd $14, %xmm4, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $3, %xmm0, %xmm0
vpsrld $3, %xmm4, %xmm4
vpxor %xmm2, %xmm0, %xmm0
vpxor %xmm6, %xmm4, %xmm4
vpaddd (\i-16)*16(%rax), %xmm0, %xmm0
vpaddd (\i-15)*16(%rax), %xmm4, %xmm4
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpaddd (\i-7)*16(%rax), %xmm0, %xmm0
vpaddd (\i-6)*16(%rax), %xmm4, %xmm4
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, \i*16(%rax)
vmovdqa %xmm7, (\i+1)*16(%rax)
.endm
.macro sha256_xop_main_round i, r0, r1, r2, r3, r4, r5, r6, r7
vpaddd 16*(\i)(%rax), \r0, %xmm6
vpaddd 16*(\i)(%rcx), %xmm6, %xmm6
vpandn \r1, \r3, %xmm1
vpand \r3, \r2, %xmm2
vpxor %xmm2, %xmm1, %xmm1
vpaddd %xmm1, %xmm6, %xmm6
vprotd $26, \r3, %xmm1
vprotd $21, \r3, %xmm2
vpxor %xmm1, %xmm2, %xmm2
vprotd $7, \r3, \r0
vpxor %xmm2, \r0, \r0
vpaddd \r0, %xmm6, %xmm6
vpaddd %xmm6, \r4, \r0
vpand \r6, \r5, %xmm2
vpand \r7, \r5, \r4
vpand \r7, \r6, %xmm1
vpxor \r4, %xmm1, %xmm1
vpxor %xmm2, %xmm1, %xmm1
vpaddd %xmm1, %xmm6, %xmm6
vprotd $30, \r7, %xmm1
vprotd $19, \r7, %xmm2
vpxor %xmm1, %xmm2, %xmm2
vprotd $10, \r7, \r4
vpxor %xmm2, \r4, \r4
vpaddd %xmm6, \r4, \r4
.endm
.macro sha256_xop_main_quadround i
sha256_xop_main_round \i+0, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3, %xmm4, %xmm5, %xmm7
sha256_xop_main_round \i+1, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4, %xmm5, %xmm7, %xmm3
sha256_xop_main_round \i+2, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5, %xmm7, %xmm3, %xmm4
sha256_xop_main_round \i+3, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7, %xmm3, %xmm4, %xmm5
.endm
#endif /* USE_XOP */
.text
.p2align 6
sha256_transform_4way_core_sse2:
leaq 256(%rsp), %rcx
leaq 48*16(%rcx), %rax
movdqa -2*16(%rcx), %xmm3
movdqa -1*16(%rcx), %xmm7
sha256_transform_4way_sse2_extend_loop:
movdqa -15*16(%rcx), %xmm0
movdqa -14*16(%rcx), %xmm4
movdqa %xmm0, %xmm2
movdqa %xmm4, %xmm6
psrld $3, %xmm0
psrld $3, %xmm4
movdqa %xmm0, %xmm1
movdqa %xmm4, %xmm5
pslld $14, %xmm2
pslld $14, %xmm6
psrld $4, %xmm1
psrld $4, %xmm5
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
psrld $11, %xmm1
psrld $11, %xmm5
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
pslld $11, %xmm2
pslld $11, %xmm6
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
paddd -16*16(%rcx), %xmm0
paddd -15*16(%rcx), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd -7*16(%rcx), %xmm0
paddd -6*16(%rcx), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, (%rcx)
movdqa %xmm7, 16(%rcx)
addq $2*16, %rcx
cmpq %rcx, %rax
jne sha256_transform_4way_sse2_extend_loop
movdqu 0(%rdi), %xmm7
movdqu 16(%rdi), %xmm5
movdqu 32(%rdi), %xmm4
movdqu 48(%rdi), %xmm3
movdqu 64(%rdi), %xmm0
movdqu 80(%rdi), %xmm8
movdqu 96(%rdi), %xmm9
movdqu 112(%rdi), %xmm10
leaq sha256_4k(%rip), %rcx
xorq %rax, %rax
sha256_transform_4way_sse2_main_loop:
movdqa (%rsp, %rax), %xmm6
paddd (%rcx, %rax), %xmm6
paddd %xmm10, %xmm6
movdqa %xmm0, %xmm1
movdqa %xmm9, %xmm2
pandn %xmm2, %xmm1
movdqa %xmm2, %xmm10
movdqa %xmm8, %xmm2
movdqa %xmm2, %xmm9
pand %xmm0, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm0, %xmm8
paddd %xmm1, %xmm6
movdqa %xmm0, %xmm1
psrld $6, %xmm0
movdqa %xmm0, %xmm2
pslld $7, %xmm1
psrld $5, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $14, %xmm1
psrld $14, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $5, %xmm1
pxor %xmm1, %xmm0
paddd %xmm0, %xmm6
movdqa %xmm3, %xmm0
paddd %xmm6, %xmm0
movdqa %xmm5, %xmm1
movdqa %xmm4, %xmm3
movdqa %xmm4, %xmm2
pand %xmm5, %xmm2
pand %xmm7, %xmm4
pand %xmm7, %xmm1
pxor %xmm4, %xmm1
movdqa %xmm5, %xmm4
movdqa %xmm7, %xmm5
pxor %xmm2, %xmm1
paddd %xmm1, %xmm6
movdqa %xmm7, %xmm2
psrld $2, %xmm7
movdqa %xmm7, %xmm1
pslld $10, %xmm2
psrld $11, %xmm1
pxor %xmm2, %xmm7
pxor %xmm1, %xmm7
pslld $9, %xmm2
psrld $9, %xmm1
pxor %xmm2, %xmm7
pxor %xmm1, %xmm7
pslld $11, %xmm2
pxor %xmm2, %xmm7
paddd %xmm6, %xmm7
addq $16, %rax
cmpq $16*64, %rax
jne sha256_transform_4way_sse2_main_loop
jmp sha256_transform_4way_finish
#if defined(USE_AVX)
.text
.p2align 6
sha256_transform_4way_core_avx:
leaq 256(%rsp), %rax
movdqa -2*16(%rax), %xmm3
movdqa -1*16(%rax), %xmm7
sha256_avx_extend_doubleround 0
sha256_avx_extend_doubleround 2
sha256_avx_extend_doubleround 4
sha256_avx_extend_doubleround 6
sha256_avx_extend_doubleround 8
sha256_avx_extend_doubleround 10
sha256_avx_extend_doubleround 12
sha256_avx_extend_doubleround 14
sha256_avx_extend_doubleround 16
sha256_avx_extend_doubleround 18
sha256_avx_extend_doubleround 20
sha256_avx_extend_doubleround 22
sha256_avx_extend_doubleround 24
sha256_avx_extend_doubleround 26
sha256_avx_extend_doubleround 28
sha256_avx_extend_doubleround 30
sha256_avx_extend_doubleround 32
sha256_avx_extend_doubleround 34
sha256_avx_extend_doubleround 36
sha256_avx_extend_doubleround 38
sha256_avx_extend_doubleround 40
sha256_avx_extend_doubleround 42
sha256_avx_extend_doubleround 44
sha256_avx_extend_doubleround 46
movdqu 0(%rdi), %xmm7
movdqu 16(%rdi), %xmm5
movdqu 32(%rdi), %xmm4
movdqu 48(%rdi), %xmm3
movdqu 64(%rdi), %xmm0
movdqu 80(%rdi), %xmm8
movdqu 96(%rdi), %xmm9
movdqu 112(%rdi), %xmm10
movq %rsp, %rax
leaq sha256_4k(%rip), %rcx
sha256_avx_main_quadround 0
sha256_avx_main_quadround 4
sha256_avx_main_quadround 8
sha256_avx_main_quadround 12
sha256_avx_main_quadround 16
sha256_avx_main_quadround 20
sha256_avx_main_quadround 24
sha256_avx_main_quadround 28
sha256_avx_main_quadround 32
sha256_avx_main_quadround 36
sha256_avx_main_quadround 40
sha256_avx_main_quadround 44
sha256_avx_main_quadround 48
sha256_avx_main_quadround 52
sha256_avx_main_quadround 56
sha256_avx_main_quadround 60
jmp sha256_transform_4way_finish
#endif /* USE_AVX */
#if defined(USE_XOP)
.text
.p2align 6
sha256_transform_4way_core_xop:
leaq 256(%rsp), %rax
movdqa -2*16(%rax), %xmm3
movdqa -1*16(%rax), %xmm7
sha256_xop_extend_doubleround 0
sha256_xop_extend_doubleround 2
sha256_xop_extend_doubleround 4
sha256_xop_extend_doubleround 6
sha256_xop_extend_doubleround 8
sha256_xop_extend_doubleround 10
sha256_xop_extend_doubleround 12
sha256_xop_extend_doubleround 14
sha256_xop_extend_doubleround 16
sha256_xop_extend_doubleround 18
sha256_xop_extend_doubleround 20
sha256_xop_extend_doubleround 22
sha256_xop_extend_doubleround 24
sha256_xop_extend_doubleround 26
sha256_xop_extend_doubleround 28
sha256_xop_extend_doubleround 30
sha256_xop_extend_doubleround 32
sha256_xop_extend_doubleround 34
sha256_xop_extend_doubleround 36
sha256_xop_extend_doubleround 38
sha256_xop_extend_doubleround 40
sha256_xop_extend_doubleround 42
sha256_xop_extend_doubleround 44
sha256_xop_extend_doubleround 46
movdqu 0(%rdi), %xmm7
movdqu 16(%rdi), %xmm5
movdqu 32(%rdi), %xmm4
movdqu 48(%rdi), %xmm3
movdqu 64(%rdi), %xmm0
movdqu 80(%rdi), %xmm8
movdqu 96(%rdi), %xmm9
movdqu 112(%rdi), %xmm10
movq %rsp, %rax
leaq sha256_4k(%rip), %rcx
sha256_xop_main_quadround 0
sha256_xop_main_quadround 4
sha256_xop_main_quadround 8
sha256_xop_main_quadround 12
sha256_xop_main_quadround 16
sha256_xop_main_quadround 20
sha256_xop_main_quadround 24
sha256_xop_main_quadround 28
sha256_xop_main_quadround 32
sha256_xop_main_quadround 36
sha256_xop_main_quadround 40
sha256_xop_main_quadround 44
sha256_xop_main_quadround 48
sha256_xop_main_quadround 52
sha256_xop_main_quadround 56
sha256_xop_main_quadround 60
jmp sha256_transform_4way_finish
#endif /* USE_XOP */
.data
.p2align 3
sha256_transform_4way_core_addr:
.quad 0x0
.macro p2bswap_rsi_rsp i
movdqu \i*16(%rsi), %xmm0
movdqu (\i+1)*16(%rsi), %xmm2
pshuflw $0xb1, %xmm0, %xmm0
pshuflw $0xb1, %xmm2, %xmm2
pshufhw $0xb1, %xmm0, %xmm0
pshufhw $0xb1, %xmm2, %xmm2
movdqa %xmm0, %xmm1
movdqa %xmm2, %xmm3
psrlw $8, %xmm1
psrlw $8, %xmm3
psllw $8, %xmm0
psllw $8, %xmm2
pxor %xmm1, %xmm0
pxor %xmm3, %xmm2
movdqa %xmm0, \i*16(%rsp)
movdqa %xmm2, (\i+1)*16(%rsp)
.endm
.text
.p2align 6
.globl sha256_transform_4way
.globl _sha256_transform_4way
sha256_transform_4way:
_sha256_transform_4way:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
subq $96, %rsp
movdqa %xmm6, 0(%rsp)
movdqa %xmm7, 16(%rsp)
movdqa %xmm8, 32(%rsp)
movdqa %xmm9, 48(%rsp)
movdqa %xmm10, 64(%rsp)
movdqa %xmm11, 80(%rsp)
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
#endif
movq %rsp, %r8
subq $1032, %rsp
andq $-128, %rsp
testq %rdx, %rdx
jnz sha256_transform_4way_swap
movdqu 0*16(%rsi), %xmm0
movdqu 1*16(%rsi), %xmm1
movdqu 2*16(%rsi), %xmm2
movdqu 3*16(%rsi), %xmm3
movdqu 4*16(%rsi), %xmm4
movdqu 5*16(%rsi), %xmm5
movdqu 6*16(%rsi), %xmm6
movdqu 7*16(%rsi), %xmm7
movdqa %xmm0, 0*16(%rsp)
movdqa %xmm1, 1*16(%rsp)
movdqa %xmm2, 2*16(%rsp)
movdqa %xmm3, 3*16(%rsp)
movdqa %xmm4, 4*16(%rsp)
movdqa %xmm5, 5*16(%rsp)
movdqa %xmm6, 6*16(%rsp)
movdqa %xmm7, 7*16(%rsp)
movdqu 8*16(%rsi), %xmm0
movdqu 9*16(%rsi), %xmm1
movdqu 10*16(%rsi), %xmm2
movdqu 11*16(%rsi), %xmm3
movdqu 12*16(%rsi), %xmm4
movdqu 13*16(%rsi), %xmm5
movdqu 14*16(%rsi), %xmm6
movdqu 15*16(%rsi), %xmm7
movdqa %xmm0, 8*16(%rsp)
movdqa %xmm1, 9*16(%rsp)
movdqa %xmm2, 10*16(%rsp)
movdqa %xmm3, 11*16(%rsp)
movdqa %xmm4, 12*16(%rsp)
movdqa %xmm5, 13*16(%rsp)
movdqa %xmm6, 14*16(%rsp)
movdqa %xmm7, 15*16(%rsp)
jmp *sha256_transform_4way_core_addr(%rip)
.p2align 6
sha256_transform_4way_swap:
p2bswap_rsi_rsp 0
p2bswap_rsi_rsp 2
p2bswap_rsi_rsp 4
p2bswap_rsi_rsp 6
p2bswap_rsi_rsp 8
p2bswap_rsi_rsp 10
p2bswap_rsi_rsp 12
p2bswap_rsi_rsp 14
jmp *sha256_transform_4way_core_addr(%rip)
.p2align 6
sha256_transform_4way_finish:
movdqu 0(%rdi), %xmm2
movdqu 16(%rdi), %xmm6
movdqu 32(%rdi), %xmm11
movdqu 48(%rdi), %xmm1
paddd %xmm2, %xmm7
paddd %xmm6, %xmm5
paddd %xmm11, %xmm4
paddd %xmm1, %xmm3
movdqu 64(%rdi), %xmm2
movdqu 80(%rdi), %xmm6
movdqu 96(%rdi), %xmm11
movdqu 112(%rdi), %xmm1
paddd %xmm2, %xmm0
paddd %xmm6, %xmm8
paddd %xmm11, %xmm9
paddd %xmm1, %xmm10
movdqu %xmm7, 0(%rdi)
movdqu %xmm5, 16(%rdi)
movdqu %xmm4, 32(%rdi)
movdqu %xmm3, 48(%rdi)
movdqu %xmm0, 64(%rdi)
movdqu %xmm8, 80(%rdi)
movdqu %xmm9, 96(%rdi)
movdqu %xmm10, 112(%rdi)
movq %r8, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
movdqa 0(%rsp), %xmm6
movdqa 16(%rsp), %xmm7
movdqa 32(%rsp), %xmm8
movdqa 48(%rsp), %xmm9
movdqa 64(%rsp), %xmm10
movdqa 80(%rsp), %xmm11
addq $96, %rsp
popq %rdi
#endif
ret
#ifdef USE_AVX2
.text
.p2align 6
sha256_transform_8way_core_avx2:
leaq 8*64(%rsp), %rax
vmovdqa -2*32(%rax), %ymm3
vmovdqa -1*32(%rax), %ymm7
sha256_avx2_extend_doubleround 0
sha256_avx2_extend_doubleround 2
sha256_avx2_extend_doubleround 4
sha256_avx2_extend_doubleround 6
sha256_avx2_extend_doubleround 8
sha256_avx2_extend_doubleround 10
sha256_avx2_extend_doubleround 12
sha256_avx2_extend_doubleround 14
sha256_avx2_extend_doubleround 16
sha256_avx2_extend_doubleround 18
sha256_avx2_extend_doubleround 20
sha256_avx2_extend_doubleround 22
sha256_avx2_extend_doubleround 24
sha256_avx2_extend_doubleround 26
sha256_avx2_extend_doubleround 28
sha256_avx2_extend_doubleround 30
sha256_avx2_extend_doubleround 32
sha256_avx2_extend_doubleround 34
sha256_avx2_extend_doubleround 36
sha256_avx2_extend_doubleround 38
sha256_avx2_extend_doubleround 40
sha256_avx2_extend_doubleround 42
sha256_avx2_extend_doubleround 44
sha256_avx2_extend_doubleround 46
vmovdqu 0*32(%rdi), %ymm7
vmovdqu 1*32(%rdi), %ymm5
vmovdqu 2*32(%rdi), %ymm4
vmovdqu 3*32(%rdi), %ymm3
vmovdqu 4*32(%rdi), %ymm0
vmovdqu 5*32(%rdi), %ymm8
vmovdqu 6*32(%rdi), %ymm9
vmovdqu 7*32(%rdi), %ymm10
movq %rsp, %rax
leaq sha256_8k(%rip), %rcx
sha256_avx2_main_quadround 0
sha256_avx2_main_quadround 4
sha256_avx2_main_quadround 8
sha256_avx2_main_quadround 12
sha256_avx2_main_quadround 16
sha256_avx2_main_quadround 20
sha256_avx2_main_quadround 24
sha256_avx2_main_quadround 28
sha256_avx2_main_quadround 32
sha256_avx2_main_quadround 36
sha256_avx2_main_quadround 40
sha256_avx2_main_quadround 44
sha256_avx2_main_quadround 48
sha256_avx2_main_quadround 52
sha256_avx2_main_quadround 56
sha256_avx2_main_quadround 60
jmp sha256_transform_8way_finish
.macro p2bswap_avx2_rsi_rsp i
vmovdqu \i*32(%rsi), %ymm0
vmovdqu (\i+1)*32(%rsi), %ymm2
vpshuflw $0xb1, %ymm0, %ymm0
vpshuflw $0xb1, %ymm2, %ymm2
vpshufhw $0xb1, %ymm0, %ymm0
vpshufhw $0xb1, %ymm2, %ymm2
vpsrlw $8, %ymm0, %ymm1
vpsrlw $8, %ymm2, %ymm3
vpsllw $8, %ymm0, %ymm0
vpsllw $8, %ymm2, %ymm2
vpxor %ymm1, %ymm0, %ymm0
vpxor %ymm3, %ymm2, %ymm2
vmovdqa %ymm0, \i*32(%rsp)
vmovdqa %ymm2, (\i+1)*32(%rsp)
.endm
.text
.p2align 6
.globl sha256_transform_8way
.globl _sha256_transform_8way
sha256_transform_8way:
_sha256_transform_8way:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
subq $96, %rsp
vmovdqa %xmm6, 0(%rsp)
vmovdqa %xmm7, 16(%rsp)
vmovdqa %xmm8, 32(%rsp)
vmovdqa %xmm9, 48(%rsp)
vmovdqa %xmm10, 64(%rsp)
vmovdqa %xmm11, 80(%rsp)
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
#endif
movq %rsp, %r8
subq $64*32, %rsp
andq $-128, %rsp
testq %rdx, %rdx
jnz sha256_transform_8way_swap
vmovdqu 0*32(%rsi), %ymm0
vmovdqu 1*32(%rsi), %ymm1
vmovdqu 2*32(%rsi), %ymm2
vmovdqu 3*32(%rsi), %ymm3
vmovdqu 4*32(%rsi), %ymm4
vmovdqu 5*32(%rsi), %ymm5
vmovdqu 6*32(%rsi), %ymm6
vmovdqu 7*32(%rsi), %ymm7
vmovdqa %ymm0, 0*32(%rsp)
vmovdqa %ymm1, 1*32(%rsp)
vmovdqa %ymm2, 2*32(%rsp)
vmovdqa %ymm3, 3*32(%rsp)
vmovdqa %ymm4, 4*32(%rsp)
vmovdqa %ymm5, 5*32(%rsp)
vmovdqa %ymm6, 6*32(%rsp)
vmovdqa %ymm7, 7*32(%rsp)
vmovdqu 8*32(%rsi), %ymm0
vmovdqu 9*32(%rsi), %ymm1
vmovdqu 10*32(%rsi), %ymm2
vmovdqu 11*32(%rsi), %ymm3
vmovdqu 12*32(%rsi), %ymm4
vmovdqu 13*32(%rsi), %ymm5
vmovdqu 14*32(%rsi), %ymm6
vmovdqu 15*32(%rsi), %ymm7
vmovdqa %ymm0, 8*32(%rsp)
vmovdqa %ymm1, 9*32(%rsp)
vmovdqa %ymm2, 10*32(%rsp)
vmovdqa %ymm3, 11*32(%rsp)
vmovdqa %ymm4, 12*32(%rsp)
vmovdqa %ymm5, 13*32(%rsp)
vmovdqa %ymm6, 14*32(%rsp)
vmovdqa %ymm7, 15*32(%rsp)
jmp sha256_transform_8way_core_avx2
.p2align 6
sha256_transform_8way_swap:
p2bswap_avx2_rsi_rsp 0
p2bswap_avx2_rsi_rsp 2
p2bswap_avx2_rsi_rsp 4
p2bswap_avx2_rsi_rsp 6
p2bswap_avx2_rsi_rsp 8
p2bswap_avx2_rsi_rsp 10
p2bswap_avx2_rsi_rsp 12
p2bswap_avx2_rsi_rsp 14
jmp sha256_transform_8way_core_avx2
.p2align 6
sha256_transform_8way_finish:
vmovdqu 0*32(%rdi), %ymm2
vmovdqu 1*32(%rdi), %ymm6
vmovdqu 2*32(%rdi), %ymm11
vmovdqu 3*32(%rdi), %ymm1
vpaddd %ymm2, %ymm7, %ymm7
vpaddd %ymm6, %ymm5, %ymm5
vpaddd %ymm11, %ymm4, %ymm4
vpaddd %ymm1, %ymm3, %ymm3
vmovdqu 4*32(%rdi), %ymm2
vmovdqu 5*32(%rdi), %ymm6
vmovdqu 6*32(%rdi), %ymm11
vmovdqu 7*32(%rdi), %ymm1
vpaddd %ymm2, %ymm0, %ymm0
vpaddd %ymm6, %ymm8, %ymm8
vpaddd %ymm11, %ymm9, %ymm9
vpaddd %ymm1, %ymm10, %ymm10
vmovdqu %ymm7, 0*32(%rdi)
vmovdqu %ymm5, 1*32(%rdi)
vmovdqu %ymm4, 2*32(%rdi)
vmovdqu %ymm3, 3*32(%rdi)
vmovdqu %ymm0, 4*32(%rdi)
vmovdqu %ymm8, 5*32(%rdi)
vmovdqu %ymm9, 6*32(%rdi)
vmovdqu %ymm10, 7*32(%rdi)
movq %r8, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
vmovdqa 0(%rsp), %xmm6
vmovdqa 16(%rsp), %xmm7
vmovdqa 32(%rsp), %xmm8
vmovdqa 48(%rsp), %xmm9
vmovdqa 64(%rsp), %xmm10
vmovdqa 80(%rsp), %xmm11
addq $96, %rsp
popq %rdi
#endif
ret
#endif /* USE_AVX2 */
.data
.p2align 3
sha256d_ms_4way_addr:
.quad 0x0
.text
.p2align 6
.globl sha256d_ms_4way
.globl _sha256d_ms_4way
sha256d_ms_4way:
_sha256d_ms_4way:
jmp *sha256d_ms_4way_addr(%rip)
.p2align 6
sha256d_ms_4way_sse2:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
subq $32, %rsp
movdqa %xmm6, 0(%rsp)
movdqa %xmm7, 16(%rsp)
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
movq %r9, %rcx
#endif
subq $8+67*16, %rsp
leaq 256(%rsi), %rax
sha256d_ms_4way_sse2_extend_loop1:
movdqa 3*16(%rsi), %xmm0
movdqa 2*16(%rax), %xmm3
movdqa 3*16(%rax), %xmm7
movdqa %xmm3, 5*16(%rsp)
movdqa %xmm7, 6*16(%rsp)
movdqa %xmm0, %xmm2
paddd %xmm0, %xmm7
psrld $3, %xmm0
movdqa %xmm0, %xmm1
pslld $14, %xmm2
psrld $4, %xmm1
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
psrld $11, %xmm1
pslld $11, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
paddd %xmm0, %xmm3
movdqa %xmm3, 2*16(%rax)
movdqa %xmm7, 3*16(%rax)
movdqa 4*16(%rax), %xmm0
movdqa %xmm0, 7*16(%rsp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
movdqa %xmm3, 4*16(%rax)
movdqa %xmm7, 5*16(%rax)
movdqa 6*16(%rax), %xmm0
movdqa 7*16(%rax), %xmm4
movdqa %xmm0, 9*16(%rsp)
movdqa %xmm4, 10*16(%rsp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 6*16(%rax)
movdqa %xmm7, 7*16(%rax)
movdqa 8*16(%rax), %xmm0
movdqa 2*16(%rax), %xmm4
movdqa %xmm0, 11*16(%rsp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 8*16(%rax)
movdqa %xmm7, 9*16(%rax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 3*16(%rax), %xmm3
paddd 4*16(%rax), %xmm7
movdqa %xmm3, 10*16(%rax)
movdqa %xmm7, 11*16(%rax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 5*16(%rax), %xmm3
paddd 6*16(%rax), %xmm7
movdqa %xmm3, 12*16(%rax)
movdqa %xmm7, 13*16(%rax)
movdqa 14*16(%rax), %xmm0
movdqa 15*16(%rax), %xmm4
movdqa %xmm0, 17*16(%rsp)
movdqa %xmm4, 18*16(%rsp)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd 7*16(%rax), %xmm0
paddd 8*16(%rax), %xmm4
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 14*16(%rax)
movdqa %xmm7, 15*16(%rax)
sha256d_ms_4way_sse2_extend_loop2:
sha256_sse2_extend_doubleround 16
sha256_sse2_extend_doubleround 18
sha256_sse2_extend_doubleround 20
sha256_sse2_extend_doubleround 22
sha256_sse2_extend_doubleround 24
sha256_sse2_extend_doubleround 26
sha256_sse2_extend_doubleround 28
sha256_sse2_extend_doubleround 30
sha256_sse2_extend_doubleround 32
sha256_sse2_extend_doubleround 34
sha256_sse2_extend_doubleround 36
sha256_sse2_extend_doubleround 38
sha256_sse2_extend_doubleround 40
sha256_sse2_extend_doubleround 42
jz sha256d_ms_4way_sse2_extend_coda2
sha256_sse2_extend_doubleround 44
sha256_sse2_extend_doubleround 46
movdqa 0(%rcx), %xmm3
movdqa 16(%rcx), %xmm0
movdqa 32(%rcx), %xmm1
movdqa 48(%rcx), %xmm2
movdqa 64(%rcx), %xmm6
movdqa 80(%rcx), %xmm7
movdqa 96(%rcx), %xmm5
movdqa 112(%rcx), %xmm4
movdqa %xmm1, 0(%rsp)
movdqa %xmm2, 16(%rsp)
movdqa %xmm6, 32(%rsp)
movq %rsi, %rax
leaq sha256_4k(%rip), %rcx
jmp sha256d_ms_4way_sse2_main_loop1
sha256d_ms_4way_sse2_main_loop2:
sha256_sse2_main_round 0
sha256_sse2_main_round 1
sha256_sse2_main_round 2
sha256d_ms_4way_sse2_main_loop1:
sha256_sse2_main_round 3
sha256_sse2_main_quadround 4
sha256_sse2_main_quadround 8
sha256_sse2_main_quadround 12
sha256_sse2_main_quadround 16
sha256_sse2_main_quadround 20
sha256_sse2_main_quadround 24
sha256_sse2_main_quadround 28
sha256_sse2_main_quadround 32
sha256_sse2_main_quadround 36
sha256_sse2_main_quadround 40
sha256_sse2_main_quadround 44
sha256_sse2_main_quadround 48
sha256_sse2_main_quadround 52
sha256_sse2_main_round 56
jz sha256d_ms_4way_sse2_finish
sha256_sse2_main_round 57
sha256_sse2_main_round 58
sha256_sse2_main_round 59
sha256_sse2_main_quadround 60
movdqa 5*16(%rsp), %xmm1
movdqa 6*16(%rsp), %xmm2
movdqa 7*16(%rsp), %xmm6
movdqa %xmm1, 18*16(%rsi)
movdqa %xmm2, 19*16(%rsi)
movdqa %xmm6, 20*16(%rsi)
movdqa 9*16(%rsp), %xmm1
movdqa 10*16(%rsp), %xmm2
movdqa 11*16(%rsp), %xmm6
movdqa %xmm1, 22*16(%rsi)
movdqa %xmm2, 23*16(%rsi)
movdqa %xmm6, 24*16(%rsi)
movdqa 17*16(%rsp), %xmm1
movdqa 18*16(%rsp), %xmm2
movdqa %xmm1, 30*16(%rsi)
movdqa %xmm2, 31*16(%rsi)
movdqa 0(%rsp), %xmm1
movdqa 16(%rsp), %xmm2
movdqa 32(%rsp), %xmm6
paddd 0(%rdx), %xmm7
paddd 16(%rdx), %xmm5
paddd 32(%rdx), %xmm4
paddd 48(%rdx), %xmm3
paddd 64(%rdx), %xmm0
paddd 80(%rdx), %xmm1
paddd 96(%rdx), %xmm2
paddd 112(%rdx), %xmm6
movdqa %xmm7, 48+0(%rsp)
movdqa %xmm5, 48+16(%rsp)
movdqa %xmm4, 48+32(%rsp)
movdqa %xmm3, 48+48(%rsp)
movdqa %xmm0, 48+64(%rsp)
movdqa %xmm1, 48+80(%rsp)
movdqa %xmm2, 48+96(%rsp)
movdqa %xmm6, 48+112(%rsp)
pxor %xmm0, %xmm0
movq $0x8000000000000100, %rax
movd %rax, %xmm1
pshufd $0x55, %xmm1, %xmm2
pshufd $0x00, %xmm1, %xmm1
movdqa %xmm2, 48+128(%rsp)
movdqa %xmm0, 48+144(%rsp)
movdqa %xmm0, 48+160(%rsp)
movdqa %xmm0, 48+176(%rsp)
movdqa %xmm0, 48+192(%rsp)
movdqa %xmm0, 48+208(%rsp)
movdqa %xmm0, 48+224(%rsp)
movdqa %xmm1, 48+240(%rsp)
leaq 19*16(%rsp), %rax
cmpq %rax, %rax
movdqa -15*16(%rax), %xmm0
movdqa -14*16(%rax), %xmm4
movdqa %xmm0, %xmm2
movdqa %xmm4, %xmm6
psrld $3, %xmm0
psrld $3, %xmm4
movdqa %xmm0, %xmm1
movdqa %xmm4, %xmm5
pslld $14, %xmm2
pslld $14, %xmm6
psrld $4, %xmm1
psrld $4, %xmm5
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
psrld $11, %xmm1
psrld $11, %xmm5
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
pslld $11, %xmm2
pslld $11, %xmm6
pxor %xmm1, %xmm0
pxor %xmm5, %xmm4
pxor %xmm2, %xmm0
pxor %xmm6, %xmm4
paddd -16*16(%rax), %xmm0
paddd -15*16(%rax), %xmm4
paddd sha256d_4preext2_17(%rip), %xmm4
movdqa %xmm0, %xmm3
movdqa %xmm4, %xmm7
movdqa %xmm3, 0*16(%rax)
movdqa %xmm7, 1*16(%rax)
sha256_sse2_extend_doubleround 2
sha256_sse2_extend_doubleround 4
movdqa -9*16(%rax), %xmm0
movdqa sha256d_4preext2_23(%rip), %xmm4
movdqa %xmm0, %xmm2
psrld $3, %xmm0
movdqa %xmm0, %xmm1
pslld $14, %xmm2
psrld $4, %xmm1
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
psrld $11, %xmm1
pslld $11, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
paddd -10*16(%rax), %xmm0
paddd -9*16(%rax), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd -1*16(%rax), %xmm0
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd 0*16(%rax), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 6*16(%rax)
movdqa %xmm7, 7*16(%rax)
movdqa sha256d_4preext2_24(%rip), %xmm0
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd 1*16(%rax), %xmm0
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd 2*16(%rax), %xmm7
movdqa %xmm3, 8*16(%rax)
movdqa %xmm7, 9*16(%rax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 3*16(%rax), %xmm3
paddd 4*16(%rax), %xmm7
movdqa %xmm3, 10*16(%rax)
movdqa %xmm7, 11*16(%rax)
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd 5*16(%rax), %xmm3
paddd 6*16(%rax), %xmm7
movdqa %xmm3, 12*16(%rax)
movdqa %xmm7, 13*16(%rax)
movdqa sha256d_4preext2_30(%rip), %xmm0
movdqa 0*16(%rax), %xmm4
movdqa %xmm4, %xmm6
psrld $3, %xmm4
movdqa %xmm4, %xmm5
pslld $14, %xmm6
psrld $4, %xmm5
pxor %xmm5, %xmm4
pxor %xmm6, %xmm4
psrld $11, %xmm5
pslld $11, %xmm6
pxor %xmm5, %xmm4
pxor %xmm6, %xmm4
paddd -1*16(%rax), %xmm4
movdqa %xmm3, %xmm2
movdqa %xmm7, %xmm6
psrld $10, %xmm3
psrld $10, %xmm7
movdqa %xmm3, %xmm1
movdqa %xmm7, %xmm5
paddd 7*16(%rax), %xmm0
pslld $13, %xmm2
pslld $13, %xmm6
psrld $7, %xmm1
psrld $7, %xmm5
paddd 8*16(%rax), %xmm4
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
psrld $2, %xmm1
psrld $2, %xmm5
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
pslld $2, %xmm2
pslld $2, %xmm6
pxor %xmm1, %xmm3
pxor %xmm5, %xmm7
pxor %xmm2, %xmm3
pxor %xmm6, %xmm7
paddd %xmm0, %xmm3
paddd %xmm4, %xmm7
movdqa %xmm3, 14*16(%rax)
movdqa %xmm7, 15*16(%rax)
jmp sha256d_ms_4way_sse2_extend_loop2
sha256d_ms_4way_sse2_extend_coda2:
sha256_sse2_extend_round 44
movdqa sha256_4h+0(%rip), %xmm7
movdqa sha256_4h+16(%rip), %xmm5
movdqa sha256_4h+32(%rip), %xmm4
movdqa sha256_4h+48(%rip), %xmm3
movdqa sha256_4h+64(%rip), %xmm0
movdqa sha256_4h+80(%rip), %xmm1
movdqa sha256_4h+96(%rip), %xmm2
movdqa sha256_4h+112(%rip), %xmm6
movdqa %xmm1, 0(%rsp)
movdqa %xmm2, 16(%rsp)
movdqa %xmm6, 32(%rsp)
leaq 48(%rsp), %rax
leaq sha256_4k(%rip), %rcx
jmp sha256d_ms_4way_sse2_main_loop2
.macro sha256_sse2_main_round_red i, r7
movdqa 16*\i(%rax), %xmm6
paddd 16*\i(%rcx), %xmm6
paddd 32(%rsp), %xmm6
movdqa %xmm0, %xmm1
movdqa 16(%rsp), %xmm2
paddd \r7, %xmm6
pandn %xmm2, %xmm1
movdqa %xmm2, 32(%rsp)
movdqa 0(%rsp), %xmm2
movdqa %xmm2, 16(%rsp)
pand %xmm0, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm0, 0(%rsp)
paddd %xmm1, %xmm6
movdqa %xmm0, %xmm1
psrld $6, %xmm0
movdqa %xmm0, %xmm2
pslld $7, %xmm1
psrld $5, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $14, %xmm1
psrld $14, %xmm2
pxor %xmm1, %xmm0
pxor %xmm2, %xmm0
pslld $5, %xmm1
pxor %xmm1, %xmm0
paddd %xmm6, %xmm0
.endm
sha256d_ms_4way_sse2_finish:
sha256_sse2_main_round_red 57, %xmm3
sha256_sse2_main_round_red 58, %xmm4
sha256_sse2_main_round_red 59, %xmm5
sha256_sse2_main_round_red 60, %xmm7
paddd sha256_4h+112(%rip), %xmm0
movdqa %xmm0, 112(%rdi)
addq $8+67*16, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
movdqa 0(%rsp), %xmm6
movdqa 16(%rsp), %xmm7
addq $32, %rsp
popq %rdi
#endif
ret
#if defined(USE_AVX)
.p2align 6
sha256d_ms_4way_avx:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
subq $80, %rsp
movdqa %xmm6, 0(%rsp)
movdqa %xmm7, 16(%rsp)
movdqa %xmm8, 32(%rsp)
movdqa %xmm9, 48(%rsp)
movdqa %xmm10, 64(%rsp)
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
movq %r9, %rcx
#endif
subq $1032, %rsp
leaq 256(%rsi), %rax
sha256d_ms_4way_avx_extend_loop1:
vmovdqa 3*16(%rsi), %xmm0
vmovdqa 2*16(%rax), %xmm3
vmovdqa 3*16(%rax), %xmm7
vmovdqa %xmm3, 2*16(%rsp)
vmovdqa %xmm7, 3*16(%rsp)
vpaddd %xmm0, %xmm7, %xmm7
vpslld $14, %xmm0, %xmm2
vpsrld $3, %xmm0, %xmm0
vpsrld $4, %xmm0, %xmm1
vpxor %xmm1, %xmm0, %xmm0
vpxor %xmm2, %xmm0, %xmm0
vpsrld $11, %xmm1, %xmm1
vpslld $11, %xmm2, %xmm2
vpxor %xmm1, %xmm0, %xmm0
vpxor %xmm2, %xmm0, %xmm0
vpaddd %xmm0, %xmm3, %xmm3
vmovdqa %xmm3, 2*16(%rax)
vmovdqa %xmm7, 3*16(%rax)
vmovdqa 4*16(%rax), %xmm0
vmovdqa %xmm0, 4*16(%rsp)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vmovdqa %xmm3, 4*16(%rax)
vmovdqa %xmm7, 5*16(%rax)
vmovdqa 6*16(%rax), %xmm0
vmovdqa 7*16(%rax), %xmm4
vmovdqa %xmm0, 6*16(%rsp)
vmovdqa %xmm4, 7*16(%rsp)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 6*16(%rax)
vmovdqa %xmm7, 7*16(%rax)
vmovdqa 8*16(%rax), %xmm0
vmovdqa 2*16(%rax), %xmm4
vmovdqa %xmm0, 8*16(%rsp)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 8*16(%rax)
vmovdqa %xmm7, 9*16(%rax)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 3*16(%rax), %xmm3, %xmm3
vpaddd 4*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 10*16(%rax)
vmovdqa %xmm7, 11*16(%rax)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 5*16(%rax), %xmm3, %xmm3
vpaddd 6*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 12*16(%rax)
vmovdqa %xmm7, 13*16(%rax)
vmovdqa 14*16(%rax), %xmm0
vmovdqa 15*16(%rax), %xmm4
vmovdqa %xmm0, 14*16(%rsp)
vmovdqa %xmm4, 15*16(%rsp)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpaddd 7*16(%rax), %xmm0, %xmm0
vpaddd 8*16(%rax), %xmm4, %xmm4
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 14*16(%rax)
vmovdqa %xmm7, 15*16(%rax)
sha256d_ms_4way_avx_extend_loop2:
sha256_avx_extend_doubleround 16
sha256_avx_extend_doubleround 18
sha256_avx_extend_doubleround 20
sha256_avx_extend_doubleround 22
sha256_avx_extend_doubleround 24
sha256_avx_extend_doubleround 26
sha256_avx_extend_doubleround 28
sha256_avx_extend_doubleround 30
sha256_avx_extend_doubleround 32
sha256_avx_extend_doubleround 34
sha256_avx_extend_doubleround 36
sha256_avx_extend_doubleround 38
sha256_avx_extend_doubleround 40
sha256_avx_extend_doubleround 42
jz sha256d_ms_4way_avx_extend_coda2
sha256_avx_extend_doubleround 44
sha256_avx_extend_doubleround 46
movdqa 0(%rcx), %xmm7
movdqa 16(%rcx), %xmm8
movdqa 32(%rcx), %xmm9
movdqa 48(%rcx), %xmm10
movdqa 64(%rcx), %xmm0
movdqa 80(%rcx), %xmm5
movdqa 96(%rcx), %xmm4
movdqa 112(%rcx), %xmm3
movq %rsi, %rax
leaq sha256_4k(%rip), %rcx
jmp sha256d_ms_4way_avx_main_loop1
sha256d_ms_4way_avx_main_loop2:
sha256_avx_main_round 0, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3, %xmm4, %xmm5, %xmm7
sha256_avx_main_round 1, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4, %xmm5, %xmm7, %xmm3
sha256_avx_main_round 2, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5, %xmm7, %xmm3, %xmm4
sha256d_ms_4way_avx_main_loop1:
sha256_avx_main_round 3, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7, %xmm3, %xmm4, %xmm5
sha256_avx_main_quadround 4
sha256_avx_main_quadround 8
sha256_avx_main_quadround 12
sha256_avx_main_quadround 16
sha256_avx_main_quadround 20
sha256_avx_main_quadround 24
sha256_avx_main_quadround 28
sha256_avx_main_quadround 32
sha256_avx_main_quadround 36
sha256_avx_main_quadround 40
sha256_avx_main_quadround 44
sha256_avx_main_quadround 48
sha256_avx_main_quadround 52
sha256_avx_main_round 56, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3, %xmm4, %xmm5, %xmm7
jz sha256d_ms_4way_avx_finish
sha256_avx_main_round 57, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4, %xmm5, %xmm7, %xmm3
sha256_avx_main_round 58, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5, %xmm7, %xmm3, %xmm4
sha256_avx_main_round 59, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7, %xmm3, %xmm4, %xmm5
sha256_avx_main_quadround 60
movdqa 2*16(%rsp), %xmm1
movdqa 3*16(%rsp), %xmm2
movdqa 4*16(%rsp), %xmm6
movdqa %xmm1, 18*16(%rsi)
movdqa %xmm2, 19*16(%rsi)
movdqa %xmm6, 20*16(%rsi)
movdqa 6*16(%rsp), %xmm1
movdqa 7*16(%rsp), %xmm2
movdqa 8*16(%rsp), %xmm6
movdqa %xmm1, 22*16(%rsi)
movdqa %xmm2, 23*16(%rsi)
movdqa %xmm6, 24*16(%rsi)
movdqa 14*16(%rsp), %xmm1
movdqa 15*16(%rsp), %xmm2
movdqa %xmm1, 30*16(%rsi)
movdqa %xmm2, 31*16(%rsi)
paddd 0(%rdx), %xmm7
paddd 16(%rdx), %xmm5
paddd 32(%rdx), %xmm4
paddd 48(%rdx), %xmm3
paddd 64(%rdx), %xmm0
paddd 80(%rdx), %xmm8
paddd 96(%rdx), %xmm9
paddd 112(%rdx), %xmm10
movdqa %xmm7, 0(%rsp)
movdqa %xmm5, 16(%rsp)
movdqa %xmm4, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm0, 64(%rsp)
movdqa %xmm8, 80(%rsp)
movdqa %xmm9, 96(%rsp)
movdqa %xmm10, 112(%rsp)
pxor %xmm0, %xmm0
movq $0x8000000000000100, %rax
movd %rax, %xmm1
pshufd $0x55, %xmm1, %xmm2
pshufd $0x00, %xmm1, %xmm1
movdqa %xmm2, 128(%rsp)
movdqa %xmm0, 144(%rsp)
movdqa %xmm0, 160(%rsp)
movdqa %xmm0, 176(%rsp)
movdqa %xmm0, 192(%rsp)
movdqa %xmm0, 208(%rsp)
movdqa %xmm0, 224(%rsp)
movdqa %xmm1, 240(%rsp)
leaq 256(%rsp), %rax
cmpq %rax, %rax
vmovdqa -15*16(%rax), %xmm0
vmovdqa -14*16(%rax), %xmm4
vpslld $14, %xmm0, %xmm2
vpslld $14, %xmm4, %xmm6
vpsrld $3, %xmm0, %xmm8
vpsrld $3, %xmm4, %xmm4
vpsrld $7, %xmm0, %xmm1
vpsrld $4, %xmm4, %xmm5
vpxor %xmm1, %xmm8, %xmm8
vpxor %xmm5, %xmm4, %xmm4
vpsrld $11, %xmm1, %xmm1
vpsrld $11, %xmm5, %xmm5
vpxor %xmm2, %xmm8, %xmm8
vpxor %xmm6, %xmm4, %xmm4
vpslld $11, %xmm2, %xmm2
vpslld $11, %xmm6, %xmm6
vpxor %xmm1, %xmm8, %xmm8
vpxor %xmm5, %xmm4, %xmm4
vpxor %xmm2, %xmm8, %xmm8
vpxor %xmm6, %xmm4, %xmm4
vpaddd %xmm0, %xmm4, %xmm4
vpaddd -16*16(%rax), %xmm8, %xmm3
vpaddd sha256d_4preext2_17(%rip), %xmm4, %xmm7
vmovdqa %xmm3, 0*16(%rax)
vmovdqa %xmm7, 1*16(%rax)
sha256_avx_extend_doubleround 2
sha256_avx_extend_doubleround 4
vmovdqa -9*16(%rax), %xmm0
vpslld $14, %xmm0, %xmm2
vpsrld $3, %xmm0, %xmm8
vpsrld $7, %xmm0, %xmm1
vpxor %xmm1, %xmm8, %xmm8
vpxor %xmm2, %xmm8, %xmm8
vpsrld $11, %xmm1, %xmm1
vpslld $11, %xmm2, %xmm2
vpxor %xmm1, %xmm8, %xmm8
vpxor %xmm2, %xmm8, %xmm8
vpaddd sha256d_4preext2_23(%rip), %xmm0, %xmm4
vpaddd -10*16(%rax), %xmm8, %xmm0
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpaddd -1*16(%rax), %xmm0, %xmm0
vpaddd 0*16(%rax), %xmm4, %xmm4
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 6*16(%rax)
vmovdqa %xmm7, 7*16(%rax)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd sha256d_4preext2_24(%rip), %xmm3, %xmm3
vpaddd 1*16(%rax), %xmm3, %xmm3
vpaddd 2*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 8*16(%rax)
vmovdqa %xmm7, 9*16(%rax)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 3*16(%rax), %xmm3, %xmm3
vpaddd 4*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 10*16(%rax)
vmovdqa %xmm7, 11*16(%rax)
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 5*16(%rax), %xmm3, %xmm3
vpaddd 6*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 12*16(%rax)
vmovdqa %xmm7, 13*16(%rax)
vmovdqa sha256d_4preext2_30(%rip), %xmm0
vmovdqa 0*16(%rax), %xmm4
vpslld $14, %xmm4, %xmm6
vpsrld $3, %xmm4, %xmm4
vpsrld $4, %xmm4, %xmm5
vpxor %xmm5, %xmm4, %xmm4
vpxor %xmm6, %xmm4, %xmm4
vpsrld $11, %xmm5, %xmm5
vpslld $11, %xmm6, %xmm6
vpxor %xmm5, %xmm4, %xmm4
vpxor %xmm6, %xmm4, %xmm4
vpaddd -1*16(%rax), %xmm4, %xmm4
vpslld $13, %xmm3, %xmm2
vpslld $13, %xmm7, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpaddd 7*16(%rax), %xmm0, %xmm0
vpaddd 8*16(%rax), %xmm4, %xmm4
vpsrld $7, %xmm3, %xmm1
vpsrld $7, %xmm7, %xmm5
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpsrld $2, %xmm1, %xmm1
vpsrld $2, %xmm5, %xmm5
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpslld $2, %xmm2, %xmm2
vpslld $2, %xmm6, %xmm6
vpxor %xmm1, %xmm3, %xmm3
vpxor %xmm5, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 14*16(%rax)
vmovdqa %xmm7, 15*16(%rax)
jmp sha256d_ms_4way_avx_extend_loop2
sha256d_ms_4way_avx_extend_coda2:
sha256_avx_extend_round 44
movdqa sha256_4h+0(%rip), %xmm7
movdqa sha256_4h+16(%rip), %xmm5
movdqa sha256_4h+32(%rip), %xmm4
movdqa sha256_4h+48(%rip), %xmm3
movdqa sha256_4h+64(%rip), %xmm0
movdqa sha256_4h+80(%rip), %xmm8
movdqa sha256_4h+96(%rip), %xmm9
movdqa sha256_4h+112(%rip), %xmm10
movq %rsp, %rax
leaq sha256_4k(%rip), %rcx
jmp sha256d_ms_4way_avx_main_loop2
.macro sha256_avx_main_round_red i, r0, r1, r2, r3, r4
vpaddd 16*\i(%rax), \r0, %xmm6
vpaddd 16*\i(%rcx), %xmm6, %xmm6
vpandn \r1, \r3, %xmm1
vpand \r3, \r2, %xmm2
vpxor %xmm2, %xmm1, %xmm1
vpaddd %xmm1, %xmm6, %xmm6
vpslld $7, \r3, %xmm1
vpsrld $6, \r3, \r0
vpsrld $5, \r0, %xmm2
vpxor %xmm1, \r0, \r0
vpxor %xmm2, \r0, \r0
vpslld $14, %xmm1, %xmm1
vpsrld $14, %xmm2, %xmm2
vpxor %xmm1, \r0, \r0
vpxor %xmm2, \r0, \r0
vpslld $5, %xmm1, %xmm1
vpxor %xmm1, \r0, \r0
vpaddd \r0, %xmm6, %xmm6
vpaddd %xmm6, \r4, \r0
.endm
sha256d_ms_4way_avx_finish:
sha256_avx_main_round_red 57, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4
sha256_avx_main_round_red 58, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5
sha256_avx_main_round_red 59, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7
sha256_avx_main_round_red 60, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3
paddd sha256_4h+112(%rip), %xmm10
movdqa %xmm10, 112(%rdi)
addq $1032, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
movdqa 0(%rsp), %xmm6
movdqa 16(%rsp), %xmm7
movdqa 32(%rsp), %xmm8
movdqa 48(%rsp), %xmm9
movdqa 64(%rsp), %xmm10
addq $80, %rsp
popq %rdi
#endif
ret
#endif /* USE_AVX */
#if defined(USE_XOP)
.p2align 6
sha256d_ms_4way_xop:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
subq $80, %rsp
movdqa %xmm6, 0(%rsp)
movdqa %xmm7, 16(%rsp)
movdqa %xmm8, 32(%rsp)
movdqa %xmm9, 48(%rsp)
movdqa %xmm10, 64(%rsp)
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
movq %r9, %rcx
#endif
subq $1032, %rsp
leaq 256(%rsi), %rax
sha256d_ms_4way_xop_extend_loop1:
vmovdqa 3*16(%rsi), %xmm0
vmovdqa 2*16(%rax), %xmm3
vmovdqa 3*16(%rax), %xmm7
vmovdqa %xmm3, 2*16(%rsp)
vmovdqa %xmm7, 3*16(%rsp)
vpaddd %xmm0, %xmm7, %xmm7
vprotd $25, %xmm0, %xmm1
vprotd $14, %xmm0, %xmm2
vpsrld $3, %xmm0, %xmm0
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm2, %xmm0, %xmm0
vpaddd %xmm0, %xmm3, %xmm3
vmovdqa %xmm3, 2*16(%rax)
vmovdqa %xmm7, 3*16(%rax)
vmovdqa 4*16(%rax), %xmm0
vmovdqa %xmm0, 4*16(%rsp)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vmovdqa %xmm3, 4*16(%rax)
vmovdqa %xmm7, 5*16(%rax)
vmovdqa 6*16(%rax), %xmm0
vmovdqa 7*16(%rax), %xmm4
vmovdqa %xmm0, 6*16(%rsp)
vmovdqa %xmm4, 7*16(%rsp)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 6*16(%rax)
vmovdqa %xmm7, 7*16(%rax)
vmovdqa 8*16(%rax), %xmm0
vmovdqa 2*16(%rax), %xmm4
vmovdqa %xmm0, 8*16(%rsp)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 8*16(%rax)
vmovdqa %xmm7, 9*16(%rax)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 3*16(%rax), %xmm3, %xmm3
vpaddd 4*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 10*16(%rax)
vmovdqa %xmm7, 11*16(%rax)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 5*16(%rax), %xmm3, %xmm3
vpaddd 6*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 12*16(%rax)
vmovdqa %xmm7, 13*16(%rax)
vmovdqa 14*16(%rax), %xmm0
vmovdqa 15*16(%rax), %xmm4
vmovdqa %xmm0, 14*16(%rsp)
vmovdqa %xmm4, 15*16(%rsp)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpaddd 7*16(%rax), %xmm0, %xmm0
vpaddd 8*16(%rax), %xmm4, %xmm4
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 14*16(%rax)
vmovdqa %xmm7, 15*16(%rax)
sha256d_ms_4way_xop_extend_loop2:
sha256_xop_extend_doubleround 16
sha256_xop_extend_doubleround 18
sha256_xop_extend_doubleround 20
sha256_xop_extend_doubleround 22
sha256_xop_extend_doubleround 24
sha256_xop_extend_doubleround 26
sha256_xop_extend_doubleround 28
sha256_xop_extend_doubleround 30
sha256_xop_extend_doubleround 32
sha256_xop_extend_doubleround 34
sha256_xop_extend_doubleround 36
sha256_xop_extend_doubleround 38
sha256_xop_extend_doubleround 40
sha256_xop_extend_doubleround 42
jz sha256d_ms_4way_xop_extend_coda2
sha256_xop_extend_doubleround 44
sha256_xop_extend_doubleround 46
movdqa 0(%rcx), %xmm7
movdqa 16(%rcx), %xmm8
movdqa 32(%rcx), %xmm9
movdqa 48(%rcx), %xmm10
movdqa 64(%rcx), %xmm0
movdqa 80(%rcx), %xmm5
movdqa 96(%rcx), %xmm4
movdqa 112(%rcx), %xmm3
movq %rsi, %rax
leaq sha256_4k(%rip), %rcx
jmp sha256d_ms_4way_xop_main_loop1
sha256d_ms_4way_xop_main_loop2:
sha256_xop_main_round 0, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3, %xmm4, %xmm5, %xmm7
sha256_xop_main_round 1, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4, %xmm5, %xmm7, %xmm3
sha256_xop_main_round 2, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5, %xmm7, %xmm3, %xmm4
sha256d_ms_4way_xop_main_loop1:
sha256_xop_main_round 3, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7, %xmm3, %xmm4, %xmm5
sha256_xop_main_quadround 4
sha256_xop_main_quadround 8
sha256_xop_main_quadround 12
sha256_xop_main_quadround 16
sha256_xop_main_quadround 20
sha256_xop_main_quadround 24
sha256_xop_main_quadround 28
sha256_xop_main_quadround 32
sha256_xop_main_quadround 36
sha256_xop_main_quadround 40
sha256_xop_main_quadround 44
sha256_xop_main_quadround 48
sha256_xop_main_quadround 52
sha256_xop_main_round 56, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3, %xmm4, %xmm5, %xmm7
jz sha256d_ms_4way_xop_finish
sha256_xop_main_round 57, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4, %xmm5, %xmm7, %xmm3
sha256_xop_main_round 58, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5, %xmm7, %xmm3, %xmm4
sha256_xop_main_round 59, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7, %xmm3, %xmm4, %xmm5
sha256_xop_main_quadround 60
movdqa 2*16(%rsp), %xmm1
movdqa 3*16(%rsp), %xmm2
movdqa 4*16(%rsp), %xmm6
movdqa %xmm1, 18*16(%rsi)
movdqa %xmm2, 19*16(%rsi)
movdqa %xmm6, 20*16(%rsi)
movdqa 6*16(%rsp), %xmm1
movdqa 7*16(%rsp), %xmm2
movdqa 8*16(%rsp), %xmm6
movdqa %xmm1, 22*16(%rsi)
movdqa %xmm2, 23*16(%rsi)
movdqa %xmm6, 24*16(%rsi)
movdqa 14*16(%rsp), %xmm1
movdqa 15*16(%rsp), %xmm2
movdqa %xmm1, 30*16(%rsi)
movdqa %xmm2, 31*16(%rsi)
paddd 0(%rdx), %xmm7
paddd 16(%rdx), %xmm5
paddd 32(%rdx), %xmm4
paddd 48(%rdx), %xmm3
paddd 64(%rdx), %xmm0
paddd 80(%rdx), %xmm8
paddd 96(%rdx), %xmm9
paddd 112(%rdx), %xmm10
movdqa %xmm7, 0(%rsp)
movdqa %xmm5, 16(%rsp)
movdqa %xmm4, 32(%rsp)
movdqa %xmm3, 48(%rsp)
movdqa %xmm0, 64(%rsp)
movdqa %xmm8, 80(%rsp)
movdqa %xmm9, 96(%rsp)
movdqa %xmm10, 112(%rsp)
pxor %xmm0, %xmm0
movq $0x8000000000000100, %rax
movd %rax, %xmm1
pshufd $0x55, %xmm1, %xmm2
pshufd $0x00, %xmm1, %xmm1
movdqa %xmm2, 128(%rsp)
movdqa %xmm0, 144(%rsp)
movdqa %xmm0, 160(%rsp)
movdqa %xmm0, 176(%rsp)
movdqa %xmm0, 192(%rsp)
movdqa %xmm0, 208(%rsp)
movdqa %xmm0, 224(%rsp)
movdqa %xmm1, 240(%rsp)
leaq 256(%rsp), %rax
cmpq %rax, %rax
vmovdqa -15*16(%rax), %xmm0
vmovdqa -14*16(%rax), %xmm4
vprotd $25, %xmm0, %xmm1
vprotd $25, %xmm4, %xmm5
vprotd $14, %xmm0, %xmm2
vprotd $14, %xmm4, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $3, %xmm0, %xmm8
vpsrld $3, %xmm4, %xmm4
vpxor %xmm2, %xmm8, %xmm8
vpxor %xmm6, %xmm4, %xmm4
vpaddd %xmm0, %xmm4, %xmm4
vpaddd -16*16(%rax), %xmm8, %xmm3
vpaddd sha256d_4preext2_17(%rip), %xmm4, %xmm7
vmovdqa %xmm3, 0*16(%rax)
vmovdqa %xmm7, 1*16(%rax)
sha256_xop_extend_doubleround 2
sha256_xop_extend_doubleround 4
vmovdqa -9*16(%rax), %xmm0
vprotd $25, %xmm0, %xmm1
vprotd $14, %xmm0, %xmm2
vpsrld $3, %xmm0, %xmm8
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm2, %xmm8, %xmm8
vpaddd sha256d_4preext2_23(%rip), %xmm0, %xmm4
vpaddd -10*16(%rax), %xmm8, %xmm0
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpaddd -1*16(%rax), %xmm0, %xmm0
vpaddd 0*16(%rax), %xmm4, %xmm4
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 6*16(%rax)
vmovdqa %xmm7, 7*16(%rax)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd sha256d_4preext2_24(%rip), %xmm3, %xmm3
vpaddd 1*16(%rax), %xmm3, %xmm3
vpaddd 2*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 8*16(%rax)
vmovdqa %xmm7, 9*16(%rax)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 3*16(%rax), %xmm3, %xmm3
vpaddd 4*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 10*16(%rax)
vmovdqa %xmm7, 11*16(%rax)
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd 5*16(%rax), %xmm3, %xmm3
vpaddd 6*16(%rax), %xmm7, %xmm7
vmovdqa %xmm3, 12*16(%rax)
vmovdqa %xmm7, 13*16(%rax)
vmovdqa sha256d_4preext2_30(%rip), %xmm0
vmovdqa 0*16(%rax), %xmm4
vprotd $25, %xmm4, %xmm5
vprotd $14, %xmm4, %xmm6
vpxor %xmm5, %xmm6, %xmm6
vpsrld $3, %xmm4, %xmm4
vpxor %xmm6, %xmm4, %xmm4
vpaddd -1*16(%rax), %xmm4, %xmm4
vprotd $15, %xmm3, %xmm1
vprotd $15, %xmm7, %xmm5
vprotd $13, %xmm3, %xmm2
vprotd $13, %xmm7, %xmm6
vpxor %xmm1, %xmm2, %xmm2
vpxor %xmm5, %xmm6, %xmm6
vpaddd 7*16(%rax), %xmm0, %xmm0
vpaddd 8*16(%rax), %xmm4, %xmm4
vpsrld $10, %xmm3, %xmm3
vpsrld $10, %xmm7, %xmm7
vpxor %xmm2, %xmm3, %xmm3
vpxor %xmm6, %xmm7, %xmm7
vpaddd %xmm0, %xmm3, %xmm3
vpaddd %xmm4, %xmm7, %xmm7
vmovdqa %xmm3, 14*16(%rax)
vmovdqa %xmm7, 15*16(%rax)
jmp sha256d_ms_4way_xop_extend_loop2
sha256d_ms_4way_xop_extend_coda2:
sha256_xop_extend_round 44
movdqa sha256_4h+0(%rip), %xmm7
movdqa sha256_4h+16(%rip), %xmm5
movdqa sha256_4h+32(%rip), %xmm4
movdqa sha256_4h+48(%rip), %xmm3
movdqa sha256_4h+64(%rip), %xmm0
movdqa sha256_4h+80(%rip), %xmm8
movdqa sha256_4h+96(%rip), %xmm9
movdqa sha256_4h+112(%rip), %xmm10
movq %rsp, %rax
leaq sha256_4k(%rip), %rcx
jmp sha256d_ms_4way_xop_main_loop2
.macro sha256_xop_main_round_red i, r0, r1, r2, r3, r4
vpaddd 16*\i(%rax), \r0, %xmm6
vpaddd 16*\i(%rcx), %xmm6, %xmm6
vpandn \r1, \r3, %xmm1
vpand \r3, \r2, %xmm2
vpxor %xmm2, %xmm1, %xmm1
vpaddd %xmm1, %xmm6, %xmm6
vprotd $26, \r3, %xmm1
vprotd $21, \r3, %xmm2
vpxor %xmm1, %xmm2, %xmm2
vprotd $7, \r3, \r0
vpxor %xmm2, \r0, \r0
vpaddd \r0, %xmm6, %xmm6
vpaddd %xmm6, \r4, \r0
.endm
sha256d_ms_4way_xop_finish:
sha256_xop_main_round_red 57, %xmm9, %xmm8, %xmm0, %xmm10, %xmm4
sha256_xop_main_round_red 58, %xmm8, %xmm0, %xmm10, %xmm9, %xmm5
sha256_xop_main_round_red 59, %xmm0, %xmm10, %xmm9, %xmm8, %xmm7
sha256_xop_main_round_red 60, %xmm10, %xmm9, %xmm8, %xmm0, %xmm3
paddd sha256_4h+112(%rip), %xmm10
movdqa %xmm10, 112(%rdi)
addq $1032, %rsp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
movdqa 0(%rsp), %xmm6
movdqa 16(%rsp), %xmm7
movdqa 32(%rsp), %xmm8
movdqa 48(%rsp), %xmm9
movdqa 64(%rsp), %xmm10
addq $80, %rsp
popq %rdi
#endif
ret
#endif /* USE_XOP */
.text
.p2align 6
.globl sha256_use_4way
.globl _sha256_use_4way
sha256_use_4way:
_sha256_use_4way:
pushq %rbx
pushq %rcx
pushq %rdx
#if defined(USE_AVX)
/* Check for AVX and OSXSAVE support */
movl $1, %eax
cpuid
andl $0x18000000, %ecx
cmpl $0x18000000, %ecx
jne sha256_use_4way_base
/* Check for XMM and YMM state support */
xorl %ecx, %ecx
xgetbv
andl $0x00000006, %eax
cmpl $0x00000006, %eax
jne sha256_use_4way_base
#if defined(USE_XOP)
/* Check for XOP support */
movl $0x80000001, %eax
cpuid
andl $0x00000800, %ecx
jz sha256_use_4way_avx
sha256_use_4way_xop:
leaq sha256d_ms_4way_xop(%rip), %rcx
leaq sha256_transform_4way_core_xop(%rip), %rdx
jmp sha256_use_4way_done
#endif /* USE_XOP */
sha256_use_4way_avx:
leaq sha256d_ms_4way_avx(%rip), %rcx
leaq sha256_transform_4way_core_avx(%rip), %rdx
jmp sha256_use_4way_done
#endif /* USE_AVX */
sha256_use_4way_base:
leaq sha256d_ms_4way_sse2(%rip), %rcx
leaq sha256_transform_4way_core_sse2(%rip), %rdx
sha256_use_4way_done:
movq %rcx, sha256d_ms_4way_addr(%rip)
movq %rdx, sha256_transform_4way_core_addr(%rip)
popq %rdx
popq %rcx
popq %rbx
movl $1, %eax
ret
#if defined(USE_AVX2)
.text
.p2align 6
.globl sha256d_ms_8way
.globl _sha256d_ms_8way
sha256d_ms_8way:
_sha256d_ms_8way:
sha256d_ms_8way_avx2:
#if defined(_WIN64) || defined(__CYGWIN__)
pushq %rdi
subq $80, %rsp
vmovdqa %xmm6, 0(%rsp)
vmovdqa %xmm7, 16(%rsp)
vmovdqa %xmm8, 32(%rsp)
vmovdqa %xmm9, 48(%rsp)
vmovdqa %xmm10, 64(%rsp)
pushq %rsi
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
movq %r9, %rcx
#endif
pushq %rbp
movq %rsp, %rbp
subq $64*32, %rsp
andq $-128, %rsp
leaq 16*32(%rsi), %rax
sha256d_ms_8way_avx2_extend_loop1:
vmovdqa 3*32(%rsi), %ymm0
vmovdqa 2*32(%rax), %ymm3
vmovdqa 3*32(%rax), %ymm7
vmovdqa %ymm3, 2*32(%rsp)
vmovdqa %ymm7, 3*32(%rsp)
vpaddd %ymm0, %ymm7, %ymm7
vpslld $14, %ymm0, %ymm2
vpsrld $3, %ymm0, %ymm0
vpsrld $4, %ymm0, %ymm1
vpxor %ymm1, %ymm0, %ymm0
vpxor %ymm2, %ymm0, %ymm0
vpsrld $11, %ymm1, %ymm1
vpslld $11, %ymm2, %ymm2
vpxor %ymm1, %ymm0, %ymm0
vpxor %ymm2, %ymm0, %ymm0
vpaddd %ymm0, %ymm3, %ymm3
vmovdqa %ymm3, 2*32(%rax)
vmovdqa %ymm7, 3*32(%rax)
vmovdqa 4*32(%rax), %ymm0
vmovdqa %ymm0, 4*32(%rsp)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vmovdqa %ymm3, 4*32(%rax)
vmovdqa %ymm7, 5*32(%rax)
vmovdqa 6*32(%rax), %ymm0
vmovdqa 7*32(%rax), %ymm4
vmovdqa %ymm0, 6*32(%rsp)
vmovdqa %ymm4, 7*32(%rsp)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vpaddd %ymm4, %ymm7, %ymm7
vmovdqa %ymm3, 6*32(%rax)
vmovdqa %ymm7, 7*32(%rax)
vmovdqa 8*32(%rax), %ymm0
vmovdqa 2*32(%rax), %ymm4
vmovdqa %ymm0, 8*32(%rsp)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vpaddd %ymm4, %ymm7, %ymm7
vmovdqa %ymm3, 8*32(%rax)
vmovdqa %ymm7, 9*32(%rax)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd 3*32(%rax), %ymm3, %ymm3
vpaddd 4*32(%rax), %ymm7, %ymm7
vmovdqa %ymm3, 10*32(%rax)
vmovdqa %ymm7, 11*32(%rax)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd 5*32(%rax), %ymm3, %ymm3
vpaddd 6*32(%rax), %ymm7, %ymm7
vmovdqa %ymm3, 12*32(%rax)
vmovdqa %ymm7, 13*32(%rax)
vmovdqa 14*32(%rax), %ymm0
vmovdqa 15*32(%rax), %ymm4
vmovdqa %ymm0, 14*32(%rsp)
vmovdqa %ymm4, 15*32(%rsp)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpaddd 7*32(%rax), %ymm0, %ymm0
vpaddd 8*32(%rax), %ymm4, %ymm4
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vpaddd %ymm4, %ymm7, %ymm7
vmovdqa %ymm3, 14*32(%rax)
vmovdqa %ymm7, 15*32(%rax)
sha256d_ms_8way_avx2_extend_loop2:
sha256_avx2_extend_doubleround 16
sha256_avx2_extend_doubleround 18
sha256_avx2_extend_doubleround 20
sha256_avx2_extend_doubleround 22
sha256_avx2_extend_doubleround 24
sha256_avx2_extend_doubleround 26
sha256_avx2_extend_doubleround 28
sha256_avx2_extend_doubleround 30
sha256_avx2_extend_doubleround 32
sha256_avx2_extend_doubleround 34
sha256_avx2_extend_doubleround 36
sha256_avx2_extend_doubleround 38
sha256_avx2_extend_doubleround 40
sha256_avx2_extend_doubleround 42
jz sha256d_ms_8way_avx2_extend_coda2
sha256_avx2_extend_doubleround 44
sha256_avx2_extend_doubleround 46
vmovdqa 0(%rcx), %ymm7
vmovdqa 32(%rcx), %ymm8
vmovdqa 64(%rcx), %ymm9
vmovdqa 96(%rcx), %ymm10
vmovdqa 128(%rcx), %ymm0
vmovdqa 160(%rcx), %ymm5
vmovdqa 192(%rcx), %ymm4
vmovdqa 224(%rcx), %ymm3
movq %rsi, %rax
leaq sha256_8k(%rip), %rcx
jmp sha256d_ms_8way_avx2_main_loop1
sha256d_ms_8way_avx2_main_loop2:
sha256_avx2_main_round 0, %ymm10, %ymm9, %ymm8, %ymm0, %ymm3, %ymm4, %ymm5, %ymm7
sha256_avx2_main_round 1, %ymm9, %ymm8, %ymm0, %ymm10, %ymm4, %ymm5, %ymm7, %ymm3
sha256_avx2_main_round 2, %ymm8, %ymm0, %ymm10, %ymm9, %ymm5, %ymm7, %ymm3, %ymm4
sha256d_ms_8way_avx2_main_loop1:
sha256_avx2_main_round 3, %ymm0, %ymm10, %ymm9, %ymm8, %ymm7, %ymm3, %ymm4, %ymm5
sha256_avx2_main_quadround 4
sha256_avx2_main_quadround 8
sha256_avx2_main_quadround 12
sha256_avx2_main_quadround 16
sha256_avx2_main_quadround 20
sha256_avx2_main_quadround 24
sha256_avx2_main_quadround 28
sha256_avx2_main_quadround 32
sha256_avx2_main_quadround 36
sha256_avx2_main_quadround 40
sha256_avx2_main_quadround 44
sha256_avx2_main_quadround 48
sha256_avx2_main_quadround 52
sha256_avx2_main_round 56, %ymm10, %ymm9, %ymm8, %ymm0, %ymm3, %ymm4, %ymm5, %ymm7
jz sha256d_ms_8way_avx2_finish
sha256_avx2_main_round 57, %ymm9, %ymm8, %ymm0, %ymm10, %ymm4, %ymm5, %ymm7, %ymm3
sha256_avx2_main_round 58, %ymm8, %ymm0, %ymm10, %ymm9, %ymm5, %ymm7, %ymm3, %ymm4
sha256_avx2_main_round 59, %ymm0, %ymm10, %ymm9, %ymm8, %ymm7, %ymm3, %ymm4, %ymm5
sha256_avx2_main_quadround 60
vmovdqa 2*32(%rsp), %ymm1
vmovdqa 3*32(%rsp), %ymm2
vmovdqa 4*32(%rsp), %ymm6
vmovdqa %ymm1, 18*32(%rsi)
vmovdqa %ymm2, 19*32(%rsi)
vmovdqa %ymm6, 20*32(%rsi)
vmovdqa 6*32(%rsp), %ymm1
vmovdqa 7*32(%rsp), %ymm2
vmovdqa 8*32(%rsp), %ymm6
vmovdqa %ymm1, 22*32(%rsi)
vmovdqa %ymm2, 23*32(%rsi)
vmovdqa %ymm6, 24*32(%rsi)
vmovdqa 14*32(%rsp), %ymm1
vmovdqa 15*32(%rsp), %ymm2
vmovdqa %ymm1, 30*32(%rsi)
vmovdqa %ymm2, 31*32(%rsi)
vpaddd 0(%rdx), %ymm7, %ymm7
vpaddd 32(%rdx), %ymm5, %ymm5
vpaddd 64(%rdx), %ymm4, %ymm4
vpaddd 96(%rdx), %ymm3, %ymm3
vpaddd 128(%rdx), %ymm0, %ymm0
vpaddd 160(%rdx), %ymm8, %ymm8
vpaddd 192(%rdx), %ymm9, %ymm9
vpaddd 224(%rdx), %ymm10, %ymm10
vmovdqa %ymm7, 0(%rsp)
vmovdqa %ymm5, 32(%rsp)
vmovdqa %ymm4, 64(%rsp)
vmovdqa %ymm3, 96(%rsp)
vmovdqa %ymm0, 128(%rsp)
vmovdqa %ymm8, 160(%rsp)
vmovdqa %ymm9, 192(%rsp)
vmovdqa %ymm10, 224(%rsp)
vpxor %ymm0, %ymm0, %ymm0
movq $0x8000000000000100, %rax
vmovd %rax, %xmm1
vinserti128 $1, %xmm1, %ymm1, %ymm1
vpshufd $0x55, %ymm1, %ymm2
vpshufd $0x00, %ymm1, %ymm1
vmovdqa %ymm2, 8*32(%rsp)
vmovdqa %ymm0, 9*32(%rsp)
vmovdqa %ymm0, 10*32(%rsp)
vmovdqa %ymm0, 11*32(%rsp)
vmovdqa %ymm0, 12*32(%rsp)
vmovdqa %ymm0, 13*32(%rsp)
vmovdqa %ymm0, 14*32(%rsp)
vmovdqa %ymm1, 15*32(%rsp)
leaq 16*32(%rsp), %rax
cmpq %rax, %rax
vmovdqa -15*32(%rax), %ymm0
vmovdqa -14*32(%rax), %ymm4
vpslld $14, %ymm0, %ymm2
vpslld $14, %ymm4, %ymm6
vpsrld $3, %ymm0, %ymm8
vpsrld $3, %ymm4, %ymm4
vpsrld $7, %ymm0, %ymm1
vpsrld $4, %ymm4, %ymm5
vpxor %ymm1, %ymm8, %ymm8
vpxor %ymm5, %ymm4, %ymm4
vpsrld $11, %ymm1, %ymm1
vpsrld $11, %ymm5, %ymm5
vpxor %ymm2, %ymm8, %ymm8
vpxor %ymm6, %ymm4, %ymm4
vpslld $11, %ymm2, %ymm2
vpslld $11, %ymm6, %ymm6
vpxor %ymm1, %ymm8, %ymm8
vpxor %ymm5, %ymm4, %ymm4
vpxor %ymm2, %ymm8, %ymm8
vpxor %ymm6, %ymm4, %ymm4
vpaddd %ymm0, %ymm4, %ymm4
vpaddd -16*32(%rax), %ymm8, %ymm3
vpaddd sha256d_8preext2_17(%rip), %ymm4, %ymm7
vmovdqa %ymm3, 0*32(%rax)
vmovdqa %ymm7, 1*32(%rax)
sha256_avx2_extend_doubleround 2
sha256_avx2_extend_doubleround 4
vmovdqa -9*32(%rax), %ymm0
vpslld $14, %ymm0, %ymm2
vpsrld $3, %ymm0, %ymm8
vpsrld $7, %ymm0, %ymm1
vpxor %ymm1, %ymm8, %ymm8
vpxor %ymm2, %ymm8, %ymm8
vpsrld $11, %ymm1, %ymm1
vpslld $11, %ymm2, %ymm2
vpxor %ymm1, %ymm8, %ymm8
vpxor %ymm2, %ymm8, %ymm8
vpaddd sha256d_8preext2_23(%rip), %ymm0, %ymm4
vpaddd -10*32(%rax), %ymm8, %ymm0
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpaddd -1*32(%rax), %ymm0, %ymm0
vpaddd 0*32(%rax), %ymm4, %ymm4
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vpaddd %ymm4, %ymm7, %ymm7
vmovdqa %ymm3, 6*32(%rax)
vmovdqa %ymm7, 7*32(%rax)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd sha256d_8preext2_24(%rip), %ymm3, %ymm3
vpaddd 1*32(%rax), %ymm3, %ymm3
vpaddd 2*32(%rax), %ymm7, %ymm7
vmovdqa %ymm3, 8*32(%rax)
vmovdqa %ymm7, 9*32(%rax)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd 3*32(%rax), %ymm3, %ymm3
vpaddd 4*32(%rax), %ymm7, %ymm7
vmovdqa %ymm3, 10*32(%rax)
vmovdqa %ymm7, 11*32(%rax)
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd 5*32(%rax), %ymm3, %ymm3
vpaddd 6*32(%rax), %ymm7, %ymm7
vmovdqa %ymm3, 12*32(%rax)
vmovdqa %ymm7, 13*32(%rax)
vmovdqa sha256d_8preext2_30(%rip), %ymm0
vmovdqa 0*32(%rax), %ymm4
vpslld $14, %ymm4, %ymm6
vpsrld $3, %ymm4, %ymm4
vpsrld $4, %ymm4, %ymm5
vpxor %ymm5, %ymm4, %ymm4
vpxor %ymm6, %ymm4, %ymm4
vpsrld $11, %ymm5, %ymm5
vpslld $11, %ymm6, %ymm6
vpxor %ymm5, %ymm4, %ymm4
vpxor %ymm6, %ymm4, %ymm4
vpaddd -1*32(%rax), %ymm4, %ymm4
vpslld $13, %ymm3, %ymm2
vpslld $13, %ymm7, %ymm6
vpsrld $10, %ymm3, %ymm3
vpsrld $10, %ymm7, %ymm7
vpaddd 7*32(%rax), %ymm0, %ymm0
vpaddd 8*32(%rax), %ymm4, %ymm4
vpsrld $7, %ymm3, %ymm1
vpsrld $7, %ymm7, %ymm5
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpsrld $2, %ymm1, %ymm1
vpsrld $2, %ymm5, %ymm5
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpslld $2, %ymm2, %ymm2
vpslld $2, %ymm6, %ymm6
vpxor %ymm1, %ymm3, %ymm3
vpxor %ymm5, %ymm7, %ymm7
vpxor %ymm2, %ymm3, %ymm3
vpxor %ymm6, %ymm7, %ymm7
vpaddd %ymm0, %ymm3, %ymm3
vpaddd %ymm4, %ymm7, %ymm7
vmovdqa %ymm3, 14*32(%rax)
vmovdqa %ymm7, 15*32(%rax)
jmp sha256d_ms_8way_avx2_extend_loop2
sha256d_ms_8way_avx2_extend_coda2:
sha256_avx2_extend_round 44
vmovdqa sha256_8h+0(%rip), %ymm7
vmovdqa sha256_8h+32(%rip), %ymm5
vmovdqa sha256_8h+64(%rip), %ymm4
vmovdqa sha256_8h+96(%rip), %ymm3
vmovdqa sha256_8h+128(%rip), %ymm0
vmovdqa sha256_8h+160(%rip), %ymm8
vmovdqa sha256_8h+192(%rip), %ymm9
vmovdqa sha256_8h+224(%rip), %ymm10
movq %rsp, %rax
leaq sha256_8k(%rip), %rcx
jmp sha256d_ms_8way_avx2_main_loop2
.macro sha256_avx2_main_round_red i, r0, r1, r2, r3, r4
vpaddd 32*\i(%rax), \r0, %ymm6
vpaddd 32*\i(%rcx), %ymm6, %ymm6
vpandn \r1, \r3, %ymm1
vpand \r3, \r2, %ymm2
vpxor %ymm2, %ymm1, %ymm1
vpaddd %ymm1, %ymm6, %ymm6
vpslld $7, \r3, %ymm1
vpsrld $6, \r3, \r0
vpsrld $5, \r0, %ymm2
vpxor %ymm1, \r0, \r0
vpxor %ymm2, \r0, \r0
vpslld $14, %ymm1, %ymm1
vpsrld $14, %ymm2, %ymm2
vpxor %ymm1, \r0, \r0
vpxor %ymm2, \r0, \r0
vpslld $5, %ymm1, %ymm1
vpxor %ymm1, \r0, \r0
vpaddd \r0, %ymm6, %ymm6
vpaddd %ymm6, \r4, \r0
.endm
sha256d_ms_8way_avx2_finish:
sha256_avx2_main_round_red 57, %ymm9, %ymm8, %ymm0, %ymm10, %ymm4
sha256_avx2_main_round_red 58, %ymm8, %ymm0, %ymm10, %ymm9, %ymm5
sha256_avx2_main_round_red 59, %ymm0, %ymm10, %ymm9, %ymm8, %ymm7
sha256_avx2_main_round_red 60, %ymm10, %ymm9, %ymm8, %ymm0, %ymm3
vpaddd sha256_8h+224(%rip), %ymm10, %ymm10
vmovdqa %ymm10, 224(%rdi)
movq %rbp, %rsp
popq %rbp
#if defined(_WIN64) || defined(__CYGWIN__)
popq %rsi
vmovdqa 0(%rsp), %xmm6
vmovdqa 16(%rsp), %xmm7
vmovdqa 32(%rsp), %xmm8
vmovdqa 48(%rsp), %xmm9
vmovdqa 64(%rsp), %xmm10
addq $80, %rsp
popq %rdi
#endif
ret
.text
.p2align 6
.globl sha256_use_8way
.globl _sha256_use_8way
sha256_use_8way:
_sha256_use_8way:
pushq %rbx
/* Check for AVX and OSXSAVE support */
movl $1, %eax
cpuid
andl $0x18000000, %ecx
cmpl $0x18000000, %ecx
jne sha256_use_8way_no
/* Check for AVX2 support */
movl $7, %eax
xorl %ecx, %ecx
cpuid
andl $0x00000020, %ebx
cmpl $0x00000020, %ebx
jne sha256_use_8way_no
/* Check for XMM and YMM state support */
xorl %ecx, %ecx
xgetbv
andl $0x00000006, %eax
cmpl $0x00000006, %eax
jne sha256_use_8way_no
sha256_use_8way_yes:
movl $1, %eax
jmp sha256_use_8way_done
sha256_use_8way_no:
xorl %eax, %eax
sha256_use_8way_done:
popq %rbx
ret
#endif /* USE_AVX2 */
#endif
|
WyvernTKC/cpuminer-gr-avx2 | 15,779 | asm/neoscrypt_asm.S | /*
* Copyright (c) 2014 John Doering <ghostlander@phoenixcoin.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef _MSC_VER
/* arch defines */
#include "miner.h"
#endif
#if defined(__GNUC__) && !defined(__arm__)
#define ASM 1
/* #define WIN64 0 */
#endif
#if (ASM) && (__x86_64__)
/* neoscrypt_blkcpy(dst, src, len) = SSE2 based block memcpy();
* len must be a multiple of 64 bytes aligned properly */
.globl neoscrypt_blkcpy
neoscrypt_blkcpy:
#if (WIN64)
movq %rdi, %r10
movq %rsi, %r11
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
#endif
xorq %rcx, %rcx
movl %edx, %ecx
shrl $6, %ecx
movq $64, %rax
.blkcpy:
movdqa 0(%rsi), %xmm0
movdqa 16(%rsi), %xmm1
movdqa 32(%rsi), %xmm2
movdqa 48(%rsi), %xmm3
movdqa %xmm0, 0(%rdi)
movdqa %xmm1, 16(%rdi)
movdqa %xmm2, 32(%rdi)
movdqa %xmm3, 48(%rdi)
addq %rax, %rdi
addq %rax, %rsi
decl %ecx
jnz .blkcpy
#if (WIN64)
movq %r10, %rdi
movq %r11, %rsi
#endif
ret
/* neoscrypt_blkswp(blkA, blkB, len) = SSE2 based block swapper;
* len must be a multiple of 64 bytes aligned properly */
.globl neoscrypt_blkswp
neoscrypt_blkswp:
#if (WIN64)
movq %rdi, %r10
movq %rsi, %r11
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
#endif
xorq %rcx, %rcx
movl %edx, %ecx
shrl $6, %ecx
movq $64, %rax
.blkswp:
movdqa 0(%rdi), %xmm0
movdqa 16(%rdi), %xmm1
movdqa 32(%rdi), %xmm2
movdqa 48(%rdi), %xmm3
movdqa 0(%rsi), %xmm4
movdqa 16(%rsi), %xmm5
movdqa 32(%rsi), %xmm8
movdqa 48(%rsi), %xmm9
movdqa %xmm0, 0(%rsi)
movdqa %xmm1, 16(%rsi)
movdqa %xmm2, 32(%rsi)
movdqa %xmm3, 48(%rsi)
movdqa %xmm4, 0(%rdi)
movdqa %xmm5, 16(%rdi)
movdqa %xmm8, 32(%rdi)
movdqa %xmm9, 48(%rdi)
addq %rax, %rdi
addq %rax, %rsi
decl %ecx
jnz .blkswp
#if (WIN64)
movq %r10, %rdi
movq %r11, %rsi
#endif
ret
/* neoscrypt_blkxor(dst, src, len) = SSE2 based block XOR engine;
* len must be a multiple of 64 bytes aligned properly */
.globl neoscrypt_blkxor
neoscrypt_blkxor:
#if (WIN64)
movq %rdi, %r10
movq %rsi, %r11
movq %rcx, %rdi
movq %rdx, %rsi
movq %r8, %rdx
#endif
xorq %rcx, %rcx
movl %edx, %ecx
shrl $6, %ecx
movq $64, %rax
.blkxor:
movdqa 0(%rdi), %xmm0
movdqa 16(%rdi), %xmm1
movdqa 32(%rdi), %xmm2
movdqa 48(%rdi), %xmm3
movdqa 0(%rsi), %xmm4
movdqa 16(%rsi), %xmm5
movdqa 32(%rsi), %xmm8
movdqa 48(%rsi), %xmm9
pxor %xmm4, %xmm0
pxor %xmm5, %xmm1
pxor %xmm8, %xmm2
pxor %xmm9, %xmm3
movdqa %xmm0, 0(%rdi)
movdqa %xmm1, 16(%rdi)
movdqa %xmm2, 32(%rdi)
movdqa %xmm3, 48(%rdi)
addq %rax, %rdi
addq %rax, %rsi
decl %ecx
jnz .blkxor
#if (WIN64)
movq %r10, %rdi
movq %r11, %rsi
#endif
ret
/* neoscrypt_salsa(mem, rounds) = SSE2 based Salsa20;
* mem must be aligned properly, rounds must be a multiple of 2 */
.globl neoscrypt_salsa
neoscrypt_salsa:
#if (WIN64)
movq %rdi, %r10
movq %rsi, %r11
movq %rcx, %rdi
movq %rdx, %rsi
#endif
xorq %rcx, %rcx
movl %esi, %ecx
shrl $1, %ecx
movdqa 0(%rdi), %xmm0
movdqa %xmm0, %xmm12
movdqa 16(%rdi), %xmm1
movdqa %xmm1, %xmm13
movdqa 32(%rdi), %xmm2
movdqa %xmm2, %xmm14
movdqa 48(%rdi), %xmm3
movdqa %xmm3, %xmm15
.salsa:
movdqa %xmm1, %xmm4
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm3
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm3, %xmm3
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm1
pshufd $0x4E, %xmm2, %xmm2
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm0
pshufd $0x39, %xmm1, %xmm1
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm1
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm1, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm1, %xmm1
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm3
pshufd $0x4E, %xmm2, %xmm2
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
pshufd $0x39, %xmm3, %xmm3
pxor %xmm5, %xmm0
decl %ecx
jnz .salsa
paddd %xmm12, %xmm0
movdqa %xmm0, 0(%rdi)
paddd %xmm13, %xmm1
movdqa %xmm1, 16(%rdi)
paddd %xmm14, %xmm2
movdqa %xmm2, 32(%rdi)
paddd %xmm15, %xmm3
movdqa %xmm3, 48(%rdi)
#if (WIN64)
movq %r10, %rdi
movq %r11, %rsi
#endif
ret
/* neoscrypt_salsa_tangle(mem, count) = Salsa20 SSE2 map switcher;
* correct map: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* SSE2 map: 0 5 10 15 12 1 6 11 8 13 2 7 4 9 14 3 */
.globl neoscrypt_salsa_tangle
neoscrypt_salsa_tangle:
#if (WIN64)
movq %rdi, %r10
movq %rsi, %r11
movq %rcx, %rdi
movq %rdx, %rsi
#endif
xorq %rcx, %rcx
movl %esi, %ecx
movq $64, %r8
.salsa_tangle:
movl 4(%rdi), %eax
movl 20(%rdi), %edx
movl %eax, 20(%rdi)
movl %edx, 4(%rdi)
movl 8(%rdi), %eax
movl 40(%rdi), %edx
movl %eax, 40(%rdi)
movl %edx, 8(%rdi)
movl 12(%rdi), %eax
movl 60(%rdi), %edx
movl %eax, 60(%rdi)
movl %edx, 12(%rdi)
movl 16(%rdi), %eax
movl 48(%rdi), %edx
movl %eax, 48(%rdi)
movl %edx, 16(%rdi)
movl 28(%rdi), %eax
movl 44(%rdi), %edx
movl %eax, 44(%rdi)
movl %edx, 28(%rdi)
movl 36(%rdi), %eax
movl 52(%rdi), %edx
movl %eax, 52(%rdi)
movl %edx, 36(%rdi)
addq %r8, %rdi
decl %ecx
jnz .salsa_tangle
#if (WIN64)
movq %r10, %rdi
movq %r11, %rsi
#endif
ret
/* neoscrypt_chacha(mem, rounds) = SSE2 based ChaCha20;
* mem must be aligned properly, rounds must be a multiple of 2 */
.globl neoscrypt_chacha
neoscrypt_chacha:
#if (WIN64)
movq %rdi, %r10
movq %rsi, %r11
movq %rcx, %rdi
movq %rdx, %rsi
#endif
xorq %rcx, %rcx
movl %esi, %ecx
shrl $1, %ecx
movdqa 0(%rdi), %xmm0
movdqa %xmm0, %xmm12
movdqa 16(%rdi), %xmm1
movdqa %xmm1, %xmm13
movdqa 32(%rdi), %xmm2
movdqa %xmm2, %xmm14
movdqa 48(%rdi), %xmm3
movdqa %xmm3, %xmm15
.chacha:
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
pshuflw $0xB1, %xmm3, %xmm3
pshufhw $0xB1, %xmm3, %xmm3
paddd %xmm3, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm1, %xmm4
pslld $12, %xmm1
psrld $20, %xmm4
pxor %xmm4, %xmm1
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
movdqa %xmm3, %xmm4
pslld $8, %xmm3
psrld $24, %xmm4
pxor %xmm4, %xmm3
pshufd $0x93, %xmm0, %xmm0
paddd %xmm3, %xmm2
pshufd $0x4E, %xmm3, %xmm3
pxor %xmm2, %xmm1
pshufd $0x39, %xmm2, %xmm2
movdqa %xmm1, %xmm4
pslld $7, %xmm1
psrld $25, %xmm4
pxor %xmm4, %xmm1
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
pshuflw $0xB1, %xmm3, %xmm3
pshufhw $0xB1, %xmm3, %xmm3
paddd %xmm3, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm1, %xmm4
pslld $12, %xmm1
psrld $20, %xmm4
pxor %xmm4, %xmm1
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
movdqa %xmm3, %xmm4
pslld $8, %xmm3
psrld $24, %xmm4
pxor %xmm4, %xmm3
pshufd $0x39, %xmm0, %xmm0
paddd %xmm3, %xmm2
pshufd $0x4E, %xmm3, %xmm3
pxor %xmm2, %xmm1
pshufd $0x93, %xmm2, %xmm2
movdqa %xmm1, %xmm4
pslld $7, %xmm1
psrld $25, %xmm4
pxor %xmm4, %xmm1
decl %ecx
jnz .chacha
paddd %xmm12, %xmm0
movdqa %xmm0, 0(%rdi)
paddd %xmm13, %xmm1
movdqa %xmm1, 16(%rdi)
paddd %xmm14, %xmm2
movdqa %xmm2, 32(%rdi)
paddd %xmm15, %xmm3
movdqa %xmm3, 48(%rdi)
#if (WIN64)
movq %r10, %rdi
movq %r11, %rsi
#endif
ret
#endif /* (ASM) && (__x86_64__) */
#if (ASM) && (__i386__)
/* neoscrypt_blkcpy(dst, src, len) = SSE2 based block memcpy();
* len must be a multiple of 64 bytes aligned properly */
.globl neoscrypt_blkcpy
.globl _neoscrypt_blkcpy
neoscrypt_blkcpy:
_neoscrypt_blkcpy:
pushl %edi
pushl %esi
movl 12(%esp), %edi
movl 16(%esp), %esi
movl 20(%esp), %ecx
shrl $6, %ecx
movl $64, %eax
.blkcpy:
movdqa 0(%esi), %xmm0
movdqa 16(%esi), %xmm1
movdqa 32(%esi), %xmm2
movdqa 48(%esi), %xmm3
movdqa %xmm0, 0(%edi)
movdqa %xmm1, 16(%edi)
movdqa %xmm2, 32(%edi)
movdqa %xmm3, 48(%edi)
addl %eax, %edi
add %eax, %esi
decl %ecx
jnz .blkcpy
popl %esi
popl %edi
ret
/* neoscrypt_blkswp(blkA, blkB, len) = SSE2 based block swapper;
* len must be a multiple of 64 bytes aligned properly */
.globl neoscrypt_blkswp
.globl _neoscrypt_blkswp
neoscrypt_blkswp:
_neoscrypt_blkswp:
pushl %edi
pushl %esi
movl 12(%esp), %edi
movl 16(%esp), %esi
movl 20(%esp), %ecx
shrl $6, %ecx
movl $64, %eax
.blkswp:
movdqa 0(%edi), %xmm0
movdqa 16(%edi), %xmm1
movdqa 32(%edi), %xmm2
movdqa 48(%edi), %xmm3
movdqa 0(%esi), %xmm4
movdqa 16(%esi), %xmm5
movdqa 32(%esi), %xmm6
movdqa 48(%esi), %xmm7
movdqa %xmm0, 0(%esi)
movdqa %xmm1, 16(%esi)
movdqa %xmm2, 32(%esi)
movdqa %xmm3, 48(%esi)
movdqa %xmm4, 0(%edi)
movdqa %xmm5, 16(%edi)
movdqa %xmm6, 32(%edi)
movdqa %xmm7, 48(%edi)
addl %eax, %edi
addl %eax, %esi
decl %ecx
jnz .blkswp
popl %esi
popl %edi
ret
/* neoscrypt_blkxor(dst, src, len) = SSE2 based block XOR engine;
* len must be a multiple of 64 bytes aligned properly */
.globl neoscrypt_blkxor
.globl _neoscrypt_blkxor
neoscrypt_blkxor:
_neoscrypt_blkxor:
pushl %edi
pushl %esi
movl 12(%esp), %edi
movl 16(%esp), %esi
movl 20(%esp), %ecx
shrl $6, %ecx
movl $64, %eax
.blkxor:
movdqa 0(%edi), %xmm0
movdqa 16(%edi), %xmm1
movdqa 32(%edi), %xmm2
movdqa 48(%edi), %xmm3
movdqa 0(%esi), %xmm4
movdqa 16(%esi), %xmm5
movdqa 32(%esi), %xmm6
movdqa 48(%esi), %xmm7
pxor %xmm4, %xmm0
pxor %xmm5, %xmm1
pxor %xmm6, %xmm2
pxor %xmm7, %xmm3
movdqa %xmm0, 0(%edi)
movdqa %xmm1, 16(%edi)
movdqa %xmm2, 32(%edi)
movdqa %xmm3, 48(%edi)
addl %eax, %edi
addl %eax, %esi
decl %ecx
jnz .blkxor
popl %esi
popl %edi
ret
/* neoscrypt_salsa(mem, rounds) = SSE2 based Salsa20;
* mem must be aligned properly, rounds must be a multiple of 2 */
.globl neoscrypt_salsa
.globl _neoscrypt_salsa
neoscrypt_salsa:
_neoscrypt_salsa:
movl 4(%esp), %edx
movl 8(%esp), %ecx
shrl $1, %ecx
movdqa 0(%edx), %xmm0
movdqa %xmm0, %xmm6
movdqa 16(%edx), %xmm1
movdqa %xmm1, %xmm7
subl $32, %esp
movdqa 32(%edx), %xmm2
movdqu %xmm2, 0(%esp)
movdqa 48(%edx), %xmm3
movdqu %xmm3, 16(%esp)
.salsa:
movdqa %xmm1, %xmm4
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm3
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm3, %xmm3
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm1
pshufd $0x4E, %xmm2, %xmm2
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
movdqa %xmm3, %xmm4
pxor %xmm5, %xmm0
pshufd $0x39, %xmm1, %xmm1
paddd %xmm0, %xmm4
movdqa %xmm4, %xmm5
pslld $7, %xmm4
psrld $25, %xmm5
pxor %xmm4, %xmm1
movdqa %xmm0, %xmm4
pxor %xmm5, %xmm1
paddd %xmm1, %xmm4
movdqa %xmm4, %xmm5
pslld $9, %xmm4
psrld $23, %xmm5
pxor %xmm4, %xmm2
movdqa %xmm1, %xmm4
pxor %xmm5, %xmm2
pshufd $0x93, %xmm1, %xmm1
paddd %xmm2, %xmm4
movdqa %xmm4, %xmm5
pslld $13, %xmm4
psrld $19, %xmm5
pxor %xmm4, %xmm3
movdqa %xmm2, %xmm4
pxor %xmm5, %xmm3
pshufd $0x4E, %xmm2, %xmm2
paddd %xmm3, %xmm4
movdqa %xmm4, %xmm5
pslld $18, %xmm4
psrld $14, %xmm5
pxor %xmm4, %xmm0
pshufd $0x39, %xmm3, %xmm3
pxor %xmm5, %xmm0
decl %ecx
jnz .salsa
paddd %xmm6, %xmm0
movdqa %xmm0, 0(%edx)
paddd %xmm7, %xmm1
movdqa %xmm1, 16(%edx)
movdqu 0(%esp), %xmm6
paddd %xmm6, %xmm2
movdqa %xmm2, 32(%edx)
movdqu 16(%esp), %xmm7
paddd %xmm7, %xmm3
movdqa %xmm3, 48(%edx)
addl $32, %esp
ret
/* neoscrypt_salsa_tangle(mem, count) = Salsa20 SSE2 map switcher;
* correct map: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
* SSE2 map: 0 5 10 15 12 1 6 11 8 13 2 7 4 9 14 3 */
.globl neoscrypt_salsa_tangle
.globl _neoscrypt_salsa_tangle
neoscrypt_salsa_tangle:
_neoscrypt_salsa_tangle:
pushl %ebx
push %ebp
movl 12(%esp), %ebp
movl 16(%esp), %ecx
movl $64, %ebx
.salsa_tangle:
movl 4(%ebp), %eax
movl 20(%ebp), %edx
movl %eax, 20(%ebp)
movl %edx, 4(%ebp)
movl 8(%ebp), %eax
movl 40(%ebp), %edx
movl %eax, 40(%ebp)
movl %edx, 8(%ebp)
movl 12(%ebp), %eax
movl 60(%ebp), %edx
movl %eax, 60(%ebp)
movl %edx, 12(%ebp)
movl 16(%ebp), %eax
movl 48(%ebp), %edx
movl %eax, 48(%ebp)
movl %edx, 16(%ebp)
movl 28(%ebp), %eax
movl 44(%ebp), %edx
movl %eax, 44(%ebp)
movl %edx, 28(%ebp)
movl 36(%ebp), %eax
movl 52(%ebp), %edx
movl %eax, 52(%ebp)
movl %edx, 36(%ebp)
addl %ebx, %ebp
decl %ecx
jnz .salsa_tangle
popl %ebp
popl %ebx
ret
/* neoscrypt_chacha(mem, rounds) = SSE2 based ChaCha20;
* mem must be aligned properly, rounds must be a multiple of 2 */
.globl neoscrypt_chacha
.globl _neoscrypt_chacha
neoscrypt_chacha:
_neoscrypt_chacha:
movl 4(%esp), %edx
movl 8(%esp), %ecx
shrl $1, %ecx
movdqa 0(%edx), %xmm0
movdqa %xmm0, %xmm5
movdqa 16(%edx), %xmm1
movdqa %xmm1, %xmm6
movdqa 32(%edx), %xmm2
movdqa %xmm2, %xmm7
subl $16, %esp
movdqa 48(%edx), %xmm3
movdqu %xmm3, 0(%esp)
.chacha:
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
pshuflw $0xB1, %xmm3, %xmm3
pshufhw $0xB1, %xmm3, %xmm3
paddd %xmm3, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm1, %xmm4
pslld $12, %xmm1
psrld $20, %xmm4
pxor %xmm4, %xmm1
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
movdqa %xmm3, %xmm4
pslld $8, %xmm3
psrld $24, %xmm4
pxor %xmm4, %xmm3
pshufd $0x93, %xmm0, %xmm0
paddd %xmm3, %xmm2
pshufd $0x4E, %xmm3, %xmm3
pxor %xmm2, %xmm1
pshufd $0x39, %xmm2, %xmm2
movdqa %xmm1, %xmm4
pslld $7, %xmm1
psrld $25, %xmm4
pxor %xmm4, %xmm1
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
pshuflw $0xB1, %xmm3, %xmm3
pshufhw $0xB1, %xmm3, %xmm3
paddd %xmm3, %xmm2
pxor %xmm2, %xmm1
movdqa %xmm1, %xmm4
pslld $12, %xmm1
psrld $20, %xmm4
pxor %xmm4, %xmm1
paddd %xmm1, %xmm0
pxor %xmm0, %xmm3
movdqa %xmm3, %xmm4
pslld $8, %xmm3
psrld $24, %xmm4
pxor %xmm4, %xmm3
pshufd $0x39, %xmm0, %xmm0
paddd %xmm3, %xmm2
pshufd $0x4E, %xmm3, %xmm3
pxor %xmm2, %xmm1
pshufd $0x93, %xmm2, %xmm2
movdqa %xmm1, %xmm4
pslld $7, %xmm1
psrld $25, %xmm4
pxor %xmm4, %xmm1
decl %ecx
jnz .chacha
paddd %xmm5, %xmm0
movdqa %xmm0, 0(%edx)
paddd %xmm6, %xmm1
movdqa %xmm1, 16(%edx)
paddd %xmm7, %xmm2
movdqa %xmm2, 32(%edx)
movdqu 0(%esp), %xmm7
paddd %xmm7, %xmm3
movdqa %xmm3, 48(%edx)
addl $16, %esp
ret
#endif /* (ASM) && (__i386__) */
|
wyvernSemi/riscV | 9,733 | freertos/rv32/crt0.S | /* ################################################################################################# */
/* # << NEORV32 - crt0.S Start-Up Code >> # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License # */
/* # # */
/* # Copyright (c) 2023, Stephan Nolting. All rights reserved. # */
/* # # */
/* # Redistribution and use in source and binary forms, with or without modification, are # */
/* # permitted provided that the following conditions are met: # */
/* # # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */
/* # conditions and the following disclaimer. # */
/* # # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */
/* # conditions and the following disclaimer in the documentation and/or other materials # */
/* # provided with the distribution. # */
/* # # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */
/* # endorse or promote products derived from this software without specific prior written # */
/* # permission. # */
/* # # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */
/* ################################################################################################# */
// Modified by Simon Southwell for RV32 project July 2023
.file "crt0.S"
.section .text.crt0
.balign 4
.global _start
_start:
.cfi_startproc
// --------------------------------------------------------------
// We need to ensure interrupts are completely disabled at start.
// This is required if this code is part of a program uploaded by
// the on-chip debugger (potentionally taking control from the
// bootloader). We setup a new stack pointer here and WE DO NOT
// WANT TO trap to an outdated trap handler with a modified stack
// pointer.
// --------------------------------------------------------------
csrrwi zero, mstatus, 0 // Clear mstatus; disable machine-level interrupts
// --------------------------------------------------------------
// Setup CPU core CSRs
// --------------------------------------------------------------
csrw mie, zero // Disable all interrupt sources
la x1, __crt0_trap_handler // Configure early-boot trap handler
csrw mtvec, x1
// --------------------------------------------------------------
// Initialize integer register file
// --------------------------------------------------------------
.option push
.option norelax
// Setup pointers using rv32.ld linker script symbols
la sp, __crt0_stack_begin // Stack pointer
la gp, __global_pointer$ // Global pointer
.option pop
//addi x0, x0, 0 // Hardwired to zero
addi x1, x0, 0
//addi x2, x0, 0 // Stack pointer sp
//addi x3, x0, 0 // Global pointer gp
addi x4, x0, 0
addi x5, x0, 0
addi x6, x0, 0
addi x7, x0, 0
addi x8, x0, 0
addi x9, x0, 0
addi x10, x0, 0
addi x11, x0, 0
addi x12, x0, 0
addi x13, x0, 0
addi x14, x0, 0
addi x15, x0, 0
#ifndef __riscv_32e // Initialize upper half (if E extension is not implemented)
addi x16, x0, 0
addi x17, x0, 0
addi x18, x0, 0
addi x19, x0, 0
addi x20, x0, 0
addi x21, x0, 0
addi x22, x0, 0
addi x23, x0, 0
addi x24, x0, 0
addi x25, x0, 0
addi x26, x0, 0
addi x27, x0, 0
addi x28, x0, 0
addi x29, x0, 0
addi x30, x0, 0
addi x31, x0, 0
#endif
// --------------------------------------------------------------
// Copy initialized .data section from ROM to RAM (word-wise,
// section begins and ends on word boundary)
//
// Simon Southwell : Only do this if loading a binary image.
// If loading ELF in ISS, data is loaded directly to location
// --------------------------------------------------------------
#ifndef RV32_ISS
la x11, __crt0_copy_data_src_begin // Start of data area (copy source)
la x12, __crt0_copy_data_dst_begin // Start of data area (copy destination)
la x13, __crt0_copy_data_dst_end // Last address of destination data area
beq x11, x12, __crt0_copy_data_loop_end // Nothing to do if source and destination address are the same
__crt0_copy_data_loop:
bge x12, x13, __crt0_copy_data_loop_end
lw x14, 0(x11)
sw x14, 0(x12)
addi x11, x11, 4
addi x12, x12, 4
j __crt0_copy_data_loop
__crt0_copy_data_loop_end:
// --------------------------------------------------------------
// Call constructors
// --------------------------------------------------------------
la x8, __init_array_start
la x9, __init_array_end
__crt0_call_constructors_loop:
bge x8, x9, __crt0_call_constructors_loop_end
lw x1, 0(x8)
jalr x1, 0(x1)
addi x8, x8, 4
j __crt0_call_constructors_loop
__crt0_call_constructors_loop_end:
// --------------------------------------------------------------
// Call destructors
// --------------------------------------------------------------
la x8, __fini_array_start
la x9, __fini_array_end
__crt0_call_destructors_loop:
bge x8, x9, __crt0_call_destructors_loop_end
lw x1, 0(x8)
jalr x1, 0(x1)
addi x8, x8, 4
j __crt0_call_destructors_loop
__crt0_call_destructors_loop_end:
#endif
// --------------------------------------------------------------
// Clear .bss section (word-wise, section begins and ends on
// word boundary)
// --------------------------------------------------------------
la x14, __crt0_bss_start
la x15, __crt0_bss_end
__crt0_clear_bss_loop:
bge x14, x15, __crt0_clear_bss_loop_end
sw zero, 0(x14)
addi x14, x14, 4
j __crt0_clear_bss_loop
__crt0_clear_bss_loop_end:
// --------------------------------------------------------------
// Setup arguments and call main function
// --------------------------------------------------------------
addi x10, zero, 0 // x10 = a0 = argc = 0
addi x11, zero, 0 // x11 = a1 = argv = 0
jal x1, main // Call actual app's main function
__crt0_main_exit: // Main's "return" and "exit" will arrive here
csrw mie, zero // Disable all interrupt sources
csrw mscratch, a0 // Backup main's return code to mscratch (for debugger)
// Simon Southwell : Set PASS exit values and break
li x10, 0
li x17, 93
ebreak
// --------------------------------------------------------------
// Dummy trap handler (for all traps during very early boot stage)
// - does nothing but trying to move on to the next instruction
// --------------------------------------------------------------
.balign 4 // The trap handler has to be 32-bit aligned
__crt0_trap_handler:
addi sp, sp, -8
sw x8, 0(sp)
sw x9, 4(sp)
csrr x8, mcause
blt x8, zero, __crt0_trap_handler_end // Skip mepc modification if interrupt
// update mepc
csrr x8, mepc
lh x9, 0(x8) // Get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
andi x9, x9, 3 // Mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
addi x8, x8, +2 // mepc +2 only for compressed instructions
csrw mepc, x8 // Set new return address
addi x8, zero, 3
bne x8, x9, __crt0_trap_handler_end // Done if compressed instruction
csrr x8, mepc
addi x8, x8, +2 // Add another +2 to mepc (making +4) for uncompressed instructions
csrw mepc, x8
__crt0_trap_handler_end:
lw x8, 0(sp)
lw x9, 4(sp)
addi sp, sp, +8
mret
.cfi_endproc
.end
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.