repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
wuxx/icesugar | 3,371 | src/advanced/picorv32/tests/sra.S | # See LICENSE for license details.
#*****************************************************************************
# sra.S
#-----------------------------------------------------------------------------
#
# Test sra instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sra, 0x80000000, 0x80000000, 0 );
TEST_RR_OP( 3, sra, 0xc0000000, 0x80000000, 1 );
TEST_RR_OP( 4, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_OP( 5, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_OP( 6, sra, 0xffffffff, 0x80000001, 31 );
TEST_RR_OP( 7, sra, 0x7fffffff, 0x7fffffff, 0 );
TEST_RR_OP( 8, sra, 0x3fffffff, 0x7fffffff, 1 );
TEST_RR_OP( 9, sra, 0x00ffffff, 0x7fffffff, 7 );
TEST_RR_OP( 10, sra, 0x0001ffff, 0x7fffffff, 14 );
TEST_RR_OP( 11, sra, 0x00000000, 0x7fffffff, 31 );
TEST_RR_OP( 12, sra, 0x81818181, 0x81818181, 0 );
TEST_RR_OP( 13, sra, 0xc0c0c0c0, 0x81818181, 1 );
TEST_RR_OP( 14, sra, 0xff030303, 0x81818181, 7 );
TEST_RR_OP( 15, sra, 0xfffe0606, 0x81818181, 14 );
TEST_RR_OP( 16, sra, 0xffffffff, 0x81818181, 31 );
# Verify that shifts only use bottom five bits
TEST_RR_OP( 17, sra, 0x81818181, 0x81818181, 0xffffffc0 );
TEST_RR_OP( 18, sra, 0xc0c0c0c0, 0x81818181, 0xffffffc1 );
TEST_RR_OP( 19, sra, 0xff030303, 0x81818181, 0xffffffc7 );
TEST_RR_OP( 20, sra, 0xfffe0606, 0x81818181, 0xffffffce );
TEST_RR_OP( 21, sra, 0xffffffff, 0x81818181, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffff, 0x80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xff000000, 0x80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
TEST_RR_ZEROSRC12( 42, sra, 0 );
TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,623 | src/advanced/picorv32/tests/or.S | # See LICENSE for license details.
#*****************************************************************************
# or.S
#-----------------------------------------------------------------------------
#
# Test or instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, or, 0 );
TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,247 | src/advanced/picorv32/tests/srai.S | # See LICENSE for license details.
#*****************************************************************************
# srai.S
#-----------------------------------------------------------------------------
#
# Test srai instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, srai, 0x00000000, 0x00000000, 0 );
TEST_IMM_OP( 3, srai, 0xc0000000, 0x80000000, 1 );
TEST_IMM_OP( 4, srai, 0xff000000, 0x80000000, 7 );
TEST_IMM_OP( 5, srai, 0xfffe0000, 0x80000000, 14 );
TEST_IMM_OP( 6, srai, 0xffffffff, 0x80000001, 31 );
TEST_IMM_OP( 7, srai, 0x7fffffff, 0x7fffffff, 0 );
TEST_IMM_OP( 8, srai, 0x3fffffff, 0x7fffffff, 1 );
TEST_IMM_OP( 9, srai, 0x00ffffff, 0x7fffffff, 7 );
TEST_IMM_OP( 10, srai, 0x0001ffff, 0x7fffffff, 14 );
TEST_IMM_OP( 11, srai, 0x00000000, 0x7fffffff, 31 );
TEST_IMM_OP( 12, srai, 0x81818181, 0x81818181, 0 );
TEST_IMM_OP( 13, srai, 0xc0c0c0c0, 0x81818181, 1 );
TEST_IMM_OP( 14, srai, 0xff030303, 0x81818181, 7 );
TEST_IMM_OP( 15, srai, 0xfffe0606, 0x81818181, 14 );
TEST_IMM_OP( 16, srai, 0xffffffff, 0x81818181, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xff000000, 0x80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xff000000, 0x80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffe0000, 0x80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffff, 0x80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xff000000, 0x80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffe0000, 0x80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffff, 0x80000001, 31 );
TEST_IMM_ZEROSRC1( 24, srai, 0, 31 );
TEST_IMM_ZERODEST( 25, srai, 33, 20 );
#
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,013 | src/advanced/picorv32/tests/bne.S | # See LICENSE for license details.
#*****************************************************************************
# bne.S
#-----------------------------------------------------------------------------
#
# Test bne instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bne, 0, 1 );
TEST_BR2_OP_TAKEN( 3, bne, 1, 0 );
TEST_BR2_OP_TAKEN( 4, bne, -1, 1 );
TEST_BR2_OP_TAKEN( 5, bne, 1, -1 );
TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 );
TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 );
TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
bne x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,997 | src/advanced/picorv32/tests/mulhsu.S | # See LICENSE for license details.
#*****************************************************************************
# mulhsu.S
#-----------------------------------------------------------------------------
#
# Test mulhsu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 1,096 | src/advanced/picorv32/tests/jal.S | # See LICENSE for license details.
#*****************************************************************************
# jal.S
#-----------------------------------------------------------------------------
#
# Test jal instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Test 2: Basic test
#-------------------------------------------------------------
test_2:
li TESTNUM, 2
li ra, 0
linkaddr_2:
jal target_2
nop
nop
j fail
target_2:
la x2, linkaddr_2
addi x2, x2, 4
bne x2, ra, fail
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 3, x2, 3, \
li x2, 1; \
jal 1f; \
addi x2, x2, 1; \
addi x2, x2, 1; \
addi x2, x2, 1; \
addi x2, x2, 1; \
1: addi x2, x2, 1; \
addi x2, x2, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 1,740 | src/advanced/picorv32/tests/jalr.S | # See LICENSE for license details.
#*****************************************************************************
# jalr.S
#-----------------------------------------------------------------------------
#
# Test jalr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Test 2: Basic test
#-------------------------------------------------------------
test_2:
li TESTNUM, 2
li x31, 0
la x2, target_2
linkaddr_2:
jalr x19, x2, 0
nop
nop
j fail
target_2:
la x1, linkaddr_2
addi x1, x1, 4
bne x1, x19, fail
#-------------------------------------------------------------
# Test 3: Check r0 target and that r31 is not modified
#-------------------------------------------------------------
test_3:
li TESTNUM, 3
li x31, 0
la x3, target_3
linkaddr_3:
jalr x0, x3, 0
nop
j fail
target_3:
bne x31, x0, fail
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 7, x1, 4, \
li x1, 1; \
la x2, 1f;
jalr x19, x2, -4; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,243 | src/advanced/picorv32/tests/srli.S | # See LICENSE for license details.
#*****************************************************************************
# srli.S
#-----------------------------------------------------------------------------
#
# Test srli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, srli, 0xffff8000, 0xffff8000, 0 );
TEST_IMM_OP( 3, srli, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_OP( 4, srli, 0x01ffff00, 0xffff8000, 7 );
TEST_IMM_OP( 5, srli, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_OP( 6, srli, 0x0001ffff, 0xffff8001, 15 );
TEST_IMM_OP( 7, srli, 0xffffffff, 0xffffffff, 0 );
TEST_IMM_OP( 8, srli, 0x7fffffff, 0xffffffff, 1 );
TEST_IMM_OP( 9, srli, 0x01ffffff, 0xffffffff, 7 );
TEST_IMM_OP( 10, srli, 0x0003ffff, 0xffffffff, 14 );
TEST_IMM_OP( 11, srli, 0x00000001, 0xffffffff, 31 );
TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0 );
TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1 );
TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7 );
TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 21, srli, 0x7fffc000, 0xffff8000, 1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
TEST_IMM_ZERODEST( 29, srli, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,247 | src/advanced/picorv32/tests/slli.S | # See LICENSE for license details.
#*****************************************************************************
# slli.S
#-----------------------------------------------------------------------------
#
# Test slli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slli, 0x00000001, 0x00000001, 0 );
TEST_IMM_OP( 3, slli, 0x00000002, 0x00000001, 1 );
TEST_IMM_OP( 4, slli, 0x00000080, 0x00000001, 7 );
TEST_IMM_OP( 5, slli, 0x00004000, 0x00000001, 14 );
TEST_IMM_OP( 6, slli, 0x80000000, 0x00000001, 31 );
TEST_IMM_OP( 7, slli, 0xffffffff, 0xffffffff, 0 );
TEST_IMM_OP( 8, slli, 0xfffffffe, 0xffffffff, 1 );
TEST_IMM_OP( 9, slli, 0xffffff80, 0xffffffff, 7 );
TEST_IMM_OP( 10, slli, 0xffffc000, 0xffffffff, 14 );
TEST_IMM_OP( 11, slli, 0x80000000, 0xffffffff, 31 );
TEST_IMM_OP( 12, slli, 0x21212121, 0x21212121, 0 );
TEST_IMM_OP( 13, slli, 0x42424242, 0x21212121, 1 );
TEST_IMM_OP( 14, slli, 0x90909080, 0x21212121, 7 );
TEST_IMM_OP( 15, slli, 0x48484000, 0x21212121, 14 );
TEST_IMM_OP( 16, slli, 0x80000000, 0x21212121, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x00000080, 0x00000001, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x00004000, 0x00000001, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x80000000, 0x00000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x00000080, 0x00000001, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x00004000, 0x00000001, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x80000000, 0x00000001, 31 );
TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
TEST_IMM_ZERODEST( 25, slli, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,162 | src/advanced/picorv32/tests/lh.S | # See LICENSE for license details.
#*****************************************************************************
# lh.S
#-----------------------------------------------------------------------------
#
# Test lh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lh, 0x000000ff, 0, tdat );
TEST_LD_OP( 3, lh, 0xffffff00, 2, tdat );
TEST_LD_OP( 4, lh, 0x00000ff0, 4, tdat );
TEST_LD_OP( 5, lh, 0xfffff00f, 6, tdat );
# Test with negative offset
TEST_LD_OP( 6, lh, 0x000000ff, -6, tdat4 );
TEST_LD_OP( 7, lh, 0xffffff00, -4, tdat4 );
TEST_LD_OP( 8, lh, 0x00000ff0, -2, tdat4 );
TEST_LD_OP( 9, lh, 0xfffff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x3, 0x000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lh x3, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0xffffff00, \
la x1, tdat; \
addi x1, x1, -5; \
lh x3, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lh, 0x00000ff0, 2, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffff00f, 2, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffff00, 2, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x00000ff0, 2, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffff00f, 2, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffff00, 2, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x3, tdat; \
lh x2, 0(x3); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x3, tdat; \
lh x2, 0(x3); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0x00ff
tdat2: .half 0xff00
tdat3: .half 0x0ff0
tdat4: .half 0xf00f
RVTEST_DATA_END
|
wuxx/icesugar | 2,865 | src/advanced/picorv32/tests/add.S | # See LICENSE for license details.
#*****************************************************************************
# add.S
#-----------------------------------------------------------------------------
#
# Test add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, add, 0xffff8000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, add, 0x80000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, add, 0x7fff8000, 0x80000000, 0xffff8000 );
TEST_RR_OP( 8, add, 0x00007fff, 0x00000000, 0x00007fff );
TEST_RR_OP( 9, add, 0x7fffffff, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 10, add, 0x80007ffe, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 11, add, 0x80007fff, 0x80000000, 0x00007fff );
TEST_RR_OP( 12, add, 0x7fff7fff, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 13, add, 0xffffffff, 0x00000000, 0xffffffff );
TEST_RR_OP( 14, add, 0x00000000, 0xffffffff, 0x00000001 );
TEST_RR_OP( 15, add, 0xfffffffe, 0xffffffff, 0xffffffff );
TEST_RR_OP( 16, add, 0x80000000, 0x00000001, 0x7fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
TEST_RR_ZEROSRC1( 35, add, 15, 15 );
TEST_RR_ZEROSRC2( 36, add, 32, 32 );
TEST_RR_ZEROSRC12( 37, add, 0 );
TEST_RR_ZERODEST( 38, add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,154 | src/advanced/picorv32/tests/lb.S | # See LICENSE for license details.
#*****************************************************************************
# lb.S
#-----------------------------------------------------------------------------
#
# Test lb instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lb, 0xffffffff, 0, tdat );
TEST_LD_OP( 3, lb, 0x00000000, 1, tdat );
TEST_LD_OP( 4, lb, 0xfffffff0, 2, tdat );
TEST_LD_OP( 5, lb, 0x0000000f, 3, tdat );
# Test with negative offset
TEST_LD_OP( 6, lb, 0xffffffff, -3, tdat4 );
TEST_LD_OP( 7, lb, 0x00000000, -2, tdat4 );
TEST_LD_OP( 8, lb, 0xfffffff0, -1, tdat4 );
TEST_LD_OP( 9, lb, 0x0000000f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x3, 0xffffffff, \
la x1, tdat; \
addi x1, x1, -32; \
lb x3, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x3, 0x00000000, \
la x1, tdat; \
addi x1, x1, -6; \
lb x3, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffff0, 1, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lb, 0x0000000f, 1, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lb, 0x00000000, 1, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffff0, 1, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x0000000f, 1, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x00000000, 1, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x3, tdat; \
lb x2, 0(x3); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x3, tdat; \
lb x2, 0(x3); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xff
tdat2: .byte 0x00
tdat3: .byte 0xf0
tdat4: .byte 0x0f
RVTEST_DATA_END
|
wuxx/icesugar | 1,685 | src/advanced/picorv32/tests/xori.S | # See LICENSE for license details.
#*****************************************************************************
# xori.S
#-----------------------------------------------------------------------------
#
# Test xori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, xori, 0xff00f00f, 0x00ff0f00, 0xf0f );
TEST_IMM_OP( 3, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f );
TEST_IMM_OP( 5, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xff00f00f, 0xff00f700, 0x70f );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f );
TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x00ff0ff0, 0x00ff0fff, 0x00f );
TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,709 | src/advanced/picorv32/tests/slt.S | # See LICENSE for license details.
#*****************************************************************************
# slt.S
#-----------------------------------------------------------------------------
#
# Test slt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, slt, 0, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, slt, 0, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, slt, 1, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, slt, 0, 0x00000007, 0x00000003 );
TEST_RR_OP( 6, slt, 0, 0x00000000, 0xffff8000 );
TEST_RR_OP( 7, slt, 1, 0x80000000, 0x00000000 );
TEST_RR_OP( 8, slt, 1, 0x80000000, 0xffff8000 );
TEST_RR_OP( 9, slt, 1, 0x00000000, 0x00007fff );
TEST_RR_OP( 10, slt, 0, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 11, slt, 0, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 12, slt, 1, 0x80000000, 0x00007fff );
TEST_RR_OP( 13, slt, 0, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 14, slt, 0, 0x00000000, 0xffffffff );
TEST_RR_OP( 15, slt, 1, 0xffffffff, 0x00000001 );
TEST_RR_OP( 16, slt, 0, 0xffffffff, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 );
TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
TEST_RR_ZEROSRC12( 37, slt, 0 );
TEST_RR_ZERODEST( 38, slt, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,149 | src/advanced/picorv32/tests/bge.S | # See LICENSE for license details.
#*****************************************************************************
# bge.S
#-----------------------------------------------------------------------------
#
# Test bge instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bge, 0, 0 );
TEST_BR2_OP_TAKEN( 3, bge, 1, 1 );
TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
TEST_BR2_OP_TAKEN( 5, bge, 1, 0 );
TEST_BR2_OP_TAKEN( 6, bge, 1, -1 );
TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 );
TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 );
TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 24, x1, 3, \
li x1, 1; \
bge x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,028 | src/advanced/picorv32/tests/blt.S | # See LICENSE for license details.
#*****************************************************************************
# blt.S
#-----------------------------------------------------------------------------
#
# Test blt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, blt, 0, 1 );
TEST_BR2_OP_TAKEN( 3, blt, -1, 1 );
TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 );
TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 );
TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
blt x0, x1, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 2,818 | src/advanced/picorv32/tests/mul.S | # See LICENSE for license details.
#*****************************************************************************
# mul.S
#-----------------------------------------------------------------------------
#
# Test mul instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV32U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
TEST_RR_ZEROSRC12( 28, mul, 0 );
TEST_RR_ZERODEST( 29, mul, 33, 34 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
wuxx/icesugar | 1,025 | src/advanced/picorv32/scripts/tomthumbtg/start.S | .section .text.start
.global testcollection
/* zero-initialize all registers */
addi x1, zero, 0
addi x2, zero, 0
addi x3, zero, 0
addi x4, zero, 0
addi x5, zero, 0
addi x6, zero, 0
addi x7, zero, 0
addi x8, zero, 0
addi x9, zero, 0
addi x10, zero, 0
addi x11, zero, 0
addi x12, zero, 0
addi x13, zero, 0
addi x14, zero, 0
addi x15, zero, 0
addi x16, zero, 0
addi x17, zero, 0
addi x18, zero, 0
addi x19, zero, 0
addi x20, zero, 0
addi x21, zero, 0
addi x22, zero, 0
addi x23, zero, 0
addi x24, zero, 0
addi x25, zero, 0
addi x26, zero, 0
addi x27, zero, 0
addi x28, zero, 0
addi x29, zero, 0
addi x30, zero, 0
addi x31, zero, 0
/* set stack pointer */
lui sp, %hi(64*1024)
addi sp, sp, %lo(64*1024)
/* push zeros on the stack for argc and argv */
/* (stack is aligned to 16 bytes in riscv calling convention) */
addi sp,sp,-16
sw zero,0(sp)
sw zero,4(sp)
sw zero,8(sp)
sw zero,12(sp)
/* call test */
call testcollection
/* write test results */
lui x1, %hi(0x10000000)
addi x1, x1, %lo(0x10000000)
sw x5, 0(x1)
ebreak
|
wuxx/openocd-toolbox | 1,716 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/erase_check/armv7m_erase_check.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
loop:
ldrb r3, [r0]
adds r0, #1
ands r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end
|
wuxx/openocd-toolbox | 1,716 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/erase_check/armv7m_0_erase_check.s | /***************************************************************************
* Copyright (C) 2014 by Jeff Ciesielski *
* jeffciesielski@gmail.com *
* *
* Based on the armv7m erase checker by: *
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
loop:
ldrb r3, [r0]
adds r0, #1
orrs r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end
|
wuxx/openocd-toolbox | 1,646 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/erase_check/armv4_5_erase_check.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in
r1 - byte count
r2 - mask - result out
*/
.text
.arm
loop:
ldrb r3, [r0], #1
and r2, r2, r3
subs r1, r1, #1
bne loop
end:
bkpt #0
.end
|
wuxx/openocd-toolbox | 3,186 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32f2x.S | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (16bit words)
* r4 = flash base
*
* Clobbered:
* r6 - temp
* r7 - rp
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x10 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
ldr r6, STM32_PROG16
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrh r6, [r7], #0x02 /* read one half-word from src, increment ptr */
strh r6, [r2], #0x02 /* write one half-word from src, increment ptr */
dsb
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xf0 /* PGSERR | PGPERR | PGAERR | WRPERR */
bne error /* fail... */
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement halfword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG16: .word 0x101 /* PG | PSIZE_16*/
|
wuxx/openocd-toolbox | 2,667 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_16.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end
|
wuxx/openocd-toolbox | 2,709 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32lx.S | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2011 Clement Burin des Roziers *
* clement.burin-des-roziers@hikob.com *
* *
* Copyright (C) 2017 Armin van der Togt *
* armin@otheruse.nl *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
// Build : arm-eabi-gcc -c stm32lx.S
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/*
r0 - destination address
r1 - source address
r2 - count
*/
// r2 = source + count * 4
lsls r2, r2, #2
adds r2, r1, r2
// Go to compare
b test_done
write_word:
// load word from address in r1 and increase r1 by 4
ldmia r1!, {r3}
// store word to address in r0 and increase r0 by 4
stmia r0!, {r3}
test_done:
// compare r1 and r2
cmp r1, r2
// loop if not equal
bne write_word
// Set breakpoint to exit
bkpt #0x00
|
wuxx/openocd-toolbox | 2,107 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_intel_8.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrb r4, [r0], #1
strb r3, [r1]
strb r4, [r1]
busy:
ldrb r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #1
b loop
done:
b done
.end
|
wuxx/openocd-toolbox | 3,878 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/efm32.S | /***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (word-32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
/* offsets of registers from flash reg base */
#define EFM32_MSC_WRITECTRL_OFFSET 0x008
#define EFM32_MSC_WRITECMD_OFFSET 0x00c
#define EFM32_MSC_ADDRB_OFFSET 0x010
#define EFM32_MSC_WDATA_OFFSET 0x018
#define EFM32_MSC_STATUS_OFFSET 0x01c
#define EFM32_MSC_LOCK_OFFSET 0x03c
/* unlock MSC */
ldr r6, =#0x1b71
str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
/* set WREN to 1 */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
/* store address in MSC_ADDRB */
str r4, [r0, #EFM32_MSC_ADDRB_OFFSET]
/* set LADDRIM bit */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
/* check status for INVADDR and/or LOCKED */
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #6
tst r6, r7
bne error
/* wait for WDATAREADY */
wait_wdataready:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #8
tst r6, r7
beq wait_wdataready
/* load data to WDATA */
ldr r6, [r5]
str r6, [r0, #EFM32_MSC_WDATA_OFFSET]
/* set WRITEONCE bit */
movs r6, #8
str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET]
adds r5, #4 /* rp++ */
adds r4, #4 /* target_address++ */
/* wait until BUSY flag is reset */
busy:
ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET]
movs r7, #1
tst r6, r7
bne busy
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
|
wuxx/openocd-toolbox | 2,778 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stellaris.s | /***************************************************************************
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start
* r1 = workarea end
* r2 = target address
* r3 = count (32bit words)
*
* Clobbered:
* r4 = pFLASH_CTRL_BASE
* r5 = FLASHWRITECMD
* r7 - rp
* r8 - wp, tmp
*/
write:
ldr r4, pFLASH_CTRL_BASE
ldr r5, FLASHWRITECMD
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r7, [r0, #4] /* read rp */
cmp r7, r8 /* wait until rp != wp */
beq wait_fifo
mainloop:
str r2, [r4, #0] /* FMA - write address */
add r2, r2, #4 /* increment target address */
ldr r8, [r7], #4
str r8, [r4, #4] /* FMD - write data */
str r5, [r4, #8] /* FMC - enable write */
busy:
ldr r8, [r4, #8]
tst r8, #1
bne busy
cmp r7, r1 /* wrap rp at end of buffer */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement word count */
cbz r3, exit /* loop if not done */
b wait_fifo
exit:
bkpt #0
pFLASH_CTRL_BASE: .word 0x400FD000
FLASHWRITECMD: .word 0xA4420001
|
wuxx/openocd-toolbox | 2,797 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/cortex-m0.S | /***************************************************************************
* Copyright (C) 2014 by Angus Gratton *
* Derived from stm32f1x.S:
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* Copyright (C) 2013 by Roman Dmitrienko *
* me@iamroman.org *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
/* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
* very generic (CPU blocks during flash writes), so this is actually
* just a generic word-oriented copy routine for Cortex-M0 (also
* suitable for Cortex-M0+/M3/M4.)
*
* To assemble:
* arm-none-eabi-gcc -c cortex-m0.S
*
* To disassemble:
* arm-none-eabi-objdump -o cortex-m0.o
*
* Thanks to Jens Bauer for providing advice on some of the tweaks.
*/
/* Params:
* r0 - byte count (in)
* r1 - workarea start
* r2 - workarea end
* r3 - target address
* Clobbered:
* r4 - rp
* r5 - wp, tmp
*/
wait_fifo:
ldr r5, [r1, #0] /* read wp */
cmp r5, #0 /* abort if wp == 0 */
beq exit
ldr r4, [r1, #4] /* read rp */
cmp r4, r5 /* wait until rp != wp */
beq wait_fifo
ldmia r4!, {r5} /* "*target_address++ = *rp++" */
stmia r3!, {r5}
cmp r4, r2 /* wrap rp at end of work area buffer */
bcc no_wrap
mov r4, r1
adds r4, #8 /* skip rp,wp at start of work area */
no_wrap:
str r4, [r1, #4] /* write back rp */
subs r0, #4 /* decrement byte count */
bne wait_fifo /* loop if not done */
exit:
bkpt #0
|
wuxx/openocd-toolbox | 2,451 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
bne busy
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end
|
wuxx/openocd-toolbox | 2,665 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32f1x.S | /***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (halfword-16bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - tmp
*/
#define STM32_FLASH_SR_OFFSET 0x0c /* offset of SR register from flash reg base */
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldrh r6, [r5] /* "*target_address++ = *rp++" */
strh r6, [r4]
adds r5, #2
adds r4, #2
busy:
ldr r6, [r0, #STM32_FLASH_SR_OFFSET] /* wait until BSY flag is reset */
movs r7, #1
tst r6, r7
bne busy
movs r7, #0x14 /* check the error bits */
tst r6, r7
bne error
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement halfword count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
|
wuxx/openocd-toolbox | 2,481 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/sim3x.s | /***************************************************************************
* Copyright (C) 2014 by Ladislav Bábel *
* ladababel@seznam.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
#define INITIAL_UNLOCK 0x5A
#define MULTIPLE_UNLOCK 0xF2
#define FLASHCTRL_KEY 0x4002E0C0
#define FLASHCTRL_CONFIG 0x4002E000
#define FLASHCTRL_WRADDR 0x4002E0A0
#define FLASHCTRL_WRDATA 0x4002E0B0
#define BUSYF 0x00100000
/* Write the initial unlock value to KEY (0xA5) */
movs r6, #INITIAL_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
/* Write the multiple unlock value to KEY (0xF2) */
movs r6, #MULTIPLE_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
wait_fifo:
ldr r6, [r2, #0]
cmp r6, #0
beq exit
ldr r5, [r2, #4]
cmp r5, r6
beq wait_fifo
/* wait for BUSYF flag */
wait_busy1:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy1
/* Write the destination address to WRADDR */
str r4, [r0, #FLASHCTRL_WRADDR]
/* Write the data half-word to WRDATA in right-justified format */
ldrh r6, [r5]
str r6, [r0, #FLASHCTRL_WRDATA]
adds r5, #2
adds r4, #2
/* wrap rp at end of buffer */
cmp r5, r3
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4]
subs r1, r1, #1
cmp r1, #0
beq exit
b wait_fifo
exit:
movs r6, #MULTIPLE_LOCK
str r6, [r0, #FLASHCTRL_KEY]
/* wait for BUSYF flag */
wait_busy2:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy2
bkpt #0
|
wuxx/openocd-toolbox | 2,717 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv7m_cfi_span_16.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrh r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
beq success
add r1, r1, #2 /* 0x2 */
b code
success:
mov r5, #128 /* 0x80 */
b done
done:
bkpt #0
.end
|
wuxx/openocd-toolbox | 2,305 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/str7x.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4t
.section .init
/*
r0 source address
r1 address
r2 FLASH_CR0
r3 dword count
r4 result
r5 busy mask
*/
write:
mov r4, #0x10000000 /* set DWPG bit */
str r4, [r2, #0x0] /* FLASH_CR0 */
str r1, [r2, #0x10] /* FLASH_AR */
ldr r4, [r0], #4 /* load data */
str r4, [r2, #0x8] /* FLASH_DR0 */
ldr r4, [r0], #4 /* load data */
str r4, [r2, #0xc] /* FLASH_DR1 */
mov r4, #0x90000000 /* set DWPG and WMS bits */
str r4, [r2, #0x0] /* FLASH_CR0 */
busy:
ldr r4, [r2, #0x0] /* FLASH_CR0 */
tst r4, r5
bne busy
ldr r4, [r2, #0x14] /* FLASH_ER */
tst r4, #0xff /* do we have errors */
tsteq r4, #0x100 /* write protection set */
bne exit
add r1, r1, #0x8 /* next 8 bytes */
subs r3, r3, #1 /* decremment dword count */
bne write
exit:
b exit
.end
|
wuxx/openocd-toolbox | 3,655 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/pic32mx.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arch m4k
.set noreorder
.set noat
/* params:
* $a0 src adr - ram + result
* $a1 dest adr - flash
* $a2 count (32bit words)
* vars
*
* temps:
* $t0, $t1, $t2, $t3, $t4, $t5
* $s0, $s1, $s3, $s4, $s5
*/
.type main, @function
.global main
.ent main
main:
/* setup constants */
lui $t0, 0xaa99
ori $t0, 0x6655 /* NVMKEY1 */
lui $t1, 0x5566
ori $t1, 0x99AA /* NVMKEY2 */
lui $t2, 0xBF80
ori $t2, 0xF400 /* NVMCON */
ori $t3, $zero, 0x4003 /* NVMCON row write cmd */
ori $t4, $zero, 0x8000 /* NVMCON start cmd */
write_row:
/* can we perform a row write: 128 32bit words */
sltiu $s3, $a2, 128
bne $s3, $zero, write_word
ori $t5, $zero, 0x4000 /* NVMCON clear cmd */
/* perform row write 512 bytes */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
sw $a0, 64($t2) /* set NVMSRCADDR with src addr - real addr */
bal progflash
addiu $a0, $a0, 512
addiu $a1, $a1, 512
beq $zero, $zero, write_row
addiu $a2, $a2, -128
write_word:
/* write 32bit words */
lui $s5, 0xa000
ori $s5, 0x0000
or $a0, $a0, $s5 /* convert to virtual addr */
beq $zero, $zero, next_word
ori $t3, $zero, 0x4001 /* NVMCON word write cmd */
prog_word:
lw $s4, 0($a0) /* load data - from virtual addr */
sw $s4, 48($t2) /* set NVMDATA with data */
sw $a1, 32($t2) /* set NVMADDR with dest addr - real addr */
bal progflash
addiu $a0, $a0, 4
addiu $a1, $a1, 4
addiu $a2, $a2, -1
next_word:
bne $a2, $zero, prog_word
nop
done:
beq $zero, $zero, exit
addiu $a0, $zero, 0
error:
/* save result to $a0 */
addiu $a0, $s1, 0
exit:
sdbbp
.end main
.type progflash, @function
.global progflash
.ent progflash
progflash:
sw $t3, 0($t2) /* set NVMWREN */
sw $t0, 16($t2) /* write NVMKEY1 */
sw $t1, 16($t2) /* write NVMKEY2 */
sw $t4, 8($t2) /* start operation */
waitflash:
lw $s0, 0($t2)
and $s0, $s0, $t4
bne $s0, $zero, waitflash
nop
/* following is to comply with errata #34
* 500ns delay required */
nop
nop
nop
nop
/* check for errors */
lw $s1, 0($t2)
andi $s1, $zero, 0x3000
bne $s1, $zero, error
sw $t5, 4($t2) /* clear NVMWREN */
jr $ra
nop
.end progflash
|
wuxx/openocd-toolbox | 2,667 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_32.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldr r5, [r0], #4
str r9, [r8]
str r11, [r10]
str r3, [r8]
str r5, [r1]
nop
busy:
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldr r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #4 /* 0x4 */
b code
done:
b done
.end
|
wuxx/openocd-toolbox | 2,431 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrh r5, [r0], #2
strh r9, [r8]
strh r11, [r10]
strh r3, [r8]
strh r5, [r1]
nop
busy:
ldrh r6, [r1]
eor r7, r5, r6
ands r7, #0x80
bne busy
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #2 /* 0x2 */
b code
done:
b done
.end
|
wuxx/openocd-toolbox | 7,671 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/lpcspifi_write.S | /***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - temp
* r11 - current page end address
*/
/*
* This code is embedded within: src/flash/nor/lpcspifi.c as a "C" array.
*
* To rebuild:
* arm-none-eabi-gcc -c lpcspifi_write.S
* arm-none-eabi-objcopy -O binary lpcspifi_write.o lpcspifi_write.bin
* xxd -c 8 -i lpcspifi_write.bin > lpcspifi_write.txt
*
* Then read and edit this result into the "C" source.
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
mov.w r11, #0x00
find_next_page_boundary:
add r11, r4 /* Increment to the next page */
cmp r11, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
page_program:
bl cs_down
mov.w r9, #0x02 /* Send the page program command */
bl write_data
write_address:
lsr r9, r2, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r2, #8
bl write_data
mov.w r9, r2
bl write_data
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cbz r3, exit /* Exit if we have written everything */
add r2, #1 /* Increment flash address by 1 */
cmp r11, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
bl cs_up /* Otherwise, end the command and keep going w/ the next page */
add r11, r4 /* Move up the end-of-page address by the page size*/
wait_flash_busy: /* Wait for the flash to finish the previous page write */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
b write_enable /* If it is done, start a new page write */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
bl cs_up /* end the command before returning */
mov r0, r6
bkpt #0x00
.end
|
wuxx/openocd-toolbox | 2,107 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_intel_32.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldr r4, [r0], #4
str r3, [r1]
str r4, [r1]
busy:
ldr r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #4
b loop
done:
b done
.end
|
wuxx/openocd-toolbox | 2,667 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_span_8.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* input parameters - */
/* R0 = source address */
/* R1 = destination address */
/* R2 = number of writes */
/* R3 = flash write command */
/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
/* output parameters - */
/* R5 = 0x80 ok 0x00 bad */
/* temp registers - */
/* R6 = value read from flash to test status */
/* R7 = holding register */
/* unlock registers - */
/* R8 = unlock1_addr */
/* R9 = unlock1_cmd */
/* R10 = unlock2_addr */
/* R11 = unlock2_cmd */
code:
ldrb r5, [r0], #1
strb r9, [r8]
strb r11, [r10]
strb r3, [r8]
strb r5, [r1]
nop
busy:
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
ands r6, r6, r4, lsr #2
beq busy /* b if DQ5 low */
ldrb r6, [r1]
eor r7, r5, r6
ands r7, r4, r7
beq cont /* b if DQ7 == Data7 */
mov r5, #0 /* 0x0 - return 0x00, error */
bne done
cont:
subs r2, r2, #1 /* 0x1 */
moveq r5, #128 /* 0x80 */
beq done
add r1, r1, #1 /* 0x1 */
b code
done:
b done
.end
|
wuxx/openocd-toolbox | 3,409 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/k1921vk01t.S | /***************************************************************************
* Copyright (C) 2015 by Bogdan Kolbov *
* kolbov@niiet.ru *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
/* K1921VK01T has 128-bitwidth flash, so it`s able to load 4x32-bit words at the time.
* And only after all words loaded we can start write
*/
/* Registers addresses */
#define FLASH_FMA 0x00 /* Address reg */
#define FLASH_FMD1 0x04 /* Data1 reg */
#define FLASH_FMC 0x08 /* Command reg */
#define FLASH_FCIS 0x0C /* Operation Status reg */
#define FLASH_FCIC 0x14 /* Operation Status Clear reg */
#define FLASH_FMD2 0x50 /* Data2 reg */
#define FLASH_FMD3 0x54 /* Data3 reg */
#define FLASH_FMD4 0x58 /* Data4 reg*/
/* Params:
* r0 - write cmd (in), status (out)
* r1 - count
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - flash base
*/
ldr r7, =#0xA001C000 /* Flash reg base*/
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
load_data:
ldr r6, [r5] /* read data1 */
str r6, [r7, #FLASH_FMD1]
adds r5, #4
ldr r6, [r5] /* read data2 */
str r6, [r7, #FLASH_FMD2]
adds r5, #4
ldr r6, [r5] /* read data3 */
str r6, [r7, #FLASH_FMD3]
adds r5, #4
ldr r6, [r5] /* read data4 */
str r6, [r7, #FLASH_FMD4]
adds r5, #4
start_write:
str r4, [r7, #FLASH_FMA] /* set addr */
adds r4, #16
str r0, [r7, #FLASH_FMC] /* write cmd */
busy:
ldr r6, [r7, #FLASH_FCIS] /* wait until flag set */
cmp r6, #0x0
beq busy
cmp r6, #2 /* check the error bit */
beq error
movs r6, #1 /* clear flags */
str r6, [r7, #FLASH_FCIC]
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement 16-byte block count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
|
wuxx/openocd-toolbox | 2,128 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/str9x.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv5t
.section .init
/*
r0 source address (in)
r1 target address (in)
r2 word count (in)
r3 result (out)
*/
write:
bic r4, r1, #3 /* word address */
mov r3, #0x40 /* write command */
strh r3, [r4, #0]
ldrh r3, [r0], #2 /* read data */
strh r3, [r1], #2 /* write data */
mov r3, #0x70 /* status command */
strh r3, [r4, #0]
busy:
ldrb r3, [r4, #0] /* status */
tst r3, #0x80
beq busy
mov r5, #0x50 /* clear status command */
strh r5, [r4, #0]
mov r5, #0xFF /* read array */
strh r5, [r4, #0]
tst r3, #0x12
bne exit
subs r2, r2, #1 /* decremment word count */
bne write
exit:
bkpt #0
.end
|
wuxx/openocd-toolbox | 3,704 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/mdr32fx.S | /***************************************************************************
* Copyright (C) 2011 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
* Copyright (C) 2013 by Paul Fertser *
* fercerpav@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.global write
/* Params:
* r0 - flash base (in), status (out)
* r1 - count (32bit)
* r2 - workarea start
* r3 - workarea end
* r4 - target address
* Clobbered:
* r5 - rp
* r6 - wp, tmp
* r7 - current FLASH_CMD
*/
#define FLASH_CMD 0x00
#define FLASH_ADR 0x04
#define FLASH_DI 0x08
#define FLASH_NVSTR (1 << 13)
#define FLASH_PROG (1 << 12)
#define FLASH_MAS1 (1 << 11)
#define FLASH_ERASE (1 << 10)
#define FLASH_SE (1 << 8)
#define FLASH_YE (1 << 7)
#define FLASH_XE (1 << 6)
ldr r7, [r0, #FLASH_CMD]
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldr r6, [r5] /* "*target_address++ = *rp++" */
str r4, [r0, #FLASH_ADR]
str r6, [r0, #FLASH_DI]
ldr r6, =(FLASH_XE | FLASH_PROG)
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 5us
movs r6, #5
bl delay
ldr r6, =#FLASH_NVSTR
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 10us
movs r6, #13
bl delay
movs r6, #FLASH_YE
orrs r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 40us
movs r6, #61
bl delay
movs r6, #FLASH_YE
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
ldr r6, =#FLASH_PROG
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
# wait 5us
movs r6, #5
bl delay
ldr r6, =#(FLASH_XE | FLASH_NVSTR)
bics r7, r7, r6
str r7, [r0, #FLASH_CMD]
adds r5, #4
adds r4, #4
cmp r5, r3 /* wrap rp at end of buffer */
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4] /* store rp */
subs r1, r1, #1 /* decrement word count */
cmp r1, #0
beq exit /* loop if not done */
b wait_fifo
exit:
mov r0, r6 /* return status in r0 */
bkpt #0
/* r6 - in
* for r6 == 1 it'll take:
* 1 (prepare operand) + 4 (bl) + 2 (subs+cmp) + 1 (bne) + 3 (b) ->
* 11 tacts == 1.4us with 8MHz
* every extra iteration will take 5 tacts == 0.6us */
delay:
subs r6, r6, #1
cmp r6, #0
bne delay
bx lr
|
wuxx/openocd-toolbox | 4,289 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/lpcspifi_init.S | /***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/***************************************************************************
* This is an algorithm for the LPC43xx family (and probably the LPC18xx *
* family as well, though they have not been tested) that will initialize *
* memory-mapped SPI flash accesses. Unfortunately NXP has published *
* neither the ROM source code that performs this initialization nor the *
* register descriptions necessary to do so, so this code is necessary to *
* call into the ROM SPIFI API. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 2
/*
* Params :
* r0 = spifi clock speed
*/
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define SPIFI_ROM_TABLE_BASE_HIGH 0x1040
#define SPIFI_ROM_TABLE_BASE_LOW 0x0118
code:
mov.w r8, r0
sub sp, #0x84
add r7, sp, #0x0
/* Initialize SPIFI pins */
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0xf3
str.w r2, [r3, #IOCONFIG_SCK_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #IOCONFIG_BASE_LOW
movt r2, #IOCONFIG_BASE_HIGH
mov.w r1, #IOCONFIG_BASE_LOW
movt r1, #IOCONFIG_BASE_HIGH
mov.w r0, #IOCONFIG_BASE_LOW
movt r0, #IOCONFIG_BASE_HIGH
mov.w r4, #0xd3
str.w r4, [r0, #IOCONFIG_MOSI_OFFSET]
mov r0, r4
str.w r0, [r1, #IOCONFIG_MISO_OFFSET]
mov r1, r0
str.w r1, [r2, #IOCONFIG_WP_OFFSET]
str.w r1, [r3, #IOCONFIG_HOLD_OFFSET]
mov.w r3, #IOCONFIG_BASE_LOW
movt r3, #IOCONFIG_BASE_HIGH
mov.w r2, #0x13
str.w r2, [r3, #IOCONFIG_CS_OFFSET]
/* Perform SPIFI init. See spifi_rom_api.h (in NXP lpc43xx driver package) for details */
/* on initialization arguments. */
movw r3, #SPIFI_ROM_TABLE_BASE_LOW /* The ROM API table is located @ 0x10400118, and */
movt r3, #SPIFI_ROM_TABLE_BASE_HIGH /* the first pointer in the struct is to the init function. */
ldr r3, [r3, #0x0]
ldr r4, [r3, #0x0] /* Grab the init function pointer from the table */
/* Set up function arguments */
movw r0, #0x3b4
movt r0, #0x1000 /* Pointer to a SPIFI data struct that we don't care about */
mov.w r1, #0x3 /* "csHigh". Not 100% sure what this does. */
mov.w r2, #0xc0 /* The configuration word: S_RCVCLOCK | S_FULLCLK */
mov.w r3, r8 /* SPIFI clock speed (12MHz) */
blx r4 /* Call the init function */
b done
done:
bkpt #0
.end
|
wuxx/openocd-toolbox | 1,928 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv7m_io.s | /***************************************************************************
* Copyright (C) 2013 by Henrik Nilsson *
* henrik.nilsson@bytequest.se *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.arch armv7-m
.thumb
.thumb_func
.align 4
/* Inputs:
* r0 buffer address
* r1 NAND data address (byte wide)
* r2 buffer length
*/
read:
ldrb r3, [r1]
strb r3, [r0], #1
subs r2, r2, #1
bne read
done_read:
bkpt #0
.align 4
/* Inputs:
* r0 NAND data address (byte wide)
* r1 buffer address
* r2 buffer length
*/
write:
ldrb r3, [r1], #1
strb r3, [r0]
subs r2, r2, #1
bne write
done_write:
bkpt #0
.end
|
wuxx/openocd-toolbox | 3,759 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/stm32l4x.S | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* Copyright (C) 2011 Øyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2015 Uwe Bonnes *
* bon@elektron.ikp.physik.tu-darmstadt.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m4
.thumb
.thumb_func
/* To assemble:
* arm-none-eabi-gcc -c stm32l4x.S
*
* To disassemble:
* arm-none-eabi-objdump -o stm32l4x.o
*
* To generate binary file:
* arm-none-eabi-objcopy -O binary stm32l4x.o stm32l4_flash_write_code.bin
*
* To generate include file:
* xxd -i stm32l4_flash_write_code.bin
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (64bit words)
* r4 = flash base
*
* Clobbered:
* r5 - rp
* r6/7 - temp (64-bit)
* r8 - wp, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
wait_fifo:
ldr r8, [r0, #0] /* read wp */
cmp r8, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r0, #4] /* read rp */
subs r6, r8, r5 /* number of bytes available for read in r6*/
itt mi /* if wrapped around*/
addmi r6, r1 /* add size of buffer */
submi r6, r0
cmp r6, #8 /* wait until 8 bytes are available */
bcc wait_fifo
ldr r6, STM32_PROG
str r6, [r4, #STM32_FLASH_CR_OFFSET]
ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */
strd r6, [r2], #0x08 /* write one word to dst, increment ptr */
dsb
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
bne busy /* wait more... */
tst r6, #0xfa /* PGSERR | PGPERR | PGAERR | WRPERR | PROGERR*/
bne error /* fail... */
cmp r5, r1 /* wrap rp at end of buffer */
it cs
addcs r5, r0, #8 /* skip loader args */
str r5, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement dword count */
cbz r3, exit /* loop if not done */
b wait_fifo
error:
movs r1, #0
str r1, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
STM32_PROG: .word 0x1 /* PG */
|
wuxx/openocd-toolbox | 6,486 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/mrvlqspi_write.S | /***************************************************************************
* Copyright (C) 2014 by Mahavir Jain <mjain@marvell.com> *
* *
* Adapted from (contrib/loaders/flash/lpcspifi_write.S): *
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* For compilation:
* arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -c contrib/loaders/flash/mrvlqspi_write.S
* arm-none-eabi-objcopy -O binary mrvlqspi_write.o code.bin
* Copy code.bin into mrvlqspi flash driver
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address (offset from flash base)
* r3 = count (bytes)
* r4 = page size
* r5 = qspi base address
* Clobbered:
* r7 - rp
* r8 - wp, tmp
* r9 - send/receive data
* r10 - current page end address
*/
#define CNTL 0x0
#define CONF 0x4
#define DOUT 0x8
#define DIN 0xc
#define INSTR 0x10
#define ADDR 0x14
#define RDMODE 0x18
#define HDRCNT 0x1c
#define DINCNT 0x20
#define SS_EN (1 << 0)
#define XFER_RDY (1 << 1)
#define RFIFO_EMPTY (1 << 4)
#define WFIFO_EMPTY (1 << 6)
#define WFIFO_FULL (1 << 7)
#define FIFO_FLUSH (1 << 9)
#define RW_EN (1 << 13)
#define XFER_STOP (1 << 14)
#define XFER_START (1 << 15)
#define INS_WRITE_ENABLE 0x06
#define INS_READ_STATUS 0x05
#define INS_PAGE_PROGRAM 0x02
init:
mov.w r10, #0x00
find_next_page_boundary:
add r10, r4 /* Increment to the next page */
cmp r10, r2
/* If we have not reached the next page boundary after the target address, keep going */
bls find_next_page_boundary
write_enable:
/* Flush read/write fifo's */
bl flush_fifo
/* Instruction byte 1 */
movs r8, #0x1
str r8, [r5, #HDRCNT]
/* Set write enable instruction */
movs r8, #INS_WRITE_ENABLE
str r8, [r5, #INSTR]
movs r9, #0x1
bl start_tx
bl stop_tx
page_program:
/* Instruction byte 1, Addr byte 3 */
movs r8, #0x31
str r8, [r5, #HDRCNT]
/* Todo: set addr and data pin to single */
write_address:
mov r8, r2
str r8, [r5, #ADDR]
/* Set page program instruction */
movs r8, #INS_PAGE_PROGRAM
str r8, [r5, #INSTR]
/* Start write transfer */
movs r9, #0x1
bl start_tx
wait_fifo:
ldr r8, [r0] /* read the write pointer */
cmp r8, #0 /* if it's zero, we're gonzo */
beq exit
ldr r7, [r0, #4] /* read the read pointer */
cmp r7, r8 /* wait until they are not equal */
beq wait_fifo
write:
ldrb r9, [r7], #0x01 /* Load one byte from the FIFO, increment the read pointer by 1 */
bl write_data /* send the byte to the flash chip */
cmp r7, r1 /* wrap the read pointer if it is at the end */
it cs
addcs r7, r0, #8 /* skip loader args */
str r7, [r0, #4] /* store the new read pointer */
subs r3, r3, #1 /* decrement count */
cmp r3, #0 /* Exit if we have written everything */
beq write_wait
add r2, #1 /* Increment flash address by 1 */
cmp r10, r2 /* See if we have reached the end of a page */
bne wait_fifo /* If not, keep writing bytes */
write_wait:
bl stop_tx /* Otherwise, end the command and keep going w/ the next page */
add r10, r4 /* Move up the end-of-page address by the page size*/
check_flash_busy: /* Wait for the flash to finish the previous page write */
/* Flush read/write fifo's */
bl flush_fifo
/* Instruction byte 1 */
movs r8, #0x1
str r8, [r5, #HDRCNT]
/* Continuous data in of status register */
movs r8, #0x0
str r8, [r5, #DINCNT]
/* Set write enable instruction */
movs r8, #INS_READ_STATUS
str r8, [r5, #INSTR]
/* Start read transfer */
movs r9, #0x0
bl start_tx
wait_flash_busy:
bl read_data
and.w r9, r9, #0x1
cmp r9, #0x0
bne.n wait_flash_busy
bl stop_tx
cmp r3, #0
bne.n write_enable /* If it is done, start a new page write */
b exit /* All data written, exit */
write_data: /* Send/receive 1 byte of data over QSPI */
ldr r8, [r5, #CNTL]
lsls r8, r8, #24
bmi.n write_data
str r9, [r5, #DOUT]
bx lr
read_data: /* Read 1 byte of data over QSPI */
ldr r8, [r5, #CNTL]
lsls r8, r8, #27
bmi.n read_data
ldr r9, [r5, #DIN]
bx lr
flush_fifo: /* Flush read write fifos */
ldr r8, [r5, #CONF]
orr.w r8, r8, #FIFO_FLUSH
str r8, [r5, #CONF]
flush_reset:
ldr r8, [r5, #CONF]
lsls r8, r8, #22
bmi.n flush_reset
bx lr
start_tx:
ldr r8, [r5, #CNTL]
orr.w r8, r8, #SS_EN
str r8, [r5, #CNTL]
xfer_rdy:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n xfer_rdy
ldr r8, [r5, #CONF]
bfi r8, r9, #13, #1
orr.w r8, r8, #XFER_START
str r8, [r5, #CONF]
bx lr
stop_tx:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n stop_tx
wfifo_wait:
ldr r8, [r5, #CNTL]
lsls r8, r8, #25
bpl.n wfifo_wait
ldr r8, [r5, #CONF]
orr.w r8, r8, #XFER_STOP
str r8, [r5, #CONF]
xfer_start:
ldr r8, [r5, #CONF]
lsls r8, r8, #16
bmi.n xfer_start
ss_disable:
# Disable SS_EN
ldr r8, [r5, #CNTL]
bic.w r8, r8, #SS_EN
str r8, [r5, #CNTL]
wait:
ldr r8, [r5, #CNTL]
lsls r8, r8, #30
bpl.n wait
bx lr
error:
movs r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
exit:
mov r0, r6
bkpt #0x00
.end
|
wuxx/openocd-toolbox | 5,997 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/lpcspifi_erase.S | /***************************************************************************
* Copyright (C) 2012 by George Harris *
* george@luminairecoffee.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m3
.thumb
.thumb_func
/*
* Params :
* r0 = start address, status (out)
* r1 = count
* r2 = erase command
* r3 = block size
*/
#define SSP_BASE_HIGH 0x4008
#define SSP_BASE_LOW 0x3000
#define SSP_CR0_OFFSET 0x00
#define SSP_CR1_OFFSET 0x04
#define SSP_DATA_OFFSET 0x08
#define SSP_CPSR_OFFSET 0x10
#define SSP_SR_OFFSET 0x0c
#define SSP_CLOCK_BASE_HIGH 0x4005
#define SSP_CLOCK_BASE_LOW 0x0000
#define SSP_BRANCH_CLOCK_BASE_HIGH 0x4005
#define SSP_BRANCH_CLOCK_BASE_LOW 0x2000
#define SSP_BASE_CLOCK_OFFSET 0x94
#define SSP_BRANCH_CLOCK_OFFSET 0x700
#define IOCONFIG_BASE_HIGH 0x4008
#define IOCONFIG_BASE_LOW 0x6000
#define IOCONFIG_SCK_OFFSET 0x18c
#define IOCONFIG_HOLD_OFFSET 0x190
#define IOCONFIG_WP_OFFSET 0x194
#define IOCONFIG_MISO_OFFSET 0x198
#define IOCONFIG_MOSI_OFFSET 0x19c
#define IOCONFIG_CS_OFFSET 0x1a0
#define IO_BASE_HIGH 0x400f
#define IO_BASE_LOW 0x4000
#define IO_CS_OFFSET 0xab
#define IODIR_BASE_HIGH 0x400f
#define IODIR_BASE_LOW 0x6000
#define IO_CS_DIR_OFFSET 0x14
setup: /* Initialize SSP pins and module */
mov.w r10, #IOCONFIG_BASE_LOW
movt r10, #IOCONFIG_BASE_HIGH
mov.w r8, #0xea
str.w r8, [r10, #IOCONFIG_SCK_OFFSET] /* Configure SCK pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_HOLD_OFFSET] /* Configure /HOLD pin function */
mov.w r8, #0x40
str.w r8, [r10, #IOCONFIG_WP_OFFSET] /* Configure /WP pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MISO_OFFSET] /* Configure MISO pin function */
mov.w r8, #0xed
str.w r8, [r10, #IOCONFIG_MOSI_OFFSET] /* Configure MOSI pin function */
mov.w r8, #0x44
str.w r8, [r10, #IOCONFIG_CS_OFFSET] /* Configure CS pin function */
mov.w r10, #IODIR_BASE_LOW
movt r10, #IODIR_BASE_HIGH
mov.w r8, #0x800
str r8, [r10, #IO_CS_DIR_OFFSET] /* Set CS as output */
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
mov.w r8, #0xff
str.w r8, [r10, #IO_CS_OFFSET] /* Set CS high */
mov.w r10, #SSP_CLOCK_BASE_LOW
movt r10, #SSP_CLOCK_BASE_HIGH
mov.w r8, #0x0000
movt r8, #0x0100
str.w r8, [r10, #SSP_BASE_CLOCK_OFFSET] /* Configure SSP0 base clock (use 12 MHz IRC) */
mov.w r10, #SSP_BRANCH_CLOCK_BASE_LOW
movt r10, #SSP_BRANCH_CLOCK_BASE_HIGH
mov.w r8, #0x01
str.w r8, [r10, #SSP_BRANCH_CLOCK_OFFSET] /* Configure (enable) SSP0 branch clock */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
mov.w r8, #0x07
str.w r8, [r10, #SSP_CR0_OFFSET] /* Set clock postscale */
mov.w r8, #0x02
str.w r8, [r10, #SSP_CPSR_OFFSET] /* Set clock prescale */
str.w r8, [r10, #SSP_CR1_OFFSET] /* Enable SSP in SPI mode */
write_enable:
bl cs_down
mov.w r9, #0x06 /* Send the write enable command */
bl write_data
bl cs_up
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x02 /* If the WE bit isn't set, we have a problem. */
beq error
erase:
bl cs_down
mov.w r9, r2 /* Send the erase command */
bl write_data
write_address:
lsr r9, r0, #16 /* Send the current 24-bit write address, MSB first */
bl write_data
lsr r9, r0, #8
bl write_data
mov.w r9, r0
bl write_data
bl cs_up
wait_flash_busy: /* Wait for the flash to finish the previous erase */
bl cs_down
mov.w r9, #0x05 /* Get status register */
bl write_data
mov.w r9, #0x00 /* Dummy data to clock in status */
bl write_data
bl cs_up
tst r9, #0x01 /* If it isn't done, keep waiting */
bne wait_flash_busy
subs r1, r1, #1 /* decrement count */
cbz r1, exit /* Exit if we have written everything */
add r0, r3 /* Move the address up by the block size */
b write_enable /* Start a new block erase */
write_data: /* Send/receive 1 byte of data over SSP */
mov.w r10, #SSP_BASE_LOW
movt r10, #SSP_BASE_HIGH
str.w r9, [r10, #SSP_DATA_OFFSET] /* Write supplied data to the SSP data reg */
wait_transmit:
ldr r9, [r10, #SSP_SR_OFFSET] /* Check SSP status */
tst r9, #0x0010 /* Check if BSY bit is set */
bne wait_transmit /* If still transmitting, keep waiting */
ldr r9, [r10, #SSP_DATA_OFFSET] /* Load received data */
bx lr /* Exit subroutine */
cs_up:
mov.w r8, #0xff
b cs_write
cs_down:
mov.w r8, #0x0000
cs_write:
mov.w r10, #IO_BASE_LOW
movt r10, #IO_BASE_HIGH
str.w r8, [r10, #IO_CS_OFFSET]
bx lr
error:
movs r0, #0
exit:
bkpt #0x00
.end
|
wuxx/openocd-toolbox | 2,107 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/armv4_5_cfi_intel_16.s | /***************************************************************************
* Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* Copyright (C) 2010 Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.text
.arm
.arch armv4
.section .init
/* algorithm register usage:
* r0: source address (in RAM)
* r1: target address (in Flash)
* r2: count
* r3: flash write command
* r4: status byte (returned to host)
* r5: busy test pattern
* r6: error test pattern
*/
loop:
ldrh r4, [r0], #2
strh r3, [r1]
strh r4, [r1]
busy:
ldrh r4, [r1]
and r7, r4, r5
cmp r7, r5
bne busy
tst r4, r6
bne done
subs r2, r2, #1
beq done
add r1, r1, #2
b loop
done:
b done
.end
|
wuxx/openocd-toolbox | 2,240 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/watchdog/armv7m_kinetis_wdog.s | /***************************************************************************
* Copyright (C) 2015 Tomas Vanek *
* vanekt@fbl.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
/*
Disable watchdog for Kinetis Kx and KVx
Parameters: none
Used instruction set should work on both Cortex-M4 and M0+
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
WDOG_ADDR = 0x40052000
/* WDOG registers offsets */
WDOG_STCTRLH = 0
WDOG_UNLOCK = 0x0e
WDOG_KEY1 = 0xc520
WDOG_KEY2 = 0xd928
.thumb_func
start:
/* WDOG_UNLOCK = 0xC520 */
ldr r3, =WDOG_ADDR
ldr r2, =WDOG_KEY1
strh r2, [r3, WDOG_UNLOCK]
/* WDOG_UNLOCK = 0xD928 */
ldr r2, =WDOG_KEY2
strh r2, [r3, WDOG_UNLOCK]
/* WDOG_STCTRLH clear bit 0 */
movs r4, #1
ldrh r2, [r3, WDOG_STCTRLH]
bics r2, r4
strh r2, [r3, WDOG_STCTRLH]
/* OpenOCD checks exit point address. Jump to the very end. */
b done
.pool
/* Avoid padding at .text segment end. Otherwise exit point check fails. */
.skip ( . - start + 2) & 2, 0
done:
bkpt #0
.end
|
wuxx/openocd-toolbox | 2,376 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/checksum/mips32.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
.global main
.text
.set noreorder
/* params:
* $a0 address in
* $a1 byte count
* vars
* $a0 crc
* $a1 crc data byte
* temps:
* t3 v0 a3 a2 t0 v1
*/
.ent main
main:
addiu $t4, $a0, 0 /* address in */
addiu $t2, $a1, 0 /* count */
addiu $a0, $zero, 0xffffffff /* a0 crc - result */
beq $zero, $zero, ncomp
addiu $t3, $zero, 0 /* clear bytes read */
nbyte:
lb $a1, ($t4) /* load byte from source address */
addi $t4, $t4, 1 /* inc byte count */
crc:
sll $a1, $a1, 24
lui $v0, 0x04c1
xor $a0, $a0, $a1
ori $a3, $v0, 0x1db7
addu $a2, $zero, $zero /* clear bit count */
loop:
sll $t0, $a0, 1
addiu $a2, $a2, 1 /* inc bit count */
slti $a0, $a0, 0
xor $t1, $t0, $a3
movn $t0, $t1, $a0
slti $v1, $a2, 8 /* 8bits processed */
bne $v1, $zero, loop
addu $a0, $t0, $zero
ncomp:
bne $t2, $t3, nbyte /* all bytes processed */
addiu $t3, $t3, 1
wait:
sdbbp
.end main
|
wuxx/openocd-toolbox | 1,919 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/checksum/armv4_5_crc.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
r0 - address in - crc out
r1 - char count
*/
.text
.arm
_start:
main:
mov r2, r0
mov r0, #0xffffffff /* crc */
mov r3, r1
mov r4, #0
b ncomp
nbyte:
ldrb r1, [r2, r4]
ldr r7, CRC32XOR
eor r0, r0, r1, asl #24
mov r5, #0
loop:
cmp r0, #0
mov r6, r0, asl #1
add r5, r5, #1
mov r0, r6
eorlt r0, r6, r7
cmp r5, #8
bne loop
add r4, r4, #1
ncomp:
cmp r4, r3
bne nbyte
end:
bkpt #0
CRC32XOR: .word 0x04c11db7
.end
|
wuxx/openocd-toolbox | 2,035 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/checksum/armv7m_crc.s | /***************************************************************************
* Copyright (C) 2010 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
/*
parameters:
r0 - address in - crc out
r1 - char count
*/
.text
.syntax unified
.cpu cortex-m0
.thumb
.thumb_func
.align 2
_start:
main:
mov r2, r0
movs r0, #0
mvns r0, r0
ldr r6, CRC32XOR
mov r3, r1
movs r4, #0
b ncomp
nbyte:
ldrb r1, [r2, r4]
lsls r1, r1, #24
eors r0, r0, r1
movs r5, #0
loop:
cmp r0, #0
bge notset
lsls r0, r0, #1
eors r0, r0, r6
b cont
notset:
lsls r0, r0, #1
cont:
adds r5, r5, #1
cmp r5, #8
bne loop
adds r4, r4, #1
ncomp:
cmp r4, r3
bne nbyte
bkpt #0
.align 2
CRC32XOR: .word 0x04c11db7
.end
|
wuxx/openocd-toolbox | 1,239 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/xmc1xxx/erase_check.S | /*
* Infineon XMC1000 flash sector erase check
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
*
* License: GPL-2.0+
*/
#include "xmc1xxx.S"
.macro verify_block, nvmbase, addr, tmp, tmp2
movs \tmp, #0x00
mvns \tmp, \tmp
str \tmp, [\addr, #0x0]
str \tmp, [\addr, #0x4]
str \tmp, [\addr, #0x8]
str \tmp, [\addr, #0xC]
busy_wait \nvmbase, \tmp, \tmp2
.endm
.macro erase_check, nvmbase, addr, end, tmp, tmp2
ldrh \tmp, [\nvmbase, #NVMCONF]
movs \tmp2, #NVMCONF_HRLEV_MASK
mvns \tmp2, \tmp2
ands \tmp, \tmp, \tmp2
movs \tmp2, #NVMCONF_HRLEV_HRE
orrs \tmp, \tmp, \tmp2
strh \tmp, [\nvmbase, #NVMCONF]
movs \tmp, #NVMPROG_ACTION_VERIFY_CONTINUOUS
strh \tmp, [\nvmbase, #NVMPROG]
2001:
verify_block \nvmbase, \addr, \tmp, \tmp2
ldrh \tmp, [\nvmbase, #NVMSTATUS]
movs \tmp2, #NVMSTATUS_VERR_MASK
ands \tmp, \tmp, \tmp2
cmp \tmp, #NVMSTATUS_VERR_NOFAIL
bne 2010f
adds \addr, \addr, #NVM_BLOCK_SIZE
cmp \addr, \end
blt 2001b
2010:
movs \tmp, #NVMPROG_ACTION_IDLE
strh \tmp, [\nvmbase, #NVMPROG]
.endm
/*
* r0 = 0x40050000
* r1 = e.g. 0x10001000
* r2 = e.g. 0x10002000
* NVMPROG.ACTION = 0x00
*/
erase_check:
erase_check r0, r1, r2, r3, r4
bkpt #0
|
wuxx/openocd-toolbox | 1,023 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/xmc1xxx/write.S | /*
* Infineon XMC1000 flash write
*
* Copyright (c) 2016 Andreas Färber
*
* Based on XMC1100 AA-Step Reference Manual
*
* License: GPL-2.0+
*/
#include "xmc1xxx.S"
.macro write_block, nvmbase, dest, src, tmp, tmp2
ldr \tmp, [\src, #0x0]
str \tmp, [\dest, #0x0]
ldr \tmp, [\src, #0x4]
str \tmp, [\dest, #0x4]
ldr \tmp, [\src, #0x8]
str \tmp, [\dest, #0x8]
ldr \tmp, [\src, #0xc]
str \tmp, [\dest, #0xc]
busy_wait \nvmbase, \tmp, \tmp2
.endm
.macro write, nvmbase, dest, src, count, tmp, tmp2
movs \tmp, #NVMPROG_ACTION_WRITE_CONTINUOUS
strh \tmp, [\nvmbase, #NVMPROG]
1001:
write_block \nvmbase, \dest, \src, \tmp, \tmp2
adds \dest, \dest, #NVM_BLOCK_SIZE
adds \src, \src, #NVM_BLOCK_SIZE
subs \count, \count, #1
cmp \count, #0
bgt 1001b
movs \tmp, #NVMPROG_ACTION_IDLE
strh \tmp, [\nvmbase, #NVMPROG]
.endm
/*
* r0 = 0x40050000
* r1 = e.g. 0x10001000
* r2 = e.g. 0x20000000
* r3 = e.g. 1
* NVMPROG.ACTION = 0x00
*/
write:
write r0, r1, r2, r3, r4, r5
bkpt #0
|
wuxx/openocd-toolbox | 1,238 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/fm4/erase.S | /*
* Spansion FM4 flash sector erase algorithm
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
#include "fm4.h"
#define RESULT_OKAY 0
#define RESULT_NONE 1
#define RESULT_TIMEOUT 2
.macro busy_wait, res, addr, tmp1, tmp2, tmp3
ldrb \tmp1, [\addr] /* ignore */
1001:
ldrb \tmp1, [\addr]
ldrb \tmp2, [\addr]
and \tmp3, \tmp1, #FLASH_TOGG
and \tmp2, \tmp2, #FLASH_TOGG
cmp \tmp3, \tmp2
beq 1010f
and \tmp2, \tmp1, #FLASH_TLOV
cmp \tmp2, #0
beq 1001b
ldrb \tmp1, [\addr]
ldrb \tmp2, [\addr]
and \tmp3, \tmp1, #FLASH_TOGG
and \tmp2, \tmp2, #FLASH_TOGG
cmp \tmp3, \tmp2
beq 1010f
mov \res, #RESULT_TIMEOUT
bkpt #0
1010:
mov \res, #RESULT_OKAY
.endm
.macro erase, cmdseqaddr1, cmdseqaddr2, sa, res, tmp1, tmp2, tmp3
mov \res, #RESULT_NONE
mov \tmp1, #0xAA
strh \tmp1, [\cmdseqaddr1]
mov \tmp2, #0x55
strh \tmp2, [\cmdseqaddr2]
mov \tmp3, #0x80
strh \tmp3, [\cmdseqaddr1]
strh \tmp1, [\cmdseqaddr1]
strh \tmp2, [\cmdseqaddr2]
mov \tmp3, #0x30
strh \tmp3, [\sa]
busy_wait \res, \sa, \tmp1, \tmp2, \tmp3
.endm
/* r0 = 0xAA8
* r1 = 0x554
* r2 = SA
* r3 = result
*/
erase:
erase r0, r1, r2, r3, r4, r5, r6
bkpt #0
data:
|
wuxx/openocd-toolbox | 1,433 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/fm4/write.S | /*
* Spansion FM4 flash write algorithm
*
* Copyright (c) 2015 Andreas Färber
*
* Based on S6E2CC_MN709-00007 for S6E2CC/C5/C4/C3/C2/C1 series
*/
#include "fm4.h"
#define RESULT_OKAY 0
#define RESULT_NONE 1
#define RESULT_TIMEOUT 2
.macro busy_wait, res, addr, data, tmp1, tmp2, tmp3
ldrb \tmp1, [\addr] /* ignore */
and \tmp2, \data, #FLASH_DPOL
1001:
ldrb \tmp1, [\addr]
and \tmp3, \tmp1, #FLASH_DPOL
cmp \tmp3, \tmp2
beq 1010f
and \tmp3, \tmp1, #FLASH_TLOV
cmp \tmp3, #0
beq 1001b
ldrb \tmp1, [\addr]
and \tmp3, \tmp1, #FLASH_DPOL
cmp \tmp3, \tmp2
beq 1010f
mov \res, #RESULT_TIMEOUT
bkpt #0
1010:
.endm
.macro write_one, res, cmdseqaddr1, cmdseqaddr2, pa, pd, tmp1, tmp2, tmp3
mov \tmp1, #0xAA
strh \tmp1, [\cmdseqaddr1]
mov \tmp1, #0x55
strh \tmp1, [\cmdseqaddr2]
mov \tmp1, #0xA0
strh \tmp1, [\cmdseqaddr1]
strh \pd, [\pa]
busy_wait \res, \pa, \pd, \tmp1, \tmp2, \tmp3
.endm
.macro write, cmdseqaddr1, cmdseqaddr2, dest, src, cnt, res, tmp1, tmp2, tmp3, tmp4
mov \res, #RESULT_NONE
2001:
cbz \cnt, 2010f
ldrh \tmp1, [\src]
write_one \res, \cmdseqaddr1, \cmdseqaddr2, \dest, \tmp1, \tmp2, \tmp3, \tmp4
sub \cnt, \cnt, #1
add \dest, \dest, #2
add \src, \src, #2
b 2001b
2010:
mov \res, #RESULT_OKAY
.endm
/* r0 = 0xAA8
* r1 = 0x554
* r2 = dest
* r3 = src
* r4 = cnt
* r5 = result
*/
write:
write r0, r1, r2, r3, r4, r5, r6, r7, r8, r9
bkpt #0
data:
|
wuxx/openocd-toolbox | 2,767 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/kinetis/kinetis_flash.s | /***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* Copyright (C) 2016 by Tomas Vanek *
* vanekt@fbl.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
/* Params:
* r0 = flash destination address in/out
* r1 = longword count
* r2 = workarea start address
* r3 = workarea end address
* r4 = FTFx base
*/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
/* r5 = rp
* r6 = wp, tmp
* r7 = tmp
*/
/* old longword algo: 6.680 KiB/s @ adapter_khz 2000
* this async algo: 19.808 KiB/s @ adapter_khz 2000
*/
FTFx_FSTAT = 0
FTFx_FCCOB3 = 4
FTFx_FCCOB0 = 7
FTFx_FCCOB7 = 8
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
str r0, [r4, #FTFx_FCCOB3] /* set flash address */
mov r7, #6
strb r7, [r4, #FTFx_FCCOB0] /* flash command */
ldr r7, [r5] /* set longword data = *rp */
str r7, [r4, #FTFx_FCCOB7]
mov r7, #128
strb r7, [r4, #FTFx_FSTAT]
add r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc no_wrap
mov r5, r2
add r5, #8
no_wrap:
str r5, [r2, #4] /* Store rp */
wait_ccif:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldrb r6, [r4, #FTFx_FSTAT]
tst r6, r7
beq wait_ccif
mov r7, #0x70
tst r6, r7
bne error
add r0, #4 /* flash address += 4, do not increment before err check */
sub r1, #1 /* word_count-- */
cmp r1, #0
bne wait_fifo
b exit
error:
mov r5, #0
str r5, [r2, #4] /* set rp = 0 on error */
exit:
bkpt #0
|
wuxx/openocd-toolbox | 6,878 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/at91sam7x/crt.s | /****************************************************************************
* Copyright (c) 2006 by Michael Fischer. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the author nor the names of its contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
****************************************************************************
*
* History:
*
* 18.12.06 mifi First Version
* The hardware initialization is based on the startup file
* crtat91sam7x256_rom.S from NutOS 4.2.1.
* Therefore partial copyright by egnite Software GmbH.
****************************************************************************/
/*
* Some defines for the program status registers
*/
ARM_MODE_USER = 0x10 /* Normal User Mode */
ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
ARM_MODE_MASK = 0x1F
I_BIT = 0x80 /* disable IRQ when I bit is set */
F_BIT = 0x40 /* disable IRQ when I bit is set */
/*
* Register Base Address
*/
AIC_BASE = 0xFFFFF000
AIC_EOICR_OFF = 0x130
AIC_IDCR_OFF = 0x124
RSTC_MR = 0xFFFFFD08
RSTC_KEY = 0xA5000000
RSTC_URSTEN = 0x00000001
WDT_BASE = 0xFFFFFD40
WDT_MR_OFF = 0x00000004
WDT_WDDIS = 0x00008000
MC_BASE = 0xFFFFFF00
MC_FMR_OFF = 0x00000060
MC_FWS_1FWS = 0x00480100
.section .vectors,"ax"
.code 32
/****************************************************************************/
/* Vector table and reset entry */
/****************************************************************************/
_vectors:
ldr pc, ResetAddr /* Reset */
ldr pc, UndefAddr /* Undefined instruction */
ldr pc, SWIAddr /* Software interrupt */
ldr pc, PAbortAddr /* Prefetch abort */
ldr pc, DAbortAddr /* Data abort */
ldr pc, ReservedAddr /* Reserved */
ldr pc, IRQAddr /* IRQ interrupt */
ldr pc, FIQAddr /* FIQ interrupt */
ResetAddr: .word ResetHandler
UndefAddr: .word UndefHandler
SWIAddr: .word SWIHandler
PAbortAddr: .word PAbortHandler
DAbortAddr: .word DAbortHandler
ReservedAddr: .word 0
IRQAddr: .word IRQHandler
FIQAddr: .word FIQHandler
.ltorg
.section .init, "ax"
.code 32
.global ResetHandler
.global ExitFunction
.extern main
/****************************************************************************/
/* Reset handler */
/****************************************************************************/
ResetHandler:
/*
* The watchdog is enabled after processor reset. Disable it.
*/
ldr r1, =WDT_BASE
ldr r0, =WDT_WDDIS
str r0, [r1, #WDT_MR_OFF]
/*
* Enable user reset: assertion length programmed to 1ms
*/
ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
ldr r1, =RSTC_MR
str r0, [r1, #0]
/*
* Use 2 cycles for flash access.
*/
ldr r1, =MC_BASE
ldr r0, =MC_FWS_1FWS
str r0, [r1, #MC_FMR_OFF]
/*
* Disable all interrupts. Useful for debugging w/o target reset.
*/
ldr r1, =AIC_BASE
mvn r0, #0
str r0, [r1, #AIC_EOICR_OFF]
str r0, [r1, #AIC_IDCR_OFF]
/*
* Setup a stack for each mode
*/
msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
ldr sp, =__stack_und_end
msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
ldr sp, =__stack_abt_end
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
ldr sp, =__stack_fiq_end
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
ldr sp, =__stack_irq_end
msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
ldr sp, =__stack_svc_end
/*
* Clear .bss section
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
ldr r3, =0
bss_clear_loop:
cmp r1, r2
strne r3, [r1], #+4
bne bss_clear_loop
/*
* Jump to main
*/
mrs r0, cpsr
bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
msr cpsr, r0
mov r0, #0 /* No arguments */
mov r1, #0 /* No arguments */
ldr r2, =main
mov lr, pc
bx r2 /* And jump... */
ExitFunction:
nop
nop
nop
b ExitFunction
/****************************************************************************/
/* Default interrupt handler */
/****************************************************************************/
UndefHandler:
b UndefHandler
SWIHandler:
b SWIHandler
PAbortHandler:
b PAbortHandler
DAbortHandler:
b DAbortHandler
IRQHandler:
b IRQHandler
FIQHandler:
b FIQHandler
.weak ExitFunction
.weak UndefHandler, PAbortHandler, DAbortHandler
.weak IRQHandler, FIQHandler
.ltorg
/*** EOF ***/
|
wuxx/openocd-toolbox | 4,230 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/kinetis_ke/kinetis_ke_flash.s | /***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
/* Params:
* r0 = flash destination address, status
* r1 = longword count
* r2 = workarea start address
* r3 = workarea end address
*/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
/* r5 = rp
* r6 = wp, tmp
* r7 = tmp
*/
wait_fifo:
ldr r6, [r2, #0] /* read wp */
cmp r6, #0 /* abort if wp == 0 */
beq exit
ldr r5, [r2, #4] /* read rp */
cmp r5, r6 /* wait until rp != wp */
beq wait_fifo
ldr r6, fstat /* Clear error flags */
mov r7, #48
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 0 */
mov r7, #0
strb r7, [r6]
ldr r6, fccobhi /* Program FLASH command */
mov r7, #6 /* FCCOBHI = 6 */
strb r7, [r6]
lsr r7, r0, #16 /* FCCOBLO = flash destination address >> 16 */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* Index for lower byte address bits[15:0] */
mov r7, #1
strb r7, [r6] /* FCCOBIX = 1*/
uxtb r7, r0 /* Memory address bits[15:0] */
ldr r6, fccoblo
strb r7, [r6] /* FCCOBLO = flash destination address */
lsr r7, r0, #8
ldr r6, fccobhi
strb r7, [r6] /* FCCOBHI = flash destination address >> 8 */
ldr r6, fccobix /* FCCOBIX = 2 */
mov r7, #2
strb r7, [r6]
ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5] /* FCCOBLO = rp */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 3 */
mov r7, #3
strb r7, [r6]
ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
ldr r6, fccoblo
strb r7, [r6]
sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
add r0, r0, #4 /* flash address += 4 */
add r5, r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc no_wrap
mov r5, r2
add r5, r5, #8
no_wrap:
cmp r1, #0 /* Done? */
beq execute
ldr r6, [r2, #0] /* read wp */
cmp r6, r5
beq execute /* execute if rp == wp */
ldr r6, fccobix /* FCCOBIX = 4 */
mov r7, #4
strb r7, [r6]
ldrb r7, [r5, #1] /* FCCOBHI = rp >> 8 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5] /* FCCOBLO = rp */
ldr r6, fccoblo
strb r7, [r6]
ldr r6, fccobix /* FCCOBIX = 5 */
mov r7, #5
strb r7, [r6]
ldrb r7, [r5, #3] /* FCCOBHI = rp >> 24 */
ldr r6, fccobhi
strb r7, [r6]
ldrb r7, [r5, #2] /* FCCOBLO = rp >> 16 */
ldr r6, fccoblo
strb r7, [r6]
sub r1, r1, #1 /* Two words (4 bytes) queued, decrement counter */
add r0, r0, #4 /* flash address += 4 */
add r5, r5, #4 /* rp += 4 */
cmp r5, r3 /* Wrap? */
bcc execute
mov r5, r2
add r5, r5, #8
execute:
ldr r6, fstat /* Launch the command */
mov r7, #128
strb r7, [r6]
wait_busy:
ldr r6, fstat
ldrb r6, [r6] /* Wait until finished */
tst r6, r7
beq wait_busy
mov r7, #48 /* Check error */
tst r6, r7
bne error
mov r6, #0 /* Clear error */
str r5, [r2, #4] /* Store rp */
cmp r1, #0 /* Done? */
beq done
b wait_fifo
error:
mov r0, #0
str r0, [r2, #4] /* set rp = 0 on error */
done:
mov r0, r6 /* Set result code */
bkpt #0
.align 2
fstat:
.word 0
fccobix:
.word 0
fccobhi:
.word 0
fccoblo:
.word 0
|
wuxx/openocd-toolbox | 1,584 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/flash/kinetis_ke/kinetis_ke_watchdog.s | /***************************************************************************
* Copyright (C) 2015 by Ivan Meleca *
* ivan@artekit.eu *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
.text
.cpu cortex-m0plus
.code 16
.thumb_func
.align 2
ldr r3, wdog_cs1
mov r2, #127
ldrb r5, [r3]
ldrb r4, [r3, #1]
and r2, r5
ldr r5, unlock1
ldrh r0, [r3, #4]
ldrh r1, [r3, #6]
strh r5, [r3, #2]
ldr r5, unlock2
strh r5, [r3, #2]
strb r4, [r3, #1]
strh r0, [r3, #4]
strh r1, [r3, #6]
strb r2, [r3]
bkpt #0
.align 2
wdog_cs1:
.word 0x40052000 // Watchdog Control and Status Register 1
unlock1:
.word 0x20C5 // 1st unlock word
unlock2:
.word 0x28D9 // 2nd unlock word
|
wuxx/openocd-toolbox | 13,426 | OpenOCD-20190426-0.10.0/share/openocd/contrib/loaders/debug/xscale/debug_handler.S | /***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#include "protocol.h"
.text
.align 4
@ Disable thumb mode
.code 32
@ send word to debugger
.macro m_send_to_debugger reg
1:
mrc p14, 0, r15, c14, c0, 0
bvs 1b
mcr p14, 0, \reg, c8, c0, 0
.endm
@ receive word from debugger
.macro m_receive_from_debugger reg
1:
mrc p14, 0, r15, c14, c0, 0
bpl 1b
mrc p14, 0, \reg, c9, c0, 0
.endm
@ save register on debugger, small
.macro m_small_save_reg reg
mov r0, \reg
bl send_to_debugger
.endm
@ save status register on debugger, small
.macro m_small_save_psr
mrs r0, spsr
bl send_to_debugger
.endm
@ wait for all outstanding coprocessor accesses to complete
.macro m_cpwait
mrc p15, 0, r0, c2, c0, 0
mov r0, r0
sub pc, pc, #4
.endm
.global reset_handler
.global undef_handler
.global swi_handler
.global prefetch_abort_handler
.global data_abort_handler
.global irq_handler
.global fiq_handler
.section .part1 , "ax"
reset_handler:
@ read DCSR
mrc p14, 0, r13, c10, c0
@ check if global enable bit (GE) is set
ands r13, r13, #0x80000000
bne debug_handler
@ set global enable bit (GE)
mov r13, #0xc0000000
mcr p14, 0, r13, c10, c0
debug_handler:
@ save r0 without modifying other registers
m_send_to_debugger r0
@ save lr (program PC) without branching (use macro)
m_send_to_debugger r14
@ save non-banked registers and spsr (program CPSR)
m_small_save_reg r1
m_small_save_reg r2
m_small_save_reg r3
m_small_save_reg r4
m_small_save_reg r5
m_small_save_reg r6
m_small_save_reg r7
m_small_save_psr
mrs r0, spsr
@ prepare program PSR for debug use (clear Thumb, set I/F to disable interrupts)
bic r0, r0, #PSR_T
orr r0, r0, #(PSR_I | PSR_F)
@ examine mode bits
and r1, r0, #MODE_MASK
cmp r1, #MODE_USR
bne not_user_mode
@ replace USR mode with SYS
bic r0, r0, #MODE_MASK
orr r0, r0, #MODE_SYS
not_user_mode:
b save_banked_registers
@ command loop
@ wait for command from debugger, than execute desired function
get_command:
bl receive_from_debugger
@ 0x0n - register access
cmp r0, #0x0
beq get_banked_registers
cmp r0, #0x1
beq set_banked_registers
@ 0x1n - read memory
cmp r0, #0x11
beq read_byte
cmp r0, #0x12
beq read_half_word
cmp r0, #0x14
beq read_word
@ 0x2n - write memory
cmp r0, #0x21
beq write_byte
cmp r0, #0x22
beq write_half_word
cmp r0, #0x24
beq write_word
@ 0x3n - program execution
cmp r0, #0x30
beq resume
cmp r0, #0x31
beq resume_w_trace
@ 0x4n - coprocessor access
cmp r0, #0x40
beq read_cp_reg
cmp r0, #0x41
beq write_cp_reg
@ 0x5n - cache and mmu functions
cmp r0, #0x50
beq clean_d_cache
cmp r0, #0x51
beq invalidate_d_cache
cmp r0, #0x52
beq invalidate_i_cache
cmp r0, #0x53
beq cpwait
@ 0x6n - misc functions
cmp r0, #0x60
beq clear_sa
cmp r0, #0x61
beq read_trace_buffer
cmp r0, #0x62
beq clean_trace_buffer
@ return (back to get_command)
b get_command
@ ----
@ resume program execution
resume:
@ restore CPSR (SPSR_dbg)
bl receive_from_debugger
msr spsr, r0
@ restore registers (r7 - r0)
bl receive_from_debugger @ r7
mov r7, r0
bl receive_from_debugger @ r6
mov r6, r0
bl receive_from_debugger @ r5
mov r5, r0
bl receive_from_debugger @ r4
mov r4, r0
bl receive_from_debugger @ r3
mov r3, r0
bl receive_from_debugger @ r2
mov r2, r0
bl receive_from_debugger @ r1
mov r1, r0
bl receive_from_debugger @ r0
@ resume addresss
m_receive_from_debugger lr
@ branch back to application code, restoring CPSR
subs pc, lr, #0
@ get banked registers
@ receive mode bits from host, then run into save_banked_registers to
get_banked_registers:
bl receive_from_debugger
@ save banked registers
@ r0[4:0]: desired mode bits
save_banked_registers:
@ backup CPSR
mrs r7, cpsr
msr cpsr_c, r0
nop
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ backup banked registers
m_send_to_debugger r8
m_send_to_debugger r9
m_send_to_debugger r10
m_send_to_debugger r11
m_send_to_debugger r12
m_send_to_debugger r13
m_send_to_debugger r14
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_save
@ backup SPSR
mrs r0, spsr
m_send_to_debugger r0
no_spsr_to_save:
@ restore CPSR for SDS
msr cpsr_c, r7
nop
@ return
b get_command
@ ----
@ set banked registers
@ receive mode bits from host, then run into save_banked_registers to
set_banked_registers:
bl receive_from_debugger
@ restore banked registers
@ r0[4:0]: desired mode bits
restore_banked_registers:
@ backup CPSR
mrs r7, cpsr
msr cpsr_c, r0
nop
@ keep current mode bits in r1 for later use
and r1, r0, #MODE_MASK
@ set banked registers
m_receive_from_debugger r8
m_receive_from_debugger r9
m_receive_from_debugger r10
m_receive_from_debugger r11
m_receive_from_debugger r12
m_receive_from_debugger r13
m_receive_from_debugger r14
@ if not in SYS mode (or USR, which we replaced with SYS before)
cmp r1, #MODE_SYS
beq no_spsr_to_restore
@ set SPSR
m_receive_from_debugger r0
msr spsr, r0
no_spsr_to_restore:
@ restore CPSR for SDS
msr cpsr_c, r7
nop
@ return
b get_command
@ ----
read_byte:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
rb_loop:
ldrb r0, [r2], #1
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
bl send_to_debugger
subs r1, r1, #1
bne rb_loop
@ return
b get_command
@ ----
read_half_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
rh_loop:
ldrh r0, [r2], #2
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
bl send_to_debugger
subs r1, r1, #1
bne rh_loop
@ return
b get_command
@ ----
read_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
rw_loop:
ldr r0, [r2], #4
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
bl send_to_debugger
subs r1, r1, #1
bne rw_loop
@ return
b get_command
@ ----
write_byte:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
wb_loop:
bl receive_from_debugger
strb r0, [r2], #1
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne wb_loop
@ return
b get_command
@ ----
write_half_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
wh_loop:
bl receive_from_debugger
strh r0, [r2], #2
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne wh_loop
@ return
b get_command
@ ----
write_word:
@ r2: address
bl receive_from_debugger
mov r2, r0
@ r1: count
bl receive_from_debugger
mov r1, r0
ww_loop:
bl receive_from_debugger
str r0, [r2], #4
@ drain write- (and fill-) buffer to work around XScale errata
mcr p15, 0, r8, c7, c10, 4
subs r1, r1, #1
bne ww_loop
@ return
b get_command
@ ----
clear_sa:
@ read DCSR
mrc p14, 0, r0, c10, c0
@ clear SA bit
bic r0, r0, #0x20
@ write DCSR
mcr p14, 0, r0, c10, c0
@ return
b get_command
@ ----
clean_d_cache:
@ r0: cache clean area
bl receive_from_debugger
mov r1, #1024
clean_loop:
mcr p15, 0, r0, c7, c2, 5
add r0, r0, #32
subs r1, r1, #1
bne clean_loop
@ return
b get_command
@ ----
invalidate_d_cache:
mcr p15, 0, r0, c7, c6, 0
@ return
b get_command
@ ----
invalidate_i_cache:
mcr p15, 0, r0, c7, c5, 0
@ return
b get_command
@ ----
cpwait:
m_cpwait
@return
b get_command
@ ----
.section .part2 , "ax"
read_cp_reg:
@ requested cp register
bl receive_from_debugger
adr r1, read_cp_table
add pc, r1, r0, lsl #3
read_cp_table:
mrc p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID
b read_cp_reg_reply
mrc p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE
b read_cp_reg_reply
mrc p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL
b read_cp_reg_reply
mrc p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL
b read_cp_reg_reply
mrc p15, 0, r0, c2, c0, 0 @ XSCALE_TTB
b read_cp_reg_reply
mrc p15, 0, r0, c3, c0, 0 @ XSCALE_DAC
b read_cp_reg_reply
mrc p15, 0, r0, c5, c0, 0 @ XSCALE_FSR
b read_cp_reg_reply
mrc p15, 0, r0, c6, c0, 0 @ XSCALE_FAR
b read_cp_reg_reply
mrc p15, 0, r0, c13, c0, 0 @ XSCALE_PID
b read_cp_reg_reply
mrc p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS
b read_cp_reg_reply
mrc p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0
b read_cp_reg_reply
mrc p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1
b read_cp_reg_reply
mrc p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0
b read_cp_reg_reply
mrc p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1
b read_cp_reg_reply
mrc p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON
b read_cp_reg_reply
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
b read_cp_reg_reply
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0
b read_cp_reg_reply
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1
b read_cp_reg_reply
mrc p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR
b read_cp_reg_reply
read_cp_reg_reply:
bl send_to_debugger
@ return
b get_command
@ ----
write_cp_reg:
@ requested cp register
bl receive_from_debugger
mov r1, r0
@ value to be written
bl receive_from_debugger
adr r2, write_cp_table
add pc, r2, r1, lsl #3
write_cp_table:
mcr p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID (0x0)
b get_command
mcr p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE (0x1)
b get_command
mcr p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL (0x2)
b get_command
mcr p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL (0x3)
b get_command
mcr p15, 0, r0, c2, c0, 0 @ XSCALE_TTB (0x4)
b get_command
mcr p15, 0, r0, c3, c0, 0 @ XSCALE_DAC (0x5)
b get_command
mcr p15, 0, r0, c5, c0, 0 @ XSCALE_FSR (0x6)
b get_command
mcr p15, 0, r0, c6, c0, 0 @ XSCALE_FAR (0x7)
b get_command
mcr p15, 0, r0, c13, c0, 0 @ XSCALE_PID (0x8)
b get_command
mcr p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS (0x9)
b get_command
mcr p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0 (0xa)
b get_command
mcr p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1 (0xb)
b get_command
mcr p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0 (0xc)
b get_command
mcr p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1 (0xd)
b get_command
mcr p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON (0xe)
b get_command
mcr p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG (0xf)
b get_command
mcr p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
b get_command
mcr p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
b get_command
mcr p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR (0x12)
b get_command
@ ----
read_trace_buffer:
@ dump 256 entries from trace buffer
mov r1, #256
read_tb_loop:
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
bl send_to_debugger
subs r1, r1, #1
bne read_tb_loop
@ dump checkpoint register 0
mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
bl send_to_debugger
@ dump checkpoint register 1
mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
bl send_to_debugger
@ return
b get_command
@ ----
clean_trace_buffer:
@ clean 256 entries from trace buffer
mov r1, #256
clean_tb_loop:
mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG
subs r1, r1, #1
bne clean_tb_loop
@ return
b get_command
@ ----
@ resume program execution with trace buffer enabled
resume_w_trace:
@ restore CPSR (SPSR_dbg)
bl receive_from_debugger
msr spsr, r0
@ restore registers (r7 - r0)
bl receive_from_debugger @ r7
mov r7, r0
bl receive_from_debugger @ r6
mov r6, r0
bl receive_from_debugger @ r5
mov r5, r0
bl receive_from_debugger @ r4
mov r4, r0
bl receive_from_debugger @ r3
mov r3, r0
bl receive_from_debugger @ r2
mov r2, r0
bl receive_from_debugger @ r1
mov r1, r0
bl receive_from_debugger @ r0
@ resume addresss
m_receive_from_debugger lr
mrc p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
orr r13, r13, #1
mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
@ branch back to application code, restoring CPSR
subs pc, lr, #0
undef_handler:
swi_handler:
prefetch_abort_handler:
data_abort_handler:
irq_handler:
fiq_handler:
1:
b 1b
send_to_debugger:
m_send_to_debugger r0
mov pc, lr
receive_from_debugger:
m_receive_from_debugger r0
mov pc, lr
|
wuxx/nanoDAP | 12,797 | software/DAPLink/source/rtos2/RTX/Source/ARM/irq_armv8mml.s | ;/*
; * Copyright (c) 2016-2020 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv8M Mainline Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
IF :LNOT::DEF:DOMAIN_NS
DOMAIN_NS EQU 0
ENDIF
IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16")
FPU_USED EQU 1
ELSE
FPU_USED EQU 0
ENDIF
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
IF DOMAIN_NS = 1
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
ENDIF
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STM R12,{R0-R1} ; Store function return values
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
IF FPU_USED = 1
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch
ELSE
CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
ENDIF
SVC_ContextSave
IF DOMAIN_NS = 1
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN
ENDIF
SVC_ContextSave1
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
ENDIF
SVC_ContextSave2
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information
SVC_ContextSwitch
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore
IF DOMAIN_NS = 1
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore1
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
MSR PSPLIM,R0 ; Set PSPLIM
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
IF DOMAIN_NS = 1
TST LR,#0x40 ; Check domain of interrupted thread
BNE SVC_ContextRestore2 ; Branch if secure
ENDIF
IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
ENDIF
LDMIA R0!,{R4-R11} ; Restore R4..R11
SVC_ContextRestore2
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
B Sys_Context
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
B Sys_Context
ALIGN
ENDP
Sys_Context PROC
EXPORT Sys_Context
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
IF DOMAIN_NS = 1
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
ENDIF
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
Sys_ContextSave
IF DOMAIN_NS = 1
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN
Sys_ContextSave1
TST LR,#0x40 ; Check domain of interrupted thread
IT NE
MRSNE R0,PSP ; Get PSP
BNE Sys_ContextSave3 ; Branch if secure
ENDIF
Sys_ContextSave2
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
ENDIF
Sys_ContextSave3
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information
Sys_ContextSwitch
STR R2,[R3] ; osRtxInfo.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
Sys_ContextRestore
IF DOMAIN_NS = 1
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
ENDIF
Sys_ContextRestore1
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
MSR PSPLIM,R0 ; Set PSPLIM
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
IF DOMAIN_NS = 1
TST LR,#0x40 ; Check domain of interrupted thread
BNE Sys_ContextRestore2 ; Branch if secure
ENDIF
IF FPU_USED = 1
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
ENDIF
LDMIA R0!,{R4-R11} ; Restore R4..R11
Sys_ContextRestore2
MSR PSP,R0 ; Set PSP
Sys_ContextExit
BX LR ; Exit from handler
ALIGN
ENDP
END
|
wuxx/nanoDAP | 6,655 | software/DAPLink/source/rtos2/RTX/Source/ARM/irq_cm4f.s | ;/*
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: Cortex-M4F Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CBNZ R1,SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STM R12,{R0-R1} ; Store function return values
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch
SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
SVC_ContextSwitch
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore
LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
ALIGN
ENDP
END
|
wuxx/nanoDAP | 5,639 | software/DAPLink/source/rtos2/RTX/Source/ARM/irq_cm3.s | ;/*
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: Cortex-M3 Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CBNZ R1,SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STM R12,{R0-R1} ; Store function return values
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11
STR R12,[R1,#TCB_SP_OFS] ; Store SP
SVC_ContextSwitch
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
ALIGN
ENDP
END
|
wuxx/nanoDAP | 6,895 | software/DAPLink/source/rtos2/RTX/Source/ARM/irq_cm0.s | ;/*
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: Cortex-M0 Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP ; Branch if return stack is MSP
MRS R0,PSP ; Get PSP
SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STMIA R2!,{R0-R1} ; Store function return values
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
CMP R1,#0
BEQ SVC_ContextSwitch ; Branch if running thread is deleted
SVC_ContextSave
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
MOVS R0,#~0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler
SVC_MSP
MRS R0,MSP ; Get MSP
B SVC_Number
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] ; Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
BX LR ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B SVC_Context
ALIGN
ENDP
END
|
wuxx/nanoDAP | 14,255 | software/DAPLink/source/rtos2/RTX/Source/ARM/irq_armv8mbl.s | ;/*
; * Copyright (c) 2016-2020 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv8M Baseline Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
IF :LNOT::DEF:DOMAIN_NS
DOMAIN_NS EQU 0
ENDIF
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
PRESERVE8
THUMB
AREA |.constdata|, DATA, READONLY
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
AREA |.text|, CODE, READONLY
SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
IF DOMAIN_NS = 1
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
ENDIF
MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP ; Branch if return stack is MSP
MRS R0,PSP ; Get PSP
SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R7 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STMIA R2!,{R0-R1} ; Store function return values
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
SVC_ContextSave
IF DOMAIN_NS = 1
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,R7} ; Save registers
MOV R7,LR ; Get EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
MOV LR,R7 ; Set EXC_RETURN
POP {R1,R2,R3,R7} ; Restore registers
ENDIF
SVC_ContextSave1
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Calculate SP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
SVC_ContextSave2
MOV R0,LR ; Get EXC_RETURN
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
STRB R0,[R1] ; Store stack frame information
SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore
IF DOMAIN_NS = 1
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
ENDIF
SVC_ContextRestore1
MOV R1,R2
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
LDRB R0,[R1] ; Load stack frame information
MOVS R1,#0xFF
MVNS R1,R1 ; R1=0xFFFFFF00
ORRS R0,R1
MOV LR,R0 ; Set EXC_RETURN
IF DOMAIN_NS = 1
LSLS R0,R0,#25 ; Check domain of interrupted thread
BPL SVC_ContextRestore2 ; Branch if non-secure
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
MSR PSP,R0 ; Set PSP
BX LR ; Exit from handler
ELSE
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
MSR PSPLIM,R0 ; Set PSPLIM
ENDIF
SVC_ContextRestore2
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
SVC_Exit
BX LR ; Exit from handler
SVC_MSP
MRS R0,MSP ; Get MSP
B SVC_Number
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] ; Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R2,R3} ; Restore SP and EXC_RETURN
STR R0,[R2] ; Store function return value
MOV LR,R3 ; Set EXC_RETURN
BX LR ; Return from handler
ALIGN
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B Sys_Context
ALIGN
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
B Sys_Context
ALIGN
ENDP
Sys_Context PROC
EXPORT Sys_Context
IMPORT osRtxInfo
IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
ENDIF
IF DOMAIN_NS = 1
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
ENDIF
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ Sys_ContextExit ; Branch when threads are the same
Sys_ContextSave
IF DOMAIN_NS = 1
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,R7} ; Save registers
MOV R7,LR ; Get EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
MOV LR,R7 ; Set EXC_RETURN
POP {R1,R2,R3,R7} ; Restore registers
Sys_ContextSave1
MOV R0,LR ; Get EXC_RETURN
LSLS R0,R0,#25 ; Check domain of interrupted thread
BPL Sys_ContextSave2 ; Branch if non-secure
MRS R0,PSP ; Get PSP
STR R0,[R1,#TCB_SP_OFS] ; Store SP
B Sys_ContextSave3
ENDIF
Sys_ContextSave2
MRS R0,PSP ; Get PSP
SUBS R0,R0,#32 ; Adjust address
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} ; Save R8..R11
Sys_ContextSave3
MOV R0,LR ; Get EXC_RETURN
ADDS R1,R1,#TCB_SF_OFS ; Adjust address
STRB R0,[R1] ; Store stack frame information
Sys_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.run: curr = next
IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
ENDIF
Sys_ContextRestore
IF DOMAIN_NS = 1
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
ENDIF
Sys_ContextRestore1
MOV R1,R2
ADDS R1,R1,#TCB_SF_OFS ; Adjust offset
LDRB R0,[R1] ; Load stack frame information
MOVS R1,#0xFF
MVNS R1,R1 ; R1=0xFFFFFF00
ORRS R0,R1
MOV LR,R0 ; Set EXC_RETURN
IF DOMAIN_NS = 1
LSLS R0,R0,#25 ; Check domain of interrupted thread
BPL Sys_ContextRestore2 ; Branch if non-secure
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
MSR PSP,R0 ; Set PSP
BX LR ; Exit from handler
ELSE
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
MSR PSPLIM,R0 ; Set PSPLIM
ENDIF
Sys_ContextRestore2
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ADDS R0,R0,#16 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 ; Set PSP
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
Sys_ContextExit
BX LR ; Exit from handler
ALIGN
ENDP
END
|
wuxx/nanoDAP | 11,157 | software/DAPLink/source/rtos2/RTX/Source/GCC/irq_armv8mml.S | /*
* Copyright (c) 2016-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
* Title: ARMv8M Mainline Exception handlers
*
* -----------------------------------------------------------------------------
*/
.syntax unified
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
#define DOMAIN_NS 1
#endif
#endif
#ifndef DOMAIN_NS
#define DOMAIN_NS 0
#endif
#if (defined(__ARM_FP) && (__ARM_FP > 0))
.equ FPU_USED, 1
#else
.equ FPU_USED, 0
#endif
#if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))
.equ MVE_USED, 1
#else
.equ MVE_USED, 0
#endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SM_OFS, 48 // TCB.stack_mem offset
.equ TCB_SP_OFS, 56 // TCB.SP offset
.equ TCB_SF_OFS, 34 // TCB.stack_frame offset
.equ TCB_TZM_OFS, 64 // TCB.tz_memory offset
.section ".rodata"
.global irqRtxLib // Non weak library reference
irqRtxLib:
.byte 0
.thumb
.section ".text"
.align 2
.thumb_func
.type SVC_Handler, %function
.global SVC_Handler
.fnstart
.cantunwind
SVC_Handler:
TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP // Get MSP if return stack is MSP
MRSNE R0,PSP // Get PSP if return stack is PSP
LDR R1,[R0,#24] // Load saved PC from stack
LDRB R1,[R1,#-2] // Load SVC number
CMP R1,#0
BNE SVC_User // Branch if not SVC 0
PUSH {R0,LR} // Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} // Load function parameters and address from stack
BLX R12 // Call service function
POP {R12,LR} // Restore SP and EXC_RETURN
STM R12,{R0-R1} // Store function return values
SVC_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
IT EQ
BXEQ LR // Exit when threads are the same
.if (FPU_USED == 1) || (MVE_USED == 1)
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
TST LR,#0x10 // Check if extended stack frame
BNE SVC_ContextSwitch
LDR R1,=0xE000EF34 // FPCCR Address
LDR R0,[R1] // Load FPCCR
BIC R0,R0,#1 // Clear LSPACT (Lazy state)
STR R0,[R1] // Store FPCCR
B SVC_ContextSwitch
.else
CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted
.endif
SVC_ContextSave:
#if (DOMAIN_NS == 1)
LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,SVC_ContextSave1 // Branch if there is no secure context
PUSH {R1,R2,R3,LR} // Save registers and EXC_RETURN
BL TZ_StoreContext_S // Store secure context
POP {R1,R2,R3,LR} // Restore registers and EXC_RETURN
#endif
SVC_ContextSave1:
MRS R0,PSP // Get PSP
STMDB R0!,{R4-R11} // Save R4..R11
.if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} // Save VFP S16.S31
.endif
SVC_ContextSave2:
STR R0,[R1,#TCB_SP_OFS] // Store SP
STRB LR,[R1,#TCB_SF_OFS] // Store stack frame information
SVC_ContextSwitch:
STR R2,[R3] // osRtxInfo.thread.run: curr = next
SVC_ContextRestore:
#if (DOMAIN_NS == 1)
LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context
PUSH {R2,R3} // Save registers
BL TZ_LoadContext_S // Load secure context
POP {R2,R3} // Restore registers
#endif
SVC_ContextRestore1:
LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base
LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information
MSR PSPLIM,R0 // Set PSPLIM
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
#if (DOMAIN_NS == 1)
TST LR,#0x40 // Check domain of interrupted thread
BNE SVC_ContextRestore2 // Branch if secure
#endif
.if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
.endif
LDMIA R0!,{R4-R11} // Restore R4..R11
SVC_ContextRestore2:
MSR PSP,R0 // Set PSP
SVC_Exit:
BX LR // Exit from handler
SVC_User:
LDR R2,=osRtxUserSVC // Load address of SVC table
LDR R3,[R2] // Load SVC maximum number
CMP R1,R3 // Check SVC number range
BHI SVC_Exit // Branch if out of range
PUSH {R0,LR} // Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] // Load address of SVC function
LDM R0,{R0-R3} // Load function parameters from stack
BLX R12 // Call service function
POP {R12,LR} // Restore SP and EXC_RETURN
STR R0,[R12] // Store function return value
BX LR // Return from handler
.fnend
.size SVC_Handler, .-SVC_Handler
.thumb_func
.type PendSV_Handler, %function
.global PendSV_Handler
.fnstart
.cantunwind
PendSV_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,LR} // Restore EXC_RETURN
B Sys_Context
.fnend
.size PendSV_Handler, .-PendSV_Handler
.thumb_func
.type SysTick_Handler, %function
.global SysTick_Handler
.fnstart
.cantunwind
SysTick_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,LR} // Restore EXC_RETURN
B Sys_Context
.fnend
.size SysTick_Handler, .-SysTick_Handler
.thumb_func
.type Sys_Context, %function
.global Sys_Context
.fnstart
.cantunwind
Sys_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
IT EQ
BXEQ LR // Exit when threads are the same
Sys_ContextSave:
#if (DOMAIN_NS == 1)
LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,Sys_ContextSave1 // Branch if there is no secure context
PUSH {R1,R2,R3,LR} // Save registers and EXC_RETURN
BL TZ_StoreContext_S // Store secure context
POP {R1,R2,R3,LR} // Restore registers and EXC_RETURN
Sys_ContextSave1:
TST LR,#0x40 // Check domain of interrupted thread
IT NE
MRSNE R0,PSP // Get PSP
BNE Sys_ContextSave3 // Branch if secure
#endif
Sys_ContextSave2:
MRS R0,PSP // Get PSP
STMDB R0!,{R4-R11} // Save R4..R11
.if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} // Save VFP S16.S31
.endif
Sys_ContextSave3:
STR R0,[R1,#TCB_SP_OFS] // Store SP
STRB LR,[R1,#TCB_SF_OFS] // Store stack frame information
Sys_ContextSwitch:
STR R2,[R3] // osRtxInfo.run: curr = next
Sys_ContextRestore:
#if (DOMAIN_NS == 1)
LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context
PUSH {R2,R3} // Save registers
BL TZ_LoadContext_S // Load secure context
POP {R2,R3} // Restore registers
#endif
Sys_ContextRestore1:
LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base
LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information
MSR PSPLIM,R0 // Set PSPLIM
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
#if (DOMAIN_NS == 1)
TST LR,#0x40 // Check domain of interrupted thread
BNE Sys_ContextRestore2 // Branch if secure
#endif
.if (FPU_USED == 1) || (MVE_USED == 1)
TST LR,#0x10 // Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
.endif
LDMIA R0!,{R4-R11} // Restore R4..R11
Sys_ContextRestore2:
MSR PSP,R0 // Set PSP
Sys_ContextExit:
BX LR // Exit from handler
.fnend
.size Sys_Context, .-Sys_Context
.end
|
wuxx/nanoDAP | 12,128 | software/DAPLink/source/rtos2/RTX/Source/GCC/irq_armv8mbl.S | /*
* Copyright (c) 2016-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
* Title: ARMv8M Baseline Exception handlers
*
* -----------------------------------------------------------------------------
*/
.syntax unified
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS
#define DOMAIN_NS 1
#endif
#endif
#ifndef DOMAIN_NS
#define DOMAIN_NS 0
#endif
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SM_OFS, 48 // TCB.stack_mem offset
.equ TCB_SP_OFS, 56 // TCB.SP offset
.equ TCB_SF_OFS, 34 // TCB.stack_frame offset
.equ TCB_TZM_OFS, 64 // TCB.tz_memory offset
.section ".rodata"
.global irqRtxLib // Non weak library reference
irqRtxLib:
.byte 0
.thumb
.section ".text"
.align 2
.thumb_func
.type SVC_Handler, %function
.global SVC_Handler
.fnstart
.cantunwind
SVC_Handler:
MOV R0,LR
LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP // Branch if return stack is MSP
MRS R0,PSP // Get PSP
SVC_Number:
LDR R1,[R0,#24] // Load saved PC from stack
SUBS R1,R1,#2 // Point to SVC instruction
LDRB R1,[R1] // Load SVC number
CMP R1,#0
BNE SVC_User // Branch if not SVC 0
PUSH {R0,LR} // Save SP and EXC_RETURN
LDM R0,{R0-R3} // Load function parameters from stack
BLX R7 // Call service function
POP {R2,R3} // Restore SP and EXC_RETURN
STMIA R2!,{R0-R1} // Store function return values
MOV LR,R3 // Set EXC_RETURN
SVC_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
BEQ SVC_Exit // Branch when threads are the same
CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted
SVC_ContextSave:
#if (DOMAIN_NS == 1)
LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,SVC_ContextSave1 // Branch if there is no secure context
PUSH {R1,R2,R3,R7} // Save registers
MOV R7,LR // Get EXC_RETURN
BL TZ_StoreContext_S // Store secure context
MOV LR,R7 // Set EXC_RETURN
POP {R1,R2,R3,R7} // Restore registers
#endif
SVC_ContextSave1:
MRS R0,PSP // Get PSP
SUBS R0,R0,#32 // Calculate SP
STR R0,[R1,#TCB_SP_OFS] // Store SP
STMIA R0!,{R4-R7} // Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} // Save R8..R11
SVC_ContextSave2:
MOV R0,LR // Get EXC_RETURN
ADDS R1,R1,#TCB_SF_OFS // Adjust address
STRB R0,[R1] // Store stack frame information
SVC_ContextSwitch:
SUBS R3,R3,#8 // Adjust address
STR R2,[R3] // osRtxInfo.thread.run: curr = next
SVC_ContextRestore:
#if (DOMAIN_NS == 1)
LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context
PUSH {R2,R3} // Save registers
BL TZ_LoadContext_S // Load secure context
POP {R2,R3} // Restore registers
#endif
SVC_ContextRestore1:
MOV R1,R2
ADDS R1,R1,#TCB_SF_OFS // Adjust address
LDRB R0,[R1] // Load stack frame information
MOVS R1,#0xFF
MVNS R1,R1 // R1=0xFFFFFF00
ORRS R0,R1
MOV LR,R0 // Set EXC_RETURN
#if (DOMAIN_NS == 1)
LSLS R0,R0,#25 // Check domain of interrupted thread
BPL SVC_ContextRestore2 // Branch if non-secure
LDR R0,[R2,#TCB_SP_OFS] // Load SP
MSR PSP,R0 // Set PSP
BX LR // Exit from handler
#else
LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base
MSR PSPLIM,R0 // Set PSPLIM
#endif
SVC_ContextRestore2:
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ADDS R0,R0,#16 // Adjust address
LDMIA R0!,{R4-R7} // Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 // Set PSP
SUBS R0,R0,#32 // Adjust address
LDMIA R0!,{R4-R7} // Restore R4..R7
SVC_Exit:
BX LR // Exit from handler
SVC_MSP:
MRS R0,MSP // Get MSP
B SVC_Number
SVC_User:
LDR R2,=osRtxUserSVC // Load address of SVC table
LDR R3,[R2] // Load SVC maximum number
CMP R1,R3 // Check SVC number range
BHI SVC_Exit // Branch if out of range
PUSH {R0,LR} // Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] // Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} // Load function parameters from stack
BLX R12 // Call service function
POP {R2,R3} // Restore SP and EXC_RETURN
STR R0,[R2] // Store function return value
MOV LR,R3 // Set EXC_RETURN
BX LR // Return from handler
.fnend
.size SVC_Handler, .-SVC_Handler
.thumb_func
.type PendSV_Handler, %function
.global PendSV_Handler
.fnstart
.cantunwind
PendSV_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,R1} // Restore EXC_RETURN
MOV LR,R1 // Set EXC_RETURN
B Sys_Context
.fnend
.size PendSV_Handler, .-PendSV_Handler
.thumb_func
.type SysTick_Handler, %function
.global SysTick_Handler
.fnstart
.cantunwind
SysTick_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,R1} // Restore EXC_RETURN
MOV LR,R1 // Set EXC_RETURN
B Sys_Context
.fnend
.size SysTick_Handler, .-SysTick_Handler
.thumb_func
.type Sys_Context, %function
.global Sys_Context
.fnstart
.cantunwind
Sys_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDM R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
BEQ Sys_ContextExit // Branch when threads are the same
Sys_ContextSave:
#if (DOMAIN_NS == 1)
LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,Sys_ContextSave1 // Branch if there is no secure context
PUSH {R1,R2,R3,R7} // Save registers
MOV R7,LR // Get EXC_RETURN
BL TZ_StoreContext_S // Store secure context
MOV LR,R7 // Set EXC_RETURN
POP {R1,R2,R3,R7} // Restore registers
Sys_ContextSave1:
MOV R0,LR // Get EXC_RETURN
LSLS R0,R0,#25 // Check domain of interrupted thread
BPL Sys_ContextSave2 // Branch if non-secure
MRS R0,PSP // Get PSP
STR R0,[R1,#TCB_SP_OFS] // Store SP
B Sys_ContextSave3
#endif
Sys_ContextSave2:
MRS R0,PSP // Get PSP
SUBS R0,R0,#32 // Adjust address
STR R0,[R1,#TCB_SP_OFS] // Store SP
STMIA R0!,{R4-R7} // Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} // Save R8..R11
Sys_ContextSave3:
MOV R0,LR // Get EXC_RETURN
ADDS R1,R1,#TCB_SF_OFS // Adjust address
STRB R0,[R1] // Store stack frame information
Sys_ContextSwitch:
SUBS R3,R3,#8 // Adjust address
STR R2,[R3] // osRtxInfo.run: curr = next
Sys_ContextRestore:
#if (DOMAIN_NS == 1)
LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier
CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context
PUSH {R2,R3} // Save registers
BL TZ_LoadContext_S // Load secure context
POP {R2,R3} // Restore registers
#endif
Sys_ContextRestore1:
MOV R1,R2
ADDS R1,R1,#TCB_SF_OFS // Adjust offset
LDRB R0,[R1] // Load stack frame information
MOVS R1,#0xFF
MVNS R1,R1 // R1=0xFFFFFF00
ORRS R0,R1
MOV LR,R0 // Set EXC_RETURN
#if (DOMAIN_NS == 1)
LSLS R0,R0,#25 // Check domain of interrupted thread
BPL Sys_ContextRestore2 // Branch if non-secure
LDR R0,[R2,#TCB_SP_OFS] // Load SP
MSR PSP,R0 // Set PSP
BX LR // Exit from handler
#else
LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base
MSR PSPLIM,R0 // Set PSPLIM
#endif
Sys_ContextRestore2:
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ADDS R0,R0,#16 // Adjust address
LDMIA R0!,{R4-R7} // Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 // Set PSP
SUBS R0,R0,#32 // Adjust address
LDMIA R0!,{R4-R7} // Restore R4..R7
Sys_ContextExit:
BX LR // Exit from handler
.fnend
.size Sys_Context, .-Sys_Context
.end
|
wuxx/nanoDAP | 5,828 | software/DAPLink/source/rtos2/RTX/Source/GCC/irq_cm4f.S | /*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
* Title: Cortex-M4F Exception handlers
*
* -----------------------------------------------------------------------------
*/
.syntax unified
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SP_OFS, 56 // TCB.SP offset
.equ TCB_SF_OFS, 34 // TCB.stack_frame offset
.section ".rodata"
.global irqRtxLib // Non weak library reference
irqRtxLib:
.byte 0
.thumb
.section ".text"
.align 2
.thumb_func
.type SVC_Handler, %function
.global SVC_Handler
.fnstart
.cantunwind
SVC_Handler:
TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP // Get MSP if return stack is MSP
MRSNE R0,PSP // Get PSP if return stack is PSP
LDR R1,[R0,#24] // Load saved PC from stack
LDRB R1,[R1,#-2] // Load SVC number
CBNZ R1,SVC_User // Branch if not SVC 0
PUSH {R0,LR} // Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} // Load function parameters and address from stack
BLX R12 // Call service function
POP {R12,LR} // Restore SP and EXC_RETURN
STM R12,{R0-R1} // Store function return values
SVC_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
IT EQ
BXEQ LR // Exit when threads are the same
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
TST LR,#0x10 // Check if extended stack frame
BNE SVC_ContextSwitch
LDR R1,=0xE000EF34 // FPCCR Address
LDR R0,[R1] // Load FPCCR
BIC R0,R0,#1 // Clear LSPACT (Lazy state)
STR R0,[R1] // Store FPCCR
B SVC_ContextSwitch
SVC_ContextSave:
STMDB R12!,{R4-R11} // Save R4..R11
TST LR,#0x10 // Check if extended stack frame
IT EQ
VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31
STR R12,[R1,#TCB_SP_OFS] // Store SP
STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information
SVC_ContextSwitch:
STR R2,[R3] // osRtxInfo.thread.run: curr = next
SVC_ContextRestore:
LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
TST LR,#0x10 // Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
LDMIA R0!,{R4-R11} // Restore R4..R11
MSR PSP,R0 // Set PSP
SVC_Exit:
BX LR // Exit from handler
SVC_User:
LDR R2,=osRtxUserSVC // Load address of SVC table
LDR R3,[R2] // Load SVC maximum number
CMP R1,R3 // Check SVC number range
BHI SVC_Exit // Branch if out of range
PUSH {R0,LR} // Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] // Load address of SVC function
LDM R0,{R0-R3} // Load function parameters from stack
BLX R12 // Call service function
POP {R12,LR} // Restore SP and EXC_RETURN
STR R0,[R12] // Store function return value
BX LR // Return from handler
.fnend
.size SVC_Handler, .-SVC_Handler
.thumb_func
.type PendSV_Handler, %function
.global PendSV_Handler
.fnstart
.cantunwind
PendSV_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,LR} // Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
.fnend
.size PendSV_Handler, .-PendSV_Handler
.thumb_func
.type SysTick_Handler, %function
.global SysTick_Handler
.fnstart
.cantunwind
SysTick_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,LR} // Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
.fnend
.size SysTick_Handler, .-SysTick_Handler
.end
|
wuxx/nanoDAP | 6,000 | software/DAPLink/source/rtos2/RTX/Source/GCC/irq_cm0.S | /*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
* Title: Cortex-M0 Exception handlers
*
* -----------------------------------------------------------------------------
*/
.syntax unified
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SP_OFS, 56 // TCB.SP offset
.section ".rodata"
.global irqRtxLib // Non weak library reference
irqRtxLib:
.byte 0
.thumb
.section ".text"
.align 2
.thumb_func
.type SVC_Handler, %function
.global SVC_Handler
.fnstart
.cantunwind
SVC_Handler:
MOV R0,LR
LSRS R0,R0,#3 // Determine return stack from EXC_RETURN bit 2
BCC SVC_MSP // Branch if return stack is MSP
MRS R0,PSP // Get PSP
SVC_Number:
LDR R1,[R0,#24] // Load saved PC from stack
SUBS R1,R1,#2 // Point to SVC instruction
LDRB R1,[R1] // Load SVC number
CMP R1,#0
BNE SVC_User // Branch if not SVC 0
PUSH {R0,LR} // Save SP and EXC_RETURN
LDMIA R0,{R0-R3} // Load function parameters from stack
BLX R7 // Call service function
POP {R2,R3} // Restore SP and EXC_RETURN
STMIA R2!,{R0-R1} // Store function return values
MOV LR,R3 // Set EXC_RETURN
SVC_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDMIA R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
BEQ SVC_Exit // Branch when threads are the same
CMP R1,#0
BEQ SVC_ContextSwitch // Branch if running thread is deleted
SVC_ContextSave:
MRS R0,PSP // Get PSP
SUBS R0,R0,#32 // Calculate SP
STR R0,[R1,#TCB_SP_OFS] // Store SP
STMIA R0!,{R4-R7} // Save R4..R7
MOV R4,R8
MOV R5,R9
MOV R6,R10
MOV R7,R11
STMIA R0!,{R4-R7} // Save R8..R11
SVC_ContextSwitch:
SUBS R3,R3,#8 // Adjust address
STR R2,[R3] // osRtxInfo.thread.run: curr = next
SVC_ContextRestore:
LDR R0,[R2,#TCB_SP_OFS] // Load SP
ADDS R0,R0,#16 // Adjust address
LDMIA R0!,{R4-R7} // Restore R8..R11
MOV R8,R4
MOV R9,R5
MOV R10,R6
MOV R11,R7
MSR PSP,R0 // Set PSP
SUBS R0,R0,#32 // Adjust address
LDMIA R0!,{R4-R7} // Restore R4..R7
MOVS R0,#~0xFFFFFFFD
MVNS R0,R0 // Set EXC_RETURN value
BX R0 // Exit from handler
SVC_MSP:
MRS R0,MSP // Get MSP
B SVC_Number
SVC_Exit:
BX LR // Exit from handler
SVC_User:
LDR R2,=osRtxUserSVC // Load address of SVC table
LDR R3,[R2] // Load SVC maximum number
CMP R1,R3 // Check SVC number range
BHI SVC_Exit // Branch if out of range
PUSH {R0,LR} // Save SP and EXC_RETURN
LSLS R1,R1,#2
LDR R3,[R2,R1] // Load address of SVC function
MOV R12,R3
LDMIA R0,{R0-R3} // Load function parameters from stack
BLX R12 // Call service function
POP {R2,R3} // Restore SP and EXC_RETURN
STR R0,[R2] // Store function return value
MOV LR,R3 // Set EXC_RETURN
BX LR // Return from handler
.fnend
.size SVC_Handler, .-SVC_Handler
.thumb_func
.type PendSV_Handler, %function
.global PendSV_Handler
.fnstart
.cantunwind
PendSV_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,R1} // Restore EXC_RETURN
MOV LR,R1 // Set EXC_RETURN
B SVC_Context
.fnend
.size PendSV_Handler, .-PendSV_Handler
.thumb_func
.type SysTick_Handler, %function
.global SysTick_Handler
.fnstart
.cantunwind
SysTick_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,R1} // Restore EXC_RETURN
MOV LR,R1 // Set EXC_RETURN
B SVC_Context
.fnend
.size SysTick_Handler, .-SysTick_Handler
.end
|
wuxx/nanoDAP | 4,927 | software/DAPLink/source/rtos2/RTX/Source/GCC/irq_cm3.S | /*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
* Title: Cortex-M3 Exception handlers
*
* -----------------------------------------------------------------------------
*/
.syntax unified
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SP_OFS, 56 // TCB.SP offset
.section ".rodata"
.global irqRtxLib // Non weak library reference
irqRtxLib:
.byte 0
.thumb
.section ".text"
.align 2
.thumb_func
.type SVC_Handler, %function
.global SVC_Handler
.fnstart
.cantunwind
SVC_Handler:
TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP // Get MSP if return stack is MSP
MRSNE R0,PSP // Get PSP if return stack is PSP
LDR R1,[R0,#24] // Load saved PC from stack
LDRB R1,[R1,#-2] // Load SVC number
CBNZ R1,SVC_User // Branch if not SVC 0
PUSH {R0,LR} // Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} // Load function parameters and address from stack
BLX R12 // Call service function
POP {R12,LR} // Restore SP and EXC_RETURN
STM R12,{R0-R1} // Store function return values
SVC_Context:
LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
IT EQ
BXEQ LR // Exit when threads are the same
CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted
SVC_ContextSave:
STMDB R12!,{R4-R11} // Save R4..R11
STR R12,[R1,#TCB_SP_OFS] // Store SP
SVC_ContextSwitch:
STR R2,[R3] // osRtxInfo.thread.run: curr = next
SVC_ContextRestore:
LDR R0,[R2,#TCB_SP_OFS] // Load SP
LDMIA R0!,{R4-R11} // Restore R4..R11
MSR PSP,R0 // Set PSP
MVN LR,#~0xFFFFFFFD // Set EXC_RETURN value
SVC_Exit:
BX LR // Exit from handler
SVC_User:
LDR R2,=osRtxUserSVC // Load address of SVC table
LDR R3,[R2] // Load SVC maximum number
CMP R1,R3 // Check SVC number range
BHI SVC_Exit // Branch if out of range
PUSH {R0,LR} // Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] // Load address of SVC function
LDM R0,{R0-R3} // Load function parameters from stack
BLX R12 // Call service function
POP {R12,LR} // Restore SP and EXC_RETURN
STR R0,[R12] // Store function return value
BX LR // Return from handler
.fnend
.size SVC_Handler, .-SVC_Handler
.thumb_func
.type PendSV_Handler, %function
.global PendSV_Handler
.fnstart
.cantunwind
PendSV_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,LR} // Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
.fnend
.size PendSV_Handler, .-PendSV_Handler
.thumb_func
.type SysTick_Handler, %function
.global SysTick_Handler
.fnstart
.cantunwind
SysTick_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,LR} // Restore EXC_RETURN
MRS R12,PSP
B SVC_Context
.fnend
.size SysTick_Handler, .-SysTick_Handler
.end
|
wuxx/nanoDAP | 1,113 | software/DAPLink/source/rtos/ARM/SVC_Table.s | ;/**
; * @file SVC_Table.s
; * @brief SVC config for application
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
AREA SVC_TABLE, CODE, READONLY
EXPORT SVC_Count
SVC_Cnt EQU (SVC_End-SVC_Table)/4
SVC_Count DCD SVC_Cnt
; Import user SVC functions here.
EXPORT SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
SVC_End
END
|
wuxx/nanoDAP | 13,327 | software/DAPLink/source/hic_hal/maxim/max32620/gcc/startup_MAX32620.S | /**
* @file startup_MK20D5.s
* @brief
*
* DAPLink Interface Firmware
* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long CLKMAN_IRQHandler /* 16:01 CLKMAN */
.long PWRMAN_IRQHandler /* 17:02 PWRMAN */
.long FLC_IRQHandler /* 18:03 Flash Controller */
.long RTC0_IRQHandler /* 19:04 RTC INT0 */
.long RTC1_IRQHandler /* 20:05 RTC INT1 */
.long RTC2_IRQHandler /* 21:06 RTC INT2 */
.long RTC3_IRQHandler /* 22:07 RTC INT3 */
.long PMU_IRQHandler /* 23:08 PMU */
.long USB_IRQHandler /* 24:09 USB */
.long AES_IRQHandler /* 25:10 AES */
.long MAA_IRQHandler /* 26:11 MAA */
.long WDT0_IRQHandler /* 27:12 WATCHDOG0 */
.long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
.long WDT1_IRQHandler /* 29:14 WATCHDOG1 */
.long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
.long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
.long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
.long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
.long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
.long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
.long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
.long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
.long TMR0_IRQHandler /* 38:23 Timer32-0 */
.long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
.long TMR1_IRQHandler /* 40:25 Timer32-1 */
.long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
.long TMR2_IRQHandler /* 42:27 Timer32-2 */
.long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
.long TMR3_IRQHandler /* 44:29 Timer32-3 */
.long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
.long TMR4_IRQHandler /* 46:31 Timer32-4 */
.long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
.long TMR5_IRQHandler /* 48:33 Timer32-5 */
.long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
.long UART0_IRQHandler /* 50:35 UART0 */
.long UART1_IRQHandler /* 51:36 UART1 */
.long UART2_IRQHandler /* 52:37 UART0 */
.long UART3_IRQHandler /* 53:38 UART1 */
.long PT_IRQHandler /* 54:39 PT */
.long I2CM0_IRQHandler /* 55:40 I2C Master 0 */
.long I2CM1_IRQHandler /* 56:41 I2C Master 1 */
.long I2CM2_IRQHandler /* 57:42 I2C Master 2 */
.long I2CS_IRQHandler /* 58:43 I2C Slave */
.long SPI0_IRQHandler /* 59:44 SPI0 */
.long SPI1_IRQHandler /* 60:45 SPI1 */
.long SPI2_IRQHandler /* 61:46 SPI2 */
.long SPIB_IRQHandler /* 62:47 SPI Bridge */
.long OWM_IRQHandler /* 63:48 1-Wire Master */
.long AFE_IRQHandler /* 64:49 AFE */
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
ldr r0,=MemManage_Handler
bx r0
.size MemManage_Handler, . - MemManage_Handler
.align 1
.thumb_func
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
ldr r0,=BusFault_Handler
bx r0
.size BusFault_Handler, . - BusFault_Handler
.align 1
.thumb_func
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
ldr r0,=UsageFault_Handler
bx r0
.size UsageFault_Handler, . - UsageFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
ldr r0,=DebugMon_Handler
bx r0
.size DebugMon_Handler, . - DebugMon_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */
def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */
def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */
def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */
def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */
def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */
def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */
def_irq_handler PMU_IRQHandler /* 23:08 PMU */
def_irq_handler USB_IRQHandler /* 24:09 USB */
def_irq_handler AES_IRQHandler /* 25:10 AES */
def_irq_handler MAA_IRQHandler /* 26:11 MAA */
def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */
def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */
def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */
def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */
def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */
def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */
def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */
def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */
def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
def_irq_handler UART0_IRQHandler /* 50:35 UART0 */
def_irq_handler UART1_IRQHandler /* 51:36 UART1 */
def_irq_handler UART2_IRQHandler /* 52:37 UART0 */
def_irq_handler UART3_IRQHandler /* 53:38 UART1 */
def_irq_handler PT_IRQHandler /* 54:39 PT */
def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */
def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */
def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */
def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */
def_irq_handler SPI0_IRQHandler /* 59:44 SPI0 */
def_irq_handler SPI1_IRQHandler /* 60:45 SPI1 */
def_irq_handler SPI2_IRQHandler /* 61:46 SPI2 */
def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */
def_irq_handler OWM_IRQHandler /* 63:48 1-Wire Master */
def_irq_handler AFE_IRQHandler /* 64:49 AFE */
.end
|
wuxx/nanoDAP | 13,622 | software/DAPLink/source/hic_hal/maxim/max32620/armcc/startup_MAX32620.S | ;*******************************************************************************
; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
; OTHER DEALINGS IN THE SOFTWARE.
;
; Except as contained in this notice, the name of Maxim Integrated
; Products, Inc. shall not be used except as stated in the Maxim Integrated
; Products, Inc. Branding Policy.
;
; The mere transfer of this software does not imply any licenses
; of trade secrets, proprietary technology, copyrights, patents,
; trademarks, maskwork rights, or any other form of intellectual
; property whatsoever. Maxim Integrated Products, Inc. retains all
; ownership rights.
;*******************************************************************************
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Maxim 32620 Externals interrupts
DCD CLKMAN_IRQHandler /* 16:01 CLKMAN */
DCD PWRMAN_IRQHandler /* 17:02 PWRMAN */
DCD FLC_IRQHandler /* 18:03 Flash Controller */
DCD RTC0_IRQHandler /* 19:04 RTC INT0 */
DCD RTC1_IRQHandler /* 20:05 RTC INT1 */
DCD RTC2_IRQHandler /* 21:06 RTC INT2 */
DCD RTC3_IRQHandler /* 22:07 RTC INT3 */
DCD PMU_IRQHandler /* 23:08 PMU */
DCD USB_IRQHandler /* 24:09 USB */
DCD AES_IRQHandler /* 25:10 AES */
DCD MAA_IRQHandler /* 26:11 MAA */
DCD WDT0_IRQHandler /* 27:12 WATCHDOG0 */
DCD WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
DCD WDT1_IRQHandler /* 29:14 WATCHDOG1 */
DCD WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
DCD GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
DCD GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
DCD GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
DCD GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
DCD GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
DCD GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
DCD GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
DCD TMR0_IRQHandler /* 38:23 Timer32-0 */
DCD TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
DCD TMR1_IRQHandler /* 40:25 Timer32-1 */
DCD TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
DCD TMR2_IRQHandler /* 42:27 Timer32-2 */
DCD TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
DCD TMR3_IRQHandler /* 44:29 Timer32-3 */
DCD TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
DCD TMR4_IRQHandler /* 46:31 Timer32-4 */
DCD TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
DCD TMR5_IRQHandler /* 48:33 Timer32-5 */
DCD TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
DCD UART0_IRQHandler /* 50:35 UART0 */
DCD UART1_IRQHandler /* 51:36 UART1 */
DCD UART2_IRQHandler /* 52:37 UART0 */
DCD UART3_IRQHandler /* 53:38 UART1 */
DCD PT_IRQHandler /* 54:39 PT */
DCD I2CM0_IRQHandler /* 55:40 I2C Master 0 */
DCD I2CM1_IRQHandler /* 56:41 I2C Master 1 */
DCD I2CM2_IRQHandler /* 57:42 I2C Master 2 */
DCD I2CS_IRQHandler /* 58:43 I2C Slave */
DCD SPI0_IRQHandler /* 59:44 SPI0 */
DCD SPI1_IRQHandler /* 60:45 SPI1 */
DCD SPI2_IRQHandler /* 61:46 SPI2 */
DCD SPIB_IRQHandler /* 62:47 SPI Bridge */
DCD OWM_IRQHandler /* 63:48 1-Wire Master */
DCD AFE_IRQHandler /* 64:49 AFE */
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT PreInit
IMPORT SystemInit
IMPORT __main
LDR R0, =PreInit
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
MemManage_Handler PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
DefaultIRQ_Handler PROC
EXPORT CLKMAN_IRQHandler [WEAK]
EXPORT PWRMAN_IRQHandler [WEAK]
EXPORT FLC_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT RTC3_IRQHandler [WEAK]
EXPORT PMU_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT MAA_IRQHandler [WEAK]
EXPORT WDT0_IRQHandler [WEAK]
EXPORT WDT0_P_IRQHandler [WEAK]
EXPORT WDT1_IRQHandler [WEAK]
EXPORT WDT1_P_IRQHandler [WEAK]
EXPORT GPIO_P0_IRQHandler [WEAK]
EXPORT GPIO_P1_IRQHandler [WEAK]
EXPORT GPIO_P2_IRQHandler [WEAK]
EXPORT GPIO_P3_IRQHandler [WEAK]
EXPORT GPIO_P4_IRQHandler [WEAK]
EXPORT GPIO_P5_IRQHandler [WEAK]
EXPORT GPIO_P6_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR16_0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR16_1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR16_2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT TMR16_3_IRQHandler [WEAK]
EXPORT TMR4_IRQHandler [WEAK]
EXPORT TMR16_4_IRQHandler [WEAK]
EXPORT TMR5_IRQHandler [WEAK]
EXPORT TMR16_5_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PT_IRQHandler [WEAK]
EXPORT I2CM0_IRQHandler [WEAK]
EXPORT I2CM1_IRQHandler [WEAK]
EXPORT I2CM2_IRQHandler [WEAK]
EXPORT I2CS_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPIB_IRQHandler [WEAK]
EXPORT OWM_IRQHandler [WEAK]
EXPORT AFE_IRQHandler [WEAK]
CLKMAN_IRQHandler
PWRMAN_IRQHandler
FLC_IRQHandler
RTC0_IRQHandler
RTC1_IRQHandler
RTC2_IRQHandler
RTC3_IRQHandler
PMU_IRQHandler
USB_IRQHandler
AES_IRQHandler
MAA_IRQHandler
WDT0_IRQHandler
WDT0_P_IRQHandler
WDT1_IRQHandler
WDT1_P_IRQHandler
GPIO_P0_IRQHandler
GPIO_P1_IRQHandler
GPIO_P2_IRQHandler
GPIO_P3_IRQHandler
GPIO_P4_IRQHandler
GPIO_P5_IRQHandler
GPIO_P6_IRQHandler
TMR0_IRQHandler
TMR16_0_IRQHandler
TMR1_IRQHandler
TMR16_1_IRQHandler
TMR2_IRQHandler
TMR16_2_IRQHandler
TMR3_IRQHandler
TMR16_3_IRQHandler
TMR4_IRQHandler
TMR16_4_IRQHandler
TMR5_IRQHandler
TMR16_5_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PT_IRQHandler
I2CM0_IRQHandler
I2CM1_IRQHandler
I2CM2_IRQHandler
I2CS_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
SPIB_IRQHandler
OWM_IRQHandler
AFE_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 12,176 | software/DAPLink/source/hic_hal/maxim/max32625/gcc/startup_max32625.S | /*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*******************************************************************************
*/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility */
.long DAPLINK_VERSION /* DAPLINK: Version */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long g_board_info /* DAPLINK: Pointer to board/family/target info */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* MAX32625 Interrupts */
.long CLKMAN_IRQHandler /* 16:01 CLKMAN */
.long PWRMAN_IRQHandler /* 17:02 PWRMAN */
.long FLC_IRQHandler /* 18:03 Flash Controller */
.long RTC0_IRQHandler /* 19:04 RTC INT0 */
.long RTC1_IRQHandler /* 20:05 RTC INT1 */
.long RTC2_IRQHandler /* 21:06 RTC INT2 */
.long RTC3_IRQHandler /* 22:07 RTC INT3 */
.long PMU_IRQHandler /* 23:08 PMU */
.long USB_IRQHandler /* 24:09 USB */
.long AES_IRQHandler /* 25:10 AES */
.long MAA_IRQHandler /* 26:11 MAA */
.long WDT0_IRQHandler /* 27:12 WATCHDOG0 */
.long WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
.long WDT1_IRQHandler /* 29:14 WATCHDOG1 */
.long WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
.long GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
.long GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
.long GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
.long GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
.long GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
.long GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
.long GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
.long TMR0_IRQHandler /* 38:23 Timer32-0 */
.long TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
.long TMR1_IRQHandler /* 40:25 Timer32-1 */
.long TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
.long TMR2_IRQHandler /* 42:27 Timer32-2 */
.long TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
.long TMR3_IRQHandler /* 44:29 Timer32-3 */
.long TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
.long TMR4_IRQHandler /* 46:31 Timer32-4 */
.long TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
.long TMR5_IRQHandler /* 48:33 Timer32-5 */
.long TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
.long UART0_IRQHandler /* 50:35 UART0 */
.long UART1_IRQHandler /* 51:36 UART1 */
.long UART2_IRQHandler /* 52:37 UART2 */
.long UART3_IRQHandler /* 53:38 UART3 */
.long PT_IRQHandler /* 54:39 PT */
.long I2CM0_IRQHandler /* 55:40 I2C Master 0 */
.long I2CM1_IRQHandler /* 56:41 I2C Master 1 */
.long I2CM2_IRQHandler /* 57:42 I2C Master 2 */
.long I2CS_IRQHandler /* 58:43 I2C Slave */
.long SPIM0_IRQHandler /* 59:44 SPIM0 */
.long SPIM1_IRQHandler /* 60:45 SPIM1 */
.long SPIM2_IRQHandler /* 61:46 SPIM2 */
.long SPIB_IRQHandler /* 62:47 SPI Bridge */
.long OWM_IRQHandler /* 63:48 1-Wire Master */
.long AFE_IRQHandler /* 64:49 AFE */
.long SPIS_IRQHandler /* 65:50 SPI Slave */
.long GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */
.long GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =__StackTop
mov sp, r0
ldr r0, =PreInit
blx r0
cbnz r0, .SKIPRAMINIT
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
.SKIPRAMINIT:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
blx r0
.SPIN:
/* Enter LP2 if main() ever returns. */
wfi
bl .SPIN
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler Default_Handler
/* MAX32625 Interrupts */
def_irq_handler CLKMAN_IRQHandler /* 16:01 CLKMAN */
def_irq_handler PWRMAN_IRQHandler /* 17:02 PWRMAN */
def_irq_handler FLC_IRQHandler /* 18:03 Flash Controller */
def_irq_handler RTC0_IRQHandler /* 19:04 RTC INT0 */
def_irq_handler RTC1_IRQHandler /* 20:05 RTC INT1 */
def_irq_handler RTC2_IRQHandler /* 21:06 RTC INT2 */
def_irq_handler RTC3_IRQHandler /* 22:07 RTC INT3 */
def_irq_handler PMU_IRQHandler /* 23:08 PMU */
def_irq_handler USB_IRQHandler /* 24:09 USB */
def_irq_handler AES_IRQHandler /* 25:10 AES */
def_irq_handler MAA_IRQHandler /* 26:11 MAA */
def_irq_handler WDT0_IRQHandler /* 27:12 WATCHDOG0 */
def_irq_handler WDT0_P_IRQHandler /* 28:13 WATCHDOG0 PRE-WINDOW */
def_irq_handler WDT1_IRQHandler /* 29:14 WATCHDOG1 */
def_irq_handler WDT1_P_IRQHandler /* 30:15 WATCHDOG1 PRE-WINDOW */
def_irq_handler GPIO_P0_IRQHandler /* 31:16 GPIO Port 0 */
def_irq_handler GPIO_P1_IRQHandler /* 32:17 GPIO Port 1 */
def_irq_handler GPIO_P2_IRQHandler /* 33:18 GPIO Port 2 */
def_irq_handler GPIO_P3_IRQHandler /* 34:19 GPIO Port 3 */
def_irq_handler GPIO_P4_IRQHandler /* 35:20 GPIO Port 4 */
def_irq_handler GPIO_P5_IRQHandler /* 36:21 GPIO Port 5 */
def_irq_handler GPIO_P6_IRQHandler /* 37:22 GPIO Port 6 */
def_irq_handler TMR0_IRQHandler /* 38:23 Timer32-0 */
def_irq_handler TMR16_0_IRQHandler /* 39:24 Timer16-s0 */
def_irq_handler TMR1_IRQHandler /* 40:25 Timer32-1 */
def_irq_handler TMR16_1_IRQHandler /* 41:26 Timer16-s1 */
def_irq_handler TMR2_IRQHandler /* 42:27 Timer32-2 */
def_irq_handler TMR16_2_IRQHandler /* 43:28 Timer16-s2 */
def_irq_handler TMR3_IRQHandler /* 44:29 Timer32-3 */
def_irq_handler TMR16_3_IRQHandler /* 45:30 Timer16-s3 */
def_irq_handler TMR4_IRQHandler /* 46:31 Timer32-4 */
def_irq_handler TMR16_4_IRQHandler /* 47:32 Timer16-s4 */
def_irq_handler TMR5_IRQHandler /* 48:33 Timer32-5 */
def_irq_handler TMR16_5_IRQHandler /* 49:34 Timer16-s5 */
def_irq_handler PT_IRQHandler /* 50:35 PT */
def_irq_handler UART0_IRQHandler /* 51:36 UART0 */
def_irq_handler UART1_IRQHandler /* 52:37 UART1 */
def_irq_handler UART2_IRQHandler /* 53:38 UART0 */
def_irq_handler UART3_IRQHandler /* 54:39 UART1 */
def_irq_handler I2CM0_IRQHandler /* 55:40 I2C Master 0 */
def_irq_handler I2CM1_IRQHandler /* 56:41 I2C Master 1 */
def_irq_handler I2CM2_IRQHandler /* 57:42 I2C Master 2 */
def_irq_handler I2CS_IRQHandler /* 58:43 I2C Slave */
def_irq_handler SPIM0_IRQHandler /* 59:44 SPIM0 */
def_irq_handler SPIM1_IRQHandler /* 60:45 SPIM1 */
def_irq_handler SPIM2_IRQHandler /* 61:46 SPIM2 */
def_irq_handler SPIB_IRQHandler /* 62:47 SPI Bridge */
def_irq_handler OWM_IRQHandler /* 63:48 1-Wire Master */
def_irq_handler AFE_IRQHandler /* 64:49 AFE */
def_irq_handler SPIS_IRQHandler /* 65:50 SPI Slave */
def_irq_handler GPIO_P7_IRQHandler /* 66:51 GPIO Port 7 */
def_irq_handler GPIO_P8_IRQHandler /* 67:52 GPIO Port 8 */
.end
|
wuxx/nanoDAP | 14,981 | software/DAPLink/source/hic_hal/maxim/max32625/armcc/startup_max32625.S | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
; OTHER DEALINGS IN THE SOFTWARE.
;
; Except as contained in this notice, the name of Maxim Integrated
; Products, Inc. shall not be used except as stated in the Maxim Integrated
; Products, Inc. Branding Policy.
;
; The mere transfer of this software does not imply any licenses
; of trade secrets, proprietary technology, copyrights, patents,
; trademarks, maskwork rights, or any other form of intellectual
; property whatsoever. Maxim Integrated Products, Inc. retains all
; ownership rights.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
#include "daplink_defaults.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU DAPLINK_STACK_SIZE
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp ; ARMCC: name is set to work with MicroLib
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU DAPLINK_HEAP_SIZE
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
EXPORT __isr_vector
IMPORT g_board_info
; Core Level - CM4 ; Most names are to help the FreeRTOS port.
__isr_vector
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Maxim 3263X Externals interrupts
DCD CLKMAN_IRQHandler ; 16:00 CLKMAN
DCD PWRMAN_IRQHandler ; 17:01 PWRMAN
DCD FLC_IRQHandler ; 18:02 Flash Controller
DCD RTC0_IRQHandler ; 19:03 RTC INT0
DCD RTC1_IRQHandler ; 20:04 RTC INT1
DCD RTC2_IRQHandler ; 21:05 RTC INT2
DCD RTC3_IRQHandler ; 22:06 RTC INT3
DCD PMU_IRQHandler ; 23:07 PMU
DCD USB_IRQHandler ; 24:08 USB
DCD AES_IRQHandler ; 25:09 AES
DCD MAA_IRQHandler ; 26:10 MAA
DCD WDT0_IRQHandler ; 27:11 WATCHDOG0
DCD WDT0_P_IRQHandler ; 28:12 WATCHDOG0 PRE-WINDOW
DCD WDT1_IRQHandler ; 29:13 WATCHDOG1
DCD WDT1_P_IRQHandler ; 30:14 WATCHDOG1 PRE-WINDOW
DCD GPIO_P0_IRQHandler ; 31:15 GPIO Port 0
DCD GPIO_P1_IRQHandler ; 32:16 GPIO Port 1
DCD GPIO_P2_IRQHandler ; 33:17 GPIO Port 2
DCD GPIO_P3_IRQHandler ; 34:18 GPIO Port 3
DCD GPIO_P4_IRQHandler ; 35:19 GPIO Port 4
DCD GPIO_P5_IRQHandler ; 36:20 GPIO Port 5
DCD GPIO_P6_IRQHandler ; 37:21 GPIO Port 6
DCD TMR0_IRQHandler ; 38:22 Timer32-0
DCD TMR16_0_IRQHandler ; 39:23 Timer16-s0
DCD TMR1_IRQHandler ; 40:24 Timer32-1
DCD TMR16_1_IRQHandler ; 41:25 Timer16-s1
DCD TMR2_IRQHandler ; 42:26 Timer32-2
DCD TMR16_2_IRQHandler ; 43:27 Timer16-s2
DCD TMR3_IRQHandler ; 44:28 Timer32-3
DCD TMR16_3_IRQHandler ; 45:29 Timer16-s3
DCD TMR4_IRQHandler ; 46:30 Timer32-4
DCD TMR16_4_IRQHandler ; 47:31 Timer16-s4
DCD TMR5_IRQHandler ; 48:32 Timer32-5
DCD TMR16_5_IRQHandler ; 49:33 Timer16-s5
DCD UART0_IRQHandler ; 50:34 UART0
DCD UART1_IRQHandler ; 51:35 UART1
DCD UART2_IRQHandler ; 52:36 UART2
DCD UART3_IRQHandler ; 53:37 UART3
DCD PT_IRQHandler ; 54:38 PT
DCD I2CM0_IRQHandler ; 55:39 I2C Master 0
DCD I2CM1_IRQHandler ; 56:40 I2C Master 1
DCD I2CM2_IRQHandler ; 57:41 I2C Master 2
DCD I2CS_IRQHandler ; 58:42 I2C Slave
DCD SPIM0_IRQHandler ; 59:43 SPIM0
DCD SPIM1_IRQHandler ; 60:44 SPIM1
DCD SPIM2_IRQHandler ; 61:45 SPIM2
DCD SPIB_IRQHandler ; 62:46 SPI Bridge
DCD OWM_IRQHandler ; 63:47 OWM Master
DCD AFE_IRQHandler ; 64:48 AFE
DCD SPIS_IRQHandler ; 65:49 SPI Slave
DCD GPIO_P7_IRQHandler ; 66:50 GPIO Port 7
DCD GPIO_P8_IRQHandler ; 67:51 GPIO Port 8
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT PreInit
IMPORT SystemInit
IMPORT __main
LDR R0, =PreInit
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
__SPIN
WFI
BL __SPIN
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B NMI_Handler
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler\
PROC
; MAX32625 Interrupts
EXPORT CLKMAN_IRQHandler [WEAK] ; 16:00 CLKMAN
EXPORT PWRMAN_IRQHandler [WEAK] ; 17:01 PWRMAN
EXPORT FLC_IRQHandler [WEAK] ; 18:02 Flash Controller
EXPORT RTC0_IRQHandler [WEAK] ; 19:03 RTC INT0
EXPORT RTC1_IRQHandler [WEAK] ; 20:04 RTC INT1
EXPORT RTC2_IRQHandler [WEAK] ; 21:05 RTC INT2
EXPORT RTC3_IRQHandler [WEAK] ; 22:06 RTC INT3
EXPORT PMU_IRQHandler [WEAK] ; 23:07 PMU
EXPORT USB_IRQHandler [WEAK] ; 24:08 USB
EXPORT AES_IRQHandler [WEAK] ; 25:09 AES
EXPORT MAA_IRQHandler [WEAK] ; 26:10 MAA
EXPORT WDT0_IRQHandler [WEAK] ; 27:11 WATCHDOG0
EXPORT WDT0_P_IRQHandler [WEAK] ; 28:12 WATCHDOG0 PRE-WINDOW
EXPORT WDT1_IRQHandler [WEAK] ; 29:13 WATCHDOG1
EXPORT WDT1_P_IRQHandler [WEAK] ; 30:14 WATCHDOG1 PRE-WINDOW
EXPORT GPIO_P0_IRQHandler [WEAK] ; 31:15 GPIO Port 0
EXPORT GPIO_P1_IRQHandler [WEAK] ; 32:16 GPIO Port 1
EXPORT GPIO_P2_IRQHandler [WEAK] ; 33:17 GPIO Port 2
EXPORT GPIO_P3_IRQHandler [WEAK] ; 34:18 GPIO Port 3
EXPORT GPIO_P4_IRQHandler [WEAK] ; 35:19 GPIO Port 4
EXPORT GPIO_P5_IRQHandler [WEAK] ; 36:20 GPIO Port 5
EXPORT GPIO_P6_IRQHandler [WEAK] ; 37:21 GPIO Port 6
EXPORT TMR0_IRQHandler [WEAK] ; 38:22 Timer32-0
EXPORT TMR16_0_IRQHandler [WEAK] ; 39:23 Timer16-s0
EXPORT TMR1_IRQHandler [WEAK] ; 40:24 Timer32-1
EXPORT TMR16_1_IRQHandler [WEAK] ; 41:25 Timer16-s1
EXPORT TMR2_IRQHandler [WEAK] ; 42:26 Timer32-2
EXPORT TMR16_2_IRQHandler [WEAK] ; 43:27 Timer16-s2
EXPORT TMR3_IRQHandler [WEAK] ; 44:28 Timer32-3
EXPORT TMR16_3_IRQHandler [WEAK] ; 45:29 Timer16-s3
EXPORT TMR4_IRQHandler [WEAK] ; 46:30 Timer32-4
EXPORT TMR16_4_IRQHandler [WEAK] ; 47:31 Timer16-s4
EXPORT TMR5_IRQHandler [WEAK] ; 48:32 Timer32-5
EXPORT TMR16_5_IRQHandler [WEAK] ; 49:33 Timer16-s5
EXPORT UART0_IRQHandler [WEAK] ; 50:34 UART0
EXPORT UART1_IRQHandler [WEAK] ; 51:35 UART1
EXPORT UART2_IRQHandler [WEAK] ; 52:36 UART2
EXPORT UART3_IRQHandler [WEAK] ; 53:37 UART3
EXPORT PT_IRQHandler [WEAK] ; 54:38 PT
EXPORT I2CM0_IRQHandler [WEAK] ; 55:39 I2C Master 0
EXPORT I2CM1_IRQHandler [WEAK] ; 56:40 I2C Master 1
EXPORT I2CM2_IRQHandler [WEAK] ; 57:41 I2C Master 2
EXPORT I2CS_IRQHandler [WEAK] ; 58:42 I2C Slave
EXPORT SPIM0_IRQHandler [WEAK] ; 59:43 SPIM0
EXPORT SPIM1_IRQHandler [WEAK] ; 60:44 SPIM1
EXPORT SPIM2_IRQHandler [WEAK] ; 61:45 SPIM2
EXPORT SPIB_IRQHandler [WEAK] ; 62:46 SPI Bridge
EXPORT OWM_IRQHandler [WEAK] ; 63:47 SPI Bridge
EXPORT AFE_IRQHandler [WEAK] ; 64:48 AFE
EXPORT SPIS_IRQHandler [WEAK] ; 65:49 SPI Slave
EXPORT GPIO_P7_IRQHandler [WEAK] ; 66:50 GPIO Port 7
EXPORT GPIO_P8_IRQHandler [WEAK] ; 67:51 GPIO Port 8
CLKMAN_IRQHandler
PWRMAN_IRQHandler
FLC_IRQHandler
RTC0_IRQHandler
RTC1_IRQHandler
RTC2_IRQHandler
RTC3_IRQHandler
PMU_IRQHandler
USB_IRQHandler
AES_IRQHandler
MAA_IRQHandler
WDT0_IRQHandler
WDT0_P_IRQHandler
WDT1_IRQHandler
WDT1_P_IRQHandler
GPIO_P0_IRQHandler
GPIO_P1_IRQHandler
GPIO_P2_IRQHandler
GPIO_P3_IRQHandler
GPIO_P4_IRQHandler
GPIO_P5_IRQHandler
GPIO_P6_IRQHandler
TMR0_IRQHandler
TMR16_0_IRQHandler
TMR1_IRQHandler
TMR16_1_IRQHandler
TMR2_IRQHandler
TMR16_2_IRQHandler
TMR3_IRQHandler
TMR16_3_IRQHandler
TMR4_IRQHandler
TMR16_4_IRQHandler
TMR5_IRQHandler
TMR16_5_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PT_IRQHandler
I2CM0_IRQHandler
I2CM1_IRQHandler
I2CM2_IRQHandler
I2CS_IRQHandler
SPIM0_IRQHandler
SPIM1_IRQHandler
SPIM2_IRQHandler
SPIB_IRQHandler
OWM_IRQHandler
AFE_IRQHandler
SPIS_IRQHandler
GPIO_P7_IRQHandler
GPIO_P8_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap\
PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
;;;;;;;;;;;;;;;;;;;;;;;;;
;; End of file.
;;;;;;;;;;;;;;;;;;;;;;;;;
|
wuxx/nanoDAP | 11,449 | software/DAPLink/source/hic_hal/atmel/sam3u2c/gcc/startup_SAM3U.S | /**
* @file startup_MK20D5.s
* @brief
*
* DAPLink Interface Firmware
* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long SUPC_IRQHandler /* 0: Supply Controller */
.long RSTC_IRQHandler /* 1: Reset Controller */
.long RTC_IRQHandler /* 2: Real Time Clock */
.long RTT_IRQHandler /* 3: Real Time Timer */
.long WDT_IRQHandler /* 4: Watchdog Timer */
.long PMC_IRQHandler /* 5: Power Management Controller */
.long EEFC0_IRQHandler /* 6: Enhanced Embedded Flash Controller 0 */
.long EEFC1_IRQHandler /* 7: Enhanced Embedded Flash Controller 1 */
.long UART_IRQHandler /* 8: UART */
.long SMC_IRQHandler /* 9: Static Memory Controller */
.long PIOA_IRQHandler /* 10: Parallel I/O Controller A */
.long PIOB_IRQHandler /* 11: Parallel I/O Controller B */
.long PIOC_IRQHandler /* 12: Parallel I/O Controller C */
.long USART0_IRQHandler /* 13: USART 0 */
.long USART1_IRQHandler /* 14: USART 1 */
.long USART2_IRQHandler /* 15: USART 2 */
.long USART3_IRQHandler /* 16: USART 3 */
.long HSMCI_IRQHandler /* 17: High Speed Multimedia Card Interface */
.long TWI0_IRQHandler /* 18: Two-wire Interface 0 */
.long TWI1_IRQHandler /* 19: Two-wire Interface 1 */
.long SPI_IRQHandler /* 20: Synchronous Peripheral Interface */
.long SSC_IRQHandler /* 21: Synchronous Serial Controller */
.long TC0_IRQHandler /* 22: Timer Counter 0 */
.long TC1_IRQHandler /* 23: Timer Counter 1 */
.long TC2_IRQHandler /* 24: Timer Counter 2 */
.long PWM_IRQHandler /* 25: Pulse Width Modulation Controller */
.long ADC12B_IRQHandler /* 26: 12-bit ADC Controller */
.long ADC_IRQHandler /* 27: 10-bit ADC Controller */
.long DMAC_IRQHandler /* 28: DMA Controller */
.long UDPHS_IRQHandler /* 29: USB Device High Speed */
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
ldr r0,=MemManage_Handler
bx r0
.size MemManage_Handler, . - MemManage_Handler
.align 1
.thumb_func
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
ldr r0,=BusFault_Handler
bx r0
.size BusFault_Handler, . - BusFault_Handler
.align 1
.thumb_func
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
ldr r0,=UsageFault_Handler
bx r0
.size UsageFault_Handler, . - UsageFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
ldr r0,=DebugMon_Handler
bx r0
.size DebugMon_Handler, . - DebugMon_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler SUPC_IRQHandler /* 0: Supply Controller */
def_irq_handler RSTC_IRQHandler /* 1: Reset Controller */
def_irq_handler RTC_IRQHandler /* 2: Real Time Clock */
def_irq_handler RTT_IRQHandler /* 3: Real Time Timer */
def_irq_handler WDT_IRQHandler /* 4: Watchdog Timer */
def_irq_handler PMC_IRQHandler /* 5: Power Management Controller */
def_irq_handler EEFC0_IRQHandler /* 6: Enhanced Embedded Flash Controller 0 */
def_irq_handler EEFC1_IRQHandler /* 7: Enhanced Embedded Flash Controller 1 */
def_irq_handler UART_IRQHandler /* 8: UART */
def_irq_handler SMC_IRQHandler /* 9: Static Memory Controller */
def_irq_handler PIOA_IRQHandler /* 10: Parallel I/O Controller A */
def_irq_handler PIOB_IRQHandler /* 11: Parallel I/O Controller B */
def_irq_handler PIOC_IRQHandler /* 12: Parallel I/O Controller C */
def_irq_handler USART0_IRQHandler /* 13: USART 0 */
def_irq_handler USART1_IRQHandler /* 14: USART 1 */
def_irq_handler USART2_IRQHandler /* 15: USART 2 */
def_irq_handler USART3_IRQHandler /* 16: USART 3 */
def_irq_handler HSMCI_IRQHandler /* 17: High Speed Multimedia Card Interface */
def_irq_handler TWI0_IRQHandler /* 18: Two-wire Interface 0 */
def_irq_handler TWI1_IRQHandler /* 19: Two-wire Interface 1 */
def_irq_handler SPI_IRQHandler /* 20: Synchronous Peripheral Interface */
def_irq_handler SSC_IRQHandler /* 21: Synchronous Serial Controller */
def_irq_handler TC0_IRQHandler /* 22: Timer Counter 0 */
def_irq_handler TC1_IRQHandler /* 23: Timer Counter 1 */
def_irq_handler TC2_IRQHandler /* 24: Timer Counter 2 */
def_irq_handler PWM_IRQHandler /* 25: Pulse Width Modulation Controller */
def_irq_handler ADC12B_IRQHandler /* 26: 12-bit ADC Controller */
def_irq_handler ADC_IRQHandler /* 27: 10-bit ADC Controller */
def_irq_handler DMAC_IRQHandler /* 28: DMA Controller */
def_irq_handler UDPHS_IRQHandler /* 29: USB Device High Speed */
.end
|
wuxx/nanoDAP | 9,905 | software/DAPLink/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s | ;/*****************************************************************************
; * @file: startup_SAM3U.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Atmel SAM3U Device Series
; * @version: V1.10
; * @date: 17. April 2013
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
#include "daplink_defaults.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU DAPLINK_STACK_SIZE
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU DAPLINK_HEAP_SIZE
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT g_board_info
__Vectors DCD __initial_sp ; 0: Top of Stack
DCD Reset_Handler ; 1: Reset Handler
DCD NMI_Handler ; 2: NMI Handler
DCD HardFault_Handler ; 3: Hard Fault Handler
DCD MemManage_Handler ; 4: MPU Fault Handler
DCD BusFault_Handler ; 5: Bus Fault Handler
DCD UsageFault_Handler ; 6: Usage Fault Handler
DCD 0 ; 7: Reserved
DCD DAPLINK_BUILD_KEY ; 8: DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; 9: DAPLINK: Compatibility
DCD DAPLINK_VERSION ; 10: DAPLINK: Version
DCD SVC_Handler ; 11: SVCall Handler
DCD DebugMon_Handler ; 12: Debug Monitor Handler
DCD g_board_info ; 13: DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; 14: PendSV Handler
DCD SysTick_Handler ; 15: SysTick Handler
; External Interrupts
DCD SUPC_IRQHandler ; 0: Supply Controller
DCD RSTC_IRQHandler ; 1: Reset Controller
DCD RTC_IRQHandler ; 2: Real Time Clock
DCD RTT_IRQHandler ; 3: Real Time Timer
DCD WDT_IRQHandler ; 4: Watchdog Timer
DCD PMC_IRQHandler ; 5: Power Management Controller
DCD EEFC0_IRQHandler ; 6: Enhanced Embedded Flash Controller 0
DCD EEFC1_IRQHandler ; 7: Enhanced Embedded Flash Controller 1
DCD UART_IRQHandler ; 8: UART
DCD SMC_IRQHandler ; 9: Static Memory Controller
DCD PIOA_IRQHandler ; 10: Parallel I/O Controller A
DCD PIOB_IRQHandler ; 11: Parallel I/O Controller B
DCD PIOC_IRQHandler ; 12: Parallel I/O Controller C
DCD USART0_IRQHandler ; 13: USART 0
DCD USART1_IRQHandler ; 14: USART 1
DCD USART2_IRQHandler ; 15: USART 2
DCD USART3_IRQHandler ; 16: USART 3
DCD HSMCI_IRQHandler ; 17: High Speed Multimedia Card Interface
DCD TWI0_IRQHandler ; 18: Two-wire Interface 0
DCD TWI1_IRQHandler ; 19: Two-wire Interface 1
DCD SPI_IRQHandler ; 20: Synchronous Peripheral Interface
DCD SSC_IRQHandler ; 21: Synchronous Serial Controller
DCD TC0_IRQHandler ; 22: Timer Counter 0
DCD TC1_IRQHandler ; 23: Timer Counter 1
DCD TC2_IRQHandler ; 24: Timer Counter 2
DCD PWM_IRQHandler ; 25: Pulse Width Modulation Controller
DCD ADC12B_IRQHandler ; 26: 12-bit ADC Controller
DCD ADC_IRQHandler ; 27: 10-bit ADC Controller
DCD DMAC_IRQHandler ; 28: DMA Controller
DCD UDPHS_IRQHandler ; 29: USB Device High Speed
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SUPC_IRQHandler [WEAK]
EXPORT RSTC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTT_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT PMC_IRQHandler [WEAK]
EXPORT EEFC0_IRQHandler [WEAK]
EXPORT EEFC1_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT SMC_IRQHandler [WEAK]
EXPORT PIOA_IRQHandler [WEAK]
EXPORT PIOB_IRQHandler [WEAK]
EXPORT PIOC_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT HSMCI_IRQHandler [WEAK]
EXPORT TWI0_IRQHandler [WEAK]
EXPORT TWI1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT SSC_IRQHandler [WEAK]
EXPORT TC0_IRQHandler [WEAK]
EXPORT TC1_IRQHandler [WEAK]
EXPORT TC2_IRQHandler [WEAK]
EXPORT PWM_IRQHandler [WEAK]
EXPORT ADC12B_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DMAC_IRQHandler [WEAK]
EXPORT UDPHS_IRQHandler [WEAK]
SUPC_IRQHandler
RSTC_IRQHandler
RTC_IRQHandler
RTT_IRQHandler
WDT_IRQHandler
PMC_IRQHandler
EEFC0_IRQHandler
EEFC1_IRQHandler
UART_IRQHandler
SMC_IRQHandler
PIOA_IRQHandler
PIOB_IRQHandler
PIOC_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
HSMCI_IRQHandler
TWI0_IRQHandler
TWI1_IRQHandler
SPI_IRQHandler
SSC_IRQHandler
TC0_IRQHandler
TC1_IRQHandler
TC2_IRQHandler
PWM_IRQHandler
ADC12B_IRQHandler
ADC_IRQHandler
DMAC_IRQHandler
UDPHS_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 16,532 | software/DAPLink/source/hic_hal/freescale/kl27z/gcc/startup_MKL27Z4.S | /* ------------------------------------------------------------------------- */
/* @file: startup_MKL27Z4.s */
/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
/* MKL27Z4 */
/* @version: 1.8 */
/* @date: 2016-6-24 */
/* @build: b190918 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2019 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long 0 /* Reserved*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
.long Reserved20_IRQHandler /* Reserved interrupt*/
.long FTFA_IRQHandler /* Command complete and read collision*/
.long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/
.long LLWU_IRQHandler /* Low leakage wakeup*/
.long I2C0_IRQHandler /* I2C0 interrupt*/
.long I2C1_IRQHandler /* I2C1 interrupt*/
.long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
.long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
.long LPUART0_IRQHandler /* LPUART0 status and error*/
.long LPUART1_IRQHandler /* LPUART1 status and error*/
.long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/
.long ADC0_IRQHandler /* ADC0 interrupt*/
.long CMP0_IRQHandler /* CMP0 interrupt*/
.long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
.long RTC_IRQHandler /* RTC alarm*/
.long RTC_Seconds_IRQHandler /* RTC seconds*/
.long PIT_IRQHandler /* PIT interrupt*/
.long I2S0_IRQHandler /* I2S0 interrupt*/
.long USB0_IRQHandler /* USB0 interrupt*/
.long DAC0_IRQHandler /* DAC0 interrupt*/
.long Reserved42_IRQHandler /* Reserved interrupt*/
.long Reserved43_IRQHandler /* Reserved interrupt*/
.long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
.long Reserved45_IRQHandler /* Reserved interrupt*/
.long PORTA_IRQHandler /* PORTA Pin detect*/
.long PORTCD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/
.size __isr_vector, . - __isr_vector
#if defined(DAPLINK_BL)
/* Bootloader Configuration Area (BCA) used by Kinetis ROM Bootloader */
.section .BootloaderConfig, "a"
.long 0x6766636B /* 0x00 Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'. */
.long 0xFFFFFFFF /* 0x04 Reserved */
.long 0xFFFFFFFF /* 0x08 Reserved */
.long 0xFFFFFFFF /* 0x0C Reserved */
.byte 0x10 /* 0x10 Bitfield of peripherals to enable. bit 0 LPUART, bit 1 I2C, bit 2 SPI, bit 4 USB. 0x10 = USB only */
.byte 0xFF /* 0x11 i2cSlaveAddress */
.byte 0xFF, 0xFF /* 0x12 peripheralDetectionTimeout */
.byte 0xFF, 0xFF /* 0x14 usbVid */
.byte 0xFF, 0xFF /* 0x16 usbPid */
.long 0xFFFFFFFF /* 0x18 usbStringsPointer */
.byte 0xFF /* 0x1C clockFlags */
.byte 0xFF /* 0x1D clockDivider */
.byte 0xFF /* 0x1E bootFlags */
.byte 0xFF /* 0x1F pad byte */
.long 0xFFFFFFFF /* 0x20 Reserved */
.long 0xFFFFFFFF /* 0x24 Reserved */
.long 0xFFFFFFFF /* 0x28 Reserved */
.long 0xFFFFFFFF /* 0x2C Reserved */
.long 0xFFFFFFFF /* 0x30 Reserved */
.long 0xFFFFFFFF /* 0x34 Reserved */
.long 0xFFFFFFFF /* 0x38 Reserved */
.long 0xFFFFFFFF /* 0x3C Reserved */
/* Flash Configuration */
.section .FlashConfig, "a"
#if defined(MICROBIT_LOCK_BOOTLOADER)
/* Backdoor Comparison Key: "MICROBIT" */
.long 0x5243494D
.long 0x5449424F
/* Program flash protection bytes (FPROT): Protect the first 32 kB of flash */
.long 0xFFFFFFF0
/* Flash security byte (FSEC)
* KEYEN [6:7] -> 0b10 Backdoor key access enabled
* MEEN [4:5] -> 0b11 Mass erase is enabled
* FSLACC [2:3] -> 0b11 NXP factory access granted
* SEC [0:1] -> 0b10 MCU security status is unsecure
*/
.byte 0xBE
/* Flash nonvolatile option byte (FOPT):
* BOOTSRC_SEL [7:6] -> 0b00 Boot from flash
* FAST_INIT [5] -> 0b1 Fast Initialization
* RESET_PIN_CFG [3] -> 0b1 RESET_b pin is dedicated
* NMI_DIS [2] -> 0b0 NMI interrupts are always blocked
* BOOTPIN_OPT [1] -> 0b0 Force Boot from ROM if BOOTCFG0 asserted
* LPBOOT [4:0] -> 0b11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1)
*/
.byte 0x39
/* 2 reserved bytes */
.byte 0xFF, 0xFF
#else
/* Backdoor Comparison Key: Unset */
.long 0xFFFFFFFF
.long 0xFFFFFFFF
/* Program flash protection bytes (FPROT): None */
.long 0xFFFFFFFF
/* Flash security byte (FSEC)
* KEYEN [6:7] -> 0b11 Backdoor key access disabled
* MEEN [4:5] -> 0b11 Mass erase is enabled
* FSLACC [2:3] -> 0b11 NXP factory access granted
* SEC [0:1] -> 0b10 MCU security status is unsecure
*/
.byte 0xFE
/* Flash nonvolatile option byte (FOPT):
* BOOTSRC_SEL [7:6] -> 0b00 Boot from flash
* FAST_INIT [5] -> 0b1 Fast Initialization
* RESET_PIN_CFG [3] -> 0b1 RESET_b pin is dedicated
* NMI_DIS [2] -> 0b0 NMI interrupts are always blocked
* BOOTPIN_OPT [1] -> 0b1 Boot source configured by FOPT[7:6] (BOOTSRC_SEL) bits
* LPBOOT [4:0] -> 0b11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1)
*/
.byte 0x3B
/* 2 reserved bytes */
.byte 0xFF, 0xFF
#endif /* MICROBIT_LOCK_BOOTLOADER */
#endif /* DAPLINK_BL */
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
subs r2, r1
ble .LC3
movs r0, 0
.LC2:
str r0, [r1, r2]
subs r2, 4
bge .LC2
.LC3:
#endif
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
ldr r0, =DefaultISR
bx r0
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak DMA0_IRQHandler
.type DMA0_IRQHandler, %function
DMA0_IRQHandler:
ldr r0,=DMA0_DriverIRQHandler
bx r0
.size DMA0_IRQHandler, . - DMA0_IRQHandler
.align 1
.thumb_func
.weak DMA1_IRQHandler
.type DMA1_IRQHandler, %function
DMA1_IRQHandler:
ldr r0,=DMA1_DriverIRQHandler
bx r0
.size DMA1_IRQHandler, . - DMA1_IRQHandler
.align 1
.thumb_func
.weak DMA2_IRQHandler
.type DMA2_IRQHandler, %function
DMA2_IRQHandler:
ldr r0,=DMA2_DriverIRQHandler
bx r0
.size DMA2_IRQHandler, . - DMA2_IRQHandler
.align 1
.thumb_func
.weak DMA3_IRQHandler
.type DMA3_IRQHandler, %function
DMA3_IRQHandler:
ldr r0,=DMA3_DriverIRQHandler
bx r0
.size DMA3_IRQHandler, . - DMA3_IRQHandler
.align 1
.thumb_func
.weak I2C0_IRQHandler
.type I2C0_IRQHandler, %function
I2C0_IRQHandler:
ldr r0,=I2C0_DriverIRQHandler
bx r0
.size I2C0_IRQHandler, . - I2C0_IRQHandler
.align 1
.thumb_func
.weak I2C1_IRQHandler
.type I2C1_IRQHandler, %function
I2C1_IRQHandler:
ldr r0,=I2C1_DriverIRQHandler
bx r0
.size I2C1_IRQHandler, . - I2C1_IRQHandler
.align 1
.thumb_func
.weak SPI0_IRQHandler
.type SPI0_IRQHandler, %function
SPI0_IRQHandler:
ldr r0,=SPI0_DriverIRQHandler
bx r0
.size SPI0_IRQHandler, . - SPI0_IRQHandler
.align 1
.thumb_func
.weak SPI1_IRQHandler
.type SPI1_IRQHandler, %function
SPI1_IRQHandler:
ldr r0,=SPI1_DriverIRQHandler
bx r0
.size SPI1_IRQHandler, . - SPI1_IRQHandler
.align 1
.thumb_func
.weak LPUART0_IRQHandler
.type LPUART0_IRQHandler, %function
LPUART0_IRQHandler:
ldr r0,=LPUART0_DriverIRQHandler
bx r0
.size LPUART0_IRQHandler, . - LPUART0_IRQHandler
.align 1
.thumb_func
.weak LPUART1_IRQHandler
.type LPUART1_IRQHandler, %function
LPUART1_IRQHandler:
ldr r0,=LPUART1_DriverIRQHandler
bx r0
.size LPUART1_IRQHandler, . - LPUART1_IRQHandler
.align 1
.thumb_func
.weak UART2_FLEXIO_IRQHandler
.type UART2_FLEXIO_IRQHandler, %function
UART2_FLEXIO_IRQHandler:
ldr r0,=UART2_FLEXIO_DriverIRQHandler
bx r0
.size UART2_FLEXIO_IRQHandler, . - UART2_FLEXIO_IRQHandler
.align 1
.thumb_func
.weak I2S0_IRQHandler
.type I2S0_IRQHandler, %function
I2S0_IRQHandler:
ldr r0,=I2S0_DriverIRQHandler
bx r0
.size I2S0_IRQHandler, . - I2S0_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler DMA0_DriverIRQHandler
def_irq_handler DMA1_DriverIRQHandler
def_irq_handler DMA2_DriverIRQHandler
def_irq_handler DMA3_DriverIRQHandler
def_irq_handler Reserved20_IRQHandler
def_irq_handler FTFA_IRQHandler
def_irq_handler PMC_IRQHandler
def_irq_handler LLWU_IRQHandler
def_irq_handler I2C0_DriverIRQHandler
def_irq_handler I2C1_DriverIRQHandler
def_irq_handler SPI0_DriverIRQHandler
def_irq_handler SPI1_DriverIRQHandler
def_irq_handler LPUART0_DriverIRQHandler
def_irq_handler LPUART1_DriverIRQHandler
def_irq_handler UART2_FLEXIO_DriverIRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler TPM0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler PIT_IRQHandler
def_irq_handler I2S0_DriverIRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler Reserved42_IRQHandler
def_irq_handler Reserved43_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler Reserved45_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTCD_IRQHandler
.end
|
wuxx/nanoDAP | 19,277 | software/DAPLink/source/hic_hal/freescale/kl27z/armcc/startup_MKL27Z4.s | ; * ---------------------------------------------------------------------------------------
; * @file: startup_MKL27Z4.s
; * @purpose: CMSIS Cortex-M0P Core Device Startup File
; * MKL27Z4
; * @version: 1.5
; * @date: 2014-9-5
; * @build: b151212
; * ---------------------------------------------------------------------------------------
; *
; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; *
; * o Redistributions of source code must retain the above copyright notice, this list
; * of conditions and the following disclaimer.
; *
; * o Redistributions in binary form must reproduce the above copyright notice, this
; * list of conditions and the following disclaimer in the documentation and/or
; * other materials provided with the distribution.
; *
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
; * contributors may be used to endorse or promote products derived from this
; * software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ;Top of Stack
DCD Reset_Handler ;Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD DAPLINK_BUILD_KEY ;DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ;DAPLINK: Compatibility
DCD DAPLINK_VERSION ;DAPLINK: Version
DCD SVC_Handler ;SVCall Handler
DCD 0 ;Reserved
DCD g_board_info ;DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
DCD Reserved20_IRQHandler ;Reserved interrupt
DCD FTFA_IRQHandler ;Command complete and read collision
DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
DCD LLWU_IRQHandler ;Low leakage wakeup
DCD I2C0_IRQHandler ;I2C0 interrupt
DCD I2C1_IRQHandler ;I2C1 interrupt
DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
DCD LPUART0_IRQHandler ;LPUART0 status and error
DCD LPUART1_IRQHandler ;LPUART1 status and error
DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
DCD ADC0_IRQHandler ;ADC0 interrupt
DCD CMP0_IRQHandler ;CMP0 interrupt
DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
DCD RTC_IRQHandler ;RTC alarm
DCD RTC_Seconds_IRQHandler ;RTC seconds
DCD PIT_IRQHandler ;PIT interrupt
DCD I2S0_IRQHandler ;I2S0 interrupt
DCD USB0_IRQHandler ;USB0 interrupt
DCD DAC0_IRQHandler ;DAC0 interrupt
DCD Reserved42_IRQHandler ;Reserved interrupt
DCD Reserved43_IRQHandler ;Reserved interrupt
DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
DCD Reserved45_IRQHandler ;Reserved interrupt
DCD PORTA_IRQHandler ;PORTA Pin detect
DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; Bootloader Configuration Area (BCA) used by Kinetis ROM Bootloader
#if defined(DAPLINK_BL)
AREA |.ARM.__at_0x3C0 |, CODE, READONLY
; Offset Description
DCD 0x6766636B ; 0x00 Magic number to verify bootloader configuration is valid. Must be set to 'kcfg'.
DCD 0xFFFFFFFF ; 0x04 Reserved
DCD 0xFFFFFFFF ; 0x08 Reserved
DCD 0xFFFFFFFF ; 0x0C Reserved
DCB 0x10 ; 0x10 Bitfield of peripherals to enable. bit 0 LPUART, bit 1 I2C, bit 2 SPI, bit 4 USB. 0x10 = USB only
DCB 0xFF ; 0x11 i2cSlaveAddress
DCB 0xFF, 0xFF ; 0x12 peripheralDetectionTimeout
DCB 0xFF, 0xFF ; 0x14 usbVid
DCB 0xFF, 0xFF ; 0x16 usbPid
DCD 0xFFFFFFFF ; 0x18 usbStringsPointer
DCB 0xFF ; 0x1C clockFlags
DCB 0xFF ; 0x1D clockDivider
DCB 0xFF ; 0x1E bootFlags
DCB 0xFF ; 0x1F pad byte
DCD 0xFFFFFFFF ; 0x20 Reserved
DCD 0xFFFFFFFF ; 0x24 Reserved
DCD 0xFFFFFFFF ; 0x28 Reserved
DCD 0xFFFFFFFF ; 0x2C Reserved
DCD 0xFFFFFFFF ; 0x30 Reserved
DCD 0xFFFFFFFF ; 0x34 Reserved
DCD 0xFFFFFFFF ; 0x38 Reserved
DCD 0xFFFFFFFF ; 0x3C Reserved
#endif
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict access to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
#if defined(MICROBIT_LOCK_BOOTLOADER)
BackDoorK0 EQU 0x4D ; 'M'
BackDoorK1 EQU 0x49 ; 'I'
BackDoorK2 EQU 0x43 ; 'C'
BackDoorK3 EQU 0x52 ; 'R'
BackDoorK4 EQU 0x4F ; 'O'
BackDoorK5 EQU 0x42 ; 'B'
BackDoorK6 EQU 0x49 ; 'I'
BackDoorK7 EQU 0x54 ; 'T'
#else
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
#endif
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 1/32 - 8/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
#if defined(MICROBIT_LOCK_BOOTLOADER)
nFPROT3 EQU 0x0F ; Enable protection of the first 32 kB of flash
#else
nFPROT3 EQU 0x00
#endif
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 9/32 - 16/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 17/32 - 24/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT0
; <i> Program Flash Region Protect Register 0
; <i> 25/32 - 32/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
; * <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
; <o.1> BOOTPIN_OPT
; * <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
; <o.2> NMI_DIS
; * <0=> NMI interrupts are always blocked
; <1=> NMI_b pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
; * <1=> RESET_b pin is dedicated
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
; * <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
; <o.5> FAST_INIT
; <0=> Slower initialization
; * <1=> Fast Initialization
; <o.6..7> BOOTSRC_SEL
; * <0=> Boot from Flash
; <2=> Boot from ROM
; <3=> Boot from ROM
; <i> Boot source selection
#if defined(MICROBIT_LOCK_BOOTLOADER)
FOPT EQU 0x39
#else
FOPT EQU 0x3B
#endif
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; * <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; * <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; * <3=> Mass erase is enabled
; <o.6..7> KEYEN
; * <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor Key Security Enable
#if defined(MICROBIT_LOCK_BOOTLOADER)
FSEC EQU 0xBE
#else
FSEC EQU 0xFE
#endif
; </h>
; </h>
#if defined(DAPLINK_BL)
AREA |.ARM.__at_0x400 |, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT3 , FPROT2 , FPROT1 , FPROT0
DCB FSEC , FOPT , 0xFF , 0xFF
#endif
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
CPSID I ; Mask interrupts
LDR R0, =SystemInit
BLX R0
CPSIE I ; Unmask interrupts
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
I2C0_IRQHandler\
PROC
EXPORT I2C0_IRQHandler [WEAK]
LDR R0, =I2C0_DriverIRQHandler
BX R0
ENDP
I2C1_IRQHandler\
PROC
EXPORT I2C1_IRQHandler [WEAK]
LDR R0, =I2C1_DriverIRQHandler
BX R0
ENDP
Default_Handler\
PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT PMC_IRQHandler [WEAK]
EXPORT LLWU_IRQHandler [WEAK]
EXPORT I2C0_DriverIRQHandler [WEAK]
EXPORT I2C1_DriverIRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT LPUART0_IRQHandler [WEAK]
EXPORT LPUART1_IRQHandler [WEAK]
EXPORT UART2_FLEXIO_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT Reserved42_IRQHandler [WEAK]
EXPORT Reserved43_IRQHandler [WEAK]
EXPORT LPTMR0_IRQHandler [WEAK]
EXPORT Reserved45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTCD_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
PMC_IRQHandler
LLWU_IRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
LPUART0_IRQHandler
LPUART1_IRQHandler
UART2_FLEXIO_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
I2S0_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
Reserved42_IRQHandler
Reserved43_IRQHandler
LPTMR0_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTCD_IRQHandler
DefaultISR
LDR R0, =DefaultISR
BX R0
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 11,988 | software/DAPLink/source/hic_hal/freescale/k20dx/gcc/startup_MK20D5.S | /**
* @file startup_MK20D5.s
* @brief
*
* DAPLink Interface Firmware
* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA channel 0 transfer complete*/
.long DMA1_IRQHandler /* DMA channel 1 transfer complete*/
.long DMA2_IRQHandler /* DMA channel 2 transfer complete*/
.long DMA3_IRQHandler /* DMA channel 3 transfer complete*/
.long DMA_Error_IRQHandler /* DMA channel 0 - 15 error*/
.long Reserved21_IRQHandler /* Reserved interrupt 21 */
.long FTFL_IRQHandler /* FTFL interrupt */
.long Read_Collision_IRQHandler /* Read collision interrupt */
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
.long LLW_IRQHandler /* Low Leakage Wakeup */
.long Watchdog_IRQHandler /* WDOG interrupt */
.long I2C0_IRQHandler /* I2C0 interrupt */
.long SPI0_IRQHandler /* SPI0 interrupt */
.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt */
.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt */
.long UART0_LON_IRQHandler /* UART0 LON interrupt */
.long UART0_RX_TX_IRQHandler /* UART0 receive/transmit interrupt */
.long UART0_ERR_IRQHandler /* UART0 error interrupt */
.long UART1_RX_TX_IRQHandler /* UART1 receive/transmit interrupt */
.long UART1_ERR_IRQHandler /* UART1 error interrupt */
.long UART2_RX_TX_IRQHandler /* UART2 receive/transmit interrupt */
.long UART2_ERR_IRQHandler /* UART2 error interrupt */
.long ADC0_IRQHandler /* ADC0 interrupt */
.long CMP0_IRQHandler /* CMP0 interrupt */
.long CMP1_IRQHandler /* CMP1 interrupt */
.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt */
.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt */
.long CMT_IRQHandler /* CMT interrupt */
.long RTC_IRQHandler /* RTC interrupt */
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
.long PIT0_IRQHandler /* PIT timer channel 0 interrupt */
.long PIT1_IRQHandler /* PIT timer channel 1 interrupt */
.long PIT2_IRQHandler /* PIT timer channel 2 interrupt */
.long PIT3_IRQHandler /* PIT timer channel 3 interrupt */
.long PDB0_IRQHandler /* PDB0 interrupt */
.long USB0_IRQHandler /* USB0 interrupt */
.long USBDCD_IRQHandler /* USBDCD interrupt */
.long TSI0_IRQHandler /* TSI0 interrupt */
.long MCG_IRQHandler /* MCG interrupt */
.long LPTimer_IRQHandler /* LPTimer interrupt */
.long PORTA_IRQHandler /* Port A interrupt */
.long PORTB_IRQHandler /* Port B interrupt */
.long PORTC_IRQHandler /* Port C interrupt */
.long PORTD_IRQHandler /* Port D interrupt */
.long PORTE_IRQHandler /* Port E interrupt */
.long SWI_IRQHandler /* Software interrupt */
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFE
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
ldr r0,=MemManage_Handler
bx r0
.size MemManage_Handler, . - MemManage_Handler
.align 1
.thumb_func
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
ldr r0,=BusFault_Handler
bx r0
.size BusFault_Handler, . - BusFault_Handler
.align 1
.thumb_func
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
ldr r0,=UsageFault_Handler
bx r0
.size UsageFault_Handler, . - UsageFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
ldr r0,=DebugMon_Handler
bx r0
.size DebugMon_Handler, . - DebugMon_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler Reserved21_IRQHandler
def_irq_handler FTFL_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler LLW_IRQHandler
def_irq_handler Watchdog_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler I2S0_Tx_IRQHandler
def_irq_handler I2S0_Rx_IRQHandler
def_irq_handler UART0_LON_IRQHandler
def_irq_handler UART0_RX_TX_IRQHandler
def_irq_handler UART0_ERR_IRQHandler
def_irq_handler UART1_RX_TX_IRQHandler
def_irq_handler UART1_ERR_IRQHandler
def_irq_handler UART2_RX_TX_IRQHandler
def_irq_handler UART2_ERR_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler CMP1_IRQHandler
def_irq_handler FTM0_IRQHandler
def_irq_handler FTM1_IRQHandler
def_irq_handler CMT_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler PIT0_IRQHandler
def_irq_handler PIT1_IRQHandler
def_irq_handler PIT2_IRQHandler
def_irq_handler PIT3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler USBDCD_IRQHandler
def_irq_handler TSI0_IRQHandler
def_irq_handler MCG_IRQHandler
def_irq_handler LPTimer_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
.end
|
wuxx/nanoDAP | 25,000 | software/DAPLink/source/hic_hal/freescale/k20dx/armcc/startup_MK20D5.s | ;/**
; * @file startup_MK20D5.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD DMA_Error_IRQHandler ; DMA error interrupt
DCD Reserved21_IRQHandler ; Reserved interrupt 21
DCD FTFL_IRQHandler ; FTFL interrupt
DCD Read_Collision_IRQHandler ; Read collision interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG interrupt
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD SWI_IRQHandler ; Software interrupt
DCD DefaultISR ; 62
DCD DefaultISR ; 63
DCD DefaultISR ; 64
DCD DefaultISR ; 65
DCD DefaultISR ; 66
DCD DefaultISR ; 67
DCD DefaultISR ; 68
DCD DefaultISR ; 69
DCD DefaultISR ; 70
DCD DefaultISR ; 71
DCD DefaultISR ; 72
DCD DefaultISR ; 73
DCD DefaultISR ; 74
DCD DefaultISR ; 75
DCD DefaultISR ; 76
DCD DefaultISR ; 77
DCD DefaultISR ; 78
DCD DefaultISR ; 79
DCD DefaultISR ; 80
DCD DefaultISR ; 81
DCD DefaultISR ; 82
DCD DefaultISR ; 83
DCD DefaultISR ; 84
DCD DefaultISR ; 85
DCD DefaultISR ; 86
DCD DefaultISR ; 87
DCD DefaultISR ; 88
DCD DefaultISR ; 89
DCD DefaultISR ; 90
DCD DefaultISR ; 91
DCD DefaultISR ; 92
DCD DefaultISR ; 93
DCD DefaultISR ; 94
DCD DefaultISR ; 95
DCD DefaultISR ; 96
DCD DefaultISR ; 97
DCD DefaultISR ; 98
DCD DefaultISR ; 99
DCD DefaultISR ; 100
DCD DefaultISR ; 101
DCD DefaultISR ; 102
DCD DefaultISR ; 103
DCD DefaultISR ; 104
DCD DefaultISR ; 105
DCD DefaultISR ; 106
DCD DefaultISR ; 107
DCD DefaultISR ; 108
DCD DefaultISR ; 109
DCD DefaultISR ; 110
DCD DefaultISR ; 111
DCD DefaultISR ; 112
DCD DefaultISR ; 113
DCD DefaultISR ; 114
DCD DefaultISR ; 115
DCD DefaultISR ; 116
DCD DefaultISR ; 117
DCD DefaultISR ; 118
DCD DefaultISR ; 119
DCD DefaultISR ; 120
DCD DefaultISR ; 121
DCD DefaultISR ; 122
DCD DefaultISR ; 123
DCD DefaultISR ; 124
DCD DefaultISR ; 125
DCD DefaultISR ; 126
DCD DefaultISR ; 127
DCD DefaultISR ; 128
DCD DefaultISR ; 129
DCD DefaultISR ; 130
DCD DefaultISR ; 131
DCD DefaultISR ; 132
DCD DefaultISR ; 133
DCD DefaultISR ; 134
DCD DefaultISR ; 135
DCD DefaultISR ; 136
DCD DefaultISR ; 137
DCD DefaultISR ; 138
DCD DefaultISR ; 139
DCD DefaultISR ; 140
DCD DefaultISR ; 141
DCD DefaultISR ; 142
DCD DefaultISR ; 143
DCD DefaultISR ; 144
DCD DefaultISR ; 145
DCD DefaultISR ; 146
DCD DefaultISR ; 147
DCD DefaultISR ; 148
DCD DefaultISR ; 149
DCD DefaultISR ; 150
DCD DefaultISR ; 151
DCD DefaultISR ; 152
DCD DefaultISR ; 153
DCD DefaultISR ; 154
DCD DefaultISR ; 155
DCD DefaultISR ; 156
DCD DefaultISR ; 157
DCD DefaultISR ; 158
DCD DefaultISR ; 159
DCD DefaultISR ; 160
DCD DefaultISR ; 161
DCD DefaultISR ; 162
DCD DefaultISR ; 163
DCD DefaultISR ; 164
DCD DefaultISR ; 165
DCD DefaultISR ; 166
DCD DefaultISR ; 167
DCD DefaultISR ; 168
DCD DefaultISR ; 169
DCD DefaultISR ; 170
DCD DefaultISR ; 171
DCD DefaultISR ; 172
DCD DefaultISR ; 173
DCD DefaultISR ; 174
DCD DefaultISR ; 175
DCD DefaultISR ; 176
DCD DefaultISR ; 177
DCD DefaultISR ; 178
DCD DefaultISR ; 179
DCD DefaultISR ; 180
DCD DefaultISR ; 181
DCD DefaultISR ; 182
DCD DefaultISR ; 183
DCD DefaultISR ; 184
DCD DefaultISR ; 185
DCD DefaultISR ; 186
DCD DefaultISR ; 187
DCD DefaultISR ; 188
DCD DefaultISR ; 189
DCD DefaultISR ; 190
DCD DefaultISR ; 191
DCD DefaultISR ; 192
DCD DefaultISR ; 193
DCD DefaultISR ; 194
DCD DefaultISR ; 195
DCD DefaultISR ; 196
DCD DefaultISR ; 197
DCD DefaultISR ; 198
DCD DefaultISR ; 199
DCD DefaultISR ; 200
DCD DefaultISR ; 201
DCD DefaultISR ; 202
DCD DefaultISR ; 203
DCD DefaultISR ; 204
DCD DefaultISR ; 205
DCD DefaultISR ; 206
DCD DefaultISR ; 207
DCD DefaultISR ; 208
DCD DefaultISR ; 209
DCD DefaultISR ; 210
DCD DefaultISR ; 211
DCD DefaultISR ; 212
DCD DefaultISR ; 213
DCD DefaultISR ; 214
DCD DefaultISR ; 215
DCD DefaultISR ; 216
DCD DefaultISR ; 217
DCD DefaultISR ; 218
DCD DefaultISR ; 219
DCD DefaultISR ; 220
DCD DefaultISR ; 221
DCD DefaultISR ; 222
DCD DefaultISR ; 223
DCD DefaultISR ; 224
DCD DefaultISR ; 225
DCD DefaultISR ; 226
DCD DefaultISR ; 227
DCD DefaultISR ; 228
DCD DefaultISR ; 229
DCD DefaultISR ; 230
DCD DefaultISR ; 231
DCD DefaultISR ; 232
DCD DefaultISR ; 233
DCD DefaultISR ; 234
DCD DefaultISR ; 235
DCD DefaultISR ; 236
DCD DefaultISR ; 237
DCD DefaultISR ; 238
DCD DefaultISR ; 239
DCD DefaultISR ; 240
DCD DefaultISR ; 241
DCD DefaultISR ; 242
DCD DefaultISR ; 243
DCD DefaultISR ; 244
DCD DefaultISR ; 245
DCD DefaultISR ; 246
DCD DefaultISR ; 247
DCD DefaultISR ; 248
DCD DefaultISR ; 249
DCD DefaultISR ; 250
DCD DefaultISR ; 251
DCD DefaultISR ; 252
DCD DefaultISR ; 253
DCD DefaultISR ; 254
DCD DefaultISR ; 255
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFD
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x8400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT Reserved21_IRQHandler [WEAK]
EXPORT FTFL_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA_Error_IRQHandler
Reserved21_IRQHandler
FTFL_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
Watchdog_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
I2S0_Tx_IRQHandler
I2S0_Rx_IRQHandler
UART0_LON_IRQHandler
UART0_RX_TX_IRQHandler
UART0_ERR_IRQHandler
UART1_RX_TX_IRQHandler
UART1_ERR_IRQHandler
UART2_RX_TX_IRQHandler
UART2_ERR_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
DefaultISR
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 12,762 | software/DAPLink/source/hic_hal/freescale/kl26z/gcc/startup_MKL26Z4.S | /* ------------------------------------------------------------------------- */
/* @file: startup_MKL26Z4.s */
/* @purpose: CMSIS Cortex-M0P Core Device Startup File */
/* MKL26Z4 */
/* @version: 1.8 */
/* @date: 2015-7-29 */
/* @build: b171205 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2017 NXP */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted (subject to the limitations in the */
/* disclaimer below) provided that the following conditions are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of the copyright holder nor the names of its */
/* contributors may be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT */
/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED */
/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */
/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */
/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */
/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */
/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN */
/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long 0 /* Reserved*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_IRQHandler /* DMA channel 0 transfer complete and error interrupt*/
.long DMA1_IRQHandler /* DMA channel 1 transfer complete and error interrupt*/
.long DMA2_IRQHandler /* DMA channel 2 transfer complete and error interrupt*/
.long DMA3_IRQHandler /* DMA channel 3 transfer complete and error interrupt*/
.long Reserved20_IRQHandler /* Reserved interrupt*/
.long FTFA_IRQHandler /* FTFA command complete and read collision*/
.long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/
.long LLWU_IRQHandler /* Low Leakage Wakeup*/
.long I2C0_IRQHandler /* I2C0 interrupt*/
.long I2C1_IRQHandler /* I2C1 interrupt*/
.long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
.long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
.long UART0_IRQHandler /* UART0 status and error*/
.long UART1_IRQHandler /* UART1 status and error*/
.long UART2_IRQHandler /* UART2 status and error*/
.long ADC0_IRQHandler /* ADC0 interrupt*/
.long CMP0_IRQHandler /* CMP0 interrupt*/
.long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
.long RTC_IRQHandler /* RTC alarm interrupt*/
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
.long PIT_IRQHandler /* PIT single interrupt vector for all channels*/
.long I2S0_IRQHandler /* I2S0 Single interrupt vector for all sources*/
.long USB0_IRQHandler /* USB0 OTG*/
.long DAC0_IRQHandler /* DAC0 interrupt*/
.long TSI0_IRQHandler /* TSI0 interrupt*/
.long MCG_IRQHandler /* MCG interrupt*/
.long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
.long Reserved45_IRQHandler /* Reserved interrupt*/
.long PORTA_IRQHandler /* PORTA pin detect*/
.long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC and PORTD pin detect*/
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFE
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
subs r2, r1
ble .LC3
movs r0, 0
.LC2:
str r0, [r1, r2]
subs r2, 4
bge .LC2
.LC3:
#endif
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
ldr r0, =DefaultISR
bx r0
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler Reserved20_IRQHandler
def_irq_handler FTFA_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler LLWU_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler TPM0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler PIT_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler TSI0_IRQHandler
def_irq_handler MCG_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler Reserved45_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTC_PORTD_IRQHandler
.end
|
wuxx/nanoDAP | 14,167 | software/DAPLink/source/hic_hal/freescale/kl26z/armcc/startup_MKL26Z4.s | ;/**
; * @file startup_MKL26Z.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD Reserved20_IRQHandler ; Reserved interrupt 20
DCD FTFA_IRQHandler ; FTFA interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C0 interrupt 25
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD UART0_IRQHandler ; UART0 status/error interrupt
DCD UART1_IRQHandler ; UART1 status/error interrupt
DCD UART2_IRQHandler ; UART2 status/error interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT_IRQHandler ; PIT timer interrupt
DCD Reserved39_IRQHandler ; Reserved interrupt 39
DCD USB0_IRQHandler ; USB0 interrupt
DCD DAC0_IRQHandler ; DAC interrupt
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved45_IRQHandler ; Reserved interrupt 45
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTD_IRQHandler ; Port D interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT0
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
; <o.4> LPBOOT1
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI pin/interrupts reset default to enabled
; <o.3> RESET_PIN_CFG
; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
; <1=> RESET pin is dedicated
; <o.3> FAST_INIT
; <0=> Slower initialization
; <1=> Fast Initialization
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x8400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, 0xFF, 0xFF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT Reserved20_IRQHandler [WEAK]
EXPORT FTFA_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT TPM0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved45_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
Reserved20_IRQHandler
FTFA_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
TPM0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT_IRQHandler
Reserved39_IRQHandler
USB0_IRQHandler
DAC0_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved45_IRQHandler
PORTA_IRQHandler
PORTD_IRQHandler
DefaultISR
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 20,730 | software/DAPLink/source/hic_hal/freescale/k26f/gcc/startup_MK26F18.S | /* ------------------------------------------------------------------------- */
/* @file: startup_MK26F18.s */
/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
/* MK26F18 */
/* @version: 2.0 */
/* @date: 2015-3-25 */
/* @build: b180801 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2018 NXP */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long DMA0_DMA16_IRQHandler /* DMA Channel 0, 16 Transfer Complete*/
.long DMA1_DMA17_IRQHandler /* DMA Channel 1, 17 Transfer Complete*/
.long DMA2_DMA18_IRQHandler /* DMA Channel 2, 18 Transfer Complete*/
.long DMA3_DMA19_IRQHandler /* DMA Channel 3, 19 Transfer Complete*/
.long DMA4_DMA20_IRQHandler /* DMA Channel 4, 20 Transfer Complete*/
.long DMA5_DMA21_IRQHandler /* DMA Channel 5, 21 Transfer Complete*/
.long DMA6_DMA22_IRQHandler /* DMA Channel 6, 22 Transfer Complete*/
.long DMA7_DMA23_IRQHandler /* DMA Channel 7, 23 Transfer Complete*/
.long DMA8_DMA24_IRQHandler /* DMA Channel 8, 24 Transfer Complete*/
.long DMA9_DMA25_IRQHandler /* DMA Channel 9, 25 Transfer Complete*/
.long DMA10_DMA26_IRQHandler /* DMA Channel 10, 26 Transfer Complete*/
.long DMA11_DMA27_IRQHandler /* DMA Channel 11, 27 Transfer Complete*/
.long DMA12_DMA28_IRQHandler /* DMA Channel 12, 28 Transfer Complete*/
.long DMA13_DMA29_IRQHandler /* DMA Channel 13, 29 Transfer Complete*/
.long DMA14_DMA30_IRQHandler /* DMA Channel 14, 30 Transfer Complete*/
.long DMA15_DMA31_IRQHandler /* DMA Channel 15, 31 Transfer Complete*/
.long DMA_Error_IRQHandler /* DMA Error Interrupt*/
.long MCM_IRQHandler /* Normal Interrupt*/
.long FTFE_IRQHandler /* FTFE Command complete interrupt*/
.long Read_Collision_IRQHandler /* Read Collision Interrupt*/
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
.long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/
.long WDOG_EWM_IRQHandler /* WDOG Interrupt*/
.long RNG_IRQHandler /* RNG Interrupt*/
.long I2C0_IRQHandler /* I2C0 interrupt*/
.long I2C1_IRQHandler /* I2C1 interrupt*/
.long SPI0_IRQHandler /* SPI0 Interrupt*/
.long SPI1_IRQHandler /* SPI1 Interrupt*/
.long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
.long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
.long Reserved46_IRQHandler /* Reserved interrupt 46*/
.long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
.long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
.long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
.long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
.long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
.long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
.long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/
.long UART3_ERR_IRQHandler /* UART3 Error interrupt*/
.long ADC0_IRQHandler /* ADC0 interrupt*/
.long CMP0_IRQHandler /* CMP0 interrupt*/
.long CMP1_IRQHandler /* CMP1 interrupt*/
.long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
.long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
.long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
.long CMT_IRQHandler /* CMT interrupt*/
.long RTC_IRQHandler /* RTC interrupt*/
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
.long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
.long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
.long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
.long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
.long PDB0_IRQHandler /* PDB0 Interrupt*/
.long USB0_IRQHandler /* USB0 interrupt*/
.long USBDCD_IRQHandler /* USBDCD Interrupt*/
.long Reserved71_IRQHandler /* Reserved interrupt 71*/
.long DAC0_IRQHandler /* DAC0 interrupt*/
.long MCG_IRQHandler /* MCG Interrupt*/
.long LPTMR0_IRQHandler /* LPTimer interrupt*/
.long PORTA_IRQHandler /* Port A interrupt*/
.long PORTB_IRQHandler /* Port B interrupt*/
.long PORTC_IRQHandler /* Port C interrupt*/
.long PORTD_IRQHandler /* Port D interrupt*/
.long PORTE_IRQHandler /* Port E interrupt*/
.long SWI_IRQHandler /* Software interrupt*/
.long SPI2_IRQHandler /* SPI2 Interrupt*/
.long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/
.long UART4_ERR_IRQHandler /* UART4 Error interrupt*/
.long Reserved84_IRQHandler /* Reserved interrupt 84*/
.long Reserved85_IRQHandler /* Reserved interrupt 85*/
.long CMP2_IRQHandler /* CMP2 interrupt*/
.long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
.long DAC1_IRQHandler /* DAC1 interrupt*/
.long ADC1_IRQHandler /* ADC1 interrupt*/
.long I2C2_IRQHandler /* I2C2 interrupt*/
.long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
.long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/
.long CAN0_Error_IRQHandler /* CAN0 error interrupt*/
.long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/
.long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/
.long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/
.long SDHC_IRQHandler /* SDHC interrupt*/
.long Reserved98_IRQHandler /* Reserved Interrupt 98*/
.long Reserved99_IRQHandler /* Reserved Interrupt 99*/
.long Reserved100_IRQHandler /* Reserved Interrupt 100*/
.long Reserved101_IRQHandler /* Reserved Interrupt 101*/
.long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/
.long TSI0_IRQHandler /* TSI0 interrupt*/
.long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt*/
.long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt*/
.long USBHSDCD_IRQHandler /* USBHSDCD, USBHS Phy Interrupt*/
.long I2C3_IRQHandler /* I2C3 interrupt*/
.long CMP3_IRQHandler /* CMP3 interrupt*/
.long USBHS_IRQHandler /* USB high speed OTG interrupt*/
.long CAN1_ORed_Message_buffer_IRQHandler /* CAN1 OR'd message buffers interrupt*/
.long CAN1_Bus_Off_IRQHandler /* CAN1 bus off interrupt*/
.long CAN1_Error_IRQHandler /* CAN1 error interrupt*/
.long CAN1_Tx_Warning_IRQHandler /* CAN1 Tx warning interrupt*/
.long CAN1_Rx_Warning_IRQHandler /* CAN1 Rx warning interrupt*/
.long CAN1_Wake_Up_IRQHandler /* CAN1 wake up interrupt*/
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFF
.long 0xFFFFFFFE
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* __noncachedata_start__/__noncachedata_end__ : none cachable region
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
ldr r2, =__noncachedata_start__
ldr r3, =__noncachedata_init_end__
#if 1
.LC2:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC2
#else
subs r3, r2
ble .LC3
.LC2:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC2
.LC3:
#endif
/* zero inited ncache section initialization */
ldr r3, =__noncachedata_end__
movs r0,0
.LC4:
cmp r2,r3
itt lt
strlt r0,[r2],#4
blt .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC5:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC5
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler DMA0_DMA16_IRQHandler
def_irq_handler DMA1_DMA17_IRQHandler
def_irq_handler DMA2_DMA18_IRQHandler
def_irq_handler DMA3_DMA19_IRQHandler
def_irq_handler DMA4_DMA20_IRQHandler
def_irq_handler DMA5_DMA21_IRQHandler
def_irq_handler DMA6_DMA22_IRQHandler
def_irq_handler DMA7_DMA23_IRQHandler
def_irq_handler DMA8_DMA24_IRQHandler
def_irq_handler DMA9_DMA25_IRQHandler
def_irq_handler DMA10_DMA26_IRQHandler
def_irq_handler DMA11_DMA27_IRQHandler
def_irq_handler DMA12_DMA28_IRQHandler
def_irq_handler DMA13_DMA29_IRQHandler
def_irq_handler DMA14_DMA30_IRQHandler
def_irq_handler DMA15_DMA31_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler MCM_IRQHandler
def_irq_handler FTFE_IRQHandler
def_irq_handler Read_Collision_IRQHandler
def_irq_handler LVD_LVW_IRQHandler
def_irq_handler LLWU_IRQHandler
def_irq_handler WDOG_EWM_IRQHandler
def_irq_handler RNG_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler I2S0_Tx_IRQHandler
def_irq_handler I2S0_Rx_IRQHandler
def_irq_handler Reserved46_IRQHandler
def_irq_handler UART0_RX_TX_IRQHandler
def_irq_handler UART0_ERR_IRQHandler
def_irq_handler UART1_RX_TX_IRQHandler
def_irq_handler UART1_ERR_IRQHandler
def_irq_handler UART2_RX_TX_IRQHandler
def_irq_handler UART2_ERR_IRQHandler
def_irq_handler UART3_RX_TX_IRQHandler
def_irq_handler UART3_ERR_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler CMP1_IRQHandler
def_irq_handler FTM0_IRQHandler
def_irq_handler FTM1_IRQHandler
def_irq_handler FTM2_IRQHandler
def_irq_handler CMT_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler PIT0_IRQHandler
def_irq_handler PIT1_IRQHandler
def_irq_handler PIT2_IRQHandler
def_irq_handler PIT3_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler USB0_IRQHandler
def_irq_handler USBDCD_IRQHandler
def_irq_handler Reserved71_IRQHandler
def_irq_handler DAC0_IRQHandler
def_irq_handler MCG_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORTA_IRQHandler
def_irq_handler PORTB_IRQHandler
def_irq_handler PORTC_IRQHandler
def_irq_handler PORTD_IRQHandler
def_irq_handler PORTE_IRQHandler
def_irq_handler SWI_IRQHandler
def_irq_handler SPI2_IRQHandler
def_irq_handler UART4_RX_TX_IRQHandler
def_irq_handler UART4_ERR_IRQHandler
def_irq_handler Reserved84_IRQHandler
def_irq_handler Reserved85_IRQHandler
def_irq_handler CMP2_IRQHandler
def_irq_handler FTM3_IRQHandler
def_irq_handler DAC1_IRQHandler
def_irq_handler ADC1_IRQHandler
def_irq_handler I2C2_IRQHandler
def_irq_handler CAN0_ORed_Message_buffer_IRQHandler
def_irq_handler CAN0_Bus_Off_IRQHandler
def_irq_handler CAN0_Error_IRQHandler
def_irq_handler CAN0_Tx_Warning_IRQHandler
def_irq_handler CAN0_Rx_Warning_IRQHandler
def_irq_handler CAN0_Wake_Up_IRQHandler
def_irq_handler SDHC_IRQHandler
def_irq_handler Reserved98_IRQHandler
def_irq_handler Reserved99_IRQHandler
def_irq_handler Reserved100_IRQHandler
def_irq_handler Reserved101_IRQHandler
def_irq_handler LPUART0_IRQHandler
def_irq_handler TSI0_IRQHandler
def_irq_handler TPM1_IRQHandler
def_irq_handler TPM2_IRQHandler
def_irq_handler USBHSDCD_IRQHandler
def_irq_handler I2C3_IRQHandler
def_irq_handler CMP3_IRQHandler
def_irq_handler USBHS_IRQHandler
def_irq_handler CAN1_ORed_Message_buffer_IRQHandler
def_irq_handler CAN1_Bus_Off_IRQHandler
def_irq_handler CAN1_Error_IRQHandler
def_irq_handler CAN1_Tx_Warning_IRQHandler
def_irq_handler CAN1_Rx_Warning_IRQHandler
def_irq_handler CAN1_Wake_Up_IRQHandler
.end
|
wuxx/nanoDAP | 47,977 | software/DAPLink/source/hic_hal/freescale/k26f/armcc/startup_MK26F18.s | ; * ---------------------------------------------------------------------------------------
; * @file: startup_MK26F18.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * MK26F18
; * @version: 2.0
; * @date: 2015-3-25
; * @build: b151210
; * ---------------------------------------------------------------------------------------
; *
; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc.
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; *
; * o Redistributions of source code must retain the above copyright notice, this list
; * of conditions and the following disclaimer.
; *
; * o Redistributions in binary form must reproduce the above copyright notice, this
; * list of conditions and the following disclaimer in the documentation and/or
; * other materials provided with the distribution.
; *
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
; * contributors may be used to endorse or promote products derived from this
; * software without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000100
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD MemManage_Handler ;MPU Fault Handler
DCD BusFault_Handler ;Bus Fault Handler
DCD UsageFault_Handler ;Usage Fault Handler
DCD 0 ;Reserved
DCD DAPLINK_BUILD_KEY ;DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ;DAPLINK: Compatibility
DCD DAPLINK_VERSION ;DAPLINK: Version
DCD SVC_Handler ;SVCall Handler
DCD DebugMon_Handler ;Debug Monitor Handler
DCD g_board_info ;DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD DMA0_DMA16_IRQHandler ;DMA Channel 0, 16 Transfer Complete
DCD DMA1_DMA17_IRQHandler ;DMA Channel 1, 17 Transfer Complete
DCD DMA2_DMA18_IRQHandler ;DMA Channel 2, 18 Transfer Complete
DCD DMA3_DMA19_IRQHandler ;DMA Channel 3, 19 Transfer Complete
DCD DMA4_DMA20_IRQHandler ;DMA Channel 4, 20 Transfer Complete
DCD DMA5_DMA21_IRQHandler ;DMA Channel 5, 21 Transfer Complete
DCD DMA6_DMA22_IRQHandler ;DMA Channel 6, 22 Transfer Complete
DCD DMA7_DMA23_IRQHandler ;DMA Channel 7, 23 Transfer Complete
DCD DMA8_DMA24_IRQHandler ;DMA Channel 8, 24 Transfer Complete
DCD DMA9_DMA25_IRQHandler ;DMA Channel 9, 25 Transfer Complete
DCD DMA10_DMA26_IRQHandler ;DMA Channel 10, 26 Transfer Complete
DCD DMA11_DMA27_IRQHandler ;DMA Channel 11, 27 Transfer Complete
DCD DMA12_DMA28_IRQHandler ;DMA Channel 12, 28 Transfer Complete
DCD DMA13_DMA29_IRQHandler ;DMA Channel 13, 29 Transfer Complete
DCD DMA14_DMA30_IRQHandler ;DMA Channel 14, 30 Transfer Complete
DCD DMA15_DMA31_IRQHandler ;DMA Channel 15, 31 Transfer Complete
DCD DMA_Error_IRQHandler ;DMA Error Interrupt
DCD MCM_IRQHandler ;Normal Interrupt
DCD FTFE_IRQHandler ;FTFE Command complete interrupt
DCD Read_Collision_IRQHandler ;Read Collision Interrupt
DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning
DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit
DCD WDOG_EWM_IRQHandler ;WDOG Interrupt
DCD RNG_IRQHandler ;RNG Interrupt
DCD I2C0_IRQHandler ;I2C0 interrupt
DCD I2C1_IRQHandler ;I2C1 interrupt
DCD SPI0_IRQHandler ;SPI0 Interrupt
DCD SPI1_IRQHandler ;SPI1 Interrupt
DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt
DCD Reserved46_IRQHandler ;Reserved interrupt 46
DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt
DCD UART0_ERR_IRQHandler ;UART0 Error interrupt
DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt
DCD UART1_ERR_IRQHandler ;UART1 Error interrupt
DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt
DCD UART2_ERR_IRQHandler ;UART2 Error interrupt
DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt
DCD UART3_ERR_IRQHandler ;UART3 Error interrupt
DCD ADC0_IRQHandler ;ADC0 interrupt
DCD CMP0_IRQHandler ;CMP0 interrupt
DCD CMP1_IRQHandler ;CMP1 interrupt
DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ;CMT interrupt
DCD RTC_IRQHandler ;RTC interrupt
DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt
DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ;PDB0 Interrupt
DCD USB0_IRQHandler ;USB0 interrupt
DCD USBDCD_IRQHandler ;USBDCD Interrupt
DCD Reserved71_IRQHandler ;Reserved interrupt 71
DCD DAC0_IRQHandler ;DAC0 interrupt
DCD MCG_IRQHandler ;MCG Interrupt
DCD LPTMR0_IRQHandler ;LPTimer interrupt
DCD PORTA_IRQHandler ;Port A interrupt
DCD PORTB_IRQHandler ;Port B interrupt
DCD PORTC_IRQHandler ;Port C interrupt
DCD PORTD_IRQHandler ;Port D interrupt
DCD PORTE_IRQHandler ;Port E interrupt
DCD SWI_IRQHandler ;Software interrupt
DCD SPI2_IRQHandler ;SPI2 Interrupt
DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt
DCD UART4_ERR_IRQHandler ;UART4 Error interrupt
DCD Reserved84_IRQHandler ;Reserved interrupt 84
DCD Reserved85_IRQHandler ;Reserved interrupt 85
DCD CMP2_IRQHandler ;CMP2 interrupt
DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt
DCD DAC1_IRQHandler ;DAC1 interrupt
DCD ADC1_IRQHandler ;ADC1 interrupt
DCD I2C2_IRQHandler ;I2C2 interrupt
DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt
DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt
DCD CAN0_Error_IRQHandler ;CAN0 error interrupt
DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt
DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt
DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt
DCD SDHC_IRQHandler ;SDHC interrupt
DCD Reserved98_IRQHandler ;Reserved Interrupt 98
DCD Reserved99_IRQHandler ;Reserved Interrupt 99
DCD Reserved100_IRQHandler ;Reserved Interrupt 100
DCD Reserved101_IRQHandler ;Reserved Interrupt 101
DCD LPUART0_IRQHandler ;LPUART0 status/error interrupt
DCD TSI0_IRQHandler ;TSI0 interrupt
DCD TPM1_IRQHandler ;TPM1 fault, overflow and channels interrupt
DCD TPM2_IRQHandler ;TPM2 fault, overflow and channels interrupt
DCD USBHSDCD_IRQHandler ;USBHSDCD, USBHS Phy Interrupt
DCD I2C3_IRQHandler ;I2C3 interrupt
DCD CMP3_IRQHandler ;CMP3 interrupt
DCD USBHS_IRQHandler ;USB high speed OTG interrupt
DCD CAN1_ORed_Message_buffer_IRQHandler ;CAN1 OR'd message buffers interrupt
DCD CAN1_Bus_Off_IRQHandler ;CAN1 bus off interrupt
DCD CAN1_Error_IRQHandler ;CAN1 error interrupt
DCD CAN1_Tx_Warning_IRQHandler ;CAN1 Tx warning interrupt
DCD CAN1_Rx_Warning_IRQHandler ;CAN1 Rx warning interrupt
DCD CAN1_Wake_Up_IRQHandler ;CAN1 wake up interrupt
DCD DefaultISR ;116
DCD DefaultISR ;117
DCD DefaultISR ;118
DCD DefaultISR ;119
DCD DefaultISR ;120
DCD DefaultISR ;121
DCD DefaultISR ;122
DCD DefaultISR ;123
DCD DefaultISR ;124
DCD DefaultISR ;125
DCD DefaultISR ;126
DCD DefaultISR ;127
DCD DefaultISR ;128
DCD DefaultISR ;129
DCD DefaultISR ;130
DCD DefaultISR ;131
DCD DefaultISR ;132
DCD DefaultISR ;133
DCD DefaultISR ;134
DCD DefaultISR ;135
DCD DefaultISR ;136
DCD DefaultISR ;137
DCD DefaultISR ;138
DCD DefaultISR ;139
DCD DefaultISR ;140
DCD DefaultISR ;141
DCD DefaultISR ;142
DCD DefaultISR ;143
DCD DefaultISR ;144
DCD DefaultISR ;145
DCD DefaultISR ;146
DCD DefaultISR ;147
DCD DefaultISR ;148
DCD DefaultISR ;149
DCD DefaultISR ;150
DCD DefaultISR ;151
DCD DefaultISR ;152
DCD DefaultISR ;153
DCD DefaultISR ;154
DCD DefaultISR ;155
DCD DefaultISR ;156
DCD DefaultISR ;157
DCD DefaultISR ;158
DCD DefaultISR ;159
DCD DefaultISR ;160
DCD DefaultISR ;161
DCD DefaultISR ;162
DCD DefaultISR ;163
DCD DefaultISR ;164
DCD DefaultISR ;165
DCD DefaultISR ;166
DCD DefaultISR ;167
DCD DefaultISR ;168
DCD DefaultISR ;169
DCD DefaultISR ;170
DCD DefaultISR ;171
DCD DefaultISR ;172
DCD DefaultISR ;173
DCD DefaultISR ;174
DCD DefaultISR ;175
DCD DefaultISR ;176
DCD DefaultISR ;177
DCD DefaultISR ;178
DCD DefaultISR ;179
DCD DefaultISR ;180
DCD DefaultISR ;181
DCD DefaultISR ;182
DCD DefaultISR ;183
DCD DefaultISR ;184
DCD DefaultISR ;185
DCD DefaultISR ;186
DCD DefaultISR ;187
DCD DefaultISR ;188
DCD DefaultISR ;189
DCD DefaultISR ;190
DCD DefaultISR ;191
DCD DefaultISR ;192
DCD DefaultISR ;193
DCD DefaultISR ;194
DCD DefaultISR ;195
DCD DefaultISR ;196
DCD DefaultISR ;197
DCD DefaultISR ;198
DCD DefaultISR ;199
DCD DefaultISR ;200
DCD DefaultISR ;201
DCD DefaultISR ;202
DCD DefaultISR ;203
DCD DefaultISR ;204
DCD DefaultISR ;205
DCD DefaultISR ;206
DCD DefaultISR ;207
DCD DefaultISR ;208
DCD DefaultISR ;209
DCD DefaultISR ;210
DCD DefaultISR ;211
DCD DefaultISR ;212
DCD DefaultISR ;213
DCD DefaultISR ;214
DCD DefaultISR ;215
DCD DefaultISR ;216
DCD DefaultISR ;217
DCD DefaultISR ;218
DCD DefaultISR ;219
DCD DefaultISR ;220
DCD DefaultISR ;221
DCD DefaultISR ;222
DCD DefaultISR ;223
DCD DefaultISR ;224
DCD DefaultISR ;225
DCD DefaultISR ;226
DCD DefaultISR ;227
DCD DefaultISR ;228
DCD DefaultISR ;229
DCD DefaultISR ;230
DCD DefaultISR ;231
DCD DefaultISR ;232
DCD DefaultISR ;233
DCD DefaultISR ;234
DCD DefaultISR ;235
DCD DefaultISR ;236
DCD DefaultISR ;237
DCD DefaultISR ;238
DCD DefaultISR ;239
DCD DefaultISR ;240
DCD DefaultISR ;241
DCD DefaultISR ;242
DCD DefaultISR ;243
DCD DefaultISR ;244
DCD DefaultISR ;245
DCD DefaultISR ;246
DCD DefaultISR ;247
DCD DefaultISR ;248
DCD DefaultISR ;249
DCD DefaultISR ;250
DCD DefaultISR ;251
DCD DefaultISR ;252
DCD DefaultISR ;253
DCD DefaultISR ;254
DCD 0xFFFFFFFF ; Reserved for user TRIM value
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict access to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program Flash Region Protect Register 0
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> Normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is disabled
; <1=> EzPort operation is enabled
; <o.2> NMI_DIS
; <0=> NMI interrupts are always blocked
; <1=> NMI_b pin/interrupts reset default to enabled
FOPT EQU 0xF9
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor Key Security Enable
FSEC EQU 0xFE
; </h>
; </h>
#if defined(DAPLINK_IF)
AREA |.ARM.__at_0x20400|, CODE, READONLY
#else
AREA |.ARM.__at_0x400 |, CODE, READONLY
#endif
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
DCB FSEC , FOPT , FEPROT , FDPROT
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
CPSID I ; Mask interrupts
LDR R0, =0xE000ED08
LDR R1, =__Vectors
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
CPSIE i ; Unmask interrupts
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
DMA0_DMA16_IRQHandler\
PROC
EXPORT DMA0_DMA16_IRQHandler [WEAK]
LDR R0, =DMA0_DMA16_DriverIRQHandler
BX R0
ENDP
DMA1_DMA17_IRQHandler\
PROC
EXPORT DMA1_DMA17_IRQHandler [WEAK]
LDR R0, =DMA1_DMA17_DriverIRQHandler
BX R0
ENDP
DMA2_DMA18_IRQHandler\
PROC
EXPORT DMA2_DMA18_IRQHandler [WEAK]
LDR R0, =DMA2_DMA18_DriverIRQHandler
BX R0
ENDP
DMA3_DMA19_IRQHandler\
PROC
EXPORT DMA3_DMA19_IRQHandler [WEAK]
LDR R0, =DMA3_DMA19_DriverIRQHandler
BX R0
ENDP
DMA4_DMA20_IRQHandler\
PROC
EXPORT DMA4_DMA20_IRQHandler [WEAK]
LDR R0, =DMA4_DMA20_DriverIRQHandler
BX R0
ENDP
DMA5_DMA21_IRQHandler\
PROC
EXPORT DMA5_DMA21_IRQHandler [WEAK]
LDR R0, =DMA5_DMA21_DriverIRQHandler
BX R0
ENDP
DMA6_DMA22_IRQHandler\
PROC
EXPORT DMA6_DMA22_IRQHandler [WEAK]
LDR R0, =DMA6_DMA22_DriverIRQHandler
BX R0
ENDP
DMA7_DMA23_IRQHandler\
PROC
EXPORT DMA7_DMA23_IRQHandler [WEAK]
LDR R0, =DMA7_DMA23_DriverIRQHandler
BX R0
ENDP
DMA8_DMA24_IRQHandler\
PROC
EXPORT DMA8_DMA24_IRQHandler [WEAK]
LDR R0, =DMA8_DMA24_DriverIRQHandler
BX R0
ENDP
DMA9_DMA25_IRQHandler\
PROC
EXPORT DMA9_DMA25_IRQHandler [WEAK]
LDR R0, =DMA9_DMA25_DriverIRQHandler
BX R0
ENDP
DMA10_DMA26_IRQHandler\
PROC
EXPORT DMA10_DMA26_IRQHandler [WEAK]
LDR R0, =DMA10_DMA26_DriverIRQHandler
BX R0
ENDP
DMA11_DMA27_IRQHandler\
PROC
EXPORT DMA11_DMA27_IRQHandler [WEAK]
LDR R0, =DMA11_DMA27_DriverIRQHandler
BX R0
ENDP
DMA12_DMA28_IRQHandler\
PROC
EXPORT DMA12_DMA28_IRQHandler [WEAK]
LDR R0, =DMA12_DMA28_DriverIRQHandler
BX R0
ENDP
DMA13_DMA29_IRQHandler\
PROC
EXPORT DMA13_DMA29_IRQHandler [WEAK]
LDR R0, =DMA13_DMA29_DriverIRQHandler
BX R0
ENDP
DMA14_DMA30_IRQHandler\
PROC
EXPORT DMA14_DMA30_IRQHandler [WEAK]
LDR R0, =DMA14_DMA30_DriverIRQHandler
BX R0
ENDP
DMA15_DMA31_IRQHandler\
PROC
EXPORT DMA15_DMA31_IRQHandler [WEAK]
LDR R0, =DMA15_DMA31_DriverIRQHandler
BX R0
ENDP
DMA_Error_IRQHandler\
PROC
EXPORT DMA_Error_IRQHandler [WEAK]
LDR R0, =DMA_Error_DriverIRQHandler
BX R0
ENDP
I2C0_IRQHandler\
PROC
EXPORT I2C0_IRQHandler [WEAK]
LDR R0, =I2C0_DriverIRQHandler
BX R0
ENDP
I2C1_IRQHandler\
PROC
EXPORT I2C1_IRQHandler [WEAK]
LDR R0, =I2C1_DriverIRQHandler
BX R0
ENDP
SPI0_IRQHandler\
PROC
EXPORT SPI0_IRQHandler [WEAK]
LDR R0, =SPI0_DriverIRQHandler
BX R0
ENDP
SPI1_IRQHandler\
PROC
EXPORT SPI1_IRQHandler [WEAK]
LDR R0, =SPI1_DriverIRQHandler
BX R0
ENDP
I2S0_Tx_IRQHandler\
PROC
EXPORT I2S0_Tx_IRQHandler [WEAK]
LDR R0, =I2S0_Tx_DriverIRQHandler
BX R0
ENDP
I2S0_Rx_IRQHandler\
PROC
EXPORT I2S0_Rx_IRQHandler [WEAK]
LDR R0, =I2S0_Rx_DriverIRQHandler
BX R0
ENDP
UART0_RX_TX_IRQHandler\
PROC
EXPORT UART0_RX_TX_IRQHandler [WEAK]
LDR R0, =UART0_RX_TX_DriverIRQHandler
BX R0
ENDP
UART0_ERR_IRQHandler\
PROC
EXPORT UART0_ERR_IRQHandler [WEAK]
LDR R0, =UART0_ERR_DriverIRQHandler
BX R0
ENDP
UART1_RX_TX_IRQHandler\
PROC
EXPORT UART1_RX_TX_IRQHandler [WEAK]
LDR R0, =UART1_RX_TX_DriverIRQHandler
BX R0
ENDP
UART1_ERR_IRQHandler\
PROC
EXPORT UART1_ERR_IRQHandler [WEAK]
LDR R0, =UART1_ERR_DriverIRQHandler
BX R0
ENDP
UART2_RX_TX_IRQHandler\
PROC
EXPORT UART2_RX_TX_IRQHandler [WEAK]
LDR R0, =UART2_RX_TX_DriverIRQHandler
BX R0
ENDP
UART2_ERR_IRQHandler\
PROC
EXPORT UART2_ERR_IRQHandler [WEAK]
LDR R0, =UART2_ERR_DriverIRQHandler
BX R0
ENDP
UART3_RX_TX_IRQHandler\
PROC
EXPORT UART3_RX_TX_IRQHandler [WEAK]
LDR R0, =UART3_RX_TX_DriverIRQHandler
BX R0
ENDP
UART3_ERR_IRQHandler\
PROC
EXPORT UART3_ERR_IRQHandler [WEAK]
LDR R0, =UART3_ERR_DriverIRQHandler
BX R0
ENDP
SPI2_IRQHandler\
PROC
EXPORT SPI2_IRQHandler [WEAK]
LDR R0, =SPI2_DriverIRQHandler
BX R0
ENDP
UART4_RX_TX_IRQHandler\
PROC
EXPORT UART4_RX_TX_IRQHandler [WEAK]
LDR R0, =UART4_RX_TX_DriverIRQHandler
BX R0
ENDP
UART4_ERR_IRQHandler\
PROC
EXPORT UART4_ERR_IRQHandler [WEAK]
LDR R0, =UART4_ERR_DriverIRQHandler
BX R0
ENDP
I2C2_IRQHandler\
PROC
EXPORT I2C2_IRQHandler [WEAK]
LDR R0, =I2C2_DriverIRQHandler
BX R0
ENDP
CAN0_ORed_Message_buffer_IRQHandler\
PROC
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Bus_Off_IRQHandler\
PROC
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Error_IRQHandler\
PROC
EXPORT CAN0_Error_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Tx_Warning_IRQHandler\
PROC
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Rx_Warning_IRQHandler\
PROC
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
CAN0_Wake_Up_IRQHandler\
PROC
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
LDR R0, =CAN0_DriverIRQHandler
BX R0
ENDP
SDHC_IRQHandler\
PROC
EXPORT SDHC_IRQHandler [WEAK]
LDR R0, =SDHC_DriverIRQHandler
BX R0
ENDP
LPUART0_IRQHandler\
PROC
EXPORT LPUART0_IRQHandler [WEAK]
LDR R0, =LPUART0_DriverIRQHandler
BX R0
ENDP
I2C3_IRQHandler\
PROC
EXPORT I2C3_IRQHandler [WEAK]
LDR R0, =I2C3_DriverIRQHandler
BX R0
ENDP
CAN1_ORed_Message_buffer_IRQHandler\
PROC
EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Bus_Off_IRQHandler\
PROC
EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Error_IRQHandler\
PROC
EXPORT CAN1_Error_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Tx_Warning_IRQHandler\
PROC
EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Rx_Warning_IRQHandler\
PROC
EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
CAN1_Wake_Up_IRQHandler\
PROC
EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
LDR R0, =CAN1_DriverIRQHandler
BX R0
ENDP
Default_Handler\
PROC
EXPORT DMA0_DMA16_DriverIRQHandler [WEAK]
EXPORT DMA1_DMA17_DriverIRQHandler [WEAK]
EXPORT DMA2_DMA18_DriverIRQHandler [WEAK]
EXPORT DMA3_DMA19_DriverIRQHandler [WEAK]
EXPORT DMA4_DMA20_DriverIRQHandler [WEAK]
EXPORT DMA5_DMA21_DriverIRQHandler [WEAK]
EXPORT DMA6_DMA22_DriverIRQHandler [WEAK]
EXPORT DMA7_DMA23_DriverIRQHandler [WEAK]
EXPORT DMA8_DMA24_DriverIRQHandler [WEAK]
EXPORT DMA9_DMA25_DriverIRQHandler [WEAK]
EXPORT DMA10_DMA26_DriverIRQHandler [WEAK]
EXPORT DMA11_DMA27_DriverIRQHandler [WEAK]
EXPORT DMA12_DMA28_DriverIRQHandler [WEAK]
EXPORT DMA13_DMA29_DriverIRQHandler [WEAK]
EXPORT DMA14_DMA30_DriverIRQHandler [WEAK]
EXPORT DMA15_DMA31_DriverIRQHandler [WEAK]
EXPORT DMA_Error_DriverIRQHandler [WEAK]
EXPORT MCM_IRQHandler [WEAK]
EXPORT FTFE_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLWU_IRQHandler [WEAK]
EXPORT WDOG_EWM_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT I2C0_DriverIRQHandler [WEAK]
EXPORT I2C1_DriverIRQHandler [WEAK]
EXPORT SPI0_DriverIRQHandler [WEAK]
EXPORT SPI1_DriverIRQHandler [WEAK]
EXPORT I2S0_Tx_DriverIRQHandler [WEAK]
EXPORT I2S0_Rx_DriverIRQHandler [WEAK]
EXPORT Reserved46_IRQHandler [WEAK]
EXPORT UART0_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART0_ERR_DriverIRQHandler [WEAK]
EXPORT UART1_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART1_ERR_DriverIRQHandler [WEAK]
EXPORT UART2_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART2_ERR_DriverIRQHandler [WEAK]
EXPORT UART3_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART3_ERR_DriverIRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT FTM2_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT Reserved71_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTMR0_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT SPI2_DriverIRQHandler [WEAK]
EXPORT UART4_RX_TX_DriverIRQHandler [WEAK]
EXPORT UART4_ERR_DriverIRQHandler [WEAK]
EXPORT Reserved84_IRQHandler [WEAK]
EXPORT Reserved85_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT FTM3_IRQHandler [WEAK]
EXPORT DAC1_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT I2C2_DriverIRQHandler [WEAK]
EXPORT CAN0_DriverIRQHandler [WEAK]
EXPORT SDHC_DriverIRQHandler [WEAK]
EXPORT Reserved98_IRQHandler [WEAK]
EXPORT Reserved99_IRQHandler [WEAK]
EXPORT Reserved100_IRQHandler [WEAK]
EXPORT Reserved101_IRQHandler [WEAK]
EXPORT LPUART0_DriverIRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT TPM1_IRQHandler [WEAK]
EXPORT TPM2_IRQHandler [WEAK]
EXPORT USBHSDCD_IRQHandler [WEAK]
EXPORT I2C3_DriverIRQHandler [WEAK]
EXPORT CMP3_IRQHandler [WEAK]
EXPORT USBHS_IRQHandler [WEAK]
EXPORT CAN1_DriverIRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_DMA16_DriverIRQHandler
DMA1_DMA17_DriverIRQHandler
DMA2_DMA18_DriverIRQHandler
DMA3_DMA19_DriverIRQHandler
DMA4_DMA20_DriverIRQHandler
DMA5_DMA21_DriverIRQHandler
DMA6_DMA22_DriverIRQHandler
DMA7_DMA23_DriverIRQHandler
DMA8_DMA24_DriverIRQHandler
DMA9_DMA25_DriverIRQHandler
DMA10_DMA26_DriverIRQHandler
DMA11_DMA27_DriverIRQHandler
DMA12_DMA28_DriverIRQHandler
DMA13_DMA29_DriverIRQHandler
DMA14_DMA30_DriverIRQHandler
DMA15_DMA31_DriverIRQHandler
DMA_Error_DriverIRQHandler
MCM_IRQHandler
FTFE_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLWU_IRQHandler
WDOG_EWM_IRQHandler
RNG_IRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
SPI0_DriverIRQHandler
SPI1_DriverIRQHandler
I2S0_Tx_DriverIRQHandler
I2S0_Rx_DriverIRQHandler
Reserved46_IRQHandler
UART0_RX_TX_DriverIRQHandler
UART0_ERR_DriverIRQHandler
UART1_RX_TX_DriverIRQHandler
UART1_ERR_DriverIRQHandler
UART2_RX_TX_DriverIRQHandler
UART2_ERR_DriverIRQHandler
UART3_RX_TX_DriverIRQHandler
UART3_ERR_DriverIRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved71_IRQHandler
DAC0_IRQHandler
MCG_IRQHandler
LPTMR0_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
SWI_IRQHandler
SPI2_DriverIRQHandler
UART4_RX_TX_DriverIRQHandler
UART4_ERR_DriverIRQHandler
Reserved84_IRQHandler
Reserved85_IRQHandler
CMP2_IRQHandler
FTM3_IRQHandler
DAC1_IRQHandler
ADC1_IRQHandler
I2C2_DriverIRQHandler
CAN0_DriverIRQHandler
SDHC_DriverIRQHandler
Reserved98_IRQHandler
Reserved99_IRQHandler
Reserved100_IRQHandler
Reserved101_IRQHandler
LPUART0_DriverIRQHandler
TSI0_IRQHandler
TPM1_IRQHandler
TPM2_IRQHandler
USBHSDCD_IRQHandler
I2C3_DriverIRQHandler
CMP3_IRQHandler
USBHS_IRQHandler
CAN1_DriverIRQHandler
DefaultISR
B DefaultISR
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 32,299 | software/DAPLink/source/hic_hal/nxp/lpc55xx/gcc/startup_LPC55S69_cm33_core0.S | /* ---------------------------------------------------------------------------------------
* @file: startup_LPC55S69_cm33_core0.s
* @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0
* @version: 1.1
* @date: 2019-5-16
* ---------------------------------------------------------------------------------------*/
/*
* Copyright 1997-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv8-m.main
.eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long SecureFault_Handler /* Secure Fault Handler*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
.long DMA0_IRQHandler /* DMA0 controller */
.long GINT0_IRQHandler /* GPIO group 0 */
.long GINT1_IRQHandler /* GPIO group 1 */
.long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
.long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
.long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
.long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
.long UTICK0_IRQHandler /* Micro-tick Timer */
.long MRT0_IRQHandler /* Multi-rate timer */
.long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */
.long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */
.long SCT0_IRQHandler /* SCTimer/PWM */
.long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */
.long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
.long ADC0_IRQHandler /* ADC0 */
.long Reserved39_IRQHandler /* Reserved interrupt */
.long ACMP_IRQHandler /* ACMP interrupts */
.long Reserved41_IRQHandler /* Reserved interrupt */
.long Reserved42_IRQHandler /* Reserved interrupt */
.long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */
.long USB0_IRQHandler /* USB device */
.long RTC_IRQHandler /* RTC alarm and wake-up interrupts */
.long Reserved46_IRQHandler /* Reserved interrupt */
.long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
.long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
.long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
.long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
.long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
.long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */
.long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */
.long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
.long Reserved55_IRQHandler /* Reserved interrupt */
.long Reserved56_IRQHandler /* Reserved interrupt */
.long Reserved57_IRQHandler /* Reserved interrupt */
.long SDIO_IRQHandler /* SD/MMC */
.long Reserved59_IRQHandler /* Reserved interrupt */
.long Reserved60_IRQHandler /* Reserved interrupt */
.long Reserved61_IRQHandler /* Reserved interrupt */
.long USB1_PHY_IRQHandler /* USB1_PHY */
.long USB1_IRQHandler /* USB1 interrupt */
.long USB1_NEEDCLK_IRQHandler /* USB1 activity */
.long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */
.long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
.long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
.long PLU_IRQHandler /* PLU interrupt */
.long SEC_VIO_IRQHandler /* SEC_VIO interrupt */
.long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */
.long CASER_IRQHandler /* CASPER interrupt */
.long PUF_IRQHandler /* PUF interrupt */
.long PQ_IRQHandler /* PQ interrupt */
.long DMA1_IRQHandler /* DMA1 interrupt */
.long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =__StackLimit
msr msplim, r0
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
/* Add stack / heap initializaiton */
movs r0, 0
ldr r1, =__HeapBase
ldr r2, =__HeapLimit
.LC3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC3
ldr r1, =__StackLimit
ldr r2, =__StackTop
.LC4:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC4
/*End of stack / heap initializaiton */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
// Alternate init code from DFP:
// cpsid i /* mask interrupts */
// ldr r0, =__StackLimit
// msr msplim, r0
// ldr r0,=SystemInit
// blx r0
// cpsie i /* Unmask interrupts */
// ldr r0,=__main
// bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
.align 1
.thumb_func
.weak WDT_BOD_IRQHandler
.type WDT_BOD_IRQHandler, %function
WDT_BOD_IRQHandler:
ldr r0,=WDT_BOD_DriverIRQHandler
bx r0
.size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
.align 1
.thumb_func
.weak DMA0_IRQHandler
.type DMA0_IRQHandler, %function
DMA0_IRQHandler:
ldr r0,=DMA0_DriverIRQHandler
bx r0
.size DMA0_IRQHandler, . - DMA0_IRQHandler
.align 1
.thumb_func
.weak GINT0_IRQHandler
.type GINT0_IRQHandler, %function
GINT0_IRQHandler:
ldr r0,=GINT0_DriverIRQHandler
bx r0
.size GINT0_IRQHandler, . - GINT0_IRQHandler
.align 1
.thumb_func
.weak GINT1_IRQHandler
.type GINT1_IRQHandler, %function
GINT1_IRQHandler:
ldr r0,=GINT1_DriverIRQHandler
bx r0
.size GINT1_IRQHandler, . - GINT1_IRQHandler
.align 1
.thumb_func
.weak PIN_INT0_IRQHandler
.type PIN_INT0_IRQHandler, %function
PIN_INT0_IRQHandler:
ldr r0,=PIN_INT0_DriverIRQHandler
bx r0
.size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
.align 1
.thumb_func
.weak PIN_INT1_IRQHandler
.type PIN_INT1_IRQHandler, %function
PIN_INT1_IRQHandler:
ldr r0,=PIN_INT1_DriverIRQHandler
bx r0
.size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
.align 1
.thumb_func
.weak PIN_INT2_IRQHandler
.type PIN_INT2_IRQHandler, %function
PIN_INT2_IRQHandler:
ldr r0,=PIN_INT2_DriverIRQHandler
bx r0
.size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
.align 1
.thumb_func
.weak PIN_INT3_IRQHandler
.type PIN_INT3_IRQHandler, %function
PIN_INT3_IRQHandler:
ldr r0,=PIN_INT3_DriverIRQHandler
bx r0
.size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
.align 1
.thumb_func
.weak UTICK0_IRQHandler
.type UTICK0_IRQHandler, %function
UTICK0_IRQHandler:
ldr r0,=UTICK0_DriverIRQHandler
bx r0
.size UTICK0_IRQHandler, . - UTICK0_IRQHandler
.align 1
.thumb_func
.weak MRT0_IRQHandler
.type MRT0_IRQHandler, %function
MRT0_IRQHandler:
ldr r0,=MRT0_DriverIRQHandler
bx r0
.size MRT0_IRQHandler, . - MRT0_IRQHandler
.align 1
.thumb_func
.weak CTIMER0_IRQHandler
.type CTIMER0_IRQHandler, %function
CTIMER0_IRQHandler:
ldr r0,=CTIMER0_DriverIRQHandler
bx r0
.size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
.align 1
.thumb_func
.weak CTIMER1_IRQHandler
.type CTIMER1_IRQHandler, %function
CTIMER1_IRQHandler:
ldr r0,=CTIMER1_DriverIRQHandler
bx r0
.size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
.align 1
.thumb_func
.weak SCT0_IRQHandler
.type SCT0_IRQHandler, %function
SCT0_IRQHandler:
ldr r0,=SCT0_DriverIRQHandler
bx r0
.size SCT0_IRQHandler, . - SCT0_IRQHandler
.align 1
.thumb_func
.weak CTIMER3_IRQHandler
.type CTIMER3_IRQHandler, %function
CTIMER3_IRQHandler:
ldr r0,=CTIMER3_DriverIRQHandler
bx r0
.size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM0_IRQHandler
.type FLEXCOMM0_IRQHandler, %function
FLEXCOMM0_IRQHandler:
ldr r0,=FLEXCOMM0_DriverIRQHandler
bx r0
.size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM1_IRQHandler
.type FLEXCOMM1_IRQHandler, %function
FLEXCOMM1_IRQHandler:
ldr r0,=FLEXCOMM1_DriverIRQHandler
bx r0
.size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM2_IRQHandler
.type FLEXCOMM2_IRQHandler, %function
FLEXCOMM2_IRQHandler:
ldr r0,=FLEXCOMM2_DriverIRQHandler
bx r0
.size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM3_IRQHandler
.type FLEXCOMM3_IRQHandler, %function
FLEXCOMM3_IRQHandler:
ldr r0,=FLEXCOMM3_DriverIRQHandler
bx r0
.size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM4_IRQHandler
.type FLEXCOMM4_IRQHandler, %function
FLEXCOMM4_IRQHandler:
ldr r0,=FLEXCOMM4_DriverIRQHandler
bx r0
.size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM5_IRQHandler
.type FLEXCOMM5_IRQHandler, %function
FLEXCOMM5_IRQHandler:
ldr r0,=FLEXCOMM5_DriverIRQHandler
bx r0
.size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM6_IRQHandler
.type FLEXCOMM6_IRQHandler, %function
FLEXCOMM6_IRQHandler:
ldr r0,=FLEXCOMM6_DriverIRQHandler
bx r0
.size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM7_IRQHandler
.type FLEXCOMM7_IRQHandler, %function
FLEXCOMM7_IRQHandler:
ldr r0,=FLEXCOMM7_DriverIRQHandler
bx r0
.size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
.align 1
.thumb_func
.weak ADC0_IRQHandler
.type ADC0_IRQHandler, %function
ADC0_IRQHandler:
ldr r0,=ADC0_DriverIRQHandler
bx r0
.size ADC0_IRQHandler, . - ADC0_IRQHandler
.align 1
.thumb_func
.weak Reserved39_IRQHandler
.type Reserved39_IRQHandler, %function
Reserved39_IRQHandler:
ldr r0,=Reserved39_DriverIRQHandler
bx r0
.size Reserved39_IRQHandler, . - Reserved39_IRQHandler
.align 1
.thumb_func
.weak ACMP_IRQHandler
.type ACMP_IRQHandler, %function
ACMP_IRQHandler:
ldr r0,=ACMP_DriverIRQHandler
bx r0
.size ACMP_IRQHandler, . - ACMP_IRQHandler
.align 1
.thumb_func
.weak Reserved41_IRQHandler
.type Reserved41_IRQHandler, %function
Reserved41_IRQHandler:
ldr r0,=Reserved41_DriverIRQHandler
bx r0
.size Reserved41_IRQHandler, . - Reserved41_IRQHandler
.align 1
.thumb_func
.weak Reserved42_IRQHandler
.type Reserved42_IRQHandler, %function
Reserved42_IRQHandler:
ldr r0,=Reserved42_DriverIRQHandler
bx r0
.size Reserved42_IRQHandler, . - Reserved42_IRQHandler
.align 1
.thumb_func
.weak USB0_NEEDCLK_IRQHandler
.type USB0_NEEDCLK_IRQHandler, %function
USB0_NEEDCLK_IRQHandler:
ldr r0,=USB0_NEEDCLK_DriverIRQHandler
bx r0
.size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
.align 1
.thumb_func
.weak USB0_IRQHandler
.type USB0_IRQHandler, %function
USB0_IRQHandler:
ldr r0,=USB0_DriverIRQHandler
bx r0
.size USB0_IRQHandler, . - USB0_IRQHandler
.align 1
.thumb_func
.weak RTC_IRQHandler
.type RTC_IRQHandler, %function
RTC_IRQHandler:
ldr r0,=RTC_DriverIRQHandler
bx r0
.size RTC_IRQHandler, . - RTC_IRQHandler
.align 1
.thumb_func
.weak Reserved46_IRQHandler
.type Reserved46_IRQHandler, %function
Reserved46_IRQHandler:
ldr r0,=Reserved46_DriverIRQHandler
bx r0
.size Reserved46_IRQHandler, . - Reserved46_IRQHandler
.align 1
.thumb_func
.weak MAILBOX_IRQHandler
.type MAILBOX_IRQHandler, %function
MAILBOX_IRQHandler:
ldr r0,=MAILBOX_DriverIRQHandler
bx r0
.size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
.align 1
.thumb_func
.weak PIN_INT4_IRQHandler
.type PIN_INT4_IRQHandler, %function
PIN_INT4_IRQHandler:
ldr r0,=PIN_INT4_DriverIRQHandler
bx r0
.size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
.align 1
.thumb_func
.weak PIN_INT5_IRQHandler
.type PIN_INT5_IRQHandler, %function
PIN_INT5_IRQHandler:
ldr r0,=PIN_INT5_DriverIRQHandler
bx r0
.size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
.align 1
.thumb_func
.weak PIN_INT6_IRQHandler
.type PIN_INT6_IRQHandler, %function
PIN_INT6_IRQHandler:
ldr r0,=PIN_INT6_DriverIRQHandler
bx r0
.size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
.align 1
.thumb_func
.weak PIN_INT7_IRQHandler
.type PIN_INT7_IRQHandler, %function
PIN_INT7_IRQHandler:
ldr r0,=PIN_INT7_DriverIRQHandler
bx r0
.size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
.align 1
.thumb_func
.weak CTIMER2_IRQHandler
.type CTIMER2_IRQHandler, %function
CTIMER2_IRQHandler:
ldr r0,=CTIMER2_DriverIRQHandler
bx r0
.size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
.align 1
.thumb_func
.weak CTIMER4_IRQHandler
.type CTIMER4_IRQHandler, %function
CTIMER4_IRQHandler:
ldr r0,=CTIMER4_DriverIRQHandler
bx r0
.size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
.align 1
.thumb_func
.weak OS_EVENT_IRQHandler
.type OS_EVENT_IRQHandler, %function
OS_EVENT_IRQHandler:
ldr r0,=OS_EVENT_DriverIRQHandler
bx r0
.size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
.align 1
.thumb_func
.weak Reserved55_IRQHandler
.type Reserved55_IRQHandler, %function
Reserved55_IRQHandler:
ldr r0,=Reserved55_DriverIRQHandler
bx r0
.size Reserved55_IRQHandler, . - Reserved55_IRQHandler
.align 1
.thumb_func
.weak Reserved56_IRQHandler
.type Reserved56_IRQHandler, %function
Reserved56_IRQHandler:
ldr r0,=Reserved56_DriverIRQHandler
bx r0
.size Reserved56_IRQHandler, . - Reserved56_IRQHandler
.align 1
.thumb_func
.weak Reserved57_IRQHandler
.type Reserved57_IRQHandler, %function
Reserved57_IRQHandler:
ldr r0,=Reserved57_DriverIRQHandler
bx r0
.size Reserved57_IRQHandler, . - Reserved57_IRQHandler
.align 1
.thumb_func
.weak SDIO_IRQHandler
.type SDIO_IRQHandler, %function
SDIO_IRQHandler:
ldr r0,=SDIO_DriverIRQHandler
bx r0
.size SDIO_IRQHandler, . - SDIO_IRQHandler
.align 1
.thumb_func
.weak Reserved59_IRQHandler
.type Reserved59_IRQHandler, %function
Reserved59_IRQHandler:
ldr r0,=Reserved59_DriverIRQHandler
bx r0
.size Reserved59_IRQHandler, . - Reserved59_IRQHandler
.align 1
.thumb_func
.weak Reserved60_IRQHandler
.type Reserved60_IRQHandler, %function
Reserved60_IRQHandler:
ldr r0,=Reserved60_DriverIRQHandler
bx r0
.size Reserved60_IRQHandler, . - Reserved60_IRQHandler
.align 1
.thumb_func
.weak Reserved61_IRQHandler
.type Reserved61_IRQHandler, %function
Reserved61_IRQHandler:
ldr r0,=Reserved61_DriverIRQHandler
bx r0
.size Reserved61_IRQHandler, . - Reserved61_IRQHandler
.align 1
.thumb_func
.weak USB1_PHY_IRQHandler
.type USB1_PHY_IRQHandler, %function
USB1_PHY_IRQHandler:
ldr r0,=USB1_PHY_DriverIRQHandler
bx r0
.size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler
.align 1
.thumb_func
.weak USB1_IRQHandler
.type USB1_IRQHandler, %function
USB1_IRQHandler:
ldr r0,=USB1_DriverIRQHandler
bx r0
.size USB1_IRQHandler, . - USB1_IRQHandler
.align 1
.thumb_func
.weak USB1_NEEDCLK_IRQHandler
.type USB1_NEEDCLK_IRQHandler, %function
USB1_NEEDCLK_IRQHandler:
ldr r0,=USB1_NEEDCLK_DriverIRQHandler
bx r0
.size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
.align 1
.thumb_func
.weak SEC_HYPERVISOR_CALL_IRQHandler
.type SEC_HYPERVISOR_CALL_IRQHandler, %function
SEC_HYPERVISOR_CALL_IRQHandler:
ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
bx r0
.size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
.align 1
.thumb_func
.weak SEC_GPIO_INT0_IRQ0_IRQHandler
.type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
SEC_GPIO_INT0_IRQ0_IRQHandler:
ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
bx r0
.size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
.align 1
.thumb_func
.weak SEC_GPIO_INT0_IRQ1_IRQHandler
.type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
SEC_GPIO_INT0_IRQ1_IRQHandler:
ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
bx r0
.size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
.align 1
.thumb_func
.weak PLU_IRQHandler
.type PLU_IRQHandler, %function
PLU_IRQHandler:
ldr r0,=PLU_DriverIRQHandler
bx r0
.size PLU_IRQHandler, . - PLU_IRQHandler
.align 1
.thumb_func
.weak SEC_VIO_IRQHandler
.type SEC_VIO_IRQHandler, %function
SEC_VIO_IRQHandler:
ldr r0,=SEC_VIO_DriverIRQHandler
bx r0
.size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
.align 1
.thumb_func
.weak HASHCRYPT_IRQHandler
.type HASHCRYPT_IRQHandler, %function
HASHCRYPT_IRQHandler:
ldr r0,=HASHCRYPT_DriverIRQHandler
bx r0
.size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
.align 1
.thumb_func
.weak CASER_IRQHandler
.type CASER_IRQHandler, %function
CASER_IRQHandler:
ldr r0,=CASER_DriverIRQHandler
bx r0
.size CASER_IRQHandler, . - CASER_IRQHandler
.align 1
.thumb_func
.weak PUF_IRQHandler
.type PUF_IRQHandler, %function
PUF_IRQHandler:
ldr r0,=PUF_DriverIRQHandler
bx r0
.size PUF_IRQHandler, . - PUF_IRQHandler
.align 1
.thumb_func
.weak PQ_IRQHandler
.type PQ_IRQHandler, %function
PQ_IRQHandler:
ldr r0,=PQ_DriverIRQHandler
bx r0
.size PQ_IRQHandler, . - PQ_IRQHandler
.align 1
.thumb_func
.weak DMA1_IRQHandler
.type DMA1_IRQHandler, %function
DMA1_IRQHandler:
ldr r0,=DMA1_DriverIRQHandler
bx r0
.size DMA1_IRQHandler, . - DMA1_IRQHandler
.align 1
.thumb_func
.weak FLEXCOMM8_IRQHandler
.type FLEXCOMM8_IRQHandler, %function
FLEXCOMM8_IRQHandler:
ldr r0,=FLEXCOMM8_DriverIRQHandler
bx r0
.size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SecureFault_Handler
def_irq_handler DebugMon_Handler
def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */
def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */
def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */
def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */
def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */
def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */
def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */
def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */
def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */
def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
def_irq_handler ADC0_DriverIRQHandler /* ADC0 */
def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */
def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */
def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */
def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */
def_irq_handler USB0_DriverIRQHandler /* USB device */
def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */
def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */
def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */
def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */
def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */
def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */
def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */
def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */
def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */
def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */
def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */
def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */
def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */
def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */
def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */
def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */
def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */
def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */
def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */
def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
.end
|
wuxx/nanoDAP | 13,965 | software/DAPLink/source/hic_hal/nxp/lpc4322/gcc/startup_LPC43xx.S | /**
* @file startup_MK20D5.s
* @brief
*
* DAPLink Interface Firmware
* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Copyright (c) 2009-2021, Arm Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0x5A5A5A5A /* Reserved */
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility */
.long DAPLINK_VERSION /* DAPLINK: Version */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long g_board_info /* DAPLINK: Pointer to board/family/target info */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External LPC43xx/M4 Interrupts */
.long DAC_IRQHandler /* 0 DAC interrupt */
.long M0APP_IRQHandler /* 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication */
.long DMA_IRQHandler /* 2 DMA interrupt */
.long 0 /* 3 Reserved */
.long FLASHEEPROM_IRQHandler /* 4 flash bank A, flash bank B, EEPROM ORed interrupt */
.long ETHERNET_IRQHandler /* 5 Ethernet interrupt */
.long SDIO_IRQHandler /* 6 SD/MMC interrupt */
.long LCD_IRQHandler /* 7 LCD interrupt */
.long USB0_IRQHandler /* 8 OTG interrupt */
.long USB1_IRQHandler /* 9 USB1 interrupt */
.long SCT_IRQHandler /* 10 SCT combined interrupt */
.long RITIMER_IRQHandler /* 11 RI Timer interrupt */
.long TIMER0_IRQHandler /* 12 Timer 0 interrupt */
.long TIMER1_IRQHandler /* 13 Timer 1 interrupt */
.long TIMER2_IRQHandler /* 14 Timer 2 interrupt */
.long TIMER3_IRQHandler /* 15 Timer 3 interrupt */
.long MCPWM_IRQHandler /* 16 Motor control PWM interrupt */
.long ADC0_IRQHandler /* 17 ADC0 interrupt */
.long I2C0_IRQHandler /* 18 I2C0 interrupt */
.long I2C1_IRQHandler /* 19 I2C1 interrupt */
.long SPI_IRQHandler /* 20 SPI interrupt */
.long ADC1_IRQHandler /* 21 ADC1 interrupt */
.long SSP0_IRQHandler /* 22 SSP0 interrupt */
.long SSP1_IRQHandler /* 23 SSP1 interrupt */
.long USART0_IRQHandler /* 24 USART0 interrupt */
.long UART1_IRQHandler /* 25 Combined UART1, Modem interrupt */
.long USART2_IRQHandler /* 26 USART2 interrupt */
.long USART3_IRQHandler /* 27 Combined USART3, IrDA interrupt */
.long I2S0_IRQHandler /* 28 I2S0 interrupt */
.long I2S1_IRQHandler /* 29 I2S1 interrupt */
.long SPIFI_IRQHandler /* 30 SPISI interrupt */
.long SGPIO_IRQHandler /* 31 SGPIO interrupt */
.long PIN_INT0_IRQHandler /* 32 GPIO pin interrupt 0 */
.long PIN_INT1_IRQHandler /* 33 GPIO pin interrupt 1 */
.long PIN_INT2_IRQHandler /* 34 GPIO pin interrupt 2 */
.long PIN_INT3_IRQHandler /* 35 GPIO pin interrupt 3 */
.long PIN_INT4_IRQHandler /* 36 GPIO pin interrupt 4 */
.long PIN_INT5_IRQHandler /* 37 GPIO pin interrupt 5 */
.long PIN_INT6_IRQHandler /* 38 GPIO pin interrupt 6 */
.long PIN_INT7_IRQHandler /* 39 GPIO pin interrupt 7 */
.long GINT0_IRQHandler /* 40 GPIO global interrupt 0 */
.long GINT1_IRQHandler /* 41 GPIO global interrupt 1 */
.long EVENTROUTER_IRQHandler /* 42 Event router interrupt */
.long C_CAN1_IRQHandler /* 43 C_CAN1 interrupt */
.long 0 /* 44 Reserved */
.long ADCHS_IRQHandler /* 45 ADCHS combined interrupt */
.long ATIMER_IRQHandler /* 46 Alarm timer interrupt */
.long RTC_IRQHandler /* 47 RTC interrupt */
.long 0 /* 48 Reserved */
.long WWDT_IRQHandler /* 49 WWDT interrupt */
.long M0SUB_IRQHandler /* 50 TXEV instruction from the M0 subsystem core interrupt */
.long C_CAN0_IRQHandler /* 51 C_CAN0 interrupt */
.long QEI_IRQHandler /* 52 QEI interrupt */
#if defined(MBED_BOOTLOADER)
// Set the CRP (Code Read Protection) configuration word at address 0x2FC to ensure that
// CRP is disabled.
#define CRP_KEY_ADDR (0x000002FC)
#define CRP_DISABLED (0xFFFFFFFF)
1: // Fill up to CRP config word address.
.dcb.l ((CRP_KEY_ADDR - (1b - __isr_vector)) / 4)
CRP_Key:
.long CRP_DISABLED
#endif // MBED_BOOTLOADER
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
ldr r0,=MemManage_Handler
bx r0
.size MemManage_Handler, . - MemManage_Handler
.align 1
.thumb_func
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
ldr r0,=BusFault_Handler
bx r0
.size BusFault_Handler, . - BusFault_Handler
.align 1
.thumb_func
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
ldr r0,=UsageFault_Handler
bx r0
.size UsageFault_Handler, . - UsageFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
ldr r0,=DebugMon_Handler
bx r0
.size DebugMon_Handler, . - DebugMon_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler DAC_IRQHandler /* D/A Converter */
def_irq_handler M0APP_IRQHandler /* M0 Core */
def_irq_handler DMA_IRQHandler /* General Purpose DMA */
def_irq_handler FLASHEEPROM_IRQHandler /* EZH/EDM */
def_irq_handler ETHERNET_IRQHandler /* Ethernet */
def_irq_handler SDIO_IRQHandler /* SD/MMC */
def_irq_handler LCD_IRQHandler /* LCD */
def_irq_handler USB0_IRQHandler /* USB0 */
def_irq_handler USB1_IRQHandler /* USB1 */
def_irq_handler SCT_IRQHandler /* State Configurable Timer */
def_irq_handler RITIMER_IRQHandler /* Repetitive Interrupt Timer */
def_irq_handler TIMER0_IRQHandler /* Timer0 */
def_irq_handler TIMER1_IRQHandler /* Timer1 */
def_irq_handler TIMER2_IRQHandler /* Timer2 */
def_irq_handler TIMER3_IRQHandler /* Timer3 */
def_irq_handler MCPWM_IRQHandler /* Motor Control PWM */
def_irq_handler ADC0_IRQHandler /* A/D Converter 0 */
def_irq_handler I2C0_IRQHandler /* I2C0 */
def_irq_handler I2C1_IRQHandler /* I2C1 */
def_irq_handler SPI_IRQHandler /* SPI */
def_irq_handler ADC1_IRQHandler /* A/D Converter 1 */
def_irq_handler SSP0_IRQHandler /* SSP0 */
def_irq_handler SSP1_IRQHandler /* SSP1 */
def_irq_handler USART0_IRQHandler /* UART0 */
def_irq_handler UART1_IRQHandler /* UART1 */
def_irq_handler USART2_IRQHandler /* UART2 */
def_irq_handler USART3_IRQHandler /* UART3 */
def_irq_handler I2S0_IRQHandler /* I2S0 */
def_irq_handler I2S1_IRQHandler /* I2S1 */
def_irq_handler SPIFI_IRQHandler /* SPI Flash Interface */
def_irq_handler SGPIO_IRQHandler /* SGPIO */
def_irq_handler PIN_INT0_IRQHandler /* GPIO0 */
def_irq_handler PIN_INT1_IRQHandler /* GPIO1 */
def_irq_handler PIN_INT2_IRQHandler /* GPIO2 */
def_irq_handler PIN_INT3_IRQHandler /* GPIO3 */
def_irq_handler PIN_INT4_IRQHandler /* GPIO4 */
def_irq_handler PIN_INT5_IRQHandler /* GPIO5 */
def_irq_handler PIN_INT6_IRQHandler /* GPIO6 */
def_irq_handler PIN_INT7_IRQHandler /* GPIO7 */
def_irq_handler GINT0_IRQHandler /* GINT0 */
def_irq_handler GINT1_IRQHandler /* GINT1 */
def_irq_handler EVENTROUTER_IRQHandler /* Event Router */
def_irq_handler C_CAN1_IRQHandler /* C_CAN1 */
def_irq_handler ADCHS_IRQHandler /* VADC */
def_irq_handler ATIMER_IRQHandler /* ATIMER */
def_irq_handler RTC_IRQHandler /* RTC */
def_irq_handler WWDT_IRQHandler /* WDT */
def_irq_handler M0SUB_IRQHandler /* M0s */
def_irq_handler C_CAN0_IRQHandler /* C_CAN0 */
def_irq_handler QEI_IRQHandler /* QEI */
.end
|
wuxx/nanoDAP | 15,214 | software/DAPLink/source/hic_hal/nxp/lpc4322/armcc/startup_LPC43xx.s | ;/**************************************************************************//**
; * @file LPC43xx.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * NXP LPC43xxDevice Series
; * @version V1.00
; * @date 03. September 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT g_board_info
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD DAPLINK_BUILD_KEY ; 8 DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; 9 DAPLINK: Compatibility
DCD DAPLINK_VERSION ; 10 DAPLINK: Version
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD g_board_info ; 13 DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External LPC43xx/M4 Interrupts
DCD DAC_IRQHandler ; 0 DAC interrupt
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
DCD DMA_IRQHandler ; 2 DMA interrupt
DCD 0 ; 3 Reserved
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
DCD LCD_IRQHandler ; 7 LCD interrupt
DCD USB0_IRQHandler ; 8 OTG interrupt
DCD USB1_IRQHandler ; 9 USB1 interrupt
DCD SCT_IRQHandler ; 10 SCT combined interrupt
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
DCD SPI_IRQHandler ; 20 SPI interrupt
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
DCD USART0_IRQHandler ; 24 USART0 interrupt
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
DCD USART2_IRQHandler ; 26 USART2 interrupt
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
DCD 0 ; 44 Reserved
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
DCD RTC_IRQHandler ; 47 RTC interrupt
DCD 0 ; 48 Reserved
DCD WWDT_IRQHandler ; 49 WWDT interrupt
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
DCD QEI_IRQHandler ; 52 QEI interrupt
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
#if defined(DAPLINK_BL)
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
#endif
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0APP_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROM_IRQHandler [WEAK]
EXPORT ETHERNET_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RITIMER_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT C_CAN1_IRQHandler [WEAK]
EXPORT ADCHS_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT M0SUB_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0APP_IRQHandler
DMA_IRQHandler
FLASHEEPROM_IRQHandler
ETHERNET_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ADCHS_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
M0SUB_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 8,575 | software/DAPLink/source/hic_hal/nxp/lpc11u35/gcc/startup_LPC11Uxx.S | /**
* @file startup_LPC11Uxx.s
* @brief CMSIS Cortex-M0 Core Device Startup File for
* NXP LPC11Uxx Device Series
*
* DAPLink Interface Firmware
* Copyright (c) 2009-2020, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
.arch armv6-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility */
.long DAPLINK_VERSION /* DAPLINK: Version */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long g_board_info /* DAPLINK: Pointer to board/family/target info */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* LPC11xx interrupts */
.long FLEX_INT0_IRQHandler /* 16+ 0 All GPIO pin can be routed to FLEX_INTx */
.long FLEX_INT1_IRQHandler /* 16+ 1 Pin interrupt */
.long FLEX_INT2_IRQHandler /* 16+ 2 Pin interrupt */
.long FLEX_INT3_IRQHandler /* 16+ 3 Pin interrupt */
.long FLEX_INT4_IRQHandler /* 16+ 4 Pin interrupt */
.long FLEX_INT5_IRQHandler /* 16+ 5 Pin interrupt */
.long FLEX_INT6_IRQHandler /* 16+ 6 Pin interrupt */
.long FLEX_INT7_IRQHandler /* 16+ 7 Pin interrupt */
.long GINT0_IRQHandler /* 16+ 8 Port interrupt */
.long GINT1_IRQHandler /* 16+ 9 Port interrupt */
.long Reserved_IRQHandler /* 16+10 Reserved */
.long Reserved_IRQHandler /* 16+11 Reserved */
.long Reserved_IRQHandler /* 16+12 Reserved */
.long Reserved_IRQHandler /* 16+13 Reserved */
.long SSP1_IRQHandler /* 16+14 SSP1 */
.long I2C_IRQHandler /* 16+15 I2C */
.long TIMER16_0_IRQHandler /* 16+16 16-bit Timer0 */
.long TIMER16_1_IRQHandler /* 16+17 16-bit Timer1 */
.long TIMER32_0_IRQHandler /* 16+18 32-bit Timer0 */
.long TIMER32_1_IRQHandler /* 16+19 32-bit Timer1 */
.long SSP0_IRQHandler /* 16+20 SSP0 */
.long UART_IRQHandler /* 16+21 UART */
.long USB_IRQHandler /* 16+22 USB IRQ */
.long USB_FIQHandler /* 16+23 USB IRQ */
.long ADC_IRQHandler /* 16+24 A/D Converter */
.long WDT_IRQHandler /* 16+25 Watchdog Timer */
.long BOD_IRQHandler /* 16+26 Brown Out Detect */
.long FMC_IRQHandler /* 16+27 IP2111 Flash Memory Controller */
.long Reserved_IRQHandler /* 16+28 Reserved */
.long Reserved_IRQHandler /* 16+29 Reserved */
.long USBWakeup_IRQHandler /* 16+30 USB wake up */
.long IOH_IRQHandler /* 16+31 I/O Handler */
/* Set the CRP (Code Read Protection) configuration word
* at address 0x2FC to ensure that CRP is disabled.
* - 0xFFFFFFFF => CRP Disabled
* - 0x12345678 => CRP Level 1
* - 0x87654321 => CRP Level 2
* - 0x43218765 => CRP Level 3 (ARE YOU SURE?)
* - 0x4E697370 => NO ISP (ARE YOU SURE?)
*/
#define CRP_KEY_ADDR (0x000002FC)
#define CRP_DISABLED (0xFFFFFFFF)
1: /* Fill up to CRP config word address. */
.dcb.l ((CRP_KEY_ADDR - (1b - __isr_vector)) / 4)
CRP_Key:
.long CRP_DISABLED
.size __isr_vector, . - __isr_vector
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
/* Power on RAM1 and USBRAM area */
ldr r0, =0x40048080 /* System clock control */
ldr r1, =0x0C00485F /* boot default + RAM1, USBRAM */
str r1, [r0]
ldr r0, =SystemInit
blx r0
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC1
movs r4, 0
.LC0:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .LC0
.LC1:
cpsie i /* Unmask interrupts */
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
def_default_handler Reserved_IRQHandler
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler FLEX_INT0_IRQHandler
def_irq_handler FLEX_INT1_IRQHandler
def_irq_handler FLEX_INT2_IRQHandler
def_irq_handler FLEX_INT3_IRQHandler
def_irq_handler FLEX_INT4_IRQHandler
def_irq_handler FLEX_INT5_IRQHandler
def_irq_handler FLEX_INT6_IRQHandler
def_irq_handler FLEX_INT7_IRQHandler
def_irq_handler GINT0_IRQHandler
def_irq_handler GINT1_IRQHandler
def_irq_handler SSP1_IRQHandler
def_irq_handler I2C_IRQHandler
def_irq_handler TIMER16_0_IRQHandler
def_irq_handler TIMER16_1_IRQHandler
def_irq_handler TIMER32_0_IRQHandler
def_irq_handler TIMER32_1_IRQHandler
def_irq_handler SSP0_IRQHandler
def_irq_handler UART_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler USB_FIQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler BOD_IRQHandler
def_irq_handler FMC_IRQHandler
def_irq_handler USBWakeup_IRQHandler
def_irq_handler IOH_IRQHandler
.end
|
wuxx/nanoDAP | 13,752 | software/DAPLink/source/hic_hal/nxp/lpc11u35/armcc/startup_LPC11Uxx.s | ;/**
; * @file startup_LPC11Uxx.s
; * @brief
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000100
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
DCD FLEX_INT1_IRQHandler
DCD FLEX_INT2_IRQHandler
DCD FLEX_INT3_IRQHandler
DCD FLEX_INT4_IRQHandler
DCD FLEX_INT5_IRQHandler
DCD FLEX_INT6_IRQHandler
DCD FLEX_INT7_IRQHandler
DCD GINT0_IRQHandler
DCD GINT1_IRQHandler ; PIO0 (0:7)
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD Reserved_IRQHandler
DCD SSP1_IRQHandler ; SSP1
DCD I2C_IRQHandler ; I2C
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
DCD SSP0_IRQHandler ; SSP0
DCD UART_IRQHandler ; UART
DCD USB_IRQHandler ; USB IRQ
DCD USB_FIQHandler ; USB FIQ
DCD ADC_IRQHandler ; A/D Converter
DCD WDT_IRQHandler ; Watchdog timer
DCD BOD_IRQHandler ; Brown Out Detect
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
DCD Reserved_IRQHandler ; Reserved
DCD Reserved_IRQHandler ; Reserved
DCD USBWakeup_IRQHandler ; USB wake up
DCD Reserved_IRQHandler ; Reserved
IF :DEF:MBED_BOOTLOADER
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
DCD 0xFFFFFFFF ; Datafill
ENDIF
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Power on RAM1 and USBRAM area
LDR R0, =0x40048080 ; System clock control
LDR R1, =0x0C00485F ; boot default + RAM1, USBRAM
STR R1, [R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
; for particular peripheral.
;NMI_Handler PROC
; EXPORT NMI_Handler [WEAK]
; B .
; ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Reserved_IRQHandler PROC
EXPORT Reserved_IRQHandler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT FLEX_INT0_IRQHandler [WEAK]
EXPORT FLEX_INT1_IRQHandler [WEAK]
EXPORT FLEX_INT2_IRQHandler [WEAK]
EXPORT FLEX_INT3_IRQHandler [WEAK]
EXPORT FLEX_INT4_IRQHandler [WEAK]
EXPORT FLEX_INT5_IRQHandler [WEAK]
EXPORT FLEX_INT6_IRQHandler [WEAK]
EXPORT FLEX_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT TIMER16_0_IRQHandler [WEAK]
EXPORT TIMER16_1_IRQHandler [WEAK]
EXPORT TIMER32_0_IRQHandler [WEAK]
EXPORT TIMER32_1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT USB_FIQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT USBWakeup_IRQHandler [WEAK]
NMI_Handler
FLEX_INT0_IRQHandler
FLEX_INT1_IRQHandler
FLEX_INT2_IRQHandler
FLEX_INT3_IRQHandler
FLEX_INT4_IRQHandler
FLEX_INT5_IRQHandler
FLEX_INT6_IRQHandler
FLEX_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
SSP1_IRQHandler
I2C_IRQHandler
TIMER16_0_IRQHandler
TIMER16_1_IRQHandler
TIMER32_0_IRQHandler
TIMER32_1_IRQHandler
SSP0_IRQHandler
UART_IRQHandler
USB_IRQHandler
USB_FIQHandler
ADC_IRQHandler
WDT_IRQHandler
BOD_IRQHandler
FMC_IRQHandler
USBWakeup_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 12,411 | software/DAPLink/source/hic_hal/stm32/stm32f103xb/gcc/startup_stm32f103xb.S | /**
* @file startup_MK20D5.s
* @brief
*
* DAPLink Interface Firmware
* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016 - 2017 NXP
* Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors */
/*****************************************************************************/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler*/
.long HardFault_Handler /* Hard Fault Handler*/
.long MemManage_Handler /* MPU Fault Handler*/
.long BusFault_Handler /* Bus Fault Handler*/
.long UsageFault_Handler /* Usage Fault Handler*/
.long 0 /* Reserved*/
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF)*/
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility*/
.long DAPLINK_VERSION /* DAPLINK: Version*/
.long SVC_Handler /* SVCall Handler*/
.long DebugMon_Handler /* Debug Monitor Handler*/
.long g_board_info /* DAPLINK: Pointer to board/family/target info*/
.long PendSV_Handler /* PendSV Handler*/
.long SysTick_Handler /* SysTick Handler*/
/* External Interrupts*/
.long WWDG_IRQHandler /* Window Watchdog */
.long PVD_IRQHandler /* PVD through EXTI Line detect */
.long TAMPER_IRQHandler /* Tamper */
.long RTC_IRQHandler /* RTC */
.long FLASH_IRQHandler /* Flash */
.long RCC_IRQHandler /* RCC */
.long EXTI0_IRQHandler /* EXTI Line 0 */
.long EXTI1_IRQHandler /* EXTI Line 1 */
.long EXTI2_IRQHandler /* EXTI Line 2 */
.long EXTI3_IRQHandler /* EXTI Line 3 */
.long EXTI4_IRQHandler /* EXTI Line 4 */
.long DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.long DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.long DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.long DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.long DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.long DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.long DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.long ADC1_2_IRQHandler /* ADC1_2 */
.long USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */
.long USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */
.long CAN1_RX1_IRQHandler /* CAN1 RX1 */
.long CAN1_SCE_IRQHandler /* CAN1 SCE */
.long EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.long TIM1_BRK_IRQHandler /* TIM1 Break */
.long TIM1_UP_IRQHandler /* TIM1 Update */
.long TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.long TIM2_IRQHandler /* TIM2 */
.long TIM3_IRQHandler /* TIM3 */
.long TIM4_IRQHandler /* TIM4 */
.long I2C1_EV_IRQHandler /* I2C1 Event */
.long I2C1_ER_IRQHandler /* I2C1 Error */
.long I2C2_EV_IRQHandler /* I2C2 Event */
.long I2C2_ER_IRQHandler /* I2C2 Error */
.long SPI1_IRQHandler /* SPI1 */
.long SPI2_IRQHandler /* SPI2 */
.long USART1_IRQHandler /* USART1 */
.long USART2_IRQHandler /* USART2 */
.long USART3_IRQHandler /* USART3 */
.long EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.long RTC_Alarm_IRQHandler /* RTC Alarm through EXTI Line */
.long USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.size __isr_vector, . - __isr_vector
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
.equ VTOR, 0xE000ED08
ldr r0, =VTOR
ldr r1, =__isr_vector
str r1, [r0]
ldr r2, [r1]
msr msp, r2
#ifndef __NO_SYSTEM_INIT
ldr r0,=SystemInit
blx r0
#endif
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
#if 1
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
#endif /* __STARTUP_CLEAR_BSS */
cpsie i /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
ldr r0,=__START
blx r0
#else
ldr r0,=__libc_init_array
blx r0
ldr r0,=main
bx r0
#endif
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
.align 1
.thumb_func
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
ldr r0,=NMI_Handler
bx r0
.size NMI_Handler, . - NMI_Handler
.align 1
.thumb_func
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
ldr r0,=HardFault_Handler
bx r0
.size HardFault_Handler, . - HardFault_Handler
.align 1
.thumb_func
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
ldr r0,=MemManage_Handler
bx r0
.size MemManage_Handler, . - MemManage_Handler
.align 1
.thumb_func
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
ldr r0,=BusFault_Handler
bx r0
.size BusFault_Handler, . - BusFault_Handler
.align 1
.thumb_func
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
ldr r0,=UsageFault_Handler
bx r0
.size UsageFault_Handler, . - UsageFault_Handler
.align 1
.thumb_func
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
ldr r0,=SVC_Handler
bx r0
.size SVC_Handler, . - SVC_Handler
.align 1
.thumb_func
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
ldr r0,=DebugMon_Handler
bx r0
.size DebugMon_Handler, . - DebugMon_Handler
.align 1
.thumb_func
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
ldr r0,=PendSV_Handler
bx r0
.size PendSV_Handler, . - PendSV_Handler
.align 1
.thumb_func
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
ldr r0,=SysTick_Handler
bx r0
.size SysTick_Handler, . - SysTick_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler WWDG_IRQHandler /* Window Watchdog */
def_irq_handler PVD_IRQHandler /* PVD through EXTI Line detect */
def_irq_handler TAMPER_IRQHandler /* Tamper */
def_irq_handler RTC_IRQHandler /* RTC */
def_irq_handler FLASH_IRQHandler /* Flash */
def_irq_handler RCC_IRQHandler /* RCC */
def_irq_handler EXTI0_IRQHandler /* EXTI Line 0 */
def_irq_handler EXTI1_IRQHandler /* EXTI Line 1 */
def_irq_handler EXTI2_IRQHandler /* EXTI Line 2 */
def_irq_handler EXTI3_IRQHandler /* EXTI Line 3 */
def_irq_handler EXTI4_IRQHandler /* EXTI Line 4 */
def_irq_handler DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
def_irq_handler DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
def_irq_handler DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
def_irq_handler DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
def_irq_handler DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
def_irq_handler DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
def_irq_handler DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
def_irq_handler ADC1_2_IRQHandler /* ADC1_2 */
def_irq_handler USB_HP_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */
def_irq_handler USB_LP_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */
def_irq_handler CAN1_RX1_IRQHandler /* CAN1 RX1 */
def_irq_handler CAN1_SCE_IRQHandler /* CAN1 SCE */
def_irq_handler EXTI9_5_IRQHandler /* EXTI Line 9..5 */
def_irq_handler TIM1_BRK_IRQHandler /* TIM1 Break */
def_irq_handler TIM1_UP_IRQHandler /* TIM1 Update */
def_irq_handler TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
def_irq_handler TIM1_CC_IRQHandler /* TIM1 Capture Compare */
def_irq_handler TIM2_IRQHandler /* TIM2 */
def_irq_handler TIM3_IRQHandler /* TIM3 */
def_irq_handler TIM4_IRQHandler /* TIM4 */
def_irq_handler I2C1_EV_IRQHandler /* I2C1 Event */
def_irq_handler I2C1_ER_IRQHandler /* I2C1 Error */
def_irq_handler I2C2_EV_IRQHandler /* I2C2 Event */
def_irq_handler I2C2_ER_IRQHandler /* I2C2 Error */
def_irq_handler SPI1_IRQHandler /* SPI1 */
def_irq_handler SPI2_IRQHandler /* SPI2 */
def_irq_handler USART1_IRQHandler /* USART1 */
def_irq_handler USART2_IRQHandler /* USART2 */
def_irq_handler USART3_IRQHandler /* USART3 */
def_irq_handler EXTI15_10_IRQHandler /* EXTI Line 15..10 */
def_irq_handler RTC_Alarm_IRQHandler /* RTC Alarm through EXTI Line */
def_irq_handler USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.end
|
wuxx/nanoDAP | 13,590 | software/DAPLink/source/hic_hal/stm32/stm32f103xb/armcc/startup_stm32f103xb.S | ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Version : V4.1.0
;* Date : 29-April-2016
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* COPYRIGHT(c) 2016 STMicroelectronics
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
wuxx/nanoDAP | 11,366 | software/DAPLink/source/hic_hal/nordic/nrf52820/gcc/gcc_startup_nrf52820.S | /*
Copyright (c) 2009-2021 Arm Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
NOTICE: This file has been modified for DAPLink
*/
.syntax unified
.arch armv7e-m
.section .isr_vector, "ax"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler
.long NMI_Handler
.long HardFault_Handler
.long MemoryManagement_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long 0 /*Reserved */
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility */
.long DAPLINK_VERSION /* DAPLINK: Version */
.long SVC_Handler
.long DebugMon_Handler
.long g_board_info /* DAPLINK: Pointer to board/family/target info */
.long PendSV_Handler
.long SysTick_Handler
/* External Interrupts */
.long POWER_CLOCK_IRQHandler
.long RADIO_IRQHandler
.long UARTE0_UART0_IRQHandler
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.long 0 /*Reserved */
.long GPIOTE_IRQHandler
.long 0 /*Reserved */
.long TIMER0_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
.long RTC0_IRQHandler
.long TEMP_IRQHandler
.long RNG_IRQHandler
.long ECB_IRQHandler
.long CCM_AAR_IRQHandler
.long WDT_IRQHandler
.long RTC1_IRQHandler
.long QDEC_IRQHandler
.long COMP_IRQHandler
.long SWI0_EGU0_IRQHandler
.long SWI1_EGU1_IRQHandler
.long SWI2_EGU2_IRQHandler
.long SWI3_EGU3_IRQHandler
.long SWI4_EGU4_IRQHandler
.long SWI5_EGU5_IRQHandler
.long TIMER3_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long USBD_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.size __isr_vector, . - __isr_vector
/* Reset Handler */
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM.
* The ranges of copy from/to are specified by following symbols:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __data_end__: VMA of end of the section to copy to.
*
* All addresses must be aligned to 4 bytes boundary.
*/
#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
* clears the RAM where BSS data is located.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* All addresses must be aligned to 4 bytes boundary.
*/
#ifdef __STARTUP_CLEAR_BSS
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS */
/* Execute SystemInit function. */
bl SystemInit
/* Call _start function provided by libraries.
* If those libraries are not accessible, define __START as your entry point.
*/
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler,.-Reset_Handler
.section ".text"
/* Dummy Exception Handlers (infinite loops which can be modified) */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
b .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
b .
.size HardFault_Handler, . - HardFault_Handler
.weak MemoryManagement_Handler
.type MemoryManagement_Handler, %function
MemoryManagement_Handler:
b .
.size MemoryManagement_Handler, . - MemoryManagement_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
b .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
b .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
b .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
b .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
b .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
b .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ POWER_CLOCK_IRQHandler
IRQ RADIO_IRQHandler
IRQ UARTE0_UART0_IRQHandler
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
IRQ GPIOTE_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ RTC0_IRQHandler
IRQ TEMP_IRQHandler
IRQ RNG_IRQHandler
IRQ ECB_IRQHandler
IRQ CCM_AAR_IRQHandler
IRQ WDT_IRQHandler
IRQ RTC1_IRQHandler
IRQ QDEC_IRQHandler
IRQ COMP_IRQHandler
IRQ SWI0_EGU0_IRQHandler
IRQ SWI1_EGU1_IRQHandler
IRQ SWI2_EGU2_IRQHandler
IRQ SWI3_EGU3_IRQHandler
IRQ SWI4_EGU4_IRQHandler
IRQ SWI5_EGU5_IRQHandler
IRQ TIMER3_IRQHandler
IRQ USBD_IRQHandler
.end
|
wuxx/nanoDAP | 13,701 | software/DAPLink/source/hic_hal/nordic/nrf52820/armcc/arm_startup_nrf52820.s | ; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
; Licensed under the Apache License, Version 2.0 (the License); you may
; not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
#endif
#endif
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 2048
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
ELSE
Stack_Align EQU 3
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
Stack_Mem SPACE Stack_Size
__initial_sp
IF :DEF: __STARTUP_CONFIG
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 2048
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler
DCD DebugMon_Handler
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD 0 ; Reserved
DCD GPIOTE_IRQHandler
DCD 0 ; Reserved
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
DCD QDEC_IRQHandler
DCD COMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
DCD SWI2_EGU2_IRQHandler
DCD SWI3_EGU3_IRQHandler
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD USBD_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_EGU2_IRQHandler [WEAK]
EXPORT SWI3_EGU3_IRQHandler [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
COMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_EGU2_IRQHandler
SWI3_EGU3_IRQHandler
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler
USBD_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
|
wuxx/nanoDAP | 17,708 | software/DAPLink/source/hic_hal/nuvoton/m48ssidae/gcc/startup_M480.S | /**
* @file startup_M480.s
* @brief
*
* DAPLink Interface Firmware
* Copyright (c) 2022 Nuvoton Technology Corp. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
.arch armv7-m
.section .isr_vector, "a"
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long DAPLINK_BUILD_KEY /* DAPLINK: Build type (BL/IF) */
.long DAPLINK_HIC_ID /* DAPLINK: Compatibility */
.long DAPLINK_VERSION /* DAPLINK: Version */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long g_board_info /* DAPLINK: Pointer to board/family/target info */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BOD_IRQHandler /* 0: BOD */
.long IRC_IRQHandler /* 1: IRC */
.long PWRWU_IRQHandler /* 2: PWRWU */
.long RAMPE_IRQHandler /* 3: RAMPE */
.long CKFAIL_IRQHandler /* 4: CKFAIL */
.long 0 /* 5: Reserved */
.long RTC_IRQHandler /* 6: RTC */
.long TAMPER_IRQHandler /* 7: TAMPER */
.long WDT_IRQHandler /* 8: WDT */
.long WWDT_IRQHandler /* 9: WWDT */
.long EINT0_IRQHandler /* 10: EINT0 */
.long EINT1_IRQHandler /* 11: EINT1 */
.long EINT2_IRQHandler /* 12: EINT2 */
.long EINT3_IRQHandler /* 13: EINT3 */
.long EINT4_IRQHandler /* 14: EINT4 */
.long EINT5_IRQHandler /* 15: EINT5 */
.long GPA_IRQHandler /* 16: GPA */
.long GPB_IRQHandler /* 17: GPB */
.long GPC_IRQHandler /* 18: GPC */
.long GPD_IRQHandler /* 19: GPD */
.long GPE_IRQHandler /* 20: GPE */
.long GPF_IRQHandler /* 21: GPF */
.long QSPI0_IRQHandler /* 22: QSPI0 */
.long SPI0_IRQHandler /* 23: SPI0 */
.long BRAKE0_IRQHandler /* 24: BRAKE0 */
.long EPWM0P0_IRQHandler /* 25: EPWM0P0 */
.long EPWM0P1_IRQHandler /* 26: EPWM0P1 */
.long EPWM0P2_IRQHandler /* 27: EPWM0P2 */
.long BRAKE1_IRQHandler /* 28: BRAKE1 */
.long EPWM1P0_IRQHandler /* 29: EPWM1P0 */
.long EPWM1P1_IRQHandler /* 30: EPWM1P1 */
.long EPWM1P2_IRQHandler /* 31: EPWM1P2 */
.long TMR0_IRQHandler /* 32: TIMER0 */
.long TMR1_IRQHandler /* 33: TIMER1 */
.long TMR2_IRQHandler /* 34: TIMER2 */
.long TMR3_IRQHandler /* 35: TIMER3 */
.long UART0_IRQHandler /* 36: UART0 */
.long UART1_IRQHandler /* 37: UART1 */
.long I2C0_IRQHandler /* 38: I2C0 */
.long I2C1_IRQHandler /* 39: I2C1 */
.long PDMA_IRQHandler /* 40: PDMA */
.long DAC_IRQHandler /* 41: DAC */
.long ADC00_IRQHandler /* 42: ADC00 */
.long ADC01_IRQHandler /* 43: ADC01 */
.long ACMP01_IRQHandler /* 44: ACMP */
.long 0 /* 45: Reserved */
.long ADC02_IRQHandler /* 46: ADC02 */
.long ADC03_IRQHandler /* 47: ADC03 */
.long UART2_IRQHandler /* 48: UART2 */
.long UART3_IRQHandler /* 49: UART3 */
.long 0 /* 50: Reserved */
.long SPI1_IRQHandler /* 51: SPI1 */
.long SPI2_IRQHandler /* 52: SPI2 */
.long USBD_IRQHandler /* 53: USBD */
.long OHCI_IRQHandler /* 54: OHCI */
.long USBOTG_IRQHandler /* 55: OTG */
.long CAN0_IRQHandler /* 56: CAN0 */
.long CAN1_IRQHandler /* 57: CAN1 */
.long SC0_IRQHandler /* 58: SC0 */
.long SC1_IRQHandler /* 59: SC1 */
.long SC2_IRQHandler /* 60: SC2 */
.long 0 /* 61: Reserved */
.long SPI3_IRQHandler /* 62: SPI3 */
.long 0 /* 63: Reserved */
.long SDH0_IRQHandler /* 64: SDH0 */
.long USBD20_IRQHandler /* 65: HSUSBD */
.long EMAC_TX_IRQHandler /* 66: EMAC_TX */
.long EMAC_RX_IRQHandler /* 67: EMAC_RX */
.long I2S0_IRQHandler /* 68: I2S */
.long 0 /* 69: Reserved */
.long OPA0_IRQHandler /* 70: OPA */
.long CRYPTO_IRQHandler /* 71: CRYPTO */
.long GPG_IRQHandler /* 72: GPG */
.long EINT6_IRQHandler /* 73: EINT6 */
.long UART4_IRQHandler /* 74: UART4 */
.long UART5_IRQHandler /* 75: UART5 */
.long USCI0_IRQHandler /* 76: USCI0 */
.long USCI1_IRQHandler /* 77: USCI1 */
.long BPWM0_IRQHandler /* 78: BPWM0 */
.long BPWM1_IRQHandler /* 79: BPWM1 */
.long SPIM_IRQHandler /* 80: SPIM */
.long 0 /* 81: Reserved */
.long I2C2_IRQHandler /* 82: I2C2 */
.long 0 /* 83: Reserved */
.long QEI0_IRQHandler /* 84: QEI0 */
.long QEI1_IRQHandler /* 85: QEI1 */
.long ECAP0_IRQHandler /* 86: ECAP0 */
.long ECAP1_IRQHandler /* 87: ECAP1 */
.long GPH_IRQHandler /* 88: GPH */
.long EINT7_IRQHandler /* 89: EINT7 */
.long SDH1_IRQHandler /* 90: SDH1 */
.long 0 /* 91: Reserved */
.long EHCI_IRQHandler /* 92: EHCI */
.long USBOTG20_IRQHandler /* 93: HSOTG */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Unlock Register */
ldr r0, =0x40000100
ldr r1, =0x59
str r1, [r0]
ldr r1, =0x16
str r1, [r0]
ldr r1, =0x88
str r1, [r0]
#ifndef ENABLE_SPIM_CACHE
ldr r0, =0x40000200 /* R0 = Clock Controller Register Base Address */
ldr r1, [r0,#0x4] /* R1 = 0x40000204 (AHBCLK) */
orr r1, r1, #0x4000
str r1, [r0,#0x4] /* CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk; */
ldr r0, =0x40007000 /* R0 = SPIM Register Base Address */
ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */
orr r1, r1,#2 /* R1 |= SPIM_CTL1_CACHEOFF_Msk */
str r1, [r0,#4] /* _SPIM_DISABLE_CACHE() */
ldr r1, [r0,#4] /* R1 = SPIM->CTL1 */
orr r1, r1, #4 /* R1 |= SPIM_CTL1_CCMEN_Msk */
str r1, [r0,#4] /* _SPIM_ENABLE_CCM() */
#endif
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
/* Init POR */
#if 0
ldr r0, =0x40000024
ldr r1, =0x00005AA5
str r1, [r0]
#endif
/* Lock register */
ldr r0, =0x40000100
ldr r1, =0
str r1, [r0]
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler BOD_IRQHandler
def_irq_handler IRC_IRQHandler
def_irq_handler PWRWU_IRQHandler
def_irq_handler RAMPE_IRQHandler
def_irq_handler CKFAIL_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler TAMPER_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler WWDT_IRQHandler
def_irq_handler EINT0_IRQHandler
def_irq_handler EINT1_IRQHandler
def_irq_handler EINT2_IRQHandler
def_irq_handler EINT3_IRQHandler
def_irq_handler EINT4_IRQHandler
def_irq_handler EINT5_IRQHandler
def_irq_handler GPA_IRQHandler
def_irq_handler GPB_IRQHandler
def_irq_handler GPC_IRQHandler
def_irq_handler GPD_IRQHandler
def_irq_handler GPE_IRQHandler
def_irq_handler GPF_IRQHandler
def_irq_handler QSPI0_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler BRAKE0_IRQHandler
def_irq_handler EPWM0P0_IRQHandler
def_irq_handler EPWM0P1_IRQHandler
def_irq_handler EPWM0P2_IRQHandler
def_irq_handler BRAKE1_IRQHandler
def_irq_handler EPWM1P0_IRQHandler
def_irq_handler EPWM1P1_IRQHandler
def_irq_handler EPWM1P2_IRQHandler
def_irq_handler TMR0_IRQHandler
def_irq_handler TMR1_IRQHandler
def_irq_handler TMR2_IRQHandler
def_irq_handler TMR3_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler I2C0_IRQHandler
def_irq_handler I2C1_IRQHandler
def_irq_handler PDMA_IRQHandler
def_irq_handler DAC_IRQHandler
def_irq_handler ADC00_IRQHandler
def_irq_handler ADC01_IRQHandler
def_irq_handler ACMP01_IRQHandler
def_irq_handler ADC02_IRQHandler
def_irq_handler ADC03_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler UART3_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler SPI2_IRQHandler
def_irq_handler USBD_IRQHandler
def_irq_handler OHCI_IRQHandler
def_irq_handler USBOTG_IRQHandler
def_irq_handler CAN0_IRQHandler
def_irq_handler CAN1_IRQHandler
def_irq_handler SC0_IRQHandler
def_irq_handler SC1_IRQHandler
def_irq_handler SC2_IRQHandler
def_irq_handler SPI3_IRQHandler
def_irq_handler SDH0_IRQHandler
def_irq_handler USBD20_IRQHandler
def_irq_handler EMAC_TX_IRQHandler
def_irq_handler EMAC_RX_IRQHandler
def_irq_handler I2S0_IRQHandler
def_irq_handler OPA0_IRQHandler
def_irq_handler CRYPTO_IRQHandler
def_irq_handler GPG_IRQHandler
def_irq_handler EINT6_IRQHandler
def_irq_handler UART4_IRQHandler
def_irq_handler UART5_IRQHandler
def_irq_handler USCI0_IRQHandler
def_irq_handler USCI1_IRQHandler
def_irq_handler BPWM0_IRQHandler
def_irq_handler BPWM1_IRQHandler
def_irq_handler SPIM_IRQHandler
def_irq_handler I2C2_IRQHandler
def_irq_handler QEI0_IRQHandler
def_irq_handler QEI1_IRQHandler
def_irq_handler ECAP0_IRQHandler
def_irq_handler ECAP1_IRQHandler
def_irq_handler GPH_IRQHandler
def_irq_handler EINT7_IRQHandler
def_irq_handler SDH1_IRQHandler
def_irq_handler EHCI_IRQHandler
def_irq_handler USBOTG20_IRQHandler
.end
|
wuxx/nanoDAP | 20,435 | software/DAPLink/source/hic_hal/nuvoton/m48ssidae/armcc/startup_M480.s | ;/******************************************************************************
; * @file startup_M480.s
; * @version V1.00
; * @brief CMSIS Cortex-M4 Core Device Startup File for M480
; *
; * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without modification,
; * are permitted provided that the following conditions are met:
; * 1. Redistributions of source code must retain the above copyright notice,
; * this list of conditions and the following disclaimer.
; * 2. Redistributions in binary form must reproduce the above copyright notice,
; * this list of conditions and the following disclaimer in the documentation
; * and/or other materials provided with the distribution.
; * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
; * may be used to endorse or promote products derived from this software
; * without specific prior written permission.
; *
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
#include "daplink_addr.h"
#include "daplink_defaults.h"
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Stack_Size
Stack_Size EQU DAPLINK_STACK_SIZE
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :LNOT: :DEF: Heap_Size
Heap_Size EQU DAPLINK_HEAP_SIZE
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT g_board_info
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD DAPLINK_BUILD_KEY ; DAPLINK: Build type (BL/IF)
DCD DAPLINK_HIC_ID ; DAPLINK: Compatibility
DCD DAPLINK_VERSION ; DAPLINK: Version
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD g_board_info ; DAPLINK: Pointer to board/family/target info
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD BOD_IRQHandler ; 0: Brown Out detection
DCD IRC_IRQHandler ; 1: Internal RC
DCD PWRWU_IRQHandler ; 2: Power down wake up
DCD RAMPE_IRQHandler ; 3: RAM parity error
DCD CKFAIL_IRQHandler ; 4: Clock detection fail
DCD Default_Handler ; 5: Reserved
DCD RTC_IRQHandler ; 6: Real Time Clock
DCD TAMPER_IRQHandler ; 7: Tamper detection
DCD WDT_IRQHandler ; 8: Watchdog timer
DCD WWDT_IRQHandler ; 9: Window watchdog timer
DCD EINT0_IRQHandler ; 10: External Input 0
DCD EINT1_IRQHandler ; 11: External Input 1
DCD EINT2_IRQHandler ; 12: External Input 2
DCD EINT3_IRQHandler ; 13: External Input 3
DCD EINT4_IRQHandler ; 14: External Input 4
DCD EINT5_IRQHandler ; 15: External Input 5
DCD GPA_IRQHandler ; 16: GPIO Port A
DCD GPB_IRQHandler ; 17: GPIO Port B
DCD GPC_IRQHandler ; 18: GPIO Port C
DCD GPD_IRQHandler ; 19: GPIO Port D
DCD GPE_IRQHandler ; 20: GPIO Port E
DCD GPF_IRQHandler ; 21: GPIO Port F
DCD QSPI0_IRQHandler ; 22: QSPI0
DCD SPI0_IRQHandler ; 23: SPI0
DCD BRAKE0_IRQHandler ; 24:
DCD EPWM0P0_IRQHandler ; 25:
DCD EPWM0P1_IRQHandler ; 26:
DCD EPWM0P2_IRQHandler ; 27:
DCD BRAKE1_IRQHandler ; 28:
DCD EPWM1P0_IRQHandler ; 29:
DCD EPWM1P1_IRQHandler ; 30:
DCD EPWM1P2_IRQHandler ; 31:
DCD TMR0_IRQHandler ; 32: Timer 0
DCD TMR1_IRQHandler ; 33: Timer 1
DCD TMR2_IRQHandler ; 34: Timer 2
DCD TMR3_IRQHandler ; 35: Timer 3
DCD UART0_IRQHandler ; 36: UART0
DCD UART1_IRQHandler ; 37: UART1
DCD I2C0_IRQHandler ; 38: I2C0
DCD I2C1_IRQHandler ; 39: I2C1
DCD PDMA_IRQHandler ; 40: Peripheral DMA
DCD DAC_IRQHandler ; 41: DAC
DCD ADC00_IRQHandler ; 42: ADC0 interrupt source 0
DCD ADC01_IRQHandler ; 43: ADC0 interrupt source 1
DCD ACMP01_IRQHandler ; 44: ACMP0 and ACMP1
DCD Default_Handler ; 45: Reserved
DCD ADC02_IRQHandler ; 46: ADC0 interrupt source 2
DCD ADC03_IRQHandler ; 47: ADC0 interrupt source 3
DCD UART2_IRQHandler ; 48: UART2
DCD UART3_IRQHandler ; 49: UART3
DCD Default_Handler ; 50: Reserved
DCD SPI1_IRQHandler ; 51: SPI1
DCD SPI2_IRQHandler ; 52: SPI2
DCD USBD_IRQHandler ; 53: USB device
DCD OHCI_IRQHandler ; 54: OHCI
DCD USBOTG_IRQHandler ; 55: USB OTG
DCD CAN0_IRQHandler ; 56: CAN0
DCD CAN1_IRQHandler ; 57: CAN1
DCD SC0_IRQHandler ; 58:
DCD SC1_IRQHandler ; 59:
DCD SC2_IRQHandler ; 60:
DCD Default_Handler ; 61:
DCD SPI3_IRQHandler ; 62: SPI3
DCD Default_Handler ; 63:
DCD SDH0_IRQHandler ; 64: SDH0
DCD USBD20_IRQHandler ; 65: USBD20
DCD EMAC_TX_IRQHandler ; 66: EMAC_TX
DCD EMAC_RX_IRQHandler ; 67: EMAX_RX
DCD I2S0_IRQHandler ; 68: I2S0
DCD Default_Handler ; 69: ToDo: Add description to this Interrupt
DCD OPA0_IRQHandler ; 70: OPA0
DCD CRYPTO_IRQHandler ; 71: CRYPTO
DCD GPG_IRQHandler ; 72:
DCD EINT6_IRQHandler ; 73:
DCD UART4_IRQHandler ; 74: UART4
DCD UART5_IRQHandler ; 75: UART5
DCD USCI0_IRQHandler ; 76: USCI0
DCD USCI1_IRQHandler ; 77: USCI1
DCD BPWM0_IRQHandler ; 78: BPWM0
DCD BPWM1_IRQHandler ; 79: BPWM1
DCD SPIM_IRQHandler ; 80: SPIM
DCD Default_Handler ; 81: ToDo: Add description to this Interrupt
DCD I2C2_IRQHandler ; 82: I2C2
DCD Default_Handler ; 83:
DCD QEI0_IRQHandler ; 84: QEI0
DCD QEI1_IRQHandler ; 85: QEI1
DCD ECAP0_IRQHandler ; 86: ECAP0
DCD ECAP1_IRQHandler ; 87: ECAP1
DCD GPH_IRQHandler ; 88:
DCD EINT7_IRQHandler ; 89:
DCD SDH1_IRQHandler ; 90: SDH1
DCD Default_Handler ; 91:
DCD EHCI_IRQHandler ; 92: EHCI
DCD USBOTG20_IRQHandler ; 93:
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; Unlock Register
LDR R0, =0x40000100
LDR R1, =0x59
STR R1, [R0]
LDR R1, =0x16
STR R1, [R0]
LDR R1, =0x88
STR R1, [R0]
IF :LNOT: :DEF: ENABLE_SPIM_CACHE
LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
ORR R1, R1, #0x4000
STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1,#2 ; R1 |= SPIM_CTL1_CACHEOFF_Msk
STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
LDR R1, [R0,#4] ; R1 = SPIM->CTL1
ORR R1, R1, #4 ; R1 |= SPIM_CTL1_CCMEN_Msk
STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
ENDIF
LDR R0, =SystemInit
BLX R0
; Init POR
; LDR R2, =0x40000024
; LDR R1, =0x00005AA5
; STR R1, [R2]
; Lock
LDR R0, =0x40000100
LDR R1, =0
STR R1, [R0]
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT BOD_IRQHandler [WEAK]
EXPORT IRC_IRQHandler [WEAK]
EXPORT PWRWU_IRQHandler [WEAK]
EXPORT RAMPE_IRQHandler [WEAK]
EXPORT CKFAIL_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT EINT4_IRQHandler [WEAK]
EXPORT EINT5_IRQHandler [WEAK]
EXPORT GPA_IRQHandler [WEAK]
EXPORT GPB_IRQHandler [WEAK]
EXPORT GPC_IRQHandler [WEAK]
EXPORT GPD_IRQHandler [WEAK]
EXPORT GPE_IRQHandler [WEAK]
EXPORT GPF_IRQHandler [WEAK]
EXPORT QSPI0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT BRAKE0_IRQHandler [WEAK]
EXPORT EPWM0P0_IRQHandler [WEAK]
EXPORT EPWM0P1_IRQHandler [WEAK]
EXPORT EPWM0P2_IRQHandler [WEAK]
EXPORT BRAKE1_IRQHandler [WEAK]
EXPORT EPWM1P0_IRQHandler [WEAK]
EXPORT EPWM1P1_IRQHandler [WEAK]
EXPORT EPWM1P2_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT PDMA_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT ADC00_IRQHandler [WEAK]
EXPORT ADC01_IRQHandler [WEAK]
EXPORT ACMP01_IRQHandler [WEAK]
EXPORT ADC02_IRQHandler [WEAK]
EXPORT ADC03_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT OHCI_IRQHandler [WEAK]
EXPORT USBOTG_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT SC0_IRQHandler [WEAK]
EXPORT SC1_IRQHandler [WEAK]
EXPORT SC2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT SDH0_IRQHandler [WEAK]
EXPORT USBD20_IRQHandler [WEAK]
EXPORT EMAC_TX_IRQHandler [WEAK]
EXPORT EMAC_RX_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT OPA0_IRQHandler [WEAK]
EXPORT CRYPTO_IRQHandler [WEAK]
EXPORT GPG_IRQHandler [WEAK]
EXPORT EINT6_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT USCI0_IRQHandler [WEAK]
EXPORT USCI1_IRQHandler [WEAK]
EXPORT BPWM0_IRQHandler [WEAK]
EXPORT BPWM1_IRQHandler [WEAK]
EXPORT SPIM_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT QEI0_IRQHandler [WEAK]
EXPORT QEI1_IRQHandler [WEAK]
EXPORT ECAP0_IRQHandler [WEAK]
EXPORT ECAP1_IRQHandler [WEAK]
EXPORT GPH_IRQHandler [WEAK]
EXPORT EINT7_IRQHandler [WEAK]
EXPORT SDH1_IRQHandler [WEAK]
EXPORT EHCI_IRQHandler [WEAK]
EXPORT USBOTG20_IRQHandler [WEAK]
Default__IRQHandler
BOD_IRQHandler
IRC_IRQHandler
PWRWU_IRQHandler
RAMPE_IRQHandler
CKFAIL_IRQHandler
RTC_IRQHandler
TAMPER_IRQHandler
WDT_IRQHandler
WWDT_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
EINT4_IRQHandler
EINT5_IRQHandler
GPA_IRQHandler
GPB_IRQHandler
GPC_IRQHandler
GPD_IRQHandler
GPE_IRQHandler
GPF_IRQHandler
QSPI0_IRQHandler
SPI0_IRQHandler
BRAKE0_IRQHandler
EPWM0P0_IRQHandler
EPWM0P1_IRQHandler
EPWM0P2_IRQHandler
BRAKE1_IRQHandler
EPWM1P0_IRQHandler
EPWM1P1_IRQHandler
EPWM1P2_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
PDMA_IRQHandler
DAC_IRQHandler
ADC00_IRQHandler
ADC01_IRQHandler
ACMP01_IRQHandler
ADC02_IRQHandler
ADC03_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USBD_IRQHandler
OHCI_IRQHandler
USBOTG_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
SC0_IRQHandler
SC1_IRQHandler
SC2_IRQHandler
SPI3_IRQHandler
SDH0_IRQHandler
USBD20_IRQHandler
EMAC_TX_IRQHandler
EMAC_RX_IRQHandler
I2S0_IRQHandler
OPA0_IRQHandler
CRYPTO_IRQHandler
GPG_IRQHandler
EINT6_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
USCI0_IRQHandler
USCI1_IRQHandler
BPWM0_IRQHandler
BPWM1_IRQHandler
SPIM_IRQHandler
I2C2_IRQHandler
QEI0_IRQHandler
QEI1_IRQHandler
ECAP0_IRQHandler
ECAP1_IRQHandler
GPH_IRQHandler
EINT7_IRQHandler
SDH1_IRQHandler
EHCI_IRQHandler
USBOTG20_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
;/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
wuxx/nanoDAP | 1,100 | software/v2.3c/source/daplink/bootloader/SVC_Table.s | ;/**
; * @file SVC_Table.s
; * @brief SVC functions
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
AREA SVC_TABLE, CODE, READONLY
EXPORT SVC_Count
SVC_Cnt EQU (SVC_End-SVC_Table)/4
SVC_Count DCD SVC_Cnt
; Import user SVC functions here.
EXPORT SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
SVC_End
END
|
wuxx/nanoDAP | 1,113 | software/v2.3c/source/daplink/interface/SVC_Table.s | ;/**
; * @file SVC_Table.s
; * @brief SVC config for application
; *
; * DAPLink Interface Firmware
; * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License"); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
AREA SVC_TABLE, CODE, READONLY
EXPORT SVC_Count
SVC_Cnt EQU (SVC_End-SVC_Table)/4
SVC_Count DCD SVC_Cnt
; Import user SVC functions here.
EXPORT SVC_Table
SVC_Table
; Insert user SVC functions here. SVC 0 used by RTL Kernel.
SVC_End
END
|
wuxx/nanoDAP | 9,760 | software/v2.3c/source/hic_hal/atmel/sam3u2c/armcc/startup_SAM3U.s | ;/*****************************************************************************
; * @file: startup_SAM3U.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the Atmel SAM3U Device Series
; * @version: V1.10
; * @date: 17. April 2013
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; 0: Top of Stack
DCD Reset_Handler ; 1: Reset Handler
DCD NMI_Handler ; 2: NMI Handler
DCD HardFault_Handler ; 3: Hard Fault Handler
DCD MemManage_Handler ; 4: MPU Fault Handler
DCD BusFault_Handler ; 5: Bus Fault Handler
DCD UsageFault_Handler ; 6: Usage Fault Handler
DCD 0 ; 7: Reserved
DCD DAPLINK_BUILD_KEY ; 8: Build type - BL/IF
DCD DAPLINK_HIC_ID ; 9: Compatibility
DCD DAPLINK_VERSION ; 10:Version
DCD SVC_Handler ; 11: SVCall Handler
DCD DebugMon_Handler ; 12: Debug Monitor Handler
DCD 0 ; 13: Reserved
DCD PendSV_Handler ; 14: PendSV Handler
DCD SysTick_Handler ; 15: SysTick Handler
; External Interrupts
DCD SUPC_IRQHandler ; 0: Supply Controller
DCD RSTC_IRQHandler ; 1: Reset Controller
DCD RTC_IRQHandler ; 2: Real Time Clock
DCD RTT_IRQHandler ; 3: Real Time Timer
DCD WDT_IRQHandler ; 4: Watchdog Timer
DCD PMC_IRQHandler ; 5: Power Management Controller
DCD EEFC0_IRQHandler ; 6: Enhanced Embedded Flash Controller 0
DCD EEFC1_IRQHandler ; 7: Enhanced Embedded Flash Controller 1
DCD UART_IRQHandler ; 8: UART
DCD SMC_IRQHandler ; 9: Static Memory Controller
DCD PIOA_IRQHandler ; 10: Parallel I/O Controller A
DCD PIOB_IRQHandler ; 11: Parallel I/O Controller B
DCD PIOC_IRQHandler ; 12: Parallel I/O Controller C
DCD USART0_IRQHandler ; 13: USART 0
DCD USART1_IRQHandler ; 14: USART 1
DCD USART2_IRQHandler ; 15: USART 2
DCD USART3_IRQHandler ; 16: USART 3
DCD HSMCI_IRQHandler ; 17: High Speed Multimedia Card Interface
DCD TWI0_IRQHandler ; 18: Two-wire Interface 0
DCD TWI1_IRQHandler ; 19: Two-wire Interface 1
DCD SPI_IRQHandler ; 20: Synchronous Peripheral Interface
DCD SSC_IRQHandler ; 21: Synchronous Serial Controller
DCD TC0_IRQHandler ; 22: Timer Counter 0
DCD TC1_IRQHandler ; 23: Timer Counter 1
DCD TC2_IRQHandler ; 24: Timer Counter 2
DCD PWM_IRQHandler ; 25: Pulse Width Modulation Controller
DCD ADC12B_IRQHandler ; 26: 12-bit ADC Controller
DCD ADC_IRQHandler ; 27: 10-bit ADC Controller
DCD DMAC_IRQHandler ; 28: DMA Controller
DCD UDPHS_IRQHandler ; 29: USB Device High Speed
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SUPC_IRQHandler [WEAK]
EXPORT RSTC_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTT_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT PMC_IRQHandler [WEAK]
EXPORT EEFC0_IRQHandler [WEAK]
EXPORT EEFC1_IRQHandler [WEAK]
EXPORT UART_IRQHandler [WEAK]
EXPORT SMC_IRQHandler [WEAK]
EXPORT PIOA_IRQHandler [WEAK]
EXPORT PIOB_IRQHandler [WEAK]
EXPORT PIOC_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT HSMCI_IRQHandler [WEAK]
EXPORT TWI0_IRQHandler [WEAK]
EXPORT TWI1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT SSC_IRQHandler [WEAK]
EXPORT TC0_IRQHandler [WEAK]
EXPORT TC1_IRQHandler [WEAK]
EXPORT TC2_IRQHandler [WEAK]
EXPORT PWM_IRQHandler [WEAK]
EXPORT ADC12B_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT DMAC_IRQHandler [WEAK]
EXPORT UDPHS_IRQHandler [WEAK]
SUPC_IRQHandler
RSTC_IRQHandler
RTC_IRQHandler
RTT_IRQHandler
WDT_IRQHandler
PMC_IRQHandler
EEFC0_IRQHandler
EEFC1_IRQHandler
UART_IRQHandler
SMC_IRQHandler
PIOA_IRQHandler
PIOB_IRQHandler
PIOC_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
HSMCI_IRQHandler
TWI0_IRQHandler
TWI1_IRQHandler
SPI_IRQHandler
SSC_IRQHandler
TC0_IRQHandler
TC1_IRQHandler
TC2_IRQHandler
PWM_IRQHandler
ADC12B_IRQHandler
ADC_IRQHandler
DMAC_IRQHandler
UDPHS_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
|
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